drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                 } else {
 435                         MLX5_ASSERT(item->spec);
 436                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 437                                                    field->offset, field->size);
 438                         /* Shift out the trailing masked bits from data. */
 439                         data = (data & mask) >> off_b;
 440                         actions[i].data1 = rte_cpu_to_be_32(data);
 441                 }
 442                 ++i;
 443                 ++field;
 444         } while (field->size);
 445         if (resource->actions_num == i)
 446                 return rte_flow_error_set(error, EINVAL,
 447                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 448                                           "invalid modification flow item");
 449         resource->actions_num = i;
 450         return 0;
 451 }
 452
 453 /**
 454  * Convert modify-header set IPv4 address action to DV specification.
 455  *
 456  * @param[in,out] resource
 457  *   Pointer to the modify-header resource.
 458  * @param[in] action
 459  *   Pointer to action specification.
 460  * @param[out] error
 461  *   Pointer to the error structure.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 static int
 467 flow_dv_convert_action_modify_ipv4
 468                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 469                          const struct rte_flow_action *action,
 470                          struct rte_flow_error *error)
 471 {
 472         const struct rte_flow_action_set_ipv4 *conf =
 473                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 474         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 475         struct rte_flow_item_ipv4 ipv4;
 476         struct rte_flow_item_ipv4 ipv4_mask;
 477
 478         memset(&ipv4, 0, sizeof(ipv4));
 479         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 480         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 481                 ipv4.hdr.src_addr = conf->ipv4_addr;
 482                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 483         } else {
 484                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 485                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 486         }
 487         item.spec = &ipv4;
 488         item.mask = &ipv4_mask;
 489         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 490                                              MLX5_MODIFICATION_TYPE_SET, error);
 491 }
 492
 493 /**
 494  * Convert modify-header set IPv6 address action to DV specification.
 495  *
 496  * @param[in,out] resource
 497  *   Pointer to the modify-header resource.
 498  * @param[in] action
 499  *   Pointer to action specification.
 500  * @param[out] error
 501  *   Pointer to the error structure.
 502  *
 503  * @return
 504  *   0 on success, a negative errno value otherwise and rte_errno is set.
 505  */
 506 static int
 507 flow_dv_convert_action_modify_ipv6
 508                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 509                          const struct rte_flow_action *action,
 510                          struct rte_flow_error *error)
 511 {
 512         const struct rte_flow_action_set_ipv6 *conf =
 513                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 514         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 515         struct rte_flow_item_ipv6 ipv6;
 516         struct rte_flow_item_ipv6 ipv6_mask;
 517
 518         memset(&ipv6, 0, sizeof(ipv6));
 519         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 520         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 521                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 522                        sizeof(ipv6.hdr.src_addr));
 523                 memcpy(&ipv6_mask.hdr.src_addr,
 524                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 525                        sizeof(ipv6.hdr.src_addr));
 526         } else {
 527                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 528                        sizeof(ipv6.hdr.dst_addr));
 529                 memcpy(&ipv6_mask.hdr.dst_addr,
 530                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 531                        sizeof(ipv6.hdr.dst_addr));
 532         }
 533         item.spec = &ipv6;
 534         item.mask = &ipv6_mask;
 535         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 536                                              MLX5_MODIFICATION_TYPE_SET, error);
 537 }
 538
 539 /**
 540  * Convert modify-header set MAC address action to DV specification.
 541  *
 542  * @param[in,out] resource
 543  *   Pointer to the modify-header resource.
 544  * @param[in] action
 545  *   Pointer to action specification.
 546  * @param[out] error
 547  *   Pointer to the error structure.
 548  *
 549  * @return
 550  *   0 on success, a negative errno value otherwise and rte_errno is set.
 551  */
 552 static int
 553 flow_dv_convert_action_modify_mac
 554                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 555                          const struct rte_flow_action *action,
 556                          struct rte_flow_error *error)
 557 {
 558         const struct rte_flow_action_set_mac *conf =
 559                 (const struct rte_flow_action_set_mac *)(action->conf);
 560         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 561         struct rte_flow_item_eth eth;
 562         struct rte_flow_item_eth eth_mask;
 563
 564         memset(&eth, 0, sizeof(eth));
 565         memset(&eth_mask, 0, sizeof(eth_mask));
 566         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 567                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 568                        sizeof(eth.src.addr_bytes));
 569                 memcpy(&eth_mask.src.addr_bytes,
 570                        &rte_flow_item_eth_mask.src.addr_bytes,
 571                        sizeof(eth_mask.src.addr_bytes));
 572         } else {
 573                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 574                        sizeof(eth.dst.addr_bytes));
 575                 memcpy(&eth_mask.dst.addr_bytes,
 576                        &rte_flow_item_eth_mask.dst.addr_bytes,
 577                        sizeof(eth_mask.dst.addr_bytes));
 578         }
 579         item.spec = &eth;
 580         item.mask = &eth_mask;
 581         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 582                                              MLX5_MODIFICATION_TYPE_SET, error);
 583 }
 584
 585 /**
 586  * Convert modify-header set VLAN VID action to DV specification.
 587  *
 588  * @param[in,out] resource
 589  *   Pointer to the modify-header resource.
 590  * @param[in] action
 591  *   Pointer to action specification.
 592  * @param[out] error
 593  *   Pointer to the error structure.
 594  *
 595  * @return
 596  *   0 on success, a negative errno value otherwise and rte_errno is set.
 597  */
 598 static int
 599 flow_dv_convert_action_modify_vlan_vid
 600                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 601                          const struct rte_flow_action *action,
 602                          struct rte_flow_error *error)
 603 {
 604         const struct rte_flow_action_of_set_vlan_vid *conf =
 605                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 606         int i = resource->actions_num;
 607         struct mlx5_modification_cmd *actions = resource->actions;
 608         struct field_modify_info *field = modify_vlan_out_first_vid;
 609
 610         if (i >= MLX5_MAX_MODIFY_NUM)
 611                 return rte_flow_error_set(error, EINVAL,
 612                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 613                          "too many items to modify");
 614         actions[i] = (struct mlx5_modification_cmd) {
 615                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 616                 .field = field->id,
 617                 .length = field->size,
 618                 .offset = field->offset,
 619         };
 620         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 621         actions[i].data1 = conf->vlan_vid;
 622         actions[i].data1 = actions[i].data1 << 16;
 623         resource->actions_num = ++i;
 624         return 0;
 625 }
 626
 627 /**
 628  * Convert modify-header set TP action to DV specification.
 629  *
 630  * @param[in,out] resource
 631  *   Pointer to the modify-header resource.
 632  * @param[in] action
 633  *   Pointer to action specification.
 634  * @param[in] items
 635  *   Pointer to rte_flow_item objects list.
 636  * @param[in] attr
 637  *   Pointer to flow attributes structure.
 638  * @param[in] dev_flow
 639  *   Pointer to the sub flow.
 640  * @param[in] tunnel_decap
 641  *   Whether action is after tunnel decapsulation.
 642  * @param[out] error
 643  *   Pointer to the error structure.
 644  *
 645  * @return
 646  *   0 on success, a negative errno value otherwise and rte_errno is set.
 647  */
 648 static int
 649 flow_dv_convert_action_modify_tp
 650                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 651                          const struct rte_flow_action *action,
 652                          const struct rte_flow_item *items,
 653                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 654                          bool tunnel_decap, struct rte_flow_error *error)
 655 {
 656         const struct rte_flow_action_set_tp *conf =
 657                 (const struct rte_flow_action_set_tp *)(action->conf);
 658         struct rte_flow_item item;
 659         struct rte_flow_item_udp udp;
 660         struct rte_flow_item_udp udp_mask;
 661         struct rte_flow_item_tcp tcp;
 662         struct rte_flow_item_tcp tcp_mask;
 663         struct field_modify_info *field;
 664
 665         if (!attr->valid)
 666                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 667         if (attr->udp) {
 668                 memset(&udp, 0, sizeof(udp));
 669                 memset(&udp_mask, 0, sizeof(udp_mask));
 670                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 671                         udp.hdr.src_port = conf->port;
 672                         udp_mask.hdr.src_port =
 673                                         rte_flow_item_udp_mask.hdr.src_port;
 674                 } else {
 675                         udp.hdr.dst_port = conf->port;
 676                         udp_mask.hdr.dst_port =
 677                                         rte_flow_item_udp_mask.hdr.dst_port;
 678                 }
 679                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 680                 item.spec = &udp;
 681                 item.mask = &udp_mask;
 682                 field = modify_udp;
 683         } else {
 684                 MLX5_ASSERT(attr->tcp);
 685                 memset(&tcp, 0, sizeof(tcp));
 686                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 687                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 688                         tcp.hdr.src_port = conf->port;
 689                         tcp_mask.hdr.src_port =
 690                                         rte_flow_item_tcp_mask.hdr.src_port;
 691                 } else {
 692                         tcp.hdr.dst_port = conf->port;
 693                         tcp_mask.hdr.dst_port =
 694                                         rte_flow_item_tcp_mask.hdr.dst_port;
 695                 }
 696                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 697                 item.spec = &tcp;
 698                 item.mask = &tcp_mask;
 699                 field = modify_tcp;
 700         }
 701         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 702                                              MLX5_MODIFICATION_TYPE_SET, error);
 703 }
 704
 705 /**
 706  * Convert modify-header set TTL action to DV specification.
 707  *
 708  * @param[in,out] resource
 709  *   Pointer to the modify-header resource.
 710  * @param[in] action
 711  *   Pointer to action specification.
 712  * @param[in] items
 713  *   Pointer to rte_flow_item objects list.
 714  * @param[in] attr
 715  *   Pointer to flow attributes structure.
 716  * @param[in] dev_flow
 717  *   Pointer to the sub flow.
 718  * @param[in] tunnel_decap
 719  *   Whether action is after tunnel decapsulation.
 720  * @param[out] error
 721  *   Pointer to the error structure.
 722  *
 723  * @return
 724  *   0 on success, a negative errno value otherwise and rte_errno is set.
 725  */
 726 static int
 727 flow_dv_convert_action_modify_ttl
 728                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 729                          const struct rte_flow_action *action,
 730                          const struct rte_flow_item *items,
 731                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 732                          bool tunnel_decap, struct rte_flow_error *error)
 733 {
 734         const struct rte_flow_action_set_ttl *conf =
 735                 (const struct rte_flow_action_set_ttl *)(action->conf);
 736         struct rte_flow_item item;
 737         struct rte_flow_item_ipv4 ipv4;
 738         struct rte_flow_item_ipv4 ipv4_mask;
 739         struct rte_flow_item_ipv6 ipv6;
 740         struct rte_flow_item_ipv6 ipv6_mask;
 741         struct field_modify_info *field;
 742
 743         if (!attr->valid)
 744                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 745         if (attr->ipv4) {
 746                 memset(&ipv4, 0, sizeof(ipv4));
 747                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 748                 ipv4.hdr.time_to_live = conf->ttl_value;
 749                 ipv4_mask.hdr.time_to_live = 0xFF;
 750                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 751                 item.spec = &ipv4;
 752                 item.mask = &ipv4_mask;
 753                 field = modify_ipv4;
 754         } else {
 755                 MLX5_ASSERT(attr->ipv6);
 756                 memset(&ipv6, 0, sizeof(ipv6));
 757                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 758                 ipv6.hdr.hop_limits = conf->ttl_value;
 759                 ipv6_mask.hdr.hop_limits = 0xFF;
 760                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 761                 item.spec = &ipv6;
 762                 item.mask = &ipv6_mask;
 763                 field = modify_ipv6;
 764         }
 765         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 766                                              MLX5_MODIFICATION_TYPE_SET, error);
 767 }
 768
 769 /**
 770  * Convert modify-header decrement TTL action to DV specification.
 771  *
 772  * @param[in,out] resource
 773  *   Pointer to the modify-header resource.
 774  * @param[in] action
 775  *   Pointer to action specification.
 776  * @param[in] items
 777  *   Pointer to rte_flow_item objects list.
 778  * @param[in] attr
 779  *   Pointer to flow attributes structure.
 780  * @param[in] dev_flow
 781  *   Pointer to the sub flow.
 782  * @param[in] tunnel_decap
 783  *   Whether action is after tunnel decapsulation.
 784  * @param[out] error
 785  *   Pointer to the error structure.
 786  *
 787  * @return
 788  *   0 on success, a negative errno value otherwise and rte_errno is set.
 789  */
 790 static int
 791 flow_dv_convert_action_modify_dec_ttl
 792                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 793                          const struct rte_flow_item *items,
 794                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 795                          bool tunnel_decap, struct rte_flow_error *error)
 796 {
 797         struct rte_flow_item item;
 798         struct rte_flow_item_ipv4 ipv4;
 799         struct rte_flow_item_ipv4 ipv4_mask;
 800         struct rte_flow_item_ipv6 ipv6;
 801         struct rte_flow_item_ipv6 ipv6_mask;
 802         struct field_modify_info *field;
 803
 804         if (!attr->valid)
 805                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 806         if (attr->ipv4) {
 807                 memset(&ipv4, 0, sizeof(ipv4));
 808                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 809                 ipv4.hdr.time_to_live = 0xFF;
 810                 ipv4_mask.hdr.time_to_live = 0xFF;
 811                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 812                 item.spec = &ipv4;
 813                 item.mask = &ipv4_mask;
 814                 field = modify_ipv4;
 815         } else {
 816                 MLX5_ASSERT(attr->ipv6);
 817                 memset(&ipv6, 0, sizeof(ipv6));
 818                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 819                 ipv6.hdr.hop_limits = 0xFF;
 820                 ipv6_mask.hdr.hop_limits = 0xFF;
 821                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 822                 item.spec = &ipv6;
 823                 item.mask = &ipv6_mask;
 824                 field = modify_ipv6;
 825         }
 826         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 827                                              MLX5_MODIFICATION_TYPE_ADD, error);
 828 }
 829
 830 /**
 831  * Convert modify-header increment/decrement TCP Sequence number
 832  * to DV specification.
 833  *
 834  * @param[in,out] resource
 835  *   Pointer to the modify-header resource.
 836  * @param[in] action
 837  *   Pointer to action specification.
 838  * @param[out] error
 839  *   Pointer to the error structure.
 840  *
 841  * @return
 842  *   0 on success, a negative errno value otherwise and rte_errno is set.
 843  */
 844 static int
 845 flow_dv_convert_action_modify_tcp_seq
 846                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 847                          const struct rte_flow_action *action,
 848                          struct rte_flow_error *error)
 849 {
 850         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 851         uint64_t value = rte_be_to_cpu_32(*conf);
 852         struct rte_flow_item item;
 853         struct rte_flow_item_tcp tcp;
 854         struct rte_flow_item_tcp tcp_mask;
 855
 856         memset(&tcp, 0, sizeof(tcp));
 857         memset(&tcp_mask, 0, sizeof(tcp_mask));
 858         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 859                 /*
 860                  * The HW has no decrement operation, only increment operation.
 861                  * To simulate decrement X from Y using increment operation
 862                  * we need to add UINT32_MAX X times to Y.
 863                  * Each adding of UINT32_MAX decrements Y by 1.
 864                  */
 865                 value *= UINT32_MAX;
 866         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 867         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 868         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 869         item.spec = &tcp;
 870         item.mask = &tcp_mask;
 871         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 872                                              MLX5_MODIFICATION_TYPE_ADD, error);
 873 }
 874
 875 /**
 876  * Convert modify-header increment/decrement TCP Acknowledgment number
 877  * to DV specification.
 878  *
 879  * @param[in,out] resource
 880  *   Pointer to the modify-header resource.
 881  * @param[in] action
 882  *   Pointer to action specification.
 883  * @param[out] error
 884  *   Pointer to the error structure.
 885  *
 886  * @return
 887  *   0 on success, a negative errno value otherwise and rte_errno is set.
 888  */
 889 static int
 890 flow_dv_convert_action_modify_tcp_ack
 891                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 892                          const struct rte_flow_action *action,
 893                          struct rte_flow_error *error)
 894 {
 895         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 896         uint64_t value = rte_be_to_cpu_32(*conf);
 897         struct rte_flow_item item;
 898         struct rte_flow_item_tcp tcp;
 899         struct rte_flow_item_tcp tcp_mask;
 900
 901         memset(&tcp, 0, sizeof(tcp));
 902         memset(&tcp_mask, 0, sizeof(tcp_mask));
 903         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 904                 /*
 905                  * The HW has no decrement operation, only increment operation.
 906                  * To simulate decrement X from Y using increment operation
 907                  * we need to add UINT32_MAX X times to Y.
 908                  * Each adding of UINT32_MAX decrements Y by 1.
 909                  */
 910                 value *= UINT32_MAX;
 911         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 912         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 913         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 914         item.spec = &tcp;
 915         item.mask = &tcp_mask;
 916         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 917                                              MLX5_MODIFICATION_TYPE_ADD, error);
 918 }
 919
 920 static enum mlx5_modification_field reg_to_field[] = {
 921         [REG_NON] = MLX5_MODI_OUT_NONE,
 922         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 923         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 924         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 925         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 926         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 927         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 928         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 929         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 930         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 931         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 932 };
 933
 934 /**
 935  * Convert register set to DV specification.
 936  *
 937  * @param[in,out] resource
 938  *   Pointer to the modify-header resource.
 939  * @param[in] action
 940  *   Pointer to action specification.
 941  * @param[out] error
 942  *   Pointer to the error structure.
 943  *
 944  * @return
 945  *   0 on success, a negative errno value otherwise and rte_errno is set.
 946  */
 947 static int
 948 flow_dv_convert_action_set_reg
 949                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 950                          const struct rte_flow_action *action,
 951                          struct rte_flow_error *error)
 952 {
 953         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 954         struct mlx5_modification_cmd *actions = resource->actions;
 955         uint32_t i = resource->actions_num;
 956
 957         if (i >= MLX5_MAX_MODIFY_NUM)
 958                 return rte_flow_error_set(error, EINVAL,
 959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 960                                           "too many items to modify");
 961         MLX5_ASSERT(conf->id != REG_NON);
 962         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 963         actions[i] = (struct mlx5_modification_cmd) {
 964                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 965                 .field = reg_to_field[conf->id],
 966         };
 967         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 968         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 969         ++i;
 970         resource->actions_num = i;
 971         return 0;
 972 }
 973
 974 /**
 975  * Convert SET_TAG action to DV specification.
 976  *
 977  * @param[in] dev
 978  *   Pointer to the rte_eth_dev structure.
 979  * @param[in,out] resource
 980  *   Pointer to the modify-header resource.
 981  * @param[in] conf
 982  *   Pointer to action specification.
 983  * @param[out] error
 984  *   Pointer to the error structure.
 985  *
 986  * @return
 987  *   0 on success, a negative errno value otherwise and rte_errno is set.
 988  */
 989 static int
 990 flow_dv_convert_action_set_tag
 991                         (struct rte_eth_dev *dev,
 992                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 993                          const struct rte_flow_action_set_tag *conf,
 994                          struct rte_flow_error *error)
 995 {
 996         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 997         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 998         struct rte_flow_item item = {
 999                 .spec = &data,
1000                 .mask = &mask,
1001         };
1002         struct field_modify_info reg_c_x[] = {
1003                 [1] = {0, 0, 0},
1004         };
1005         enum mlx5_modification_field reg_type;
1006         int ret;
1007
1008         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1009         if (ret < 0)
1010                 return ret;
1011         MLX5_ASSERT(ret != REG_NON);
1012         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1013         reg_type = reg_to_field[ret];
1014         MLX5_ASSERT(reg_type > 0);
1015         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1016         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1017                                              MLX5_MODIFICATION_TYPE_SET, error);
1018 }
1019
1020 /**
1021  * Convert internal COPY_REG action to DV specification.
1022  *
1023  * @param[in] dev
1024  *   Pointer to the rte_eth_dev structure.
1025  * @param[in,out] res
1026  *   Pointer to the modify-header resource.
1027  * @param[in] action
1028  *   Pointer to action specification.
1029  * @param[out] error
1030  *   Pointer to the error structure.
1031  *
1032  * @return
1033  *   0 on success, a negative errno value otherwise and rte_errno is set.
1034  */
1035 static int
1036 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1037                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1038                                  const struct rte_flow_action *action,
1039                                  struct rte_flow_error *error)
1040 {
1041         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1042         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1043         struct rte_flow_item item = {
1044                 .spec = NULL,
1045                 .mask = &mask,
1046         };
1047         struct field_modify_info reg_src[] = {
1048                 {4, 0, reg_to_field[conf->src]},
1049                 {0, 0, 0},
1050         };
1051         struct field_modify_info reg_dst = {
1052                 .offset = 0,
1053                 .id = reg_to_field[conf->dst],
1054         };
1055         /* Adjust reg_c[0] usage according to reported mask. */
1056         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1057                 struct mlx5_priv *priv = dev->data->dev_private;
1058                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1059
1060                 MLX5_ASSERT(reg_c0);
1061                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1062                 if (conf->dst == REG_C_0) {
1063                         /* Copy to reg_c[0], within mask only. */
1064                         reg_dst.offset = rte_bsf32(reg_c0);
1065                         /*
1066                          * Mask is ignoring the enianness, because
1067                          * there is no conversion in datapath.
1068                          */
1069 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1070                         /* Copy from destination lower bits to reg_c[0]. */
1071                         mask = reg_c0 >> reg_dst.offset;
1072 #else
1073                         /* Copy from destination upper bits to reg_c[0]. */
1074                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1075                                           rte_fls_u32(reg_c0));
1076 #endif
1077                 } else {
1078                         mask = rte_cpu_to_be_32(reg_c0);
1079 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1080                         /* Copy from reg_c[0] to destination lower bits. */
1081                         reg_dst.offset = 0;
1082 #else
1083                         /* Copy from reg_c[0] to destination upper bits. */
1084                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1085                                          (rte_fls_u32(reg_c0) -
1086                                           rte_bsf32(reg_c0));
1087 #endif
1088                 }
1089         }
1090         return flow_dv_convert_modify_action(&item,
1091                                              reg_src, &reg_dst, res,
1092                                              MLX5_MODIFICATION_TYPE_COPY,
1093                                              error);
1094 }
1095
1096 /**
1097  * Convert MARK action to DV specification. This routine is used
1098  * in extensive metadata only and requires metadata register to be
1099  * handled. In legacy mode hardware tag resource is engaged.
1100  *
1101  * @param[in] dev
1102  *   Pointer to the rte_eth_dev structure.
1103  * @param[in] conf
1104  *   Pointer to MARK action specification.
1105  * @param[in,out] resource
1106  *   Pointer to the modify-header resource.
1107  * @param[out] error
1108  *   Pointer to the error structure.
1109  *
1110  * @return
1111  *   0 on success, a negative errno value otherwise and rte_errno is set.
1112  */
1113 static int
1114 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1115                             const struct rte_flow_action_mark *conf,
1116                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1117                             struct rte_flow_error *error)
1118 {
1119         struct mlx5_priv *priv = dev->data->dev_private;
1120         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1121                                            priv->sh->dv_mark_mask);
1122         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1123         struct rte_flow_item item = {
1124                 .spec = &data,
1125                 .mask = &mask,
1126         };
1127         struct field_modify_info reg_c_x[] = {
1128                 [1] = {0, 0, 0},
1129         };
1130         int reg;
1131
1132         if (!mask)
1133                 return rte_flow_error_set(error, EINVAL,
1134                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135                                           NULL, "zero mark action mask");
1136         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1137         if (reg < 0)
1138                 return reg;
1139         MLX5_ASSERT(reg > 0);
1140         if (reg == REG_C_0) {
1141                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1143
1144                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146                 mask = rte_cpu_to_be_32(mask << shl_c0);
1147         }
1148         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1149         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150                                              MLX5_MODIFICATION_TYPE_SET, error);
1151 }
1152
1153 /**
1154  * Get metadata register index for specified steering domain.
1155  *
1156  * @param[in] dev
1157  *   Pointer to the rte_eth_dev structure.
1158  * @param[in] attr
1159  *   Attributes of flow to determine steering domain.
1160  * @param[out] error
1161  *   Pointer to the error structure.
1162  *
1163  * @return
1164  *   positive index on success, a negative errno value otherwise
1165  *   and rte_errno is set.
1166  */
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169                          const struct rte_flow_attr *attr,
1170                          struct rte_flow_error *error)
1171 {
1172         int reg =
1173                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1174                                           MLX5_METADATA_FDB :
1175                                             attr->egress ?
1176                                             MLX5_METADATA_TX :
1177                                             MLX5_METADATA_RX, 0, error);
1178         if (reg < 0)
1179                 return rte_flow_error_set(error,
1180                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181                                           NULL, "unavailable "
1182                                           "metadata register");
1183         return reg;
1184 }
1185
1186 /**
1187  * Convert SET_META action to DV specification.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in,out] resource
1192  *   Pointer to the modify-header resource.
1193  * @param[in] attr
1194  *   Attributes of flow that includes this item.
1195  * @param[in] conf
1196  *   Pointer to action specification.
1197  * @param[out] error
1198  *   Pointer to the error structure.
1199  *
1200  * @return
1201  *   0 on success, a negative errno value otherwise and rte_errno is set.
1202  */
1203 static int
1204 flow_dv_convert_action_set_meta
1205                         (struct rte_eth_dev *dev,
1206                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1207                          const struct rte_flow_attr *attr,
1208                          const struct rte_flow_action_set_meta *conf,
1209                          struct rte_flow_error *error)
1210 {
1211         uint32_t data = conf->data;
1212         uint32_t mask = conf->mask;
1213         struct rte_flow_item item = {
1214                 .spec = &data,
1215                 .mask = &mask,
1216         };
1217         struct field_modify_info reg_c_x[] = {
1218                 [1] = {0, 0, 0},
1219         };
1220         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1221
1222         if (reg < 0)
1223                 return reg;
1224         MLX5_ASSERT(reg != REG_NON);
1225         /*
1226          * In datapath code there is no endianness
1227          * coversions for perfromance reasons, all
1228          * pattern conversions are done in rte_flow.
1229          */
1230         if (reg == REG_C_0) {
1231                 struct mlx5_priv *priv = dev->data->dev_private;
1232                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1233                 uint32_t shl_c0;
1234
1235                 MLX5_ASSERT(msk_c0);
1236 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1237                 shl_c0 = rte_bsf32(msk_c0);
1238 #else
1239                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1240 #endif
1241                 mask <<= shl_c0;
1242                 data <<= shl_c0;
1243                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1244         }
1245         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1246         /* The routine expects parameters in memory as big-endian ones. */
1247         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1248                                              MLX5_MODIFICATION_TYPE_SET, error);
1249 }
1250
1251 /**
1252  * Convert modify-header set IPv4 DSCP action to DV specification.
1253  *
1254  * @param[in,out] resource
1255  *   Pointer to the modify-header resource.
1256  * @param[in] action
1257  *   Pointer to action specification.
1258  * @param[out] error
1259  *   Pointer to the error structure.
1260  *
1261  * @return
1262  *   0 on success, a negative errno value otherwise and rte_errno is set.
1263  */
1264 static int
1265 flow_dv_convert_action_modify_ipv4_dscp
1266                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1267                          const struct rte_flow_action *action,
1268                          struct rte_flow_error *error)
1269 {
1270         const struct rte_flow_action_set_dscp *conf =
1271                 (const struct rte_flow_action_set_dscp *)(action->conf);
1272         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1273         struct rte_flow_item_ipv4 ipv4;
1274         struct rte_flow_item_ipv4 ipv4_mask;
1275
1276         memset(&ipv4, 0, sizeof(ipv4));
1277         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1278         ipv4.hdr.type_of_service = conf->dscp;
1279         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1280         item.spec = &ipv4;
1281         item.mask = &ipv4_mask;
1282         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1283                                              MLX5_MODIFICATION_TYPE_SET, error);
1284 }
1285
1286 /**
1287  * Convert modify-header set IPv6 DSCP action to DV specification.
1288  *
1289  * @param[in,out] resource
1290  *   Pointer to the modify-header resource.
1291  * @param[in] action
1292  *   Pointer to action specification.
1293  * @param[out] error
1294  *   Pointer to the error structure.
1295  *
1296  * @return
1297  *   0 on success, a negative errno value otherwise and rte_errno is set.
1298  */
1299 static int
1300 flow_dv_convert_action_modify_ipv6_dscp
1301                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302                          const struct rte_flow_action *action,
1303                          struct rte_flow_error *error)
1304 {
1305         const struct rte_flow_action_set_dscp *conf =
1306                 (const struct rte_flow_action_set_dscp *)(action->conf);
1307         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1308         struct rte_flow_item_ipv6 ipv6;
1309         struct rte_flow_item_ipv6 ipv6_mask;
1310
1311         memset(&ipv6, 0, sizeof(ipv6));
1312         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1313         /*
1314          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1315          * rdma-core only accept the DSCP bits byte aligned start from
1316          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1317          * bits in IPv6 case as rdma-core requires byte aligned value.
1318          */
1319         ipv6.hdr.vtc_flow = conf->dscp;
1320         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1321         item.spec = &ipv6;
1322         item.mask = &ipv6_mask;
1323         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1324                                              MLX5_MODIFICATION_TYPE_SET, error);
1325 }
1326
1327 /**
1328  * Validate MARK item.
1329  *
1330  * @param[in] dev
1331  *   Pointer to the rte_eth_dev structure.
1332  * @param[in] item
1333  *   Item specification.
1334  * @param[in] attr
1335  *   Attributes of flow that includes this item.
1336  * @param[out] error
1337  *   Pointer to error structure.
1338  *
1339  * @return
1340  *   0 on success, a negative errno value otherwise and rte_errno is set.
1341  */
1342 static int
1343 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1344                            const struct rte_flow_item *item,
1345                            const struct rte_flow_attr *attr __rte_unused,
1346                            struct rte_flow_error *error)
1347 {
1348         struct mlx5_priv *priv = dev->data->dev_private;
1349         struct mlx5_dev_config *config = &priv->config;
1350         const struct rte_flow_item_mark *spec = item->spec;
1351         const struct rte_flow_item_mark *mask = item->mask;
1352         const struct rte_flow_item_mark nic_mask = {
1353                 .id = priv->sh->dv_mark_mask,
1354         };
1355         int ret;
1356
1357         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1358                 return rte_flow_error_set(error, ENOTSUP,
1359                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1360                                           "extended metadata feature"
1361                                           " isn't enabled");
1362         if (!mlx5_flow_ext_mreg_supported(dev))
1363                 return rte_flow_error_set(error, ENOTSUP,
1364                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1365                                           "extended metadata register"
1366                                           " isn't supported");
1367         if (!nic_mask.id)
1368                 return rte_flow_error_set(error, ENOTSUP,
1369                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1370                                           "extended metadata register"
1371                                           " isn't available");
1372         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1373         if (ret < 0)
1374                 return ret;
1375         if (!spec)
1376                 return rte_flow_error_set(error, EINVAL,
1377                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1378                                           item->spec,
1379                                           "data cannot be empty");
1380         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1381                 return rte_flow_error_set(error, EINVAL,
1382                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1383                                           &spec->id,
1384                                           "mark id exceeds the limit");
1385         if (!mask)
1386                 mask = &nic_mask;
1387         if (!mask->id)
1388                 return rte_flow_error_set(error, EINVAL,
1389                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1390                                         "mask cannot be zero");
1391
1392         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1393                                         (const uint8_t *)&nic_mask,
1394                                         sizeof(struct rte_flow_item_mark),
1395                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1396         if (ret < 0)
1397                 return ret;
1398         return 0;
1399 }
1400
1401 /**
1402  * Validate META item.
1403  *
1404  * @param[in] dev
1405  *   Pointer to the rte_eth_dev structure.
1406  * @param[in] item
1407  *   Item specification.
1408  * @param[in] attr
1409  *   Attributes of flow that includes this item.
1410  * @param[out] error
1411  *   Pointer to error structure.
1412  *
1413  * @return
1414  *   0 on success, a negative errno value otherwise and rte_errno is set.
1415  */
1416 static int
1417 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1418                            const struct rte_flow_item *item,
1419                            const struct rte_flow_attr *attr,
1420                            struct rte_flow_error *error)
1421 {
1422         struct mlx5_priv *priv = dev->data->dev_private;
1423         struct mlx5_dev_config *config = &priv->config;
1424         const struct rte_flow_item_meta *spec = item->spec;
1425         const struct rte_flow_item_meta *mask = item->mask;
1426         struct rte_flow_item_meta nic_mask = {
1427                 .data = UINT32_MAX
1428         };
1429         int reg;
1430         int ret;
1431
1432         if (!spec)
1433                 return rte_flow_error_set(error, EINVAL,
1434                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1435                                           item->spec,
1436                                           "data cannot be empty");
1437         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1438                 if (!mlx5_flow_ext_mreg_supported(dev))
1439                         return rte_flow_error_set(error, ENOTSUP,
1440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1441                                           "extended metadata register"
1442                                           " isn't supported");
1443                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1444                 if (reg < 0)
1445                         return reg;
1446                 if (reg == REG_NON)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                         "unavalable extended metadata register");
1450                 if (reg == REG_B)
1451                         return rte_flow_error_set(error, ENOTSUP,
1452                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1453                                           "match on reg_b "
1454                                           "isn't supported");
1455                 if (reg != REG_A)
1456                         nic_mask.data = priv->sh->dv_meta_mask;
1457         } else if (attr->transfer) {
1458                 return rte_flow_error_set(error, ENOTSUP,
1459                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1460                                         "extended metadata feature "
1461                                         "should be enabled when "
1462                                         "meta item is requested "
1463                                         "with e-switch mode ");
1464         }
1465         if (!mask)
1466                 mask = &rte_flow_item_meta_mask;
1467         if (!mask->data)
1468                 return rte_flow_error_set(error, EINVAL,
1469                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1470                                         "mask cannot be zero");
1471
1472         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1473                                         (const uint8_t *)&nic_mask,
1474                                         sizeof(struct rte_flow_item_meta),
1475                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1476         return ret;
1477 }
1478
1479 /**
1480  * Validate TAG item.
1481  *
1482  * @param[in] dev
1483  *   Pointer to the rte_eth_dev structure.
1484  * @param[in] item
1485  *   Item specification.
1486  * @param[in] attr
1487  *   Attributes of flow that includes this item.
1488  * @param[out] error
1489  *   Pointer to error structure.
1490  *
1491  * @return
1492  *   0 on success, a negative errno value otherwise and rte_errno is set.
1493  */
1494 static int
1495 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1496                           const struct rte_flow_item *item,
1497                           const struct rte_flow_attr *attr __rte_unused,
1498                           struct rte_flow_error *error)
1499 {
1500         const struct rte_flow_item_tag *spec = item->spec;
1501         const struct rte_flow_item_tag *mask = item->mask;
1502         const struct rte_flow_item_tag nic_mask = {
1503                 .data = RTE_BE32(UINT32_MAX),
1504                 .index = 0xff,
1505         };
1506         int ret;
1507
1508         if (!mlx5_flow_ext_mreg_supported(dev))
1509                 return rte_flow_error_set(error, ENOTSUP,
1510                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1511                                           "extensive metadata register"
1512                                           " isn't supported");
1513         if (!spec)
1514                 return rte_flow_error_set(error, EINVAL,
1515                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1516                                           item->spec,
1517                                           "data cannot be empty");
1518         if (!mask)
1519                 mask = &rte_flow_item_tag_mask;
1520         if (!mask->data)
1521                 return rte_flow_error_set(error, EINVAL,
1522                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1523                                         "mask cannot be zero");
1524
1525         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526                                         (const uint8_t *)&nic_mask,
1527                                         sizeof(struct rte_flow_item_tag),
1528                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1529         if (ret < 0)
1530                 return ret;
1531         if (mask->index != 0xff)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534                                           "partial mask for tag index"
1535                                           " is not supported");
1536         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1537         if (ret < 0)
1538                 return ret;
1539         MLX5_ASSERT(ret != REG_NON);
1540         return 0;
1541 }
1542
1543 /**
1544  * Validate vport item.
1545  *
1546  * @param[in] dev
1547  *   Pointer to the rte_eth_dev structure.
1548  * @param[in] item
1549  *   Item specification.
1550  * @param[in] attr
1551  *   Attributes of flow that includes this item.
1552  * @param[in] item_flags
1553  *   Bit-fields that holds the items detected until now.
1554  * @param[out] error
1555  *   Pointer to error structure.
1556  *
1557  * @return
1558  *   0 on success, a negative errno value otherwise and rte_errno is set.
1559  */
1560 static int
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562                               const struct rte_flow_item *item,
1563                               const struct rte_flow_attr *attr,
1564                               uint64_t item_flags,
1565                               struct rte_flow_error *error)
1566 {
1567         const struct rte_flow_item_port_id *spec = item->spec;
1568         const struct rte_flow_item_port_id *mask = item->mask;
1569         const struct rte_flow_item_port_id switch_mask = {
1570                         .id = 0xffffffff,
1571         };
1572         struct mlx5_priv *esw_priv;
1573         struct mlx5_priv *dev_priv;
1574         int ret;
1575
1576         if (!attr->transfer)
1577                 return rte_flow_error_set(error, EINVAL,
1578                                           RTE_FLOW_ERROR_TYPE_ITEM,
1579                                           NULL,
1580                                           "match on port id is valid only"
1581                                           " when transfer flag is enabled");
1582         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583                 return rte_flow_error_set(error, ENOTSUP,
1584                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1585                                           "multiple source ports are not"
1586                                           " supported");
1587         if (!mask)
1588                 mask = &switch_mask;
1589         if (mask->id != 0xffffffff)
1590                 return rte_flow_error_set(error, ENOTSUP,
1591                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1592                                            mask,
1593                                            "no support for partial mask on"
1594                                            " \"id\" field");
1595         ret = mlx5_flow_item_acceptable
1596                                 (item, (const uint8_t *)mask,
1597                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1598                                  sizeof(struct rte_flow_item_port_id),
1599                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1600         if (ret)
1601                 return ret;
1602         if (!spec)
1603                 return 0;
1604         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1605         if (!esw_priv)
1606                 return rte_flow_error_set(error, rte_errno,
1607                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608                                           "failed to obtain E-Switch info for"
1609                                           " port");
1610         dev_priv = mlx5_dev_to_eswitch_info(dev);
1611         if (!dev_priv)
1612                 return rte_flow_error_set(error, rte_errno,
1613                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1614                                           NULL,
1615                                           "failed to obtain E-Switch info");
1616         if (esw_priv->domain_id != dev_priv->domain_id)
1617                 return rte_flow_error_set(error, EINVAL,
1618                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619                                           "cannot match on a port from a"
1620                                           " different E-Switch");
1621         return 0;
1622 }
1623
1624 /**
1625  * Validate VLAN item.
1626  *
1627  * @param[in] item
1628  *   Item specification.
1629  * @param[in] item_flags
1630  *   Bit-fields that holds the items detected until now.
1631  * @param[in] dev
1632  *   Ethernet device flow is being created on.
1633  * @param[out] error
1634  *   Pointer to error structure.
1635  *
1636  * @return
1637  *   0 on success, a negative errno value otherwise and rte_errno is set.
1638  */
1639 static int
1640 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1641                            uint64_t item_flags,
1642                            struct rte_eth_dev *dev,
1643                            struct rte_flow_error *error)
1644 {
1645         const struct rte_flow_item_vlan *mask = item->mask;
1646         const struct rte_flow_item_vlan nic_mask = {
1647                 .tci = RTE_BE16(UINT16_MAX),
1648                 .inner_type = RTE_BE16(UINT16_MAX),
1649                 .has_more_vlan = 1,
1650         };
1651         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1652         int ret;
1653         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1654                                         MLX5_FLOW_LAYER_INNER_L4) :
1655                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1656                                         MLX5_FLOW_LAYER_OUTER_L4);
1657         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1658                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1659
1660         if (item_flags & vlanm)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "multiple VLAN layers not supported");
1664         else if ((item_flags & l34m) != 0)
1665                 return rte_flow_error_set(error, EINVAL,
1666                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1667                                           "VLAN cannot follow L3/L4 layer");
1668         if (!mask)
1669                 mask = &rte_flow_item_vlan_mask;
1670         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1671                                         (const uint8_t *)&nic_mask,
1672                                         sizeof(struct rte_flow_item_vlan),
1673                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1674         if (ret)
1675                 return ret;
1676         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1677                 struct mlx5_priv *priv = dev->data->dev_private;
1678
1679                 if (priv->vmwa_context) {
1680                         /*
1681                          * Non-NULL context means we have a virtual machine
1682                          * and SR-IOV enabled, we have to create VLAN interface
1683                          * to make hypervisor to setup E-Switch vport
1684                          * context correctly. We avoid creating the multiple
1685                          * VLAN interfaces, so we cannot support VLAN tag mask.
1686                          */
1687                         return rte_flow_error_set(error, EINVAL,
1688                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1689                                                   item,
1690                                                   "VLAN tag mask is not"
1691                                                   " supported in virtual"
1692                                                   " environment");
1693                 }
1694         }
1695         return 0;
1696 }
1697
1698 /*
1699  * GTP flags are contained in 1 byte of the format:
1700  * -------------------------------------------
1701  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1702  * |-----------------------------------------|
1703  * | value | Version | PT | Res | E | S | PN |
1704  * -------------------------------------------
1705  *
1706  * Matching is supported only for GTP flags E, S, PN.
1707  */
1708 #define MLX5_GTP_FLAGS_MASK     0x07
1709
1710 /**
1711  * Validate GTP item.
1712  *
1713  * @param[in] dev
1714  *   Pointer to the rte_eth_dev structure.
1715  * @param[in] item
1716  *   Item specification.
1717  * @param[in] item_flags
1718  *   Bit-fields that holds the items detected until now.
1719  * @param[out] error
1720  *   Pointer to error structure.
1721  *
1722  * @return
1723  *   0 on success, a negative errno value otherwise and rte_errno is set.
1724  */
1725 static int
1726 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1727                           const struct rte_flow_item *item,
1728                           uint64_t item_flags,
1729                           struct rte_flow_error *error)
1730 {
1731         struct mlx5_priv *priv = dev->data->dev_private;
1732         const struct rte_flow_item_gtp *spec = item->spec;
1733         const struct rte_flow_item_gtp *mask = item->mask;
1734         const struct rte_flow_item_gtp nic_mask = {
1735                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1736                 .msg_type = 0xff,
1737                 .teid = RTE_BE32(0xffffffff),
1738         };
1739
1740         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "GTP support is not enabled");
1744         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1745                 return rte_flow_error_set(error, ENOTSUP,
1746                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1747                                           "multiple tunnel layers not"
1748                                           " supported");
1749         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1750                 return rte_flow_error_set(error, EINVAL,
1751                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1752                                           "no outer UDP layer found");
1753         if (!mask)
1754                 mask = &rte_flow_item_gtp_mask;
1755         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1756                 return rte_flow_error_set(error, ENOTSUP,
1757                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1758                                           "Match is supported for GTP"
1759                                           " flags only");
1760         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1761                                          (const uint8_t *)&nic_mask,
1762                                          sizeof(struct rte_flow_item_gtp),
1763                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1764 }
1765
1766 /**
1767  * Validate GTP PSC item.
1768  *
1769  * @param[in] item
1770  *   Item specification.
1771  * @param[in] last_item
1772  *   Previous validated item in the pattern items.
1773  * @param[in] gtp_item
1774  *   Previous GTP item specification.
1775  * @param[in] attr
1776  *   Pointer to flow attributes.
1777  * @param[out] error
1778  *   Pointer to error structure.
1779  *
1780  * @return
1781  *   0 on success, a negative errno value otherwise and rte_errno is set.
1782  */
1783 static int
1784 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
1785                               uint64_t last_item,
1786                               const struct rte_flow_item *gtp_item,
1787                               const struct rte_flow_attr *attr,
1788                               struct rte_flow_error *error)
1789 {
1790         const struct rte_flow_item_gtp *gtp_spec;
1791         const struct rte_flow_item_gtp *gtp_mask;
1792         const struct rte_flow_item_gtp_psc *spec;
1793         const struct rte_flow_item_gtp_psc *mask;
1794         const struct rte_flow_item_gtp_psc nic_mask = {
1795                 .pdu_type = 0xFF,
1796                 .qfi = 0xFF,
1797         };
1798
1799         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
1800                 return rte_flow_error_set
1801                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1802                          "GTP PSC item must be preceded with GTP item");
1803         gtp_spec = gtp_item->spec;
1804         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
1805         /* GTP spec and E flag is requested to match zero. */
1806         if (gtp_spec &&
1807                 (gtp_mask->v_pt_rsv_flags &
1808                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
1809                 return rte_flow_error_set
1810                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1811                          "GTP E flag must be 1 to match GTP PSC");
1812         /* Check the flow is not created in group zero. */
1813         if (!attr->transfer && !attr->group)
1814                 return rte_flow_error_set
1815                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1816                          "GTP PSC is not supported for group 0");
1817         /* GTP spec is here and E flag is requested to match zero. */
1818         if (!item->spec)
1819                 return 0;
1820         spec = item->spec;
1821         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
1822         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
1823                 return rte_flow_error_set
1824                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
1825                          "PDU type should be smaller than 16");
1826         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1827                                          (const uint8_t *)&nic_mask,
1828                                          sizeof(struct rte_flow_item_gtp_psc),
1829                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1830 }
1831
1832 /**
1833  * Validate IPV4 item.
1834  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1835  * add specific validation of fragment_offset field,
1836  *
1837  * @param[in] item
1838  *   Item specification.
1839  * @param[in] item_flags
1840  *   Bit-fields that holds the items detected until now.
1841  * @param[out] error
1842  *   Pointer to error structure.
1843  *
1844  * @return
1845  *   0 on success, a negative errno value otherwise and rte_errno is set.
1846  */
1847 static int
1848 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1849                            uint64_t item_flags,
1850                            uint64_t last_item,
1851                            uint16_t ether_type,
1852                            struct rte_flow_error *error)
1853 {
1854         int ret;
1855         const struct rte_flow_item_ipv4 *spec = item->spec;
1856         const struct rte_flow_item_ipv4 *last = item->last;
1857         const struct rte_flow_item_ipv4 *mask = item->mask;
1858         rte_be16_t fragment_offset_spec = 0;
1859         rte_be16_t fragment_offset_last = 0;
1860         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1861                 .hdr = {
1862                         .src_addr = RTE_BE32(0xffffffff),
1863                         .dst_addr = RTE_BE32(0xffffffff),
1864                         .type_of_service = 0xff,
1865                         .fragment_offset = RTE_BE16(0xffff),
1866                         .next_proto_id = 0xff,
1867                         .time_to_live = 0xff,
1868                 },
1869         };
1870
1871         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1872                                            ether_type, &nic_ipv4_mask,
1873                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1874         if (ret < 0)
1875                 return ret;
1876         if (spec && mask)
1877                 fragment_offset_spec = spec->hdr.fragment_offset &
1878                                        mask->hdr.fragment_offset;
1879         if (!fragment_offset_spec)
1880                 return 0;
1881         /*
1882          * spec and mask are valid, enforce using full mask to make sure the
1883          * complete value is used correctly.
1884          */
1885         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1886                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1887                 return rte_flow_error_set(error, EINVAL,
1888                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1889                                           item, "must use full mask for"
1890                                           " fragment_offset");
1891         /*
1892          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1893          * indicating this is 1st fragment of fragmented packet.
1894          * This is not yet supported in MLX5, return appropriate error message.
1895          */
1896         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1897                 return rte_flow_error_set(error, ENOTSUP,
1898                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1899                                           "match on first fragment not "
1900                                           "supported");
1901         if (fragment_offset_spec && !last)
1902                 return rte_flow_error_set(error, ENOTSUP,
1903                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1904                                           "specified value not supported");
1905         /* spec and last are valid, validate the specified range. */
1906         fragment_offset_last = last->hdr.fragment_offset &
1907                                mask->hdr.fragment_offset;
1908         /*
1909          * Match on fragment_offset spec 0x2001 and last 0x3fff
1910          * means MF is 1 and frag-offset is > 0.
1911          * This packet is fragment 2nd and onward, excluding last.
1912          * This is not yet supported in MLX5, return appropriate
1913          * error message.
1914          */
1915         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1916             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1917                 return rte_flow_error_set(error, ENOTSUP,
1918                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1919                                           last, "match on following "
1920                                           "fragments not supported");
1921         /*
1922          * Match on fragment_offset spec 0x0001 and last 0x1fff
1923          * means MF is 0 and frag-offset is > 0.
1924          * This packet is last fragment of fragmented packet.
1925          * This is not yet supported in MLX5, return appropriate
1926          * error message.
1927          */
1928         if (fragment_offset_spec == RTE_BE16(1) &&
1929             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1930                 return rte_flow_error_set(error, ENOTSUP,
1931                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1932                                           last, "match on last "
1933                                           "fragment not supported");
1934         /*
1935          * Match on fragment_offset spec 0x0001 and last 0x3fff
1936          * means MF and/or frag-offset is not 0.
1937          * This is a fragmented packet.
1938          * Other range values are invalid and rejected.
1939          */
1940         if (!(fragment_offset_spec == RTE_BE16(1) &&
1941               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1942                 return rte_flow_error_set(error, ENOTSUP,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1944                                           "specified range not supported");
1945         return 0;
1946 }
1947
1948 /**
1949  * Validate IPV6 fragment extension item.
1950  *
1951  * @param[in] item
1952  *   Item specification.
1953  * @param[in] item_flags
1954  *   Bit-fields that holds the items detected until now.
1955  * @param[out] error
1956  *   Pointer to error structure.
1957  *
1958  * @return
1959  *   0 on success, a negative errno value otherwise and rte_errno is set.
1960  */
1961 static int
1962 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1963                                     uint64_t item_flags,
1964                                     struct rte_flow_error *error)
1965 {
1966         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1967         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1968         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1969         rte_be16_t frag_data_spec = 0;
1970         rte_be16_t frag_data_last = 0;
1971         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1972         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1973                                       MLX5_FLOW_LAYER_OUTER_L4;
1974         int ret = 0;
1975         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1976                 .hdr = {
1977                         .next_header = 0xff,
1978                         .frag_data = RTE_BE16(0xffff),
1979                 },
1980         };
1981
1982         if (item_flags & l4m)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1985                                           "ipv6 fragment extension item cannot "
1986                                           "follow L4 item.");
1987         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1988             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1989                 return rte_flow_error_set(error, EINVAL,
1990                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                           "ipv6 fragment extension item must "
1992                                           "follow ipv6 item");
1993         if (spec && mask)
1994                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1995         if (!frag_data_spec)
1996                 return 0;
1997         /*
1998          * spec and mask are valid, enforce using full mask to make sure the
1999          * complete value is used correctly.
2000          */
2001         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2002                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2003                 return rte_flow_error_set(error, EINVAL,
2004                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2005                                           item, "must use full mask for"
2006                                           " frag_data");
2007         /*
2008          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2009          * This is 1st fragment of fragmented packet.
2010          */
2011         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2012                 return rte_flow_error_set(error, ENOTSUP,
2013                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2014                                           "match on first fragment not "
2015                                           "supported");
2016         if (frag_data_spec && !last)
2017                 return rte_flow_error_set(error, EINVAL,
2018                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2019                                           "specified value not supported");
2020         ret = mlx5_flow_item_acceptable
2021                                 (item, (const uint8_t *)mask,
2022                                  (const uint8_t *)&nic_mask,
2023                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2024                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2025         if (ret)
2026                 return ret;
2027         /* spec and last are valid, validate the specified range. */
2028         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2029         /*
2030          * Match on frag_data spec 0x0009 and last 0xfff9
2031          * means M is 1 and frag-offset is > 0.
2032          * This packet is fragment 2nd and onward, excluding last.
2033          * This is not yet supported in MLX5, return appropriate
2034          * error message.
2035          */
2036         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2037                                        RTE_IPV6_EHDR_MF_MASK) &&
2038             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2039                 return rte_flow_error_set(error, ENOTSUP,
2040                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2041                                           last, "match on following "
2042                                           "fragments not supported");
2043         /*
2044          * Match on frag_data spec 0x0008 and last 0xfff8
2045          * means M is 0 and frag-offset is > 0.
2046          * This packet is last fragment of fragmented packet.
2047          * This is not yet supported in MLX5, return appropriate
2048          * error message.
2049          */
2050         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2051             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2052                 return rte_flow_error_set(error, ENOTSUP,
2053                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2054                                           last, "match on last "
2055                                           "fragment not supported");
2056         /* Other range values are invalid and rejected. */
2057         return rte_flow_error_set(error, EINVAL,
2058                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2059                                   "specified range not supported");
2060 }
2061
2062 /**
2063  * Validate the pop VLAN action.
2064  *
2065  * @param[in] dev
2066  *   Pointer to the rte_eth_dev structure.
2067  * @param[in] action_flags
2068  *   Holds the actions detected until now.
2069  * @param[in] action
2070  *   Pointer to the pop vlan action.
2071  * @param[in] item_flags
2072  *   The items found in this flow rule.
2073  * @param[in] attr
2074  *   Pointer to flow attributes.
2075  * @param[out] error
2076  *   Pointer to error structure.
2077  *
2078  * @return
2079  *   0 on success, a negative errno value otherwise and rte_errno is set.
2080  */
2081 static int
2082 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2083                                  uint64_t action_flags,
2084                                  const struct rte_flow_action *action,
2085                                  uint64_t item_flags,
2086                                  const struct rte_flow_attr *attr,
2087                                  struct rte_flow_error *error)
2088 {
2089         const struct mlx5_priv *priv = dev->data->dev_private;
2090
2091         (void)action;
2092         (void)attr;
2093         if (!priv->sh->pop_vlan_action)
2094                 return rte_flow_error_set(error, ENOTSUP,
2095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2096                                           NULL,
2097                                           "pop vlan action is not supported");
2098         if (attr->egress)
2099                 return rte_flow_error_set(error, ENOTSUP,
2100                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2101                                           NULL,
2102                                           "pop vlan action not supported for "
2103                                           "egress");
2104         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2105                 return rte_flow_error_set(error, ENOTSUP,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2107                                           "no support for multiple VLAN "
2108                                           "actions");
2109         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2110         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2111             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2112                 return rte_flow_error_set(error, ENOTSUP,
2113                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2114                                           NULL,
2115                                           "cannot pop vlan after decap without "
2116                                           "match on inner vlan in the flow");
2117         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2118         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2119             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2122                                           NULL,
2123                                           "cannot pop vlan without a "
2124                                           "match on (outer) vlan in the flow");
2125         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2126                 return rte_flow_error_set(error, EINVAL,
2127                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2128                                           "wrong action order, port_id should "
2129                                           "be after pop VLAN action");
2130         if (!attr->transfer && priv->representor)
2131                 return rte_flow_error_set(error, ENOTSUP,
2132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2133                                           "pop vlan action for VF representor "
2134                                           "not supported on NIC table");
2135         return 0;
2136 }
2137
2138 /**
2139  * Get VLAN default info from vlan match info.
2140  *
2141  * @param[in] items
2142  *   the list of item specifications.
2143  * @param[out] vlan
2144  *   pointer VLAN info to fill to.
2145  *
2146  * @return
2147  *   0 on success, a negative errno value otherwise and rte_errno is set.
2148  */
2149 static void
2150 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2151                                   struct rte_vlan_hdr *vlan)
2152 {
2153         const struct rte_flow_item_vlan nic_mask = {
2154                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2155                                 MLX5DV_FLOW_VLAN_VID_MASK),
2156                 .inner_type = RTE_BE16(0xffff),
2157         };
2158
2159         if (items == NULL)
2160                 return;
2161         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2162                 int type = items->type;
2163
2164                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2165                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2166                         break;
2167         }
2168         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2169                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2170                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2171
2172                 /* If VLAN item in pattern doesn't contain data, return here. */
2173                 if (!vlan_v)
2174                         return;
2175                 if (!vlan_m)
2176                         vlan_m = &nic_mask;
2177                 /* Only full match values are accepted */
2178                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2179                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2180                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2181                         vlan->vlan_tci |=
2182                                 rte_be_to_cpu_16(vlan_v->tci &
2183                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2184                 }
2185                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2186                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2187                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2188                         vlan->vlan_tci |=
2189                                 rte_be_to_cpu_16(vlan_v->tci &
2190                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2191                 }
2192                 if (vlan_m->inner_type == nic_mask.inner_type)
2193                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2194                                                            vlan_m->inner_type);
2195         }
2196 }
2197
2198 /**
2199  * Validate the push VLAN action.
2200  *
2201  * @param[in] dev
2202  *   Pointer to the rte_eth_dev structure.
2203  * @param[in] action_flags
2204  *   Holds the actions detected until now.
2205  * @param[in] item_flags
2206  *   The items found in this flow rule.
2207  * @param[in] action
2208  *   Pointer to the action structure.
2209  * @param[in] attr
2210  *   Pointer to flow attributes
2211  * @param[out] error
2212  *   Pointer to error structure.
2213  *
2214  * @return
2215  *   0 on success, a negative errno value otherwise and rte_errno is set.
2216  */
2217 static int
2218 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2219                                   uint64_t action_flags,
2220                                   const struct rte_flow_item_vlan *vlan_m,
2221                                   const struct rte_flow_action *action,
2222                                   const struct rte_flow_attr *attr,
2223                                   struct rte_flow_error *error)
2224 {
2225         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2226         const struct mlx5_priv *priv = dev->data->dev_private;
2227
2228         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2229             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2230                 return rte_flow_error_set(error, EINVAL,
2231                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2232                                           "invalid vlan ethertype");
2233         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2234                 return rte_flow_error_set(error, EINVAL,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "wrong action order, port_id should "
2237                                           "be after push VLAN");
2238         if (!attr->transfer && priv->representor)
2239                 return rte_flow_error_set(error, ENOTSUP,
2240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241                                           "push vlan action for VF representor "
2242                                           "not supported on NIC table");
2243         if (vlan_m &&
2244             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2245             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2246                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2247             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2248             !(mlx5_flow_find_action
2249                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2250                 return rte_flow_error_set(error, EINVAL,
2251                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2252                                           "not full match mask on VLAN PCP and "
2253                                           "there is no of_set_vlan_pcp action, "
2254                                           "push VLAN action cannot figure out "
2255                                           "PCP value");
2256         if (vlan_m &&
2257             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2258             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2259                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2260             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2261             !(mlx5_flow_find_action
2262                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2263                 return rte_flow_error_set(error, EINVAL,
2264                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2265                                           "not full match mask on VLAN VID and "
2266                                           "there is no of_set_vlan_vid action, "
2267                                           "push VLAN action cannot figure out "
2268                                           "VID value");
2269         (void)attr;
2270         return 0;
2271 }
2272
2273 /**
2274  * Validate the set VLAN PCP.
2275  *
2276  * @param[in] action_flags
2277  *   Holds the actions detected until now.
2278  * @param[in] actions
2279  *   Pointer to the list of actions remaining in the flow rule.
2280  * @param[out] error
2281  *   Pointer to error structure.
2282  *
2283  * @return
2284  *   0 on success, a negative errno value otherwise and rte_errno is set.
2285  */
2286 static int
2287 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2288                                      const struct rte_flow_action actions[],
2289                                      struct rte_flow_error *error)
2290 {
2291         const struct rte_flow_action *action = actions;
2292         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2293
2294         if (conf->vlan_pcp > 7)
2295                 return rte_flow_error_set(error, EINVAL,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "VLAN PCP value is too big");
2298         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "set VLAN PCP action must follow "
2302                                           "the push VLAN action");
2303         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2304                 return rte_flow_error_set(error, ENOTSUP,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "Multiple VLAN PCP modification are "
2307                                           "not supported");
2308         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "wrong action order, port_id should "
2312                                           "be after set VLAN PCP");
2313         return 0;
2314 }
2315
2316 /**
2317  * Validate the set VLAN VID.
2318  *
2319  * @param[in] item_flags
2320  *   Holds the items detected in this rule.
2321  * @param[in] action_flags
2322  *   Holds the actions detected until now.
2323  * @param[in] actions
2324  *   Pointer to the list of actions remaining in the flow rule.
2325  * @param[out] error
2326  *   Pointer to error structure.
2327  *
2328  * @return
2329  *   0 on success, a negative errno value otherwise and rte_errno is set.
2330  */
2331 static int
2332 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2333                                      uint64_t action_flags,
2334                                      const struct rte_flow_action actions[],
2335                                      struct rte_flow_error *error)
2336 {
2337         const struct rte_flow_action *action = actions;
2338         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2339
2340         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2341                 return rte_flow_error_set(error, EINVAL,
2342                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2343                                           "VLAN VID value is too big");
2344         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2345             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2346                 return rte_flow_error_set(error, ENOTSUP,
2347                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2348                                           "set VLAN VID action must follow push"
2349                                           " VLAN action or match on VLAN item");
2350         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2351                 return rte_flow_error_set(error, ENOTSUP,
2352                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2353                                           "Multiple VLAN VID modifications are "
2354                                           "not supported");
2355         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2356                 return rte_flow_error_set(error, EINVAL,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2358                                           "wrong action order, port_id should "
2359                                           "be after set VLAN VID");
2360         return 0;
2361 }
2362
2363 /*
2364  * Validate the FLAG action.
2365  *
2366  * @param[in] dev
2367  *   Pointer to the rte_eth_dev structure.
2368  * @param[in] action_flags
2369  *   Holds the actions detected until now.
2370  * @param[in] attr
2371  *   Pointer to flow attributes
2372  * @param[out] error
2373  *   Pointer to error structure.
2374  *
2375  * @return
2376  *   0 on success, a negative errno value otherwise and rte_errno is set.
2377  */
2378 static int
2379 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2380                              uint64_t action_flags,
2381                              const struct rte_flow_attr *attr,
2382                              struct rte_flow_error *error)
2383 {
2384         struct mlx5_priv *priv = dev->data->dev_private;
2385         struct mlx5_dev_config *config = &priv->config;
2386         int ret;
2387
2388         /* Fall back if no extended metadata register support. */
2389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2390                 return mlx5_flow_validate_action_flag(action_flags, attr,
2391                                                       error);
2392         /* Extensive metadata mode requires registers. */
2393         if (!mlx5_flow_ext_mreg_supported(dev))
2394                 return rte_flow_error_set(error, ENOTSUP,
2395                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2396                                           "no metadata registers "
2397                                           "to support flag action");
2398         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2399                 return rte_flow_error_set(error, ENOTSUP,
2400                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401                                           "extended metadata register"
2402                                           " isn't available");
2403         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2404         if (ret < 0)
2405                 return ret;
2406         MLX5_ASSERT(ret > 0);
2407         if (action_flags & MLX5_FLOW_ACTION_MARK)
2408                 return rte_flow_error_set(error, EINVAL,
2409                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2410                                           "can't mark and flag in same flow");
2411         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2412                 return rte_flow_error_set(error, EINVAL,
2413                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2414                                           "can't have 2 flag"
2415                                           " actions in same flow");
2416         return 0;
2417 }
2418
2419 /**
2420  * Validate MARK action.
2421  *
2422  * @param[in] dev
2423  *   Pointer to the rte_eth_dev structure.
2424  * @param[in] action
2425  *   Pointer to action.
2426  * @param[in] action_flags
2427  *   Holds the actions detected until now.
2428  * @param[in] attr
2429  *   Pointer to flow attributes
2430  * @param[out] error
2431  *   Pointer to error structure.
2432  *
2433  * @return
2434  *   0 on success, a negative errno value otherwise and rte_errno is set.
2435  */
2436 static int
2437 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2438                              const struct rte_flow_action *action,
2439                              uint64_t action_flags,
2440                              const struct rte_flow_attr *attr,
2441                              struct rte_flow_error *error)
2442 {
2443         struct mlx5_priv *priv = dev->data->dev_private;
2444         struct mlx5_dev_config *config = &priv->config;
2445         const struct rte_flow_action_mark *mark = action->conf;
2446         int ret;
2447
2448         if (is_tunnel_offload_active(dev))
2449                 return rte_flow_error_set(error, ENOTSUP,
2450                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2451                                           "no mark action "
2452                                           "if tunnel offload active");
2453         /* Fall back if no extended metadata register support. */
2454         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2455                 return mlx5_flow_validate_action_mark(action, action_flags,
2456                                                       attr, error);
2457         /* Extensive metadata mode requires registers. */
2458         if (!mlx5_flow_ext_mreg_supported(dev))
2459                 return rte_flow_error_set(error, ENOTSUP,
2460                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461                                           "no metadata registers "
2462                                           "to support mark action");
2463         if (!priv->sh->dv_mark_mask)
2464                 return rte_flow_error_set(error, ENOTSUP,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2466                                           "extended metadata register"
2467                                           " isn't available");
2468         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2469         if (ret < 0)
2470                 return ret;
2471         MLX5_ASSERT(ret > 0);
2472         if (!mark)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2475                                           "configuration cannot be null");
2476         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2477                 return rte_flow_error_set(error, EINVAL,
2478                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2479                                           &mark->id,
2480                                           "mark id exceeds the limit");
2481         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2482                 return rte_flow_error_set(error, EINVAL,
2483                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2484                                           "can't flag and mark in same flow");
2485         if (action_flags & MLX5_FLOW_ACTION_MARK)
2486                 return rte_flow_error_set(error, EINVAL,
2487                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2488                                           "can't have 2 mark actions in same"
2489                                           " flow");
2490         return 0;
2491 }
2492
2493 /**
2494  * Validate SET_META action.
2495  *
2496  * @param[in] dev
2497  *   Pointer to the rte_eth_dev structure.
2498  * @param[in] action
2499  *   Pointer to the action structure.
2500  * @param[in] action_flags
2501  *   Holds the actions detected until now.
2502  * @param[in] attr
2503  *   Pointer to flow attributes
2504  * @param[out] error
2505  *   Pointer to error structure.
2506  *
2507  * @return
2508  *   0 on success, a negative errno value otherwise and rte_errno is set.
2509  */
2510 static int
2511 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2512                                  const struct rte_flow_action *action,
2513                                  uint64_t action_flags __rte_unused,
2514                                  const struct rte_flow_attr *attr,
2515                                  struct rte_flow_error *error)
2516 {
2517         const struct rte_flow_action_set_meta *conf;
2518         uint32_t nic_mask = UINT32_MAX;
2519         int reg;
2520
2521         if (!mlx5_flow_ext_mreg_supported(dev))
2522                 return rte_flow_error_set(error, ENOTSUP,
2523                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2524                                           "extended metadata register"
2525                                           " isn't supported");
2526         reg = flow_dv_get_metadata_reg(dev, attr, error);
2527         if (reg < 0)
2528                 return reg;
2529         if (reg == REG_NON)
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2532                                           "unavalable extended metadata register");
2533         if (reg != REG_A && reg != REG_B) {
2534                 struct mlx5_priv *priv = dev->data->dev_private;
2535
2536                 nic_mask = priv->sh->dv_meta_mask;
2537         }
2538         if (!(action->conf))
2539                 return rte_flow_error_set(error, EINVAL,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "configuration cannot be null");
2542         conf = (const struct rte_flow_action_set_meta *)action->conf;
2543         if (!conf->mask)
2544                 return rte_flow_error_set(error, EINVAL,
2545                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2546                                           "zero mask doesn't have any effect");
2547         if (conf->mask & ~nic_mask)
2548                 return rte_flow_error_set(error, EINVAL,
2549                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2550                                           "meta data must be within reg C0");
2551         return 0;
2552 }
2553
2554 /**
2555  * Validate SET_TAG action.
2556  *
2557  * @param[in] dev
2558  *   Pointer to the rte_eth_dev structure.
2559  * @param[in] action
2560  *   Pointer to the action structure.
2561  * @param[in] action_flags
2562  *   Holds the actions detected until now.
2563  * @param[in] attr
2564  *   Pointer to flow attributes
2565  * @param[out] error
2566  *   Pointer to error structure.
2567  *
2568  * @return
2569  *   0 on success, a negative errno value otherwise and rte_errno is set.
2570  */
2571 static int
2572 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2573                                 const struct rte_flow_action *action,
2574                                 uint64_t action_flags,
2575                                 const struct rte_flow_attr *attr,
2576                                 struct rte_flow_error *error)
2577 {
2578         const struct rte_flow_action_set_tag *conf;
2579         const uint64_t terminal_action_flags =
2580                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2581                 MLX5_FLOW_ACTION_RSS;
2582         int ret;
2583
2584         if (!mlx5_flow_ext_mreg_supported(dev))
2585                 return rte_flow_error_set(error, ENOTSUP,
2586                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2587                                           "extensive metadata register"
2588                                           " isn't supported");
2589         if (!(action->conf))
2590                 return rte_flow_error_set(error, EINVAL,
2591                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2592                                           "configuration cannot be null");
2593         conf = (const struct rte_flow_action_set_tag *)action->conf;
2594         if (!conf->mask)
2595                 return rte_flow_error_set(error, EINVAL,
2596                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2597                                           "zero mask doesn't have any effect");
2598         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2599         if (ret < 0)
2600                 return ret;
2601         if (!attr->transfer && attr->ingress &&
2602             (action_flags & terminal_action_flags))
2603                 return rte_flow_error_set(error, EINVAL,
2604                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2605                                           "set_tag has no effect"
2606                                           " with terminal actions");
2607         return 0;
2608 }
2609
2610 /**
2611  * Validate count action.
2612  *
2613  * @param[in] dev
2614  *   Pointer to rte_eth_dev structure.
2615  * @param[out] error
2616  *   Pointer to error structure.
2617  *
2618  * @return
2619  *   0 on success, a negative errno value otherwise and rte_errno is set.
2620  */
2621 static int
2622 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2623                               struct rte_flow_error *error)
2624 {
2625         struct mlx5_priv *priv = dev->data->dev_private;
2626
2627         if (!priv->config.devx)
2628                 goto notsup_err;
2629 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2630         return 0;
2631 #endif
2632 notsup_err:
2633         return rte_flow_error_set
2634                       (error, ENOTSUP,
2635                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2636                        NULL,
2637                        "count action not supported");
2638 }
2639
2640 /**
2641  * Validate the L2 encap action.
2642  *
2643  * @param[in] dev
2644  *   Pointer to the rte_eth_dev structure.
2645  * @param[in] action_flags
2646  *   Holds the actions detected until now.
2647  * @param[in] action
2648  *   Pointer to the action structure.
2649  * @param[in] attr
2650  *   Pointer to flow attributes.
2651  * @param[out] error
2652  *   Pointer to error structure.
2653  *
2654  * @return
2655  *   0 on success, a negative errno value otherwise and rte_errno is set.
2656  */
2657 static int
2658 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2659                                  uint64_t action_flags,
2660                                  const struct rte_flow_action *action,
2661                                  const struct rte_flow_attr *attr,
2662                                  struct rte_flow_error *error)
2663 {
2664         const struct mlx5_priv *priv = dev->data->dev_private;
2665
2666         if (!(action->conf))
2667                 return rte_flow_error_set(error, EINVAL,
2668                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2669                                           "configuration cannot be null");
2670         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2671                 return rte_flow_error_set(error, EINVAL,
2672                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2673                                           "can only have a single encap action "
2674                                           "in a flow");
2675         if (!attr->transfer && priv->representor)
2676                 return rte_flow_error_set(error, ENOTSUP,
2677                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2678                                           "encap action for VF representor "
2679                                           "not supported on NIC table");
2680         return 0;
2681 }
2682
2683 /**
2684  * Validate a decap action.
2685  *
2686  * @param[in] dev
2687  *   Pointer to the rte_eth_dev structure.
2688  * @param[in] action_flags
2689  *   Holds the actions detected until now.
2690  * @param[in] action
2691  *   Pointer to the action structure.
2692  * @param[in] item_flags
2693  *   Holds the items detected.
2694  * @param[in] attr
2695  *   Pointer to flow attributes
2696  * @param[out] error
2697  *   Pointer to error structure.
2698  *
2699  * @return
2700  *   0 on success, a negative errno value otherwise and rte_errno is set.
2701  */
2702 static int
2703 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2704                               uint64_t action_flags,
2705                               const struct rte_flow_action *action,
2706                               const uint64_t item_flags,
2707                               const struct rte_flow_attr *attr,
2708                               struct rte_flow_error *error)
2709 {
2710         const struct mlx5_priv *priv = dev->data->dev_private;
2711
2712         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2713             !priv->config.decap_en)
2714                 return rte_flow_error_set(error, ENOTSUP,
2715                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2716                                           "decap is not enabled");
2717         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2718                 return rte_flow_error_set(error, ENOTSUP,
2719                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2720                                           action_flags &
2721                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2722                                           "have a single decap action" : "decap "
2723                                           "after encap is not supported");
2724         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2725                 return rte_flow_error_set(error, EINVAL,
2726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727                                           "can't have decap action after"
2728                                           " modify action");
2729         if (attr->egress)
2730                 return rte_flow_error_set(error, ENOTSUP,
2731                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2732                                           NULL,
2733                                           "decap action not supported for "
2734                                           "egress");
2735         if (!attr->transfer && priv->representor)
2736                 return rte_flow_error_set(error, ENOTSUP,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2738                                           "decap action for VF representor "
2739                                           "not supported on NIC table");
2740         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2741             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2742                 return rte_flow_error_set(error, ENOTSUP,
2743                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2744                                 "VXLAN item should be present for VXLAN decap");
2745         return 0;
2746 }
2747
2748 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2749
2750 /**
2751  * Validate the raw encap and decap actions.
2752  *
2753  * @param[in] dev
2754  *   Pointer to the rte_eth_dev structure.
2755  * @param[in] decap
2756  *   Pointer to the decap action.
2757  * @param[in] encap
2758  *   Pointer to the encap action.
2759  * @param[in] attr
2760  *   Pointer to flow attributes
2761  * @param[in/out] action_flags
2762  *   Holds the actions detected until now.
2763  * @param[out] actions_n
2764  *   pointer to the number of actions counter.
2765  * @param[in] action
2766  *   Pointer to the action structure.
2767  * @param[in] item_flags
2768  *   Holds the items detected.
2769  * @param[out] error
2770  *   Pointer to error structure.
2771  *
2772  * @return
2773  *   0 on success, a negative errno value otherwise and rte_errno is set.
2774  */
2775 static int
2776 flow_dv_validate_action_raw_encap_decap
2777         (struct rte_eth_dev *dev,
2778          const struct rte_flow_action_raw_decap *decap,
2779          const struct rte_flow_action_raw_encap *encap,
2780          const struct rte_flow_attr *attr, uint64_t *action_flags,
2781          int *actions_n, const struct rte_flow_action *action,
2782          uint64_t item_flags, struct rte_flow_error *error)
2783 {
2784         const struct mlx5_priv *priv = dev->data->dev_private;
2785         int ret;
2786
2787         if (encap && (!encap->size || !encap->data))
2788                 return rte_flow_error_set(error, EINVAL,
2789                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2790                                           "raw encap data cannot be empty");
2791         if (decap && encap) {
2792                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2793                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2794                         /* L3 encap. */
2795                         decap = NULL;
2796                 else if (encap->size <=
2797                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2798                            decap->size >
2799                            MLX5_ENCAPSULATION_DECISION_SIZE)
2800                         /* L3 decap. */
2801                         encap = NULL;
2802                 else if (encap->size >
2803                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2804                            decap->size >
2805                            MLX5_ENCAPSULATION_DECISION_SIZE)
2806                         /* 2 L2 actions: encap and decap. */
2807                         ;
2808                 else
2809                         return rte_flow_error_set(error,
2810                                 ENOTSUP,
2811                                 RTE_FLOW_ERROR_TYPE_ACTION,
2812                                 NULL, "unsupported too small "
2813                                 "raw decap and too small raw "
2814                                 "encap combination");
2815         }
2816         if (decap) {
2817                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2818                                                     item_flags, attr, error);
2819                 if (ret < 0)
2820                         return ret;
2821                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2822                 ++(*actions_n);
2823         }
2824         if (encap) {
2825                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2826                         return rte_flow_error_set(error, ENOTSUP,
2827                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2828                                                   NULL,
2829                                                   "small raw encap size");
2830                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2831                         return rte_flow_error_set(error, EINVAL,
2832                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2833                                                   NULL,
2834                                                   "more than one encap action");
2835                 if (!attr->transfer && priv->representor)
2836                         return rte_flow_error_set
2837                                         (error, ENOTSUP,
2838                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2839                                          "encap action for VF representor "
2840                                          "not supported on NIC table");
2841                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2842                 ++(*actions_n);
2843         }
2844         return 0;
2845 }
2846
2847 /**
2848  * Match encap_decap resource.
2849  *
2850  * @param list
2851  *   Pointer to the hash list.
2852  * @param entry
2853  *   Pointer to exist resource entry object.
2854  * @param key
2855  *   Key of the new entry.
2856  * @param ctx_cb
2857  *   Pointer to new encap_decap resource.
2858  *
2859  * @return
2860  *   0 on matching, none-zero otherwise.
2861  */
2862 int
2863 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2864                              struct mlx5_hlist_entry *entry,
2865                              uint64_t key __rte_unused, void *cb_ctx)
2866 {
2867         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2868         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2869         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2870
2871         cache_resource = container_of(entry,
2872                                       struct mlx5_flow_dv_encap_decap_resource,
2873                                       entry);
2874         if (resource->reformat_type == cache_resource->reformat_type &&
2875             resource->ft_type == cache_resource->ft_type &&
2876             resource->flags == cache_resource->flags &&
2877             resource->size == cache_resource->size &&
2878             !memcmp((const void *)resource->buf,
2879                     (const void *)cache_resource->buf,
2880                     resource->size))
2881                 return 0;
2882         return -1;
2883 }
2884
2885 /**
2886  * Allocate encap_decap resource.
2887  *
2888  * @param list
2889  *   Pointer to the hash list.
2890  * @param entry
2891  *   Pointer to exist resource entry object.
2892  * @param ctx_cb
2893  *   Pointer to new encap_decap resource.
2894  *
2895  * @return
2896  *   0 on matching, none-zero otherwise.
2897  */
2898 struct mlx5_hlist_entry *
2899 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2900                               uint64_t key __rte_unused,
2901                               void *cb_ctx)
2902 {
2903         struct mlx5_dev_ctx_shared *sh = list->ctx;
2904         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2905         struct mlx5dv_dr_domain *domain;
2906         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2907         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2908         uint32_t idx;
2909         int ret;
2910
2911         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2912                 domain = sh->fdb_domain;
2913         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2914                 domain = sh->rx_domain;
2915         else
2916                 domain = sh->tx_domain;
2917         /* Register new encap/decap resource. */
2918         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2919                                        &idx);
2920         if (!cache_resource) {
2921                 rte_flow_error_set(ctx->error, ENOMEM,
2922                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2923                                    "cannot allocate resource memory");
2924                 return NULL;
2925         }
2926         *cache_resource = *resource;
2927         cache_resource->idx = idx;
2928         ret = mlx5_flow_os_create_flow_action_packet_reformat
2929                                         (sh->ctx, domain, cache_resource,
2930                                          &cache_resource->action);
2931         if (ret) {
2932                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2933                 rte_flow_error_set(ctx->error, ENOMEM,
2934                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2935                                    NULL, "cannot create action");
2936                 return NULL;
2937         }
2938
2939         return &cache_resource->entry;
2940 }
2941
2942 /**
2943  * Find existing encap/decap resource or create and register a new one.
2944  *
2945  * @param[in, out] dev
2946  *   Pointer to rte_eth_dev structure.
2947  * @param[in, out] resource
2948  *   Pointer to encap/decap resource.
2949  * @parm[in, out] dev_flow
2950  *   Pointer to the dev_flow.
2951  * @param[out] error
2952  *   pointer to error structure.
2953  *
2954  * @return
2955  *   0 on success otherwise -errno and errno is set.
2956  */
2957 static int
2958 flow_dv_encap_decap_resource_register
2959                         (struct rte_eth_dev *dev,
2960                          struct mlx5_flow_dv_encap_decap_resource *resource,
2961                          struct mlx5_flow *dev_flow,
2962                          struct rte_flow_error *error)
2963 {
2964         struct mlx5_priv *priv = dev->data->dev_private;
2965         struct mlx5_dev_ctx_shared *sh = priv->sh;
2966         struct mlx5_hlist_entry *entry;
2967         union {
2968                 struct {
2969                         uint32_t ft_type:8;
2970                         uint32_t refmt_type:8;
2971                         /*
2972                          * Header reformat actions can be shared between
2973                          * non-root tables. One bit to indicate non-root
2974                          * table or not.
2975                          */
2976                         uint32_t is_root:1;
2977                         uint32_t reserve:15;
2978                 };
2979                 uint32_t v32;
2980         } encap_decap_key = {
2981                 {
2982                         .ft_type = resource->ft_type,
2983                         .refmt_type = resource->reformat_type,
2984                         .is_root = !!dev_flow->dv.group,
2985                         .reserve = 0,
2986                 }
2987         };
2988         struct mlx5_flow_cb_ctx ctx = {
2989                 .error = error,
2990                 .data = resource,
2991         };
2992         uint64_t key64;
2993
2994         resource->flags = dev_flow->dv.group ? 0 : 1;
2995         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2996                                  sizeof(encap_decap_key.v32), 0);
2997         if (resource->reformat_type !=
2998             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2999             resource->size)
3000                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3001         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3002         if (!entry)
3003                 return -rte_errno;
3004         resource = container_of(entry, typeof(*resource), entry);
3005         dev_flow->dv.encap_decap = resource;
3006         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3007         return 0;
3008 }
3009
3010 /**
3011  * Find existing table jump resource or create and register a new one.
3012  *
3013  * @param[in, out] dev
3014  *   Pointer to rte_eth_dev structure.
3015  * @param[in, out] tbl
3016  *   Pointer to flow table resource.
3017  * @parm[in, out] dev_flow
3018  *   Pointer to the dev_flow.
3019  * @param[out] error
3020  *   pointer to error structure.
3021  *
3022  * @return
3023  *   0 on success otherwise -errno and errno is set.
3024  */
3025 static int
3026 flow_dv_jump_tbl_resource_register
3027                         (struct rte_eth_dev *dev __rte_unused,
3028                          struct mlx5_flow_tbl_resource *tbl,
3029                          struct mlx5_flow *dev_flow,
3030                          struct rte_flow_error *error __rte_unused)
3031 {
3032         struct mlx5_flow_tbl_data_entry *tbl_data =
3033                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3034
3035         MLX5_ASSERT(tbl);
3036         MLX5_ASSERT(tbl_data->jump.action);
3037         dev_flow->handle->rix_jump = tbl_data->idx;
3038         dev_flow->dv.jump = &tbl_data->jump;
3039         return 0;
3040 }
3041
3042 int
3043 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3044                          struct mlx5_cache_entry *entry, void *cb_ctx)
3045 {
3046         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3047         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3048         struct mlx5_flow_dv_port_id_action_resource *res =
3049                         container_of(entry, typeof(*res), entry);
3050
3051         return ref->port_id != res->port_id;
3052 }
3053
3054 struct mlx5_cache_entry *
3055 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3056                           struct mlx5_cache_entry *entry __rte_unused,
3057                           void *cb_ctx)
3058 {
3059         struct mlx5_dev_ctx_shared *sh = list->ctx;
3060         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3061         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3062         struct mlx5_flow_dv_port_id_action_resource *cache;
3063         uint32_t idx;
3064         int ret;
3065
3066         /* Register new port id action resource. */
3067         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3068         if (!cache) {
3069                 rte_flow_error_set(ctx->error, ENOMEM,
3070                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3071                                    "cannot allocate port_id action cache memory");
3072                 return NULL;
3073         }
3074         *cache = *ref;
3075         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3076                                                         ref->port_id,
3077                                                         &cache->action);
3078         if (ret) {
3079                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3080                 rte_flow_error_set(ctx->error, ENOMEM,
3081                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082                                    "cannot create action");
3083                 return NULL;
3084         }
3085         return &cache->entry;
3086 }
3087
3088 /**
3089  * Find existing table port ID resource or create and register a new one.
3090  *
3091  * @param[in, out] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in, out] resource
3094  *   Pointer to port ID action resource.
3095  * @parm[in, out] dev_flow
3096  *   Pointer to the dev_flow.
3097  * @param[out] error
3098  *   pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success otherwise -errno and errno is set.
3102  */
3103 static int
3104 flow_dv_port_id_action_resource_register
3105                         (struct rte_eth_dev *dev,
3106                          struct mlx5_flow_dv_port_id_action_resource *resource,
3107                          struct mlx5_flow *dev_flow,
3108                          struct rte_flow_error *error)
3109 {
3110         struct mlx5_priv *priv = dev->data->dev_private;
3111         struct mlx5_cache_entry *entry;
3112         struct mlx5_flow_dv_port_id_action_resource *cache;
3113         struct mlx5_flow_cb_ctx ctx = {
3114                 .error = error,
3115                 .data = resource,
3116         };
3117
3118         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3119         if (!entry)
3120                 return -rte_errno;
3121         cache = container_of(entry, typeof(*cache), entry);
3122         dev_flow->dv.port_id_action = cache;
3123         dev_flow->handle->rix_port_id_action = cache->idx;
3124         return 0;
3125 }
3126
3127 int
3128 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3129                          struct mlx5_cache_entry *entry, void *cb_ctx)
3130 {
3131         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3132         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3133         struct mlx5_flow_dv_push_vlan_action_resource *res =
3134                         container_of(entry, typeof(*res), entry);
3135
3136         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3137 }
3138
3139 struct mlx5_cache_entry *
3140 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3141                           struct mlx5_cache_entry *entry __rte_unused,
3142                           void *cb_ctx)
3143 {
3144         struct mlx5_dev_ctx_shared *sh = list->ctx;
3145         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3146         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3147         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3148         struct mlx5dv_dr_domain *domain;
3149         uint32_t idx;
3150         int ret;
3151
3152         /* Register new port id action resource. */
3153         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3154         if (!cache) {
3155                 rte_flow_error_set(ctx->error, ENOMEM,
3156                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3157                                    "cannot allocate push_vlan action cache memory");
3158                 return NULL;
3159         }
3160         *cache = *ref;
3161         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3162                 domain = sh->fdb_domain;
3163         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3164                 domain = sh->rx_domain;
3165         else
3166                 domain = sh->tx_domain;
3167         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3168                                                         &cache->action);
3169         if (ret) {
3170                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3171                 rte_flow_error_set(ctx->error, ENOMEM,
3172                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                    "cannot create push vlan action");
3174                 return NULL;
3175         }
3176         return &cache->entry;
3177 }
3178
3179 /**
3180  * Find existing push vlan resource or create and register a new one.
3181  *
3182  * @param [in, out] dev
3183  *   Pointer to rte_eth_dev structure.
3184  * @param[in, out] resource
3185  *   Pointer to port ID action resource.
3186  * @parm[in, out] dev_flow
3187  *   Pointer to the dev_flow.
3188  * @param[out] error
3189  *   pointer to error structure.
3190  *
3191  * @return
3192  *   0 on success otherwise -errno and errno is set.
3193  */
3194 static int
3195 flow_dv_push_vlan_action_resource_register
3196                        (struct rte_eth_dev *dev,
3197                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3198                         struct mlx5_flow *dev_flow,
3199                         struct rte_flow_error *error)
3200 {
3201         struct mlx5_priv *priv = dev->data->dev_private;
3202         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3203         struct mlx5_cache_entry *entry;
3204         struct mlx5_flow_cb_ctx ctx = {
3205                 .error = error,
3206                 .data = resource,
3207         };
3208
3209         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3210         if (!entry)
3211                 return -rte_errno;
3212         cache = container_of(entry, typeof(*cache), entry);
3213
3214         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3215         dev_flow->dv.push_vlan_res = cache;
3216         return 0;
3217 }
3218
3219 /**
3220  * Get the size of specific rte_flow_item_type hdr size
3221  *
3222  * @param[in] item_type
3223  *   Tested rte_flow_item_type.
3224  *
3225  * @return
3226  *   sizeof struct item_type, 0 if void or irrelevant.
3227  */
3228 static size_t
3229 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3230 {
3231         size_t retval;
3232
3233         switch (item_type) {
3234         case RTE_FLOW_ITEM_TYPE_ETH:
3235                 retval = sizeof(struct rte_ether_hdr);
3236                 break;
3237         case RTE_FLOW_ITEM_TYPE_VLAN:
3238                 retval = sizeof(struct rte_vlan_hdr);
3239                 break;
3240         case RTE_FLOW_ITEM_TYPE_IPV4:
3241                 retval = sizeof(struct rte_ipv4_hdr);
3242                 break;
3243         case RTE_FLOW_ITEM_TYPE_IPV6:
3244                 retval = sizeof(struct rte_ipv6_hdr);
3245                 break;
3246         case RTE_FLOW_ITEM_TYPE_UDP:
3247                 retval = sizeof(struct rte_udp_hdr);
3248                 break;
3249         case RTE_FLOW_ITEM_TYPE_TCP:
3250                 retval = sizeof(struct rte_tcp_hdr);
3251                 break;
3252         case RTE_FLOW_ITEM_TYPE_VXLAN:
3253         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3254                 retval = sizeof(struct rte_vxlan_hdr);
3255                 break;
3256         case RTE_FLOW_ITEM_TYPE_GRE:
3257         case RTE_FLOW_ITEM_TYPE_NVGRE:
3258                 retval = sizeof(struct rte_gre_hdr);
3259                 break;
3260         case RTE_FLOW_ITEM_TYPE_MPLS:
3261                 retval = sizeof(struct rte_mpls_hdr);
3262                 break;
3263         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3264         default:
3265                 retval = 0;
3266                 break;
3267         }
3268         return retval;
3269 }
3270
3271 #define MLX5_ENCAP_IPV4_VERSION         0x40
3272 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3273 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3274 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3275 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3276 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3277 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3278
3279 /**
3280  * Convert the encap action data from list of rte_flow_item to raw buffer
3281  *
3282  * @param[in] items
3283  *   Pointer to rte_flow_item objects list.
3284  * @param[out] buf
3285  *   Pointer to the output buffer.
3286  * @param[out] size
3287  *   Pointer to the output buffer size.
3288  * @param[out] error
3289  *   Pointer to the error structure.
3290  *
3291  * @return
3292  *   0 on success, a negative errno value otherwise and rte_errno is set.
3293  */
3294 static int
3295 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3296                            size_t *size, struct rte_flow_error *error)
3297 {
3298         struct rte_ether_hdr *eth = NULL;
3299         struct rte_vlan_hdr *vlan = NULL;
3300         struct rte_ipv4_hdr *ipv4 = NULL;
3301         struct rte_ipv6_hdr *ipv6 = NULL;
3302         struct rte_udp_hdr *udp = NULL;
3303         struct rte_vxlan_hdr *vxlan = NULL;
3304         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3305         struct rte_gre_hdr *gre = NULL;
3306         size_t len;
3307         size_t temp_size = 0;
3308
3309         if (!items)
3310                 return rte_flow_error_set(error, EINVAL,
3311                                           RTE_FLOW_ERROR_TYPE_ACTION,
3312                                           NULL, "invalid empty data");
3313         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3314                 len = flow_dv_get_item_hdr_len(items->type);
3315                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3316                         return rte_flow_error_set(error, EINVAL,
3317                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3318                                                   (void *)items->type,
3319                                                   "items total size is too big"
3320                                                   " for encap action");
3321                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3322                 switch (items->type) {
3323                 case RTE_FLOW_ITEM_TYPE_ETH:
3324                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3325                         break;
3326                 case RTE_FLOW_ITEM_TYPE_VLAN:
3327                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3328                         if (!eth)
3329                                 return rte_flow_error_set(error, EINVAL,
3330                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3331                                                 (void *)items->type,
3332                                                 "eth header not found");
3333                         if (!eth->ether_type)
3334                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3335                         break;
3336                 case RTE_FLOW_ITEM_TYPE_IPV4:
3337                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3338                         if (!vlan && !eth)
3339                                 return rte_flow_error_set(error, EINVAL,
3340                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3341                                                 (void *)items->type,
3342                                                 "neither eth nor vlan"
3343                                                 " header found");
3344                         if (vlan && !vlan->eth_proto)
3345                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3346                         else if (eth && !eth->ether_type)
3347                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3348                         if (!ipv4->version_ihl)
3349                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3350                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3351                         if (!ipv4->time_to_live)
3352                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3353                         break;
3354                 case RTE_FLOW_ITEM_TYPE_IPV6:
3355                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3356                         if (!vlan && !eth)
3357                                 return rte_flow_error_set(error, EINVAL,
3358                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3359                                                 (void *)items->type,
3360                                                 "neither eth nor vlan"
3361                                                 " header found");
3362                         if (vlan && !vlan->eth_proto)
3363                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3364                         else if (eth && !eth->ether_type)
3365                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3366                         if (!ipv6->vtc_flow)
3367                                 ipv6->vtc_flow =
3368                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3369                         if (!ipv6->hop_limits)
3370                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3371                         break;
3372                 case RTE_FLOW_ITEM_TYPE_UDP:
3373                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3374                         if (!ipv4 && !ipv6)
3375                                 return rte_flow_error_set(error, EINVAL,
3376                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3377                                                 (void *)items->type,
3378                                                 "ip header not found");
3379                         if (ipv4 && !ipv4->next_proto_id)
3380                                 ipv4->next_proto_id = IPPROTO_UDP;
3381                         else if (ipv6 && !ipv6->proto)
3382                                 ipv6->proto = IPPROTO_UDP;
3383                         break;
3384                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3385                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3386                         if (!udp)
3387                                 return rte_flow_error_set(error, EINVAL,
3388                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3389                                                 (void *)items->type,
3390                                                 "udp header not found");
3391                         if (!udp->dst_port)
3392                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3393                         if (!vxlan->vx_flags)
3394                                 vxlan->vx_flags =
3395                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3396                         break;
3397                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3398                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3399                         if (!udp)
3400                                 return rte_flow_error_set(error, EINVAL,
3401                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3402                                                 (void *)items->type,
3403                                                 "udp header not found");
3404                         if (!vxlan_gpe->proto)
3405                                 return rte_flow_error_set(error, EINVAL,
3406                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3407                                                 (void *)items->type,
3408                                                 "next protocol not found");
3409                         if (!udp->dst_port)
3410                                 udp->dst_port =
3411                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3412                         if (!vxlan_gpe->vx_flags)
3413                                 vxlan_gpe->vx_flags =
3414                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3415                         break;
3416                 case RTE_FLOW_ITEM_TYPE_GRE:
3417                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3418                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3419                         if (!gre->proto)
3420                                 return rte_flow_error_set(error, EINVAL,
3421                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3422                                                 (void *)items->type,
3423                                                 "next protocol not found");
3424                         if (!ipv4 && !ipv6)
3425                                 return rte_flow_error_set(error, EINVAL,
3426                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3427                                                 (void *)items->type,
3428                                                 "ip header not found");
3429                         if (ipv4 && !ipv4->next_proto_id)
3430                                 ipv4->next_proto_id = IPPROTO_GRE;
3431                         else if (ipv6 && !ipv6->proto)
3432                                 ipv6->proto = IPPROTO_GRE;
3433                         break;
3434                 case RTE_FLOW_ITEM_TYPE_VOID:
3435                         break;
3436                 default:
3437                         return rte_flow_error_set(error, EINVAL,
3438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3439                                                   (void *)items->type,
3440                                                   "unsupported item type");
3441                         break;
3442                 }
3443                 temp_size += len;
3444         }
3445         *size = temp_size;
3446         return 0;
3447 }
3448
3449 static int
3450 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3451 {
3452         struct rte_ether_hdr *eth = NULL;
3453         struct rte_vlan_hdr *vlan = NULL;
3454         struct rte_ipv6_hdr *ipv6 = NULL;
3455         struct rte_udp_hdr *udp = NULL;
3456         char *next_hdr;
3457         uint16_t proto;
3458
3459         eth = (struct rte_ether_hdr *)data;
3460         next_hdr = (char *)(eth + 1);
3461         proto = RTE_BE16(eth->ether_type);
3462
3463         /* VLAN skipping */
3464         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3465                 vlan = (struct rte_vlan_hdr *)next_hdr;
3466                 proto = RTE_BE16(vlan->eth_proto);
3467                 next_hdr += sizeof(struct rte_vlan_hdr);
3468         }
3469
3470         /* HW calculates IPv4 csum. no need to proceed */
3471         if (proto == RTE_ETHER_TYPE_IPV4)
3472                 return 0;
3473
3474         /* non IPv4/IPv6 header. not supported */
3475         if (proto != RTE_ETHER_TYPE_IPV6) {
3476                 return rte_flow_error_set(error, ENOTSUP,
3477                                           RTE_FLOW_ERROR_TYPE_ACTION,
3478                                           NULL, "Cannot offload non IPv4/IPv6");
3479         }
3480
3481         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3482
3483         /* ignore non UDP */
3484         if (ipv6->proto != IPPROTO_UDP)
3485                 return 0;
3486
3487         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3488         udp->dgram_cksum = 0;
3489
3490         return 0;
3491 }
3492
3493 /**
3494  * Convert L2 encap action to DV specification.
3495  *
3496  * @param[in] dev
3497  *   Pointer to rte_eth_dev structure.
3498  * @param[in] action
3499  *   Pointer to action structure.
3500  * @param[in, out] dev_flow
3501  *   Pointer to the mlx5_flow.
3502  * @param[in] transfer
3503  *   Mark if the flow is E-Switch flow.
3504  * @param[out] error
3505  *   Pointer to the error structure.
3506  *
3507  * @return
3508  *   0 on success, a negative errno value otherwise and rte_errno is set.
3509  */
3510 static int
3511 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3512                                const struct rte_flow_action *action,
3513                                struct mlx5_flow *dev_flow,
3514                                uint8_t transfer,
3515                                struct rte_flow_error *error)
3516 {
3517         const struct rte_flow_item *encap_data;
3518         const struct rte_flow_action_raw_encap *raw_encap_data;
3519         struct mlx5_flow_dv_encap_decap_resource res = {
3520                 .reformat_type =
3521                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3522                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3523                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3524         };
3525
3526         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3527                 raw_encap_data =
3528                         (const struct rte_flow_action_raw_encap *)action->conf;
3529                 res.size = raw_encap_data->size;
3530                 memcpy(res.buf, raw_encap_data->data, res.size);
3531         } else {
3532                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3533                         encap_data =
3534                                 ((const struct rte_flow_action_vxlan_encap *)
3535                                                 action->conf)->definition;
3536                 else
3537                         encap_data =
3538                                 ((const struct rte_flow_action_nvgre_encap *)
3539                                                 action->conf)->definition;
3540                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3541                                                &res.size, error))
3542                         return -rte_errno;
3543         }
3544         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3545                 return -rte_errno;
3546         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3547                 return rte_flow_error_set(error, EINVAL,
3548                                           RTE_FLOW_ERROR_TYPE_ACTION,
3549                                           NULL, "can't create L2 encap action");
3550         return 0;
3551 }
3552
3553 /**
3554  * Convert L2 decap action to DV specification.
3555  *
3556  * @param[in] dev
3557  *   Pointer to rte_eth_dev structure.
3558  * @param[in, out] dev_flow
3559  *   Pointer to the mlx5_flow.
3560  * @param[in] transfer
3561  *   Mark if the flow is E-Switch flow.
3562  * @param[out] error
3563  *   Pointer to the error structure.
3564  *
3565  * @return
3566  *   0 on success, a negative errno value otherwise and rte_errno is set.
3567  */
3568 static int
3569 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3570                                struct mlx5_flow *dev_flow,
3571                                uint8_t transfer,
3572                                struct rte_flow_error *error)
3573 {
3574         struct mlx5_flow_dv_encap_decap_resource res = {
3575                 .size = 0,
3576                 .reformat_type =
3577                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3578                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3579                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3580         };
3581
3582         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3583                 return rte_flow_error_set(error, EINVAL,
3584                                           RTE_FLOW_ERROR_TYPE_ACTION,
3585                                           NULL, "can't create L2 decap action");
3586         return 0;
3587 }
3588
3589 /**
3590  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3591  *
3592  * @param[in] dev
3593  *   Pointer to rte_eth_dev structure.
3594  * @param[in] action
3595  *   Pointer to action structure.
3596  * @param[in, out] dev_flow
3597  *   Pointer to the mlx5_flow.
3598  * @param[in] attr
3599  *   Pointer to the flow attributes.
3600  * @param[out] error
3601  *   Pointer to the error structure.
3602  *
3603  * @return
3604  *   0 on success, a negative errno value otherwise and rte_errno is set.
3605  */
3606 static int
3607 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3608                                 const struct rte_flow_action *action,
3609                                 struct mlx5_flow *dev_flow,
3610                                 const struct rte_flow_attr *attr,
3611                                 struct rte_flow_error *error)
3612 {
3613         const struct rte_flow_action_raw_encap *encap_data;
3614         struct mlx5_flow_dv_encap_decap_resource res;
3615
3616         memset(&res, 0, sizeof(res));
3617         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3618         res.size = encap_data->size;
3619         memcpy(res.buf, encap_data->data, res.size);
3620         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3621                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3622                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3623         if (attr->transfer)
3624                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3625         else
3626                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3627                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3628         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3629                 return rte_flow_error_set(error, EINVAL,
3630                                           RTE_FLOW_ERROR_TYPE_ACTION,
3631                                           NULL, "can't create encap action");
3632         return 0;
3633 }
3634
3635 /**
3636  * Create action push VLAN.
3637  *
3638  * @param[in] dev
3639  *   Pointer to rte_eth_dev structure.
3640  * @param[in] attr
3641  *   Pointer to the flow attributes.
3642  * @param[in] vlan
3643  *   Pointer to the vlan to push to the Ethernet header.
3644  * @param[in, out] dev_flow
3645  *   Pointer to the mlx5_flow.
3646  * @param[out] error
3647  *   Pointer to the error structure.
3648  *
3649  * @return
3650  *   0 on success, a negative errno value otherwise and rte_errno is set.
3651  */
3652 static int
3653 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3654                                 const struct rte_flow_attr *attr,
3655                                 const struct rte_vlan_hdr *vlan,
3656                                 struct mlx5_flow *dev_flow,
3657                                 struct rte_flow_error *error)
3658 {
3659         struct mlx5_flow_dv_push_vlan_action_resource res;
3660
3661         memset(&res, 0, sizeof(res));
3662         res.vlan_tag =
3663                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3664                                  vlan->vlan_tci);
3665         if (attr->transfer)
3666                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3667         else
3668                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3669                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3670         return flow_dv_push_vlan_action_resource_register
3671                                             (dev, &res, dev_flow, error);
3672 }
3673
3674 /**
3675  * Validate the modify-header actions.
3676  *
3677  * @param[in] action_flags
3678  *   Holds the actions detected until now.
3679  * @param[in] action
3680  *   Pointer to the modify action.
3681  * @param[out] error
3682  *   Pointer to error structure.
3683  *
3684  * @return
3685  *   0 on success, a negative errno value otherwise and rte_errno is set.
3686  */
3687 static int
3688 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3689                                    const struct rte_flow_action *action,
3690                                    struct rte_flow_error *error)
3691 {
3692         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3693                 return rte_flow_error_set(error, EINVAL,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL, "action configuration not set");
3696         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3697                 return rte_flow_error_set(error, EINVAL,
3698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699                                           "can't have encap action before"
3700                                           " modify action");
3701         return 0;
3702 }
3703
3704 /**
3705  * Validate the modify-header MAC address actions.
3706  *
3707  * @param[in] action_flags
3708  *   Holds the actions detected until now.
3709  * @param[in] action
3710  *   Pointer to the modify action.
3711  * @param[in] item_flags
3712  *   Holds the items detected.
3713  * @param[out] error
3714  *   Pointer to error structure.
3715  *
3716  * @return
3717  *   0 on success, a negative errno value otherwise and rte_errno is set.
3718  */
3719 static int
3720 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3721                                    const struct rte_flow_action *action,
3722                                    const uint64_t item_flags,
3723                                    struct rte_flow_error *error)
3724 {
3725         int ret = 0;
3726
3727         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3728         if (!ret) {
3729                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3730                         return rte_flow_error_set(error, EINVAL,
3731                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3732                                                   NULL,
3733                                                   "no L2 item in pattern");
3734         }
3735         return ret;
3736 }
3737
3738 /**
3739  * Validate the modify-header IPv4 address actions.
3740  *
3741  * @param[in] action_flags
3742  *   Holds the actions detected until now.
3743  * @param[in] action
3744  *   Pointer to the modify action.
3745  * @param[in] item_flags
3746  *   Holds the items detected.
3747  * @param[out] error
3748  *   Pointer to error structure.
3749  *
3750  * @return
3751  *   0 on success, a negative errno value otherwise and rte_errno is set.
3752  */
3753 static int
3754 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3755                                     const struct rte_flow_action *action,
3756                                     const uint64_t item_flags,
3757                                     struct rte_flow_error *error)
3758 {
3759         int ret = 0;
3760         uint64_t layer;
3761
3762         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3763         if (!ret) {
3764                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3765                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3766                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3767                 if (!(item_flags & layer))
3768                         return rte_flow_error_set(error, EINVAL,
3769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3770                                                   NULL,
3771                                                   "no ipv4 item in pattern");
3772         }
3773         return ret;
3774 }
3775
3776 /**
3777  * Validate the modify-header IPv6 address actions.
3778  *
3779  * @param[in] action_flags
3780  *   Holds the actions detected until now.
3781  * @param[in] action
3782  *   Pointer to the modify action.
3783  * @param[in] item_flags
3784  *   Holds the items detected.
3785  * @param[out] error
3786  *   Pointer to error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3793                                     const struct rte_flow_action *action,
3794                                     const uint64_t item_flags,
3795                                     struct rte_flow_error *error)
3796 {
3797         int ret = 0;
3798         uint64_t layer;
3799
3800         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3801         if (!ret) {
3802                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3803                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3804                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3805                 if (!(item_flags & layer))
3806                         return rte_flow_error_set(error, EINVAL,
3807                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3808                                                   NULL,
3809                                                   "no ipv6 item in pattern");
3810         }
3811         return ret;
3812 }
3813
3814 /**
3815  * Validate the modify-header TP actions.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the modify action.
3821  * @param[in] item_flags
3822  *   Holds the items detected.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3831                                   const struct rte_flow_action *action,
3832                                   const uint64_t item_flags,
3833                                   struct rte_flow_error *error)
3834 {
3835         int ret = 0;
3836         uint64_t layer;
3837
3838         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3839         if (!ret) {
3840                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3841                                  MLX5_FLOW_LAYER_INNER_L4 :
3842                                  MLX5_FLOW_LAYER_OUTER_L4;
3843                 if (!(item_flags & layer))
3844                         return rte_flow_error_set(error, EINVAL,
3845                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3846                                                   NULL, "no transport layer "
3847                                                   "in pattern");
3848         }
3849         return ret;
3850 }
3851
3852 /**
3853  * Validate the modify-header actions of increment/decrement
3854  * TCP Sequence-number.
3855  *
3856  * @param[in] action_flags
3857  *   Holds the actions detected until now.
3858  * @param[in] action
3859  *   Pointer to the modify action.
3860  * @param[in] item_flags
3861  *   Holds the items detected.
3862  * @param[out] error
3863  *   Pointer to error structure.
3864  *
3865  * @return
3866  *   0 on success, a negative errno value otherwise and rte_errno is set.
3867  */
3868 static int
3869 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3870                                        const struct rte_flow_action *action,
3871                                        const uint64_t item_flags,
3872                                        struct rte_flow_error *error)
3873 {
3874         int ret = 0;
3875         uint64_t layer;
3876
3877         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3878         if (!ret) {
3879                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3880                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3881                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3882                 if (!(item_flags & layer))
3883                         return rte_flow_error_set(error, EINVAL,
3884                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3885                                                   NULL, "no TCP item in"
3886                                                   " pattern");
3887                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3888                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3889                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3890                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3891                         return rte_flow_error_set(error, EINVAL,
3892                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3893                                                   NULL,
3894                                                   "cannot decrease and increase"
3895                                                   " TCP sequence number"
3896                                                   " at the same time");
3897         }
3898         return ret;
3899 }
3900
3901 /**
3902  * Validate the modify-header actions of increment/decrement
3903  * TCP Acknowledgment number.
3904  *
3905  * @param[in] action_flags
3906  *   Holds the actions detected until now.
3907  * @param[in] action
3908  *   Pointer to the modify action.
3909  * @param[in] item_flags
3910  *   Holds the items detected.
3911  * @param[out] error
3912  *   Pointer to error structure.
3913  *
3914  * @return
3915  *   0 on success, a negative errno value otherwise and rte_errno is set.
3916  */
3917 static int
3918 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3919                                        const struct rte_flow_action *action,
3920                                        const uint64_t item_flags,
3921                                        struct rte_flow_error *error)
3922 {
3923         int ret = 0;
3924         uint64_t layer;
3925
3926         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3927         if (!ret) {
3928                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3929                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3930                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3931                 if (!(item_flags & layer))
3932                         return rte_flow_error_set(error, EINVAL,
3933                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3934                                                   NULL, "no TCP item in"
3935                                                   " pattern");
3936                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3937                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3938                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3939                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3940                         return rte_flow_error_set(error, EINVAL,
3941                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3942                                                   NULL,
3943                                                   "cannot decrease and increase"
3944                                                   " TCP acknowledgment number"
3945                                                   " at the same time");
3946         }
3947         return ret;
3948 }
3949
3950 /**
3951  * Validate the modify-header TTL actions.
3952  *
3953  * @param[in] action_flags
3954  *   Holds the actions detected until now.
3955  * @param[in] action
3956  *   Pointer to the modify action.
3957  * @param[in] item_flags
3958  *   Holds the items detected.
3959  * @param[out] error
3960  *   Pointer to error structure.
3961  *
3962  * @return
3963  *   0 on success, a negative errno value otherwise and rte_errno is set.
3964  */
3965 static int
3966 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3967                                    const struct rte_flow_action *action,
3968                                    const uint64_t item_flags,
3969                                    struct rte_flow_error *error)
3970 {
3971         int ret = 0;
3972         uint64_t layer;
3973
3974         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3975         if (!ret) {
3976                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3977                                  MLX5_FLOW_LAYER_INNER_L3 :
3978                                  MLX5_FLOW_LAYER_OUTER_L3;
3979                 if (!(item_flags & layer))
3980                         return rte_flow_error_set(error, EINVAL,
3981                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3982                                                   NULL,
3983                                                   "no IP protocol in pattern");
3984         }
3985         return ret;
3986 }
3987
3988 /**
3989  * Validate jump action.
3990  *
3991  * @param[in] action
3992  *   Pointer to the jump action.
3993  * @param[in] action_flags
3994  *   Holds the actions detected until now.
3995  * @param[in] attributes
3996  *   Pointer to flow attributes
3997  * @param[in] external
3998  *   Action belongs to flow rule created by request external to PMD.
3999  * @param[out] error
4000  *   Pointer to error structure.
4001  *
4002  * @return
4003  *   0 on success, a negative errno value otherwise and rte_errno is set.
4004  */
4005 static int
4006 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4007                              const struct mlx5_flow_tunnel *tunnel,
4008                              const struct rte_flow_action *action,
4009                              uint64_t action_flags,
4010                              const struct rte_flow_attr *attributes,
4011                              bool external, struct rte_flow_error *error)
4012 {
4013         uint32_t target_group, table;
4014         int ret = 0;
4015         struct flow_grp_info grp_info = {
4016                 .external = !!external,
4017                 .transfer = !!attributes->transfer,
4018                 .fdb_def_rule = 1,
4019                 .std_tbl_fix = 0
4020         };
4021         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4022                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4023                 return rte_flow_error_set(error, EINVAL,
4024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4025                                           "can't have 2 fate actions in"
4026                                           " same flow");
4027         if (action_flags & MLX5_FLOW_ACTION_METER)
4028                 return rte_flow_error_set(error, ENOTSUP,
4029                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4030                                           "jump with meter not support");
4031         if (!action->conf)
4032                 return rte_flow_error_set(error, EINVAL,
4033                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4034                                           NULL, "action configuration not set");
4035         target_group =
4036                 ((const struct rte_flow_action_jump *)action->conf)->group;
4037         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4038                                        &grp_info, error);
4039         if (ret)
4040                 return ret;
4041         if (attributes->group == target_group &&
4042             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4043                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4046                                           "target group must be other than"
4047                                           " the current flow group");
4048         return 0;
4049 }
4050
4051 /*
4052  * Validate the port_id action.
4053  *
4054  * @param[in] dev
4055  *   Pointer to rte_eth_dev structure.
4056  * @param[in] action_flags
4057  *   Bit-fields that holds the actions detected until now.
4058  * @param[in] action
4059  *   Port_id RTE action structure.
4060  * @param[in] attr
4061  *   Attributes of flow that includes this action.
4062  * @param[out] error
4063  *   Pointer to error structure.
4064  *
4065  * @return
4066  *   0 on success, a negative errno value otherwise and rte_errno is set.
4067  */
4068 static int
4069 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4070                                 uint64_t action_flags,
4071                                 const struct rte_flow_action *action,
4072                                 const struct rte_flow_attr *attr,
4073                                 struct rte_flow_error *error)
4074 {
4075         const struct rte_flow_action_port_id *port_id;
4076         struct mlx5_priv *act_priv;
4077         struct mlx5_priv *dev_priv;
4078         uint16_t port;
4079
4080         if (!attr->transfer)
4081                 return rte_flow_error_set(error, ENOTSUP,
4082                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4083                                           NULL,
4084                                           "port id action is valid in transfer"
4085                                           " mode only");
4086         if (!action || !action->conf)
4087                 return rte_flow_error_set(error, ENOTSUP,
4088                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4089                                           NULL,
4090                                           "port id action parameters must be"
4091                                           " specified");
4092         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4093                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4094                 return rte_flow_error_set(error, EINVAL,
4095                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4096                                           "can have only one fate actions in"
4097                                           " a flow");
4098         dev_priv = mlx5_dev_to_eswitch_info(dev);
4099         if (!dev_priv)
4100                 return rte_flow_error_set(error, rte_errno,
4101                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4102                                           NULL,
4103                                           "failed to obtain E-Switch info");
4104         port_id = action->conf;
4105         port = port_id->original ? dev->data->port_id : port_id->id;
4106         act_priv = mlx5_port_to_eswitch_info(port, false);
4107         if (!act_priv)
4108                 return rte_flow_error_set
4109                                 (error, rte_errno,
4110                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4111                                  "failed to obtain E-Switch port id for port");
4112         if (act_priv->domain_id != dev_priv->domain_id)
4113                 return rte_flow_error_set
4114                                 (error, EINVAL,
4115                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4116                                  "port does not belong to"
4117                                  " E-Switch being configured");
4118         return 0;
4119 }
4120
4121 /**
4122  * Get the maximum number of modify header actions.
4123  *
4124  * @param dev
4125  *   Pointer to rte_eth_dev structure.
4126  * @param flags
4127  *   Flags bits to check if root level.
4128  *
4129  * @return
4130  *   Max number of modify header actions device can support.
4131  */
4132 static inline unsigned int
4133 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4134                               uint64_t flags)
4135 {
4136         /*
4137          * There's no way to directly query the max capacity from FW.
4138          * The maximal value on root table should be assumed to be supported.
4139          */
4140         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4141                 return MLX5_MAX_MODIFY_NUM;
4142         else
4143                 return MLX5_ROOT_TBL_MODIFY_NUM;
4144 }
4145
4146 /**
4147  * Validate the meter action.
4148  *
4149  * @param[in] dev
4150  *   Pointer to rte_eth_dev structure.
4151  * @param[in] action_flags
4152  *   Bit-fields that holds the actions detected until now.
4153  * @param[in] action
4154  *   Pointer to the meter action.
4155  * @param[in] attr
4156  *   Attributes of flow that includes this action.
4157  * @param[out] error
4158  *   Pointer to error structure.
4159  *
4160  * @return
4161  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4162  */
4163 static int
4164 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4165                                 uint64_t action_flags,
4166                                 const struct rte_flow_action *action,
4167                                 const struct rte_flow_attr *attr,
4168                                 struct rte_flow_error *error)
4169 {
4170         struct mlx5_priv *priv = dev->data->dev_private;
4171         const struct rte_flow_action_meter *am = action->conf;
4172         struct mlx5_flow_meter *fm;
4173
4174         if (!am)
4175                 return rte_flow_error_set(error, EINVAL,
4176                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4177                                           "meter action conf is NULL");
4178
4179         if (action_flags & MLX5_FLOW_ACTION_METER)
4180                 return rte_flow_error_set(error, ENOTSUP,
4181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4182                                           "meter chaining not support");
4183         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4184                 return rte_flow_error_set(error, ENOTSUP,
4185                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4186                                           "meter with jump not support");
4187         if (!priv->mtr_en)
4188                 return rte_flow_error_set(error, ENOTSUP,
4189                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4190                                           NULL,
4191                                           "meter action not supported");
4192         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4193         if (!fm)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "Meter not found");
4197         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4198               (!fm->ingress && !attr->ingress && attr->egress) ||
4199               (!fm->egress && !attr->egress && attr->ingress))))
4200                 return rte_flow_error_set(error, EINVAL,
4201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4202                                           "Flow attributes are either invalid "
4203                                           "or have a conflict with current "
4204                                           "meter attributes");
4205         return 0;
4206 }
4207
4208 /**
4209  * Validate the age action.
4210  *
4211  * @param[in] action_flags
4212  *   Holds the actions detected until now.
4213  * @param[in] action
4214  *   Pointer to the age action.
4215  * @param[in] dev
4216  *   Pointer to the Ethernet device structure.
4217  * @param[out] error
4218  *   Pointer to error structure.
4219  *
4220  * @return
4221  *   0 on success, a negative errno value otherwise and rte_errno is set.
4222  */
4223 static int
4224 flow_dv_validate_action_age(uint64_t action_flags,
4225                             const struct rte_flow_action *action,
4226                             struct rte_eth_dev *dev,
4227                             struct rte_flow_error *error)
4228 {
4229         struct mlx5_priv *priv = dev->data->dev_private;
4230         const struct rte_flow_action_age *age = action->conf;
4231
4232         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4233             !priv->sh->aso_age_mng))
4234                 return rte_flow_error_set(error, ENOTSUP,
4235                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4236                                           NULL,
4237                                           "age action not supported");
4238         if (!(action->conf))
4239                 return rte_flow_error_set(error, EINVAL,
4240                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4241                                           "configuration cannot be null");
4242         if (!(age->timeout))
4243                 return rte_flow_error_set(error, EINVAL,
4244                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4245                                           "invalid timeout value 0");
4246         if (action_flags & MLX5_FLOW_ACTION_AGE)
4247                 return rte_flow_error_set(error, EINVAL,
4248                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4249                                           "duplicate age actions set");
4250         return 0;
4251 }
4252
4253 /**
4254  * Validate the modify-header IPv4 DSCP actions.
4255  *
4256  * @param[in] action_flags
4257  *   Holds the actions detected until now.
4258  * @param[in] action
4259  *   Pointer to the modify action.
4260  * @param[in] item_flags
4261  *   Holds the items detected.
4262  * @param[out] error
4263  *   Pointer to error structure.
4264  *
4265  * @return
4266  *   0 on success, a negative errno value otherwise and rte_errno is set.
4267  */
4268 static int
4269 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4270                                          const struct rte_flow_action *action,
4271                                          const uint64_t item_flags,
4272                                          struct rte_flow_error *error)
4273 {
4274         int ret = 0;
4275
4276         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4277         if (!ret) {
4278                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4279                         return rte_flow_error_set(error, EINVAL,
4280                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4281                                                   NULL,
4282                                                   "no ipv4 item in pattern");
4283         }
4284         return ret;
4285 }
4286
4287 /**
4288  * Validate the modify-header IPv6 DSCP actions.
4289  *
4290  * @param[in] action_flags
4291  *   Holds the actions detected until now.
4292  * @param[in] action
4293  *   Pointer to the modify action.
4294  * @param[in] item_flags
4295  *   Holds the items detected.
4296  * @param[out] error
4297  *   Pointer to error structure.
4298  *
4299  * @return
4300  *   0 on success, a negative errno value otherwise and rte_errno is set.
4301  */
4302 static int
4303 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4304                                          const struct rte_flow_action *action,
4305                                          const uint64_t item_flags,
4306                                          struct rte_flow_error *error)
4307 {
4308         int ret = 0;
4309
4310         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4311         if (!ret) {
4312                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4313                         return rte_flow_error_set(error, EINVAL,
4314                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4315                                                   NULL,
4316                                                   "no ipv6 item in pattern");
4317         }
4318         return ret;
4319 }
4320
4321 /**
4322  * Match modify-header resource.
4323  *
4324  * @param list
4325  *   Pointer to the hash list.
4326  * @param entry
4327  *   Pointer to exist resource entry object.
4328  * @param key
4329  *   Key of the new entry.
4330  * @param ctx
4331  *   Pointer to new modify-header resource.
4332  *
4333  * @return
4334  *   0 on matching, non-zero otherwise.
4335  */
4336 int
4337 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4338                         struct mlx5_hlist_entry *entry,
4339                         uint64_t key __rte_unused, void *cb_ctx)
4340 {
4341         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4342         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4343         struct mlx5_flow_dv_modify_hdr_resource *resource =
4344                         container_of(entry, typeof(*resource), entry);
4345         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4346
4347         key_len += ref->actions_num * sizeof(ref->actions[0]);
4348         return ref->actions_num != resource->actions_num ||
4349                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4350 }
4351
4352 struct mlx5_hlist_entry *
4353 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4354                          void *cb_ctx)
4355 {
4356         struct mlx5_dev_ctx_shared *sh = list->ctx;
4357         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4358         struct mlx5dv_dr_domain *ns;
4359         struct mlx5_flow_dv_modify_hdr_resource *entry;
4360         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4361         int ret;
4362         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4363         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4364
4365         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4366                             SOCKET_ID_ANY);
4367         if (!entry) {
4368                 rte_flow_error_set(ctx->error, ENOMEM,
4369                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4370                                    "cannot allocate resource memory");
4371                 return NULL;
4372         }
4373         rte_memcpy(&entry->ft_type,
4374                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4375                    key_len + data_len);
4376         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4377                 ns = sh->fdb_domain;
4378         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4379                 ns = sh->tx_domain;
4380         else
4381                 ns = sh->rx_domain;
4382         ret = mlx5_flow_os_create_flow_action_modify_header
4383                                         (sh->ctx, ns, entry,
4384                                          data_len, &entry->action);
4385         if (ret) {
4386                 mlx5_free(entry);
4387                 rte_flow_error_set(ctx->error, ENOMEM,
4388                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4389                                    NULL, "cannot create modification action");
4390                 return NULL;
4391         }
4392         return &entry->entry;
4393 }
4394
4395 /**
4396  * Validate the sample action.
4397  *
4398  * @param[in] action_flags
4399  *   Holds the actions detected until now.
4400  * @param[in] action
4401  *   Pointer to the sample action.
4402  * @param[in] dev
4403  *   Pointer to the Ethernet device structure.
4404  * @param[in] attr
4405  *   Attributes of flow that includes this action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[in] rss
4409  *   Pointer to the RSS action.
4410  * @param[out] sample_rss
4411  *   Pointer to the RSS action in sample action list.
4412  * @param[out] error
4413  *   Pointer to error structure.
4414  *
4415  * @return
4416  *   0 on success, a negative errno value otherwise and rte_errno is set.
4417  */
4418 static int
4419 flow_dv_validate_action_sample(uint64_t action_flags,
4420                                const struct rte_flow_action *action,
4421                                struct rte_eth_dev *dev,
4422                                const struct rte_flow_attr *attr,
4423                                uint64_t item_flags,
4424                                const struct rte_flow_action_rss *rss,
4425                                const struct rte_flow_action_rss **sample_rss,
4426                                struct rte_flow_error *error)
4427 {
4428         struct mlx5_priv *priv = dev->data->dev_private;
4429         struct mlx5_dev_config *dev_conf = &priv->config;
4430         const struct rte_flow_action_sample *sample = action->conf;
4431         const struct rte_flow_action *act;
4432         uint64_t sub_action_flags = 0;
4433         uint16_t queue_index = 0xFFFF;
4434         int actions_n = 0;
4435         int ret;
4436
4437         if (!sample)
4438                 return rte_flow_error_set(error, EINVAL,
4439                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4440                                           "configuration cannot be NULL");
4441         if (sample->ratio == 0)
4442                 return rte_flow_error_set(error, EINVAL,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4444                                           "ratio value starts from 1");
4445         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4446                 return rte_flow_error_set(error, ENOTSUP,
4447                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4448                                           NULL,
4449                                           "sample action not supported");
4450         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4451                 return rte_flow_error_set(error, EINVAL,
4452                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4453                                           "Multiple sample actions not "
4454                                           "supported");
4455         if (action_flags & MLX5_FLOW_ACTION_METER)
4456                 return rte_flow_error_set(error, EINVAL,
4457                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4458                                           "wrong action order, meter should "
4459                                           "be after sample action");
4460         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4461                 return rte_flow_error_set(error, EINVAL,
4462                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4463                                           "wrong action order, jump should "
4464                                           "be after sample action");
4465         act = sample->actions;
4466         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4467                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4468                         return rte_flow_error_set(error, ENOTSUP,
4469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4470                                                   act, "too many actions");
4471                 switch (act->type) {
4472                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4473                         ret = mlx5_flow_validate_action_queue(act,
4474                                                               sub_action_flags,
4475                                                               dev,
4476                                                               attr, error);
4477                         if (ret < 0)
4478                                 return ret;
4479                         queue_index = ((const struct rte_flow_action_queue *)
4480                                                         (act->conf))->index;
4481                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4482                         ++actions_n;
4483                         break;
4484                 case RTE_FLOW_ACTION_TYPE_RSS:
4485                         *sample_rss = act->conf;
4486                         ret = mlx5_flow_validate_action_rss(act,
4487                                                             sub_action_flags,
4488                                                             dev, attr,
4489                                                             item_flags,
4490                                                             error);
4491                         if (ret < 0)
4492                                 return ret;
4493                         if (rss && *sample_rss &&
4494                             ((*sample_rss)->level != rss->level ||
4495                             (*sample_rss)->types != rss->types))
4496                                 return rte_flow_error_set(error, ENOTSUP,
4497                                         RTE_FLOW_ERROR_TYPE_ACTION,
4498                                         NULL,
4499                                         "Can't use the different RSS types "
4500                                         "or level in the same flow");
4501                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
4502                                 queue_index = (*sample_rss)->queue[0];
4503                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
4504                         ++actions_n;
4505                         break;
4506                 case RTE_FLOW_ACTION_TYPE_MARK:
4507                         ret = flow_dv_validate_action_mark(dev, act,
4508                                                            sub_action_flags,
4509                                                            attr, error);
4510                         if (ret < 0)
4511                                 return ret;
4512                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4513                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4514                                                 MLX5_FLOW_ACTION_MARK_EXT;
4515                         else
4516                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4517                         ++actions_n;
4518                         break;
4519                 case RTE_FLOW_ACTION_TYPE_COUNT:
4520                         ret = flow_dv_validate_action_count(dev, error);
4521                         if (ret < 0)
4522                                 return ret;
4523                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4524                         ++actions_n;
4525                         break;
4526                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4527                         ret = flow_dv_validate_action_port_id(dev,
4528                                                               sub_action_flags,
4529                                                               act,
4530                                                               attr,
4531                                                               error);
4532                         if (ret)
4533                                 return ret;
4534                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4535                         ++actions_n;
4536                         break;
4537                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4538                         ret = flow_dv_validate_action_raw_encap_decap
4539                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4540                                  &actions_n, action, item_flags, error);
4541                         if (ret < 0)
4542                                 return ret;
4543                         ++actions_n;
4544                         break;
4545                 default:
4546                         return rte_flow_error_set(error, ENOTSUP,
4547                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4548                                                   NULL,
4549                                                   "Doesn't support optional "
4550                                                   "action");
4551                 }
4552         }
4553         if (attr->ingress && !attr->transfer) {
4554                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
4555                                           MLX5_FLOW_ACTION_RSS)))
4556                         return rte_flow_error_set(error, EINVAL,
4557                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4558                                                   NULL,
4559                                                   "Ingress must has a dest "
4560                                                   "QUEUE for Sample");
4561         } else if (attr->egress && !attr->transfer) {
4562                 return rte_flow_error_set(error, ENOTSUP,
4563                                           RTE_FLOW_ERROR_TYPE_ACTION,
4564                                           NULL,
4565                                           "Sample Only support Ingress "
4566                                           "or E-Switch");
4567         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4568                 MLX5_ASSERT(attr->transfer);
4569                 if (sample->ratio > 1)
4570                         return rte_flow_error_set(error, ENOTSUP,
4571                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4572                                                   NULL,
4573                                                   "E-Switch doesn't support "
4574                                                   "any optional action "
4575                                                   "for sampling");
4576                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4577                         return rte_flow_error_set(error, ENOTSUP,
4578                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4579                                                   NULL,
4580                                                   "unsupported action QUEUE");
4581                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
4582                         return rte_flow_error_set(error, ENOTSUP,
4583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4584                                                   NULL,
4585                                                   "unsupported action QUEUE");
4586                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4587                         return rte_flow_error_set(error, EINVAL,
4588                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4589                                                   NULL,
4590                                                   "E-Switch must has a dest "
4591                                                   "port for mirroring");
4592         }
4593         /* Continue validation for Xcap actions.*/
4594         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4595             (queue_index == 0xFFFF ||
4596              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4597                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4598                      MLX5_FLOW_XCAP_ACTIONS)
4599                         return rte_flow_error_set(error, ENOTSUP,
4600                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4601                                                   NULL, "encap and decap "
4602                                                   "combination aren't "
4603                                                   "supported");
4604                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4605                                                         MLX5_FLOW_ACTION_ENCAP))
4606                         return rte_flow_error_set(error, ENOTSUP,
4607                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4608                                                   NULL, "encap is not supported"
4609                                                   " for ingress traffic");
4610         }
4611         return 0;
4612 }
4613
4614 /**
4615  * Find existing modify-header resource or create and register a new one.
4616  *
4617  * @param dev[in, out]
4618  *   Pointer to rte_eth_dev structure.
4619  * @param[in, out] resource
4620  *   Pointer to modify-header resource.
4621  * @parm[in, out] dev_flow
4622  *   Pointer to the dev_flow.
4623  * @param[out] error
4624  *   pointer to error structure.
4625  *
4626  * @return
4627  *   0 on success otherwise -errno and errno is set.
4628  */
4629 static int
4630 flow_dv_modify_hdr_resource_register
4631                         (struct rte_eth_dev *dev,
4632                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4633                          struct mlx5_flow *dev_flow,
4634                          struct rte_flow_error *error)
4635 {
4636         struct mlx5_priv *priv = dev->data->dev_private;
4637         struct mlx5_dev_ctx_shared *sh = priv->sh;
4638         uint32_t key_len = sizeof(*resource) -
4639                            offsetof(typeof(*resource), ft_type) +
4640                            resource->actions_num * sizeof(resource->actions[0]);
4641         struct mlx5_hlist_entry *entry;
4642         struct mlx5_flow_cb_ctx ctx = {
4643                 .error = error,
4644                 .data = resource,
4645         };
4646         uint64_t key64;
4647
4648         resource->flags = dev_flow->dv.group ? 0 :
4649                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4650         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4651                                     resource->flags))
4652                 return rte_flow_error_set(error, EOVERFLOW,
4653                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4654                                           "too many modify header items");
4655         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4656         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4657         if (!entry)
4658                 return -rte_errno;
4659         resource = container_of(entry, typeof(*resource), entry);
4660         dev_flow->handle->dvh.modify_hdr = resource;
4661         return 0;
4662 }
4663
4664 /**
4665  * Get DV flow counter by index.
4666  *
4667  * @param[in] dev
4668  *   Pointer to the Ethernet device structure.
4669  * @param[in] idx
4670  *   mlx5 flow counter index in the container.
4671  * @param[out] ppool
4672  *   mlx5 flow counter pool in the container,
4673  *
4674  * @return
4675  *   Pointer to the counter, NULL otherwise.
4676  */
4677 static struct mlx5_flow_counter *
4678 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4679                            uint32_t idx,
4680                            struct mlx5_flow_counter_pool **ppool)
4681 {
4682         struct mlx5_priv *priv = dev->data->dev_private;
4683         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4684         struct mlx5_flow_counter_pool *pool;
4685
4686         /* Decrease to original index and clear shared bit. */
4687         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4688         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4689         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4690         MLX5_ASSERT(pool);
4691         if (ppool)
4692                 *ppool = pool;
4693         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4694 }
4695
4696 /**
4697  * Check the devx counter belongs to the pool.
4698  *
4699  * @param[in] pool
4700  *   Pointer to the counter pool.
4701  * @param[in] id
4702  *   The counter devx ID.
4703  *
4704  * @return
4705  *   True if counter belongs to the pool, false otherwise.
4706  */
4707 static bool
4708 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4709 {
4710         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4711                    MLX5_COUNTERS_PER_POOL;
4712
4713         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4714                 return true;
4715         return false;
4716 }
4717
4718 /**
4719  * Get a pool by devx counter ID.
4720  *
4721  * @param[in] cmng
4722  *   Pointer to the counter management.
4723  * @param[in] id
4724  *   The counter devx ID.
4725  *
4726  * @return
4727  *   The counter pool pointer if exists, NULL otherwise,
4728  */
4729 static struct mlx5_flow_counter_pool *
4730 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4731 {
4732         uint32_t i;
4733         struct mlx5_flow_counter_pool *pool = NULL;
4734
4735         rte_spinlock_lock(&cmng->pool_update_sl);
4736         /* Check last used pool. */
4737         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4738             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4739                 pool = cmng->pools[cmng->last_pool_idx];
4740                 goto out;
4741         }
4742         /* ID out of range means no suitable pool in the container. */
4743         if (id > cmng->max_id || id < cmng->min_id)
4744                 goto out;
4745         /*
4746          * Find the pool from the end of the container, since mostly counter
4747          * ID is sequence increasing, and the last pool should be the needed
4748          * one.
4749          */
4750         i = cmng->n_valid;
4751         while (i--) {
4752                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4753
4754                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4755                         pool = pool_tmp;
4756                         break;
4757                 }
4758         }
4759 out:
4760         rte_spinlock_unlock(&cmng->pool_update_sl);
4761         return pool;
4762 }
4763
4764 /**
4765  * Resize a counter container.
4766  *
4767  * @param[in] dev
4768  *   Pointer to the Ethernet device structure.
4769  *
4770  * @return
4771  *   0 on success, otherwise negative errno value and rte_errno is set.
4772  */
4773 static int
4774 flow_dv_container_resize(struct rte_eth_dev *dev)
4775 {
4776         struct mlx5_priv *priv = dev->data->dev_private;
4777         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4778         void *old_pools = cmng->pools;
4779         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4780         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4781         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4782
4783         if (!pools) {
4784                 rte_errno = ENOMEM;
4785                 return -ENOMEM;
4786         }
4787         if (old_pools)
4788                 memcpy(pools, old_pools, cmng->n *
4789                                        sizeof(struct mlx5_flow_counter_pool *));
4790         cmng->n = resize;
4791         cmng->pools = pools;
4792         if (old_pools)
4793                 mlx5_free(old_pools);
4794         return 0;
4795 }
4796
4797 /**
4798  * Query a devx flow counter.
4799  *
4800  * @param[in] dev
4801  *   Pointer to the Ethernet device structure.
4802  * @param[in] cnt
4803  *   Index to the flow counter.
4804  * @param[out] pkts
4805  *   The statistics value of packets.
4806  * @param[out] bytes
4807  *   The statistics value of bytes.
4808  *
4809  * @return
4810  *   0 on success, otherwise a negative errno value and rte_errno is set.
4811  */
4812 static inline int
4813 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4814                      uint64_t *bytes)
4815 {
4816         struct mlx5_priv *priv = dev->data->dev_private;
4817         struct mlx5_flow_counter_pool *pool = NULL;
4818         struct mlx5_flow_counter *cnt;
4819         int offset;
4820
4821         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4822         MLX5_ASSERT(pool);
4823         if (priv->sh->cmng.counter_fallback)
4824                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4825                                         0, pkts, bytes, 0, NULL, NULL, 0);
4826         rte_spinlock_lock(&pool->sl);
4827         if (!pool->raw) {
4828                 *pkts = 0;
4829                 *bytes = 0;
4830         } else {
4831                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4832                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4833                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4834         }
4835         rte_spinlock_unlock(&pool->sl);
4836         return 0;
4837 }
4838
4839 /**
4840  * Create and initialize a new counter pool.
4841  *
4842  * @param[in] dev
4843  *   Pointer to the Ethernet device structure.
4844  * @param[out] dcs
4845  *   The devX counter handle.
4846  * @param[in] age
4847  *   Whether the pool is for counter that was allocated for aging.
4848  * @param[in/out] cont_cur
4849  *   Pointer to the container pointer, it will be update in pool resize.
4850  *
4851  * @return
4852  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4853  */
4854 static struct mlx5_flow_counter_pool *
4855 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4856                     uint32_t age)
4857 {
4858         struct mlx5_priv *priv = dev->data->dev_private;
4859         struct mlx5_flow_counter_pool *pool;
4860         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4861         bool fallback = priv->sh->cmng.counter_fallback;
4862         uint32_t size = sizeof(*pool);
4863
4864         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4865         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4866         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4867         if (!pool) {
4868                 rte_errno = ENOMEM;
4869                 return NULL;
4870         }
4871         pool->raw = NULL;
4872         pool->is_aged = !!age;
4873         pool->query_gen = 0;
4874         pool->min_dcs = dcs;
4875         rte_spinlock_init(&pool->sl);
4876         rte_spinlock_init(&pool->csl);
4877         TAILQ_INIT(&pool->counters[0]);
4878         TAILQ_INIT(&pool->counters[1]);
4879         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4880         rte_spinlock_lock(&cmng->pool_update_sl);
4881         pool->index = cmng->n_valid;
4882         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4883                 mlx5_free(pool);
4884                 rte_spinlock_unlock(&cmng->pool_update_sl);
4885                 return NULL;
4886         }
4887         cmng->pools[pool->index] = pool;
4888         cmng->n_valid++;
4889         if (unlikely(fallback)) {
4890                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4891
4892                 if (base < cmng->min_id)
4893                         cmng->min_id = base;
4894                 if (base > cmng->max_id)
4895                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4896                 cmng->last_pool_idx = pool->index;
4897         }
4898         rte_spinlock_unlock(&cmng->pool_update_sl);
4899         return pool;
4900 }
4901
4902 /**
4903  * Prepare a new counter and/or a new counter pool.
4904  *
4905  * @param[in] dev
4906  *   Pointer to the Ethernet device structure.
4907  * @param[out] cnt_free
4908  *   Where to put the pointer of a new counter.
4909  * @param[in] age
4910  *   Whether the pool is for counter that was allocated for aging.
4911  *
4912  * @return
4913  *   The counter pool pointer and @p cnt_free is set on success,
4914  *   NULL otherwise and rte_errno is set.
4915  */
4916 static struct mlx5_flow_counter_pool *
4917 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4918                              struct mlx5_flow_counter **cnt_free,
4919                              uint32_t age)
4920 {
4921         struct mlx5_priv *priv = dev->data->dev_private;
4922         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4923         struct mlx5_flow_counter_pool *pool;
4924         struct mlx5_counters tmp_tq;
4925         struct mlx5_devx_obj *dcs = NULL;
4926         struct mlx5_flow_counter *cnt;
4927         enum mlx5_counter_type cnt_type =
4928                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4929         bool fallback = priv->sh->cmng.counter_fallback;
4930         uint32_t i;
4931
4932         if (fallback) {
4933                 /* bulk_bitmap must be 0 for single counter allocation. */
4934                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4935                 if (!dcs)
4936                         return NULL;
4937                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4938                 if (!pool) {
4939                         pool = flow_dv_pool_create(dev, dcs, age);
4940                         if (!pool) {
4941                                 mlx5_devx_cmd_destroy(dcs);
4942                                 return NULL;
4943                         }
4944                 }
4945                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4946                 cnt = MLX5_POOL_GET_CNT(pool, i);
4947                 cnt->pool = pool;
4948                 cnt->dcs_when_free = dcs;
4949                 *cnt_free = cnt;
4950                 return pool;
4951         }
4952         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4953         if (!dcs) {
4954                 rte_errno = ENODATA;
4955                 return NULL;
4956         }
4957         pool = flow_dv_pool_create(dev, dcs, age);
4958         if (!pool) {
4959                 mlx5_devx_cmd_destroy(dcs);
4960                 return NULL;
4961         }
4962         TAILQ_INIT(&tmp_tq);
4963         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4964                 cnt = MLX5_POOL_GET_CNT(pool, i);
4965                 cnt->pool = pool;
4966                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4967         }
4968         rte_spinlock_lock(&cmng->csl[cnt_type]);
4969         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4970         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4971         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4972         (*cnt_free)->pool = pool;
4973         return pool;
4974 }
4975
4976 /**
4977  * Allocate a flow counter.
4978  *
4979  * @param[in] dev
4980  *   Pointer to the Ethernet device structure.
4981  * @param[in] age
4982  *   Whether the counter was allocated for aging.
4983  *
4984  * @return
4985  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4986  */
4987 static uint32_t
4988 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4989 {
4990         struct mlx5_priv *priv = dev->data->dev_private;
4991         struct mlx5_flow_counter_pool *pool = NULL;
4992         struct mlx5_flow_counter *cnt_free = NULL;
4993         bool fallback = priv->sh->cmng.counter_fallback;
4994         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4995         enum mlx5_counter_type cnt_type =
4996                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4997         uint32_t cnt_idx;
4998
4999         if (!priv->config.devx) {
5000                 rte_errno = ENOTSUP;
5001                 return 0;
5002         }
5003         /* Get free counters from container. */
5004         rte_spinlock_lock(&cmng->csl[cnt_type]);
5005         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5006         if (cnt_free)
5007                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5008         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5009         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5010                 goto err;
5011         pool = cnt_free->pool;
5012         if (fallback)
5013                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5014         /* Create a DV counter action only in the first time usage. */
5015         if (!cnt_free->action) {
5016                 uint16_t offset;
5017                 struct mlx5_devx_obj *dcs;
5018                 int ret;
5019
5020                 if (!fallback) {
5021                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5022                         dcs = pool->min_dcs;
5023                 } else {
5024                         offset = 0;
5025                         dcs = cnt_free->dcs_when_free;
5026                 }
5027                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5028                                                             &cnt_free->action);
5029                 if (ret) {
5030                         rte_errno = errno;
5031                         goto err;
5032                 }
5033         }
5034         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5035                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5036         /* Update the counter reset values. */
5037         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5038                                  &cnt_free->bytes))
5039                 goto err;
5040         if (!fallback && !priv->sh->cmng.query_thread_on)
5041                 /* Start the asynchronous batch query by the host thread. */
5042                 mlx5_set_query_alarm(priv->sh);
5043         return cnt_idx;
5044 err:
5045         if (cnt_free) {
5046                 cnt_free->pool = pool;
5047                 if (fallback)
5048                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5049                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5050                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5051                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5052         }
5053         return 0;
5054 }
5055
5056 /**
5057  * Allocate a shared flow counter.
5058  *
5059  * @param[in] ctx
5060  *   Pointer to the shared counter configuration.
5061  * @param[in] data
5062  *   Pointer to save the allocated counter index.
5063  *
5064  * @return
5065  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5066  */
5067
5068 static int32_t
5069 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5070 {
5071         struct mlx5_shared_counter_conf *conf = ctx;
5072         struct rte_eth_dev *dev = conf->dev;
5073         struct mlx5_flow_counter *cnt;
5074
5075         data->dword = flow_dv_counter_alloc(dev, 0);
5076         data->dword |= MLX5_CNT_SHARED_OFFSET;
5077         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5078         cnt->shared_info.id = conf->id;
5079         return 0;
5080 }
5081
5082 /**
5083  * Get a shared flow counter.
5084  *
5085  * @param[in] dev
5086  *   Pointer to the Ethernet device structure.
5087  * @param[in] id
5088  *   Counter identifier.
5089  *
5090  * @return
5091  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5092  */
5093 static uint32_t
5094 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5095 {
5096         struct mlx5_priv *priv = dev->data->dev_private;
5097         struct mlx5_shared_counter_conf conf = {
5098                 .dev = dev,
5099                 .id = id,
5100         };
5101         union mlx5_l3t_data data = {
5102                 .dword = 0,
5103         };
5104
5105         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5106                                flow_dv_counter_alloc_shared_cb, &conf);
5107         return data.dword;
5108 }
5109
5110 /**
5111  * Get age param from counter index.
5112  *
5113  * @param[in] dev
5114  *   Pointer to the Ethernet device structure.
5115  * @param[in] counter
5116  *   Index to the counter handler.
5117  *
5118  * @return
5119  *   The aging parameter specified for the counter index.
5120  */
5121 static struct mlx5_age_param*
5122 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5123                                 uint32_t counter)
5124 {
5125         struct mlx5_flow_counter *cnt;
5126         struct mlx5_flow_counter_pool *pool = NULL;
5127
5128         flow_dv_counter_get_by_idx(dev, counter, &pool);
5129         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5130         cnt = MLX5_POOL_GET_CNT(pool, counter);
5131         return MLX5_CNT_TO_AGE(cnt);
5132 }
5133
5134 /**
5135  * Remove a flow counter from aged counter list.
5136  *
5137  * @param[in] dev
5138  *   Pointer to the Ethernet device structure.
5139  * @param[in] counter
5140  *   Index to the counter handler.
5141  * @param[in] cnt
5142  *   Pointer to the counter handler.
5143  */
5144 static void
5145 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5146                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5147 {
5148         struct mlx5_age_info *age_info;
5149         struct mlx5_age_param *age_param;
5150         struct mlx5_priv *priv = dev->data->dev_private;
5151         uint16_t expected = AGE_CANDIDATE;
5152
5153         age_info = GET_PORT_AGE_INFO(priv);
5154         age_param = flow_dv_counter_idx_get_age(dev, counter);
5155         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5156                                          AGE_FREE, false, __ATOMIC_RELAXED,
5157                                          __ATOMIC_RELAXED)) {
5158                 /**
5159                  * We need the lock even it is age timeout,
5160                  * since counter may still in process.
5161                  */
5162                 rte_spinlock_lock(&age_info->aged_sl);
5163                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5164                 rte_spinlock_unlock(&age_info->aged_sl);
5165                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5166         }
5167 }
5168
5169 /**
5170  * Release a flow counter.
5171  *
5172  * @param[in] dev
5173  *   Pointer to the Ethernet device structure.
5174  * @param[in] counter
5175  *   Index to the counter handler.
5176  */
5177 static void
5178 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5179 {
5180         struct mlx5_priv *priv = dev->data->dev_private;
5181         struct mlx5_flow_counter_pool *pool = NULL;
5182         struct mlx5_flow_counter *cnt;
5183         enum mlx5_counter_type cnt_type;
5184
5185         if (!counter)
5186                 return;
5187         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5188         MLX5_ASSERT(pool);
5189         if (IS_SHARED_CNT(counter) &&
5190             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5191                 return;
5192         if (pool->is_aged)
5193                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5194         cnt->pool = pool;
5195         /*
5196          * Put the counter back to list to be updated in none fallback mode.
5197          * Currently, we are using two list alternately, while one is in query,
5198          * add the freed counter to the other list based on the pool query_gen
5199          * value. After query finishes, add counter the list to the global
5200          * container counter list. The list changes while query starts. In
5201          * this case, lock will not be needed as query callback and release
5202          * function both operate with the different list.
5203          *
5204          */
5205         if (!priv->sh->cmng.counter_fallback) {
5206                 rte_spinlock_lock(&pool->csl);
5207                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5208                 rte_spinlock_unlock(&pool->csl);
5209         } else {
5210                 cnt->dcs_when_free = cnt->dcs_when_active;
5211                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5212                                            MLX5_COUNTER_TYPE_ORIGIN;
5213                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5214                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5215                                   cnt, next);
5216                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5217         }
5218 }
5219
5220 /**
5221  * Verify the @p attributes will be correctly understood by the NIC and store
5222  * them in the @p flow if everything is correct.
5223  *
5224  * @param[in] dev
5225  *   Pointer to dev struct.
5226  * @param[in] attributes
5227  *   Pointer to flow attributes
5228  * @param[in] external
5229  *   This flow rule is created by request external to PMD.
5230  * @param[out] error
5231  *   Pointer to error structure.
5232  *
5233  * @return
5234  *   - 0 on success and non root table.
5235  *   - 1 on success and root table.
5236  *   - a negative errno value otherwise and rte_errno is set.
5237  */
5238 static int
5239 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5240                             const struct mlx5_flow_tunnel *tunnel,
5241                             const struct rte_flow_attr *attributes,
5242                             const struct flow_grp_info *grp_info,
5243                             struct rte_flow_error *error)
5244 {
5245         struct mlx5_priv *priv = dev->data->dev_private;
5246         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5247         int ret = 0;
5248
5249 #ifndef HAVE_MLX5DV_DR
5250         RTE_SET_USED(tunnel);
5251         RTE_SET_USED(grp_info);
5252         if (attributes->group)
5253                 return rte_flow_error_set(error, ENOTSUP,
5254                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5255                                           NULL,
5256                                           "groups are not supported");
5257 #else
5258         uint32_t table = 0;
5259
5260         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5261                                        grp_info, error);
5262         if (ret)
5263                 return ret;
5264         if (!table)
5265                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5266 #endif
5267         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5268             attributes->priority > lowest_priority)
5269                 return rte_flow_error_set(error, ENOTSUP,
5270                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5271                                           NULL,
5272                                           "priority out of range");
5273         if (attributes->transfer) {
5274                 if (!priv->config.dv_esw_en)
5275                         return rte_flow_error_set
5276                                 (error, ENOTSUP,
5277                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5278                                  "E-Switch dr is not supported");
5279                 if (!(priv->representor || priv->master))
5280                         return rte_flow_error_set
5281                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5282                                  NULL, "E-Switch configuration can only be"
5283                                  " done by a master or a representor device");
5284                 if (attributes->egress)
5285                         return rte_flow_error_set
5286                                 (error, ENOTSUP,
5287                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5288                                  "egress is not supported");
5289         }
5290         if (!(attributes->egress ^ attributes->ingress))
5291                 return rte_flow_error_set(error, ENOTSUP,
5292                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5293                                           "must specify exactly one of "
5294                                           "ingress or egress");
5295         return ret;
5296 }
5297
5298 /**
5299  * Internal validation function. For validating both actions and items.
5300  *
5301  * @param[in] dev
5302  *   Pointer to the rte_eth_dev structure.
5303  * @param[in] attr
5304  *   Pointer to the flow attributes.
5305  * @param[in] items
5306  *   Pointer to the list of items.
5307  * @param[in] actions
5308  *   Pointer to the list of actions.
5309  * @param[in] external
5310  *   This flow rule is created by request external to PMD.
5311  * @param[in] hairpin
5312  *   Number of hairpin TX actions, 0 means classic flow.
5313  * @param[out] error
5314  *   Pointer to the error structure.
5315  *
5316  * @return
5317  *   0 on success, a negative errno value otherwise and rte_errno is set.
5318  */
5319 static int
5320 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5321                  const struct rte_flow_item items[],
5322                  const struct rte_flow_action actions[],
5323                  bool external, int hairpin, struct rte_flow_error *error)
5324 {
5325         int ret;
5326         uint64_t action_flags = 0;
5327         uint64_t item_flags = 0;
5328         uint64_t last_item = 0;
5329         uint8_t next_protocol = 0xff;
5330         uint16_t ether_type = 0;
5331         int actions_n = 0;
5332         uint8_t item_ipv6_proto = 0;
5333         const struct rte_flow_item *geneve_item = NULL;
5334         const struct rte_flow_item *gre_item = NULL;
5335         const struct rte_flow_item *gtp_item = NULL;
5336         const struct rte_flow_action_raw_decap *decap;
5337         const struct rte_flow_action_raw_encap *encap;
5338         const struct rte_flow_action_rss *rss = NULL;
5339         const struct rte_flow_action_rss *sample_rss = NULL;
5340         const struct rte_flow_item_tcp nic_tcp_mask = {
5341                 .hdr = {
5342                         .tcp_flags = 0xFF,
5343                         .src_port = RTE_BE16(UINT16_MAX),
5344                         .dst_port = RTE_BE16(UINT16_MAX),
5345                 }
5346         };
5347         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5348                 .hdr = {
5349                         .src_addr =
5350                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5351                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5352                         .dst_addr =
5353                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5354                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5355                         .vtc_flow = RTE_BE32(0xffffffff),
5356                         .proto = 0xff,
5357                         .hop_limits = 0xff,
5358                 },
5359                 .has_frag_ext = 1,
5360         };
5361         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5362                 .hdr = {
5363                         .common = {
5364                                 .u32 =
5365                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5366                                         .type = 0xFF,
5367                                         }).u32),
5368                         },
5369                         .dummy[0] = 0xffffffff,
5370                 },
5371         };
5372         struct mlx5_priv *priv = dev->data->dev_private;
5373         struct mlx5_dev_config *dev_conf = &priv->config;
5374         uint16_t queue_index = 0xFFFF;
5375         const struct rte_flow_item_vlan *vlan_m = NULL;
5376         int16_t rw_act_num = 0;
5377         uint64_t is_root;
5378         const struct mlx5_flow_tunnel *tunnel;
5379         struct flow_grp_info grp_info = {
5380                 .external = !!external,
5381                 .transfer = !!attr->transfer,
5382                 .fdb_def_rule = !!priv->fdb_def_rule,
5383         };
5384         const struct rte_eth_hairpin_conf *conf;
5385
5386         if (items == NULL)
5387                 return -1;
5388         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5389                 tunnel = flow_items_to_tunnel(items);
5390                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5391                                 MLX5_FLOW_ACTION_DECAP;
5392         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5393                 tunnel = flow_actions_to_tunnel(actions);
5394                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5395         } else {
5396                 tunnel = NULL;
5397         }
5398         if (tunnel && priv->representor)
5399                 return rte_flow_error_set(error, ENOTSUP,
5400                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5401                                           "decap not supported "
5402                                           "for VF representor");
5403         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5404                                 (dev, tunnel, attr, items, actions);
5405         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5406         if (ret < 0)
5407                 return ret;
5408         is_root = (uint64_t)ret;
5409         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5410                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5411                 int type = items->type;
5412
5413                 if (!mlx5_flow_os_item_supported(type))
5414                         return rte_flow_error_set(error, ENOTSUP,
5415                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5416                                                   NULL, "item not supported");
5417                 switch (type) {
5418                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5419                         if (items[0].type != (typeof(items[0].type))
5420                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5421                                 return rte_flow_error_set
5422                                                 (error, EINVAL,
5423                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5424                                                 NULL, "MLX5 private items "
5425                                                 "must be the first");
5426                         break;
5427                 case RTE_FLOW_ITEM_TYPE_VOID:
5428                         break;
5429                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5430                         ret = flow_dv_validate_item_port_id
5431                                         (dev, items, attr, item_flags, error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5435                         break;
5436                 case RTE_FLOW_ITEM_TYPE_ETH:
5437                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5438                                                           true, error);
5439                         if (ret < 0)
5440                                 return ret;
5441                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5442                                              MLX5_FLOW_LAYER_OUTER_L2;
5443                         if (items->mask != NULL && items->spec != NULL) {
5444                                 ether_type =
5445                                         ((const struct rte_flow_item_eth *)
5446                                          items->spec)->type;
5447                                 ether_type &=
5448                                         ((const struct rte_flow_item_eth *)
5449                                          items->mask)->type;
5450                                 ether_type = rte_be_to_cpu_16(ether_type);
5451                         } else {
5452                                 ether_type = 0;
5453                         }
5454                         break;
5455                 case RTE_FLOW_ITEM_TYPE_VLAN:
5456                         ret = flow_dv_validate_item_vlan(items, item_flags,
5457                                                          dev, error);
5458                         if (ret < 0)
5459                                 return ret;
5460                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5461                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5462                         if (items->mask != NULL && items->spec != NULL) {
5463                                 ether_type =
5464                                         ((const struct rte_flow_item_vlan *)
5465                                          items->spec)->inner_type;
5466                                 ether_type &=
5467                                         ((const struct rte_flow_item_vlan *)
5468                                          items->mask)->inner_type;
5469                                 ether_type = rte_be_to_cpu_16(ether_type);
5470                         } else {
5471                                 ether_type = 0;
5472                         }
5473                         /* Store outer VLAN mask for of_push_vlan action. */
5474                         if (!tunnel)
5475                                 vlan_m = items->mask;
5476                         break;
5477                 case RTE_FLOW_ITEM_TYPE_IPV4:
5478                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5479                                                   &item_flags, &tunnel);
5480                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5481                                                          last_item, ether_type,
5482                                                          error);
5483                         if (ret < 0)
5484                                 return ret;
5485                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5486                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5487                         if (items->mask != NULL &&
5488                             ((const struct rte_flow_item_ipv4 *)
5489                              items->mask)->hdr.next_proto_id) {
5490                                 next_protocol =
5491                                         ((const struct rte_flow_item_ipv4 *)
5492                                          (items->spec))->hdr.next_proto_id;
5493                                 next_protocol &=
5494                                         ((const struct rte_flow_item_ipv4 *)
5495                                          (items->mask))->hdr.next_proto_id;
5496                         } else {
5497                                 /* Reset for inner layer. */
5498                                 next_protocol = 0xff;
5499                         }
5500                         break;
5501                 case RTE_FLOW_ITEM_TYPE_IPV6:
5502                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5503                                                   &item_flags, &tunnel);
5504                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5505                                                            last_item,
5506                                                            ether_type,
5507                                                            &nic_ipv6_mask,
5508                                                            error);
5509                         if (ret < 0)
5510                                 return ret;
5511                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5512                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5513                         if (items->mask != NULL &&
5514                             ((const struct rte_flow_item_ipv6 *)
5515                              items->mask)->hdr.proto) {
5516                                 item_ipv6_proto =
5517                                         ((const struct rte_flow_item_ipv6 *)
5518                                          items->spec)->hdr.proto;
5519                                 next_protocol =
5520                                         ((const struct rte_flow_item_ipv6 *)
5521                                          items->spec)->hdr.proto;
5522                                 next_protocol &=
5523                                         ((const struct rte_flow_item_ipv6 *)
5524                                          items->mask)->hdr.proto;
5525                         } else {
5526                                 /* Reset for inner layer. */
5527                                 next_protocol = 0xff;
5528                         }
5529                         break;
5530                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5531                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5532                                                                   item_flags,
5533                                                                   error);
5534                         if (ret < 0)
5535                                 return ret;
5536                         last_item = tunnel ?
5537                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5538                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5539                         if (items->mask != NULL &&
5540                             ((const struct rte_flow_item_ipv6_frag_ext *)
5541                              items->mask)->hdr.next_header) {
5542                                 next_protocol =
5543                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5544                                  items->spec)->hdr.next_header;
5545                                 next_protocol &=
5546                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5547                                  items->mask)->hdr.next_header;
5548                         } else {
5549                                 /* Reset for inner layer. */
5550                                 next_protocol = 0xff;
5551                         }
5552                         break;
5553                 case RTE_FLOW_ITEM_TYPE_TCP:
5554                         ret = mlx5_flow_validate_item_tcp
5555                                                 (items, item_flags,
5556                                                  next_protocol,
5557                                                  &nic_tcp_mask,
5558                                                  error);
5559                         if (ret < 0)
5560                                 return ret;
5561                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5562                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5563                         break;
5564                 case RTE_FLOW_ITEM_TYPE_UDP:
5565                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5566                                                           next_protocol,
5567                                                           error);
5568                         if (ret < 0)
5569                                 return ret;
5570                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5571                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5572                         break;
5573                 case RTE_FLOW_ITEM_TYPE_GRE:
5574                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5575                                                           next_protocol, error);
5576                         if (ret < 0)
5577                                 return ret;
5578                         gre_item = items;
5579                         last_item = MLX5_FLOW_LAYER_GRE;
5580                         break;
5581                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5582                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5583                                                             next_protocol,
5584                                                             error);
5585                         if (ret < 0)
5586                                 return ret;
5587                         last_item = MLX5_FLOW_LAYER_NVGRE;
5588                         break;
5589                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5590                         ret = mlx5_flow_validate_item_gre_key
5591                                 (items, item_flags, gre_item, error);
5592                         if (ret < 0)
5593                                 return ret;
5594                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5595                         break;
5596                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5597                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5598                                                             error);
5599                         if (ret < 0)
5600                                 return ret;
5601                         last_item = MLX5_FLOW_LAYER_VXLAN;
5602                         break;
5603                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5604                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5605                                                                 item_flags, dev,
5606                                                                 error);
5607                         if (ret < 0)
5608                                 return ret;
5609                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5610                         break;
5611                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5612                         ret = mlx5_flow_validate_item_geneve(items,
5613                                                              item_flags, dev,
5614                                                              error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         geneve_item = items;
5618                         last_item = MLX5_FLOW_LAYER_GENEVE;
5619                         break;
5620                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
5621                         ret = mlx5_flow_validate_item_geneve_opt(items,
5622                                                                  last_item,
5623                                                                  geneve_item,
5624                                                                  dev,
5625                                                                  error);
5626                         if (ret < 0)
5627                                 return ret;
5628                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
5629                         break;
5630                 case RTE_FLOW_ITEM_TYPE_MPLS:
5631                         ret = mlx5_flow_validate_item_mpls(dev, items,
5632                                                            item_flags,
5633                                                            last_item, error);
5634                         if (ret < 0)
5635                                 return ret;
5636                         last_item = MLX5_FLOW_LAYER_MPLS;
5637                         break;
5638
5639                 case RTE_FLOW_ITEM_TYPE_MARK:
5640                         ret = flow_dv_validate_item_mark(dev, items, attr,
5641                                                          error);
5642                         if (ret < 0)
5643                                 return ret;
5644                         last_item = MLX5_FLOW_ITEM_MARK;
5645                         break;
5646                 case RTE_FLOW_ITEM_TYPE_META:
5647                         ret = flow_dv_validate_item_meta(dev, items, attr,
5648                                                          error);
5649                         if (ret < 0)
5650                                 return ret;
5651                         last_item = MLX5_FLOW_ITEM_METADATA;
5652                         break;
5653                 case RTE_FLOW_ITEM_TYPE_ICMP:
5654                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5655                                                            next_protocol,
5656                                                            error);
5657                         if (ret < 0)
5658                                 return ret;
5659                         last_item = MLX5_FLOW_LAYER_ICMP;
5660                         break;
5661                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5662                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5663                                                             next_protocol,
5664                                                             error);
5665                         if (ret < 0)
5666                                 return ret;
5667                         item_ipv6_proto = IPPROTO_ICMPV6;
5668                         last_item = MLX5_FLOW_LAYER_ICMP6;
5669                         break;
5670                 case RTE_FLOW_ITEM_TYPE_TAG:
5671                         ret = flow_dv_validate_item_tag(dev, items,
5672                                                         attr, error);
5673                         if (ret < 0)
5674                                 return ret;
5675                         last_item = MLX5_FLOW_ITEM_TAG;
5676                         break;
5677                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5678                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5679                         break;
5680                 case RTE_FLOW_ITEM_TYPE_GTP:
5681                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5682                                                         error);
5683                         if (ret < 0)
5684                                 return ret;
5685                         gtp_item = items;
5686                         last_item = MLX5_FLOW_LAYER_GTP;
5687                         break;
5688                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
5689                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
5690                                                             gtp_item, attr,
5691                                                             error);
5692                         if (ret < 0)
5693                                 return ret;
5694                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
5695                         break;
5696                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5697                         /* Capacity will be checked in the translate stage. */
5698                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5699                                                             last_item,
5700                                                             ether_type,
5701                                                             &nic_ecpri_mask,
5702                                                             error);
5703                         if (ret < 0)
5704                                 return ret;
5705                         last_item = MLX5_FLOW_LAYER_ECPRI;
5706                         break;
5707                 default:
5708                         return rte_flow_error_set(error, ENOTSUP,
5709                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5710                                                   NULL, "item not supported");
5711                 }
5712                 item_flags |= last_item;
5713         }
5714         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5715                 int type = actions->type;
5716
5717                 if (!mlx5_flow_os_action_supported(type))
5718                         return rte_flow_error_set(error, ENOTSUP,
5719                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5720                                                   actions,
5721                                                   "action not supported");
5722                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5723                         return rte_flow_error_set(error, ENOTSUP,
5724                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5725                                                   actions, "too many actions");
5726                 switch (type) {
5727                 case RTE_FLOW_ACTION_TYPE_VOID:
5728                         break;
5729                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5730                         ret = flow_dv_validate_action_port_id(dev,
5731                                                               action_flags,
5732                                                               actions,
5733                                                               attr,
5734                                                               error);
5735                         if (ret)
5736                                 return ret;
5737                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5738                         ++actions_n;
5739                         break;
5740                 case RTE_FLOW_ACTION_TYPE_FLAG:
5741                         ret = flow_dv_validate_action_flag(dev, action_flags,
5742                                                            attr, error);
5743                         if (ret < 0)
5744                                 return ret;
5745                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5746                                 /* Count all modify-header actions as one. */
5747                                 if (!(action_flags &
5748                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5749                                         ++actions_n;
5750                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5751                                                 MLX5_FLOW_ACTION_MARK_EXT;
5752                         } else {
5753                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5754                                 ++actions_n;
5755                         }
5756                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5757                         break;
5758                 case RTE_FLOW_ACTION_TYPE_MARK:
5759                         ret = flow_dv_validate_action_mark(dev, actions,
5760                                                            action_flags,
5761                                                            attr, error);
5762                         if (ret < 0)
5763                                 return ret;
5764                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5765                                 /* Count all modify-header actions as one. */
5766                                 if (!(action_flags &
5767                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5768                                         ++actions_n;
5769                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5770                                                 MLX5_FLOW_ACTION_MARK_EXT;
5771                         } else {
5772                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5773                                 ++actions_n;
5774                         }
5775                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5776                         break;
5777                 case RTE_FLOW_ACTION_TYPE_SET_META:
5778                         ret = flow_dv_validate_action_set_meta(dev, actions,
5779                                                                action_flags,
5780                                                                attr, error);
5781                         if (ret < 0)
5782                                 return ret;
5783                         /* Count all modify-header actions as one action. */
5784                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5785                                 ++actions_n;
5786                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5787                         rw_act_num += MLX5_ACT_NUM_SET_META;
5788                         break;
5789                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5790                         ret = flow_dv_validate_action_set_tag(dev, actions,
5791                                                               action_flags,
5792                                                               attr, error);
5793                         if (ret < 0)
5794                                 return ret;
5795                         /* Count all modify-header actions as one action. */
5796                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5797                                 ++actions_n;
5798                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5799                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5800                         break;
5801                 case RTE_FLOW_ACTION_TYPE_DROP:
5802                         ret = mlx5_flow_validate_action_drop(action_flags,
5803                                                              attr, error);
5804                         if (ret < 0)
5805                                 return ret;
5806                         action_flags |= MLX5_FLOW_ACTION_DROP;
5807                         ++actions_n;
5808                         break;
5809                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5810                         ret = mlx5_flow_validate_action_queue(actions,
5811                                                               action_flags, dev,
5812                                                               attr, error);
5813                         if (ret < 0)
5814                                 return ret;
5815                         queue_index = ((const struct rte_flow_action_queue *)
5816                                                         (actions->conf))->index;
5817                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5818                         ++actions_n;
5819                         break;
5820                 case RTE_FLOW_ACTION_TYPE_RSS:
5821                         rss = actions->conf;
5822                         ret = mlx5_flow_validate_action_rss(actions,
5823                                                             action_flags, dev,
5824                                                             attr, item_flags,
5825                                                             error);
5826                         if (ret < 0)
5827                                 return ret;
5828                         if (rss && sample_rss &&
5829                             (sample_rss->level != rss->level ||
5830                             sample_rss->types != rss->types))
5831                                 return rte_flow_error_set(error, ENOTSUP,
5832                                         RTE_FLOW_ERROR_TYPE_ACTION,
5833                                         NULL,
5834                                         "Can't use the different RSS types "
5835                                         "or level in the same flow");
5836                         if (rss != NULL && rss->queue_num)
5837                                 queue_index = rss->queue[0];
5838                         action_flags |= MLX5_FLOW_ACTION_RSS;
5839                         ++actions_n;
5840                         break;
5841                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5842                         ret =
5843                         mlx5_flow_validate_action_default_miss(action_flags,
5844                                         attr, error);
5845                         if (ret < 0)
5846                                 return ret;
5847                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5848                         ++actions_n;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_COUNT:
5851                         ret = flow_dv_validate_action_count(dev, error);
5852                         if (ret < 0)
5853                                 return ret;
5854                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5855                         ++actions_n;
5856                         break;
5857                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5858                         if (flow_dv_validate_action_pop_vlan(dev,
5859                                                              action_flags,
5860                                                              actions,
5861                                                              item_flags, attr,
5862                                                              error))
5863                                 return -rte_errno;
5864                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5865                         ++actions_n;
5866                         break;
5867                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5868                         ret = flow_dv_validate_action_push_vlan(dev,
5869                                                                 action_flags,
5870                                                                 vlan_m,
5871                                                                 actions, attr,
5872                                                                 error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5876                         ++actions_n;
5877                         break;
5878                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5879                         ret = flow_dv_validate_action_set_vlan_pcp
5880                                                 (action_flags, actions, error);
5881                         if (ret < 0)
5882                                 return ret;
5883                         /* Count PCP with push_vlan command. */
5884                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5885                         break;
5886                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5887                         ret = flow_dv_validate_action_set_vlan_vid
5888                                                 (item_flags, action_flags,
5889                                                  actions, error);
5890                         if (ret < 0)
5891                                 return ret;
5892                         /* Count VID with push_vlan command. */
5893                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5894                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5895                         break;
5896                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5897                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5898                         ret = flow_dv_validate_action_l2_encap(dev,
5899                                                                action_flags,
5900                                                                actions, attr,
5901                                                                error);
5902                         if (ret < 0)
5903                                 return ret;
5904                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5905                         ++actions_n;
5906                         break;
5907                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5908                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5909                         ret = flow_dv_validate_action_decap(dev, action_flags,
5910                                                             actions, item_flags,
5911                                                             attr, error);
5912                         if (ret < 0)
5913                                 return ret;
5914                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5915                         ++actions_n;
5916                         break;
5917                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5918                         ret = flow_dv_validate_action_raw_encap_decap
5919                                 (dev, NULL, actions->conf, attr, &action_flags,
5920                                  &actions_n, actions, item_flags, error);
5921                         if (ret < 0)
5922                                 return ret;
5923                         break;
5924                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5925                         decap = actions->conf;
5926                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5927                                 ;
5928                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5929                                 encap = NULL;
5930                                 actions--;
5931                         } else {
5932                                 encap = actions->conf;
5933                         }
5934                         ret = flow_dv_validate_action_raw_encap_decap
5935                                            (dev,
5936                                             decap ? decap : &empty_decap, encap,
5937                                             attr, &action_flags, &actions_n,
5938                                             actions, item_flags, error);
5939                         if (ret < 0)
5940                                 return ret;
5941                         break;
5942                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5943                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5944                         ret = flow_dv_validate_action_modify_mac(action_flags,
5945                                                                  actions,
5946                                                                  item_flags,
5947                                                                  error);
5948                         if (ret < 0)
5949                                 return ret;
5950                         /* Count all modify-header actions as one action. */
5951                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5952                                 ++actions_n;
5953                         action_flags |= actions->type ==
5954                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5955                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5956                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5957                         /*
5958                          * Even if the source and destination MAC addresses have
5959                          * overlap in the header with 4B alignment, the convert
5960                          * function will handle them separately and 4 SW actions
5961                          * will be created. And 2 actions will be added each
5962                          * time no matter how many bytes of address will be set.
5963                          */
5964                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5965                         break;
5966                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5967                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5968                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5969                                                                   actions,
5970                                                                   item_flags,
5971                                                                   error);
5972                         if (ret < 0)
5973                                 return ret;
5974                         /* Count all modify-header actions as one action. */
5975                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5976                                 ++actions_n;
5977                         action_flags |= actions->type ==
5978                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5979                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5980                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5981                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5982                         break;
5983                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5984                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5985                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5986                                                                   actions,
5987                                                                   item_flags,
5988                                                                   error);
5989                         if (ret < 0)
5990                                 return ret;
5991                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5992                                 return rte_flow_error_set(error, ENOTSUP,
5993                                         RTE_FLOW_ERROR_TYPE_ACTION,
5994                                         actions,
5995                                         "Can't change header "
5996                                         "with ICMPv6 proto");
5997                         /* Count all modify-header actions as one action. */
5998                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5999                                 ++actions_n;
6000                         action_flags |= actions->type ==
6001                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6002                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6003                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6004                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6005                         break;
6006                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6007                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6008                         ret = flow_dv_validate_action_modify_tp(action_flags,
6009                                                                 actions,
6010                                                                 item_flags,
6011                                                                 error);
6012                         if (ret < 0)
6013                                 return ret;
6014                         /* Count all modify-header actions as one action. */
6015                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6016                                 ++actions_n;
6017                         action_flags |= actions->type ==
6018                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6019                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6020                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6021                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6022                         break;
6023                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6024                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6025                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6026                                                                  actions,
6027                                                                  item_flags,
6028                                                                  error);
6029                         if (ret < 0)
6030                                 return ret;
6031                         /* Count all modify-header actions as one action. */
6032                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6033                                 ++actions_n;
6034                         action_flags |= actions->type ==
6035                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6036                                                 MLX5_FLOW_ACTION_SET_TTL :
6037                                                 MLX5_FLOW_ACTION_DEC_TTL;
6038                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6039                         break;
6040                 case RTE_FLOW_ACTION_TYPE_JUMP:
6041                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6042                                                            action_flags,
6043                                                            attr, external,
6044                                                            error);
6045                         if (ret)
6046                                 return ret;
6047                         ++actions_n;
6048                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6049                         break;
6050                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6051                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6052                         ret = flow_dv_validate_action_modify_tcp_seq
6053                                                                 (action_flags,
6054                                                                  actions,
6055                                                                  item_flags,
6056                                                                  error);
6057                         if (ret < 0)
6058                                 return ret;
6059                         /* Count all modify-header actions as one action. */
6060                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6061                                 ++actions_n;
6062                         action_flags |= actions->type ==
6063                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6064                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6065                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6066                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6067                         break;
6068                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6069                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6070                         ret = flow_dv_validate_action_modify_tcp_ack
6071                                                                 (action_flags,
6072                                                                  actions,
6073                                                                  item_flags,
6074                                                                  error);
6075                         if (ret < 0)
6076                                 return ret;
6077                         /* Count all modify-header actions as one action. */
6078                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6079                                 ++actions_n;
6080                         action_flags |= actions->type ==
6081                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6082                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6083                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6084                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6085                         break;
6086                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6087                         break;
6088                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6089                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6090                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6091                         break;
6092                 case RTE_FLOW_ACTION_TYPE_METER:
6093                         ret = mlx5_flow_validate_action_meter(dev,
6094                                                               action_flags,
6095                                                               actions, attr,
6096                                                               error);
6097                         if (ret < 0)
6098                                 return ret;
6099                         action_flags |= MLX5_FLOW_ACTION_METER;
6100                         ++actions_n;
6101                         /* Meter action will add one more TAG action. */
6102                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6103                         break;
6104                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6105                         if (!attr->transfer && !attr->group)
6106                                 return rte_flow_error_set(error, ENOTSUP,
6107                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6108                                                                            NULL,
6109                           "Shared ASO age action is not supported for group 0");
6110                         action_flags |= MLX5_FLOW_ACTION_AGE;
6111                         ++actions_n;
6112                         break;
6113                 case RTE_FLOW_ACTION_TYPE_AGE:
6114                         ret = flow_dv_validate_action_age(action_flags,
6115                                                           actions, dev,
6116                                                           error);
6117                         if (ret < 0)
6118                                 return ret;
6119                         action_flags |= MLX5_FLOW_ACTION_AGE;
6120                         ++actions_n;
6121                         break;
6122                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6123                         ret = flow_dv_validate_action_modify_ipv4_dscp
6124                                                          (action_flags,
6125                                                           actions,
6126                                                           item_flags,
6127                                                           error);
6128                         if (ret < 0)
6129                                 return ret;
6130                         /* Count all modify-header actions as one action. */
6131                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6132                                 ++actions_n;
6133                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6134                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6135                         break;
6136                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6137                         ret = flow_dv_validate_action_modify_ipv6_dscp
6138                                                                 (action_flags,
6139                                                                  actions,
6140                                                                  item_flags,
6141                                                                  error);
6142                         if (ret < 0)
6143                                 return ret;
6144                         /* Count all modify-header actions as one action. */
6145                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6146                                 ++actions_n;
6147                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6148                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6149                         break;
6150                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6151                         ret = flow_dv_validate_action_sample(action_flags,
6152                                                              actions, dev,
6153                                                              attr, item_flags,
6154                                                              rss, &sample_rss,
6155                                                              error);
6156                         if (ret < 0)
6157                                 return ret;
6158                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6159                         ++actions_n;
6160                         break;
6161                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6162                         if (actions[0].type != (typeof(actions[0].type))
6163                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6164                                 return rte_flow_error_set
6165                                                 (error, EINVAL,
6166                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6167                                                 NULL, "MLX5 private action "
6168                                                 "must be the first");
6169
6170                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6171                         break;
6172                 default:
6173                         return rte_flow_error_set(error, ENOTSUP,
6174                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6175                                                   actions,
6176                                                   "action not supported");
6177                 }
6178         }
6179         /*
6180          * Validate actions in flow rules
6181          * - Explicit decap action is prohibited by the tunnel offload API.
6182          * - Drop action in tunnel steer rule is prohibited by the API.
6183          * - Application cannot use MARK action because it's value can mask
6184          *   tunnel default miss nitification.
6185          * - JUMP in tunnel match rule has no support in current PMD
6186          *   implementation.
6187          * - TAG & META are reserved for future uses.
6188          */
6189         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6190                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6191                                             MLX5_FLOW_ACTION_MARK     |
6192                                             MLX5_FLOW_ACTION_SET_TAG  |
6193                                             MLX5_FLOW_ACTION_SET_META |
6194                                             MLX5_FLOW_ACTION_DROP;
6195
6196                 if (action_flags & bad_actions_mask)
6197                         return rte_flow_error_set
6198                                         (error, EINVAL,
6199                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6200                                         "Invalid RTE action in tunnel "
6201                                         "set decap rule");
6202                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6203                         return rte_flow_error_set
6204                                         (error, EINVAL,
6205                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6206                                         "tunnel set decap rule must terminate "
6207                                         "with JUMP");
6208                 if (!attr->ingress)
6209                         return rte_flow_error_set
6210                                         (error, EINVAL,
6211                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6212                                         "tunnel flows for ingress traffic only");
6213         }
6214         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6215                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6216                                             MLX5_FLOW_ACTION_MARK    |
6217                                             MLX5_FLOW_ACTION_SET_TAG |
6218                                             MLX5_FLOW_ACTION_SET_META;
6219
6220                 if (action_flags & bad_actions_mask)
6221                         return rte_flow_error_set
6222                                         (error, EINVAL,
6223                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6224                                         "Invalid RTE action in tunnel "
6225                                         "set match rule");
6226         }
6227         /*
6228          * Validate the drop action mutual exclusion with other actions.
6229          * Drop action is mutually-exclusive with any other action, except for
6230          * Count action.
6231          * Drop action compatibility with tunnel offload was already validated.
6232          */
6233         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
6234                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
6235         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6236             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6237                 return rte_flow_error_set(error, EINVAL,
6238                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6239                                           "Drop action is mutually-exclusive "
6240                                           "with any other action, except for "
6241                                           "Count action");
6242         /* Eswitch has few restrictions on using items and actions */
6243         if (attr->transfer) {
6244                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6245                     action_flags & MLX5_FLOW_ACTION_FLAG)
6246                         return rte_flow_error_set(error, ENOTSUP,
6247                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6248                                                   NULL,
6249                                                   "unsupported action FLAG");
6250                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6251                     action_flags & MLX5_FLOW_ACTION_MARK)
6252                         return rte_flow_error_set(error, ENOTSUP,
6253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6254                                                   NULL,
6255                                                   "unsupported action MARK");
6256                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6257                         return rte_flow_error_set(error, ENOTSUP,
6258                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6259                                                   NULL,
6260                                                   "unsupported action QUEUE");
6261                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6262                         return rte_flow_error_set(error, ENOTSUP,
6263                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6264                                                   NULL,
6265                                                   "unsupported action RSS");
6266                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6267                         return rte_flow_error_set(error, EINVAL,
6268                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6269                                                   actions,
6270                                                   "no fate action is found");
6271         } else {
6272                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6273                         return rte_flow_error_set(error, EINVAL,
6274                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6275                                                   actions,
6276                                                   "no fate action is found");
6277         }
6278         /*
6279          * Continue validation for Xcap and VLAN actions.
6280          * If hairpin is working in explicit TX rule mode, there is no actions
6281          * splitting and the validation of hairpin ingress flow should be the
6282          * same as other standard flows.
6283          */
6284         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6285                              MLX5_FLOW_VLAN_ACTIONS)) &&
6286             (queue_index == 0xFFFF ||
6287              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6288              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6289              conf->tx_explicit != 0))) {
6290                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6291                     MLX5_FLOW_XCAP_ACTIONS)
6292                         return rte_flow_error_set(error, ENOTSUP,
6293                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6294                                                   NULL, "encap and decap "
6295                                                   "combination aren't supported");
6296                 if (!attr->transfer && attr->ingress) {
6297                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6298                                 return rte_flow_error_set
6299                                                 (error, ENOTSUP,
6300                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6301                                                  NULL, "encap is not supported"
6302                                                  " for ingress traffic");
6303                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6304                                 return rte_flow_error_set
6305                                                 (error, ENOTSUP,
6306                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6307                                                  NULL, "push VLAN action not "
6308                                                  "supported for ingress");
6309                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6310                                         MLX5_FLOW_VLAN_ACTIONS)
6311                                 return rte_flow_error_set
6312                                                 (error, ENOTSUP,
6313                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6314                                                  NULL, "no support for "
6315                                                  "multiple VLAN actions");
6316                 }
6317         }
6318         /*
6319          * Hairpin flow will add one more TAG action in TX implicit mode.
6320          * In TX explicit mode, there will be no hairpin flow ID.
6321          */
6322         if (hairpin > 0)
6323                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6324         /* extra metadata enabled: one more TAG action will be add. */
6325         if (dev_conf->dv_flow_en &&
6326             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6327             mlx5_flow_ext_mreg_supported(dev))
6328                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6329         if ((uint32_t)rw_act_num >
6330                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6331                 return rte_flow_error_set(error, ENOTSUP,
6332                                           RTE_FLOW_ERROR_TYPE_ACTION,
6333                                           NULL, "too many header modify"
6334                                           " actions to support");
6335         }
6336         return 0;
6337 }
6338
6339 /**
6340  * Internal preparation function. Allocates the DV flow size,
6341  * this size is constant.
6342  *
6343  * @param[in] dev
6344  *   Pointer to the rte_eth_dev structure.
6345  * @param[in] attr
6346  *   Pointer to the flow attributes.
6347  * @param[in] items
6348  *   Pointer to the list of items.
6349  * @param[in] actions
6350  *   Pointer to the list of actions.
6351  * @param[out] error
6352  *   Pointer to the error structure.
6353  *
6354  * @return
6355  *   Pointer to mlx5_flow object on success,
6356  *   otherwise NULL and rte_errno is set.
6357  */
6358 static struct mlx5_flow *
6359 flow_dv_prepare(struct rte_eth_dev *dev,
6360                 const struct rte_flow_attr *attr __rte_unused,
6361                 const struct rte_flow_item items[] __rte_unused,
6362                 const struct rte_flow_action actions[] __rte_unused,
6363                 struct rte_flow_error *error)
6364 {
6365         uint32_t handle_idx = 0;
6366         struct mlx5_flow *dev_flow;
6367         struct mlx5_flow_handle *dev_handle;
6368         struct mlx5_priv *priv = dev->data->dev_private;
6369         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6370
6371         MLX5_ASSERT(wks);
6372         /* In case of corrupting the memory. */
6373         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6374                 rte_flow_error_set(error, ENOSPC,
6375                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6376                                    "not free temporary device flow");
6377                 return NULL;
6378         }
6379         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6380                                    &handle_idx);
6381         if (!dev_handle) {
6382                 rte_flow_error_set(error, ENOMEM,
6383                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6384                                    "not enough memory to create flow handle");
6385                 return NULL;
6386         }
6387         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6388         dev_flow = &wks->flows[wks->flow_idx++];
6389         memset(dev_flow, 0, sizeof(*dev_flow));
6390         dev_flow->handle = dev_handle;
6391         dev_flow->handle_idx = handle_idx;
6392         /*
6393          * In some old rdma-core releases, before continuing, a check of the
6394          * length of matching parameter will be done at first. It needs to use
6395          * the length without misc4 param. If the flow has misc4 support, then
6396          * the length needs to be adjusted accordingly. Each param member is
6397          * aligned with a 64B boundary naturally.
6398          */
6399         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6400                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6401         dev_flow->ingress = attr->ingress;
6402         dev_flow->dv.transfer = attr->transfer;
6403         return dev_flow;
6404 }
6405
6406 #ifdef RTE_LIBRTE_MLX5_DEBUG
6407 /**
6408  * Sanity check for match mask and value. Similar to check_valid_spec() in
6409  * kernel driver. If unmasked bit is present in value, it returns failure.
6410  *
6411  * @param match_mask
6412  *   pointer to match mask buffer.
6413  * @param match_value
6414  *   pointer to match value buffer.
6415  *
6416  * @return
6417  *   0 if valid, -EINVAL otherwise.
6418  */
6419 static int
6420 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6421 {
6422         uint8_t *m = match_mask;
6423         uint8_t *v = match_value;
6424         unsigned int i;
6425
6426         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6427                 if (v[i] & ~m[i]) {
6428                         DRV_LOG(ERR,
6429                                 "match_value differs from match_criteria"
6430                                 " %p[%u] != %p[%u]",
6431                                 match_value, i, match_mask, i);
6432                         return -EINVAL;
6433                 }
6434         }
6435         return 0;
6436 }
6437 #endif
6438
6439 /**
6440  * Add match of ip_version.
6441  *
6442  * @param[in] group
6443  *   Flow group.
6444  * @param[in] headers_v
6445  *   Values header pointer.
6446  * @param[in] headers_m
6447  *   Masks header pointer.
6448  * @param[in] ip_version
6449  *   The IP version to set.
6450  */
6451 static inline void
6452 flow_dv_set_match_ip_version(uint32_t group,
6453                              void *headers_v,
6454                              void *headers_m,
6455                              uint8_t ip_version)
6456 {
6457         if (group == 0)
6458                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6459         else
6460                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6461                          ip_version);
6462         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6463         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6464         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6465 }
6466
6467 /**
6468  * Add Ethernet item to matcher and to the value.
6469  *
6470  * @param[in, out] matcher
6471  *   Flow matcher.
6472  * @param[in, out] key
6473  *   Flow matcher value.
6474  * @param[in] item
6475  *   Flow pattern to translate.
6476  * @param[in] inner
6477  *   Item is inner pattern.
6478  */
6479 static void
6480 flow_dv_translate_item_eth(void *matcher, void *key,
6481                            const struct rte_flow_item *item, int inner,
6482                            uint32_t group)
6483 {
6484         const struct rte_flow_item_eth *eth_m = item->mask;
6485         const struct rte_flow_item_eth *eth_v = item->spec;
6486         const struct rte_flow_item_eth nic_mask = {
6487                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6488                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6489                 .type = RTE_BE16(0xffff),
6490                 .has_vlan = 0,
6491         };
6492         void *hdrs_m;
6493         void *hdrs_v;
6494         char *l24_v;
6495         unsigned int i;
6496
6497         if (!eth_v)
6498                 return;
6499         if (!eth_m)
6500                 eth_m = &nic_mask;
6501         if (inner) {
6502                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6503                                          inner_headers);
6504                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6505         } else {
6506                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6507                                          outer_headers);
6508                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6509         }
6510         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6511                &eth_m->dst, sizeof(eth_m->dst));
6512         /* The value must be in the range of the mask. */
6513         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6514         for (i = 0; i < sizeof(eth_m->dst); ++i)
6515                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6516         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6517                &eth_m->src, sizeof(eth_m->src));
6518         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6519         /* The value must be in the range of the mask. */
6520         for (i = 0; i < sizeof(eth_m->dst); ++i)
6521                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6522         /*
6523          * HW supports match on one Ethertype, the Ethertype following the last
6524          * VLAN tag of the packet (see PRM).
6525          * Set match on ethertype only if ETH header is not followed by VLAN.
6526          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6527          * ethertype, and use ip_version field instead.
6528          * eCPRI over Ether layer will use type value 0xAEFE.
6529          */
6530         if (eth_m->type == 0xFFFF) {
6531                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6532                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6533                 switch (eth_v->type) {
6534                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6535                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6536                         return;
6537                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6538                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6539                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6540                         return;
6541                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6542                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6543                         return;
6544                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6545                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6546                         return;
6547                 default:
6548                         break;
6549                 }
6550         }
6551         if (eth_m->has_vlan) {
6552                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6553                 if (eth_v->has_vlan) {
6554                         /*
6555                          * Here, when also has_more_vlan field in VLAN item is
6556                          * not set, only single-tagged packets will be matched.
6557                          */
6558                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6559                         return;
6560                 }
6561         }
6562         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6563                  rte_be_to_cpu_16(eth_m->type));
6564         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6565         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6566 }
6567
6568 /**
6569  * Add VLAN item to matcher and to the value.
6570  *
6571  * @param[in, out] dev_flow
6572  *   Flow descriptor.
6573  * @param[in, out] matcher
6574  *   Flow matcher.
6575  * @param[in, out] key
6576  *   Flow matcher value.
6577  * @param[in] item
6578  *   Flow pattern to translate.
6579  * @param[in] inner
6580  *   Item is inner pattern.
6581  */
6582 static void
6583 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6584                             void *matcher, void *key,
6585                             const struct rte_flow_item *item,
6586                             int inner, uint32_t group)
6587 {
6588         const struct rte_flow_item_vlan *vlan_m = item->mask;
6589         const struct rte_flow_item_vlan *vlan_v = item->spec;
6590         void *hdrs_m;
6591         void *hdrs_v;
6592         uint16_t tci_m;
6593         uint16_t tci_v;
6594
6595         if (inner) {
6596                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6597                                          inner_headers);
6598                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6599         } else {
6600                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6601                                          outer_headers);
6602                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6603                 /*
6604                  * This is workaround, masks are not supported,
6605                  * and pre-validated.
6606                  */
6607                 if (vlan_v)
6608                         dev_flow->handle->vf_vlan.tag =
6609                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6610         }
6611         /*
6612          * When VLAN item exists in flow, mark packet as tagged,
6613          * even if TCI is not specified.
6614          */
6615         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6616                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6617                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6618         }
6619         if (!vlan_v)
6620                 return;
6621         if (!vlan_m)
6622                 vlan_m = &rte_flow_item_vlan_mask;
6623         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6624         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6625         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6626         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6627         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6628         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6629         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6630         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6631         /*
6632          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6633          * ethertype, and use ip_version field instead.
6634          */
6635         if (vlan_m->inner_type == 0xFFFF) {
6636                 switch (vlan_v->inner_type) {
6637                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6638                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6639                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6640                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6641                         return;
6642                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6643                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6644                         return;
6645                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6646                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6647                         return;
6648                 default:
6649                         break;
6650                 }
6651         }
6652         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6653                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6654                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6655                 /* Only one vlan_tag bit can be set. */
6656                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6657                 return;
6658         }
6659         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6660                  rte_be_to_cpu_16(vlan_m->inner_type));
6661         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6662                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6663 }
6664
6665 /**
6666  * Add IPV4 item to matcher and to the value.
6667  *
6668  * @param[in, out] matcher
6669  *   Flow matcher.
6670  * @param[in, out] key
6671  *   Flow matcher value.
6672  * @param[in] item
6673  *   Flow pattern to translate.
6674  * @param[in] inner
6675  *   Item is inner pattern.
6676  * @param[in] group
6677  *   The group to insert the rule.
6678  */
6679 static void
6680 flow_dv_translate_item_ipv4(void *matcher, void *key,
6681                             const struct rte_flow_item *item,
6682                             int inner, uint32_t group)
6683 {
6684         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6685         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6686         const struct rte_flow_item_ipv4 nic_mask = {
6687                 .hdr = {
6688                         .src_addr = RTE_BE32(0xffffffff),
6689                         .dst_addr = RTE_BE32(0xffffffff),
6690                         .type_of_service = 0xff,
6691                         .next_proto_id = 0xff,
6692                         .time_to_live = 0xff,
6693                 },
6694         };
6695         void *headers_m;
6696         void *headers_v;
6697         char *l24_m;
6698         char *l24_v;
6699         uint8_t tos;
6700
6701         if (inner) {
6702                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6703                                          inner_headers);
6704                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6705         } else {
6706                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6707                                          outer_headers);
6708                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6709         }
6710         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6711         if (!ipv4_v)
6712                 return;
6713         if (!ipv4_m)
6714                 ipv4_m = &nic_mask;
6715         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6716                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6717         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6718                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6719         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6720         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6721         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6722                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6723         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6724                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6725         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6726         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6727         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6729                  ipv4_m->hdr.type_of_service);
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6731         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6732                  ipv4_m->hdr.type_of_service >> 2);
6733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6734         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6735                  ipv4_m->hdr.next_proto_id);
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6737                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6738         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6739                  ipv4_m->hdr.time_to_live);
6740         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6741                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6742         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6743                  !!(ipv4_m->hdr.fragment_offset));
6744         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6745                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6746 }
6747
6748 /**
6749  * Add IPV6 item to matcher and to the value.
6750  *
6751  * @param[in, out] matcher
6752  *   Flow matcher.
6753  * @param[in, out] key
6754  *   Flow matcher value.
6755  * @param[in] item
6756  *   Flow pattern to translate.
6757  * @param[in] inner
6758  *   Item is inner pattern.
6759  * @param[in] group
6760  *   The group to insert the rule.
6761  */
6762 static void
6763 flow_dv_translate_item_ipv6(void *matcher, void *key,
6764                             const struct rte_flow_item *item,
6765                             int inner, uint32_t group)
6766 {
6767         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6768         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6769         const struct rte_flow_item_ipv6 nic_mask = {
6770                 .hdr = {
6771                         .src_addr =
6772                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6773                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6774                         .dst_addr =
6775                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6776                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6777                         .vtc_flow = RTE_BE32(0xffffffff),
6778                         .proto = 0xff,
6779                         .hop_limits = 0xff,
6780                 },
6781         };
6782         void *headers_m;
6783         void *headers_v;
6784         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6785         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6786         char *l24_m;
6787         char *l24_v;
6788         uint32_t vtc_m;
6789         uint32_t vtc_v;
6790         int i;
6791         int size;
6792
6793         if (inner) {
6794                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6795                                          inner_headers);
6796                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6797         } else {
6798                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6799                                          outer_headers);
6800                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6801         }
6802         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6803         if (!ipv6_v)
6804                 return;
6805         if (!ipv6_m)
6806                 ipv6_m = &nic_mask;
6807         size = sizeof(ipv6_m->hdr.dst_addr);
6808         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6809                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6810         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6811                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6812         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6813         for (i = 0; i < size; ++i)
6814                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6815         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6816                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6817         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6818                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6819         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6820         for (i = 0; i < size; ++i)
6821                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6822         /* TOS. */
6823         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6824         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6826         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6827         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6828         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6829         /* Label. */
6830         if (inner) {
6831                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6832                          vtc_m);
6833                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6834                          vtc_v);
6835         } else {
6836                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6837                          vtc_m);
6838                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6839                          vtc_v);
6840         }
6841         /* Protocol. */
6842         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6843                  ipv6_m->hdr.proto);
6844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6845                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6846         /* Hop limit. */
6847         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6848                  ipv6_m->hdr.hop_limits);
6849         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6850                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6851         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6852                  !!(ipv6_m->has_frag_ext));
6853         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6854                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6855 }
6856
6857 /**
6858  * Add IPV6 fragment extension item to matcher and to the value.
6859  *
6860  * @param[in, out] matcher
6861  *   Flow matcher.
6862  * @param[in, out] key
6863  *   Flow matcher value.
6864  * @param[in] item
6865  *   Flow pattern to translate.
6866  * @param[in] inner
6867  *   Item is inner pattern.
6868  */
6869 static void
6870 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6871                                      const struct rte_flow_item *item,
6872                                      int inner)
6873 {
6874         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6875         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6876         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6877                 .hdr = {
6878                         .next_header = 0xff,
6879                         .frag_data = RTE_BE16(0xffff),
6880                 },
6881         };
6882         void *headers_m;
6883         void *headers_v;
6884
6885         if (inner) {
6886                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6887                                          inner_headers);
6888                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6889         } else {
6890                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6891                                          outer_headers);
6892                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6893         }
6894         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6895         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6896         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6897         if (!ipv6_frag_ext_v)
6898                 return;
6899         if (!ipv6_frag_ext_m)
6900                 ipv6_frag_ext_m = &nic_mask;
6901         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6902                  ipv6_frag_ext_m->hdr.next_header);
6903         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6904                  ipv6_frag_ext_v->hdr.next_header &
6905                  ipv6_frag_ext_m->hdr.next_header);
6906 }
6907
6908 /**
6909  * Add TCP item to matcher and to the value.
6910  *
6911  * @param[in, out] matcher
6912  *   Flow matcher.
6913  * @param[in, out] key
6914  *   Flow matcher value.
6915  * @param[in] item
6916  *   Flow pattern to translate.
6917  * @param[in] inner
6918  *   Item is inner pattern.
6919  */
6920 static void
6921 flow_dv_translate_item_tcp(void *matcher, void *key,
6922                            const struct rte_flow_item *item,
6923                            int inner)
6924 {
6925         const struct rte_flow_item_tcp *tcp_m = item->mask;
6926         const struct rte_flow_item_tcp *tcp_v = item->spec;
6927         void *headers_m;
6928         void *headers_v;
6929
6930         if (inner) {
6931                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6932                                          inner_headers);
6933                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6934         } else {
6935                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6936                                          outer_headers);
6937                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6938         }
6939         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6940         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6941         if (!tcp_v)
6942                 return;
6943         if (!tcp_m)
6944                 tcp_m = &rte_flow_item_tcp_mask;
6945         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6946                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6947         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6948                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6949         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6950                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6951         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6952                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6953         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6954                  tcp_m->hdr.tcp_flags);
6955         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6956                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6957 }
6958
6959 /**
6960  * Add UDP item to matcher and to the value.
6961  *
6962  * @param[in, out] matcher
6963  *   Flow matcher.
6964  * @param[in, out] key
6965  *   Flow matcher value.
6966  * @param[in] item
6967  *   Flow pattern to translate.
6968  * @param[in] inner
6969  *   Item is inner pattern.
6970  */
6971 static void
6972 flow_dv_translate_item_udp(void *matcher, void *key,
6973                            const struct rte_flow_item *item,
6974                            int inner)
6975 {
6976         const struct rte_flow_item_udp *udp_m = item->mask;
6977         const struct rte_flow_item_udp *udp_v = item->spec;
6978         void *headers_m;
6979         void *headers_v;
6980
6981         if (inner) {
6982                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6983                                          inner_headers);
6984                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6985         } else {
6986                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6987                                          outer_headers);
6988                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6989         }
6990         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6991         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6992         if (!udp_v)
6993                 return;
6994         if (!udp_m)
6995                 udp_m = &rte_flow_item_udp_mask;
6996         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6997                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6998         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6999                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7000         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7001                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7002         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7003                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7004 }
7005
7006 /**
7007  * Add GRE optional Key item to matcher and to the value.
7008  *
7009  * @param[in, out] matcher
7010  *   Flow matcher.
7011  * @param[in, out] key
7012  *   Flow matcher value.
7013  * @param[in] item
7014  *   Flow pattern to translate.
7015  * @param[in] inner
7016  *   Item is inner pattern.
7017  */
7018 static void
7019 flow_dv_translate_item_gre_key(void *matcher, void *key,
7020                                    const struct rte_flow_item *item)
7021 {
7022         const rte_be32_t *key_m = item->mask;
7023         const rte_be32_t *key_v = item->spec;
7024         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7025         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7026         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7027
7028         /* GRE K bit must be on and should already be validated */
7029         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7030         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7031         if (!key_v)
7032                 return;
7033         if (!key_m)
7034                 key_m = &gre_key_default_mask;
7035         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7036                  rte_be_to_cpu_32(*key_m) >> 8);
7037         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7038                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7039         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7040                  rte_be_to_cpu_32(*key_m) & 0xFF);
7041         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7042                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7043 }
7044
7045 /**
7046  * Add GRE item to matcher and to the value.
7047  *
7048  * @param[in, out] matcher
7049  *   Flow matcher.
7050  * @param[in, out] key
7051  *   Flow matcher value.
7052  * @param[in] item
7053  *   Flow pattern to translate.
7054  * @param[in] inner
7055  *   Item is inner pattern.
7056  */
7057 static void
7058 flow_dv_translate_item_gre(void *matcher, void *key,
7059                            const struct rte_flow_item *item,
7060                            int inner)
7061 {
7062         const struct rte_flow_item_gre *gre_m = item->mask;
7063         const struct rte_flow_item_gre *gre_v = item->spec;
7064         void *headers_m;
7065         void *headers_v;
7066         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7067         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7068         struct {
7069                 union {
7070                         __extension__
7071                         struct {
7072                                 uint16_t version:3;
7073                                 uint16_t rsvd0:9;
7074                                 uint16_t s_present:1;
7075                                 uint16_t k_present:1;
7076                                 uint16_t rsvd_bit1:1;
7077                                 uint16_t c_present:1;
7078                         };
7079                         uint16_t value;
7080                 };
7081         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7082
7083         if (inner) {
7084                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7085                                          inner_headers);
7086                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7087         } else {
7088                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7089                                          outer_headers);
7090                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7091         }
7092         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7093         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7094         if (!gre_v)
7095                 return;
7096         if (!gre_m)
7097                 gre_m = &rte_flow_item_gre_mask;
7098         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7099                  rte_be_to_cpu_16(gre_m->protocol));
7100         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7101                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7102         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7103         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7104         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7105                  gre_crks_rsvd0_ver_m.c_present);
7106         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7107                  gre_crks_rsvd0_ver_v.c_present &
7108                  gre_crks_rsvd0_ver_m.c_present);
7109         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7110                  gre_crks_rsvd0_ver_m.k_present);
7111         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7112                  gre_crks_rsvd0_ver_v.k_present &
7113                  gre_crks_rsvd0_ver_m.k_present);
7114         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7115                  gre_crks_rsvd0_ver_m.s_present);
7116         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7117                  gre_crks_rsvd0_ver_v.s_present &
7118                  gre_crks_rsvd0_ver_m.s_present);
7119 }
7120
7121 /**
7122  * Add NVGRE item to matcher and to the value.
7123  *
7124  * @param[in, out] matcher
7125  *   Flow matcher.
7126  * @param[in, out] key
7127  *   Flow matcher value.
7128  * @param[in] item
7129  *   Flow pattern to translate.
7130  * @param[in] inner
7131  *   Item is inner pattern.
7132  */
7133 static void
7134 flow_dv_translate_item_nvgre(void *matcher, void *key,
7135                              const struct rte_flow_item *item,
7136                              int inner)
7137 {
7138         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7139         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7140         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7141         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7142         const char *tni_flow_id_m;
7143         const char *tni_flow_id_v;
7144         char *gre_key_m;
7145         char *gre_key_v;
7146         int size;
7147         int i;
7148
7149         /* For NVGRE, GRE header fields must be set with defined values. */
7150         const struct rte_flow_item_gre gre_spec = {
7151                 .c_rsvd0_ver = RTE_BE16(0x2000),
7152                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7153         };
7154         const struct rte_flow_item_gre gre_mask = {
7155                 .c_rsvd0_ver = RTE_BE16(0xB000),
7156                 .protocol = RTE_BE16(UINT16_MAX),
7157         };
7158         const struct rte_flow_item gre_item = {
7159                 .spec = &gre_spec,
7160                 .mask = &gre_mask,
7161                 .last = NULL,
7162         };
7163         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7164         if (!nvgre_v)
7165                 return;
7166         if (!nvgre_m)
7167                 nvgre_m = &rte_flow_item_nvgre_mask;
7168         tni_flow_id_m = (const char *)nvgre_m->tni;
7169         tni_flow_id_v = (const char *)nvgre_v->tni;
7170         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7171         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7172         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7173         memcpy(gre_key_m, tni_flow_id_m, size);
7174         for (i = 0; i < size; ++i)
7175                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7176 }
7177
7178 /**
7179  * Add VXLAN item to matcher and to the value.
7180  *
7181  * @param[in, out] matcher
7182  *   Flow matcher.
7183  * @param[in, out] key
7184  *   Flow matcher value.
7185  * @param[in] item
7186  *   Flow pattern to translate.
7187  * @param[in] inner
7188  *   Item is inner pattern.
7189  */
7190 static void
7191 flow_dv_translate_item_vxlan(void *matcher, void *key,
7192                              const struct rte_flow_item *item,
7193                              int inner)
7194 {
7195         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7196         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7197         void *headers_m;
7198         void *headers_v;
7199         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7200         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7201         char *vni_m;
7202         char *vni_v;
7203         uint16_t dport;
7204         int size;
7205         int i;
7206
7207         if (inner) {
7208                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7209                                          inner_headers);
7210                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7211         } else {
7212                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7213                                          outer_headers);
7214                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7215         }
7216         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7217                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7218         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7219                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7220                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7221         }
7222         if (!vxlan_v)
7223                 return;
7224         if (!vxlan_m)
7225                 vxlan_m = &rte_flow_item_vxlan_mask;
7226         size = sizeof(vxlan_m->vni);
7227         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7228         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7229         memcpy(vni_m, vxlan_m->vni, size);
7230         for (i = 0; i < size; ++i)
7231                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7232 }
7233
7234 /**
7235  * Add VXLAN-GPE item to matcher and to the value.
7236  *
7237  * @param[in, out] matcher
7238  *   Flow matcher.
7239  * @param[in, out] key
7240  *   Flow matcher value.
7241  * @param[in] item
7242  *   Flow pattern to translate.
7243  * @param[in] inner
7244  *   Item is inner pattern.
7245  */
7246
7247 static void
7248 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7249                                  const struct rte_flow_item *item, int inner)
7250 {
7251         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7252         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7253         void *headers_m;
7254         void *headers_v;
7255         void *misc_m =
7256                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7257         void *misc_v =
7258                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7259         char *vni_m;
7260         char *vni_v;
7261         uint16_t dport;
7262         int size;
7263         int i;
7264         uint8_t flags_m = 0xff;
7265         uint8_t flags_v = 0xc;
7266
7267         if (inner) {
7268                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7269                                          inner_headers);
7270                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7271         } else {
7272                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7273                                          outer_headers);
7274                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7275         }
7276         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7277                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7278         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7279                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7280                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7281         }
7282         if (!vxlan_v)
7283                 return;
7284         if (!vxlan_m)
7285                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7286         size = sizeof(vxlan_m->vni);
7287         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7288         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7289         memcpy(vni_m, vxlan_m->vni, size);
7290         for (i = 0; i < size; ++i)
7291                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7292         if (vxlan_m->flags) {
7293                 flags_m = vxlan_m->flags;
7294                 flags_v = vxlan_v->flags;
7295         }
7296         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7297         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7298         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7299                  vxlan_m->protocol);
7300         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7301                  vxlan_v->protocol);
7302 }
7303
7304 /**
7305  * Add Geneve item to matcher and to the value.
7306  *
7307  * @param[in, out] matcher
7308  *   Flow matcher.
7309  * @param[in, out] key
7310  *   Flow matcher value.
7311  * @param[in] item
7312  *   Flow pattern to translate.
7313  * @param[in] inner
7314  *   Item is inner pattern.
7315  */
7316
7317 static void
7318 flow_dv_translate_item_geneve(void *matcher, void *key,
7319                               const struct rte_flow_item *item, int inner)
7320 {
7321         const struct rte_flow_item_geneve *geneve_m = item->mask;
7322         const struct rte_flow_item_geneve *geneve_v = item->spec;
7323         void *headers_m;
7324         void *headers_v;
7325         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7326         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7327         uint16_t dport;
7328         uint16_t gbhdr_m;
7329         uint16_t gbhdr_v;
7330         char *vni_m;
7331         char *vni_v;
7332         size_t size, i;
7333
7334         if (inner) {
7335                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7336                                          inner_headers);
7337                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7338         } else {
7339                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7340                                          outer_headers);
7341                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7342         }
7343         dport = MLX5_UDP_PORT_GENEVE;
7344         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7345                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7346                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7347         }
7348         if (!geneve_v)
7349                 return;
7350         if (!geneve_m)
7351                 geneve_m = &rte_flow_item_geneve_mask;
7352         size = sizeof(geneve_m->vni);
7353         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7354         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7355         memcpy(vni_m, geneve_m->vni, size);
7356         for (i = 0; i < size; ++i)
7357                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7358         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7359                  rte_be_to_cpu_16(geneve_m->protocol));
7360         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7361                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7362         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7363         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7364         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7365                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7366         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7367                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7368         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7369                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7370         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7371                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7372                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7373 }
7374
7375 /**
7376  * Create Geneve TLV option resource.
7377  *
7378  * @param dev[in, out]
7379  *   Pointer to rte_eth_dev structure.
7380  * @param[in, out] tag_be24
7381  *   Tag value in big endian then R-shift 8.
7382  * @parm[in, out] dev_flow
7383  *   Pointer to the dev_flow.
7384  * @param[out] error
7385  *   pointer to error structure.
7386  *
7387  * @return
7388  *   0 on success otherwise -errno and errno is set.
7389  */
7390
7391 int
7392 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
7393                                              const struct rte_flow_item *item,
7394                                              struct rte_flow_error *error)
7395 {
7396         struct mlx5_priv *priv = dev->data->dev_private;
7397         struct mlx5_dev_ctx_shared *sh = priv->sh;
7398         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
7399                         sh->geneve_tlv_option_resource;
7400         struct mlx5_devx_obj *obj;
7401         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7402         int ret = 0;
7403
7404         if (!geneve_opt_v)
7405                 return -1;
7406         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
7407         if (geneve_opt_resource != NULL) {
7408                 if (geneve_opt_resource->option_class ==
7409                         geneve_opt_v->option_class &&
7410                         geneve_opt_resource->option_type ==
7411                         geneve_opt_v->option_type &&
7412                         geneve_opt_resource->length ==
7413                         geneve_opt_v->option_len) {
7414                         /* We already have GENVE TLV option obj allocated. */
7415                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
7416                                            __ATOMIC_RELAXED);
7417                 } else {
7418                         ret = rte_flow_error_set(error, ENOMEM,
7419                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7420                                 "Only one GENEVE TLV option supported");
7421                         goto exit;
7422                 }
7423         } else {
7424                 /* Create a GENEVE TLV object and resource. */
7425                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
7426                                 geneve_opt_v->option_class,
7427                                 geneve_opt_v->option_type,
7428                                 geneve_opt_v->option_len);
7429                 if (!obj) {
7430                         ret = rte_flow_error_set(error, ENODATA,
7431                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7432                                 "Failed to create GENEVE TLV Devx object");
7433                         goto exit;
7434                 }
7435                 sh->geneve_tlv_option_resource =
7436                                 mlx5_malloc(MLX5_MEM_ZERO,
7437                                                 sizeof(*geneve_opt_resource),
7438                                                 0, SOCKET_ID_ANY);
7439                 if (!sh->geneve_tlv_option_resource) {
7440                         claim_zero(mlx5_devx_cmd_destroy(obj));
7441                         ret = rte_flow_error_set(error, ENOMEM,
7442                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7443                                 "GENEVE TLV object memory allocation failed");
7444                         goto exit;
7445                 }
7446                 geneve_opt_resource = sh->geneve_tlv_option_resource;
7447                 geneve_opt_resource->obj = obj;
7448                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
7449                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
7450                 geneve_opt_resource->length = geneve_opt_v->option_len;
7451                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
7452                                 __ATOMIC_RELAXED);
7453         }
7454 exit:
7455         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
7456         return ret;
7457 }
7458
7459 /**
7460  * Add Geneve TLV option item to matcher.
7461  *
7462  * @param[in, out] dev
7463  *   Pointer to rte_eth_dev structure.
7464  * @param[in, out] matcher
7465  *   Flow matcher.
7466  * @param[in, out] key
7467  *   Flow matcher value.
7468  * @param[in] item
7469  *   Flow pattern to translate.
7470  * @param[out] error
7471  *   Pointer to error structure.
7472  */
7473 static int
7474 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
7475                                   void *key, const struct rte_flow_item *item,
7476                                   struct rte_flow_error *error)
7477 {
7478         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
7479         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
7480         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7481         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7482         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7483                         misc_parameters_3);
7484         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7485         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
7486         int ret = 0;
7487
7488         if (!geneve_opt_v)
7489                 return -1;
7490         if (!geneve_opt_m)
7491                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
7492         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
7493                                                            error);
7494         if (ret) {
7495                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
7496                 return ret;
7497         }
7498         /*
7499          * Set the option length in GENEVE header if not requested.
7500          * The GENEVE TLV option length is expressed by the option length field
7501          * in the GENEVE header.
7502          * If the option length was not requested but the GENEVE TLV option item
7503          * is present we set the option length field implicitly.
7504          */
7505         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
7506                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7507                          MLX5_GENEVE_OPTLEN_MASK);
7508                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7509                          geneve_opt_v->option_len + 1);
7510         }
7511         /* Set the data. */
7512         if (geneve_opt_v->data) {
7513                 memcpy(&opt_data_key, geneve_opt_v->data,
7514                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7515                                 sizeof(opt_data_key)));
7516                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7517                                 sizeof(opt_data_key));
7518                 memcpy(&opt_data_mask, geneve_opt_m->data,
7519                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
7520                                 sizeof(opt_data_mask)));
7521                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
7522                                 sizeof(opt_data_mask));
7523                 MLX5_SET(fte_match_set_misc3, misc3_m,
7524                                 geneve_tlv_option_0_data,
7525                                 rte_be_to_cpu_32(opt_data_mask));
7526                 MLX5_SET(fte_match_set_misc3, misc3_v,
7527                                 geneve_tlv_option_0_data,
7528                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
7529         }
7530         return ret;
7531 }
7532
7533 /**
7534  * Add MPLS item to matcher and to the value.
7535  *
7536  * @param[in, out] matcher
7537  *   Flow matcher.
7538  * @param[in, out] key
7539  *   Flow matcher value.
7540  * @param[in] item
7541  *   Flow pattern to translate.
7542  * @param[in] prev_layer
7543  *   The protocol layer indicated in previous item.
7544  * @param[in] inner
7545  *   Item is inner pattern.
7546  */
7547 static void
7548 flow_dv_translate_item_mpls(void *matcher, void *key,
7549                             const struct rte_flow_item *item,
7550                             uint64_t prev_layer,
7551                             int inner)
7552 {
7553         const uint32_t *in_mpls_m = item->mask;
7554         const uint32_t *in_mpls_v = item->spec;
7555         uint32_t *out_mpls_m = 0;
7556         uint32_t *out_mpls_v = 0;
7557         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7558         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7559         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7560                                      misc_parameters_2);
7561         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7562         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7563         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7564
7565         switch (prev_layer) {
7566         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7567                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7568                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7569                          MLX5_UDP_PORT_MPLS);
7570                 break;
7571         case MLX5_FLOW_LAYER_GRE:
7572                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7573                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7574                          RTE_ETHER_TYPE_MPLS);
7575                 break;
7576         default:
7577                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7578                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7579                          IPPROTO_MPLS);
7580                 break;
7581         }
7582         if (!in_mpls_v)
7583                 return;
7584         if (!in_mpls_m)
7585                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7586         switch (prev_layer) {
7587         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7588                 out_mpls_m =
7589                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7590                                                  outer_first_mpls_over_udp);
7591                 out_mpls_v =
7592                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7593                                                  outer_first_mpls_over_udp);
7594                 break;
7595         case MLX5_FLOW_LAYER_GRE:
7596                 out_mpls_m =
7597                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7598                                                  outer_first_mpls_over_gre);
7599                 out_mpls_v =
7600                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7601                                                  outer_first_mpls_over_gre);
7602                 break;
7603         default:
7604                 /* Inner MPLS not over GRE is not supported. */
7605                 if (!inner) {
7606                         out_mpls_m =
7607                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7608                                                          misc2_m,
7609                                                          outer_first_mpls);
7610                         out_mpls_v =
7611                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7612                                                          misc2_v,
7613                                                          outer_first_mpls);
7614                 }
7615                 break;
7616         }
7617         if (out_mpls_m && out_mpls_v) {
7618                 *out_mpls_m = *in_mpls_m;
7619                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7620         }
7621 }
7622
7623 /**
7624  * Add metadata register item to matcher
7625  *
7626  * @param[in, out] matcher
7627  *   Flow matcher.
7628  * @param[in, out] key
7629  *   Flow matcher value.
7630  * @param[in] reg_type
7631  *   Type of device metadata register
7632  * @param[in] value
7633  *   Register value
7634  * @param[in] mask
7635  *   Register mask
7636  */
7637 static void
7638 flow_dv_match_meta_reg(void *matcher, void *key,
7639                        enum modify_reg reg_type,
7640                        uint32_t data, uint32_t mask)
7641 {
7642         void *misc2_m =
7643                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7644         void *misc2_v =
7645                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7646         uint32_t temp;
7647
7648         data &= mask;
7649         switch (reg_type) {
7650         case REG_A:
7651                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7652                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7653                 break;
7654         case REG_B:
7655                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7656                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7657                 break;
7658         case REG_C_0:
7659                 /*
7660                  * The metadata register C0 field might be divided into
7661                  * source vport index and META item value, we should set
7662                  * this field according to specified mask, not as whole one.
7663                  */
7664                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7665                 temp |= mask;
7666                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7667                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7668                 temp &= ~mask;
7669                 temp |= data;
7670                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7671                 break;
7672         case REG_C_1:
7673                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7674                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7675                 break;
7676         case REG_C_2:
7677                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7678                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7679                 break;
7680         case REG_C_3:
7681                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7682                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7683                 break;
7684         case REG_C_4:
7685                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7686                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7687                 break;
7688         case REG_C_5:
7689                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7690                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7691                 break;
7692         case REG_C_6:
7693                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7694                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7695                 break;
7696         case REG_C_7:
7697                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7698                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7699                 break;
7700         default:
7701                 MLX5_ASSERT(false);
7702                 break;
7703         }
7704 }
7705
7706 /**
7707  * Add MARK item to matcher
7708  *
7709  * @param[in] dev
7710  *   The device to configure through.
7711  * @param[in, out] matcher
7712  *   Flow matcher.
7713  * @param[in, out] key
7714  *   Flow matcher value.
7715  * @param[in] item
7716  *   Flow pattern to translate.
7717  */
7718 static void
7719 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7720                             void *matcher, void *key,
7721                             const struct rte_flow_item *item)
7722 {
7723         struct mlx5_priv *priv = dev->data->dev_private;
7724         const struct rte_flow_item_mark *mark;
7725         uint32_t value;
7726         uint32_t mask;
7727
7728         mark = item->mask ? (const void *)item->mask :
7729                             &rte_flow_item_mark_mask;
7730         mask = mark->id & priv->sh->dv_mark_mask;
7731         mark = (const void *)item->spec;
7732         MLX5_ASSERT(mark);
7733         value = mark->id & priv->sh->dv_mark_mask & mask;
7734         if (mask) {
7735                 enum modify_reg reg;
7736
7737                 /* Get the metadata register index for the mark. */
7738                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7739                 MLX5_ASSERT(reg > 0);
7740                 if (reg == REG_C_0) {
7741                         struct mlx5_priv *priv = dev->data->dev_private;
7742                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7743                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7744
7745                         mask &= msk_c0;
7746                         mask <<= shl_c0;
7747                         value <<= shl_c0;
7748                 }
7749                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7750         }
7751 }
7752
7753 /**
7754  * Add META item to matcher
7755  *
7756  * @param[in] dev
7757  *   The devich to configure through.
7758  * @param[in, out] matcher
7759  *   Flow matcher.
7760  * @param[in, out] key
7761  *   Flow matcher value.
7762  * @param[in] attr
7763  *   Attributes of flow that includes this item.
7764  * @param[in] item
7765  *   Flow pattern to translate.
7766  */
7767 static void
7768 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7769                             void *matcher, void *key,
7770                             const struct rte_flow_attr *attr,
7771                             const struct rte_flow_item *item)
7772 {
7773         const struct rte_flow_item_meta *meta_m;
7774         const struct rte_flow_item_meta *meta_v;
7775
7776         meta_m = (const void *)item->mask;
7777         if (!meta_m)
7778                 meta_m = &rte_flow_item_meta_mask;
7779         meta_v = (const void *)item->spec;
7780         if (meta_v) {
7781                 int reg;
7782                 uint32_t value = meta_v->data;
7783                 uint32_t mask = meta_m->data;
7784
7785                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7786                 if (reg < 0)
7787                         return;
7788                 MLX5_ASSERT(reg != REG_NON);
7789                 /*
7790                  * In datapath code there is no endianness
7791                  * coversions for perfromance reasons, all
7792                  * pattern conversions are done in rte_flow.
7793                  */
7794                 value = rte_cpu_to_be_32(value);
7795                 mask = rte_cpu_to_be_32(mask);
7796                 if (reg == REG_C_0) {
7797                         struct mlx5_priv *priv = dev->data->dev_private;
7798                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7799                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7800 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7801                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7802
7803                         value >>= shr_c0;
7804                         mask >>= shr_c0;
7805 #endif
7806                         value <<= shl_c0;
7807                         mask <<= shl_c0;
7808                         MLX5_ASSERT(msk_c0);
7809                         MLX5_ASSERT(!(~msk_c0 & mask));
7810                 }
7811                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7812         }
7813 }
7814
7815 /**
7816  * Add vport metadata Reg C0 item to matcher
7817  *
7818  * @param[in, out] matcher
7819  *   Flow matcher.
7820  * @param[in, out] key
7821  *   Flow matcher value.
7822  * @param[in] reg
7823  *   Flow pattern to translate.
7824  */
7825 static void
7826 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7827                                   uint32_t value, uint32_t mask)
7828 {
7829         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7830 }
7831
7832 /**
7833  * Add tag item to matcher
7834  *
7835  * @param[in] dev
7836  *   The devich to configure through.
7837  * @param[in, out] matcher
7838  *   Flow matcher.
7839  * @param[in, out] key
7840  *   Flow matcher value.
7841  * @param[in] item
7842  *   Flow pattern to translate.
7843  */
7844 static void
7845 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7846                                 void *matcher, void *key,
7847                                 const struct rte_flow_item *item)
7848 {
7849         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7850         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7851         uint32_t mask, value;
7852
7853         MLX5_ASSERT(tag_v);
7854         value = tag_v->data;
7855         mask = tag_m ? tag_m->data : UINT32_MAX;
7856         if (tag_v->id == REG_C_0) {
7857                 struct mlx5_priv *priv = dev->data->dev_private;
7858                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7859                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7860
7861                 mask &= msk_c0;
7862                 mask <<= shl_c0;
7863                 value <<= shl_c0;
7864         }
7865         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7866 }
7867
7868 /**
7869  * Add TAG item to matcher
7870  *
7871  * @param[in] dev
7872  *   The devich to configure through.
7873  * @param[in, out] matcher
7874  *   Flow matcher.
7875  * @param[in, out] key
7876  *   Flow matcher value.
7877  * @param[in] item
7878  *   Flow pattern to translate.
7879  */
7880 static void
7881 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7882                            void *matcher, void *key,
7883                            const struct rte_flow_item *item)
7884 {
7885         const struct rte_flow_item_tag *tag_v = item->spec;
7886         const struct rte_flow_item_tag *tag_m = item->mask;
7887         enum modify_reg reg;
7888
7889         MLX5_ASSERT(tag_v);
7890         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7891         /* Get the metadata register index for the tag. */
7892         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7893         MLX5_ASSERT(reg > 0);
7894         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7895 }
7896
7897 /**
7898  * Add source vport match to the specified matcher.
7899  *
7900  * @param[in, out] matcher
7901  *   Flow matcher.
7902  * @param[in, out] key
7903  *   Flow matcher value.
7904  * @param[in] port
7905  *   Source vport value to match
7906  * @param[in] mask
7907  *   Mask
7908  */
7909 static void
7910 flow_dv_translate_item_source_vport(void *matcher, void *key,
7911                                     int16_t port, uint16_t mask)
7912 {
7913         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7914         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7915
7916         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7917         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7918 }
7919
7920 /**
7921  * Translate port-id item to eswitch match on  port-id.
7922  *
7923  * @param[in] dev
7924  *   The devich to configure through.
7925  * @param[in, out] matcher
7926  *   Flow matcher.
7927  * @param[in, out] key
7928  *   Flow matcher value.
7929  * @param[in] item
7930  *   Flow pattern to translate.
7931  * @param[in]
7932  *   Flow attributes.
7933  *
7934  * @return
7935  *   0 on success, a negative errno value otherwise.
7936  */
7937 static int
7938 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7939                                void *key, const struct rte_flow_item *item,
7940                                const struct rte_flow_attr *attr)
7941 {
7942         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7943         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7944         struct mlx5_priv *priv;
7945         uint16_t mask, id;
7946
7947         mask = pid_m ? pid_m->id : 0xffff;
7948         id = pid_v ? pid_v->id : dev->data->port_id;
7949         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7950         if (!priv)
7951                 return -rte_errno;
7952         /*
7953          * Translate to vport field or to metadata, depending on mode.
7954          * Kernel can use either misc.source_port or half of C0 metadata
7955          * register.
7956          */
7957         if (priv->vport_meta_mask) {
7958                 /*
7959                  * Provide the hint for SW steering library
7960                  * to insert the flow into ingress domain and
7961                  * save the extra vport match.
7962                  */
7963                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7964                     priv->pf_bond < 0 && attr->transfer)
7965                         flow_dv_translate_item_source_vport
7966                                 (matcher, key, priv->vport_id, mask);
7967                 else
7968                         flow_dv_translate_item_meta_vport
7969                                 (matcher, key,
7970                                  priv->vport_meta_tag,
7971                                  priv->vport_meta_mask);
7972         } else {
7973                 flow_dv_translate_item_source_vport(matcher, key,
7974                                                     priv->vport_id, mask);
7975         }
7976         return 0;
7977 }
7978
7979 /**
7980  * Add ICMP6 item to matcher and to the value.
7981  *
7982  * @param[in, out] matcher
7983  *   Flow matcher.
7984  * @param[in, out] key
7985  *   Flow matcher value.
7986  * @param[in] item
7987  *   Flow pattern to translate.
7988  * @param[in] inner
7989  *   Item is inner pattern.
7990  */
7991 static void
7992 flow_dv_translate_item_icmp6(void *matcher, void *key,
7993                               const struct rte_flow_item *item,
7994                               int inner)
7995 {
7996         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7997         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7998         void *headers_m;
7999         void *headers_v;
8000         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8001                                      misc_parameters_3);
8002         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8003         if (inner) {
8004                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8005                                          inner_headers);
8006                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8007         } else {
8008                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8009                                          outer_headers);
8010                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8011         }
8012         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8013         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8014         if (!icmp6_v)
8015                 return;
8016         if (!icmp6_m)
8017                 icmp6_m = &rte_flow_item_icmp6_mask;
8018         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8019         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8020                  icmp6_v->type & icmp6_m->type);
8021         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8022         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8023                  icmp6_v->code & icmp6_m->code);
8024 }
8025
8026 /**
8027  * Add ICMP item to matcher and to the value.
8028  *
8029  * @param[in, out] matcher
8030  *   Flow matcher.
8031  * @param[in, out] key
8032  *   Flow matcher value.
8033  * @param[in] item
8034  *   Flow pattern to translate.
8035  * @param[in] inner
8036  *   Item is inner pattern.
8037  */
8038 static void
8039 flow_dv_translate_item_icmp(void *matcher, void *key,
8040                             const struct rte_flow_item *item,
8041                             int inner)
8042 {
8043         const struct rte_flow_item_icmp *icmp_m = item->mask;
8044         const struct rte_flow_item_icmp *icmp_v = item->spec;
8045         uint32_t icmp_header_data_m = 0;
8046         uint32_t icmp_header_data_v = 0;
8047         void *headers_m;
8048         void *headers_v;
8049         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8050                                      misc_parameters_3);
8051         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8052         if (inner) {
8053                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8054                                          inner_headers);
8055                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8056         } else {
8057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8058                                          outer_headers);
8059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8060         }
8061         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8062         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8063         if (!icmp_v)
8064                 return;
8065         if (!icmp_m)
8066                 icmp_m = &rte_flow_item_icmp_mask;
8067         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8068                  icmp_m->hdr.icmp_type);
8069         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8070                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8071         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8072                  icmp_m->hdr.icmp_code);
8073         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8074                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8075         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8076         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8077         if (icmp_header_data_m) {
8078                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8079                 icmp_header_data_v |=
8080                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8081                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8082                          icmp_header_data_m);
8083                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8084                          icmp_header_data_v & icmp_header_data_m);
8085         }
8086 }
8087
8088 /**
8089  * Add GTP item to matcher and to the value.
8090  *
8091  * @param[in, out] matcher
8092  *   Flow matcher.
8093  * @param[in, out] key
8094  *   Flow matcher value.
8095  * @param[in] item
8096  *   Flow pattern to translate.
8097  * @param[in] inner
8098  *   Item is inner pattern.
8099  */
8100 static void
8101 flow_dv_translate_item_gtp(void *matcher, void *key,
8102                            const struct rte_flow_item *item, int inner)
8103 {
8104         const struct rte_flow_item_gtp *gtp_m = item->mask;
8105         const struct rte_flow_item_gtp *gtp_v = item->spec;
8106         void *headers_m;
8107         void *headers_v;
8108         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8109                                      misc_parameters_3);
8110         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8111         uint16_t dport = RTE_GTPU_UDP_PORT;
8112
8113         if (inner) {
8114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8115                                          inner_headers);
8116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8117         } else {
8118                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8119                                          outer_headers);
8120                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8121         }
8122         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8123                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8124                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8125         }
8126         if (!gtp_v)
8127                 return;
8128         if (!gtp_m)
8129                 gtp_m = &rte_flow_item_gtp_mask;
8130         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8131                  gtp_m->v_pt_rsv_flags);
8132         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8133                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8134         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8135         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8136                  gtp_v->msg_type & gtp_m->msg_type);
8137         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8138                  rte_be_to_cpu_32(gtp_m->teid));
8139         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8140                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8141 }
8142
8143 /**
8144  * Add GTP PSC item to matcher.
8145  *
8146  * @param[in, out] matcher
8147  *   Flow matcher.
8148  * @param[in, out] key
8149  *   Flow matcher value.
8150  * @param[in] item
8151  *   Flow pattern to translate.
8152  */
8153 static int
8154 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8155                                const struct rte_flow_item *item)
8156 {
8157         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8158         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8159         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8160                         misc_parameters_3);
8161         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8162         union {
8163                 uint32_t w32;
8164                 struct {
8165                         uint16_t seq_num;
8166                         uint8_t npdu_num;
8167                         uint8_t next_ext_header_type;
8168                 };
8169         } dw_2;
8170         uint8_t gtp_flags;
8171
8172         /* Always set E-flag match on one, regardless of GTP item settings. */
8173         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8174         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8175         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8176         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8177         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8178         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8179         /*Set next extension header type. */
8180         dw_2.seq_num = 0;
8181         dw_2.npdu_num = 0;
8182         dw_2.next_ext_header_type = 0xff;
8183         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8184                  rte_cpu_to_be_32(dw_2.w32));
8185         dw_2.seq_num = 0;
8186         dw_2.npdu_num = 0;
8187         dw_2.next_ext_header_type = 0x85;
8188         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8189                  rte_cpu_to_be_32(dw_2.w32));
8190         if (gtp_psc_v) {
8191                 union {
8192                         uint32_t w32;
8193                         struct {
8194                                 uint8_t len;
8195                                 uint8_t type_flags;
8196                                 uint8_t qfi;
8197                                 uint8_t reserved;
8198                         };
8199                 } dw_0;
8200
8201                 /*Set extension header PDU type and Qos. */
8202                 if (!gtp_psc_m)
8203                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8204                 dw_0.w32 = 0;
8205                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8206                 dw_0.qfi = gtp_psc_m->qfi;
8207                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8208                          rte_cpu_to_be_32(dw_0.w32));
8209                 dw_0.w32 = 0;
8210                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8211                                                         gtp_psc_m->pdu_type);
8212                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8213                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8214                          rte_cpu_to_be_32(dw_0.w32));
8215         }
8216         return 0;
8217 }
8218
8219 /**
8220  * Add eCPRI item to matcher and to the value.
8221  *
8222  * @param[in] dev
8223  *   The devich to configure through.
8224  * @param[in, out] matcher
8225  *   Flow matcher.
8226  * @param[in, out] key
8227  *   Flow matcher value.
8228  * @param[in] item
8229  *   Flow pattern to translate.
8230  * @param[in] samples
8231  *   Sample IDs to be used in the matching.
8232  */
8233 static void
8234 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
8235                              void *key, const struct rte_flow_item *item)
8236 {
8237         struct mlx5_priv *priv = dev->data->dev_private;
8238         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
8239         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
8240         struct rte_ecpri_common_hdr common;
8241         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
8242                                      misc_parameters_4);
8243         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
8244         uint32_t *samples;
8245         void *dw_m;
8246         void *dw_v;
8247
8248         if (!ecpri_v)
8249                 return;
8250         if (!ecpri_m)
8251                 ecpri_m = &rte_flow_item_ecpri_mask;
8252         /*
8253          * Maximal four DW samples are supported in a single matching now.
8254          * Two are used now for a eCPRI matching:
8255          * 1. Type: one byte, mask should be 0x00ff0000 in network order
8256          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
8257          *    if any.
8258          */
8259         if (!ecpri_m->hdr.common.u32)
8260                 return;
8261         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
8262         /* Need to take the whole DW as the mask to fill the entry. */
8263         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8264                             prog_sample_field_value_0);
8265         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8266                             prog_sample_field_value_0);
8267         /* Already big endian (network order) in the header. */
8268         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
8269         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
8270         /* Sample#0, used for matching type, offset 0. */
8271         MLX5_SET(fte_match_set_misc4, misc4_m,
8272                  prog_sample_field_id_0, samples[0]);
8273         /* It makes no sense to set the sample ID in the mask field. */
8274         MLX5_SET(fte_match_set_misc4, misc4_v,
8275                  prog_sample_field_id_0, samples[0]);
8276         /*
8277          * Checking if message body part needs to be matched.
8278          * Some wildcard rules only matching type field should be supported.
8279          */
8280         if (ecpri_m->hdr.dummy[0]) {
8281                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
8282                 switch (common.type) {
8283                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
8284                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
8285                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
8286                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
8287                                             prog_sample_field_value_1);
8288                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
8289                                             prog_sample_field_value_1);
8290                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
8291                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
8292                                             ecpri_m->hdr.dummy[0];
8293                         /* Sample#1, to match message body, offset 4. */
8294                         MLX5_SET(fte_match_set_misc4, misc4_m,
8295                                  prog_sample_field_id_1, samples[1]);
8296                         MLX5_SET(fte_match_set_misc4, misc4_v,
8297                                  prog_sample_field_id_1, samples[1]);
8298                         break;
8299                 default:
8300                         /* Others, do not match any sample ID. */
8301                         break;
8302                 }
8303         }
8304 }
8305
8306 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
8307
8308 #define HEADER_IS_ZERO(match_criteria, headers)                              \
8309         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
8310                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
8311
8312 /**
8313  * Calculate flow matcher enable bitmap.
8314  *
8315  * @param match_criteria
8316  *   Pointer to flow matcher criteria.
8317  *
8318  * @return
8319  *   Bitmap of enabled fields.
8320  */
8321 static uint8_t
8322 flow_dv_matcher_enable(uint32_t *match_criteria)
8323 {
8324         uint8_t match_criteria_enable;
8325
8326         match_criteria_enable =
8327                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
8328                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
8329         match_criteria_enable |=
8330                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
8331                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
8332         match_criteria_enable |=
8333                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
8334                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
8335         match_criteria_enable |=
8336                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
8337                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8338         match_criteria_enable |=
8339                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
8340                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
8341         match_criteria_enable |=
8342                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
8343                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
8344         return match_criteria_enable;
8345 }
8346
8347 struct mlx5_hlist_entry *
8348 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
8349 {
8350         struct mlx5_dev_ctx_shared *sh = list->ctx;
8351         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8352         struct rte_eth_dev *dev = ctx->dev;
8353         struct mlx5_flow_tbl_data_entry *tbl_data;
8354         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
8355         struct rte_flow_error *error = ctx->error;
8356         union mlx5_flow_tbl_key key = { .v64 = key64 };
8357         struct mlx5_flow_tbl_resource *tbl;
8358         void *domain;
8359         uint32_t idx = 0;
8360         int ret;
8361
8362         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8363         if (!tbl_data) {
8364                 rte_flow_error_set(error, ENOMEM,
8365                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8366                                    NULL,
8367                                    "cannot allocate flow table data entry");
8368                 return NULL;
8369         }
8370         tbl_data->idx = idx;
8371         tbl_data->tunnel = tt_prm->tunnel;
8372         tbl_data->group_id = tt_prm->group_id;
8373         tbl_data->external = !!tt_prm->external;
8374         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8375         tbl_data->is_egress = !!key.direction;
8376         tbl_data->is_transfer = !!key.domain;
8377         tbl_data->dummy = !!key.dummy;
8378         tbl_data->table_id = key.table_id;
8379         tbl = &tbl_data->tbl;
8380         if (key.dummy)
8381                 return &tbl_data->entry;
8382         if (key.domain)
8383                 domain = sh->fdb_domain;
8384         else if (key.direction)
8385                 domain = sh->tx_domain;
8386         else
8387                 domain = sh->rx_domain;
8388         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8389         if (ret) {
8390                 rte_flow_error_set(error, ENOMEM,
8391                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8392                                    NULL, "cannot create flow table object");
8393                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8394                 return NULL;
8395         }
8396         if (key.table_id) {
8397                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8398                                         (tbl->obj, &tbl_data->jump.action);
8399                 if (ret) {
8400                         rte_flow_error_set(error, ENOMEM,
8401                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8402                                            NULL,
8403                                            "cannot create flow jump action");
8404                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8405                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8406                         return NULL;
8407                 }
8408         }
8409         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8410               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8411               key.table_id);
8412         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8413                              flow_dv_matcher_create_cb,
8414                              flow_dv_matcher_match_cb,
8415                              flow_dv_matcher_remove_cb);
8416         return &tbl_data->entry;
8417 }
8418
8419 int
8420 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8421                      struct mlx5_hlist_entry *entry, uint64_t key64,
8422                      void *cb_ctx __rte_unused)
8423 {
8424         struct mlx5_flow_tbl_data_entry *tbl_data =
8425                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8426         union mlx5_flow_tbl_key key = { .v64 = key64 };
8427
8428         return tbl_data->table_id != key.table_id ||
8429                tbl_data->dummy != key.dummy ||
8430                tbl_data->is_transfer != key.domain ||
8431                tbl_data->is_egress != key.direction;
8432 }
8433
8434 /**
8435  * Get a flow table.
8436  *
8437  * @param[in, out] dev
8438  *   Pointer to rte_eth_dev structure.
8439  * @param[in] table_id
8440  *   Table id to use.
8441  * @param[in] egress
8442  *   Direction of the table.
8443  * @param[in] transfer
8444  *   E-Switch or NIC flow.
8445  * @param[in] dummy
8446  *   Dummy entry for dv API.
8447  * @param[out] error
8448  *   pointer to error structure.
8449  *
8450  * @return
8451  *   Returns tables resource based on the index, NULL in case of failed.
8452  */
8453 struct mlx5_flow_tbl_resource *
8454 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8455                          uint32_t table_id, uint8_t egress,
8456                          uint8_t transfer,
8457                          bool external,
8458                          const struct mlx5_flow_tunnel *tunnel,
8459                          uint32_t group_id, uint8_t dummy,
8460                          struct rte_flow_error *error)
8461 {
8462         struct mlx5_priv *priv = dev->data->dev_private;
8463         union mlx5_flow_tbl_key table_key = {
8464                 {
8465                         .table_id = table_id,
8466                         .dummy = dummy,
8467                         .domain = !!transfer,
8468                         .direction = !!egress,
8469                 }
8470         };
8471         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8472                 .tunnel = tunnel,
8473                 .group_id = group_id,
8474                 .external = external,
8475         };
8476         struct mlx5_flow_cb_ctx ctx = {
8477                 .dev = dev,
8478                 .error = error,
8479                 .data = &tt_prm,
8480         };
8481         struct mlx5_hlist_entry *entry;
8482         struct mlx5_flow_tbl_data_entry *tbl_data;
8483
8484         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8485         if (!entry) {
8486                 rte_flow_error_set(error, ENOMEM,
8487                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8488                                    "cannot get table");
8489                 return NULL;
8490         }
8491         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8492                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8493         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8494         return &tbl_data->tbl;
8495 }
8496
8497 void
8498 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8499                       struct mlx5_hlist_entry *entry)
8500 {
8501         struct mlx5_dev_ctx_shared *sh = list->ctx;
8502         struct mlx5_flow_tbl_data_entry *tbl_data =
8503                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8504
8505         MLX5_ASSERT(entry && sh);
8506         if (tbl_data->jump.action)
8507                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8508         if (tbl_data->tbl.obj)
8509                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8510         if (tbl_data->tunnel_offload && tbl_data->external) {
8511                 struct mlx5_hlist_entry *he;
8512                 struct mlx5_hlist *tunnel_grp_hash;
8513                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8514                 union tunnel_tbl_key tunnel_key = {
8515                         .tunnel_id = tbl_data->tunnel ?
8516                                         tbl_data->tunnel->tunnel_id : 0,
8517                         .group = tbl_data->group_id
8518                 };
8519                 uint32_t table_id = tbl_data->table_id;
8520
8521                 tunnel_grp_hash = tbl_data->tunnel ?
8522                                         tbl_data->tunnel->groups :
8523                                         thub->groups;
8524                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8525                 if (he)
8526                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8527                 DRV_LOG(DEBUG,
8528                         "Table_id %u tunnel %u group %u released.",
8529                         table_id,
8530                         tbl_data->tunnel ?
8531                         tbl_data->tunnel->tunnel_id : 0,
8532                         tbl_data->group_id);
8533         }
8534         mlx5_cache_list_destroy(&tbl_data->matchers);
8535         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8536 }
8537
8538 /**
8539  * Release a flow table.
8540  *
8541  * @param[in] sh
8542  *   Pointer to device shared structure.
8543  * @param[in] tbl
8544  *   Table resource to be released.
8545  *
8546  * @return
8547  *   Returns 0 if table was released, else return 1;
8548  */
8549 static int
8550 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8551                              struct mlx5_flow_tbl_resource *tbl)
8552 {
8553         struct mlx5_flow_tbl_data_entry *tbl_data =
8554                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8555
8556         if (!tbl)
8557                 return 0;
8558         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8559 }
8560
8561 int
8562 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8563                          struct mlx5_cache_entry *entry, void *cb_ctx)
8564 {
8565         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8566         struct mlx5_flow_dv_matcher *ref = ctx->data;
8567         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8568                                                         entry);
8569
8570         return cur->crc != ref->crc ||
8571                cur->priority != ref->priority ||
8572                memcmp((const void *)cur->mask.buf,
8573                       (const void *)ref->mask.buf, ref->mask.size);
8574 }
8575
8576 struct mlx5_cache_entry *
8577 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8578                           struct mlx5_cache_entry *entry __rte_unused,
8579                           void *cb_ctx)
8580 {
8581         struct mlx5_dev_ctx_shared *sh = list->ctx;
8582         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8583         struct mlx5_flow_dv_matcher *ref = ctx->data;
8584         struct mlx5_flow_dv_matcher *cache;
8585         struct mlx5dv_flow_matcher_attr dv_attr = {
8586                 .type = IBV_FLOW_ATTR_NORMAL,
8587                 .match_mask = (void *)&ref->mask,
8588         };
8589         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8590                                                             typeof(*tbl), tbl);
8591         int ret;
8592
8593         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8594         if (!cache) {
8595                 rte_flow_error_set(ctx->error, ENOMEM,
8596                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8597                                    "cannot create matcher");
8598                 return NULL;
8599         }
8600         *cache = *ref;
8601         dv_attr.match_criteria_enable =
8602                 flow_dv_matcher_enable(cache->mask.buf);
8603         dv_attr.priority = ref->priority;
8604         if (tbl->is_egress)
8605                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8606         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8607                                                &cache->matcher_object);
8608         if (ret) {
8609                 mlx5_free(cache);
8610                 rte_flow_error_set(ctx->error, ENOMEM,
8611                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8612                                    "cannot create matcher");
8613                 return NULL;
8614         }
8615         return &cache->entry;
8616 }
8617
8618 /**
8619  * Register the flow matcher.
8620  *
8621  * @param[in, out] dev
8622  *   Pointer to rte_eth_dev structure.
8623  * @param[in, out] matcher
8624  *   Pointer to flow matcher.
8625  * @param[in, out] key
8626  *   Pointer to flow table key.
8627  * @parm[in, out] dev_flow
8628  *   Pointer to the dev_flow.
8629  * @param[out] error
8630  *   pointer to error structure.
8631  *
8632  * @return
8633  *   0 on success otherwise -errno and errno is set.
8634  */
8635 static int
8636 flow_dv_matcher_register(struct rte_eth_dev *dev,
8637                          struct mlx5_flow_dv_matcher *ref,
8638                          union mlx5_flow_tbl_key *key,
8639                          struct mlx5_flow *dev_flow,
8640                          const struct mlx5_flow_tunnel *tunnel,
8641                          uint32_t group_id,
8642                          struct rte_flow_error *error)
8643 {
8644         struct mlx5_cache_entry *entry;
8645         struct mlx5_flow_dv_matcher *cache;
8646         struct mlx5_flow_tbl_resource *tbl;
8647         struct mlx5_flow_tbl_data_entry *tbl_data;
8648         struct mlx5_flow_cb_ctx ctx = {
8649                 .error = error,
8650                 .data = ref,
8651         };
8652
8653         /**
8654          * tunnel offload API requires this registration for cases when
8655          * tunnel match rule was inserted before tunnel set rule.
8656          */
8657         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8658                                        key->direction, key->domain,
8659                                        dev_flow->external, tunnel,
8660                                        group_id, 0, error);
8661         if (!tbl)
8662                 return -rte_errno;      /* No need to refill the error info */
8663         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8664         ref->tbl = tbl;
8665         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8666         if (!entry) {
8667                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8668                 return rte_flow_error_set(error, ENOMEM,
8669                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8670                                           "cannot allocate ref memory");
8671         }
8672         cache = container_of(entry, typeof(*cache), entry);
8673         dev_flow->handle->dvh.matcher = cache;
8674         return 0;
8675 }
8676
8677 struct mlx5_hlist_entry *
8678 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8679 {
8680         struct mlx5_dev_ctx_shared *sh = list->ctx;
8681         struct rte_flow_error *error = ctx;
8682         struct mlx5_flow_dv_tag_resource *entry;
8683         uint32_t idx = 0;
8684         int ret;
8685
8686         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8687         if (!entry) {
8688                 rte_flow_error_set(error, ENOMEM,
8689                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8690                                    "cannot allocate resource memory");
8691                 return NULL;
8692         }
8693         entry->idx = idx;
8694         entry->tag_id = key;
8695         ret = mlx5_flow_os_create_flow_action_tag(key,
8696                                                   &entry->action);
8697         if (ret) {
8698                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8699                 rte_flow_error_set(error, ENOMEM,
8700                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8701                                    NULL, "cannot create action");
8702                 return NULL;
8703         }
8704         return &entry->entry;
8705 }
8706
8707 int
8708 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8709                      struct mlx5_hlist_entry *entry, uint64_t key,
8710                      void *cb_ctx __rte_unused)
8711 {
8712         struct mlx5_flow_dv_tag_resource *tag =
8713                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8714
8715         return key != tag->tag_id;
8716 }
8717
8718 /**
8719  * Find existing tag resource or create and register a new one.
8720  *
8721  * @param dev[in, out]
8722  *   Pointer to rte_eth_dev structure.
8723  * @param[in, out] tag_be24
8724  *   Tag value in big endian then R-shift 8.
8725  * @parm[in, out] dev_flow
8726  *   Pointer to the dev_flow.
8727  * @param[out] error
8728  *   pointer to error structure.
8729  *
8730  * @return
8731  *   0 on success otherwise -errno and errno is set.
8732  */
8733 static int
8734 flow_dv_tag_resource_register
8735                         (struct rte_eth_dev *dev,
8736                          uint32_t tag_be24,
8737                          struct mlx5_flow *dev_flow,
8738                          struct rte_flow_error *error)
8739 {
8740         struct mlx5_priv *priv = dev->data->dev_private;
8741         struct mlx5_flow_dv_tag_resource *cache_resource;
8742         struct mlx5_hlist_entry *entry;
8743
8744         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8745         if (entry) {
8746                 cache_resource = container_of
8747                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8748                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8749                 dev_flow->dv.tag_resource = cache_resource;
8750                 return 0;
8751         }
8752         return -rte_errno;
8753 }
8754
8755 void
8756 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8757                       struct mlx5_hlist_entry *entry)
8758 {
8759         struct mlx5_dev_ctx_shared *sh = list->ctx;
8760         struct mlx5_flow_dv_tag_resource *tag =
8761                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8762
8763         MLX5_ASSERT(tag && sh && tag->action);
8764         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8765         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8766         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8767 }
8768
8769 /**
8770  * Release the tag.
8771  *
8772  * @param dev
8773  *   Pointer to Ethernet device.
8774  * @param tag_idx
8775  *   Tag index.
8776  *
8777  * @return
8778  *   1 while a reference on it exists, 0 when freed.
8779  */
8780 static int
8781 flow_dv_tag_release(struct rte_eth_dev *dev,
8782                     uint32_t tag_idx)
8783 {
8784         struct mlx5_priv *priv = dev->data->dev_private;
8785         struct mlx5_flow_dv_tag_resource *tag;
8786
8787         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8788         if (!tag)
8789                 return 0;
8790         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8791                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8792         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8793 }
8794
8795 /**
8796  * Translate port ID action to vport.
8797  *
8798  * @param[in] dev
8799  *   Pointer to rte_eth_dev structure.
8800  * @param[in] action
8801  *   Pointer to the port ID action.
8802  * @param[out] dst_port_id
8803  *   The target port ID.
8804  * @param[out] error
8805  *   Pointer to the error structure.
8806  *
8807  * @return
8808  *   0 on success, a negative errno value otherwise and rte_errno is set.
8809  */
8810 static int
8811 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8812                                  const struct rte_flow_action *action,
8813                                  uint32_t *dst_port_id,
8814                                  struct rte_flow_error *error)
8815 {
8816         uint32_t port;
8817         struct mlx5_priv *priv;
8818         const struct rte_flow_action_port_id *conf =
8819                         (const struct rte_flow_action_port_id *)action->conf;
8820
8821         port = conf->original ? dev->data->port_id : conf->id;
8822         priv = mlx5_port_to_eswitch_info(port, false);
8823         if (!priv)
8824                 return rte_flow_error_set(error, -rte_errno,
8825                                           RTE_FLOW_ERROR_TYPE_ACTION,
8826                                           NULL,
8827                                           "No eswitch info was found for port");
8828 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8829         /*
8830          * This parameter is transferred to
8831          * mlx5dv_dr_action_create_dest_ib_port().
8832          */
8833         *dst_port_id = priv->dev_port;
8834 #else
8835         /*
8836          * Legacy mode, no LAG configurations is supported.
8837          * This parameter is transferred to
8838          * mlx5dv_dr_action_create_dest_vport().
8839          */
8840         *dst_port_id = priv->vport_id;
8841 #endif
8842         return 0;
8843 }
8844
8845 /**
8846  * Create a counter with aging configuration.
8847  *
8848  * @param[in] dev
8849  *   Pointer to rte_eth_dev structure.
8850  * @param[out] count
8851  *   Pointer to the counter action configuration.
8852  * @param[in] age
8853  *   Pointer to the aging action configuration.
8854  *
8855  * @return
8856  *   Index to flow counter on success, 0 otherwise.
8857  */
8858 static uint32_t
8859 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8860                                 struct mlx5_flow *dev_flow,
8861                                 const struct rte_flow_action_count *count,
8862                                 const struct rte_flow_action_age *age)
8863 {
8864         uint32_t counter;
8865         struct mlx5_age_param *age_param;
8866
8867         if (count && count->shared)
8868                 counter = flow_dv_counter_get_shared(dev, count->id);
8869         else
8870                 counter = flow_dv_counter_alloc(dev, !!age);
8871         if (!counter || age == NULL)
8872                 return counter;
8873         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8874         age_param->context = age->context ? age->context :
8875                 (void *)(uintptr_t)(dev_flow->flow_idx);
8876         age_param->timeout = age->timeout;
8877         age_param->port_id = dev->data->port_id;
8878         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8879         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8880         return counter;
8881 }
8882
8883 /**
8884  * Add Tx queue matcher
8885  *
8886  * @param[in] dev
8887  *   Pointer to the dev struct.
8888  * @param[in, out] matcher
8889  *   Flow matcher.
8890  * @param[in, out] key
8891  *   Flow matcher value.
8892  * @param[in] item
8893  *   Flow pattern to translate.
8894  * @param[in] inner
8895  *   Item is inner pattern.
8896  */
8897 static void
8898 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8899                                 void *matcher, void *key,
8900                                 const struct rte_flow_item *item)
8901 {
8902         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8903         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8904         void *misc_m =
8905                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8906         void *misc_v =
8907                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8908         struct mlx5_txq_ctrl *txq;
8909         uint32_t queue;
8910
8911
8912         queue_m = (const void *)item->mask;
8913         if (!queue_m)
8914                 return;
8915         queue_v = (const void *)item->spec;
8916         if (!queue_v)
8917                 return;
8918         txq = mlx5_txq_get(dev, queue_v->queue);
8919         if (!txq)
8920                 return;
8921         queue = txq->obj->sq->id;
8922         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8923         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8924                  queue & queue_m->queue);
8925         mlx5_txq_release(dev, queue_v->queue);
8926 }
8927
8928 /**
8929  * Set the hash fields according to the @p flow information.
8930  *
8931  * @param[in] dev_flow
8932  *   Pointer to the mlx5_flow.
8933  * @param[in] rss_desc
8934  *   Pointer to the mlx5_flow_rss_desc.
8935  */
8936 static void
8937 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8938                        struct mlx5_flow_rss_desc *rss_desc)
8939 {
8940         uint64_t items = dev_flow->handle->layers;
8941         int rss_inner = 0;
8942         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8943
8944         dev_flow->hash_fields = 0;
8945 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8946         if (rss_desc->level >= 2) {
8947                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8948                 rss_inner = 1;
8949         }
8950 #endif
8951         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8952             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8953                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8954                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8955                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8956                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8957                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8958                         else
8959                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8960                 }
8961         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8962                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8963                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8964                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8965                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8966                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8967                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8968                         else
8969                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8970                 }
8971         }
8972         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8973             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8974                 if (rss_types & ETH_RSS_UDP) {
8975                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8976                                 dev_flow->hash_fields |=
8977                                                 IBV_RX_HASH_SRC_PORT_UDP;
8978                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8979                                 dev_flow->hash_fields |=
8980                                                 IBV_RX_HASH_DST_PORT_UDP;
8981                         else
8982                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8983                 }
8984         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8985                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8986                 if (rss_types & ETH_RSS_TCP) {
8987                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8988                                 dev_flow->hash_fields |=
8989                                                 IBV_RX_HASH_SRC_PORT_TCP;
8990                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8991                                 dev_flow->hash_fields |=
8992                                                 IBV_RX_HASH_DST_PORT_TCP;
8993                         else
8994                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8995                 }
8996         }
8997 }
8998
8999 /**
9000  * Prepare an Rx Hash queue.
9001  *
9002  * @param dev
9003  *   Pointer to Ethernet device.
9004  * @param[in] dev_flow
9005  *   Pointer to the mlx5_flow.
9006  * @param[in] rss_desc
9007  *   Pointer to the mlx5_flow_rss_desc.
9008  * @param[out] hrxq_idx
9009  *   Hash Rx queue index.
9010  *
9011  * @return
9012  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9013  */
9014 static struct mlx5_hrxq *
9015 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9016                      struct mlx5_flow *dev_flow,
9017                      struct mlx5_flow_rss_desc *rss_desc,
9018                      uint32_t *hrxq_idx)
9019 {
9020         struct mlx5_priv *priv = dev->data->dev_private;
9021         struct mlx5_flow_handle *dh = dev_flow->handle;
9022         struct mlx5_hrxq *hrxq;
9023
9024         MLX5_ASSERT(rss_desc->queue_num);
9025         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9026         rss_desc->hash_fields = dev_flow->hash_fields;
9027         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9028         rss_desc->shared_rss = 0;
9029         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9030         if (!*hrxq_idx)
9031                 return NULL;
9032         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9033                               *hrxq_idx);
9034         return hrxq;
9035 }
9036
9037 /**
9038  * Release sample sub action resource.
9039  *
9040  * @param[in, out] dev
9041  *   Pointer to rte_eth_dev structure.
9042  * @param[in] act_res
9043  *   Pointer to sample sub action resource.
9044  */
9045 static void
9046 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9047                                    struct mlx5_flow_sub_actions_idx *act_res)
9048 {
9049         if (act_res->rix_hrxq) {
9050                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9051                 act_res->rix_hrxq = 0;
9052         }
9053         if (act_res->rix_encap_decap) {
9054                 flow_dv_encap_decap_resource_release(dev,
9055                                                      act_res->rix_encap_decap);
9056                 act_res->rix_encap_decap = 0;
9057         }
9058         if (act_res->rix_port_id_action) {
9059                 flow_dv_port_id_action_resource_release(dev,
9060                                                 act_res->rix_port_id_action);
9061                 act_res->rix_port_id_action = 0;
9062         }
9063         if (act_res->rix_tag) {
9064                 flow_dv_tag_release(dev, act_res->rix_tag);
9065                 act_res->rix_tag = 0;
9066         }
9067         if (act_res->cnt) {
9068                 flow_dv_counter_free(dev, act_res->cnt);
9069                 act_res->cnt = 0;
9070         }
9071         if (act_res->rix_jump) {
9072                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9073                 act_res->rix_jump = 0;
9074         }
9075 }
9076
9077 int
9078 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9079                         struct mlx5_cache_entry *entry, void *cb_ctx)
9080 {
9081         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9082         struct rte_eth_dev *dev = ctx->dev;
9083         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9084         struct mlx5_flow_dv_sample_resource *cache_resource =
9085                         container_of(entry, typeof(*cache_resource), entry);
9086
9087         if (resource->ratio == cache_resource->ratio &&
9088             resource->ft_type == cache_resource->ft_type &&
9089             resource->ft_id == cache_resource->ft_id &&
9090             resource->set_action == cache_resource->set_action &&
9091             !memcmp((void *)&resource->sample_act,
9092                     (void *)&cache_resource->sample_act,
9093                     sizeof(struct mlx5_flow_sub_actions_list))) {
9094                 /*
9095                  * Existing sample action should release the prepared
9096                  * sub-actions reference counter.
9097                  */
9098                 flow_dv_sample_sub_actions_release(dev,
9099                                                 &resource->sample_idx);
9100                 return 0;
9101         }
9102         return 1;
9103 }
9104
9105 struct mlx5_cache_entry *
9106 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9107                          struct mlx5_cache_entry *entry __rte_unused,
9108                          void *cb_ctx)
9109 {
9110         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9111         struct rte_eth_dev *dev = ctx->dev;
9112         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9113         void **sample_dv_actions = resource->sub_actions;
9114         struct mlx5_flow_dv_sample_resource *cache_resource;
9115         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9116         struct mlx5_priv *priv = dev->data->dev_private;
9117         struct mlx5_dev_ctx_shared *sh = priv->sh;
9118         struct mlx5_flow_tbl_resource *tbl;
9119         uint32_t idx = 0;
9120         const uint32_t next_ft_step = 1;
9121         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9122         uint8_t is_egress = 0;
9123         uint8_t is_transfer = 0;
9124         struct rte_flow_error *error = ctx->error;
9125
9126         /* Register new sample resource. */
9127         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9128         if (!cache_resource) {
9129                 rte_flow_error_set(error, ENOMEM,
9130                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9131                                           NULL,
9132                                           "cannot allocate resource memory");
9133                 return NULL;
9134         }
9135         *cache_resource = *resource;
9136         /* Create normal path table level */
9137         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9138                 is_transfer = 1;
9139         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9140                 is_egress = 1;
9141         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9142                                         is_egress, is_transfer,
9143                                         true, NULL, 0, 0, error);
9144         if (!tbl) {
9145                 rte_flow_error_set(error, ENOMEM,
9146                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9147                                           NULL,
9148                                           "fail to create normal path table "
9149                                           "for sample");
9150                 goto error;
9151         }
9152         int ret;
9153
9154         cache_resource->normal_path_tbl = tbl;
9155         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9156                 ret = mlx5_flow_os_create_flow_action_default_miss
9157                         (&cache_resource->default_miss);
9158                 if (!ret) {
9159                         rte_flow_error_set(error, ENOMEM,
9160                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9161                                                 NULL,
9162                                                 "cannot create default miss "
9163                                                 "action");
9164                         goto error;
9165                 }
9166                 sample_dv_actions[resource->sample_act.actions_num++] =
9167                                                 cache_resource->default_miss;
9168         }
9169         /* Create a DR sample action */
9170         sampler_attr.sample_ratio = cache_resource->ratio;
9171         sampler_attr.default_next_table = tbl->obj;
9172         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9173         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9174                                                         &sample_dv_actions[0];
9175         sampler_attr.action = cache_resource->set_action;
9176         if (mlx5_os_flow_dr_create_flow_action_sampler
9177                         (&sampler_attr, &cache_resource->verbs_action)) {
9178                 rte_flow_error_set(error, ENOMEM,
9179                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9180                                         NULL, "cannot create sample action");
9181                 goto error;
9182         }
9183         cache_resource->idx = idx;
9184         cache_resource->dev = dev;
9185         return &cache_resource->entry;
9186 error:
9187         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
9188             cache_resource->default_miss)
9189                 claim_zero(mlx5_flow_os_destroy_flow_action
9190                                 (cache_resource->default_miss));
9191         else
9192                 flow_dv_sample_sub_actions_release(dev,
9193                                                    &cache_resource->sample_idx);
9194         if (cache_resource->normal_path_tbl)
9195                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9196                                 cache_resource->normal_path_tbl);
9197         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9198         return NULL;
9199
9200 }
9201
9202 /**
9203  * Find existing sample resource or create and register a new one.
9204  *
9205  * @param[in, out] dev
9206  *   Pointer to rte_eth_dev structure.
9207  * @param[in] resource
9208  *   Pointer to sample resource.
9209  * @parm[in, out] dev_flow
9210  *   Pointer to the dev_flow.
9211  * @param[out] error
9212  *   pointer to error structure.
9213  *
9214  * @return
9215  *   0 on success otherwise -errno and errno is set.
9216  */
9217 static int
9218 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9219                          struct mlx5_flow_dv_sample_resource *resource,
9220                          struct mlx5_flow *dev_flow,
9221                          struct rte_flow_error *error)
9222 {
9223         struct mlx5_flow_dv_sample_resource *cache_resource;
9224         struct mlx5_cache_entry *entry;
9225         struct mlx5_priv *priv = dev->data->dev_private;
9226         struct mlx5_flow_cb_ctx ctx = {
9227                 .dev = dev,
9228                 .error = error,
9229                 .data = resource,
9230         };
9231
9232         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
9233         if (!entry)
9234                 return -rte_errno;
9235         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9236         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
9237         dev_flow->dv.sample_res = cache_resource;
9238         return 0;
9239 }
9240
9241 int
9242 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
9243                             struct mlx5_cache_entry *entry, void *cb_ctx)
9244 {
9245         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9246         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9247         struct rte_eth_dev *dev = ctx->dev;
9248         struct mlx5_flow_dv_dest_array_resource *cache_resource =
9249                         container_of(entry, typeof(*cache_resource), entry);
9250         uint32_t idx = 0;
9251
9252         if (resource->num_of_dest == cache_resource->num_of_dest &&
9253             resource->ft_type == cache_resource->ft_type &&
9254             !memcmp((void *)cache_resource->sample_act,
9255                     (void *)resource->sample_act,
9256                    (resource->num_of_dest *
9257                    sizeof(struct mlx5_flow_sub_actions_list)))) {
9258                 /*
9259                  * Existing sample action should release the prepared
9260                  * sub-actions reference counter.
9261                  */
9262                 for (idx = 0; idx < resource->num_of_dest; idx++)
9263                         flow_dv_sample_sub_actions_release(dev,
9264                                         &resource->sample_idx[idx]);
9265                 return 0;
9266         }
9267         return 1;
9268 }
9269
9270 struct mlx5_cache_entry *
9271 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
9272                          struct mlx5_cache_entry *entry __rte_unused,
9273                          void *cb_ctx)
9274 {
9275         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9276         struct rte_eth_dev *dev = ctx->dev;
9277         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9278         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
9279         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
9280         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
9281         struct mlx5_priv *priv = dev->data->dev_private;
9282         struct mlx5_dev_ctx_shared *sh = priv->sh;
9283         struct mlx5_flow_sub_actions_list *sample_act;
9284         struct mlx5dv_dr_domain *domain;
9285         uint32_t idx = 0, res_idx = 0;
9286         struct rte_flow_error *error = ctx->error;
9287         uint64_t action_flags;
9288         int ret;
9289
9290         /* Register new destination array resource. */
9291         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
9292                                             &res_idx);
9293         if (!cache_resource) {
9294                 rte_flow_error_set(error, ENOMEM,
9295                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9296                                           NULL,
9297                                           "cannot allocate resource memory");
9298                 return NULL;
9299         }
9300         *cache_resource = *resource;
9301         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9302                 domain = sh->fdb_domain;
9303         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
9304                 domain = sh->rx_domain;
9305         else
9306                 domain = sh->tx_domain;
9307         for (idx = 0; idx < resource->num_of_dest; idx++) {
9308                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
9309                                  mlx5_malloc(MLX5_MEM_ZERO,
9310                                  sizeof(struct mlx5dv_dr_action_dest_attr),
9311                                  0, SOCKET_ID_ANY);
9312                 if (!dest_attr[idx]) {
9313                         rte_flow_error_set(error, ENOMEM,
9314                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9315                                            NULL,
9316                                            "cannot allocate resource memory");
9317                         goto error;
9318                 }
9319                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
9320                 sample_act = &resource->sample_act[idx];
9321                 action_flags = sample_act->action_flags;
9322                 switch (action_flags) {
9323                 case MLX5_FLOW_ACTION_QUEUE:
9324                         dest_attr[idx]->dest = sample_act->dr_queue_action;
9325                         break;
9326                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
9327                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
9328                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
9329                         dest_attr[idx]->dest_reformat->reformat =
9330                                         sample_act->dr_encap_action;
9331                         dest_attr[idx]->dest_reformat->dest =
9332                                         sample_act->dr_port_id_action;
9333                         break;
9334                 case MLX5_FLOW_ACTION_PORT_ID:
9335                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
9336                         break;
9337                 case MLX5_FLOW_ACTION_JUMP:
9338                         dest_attr[idx]->dest = sample_act->dr_jump_action;
9339                         break;
9340                 default:
9341                         rte_flow_error_set(error, EINVAL,
9342                                            RTE_FLOW_ERROR_TYPE_ACTION,
9343                                            NULL,
9344                                            "unsupported actions type");
9345                         goto error;
9346                 }
9347         }
9348         /* create a dest array actioin */
9349         ret = mlx5_os_flow_dr_create_flow_action_dest_array
9350                                                 (domain,
9351                                                  cache_resource->num_of_dest,
9352                                                  dest_attr,
9353                                                  &cache_resource->action);
9354         if (ret) {
9355                 rte_flow_error_set(error, ENOMEM,
9356                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9357                                    NULL,
9358                                    "cannot create destination array action");
9359                 goto error;
9360         }
9361         cache_resource->idx = res_idx;
9362         cache_resource->dev = dev;
9363         for (idx = 0; idx < resource->num_of_dest; idx++)
9364                 mlx5_free(dest_attr[idx]);
9365         return &cache_resource->entry;
9366 error:
9367         for (idx = 0; idx < resource->num_of_dest; idx++) {
9368                 struct mlx5_flow_sub_actions_idx *act_res =
9369                                         &cache_resource->sample_idx[idx];
9370                 if (act_res->rix_hrxq &&
9371                     !mlx5_hrxq_release(dev,
9372                                 act_res->rix_hrxq))
9373                         act_res->rix_hrxq = 0;
9374                 if (act_res->rix_encap_decap &&
9375                         !flow_dv_encap_decap_resource_release(dev,
9376                                 act_res->rix_encap_decap))
9377                         act_res->rix_encap_decap = 0;
9378                 if (act_res->rix_port_id_action &&
9379                         !flow_dv_port_id_action_resource_release(dev,
9380                                 act_res->rix_port_id_action))
9381                         act_res->rix_port_id_action = 0;
9382                 if (act_res->rix_jump &&
9383                         !flow_dv_jump_tbl_resource_release(dev,
9384                                 act_res->rix_jump))
9385                         act_res->rix_jump = 0;
9386                 if (dest_attr[idx])
9387                         mlx5_free(dest_attr[idx]);
9388         }
9389
9390         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9391         return NULL;
9392 }
9393
9394 /**
9395  * Find existing destination array resource or create and register a new one.
9396  *
9397  * @param[in, out] dev
9398  *   Pointer to rte_eth_dev structure.
9399  * @param[in] resource
9400  *   Pointer to destination array resource.
9401  * @parm[in, out] dev_flow
9402  *   Pointer to the dev_flow.
9403  * @param[out] error
9404  *   pointer to error structure.
9405  *
9406  * @return
9407  *   0 on success otherwise -errno and errno is set.
9408  */
9409 static int
9410 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9411                          struct mlx5_flow_dv_dest_array_resource *resource,
9412                          struct mlx5_flow *dev_flow,
9413                          struct rte_flow_error *error)
9414 {
9415         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9416         struct mlx5_priv *priv = dev->data->dev_private;
9417         struct mlx5_cache_entry *entry;
9418         struct mlx5_flow_cb_ctx ctx = {
9419                 .dev = dev,
9420                 .error = error,
9421                 .data = resource,
9422         };
9423
9424         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9425         if (!entry)
9426                 return -rte_errno;
9427         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9428         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9429         dev_flow->dv.dest_array_res = cache_resource;
9430         return 0;
9431 }
9432
9433 /**
9434  * Convert Sample action to DV specification.
9435  *
9436  * @param[in] dev
9437  *   Pointer to rte_eth_dev structure.
9438  * @param[in] action
9439  *   Pointer to sample action structure.
9440  * @param[in, out] dev_flow
9441  *   Pointer to the mlx5_flow.
9442  * @param[in] attr
9443  *   Pointer to the flow attributes.
9444  * @param[in, out] num_of_dest
9445  *   Pointer to the num of destination.
9446  * @param[in, out] sample_actions
9447  *   Pointer to sample actions list.
9448  * @param[in, out] res
9449  *   Pointer to sample resource.
9450  * @param[out] error
9451  *   Pointer to the error structure.
9452  *
9453  * @return
9454  *   0 on success, a negative errno value otherwise and rte_errno is set.
9455  */
9456 static int
9457 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9458                                 const struct rte_flow_action_sample *action,
9459                                 struct mlx5_flow *dev_flow,
9460                                 const struct rte_flow_attr *attr,
9461                                 uint32_t *num_of_dest,
9462                                 void **sample_actions,
9463                                 struct mlx5_flow_dv_sample_resource *res,
9464                                 struct rte_flow_error *error)
9465 {
9466         struct mlx5_priv *priv = dev->data->dev_private;
9467         const struct rte_flow_action *sub_actions;
9468         struct mlx5_flow_sub_actions_list *sample_act;
9469         struct mlx5_flow_sub_actions_idx *sample_idx;
9470         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9471         struct mlx5_flow_rss_desc *rss_desc;
9472         uint64_t action_flags = 0;
9473
9474         MLX5_ASSERT(wks);
9475         rss_desc = &wks->rss_desc;
9476         sample_act = &res->sample_act;
9477         sample_idx = &res->sample_idx;
9478         res->ratio = action->ratio;
9479         sub_actions = action->actions;
9480         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9481                 int type = sub_actions->type;
9482                 uint32_t pre_rix = 0;
9483                 void *pre_r;
9484                 switch (type) {
9485                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9486                 {
9487                         const struct rte_flow_action_queue *queue;
9488                         struct mlx5_hrxq *hrxq;
9489                         uint32_t hrxq_idx;
9490
9491                         queue = sub_actions->conf;
9492                         rss_desc->queue_num = 1;
9493                         rss_desc->queue[0] = queue->index;
9494                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9495                                                     rss_desc, &hrxq_idx);
9496                         if (!hrxq)
9497                                 return rte_flow_error_set
9498                                         (error, rte_errno,
9499                                          RTE_FLOW_ERROR_TYPE_ACTION,
9500                                          NULL,
9501                                          "cannot create fate queue");
9502                         sample_act->dr_queue_action = hrxq->action;
9503                         sample_idx->rix_hrxq = hrxq_idx;
9504                         sample_actions[sample_act->actions_num++] =
9505                                                 hrxq->action;
9506                         (*num_of_dest)++;
9507                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9508                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9509                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9510                         dev_flow->handle->fate_action =
9511                                         MLX5_FLOW_FATE_QUEUE;
9512                         break;
9513                 }
9514                 case RTE_FLOW_ACTION_TYPE_RSS:
9515                 {
9516                         struct mlx5_hrxq *hrxq;
9517                         uint32_t hrxq_idx;
9518                         const struct rte_flow_action_rss *rss;
9519                         const uint8_t *rss_key;
9520
9521                         rss = sub_actions->conf;
9522                         memcpy(rss_desc->queue, rss->queue,
9523                                rss->queue_num * sizeof(uint16_t));
9524                         rss_desc->queue_num = rss->queue_num;
9525                         /* NULL RSS key indicates default RSS key. */
9526                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9527                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9528                         /*
9529                          * rss->level and rss.types should be set in advance
9530                          * when expanding items for RSS.
9531                          */
9532                         flow_dv_hashfields_set(dev_flow, rss_desc);
9533                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9534                                                     rss_desc, &hrxq_idx);
9535                         if (!hrxq)
9536                                 return rte_flow_error_set
9537                                         (error, rte_errno,
9538                                          RTE_FLOW_ERROR_TYPE_ACTION,
9539                                          NULL,
9540                                          "cannot create fate queue");
9541                         sample_act->dr_queue_action = hrxq->action;
9542                         sample_idx->rix_hrxq = hrxq_idx;
9543                         sample_actions[sample_act->actions_num++] =
9544                                                 hrxq->action;
9545                         (*num_of_dest)++;
9546                         action_flags |= MLX5_FLOW_ACTION_RSS;
9547                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9548                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9549                         dev_flow->handle->fate_action =
9550                                         MLX5_FLOW_FATE_QUEUE;
9551                         break;
9552                 }
9553                 case RTE_FLOW_ACTION_TYPE_MARK:
9554                 {
9555                         uint32_t tag_be = mlx5_flow_mark_set
9556                                 (((const struct rte_flow_action_mark *)
9557                                 (sub_actions->conf))->id);
9558
9559                         dev_flow->handle->mark = 1;
9560                         pre_rix = dev_flow->handle->dvh.rix_tag;
9561                         /* Save the mark resource before sample */
9562                         pre_r = dev_flow->dv.tag_resource;
9563                         if (flow_dv_tag_resource_register(dev, tag_be,
9564                                                   dev_flow, error))
9565                                 return -rte_errno;
9566                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9567                         sample_act->dr_tag_action =
9568                                 dev_flow->dv.tag_resource->action;
9569                         sample_idx->rix_tag =
9570                                 dev_flow->handle->dvh.rix_tag;
9571                         sample_actions[sample_act->actions_num++] =
9572                                                 sample_act->dr_tag_action;
9573                         /* Recover the mark resource after sample */
9574                         dev_flow->dv.tag_resource = pre_r;
9575                         dev_flow->handle->dvh.rix_tag = pre_rix;
9576                         action_flags |= MLX5_FLOW_ACTION_MARK;
9577                         break;
9578                 }
9579                 case RTE_FLOW_ACTION_TYPE_COUNT:
9580                 {
9581                         uint32_t counter;
9582
9583                         counter = flow_dv_translate_create_counter(dev,
9584                                         dev_flow, sub_actions->conf, 0);
9585                         if (!counter)
9586                                 return rte_flow_error_set
9587                                                 (error, rte_errno,
9588                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9589                                                  NULL,
9590                                                  "cannot create counter"
9591                                                  " object.");
9592                         sample_idx->cnt = counter;
9593                         sample_act->dr_cnt_action =
9594                                   (flow_dv_counter_get_by_idx(dev,
9595                                   counter, NULL))->action;
9596                         sample_actions[sample_act->actions_num++] =
9597                                                 sample_act->dr_cnt_action;
9598                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9599                         break;
9600                 }
9601                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9602                 {
9603                         struct mlx5_flow_dv_port_id_action_resource
9604                                         port_id_resource;
9605                         uint32_t port_id = 0;
9606
9607                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9608                         /* Save the port id resource before sample */
9609                         pre_rix = dev_flow->handle->rix_port_id_action;
9610                         pre_r = dev_flow->dv.port_id_action;
9611                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9612                                                              &port_id, error))
9613                                 return -rte_errno;
9614                         port_id_resource.port_id = port_id;
9615                         if (flow_dv_port_id_action_resource_register
9616                             (dev, &port_id_resource, dev_flow, error))
9617                                 return -rte_errno;
9618                         sample_act->dr_port_id_action =
9619                                 dev_flow->dv.port_id_action->action;
9620                         sample_idx->rix_port_id_action =
9621                                 dev_flow->handle->rix_port_id_action;
9622                         sample_actions[sample_act->actions_num++] =
9623                                                 sample_act->dr_port_id_action;
9624                         /* Recover the port id resource after sample */
9625                         dev_flow->dv.port_id_action = pre_r;
9626                         dev_flow->handle->rix_port_id_action = pre_rix;
9627                         (*num_of_dest)++;
9628                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9629                         break;
9630                 }
9631                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9632                         /* Save the encap resource before sample */
9633                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9634                         pre_r = dev_flow->dv.encap_decap;
9635                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9636                                                            dev_flow,
9637                                                            attr->transfer,
9638                                                            error))
9639                                 return -rte_errno;
9640                         sample_act->dr_encap_action =
9641                                 dev_flow->dv.encap_decap->action;
9642                         sample_idx->rix_encap_decap =
9643                                 dev_flow->handle->dvh.rix_encap_decap;
9644                         sample_actions[sample_act->actions_num++] =
9645                                                 sample_act->dr_encap_action;
9646                         /* Recover the encap resource after sample */
9647                         dev_flow->dv.encap_decap = pre_r;
9648                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9649                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9650                         break;
9651                 default:
9652                         return rte_flow_error_set(error, EINVAL,
9653                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9654                                 NULL,
9655                                 "Not support for sampler action");
9656                 }
9657         }
9658         sample_act->action_flags = action_flags;
9659         res->ft_id = dev_flow->dv.group;
9660         if (attr->transfer) {
9661                 union {
9662                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9663                         uint64_t set_action;
9664                 } action_ctx = { .set_action = 0 };
9665
9666                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9667                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9668                          MLX5_MODIFICATION_TYPE_SET);
9669                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9670                          MLX5_MODI_META_REG_C_0);
9671                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9672                          priv->vport_meta_tag);
9673                 res->set_action = action_ctx.set_action;
9674         } else if (attr->ingress) {
9675                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9676         } else {
9677                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9678         }
9679         return 0;
9680 }
9681
9682 /**
9683  * Convert Sample action to DV specification.
9684  *
9685  * @param[in] dev
9686  *   Pointer to rte_eth_dev structure.
9687  * @param[in, out] dev_flow
9688  *   Pointer to the mlx5_flow.
9689  * @param[in] num_of_dest
9690  *   The num of destination.
9691  * @param[in, out] res
9692  *   Pointer to sample resource.
9693  * @param[in, out] mdest_res
9694  *   Pointer to destination array resource.
9695  * @param[in] sample_actions
9696  *   Pointer to sample path actions list.
9697  * @param[in] action_flags
9698  *   Holds the actions detected until now.
9699  * @param[out] error
9700  *   Pointer to the error structure.
9701  *
9702  * @return
9703  *   0 on success, a negative errno value otherwise and rte_errno is set.
9704  */
9705 static int
9706 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9707                              struct mlx5_flow *dev_flow,
9708                              uint32_t num_of_dest,
9709                              struct mlx5_flow_dv_sample_resource *res,
9710                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9711                              void **sample_actions,
9712                              uint64_t action_flags,
9713                              struct rte_flow_error *error)
9714 {
9715         /* update normal path action resource into last index of array */
9716         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9717         struct mlx5_flow_sub_actions_list *sample_act =
9718                                         &mdest_res->sample_act[dest_index];
9719         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9720         struct mlx5_flow_rss_desc *rss_desc;
9721         uint32_t normal_idx = 0;
9722         struct mlx5_hrxq *hrxq;
9723         uint32_t hrxq_idx;
9724
9725         MLX5_ASSERT(wks);
9726         rss_desc = &wks->rss_desc;
9727         if (num_of_dest > 1) {
9728                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9729                         /* Handle QP action for mirroring */
9730                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9731                                                     rss_desc, &hrxq_idx);
9732                         if (!hrxq)
9733                                 return rte_flow_error_set
9734                                      (error, rte_errno,
9735                                       RTE_FLOW_ERROR_TYPE_ACTION,
9736                                       NULL,
9737                                       "cannot create rx queue");
9738                         normal_idx++;
9739                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9740                         sample_act->dr_queue_action = hrxq->action;
9741                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9742                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9743                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9744                 }
9745                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9746                         normal_idx++;
9747                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9748                                 dev_flow->handle->dvh.rix_encap_decap;
9749                         sample_act->dr_encap_action =
9750                                 dev_flow->dv.encap_decap->action;
9751                 }
9752                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9753                         normal_idx++;
9754                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9755                                 dev_flow->handle->rix_port_id_action;
9756                         sample_act->dr_port_id_action =
9757                                 dev_flow->dv.port_id_action->action;
9758                 }
9759                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
9760                         normal_idx++;
9761                         mdest_res->sample_idx[dest_index].rix_jump =
9762                                 dev_flow->handle->rix_jump;
9763                         sample_act->dr_jump_action =
9764                                 dev_flow->dv.jump->action;
9765                         dev_flow->handle->rix_jump = 0;
9766                 }
9767                 sample_act->actions_num = normal_idx;
9768                 /* update sample action resource into first index of array */
9769                 mdest_res->ft_type = res->ft_type;
9770                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9771                                 sizeof(struct mlx5_flow_sub_actions_idx));
9772                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9773                                 sizeof(struct mlx5_flow_sub_actions_list));
9774                 mdest_res->num_of_dest = num_of_dest;
9775                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9776                                                          dev_flow, error))
9777                         return rte_flow_error_set(error, EINVAL,
9778                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9779                                                   NULL, "can't create sample "
9780                                                   "action");
9781         } else {
9782                 res->sub_actions = sample_actions;
9783                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9784                         return rte_flow_error_set(error, EINVAL,
9785                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9786                                                   NULL,
9787                                                   "can't create sample action");
9788         }
9789         return 0;
9790 }
9791
9792 /**
9793  * Remove an ASO age action from age actions list.
9794  *
9795  * @param[in] dev
9796  *   Pointer to the Ethernet device structure.
9797  * @param[in] age
9798  *   Pointer to the aso age action handler.
9799  */
9800 static void
9801 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9802                                 struct mlx5_aso_age_action *age)
9803 {
9804         struct mlx5_age_info *age_info;
9805         struct mlx5_age_param *age_param = &age->age_params;
9806         struct mlx5_priv *priv = dev->data->dev_private;
9807         uint16_t expected = AGE_CANDIDATE;
9808
9809         age_info = GET_PORT_AGE_INFO(priv);
9810         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9811                                          AGE_FREE, false, __ATOMIC_RELAXED,
9812                                          __ATOMIC_RELAXED)) {
9813                 /**
9814                  * We need the lock even it is age timeout,
9815                  * since age action may still in process.
9816                  */
9817                 rte_spinlock_lock(&age_info->aged_sl);
9818                 LIST_REMOVE(age, next);
9819                 rte_spinlock_unlock(&age_info->aged_sl);
9820                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9821         }
9822 }
9823
9824 /**
9825  * Release an ASO age action.
9826  *
9827  * @param[in] dev
9828  *   Pointer to the Ethernet device structure.
9829  * @param[in] age_idx
9830  *   Index of ASO age action to release.
9831  * @param[in] flow
9832  *   True if the release operation is during flow destroy operation.
9833  *   False if the release operation is during action destroy operation.
9834  *
9835  * @return
9836  *   0 when age action was removed, otherwise the number of references.
9837  */
9838 static int
9839 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9840 {
9841         struct mlx5_priv *priv = dev->data->dev_private;
9842         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9843         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9844         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9845
9846         if (!ret) {
9847                 flow_dv_aso_age_remove_from_age(dev, age);
9848                 rte_spinlock_lock(&mng->free_sl);
9849                 LIST_INSERT_HEAD(&mng->free, age, next);
9850                 rte_spinlock_unlock(&mng->free_sl);
9851         }
9852         return ret;
9853 }
9854
9855 /**
9856  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9857  *
9858  * @param[in] dev
9859  *   Pointer to the Ethernet device structure.
9860  *
9861  * @return
9862  *   0 on success, otherwise negative errno value and rte_errno is set.
9863  */
9864 static int
9865 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9866 {
9867         struct mlx5_priv *priv = dev->data->dev_private;
9868         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9869         void *old_pools = mng->pools;
9870         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9871         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9872         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9873
9874         if (!pools) {
9875                 rte_errno = ENOMEM;
9876                 return -ENOMEM;
9877         }
9878         if (old_pools) {
9879                 memcpy(pools, old_pools,
9880                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9881                 mlx5_free(old_pools);
9882         } else {
9883                 /* First ASO flow hit allocation - starting ASO data-path. */
9884                 int ret = mlx5_aso_queue_start(priv->sh);
9885
9886                 if (ret) {
9887                         mlx5_free(pools);
9888                         return ret;
9889                 }
9890         }
9891         mng->n = resize;
9892         mng->pools = pools;
9893         return 0;
9894 }
9895
9896 /**
9897  * Create and initialize a new ASO aging pool.
9898  *
9899  * @param[in] dev
9900  *   Pointer to the Ethernet device structure.
9901  * @param[out] age_free
9902  *   Where to put the pointer of a new age action.
9903  *
9904  * @return
9905  *   The age actions pool pointer and @p age_free is set on success,
9906  *   NULL otherwise and rte_errno is set.
9907  */
9908 static struct mlx5_aso_age_pool *
9909 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9910                         struct mlx5_aso_age_action **age_free)
9911 {
9912         struct mlx5_priv *priv = dev->data->dev_private;
9913         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9914         struct mlx5_aso_age_pool *pool = NULL;
9915         struct mlx5_devx_obj *obj = NULL;
9916         uint32_t i;
9917
9918         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9919                                                     priv->sh->pdn);
9920         if (!obj) {
9921                 rte_errno = ENODATA;
9922                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9923                 return NULL;
9924         }
9925         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9926         if (!pool) {
9927                 claim_zero(mlx5_devx_cmd_destroy(obj));
9928                 rte_errno = ENOMEM;
9929                 return NULL;
9930         }
9931         pool->flow_hit_aso_obj = obj;
9932         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9933         rte_spinlock_lock(&mng->resize_sl);
9934         pool->index = mng->next;
9935         /* Resize pools array if there is no room for the new pool in it. */
9936         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9937                 claim_zero(mlx5_devx_cmd_destroy(obj));
9938                 mlx5_free(pool);
9939                 rte_spinlock_unlock(&mng->resize_sl);
9940                 return NULL;
9941         }
9942         mng->pools[pool->index] = pool;
9943         mng->next++;
9944         rte_spinlock_unlock(&mng->resize_sl);
9945         /* Assign the first action in the new pool, the rest go to free list. */
9946         *age_free = &pool->actions[0];
9947         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9948                 pool->actions[i].offset = i;
9949                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9950         }
9951         return pool;
9952 }
9953
9954 /**
9955  * Allocate a ASO aging bit.
9956  *
9957  * @param[in] dev
9958  *   Pointer to the Ethernet device structure.
9959  * @param[out] error
9960  *   Pointer to the error structure.
9961  *
9962  * @return
9963  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9964  */
9965 static uint32_t
9966 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9967 {
9968         struct mlx5_priv *priv = dev->data->dev_private;
9969         const struct mlx5_aso_age_pool *pool;
9970         struct mlx5_aso_age_action *age_free = NULL;
9971         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9972
9973         MLX5_ASSERT(mng);
9974         /* Try to get the next free age action bit. */
9975         rte_spinlock_lock(&mng->free_sl);
9976         age_free = LIST_FIRST(&mng->free);
9977         if (age_free) {
9978                 LIST_REMOVE(age_free, next);
9979         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9980                 rte_spinlock_unlock(&mng->free_sl);
9981                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9982                                    NULL, "failed to create ASO age pool");
9983                 return 0; /* 0 is an error. */
9984         }
9985         rte_spinlock_unlock(&mng->free_sl);
9986         pool = container_of
9987           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9988                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9989                                                                        actions);
9990         if (!age_free->dr_action) {
9991                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9992                                                  error);
9993
9994                 if (reg_c < 0) {
9995                         rte_flow_error_set(error, rte_errno,
9996                                            RTE_FLOW_ERROR_TYPE_ACTION,
9997                                            NULL, "failed to get reg_c "
9998                                            "for ASO flow hit");
9999                         return 0; /* 0 is an error. */
10000                 }
10001 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10002                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10003                                 (priv->sh->rx_domain,
10004                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10005                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10006                                  (reg_c - REG_C_0));
10007 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10008                 if (!age_free->dr_action) {
10009                         rte_errno = errno;
10010                         rte_spinlock_lock(&mng->free_sl);
10011                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10012                         rte_spinlock_unlock(&mng->free_sl);
10013                         rte_flow_error_set(error, rte_errno,
10014                                            RTE_FLOW_ERROR_TYPE_ACTION,
10015                                            NULL, "failed to create ASO "
10016                                            "flow hit action");
10017                         return 0; /* 0 is an error. */
10018                 }
10019         }
10020         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10021         return pool->index | ((age_free->offset + 1) << 16);
10022 }
10023
10024 /**
10025  * Create a age action using ASO mechanism.
10026  *
10027  * @param[in] dev
10028  *   Pointer to rte_eth_dev structure.
10029  * @param[in] age
10030  *   Pointer to the aging action configuration.
10031  * @param[out] error
10032  *   Pointer to the error structure.
10033  *
10034  * @return
10035  *   Index to flow counter on success, 0 otherwise.
10036  */
10037 static uint32_t
10038 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10039                                  const struct rte_flow_action_age *age,
10040                                  struct rte_flow_error *error)
10041 {
10042         uint32_t age_idx = 0;
10043         struct mlx5_aso_age_action *aso_age;
10044
10045         age_idx = flow_dv_aso_age_alloc(dev, error);
10046         if (!age_idx)
10047                 return 0;
10048         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10049         aso_age->age_params.context = age->context;
10050         aso_age->age_params.timeout = age->timeout;
10051         aso_age->age_params.port_id = dev->data->port_id;
10052         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10053                          __ATOMIC_RELAXED);
10054         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10055                          __ATOMIC_RELAXED);
10056         return age_idx;
10057 }
10058
10059 /**
10060  * Fill the flow with DV spec, lock free
10061  * (mutex should be acquired by caller).
10062  *
10063  * @param[in] dev
10064  *   Pointer to rte_eth_dev structure.
10065  * @param[in, out] dev_flow
10066  *   Pointer to the sub flow.
10067  * @param[in] attr
10068  *   Pointer to the flow attributes.
10069  * @param[in] items
10070  *   Pointer to the list of items.
10071  * @param[in] actions
10072  *   Pointer to the list of actions.
10073  * @param[out] error
10074  *   Pointer to the error structure.
10075  *
10076  * @return
10077  *   0 on success, a negative errno value otherwise and rte_errno is set.
10078  */
10079 static int
10080 flow_dv_translate(struct rte_eth_dev *dev,
10081                   struct mlx5_flow *dev_flow,
10082                   const struct rte_flow_attr *attr,
10083                   const struct rte_flow_item items[],
10084                   const struct rte_flow_action actions[],
10085                   struct rte_flow_error *error)
10086 {
10087         struct mlx5_priv *priv = dev->data->dev_private;
10088         struct mlx5_dev_config *dev_conf = &priv->config;
10089         struct rte_flow *flow = dev_flow->flow;
10090         struct mlx5_flow_handle *handle = dev_flow->handle;
10091         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10092         struct mlx5_flow_rss_desc *rss_desc;
10093         uint64_t item_flags = 0;
10094         uint64_t last_item = 0;
10095         uint64_t action_flags = 0;
10096         struct mlx5_flow_dv_matcher matcher = {
10097                 .mask = {
10098                         .size = sizeof(matcher.mask.buf) -
10099                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10100                 },
10101         };
10102         int actions_n = 0;
10103         bool actions_end = false;
10104         union {
10105                 struct mlx5_flow_dv_modify_hdr_resource res;
10106                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10107                             sizeof(struct mlx5_modification_cmd) *
10108                             (MLX5_MAX_MODIFY_NUM + 1)];
10109         } mhdr_dummy;
10110         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10111         const struct rte_flow_action_count *count = NULL;
10112         const struct rte_flow_action_age *age = NULL;
10113         union flow_dv_attr flow_attr = { .attr = 0 };
10114         uint32_t tag_be;
10115         union mlx5_flow_tbl_key tbl_key;
10116         uint32_t modify_action_position = UINT32_MAX;
10117         void *match_mask = matcher.mask.buf;
10118         void *match_value = dev_flow->dv.value.buf;
10119         uint8_t next_protocol = 0xff;
10120         struct rte_vlan_hdr vlan = { 0 };
10121         struct mlx5_flow_dv_dest_array_resource mdest_res;
10122         struct mlx5_flow_dv_sample_resource sample_res;
10123         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10124         const struct rte_flow_action_sample *sample = NULL;
10125         struct mlx5_flow_sub_actions_list *sample_act;
10126         uint32_t sample_act_pos = UINT32_MAX;
10127         uint32_t num_of_dest = 0;
10128         int tmp_actions_n = 0;
10129         uint32_t table;
10130         int ret = 0;
10131         const struct mlx5_flow_tunnel *tunnel;
10132         struct flow_grp_info grp_info = {
10133                 .external = !!dev_flow->external,
10134                 .transfer = !!attr->transfer,
10135                 .fdb_def_rule = !!priv->fdb_def_rule,
10136                 .skip_scale = dev_flow->skip_scale &
10137                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10138         };
10139
10140         if (!wks)
10141                 return rte_flow_error_set(error, ENOMEM,
10142                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10143                                           NULL,
10144                                           "failed to push flow workspace");
10145         rss_desc = &wks->rss_desc;
10146         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10147         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10148         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10149                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10150         /* update normal path action resource into last index of array */
10151         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10152         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10153                  flow_items_to_tunnel(items) :
10154                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10155                  flow_actions_to_tunnel(actions) :
10156                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10157         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10158                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10159         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10160                                 (dev, tunnel, attr, items, actions);
10161         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10162                                        &grp_info, error);
10163         if (ret)
10164                 return ret;
10165         dev_flow->dv.group = table;
10166         if (attr->transfer)
10167                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10168         /* number of actions must be set to 0 in case of dirty stack. */
10169         mhdr_res->actions_num = 0;
10170         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10171                 /*
10172                  * do not add decap action if match rule drops packet
10173                  * HW rejects rules with decap & drop
10174                  *
10175                  * if tunnel match rule was inserted before matching tunnel set
10176                  * rule flow table used in the match rule must be registered.
10177                  * current implementation handles that in the
10178                  * flow_dv_match_register() at the function end.
10179                  */
10180                 bool add_decap = true;
10181                 const struct rte_flow_action *ptr = actions;
10182
10183                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10184                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10185                                 add_decap = false;
10186                                 break;
10187                         }
10188                 }
10189                 if (add_decap) {
10190                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10191                                                            attr->transfer,
10192                                                            error))
10193                                 return -rte_errno;
10194                         dev_flow->dv.actions[actions_n++] =
10195                                         dev_flow->dv.encap_decap->action;
10196                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10197                 }
10198         }
10199         for (; !actions_end ; actions++) {
10200                 const struct rte_flow_action_queue *queue;
10201                 const struct rte_flow_action_rss *rss;
10202                 const struct rte_flow_action *action = actions;
10203                 const uint8_t *rss_key;
10204                 const struct rte_flow_action_meter *mtr;
10205                 struct mlx5_flow_tbl_resource *tbl;
10206                 struct mlx5_aso_age_action *age_act;
10207                 uint32_t port_id = 0;
10208                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10209                 int action_type = actions->type;
10210                 const struct rte_flow_action *found_action = NULL;
10211                 struct mlx5_flow_meter *fm = NULL;
10212                 uint32_t jump_group = 0;
10213
10214                 if (!mlx5_flow_os_action_supported(action_type))
10215                         return rte_flow_error_set(error, ENOTSUP,
10216                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10217                                                   actions,
10218                                                   "action not supported");
10219                 switch (action_type) {
10220                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10221                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10222                         break;
10223                 case RTE_FLOW_ACTION_TYPE_VOID:
10224                         break;
10225                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10226                         if (flow_dv_translate_action_port_id(dev, action,
10227                                                              &port_id, error))
10228                                 return -rte_errno;
10229                         port_id_resource.port_id = port_id;
10230                         MLX5_ASSERT(!handle->rix_port_id_action);
10231                         if (flow_dv_port_id_action_resource_register
10232                             (dev, &port_id_resource, dev_flow, error))
10233                                 return -rte_errno;
10234                         dev_flow->dv.actions[actions_n++] =
10235                                         dev_flow->dv.port_id_action->action;
10236                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10237                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
10238                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10239                         num_of_dest++;
10240                         break;
10241                 case RTE_FLOW_ACTION_TYPE_FLAG:
10242                         action_flags |= MLX5_FLOW_ACTION_FLAG;
10243                         dev_flow->handle->mark = 1;
10244                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10245                                 struct rte_flow_action_mark mark = {
10246                                         .id = MLX5_FLOW_MARK_DEFAULT,
10247                                 };
10248
10249                                 if (flow_dv_convert_action_mark(dev, &mark,
10250                                                                 mhdr_res,
10251                                                                 error))
10252                                         return -rte_errno;
10253                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10254                                 break;
10255                         }
10256                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
10257                         /*
10258                          * Only one FLAG or MARK is supported per device flow
10259                          * right now. So the pointer to the tag resource must be
10260                          * zero before the register process.
10261                          */
10262                         MLX5_ASSERT(!handle->dvh.rix_tag);
10263                         if (flow_dv_tag_resource_register(dev, tag_be,
10264                                                           dev_flow, error))
10265                                 return -rte_errno;
10266                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10267                         dev_flow->dv.actions[actions_n++] =
10268                                         dev_flow->dv.tag_resource->action;
10269                         break;
10270                 case RTE_FLOW_ACTION_TYPE_MARK:
10271                         action_flags |= MLX5_FLOW_ACTION_MARK;
10272                         dev_flow->handle->mark = 1;
10273                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
10274                                 const struct rte_flow_action_mark *mark =
10275                                         (const struct rte_flow_action_mark *)
10276                                                 actions->conf;
10277
10278                                 if (flow_dv_convert_action_mark(dev, mark,
10279                                                                 mhdr_res,
10280                                                                 error))
10281                                         return -rte_errno;
10282                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
10283                                 break;
10284                         }
10285                         /* Fall-through */
10286                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
10287                         /* Legacy (non-extensive) MARK action. */
10288                         tag_be = mlx5_flow_mark_set
10289                               (((const struct rte_flow_action_mark *)
10290                                (actions->conf))->id);
10291                         MLX5_ASSERT(!handle->dvh.rix_tag);
10292                         if (flow_dv_tag_resource_register(dev, tag_be,
10293                                                           dev_flow, error))
10294                                 return -rte_errno;
10295                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10296                         dev_flow->dv.actions[actions_n++] =
10297                                         dev_flow->dv.tag_resource->action;
10298                         break;
10299                 case RTE_FLOW_ACTION_TYPE_SET_META:
10300                         if (flow_dv_convert_action_set_meta
10301                                 (dev, mhdr_res, attr,
10302                                  (const struct rte_flow_action_set_meta *)
10303                                   actions->conf, error))
10304                                 return -rte_errno;
10305                         action_flags |= MLX5_FLOW_ACTION_SET_META;
10306                         break;
10307                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
10308                         if (flow_dv_convert_action_set_tag
10309                                 (dev, mhdr_res,
10310                                  (const struct rte_flow_action_set_tag *)
10311                                   actions->conf, error))
10312                                 return -rte_errno;
10313                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10314                         break;
10315                 case RTE_FLOW_ACTION_TYPE_DROP:
10316                         action_flags |= MLX5_FLOW_ACTION_DROP;
10317                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
10318                         break;
10319                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10320                         queue = actions->conf;
10321                         rss_desc->queue_num = 1;
10322                         rss_desc->queue[0] = queue->index;
10323                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10324                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10325                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
10326                         num_of_dest++;
10327                         break;
10328                 case RTE_FLOW_ACTION_TYPE_RSS:
10329                         rss = actions->conf;
10330                         memcpy(rss_desc->queue, rss->queue,
10331                                rss->queue_num * sizeof(uint16_t));
10332                         rss_desc->queue_num = rss->queue_num;
10333                         /* NULL RSS key indicates default RSS key. */
10334                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10335                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10336                         /*
10337                          * rss->level and rss.types should be set in advance
10338                          * when expanding items for RSS.
10339                          */
10340                         action_flags |= MLX5_FLOW_ACTION_RSS;
10341                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
10342                                 MLX5_FLOW_FATE_SHARED_RSS :
10343                                 MLX5_FLOW_FATE_QUEUE;
10344                         break;
10345                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
10346                         flow->age = (uint32_t)(uintptr_t)(action->conf);
10347                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
10348                         __atomic_fetch_add(&age_act->refcnt, 1,
10349                                            __ATOMIC_RELAXED);
10350                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
10351                         action_flags |= MLX5_FLOW_ACTION_AGE;
10352                         break;
10353                 case RTE_FLOW_ACTION_TYPE_AGE:
10354                         if (priv->sh->flow_hit_aso_en && attr->group) {
10355                                 /*
10356                                  * Create one shared age action, to be used
10357                                  * by all sub-flows.
10358                                  */
10359                                 if (!flow->age) {
10360                                         flow->age =
10361                                                 flow_dv_translate_create_aso_age
10362                                                         (dev, action->conf,
10363                                                          error);
10364                                         if (!flow->age)
10365                                                 return rte_flow_error_set
10366                                                 (error, rte_errno,
10367                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10368                                                  NULL,
10369                                                  "can't create ASO age action");
10370                                 }
10371                                 dev_flow->dv.actions[actions_n++] =
10372                                           (flow_aso_age_get_by_idx
10373                                                 (dev, flow->age))->dr_action;
10374                                 action_flags |= MLX5_FLOW_ACTION_AGE;
10375                                 break;
10376                         }
10377                         /* Fall-through */
10378                 case RTE_FLOW_ACTION_TYPE_COUNT:
10379                         if (!dev_conf->devx) {
10380                                 return rte_flow_error_set
10381                                               (error, ENOTSUP,
10382                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10383                                                NULL,
10384                                                "count action not supported");
10385                         }
10386                         /* Save information first, will apply later. */
10387                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
10388                                 count = action->conf;
10389                         else
10390                                 age = action->conf;
10391                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10392                         break;
10393                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
10394                         dev_flow->dv.actions[actions_n++] =
10395                                                 priv->sh->pop_vlan_action;
10396                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
10397                         break;
10398                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
10399                         if (!(action_flags &
10400                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
10401                                 flow_dev_get_vlan_info_from_items(items, &vlan);
10402                         vlan.eth_proto = rte_be_to_cpu_16
10403                              ((((const struct rte_flow_action_of_push_vlan *)
10404                                                    actions->conf)->ethertype));
10405                         found_action = mlx5_flow_find_action
10406                                         (actions + 1,
10407                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
10408                         if (found_action)
10409                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10410                         found_action = mlx5_flow_find_action
10411                                         (actions + 1,
10412                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
10413                         if (found_action)
10414                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
10415                         if (flow_dv_create_action_push_vlan
10416                                             (dev, attr, &vlan, dev_flow, error))
10417                                 return -rte_errno;
10418                         dev_flow->dv.actions[actions_n++] =
10419                                         dev_flow->dv.push_vlan_res->action;
10420                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
10421                         break;
10422                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
10423                         /* of_vlan_push action handled this action */
10424                         MLX5_ASSERT(action_flags &
10425                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
10426                         break;
10427                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
10428                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
10429                                 break;
10430                         flow_dev_get_vlan_info_from_items(items, &vlan);
10431                         mlx5_update_vlan_vid_pcp(actions, &vlan);
10432                         /* If no VLAN push - this is a modify header action */
10433                         if (flow_dv_convert_action_modify_vlan_vid
10434                                                 (mhdr_res, actions, error))
10435                                 return -rte_errno;
10436                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10437                         break;
10438                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10439                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10440                         if (flow_dv_create_action_l2_encap(dev, actions,
10441                                                            dev_flow,
10442                                                            attr->transfer,
10443                                                            error))
10444                                 return -rte_errno;
10445                         dev_flow->dv.actions[actions_n++] =
10446                                         dev_flow->dv.encap_decap->action;
10447                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10448                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10449                                 sample_act->action_flags |=
10450                                                         MLX5_FLOW_ACTION_ENCAP;
10451                         break;
10452                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10453                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10454                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10455                                                            attr->transfer,
10456                                                            error))
10457                                 return -rte_errno;
10458                         dev_flow->dv.actions[actions_n++] =
10459                                         dev_flow->dv.encap_decap->action;
10460                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10461                         break;
10462                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10463                         /* Handle encap with preceding decap. */
10464                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10465                                 if (flow_dv_create_action_raw_encap
10466                                         (dev, actions, dev_flow, attr, error))
10467                                         return -rte_errno;
10468                                 dev_flow->dv.actions[actions_n++] =
10469                                         dev_flow->dv.encap_decap->action;
10470                         } else {
10471                                 /* Handle encap without preceding decap. */
10472                                 if (flow_dv_create_action_l2_encap
10473                                     (dev, actions, dev_flow, attr->transfer,
10474                                      error))
10475                                         return -rte_errno;
10476                                 dev_flow->dv.actions[actions_n++] =
10477                                         dev_flow->dv.encap_decap->action;
10478                         }
10479                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10480                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10481                                 sample_act->action_flags |=
10482                                                         MLX5_FLOW_ACTION_ENCAP;
10483                         break;
10484                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10485                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10486                                 ;
10487                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10488                                 if (flow_dv_create_action_l2_decap
10489                                     (dev, dev_flow, attr->transfer, error))
10490                                         return -rte_errno;
10491                                 dev_flow->dv.actions[actions_n++] =
10492                                         dev_flow->dv.encap_decap->action;
10493                         }
10494                         /* If decap is followed by encap, handle it at encap. */
10495                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10496                         break;
10497                 case RTE_FLOW_ACTION_TYPE_JUMP:
10498                         jump_group = ((const struct rte_flow_action_jump *)
10499                                                         action->conf)->group;
10500                         grp_info.std_tbl_fix = 0;
10501                         if (dev_flow->skip_scale &
10502                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
10503                                 grp_info.skip_scale = 1;
10504                         else
10505                                 grp_info.skip_scale = 0;
10506                         ret = mlx5_flow_group_to_table(dev, tunnel,
10507                                                        jump_group,
10508                                                        &table,
10509                                                        &grp_info, error);
10510                         if (ret)
10511                                 return ret;
10512                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10513                                                        attr->transfer,
10514                                                        !!dev_flow->external,
10515                                                        tunnel, jump_group, 0,
10516                                                        error);
10517                         if (!tbl)
10518                                 return rte_flow_error_set
10519                                                 (error, errno,
10520                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10521                                                  NULL,
10522                                                  "cannot create jump action.");
10523                         if (flow_dv_jump_tbl_resource_register
10524                             (dev, tbl, dev_flow, error)) {
10525                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10526                                 return rte_flow_error_set
10527                                                 (error, errno,
10528                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10529                                                  NULL,
10530                                                  "cannot create jump action.");
10531                         }
10532                         dev_flow->dv.actions[actions_n++] =
10533                                         dev_flow->dv.jump->action;
10534                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10535                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10536                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
10537                         num_of_dest++;
10538                         break;
10539                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10540                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10541                         if (flow_dv_convert_action_modify_mac
10542                                         (mhdr_res, actions, error))
10543                                 return -rte_errno;
10544                         action_flags |= actions->type ==
10545                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10546                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10547                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10548                         break;
10549                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10550                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10551                         if (flow_dv_convert_action_modify_ipv4
10552                                         (mhdr_res, actions, error))
10553                                 return -rte_errno;
10554                         action_flags |= actions->type ==
10555                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10556                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10557                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10558                         break;
10559                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10560                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10561                         if (flow_dv_convert_action_modify_ipv6
10562                                         (mhdr_res, actions, error))
10563                                 return -rte_errno;
10564                         action_flags |= actions->type ==
10565                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10566                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10567                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10568                         break;
10569                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10570                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10571                         if (flow_dv_convert_action_modify_tp
10572                                         (mhdr_res, actions, items,
10573                                          &flow_attr, dev_flow, !!(action_flags &
10574                                          MLX5_FLOW_ACTION_DECAP), error))
10575                                 return -rte_errno;
10576                         action_flags |= actions->type ==
10577                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10578                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10579                                         MLX5_FLOW_ACTION_SET_TP_DST;
10580                         break;
10581                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10582                         if (flow_dv_convert_action_modify_dec_ttl
10583                                         (mhdr_res, items, &flow_attr, dev_flow,
10584                                          !!(action_flags &
10585                                          MLX5_FLOW_ACTION_DECAP), error))
10586                                 return -rte_errno;
10587                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10588                         break;
10589                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10590                         if (flow_dv_convert_action_modify_ttl
10591                                         (mhdr_res, actions, items, &flow_attr,
10592                                          dev_flow, !!(action_flags &
10593                                          MLX5_FLOW_ACTION_DECAP), error))
10594                                 return -rte_errno;
10595                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10596                         break;
10597                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10598                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10599                         if (flow_dv_convert_action_modify_tcp_seq
10600                                         (mhdr_res, actions, error))
10601                                 return -rte_errno;
10602                         action_flags |= actions->type ==
10603                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10604                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10605                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10606                         break;
10607
10608                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10609                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10610                         if (flow_dv_convert_action_modify_tcp_ack
10611                                         (mhdr_res, actions, error))
10612                                 return -rte_errno;
10613                         action_flags |= actions->type ==
10614                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10615                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10616                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10617                         break;
10618                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10619                         if (flow_dv_convert_action_set_reg
10620                                         (mhdr_res, actions, error))
10621                                 return -rte_errno;
10622                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10623                         break;
10624                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10625                         if (flow_dv_convert_action_copy_mreg
10626                                         (dev, mhdr_res, actions, error))
10627                                 return -rte_errno;
10628                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10629                         break;
10630                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10631                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10632                         dev_flow->handle->fate_action =
10633                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10634                         break;
10635                 case RTE_FLOW_ACTION_TYPE_METER:
10636                         mtr = actions->conf;
10637                         if (!flow->meter) {
10638                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10639                                                             attr, error);
10640                                 if (!fm)
10641                                         return rte_flow_error_set(error,
10642                                                 rte_errno,
10643                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10644                                                 NULL,
10645                                                 "meter not found "
10646                                                 "or invalid parameters");
10647                                 flow->meter = fm->idx;
10648                         }
10649                         /* Set the meter action. */
10650                         if (!fm) {
10651                                 fm = mlx5_ipool_get(priv->sh->ipool
10652                                                 [MLX5_IPOOL_MTR], flow->meter);
10653                                 if (!fm)
10654                                         return rte_flow_error_set(error,
10655                                                 rte_errno,
10656                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10657                                                 NULL,
10658                                                 "meter not found "
10659                                                 "or invalid parameters");
10660                         }
10661                         dev_flow->dv.actions[actions_n++] =
10662                                 fm->mfts->meter_action;
10663                         action_flags |= MLX5_FLOW_ACTION_METER;
10664                         break;
10665                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10666                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10667                                                               actions, error))
10668                                 return -rte_errno;
10669                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10670                         break;
10671                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10672                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10673                                                               actions, error))
10674                                 return -rte_errno;
10675                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10676                         break;
10677                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10678                         sample_act_pos = actions_n;
10679                         sample = (const struct rte_flow_action_sample *)
10680                                  action->conf;
10681                         actions_n++;
10682                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10683                         /* put encap action into group if work with port id */
10684                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10685                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10686                                 sample_act->action_flags |=
10687                                                         MLX5_FLOW_ACTION_ENCAP;
10688                         break;
10689                 case RTE_FLOW_ACTION_TYPE_END:
10690                         actions_end = true;
10691                         if (mhdr_res->actions_num) {
10692                                 /* create modify action if needed. */
10693                                 if (flow_dv_modify_hdr_resource_register
10694                                         (dev, mhdr_res, dev_flow, error))
10695                                         return -rte_errno;
10696                                 dev_flow->dv.actions[modify_action_position] =
10697                                         handle->dvh.modify_hdr->action;
10698                         }
10699                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10700                                 /*
10701                                  * Create one count action, to be used
10702                                  * by all sub-flows.
10703                                  */
10704                                 if (!flow->counter) {
10705                                         flow->counter =
10706                                                 flow_dv_translate_create_counter
10707                                                         (dev, dev_flow, count,
10708                                                          age);
10709                                         if (!flow->counter)
10710                                                 return rte_flow_error_set
10711                                                 (error, rte_errno,
10712                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10713                                                  NULL, "cannot create counter"
10714                                                  " object.");
10715                                 }
10716                                 dev_flow->dv.actions[actions_n] =
10717                                           (flow_dv_counter_get_by_idx(dev,
10718                                           flow->counter, NULL))->action;
10719                                 actions_n++;
10720                         }
10721                 default:
10722                         break;
10723                 }
10724                 if (mhdr_res->actions_num &&
10725                     modify_action_position == UINT32_MAX)
10726                         modify_action_position = actions_n++;
10727         }
10728         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10729                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10730                 int item_type = items->type;
10731
10732                 if (!mlx5_flow_os_item_supported(item_type))
10733                         return rte_flow_error_set(error, ENOTSUP,
10734                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10735                                                   NULL, "item not supported");
10736                 switch (item_type) {
10737                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10738                         flow_dv_translate_item_port_id
10739                                 (dev, match_mask, match_value, items, attr);
10740                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10741                         break;
10742                 case RTE_FLOW_ITEM_TYPE_ETH:
10743                         flow_dv_translate_item_eth(match_mask, match_value,
10744                                                    items, tunnel,
10745                                                    dev_flow->dv.group);
10746                         matcher.priority = action_flags &
10747                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10748                                         !dev_flow->external ?
10749                                         MLX5_PRIORITY_MAP_L3 :
10750                                         MLX5_PRIORITY_MAP_L2;
10751                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10752                                              MLX5_FLOW_LAYER_OUTER_L2;
10753                         break;
10754                 case RTE_FLOW_ITEM_TYPE_VLAN:
10755                         flow_dv_translate_item_vlan(dev_flow,
10756                                                     match_mask, match_value,
10757                                                     items, tunnel,
10758                                                     dev_flow->dv.group);
10759                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10760                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10761                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10762                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10763                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10764                         break;
10765                 case RTE_FLOW_ITEM_TYPE_IPV4:
10766                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10767                                                   &item_flags, &tunnel);
10768                         flow_dv_translate_item_ipv4(match_mask, match_value,
10769                                                     items, tunnel,
10770                                                     dev_flow->dv.group);
10771                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10772                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10773                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10774                         if (items->mask != NULL &&
10775                             ((const struct rte_flow_item_ipv4 *)
10776                              items->mask)->hdr.next_proto_id) {
10777                                 next_protocol =
10778                                         ((const struct rte_flow_item_ipv4 *)
10779                                          (items->spec))->hdr.next_proto_id;
10780                                 next_protocol &=
10781                                         ((const struct rte_flow_item_ipv4 *)
10782                                          (items->mask))->hdr.next_proto_id;
10783                         } else {
10784                                 /* Reset for inner layer. */
10785                                 next_protocol = 0xff;
10786                         }
10787                         break;
10788                 case RTE_FLOW_ITEM_TYPE_IPV6:
10789                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10790                                                   &item_flags, &tunnel);
10791                         flow_dv_translate_item_ipv6(match_mask, match_value,
10792                                                     items, tunnel,
10793                                                     dev_flow->dv.group);
10794                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10795                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10796                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10797                         if (items->mask != NULL &&
10798                             ((const struct rte_flow_item_ipv6 *)
10799                              items->mask)->hdr.proto) {
10800                                 next_protocol =
10801                                         ((const struct rte_flow_item_ipv6 *)
10802                                          items->spec)->hdr.proto;
10803                                 next_protocol &=
10804                                         ((const struct rte_flow_item_ipv6 *)
10805                                          items->mask)->hdr.proto;
10806                         } else {
10807                                 /* Reset for inner layer. */
10808                                 next_protocol = 0xff;
10809                         }
10810                         break;
10811                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10812                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10813                                                              match_value,
10814                                                              items, tunnel);
10815                         last_item = tunnel ?
10816                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10817                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10818                         if (items->mask != NULL &&
10819                             ((const struct rte_flow_item_ipv6_frag_ext *)
10820                              items->mask)->hdr.next_header) {
10821                                 next_protocol =
10822                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10823                                  items->spec)->hdr.next_header;
10824                                 next_protocol &=
10825                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10826                                  items->mask)->hdr.next_header;
10827                         } else {
10828                                 /* Reset for inner layer. */
10829                                 next_protocol = 0xff;
10830                         }
10831                         break;
10832                 case RTE_FLOW_ITEM_TYPE_TCP:
10833                         flow_dv_translate_item_tcp(match_mask, match_value,
10834                                                    items, tunnel);
10835                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10836                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10837                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10838                         break;
10839                 case RTE_FLOW_ITEM_TYPE_UDP:
10840                         flow_dv_translate_item_udp(match_mask, match_value,
10841                                                    items, tunnel);
10842                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10843                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10844                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10845                         break;
10846                 case RTE_FLOW_ITEM_TYPE_GRE:
10847                         flow_dv_translate_item_gre(match_mask, match_value,
10848                                                    items, tunnel);
10849                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10850                         last_item = MLX5_FLOW_LAYER_GRE;
10851                         break;
10852                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10853                         flow_dv_translate_item_gre_key(match_mask,
10854                                                        match_value, items);
10855                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10856                         break;
10857                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10858                         flow_dv_translate_item_nvgre(match_mask, match_value,
10859                                                      items, tunnel);
10860                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10861                         last_item = MLX5_FLOW_LAYER_GRE;
10862                         break;
10863                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10864                         flow_dv_translate_item_vxlan(match_mask, match_value,
10865                                                      items, tunnel);
10866                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10867                         last_item = MLX5_FLOW_LAYER_VXLAN;
10868                         break;
10869                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10870                         flow_dv_translate_item_vxlan_gpe(match_mask,
10871                                                          match_value, items,
10872                                                          tunnel);
10873                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10874                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10875                         break;
10876                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10877                         flow_dv_translate_item_geneve(match_mask, match_value,
10878                                                       items, tunnel);
10879                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10880                         last_item = MLX5_FLOW_LAYER_GENEVE;
10881                         break;
10882                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
10883                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
10884                                                           match_value,
10885                                                           items, error);
10886                         if (ret)
10887                                 return rte_flow_error_set(error, -ret,
10888                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10889                                         "cannot create GENEVE TLV option");
10890                         flow->geneve_tlv_option = 1;
10891                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
10892                         break;
10893                 case RTE_FLOW_ITEM_TYPE_MPLS:
10894                         flow_dv_translate_item_mpls(match_mask, match_value,
10895                                                     items, last_item, tunnel);
10896                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10897                         last_item = MLX5_FLOW_LAYER_MPLS;
10898                         break;
10899                 case RTE_FLOW_ITEM_TYPE_MARK:
10900                         flow_dv_translate_item_mark(dev, match_mask,
10901                                                     match_value, items);
10902                         last_item = MLX5_FLOW_ITEM_MARK;
10903                         break;
10904                 case RTE_FLOW_ITEM_TYPE_META:
10905                         flow_dv_translate_item_meta(dev, match_mask,
10906                                                     match_value, attr, items);
10907                         last_item = MLX5_FLOW_ITEM_METADATA;
10908                         break;
10909                 case RTE_FLOW_ITEM_TYPE_ICMP:
10910                         flow_dv_translate_item_icmp(match_mask, match_value,
10911                                                     items, tunnel);
10912                         last_item = MLX5_FLOW_LAYER_ICMP;
10913                         break;
10914                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10915                         flow_dv_translate_item_icmp6(match_mask, match_value,
10916                                                       items, tunnel);
10917                         last_item = MLX5_FLOW_LAYER_ICMP6;
10918                         break;
10919                 case RTE_FLOW_ITEM_TYPE_TAG:
10920                         flow_dv_translate_item_tag(dev, match_mask,
10921                                                    match_value, items);
10922                         last_item = MLX5_FLOW_ITEM_TAG;
10923                         break;
10924                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10925                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10926                                                         match_value, items);
10927                         last_item = MLX5_FLOW_ITEM_TAG;
10928                         break;
10929                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10930                         flow_dv_translate_item_tx_queue(dev, match_mask,
10931                                                         match_value,
10932                                                         items);
10933                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10934                         break;
10935                 case RTE_FLOW_ITEM_TYPE_GTP:
10936                         flow_dv_translate_item_gtp(match_mask, match_value,
10937                                                    items, tunnel);
10938                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10939                         last_item = MLX5_FLOW_LAYER_GTP;
10940                         break;
10941                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
10942                         ret = flow_dv_translate_item_gtp_psc(match_mask,
10943                                                           match_value,
10944                                                           items);
10945                         if (ret)
10946                                 return rte_flow_error_set(error, -ret,
10947                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
10948                                         "cannot create GTP PSC item");
10949                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
10950                         break;
10951                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10952                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10953                                 /* Create it only the first time to be used. */
10954                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10955                                 if (ret)
10956                                         return rte_flow_error_set
10957                                                 (error, -ret,
10958                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10959                                                 NULL,
10960                                                 "cannot create eCPRI parser");
10961                         }
10962                         /* Adjust the length matcher and device flow value. */
10963                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10964                         dev_flow->dv.value.size =
10965                                         MLX5_ST_SZ_BYTES(fte_match_param);
10966                         flow_dv_translate_item_ecpri(dev, match_mask,
10967                                                      match_value, items);
10968                         /* No other protocol should follow eCPRI layer. */
10969                         last_item = MLX5_FLOW_LAYER_ECPRI;
10970                         break;
10971                 default:
10972                         break;
10973                 }
10974                 item_flags |= last_item;
10975         }
10976         /*
10977          * When E-Switch mode is enabled, we have two cases where we need to
10978          * set the source port manually.
10979          * The first one, is in case of Nic steering rule, and the second is
10980          * E-Switch rule where no port_id item was found. In both cases
10981          * the source port is set according the current port in use.
10982          */
10983         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10984             (priv->representor || priv->master)) {
10985                 if (flow_dv_translate_item_port_id(dev, match_mask,
10986                                                    match_value, NULL, attr))
10987                         return -rte_errno;
10988         }
10989 #ifdef RTE_LIBRTE_MLX5_DEBUG
10990         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10991                                               dev_flow->dv.value.buf));
10992 #endif
10993         /*
10994          * Layers may be already initialized from prefix flow if this dev_flow
10995          * is the suffix flow.
10996          */
10997         handle->layers |= item_flags;
10998         if (action_flags & MLX5_FLOW_ACTION_RSS)
10999                 flow_dv_hashfields_set(dev_flow, rss_desc);
11000         /* If has RSS action in the sample action, the Sample/Mirror resource
11001          * should be registered after the hash filed be update.
11002          */
11003         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11004                 ret = flow_dv_translate_action_sample(dev,
11005                                                       sample,
11006                                                       dev_flow, attr,
11007                                                       &num_of_dest,
11008                                                       sample_actions,
11009                                                       &sample_res,
11010                                                       error);
11011                 if (ret < 0)
11012                         return ret;
11013                 ret = flow_dv_create_action_sample(dev,
11014                                                    dev_flow,
11015                                                    num_of_dest,
11016                                                    &sample_res,
11017                                                    &mdest_res,
11018                                                    sample_actions,
11019                                                    action_flags,
11020                                                    error);
11021                 if (ret < 0)
11022                         return rte_flow_error_set
11023                                                 (error, rte_errno,
11024                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11025                                                 NULL,
11026                                                 "cannot create sample action");
11027                 if (num_of_dest > 1) {
11028                         dev_flow->dv.actions[sample_act_pos] =
11029                         dev_flow->dv.dest_array_res->action;
11030                 } else {
11031                         dev_flow->dv.actions[sample_act_pos] =
11032                         dev_flow->dv.sample_res->verbs_action;
11033                 }
11034         }
11035         /*
11036          * For multiple destination (sample action with ratio=1), the encap
11037          * action and port id action will be combined into group action.
11038          * So need remove the original these actions in the flow and only
11039          * use the sample action instead of.
11040          */
11041         if (num_of_dest > 1 &&
11042             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11043                 int i;
11044                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11045
11046                 for (i = 0; i < actions_n; i++) {
11047                         if ((sample_act->dr_encap_action &&
11048                                 sample_act->dr_encap_action ==
11049                                 dev_flow->dv.actions[i]) ||
11050                                 (sample_act->dr_port_id_action &&
11051                                 sample_act->dr_port_id_action ==
11052                                 dev_flow->dv.actions[i]) ||
11053                                 (sample_act->dr_jump_action &&
11054                                 sample_act->dr_jump_action ==
11055                                 dev_flow->dv.actions[i]))
11056                                 continue;
11057                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11058                 }
11059                 memcpy((void *)dev_flow->dv.actions,
11060                                 (void *)temp_actions,
11061                                 tmp_actions_n * sizeof(void *));
11062                 actions_n = tmp_actions_n;
11063         }
11064         dev_flow->dv.actions_n = actions_n;
11065         dev_flow->act_flags = action_flags;
11066         /* Register matcher. */
11067         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11068                                     matcher.mask.size);
11069         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11070                                         matcher.priority);
11071         /* reserved field no needs to be set to 0 here. */
11072         tbl_key.domain = attr->transfer;
11073         tbl_key.direction = attr->egress;
11074         tbl_key.table_id = dev_flow->dv.group;
11075         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11076                                      tunnel, attr->group, error))
11077                 return -rte_errno;
11078         return 0;
11079 }
11080
11081 /**
11082  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11083  * and tunnel.
11084  *
11085  * @param[in, out] action
11086  *   Shred RSS action holding hash RX queue objects.
11087  * @param[in] hash_fields
11088  *   Defines combination of packet fields to participate in RX hash.
11089  * @param[in] tunnel
11090  *   Tunnel type
11091  * @param[in] hrxq_idx
11092  *   Hash RX queue index to set.
11093  *
11094  * @return
11095  *   0 on success, otherwise negative errno value.
11096  */
11097 static int
11098 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11099                               const uint64_t hash_fields,
11100                               const int tunnel,
11101                               uint32_t hrxq_idx)
11102 {
11103         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11104
11105         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11106         case MLX5_RSS_HASH_IPV4:
11107                 hrxqs[0] = hrxq_idx;
11108                 return 0;
11109         case MLX5_RSS_HASH_IPV4_TCP:
11110                 hrxqs[1] = hrxq_idx;
11111                 return 0;
11112         case MLX5_RSS_HASH_IPV4_UDP:
11113                 hrxqs[2] = hrxq_idx;
11114                 return 0;
11115         case MLX5_RSS_HASH_IPV6:
11116                 hrxqs[3] = hrxq_idx;
11117                 return 0;
11118         case MLX5_RSS_HASH_IPV6_TCP:
11119                 hrxqs[4] = hrxq_idx;
11120                 return 0;
11121         case MLX5_RSS_HASH_IPV6_UDP:
11122                 hrxqs[5] = hrxq_idx;
11123                 return 0;
11124         case MLX5_RSS_HASH_NONE:
11125                 hrxqs[6] = hrxq_idx;
11126                 return 0;
11127         default:
11128                 return -1;
11129         }
11130 }
11131
11132 /**
11133  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11134  * and tunnel.
11135  *
11136  * @param[in] dev
11137  *   Pointer to the Ethernet device structure.
11138  * @param[in] idx
11139  *   Shared RSS action ID holding hash RX queue objects.
11140  * @param[in] hash_fields
11141  *   Defines combination of packet fields to participate in RX hash.
11142  * @param[in] tunnel
11143  *   Tunnel type
11144  *
11145  * @return
11146  *   Valid hash RX queue index, otherwise 0.
11147  */
11148 static uint32_t
11149 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11150                                  const uint64_t hash_fields,
11151                                  const int tunnel)
11152 {
11153         struct mlx5_priv *priv = dev->data->dev_private;
11154         struct mlx5_shared_action_rss *shared_rss =
11155             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11156         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11157                                                         shared_rss->hrxq_tunnel;
11158
11159         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11160         case MLX5_RSS_HASH_IPV4:
11161                 return hrxqs[0];
11162         case MLX5_RSS_HASH_IPV4_TCP:
11163                 return hrxqs[1];
11164         case MLX5_RSS_HASH_IPV4_UDP:
11165                 return hrxqs[2];
11166         case MLX5_RSS_HASH_IPV6:
11167                 return hrxqs[3];
11168         case MLX5_RSS_HASH_IPV6_TCP:
11169                 return hrxqs[4];
11170         case MLX5_RSS_HASH_IPV6_UDP:
11171                 return hrxqs[5];
11172         case MLX5_RSS_HASH_NONE:
11173                 return hrxqs[6];
11174         default:
11175                 return 0;
11176         }
11177 }
11178
11179 /**
11180  * Apply the flow to the NIC, lock free,
11181  * (mutex should be acquired by caller).
11182  *
11183  * @param[in] dev
11184  *   Pointer to the Ethernet device structure.
11185  * @param[in, out] flow
11186  *   Pointer to flow structure.
11187  * @param[out] error
11188  *   Pointer to error structure.
11189  *
11190  * @return
11191  *   0 on success, a negative errno value otherwise and rte_errno is set.
11192  */
11193 static int
11194 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11195               struct rte_flow_error *error)
11196 {
11197         struct mlx5_flow_dv_workspace *dv;
11198         struct mlx5_flow_handle *dh;
11199         struct mlx5_flow_handle_dv *dv_h;
11200         struct mlx5_flow *dev_flow;
11201         struct mlx5_priv *priv = dev->data->dev_private;
11202         uint32_t handle_idx;
11203         int n;
11204         int err;
11205         int idx;
11206         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11207         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11208
11209         MLX5_ASSERT(wks);
11210         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11211                 dev_flow = &wks->flows[idx];
11212                 dv = &dev_flow->dv;
11213                 dh = dev_flow->handle;
11214                 dv_h = &dh->dvh;
11215                 n = dv->actions_n;
11216                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11217                         if (dv->transfer) {
11218                                 dv->actions[n++] = priv->sh->esw_drop_action;
11219                         } else {
11220                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11221                                 dv->actions[n++] =
11222                                                 priv->drop_queue.hrxq->action;
11223                         }
11224                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
11225                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
11226                         struct mlx5_hrxq *hrxq;
11227                         uint32_t hrxq_idx;
11228
11229                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
11230                                                     &hrxq_idx);
11231                         if (!hrxq) {
11232                                 rte_flow_error_set
11233                                         (error, rte_errno,
11234                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11235                                          "cannot get hash queue");
11236                                 goto error;
11237                         }
11238                         dh->rix_hrxq = hrxq_idx;
11239                         dv->actions[n++] = hrxq->action;
11240                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11241                         struct mlx5_hrxq *hrxq = NULL;
11242                         uint32_t hrxq_idx;
11243
11244                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
11245                                                 rss_desc->shared_rss,
11246                                                 dev_flow->hash_fields,
11247                                                 !!(dh->layers &
11248                                                 MLX5_FLOW_LAYER_TUNNEL));
11249                         if (hrxq_idx)
11250                                 hrxq = mlx5_ipool_get
11251                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
11252                                          hrxq_idx);
11253                         if (!hrxq) {
11254                                 rte_flow_error_set
11255                                         (error, rte_errno,
11256                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11257                                          "cannot get hash queue");
11258                                 goto error;
11259                         }
11260                         dh->rix_srss = rss_desc->shared_rss;
11261                         dv->actions[n++] = hrxq->action;
11262                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
11263                         if (!priv->sh->default_miss_action) {
11264                                 rte_flow_error_set
11265                                         (error, rte_errno,
11266                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11267                                          "default miss action not be created.");
11268                                 goto error;
11269                         }
11270                         dv->actions[n++] = priv->sh->default_miss_action;
11271                 }
11272                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
11273                                                (void *)&dv->value, n,
11274                                                dv->actions, &dh->drv_flow);
11275                 if (err) {
11276                         rte_flow_error_set(error, errno,
11277                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11278                                            NULL,
11279                                            "hardware refuses to create flow");
11280                         goto error;
11281                 }
11282                 if (priv->vmwa_context &&
11283                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
11284                         /*
11285                          * The rule contains the VLAN pattern.
11286                          * For VF we are going to create VLAN
11287                          * interface to make hypervisor set correct
11288                          * e-Switch vport context.
11289                          */
11290                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
11291                 }
11292         }
11293         return 0;
11294 error:
11295         err = rte_errno; /* Save rte_errno before cleanup. */
11296         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
11297                        handle_idx, dh, next) {
11298                 /* hrxq is union, don't clear it if the flag is not set. */
11299                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
11300                         mlx5_hrxq_release(dev, dh->rix_hrxq);
11301                         dh->rix_hrxq = 0;
11302                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
11303                         dh->rix_srss = 0;
11304                 }
11305                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11306                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11307         }
11308         rte_errno = err; /* Restore rte_errno. */
11309         return -rte_errno;
11310 }
11311
11312 void
11313 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
11314                           struct mlx5_cache_entry *entry)
11315 {
11316         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
11317                                                           entry);
11318
11319         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
11320         mlx5_free(cache);
11321 }
11322
11323 /**
11324  * Release the flow matcher.
11325  *
11326  * @param dev
11327  *   Pointer to Ethernet device.
11328  * @param port_id
11329  *   Index to port ID action resource.
11330  *
11331  * @return
11332  *   1 while a reference on it exists, 0 when freed.
11333  */
11334 static int
11335 flow_dv_matcher_release(struct rte_eth_dev *dev,
11336                         struct mlx5_flow_handle *handle)
11337 {
11338         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
11339         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
11340                                                             typeof(*tbl), tbl);
11341         int ret;
11342
11343         MLX5_ASSERT(matcher->matcher_object);
11344         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
11345         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
11346         return ret;
11347 }
11348
11349 /**
11350  * Release encap_decap resource.
11351  *
11352  * @param list
11353  *   Pointer to the hash list.
11354  * @param entry
11355  *   Pointer to exist resource entry object.
11356  */
11357 void
11358 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
11359                               struct mlx5_hlist_entry *entry)
11360 {
11361         struct mlx5_dev_ctx_shared *sh = list->ctx;
11362         struct mlx5_flow_dv_encap_decap_resource *res =
11363                 container_of(entry, typeof(*res), entry);
11364
11365         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11366         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
11367 }
11368
11369 /**
11370  * Release an encap/decap resource.
11371  *
11372  * @param dev
11373  *   Pointer to Ethernet device.
11374  * @param encap_decap_idx
11375  *   Index of encap decap resource.
11376  *
11377  * @return
11378  *   1 while a reference on it exists, 0 when freed.
11379  */
11380 static int
11381 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
11382                                      uint32_t encap_decap_idx)
11383 {
11384         struct mlx5_priv *priv = dev->data->dev_private;
11385         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
11386
11387         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
11388                                         encap_decap_idx);
11389         if (!cache_resource)
11390                 return 0;
11391         MLX5_ASSERT(cache_resource->action);
11392         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
11393                                      &cache_resource->entry);
11394 }
11395
11396 /**
11397  * Release an jump to table action resource.
11398  *
11399  * @param dev
11400  *   Pointer to Ethernet device.
11401  * @param rix_jump
11402  *   Index to the jump action resource.
11403  *
11404  * @return
11405  *   1 while a reference on it exists, 0 when freed.
11406  */
11407 static int
11408 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
11409                                   uint32_t rix_jump)
11410 {
11411         struct mlx5_priv *priv = dev->data->dev_private;
11412         struct mlx5_flow_tbl_data_entry *tbl_data;
11413
11414         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
11415                                   rix_jump);
11416         if (!tbl_data)
11417                 return 0;
11418         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
11419 }
11420
11421 void
11422 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
11423                          struct mlx5_hlist_entry *entry)
11424 {
11425         struct mlx5_flow_dv_modify_hdr_resource *res =
11426                 container_of(entry, typeof(*res), entry);
11427
11428         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
11429         mlx5_free(entry);
11430 }
11431
11432 /**
11433  * Release a modify-header resource.
11434  *
11435  * @param dev
11436  *   Pointer to Ethernet device.
11437  * @param handle
11438  *   Pointer to mlx5_flow_handle.
11439  *
11440  * @return
11441  *   1 while a reference on it exists, 0 when freed.
11442  */
11443 static int
11444 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
11445                                     struct mlx5_flow_handle *handle)
11446 {
11447         struct mlx5_priv *priv = dev->data->dev_private;
11448         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
11449
11450         MLX5_ASSERT(entry->action);
11451         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
11452 }
11453
11454 void
11455 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
11456                           struct mlx5_cache_entry *entry)
11457 {
11458         struct mlx5_dev_ctx_shared *sh = list->ctx;
11459         struct mlx5_flow_dv_port_id_action_resource *cache =
11460                         container_of(entry, typeof(*cache), entry);
11461
11462         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11463         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
11464 }
11465
11466 /**
11467  * Release port ID action resource.
11468  *
11469  * @param dev
11470  *   Pointer to Ethernet device.
11471  * @param handle
11472  *   Pointer to mlx5_flow_handle.
11473  *
11474  * @return
11475  *   1 while a reference on it exists, 0 when freed.
11476  */
11477 static int
11478 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11479                                         uint32_t port_id)
11480 {
11481         struct mlx5_priv *priv = dev->data->dev_private;
11482         struct mlx5_flow_dv_port_id_action_resource *cache;
11483
11484         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11485         if (!cache)
11486                 return 0;
11487         MLX5_ASSERT(cache->action);
11488         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11489                                      &cache->entry);
11490 }
11491
11492 /**
11493  * Release shared RSS action resource.
11494  *
11495  * @param dev
11496  *   Pointer to Ethernet device.
11497  * @param srss
11498  *   Shared RSS action index.
11499  */
11500 static void
11501 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11502 {
11503         struct mlx5_priv *priv = dev->data->dev_private;
11504         struct mlx5_shared_action_rss *shared_rss;
11505
11506         shared_rss = mlx5_ipool_get
11507                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11508         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11509 }
11510
11511 void
11512 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11513                             struct mlx5_cache_entry *entry)
11514 {
11515         struct mlx5_dev_ctx_shared *sh = list->ctx;
11516         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11517                         container_of(entry, typeof(*cache), entry);
11518
11519         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11520         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11521 }
11522
11523 /**
11524  * Release push vlan action resource.
11525  *
11526  * @param dev
11527  *   Pointer to Ethernet device.
11528  * @param handle
11529  *   Pointer to mlx5_flow_handle.
11530  *
11531  * @return
11532  *   1 while a reference on it exists, 0 when freed.
11533  */
11534 static int
11535 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11536                                           struct mlx5_flow_handle *handle)
11537 {
11538         struct mlx5_priv *priv = dev->data->dev_private;
11539         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11540         uint32_t idx = handle->dvh.rix_push_vlan;
11541
11542         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11543         if (!cache)
11544                 return 0;
11545         MLX5_ASSERT(cache->action);
11546         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11547                                      &cache->entry);
11548 }
11549
11550 /**
11551  * Release the fate resource.
11552  *
11553  * @param dev
11554  *   Pointer to Ethernet device.
11555  * @param handle
11556  *   Pointer to mlx5_flow_handle.
11557  */
11558 static void
11559 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11560                                struct mlx5_flow_handle *handle)
11561 {
11562         if (!handle->rix_fate)
11563                 return;
11564         switch (handle->fate_action) {
11565         case MLX5_FLOW_FATE_QUEUE:
11566                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11567                 break;
11568         case MLX5_FLOW_FATE_JUMP:
11569                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
11570                 break;
11571         case MLX5_FLOW_FATE_PORT_ID:
11572                 flow_dv_port_id_action_resource_release(dev,
11573                                 handle->rix_port_id_action);
11574                 break;
11575         default:
11576                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11577                 break;
11578         }
11579         handle->rix_fate = 0;
11580 }
11581
11582 void
11583 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11584                          struct mlx5_cache_entry *entry)
11585 {
11586         struct mlx5_flow_dv_sample_resource *cache_resource =
11587                         container_of(entry, typeof(*cache_resource), entry);
11588         struct rte_eth_dev *dev = cache_resource->dev;
11589         struct mlx5_priv *priv = dev->data->dev_private;
11590
11591         if (cache_resource->verbs_action)
11592                 claim_zero(mlx5_flow_os_destroy_flow_action
11593                                 (cache_resource->verbs_action));
11594         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11595                 if (cache_resource->default_miss)
11596                         claim_zero(mlx5_flow_os_destroy_flow_action
11597                           (cache_resource->default_miss));
11598         }
11599         if (cache_resource->normal_path_tbl)
11600                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11601                         cache_resource->normal_path_tbl);
11602         flow_dv_sample_sub_actions_release(dev,
11603                                 &cache_resource->sample_idx);
11604         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11605                         cache_resource->idx);
11606         DRV_LOG(DEBUG, "sample resource %p: removed",
11607                 (void *)cache_resource);
11608 }
11609
11610 /**
11611  * Release an sample resource.
11612  *
11613  * @param dev
11614  *   Pointer to Ethernet device.
11615  * @param handle
11616  *   Pointer to mlx5_flow_handle.
11617  *
11618  * @return
11619  *   1 while a reference on it exists, 0 when freed.
11620  */
11621 static int
11622 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11623                                      struct mlx5_flow_handle *handle)
11624 {
11625         struct mlx5_priv *priv = dev->data->dev_private;
11626         struct mlx5_flow_dv_sample_resource *cache_resource;
11627
11628         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11629                          handle->dvh.rix_sample);
11630         if (!cache_resource)
11631                 return 0;
11632         MLX5_ASSERT(cache_resource->verbs_action);
11633         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11634                                      &cache_resource->entry);
11635 }
11636
11637 void
11638 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11639                              struct mlx5_cache_entry *entry)
11640 {
11641         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11642                         container_of(entry, typeof(*cache_resource), entry);
11643         struct rte_eth_dev *dev = cache_resource->dev;
11644         struct mlx5_priv *priv = dev->data->dev_private;
11645         uint32_t i = 0;
11646
11647         MLX5_ASSERT(cache_resource->action);
11648         if (cache_resource->action)
11649                 claim_zero(mlx5_flow_os_destroy_flow_action
11650                                         (cache_resource->action));
11651         for (; i < cache_resource->num_of_dest; i++)
11652                 flow_dv_sample_sub_actions_release(dev,
11653                                 &cache_resource->sample_idx[i]);
11654         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11655                         cache_resource->idx);
11656         DRV_LOG(DEBUG, "destination array resource %p: removed",
11657                 (void *)cache_resource);
11658 }
11659
11660 /**
11661  * Release an destination array resource.
11662  *
11663  * @param dev
11664  *   Pointer to Ethernet device.
11665  * @param handle
11666  *   Pointer to mlx5_flow_handle.
11667  *
11668  * @return
11669  *   1 while a reference on it exists, 0 when freed.
11670  */
11671 static int
11672 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11673                                     struct mlx5_flow_handle *handle)
11674 {
11675         struct mlx5_priv *priv = dev->data->dev_private;
11676         struct mlx5_flow_dv_dest_array_resource *cache;
11677
11678         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11679                                handle->dvh.rix_dest_array);
11680         if (!cache)
11681                 return 0;
11682         MLX5_ASSERT(cache->action);
11683         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11684                                      &cache->entry);
11685 }
11686
11687 static void
11688 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
11689 {
11690         struct mlx5_priv *priv = dev->data->dev_private;
11691         struct mlx5_dev_ctx_shared *sh = priv->sh;
11692         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
11693                                 sh->geneve_tlv_option_resource;
11694         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
11695         if (geneve_opt_resource) {
11696                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
11697                                          __ATOMIC_RELAXED))) {
11698                         claim_zero(mlx5_devx_cmd_destroy
11699                                         (geneve_opt_resource->obj));
11700                         mlx5_free(sh->geneve_tlv_option_resource);
11701                         sh->geneve_tlv_option_resource = NULL;
11702                 }
11703         }
11704         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
11705 }
11706
11707 /**
11708  * Remove the flow from the NIC but keeps it in memory.
11709  * Lock free, (mutex should be acquired by caller).
11710  *
11711  * @param[in] dev
11712  *   Pointer to Ethernet device.
11713  * @param[in, out] flow
11714  *   Pointer to flow structure.
11715  */
11716 static void
11717 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11718 {
11719         struct mlx5_flow_handle *dh;
11720         uint32_t handle_idx;
11721         struct mlx5_priv *priv = dev->data->dev_private;
11722
11723         if (!flow)
11724                 return;
11725         handle_idx = flow->dev_handles;
11726         while (handle_idx) {
11727                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11728                                     handle_idx);
11729                 if (!dh)
11730                         return;
11731                 if (dh->drv_flow) {
11732                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11733                         dh->drv_flow = NULL;
11734                 }
11735                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11736                         flow_dv_fate_resource_release(dev, dh);
11737                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11738                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11739                 handle_idx = dh->next.next;
11740         }
11741 }
11742
11743 /**
11744  * Remove the flow from the NIC and the memory.
11745  * Lock free, (mutex should be acquired by caller).
11746  *
11747  * @param[in] dev
11748  *   Pointer to the Ethernet device structure.
11749  * @param[in, out] flow
11750  *   Pointer to flow structure.
11751  */
11752 static void
11753 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11754 {
11755         struct mlx5_flow_handle *dev_handle;
11756         struct mlx5_priv *priv = dev->data->dev_private;
11757         uint32_t srss = 0;
11758
11759         if (!flow)
11760                 return;
11761         flow_dv_remove(dev, flow);
11762         if (flow->counter) {
11763                 flow_dv_counter_free(dev, flow->counter);
11764                 flow->counter = 0;
11765         }
11766         if (flow->meter) {
11767                 struct mlx5_flow_meter *fm;
11768
11769                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11770                                     flow->meter);
11771                 if (fm)
11772                         mlx5_flow_meter_detach(fm);
11773                 flow->meter = 0;
11774         }
11775         if (flow->age)
11776                 flow_dv_aso_age_release(dev, flow->age);
11777         if (flow->geneve_tlv_option) {
11778                 flow_dv_geneve_tlv_option_resource_release(dev);
11779                 flow->geneve_tlv_option = 0;
11780         }
11781         while (flow->dev_handles) {
11782                 uint32_t tmp_idx = flow->dev_handles;
11783
11784                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11785                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11786                 if (!dev_handle)
11787                         return;
11788                 flow->dev_handles = dev_handle->next.next;
11789                 if (dev_handle->dvh.matcher)
11790                         flow_dv_matcher_release(dev, dev_handle);
11791                 if (dev_handle->dvh.rix_sample)
11792                         flow_dv_sample_resource_release(dev, dev_handle);
11793                 if (dev_handle->dvh.rix_dest_array)
11794                         flow_dv_dest_array_resource_release(dev, dev_handle);
11795                 if (dev_handle->dvh.rix_encap_decap)
11796                         flow_dv_encap_decap_resource_release(dev,
11797                                 dev_handle->dvh.rix_encap_decap);
11798                 if (dev_handle->dvh.modify_hdr)
11799                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11800                 if (dev_handle->dvh.rix_push_vlan)
11801                         flow_dv_push_vlan_action_resource_release(dev,
11802                                                                   dev_handle);
11803                 if (dev_handle->dvh.rix_tag)
11804                         flow_dv_tag_release(dev,
11805                                             dev_handle->dvh.rix_tag);
11806                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11807                         flow_dv_fate_resource_release(dev, dev_handle);
11808                 else if (!srss)
11809                         srss = dev_handle->rix_srss;
11810                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11811                            tmp_idx);
11812         }
11813         if (srss)
11814                 flow_dv_shared_rss_action_release(dev, srss);
11815 }
11816
11817 /**
11818  * Release array of hash RX queue objects.
11819  * Helper function.
11820  *
11821  * @param[in] dev
11822  *   Pointer to the Ethernet device structure.
11823  * @param[in, out] hrxqs
11824  *   Array of hash RX queue objects.
11825  *
11826  * @return
11827  *   Total number of references to hash RX queue objects in *hrxqs* array
11828  *   after this operation.
11829  */
11830 static int
11831 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11832                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11833 {
11834         size_t i;
11835         int remaining = 0;
11836
11837         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11838                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11839
11840                 if (!ret)
11841                         (*hrxqs)[i] = 0;
11842                 remaining += ret;
11843         }
11844         return remaining;
11845 }
11846
11847 /**
11848  * Release all hash RX queue objects representing shared RSS action.
11849  *
11850  * @param[in] dev
11851  *   Pointer to the Ethernet device structure.
11852  * @param[in, out] action
11853  *   Shared RSS action to remove hash RX queue objects from.
11854  *
11855  * @return
11856  *   Total number of references to hash RX queue objects stored in *action*
11857  *   after this operation.
11858  *   Expected to be 0 if no external references held.
11859  */
11860 static int
11861 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11862                                  struct mlx5_shared_action_rss *action)
11863 {
11864         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11865                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11866 }
11867
11868 /**
11869  * Setup shared RSS action.
11870  * Prepare set of hash RX queue objects sufficient to handle all valid
11871  * hash_fields combinations (see enum ibv_rx_hash_fields).
11872  *
11873  * @param[in] dev
11874  *   Pointer to the Ethernet device structure.
11875  * @param[in] action_idx
11876  *   Shared RSS action ipool index.
11877  * @param[in, out] action
11878  *   Partially initialized shared RSS action.
11879  * @param[out] error
11880  *   Perform verbose error reporting if not NULL. Initialized in case of
11881  *   error only.
11882  *
11883  * @return
11884  *   0 on success, otherwise negative errno value.
11885  */
11886 static int
11887 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11888                            uint32_t action_idx,
11889                            struct mlx5_shared_action_rss *action,
11890                            struct rte_flow_error *error)
11891 {
11892         struct mlx5_flow_rss_desc rss_desc = { 0 };
11893         size_t i;
11894         int err;
11895
11896         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11897                 return rte_flow_error_set(error, rte_errno,
11898                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11899                                           "cannot setup indirection table");
11900         }
11901         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11902         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11903         rss_desc.const_q = action->origin.queue;
11904         rss_desc.queue_num = action->origin.queue_num;
11905         /* Set non-zero value to indicate a shared RSS. */
11906         rss_desc.shared_rss = action_idx;
11907         rss_desc.ind_tbl = action->ind_tbl;
11908         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11909                 uint32_t hrxq_idx;
11910                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11911                 int tunnel;
11912
11913                 for (tunnel = 0; tunnel < 2; tunnel++) {
11914                         rss_desc.tunnel = tunnel;
11915                         rss_desc.hash_fields = hash_fields;
11916                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11917                         if (!hrxq_idx) {
11918                                 rte_flow_error_set
11919                                         (error, rte_errno,
11920                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11921                                          "cannot get hash queue");
11922                                 goto error_hrxq_new;
11923                         }
11924                         err = __flow_dv_action_rss_hrxq_set
11925                                 (action, hash_fields, tunnel, hrxq_idx);
11926                         MLX5_ASSERT(!err);
11927                 }
11928         }
11929         return 0;
11930 error_hrxq_new:
11931         err = rte_errno;
11932         __flow_dv_action_rss_hrxqs_release(dev, action);
11933         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11934                 action->ind_tbl = NULL;
11935         rte_errno = err;
11936         return -rte_errno;
11937 }
11938
11939 /**
11940  * Create shared RSS action.
11941  *
11942  * @param[in] dev
11943  *   Pointer to the Ethernet device structure.
11944  * @param[in] conf
11945  *   Shared action configuration.
11946  * @param[in] rss
11947  *   RSS action specification used to create shared action.
11948  * @param[out] error
11949  *   Perform verbose error reporting if not NULL. Initialized in case of
11950  *   error only.
11951  *
11952  * @return
11953  *   A valid shared action ID in case of success, 0 otherwise and
11954  *   rte_errno is set.
11955  */
11956 static uint32_t
11957 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11958                             const struct rte_flow_shared_action_conf *conf,
11959                             const struct rte_flow_action_rss *rss,
11960                             struct rte_flow_error *error)
11961 {
11962         struct mlx5_priv *priv = dev->data->dev_private;
11963         struct mlx5_shared_action_rss *shared_action = NULL;
11964         void *queue = NULL;
11965         struct rte_flow_action_rss *origin;
11966         const uint8_t *rss_key;
11967         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11968         uint32_t idx;
11969
11970         RTE_SET_USED(conf);
11971         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11972                             0, SOCKET_ID_ANY);
11973         shared_action = mlx5_ipool_zmalloc
11974                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11975         if (!shared_action || !queue) {
11976                 rte_flow_error_set(error, ENOMEM,
11977                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11978                                    "cannot allocate resource memory");
11979                 goto error_rss_init;
11980         }
11981         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11982                 rte_flow_error_set(error, E2BIG,
11983                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11984                                    "rss action number out of range");
11985                 goto error_rss_init;
11986         }
11987         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11988                                              sizeof(*shared_action->ind_tbl),
11989                                              0, SOCKET_ID_ANY);
11990         if (!shared_action->ind_tbl) {
11991                 rte_flow_error_set(error, ENOMEM,
11992                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11993                                    "cannot allocate resource memory");
11994                 goto error_rss_init;
11995         }
11996         memcpy(queue, rss->queue, queue_size);
11997         shared_action->ind_tbl->queues = queue;
11998         shared_action->ind_tbl->queues_n = rss->queue_num;
11999         origin = &shared_action->origin;
12000         origin->func = rss->func;
12001         origin->level = rss->level;
12002         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12003         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12004         /* NULL RSS key indicates default RSS key. */
12005         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12006         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12007         origin->key = &shared_action->key[0];
12008         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12009         origin->queue = queue;
12010         origin->queue_num = rss->queue_num;
12011         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
12012                 goto error_rss_init;
12013         rte_spinlock_init(&shared_action->action_rss_sl);
12014         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
12015         rte_spinlock_lock(&priv->shared_act_sl);
12016         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12017                      &priv->rss_shared_actions, idx, shared_action, next);
12018         rte_spinlock_unlock(&priv->shared_act_sl);
12019         return idx;
12020 error_rss_init:
12021         if (shared_action) {
12022                 if (shared_action->ind_tbl)
12023                         mlx5_free(shared_action->ind_tbl);
12024                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12025                                 idx);
12026         }
12027         if (queue)
12028                 mlx5_free(queue);
12029         return 0;
12030 }
12031
12032 /**
12033  * Destroy the shared RSS action.
12034  * Release related hash RX queue objects.
12035  *
12036  * @param[in] dev
12037  *   Pointer to the Ethernet device structure.
12038  * @param[in] idx
12039  *   The shared RSS action object ID to be removed.
12040  * @param[out] error
12041  *   Perform verbose error reporting if not NULL. Initialized in case of
12042  *   error only.
12043  *
12044  * @return
12045  *   0 on success, otherwise negative errno value.
12046  */
12047 static int
12048 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12049                              struct rte_flow_error *error)
12050 {
12051         struct mlx5_priv *priv = dev->data->dev_private;
12052         struct mlx5_shared_action_rss *shared_rss =
12053             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12054         uint32_t old_refcnt = 1;
12055         int remaining;
12056         uint16_t *queue = NULL;
12057
12058         if (!shared_rss)
12059                 return rte_flow_error_set(error, EINVAL,
12060                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12061                                           "invalid shared action");
12062         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12063         if (remaining)
12064                 return rte_flow_error_set(error, EBUSY,
12065                                           RTE_FLOW_ERROR_TYPE_ACTION,
12066                                           NULL,
12067                                           "shared rss hrxq has references");
12068         queue = shared_rss->ind_tbl->queues;
12069         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12070         if (remaining)
12071                 return rte_flow_error_set(error, EBUSY,
12072                                           RTE_FLOW_ERROR_TYPE_ACTION,
12073                                           NULL,
12074                                           "shared rss indirection table has"
12075                                           " references");
12076         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12077                                          0, 0, __ATOMIC_ACQUIRE,
12078                                          __ATOMIC_RELAXED))
12079                 return rte_flow_error_set(error, EBUSY,
12080                                           RTE_FLOW_ERROR_TYPE_ACTION,
12081                                           NULL,
12082                                           "shared rss has references");
12083         mlx5_free(queue);
12084         rte_spinlock_lock(&priv->shared_act_sl);
12085         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12086                      &priv->rss_shared_actions, idx, shared_rss, next);
12087         rte_spinlock_unlock(&priv->shared_act_sl);
12088         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12089                         idx);
12090         return 0;
12091 }
12092
12093 /**
12094  * Create shared action, lock free,
12095  * (mutex should be acquired by caller).
12096  * Dispatcher for action type specific call.
12097  *
12098  * @param[in] dev
12099  *   Pointer to the Ethernet device structure.
12100  * @param[in] conf
12101  *   Shared action configuration.
12102  * @param[in] action
12103  *   Action specification used to create shared action.
12104  * @param[out] error
12105  *   Perform verbose error reporting if not NULL. Initialized in case of
12106  *   error only.
12107  *
12108  * @return
12109  *   A valid shared action handle in case of success, NULL otherwise and
12110  *   rte_errno is set.
12111  */
12112 static struct rte_flow_shared_action *
12113 flow_dv_action_create(struct rte_eth_dev *dev,
12114                       const struct rte_flow_shared_action_conf *conf,
12115                       const struct rte_flow_action *action,
12116                       struct rte_flow_error *err)
12117 {
12118         uint32_t idx = 0;
12119         uint32_t ret = 0;
12120
12121         switch (action->type) {
12122         case RTE_FLOW_ACTION_TYPE_RSS:
12123                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12124                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12125                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12126                 break;
12127         case RTE_FLOW_ACTION_TYPE_AGE:
12128                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12129                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12130                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12131                 if (ret) {
12132                         struct mlx5_aso_age_action *aso_age =
12133                                               flow_aso_age_get_by_idx(dev, ret);
12134
12135                         if (!aso_age->age_params.context)
12136                                 aso_age->age_params.context =
12137                                                          (void *)(uintptr_t)idx;
12138                 }
12139                 break;
12140         default:
12141                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12142                                    NULL, "action type not supported");
12143                 break;
12144         }
12145         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12146 }
12147
12148 /**
12149  * Destroy the shared action.
12150  * Release action related resources on the NIC and the memory.
12151  * Lock free, (mutex should be acquired by caller).
12152  * Dispatcher for action type specific call.
12153  *
12154  * @param[in] dev
12155  *   Pointer to the Ethernet device structure.
12156  * @param[in] action
12157  *   The shared action object to be removed.
12158  * @param[out] error
12159  *   Perform verbose error reporting if not NULL. Initialized in case of
12160  *   error only.
12161  *
12162  * @return
12163  *   0 on success, otherwise negative errno value.
12164  */
12165 static int
12166 flow_dv_action_destroy(struct rte_eth_dev *dev,
12167                        struct rte_flow_shared_action *action,
12168                        struct rte_flow_error *error)
12169 {
12170         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12171         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12172         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12173         int ret;
12174
12175         switch (type) {
12176         case MLX5_SHARED_ACTION_TYPE_RSS:
12177                 return __flow_dv_action_rss_release(dev, idx, error);
12178         case MLX5_SHARED_ACTION_TYPE_AGE:
12179                 ret = flow_dv_aso_age_release(dev, idx);
12180                 if (ret)
12181                         /*
12182                          * In this case, the last flow has a reference will
12183                          * actually release the age action.
12184                          */
12185                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12186                                 " released with references %d.", idx, ret);
12187                 return 0;
12188         default:
12189                 return rte_flow_error_set(error, ENOTSUP,
12190                                           RTE_FLOW_ERROR_TYPE_ACTION,
12191                                           NULL,
12192                                           "action type not supported");
12193         }
12194 }
12195
12196 /**
12197  * Updates in place shared RSS action configuration.
12198  *
12199  * @param[in] dev
12200  *   Pointer to the Ethernet device structure.
12201  * @param[in] idx
12202  *   The shared RSS action object ID to be updated.
12203  * @param[in] action_conf
12204  *   RSS action specification used to modify *shared_rss*.
12205  * @param[out] error
12206  *   Perform verbose error reporting if not NULL. Initialized in case of
12207  *   error only.
12208  *
12209  * @return
12210  *   0 on success, otherwise negative errno value.
12211  * @note: currently only support update of RSS queues.
12212  */
12213 static int
12214 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12215                             const struct rte_flow_action_rss *action_conf,
12216                             struct rte_flow_error *error)
12217 {
12218         struct mlx5_priv *priv = dev->data->dev_private;
12219         struct mlx5_shared_action_rss *shared_rss =
12220             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12221         int ret = 0;
12222         void *queue = NULL;
12223         uint16_t *queue_old = NULL;
12224         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12225
12226         if (!shared_rss)
12227                 return rte_flow_error_set(error, EINVAL,
12228                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12229                                           "invalid shared action to update");
12230         queue = mlx5_malloc(MLX5_MEM_ZERO,
12231                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12232                             0, SOCKET_ID_ANY);
12233         if (!queue)
12234                 return rte_flow_error_set(error, ENOMEM,
12235                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12236                                           NULL,
12237                                           "cannot allocate resource memory");
12238         memcpy(queue, action_conf->queue, queue_size);
12239         MLX5_ASSERT(shared_rss->ind_tbl);
12240         rte_spinlock_lock(&shared_rss->action_rss_sl);
12241         queue_old = shared_rss->ind_tbl->queues;
12242         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
12243                                         queue, action_conf->queue_num, true);
12244         if (ret) {
12245                 mlx5_free(queue);
12246                 ret = rte_flow_error_set(error, rte_errno,
12247                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12248                                           "cannot update indirection table");
12249         } else {
12250                 mlx5_free(queue_old);
12251                 shared_rss->origin.queue = queue;
12252                 shared_rss->origin.queue_num = action_conf->queue_num;
12253         }
12254         rte_spinlock_unlock(&shared_rss->action_rss_sl);
12255         return ret;
12256 }
12257
12258 /**
12259  * Updates in place shared action configuration, lock free,
12260  * (mutex should be acquired by caller).
12261  *
12262  * @param[in] dev
12263  *   Pointer to the Ethernet device structure.
12264  * @param[in] action
12265  *   The shared action object to be updated.
12266  * @param[in] action_conf
12267  *   Action specification used to modify *action*.
12268  *   *action_conf* should be of type correlating with type of the *action*,
12269  *   otherwise considered as invalid.
12270  * @param[out] error
12271  *   Perform verbose error reporting if not NULL. Initialized in case of
12272  *   error only.
12273  *
12274  * @return
12275  *   0 on success, otherwise negative errno value.
12276  */
12277 static int
12278 flow_dv_action_update(struct rte_eth_dev *dev,
12279                         struct rte_flow_shared_action *action,
12280                         const void *action_conf,
12281                         struct rte_flow_error *err)
12282 {
12283         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12284         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12285         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12286
12287         switch (type) {
12288         case MLX5_SHARED_ACTION_TYPE_RSS:
12289                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
12290         default:
12291                 return rte_flow_error_set(err, ENOTSUP,
12292                                           RTE_FLOW_ERROR_TYPE_ACTION,
12293                                           NULL,
12294                                           "action type update not supported");
12295         }
12296 }
12297
12298 static int
12299 flow_dv_action_query(struct rte_eth_dev *dev,
12300                      const struct rte_flow_shared_action *action, void *data,
12301                      struct rte_flow_error *error)
12302 {
12303         struct mlx5_age_param *age_param;
12304         struct rte_flow_query_age *resp;
12305         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12306         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12307         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12308
12309         switch (type) {
12310         case MLX5_SHARED_ACTION_TYPE_AGE:
12311                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
12312                 resp = data;
12313                 resp->aged = __atomic_load_n(&age_param->state,
12314                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
12315                                                                           1 : 0;
12316                 resp->sec_since_last_hit_valid = !resp->aged;
12317                 if (resp->sec_since_last_hit_valid)
12318                         resp->sec_since_last_hit = __atomic_load_n
12319                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12320                 return 0;
12321         default:
12322                 return rte_flow_error_set(error, ENOTSUP,
12323                                           RTE_FLOW_ERROR_TYPE_ACTION,
12324                                           NULL,
12325                                           "action type query not supported");
12326         }
12327 }
12328
12329 /**
12330  * Query a dv flow  rule for its statistics via devx.
12331  *
12332  * @param[in] dev
12333  *   Pointer to Ethernet device.
12334  * @param[in] flow
12335  *   Pointer to the sub flow.
12336  * @param[out] data
12337  *   data retrieved by the query.
12338  * @param[out] error
12339  *   Perform verbose error reporting if not NULL.
12340  *
12341  * @return
12342  *   0 on success, a negative errno value otherwise and rte_errno is set.
12343  */
12344 static int
12345 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
12346                     void *data, struct rte_flow_error *error)
12347 {
12348         struct mlx5_priv *priv = dev->data->dev_private;
12349         struct rte_flow_query_count *qc = data;
12350
12351         if (!priv->config.devx)
12352                 return rte_flow_error_set(error, ENOTSUP,
12353                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12354                                           NULL,
12355                                           "counters are not supported");
12356         if (flow->counter) {
12357                 uint64_t pkts, bytes;
12358                 struct mlx5_flow_counter *cnt;
12359
12360                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
12361                                                  NULL);
12362                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
12363                                                &bytes);
12364
12365                 if (err)
12366                         return rte_flow_error_set(error, -err,
12367                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12368                                         NULL, "cannot read counters");
12369                 qc->hits_set = 1;
12370                 qc->bytes_set = 1;
12371                 qc->hits = pkts - cnt->hits;
12372                 qc->bytes = bytes - cnt->bytes;
12373                 if (qc->reset) {
12374                         cnt->hits = pkts;
12375                         cnt->bytes = bytes;
12376                 }
12377                 return 0;
12378         }
12379         return rte_flow_error_set(error, EINVAL,
12380                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12381                                   NULL,
12382                                   "counters are not available");
12383 }
12384
12385 /**
12386  * Query a flow rule AGE action for aging information.
12387  *
12388  * @param[in] dev
12389  *   Pointer to Ethernet device.
12390  * @param[in] flow
12391  *   Pointer to the sub flow.
12392  * @param[out] data
12393  *   data retrieved by the query.
12394  * @param[out] error
12395  *   Perform verbose error reporting if not NULL.
12396  *
12397  * @return
12398  *   0 on success, a negative errno value otherwise and rte_errno is set.
12399  */
12400 static int
12401 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
12402                   void *data, struct rte_flow_error *error)
12403 {
12404         struct rte_flow_query_age *resp = data;
12405         struct mlx5_age_param *age_param;
12406
12407         if (flow->age) {
12408                 struct mlx5_aso_age_action *act =
12409                                      flow_aso_age_get_by_idx(dev, flow->age);
12410
12411                 age_param = &act->age_params;
12412         } else if (flow->counter) {
12413                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
12414
12415                 if (!age_param || !age_param->timeout)
12416                         return rte_flow_error_set
12417                                         (error, EINVAL,
12418                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12419                                          NULL, "cannot read age data");
12420         } else {
12421                 return rte_flow_error_set(error, EINVAL,
12422                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12423                                           NULL, "age data not available");
12424         }
12425         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
12426                                      AGE_TMOUT ? 1 : 0;
12427         resp->sec_since_last_hit_valid = !resp->aged;
12428         if (resp->sec_since_last_hit_valid)
12429                 resp->sec_since_last_hit = __atomic_load_n
12430                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
12431         return 0;
12432 }
12433
12434 /**
12435  * Query a flow.
12436  *
12437  * @see rte_flow_query()
12438  * @see rte_flow_ops
12439  */
12440 static int
12441 flow_dv_query(struct rte_eth_dev *dev,
12442               struct rte_flow *flow __rte_unused,
12443               const struct rte_flow_action *actions __rte_unused,
12444               void *data __rte_unused,
12445               struct rte_flow_error *error __rte_unused)
12446 {
12447         int ret = -EINVAL;
12448
12449         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
12450                 switch (actions->type) {
12451                 case RTE_FLOW_ACTION_TYPE_VOID:
12452                         break;
12453                 case RTE_FLOW_ACTION_TYPE_COUNT:
12454                         ret = flow_dv_query_count(dev, flow, data, error);
12455                         break;
12456                 case RTE_FLOW_ACTION_TYPE_AGE:
12457                         ret = flow_dv_query_age(dev, flow, data, error);
12458                         break;
12459                 default:
12460                         return rte_flow_error_set(error, ENOTSUP,
12461                                                   RTE_FLOW_ERROR_TYPE_ACTION,
12462                                                   actions,
12463                                                   "action not supported");
12464                 }
12465         }
12466         return ret;
12467 }
12468
12469 /**
12470  * Destroy the meter table set.
12471  * Lock free, (mutex should be acquired by caller).
12472  *
12473  * @param[in] dev
12474  *   Pointer to Ethernet device.
12475  * @param[in] tbl
12476  *   Pointer to the meter table set.
12477  *
12478  * @return
12479  *   Always 0.
12480  */
12481 static int
12482 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
12483                         struct mlx5_meter_domains_infos *tbl)
12484 {
12485         struct mlx5_priv *priv = dev->data->dev_private;
12486         struct mlx5_meter_domains_infos *mtd =
12487                                 (struct mlx5_meter_domains_infos *)tbl;
12488
12489         if (!mtd || !priv->config.dv_flow_en)
12490                 return 0;
12491         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
12492                 claim_zero(mlx5_flow_os_destroy_flow
12493                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
12494         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
12495                 claim_zero(mlx5_flow_os_destroy_flow
12496                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
12497         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12498                 claim_zero(mlx5_flow_os_destroy_flow
12499                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12500         if (mtd->egress.color_matcher)
12501                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12502                            (mtd->egress.color_matcher));
12503         if (mtd->egress.any_matcher)
12504                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12505                            (mtd->egress.any_matcher));
12506         if (mtd->egress.tbl)
12507                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12508         if (mtd->egress.sfx_tbl)
12509                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12510         if (mtd->ingress.color_matcher)
12511                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12512                            (mtd->ingress.color_matcher));
12513         if (mtd->ingress.any_matcher)
12514                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12515                            (mtd->ingress.any_matcher));
12516         if (mtd->ingress.tbl)
12517                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12518         if (mtd->ingress.sfx_tbl)
12519                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12520                                              mtd->ingress.sfx_tbl);
12521         if (mtd->transfer.color_matcher)
12522                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12523                            (mtd->transfer.color_matcher));
12524         if (mtd->transfer.any_matcher)
12525                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12526                            (mtd->transfer.any_matcher));
12527         if (mtd->transfer.tbl)
12528                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12529         if (mtd->transfer.sfx_tbl)
12530                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12531                                              mtd->transfer.sfx_tbl);
12532         if (mtd->drop_actn)
12533                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12534         mlx5_free(mtd);
12535         return 0;
12536 }
12537
12538 /* Number of meter flow actions, count and jump or count and drop. */
12539 #define METER_ACTIONS 2
12540
12541 /**
12542  * Create specify domain meter table and suffix table.
12543  *
12544  * @param[in] dev
12545  *   Pointer to Ethernet device.
12546  * @param[in,out] mtb
12547  *   Pointer to DV meter table set.
12548  * @param[in] egress
12549  *   Table attribute.
12550  * @param[in] transfer
12551  *   Table attribute.
12552  * @param[in] color_reg_c_idx
12553  *   Reg C index for color match.
12554  *
12555  * @return
12556  *   0 on success, -1 otherwise and rte_errno is set.
12557  */
12558 static int
12559 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12560                            struct mlx5_meter_domains_infos *mtb,
12561                            uint8_t egress, uint8_t transfer,
12562                            uint32_t color_reg_c_idx)
12563 {
12564         struct mlx5_priv *priv = dev->data->dev_private;
12565         struct mlx5_dev_ctx_shared *sh = priv->sh;
12566         struct mlx5_flow_dv_match_params mask = {
12567                 .size = sizeof(mask.buf),
12568         };
12569         struct mlx5_flow_dv_match_params value = {
12570                 .size = sizeof(value.buf),
12571         };
12572         struct mlx5dv_flow_matcher_attr dv_attr = {
12573                 .type = IBV_FLOW_ATTR_NORMAL,
12574                 .priority = 0,
12575                 .match_criteria_enable = 0,
12576                 .match_mask = (void *)&mask,
12577         };
12578         void *actions[METER_ACTIONS];
12579         struct mlx5_meter_domain_info *dtb;
12580         struct rte_flow_error error;
12581         int i = 0;
12582         int ret;
12583
12584         if (transfer)
12585                 dtb = &mtb->transfer;
12586         else if (egress)
12587                 dtb = &mtb->egress;
12588         else
12589                 dtb = &mtb->ingress;
12590         /* Create the meter table with METER level. */
12591         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12592                                             egress, transfer, false, NULL, 0,
12593                                             0, &error);
12594         if (!dtb->tbl) {
12595                 DRV_LOG(ERR, "Failed to create meter policer table.");
12596                 return -1;
12597         }
12598         /* Create the meter suffix table with SUFFIX level. */
12599         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12600                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12601                                             egress, transfer, false, NULL, 0,
12602                                             0, &error);
12603         if (!dtb->sfx_tbl) {
12604                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12605                 return -1;
12606         }
12607         /* Create matchers, Any and Color. */
12608         dv_attr.priority = 3;
12609         dv_attr.match_criteria_enable = 0;
12610         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12611                                                &dtb->any_matcher);
12612         if (ret) {
12613                 DRV_LOG(ERR, "Failed to create meter"
12614                              " policer default matcher.");
12615                 goto error_exit;
12616         }
12617         dv_attr.priority = 0;
12618         dv_attr.match_criteria_enable =
12619                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12620         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12621                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12622         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12623                                                &dtb->color_matcher);
12624         if (ret) {
12625                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12626                 goto error_exit;
12627         }
12628         if (mtb->count_actns[RTE_MTR_DROPPED])
12629                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12630         actions[i++] = mtb->drop_actn;
12631         /* Default rule: lowest priority, match any, actions: drop. */
12632         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12633                                        actions,
12634                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12635         if (ret) {
12636                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12637                 goto error_exit;
12638         }
12639         return 0;
12640 error_exit:
12641         return -1;
12642 }
12643
12644 /**
12645  * Create the needed meter and suffix tables.
12646  * Lock free, (mutex should be acquired by caller).
12647  *
12648  * @param[in] dev
12649  *   Pointer to Ethernet device.
12650  * @param[in] fm
12651  *   Pointer to the flow meter.
12652  *
12653  * @return
12654  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12655  */
12656 static struct mlx5_meter_domains_infos *
12657 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12658                        const struct mlx5_flow_meter *fm)
12659 {
12660         struct mlx5_priv *priv = dev->data->dev_private;
12661         struct mlx5_meter_domains_infos *mtb;
12662         int ret;
12663         int i;
12664
12665         if (!priv->mtr_en) {
12666                 rte_errno = ENOTSUP;
12667                 return NULL;
12668         }
12669         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12670         if (!mtb) {
12671                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12672                 return NULL;
12673         }
12674         /* Create meter count actions */
12675         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12676                 struct mlx5_flow_counter *cnt;
12677                 if (!fm->policer_stats.cnt[i])
12678                         continue;
12679                 cnt = flow_dv_counter_get_by_idx(dev,
12680                       fm->policer_stats.cnt[i], NULL);
12681                 mtb->count_actns[i] = cnt->action;
12682         }
12683         /* Create drop action. */
12684         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12685         if (ret) {
12686                 DRV_LOG(ERR, "Failed to create drop action.");
12687                 goto error_exit;
12688         }
12689         /* Egress meter table. */
12690         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12691         if (ret) {
12692                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12693                 goto error_exit;
12694         }
12695         /* Ingress meter table. */
12696         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12697         if (ret) {
12698                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12699                 goto error_exit;
12700         }
12701         /* FDB meter table. */
12702         if (priv->config.dv_esw_en) {
12703                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12704                                                  priv->mtr_color_reg);
12705                 if (ret) {
12706                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12707                         goto error_exit;
12708                 }
12709         }
12710         return mtb;
12711 error_exit:
12712         flow_dv_destroy_mtr_tbl(dev, mtb);
12713         return NULL;
12714 }
12715
12716 /**
12717  * Destroy domain policer rule.
12718  *
12719  * @param[in] dt
12720  *   Pointer to domain table.
12721  */
12722 static void
12723 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12724 {
12725         int i;
12726
12727         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12728                 if (dt->policer_rules[i]) {
12729                         claim_zero(mlx5_flow_os_destroy_flow
12730                                    (dt->policer_rules[i]));
12731                         dt->policer_rules[i] = NULL;
12732                 }
12733         }
12734         if (dt->jump_actn) {
12735                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12736                 dt->jump_actn = NULL;
12737         }
12738 }
12739
12740 /**
12741  * Destroy policer rules.
12742  *
12743  * @param[in] dev
12744  *   Pointer to Ethernet device.
12745  * @param[in] fm
12746  *   Pointer to flow meter structure.
12747  * @param[in] attr
12748  *   Pointer to flow attributes.
12749  *
12750  * @return
12751  *   Always 0.
12752  */
12753 static int
12754 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12755                               const struct mlx5_flow_meter *fm,
12756                               const struct rte_flow_attr *attr)
12757 {
12758         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12759
12760         if (!mtb)
12761                 return 0;
12762         if (attr->egress)
12763                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12764         if (attr->ingress)
12765                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12766         if (attr->transfer)
12767                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12768         return 0;
12769 }
12770
12771 /**
12772  * Create specify domain meter policer rule.
12773  *
12774  * @param[in] fm
12775  *   Pointer to flow meter structure.
12776  * @param[in] mtb
12777  *   Pointer to DV meter table set.
12778  * @param[in] mtr_reg_c
12779  *   Color match REG_C.
12780  *
12781  * @return
12782  *   0 on success, -1 otherwise.
12783  */
12784 static int
12785 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12786                                     struct mlx5_meter_domain_info *dtb,
12787                                     uint8_t mtr_reg_c)
12788 {
12789         struct mlx5_flow_dv_match_params matcher = {
12790                 .size = sizeof(matcher.buf),
12791         };
12792         struct mlx5_flow_dv_match_params value = {
12793                 .size = sizeof(value.buf),
12794         };
12795         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12796         void *actions[METER_ACTIONS];
12797         int i;
12798         int ret = 0;
12799
12800         /* Create jump action. */
12801         if (!dtb->jump_actn)
12802                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12803                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12804         if (ret) {
12805                 DRV_LOG(ERR, "Failed to create policer jump action.");
12806                 goto error;
12807         }
12808         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12809                 int j = 0;
12810
12811                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12812                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12813                 if (mtb->count_actns[i])
12814                         actions[j++] = mtb->count_actns[i];
12815                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12816                         actions[j++] = mtb->drop_actn;
12817                 else
12818                         actions[j++] = dtb->jump_actn;
12819                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12820                                                (void *)&value, j, actions,
12821                                                &dtb->policer_rules[i]);
12822                 if (ret) {
12823                         DRV_LOG(ERR, "Failed to create policer rule.");
12824                         goto error;
12825                 }
12826         }
12827         return 0;
12828 error:
12829         rte_errno = errno;
12830         return -1;
12831 }
12832
12833 /**
12834  * Create policer rules.
12835  *
12836  * @param[in] dev
12837  *   Pointer to Ethernet device.
12838  * @param[in] fm
12839  *   Pointer to flow meter structure.
12840  * @param[in] attr
12841  *   Pointer to flow attributes.
12842  *
12843  * @return
12844  *   0 on success, -1 otherwise.
12845  */
12846 static int
12847 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12848                              struct mlx5_flow_meter *fm,
12849                              const struct rte_flow_attr *attr)
12850 {
12851         struct mlx5_priv *priv = dev->data->dev_private;
12852         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12853         int ret;
12854
12855         if (attr->egress) {
12856                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12857                                                 priv->mtr_color_reg);
12858                 if (ret) {
12859                         DRV_LOG(ERR, "Failed to create egress policer.");
12860                         goto error;
12861                 }
12862         }
12863         if (attr->ingress) {
12864                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12865                                                 priv->mtr_color_reg);
12866                 if (ret) {
12867                         DRV_LOG(ERR, "Failed to create ingress policer.");
12868                         goto error;
12869                 }
12870         }
12871         if (attr->transfer) {
12872                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12873                                                 priv->mtr_color_reg);
12874                 if (ret) {
12875                         DRV_LOG(ERR, "Failed to create transfer policer.");
12876                         goto error;
12877                 }
12878         }
12879         return 0;
12880 error:
12881         flow_dv_destroy_policer_rules(dev, fm, attr);
12882         return -1;
12883 }
12884
12885 /**
12886  * Validate the batch counter support in root table.
12887  *
12888  * Create a simple flow with invalid counter and drop action on root table to
12889  * validate if batch counter with offset on root table is supported or not.
12890  *
12891  * @param[in] dev
12892  *   Pointer to rte_eth_dev structure.
12893  *
12894  * @return
12895  *   0 on success, a negative errno value otherwise and rte_errno is set.
12896  */
12897 int
12898 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12899 {
12900         struct mlx5_priv *priv = dev->data->dev_private;
12901         struct mlx5_dev_ctx_shared *sh = priv->sh;
12902         struct mlx5_flow_dv_match_params mask = {
12903                 .size = sizeof(mask.buf),
12904         };
12905         struct mlx5_flow_dv_match_params value = {
12906                 .size = sizeof(value.buf),
12907         };
12908         struct mlx5dv_flow_matcher_attr dv_attr = {
12909                 .type = IBV_FLOW_ATTR_NORMAL,
12910                 .priority = 0,
12911                 .match_criteria_enable = 0,
12912                 .match_mask = (void *)&mask,
12913         };
12914         void *actions[2] = { 0 };
12915         struct mlx5_flow_tbl_resource *tbl = NULL;
12916         struct mlx5_devx_obj *dcs = NULL;
12917         void *matcher = NULL;
12918         void *flow = NULL;
12919         int ret = -1;
12920
12921         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12922         if (!tbl)
12923                 goto err;
12924         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12925         if (!dcs)
12926                 goto err;
12927         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12928                                                     &actions[0]);
12929         if (ret)
12930                 goto err;
12931         actions[1] = priv->drop_queue.hrxq->action;
12932         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12933         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12934                                                &matcher);
12935         if (ret)
12936                 goto err;
12937         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12938                                        actions, &flow);
12939 err:
12940         /*
12941          * If batch counter with offset is not supported, the driver will not
12942          * validate the invalid offset value, flow create should success.
12943          * In this case, it means batch counter is not supported in root table.
12944          *
12945          * Otherwise, if flow create is failed, counter offset is supported.
12946          */
12947         if (flow) {
12948                 DRV_LOG(INFO, "Batch counter is not supported in root "
12949                               "table. Switch to fallback mode.");
12950                 rte_errno = ENOTSUP;
12951                 ret = -rte_errno;
12952                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12953         } else {
12954                 /* Check matcher to make sure validate fail at flow create. */
12955                 if (!matcher || (matcher && errno != EINVAL))
12956                         DRV_LOG(ERR, "Unexpected error in counter offset "
12957                                      "support detection");
12958                 ret = 0;
12959         }
12960         if (actions[0])
12961                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12962         if (matcher)
12963                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12964         if (tbl)
12965                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12966         if (dcs)
12967                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12968         return ret;
12969 }
12970
12971 /**
12972  * Query a devx counter.
12973  *
12974  * @param[in] dev
12975  *   Pointer to the Ethernet device structure.
12976  * @param[in] cnt
12977  *   Index to the flow counter.
12978  * @param[in] clear
12979  *   Set to clear the counter statistics.
12980  * @param[out] pkts
12981  *   The statistics value of packets.
12982  * @param[out] bytes
12983  *   The statistics value of bytes.
12984  *
12985  * @return
12986  *   0 on success, otherwise return -1.
12987  */
12988 static int
12989 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12990                       uint64_t *pkts, uint64_t *bytes)
12991 {
12992         struct mlx5_priv *priv = dev->data->dev_private;
12993         struct mlx5_flow_counter *cnt;
12994         uint64_t inn_pkts, inn_bytes;
12995         int ret;
12996
12997         if (!priv->config.devx)
12998                 return -1;
12999
13000         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13001         if (ret)
13002                 return -1;
13003         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13004         *pkts = inn_pkts - cnt->hits;
13005         *bytes = inn_bytes - cnt->bytes;
13006         if (clear) {
13007                 cnt->hits = inn_pkts;
13008                 cnt->bytes = inn_bytes;
13009         }
13010         return 0;
13011 }
13012
13013 /**
13014  * Get aged-out flows.
13015  *
13016  * @param[in] dev
13017  *   Pointer to the Ethernet device structure.
13018  * @param[in] context
13019  *   The address of an array of pointers to the aged-out flows contexts.
13020  * @param[in] nb_contexts
13021  *   The length of context array pointers.
13022  * @param[out] error
13023  *   Perform verbose error reporting if not NULL. Initialized in case of
13024  *   error only.
13025  *
13026  * @return
13027  *   how many contexts get in success, otherwise negative errno value.
13028  *   if nb_contexts is 0, return the amount of all aged contexts.
13029  *   if nb_contexts is not 0 , return the amount of aged flows reported
13030  *   in the context array.
13031  * @note: only stub for now
13032  */
13033 static int
13034 flow_get_aged_flows(struct rte_eth_dev *dev,
13035                     void **context,
13036                     uint32_t nb_contexts,
13037                     struct rte_flow_error *error)
13038 {
13039         struct mlx5_priv *priv = dev->data->dev_private;
13040         struct mlx5_age_info *age_info;
13041         struct mlx5_age_param *age_param;
13042         struct mlx5_flow_counter *counter;
13043         struct mlx5_aso_age_action *act;
13044         int nb_flows = 0;
13045
13046         if (nb_contexts && !context)
13047                 return rte_flow_error_set(error, EINVAL,
13048                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13049                                           NULL, "empty context");
13050         age_info = GET_PORT_AGE_INFO(priv);
13051         rte_spinlock_lock(&age_info->aged_sl);
13052         LIST_FOREACH(act, &age_info->aged_aso, next) {
13053                 nb_flows++;
13054                 if (nb_contexts) {
13055                         context[nb_flows - 1] =
13056                                                 act->age_params.context;
13057                         if (!(--nb_contexts))
13058                                 break;
13059                 }
13060         }
13061         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13062                 nb_flows++;
13063                 if (nb_contexts) {
13064                         age_param = MLX5_CNT_TO_AGE(counter);
13065                         context[nb_flows - 1] = age_param->context;
13066                         if (!(--nb_contexts))
13067                                 break;
13068                 }
13069         }
13070         rte_spinlock_unlock(&age_info->aged_sl);
13071         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13072         return nb_flows;
13073 }
13074
13075 /*
13076  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13077  */
13078 static uint32_t
13079 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13080 {
13081         return flow_dv_counter_alloc(dev, 0);
13082 }
13083
13084 /**
13085  * Validate shared action.
13086  * Dispatcher for action type specific validation.
13087  *
13088  * @param[in] dev
13089  *   Pointer to the Ethernet device structure.
13090  * @param[in] conf
13091  *   Shared action configuration.
13092  * @param[in] action
13093  *   The shared action object to validate.
13094  * @param[out] error
13095  *   Perform verbose error reporting if not NULL. Initialized in case of
13096  *   error only.
13097  *
13098  * @return
13099  *   0 on success, otherwise negative errno value.
13100  */
13101 static int
13102 flow_dv_action_validate(struct rte_eth_dev *dev,
13103                         const struct rte_flow_shared_action_conf *conf,
13104                         const struct rte_flow_action *action,
13105                         struct rte_flow_error *err)
13106 {
13107         struct mlx5_priv *priv = dev->data->dev_private;
13108
13109         RTE_SET_USED(conf);
13110         switch (action->type) {
13111         case RTE_FLOW_ACTION_TYPE_RSS:
13112                 return mlx5_validate_action_rss(dev, action, err);
13113         case RTE_FLOW_ACTION_TYPE_AGE:
13114                 if (!priv->sh->aso_age_mng)
13115                         return rte_flow_error_set(err, ENOTSUP,
13116                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13117                                                 NULL,
13118                                              "shared age action not supported");
13119                 return flow_dv_validate_action_age(0, action, dev, err);
13120         default:
13121                 return rte_flow_error_set(err, ENOTSUP,
13122                                           RTE_FLOW_ERROR_TYPE_ACTION,
13123                                           NULL,
13124                                           "action type not supported");
13125         }
13126 }
13127
13128 static int
13129 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13130 {
13131         struct mlx5_priv *priv = dev->data->dev_private;
13132         int ret = 0;
13133
13134         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13135                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13136                                                 flags);
13137                 if (ret != 0)
13138                         return ret;
13139         }
13140         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13141                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13142                 if (ret != 0)
13143                         return ret;
13144         }
13145         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13146                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13147                 if (ret != 0)
13148                         return ret;
13149         }
13150         return 0;
13151 }
13152
13153 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13154         .validate = flow_dv_validate,
13155         .prepare = flow_dv_prepare,
13156         .translate = flow_dv_translate,
13157         .apply = flow_dv_apply,
13158         .remove = flow_dv_remove,
13159         .destroy = flow_dv_destroy,
13160         .query = flow_dv_query,
13161         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13162         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13163         .create_policer_rules = flow_dv_create_policer_rules,
13164         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13165         .counter_alloc = flow_dv_counter_allocate,
13166         .counter_free = flow_dv_counter_free,
13167         .counter_query = flow_dv_counter_query,
13168         .get_aged_flows = flow_get_aged_flows,
13169         .action_validate = flow_dv_action_validate,
13170         .action_create = flow_dv_action_create,
13171         .action_destroy = flow_dv_action_destroy,
13172         .action_update = flow_dv_action_update,
13173         .action_query = flow_dv_action_query,
13174         .sync_domain = flow_dv_sync_domain,
13175 };
13176
13177 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13178