drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rx.h"
  36 #include "mlx5_tx.h"
  37 #include "rte_pmd_mlx5.h"
  38
  39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  40
  41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  43 #endif
  44
  45 #ifndef HAVE_MLX5DV_DR_ESWITCH
  46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  48 #endif
  49 #endif
  50
  51 #ifndef HAVE_MLX5DV_DR
  52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  53 #endif
  54
  55 /* VLAN header definitions */
  56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  61
  62 union flow_dv_attr {
  63         struct {
  64                 uint32_t valid:1;
  65                 uint32_t ipv4:1;
  66                 uint32_t ipv6:1;
  67                 uint32_t tcp:1;
  68                 uint32_t udp:1;
  69                 uint32_t reserved:27;
  70         };
  71         uint32_t attr;
  72 };
  73
  74 static int
  75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  76                              struct mlx5_flow_tbl_resource *tbl);
  77
  78 static int
  79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  80                                      uint32_t encap_decap_idx);
  81
  82 static int
  83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  84                                         uint32_t port_id);
  85 static void
  86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  87
  88 static int
  89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  90                                   uint32_t rix_jump);
  91
  92 /**
  93  * Initialize flow attributes structure according to flow items' types.
  94  *
  95  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  96  * mode. For tunnel mode, the items to be modified are the outermost ones.
  97  *
  98  * @param[in] item
  99  *   Pointer to item specification.
 100  * @param[out] attr
 101  *   Pointer to flow attributes structure.
 102  * @param[in] dev_flow
 103  *   Pointer to the sub flow.
 104  * @param[in] tunnel_decap
 105  *   Whether action is after tunnel decapsulation.
 106  */
 107 static void
 108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 109                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 110 {
 111         uint64_t layers = dev_flow->handle->layers;
 112
 113         /*
 114          * If layers is already initialized, it means this dev_flow is the
 115          * suffix flow, the layers flags is set by the prefix flow. Need to
 116          * use the layer flags from prefix flow as the suffix flow may not
 117          * have the user defined items as the flow is split.
 118          */
 119         if (layers) {
 120                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 121                         attr->ipv4 = 1;
 122                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 123                         attr->ipv6 = 1;
 124                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 125                         attr->tcp = 1;
 126                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 127                         attr->udp = 1;
 128                 attr->valid = 1;
 129                 return;
 130         }
 131         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 132                 uint8_t next_protocol = 0xff;
 133                 switch (item->type) {
 134                 case RTE_FLOW_ITEM_TYPE_GRE:
 135                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 137                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 138                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 139                 case RTE_FLOW_ITEM_TYPE_MPLS:
 140                         if (tunnel_decap)
 141                                 attr->attr = 0;
 142                         break;
 143                 case RTE_FLOW_ITEM_TYPE_IPV4:
 144                         if (!attr->ipv6)
 145                                 attr->ipv4 = 1;
 146                         if (item->mask != NULL &&
 147                             ((const struct rte_flow_item_ipv4 *)
 148                             item->mask)->hdr.next_proto_id)
 149                                 next_protocol =
 150                                     ((const struct rte_flow_item_ipv4 *)
 151                                       (item->spec))->hdr.next_proto_id &
 152                                     ((const struct rte_flow_item_ipv4 *)
 153                                       (item->mask))->hdr.next_proto_id;
 154                         if ((next_protocol == IPPROTO_IPIP ||
 155                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 156                                 attr->attr = 0;
 157                         break;
 158                 case RTE_FLOW_ITEM_TYPE_IPV6:
 159                         if (!attr->ipv4)
 160                                 attr->ipv6 = 1;
 161                         if (item->mask != NULL &&
 162                             ((const struct rte_flow_item_ipv6 *)
 163                             item->mask)->hdr.proto)
 164                                 next_protocol =
 165                                     ((const struct rte_flow_item_ipv6 *)
 166                                       (item->spec))->hdr.proto &
 167                                     ((const struct rte_flow_item_ipv6 *)
 168                                       (item->mask))->hdr.proto;
 169                         if ((next_protocol == IPPROTO_IPIP ||
 170                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 171                                 attr->attr = 0;
 172                         break;
 173                 case RTE_FLOW_ITEM_TYPE_UDP:
 174                         if (!attr->tcp)
 175                                 attr->udp = 1;
 176                         break;
 177                 case RTE_FLOW_ITEM_TYPE_TCP:
 178                         if (!attr->udp)
 179                                 attr->tcp = 1;
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         }
 185         attr->valid = 1;
 186 }
 187
 188 /**
 189  * Convert rte_mtr_color to mlx5 color.
 190  *
 191  * @param[in] rcol
 192  *   rte_mtr_color.
 193  *
 194  * @return
 195  *   mlx5 color.
 196  */
 197 static int
 198 rte_col_2_mlx5_col(enum rte_color rcol)
 199 {
 200         switch (rcol) {
 201         case RTE_COLOR_GREEN:
 202                 return MLX5_FLOW_COLOR_GREEN;
 203         case RTE_COLOR_YELLOW:
 204                 return MLX5_FLOW_COLOR_YELLOW;
 205         case RTE_COLOR_RED:
 206                 return MLX5_FLOW_COLOR_RED;
 207         default:
 208                 break;
 209         }
 210         return MLX5_FLOW_COLOR_UNDEFINED;
 211 }
 212
 213 struct field_modify_info {
 214         uint32_t size; /* Size of field in protocol header, in bytes. */
 215         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 216         enum mlx5_modification_field id;
 217 };
 218
 219 struct field_modify_info modify_eth[] = {
 220         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 221         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 222         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 223         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 224         {0, 0, 0},
 225 };
 226
 227 struct field_modify_info modify_vlan_out_first_vid[] = {
 228         /* Size in bits !!! */
 229         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 230         {0, 0, 0},
 231 };
 232
 233 struct field_modify_info modify_ipv4[] = {
 234         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 235         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 236         {4, 12, MLX5_MODI_OUT_SIPV4},
 237         {4, 16, MLX5_MODI_OUT_DIPV4},
 238         {0, 0, 0},
 239 };
 240
 241 struct field_modify_info modify_ipv6[] = {
 242         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 243         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 244         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 245         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 246         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 247         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 248         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 249         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 250         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 251         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 252         {0, 0, 0},
 253 };
 254
 255 struct field_modify_info modify_udp[] = {
 256         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 257         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 258         {0, 0, 0},
 259 };
 260
 261 struct field_modify_info modify_tcp[] = {
 262         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 263         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 264         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 265         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 266         {0, 0, 0},
 267 };
 268
 269 static void
 270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 271                           uint8_t next_protocol, uint64_t *item_flags,
 272                           int *tunnel)
 273 {
 274         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 275                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 276         if (next_protocol == IPPROTO_IPIP) {
 277                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 278                 *tunnel = 1;
 279         }
 280         if (next_protocol == IPPROTO_IPV6) {
 281                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 282                 *tunnel = 1;
 283         }
 284 }
 285
 286 /* Update VLAN's VID/PCP based on input rte_flow_action.
 287  *
 288  * @param[in] action
 289  *   Pointer to struct rte_flow_action.
 290  * @param[out] vlan
 291  *   Pointer to struct rte_vlan_hdr.
 292  */
 293 static void
 294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 295                          struct rte_vlan_hdr *vlan)
 296 {
 297         uint16_t vlan_tci;
 298         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 299                 vlan_tci =
 300                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 301                                                action->conf)->vlan_pcp;
 302                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 303                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 304                 vlan->vlan_tci |= vlan_tci;
 305         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 306                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 307                 vlan->vlan_tci |= rte_be_to_cpu_16
 308                     (((const struct rte_flow_action_of_set_vlan_vid *)
 309                                              action->conf)->vlan_vid);
 310         }
 311 }
 312
 313 /**
 314  * Fetch 1, 2, 3 or 4 byte field from the byte array
 315  * and return as unsigned integer in host-endian format.
 316  *
 317  * @param[in] data
 318  *   Pointer to data array.
 319  * @param[in] size
 320  *   Size of field to extract.
 321  *
 322  * @return
 323  *   converted field in host endian format.
 324  */
 325 static inline uint32_t
 326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 327 {
 328         uint32_t ret;
 329
 330         switch (size) {
 331         case 1:
 332                 ret = *data;
 333                 break;
 334         case 2:
 335                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 336                 break;
 337         case 3:
 338                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 339                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 340                 break;
 341         case 4:
 342                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 343                 break;
 344         default:
 345                 MLX5_ASSERT(false);
 346                 ret = 0;
 347                 break;
 348         }
 349         return ret;
 350 }
 351
 352 /**
 353  * Convert modify-header action to DV specification.
 354  *
 355  * Data length of each action is determined by provided field description
 356  * and the item mask. Data bit offset and width of each action is determined
 357  * by provided item mask.
 358  *
 359  * @param[in] item
 360  *   Pointer to item specification.
 361  * @param[in] field
 362  *   Pointer to field modification information.
 363  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 365  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 366  * @param[in] dcopy
 367  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 368  *   Negative offset value sets the same offset as source offset.
 369  *   size field is ignored, value is taken from source field.
 370  * @param[in,out] resource
 371  *   Pointer to the modify-header resource.
 372  * @param[in] type
 373  *   Type of modification.
 374  * @param[out] error
 375  *   Pointer to the error structure.
 376  *
 377  * @return
 378  *   0 on success, a negative errno value otherwise and rte_errno is set.
 379  */
 380 static int
 381 flow_dv_convert_modify_action(struct rte_flow_item *item,
 382                               struct field_modify_info *field,
 383                               struct field_modify_info *dcopy,
 384                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 385                               uint32_t type, struct rte_flow_error *error)
 386 {
 387         uint32_t i = resource->actions_num;
 388         struct mlx5_modification_cmd *actions = resource->actions;
 389
 390         /*
 391          * The item and mask are provided in big-endian format.
 392          * The fields should be presented as in big-endian format either.
 393          * Mask must be always present, it defines the actual field width.
 394          */
 395         MLX5_ASSERT(item->mask);
 396         MLX5_ASSERT(field->size);
 397         do {
 398                 unsigned int size_b;
 399                 unsigned int off_b;
 400                 uint32_t mask;
 401                 uint32_t data;
 402
 403                 if (i >= MLX5_MAX_MODIFY_NUM)
 404                         return rte_flow_error_set(error, EINVAL,
 405                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 406                                  "too many items to modify");
 407                 /* Fetch variable byte size mask from the array. */
 408                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 409                                            field->offset, field->size);
 410                 if (!mask) {
 411                         ++field;
 412                         continue;
 413                 }
 414                 /* Deduce actual data width in bits from mask value. */
 415                 off_b = rte_bsf32(mask);
 416                 size_b = sizeof(uint32_t) * CHAR_BIT -
 417                          off_b - __builtin_clz(mask);
 418                 MLX5_ASSERT(size_b);
 419                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 420                 actions[i] = (struct mlx5_modification_cmd) {
 421                         .action_type = type,
 422                         .field = field->id,
 423                         .offset = off_b,
 424                         .length = size_b,
 425                 };
 426                 /* Convert entire record to expected big-endian format. */
 427                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 428                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 429                         MLX5_ASSERT(dcopy);
 430                         actions[i].dst_field = dcopy->id;
 431                         actions[i].dst_offset =
 432                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 433                         /* Convert entire record to big-endian format. */
 434                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 435                         ++dcopy;
 436                 } else {
 437                         MLX5_ASSERT(item->spec);
 438                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 439                                                    field->offset, field->size);
 440                         /* Shift out the trailing masked bits from data. */
 441                         data = (data & mask) >> off_b;
 442                         actions[i].data1 = rte_cpu_to_be_32(data);
 443                 }
 444                 ++i;
 445                 ++field;
 446         } while (field->size);
 447         if (resource->actions_num == i)
 448                 return rte_flow_error_set(error, EINVAL,
 449                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 450                                           "invalid modification flow item");
 451         resource->actions_num = i;
 452         return 0;
 453 }
 454
 455 /**
 456  * Convert modify-header set IPv4 address action to DV specification.
 457  *
 458  * @param[in,out] resource
 459  *   Pointer to the modify-header resource.
 460  * @param[in] action
 461  *   Pointer to action specification.
 462  * @param[out] error
 463  *   Pointer to the error structure.
 464  *
 465  * @return
 466  *   0 on success, a negative errno value otherwise and rte_errno is set.
 467  */
 468 static int
 469 flow_dv_convert_action_modify_ipv4
 470                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 471                          const struct rte_flow_action *action,
 472                          struct rte_flow_error *error)
 473 {
 474         const struct rte_flow_action_set_ipv4 *conf =
 475                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 476         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 477         struct rte_flow_item_ipv4 ipv4;
 478         struct rte_flow_item_ipv4 ipv4_mask;
 479
 480         memset(&ipv4, 0, sizeof(ipv4));
 481         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 482         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 483                 ipv4.hdr.src_addr = conf->ipv4_addr;
 484                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 485         } else {
 486                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 487                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 488         }
 489         item.spec = &ipv4;
 490         item.mask = &ipv4_mask;
 491         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 492                                              MLX5_MODIFICATION_TYPE_SET, error);
 493 }
 494
 495 /**
 496  * Convert modify-header set IPv6 address action to DV specification.
 497  *
 498  * @param[in,out] resource
 499  *   Pointer to the modify-header resource.
 500  * @param[in] action
 501  *   Pointer to action specification.
 502  * @param[out] error
 503  *   Pointer to the error structure.
 504  *
 505  * @return
 506  *   0 on success, a negative errno value otherwise and rte_errno is set.
 507  */
 508 static int
 509 flow_dv_convert_action_modify_ipv6
 510                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 511                          const struct rte_flow_action *action,
 512                          struct rte_flow_error *error)
 513 {
 514         const struct rte_flow_action_set_ipv6 *conf =
 515                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 516         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 517         struct rte_flow_item_ipv6 ipv6;
 518         struct rte_flow_item_ipv6 ipv6_mask;
 519
 520         memset(&ipv6, 0, sizeof(ipv6));
 521         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 522         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 523                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.src_addr));
 525                 memcpy(&ipv6_mask.hdr.src_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 527                        sizeof(ipv6.hdr.src_addr));
 528         } else {
 529                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 530                        sizeof(ipv6.hdr.dst_addr));
 531                 memcpy(&ipv6_mask.hdr.dst_addr,
 532                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 533                        sizeof(ipv6.hdr.dst_addr));
 534         }
 535         item.spec = &ipv6;
 536         item.mask = &ipv6_mask;
 537         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 538                                              MLX5_MODIFICATION_TYPE_SET, error);
 539 }
 540
 541 /**
 542  * Convert modify-header set MAC address action to DV specification.
 543  *
 544  * @param[in,out] resource
 545  *   Pointer to the modify-header resource.
 546  * @param[in] action
 547  *   Pointer to action specification.
 548  * @param[out] error
 549  *   Pointer to the error structure.
 550  *
 551  * @return
 552  *   0 on success, a negative errno value otherwise and rte_errno is set.
 553  */
 554 static int
 555 flow_dv_convert_action_modify_mac
 556                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 557                          const struct rte_flow_action *action,
 558                          struct rte_flow_error *error)
 559 {
 560         const struct rte_flow_action_set_mac *conf =
 561                 (const struct rte_flow_action_set_mac *)(action->conf);
 562         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 563         struct rte_flow_item_eth eth;
 564         struct rte_flow_item_eth eth_mask;
 565
 566         memset(&eth, 0, sizeof(eth));
 567         memset(&eth_mask, 0, sizeof(eth_mask));
 568         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 569                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.src.addr_bytes));
 571                 memcpy(&eth_mask.src.addr_bytes,
 572                        &rte_flow_item_eth_mask.src.addr_bytes,
 573                        sizeof(eth_mask.src.addr_bytes));
 574         } else {
 575                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 576                        sizeof(eth.dst.addr_bytes));
 577                 memcpy(&eth_mask.dst.addr_bytes,
 578                        &rte_flow_item_eth_mask.dst.addr_bytes,
 579                        sizeof(eth_mask.dst.addr_bytes));
 580         }
 581         item.spec = &eth;
 582         item.mask = &eth_mask;
 583         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 584                                              MLX5_MODIFICATION_TYPE_SET, error);
 585 }
 586
 587 /**
 588  * Convert modify-header set VLAN VID action to DV specification.
 589  *
 590  * @param[in,out] resource
 591  *   Pointer to the modify-header resource.
 592  * @param[in] action
 593  *   Pointer to action specification.
 594  * @param[out] error
 595  *   Pointer to the error structure.
 596  *
 597  * @return
 598  *   0 on success, a negative errno value otherwise and rte_errno is set.
 599  */
 600 static int
 601 flow_dv_convert_action_modify_vlan_vid
 602                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 603                          const struct rte_flow_action *action,
 604                          struct rte_flow_error *error)
 605 {
 606         const struct rte_flow_action_of_set_vlan_vid *conf =
 607                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 608         int i = resource->actions_num;
 609         struct mlx5_modification_cmd *actions = resource->actions;
 610         struct field_modify_info *field = modify_vlan_out_first_vid;
 611
 612         if (i >= MLX5_MAX_MODIFY_NUM)
 613                 return rte_flow_error_set(error, EINVAL,
 614                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 615                          "too many items to modify");
 616         actions[i] = (struct mlx5_modification_cmd) {
 617                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 618                 .field = field->id,
 619                 .length = field->size,
 620                 .offset = field->offset,
 621         };
 622         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 623         actions[i].data1 = conf->vlan_vid;
 624         actions[i].data1 = actions[i].data1 << 16;
 625         resource->actions_num = ++i;
 626         return 0;
 627 }
 628
 629 /**
 630  * Convert modify-header set TP action to DV specification.
 631  *
 632  * @param[in,out] resource
 633  *   Pointer to the modify-header resource.
 634  * @param[in] action
 635  *   Pointer to action specification.
 636  * @param[in] items
 637  *   Pointer to rte_flow_item objects list.
 638  * @param[in] attr
 639  *   Pointer to flow attributes structure.
 640  * @param[in] dev_flow
 641  *   Pointer to the sub flow.
 642  * @param[in] tunnel_decap
 643  *   Whether action is after tunnel decapsulation.
 644  * @param[out] error
 645  *   Pointer to the error structure.
 646  *
 647  * @return
 648  *   0 on success, a negative errno value otherwise and rte_errno is set.
 649  */
 650 static int
 651 flow_dv_convert_action_modify_tp
 652                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 653                          const struct rte_flow_action *action,
 654                          const struct rte_flow_item *items,
 655                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 656                          bool tunnel_decap, struct rte_flow_error *error)
 657 {
 658         const struct rte_flow_action_set_tp *conf =
 659                 (const struct rte_flow_action_set_tp *)(action->conf);
 660         struct rte_flow_item item;
 661         struct rte_flow_item_udp udp;
 662         struct rte_flow_item_udp udp_mask;
 663         struct rte_flow_item_tcp tcp;
 664         struct rte_flow_item_tcp tcp_mask;
 665         struct field_modify_info *field;
 666
 667         if (!attr->valid)
 668                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 669         if (attr->udp) {
 670                 memset(&udp, 0, sizeof(udp));
 671                 memset(&udp_mask, 0, sizeof(udp_mask));
 672                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 673                         udp.hdr.src_port = conf->port;
 674                         udp_mask.hdr.src_port =
 675                                         rte_flow_item_udp_mask.hdr.src_port;
 676                 } else {
 677                         udp.hdr.dst_port = conf->port;
 678                         udp_mask.hdr.dst_port =
 679                                         rte_flow_item_udp_mask.hdr.dst_port;
 680                 }
 681                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 682                 item.spec = &udp;
 683                 item.mask = &udp_mask;
 684                 field = modify_udp;
 685         } else {
 686                 MLX5_ASSERT(attr->tcp);
 687                 memset(&tcp, 0, sizeof(tcp));
 688                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 689                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 690                         tcp.hdr.src_port = conf->port;
 691                         tcp_mask.hdr.src_port =
 692                                         rte_flow_item_tcp_mask.hdr.src_port;
 693                 } else {
 694                         tcp.hdr.dst_port = conf->port;
 695                         tcp_mask.hdr.dst_port =
 696                                         rte_flow_item_tcp_mask.hdr.dst_port;
 697                 }
 698                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 699                 item.spec = &tcp;
 700                 item.mask = &tcp_mask;
 701                 field = modify_tcp;
 702         }
 703         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 704                                              MLX5_MODIFICATION_TYPE_SET, error);
 705 }
 706
 707 /**
 708  * Convert modify-header set TTL action to DV specification.
 709  *
 710  * @param[in,out] resource
 711  *   Pointer to the modify-header resource.
 712  * @param[in] action
 713  *   Pointer to action specification.
 714  * @param[in] items
 715  *   Pointer to rte_flow_item objects list.
 716  * @param[in] attr
 717  *   Pointer to flow attributes structure.
 718  * @param[in] dev_flow
 719  *   Pointer to the sub flow.
 720  * @param[in] tunnel_decap
 721  *   Whether action is after tunnel decapsulation.
 722  * @param[out] error
 723  *   Pointer to the error structure.
 724  *
 725  * @return
 726  *   0 on success, a negative errno value otherwise and rte_errno is set.
 727  */
 728 static int
 729 flow_dv_convert_action_modify_ttl
 730                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 731                          const struct rte_flow_action *action,
 732                          const struct rte_flow_item *items,
 733                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 734                          bool tunnel_decap, struct rte_flow_error *error)
 735 {
 736         const struct rte_flow_action_set_ttl *conf =
 737                 (const struct rte_flow_action_set_ttl *)(action->conf);
 738         struct rte_flow_item item;
 739         struct rte_flow_item_ipv4 ipv4;
 740         struct rte_flow_item_ipv4 ipv4_mask;
 741         struct rte_flow_item_ipv6 ipv6;
 742         struct rte_flow_item_ipv6 ipv6_mask;
 743         struct field_modify_info *field;
 744
 745         if (!attr->valid)
 746                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 747         if (attr->ipv4) {
 748                 memset(&ipv4, 0, sizeof(ipv4));
 749                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 750                 ipv4.hdr.time_to_live = conf->ttl_value;
 751                 ipv4_mask.hdr.time_to_live = 0xFF;
 752                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 753                 item.spec = &ipv4;
 754                 item.mask = &ipv4_mask;
 755                 field = modify_ipv4;
 756         } else {
 757                 MLX5_ASSERT(attr->ipv6);
 758                 memset(&ipv6, 0, sizeof(ipv6));
 759                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 760                 ipv6.hdr.hop_limits = conf->ttl_value;
 761                 ipv6_mask.hdr.hop_limits = 0xFF;
 762                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 763                 item.spec = &ipv6;
 764                 item.mask = &ipv6_mask;
 765                 field = modify_ipv6;
 766         }
 767         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 768                                              MLX5_MODIFICATION_TYPE_SET, error);
 769 }
 770
 771 /**
 772  * Convert modify-header decrement TTL action to DV specification.
 773  *
 774  * @param[in,out] resource
 775  *   Pointer to the modify-header resource.
 776  * @param[in] action
 777  *   Pointer to action specification.
 778  * @param[in] items
 779  *   Pointer to rte_flow_item objects list.
 780  * @param[in] attr
 781  *   Pointer to flow attributes structure.
 782  * @param[in] dev_flow
 783  *   Pointer to the sub flow.
 784  * @param[in] tunnel_decap
 785  *   Whether action is after tunnel decapsulation.
 786  * @param[out] error
 787  *   Pointer to the error structure.
 788  *
 789  * @return
 790  *   0 on success, a negative errno value otherwise and rte_errno is set.
 791  */
 792 static int
 793 flow_dv_convert_action_modify_dec_ttl
 794                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 795                          const struct rte_flow_item *items,
 796                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 797                          bool tunnel_decap, struct rte_flow_error *error)
 798 {
 799         struct rte_flow_item item;
 800         struct rte_flow_item_ipv4 ipv4;
 801         struct rte_flow_item_ipv4 ipv4_mask;
 802         struct rte_flow_item_ipv6 ipv6;
 803         struct rte_flow_item_ipv6 ipv6_mask;
 804         struct field_modify_info *field;
 805
 806         if (!attr->valid)
 807                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 808         if (attr->ipv4) {
 809                 memset(&ipv4, 0, sizeof(ipv4));
 810                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 811                 ipv4.hdr.time_to_live = 0xFF;
 812                 ipv4_mask.hdr.time_to_live = 0xFF;
 813                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 814                 item.spec = &ipv4;
 815                 item.mask = &ipv4_mask;
 816                 field = modify_ipv4;
 817         } else {
 818                 MLX5_ASSERT(attr->ipv6);
 819                 memset(&ipv6, 0, sizeof(ipv6));
 820                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 821                 ipv6.hdr.hop_limits = 0xFF;
 822                 ipv6_mask.hdr.hop_limits = 0xFF;
 823                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 824                 item.spec = &ipv6;
 825                 item.mask = &ipv6_mask;
 826                 field = modify_ipv6;
 827         }
 828         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 829                                              MLX5_MODIFICATION_TYPE_ADD, error);
 830 }
 831
 832 /**
 833  * Convert modify-header increment/decrement TCP Sequence number
 834  * to DV specification.
 835  *
 836  * @param[in,out] resource
 837  *   Pointer to the modify-header resource.
 838  * @param[in] action
 839  *   Pointer to action specification.
 840  * @param[out] error
 841  *   Pointer to the error structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 static int
 847 flow_dv_convert_action_modify_tcp_seq
 848                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 849                          const struct rte_flow_action *action,
 850                          struct rte_flow_error *error)
 851 {
 852         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 853         uint64_t value = rte_be_to_cpu_32(*conf);
 854         struct rte_flow_item item;
 855         struct rte_flow_item_tcp tcp;
 856         struct rte_flow_item_tcp tcp_mask;
 857
 858         memset(&tcp, 0, sizeof(tcp));
 859         memset(&tcp_mask, 0, sizeof(tcp_mask));
 860         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 861                 /*
 862                  * The HW has no decrement operation, only increment operation.
 863                  * To simulate decrement X from Y using increment operation
 864                  * we need to add UINT32_MAX X times to Y.
 865                  * Each adding of UINT32_MAX decrements Y by 1.
 866                  */
 867                 value *= UINT32_MAX;
 868         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 869         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 870         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 871         item.spec = &tcp;
 872         item.mask = &tcp_mask;
 873         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 874                                              MLX5_MODIFICATION_TYPE_ADD, error);
 875 }
 876
 877 /**
 878  * Convert modify-header increment/decrement TCP Acknowledgment number
 879  * to DV specification.
 880  *
 881  * @param[in,out] resource
 882  *   Pointer to the modify-header resource.
 883  * @param[in] action
 884  *   Pointer to action specification.
 885  * @param[out] error
 886  *   Pointer to the error structure.
 887  *
 888  * @return
 889  *   0 on success, a negative errno value otherwise and rte_errno is set.
 890  */
 891 static int
 892 flow_dv_convert_action_modify_tcp_ack
 893                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 894                          const struct rte_flow_action *action,
 895                          struct rte_flow_error *error)
 896 {
 897         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 898         uint64_t value = rte_be_to_cpu_32(*conf);
 899         struct rte_flow_item item;
 900         struct rte_flow_item_tcp tcp;
 901         struct rte_flow_item_tcp tcp_mask;
 902
 903         memset(&tcp, 0, sizeof(tcp));
 904         memset(&tcp_mask, 0, sizeof(tcp_mask));
 905         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 906                 /*
 907                  * The HW has no decrement operation, only increment operation.
 908                  * To simulate decrement X from Y using increment operation
 909                  * we need to add UINT32_MAX X times to Y.
 910                  * Each adding of UINT32_MAX decrements Y by 1.
 911                  */
 912                 value *= UINT32_MAX;
 913         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 914         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 915         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 916         item.spec = &tcp;
 917         item.mask = &tcp_mask;
 918         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 919                                              MLX5_MODIFICATION_TYPE_ADD, error);
 920 }
 921
 922 static enum mlx5_modification_field reg_to_field[] = {
 923         [REG_NON] = MLX5_MODI_OUT_NONE,
 924         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 925         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 926         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 927         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 928         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 929         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 930         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 931         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 932         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 933         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 934 };
 935
 936 /**
 937  * Convert register set to DV specification.
 938  *
 939  * @param[in,out] resource
 940  *   Pointer to the modify-header resource.
 941  * @param[in] action
 942  *   Pointer to action specification.
 943  * @param[out] error
 944  *   Pointer to the error structure.
 945  *
 946  * @return
 947  *   0 on success, a negative errno value otherwise and rte_errno is set.
 948  */
 949 static int
 950 flow_dv_convert_action_set_reg
 951                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 952                          const struct rte_flow_action *action,
 953                          struct rte_flow_error *error)
 954 {
 955         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 956         struct mlx5_modification_cmd *actions = resource->actions;
 957         uint32_t i = resource->actions_num;
 958
 959         if (i >= MLX5_MAX_MODIFY_NUM)
 960                 return rte_flow_error_set(error, EINVAL,
 961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 962                                           "too many items to modify");
 963         MLX5_ASSERT(conf->id != REG_NON);
 964         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 965         actions[i] = (struct mlx5_modification_cmd) {
 966                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 967                 .field = reg_to_field[conf->id],
 968                 .offset = conf->offset,
 969                 .length = conf->length,
 970         };
 971         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 972         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 973         ++i;
 974         resource->actions_num = i;
 975         return 0;
 976 }
 977
 978 /**
 979  * Convert SET_TAG action to DV specification.
 980  *
 981  * @param[in] dev
 982  *   Pointer to the rte_eth_dev structure.
 983  * @param[in,out] resource
 984  *   Pointer to the modify-header resource.
 985  * @param[in] conf
 986  *   Pointer to action specification.
 987  * @param[out] error
 988  *   Pointer to the error structure.
 989  *
 990  * @return
 991  *   0 on success, a negative errno value otherwise and rte_errno is set.
 992  */
 993 static int
 994 flow_dv_convert_action_set_tag
 995                         (struct rte_eth_dev *dev,
 996                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 997                          const struct rte_flow_action_set_tag *conf,
 998                          struct rte_flow_error *error)
 999 {
1000         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1001         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1002         struct rte_flow_item item = {
1003                 .spec = &data,
1004                 .mask = &mask,
1005         };
1006         struct field_modify_info reg_c_x[] = {
1007                 [1] = {0, 0, 0},
1008         };
1009         enum mlx5_modification_field reg_type;
1010         int ret;
1011
1012         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1013         if (ret < 0)
1014                 return ret;
1015         MLX5_ASSERT(ret != REG_NON);
1016         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1017         reg_type = reg_to_field[ret];
1018         MLX5_ASSERT(reg_type > 0);
1019         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1020         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1021                                              MLX5_MODIFICATION_TYPE_SET, error);
1022 }
1023
1024 /**
1025  * Convert internal COPY_REG action to DV specification.
1026  *
1027  * @param[in] dev
1028  *   Pointer to the rte_eth_dev structure.
1029  * @param[in,out] res
1030  *   Pointer to the modify-header resource.
1031  * @param[in] action
1032  *   Pointer to action specification.
1033  * @param[out] error
1034  *   Pointer to the error structure.
1035  *
1036  * @return
1037  *   0 on success, a negative errno value otherwise and rte_errno is set.
1038  */
1039 static int
1040 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1041                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1042                                  const struct rte_flow_action *action,
1043                                  struct rte_flow_error *error)
1044 {
1045         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1046         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1047         struct rte_flow_item item = {
1048                 .spec = NULL,
1049                 .mask = &mask,
1050         };
1051         struct field_modify_info reg_src[] = {
1052                 {4, 0, reg_to_field[conf->src]},
1053                 {0, 0, 0},
1054         };
1055         struct field_modify_info reg_dst = {
1056                 .offset = 0,
1057                 .id = reg_to_field[conf->dst],
1058         };
1059         /* Adjust reg_c[0] usage according to reported mask. */
1060         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1061                 struct mlx5_priv *priv = dev->data->dev_private;
1062                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1063
1064                 MLX5_ASSERT(reg_c0);
1065                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1066                 if (conf->dst == REG_C_0) {
1067                         /* Copy to reg_c[0], within mask only. */
1068                         reg_dst.offset = rte_bsf32(reg_c0);
1069                         /*
1070                          * Mask is ignoring the enianness, because
1071                          * there is no conversion in datapath.
1072                          */
1073 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1074                         /* Copy from destination lower bits to reg_c[0]. */
1075                         mask = reg_c0 >> reg_dst.offset;
1076 #else
1077                         /* Copy from destination upper bits to reg_c[0]. */
1078                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1079                                           rte_fls_u32(reg_c0));
1080 #endif
1081                 } else {
1082                         mask = rte_cpu_to_be_32(reg_c0);
1083 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1084                         /* Copy from reg_c[0] to destination lower bits. */
1085                         reg_dst.offset = 0;
1086 #else
1087                         /* Copy from reg_c[0] to destination upper bits. */
1088                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1089                                          (rte_fls_u32(reg_c0) -
1090                                           rte_bsf32(reg_c0));
1091 #endif
1092                 }
1093         }
1094         return flow_dv_convert_modify_action(&item,
1095                                              reg_src, &reg_dst, res,
1096                                              MLX5_MODIFICATION_TYPE_COPY,
1097                                              error);
1098 }
1099
1100 /**
1101  * Convert MARK action to DV specification. This routine is used
1102  * in extensive metadata only and requires metadata register to be
1103  * handled. In legacy mode hardware tag resource is engaged.
1104  *
1105  * @param[in] dev
1106  *   Pointer to the rte_eth_dev structure.
1107  * @param[in] conf
1108  *   Pointer to MARK action specification.
1109  * @param[in,out] resource
1110  *   Pointer to the modify-header resource.
1111  * @param[out] error
1112  *   Pointer to the error structure.
1113  *
1114  * @return
1115  *   0 on success, a negative errno value otherwise and rte_errno is set.
1116  */
1117 static int
1118 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1119                             const struct rte_flow_action_mark *conf,
1120                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1121                             struct rte_flow_error *error)
1122 {
1123         struct mlx5_priv *priv = dev->data->dev_private;
1124         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1125                                            priv->sh->dv_mark_mask);
1126         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1127         struct rte_flow_item item = {
1128                 .spec = &data,
1129                 .mask = &mask,
1130         };
1131         struct field_modify_info reg_c_x[] = {
1132                 [1] = {0, 0, 0},
1133         };
1134         int reg;
1135
1136         if (!mask)
1137                 return rte_flow_error_set(error, EINVAL,
1138                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1139                                           NULL, "zero mark action mask");
1140         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1141         if (reg < 0)
1142                 return reg;
1143         MLX5_ASSERT(reg > 0);
1144         if (reg == REG_C_0) {
1145                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1146                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1147
1148                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1149                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1150                 mask = rte_cpu_to_be_32(mask << shl_c0);
1151         }
1152         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1153         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1154                                              MLX5_MODIFICATION_TYPE_SET, error);
1155 }
1156
1157 /**
1158  * Get metadata register index for specified steering domain.
1159  *
1160  * @param[in] dev
1161  *   Pointer to the rte_eth_dev structure.
1162  * @param[in] attr
1163  *   Attributes of flow to determine steering domain.
1164  * @param[out] error
1165  *   Pointer to the error structure.
1166  *
1167  * @return
1168  *   positive index on success, a negative errno value otherwise
1169  *   and rte_errno is set.
1170  */
1171 static enum modify_reg
1172 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1173                          const struct rte_flow_attr *attr,
1174                          struct rte_flow_error *error)
1175 {
1176         int reg =
1177                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178                                           MLX5_METADATA_FDB :
1179                                             attr->egress ?
1180                                             MLX5_METADATA_TX :
1181                                             MLX5_METADATA_RX, 0, error);
1182         if (reg < 0)
1183                 return rte_flow_error_set(error,
1184                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1185                                           NULL, "unavailable "
1186                                           "metadata register");
1187         return reg;
1188 }
1189
1190 /**
1191  * Convert SET_META action to DV specification.
1192  *
1193  * @param[in] dev
1194  *   Pointer to the rte_eth_dev structure.
1195  * @param[in,out] resource
1196  *   Pointer to the modify-header resource.
1197  * @param[in] attr
1198  *   Attributes of flow that includes this item.
1199  * @param[in] conf
1200  *   Pointer to action specification.
1201  * @param[out] error
1202  *   Pointer to the error structure.
1203  *
1204  * @return
1205  *   0 on success, a negative errno value otherwise and rte_errno is set.
1206  */
1207 static int
1208 flow_dv_convert_action_set_meta
1209                         (struct rte_eth_dev *dev,
1210                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1211                          const struct rte_flow_attr *attr,
1212                          const struct rte_flow_action_set_meta *conf,
1213                          struct rte_flow_error *error)
1214 {
1215         uint32_t data = conf->data;
1216         uint32_t mask = conf->mask;
1217         struct rte_flow_item item = {
1218                 .spec = &data,
1219                 .mask = &mask,
1220         };
1221         struct field_modify_info reg_c_x[] = {
1222                 [1] = {0, 0, 0},
1223         };
1224         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225
1226         if (reg < 0)
1227                 return reg;
1228         MLX5_ASSERT(reg != REG_NON);
1229         /*
1230          * In datapath code there is no endianness
1231          * coversions for perfromance reasons, all
1232          * pattern conversions are done in rte_flow.
1233          */
1234         if (reg == REG_C_0) {
1235                 struct mlx5_priv *priv = dev->data->dev_private;
1236                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1237                 uint32_t shl_c0;
1238
1239                 MLX5_ASSERT(msk_c0);
1240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1241                 shl_c0 = rte_bsf32(msk_c0);
1242 #else
1243                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 #endif
1245                 mask <<= shl_c0;
1246                 data <<= shl_c0;
1247                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1248         }
1249         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1250         /* The routine expects parameters in memory as big-endian ones. */
1251         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1252                                              MLX5_MODIFICATION_TYPE_SET, error);
1253 }
1254
1255 /**
1256  * Convert modify-header set IPv4 DSCP action to DV specification.
1257  *
1258  * @param[in,out] resource
1259  *   Pointer to the modify-header resource.
1260  * @param[in] action
1261  *   Pointer to action specification.
1262  * @param[out] error
1263  *   Pointer to the error structure.
1264  *
1265  * @return
1266  *   0 on success, a negative errno value otherwise and rte_errno is set.
1267  */
1268 static int
1269 flow_dv_convert_action_modify_ipv4_dscp
1270                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1271                          const struct rte_flow_action *action,
1272                          struct rte_flow_error *error)
1273 {
1274         const struct rte_flow_action_set_dscp *conf =
1275                 (const struct rte_flow_action_set_dscp *)(action->conf);
1276         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1277         struct rte_flow_item_ipv4 ipv4;
1278         struct rte_flow_item_ipv4 ipv4_mask;
1279
1280         memset(&ipv4, 0, sizeof(ipv4));
1281         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1282         ipv4.hdr.type_of_service = conf->dscp;
1283         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1284         item.spec = &ipv4;
1285         item.mask = &ipv4_mask;
1286         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1287                                              MLX5_MODIFICATION_TYPE_SET, error);
1288 }
1289
1290 /**
1291  * Convert modify-header set IPv6 DSCP action to DV specification.
1292  *
1293  * @param[in,out] resource
1294  *   Pointer to the modify-header resource.
1295  * @param[in] action
1296  *   Pointer to action specification.
1297  * @param[out] error
1298  *   Pointer to the error structure.
1299  *
1300  * @return
1301  *   0 on success, a negative errno value otherwise and rte_errno is set.
1302  */
1303 static int
1304 flow_dv_convert_action_modify_ipv6_dscp
1305                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1306                          const struct rte_flow_action *action,
1307                          struct rte_flow_error *error)
1308 {
1309         const struct rte_flow_action_set_dscp *conf =
1310                 (const struct rte_flow_action_set_dscp *)(action->conf);
1311         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1312         struct rte_flow_item_ipv6 ipv6;
1313         struct rte_flow_item_ipv6 ipv6_mask;
1314
1315         memset(&ipv6, 0, sizeof(ipv6));
1316         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1317         /*
1318          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1319          * rdma-core only accept the DSCP bits byte aligned start from
1320          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1321          * bits in IPv6 case as rdma-core requires byte aligned value.
1322          */
1323         ipv6.hdr.vtc_flow = conf->dscp;
1324         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1325         item.spec = &ipv6;
1326         item.mask = &ipv6_mask;
1327         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1328                                              MLX5_MODIFICATION_TYPE_SET, error);
1329 }
1330
1331 static int
1332 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1333 {
1334         switch (field) {
1335         case RTE_FLOW_FIELD_START:
1336                 return 32;
1337         case RTE_FLOW_FIELD_MAC_DST:
1338         case RTE_FLOW_FIELD_MAC_SRC:
1339                 return 48;
1340         case RTE_FLOW_FIELD_VLAN_TYPE:
1341                 return 16;
1342         case RTE_FLOW_FIELD_VLAN_ID:
1343                 return 12;
1344         case RTE_FLOW_FIELD_MAC_TYPE:
1345                 return 16;
1346         case RTE_FLOW_FIELD_IPV4_DSCP:
1347                 return 6;
1348         case RTE_FLOW_FIELD_IPV4_TTL:
1349                 return 8;
1350         case RTE_FLOW_FIELD_IPV4_SRC:
1351         case RTE_FLOW_FIELD_IPV4_DST:
1352                 return 32;
1353         case RTE_FLOW_FIELD_IPV6_DSCP:
1354                 return 6;
1355         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1356                 return 8;
1357         case RTE_FLOW_FIELD_IPV6_SRC:
1358         case RTE_FLOW_FIELD_IPV6_DST:
1359                 return 128;
1360         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1361         case RTE_FLOW_FIELD_TCP_PORT_DST:
1362                 return 16;
1363         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1364         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1365                 return 32;
1366         case RTE_FLOW_FIELD_TCP_FLAGS:
1367                 return 6;
1368         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1369         case RTE_FLOW_FIELD_UDP_PORT_DST:
1370                 return 16;
1371         case RTE_FLOW_FIELD_VXLAN_VNI:
1372         case RTE_FLOW_FIELD_GENEVE_VNI:
1373                 return 24;
1374         case RTE_FLOW_FIELD_GTP_TEID:
1375         case RTE_FLOW_FIELD_TAG:
1376                 return 32;
1377         case RTE_FLOW_FIELD_MARK:
1378                 return 24;
1379         case RTE_FLOW_FIELD_META:
1380                 return 32;
1381         case RTE_FLOW_FIELD_POINTER:
1382         case RTE_FLOW_FIELD_VALUE:
1383                 return 64;
1384         default:
1385                 MLX5_ASSERT(false);
1386         }
1387         return 0;
1388 }
1389
1390 static void
1391 mlx5_flow_field_id_to_modify_info
1392                 (const struct rte_flow_action_modify_data *data,
1393                  struct field_modify_info *info,
1394                  uint32_t *mask, uint32_t *value,
1395                  uint32_t width, uint32_t dst_width,
1396                  struct rte_eth_dev *dev,
1397                  const struct rte_flow_attr *attr,
1398                  struct rte_flow_error *error)
1399 {
1400         uint32_t idx = 0;
1401         uint64_t val = 0;
1402         switch (data->field) {
1403         case RTE_FLOW_FIELD_START:
1404                 /* not supported yet */
1405                 MLX5_ASSERT(false);
1406                 break;
1407         case RTE_FLOW_FIELD_MAC_DST:
1408                 if (mask) {
1409                         if (data->offset < 32) {
1410                                 info[idx] = (struct field_modify_info){4, 0,
1411                                                 MLX5_MODI_OUT_DMAC_47_16};
1412                                 if (width < 32) {
1413                                         mask[idx] =
1414                                                 rte_cpu_to_be_32(0xffffffff >>
1415                                                                  (32 - width));
1416                                         width = 0;
1417                                 } else {
1418                                         mask[idx] = RTE_BE32(0xffffffff);
1419                                         width -= 32;
1420                                 }
1421                                 if (!width)
1422                                         break;
1423                                 ++idx;
1424                         }
1425                         info[idx] = (struct field_modify_info){2, 4 * idx,
1426                                                 MLX5_MODI_OUT_DMAC_15_0};
1427                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1428                 } else {
1429                         if (data->offset < 32)
1430                                 info[idx++] = (struct field_modify_info){4, 0,
1431                                                 MLX5_MODI_OUT_DMAC_47_16};
1432                         info[idx] = (struct field_modify_info){2, 0,
1433                                                 MLX5_MODI_OUT_DMAC_15_0};
1434                 }
1435                 break;
1436         case RTE_FLOW_FIELD_MAC_SRC:
1437                 if (mask) {
1438                         if (data->offset < 32) {
1439                                 info[idx] = (struct field_modify_info){4, 0,
1440                                                 MLX5_MODI_OUT_SMAC_47_16};
1441                                 if (width < 32) {
1442                                         mask[idx] =
1443                                                 rte_cpu_to_be_32(0xffffffff >>
1444                                                                 (32 - width));
1445                                         width = 0;
1446                                 } else {
1447                                         mask[idx] = RTE_BE32(0xffffffff);
1448                                         width -= 32;
1449                                 }
1450                                 if (!width)
1451                                         break;
1452                                 ++idx;
1453                         }
1454                         info[idx] = (struct field_modify_info){2, 4 * idx,
1455                                                 MLX5_MODI_OUT_SMAC_15_0};
1456                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1457                 } else {
1458                         if (data->offset < 32)
1459                                 info[idx++] = (struct field_modify_info){4, 0,
1460                                                 MLX5_MODI_OUT_SMAC_47_16};
1461                         info[idx] = (struct field_modify_info){2, 0,
1462                                                 MLX5_MODI_OUT_SMAC_15_0};
1463                 }
1464                 break;
1465         case RTE_FLOW_FIELD_VLAN_TYPE:
1466                 /* not supported yet */
1467                 break;
1468         case RTE_FLOW_FIELD_VLAN_ID:
1469                 info[idx] = (struct field_modify_info){2, 0,
1470                                         MLX5_MODI_OUT_FIRST_VID};
1471                 if (mask)
1472                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1473                 break;
1474         case RTE_FLOW_FIELD_MAC_TYPE:
1475                 info[idx] = (struct field_modify_info){2, 0,
1476                                         MLX5_MODI_OUT_ETHERTYPE};
1477                 if (mask)
1478                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1479                 break;
1480         case RTE_FLOW_FIELD_IPV4_DSCP:
1481                 info[idx] = (struct field_modify_info){1, 0,
1482                                         MLX5_MODI_OUT_IP_DSCP};
1483                 if (mask)
1484                         mask[idx] = 0x3f >> (6 - width);
1485                 break;
1486         case RTE_FLOW_FIELD_IPV4_TTL:
1487                 info[idx] = (struct field_modify_info){1, 0,
1488                                         MLX5_MODI_OUT_IPV4_TTL};
1489                 if (mask)
1490                         mask[idx] = 0xff >> (8 - width);
1491                 break;
1492         case RTE_FLOW_FIELD_IPV4_SRC:
1493                 info[idx] = (struct field_modify_info){4, 0,
1494                                         MLX5_MODI_OUT_SIPV4};
1495                 if (mask)
1496                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1497                                                      (32 - width));
1498                 break;
1499         case RTE_FLOW_FIELD_IPV4_DST:
1500                 info[idx] = (struct field_modify_info){4, 0,
1501                                         MLX5_MODI_OUT_DIPV4};
1502                 if (mask)
1503                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1504                                                      (32 - width));
1505                 break;
1506         case RTE_FLOW_FIELD_IPV6_DSCP:
1507                 info[idx] = (struct field_modify_info){1, 0,
1508                                         MLX5_MODI_OUT_IP_DSCP};
1509                 if (mask)
1510                         mask[idx] = 0x3f >> (6 - width);
1511                 break;
1512         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1513                 info[idx] = (struct field_modify_info){1, 0,
1514                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1515                 if (mask)
1516                         mask[idx] = 0xff >> (8 - width);
1517                 break;
1518         case RTE_FLOW_FIELD_IPV6_SRC:
1519                 if (mask) {
1520                         if (data->offset < 32) {
1521                                 info[idx] = (struct field_modify_info){4,
1522                                                 4 * idx,
1523                                                 MLX5_MODI_OUT_SIPV6_31_0};
1524                                 if (width < 32) {
1525                                         mask[idx] =
1526                                                 rte_cpu_to_be_32(0xffffffff >>
1527                                                                  (32 - width));
1528                                         width = 0;
1529                                 } else {
1530                                         mask[idx] = RTE_BE32(0xffffffff);
1531                                         width -= 32;
1532                                 }
1533                                 if (!width)
1534                                         break;
1535                                 ++idx;
1536                         }
1537                         if (data->offset < 64) {
1538                                 info[idx] = (struct field_modify_info){4,
1539                                                 4 * idx,
1540                                                 MLX5_MODI_OUT_SIPV6_63_32};
1541                                 if (width < 32) {
1542                                         mask[idx] =
1543                                                 rte_cpu_to_be_32(0xffffffff >>
1544                                                                  (32 - width));
1545                                         width = 0;
1546                                 } else {
1547                                         mask[idx] = RTE_BE32(0xffffffff);
1548                                         width -= 32;
1549                                 }
1550                                 if (!width)
1551                                         break;
1552                                 ++idx;
1553                         }
1554                         if (data->offset < 96) {
1555                                 info[idx] = (struct field_modify_info){4,
1556                                                 4 * idx,
1557                                                 MLX5_MODI_OUT_SIPV6_95_64};
1558                                 if (width < 32) {
1559                                         mask[idx] =
1560                                                 rte_cpu_to_be_32(0xffffffff >>
1561                                                                  (32 - width));
1562                                         width = 0;
1563                                 } else {
1564                                         mask[idx] = RTE_BE32(0xffffffff);
1565                                         width -= 32;
1566                                 }
1567                                 if (!width)
1568                                         break;
1569                                 ++idx;
1570                         }
1571                         info[idx] = (struct field_modify_info){4, 4 * idx,
1572                                                 MLX5_MODI_OUT_SIPV6_127_96};
1573                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574                                                      (32 - width));
1575                 } else {
1576                         if (data->offset < 32)
1577                                 info[idx++] = (struct field_modify_info){4, 0,
1578                                                 MLX5_MODI_OUT_SIPV6_31_0};
1579                         if (data->offset < 64)
1580                                 info[idx++] = (struct field_modify_info){4, 0,
1581                                                 MLX5_MODI_OUT_SIPV6_63_32};
1582                         if (data->offset < 96)
1583                                 info[idx++] = (struct field_modify_info){4, 0,
1584                                                 MLX5_MODI_OUT_SIPV6_95_64};
1585                         if (data->offset < 128)
1586                                 info[idx++] = (struct field_modify_info){4, 0,
1587                                                 MLX5_MODI_OUT_SIPV6_127_96};
1588                 }
1589                 break;
1590         case RTE_FLOW_FIELD_IPV6_DST:
1591                 if (mask) {
1592                         if (data->offset < 32) {
1593                                 info[idx] = (struct field_modify_info){4,
1594                                                 4 * idx,
1595                                                 MLX5_MODI_OUT_DIPV6_31_0};
1596                                 if (width < 32) {
1597                                         mask[idx] =
1598                                                 rte_cpu_to_be_32(0xffffffff >>
1599                                                                  (32 - width));
1600                                         width = 0;
1601                                 } else {
1602                                         mask[idx] = RTE_BE32(0xffffffff);
1603                                         width -= 32;
1604                                 }
1605                                 if (!width)
1606                                         break;
1607                                 ++idx;
1608                         }
1609                         if (data->offset < 64) {
1610                                 info[idx] = (struct field_modify_info){4,
1611                                                 4 * idx,
1612                                                 MLX5_MODI_OUT_DIPV6_63_32};
1613                                 if (width < 32) {
1614                                         mask[idx] =
1615                                                 rte_cpu_to_be_32(0xffffffff >>
1616                                                                  (32 - width));
1617                                         width = 0;
1618                                 } else {
1619                                         mask[idx] = RTE_BE32(0xffffffff);
1620                                         width -= 32;
1621                                 }
1622                                 if (!width)
1623                                         break;
1624                                 ++idx;
1625                         }
1626                         if (data->offset < 96) {
1627                                 info[idx] = (struct field_modify_info){4,
1628                                                 4 * idx,
1629                                                 MLX5_MODI_OUT_DIPV6_95_64};
1630                                 if (width < 32) {
1631                                         mask[idx] =
1632                                                 rte_cpu_to_be_32(0xffffffff >>
1633                                                                  (32 - width));
1634                                         width = 0;
1635                                 } else {
1636                                         mask[idx] = RTE_BE32(0xffffffff);
1637                                         width -= 32;
1638                                 }
1639                                 if (!width)
1640                                         break;
1641                                 ++idx;
1642                         }
1643                         info[idx] = (struct field_modify_info){4, 4 * idx,
1644                                                 MLX5_MODI_OUT_DIPV6_127_96};
1645                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1646                                                      (32 - width));
1647                 } else {
1648                         if (data->offset < 32)
1649                                 info[idx++] = (struct field_modify_info){4, 0,
1650                                                 MLX5_MODI_OUT_DIPV6_31_0};
1651                         if (data->offset < 64)
1652                                 info[idx++] = (struct field_modify_info){4, 0,
1653                                                 MLX5_MODI_OUT_DIPV6_63_32};
1654                         if (data->offset < 96)
1655                                 info[idx++] = (struct field_modify_info){4, 0,
1656                                                 MLX5_MODI_OUT_DIPV6_95_64};
1657                         if (data->offset < 128)
1658                                 info[idx++] = (struct field_modify_info){4, 0,
1659                                                 MLX5_MODI_OUT_DIPV6_127_96};
1660                 }
1661                 break;
1662         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1663                 info[idx] = (struct field_modify_info){2, 0,
1664                                         MLX5_MODI_OUT_TCP_SPORT};
1665                 if (mask)
1666                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1667                 break;
1668         case RTE_FLOW_FIELD_TCP_PORT_DST:
1669                 info[idx] = (struct field_modify_info){2, 0,
1670                                         MLX5_MODI_OUT_TCP_DPORT};
1671                 if (mask)
1672                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1673                 break;
1674         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1675                 info[idx] = (struct field_modify_info){4, 0,
1676                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1677                 if (mask)
1678                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1679                                                      (32 - width));
1680                 break;
1681         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1682                 info[idx] = (struct field_modify_info){4, 0,
1683                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1684                 if (mask)
1685                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1686                                                      (32 - width));
1687                 break;
1688         case RTE_FLOW_FIELD_TCP_FLAGS:
1689                 info[idx] = (struct field_modify_info){1, 0,
1690                                         MLX5_MODI_OUT_TCP_FLAGS};
1691                 if (mask)
1692                         mask[idx] = 0x3f >> (6 - width);
1693                 break;
1694         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1695                 info[idx] = (struct field_modify_info){2, 0,
1696                                         MLX5_MODI_OUT_UDP_SPORT};
1697                 if (mask)
1698                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1699                 break;
1700         case RTE_FLOW_FIELD_UDP_PORT_DST:
1701                 info[idx] = (struct field_modify_info){2, 0,
1702                                         MLX5_MODI_OUT_UDP_DPORT};
1703                 if (mask)
1704                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1705                 break;
1706         case RTE_FLOW_FIELD_VXLAN_VNI:
1707                 /* not supported yet */
1708                 break;
1709         case RTE_FLOW_FIELD_GENEVE_VNI:
1710                 /* not supported yet*/
1711                 break;
1712         case RTE_FLOW_FIELD_GTP_TEID:
1713                 info[idx] = (struct field_modify_info){4, 0,
1714                                         MLX5_MODI_GTP_TEID};
1715                 if (mask)
1716                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1717                                                      (32 - width));
1718                 break;
1719         case RTE_FLOW_FIELD_TAG:
1720                 {
1721                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1722                                                    data->level, error);
1723                         if (reg < 0)
1724                                 return;
1725                         MLX5_ASSERT(reg != REG_NON);
1726                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1727                         info[idx] = (struct field_modify_info){4, 0,
1728                                                 reg_to_field[reg]};
1729                         if (mask)
1730                                 mask[idx] =
1731                                         rte_cpu_to_be_32(0xffffffff >>
1732                                                          (32 - width));
1733                 }
1734                 break;
1735         case RTE_FLOW_FIELD_MARK:
1736                 {
1737                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1738                                                        0, error);
1739                         if (reg < 0)
1740                                 return;
1741                         MLX5_ASSERT(reg != REG_NON);
1742                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1743                         info[idx] = (struct field_modify_info){4, 0,
1744                                                 reg_to_field[reg]};
1745                         if (mask)
1746                                 mask[idx] =
1747                                         rte_cpu_to_be_32(0xffffffff >>
1748                                                          (32 - width));
1749                 }
1750                 break;
1751         case RTE_FLOW_FIELD_META:
1752                 {
1753                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1754                         if (reg < 0)
1755                                 return;
1756                         MLX5_ASSERT(reg != REG_NON);
1757                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1758                         info[idx] = (struct field_modify_info){4, 0,
1759                                                 reg_to_field[reg]};
1760                         if (mask)
1761                                 mask[idx] =
1762                                         rte_cpu_to_be_32(0xffffffff >>
1763                                                          (32 - width));
1764                 }
1765                 break;
1766         case RTE_FLOW_FIELD_POINTER:
1767         case RTE_FLOW_FIELD_VALUE:
1768                 if (data->field == RTE_FLOW_FIELD_POINTER)
1769                         memcpy(&val, (void *)(uintptr_t)data->value,
1770                                sizeof(uint64_t));
1771                 else
1772                         val = data->value;
1773                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1774                         if (mask[idx]) {
1775                                 if (dst_width > 16) {
1776                                         value[idx] = rte_cpu_to_be_32(val);
1777                                         val >>= 32;
1778                                 } else if (dst_width > 8) {
1779                                         value[idx] = rte_cpu_to_be_16(val);
1780                                         val >>= 16;
1781                                 } else {
1782                                         value[idx] = (uint8_t)val;
1783                                         val >>= 8;
1784                                 }
1785                                 if (!val)
1786                                         break;
1787                         }
1788                 }
1789                 break;
1790         default:
1791                 MLX5_ASSERT(false);
1792                 break;
1793         }
1794 }
1795
1796 /**
1797  * Convert modify_field action to DV specification.
1798  *
1799  * @param[in] dev
1800  *   Pointer to the rte_eth_dev structure.
1801  * @param[in,out] resource
1802  *   Pointer to the modify-header resource.
1803  * @param[in] action
1804  *   Pointer to action specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to the error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_convert_action_modify_field
1815                         (struct rte_eth_dev *dev,
1816                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1817                          const struct rte_flow_action *action,
1818                          const struct rte_flow_attr *attr,
1819                          struct rte_flow_error *error)
1820 {
1821         const struct rte_flow_action_modify_field *conf =
1822                 (const struct rte_flow_action_modify_field *)(action->conf);
1823         struct rte_flow_item item;
1824         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1825                                                                 {0, 0, 0} };
1826         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1827                                                                 {0, 0, 0} };
1828         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1830         uint32_t type;
1831         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1832
1833         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1834                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1835                 type = MLX5_MODIFICATION_TYPE_SET;
1836                 /** For SET fill the destination field (field) first. */
1837                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1838                         value, conf->width, dst_width, dev, attr, error);
1839                 /** Then copy immediate value from source as per mask. */
1840                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1841                         value, conf->width, dst_width, dev, attr, error);
1842                 item.spec = &value;
1843         } else {
1844                 type = MLX5_MODIFICATION_TYPE_COPY;
1845                 /** For COPY fill the destination field (dcopy) without mask. */
1846                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1847                         value, conf->width, dst_width, dev, attr, error);
1848                 /** Then construct the source field (field) with mask. */
1849                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1850                         value, conf->width, dst_width, dev, attr, error);
1851         }
1852         item.mask = &mask;
1853         return flow_dv_convert_modify_action(&item,
1854                         field, dcopy, resource, type, error);
1855 }
1856
1857 /**
1858  * Validate MARK item.
1859  *
1860  * @param[in] dev
1861  *   Pointer to the rte_eth_dev structure.
1862  * @param[in] item
1863  *   Item specification.
1864  * @param[in] attr
1865  *   Attributes of flow that includes this item.
1866  * @param[out] error
1867  *   Pointer to error structure.
1868  *
1869  * @return
1870  *   0 on success, a negative errno value otherwise and rte_errno is set.
1871  */
1872 static int
1873 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1874                            const struct rte_flow_item *item,
1875                            const struct rte_flow_attr *attr __rte_unused,
1876                            struct rte_flow_error *error)
1877 {
1878         struct mlx5_priv *priv = dev->data->dev_private;
1879         struct mlx5_dev_config *config = &priv->config;
1880         const struct rte_flow_item_mark *spec = item->spec;
1881         const struct rte_flow_item_mark *mask = item->mask;
1882         const struct rte_flow_item_mark nic_mask = {
1883                 .id = priv->sh->dv_mark_mask,
1884         };
1885         int ret;
1886
1887         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1888                 return rte_flow_error_set(error, ENOTSUP,
1889                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1890                                           "extended metadata feature"
1891                                           " isn't enabled");
1892         if (!mlx5_flow_ext_mreg_supported(dev))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "extended metadata register"
1896                                           " isn't supported");
1897         if (!nic_mask.id)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "extended metadata register"
1901                                           " isn't available");
1902         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1903         if (ret < 0)
1904                 return ret;
1905         if (!spec)
1906                 return rte_flow_error_set(error, EINVAL,
1907                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1908                                           item->spec,
1909                                           "data cannot be empty");
1910         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1911                 return rte_flow_error_set(error, EINVAL,
1912                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1913                                           &spec->id,
1914                                           "mark id exceeds the limit");
1915         if (!mask)
1916                 mask = &nic_mask;
1917         if (!mask->id)
1918                 return rte_flow_error_set(error, EINVAL,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1920                                         "mask cannot be zero");
1921
1922         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1923                                         (const uint8_t *)&nic_mask,
1924                                         sizeof(struct rte_flow_item_mark),
1925                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1926         if (ret < 0)
1927                 return ret;
1928         return 0;
1929 }
1930
1931 /**
1932  * Validate META item.
1933  *
1934  * @param[in] dev
1935  *   Pointer to the rte_eth_dev structure.
1936  * @param[in] item
1937  *   Item specification.
1938  * @param[in] attr
1939  *   Attributes of flow that includes this item.
1940  * @param[out] error
1941  *   Pointer to error structure.
1942  *
1943  * @return
1944  *   0 on success, a negative errno value otherwise and rte_errno is set.
1945  */
1946 static int
1947 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1948                            const struct rte_flow_item *item,
1949                            const struct rte_flow_attr *attr,
1950                            struct rte_flow_error *error)
1951 {
1952         struct mlx5_priv *priv = dev->data->dev_private;
1953         struct mlx5_dev_config *config = &priv->config;
1954         const struct rte_flow_item_meta *spec = item->spec;
1955         const struct rte_flow_item_meta *mask = item->mask;
1956         struct rte_flow_item_meta nic_mask = {
1957                 .data = UINT32_MAX
1958         };
1959         int reg;
1960         int ret;
1961
1962         if (!spec)
1963                 return rte_flow_error_set(error, EINVAL,
1964                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965                                           item->spec,
1966                                           "data cannot be empty");
1967         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1968                 if (!mlx5_flow_ext_mreg_supported(dev))
1969                         return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1971                                           "extended metadata register"
1972                                           " isn't supported");
1973                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1974                 if (reg < 0)
1975                         return reg;
1976                 if (reg == REG_NON)
1977                         return rte_flow_error_set(error, ENOTSUP,
1978                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1979                                         "unavalable extended metadata register");
1980                 if (reg == REG_B)
1981                         return rte_flow_error_set(error, ENOTSUP,
1982                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1983                                           "match on reg_b "
1984                                           "isn't supported");
1985                 if (reg != REG_A)
1986                         nic_mask.data = priv->sh->dv_meta_mask;
1987         } else {
1988                 if (attr->transfer)
1989                         return rte_flow_error_set(error, ENOTSUP,
1990                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                         "extended metadata feature "
1992                                         "should be enabled when "
1993                                         "meta item is requested "
1994                                         "with e-switch mode ");
1995                 if (attr->ingress)
1996                         return rte_flow_error_set(error, ENOTSUP,
1997                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1998                                         "match on metadata for ingress "
1999                                         "is not supported in legacy "
2000                                         "metadata mode");
2001         }
2002         if (!mask)
2003                 mask = &rte_flow_item_meta_mask;
2004         if (!mask->data)
2005                 return rte_flow_error_set(error, EINVAL,
2006                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2007                                         "mask cannot be zero");
2008
2009         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2010                                         (const uint8_t *)&nic_mask,
2011                                         sizeof(struct rte_flow_item_meta),
2012                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2013         return ret;
2014 }
2015
2016 /**
2017  * Validate TAG item.
2018  *
2019  * @param[in] dev
2020  *   Pointer to the rte_eth_dev structure.
2021  * @param[in] item
2022  *   Item specification.
2023  * @param[in] attr
2024  *   Attributes of flow that includes this item.
2025  * @param[out] error
2026  *   Pointer to error structure.
2027  *
2028  * @return
2029  *   0 on success, a negative errno value otherwise and rte_errno is set.
2030  */
2031 static int
2032 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2033                           const struct rte_flow_item *item,
2034                           const struct rte_flow_attr *attr __rte_unused,
2035                           struct rte_flow_error *error)
2036 {
2037         const struct rte_flow_item_tag *spec = item->spec;
2038         const struct rte_flow_item_tag *mask = item->mask;
2039         const struct rte_flow_item_tag nic_mask = {
2040                 .data = RTE_BE32(UINT32_MAX),
2041                 .index = 0xff,
2042         };
2043         int ret;
2044
2045         if (!mlx5_flow_ext_mreg_supported(dev))
2046                 return rte_flow_error_set(error, ENOTSUP,
2047                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2048                                           "extensive metadata register"
2049                                           " isn't supported");
2050         if (!spec)
2051                 return rte_flow_error_set(error, EINVAL,
2052                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2053                                           item->spec,
2054                                           "data cannot be empty");
2055         if (!mask)
2056                 mask = &rte_flow_item_tag_mask;
2057         if (!mask->data)
2058                 return rte_flow_error_set(error, EINVAL,
2059                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2060                                         "mask cannot be zero");
2061
2062         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2063                                         (const uint8_t *)&nic_mask,
2064                                         sizeof(struct rte_flow_item_tag),
2065                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066         if (ret < 0)
2067                 return ret;
2068         if (mask->index != 0xff)
2069                 return rte_flow_error_set(error, EINVAL,
2070                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2071                                           "partial mask for tag index"
2072                                           " is not supported");
2073         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2074         if (ret < 0)
2075                 return ret;
2076         MLX5_ASSERT(ret != REG_NON);
2077         return 0;
2078 }
2079
2080 /**
2081  * Validate vport item.
2082  *
2083  * @param[in] dev
2084  *   Pointer to the rte_eth_dev structure.
2085  * @param[in] item
2086  *   Item specification.
2087  * @param[in] attr
2088  *   Attributes of flow that includes this item.
2089  * @param[in] item_flags
2090  *   Bit-fields that holds the items detected until now.
2091  * @param[out] error
2092  *   Pointer to error structure.
2093  *
2094  * @return
2095  *   0 on success, a negative errno value otherwise and rte_errno is set.
2096  */
2097 static int
2098 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2099                               const struct rte_flow_item *item,
2100                               const struct rte_flow_attr *attr,
2101                               uint64_t item_flags,
2102                               struct rte_flow_error *error)
2103 {
2104         const struct rte_flow_item_port_id *spec = item->spec;
2105         const struct rte_flow_item_port_id *mask = item->mask;
2106         const struct rte_flow_item_port_id switch_mask = {
2107                         .id = 0xffffffff,
2108         };
2109         struct mlx5_priv *esw_priv;
2110         struct mlx5_priv *dev_priv;
2111         int ret;
2112
2113         if (!attr->transfer)
2114                 return rte_flow_error_set(error, EINVAL,
2115                                           RTE_FLOW_ERROR_TYPE_ITEM,
2116                                           NULL,
2117                                           "match on port id is valid only"
2118                                           " when transfer flag is enabled");
2119         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2122                                           "multiple source ports are not"
2123                                           " supported");
2124         if (!mask)
2125                 mask = &switch_mask;
2126         if (mask->id != 0xffffffff)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2129                                            mask,
2130                                            "no support for partial mask on"
2131                                            " \"id\" field");
2132         ret = mlx5_flow_item_acceptable
2133                                 (item, (const uint8_t *)mask,
2134                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2135                                  sizeof(struct rte_flow_item_port_id),
2136                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2137         if (ret)
2138                 return ret;
2139         if (!spec)
2140                 return 0;
2141         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2142         if (!esw_priv)
2143                 return rte_flow_error_set(error, rte_errno,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2145                                           "failed to obtain E-Switch info for"
2146                                           " port");
2147         dev_priv = mlx5_dev_to_eswitch_info(dev);
2148         if (!dev_priv)
2149                 return rte_flow_error_set(error, rte_errno,
2150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2151                                           NULL,
2152                                           "failed to obtain E-Switch info");
2153         if (esw_priv->domain_id != dev_priv->domain_id)
2154                 return rte_flow_error_set(error, EINVAL,
2155                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2156                                           "cannot match on a port from a"
2157                                           " different E-Switch");
2158         return 0;
2159 }
2160
2161 /**
2162  * Validate VLAN item.
2163  *
2164  * @param[in] item
2165  *   Item specification.
2166  * @param[in] item_flags
2167  *   Bit-fields that holds the items detected until now.
2168  * @param[in] dev
2169  *   Ethernet device flow is being created on.
2170  * @param[out] error
2171  *   Pointer to error structure.
2172  *
2173  * @return
2174  *   0 on success, a negative errno value otherwise and rte_errno is set.
2175  */
2176 static int
2177 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2178                            uint64_t item_flags,
2179                            struct rte_eth_dev *dev,
2180                            struct rte_flow_error *error)
2181 {
2182         const struct rte_flow_item_vlan *mask = item->mask;
2183         const struct rte_flow_item_vlan nic_mask = {
2184                 .tci = RTE_BE16(UINT16_MAX),
2185                 .inner_type = RTE_BE16(UINT16_MAX),
2186                 .has_more_vlan = 1,
2187         };
2188         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2189         int ret;
2190         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2191                                         MLX5_FLOW_LAYER_INNER_L4) :
2192                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2193                                         MLX5_FLOW_LAYER_OUTER_L4);
2194         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2195                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2196
2197         if (item_flags & vlanm)
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2200                                           "multiple VLAN layers not supported");
2201         else if ((item_flags & l34m) != 0)
2202                 return rte_flow_error_set(error, EINVAL,
2203                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2204                                           "VLAN cannot follow L3/L4 layer");
2205         if (!mask)
2206                 mask = &rte_flow_item_vlan_mask;
2207         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2208                                         (const uint8_t *)&nic_mask,
2209                                         sizeof(struct rte_flow_item_vlan),
2210                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2211         if (ret)
2212                 return ret;
2213         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2214                 struct mlx5_priv *priv = dev->data->dev_private;
2215
2216                 if (priv->vmwa_context) {
2217                         /*
2218                          * Non-NULL context means we have a virtual machine
2219                          * and SR-IOV enabled, we have to create VLAN interface
2220                          * to make hypervisor to setup E-Switch vport
2221                          * context correctly. We avoid creating the multiple
2222                          * VLAN interfaces, so we cannot support VLAN tag mask.
2223                          */
2224                         return rte_flow_error_set(error, EINVAL,
2225                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2226                                                   item,
2227                                                   "VLAN tag mask is not"
2228                                                   " supported in virtual"
2229                                                   " environment");
2230                 }
2231         }
2232         return 0;
2233 }
2234
2235 /*
2236  * GTP flags are contained in 1 byte of the format:
2237  * -------------------------------------------
2238  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2239  * |-----------------------------------------|
2240  * | value | Version | PT | Res | E | S | PN |
2241  * -------------------------------------------
2242  *
2243  * Matching is supported only for GTP flags E, S, PN.
2244  */
2245 #define MLX5_GTP_FLAGS_MASK     0x07
2246
2247 /**
2248  * Validate GTP item.
2249  *
2250  * @param[in] dev
2251  *   Pointer to the rte_eth_dev structure.
2252  * @param[in] item
2253  *   Item specification.
2254  * @param[in] item_flags
2255  *   Bit-fields that holds the items detected until now.
2256  * @param[out] error
2257  *   Pointer to error structure.
2258  *
2259  * @return
2260  *   0 on success, a negative errno value otherwise and rte_errno is set.
2261  */
2262 static int
2263 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2264                           const struct rte_flow_item *item,
2265                           uint64_t item_flags,
2266                           struct rte_flow_error *error)
2267 {
2268         struct mlx5_priv *priv = dev->data->dev_private;
2269         const struct rte_flow_item_gtp *spec = item->spec;
2270         const struct rte_flow_item_gtp *mask = item->mask;
2271         const struct rte_flow_item_gtp nic_mask = {
2272                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2273                 .msg_type = 0xff,
2274                 .teid = RTE_BE32(0xffffffff),
2275         };
2276
2277         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2278                 return rte_flow_error_set(error, ENOTSUP,
2279                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                                           "GTP support is not enabled");
2281         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2282                 return rte_flow_error_set(error, ENOTSUP,
2283                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2284                                           "multiple tunnel layers not"
2285                                           " supported");
2286         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2287                 return rte_flow_error_set(error, EINVAL,
2288                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                                           "no outer UDP layer found");
2290         if (!mask)
2291                 mask = &rte_flow_item_gtp_mask;
2292         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2293                 return rte_flow_error_set(error, ENOTSUP,
2294                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2295                                           "Match is supported for GTP"
2296                                           " flags only");
2297         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2298                                          (const uint8_t *)&nic_mask,
2299                                          sizeof(struct rte_flow_item_gtp),
2300                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2301 }
2302
2303 /**
2304  * Validate GTP PSC item.
2305  *
2306  * @param[in] item
2307  *   Item specification.
2308  * @param[in] last_item
2309  *   Previous validated item in the pattern items.
2310  * @param[in] gtp_item
2311  *   Previous GTP item specification.
2312  * @param[in] attr
2313  *   Pointer to flow attributes.
2314  * @param[out] error
2315  *   Pointer to error structure.
2316  *
2317  * @return
2318  *   0 on success, a negative errno value otherwise and rte_errno is set.
2319  */
2320 static int
2321 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2322                               uint64_t last_item,
2323                               const struct rte_flow_item *gtp_item,
2324                               const struct rte_flow_attr *attr,
2325                               struct rte_flow_error *error)
2326 {
2327         const struct rte_flow_item_gtp *gtp_spec;
2328         const struct rte_flow_item_gtp *gtp_mask;
2329         const struct rte_flow_item_gtp_psc *spec;
2330         const struct rte_flow_item_gtp_psc *mask;
2331         const struct rte_flow_item_gtp_psc nic_mask = {
2332                 .pdu_type = 0xFF,
2333                 .qfi = 0xFF,
2334         };
2335
2336         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2337                 return rte_flow_error_set
2338                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2339                          "GTP PSC item must be preceded with GTP item");
2340         gtp_spec = gtp_item->spec;
2341         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2342         /* GTP spec and E flag is requested to match zero. */
2343         if (gtp_spec &&
2344                 (gtp_mask->v_pt_rsv_flags &
2345                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2346                 return rte_flow_error_set
2347                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2348                          "GTP E flag must be 1 to match GTP PSC");
2349         /* Check the flow is not created in group zero. */
2350         if (!attr->transfer && !attr->group)
2351                 return rte_flow_error_set
2352                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2353                          "GTP PSC is not supported for group 0");
2354         /* GTP spec is here and E flag is requested to match zero. */
2355         if (!item->spec)
2356                 return 0;
2357         spec = item->spec;
2358         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2359         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2360                 return rte_flow_error_set
2361                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2362                          "PDU type should be smaller than 16");
2363         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2364                                          (const uint8_t *)&nic_mask,
2365                                          sizeof(struct rte_flow_item_gtp_psc),
2366                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2367 }
2368
2369 /**
2370  * Validate IPV4 item.
2371  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2372  * add specific validation of fragment_offset field,
2373  *
2374  * @param[in] item
2375  *   Item specification.
2376  * @param[in] item_flags
2377  *   Bit-fields that holds the items detected until now.
2378  * @param[out] error
2379  *   Pointer to error structure.
2380  *
2381  * @return
2382  *   0 on success, a negative errno value otherwise and rte_errno is set.
2383  */
2384 static int
2385 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2386                            uint64_t item_flags,
2387                            uint64_t last_item,
2388                            uint16_t ether_type,
2389                            struct rte_flow_error *error)
2390 {
2391         int ret;
2392         const struct rte_flow_item_ipv4 *spec = item->spec;
2393         const struct rte_flow_item_ipv4 *last = item->last;
2394         const struct rte_flow_item_ipv4 *mask = item->mask;
2395         rte_be16_t fragment_offset_spec = 0;
2396         rte_be16_t fragment_offset_last = 0;
2397         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2398                 .hdr = {
2399                         .src_addr = RTE_BE32(0xffffffff),
2400                         .dst_addr = RTE_BE32(0xffffffff),
2401                         .type_of_service = 0xff,
2402                         .fragment_offset = RTE_BE16(0xffff),
2403                         .next_proto_id = 0xff,
2404                         .time_to_live = 0xff,
2405                 },
2406         };
2407
2408         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2409                                            ether_type, &nic_ipv4_mask,
2410                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2411         if (ret < 0)
2412                 return ret;
2413         if (spec && mask)
2414                 fragment_offset_spec = spec->hdr.fragment_offset &
2415                                        mask->hdr.fragment_offset;
2416         if (!fragment_offset_spec)
2417                 return 0;
2418         /*
2419          * spec and mask are valid, enforce using full mask to make sure the
2420          * complete value is used correctly.
2421          */
2422         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2424                 return rte_flow_error_set(error, EINVAL,
2425                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2426                                           item, "must use full mask for"
2427                                           " fragment_offset");
2428         /*
2429          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2430          * indicating this is 1st fragment of fragmented packet.
2431          * This is not yet supported in MLX5, return appropriate error message.
2432          */
2433         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2434                 return rte_flow_error_set(error, ENOTSUP,
2435                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2436                                           "match on first fragment not "
2437                                           "supported");
2438         if (fragment_offset_spec && !last)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2441                                           "specified value not supported");
2442         /* spec and last are valid, validate the specified range. */
2443         fragment_offset_last = last->hdr.fragment_offset &
2444                                mask->hdr.fragment_offset;
2445         /*
2446          * Match on fragment_offset spec 0x2001 and last 0x3fff
2447          * means MF is 1 and frag-offset is > 0.
2448          * This packet is fragment 2nd and onward, excluding last.
2449          * This is not yet supported in MLX5, return appropriate
2450          * error message.
2451          */
2452         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2453             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2454                 return rte_flow_error_set(error, ENOTSUP,
2455                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2456                                           last, "match on following "
2457                                           "fragments not supported");
2458         /*
2459          * Match on fragment_offset spec 0x0001 and last 0x1fff
2460          * means MF is 0 and frag-offset is > 0.
2461          * This packet is last fragment of fragmented packet.
2462          * This is not yet supported in MLX5, return appropriate
2463          * error message.
2464          */
2465         if (fragment_offset_spec == RTE_BE16(1) &&
2466             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2467                 return rte_flow_error_set(error, ENOTSUP,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2469                                           last, "match on last "
2470                                           "fragment not supported");
2471         /*
2472          * Match on fragment_offset spec 0x0001 and last 0x3fff
2473          * means MF and/or frag-offset is not 0.
2474          * This is a fragmented packet.
2475          * Other range values are invalid and rejected.
2476          */
2477         if (!(fragment_offset_spec == RTE_BE16(1) &&
2478               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2481                                           "specified range not supported");
2482         return 0;
2483 }
2484
2485 /**
2486  * Validate IPV6 fragment extension item.
2487  *
2488  * @param[in] item
2489  *   Item specification.
2490  * @param[in] item_flags
2491  *   Bit-fields that holds the items detected until now.
2492  * @param[out] error
2493  *   Pointer to error structure.
2494  *
2495  * @return
2496  *   0 on success, a negative errno value otherwise and rte_errno is set.
2497  */
2498 static int
2499 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2500                                     uint64_t item_flags,
2501                                     struct rte_flow_error *error)
2502 {
2503         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2504         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2505         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2506         rte_be16_t frag_data_spec = 0;
2507         rte_be16_t frag_data_last = 0;
2508         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2509         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2510                                       MLX5_FLOW_LAYER_OUTER_L4;
2511         int ret = 0;
2512         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2513                 .hdr = {
2514                         .next_header = 0xff,
2515                         .frag_data = RTE_BE16(0xffff),
2516                 },
2517         };
2518
2519         if (item_flags & l4m)
2520                 return rte_flow_error_set(error, EINVAL,
2521                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2522                                           "ipv6 fragment extension item cannot "
2523                                           "follow L4 item.");
2524         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2525             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2526                 return rte_flow_error_set(error, EINVAL,
2527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2528                                           "ipv6 fragment extension item must "
2529                                           "follow ipv6 item");
2530         if (spec && mask)
2531                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2532         if (!frag_data_spec)
2533                 return 0;
2534         /*
2535          * spec and mask are valid, enforce using full mask to make sure the
2536          * complete value is used correctly.
2537          */
2538         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2539                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2540                 return rte_flow_error_set(error, EINVAL,
2541                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2542                                           item, "must use full mask for"
2543                                           " frag_data");
2544         /*
2545          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2546          * This is 1st fragment of fragmented packet.
2547          */
2548         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2549                 return rte_flow_error_set(error, ENOTSUP,
2550                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2551                                           "match on first fragment not "
2552                                           "supported");
2553         if (frag_data_spec && !last)
2554                 return rte_flow_error_set(error, EINVAL,
2555                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2556                                           "specified value not supported");
2557         ret = mlx5_flow_item_acceptable
2558                                 (item, (const uint8_t *)mask,
2559                                  (const uint8_t *)&nic_mask,
2560                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2561                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2562         if (ret)
2563                 return ret;
2564         /* spec and last are valid, validate the specified range. */
2565         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2566         /*
2567          * Match on frag_data spec 0x0009 and last 0xfff9
2568          * means M is 1 and frag-offset is > 0.
2569          * This packet is fragment 2nd and onward, excluding last.
2570          * This is not yet supported in MLX5, return appropriate
2571          * error message.
2572          */
2573         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2574                                        RTE_IPV6_EHDR_MF_MASK) &&
2575             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2578                                           last, "match on following "
2579                                           "fragments not supported");
2580         /*
2581          * Match on frag_data spec 0x0008 and last 0xfff8
2582          * means M is 0 and frag-offset is > 0.
2583          * This packet is last fragment of fragmented packet.
2584          * This is not yet supported in MLX5, return appropriate
2585          * error message.
2586          */
2587         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2588             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2589                 return rte_flow_error_set(error, ENOTSUP,
2590                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2591                                           last, "match on last "
2592                                           "fragment not supported");
2593         /* Other range values are invalid and rejected. */
2594         return rte_flow_error_set(error, EINVAL,
2595                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2596                                   "specified range not supported");
2597 }
2598
2599 /**
2600  * Validate the pop VLAN action.
2601  *
2602  * @param[in] dev
2603  *   Pointer to the rte_eth_dev structure.
2604  * @param[in] action_flags
2605  *   Holds the actions detected until now.
2606  * @param[in] action
2607  *   Pointer to the pop vlan action.
2608  * @param[in] item_flags
2609  *   The items found in this flow rule.
2610  * @param[in] attr
2611  *   Pointer to flow attributes.
2612  * @param[out] error
2613  *   Pointer to error structure.
2614  *
2615  * @return
2616  *   0 on success, a negative errno value otherwise and rte_errno is set.
2617  */
2618 static int
2619 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2620                                  uint64_t action_flags,
2621                                  const struct rte_flow_action *action,
2622                                  uint64_t item_flags,
2623                                  const struct rte_flow_attr *attr,
2624                                  struct rte_flow_error *error)
2625 {
2626         const struct mlx5_priv *priv = dev->data->dev_private;
2627
2628         (void)action;
2629         (void)attr;
2630         if (!priv->sh->pop_vlan_action)
2631                 return rte_flow_error_set(error, ENOTSUP,
2632                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2633                                           NULL,
2634                                           "pop vlan action is not supported");
2635         if (attr->egress)
2636                 return rte_flow_error_set(error, ENOTSUP,
2637                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2638                                           NULL,
2639                                           "pop vlan action not supported for "
2640                                           "egress");
2641         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2642                 return rte_flow_error_set(error, ENOTSUP,
2643                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2644                                           "no support for multiple VLAN "
2645                                           "actions");
2646         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2647         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2648             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2649                 return rte_flow_error_set(error, ENOTSUP,
2650                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2651                                           NULL,
2652                                           "cannot pop vlan after decap without "
2653                                           "match on inner vlan in the flow");
2654         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2655         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2656             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2657                 return rte_flow_error_set(error, ENOTSUP,
2658                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2659                                           NULL,
2660                                           "cannot pop vlan without a "
2661                                           "match on (outer) vlan in the flow");
2662         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2663                 return rte_flow_error_set(error, EINVAL,
2664                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2665                                           "wrong action order, port_id should "
2666                                           "be after pop VLAN action");
2667         if (!attr->transfer && priv->representor)
2668                 return rte_flow_error_set(error, ENOTSUP,
2669                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2670                                           "pop vlan action for VF representor "
2671                                           "not supported on NIC table");
2672         return 0;
2673 }
2674
2675 /**
2676  * Get VLAN default info from vlan match info.
2677  *
2678  * @param[in] items
2679  *   the list of item specifications.
2680  * @param[out] vlan
2681  *   pointer VLAN info to fill to.
2682  *
2683  * @return
2684  *   0 on success, a negative errno value otherwise and rte_errno is set.
2685  */
2686 static void
2687 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2688                                   struct rte_vlan_hdr *vlan)
2689 {
2690         const struct rte_flow_item_vlan nic_mask = {
2691                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2692                                 MLX5DV_FLOW_VLAN_VID_MASK),
2693                 .inner_type = RTE_BE16(0xffff),
2694         };
2695
2696         if (items == NULL)
2697                 return;
2698         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2699                 int type = items->type;
2700
2701                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2702                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2703                         break;
2704         }
2705         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2706                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2707                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2708
2709                 /* If VLAN item in pattern doesn't contain data, return here. */
2710                 if (!vlan_v)
2711                         return;
2712                 if (!vlan_m)
2713                         vlan_m = &nic_mask;
2714                 /* Only full match values are accepted */
2715                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2716                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2717                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2718                         vlan->vlan_tci |=
2719                                 rte_be_to_cpu_16(vlan_v->tci &
2720                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2721                 }
2722                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2723                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2724                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2725                         vlan->vlan_tci |=
2726                                 rte_be_to_cpu_16(vlan_v->tci &
2727                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2728                 }
2729                 if (vlan_m->inner_type == nic_mask.inner_type)
2730                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2731                                                            vlan_m->inner_type);
2732         }
2733 }
2734
2735 /**
2736  * Validate the push VLAN action.
2737  *
2738  * @param[in] dev
2739  *   Pointer to the rte_eth_dev structure.
2740  * @param[in] action_flags
2741  *   Holds the actions detected until now.
2742  * @param[in] item_flags
2743  *   The items found in this flow rule.
2744  * @param[in] action
2745  *   Pointer to the action structure.
2746  * @param[in] attr
2747  *   Pointer to flow attributes
2748  * @param[out] error
2749  *   Pointer to error structure.
2750  *
2751  * @return
2752  *   0 on success, a negative errno value otherwise and rte_errno is set.
2753  */
2754 static int
2755 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2756                                   uint64_t action_flags,
2757                                   const struct rte_flow_item_vlan *vlan_m,
2758                                   const struct rte_flow_action *action,
2759                                   const struct rte_flow_attr *attr,
2760                                   struct rte_flow_error *error)
2761 {
2762         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2763         const struct mlx5_priv *priv = dev->data->dev_private;
2764
2765         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2766             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2767                 return rte_flow_error_set(error, EINVAL,
2768                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2769                                           "invalid vlan ethertype");
2770         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2771                 return rte_flow_error_set(error, EINVAL,
2772                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2773                                           "wrong action order, port_id should "
2774                                           "be after push VLAN");
2775         if (!attr->transfer && priv->representor)
2776                 return rte_flow_error_set(error, ENOTSUP,
2777                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2778                                           "push vlan action for VF representor "
2779                                           "not supported on NIC table");
2780         if (vlan_m &&
2781             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2782             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2783                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2784             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2785             !(mlx5_flow_find_action
2786                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "not full match mask on VLAN PCP and "
2790                                           "there is no of_set_vlan_pcp action, "
2791                                           "push VLAN action cannot figure out "
2792                                           "PCP value");
2793         if (vlan_m &&
2794             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2795             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2796                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2797             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2798             !(mlx5_flow_find_action
2799                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2800                 return rte_flow_error_set(error, EINVAL,
2801                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2802                                           "not full match mask on VLAN VID and "
2803                                           "there is no of_set_vlan_vid action, "
2804                                           "push VLAN action cannot figure out "
2805                                           "VID value");
2806         (void)attr;
2807         return 0;
2808 }
2809
2810 /**
2811  * Validate the set VLAN PCP.
2812  *
2813  * @param[in] action_flags
2814  *   Holds the actions detected until now.
2815  * @param[in] actions
2816  *   Pointer to the list of actions remaining in the flow rule.
2817  * @param[out] error
2818  *   Pointer to error structure.
2819  *
2820  * @return
2821  *   0 on success, a negative errno value otherwise and rte_errno is set.
2822  */
2823 static int
2824 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2825                                      const struct rte_flow_action actions[],
2826                                      struct rte_flow_error *error)
2827 {
2828         const struct rte_flow_action *action = actions;
2829         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2830
2831         if (conf->vlan_pcp > 7)
2832                 return rte_flow_error_set(error, EINVAL,
2833                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2834                                           "VLAN PCP value is too big");
2835         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2836                 return rte_flow_error_set(error, ENOTSUP,
2837                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2838                                           "set VLAN PCP action must follow "
2839                                           "the push VLAN action");
2840         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2841                 return rte_flow_error_set(error, ENOTSUP,
2842                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2843                                           "Multiple VLAN PCP modification are "
2844                                           "not supported");
2845         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2846                 return rte_flow_error_set(error, EINVAL,
2847                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2848                                           "wrong action order, port_id should "
2849                                           "be after set VLAN PCP");
2850         return 0;
2851 }
2852
2853 /**
2854  * Validate the set VLAN VID.
2855  *
2856  * @param[in] item_flags
2857  *   Holds the items detected in this rule.
2858  * @param[in] action_flags
2859  *   Holds the actions detected until now.
2860  * @param[in] actions
2861  *   Pointer to the list of actions remaining in the flow rule.
2862  * @param[out] error
2863  *   Pointer to error structure.
2864  *
2865  * @return
2866  *   0 on success, a negative errno value otherwise and rte_errno is set.
2867  */
2868 static int
2869 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2870                                      uint64_t action_flags,
2871                                      const struct rte_flow_action actions[],
2872                                      struct rte_flow_error *error)
2873 {
2874         const struct rte_flow_action *action = actions;
2875         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2876
2877         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2878                 return rte_flow_error_set(error, EINVAL,
2879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2880                                           "VLAN VID value is too big");
2881         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2882             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2883                 return rte_flow_error_set(error, ENOTSUP,
2884                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2885                                           "set VLAN VID action must follow push"
2886                                           " VLAN action or match on VLAN item");
2887         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2888                 return rte_flow_error_set(error, ENOTSUP,
2889                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2890                                           "Multiple VLAN VID modifications are "
2891                                           "not supported");
2892         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2893                 return rte_flow_error_set(error, EINVAL,
2894                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2895                                           "wrong action order, port_id should "
2896                                           "be after set VLAN VID");
2897         return 0;
2898 }
2899
2900 /*
2901  * Validate the FLAG action.
2902  *
2903  * @param[in] dev
2904  *   Pointer to the rte_eth_dev structure.
2905  * @param[in] action_flags
2906  *   Holds the actions detected until now.
2907  * @param[in] attr
2908  *   Pointer to flow attributes
2909  * @param[out] error
2910  *   Pointer to error structure.
2911  *
2912  * @return
2913  *   0 on success, a negative errno value otherwise and rte_errno is set.
2914  */
2915 static int
2916 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         int ret;
2924
2925         /* Fall back if no extended metadata register support. */
2926         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2927                 return mlx5_flow_validate_action_flag(action_flags, attr,
2928                                                       error);
2929         /* Extensive metadata mode requires registers. */
2930         if (!mlx5_flow_ext_mreg_supported(dev))
2931                 return rte_flow_error_set(error, ENOTSUP,
2932                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933                                           "no metadata registers "
2934                                           "to support flag action");
2935         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2936                 return rte_flow_error_set(error, ENOTSUP,
2937                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2938                                           "extended metadata register"
2939                                           " isn't available");
2940         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2941         if (ret < 0)
2942                 return ret;
2943         MLX5_ASSERT(ret > 0);
2944         if (action_flags & MLX5_FLOW_ACTION_MARK)
2945                 return rte_flow_error_set(error, EINVAL,
2946                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2947                                           "can't mark and flag in same flow");
2948         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949                 return rte_flow_error_set(error, EINVAL,
2950                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2951                                           "can't have 2 flag"
2952                                           " actions in same flow");
2953         return 0;
2954 }
2955
2956 /**
2957  * Validate MARK action.
2958  *
2959  * @param[in] dev
2960  *   Pointer to the rte_eth_dev structure.
2961  * @param[in] action
2962  *   Pointer to action.
2963  * @param[in] action_flags
2964  *   Holds the actions detected until now.
2965  * @param[in] attr
2966  *   Pointer to flow attributes
2967  * @param[out] error
2968  *   Pointer to error structure.
2969  *
2970  * @return
2971  *   0 on success, a negative errno value otherwise and rte_errno is set.
2972  */
2973 static int
2974 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2975                              const struct rte_flow_action *action,
2976                              uint64_t action_flags,
2977                              const struct rte_flow_attr *attr,
2978                              struct rte_flow_error *error)
2979 {
2980         struct mlx5_priv *priv = dev->data->dev_private;
2981         struct mlx5_dev_config *config = &priv->config;
2982         const struct rte_flow_action_mark *mark = action->conf;
2983         int ret;
2984
2985         if (is_tunnel_offload_active(dev))
2986                 return rte_flow_error_set(error, ENOTSUP,
2987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2988                                           "no mark action "
2989                                           "if tunnel offload active");
2990         /* Fall back if no extended metadata register support. */
2991         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2992                 return mlx5_flow_validate_action_mark(action, action_flags,
2993                                                       attr, error);
2994         /* Extensive metadata mode requires registers. */
2995         if (!mlx5_flow_ext_mreg_supported(dev))
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2998                                           "no metadata registers "
2999                                           "to support mark action");
3000         if (!priv->sh->dv_mark_mask)
3001                 return rte_flow_error_set(error, ENOTSUP,
3002                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3003                                           "extended metadata register"
3004                                           " isn't available");
3005         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3006         if (ret < 0)
3007                 return ret;
3008         MLX5_ASSERT(ret > 0);
3009         if (!mark)
3010                 return rte_flow_error_set(error, EINVAL,
3011                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3012                                           "configuration cannot be null");
3013         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3014                 return rte_flow_error_set(error, EINVAL,
3015                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3016                                           &mark->id,
3017                                           "mark id exceeds the limit");
3018         if (action_flags & MLX5_FLOW_ACTION_FLAG)
3019                 return rte_flow_error_set(error, EINVAL,
3020                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3021                                           "can't flag and mark in same flow");
3022         if (action_flags & MLX5_FLOW_ACTION_MARK)
3023                 return rte_flow_error_set(error, EINVAL,
3024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025                                           "can't have 2 mark actions in same"
3026                                           " flow");
3027         return 0;
3028 }
3029
3030 /**
3031  * Validate SET_META action.
3032  *
3033  * @param[in] dev
3034  *   Pointer to the rte_eth_dev structure.
3035  * @param[in] action
3036  *   Pointer to the action structure.
3037  * @param[in] action_flags
3038  *   Holds the actions detected until now.
3039  * @param[in] attr
3040  *   Pointer to flow attributes
3041  * @param[out] error
3042  *   Pointer to error structure.
3043  *
3044  * @return
3045  *   0 on success, a negative errno value otherwise and rte_errno is set.
3046  */
3047 static int
3048 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3049                                  const struct rte_flow_action *action,
3050                                  uint64_t action_flags __rte_unused,
3051                                  const struct rte_flow_attr *attr,
3052                                  struct rte_flow_error *error)
3053 {
3054         const struct rte_flow_action_set_meta *conf;
3055         uint32_t nic_mask = UINT32_MAX;
3056         int reg;
3057
3058         if (!mlx5_flow_ext_mreg_supported(dev))
3059                 return rte_flow_error_set(error, ENOTSUP,
3060                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3061                                           "extended metadata register"
3062                                           " isn't supported");
3063         reg = flow_dv_get_metadata_reg(dev, attr, error);
3064         if (reg < 0)
3065                 return reg;
3066         if (reg == REG_NON)
3067                 return rte_flow_error_set(error, ENOTSUP,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3069                                           "unavalable extended metadata register");
3070         if (reg != REG_A && reg != REG_B) {
3071                 struct mlx5_priv *priv = dev->data->dev_private;
3072
3073                 nic_mask = priv->sh->dv_meta_mask;
3074         }
3075         if (!(action->conf))
3076                 return rte_flow_error_set(error, EINVAL,
3077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3078                                           "configuration cannot be null");
3079         conf = (const struct rte_flow_action_set_meta *)action->conf;
3080         if (!conf->mask)
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "zero mask doesn't have any effect");
3084         if (conf->mask & ~nic_mask)
3085                 return rte_flow_error_set(error, EINVAL,
3086                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3087                                           "meta data must be within reg C0");
3088         return 0;
3089 }
3090
3091 /**
3092  * Validate SET_TAG action.
3093  *
3094  * @param[in] dev
3095  *   Pointer to the rte_eth_dev structure.
3096  * @param[in] action
3097  *   Pointer to the action structure.
3098  * @param[in] action_flags
3099  *   Holds the actions detected until now.
3100  * @param[in] attr
3101  *   Pointer to flow attributes
3102  * @param[out] error
3103  *   Pointer to error structure.
3104  *
3105  * @return
3106  *   0 on success, a negative errno value otherwise and rte_errno is set.
3107  */
3108 static int
3109 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3110                                 const struct rte_flow_action *action,
3111                                 uint64_t action_flags,
3112                                 const struct rte_flow_attr *attr,
3113                                 struct rte_flow_error *error)
3114 {
3115         const struct rte_flow_action_set_tag *conf;
3116         const uint64_t terminal_action_flags =
3117                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3118                 MLX5_FLOW_ACTION_RSS;
3119         int ret;
3120
3121         if (!mlx5_flow_ext_mreg_supported(dev))
3122                 return rte_flow_error_set(error, ENOTSUP,
3123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3124                                           "extensive metadata register"
3125                                           " isn't supported");
3126         if (!(action->conf))
3127                 return rte_flow_error_set(error, EINVAL,
3128                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3129                                           "configuration cannot be null");
3130         conf = (const struct rte_flow_action_set_tag *)action->conf;
3131         if (!conf->mask)
3132                 return rte_flow_error_set(error, EINVAL,
3133                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3134                                           "zero mask doesn't have any effect");
3135         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3136         if (ret < 0)
3137                 return ret;
3138         if (!attr->transfer && attr->ingress &&
3139             (action_flags & terminal_action_flags))
3140                 return rte_flow_error_set(error, EINVAL,
3141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3142                                           "set_tag has no effect"
3143                                           " with terminal actions");
3144         return 0;
3145 }
3146
3147 /**
3148  * Validate count action.
3149  *
3150  * @param[in] dev
3151  *   Pointer to rte_eth_dev structure.
3152  * @param[in] action
3153  *   Pointer to the action structure.
3154  * @param[in] action_flags
3155  *   Holds the actions detected until now.
3156  * @param[out] error
3157  *   Pointer to error structure.
3158  *
3159  * @return
3160  *   0 on success, a negative errno value otherwise and rte_errno is set.
3161  */
3162 static int
3163 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3164                               const struct rte_flow_action *action,
3165                               uint64_t action_flags,
3166                               struct rte_flow_error *error)
3167 {
3168         struct mlx5_priv *priv = dev->data->dev_private;
3169         const struct rte_flow_action_count *count;
3170
3171         if (!priv->config.devx)
3172                 goto notsup_err;
3173         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3174                 return rte_flow_error_set(error, EINVAL,
3175                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3176                                           "duplicate count actions set");
3177         count = (const struct rte_flow_action_count *)action->conf;
3178         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3179             !priv->sh->flow_hit_aso_en)
3180                 return rte_flow_error_set(error, EINVAL,
3181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3182                                           "old age and shared count combination is not supported");
3183 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3184         return 0;
3185 #endif
3186 notsup_err:
3187         return rte_flow_error_set
3188                       (error, ENOTSUP,
3189                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3190                        NULL,
3191                        "count action not supported");
3192 }
3193
3194 /**
3195  * Validate the L2 encap action.
3196  *
3197  * @param[in] dev
3198  *   Pointer to the rte_eth_dev structure.
3199  * @param[in] action_flags
3200  *   Holds the actions detected until now.
3201  * @param[in] action
3202  *   Pointer to the action structure.
3203  * @param[in] attr
3204  *   Pointer to flow attributes.
3205  * @param[out] error
3206  *   Pointer to error structure.
3207  *
3208  * @return
3209  *   0 on success, a negative errno value otherwise and rte_errno is set.
3210  */
3211 static int
3212 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3213                                  uint64_t action_flags,
3214                                  const struct rte_flow_action *action,
3215                                  const struct rte_flow_attr *attr,
3216                                  struct rte_flow_error *error)
3217 {
3218         const struct mlx5_priv *priv = dev->data->dev_private;
3219
3220         if (!(action->conf))
3221                 return rte_flow_error_set(error, EINVAL,
3222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3223                                           "configuration cannot be null");
3224         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3225                 return rte_flow_error_set(error, EINVAL,
3226                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3227                                           "can only have a single encap action "
3228                                           "in a flow");
3229         if (!attr->transfer && priv->representor)
3230                 return rte_flow_error_set(error, ENOTSUP,
3231                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3232                                           "encap action for VF representor "
3233                                           "not supported on NIC table");
3234         return 0;
3235 }
3236
3237 /**
3238  * Validate a decap action.
3239  *
3240  * @param[in] dev
3241  *   Pointer to the rte_eth_dev structure.
3242  * @param[in] action_flags
3243  *   Holds the actions detected until now.
3244  * @param[in] action
3245  *   Pointer to the action structure.
3246  * @param[in] item_flags
3247  *   Holds the items detected.
3248  * @param[in] attr
3249  *   Pointer to flow attributes
3250  * @param[out] error
3251  *   Pointer to error structure.
3252  *
3253  * @return
3254  *   0 on success, a negative errno value otherwise and rte_errno is set.
3255  */
3256 static int
3257 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3258                               uint64_t action_flags,
3259                               const struct rte_flow_action *action,
3260                               const uint64_t item_flags,
3261                               const struct rte_flow_attr *attr,
3262                               struct rte_flow_error *error)
3263 {
3264         const struct mlx5_priv *priv = dev->data->dev_private;
3265
3266         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3267             !priv->config.decap_en)
3268                 return rte_flow_error_set(error, ENOTSUP,
3269                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3270                                           "decap is not enabled");
3271         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3272                 return rte_flow_error_set(error, ENOTSUP,
3273                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3274                                           action_flags &
3275                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3276                                           "have a single decap action" : "decap "
3277                                           "after encap is not supported");
3278         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3281                                           "can't have decap action after"
3282                                           " modify action");
3283         if (attr->egress)
3284                 return rte_flow_error_set(error, ENOTSUP,
3285                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3286                                           NULL,
3287                                           "decap action not supported for "
3288                                           "egress");
3289         if (!attr->transfer && priv->representor)
3290                 return rte_flow_error_set(error, ENOTSUP,
3291                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3292                                           "decap action for VF representor "
3293                                           "not supported on NIC table");
3294         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3295             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3296                 return rte_flow_error_set(error, ENOTSUP,
3297                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3298                                 "VXLAN item should be present for VXLAN decap");
3299         return 0;
3300 }
3301
3302 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3303
3304 /**
3305  * Validate the raw encap and decap actions.
3306  *
3307  * @param[in] dev
3308  *   Pointer to the rte_eth_dev structure.
3309  * @param[in] decap
3310  *   Pointer to the decap action.
3311  * @param[in] encap
3312  *   Pointer to the encap action.
3313  * @param[in] attr
3314  *   Pointer to flow attributes
3315  * @param[in/out] action_flags
3316  *   Holds the actions detected until now.
3317  * @param[out] actions_n
3318  *   pointer to the number of actions counter.
3319  * @param[in] action
3320  *   Pointer to the action structure.
3321  * @param[in] item_flags
3322  *   Holds the items detected.
3323  * @param[out] error
3324  *   Pointer to error structure.
3325  *
3326  * @return
3327  *   0 on success, a negative errno value otherwise and rte_errno is set.
3328  */
3329 static int
3330 flow_dv_validate_action_raw_encap_decap
3331         (struct rte_eth_dev *dev,
3332          const struct rte_flow_action_raw_decap *decap,
3333          const struct rte_flow_action_raw_encap *encap,
3334          const struct rte_flow_attr *attr, uint64_t *action_flags,
3335          int *actions_n, const struct rte_flow_action *action,
3336          uint64_t item_flags, struct rte_flow_error *error)
3337 {
3338         const struct mlx5_priv *priv = dev->data->dev_private;
3339         int ret;
3340
3341         if (encap && (!encap->size || !encap->data))
3342                 return rte_flow_error_set(error, EINVAL,
3343                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3344                                           "raw encap data cannot be empty");
3345         if (decap && encap) {
3346                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3347                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3348                         /* L3 encap. */
3349                         decap = NULL;
3350                 else if (encap->size <=
3351                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3352                            decap->size >
3353                            MLX5_ENCAPSULATION_DECISION_SIZE)
3354                         /* L3 decap. */
3355                         encap = NULL;
3356                 else if (encap->size >
3357                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3358                            decap->size >
3359                            MLX5_ENCAPSULATION_DECISION_SIZE)
3360                         /* 2 L2 actions: encap and decap. */
3361                         ;
3362                 else
3363                         return rte_flow_error_set(error,
3364                                 ENOTSUP,
3365                                 RTE_FLOW_ERROR_TYPE_ACTION,
3366                                 NULL, "unsupported too small "
3367                                 "raw decap and too small raw "
3368                                 "encap combination");
3369         }
3370         if (decap) {
3371                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3372                                                     item_flags, attr, error);
3373                 if (ret < 0)
3374                         return ret;
3375                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3376                 ++(*actions_n);
3377         }
3378         if (encap) {
3379                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3380                         return rte_flow_error_set(error, ENOTSUP,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "small raw encap size");
3384                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3385                         return rte_flow_error_set(error, EINVAL,
3386                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3387                                                   NULL,
3388                                                   "more than one encap action");
3389                 if (!attr->transfer && priv->representor)
3390                         return rte_flow_error_set
3391                                         (error, ENOTSUP,
3392                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3393                                          "encap action for VF representor "
3394                                          "not supported on NIC table");
3395                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3396                 ++(*actions_n);
3397         }
3398         return 0;
3399 }
3400
3401 /**
3402  * Match encap_decap resource.
3403  *
3404  * @param list
3405  *   Pointer to the hash list.
3406  * @param entry
3407  *   Pointer to exist resource entry object.
3408  * @param key
3409  *   Key of the new entry.
3410  * @param ctx_cb
3411  *   Pointer to new encap_decap resource.
3412  *
3413  * @return
3414  *   0 on matching, none-zero otherwise.
3415  */
3416 int
3417 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3418                              struct mlx5_hlist_entry *entry,
3419                              uint64_t key __rte_unused, void *cb_ctx)
3420 {
3421         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3422         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3423         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3424
3425         cache_resource = container_of(entry,
3426                                       struct mlx5_flow_dv_encap_decap_resource,
3427                                       entry);
3428         if (resource->reformat_type == cache_resource->reformat_type &&
3429             resource->ft_type == cache_resource->ft_type &&
3430             resource->flags == cache_resource->flags &&
3431             resource->size == cache_resource->size &&
3432             !memcmp((const void *)resource->buf,
3433                     (const void *)cache_resource->buf,
3434                     resource->size))
3435                 return 0;
3436         return -1;
3437 }
3438
3439 /**
3440  * Allocate encap_decap resource.
3441  *
3442  * @param list
3443  *   Pointer to the hash list.
3444  * @param entry
3445  *   Pointer to exist resource entry object.
3446  * @param ctx_cb
3447  *   Pointer to new encap_decap resource.
3448  *
3449  * @return
3450  *   0 on matching, none-zero otherwise.
3451  */
3452 struct mlx5_hlist_entry *
3453 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3454                               uint64_t key __rte_unused,
3455                               void *cb_ctx)
3456 {
3457         struct mlx5_dev_ctx_shared *sh = list->ctx;
3458         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3459         struct mlx5dv_dr_domain *domain;
3460         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3461         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3462         uint32_t idx;
3463         int ret;
3464
3465         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3466                 domain = sh->fdb_domain;
3467         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3468                 domain = sh->rx_domain;
3469         else
3470                 domain = sh->tx_domain;
3471         /* Register new encap/decap resource. */
3472         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3473                                        &idx);
3474         if (!cache_resource) {
3475                 rte_flow_error_set(ctx->error, ENOMEM,
3476                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3477                                    "cannot allocate resource memory");
3478                 return NULL;
3479         }
3480         *cache_resource = *resource;
3481         cache_resource->idx = idx;
3482         ret = mlx5_flow_os_create_flow_action_packet_reformat
3483                                         (sh->ctx, domain, cache_resource,
3484                                          &cache_resource->action);
3485         if (ret) {
3486                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3487                 rte_flow_error_set(ctx->error, ENOMEM,
3488                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3489                                    NULL, "cannot create action");
3490                 return NULL;
3491         }
3492
3493         return &cache_resource->entry;
3494 }
3495
3496 /**
3497  * Find existing encap/decap resource or create and register a new one.
3498  *
3499  * @param[in, out] dev
3500  *   Pointer to rte_eth_dev structure.
3501  * @param[in, out] resource
3502  *   Pointer to encap/decap resource.
3503  * @parm[in, out] dev_flow
3504  *   Pointer to the dev_flow.
3505  * @param[out] error
3506  *   pointer to error structure.
3507  *
3508  * @return
3509  *   0 on success otherwise -errno and errno is set.
3510  */
3511 static int
3512 flow_dv_encap_decap_resource_register
3513                         (struct rte_eth_dev *dev,
3514                          struct mlx5_flow_dv_encap_decap_resource *resource,
3515                          struct mlx5_flow *dev_flow,
3516                          struct rte_flow_error *error)
3517 {
3518         struct mlx5_priv *priv = dev->data->dev_private;
3519         struct mlx5_dev_ctx_shared *sh = priv->sh;
3520         struct mlx5_hlist_entry *entry;
3521         union {
3522                 struct {
3523                         uint32_t ft_type:8;
3524                         uint32_t refmt_type:8;
3525                         /*
3526                          * Header reformat actions can be shared between
3527                          * non-root tables. One bit to indicate non-root
3528                          * table or not.
3529                          */
3530                         uint32_t is_root:1;
3531                         uint32_t reserve:15;
3532                 };
3533                 uint32_t v32;
3534         } encap_decap_key = {
3535                 {
3536                         .ft_type = resource->ft_type,
3537                         .refmt_type = resource->reformat_type,
3538                         .is_root = !!dev_flow->dv.group,
3539                         .reserve = 0,
3540                 }
3541         };
3542         struct mlx5_flow_cb_ctx ctx = {
3543                 .error = error,
3544                 .data = resource,
3545         };
3546         uint64_t key64;
3547
3548         resource->flags = dev_flow->dv.group ? 0 : 1;
3549         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3550                                  sizeof(encap_decap_key.v32), 0);
3551         if (resource->reformat_type !=
3552             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3553             resource->size)
3554                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3555         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3556         if (!entry)
3557                 return -rte_errno;
3558         resource = container_of(entry, typeof(*resource), entry);
3559         dev_flow->dv.encap_decap = resource;
3560         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3561         return 0;
3562 }
3563
3564 /**
3565  * Find existing table jump resource or create and register a new one.
3566  *
3567  * @param[in, out] dev
3568  *   Pointer to rte_eth_dev structure.
3569  * @param[in, out] tbl
3570  *   Pointer to flow table resource.
3571  * @parm[in, out] dev_flow
3572  *   Pointer to the dev_flow.
3573  * @param[out] error
3574  *   pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success otherwise -errno and errno is set.
3578  */
3579 static int
3580 flow_dv_jump_tbl_resource_register
3581                         (struct rte_eth_dev *dev __rte_unused,
3582                          struct mlx5_flow_tbl_resource *tbl,
3583                          struct mlx5_flow *dev_flow,
3584                          struct rte_flow_error *error __rte_unused)
3585 {
3586         struct mlx5_flow_tbl_data_entry *tbl_data =
3587                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3588
3589         MLX5_ASSERT(tbl);
3590         MLX5_ASSERT(tbl_data->jump.action);
3591         dev_flow->handle->rix_jump = tbl_data->idx;
3592         dev_flow->dv.jump = &tbl_data->jump;
3593         return 0;
3594 }
3595
3596 int
3597 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3598                          struct mlx5_cache_entry *entry, void *cb_ctx)
3599 {
3600         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3601         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3602         struct mlx5_flow_dv_port_id_action_resource *res =
3603                         container_of(entry, typeof(*res), entry);
3604
3605         return ref->port_id != res->port_id;
3606 }
3607
3608 struct mlx5_cache_entry *
3609 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3610                           struct mlx5_cache_entry *entry __rte_unused,
3611                           void *cb_ctx)
3612 {
3613         struct mlx5_dev_ctx_shared *sh = list->ctx;
3614         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3615         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3616         struct mlx5_flow_dv_port_id_action_resource *cache;
3617         uint32_t idx;
3618         int ret;
3619
3620         /* Register new port id action resource. */
3621         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3622         if (!cache) {
3623                 rte_flow_error_set(ctx->error, ENOMEM,
3624                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3625                                    "cannot allocate port_id action cache memory");
3626                 return NULL;
3627         }
3628         *cache = *ref;
3629         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3630                                                         ref->port_id,
3631                                                         &cache->action);
3632         if (ret) {
3633                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3634                 rte_flow_error_set(ctx->error, ENOMEM,
3635                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3636                                    "cannot create action");
3637                 return NULL;
3638         }
3639         cache->idx = idx;
3640         return &cache->entry;
3641 }
3642
3643 /**
3644  * Find existing table port ID resource or create and register a new one.
3645  *
3646  * @param[in, out] dev
3647  *   Pointer to rte_eth_dev structure.
3648  * @param[in, out] resource
3649  *   Pointer to port ID action resource.
3650  * @parm[in, out] dev_flow
3651  *   Pointer to the dev_flow.
3652  * @param[out] error
3653  *   pointer to error structure.
3654  *
3655  * @return
3656  *   0 on success otherwise -errno and errno is set.
3657  */
3658 static int
3659 flow_dv_port_id_action_resource_register
3660                         (struct rte_eth_dev *dev,
3661                          struct mlx5_flow_dv_port_id_action_resource *resource,
3662                          struct mlx5_flow *dev_flow,
3663                          struct rte_flow_error *error)
3664 {
3665         struct mlx5_priv *priv = dev->data->dev_private;
3666         struct mlx5_cache_entry *entry;
3667         struct mlx5_flow_dv_port_id_action_resource *cache;
3668         struct mlx5_flow_cb_ctx ctx = {
3669                 .error = error,
3670                 .data = resource,
3671         };
3672
3673         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3674         if (!entry)
3675                 return -rte_errno;
3676         cache = container_of(entry, typeof(*cache), entry);
3677         dev_flow->dv.port_id_action = cache;
3678         dev_flow->handle->rix_port_id_action = cache->idx;
3679         return 0;
3680 }
3681
3682 int
3683 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3684                          struct mlx5_cache_entry *entry, void *cb_ctx)
3685 {
3686         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3687         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3688         struct mlx5_flow_dv_push_vlan_action_resource *res =
3689                         container_of(entry, typeof(*res), entry);
3690
3691         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3692 }
3693
3694 struct mlx5_cache_entry *
3695 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3696                           struct mlx5_cache_entry *entry __rte_unused,
3697                           void *cb_ctx)
3698 {
3699         struct mlx5_dev_ctx_shared *sh = list->ctx;
3700         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3701         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3702         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3703         struct mlx5dv_dr_domain *domain;
3704         uint32_t idx;
3705         int ret;
3706
3707         /* Register new port id action resource. */
3708         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3709         if (!cache) {
3710                 rte_flow_error_set(ctx->error, ENOMEM,
3711                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3712                                    "cannot allocate push_vlan action cache memory");
3713                 return NULL;
3714         }
3715         *cache = *ref;
3716         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3717                 domain = sh->fdb_domain;
3718         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3719                 domain = sh->rx_domain;
3720         else
3721                 domain = sh->tx_domain;
3722         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3723                                                         &cache->action);
3724         if (ret) {
3725                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3726                 rte_flow_error_set(ctx->error, ENOMEM,
3727                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3728                                    "cannot create push vlan action");
3729                 return NULL;
3730         }
3731         cache->idx = idx;
3732         return &cache->entry;
3733 }
3734
3735 /**
3736  * Find existing push vlan resource or create and register a new one.
3737  *
3738  * @param [in, out] dev
3739  *   Pointer to rte_eth_dev structure.
3740  * @param[in, out] resource
3741  *   Pointer to port ID action resource.
3742  * @parm[in, out] dev_flow
3743  *   Pointer to the dev_flow.
3744  * @param[out] error
3745  *   pointer to error structure.
3746  *
3747  * @return
3748  *   0 on success otherwise -errno and errno is set.
3749  */
3750 static int
3751 flow_dv_push_vlan_action_resource_register
3752                        (struct rte_eth_dev *dev,
3753                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3754                         struct mlx5_flow *dev_flow,
3755                         struct rte_flow_error *error)
3756 {
3757         struct mlx5_priv *priv = dev->data->dev_private;
3758         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3759         struct mlx5_cache_entry *entry;
3760         struct mlx5_flow_cb_ctx ctx = {
3761                 .error = error,
3762                 .data = resource,
3763         };
3764
3765         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3766         if (!entry)
3767                 return -rte_errno;
3768         cache = container_of(entry, typeof(*cache), entry);
3769
3770         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3771         dev_flow->dv.push_vlan_res = cache;
3772         return 0;
3773 }
3774
3775 /**
3776  * Get the size of specific rte_flow_item_type hdr size
3777  *
3778  * @param[in] item_type
3779  *   Tested rte_flow_item_type.
3780  *
3781  * @return
3782  *   sizeof struct item_type, 0 if void or irrelevant.
3783  */
3784 static size_t
3785 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3786 {
3787         size_t retval;
3788
3789         switch (item_type) {
3790         case RTE_FLOW_ITEM_TYPE_ETH:
3791                 retval = sizeof(struct rte_ether_hdr);
3792                 break;
3793         case RTE_FLOW_ITEM_TYPE_VLAN:
3794                 retval = sizeof(struct rte_vlan_hdr);
3795                 break;
3796         case RTE_FLOW_ITEM_TYPE_IPV4:
3797                 retval = sizeof(struct rte_ipv4_hdr);
3798                 break;
3799         case RTE_FLOW_ITEM_TYPE_IPV6:
3800                 retval = sizeof(struct rte_ipv6_hdr);
3801                 break;
3802         case RTE_FLOW_ITEM_TYPE_UDP:
3803                 retval = sizeof(struct rte_udp_hdr);
3804                 break;
3805         case RTE_FLOW_ITEM_TYPE_TCP:
3806                 retval = sizeof(struct rte_tcp_hdr);
3807                 break;
3808         case RTE_FLOW_ITEM_TYPE_VXLAN:
3809         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3810                 retval = sizeof(struct rte_vxlan_hdr);
3811                 break;
3812         case RTE_FLOW_ITEM_TYPE_GRE:
3813         case RTE_FLOW_ITEM_TYPE_NVGRE:
3814                 retval = sizeof(struct rte_gre_hdr);
3815                 break;
3816         case RTE_FLOW_ITEM_TYPE_MPLS:
3817                 retval = sizeof(struct rte_mpls_hdr);
3818                 break;
3819         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3820         default:
3821                 retval = 0;
3822                 break;
3823         }
3824         return retval;
3825 }
3826
3827 #define MLX5_ENCAP_IPV4_VERSION         0x40
3828 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3829 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3830 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3831 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3832 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3833 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3834
3835 /**
3836  * Convert the encap action data from list of rte_flow_item to raw buffer
3837  *
3838  * @param[in] items
3839  *   Pointer to rte_flow_item objects list.
3840  * @param[out] buf
3841  *   Pointer to the output buffer.
3842  * @param[out] size
3843  *   Pointer to the output buffer size.
3844  * @param[out] error
3845  *   Pointer to the error structure.
3846  *
3847  * @return
3848  *   0 on success, a negative errno value otherwise and rte_errno is set.
3849  */
3850 static int
3851 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3852                            size_t *size, struct rte_flow_error *error)
3853 {
3854         struct rte_ether_hdr *eth = NULL;
3855         struct rte_vlan_hdr *vlan = NULL;
3856         struct rte_ipv4_hdr *ipv4 = NULL;
3857         struct rte_ipv6_hdr *ipv6 = NULL;
3858         struct rte_udp_hdr *udp = NULL;
3859         struct rte_vxlan_hdr *vxlan = NULL;
3860         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3861         struct rte_gre_hdr *gre = NULL;
3862         size_t len;
3863         size_t temp_size = 0;
3864
3865         if (!items)
3866                 return rte_flow_error_set(error, EINVAL,
3867                                           RTE_FLOW_ERROR_TYPE_ACTION,
3868                                           NULL, "invalid empty data");
3869         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3870                 len = flow_dv_get_item_hdr_len(items->type);
3871                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3872                         return rte_flow_error_set(error, EINVAL,
3873                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                   (void *)items->type,
3875                                                   "items total size is too big"
3876                                                   " for encap action");
3877                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3878                 switch (items->type) {
3879                 case RTE_FLOW_ITEM_TYPE_ETH:
3880                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3881                         break;
3882                 case RTE_FLOW_ITEM_TYPE_VLAN:
3883                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3884                         if (!eth)
3885                                 return rte_flow_error_set(error, EINVAL,
3886                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3887                                                 (void *)items->type,
3888                                                 "eth header not found");
3889                         if (!eth->ether_type)
3890                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3891                         break;
3892                 case RTE_FLOW_ITEM_TYPE_IPV4:
3893                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3894                         if (!vlan && !eth)
3895                                 return rte_flow_error_set(error, EINVAL,
3896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3897                                                 (void *)items->type,
3898                                                 "neither eth nor vlan"
3899                                                 " header found");
3900                         if (vlan && !vlan->eth_proto)
3901                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902                         else if (eth && !eth->ether_type)
3903                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3904                         if (!ipv4->version_ihl)
3905                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3906                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3907                         if (!ipv4->time_to_live)
3908                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3909                         break;
3910                 case RTE_FLOW_ITEM_TYPE_IPV6:
3911                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3912                         if (!vlan && !eth)
3913                                 return rte_flow_error_set(error, EINVAL,
3914                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3915                                                 (void *)items->type,
3916                                                 "neither eth nor vlan"
3917                                                 " header found");
3918                         if (vlan && !vlan->eth_proto)
3919                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920                         else if (eth && !eth->ether_type)
3921                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3922                         if (!ipv6->vtc_flow)
3923                                 ipv6->vtc_flow =
3924                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3925                         if (!ipv6->hop_limits)
3926                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3927                         break;
3928                 case RTE_FLOW_ITEM_TYPE_UDP:
3929                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3930                         if (!ipv4 && !ipv6)
3931                                 return rte_flow_error_set(error, EINVAL,
3932                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                 (void *)items->type,
3934                                                 "ip header not found");
3935                         if (ipv4 && !ipv4->next_proto_id)
3936                                 ipv4->next_proto_id = IPPROTO_UDP;
3937                         else if (ipv6 && !ipv6->proto)
3938                                 ipv6->proto = IPPROTO_UDP;
3939                         break;
3940                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3941                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3942                         if (!udp)
3943                                 return rte_flow_error_set(error, EINVAL,
3944                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3945                                                 (void *)items->type,
3946                                                 "udp header not found");
3947                         if (!udp->dst_port)
3948                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3949                         if (!vxlan->vx_flags)
3950                                 vxlan->vx_flags =
3951                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3952                         break;
3953                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3954                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3955                         if (!udp)
3956                                 return rte_flow_error_set(error, EINVAL,
3957                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3958                                                 (void *)items->type,
3959                                                 "udp header not found");
3960                         if (!vxlan_gpe->proto)
3961                                 return rte_flow_error_set(error, EINVAL,
3962                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3963                                                 (void *)items->type,
3964                                                 "next protocol not found");
3965                         if (!udp->dst_port)
3966                                 udp->dst_port =
3967                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3968                         if (!vxlan_gpe->vx_flags)
3969                                 vxlan_gpe->vx_flags =
3970                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3971                         break;
3972                 case RTE_FLOW_ITEM_TYPE_GRE:
3973                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3974                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3975                         if (!gre->proto)
3976                                 return rte_flow_error_set(error, EINVAL,
3977                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3978                                                 (void *)items->type,
3979                                                 "next protocol not found");
3980                         if (!ipv4 && !ipv6)
3981                                 return rte_flow_error_set(error, EINVAL,
3982                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3983                                                 (void *)items->type,
3984                                                 "ip header not found");
3985                         if (ipv4 && !ipv4->next_proto_id)
3986                                 ipv4->next_proto_id = IPPROTO_GRE;
3987                         else if (ipv6 && !ipv6->proto)
3988                                 ipv6->proto = IPPROTO_GRE;
3989                         break;
3990                 case RTE_FLOW_ITEM_TYPE_VOID:
3991                         break;
3992                 default:
3993                         return rte_flow_error_set(error, EINVAL,
3994                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3995                                                   (void *)items->type,
3996                                                   "unsupported item type");
3997                         break;
3998                 }
3999                 temp_size += len;
4000         }
4001         *size = temp_size;
4002         return 0;
4003 }
4004
4005 static int
4006 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4007 {
4008         struct rte_ether_hdr *eth = NULL;
4009         struct rte_vlan_hdr *vlan = NULL;
4010         struct rte_ipv6_hdr *ipv6 = NULL;
4011         struct rte_udp_hdr *udp = NULL;
4012         char *next_hdr;
4013         uint16_t proto;
4014
4015         eth = (struct rte_ether_hdr *)data;
4016         next_hdr = (char *)(eth + 1);
4017         proto = RTE_BE16(eth->ether_type);
4018
4019         /* VLAN skipping */
4020         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4021                 vlan = (struct rte_vlan_hdr *)next_hdr;
4022                 proto = RTE_BE16(vlan->eth_proto);
4023                 next_hdr += sizeof(struct rte_vlan_hdr);
4024         }
4025
4026         /* HW calculates IPv4 csum. no need to proceed */
4027         if (proto == RTE_ETHER_TYPE_IPV4)
4028                 return 0;
4029
4030         /* non IPv4/IPv6 header. not supported */
4031         if (proto != RTE_ETHER_TYPE_IPV6) {
4032                 return rte_flow_error_set(error, ENOTSUP,
4033                                           RTE_FLOW_ERROR_TYPE_ACTION,
4034                                           NULL, "Cannot offload non IPv4/IPv6");
4035         }
4036
4037         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4038
4039         /* ignore non UDP */
4040         if (ipv6->proto != IPPROTO_UDP)
4041                 return 0;
4042
4043         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4044         udp->dgram_cksum = 0;
4045
4046         return 0;
4047 }
4048
4049 /**
4050  * Convert L2 encap action to DV specification.
4051  *
4052  * @param[in] dev
4053  *   Pointer to rte_eth_dev structure.
4054  * @param[in] action
4055  *   Pointer to action structure.
4056  * @param[in, out] dev_flow
4057  *   Pointer to the mlx5_flow.
4058  * @param[in] transfer
4059  *   Mark if the flow is E-Switch flow.
4060  * @param[out] error
4061  *   Pointer to the error structure.
4062  *
4063  * @return
4064  *   0 on success, a negative errno value otherwise and rte_errno is set.
4065  */
4066 static int
4067 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4068                                const struct rte_flow_action *action,
4069                                struct mlx5_flow *dev_flow,
4070                                uint8_t transfer,
4071                                struct rte_flow_error *error)
4072 {
4073         const struct rte_flow_item *encap_data;
4074         const struct rte_flow_action_raw_encap *raw_encap_data;
4075         struct mlx5_flow_dv_encap_decap_resource res = {
4076                 .reformat_type =
4077                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4078                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4079                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4080         };
4081
4082         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4083                 raw_encap_data =
4084                         (const struct rte_flow_action_raw_encap *)action->conf;
4085                 res.size = raw_encap_data->size;
4086                 memcpy(res.buf, raw_encap_data->data, res.size);
4087         } else {
4088                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4089                         encap_data =
4090                                 ((const struct rte_flow_action_vxlan_encap *)
4091                                                 action->conf)->definition;
4092                 else
4093                         encap_data =
4094                                 ((const struct rte_flow_action_nvgre_encap *)
4095                                                 action->conf)->definition;
4096                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4097                                                &res.size, error))
4098                         return -rte_errno;
4099         }
4100         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4101                 return -rte_errno;
4102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4103                 return rte_flow_error_set(error, EINVAL,
4104                                           RTE_FLOW_ERROR_TYPE_ACTION,
4105                                           NULL, "can't create L2 encap action");
4106         return 0;
4107 }
4108
4109 /**
4110  * Convert L2 decap action to DV specification.
4111  *
4112  * @param[in] dev
4113  *   Pointer to rte_eth_dev structure.
4114  * @param[in, out] dev_flow
4115  *   Pointer to the mlx5_flow.
4116  * @param[in] transfer
4117  *   Mark if the flow is E-Switch flow.
4118  * @param[out] error
4119  *   Pointer to the error structure.
4120  *
4121  * @return
4122  *   0 on success, a negative errno value otherwise and rte_errno is set.
4123  */
4124 static int
4125 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4126                                struct mlx5_flow *dev_flow,
4127                                uint8_t transfer,
4128                                struct rte_flow_error *error)
4129 {
4130         struct mlx5_flow_dv_encap_decap_resource res = {
4131                 .size = 0,
4132                 .reformat_type =
4133                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4134                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4135                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4136         };
4137
4138         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4139                 return rte_flow_error_set(error, EINVAL,
4140                                           RTE_FLOW_ERROR_TYPE_ACTION,
4141                                           NULL, "can't create L2 decap action");
4142         return 0;
4143 }
4144
4145 /**
4146  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4147  *
4148  * @param[in] dev
4149  *   Pointer to rte_eth_dev structure.
4150  * @param[in] action
4151  *   Pointer to action structure.
4152  * @param[in, out] dev_flow
4153  *   Pointer to the mlx5_flow.
4154  * @param[in] attr
4155  *   Pointer to the flow attributes.
4156  * @param[out] error
4157  *   Pointer to the error structure.
4158  *
4159  * @return
4160  *   0 on success, a negative errno value otherwise and rte_errno is set.
4161  */
4162 static int
4163 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4164                                 const struct rte_flow_action *action,
4165                                 struct mlx5_flow *dev_flow,
4166                                 const struct rte_flow_attr *attr,
4167                                 struct rte_flow_error *error)
4168 {
4169         const struct rte_flow_action_raw_encap *encap_data;
4170         struct mlx5_flow_dv_encap_decap_resource res;
4171
4172         memset(&res, 0, sizeof(res));
4173         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4174         res.size = encap_data->size;
4175         memcpy(res.buf, encap_data->data, res.size);
4176         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4177                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4178                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4179         if (attr->transfer)
4180                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4181         else
4182                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4183                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4184         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4185                 return rte_flow_error_set(error, EINVAL,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION,
4187                                           NULL, "can't create encap action");
4188         return 0;
4189 }
4190
4191 /**
4192  * Create action push VLAN.
4193  *
4194  * @param[in] dev
4195  *   Pointer to rte_eth_dev structure.
4196  * @param[in] attr
4197  *   Pointer to the flow attributes.
4198  * @param[in] vlan
4199  *   Pointer to the vlan to push to the Ethernet header.
4200  * @param[in, out] dev_flow
4201  *   Pointer to the mlx5_flow.
4202  * @param[out] error
4203  *   Pointer to the error structure.
4204  *
4205  * @return
4206  *   0 on success, a negative errno value otherwise and rte_errno is set.
4207  */
4208 static int
4209 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4210                                 const struct rte_flow_attr *attr,
4211                                 const struct rte_vlan_hdr *vlan,
4212                                 struct mlx5_flow *dev_flow,
4213                                 struct rte_flow_error *error)
4214 {
4215         struct mlx5_flow_dv_push_vlan_action_resource res;
4216
4217         memset(&res, 0, sizeof(res));
4218         res.vlan_tag =
4219                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4220                                  vlan->vlan_tci);
4221         if (attr->transfer)
4222                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4223         else
4224                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4225                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4226         return flow_dv_push_vlan_action_resource_register
4227                                             (dev, &res, dev_flow, error);
4228 }
4229
4230 /**
4231  * Validate the modify-header actions.
4232  *
4233  * @param[in] action_flags
4234  *   Holds the actions detected until now.
4235  * @param[in] action
4236  *   Pointer to the modify action.
4237  * @param[out] error
4238  *   Pointer to error structure.
4239  *
4240  * @return
4241  *   0 on success, a negative errno value otherwise and rte_errno is set.
4242  */
4243 static int
4244 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4245                                    const struct rte_flow_action *action,
4246                                    struct rte_flow_error *error)
4247 {
4248         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4249                 return rte_flow_error_set(error, EINVAL,
4250                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4251                                           NULL, "action configuration not set");
4252         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4253                 return rte_flow_error_set(error, EINVAL,
4254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4255                                           "can't have encap action before"
4256                                           " modify action");
4257         return 0;
4258 }
4259
4260 /**
4261  * Validate the modify-header MAC address actions.
4262  *
4263  * @param[in] action_flags
4264  *   Holds the actions detected until now.
4265  * @param[in] action
4266  *   Pointer to the modify action.
4267  * @param[in] item_flags
4268  *   Holds the items detected.
4269  * @param[out] error
4270  *   Pointer to error structure.
4271  *
4272  * @return
4273  *   0 on success, a negative errno value otherwise and rte_errno is set.
4274  */
4275 static int
4276 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4277                                    const struct rte_flow_action *action,
4278                                    const uint64_t item_flags,
4279                                    struct rte_flow_error *error)
4280 {
4281         int ret = 0;
4282
4283         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4284         if (!ret) {
4285                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4286                         return rte_flow_error_set(error, EINVAL,
4287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4288                                                   NULL,
4289                                                   "no L2 item in pattern");
4290         }
4291         return ret;
4292 }
4293
4294 /**
4295  * Validate the modify-header IPv4 address actions.
4296  *
4297  * @param[in] action_flags
4298  *   Holds the actions detected until now.
4299  * @param[in] action
4300  *   Pointer to the modify action.
4301  * @param[in] item_flags
4302  *   Holds the items detected.
4303  * @param[out] error
4304  *   Pointer to error structure.
4305  *
4306  * @return
4307  *   0 on success, a negative errno value otherwise and rte_errno is set.
4308  */
4309 static int
4310 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4311                                     const struct rte_flow_action *action,
4312                                     const uint64_t item_flags,
4313                                     struct rte_flow_error *error)
4314 {
4315         int ret = 0;
4316         uint64_t layer;
4317
4318         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4319         if (!ret) {
4320                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4321                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4322                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4323                 if (!(item_flags & layer))
4324                         return rte_flow_error_set(error, EINVAL,
4325                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4326                                                   NULL,
4327                                                   "no ipv4 item in pattern");
4328         }
4329         return ret;
4330 }
4331
4332 /**
4333  * Validate the modify-header IPv6 address actions.
4334  *
4335  * @param[in] action_flags
4336  *   Holds the actions detected until now.
4337  * @param[in] action
4338  *   Pointer to the modify action.
4339  * @param[in] item_flags
4340  *   Holds the items detected.
4341  * @param[out] error
4342  *   Pointer to error structure.
4343  *
4344  * @return
4345  *   0 on success, a negative errno value otherwise and rte_errno is set.
4346  */
4347 static int
4348 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4349                                     const struct rte_flow_action *action,
4350                                     const uint64_t item_flags,
4351                                     struct rte_flow_error *error)
4352 {
4353         int ret = 0;
4354         uint64_t layer;
4355
4356         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4357         if (!ret) {
4358                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4359                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4360                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4361                 if (!(item_flags & layer))
4362                         return rte_flow_error_set(error, EINVAL,
4363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4364                                                   NULL,
4365                                                   "no ipv6 item in pattern");
4366         }
4367         return ret;
4368 }
4369
4370 /**
4371  * Validate the modify-header TP actions.
4372  *
4373  * @param[in] action_flags
4374  *   Holds the actions detected until now.
4375  * @param[in] action
4376  *   Pointer to the modify action.
4377  * @param[in] item_flags
4378  *   Holds the items detected.
4379  * @param[out] error
4380  *   Pointer to error structure.
4381  *
4382  * @return
4383  *   0 on success, a negative errno value otherwise and rte_errno is set.
4384  */
4385 static int
4386 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4387                                   const struct rte_flow_action *action,
4388                                   const uint64_t item_flags,
4389                                   struct rte_flow_error *error)
4390 {
4391         int ret = 0;
4392         uint64_t layer;
4393
4394         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4395         if (!ret) {
4396                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4397                                  MLX5_FLOW_LAYER_INNER_L4 :
4398                                  MLX5_FLOW_LAYER_OUTER_L4;
4399                 if (!(item_flags & layer))
4400                         return rte_flow_error_set(error, EINVAL,
4401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4402                                                   NULL, "no transport layer "
4403                                                   "in pattern");
4404         }
4405         return ret;
4406 }
4407
4408 /**
4409  * Validate the modify-header actions of increment/decrement
4410  * TCP Sequence-number.
4411  *
4412  * @param[in] action_flags
4413  *   Holds the actions detected until now.
4414  * @param[in] action
4415  *   Pointer to the modify action.
4416  * @param[in] item_flags
4417  *   Holds the items detected.
4418  * @param[out] error
4419  *   Pointer to error structure.
4420  *
4421  * @return
4422  *   0 on success, a negative errno value otherwise and rte_errno is set.
4423  */
4424 static int
4425 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4426                                        const struct rte_flow_action *action,
4427                                        const uint64_t item_flags,
4428                                        struct rte_flow_error *error)
4429 {
4430         int ret = 0;
4431         uint64_t layer;
4432
4433         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4434         if (!ret) {
4435                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4436                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4437                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4438                 if (!(item_flags & layer))
4439                         return rte_flow_error_set(error, EINVAL,
4440                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4441                                                   NULL, "no TCP item in"
4442                                                   " pattern");
4443                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4444                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4445                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4446                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4447                         return rte_flow_error_set(error, EINVAL,
4448                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4449                                                   NULL,
4450                                                   "cannot decrease and increase"
4451                                                   " TCP sequence number"
4452                                                   " at the same time");
4453         }
4454         return ret;
4455 }
4456
4457 /**
4458  * Validate the modify-header actions of increment/decrement
4459  * TCP Acknowledgment number.
4460  *
4461  * @param[in] action_flags
4462  *   Holds the actions detected until now.
4463  * @param[in] action
4464  *   Pointer to the modify action.
4465  * @param[in] item_flags
4466  *   Holds the items detected.
4467  * @param[out] error
4468  *   Pointer to error structure.
4469  *
4470  * @return
4471  *   0 on success, a negative errno value otherwise and rte_errno is set.
4472  */
4473 static int
4474 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4475                                        const struct rte_flow_action *action,
4476                                        const uint64_t item_flags,
4477                                        struct rte_flow_error *error)
4478 {
4479         int ret = 0;
4480         uint64_t layer;
4481
4482         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4483         if (!ret) {
4484                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4485                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4486                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4487                 if (!(item_flags & layer))
4488                         return rte_flow_error_set(error, EINVAL,
4489                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4490                                                   NULL, "no TCP item in"
4491                                                   " pattern");
4492                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4493                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4494                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4495                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4496                         return rte_flow_error_set(error, EINVAL,
4497                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4498                                                   NULL,
4499                                                   "cannot decrease and increase"
4500                                                   " TCP acknowledgment number"
4501                                                   " at the same time");
4502         }
4503         return ret;
4504 }
4505
4506 /**
4507  * Validate the modify-header TTL actions.
4508  *
4509  * @param[in] action_flags
4510  *   Holds the actions detected until now.
4511  * @param[in] action
4512  *   Pointer to the modify action.
4513  * @param[in] item_flags
4514  *   Holds the items detected.
4515  * @param[out] error
4516  *   Pointer to error structure.
4517  *
4518  * @return
4519  *   0 on success, a negative errno value otherwise and rte_errno is set.
4520  */
4521 static int
4522 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4523                                    const struct rte_flow_action *action,
4524                                    const uint64_t item_flags,
4525                                    struct rte_flow_error *error)
4526 {
4527         int ret = 0;
4528         uint64_t layer;
4529
4530         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4531         if (!ret) {
4532                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4533                                  MLX5_FLOW_LAYER_INNER_L3 :
4534                                  MLX5_FLOW_LAYER_OUTER_L3;
4535                 if (!(item_flags & layer))
4536                         return rte_flow_error_set(error, EINVAL,
4537                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4538                                                   NULL,
4539                                                   "no IP protocol in pattern");
4540         }
4541         return ret;
4542 }
4543
4544 /**
4545  * Validate the generic modify field actions.
4546  * @param[in] dev
4547  *   Pointer to the rte_eth_dev structure.
4548  * @param[in] action_flags
4549  *   Holds the actions detected until now.
4550  * @param[in] action
4551  *   Pointer to the modify action.
4552  * @param[in] attr
4553  *   Pointer to the flow attributes.
4554  * @param[out] error
4555  *   Pointer to error structure.
4556  *
4557  * @return
4558  *   Number of header fields to modify (0 or more) on success,
4559  *   a negative errno value otherwise and rte_errno is set.
4560  */
4561 static int
4562 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4563                                    const uint64_t action_flags,
4564                                    const struct rte_flow_action *action,
4565                                    const struct rte_flow_attr *attr,
4566                                    struct rte_flow_error *error)
4567 {
4568         int ret = 0;
4569         struct mlx5_priv *priv = dev->data->dev_private;
4570         struct mlx5_dev_config *config = &priv->config;
4571         const struct rte_flow_action_modify_field *action_modify_field =
4572                 action->conf;
4573         uint32_t dst_width =
4574                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4575         uint32_t src_width =
4576                 mlx5_flow_item_field_width(action_modify_field->src.field);
4577
4578         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4579         if (ret)
4580                 return ret;
4581
4582         if (action_modify_field->width == 0)
4583                 return rte_flow_error_set(error, EINVAL,
4584                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4585                                 "no bits are requested to be modified");
4586         else if (action_modify_field->width > dst_width ||
4587                  action_modify_field->width > src_width)
4588                 return rte_flow_error_set(error, EINVAL,
4589                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4590                                 "cannot modify more bits than"
4591                                 " the width of a field");
4592         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594                 if ((action_modify_field->dst.offset +
4595                      action_modify_field->width > dst_width) ||
4596                     (action_modify_field->dst.offset % 32))
4597                         return rte_flow_error_set(error, EINVAL,
4598                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4599                                         "destination offset is too big"
4600                                         " or not aligned to 4 bytes");
4601                 if (action_modify_field->dst.level &&
4602                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4603                         return rte_flow_error_set(error, ENOTSUP,
4604                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4605                                         "inner header fields modification"
4606                                         " is not supported");
4607         }
4608         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4609             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4610                 if (!attr->transfer && !attr->group)
4611                         return rte_flow_error_set(error, ENOTSUP,
4612                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4613                                         "modify field action is not"
4614                                         " supported for group 0");
4615                 if ((action_modify_field->src.offset +
4616                      action_modify_field->width > src_width) ||
4617                     (action_modify_field->src.offset % 32))
4618                         return rte_flow_error_set(error, EINVAL,
4619                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4620                                         "source offset is too big"
4621                                         " or not aligned to 4 bytes");
4622                 if (action_modify_field->src.level &&
4623                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4624                         return rte_flow_error_set(error, ENOTSUP,
4625                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4626                                         "inner header fields modification"
4627                                         " is not supported");
4628         }
4629         if (action_modify_field->dst.field ==
4630             action_modify_field->src.field)
4631                 return rte_flow_error_set(error, EINVAL,
4632                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633                                 "source and destination fields"
4634                                 " cannot be the same");
4635         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4636             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4637                 return rte_flow_error_set(error, EINVAL,
4638                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639                                 "immediate value or a pointer to it"
4640                                 " cannot be used as a destination");
4641         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4642             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4643                 return rte_flow_error_set(error, ENOTSUP,
4644                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645                                 "modifications of an arbitrary"
4646                                 " place in a packet is not supported");
4647         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4648             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4649                 return rte_flow_error_set(error, ENOTSUP,
4650                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651                                 "modifications of the 802.1Q Tag"
4652                                 " Identifier is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4655                 return rte_flow_error_set(error, ENOTSUP,
4656                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657                                 "modifications of the VXLAN Network"
4658                                 " Identifier is not supported");
4659         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4660             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4661                 return rte_flow_error_set(error, ENOTSUP,
4662                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4663                                 "modifications of the GENEVE Network"
4664                                 " Identifier is not supported");
4665         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4666             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4667             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4668             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4669                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4670                     !mlx5_flow_ext_mreg_supported(dev))
4671                         return rte_flow_error_set(error, ENOTSUP,
4672                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4673                                         "cannot modify mark or metadata without"
4674                                         " extended metadata register support");
4675         }
4676         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4677                 return rte_flow_error_set(error, ENOTSUP,
4678                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4679                                 "add and sub operations"
4680                                 " are not supported");
4681         return (action_modify_field->width / 32) +
4682                !!(action_modify_field->width % 32);
4683 }
4684
4685 /**
4686  * Validate jump action.
4687  *
4688  * @param[in] action
4689  *   Pointer to the jump action.
4690  * @param[in] action_flags
4691  *   Holds the actions detected until now.
4692  * @param[in] attributes
4693  *   Pointer to flow attributes
4694  * @param[in] external
4695  *   Action belongs to flow rule created by request external to PMD.
4696  * @param[out] error
4697  *   Pointer to error structure.
4698  *
4699  * @return
4700  *   0 on success, a negative errno value otherwise and rte_errno is set.
4701  */
4702 static int
4703 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4704                              const struct mlx5_flow_tunnel *tunnel,
4705                              const struct rte_flow_action *action,
4706                              uint64_t action_flags,
4707                              const struct rte_flow_attr *attributes,
4708                              bool external, struct rte_flow_error *error)
4709 {
4710         uint32_t target_group, table;
4711         int ret = 0;
4712         struct flow_grp_info grp_info = {
4713                 .external = !!external,
4714                 .transfer = !!attributes->transfer,
4715                 .fdb_def_rule = 1,
4716                 .std_tbl_fix = 0
4717         };
4718         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4719                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4720                 return rte_flow_error_set(error, EINVAL,
4721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4722                                           "can't have 2 fate actions in"
4723                                           " same flow");
4724         if (action_flags & MLX5_FLOW_ACTION_METER)
4725                 return rte_flow_error_set(error, ENOTSUP,
4726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4727                                           "jump with meter not support");
4728         if (!action->conf)
4729                 return rte_flow_error_set(error, EINVAL,
4730                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4731                                           NULL, "action configuration not set");
4732         target_group =
4733                 ((const struct rte_flow_action_jump *)action->conf)->group;
4734         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4735                                        &grp_info, error);
4736         if (ret)
4737                 return ret;
4738         if (attributes->group == target_group &&
4739             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4740                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4741                 return rte_flow_error_set(error, EINVAL,
4742                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4743                                           "target group must be other than"
4744                                           " the current flow group");
4745         return 0;
4746 }
4747
4748 /*
4749  * Validate the port_id action.
4750  *
4751  * @param[in] dev
4752  *   Pointer to rte_eth_dev structure.
4753  * @param[in] action_flags
4754  *   Bit-fields that holds the actions detected until now.
4755  * @param[in] action
4756  *   Port_id RTE action structure.
4757  * @param[in] attr
4758  *   Attributes of flow that includes this action.
4759  * @param[out] error
4760  *   Pointer to error structure.
4761  *
4762  * @return
4763  *   0 on success, a negative errno value otherwise and rte_errno is set.
4764  */
4765 static int
4766 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4767                                 uint64_t action_flags,
4768                                 const struct rte_flow_action *action,
4769                                 const struct rte_flow_attr *attr,
4770                                 struct rte_flow_error *error)
4771 {
4772         const struct rte_flow_action_port_id *port_id;
4773         struct mlx5_priv *act_priv;
4774         struct mlx5_priv *dev_priv;
4775         uint16_t port;
4776
4777         if (!attr->transfer)
4778                 return rte_flow_error_set(error, ENOTSUP,
4779                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4780                                           NULL,
4781                                           "port id action is valid in transfer"
4782                                           " mode only");
4783         if (!action || !action->conf)
4784                 return rte_flow_error_set(error, ENOTSUP,
4785                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4786                                           NULL,
4787                                           "port id action parameters must be"
4788                                           " specified");
4789         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4790                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4791                 return rte_flow_error_set(error, EINVAL,
4792                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4793                                           "can have only one fate actions in"
4794                                           " a flow");
4795         dev_priv = mlx5_dev_to_eswitch_info(dev);
4796         if (!dev_priv)
4797                 return rte_flow_error_set(error, rte_errno,
4798                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4799                                           NULL,
4800                                           "failed to obtain E-Switch info");
4801         port_id = action->conf;
4802         port = port_id->original ? dev->data->port_id : port_id->id;
4803         act_priv = mlx5_port_to_eswitch_info(port, false);
4804         if (!act_priv)
4805                 return rte_flow_error_set
4806                                 (error, rte_errno,
4807                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4808                                  "failed to obtain E-Switch port id for port");
4809         if (act_priv->domain_id != dev_priv->domain_id)
4810                 return rte_flow_error_set
4811                                 (error, EINVAL,
4812                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4813                                  "port does not belong to"
4814                                  " E-Switch being configured");
4815         return 0;
4816 }
4817
4818 /**
4819  * Get the maximum number of modify header actions.
4820  *
4821  * @param dev
4822  *   Pointer to rte_eth_dev structure.
4823  * @param flags
4824  *   Flags bits to check if root level.
4825  *
4826  * @return
4827  *   Max number of modify header actions device can support.
4828  */
4829 static inline unsigned int
4830 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4831                               uint64_t flags)
4832 {
4833         /*
4834          * There's no way to directly query the max capacity from FW.
4835          * The maximal value on root table should be assumed to be supported.
4836          */
4837         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4838                 return MLX5_MAX_MODIFY_NUM;
4839         else
4840                 return MLX5_ROOT_TBL_MODIFY_NUM;
4841 }
4842
4843 /**
4844  * Validate the meter action.
4845  *
4846  * @param[in] dev
4847  *   Pointer to rte_eth_dev structure.
4848  * @param[in] action_flags
4849  *   Bit-fields that holds the actions detected until now.
4850  * @param[in] action
4851  *   Pointer to the meter action.
4852  * @param[in] attr
4853  *   Attributes of flow that includes this action.
4854  * @param[out] error
4855  *   Pointer to error structure.
4856  *
4857  * @return
4858  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4859  */
4860 static int
4861 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4862                                 uint64_t action_flags,
4863                                 const struct rte_flow_action *action,
4864                                 const struct rte_flow_attr *attr,
4865                                 struct rte_flow_error *error)
4866 {
4867         struct mlx5_priv *priv = dev->data->dev_private;
4868         const struct rte_flow_action_meter *am = action->conf;
4869         struct mlx5_flow_meter_info *fm;
4870
4871         if (!am)
4872                 return rte_flow_error_set(error, EINVAL,
4873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874                                           "meter action conf is NULL");
4875
4876         if (action_flags & MLX5_FLOW_ACTION_METER)
4877                 return rte_flow_error_set(error, ENOTSUP,
4878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4879                                           "meter chaining not support");
4880         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4881                 return rte_flow_error_set(error, ENOTSUP,
4882                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4883                                           "meter with jump not support");
4884         if (!priv->mtr_en)
4885                 return rte_flow_error_set(error, ENOTSUP,
4886                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4887                                           NULL,
4888                                           "meter action not supported");
4889         fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4890         if (!fm)
4891                 return rte_flow_error_set(error, EINVAL,
4892                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4893                                           "Meter not found");
4894         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4895               (!fm->ingress && !attr->ingress && attr->egress) ||
4896               (!fm->egress && !attr->egress && attr->ingress))))
4897                 return rte_flow_error_set(error, EINVAL,
4898                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4899                                           "Flow attributes are either invalid "
4900                                           "or have a conflict with current "
4901                                           "meter attributes");
4902         return 0;
4903 }
4904
4905 /**
4906  * Validate the age action.
4907  *
4908  * @param[in] action_flags
4909  *   Holds the actions detected until now.
4910  * @param[in] action
4911  *   Pointer to the age action.
4912  * @param[in] dev
4913  *   Pointer to the Ethernet device structure.
4914  * @param[out] error
4915  *   Pointer to error structure.
4916  *
4917  * @return
4918  *   0 on success, a negative errno value otherwise and rte_errno is set.
4919  */
4920 static int
4921 flow_dv_validate_action_age(uint64_t action_flags,
4922                             const struct rte_flow_action *action,
4923                             struct rte_eth_dev *dev,
4924                             struct rte_flow_error *error)
4925 {
4926         struct mlx5_priv *priv = dev->data->dev_private;
4927         const struct rte_flow_action_age *age = action->conf;
4928
4929         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4930             !priv->sh->aso_age_mng))
4931                 return rte_flow_error_set(error, ENOTSUP,
4932                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4933                                           NULL,
4934                                           "age action not supported");
4935         if (!(action->conf))
4936                 return rte_flow_error_set(error, EINVAL,
4937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4938                                           "configuration cannot be null");
4939         if (!(age->timeout))
4940                 return rte_flow_error_set(error, EINVAL,
4941                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4942                                           "invalid timeout value 0");
4943         if (action_flags & MLX5_FLOW_ACTION_AGE)
4944                 return rte_flow_error_set(error, EINVAL,
4945                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4946                                           "duplicate age actions set");
4947         return 0;
4948 }
4949
4950 /**
4951  * Validate the modify-header IPv4 DSCP actions.
4952  *
4953  * @param[in] action_flags
4954  *   Holds the actions detected until now.
4955  * @param[in] action
4956  *   Pointer to the modify action.
4957  * @param[in] item_flags
4958  *   Holds the items detected.
4959  * @param[out] error
4960  *   Pointer to error structure.
4961  *
4962  * @return
4963  *   0 on success, a negative errno value otherwise and rte_errno is set.
4964  */
4965 static int
4966 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4967                                          const struct rte_flow_action *action,
4968                                          const uint64_t item_flags,
4969                                          struct rte_flow_error *error)
4970 {
4971         int ret = 0;
4972
4973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4974         if (!ret) {
4975                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4976                         return rte_flow_error_set(error, EINVAL,
4977                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4978                                                   NULL,
4979                                                   "no ipv4 item in pattern");
4980         }
4981         return ret;
4982 }
4983
4984 /**
4985  * Validate the modify-header IPv6 DSCP actions.
4986  *
4987  * @param[in] action_flags
4988  *   Holds the actions detected until now.
4989  * @param[in] action
4990  *   Pointer to the modify action.
4991  * @param[in] item_flags
4992  *   Holds the items detected.
4993  * @param[out] error
4994  *   Pointer to error structure.
4995  *
4996  * @return
4997  *   0 on success, a negative errno value otherwise and rte_errno is set.
4998  */
4999 static int
5000 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5001                                          const struct rte_flow_action *action,
5002                                          const uint64_t item_flags,
5003                                          struct rte_flow_error *error)
5004 {
5005         int ret = 0;
5006
5007         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5008         if (!ret) {
5009                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5010                         return rte_flow_error_set(error, EINVAL,
5011                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5012                                                   NULL,
5013                                                   "no ipv6 item in pattern");
5014         }
5015         return ret;
5016 }
5017
5018 /**
5019  * Match modify-header resource.
5020  *
5021  * @param list
5022  *   Pointer to the hash list.
5023  * @param entry
5024  *   Pointer to exist resource entry object.
5025  * @param key
5026  *   Key of the new entry.
5027  * @param ctx
5028  *   Pointer to new modify-header resource.
5029  *
5030  * @return
5031  *   0 on matching, non-zero otherwise.
5032  */
5033 int
5034 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5035                         struct mlx5_hlist_entry *entry,
5036                         uint64_t key __rte_unused, void *cb_ctx)
5037 {
5038         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5039         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5040         struct mlx5_flow_dv_modify_hdr_resource *resource =
5041                         container_of(entry, typeof(*resource), entry);
5042         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5043
5044         key_len += ref->actions_num * sizeof(ref->actions[0]);
5045         return ref->actions_num != resource->actions_num ||
5046                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5047 }
5048
5049 struct mlx5_hlist_entry *
5050 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5051                          void *cb_ctx)
5052 {
5053         struct mlx5_dev_ctx_shared *sh = list->ctx;
5054         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5055         struct mlx5dv_dr_domain *ns;
5056         struct mlx5_flow_dv_modify_hdr_resource *entry;
5057         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5058         int ret;
5059         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5060         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5061
5062         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5063                             SOCKET_ID_ANY);
5064         if (!entry) {
5065                 rte_flow_error_set(ctx->error, ENOMEM,
5066                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5067                                    "cannot allocate resource memory");
5068                 return NULL;
5069         }
5070         rte_memcpy(&entry->ft_type,
5071                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5072                    key_len + data_len);
5073         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5074                 ns = sh->fdb_domain;
5075         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5076                 ns = sh->tx_domain;
5077         else
5078                 ns = sh->rx_domain;
5079         ret = mlx5_flow_os_create_flow_action_modify_header
5080                                         (sh->ctx, ns, entry,
5081                                          data_len, &entry->action);
5082         if (ret) {
5083                 mlx5_free(entry);
5084                 rte_flow_error_set(ctx->error, ENOMEM,
5085                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5086                                    NULL, "cannot create modification action");
5087                 return NULL;
5088         }
5089         return &entry->entry;
5090 }
5091
5092 /**
5093  * Validate the sample action.
5094  *
5095  * @param[in, out] action_flags
5096  *   Holds the actions detected until now.
5097  * @param[in] action
5098  *   Pointer to the sample action.
5099  * @param[in] dev
5100  *   Pointer to the Ethernet device structure.
5101  * @param[in] attr
5102  *   Attributes of flow that includes this action.
5103  * @param[in] item_flags
5104  *   Holds the items detected.
5105  * @param[in] rss
5106  *   Pointer to the RSS action.
5107  * @param[out] sample_rss
5108  *   Pointer to the RSS action in sample action list.
5109  * @param[out] count
5110  *   Pointer to the COUNT action in sample action list.
5111  * @param[out] fdb_mirror_limit
5112  *   Pointer to the FDB mirror limitation flag.
5113  * @param[out] error
5114  *   Pointer to error structure.
5115  *
5116  * @return
5117  *   0 on success, a negative errno value otherwise and rte_errno is set.
5118  */
5119 static int
5120 flow_dv_validate_action_sample(uint64_t *action_flags,
5121                                const struct rte_flow_action *action,
5122                                struct rte_eth_dev *dev,
5123                                const struct rte_flow_attr *attr,
5124                                uint64_t item_flags,
5125                                const struct rte_flow_action_rss *rss,
5126                                const struct rte_flow_action_rss **sample_rss,
5127                                const struct rte_flow_action_count **count,
5128                                int *fdb_mirror_limit,
5129                                struct rte_flow_error *error)
5130 {
5131         struct mlx5_priv *priv = dev->data->dev_private;
5132         struct mlx5_dev_config *dev_conf = &priv->config;
5133         const struct rte_flow_action_sample *sample = action->conf;
5134         const struct rte_flow_action *act;
5135         uint64_t sub_action_flags = 0;
5136         uint16_t queue_index = 0xFFFF;
5137         int actions_n = 0;
5138         int ret;
5139
5140         if (!sample)
5141                 return rte_flow_error_set(error, EINVAL,
5142                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5143                                           "configuration cannot be NULL");
5144         if (sample->ratio == 0)
5145                 return rte_flow_error_set(error, EINVAL,
5146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5147                                           "ratio value starts from 1");
5148         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5149                 return rte_flow_error_set(error, ENOTSUP,
5150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5151                                           NULL,
5152                                           "sample action not supported");
5153         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5154                 return rte_flow_error_set(error, EINVAL,
5155                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5156                                           "Multiple sample actions not "
5157                                           "supported");
5158         if (*action_flags & MLX5_FLOW_ACTION_METER)
5159                 return rte_flow_error_set(error, EINVAL,
5160                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5161                                           "wrong action order, meter should "
5162                                           "be after sample action");
5163         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5164                 return rte_flow_error_set(error, EINVAL,
5165                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5166                                           "wrong action order, jump should "
5167                                           "be after sample action");
5168         act = sample->actions;
5169         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5170                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5171                         return rte_flow_error_set(error, ENOTSUP,
5172                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5173                                                   act, "too many actions");
5174                 switch (act->type) {
5175                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5176                         ret = mlx5_flow_validate_action_queue(act,
5177                                                               sub_action_flags,
5178                                                               dev,
5179                                                               attr, error);
5180                         if (ret < 0)
5181                                 return ret;
5182                         queue_index = ((const struct rte_flow_action_queue *)
5183                                                         (act->conf))->index;
5184                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5185                         ++actions_n;
5186                         break;
5187                 case RTE_FLOW_ACTION_TYPE_RSS:
5188                         *sample_rss = act->conf;
5189                         ret = mlx5_flow_validate_action_rss(act,
5190                                                             sub_action_flags,
5191                                                             dev, attr,
5192                                                             item_flags,
5193                                                             error);
5194                         if (ret < 0)
5195                                 return ret;
5196                         if (rss && *sample_rss &&
5197                             ((*sample_rss)->level != rss->level ||
5198                             (*sample_rss)->types != rss->types))
5199                                 return rte_flow_error_set(error, ENOTSUP,
5200                                         RTE_FLOW_ERROR_TYPE_ACTION,
5201                                         NULL,
5202                                         "Can't use the different RSS types "
5203                                         "or level in the same flow");
5204                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5205                                 queue_index = (*sample_rss)->queue[0];
5206                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5207                         ++actions_n;
5208                         break;
5209                 case RTE_FLOW_ACTION_TYPE_MARK:
5210                         ret = flow_dv_validate_action_mark(dev, act,
5211                                                            sub_action_flags,
5212                                                            attr, error);
5213                         if (ret < 0)
5214                                 return ret;
5215                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5216                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5217                                                 MLX5_FLOW_ACTION_MARK_EXT;
5218                         else
5219                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_COUNT:
5223                         ret = flow_dv_validate_action_count
5224                                 (dev, act,
5225                                  *action_flags | sub_action_flags,
5226                                  error);
5227                         if (ret < 0)
5228                                 return ret;
5229                         *count = act->conf;
5230                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5231                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5232                         ++actions_n;
5233                         break;
5234                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5235                         ret = flow_dv_validate_action_port_id(dev,
5236                                                               sub_action_flags,
5237                                                               act,
5238                                                               attr,
5239                                                               error);
5240                         if (ret)
5241                                 return ret;
5242                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5243                         ++actions_n;
5244                         break;
5245                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5246                         ret = flow_dv_validate_action_raw_encap_decap
5247                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5248                                  &actions_n, action, item_flags, error);
5249                         if (ret < 0)
5250                                 return ret;
5251                         ++actions_n;
5252                         break;
5253                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5254                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5255                         ret = flow_dv_validate_action_l2_encap(dev,
5256                                                                sub_action_flags,
5257                                                                act, attr,
5258                                                                error);
5259                         if (ret < 0)
5260                                 return ret;
5261                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5262                         ++actions_n;
5263                         break;
5264                 default:
5265                         return rte_flow_error_set(error, ENOTSUP,
5266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5267                                                   NULL,
5268                                                   "Doesn't support optional "
5269                                                   "action");
5270                 }
5271         }
5272         if (attr->ingress && !attr->transfer) {
5273                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5274                                           MLX5_FLOW_ACTION_RSS)))
5275                         return rte_flow_error_set(error, EINVAL,
5276                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5277                                                   NULL,
5278                                                   "Ingress must has a dest "
5279                                                   "QUEUE for Sample");
5280         } else if (attr->egress && !attr->transfer) {
5281                 return rte_flow_error_set(error, ENOTSUP,
5282                                           RTE_FLOW_ERROR_TYPE_ACTION,
5283                                           NULL,
5284                                           "Sample Only support Ingress "
5285                                           "or E-Switch");
5286         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5287                 MLX5_ASSERT(attr->transfer);
5288                 if (sample->ratio > 1)
5289                         return rte_flow_error_set(error, ENOTSUP,
5290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5291                                                   NULL,
5292                                                   "E-Switch doesn't support "
5293                                                   "any optional action "
5294                                                   "for sampling");
5295                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5296                         return rte_flow_error_set(error, ENOTSUP,
5297                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5298                                                   NULL,
5299                                                   "unsupported action QUEUE");
5300                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5301                         return rte_flow_error_set(error, ENOTSUP,
5302                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5303                                                   NULL,
5304                                                   "unsupported action QUEUE");
5305                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5306                         return rte_flow_error_set(error, EINVAL,
5307                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5308                                                   NULL,
5309                                                   "E-Switch must has a dest "
5310                                                   "port for mirroring");
5311                 if (!priv->config.hca_attr.reg_c_preserve &&
5312                      priv->representor_id != -1)
5313                         *fdb_mirror_limit = 1;
5314         }
5315         /* Continue validation for Xcap actions.*/
5316         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5317             (queue_index == 0xFFFF ||
5318              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5319                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5320                      MLX5_FLOW_XCAP_ACTIONS)
5321                         return rte_flow_error_set(error, ENOTSUP,
5322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5323                                                   NULL, "encap and decap "
5324                                                   "combination aren't "
5325                                                   "supported");
5326                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5327                                                         MLX5_FLOW_ACTION_ENCAP))
5328                         return rte_flow_error_set(error, ENOTSUP,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   NULL, "encap is not supported"
5331                                                   " for ingress traffic");
5332         }
5333         return 0;
5334 }
5335
5336 /**
5337  * Find existing modify-header resource or create and register a new one.
5338  *
5339  * @param dev[in, out]
5340  *   Pointer to rte_eth_dev structure.
5341  * @param[in, out] resource
5342  *   Pointer to modify-header resource.
5343  * @parm[in, out] dev_flow
5344  *   Pointer to the dev_flow.
5345  * @param[out] error
5346  *   pointer to error structure.
5347  *
5348  * @return
5349  *   0 on success otherwise -errno and errno is set.
5350  */
5351 static int
5352 flow_dv_modify_hdr_resource_register
5353                         (struct rte_eth_dev *dev,
5354                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5355                          struct mlx5_flow *dev_flow,
5356                          struct rte_flow_error *error)
5357 {
5358         struct mlx5_priv *priv = dev->data->dev_private;
5359         struct mlx5_dev_ctx_shared *sh = priv->sh;
5360         uint32_t key_len = sizeof(*resource) -
5361                            offsetof(typeof(*resource), ft_type) +
5362                            resource->actions_num * sizeof(resource->actions[0]);
5363         struct mlx5_hlist_entry *entry;
5364         struct mlx5_flow_cb_ctx ctx = {
5365                 .error = error,
5366                 .data = resource,
5367         };
5368         uint64_t key64;
5369
5370         resource->flags = dev_flow->dv.group ? 0 :
5371                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5372         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5373                                     resource->flags))
5374                 return rte_flow_error_set(error, EOVERFLOW,
5375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5376                                           "too many modify header items");
5377         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5378         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5379         if (!entry)
5380                 return -rte_errno;
5381         resource = container_of(entry, typeof(*resource), entry);
5382         dev_flow->handle->dvh.modify_hdr = resource;
5383         return 0;
5384 }
5385
5386 /**
5387  * Get DV flow counter by index.
5388  *
5389  * @param[in] dev
5390  *   Pointer to the Ethernet device structure.
5391  * @param[in] idx
5392  *   mlx5 flow counter index in the container.
5393  * @param[out] ppool
5394  *   mlx5 flow counter pool in the container,
5395  *
5396  * @return
5397  *   Pointer to the counter, NULL otherwise.
5398  */
5399 static struct mlx5_flow_counter *
5400 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5401                            uint32_t idx,
5402                            struct mlx5_flow_counter_pool **ppool)
5403 {
5404         struct mlx5_priv *priv = dev->data->dev_private;
5405         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5406         struct mlx5_flow_counter_pool *pool;
5407
5408         /* Decrease to original index and clear shared bit. */
5409         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5410         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5411         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5412         MLX5_ASSERT(pool);
5413         if (ppool)
5414                 *ppool = pool;
5415         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5416 }
5417
5418 /**
5419  * Check the devx counter belongs to the pool.
5420  *
5421  * @param[in] pool
5422  *   Pointer to the counter pool.
5423  * @param[in] id
5424  *   The counter devx ID.
5425  *
5426  * @return
5427  *   True if counter belongs to the pool, false otherwise.
5428  */
5429 static bool
5430 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5431 {
5432         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5433                    MLX5_COUNTERS_PER_POOL;
5434
5435         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5436                 return true;
5437         return false;
5438 }
5439
5440 /**
5441  * Get a pool by devx counter ID.
5442  *
5443  * @param[in] cmng
5444  *   Pointer to the counter management.
5445  * @param[in] id
5446  *   The counter devx ID.
5447  *
5448  * @return
5449  *   The counter pool pointer if exists, NULL otherwise,
5450  */
5451 static struct mlx5_flow_counter_pool *
5452 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5453 {
5454         uint32_t i;
5455         struct mlx5_flow_counter_pool *pool = NULL;
5456
5457         rte_spinlock_lock(&cmng->pool_update_sl);
5458         /* Check last used pool. */
5459         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5460             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5461                 pool = cmng->pools[cmng->last_pool_idx];
5462                 goto out;
5463         }
5464         /* ID out of range means no suitable pool in the container. */
5465         if (id > cmng->max_id || id < cmng->min_id)
5466                 goto out;
5467         /*
5468          * Find the pool from the end of the container, since mostly counter
5469          * ID is sequence increasing, and the last pool should be the needed
5470          * one.
5471          */
5472         i = cmng->n_valid;
5473         while (i--) {
5474                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5475
5476                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5477                         pool = pool_tmp;
5478                         break;
5479                 }
5480         }
5481 out:
5482         rte_spinlock_unlock(&cmng->pool_update_sl);
5483         return pool;
5484 }
5485
5486 /**
5487  * Resize a counter container.
5488  *
5489  * @param[in] dev
5490  *   Pointer to the Ethernet device structure.
5491  *
5492  * @return
5493  *   0 on success, otherwise negative errno value and rte_errno is set.
5494  */
5495 static int
5496 flow_dv_container_resize(struct rte_eth_dev *dev)
5497 {
5498         struct mlx5_priv *priv = dev->data->dev_private;
5499         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5500         void *old_pools = cmng->pools;
5501         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5502         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5503         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5504
5505         if (!pools) {
5506                 rte_errno = ENOMEM;
5507                 return -ENOMEM;
5508         }
5509         if (old_pools)
5510                 memcpy(pools, old_pools, cmng->n *
5511                                        sizeof(struct mlx5_flow_counter_pool *));
5512         cmng->n = resize;
5513         cmng->pools = pools;
5514         if (old_pools)
5515                 mlx5_free(old_pools);
5516         return 0;
5517 }
5518
5519 /**
5520  * Query a devx flow counter.
5521  *
5522  * @param[in] dev
5523  *   Pointer to the Ethernet device structure.
5524  * @param[in] cnt
5525  *   Index to the flow counter.
5526  * @param[out] pkts
5527  *   The statistics value of packets.
5528  * @param[out] bytes
5529  *   The statistics value of bytes.
5530  *
5531  * @return
5532  *   0 on success, otherwise a negative errno value and rte_errno is set.
5533  */
5534 static inline int
5535 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5536                      uint64_t *bytes)
5537 {
5538         struct mlx5_priv *priv = dev->data->dev_private;
5539         struct mlx5_flow_counter_pool *pool = NULL;
5540         struct mlx5_flow_counter *cnt;
5541         int offset;
5542
5543         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5544         MLX5_ASSERT(pool);
5545         if (priv->sh->cmng.counter_fallback)
5546                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5547                                         0, pkts, bytes, 0, NULL, NULL, 0);
5548         rte_spinlock_lock(&pool->sl);
5549         if (!pool->raw) {
5550                 *pkts = 0;
5551                 *bytes = 0;
5552         } else {
5553                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5554                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5555                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5556         }
5557         rte_spinlock_unlock(&pool->sl);
5558         return 0;
5559 }
5560
5561 /**
5562  * Create and initialize a new counter pool.
5563  *
5564  * @param[in] dev
5565  *   Pointer to the Ethernet device structure.
5566  * @param[out] dcs
5567  *   The devX counter handle.
5568  * @param[in] age
5569  *   Whether the pool is for counter that was allocated for aging.
5570  * @param[in/out] cont_cur
5571  *   Pointer to the container pointer, it will be update in pool resize.
5572  *
5573  * @return
5574  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5575  */
5576 static struct mlx5_flow_counter_pool *
5577 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5578                     uint32_t age)
5579 {
5580         struct mlx5_priv *priv = dev->data->dev_private;
5581         struct mlx5_flow_counter_pool *pool;
5582         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5583         bool fallback = priv->sh->cmng.counter_fallback;
5584         uint32_t size = sizeof(*pool);
5585
5586         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5587         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5588         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5589         if (!pool) {
5590                 rte_errno = ENOMEM;
5591                 return NULL;
5592         }
5593         pool->raw = NULL;
5594         pool->is_aged = !!age;
5595         pool->query_gen = 0;
5596         pool->min_dcs = dcs;
5597         rte_spinlock_init(&pool->sl);
5598         rte_spinlock_init(&pool->csl);
5599         TAILQ_INIT(&pool->counters[0]);
5600         TAILQ_INIT(&pool->counters[1]);
5601         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5602         rte_spinlock_lock(&cmng->pool_update_sl);
5603         pool->index = cmng->n_valid;
5604         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5605                 mlx5_free(pool);
5606                 rte_spinlock_unlock(&cmng->pool_update_sl);
5607                 return NULL;
5608         }
5609         cmng->pools[pool->index] = pool;
5610         cmng->n_valid++;
5611         if (unlikely(fallback)) {
5612                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5613
5614                 if (base < cmng->min_id)
5615                         cmng->min_id = base;
5616                 if (base > cmng->max_id)
5617                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5618                 cmng->last_pool_idx = pool->index;
5619         }
5620         rte_spinlock_unlock(&cmng->pool_update_sl);
5621         return pool;
5622 }
5623
5624 /**
5625  * Prepare a new counter and/or a new counter pool.
5626  *
5627  * @param[in] dev
5628  *   Pointer to the Ethernet device structure.
5629  * @param[out] cnt_free
5630  *   Where to put the pointer of a new counter.
5631  * @param[in] age
5632  *   Whether the pool is for counter that was allocated for aging.
5633  *
5634  * @return
5635  *   The counter pool pointer and @p cnt_free is set on success,
5636  *   NULL otherwise and rte_errno is set.
5637  */
5638 static struct mlx5_flow_counter_pool *
5639 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5640                              struct mlx5_flow_counter **cnt_free,
5641                              uint32_t age)
5642 {
5643         struct mlx5_priv *priv = dev->data->dev_private;
5644         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5645         struct mlx5_flow_counter_pool *pool;
5646         struct mlx5_counters tmp_tq;
5647         struct mlx5_devx_obj *dcs = NULL;
5648         struct mlx5_flow_counter *cnt;
5649         enum mlx5_counter_type cnt_type =
5650                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5651         bool fallback = priv->sh->cmng.counter_fallback;
5652         uint32_t i;
5653
5654         if (fallback) {
5655                 /* bulk_bitmap must be 0 for single counter allocation. */
5656                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5657                 if (!dcs)
5658                         return NULL;
5659                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5660                 if (!pool) {
5661                         pool = flow_dv_pool_create(dev, dcs, age);
5662                         if (!pool) {
5663                                 mlx5_devx_cmd_destroy(dcs);
5664                                 return NULL;
5665                         }
5666                 }
5667                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5668                 cnt = MLX5_POOL_GET_CNT(pool, i);
5669                 cnt->pool = pool;
5670                 cnt->dcs_when_free = dcs;
5671                 *cnt_free = cnt;
5672                 return pool;
5673         }
5674         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5675         if (!dcs) {
5676                 rte_errno = ENODATA;
5677                 return NULL;
5678         }
5679         pool = flow_dv_pool_create(dev, dcs, age);
5680         if (!pool) {
5681                 mlx5_devx_cmd_destroy(dcs);
5682                 return NULL;
5683         }
5684         TAILQ_INIT(&tmp_tq);
5685         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5686                 cnt = MLX5_POOL_GET_CNT(pool, i);
5687                 cnt->pool = pool;
5688                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5689         }
5690         rte_spinlock_lock(&cmng->csl[cnt_type]);
5691         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5692         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5693         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5694         (*cnt_free)->pool = pool;
5695         return pool;
5696 }
5697
5698 /**
5699  * Allocate a flow counter.
5700  *
5701  * @param[in] dev
5702  *   Pointer to the Ethernet device structure.
5703  * @param[in] age
5704  *   Whether the counter was allocated for aging.
5705  *
5706  * @return
5707  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5708  */
5709 static uint32_t
5710 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5711 {
5712         struct mlx5_priv *priv = dev->data->dev_private;
5713         struct mlx5_flow_counter_pool *pool = NULL;
5714         struct mlx5_flow_counter *cnt_free = NULL;
5715         bool fallback = priv->sh->cmng.counter_fallback;
5716         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5717         enum mlx5_counter_type cnt_type =
5718                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5719         uint32_t cnt_idx;
5720
5721         if (!priv->config.devx) {
5722                 rte_errno = ENOTSUP;
5723                 return 0;
5724         }
5725         /* Get free counters from container. */
5726         rte_spinlock_lock(&cmng->csl[cnt_type]);
5727         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5728         if (cnt_free)
5729                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5730         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5731         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5732                 goto err;
5733         pool = cnt_free->pool;
5734         if (fallback)
5735                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5736         /* Create a DV counter action only in the first time usage. */
5737         if (!cnt_free->action) {
5738                 uint16_t offset;
5739                 struct mlx5_devx_obj *dcs;
5740                 int ret;
5741
5742                 if (!fallback) {
5743                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5744                         dcs = pool->min_dcs;
5745                 } else {
5746                         offset = 0;
5747                         dcs = cnt_free->dcs_when_free;
5748                 }
5749                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5750                                                             &cnt_free->action);
5751                 if (ret) {
5752                         rte_errno = errno;
5753                         goto err;
5754                 }
5755         }
5756         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5757                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5758         /* Update the counter reset values. */
5759         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5760                                  &cnt_free->bytes))
5761                 goto err;
5762         if (!fallback && !priv->sh->cmng.query_thread_on)
5763                 /* Start the asynchronous batch query by the host thread. */
5764                 mlx5_set_query_alarm(priv->sh);
5765         return cnt_idx;
5766 err:
5767         if (cnt_free) {
5768                 cnt_free->pool = pool;
5769                 if (fallback)
5770                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5771                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5772                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5773                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5774         }
5775         return 0;
5776 }
5777
5778 /**
5779  * Allocate a shared flow counter.
5780  *
5781  * @param[in] ctx
5782  *   Pointer to the shared counter configuration.
5783  * @param[in] data
5784  *   Pointer to save the allocated counter index.
5785  *
5786  * @return
5787  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5788  */
5789
5790 static int32_t
5791 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5792 {
5793         struct mlx5_shared_counter_conf *conf = ctx;
5794         struct rte_eth_dev *dev = conf->dev;
5795         struct mlx5_flow_counter *cnt;
5796
5797         data->dword = flow_dv_counter_alloc(dev, 0);
5798         data->dword |= MLX5_CNT_SHARED_OFFSET;
5799         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5800         cnt->shared_info.id = conf->id;
5801         return 0;
5802 }
5803
5804 /**
5805  * Get a shared flow counter.
5806  *
5807  * @param[in] dev
5808  *   Pointer to the Ethernet device structure.
5809  * @param[in] id
5810  *   Counter identifier.
5811  *
5812  * @return
5813  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5814  */
5815 static uint32_t
5816 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5817 {
5818         struct mlx5_priv *priv = dev->data->dev_private;
5819         struct mlx5_shared_counter_conf conf = {
5820                 .dev = dev,
5821                 .id = id,
5822         };
5823         union mlx5_l3t_data data = {
5824                 .dword = 0,
5825         };
5826
5827         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5828                                flow_dv_counter_alloc_shared_cb, &conf);
5829         return data.dword;
5830 }
5831
5832 /**
5833  * Get age param from counter index.
5834  *
5835  * @param[in] dev
5836  *   Pointer to the Ethernet device structure.
5837  * @param[in] counter
5838  *   Index to the counter handler.
5839  *
5840  * @return
5841  *   The aging parameter specified for the counter index.
5842  */
5843 static struct mlx5_age_param*
5844 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5845                                 uint32_t counter)
5846 {
5847         struct mlx5_flow_counter *cnt;
5848         struct mlx5_flow_counter_pool *pool = NULL;
5849
5850         flow_dv_counter_get_by_idx(dev, counter, &pool);
5851         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5852         cnt = MLX5_POOL_GET_CNT(pool, counter);
5853         return MLX5_CNT_TO_AGE(cnt);
5854 }
5855
5856 /**
5857  * Remove a flow counter from aged counter list.
5858  *
5859  * @param[in] dev
5860  *   Pointer to the Ethernet device structure.
5861  * @param[in] counter
5862  *   Index to the counter handler.
5863  * @param[in] cnt
5864  *   Pointer to the counter handler.
5865  */
5866 static void
5867 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5868                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5869 {
5870         struct mlx5_age_info *age_info;
5871         struct mlx5_age_param *age_param;
5872         struct mlx5_priv *priv = dev->data->dev_private;
5873         uint16_t expected = AGE_CANDIDATE;
5874
5875         age_info = GET_PORT_AGE_INFO(priv);
5876         age_param = flow_dv_counter_idx_get_age(dev, counter);
5877         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5878                                          AGE_FREE, false, __ATOMIC_RELAXED,
5879                                          __ATOMIC_RELAXED)) {
5880                 /**
5881                  * We need the lock even it is age timeout,
5882                  * since counter may still in process.
5883                  */
5884                 rte_spinlock_lock(&age_info->aged_sl);
5885                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5886                 rte_spinlock_unlock(&age_info->aged_sl);
5887                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5888         }
5889 }
5890
5891 /**
5892  * Release a flow counter.
5893  *
5894  * @param[in] dev
5895  *   Pointer to the Ethernet device structure.
5896  * @param[in] counter
5897  *   Index to the counter handler.
5898  */
5899 static void
5900 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5901 {
5902         struct mlx5_priv *priv = dev->data->dev_private;
5903         struct mlx5_flow_counter_pool *pool = NULL;
5904         struct mlx5_flow_counter *cnt;
5905         enum mlx5_counter_type cnt_type;
5906
5907         if (!counter)
5908                 return;
5909         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5910         MLX5_ASSERT(pool);
5911         if (IS_SHARED_CNT(counter) &&
5912             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5913                 return;
5914         if (pool->is_aged)
5915                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5916         cnt->pool = pool;
5917         /*
5918          * Put the counter back to list to be updated in none fallback mode.
5919          * Currently, we are using two list alternately, while one is in query,
5920          * add the freed counter to the other list based on the pool query_gen
5921          * value. After query finishes, add counter the list to the global
5922          * container counter list. The list changes while query starts. In
5923          * this case, lock will not be needed as query callback and release
5924          * function both operate with the different list.
5925          *
5926          */
5927         if (!priv->sh->cmng.counter_fallback) {
5928                 rte_spinlock_lock(&pool->csl);
5929                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5930                 rte_spinlock_unlock(&pool->csl);
5931         } else {
5932                 cnt->dcs_when_free = cnt->dcs_when_active;
5933                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5934                                            MLX5_COUNTER_TYPE_ORIGIN;
5935                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5936                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5937                                   cnt, next);
5938                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5939         }
5940 }
5941
5942 /**
5943  * Resize a meter id container.
5944  *
5945  * @param[in] dev
5946  *   Pointer to the Ethernet device structure.
5947  *
5948  * @return
5949  *   0 on success, otherwise negative errno value and rte_errno is set.
5950  */
5951 static int
5952 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5953 {
5954         struct mlx5_priv *priv = dev->data->dev_private;
5955         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5956         void *old_pools = mtrmng->pools;
5957         uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5958         uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5959         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5960
5961         if (!pools) {
5962                 rte_errno = ENOMEM;
5963                 return -ENOMEM;
5964         }
5965         if (!mtrmng->n)
5966                 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
5967                         mlx5_free(pools);
5968                         return -ENOMEM;
5969                 }
5970         if (old_pools)
5971                 memcpy(pools, old_pools, mtrmng->n *
5972                                        sizeof(struct mlx5_aso_mtr_pool *));
5973         mtrmng->n = resize;
5974         mtrmng->pools = pools;
5975         if (old_pools)
5976                 mlx5_free(old_pools);
5977         return 0;
5978 }
5979
5980 /**
5981  * Prepare a new meter and/or a new meter pool.
5982  *
5983  * @param[in] dev
5984  *   Pointer to the Ethernet device structure.
5985  * @param[out] mtr_free
5986  *   Where to put the pointer of a new meter.g.
5987  *
5988  * @return
5989  *   The meter pool pointer and @mtr_free is set on success,
5990  *   NULL otherwise and rte_errno is set.
5991  */
5992 static struct mlx5_aso_mtr_pool *
5993 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5994                              struct mlx5_aso_mtr **mtr_free)
5995 {
5996         struct mlx5_priv *priv = dev->data->dev_private;
5997         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5998         struct mlx5_aso_mtr_pool *pool = NULL;
5999         struct mlx5_devx_obj *dcs = NULL;
6000         uint32_t i;
6001         uint32_t log_obj_size;
6002
6003         log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6004         dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6005                         priv->sh->pdn, log_obj_size);
6006         if (!dcs) {
6007                 rte_errno = ENODATA;
6008                 return NULL;
6009         }
6010         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6011         if (!pool) {
6012                 rte_errno = ENOMEM;
6013                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6014                 return NULL;
6015         }
6016         pool->devx_obj = dcs;
6017         pool->index = mtrmng->n_valid;
6018         if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
6019                 mlx5_free(pool);
6020                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6021                 return NULL;
6022         }
6023         mtrmng->pools[pool->index] = pool;
6024         mtrmng->n_valid++;
6025         for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6026                 pool->mtrs[i].offset = i;
6027                 pool->mtrs[i].fm.meter_id = UINT32_MAX;
6028                 LIST_INSERT_HEAD(&mtrmng->meters,
6029                                                 &pool->mtrs[i], next);
6030         }
6031         pool->mtrs[0].offset = 0;
6032         pool->mtrs[0].fm.meter_id = UINT32_MAX;
6033         *mtr_free = &pool->mtrs[0];
6034         return pool;
6035 }
6036
6037 /**
6038  * Release a flow meter into pool.
6039  *
6040  * @param[in] dev
6041  *   Pointer to the Ethernet device structure.
6042  * @param[in] mtr_idx
6043  *   Index to aso flow meter.
6044  */
6045 static void
6046 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6047 {
6048         struct mlx5_priv *priv = dev->data->dev_private;
6049         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6050         struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6051
6052         MLX5_ASSERT(aso_mtr);
6053         rte_spinlock_lock(&mtrmng->mtrsl);
6054         memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6055         aso_mtr->state = ASO_METER_FREE;
6056         aso_mtr->fm.meter_id = UINT32_MAX;
6057         LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6058         rte_spinlock_unlock(&mtrmng->mtrsl);
6059 }
6060
6061 /**
6062  * Allocate a aso flow meter.
6063  *
6064  * @param[in] dev
6065  *   Pointer to the Ethernet device structure.
6066  *
6067  * @return
6068  *   Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6069  */
6070 static uint32_t
6071 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6072 {
6073         struct mlx5_priv *priv = dev->data->dev_private;
6074         struct mlx5_aso_mtr *mtr_free = NULL;
6075         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6076         struct mlx5_aso_mtr_pool *pool;
6077         uint32_t mtr_idx = 0;
6078
6079         if (!priv->config.devx) {
6080                 rte_errno = ENOTSUP;
6081                 return 0;
6082         }
6083         /* Allocate the flow meter memory. */
6084         /* Get free meters from management. */
6085         rte_spinlock_lock(&mtrmng->mtrsl);
6086         mtr_free = LIST_FIRST(&mtrmng->meters);
6087         if (mtr_free)
6088                 LIST_REMOVE(mtr_free, next);
6089         if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6090                 rte_spinlock_unlock(&mtrmng->mtrsl);
6091                 return 0;
6092         }
6093         mtr_free->state = ASO_METER_WAIT;
6094         rte_spinlock_unlock(&mtrmng->mtrsl);
6095         pool = container_of(mtr_free,
6096                                         struct mlx5_aso_mtr_pool,
6097                                         mtrs[mtr_free->offset]);
6098         mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6099         return mtr_idx;
6100 }
6101
6102 /**
6103  * Verify the @p attributes will be correctly understood by the NIC and store
6104  * them in the @p flow if everything is correct.
6105  *
6106  * @param[in] dev
6107  *   Pointer to dev struct.
6108  * @param[in] attributes
6109  *   Pointer to flow attributes
6110  * @param[in] external
6111  *   This flow rule is created by request external to PMD.
6112  * @param[out] error
6113  *   Pointer to error structure.
6114  *
6115  * @return
6116  *   - 0 on success and non root table.
6117  *   - 1 on success and root table.
6118  *   - a negative errno value otherwise and rte_errno is set.
6119  */
6120 static int
6121 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6122                             const struct mlx5_flow_tunnel *tunnel,
6123                             const struct rte_flow_attr *attributes,
6124                             const struct flow_grp_info *grp_info,
6125                             struct rte_flow_error *error)
6126 {
6127         struct mlx5_priv *priv = dev->data->dev_private;
6128         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6129         int ret = 0;
6130
6131 #ifndef HAVE_MLX5DV_DR
6132         RTE_SET_USED(tunnel);
6133         RTE_SET_USED(grp_info);
6134         if (attributes->group)
6135                 return rte_flow_error_set(error, ENOTSUP,
6136                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6137                                           NULL,
6138                                           "groups are not supported");
6139 #else
6140         uint32_t table = 0;
6141
6142         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6143                                        grp_info, error);
6144         if (ret)
6145                 return ret;
6146         if (!table)
6147                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6148 #endif
6149         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6150             attributes->priority > lowest_priority)
6151                 return rte_flow_error_set(error, ENOTSUP,
6152                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6153                                           NULL,
6154                                           "priority out of range");
6155         if (attributes->transfer) {
6156                 if (!priv->config.dv_esw_en)
6157                         return rte_flow_error_set
6158                                 (error, ENOTSUP,
6159                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6160                                  "E-Switch dr is not supported");
6161                 if (!(priv->representor || priv->master))
6162                         return rte_flow_error_set
6163                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6164                                  NULL, "E-Switch configuration can only be"
6165                                  " done by a master or a representor device");
6166                 if (attributes->egress)
6167                         return rte_flow_error_set
6168                                 (error, ENOTSUP,
6169                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6170                                  "egress is not supported");
6171         }
6172         if (!(attributes->egress ^ attributes->ingress))
6173                 return rte_flow_error_set(error, ENOTSUP,
6174                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6175                                           "must specify exactly one of "
6176                                           "ingress or egress");
6177         return ret;
6178 }
6179
6180 /**
6181  * Internal validation function. For validating both actions and items.
6182  *
6183  * @param[in] dev
6184  *   Pointer to the rte_eth_dev structure.
6185  * @param[in] attr
6186  *   Pointer to the flow attributes.
6187  * @param[in] items
6188  *   Pointer to the list of items.
6189  * @param[in] actions
6190  *   Pointer to the list of actions.
6191  * @param[in] external
6192  *   This flow rule is created by request external to PMD.
6193  * @param[in] hairpin
6194  *   Number of hairpin TX actions, 0 means classic flow.
6195  * @param[out] error
6196  *   Pointer to the error structure.
6197  *
6198  * @return
6199  *   0 on success, a negative errno value otherwise and rte_errno is set.
6200  */
6201 static int
6202 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6203                  const struct rte_flow_item items[],
6204                  const struct rte_flow_action actions[],
6205                  bool external, int hairpin, struct rte_flow_error *error)
6206 {
6207         int ret;
6208         uint64_t action_flags = 0;
6209         uint64_t item_flags = 0;
6210         uint64_t last_item = 0;
6211         uint8_t next_protocol = 0xff;
6212         uint16_t ether_type = 0;
6213         int actions_n = 0;
6214         uint8_t item_ipv6_proto = 0;
6215         int fdb_mirror_limit = 0;
6216         int modify_after_mirror = 0;
6217         const struct rte_flow_item *geneve_item = NULL;
6218         const struct rte_flow_item *gre_item = NULL;
6219         const struct rte_flow_item *gtp_item = NULL;
6220         const struct rte_flow_action_raw_decap *decap;
6221         const struct rte_flow_action_raw_encap *encap;
6222         const struct rte_flow_action_rss *rss = NULL;
6223         const struct rte_flow_action_rss *sample_rss = NULL;
6224         const struct rte_flow_action_count *count = NULL;
6225         const struct rte_flow_action_count *sample_count = NULL;
6226         const struct rte_flow_item_tcp nic_tcp_mask = {
6227                 .hdr = {
6228                         .tcp_flags = 0xFF,
6229                         .src_port = RTE_BE16(UINT16_MAX),
6230                         .dst_port = RTE_BE16(UINT16_MAX),
6231                 }
6232         };
6233         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6234                 .hdr = {
6235                         .src_addr =
6236                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6237                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6238                         .dst_addr =
6239                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6240                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6241                         .vtc_flow = RTE_BE32(0xffffffff),
6242                         .proto = 0xff,
6243                         .hop_limits = 0xff,
6244                 },
6245                 .has_frag_ext = 1,
6246         };
6247         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6248                 .hdr = {
6249                         .common = {
6250                                 .u32 =
6251                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6252                                         .type = 0xFF,
6253                                         }).u32),
6254                         },
6255                         .dummy[0] = 0xffffffff,
6256                 },
6257         };
6258         struct mlx5_priv *priv = dev->data->dev_private;
6259         struct mlx5_dev_config *dev_conf = &priv->config;
6260         uint16_t queue_index = 0xFFFF;
6261         const struct rte_flow_item_vlan *vlan_m = NULL;
6262         uint32_t rw_act_num = 0;
6263         uint64_t is_root;
6264         const struct mlx5_flow_tunnel *tunnel;
6265         struct flow_grp_info grp_info = {
6266                 .external = !!external,
6267                 .transfer = !!attr->transfer,
6268                 .fdb_def_rule = !!priv->fdb_def_rule,
6269         };
6270         const struct rte_eth_hairpin_conf *conf;
6271
6272         if (items == NULL)
6273                 return -1;
6274         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6275                 tunnel = flow_items_to_tunnel(items);
6276                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6277                                 MLX5_FLOW_ACTION_DECAP;
6278         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6279                 tunnel = flow_actions_to_tunnel(actions);
6280                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6281         } else {
6282                 tunnel = NULL;
6283         }
6284         if (tunnel && priv->representor)
6285                 return rte_flow_error_set(error, ENOTSUP,
6286                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6287                                           "decap not supported "
6288                                           "for VF representor");
6289         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6290                                 (dev, tunnel, attr, items, actions);
6291         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6292         if (ret < 0)
6293                 return ret;
6294         is_root = (uint64_t)ret;
6295         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6296                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6297                 int type = items->type;
6298
6299                 if (!mlx5_flow_os_item_supported(type))
6300                         return rte_flow_error_set(error, ENOTSUP,
6301                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6302                                                   NULL, "item not supported");
6303                 switch (type) {
6304                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6305                         if (items[0].type != (typeof(items[0].type))
6306                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6307                                 return rte_flow_error_set
6308                                                 (error, EINVAL,
6309                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6310                                                 NULL, "MLX5 private items "
6311                                                 "must be the first");
6312                         break;
6313                 case RTE_FLOW_ITEM_TYPE_VOID:
6314                         break;
6315                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6316                         ret = flow_dv_validate_item_port_id
6317                                         (dev, items, attr, item_flags, error);
6318                         if (ret < 0)
6319                                 return ret;
6320                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6321                         break;
6322                 case RTE_FLOW_ITEM_TYPE_ETH:
6323                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6324                                                           true, error);
6325                         if (ret < 0)
6326                                 return ret;
6327                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6328                                              MLX5_FLOW_LAYER_OUTER_L2;
6329                         if (items->mask != NULL && items->spec != NULL) {
6330                                 ether_type =
6331                                         ((const struct rte_flow_item_eth *)
6332                                          items->spec)->type;
6333                                 ether_type &=
6334                                         ((const struct rte_flow_item_eth *)
6335                                          items->mask)->type;
6336                                 ether_type = rte_be_to_cpu_16(ether_type);
6337                         } else {
6338                                 ether_type = 0;
6339                         }
6340                         break;
6341                 case RTE_FLOW_ITEM_TYPE_VLAN:
6342                         ret = flow_dv_validate_item_vlan(items, item_flags,
6343                                                          dev, error);
6344                         if (ret < 0)
6345                                 return ret;
6346                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6347                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6348                         if (items->mask != NULL && items->spec != NULL) {
6349                                 ether_type =
6350                                         ((const struct rte_flow_item_vlan *)
6351                                          items->spec)->inner_type;
6352                                 ether_type &=
6353                                         ((const struct rte_flow_item_vlan *)
6354                                          items->mask)->inner_type;
6355                                 ether_type = rte_be_to_cpu_16(ether_type);
6356                         } else {
6357                                 ether_type = 0;
6358                         }
6359                         /* Store outer VLAN mask for of_push_vlan action. */
6360                         if (!tunnel)
6361                                 vlan_m = items->mask;
6362                         break;
6363                 case RTE_FLOW_ITEM_TYPE_IPV4:
6364                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6365                                                   &item_flags, &tunnel);
6366                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6367                                                          last_item, ether_type,
6368                                                          error);
6369                         if (ret < 0)
6370                                 return ret;
6371                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6372                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6373                         if (items->mask != NULL &&
6374                             ((const struct rte_flow_item_ipv4 *)
6375                              items->mask)->hdr.next_proto_id) {
6376                                 next_protocol =
6377                                         ((const struct rte_flow_item_ipv4 *)
6378                                          (items->spec))->hdr.next_proto_id;
6379                                 next_protocol &=
6380                                         ((const struct rte_flow_item_ipv4 *)
6381                                          (items->mask))->hdr.next_proto_id;
6382                         } else {
6383                                 /* Reset for inner layer. */
6384                                 next_protocol = 0xff;
6385                         }
6386                         break;
6387                 case RTE_FLOW_ITEM_TYPE_IPV6:
6388                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6389                                                   &item_flags, &tunnel);
6390                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6391                                                            last_item,
6392                                                            ether_type,
6393                                                            &nic_ipv6_mask,
6394                                                            error);
6395                         if (ret < 0)
6396                                 return ret;
6397                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6398                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6399                         if (items->mask != NULL &&
6400                             ((const struct rte_flow_item_ipv6 *)
6401                              items->mask)->hdr.proto) {
6402                                 item_ipv6_proto =
6403                                         ((const struct rte_flow_item_ipv6 *)
6404                                          items->spec)->hdr.proto;
6405                                 next_protocol =
6406                                         ((const struct rte_flow_item_ipv6 *)
6407                                          items->spec)->hdr.proto;
6408                                 next_protocol &=
6409                                         ((const struct rte_flow_item_ipv6 *)
6410                                          items->mask)->hdr.proto;
6411                         } else {
6412                                 /* Reset for inner layer. */
6413                                 next_protocol = 0xff;
6414                         }
6415                         break;
6416                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6417                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6418                                                                   item_flags,
6419                                                                   error);
6420                         if (ret < 0)
6421                                 return ret;
6422                         last_item = tunnel ?
6423                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6424                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6425                         if (items->mask != NULL &&
6426                             ((const struct rte_flow_item_ipv6_frag_ext *)
6427                              items->mask)->hdr.next_header) {
6428                                 next_protocol =
6429                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6430                                  items->spec)->hdr.next_header;
6431                                 next_protocol &=
6432                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6433                                  items->mask)->hdr.next_header;
6434                         } else {
6435                                 /* Reset for inner layer. */
6436                                 next_protocol = 0xff;
6437                         }
6438                         break;
6439                 case RTE_FLOW_ITEM_TYPE_TCP:
6440                         ret = mlx5_flow_validate_item_tcp
6441                                                 (items, item_flags,
6442                                                  next_protocol,
6443                                                  &nic_tcp_mask,
6444                                                  error);
6445                         if (ret < 0)
6446                                 return ret;
6447                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6448                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6449                         break;
6450                 case RTE_FLOW_ITEM_TYPE_UDP:
6451                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6452                                                           next_protocol,
6453                                                           error);
6454                         if (ret < 0)
6455                                 return ret;
6456                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6457                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6458                         break;
6459                 case RTE_FLOW_ITEM_TYPE_GRE:
6460                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6461                                                           next_protocol, error);
6462                         if (ret < 0)
6463                                 return ret;
6464                         gre_item = items;
6465                         last_item = MLX5_FLOW_LAYER_GRE;
6466                         break;
6467                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6468                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6469                                                             next_protocol,
6470                                                             error);
6471                         if (ret < 0)
6472                                 return ret;
6473                         last_item = MLX5_FLOW_LAYER_NVGRE;
6474                         break;
6475                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6476                         ret = mlx5_flow_validate_item_gre_key
6477                                 (items, item_flags, gre_item, error);
6478                         if (ret < 0)
6479                                 return ret;
6480                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6481                         break;
6482                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6483                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6484                                                             error);
6485                         if (ret < 0)
6486                                 return ret;
6487                         last_item = MLX5_FLOW_LAYER_VXLAN;
6488                         break;
6489                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6490                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6491                                                                 item_flags, dev,
6492                                                                 error);
6493                         if (ret < 0)
6494                                 return ret;
6495                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6496                         break;
6497                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6498                         ret = mlx5_flow_validate_item_geneve(items,
6499                                                              item_flags, dev,
6500                                                              error);
6501                         if (ret < 0)
6502                                 return ret;
6503                         geneve_item = items;
6504                         last_item = MLX5_FLOW_LAYER_GENEVE;
6505                         break;
6506                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6507                         ret = mlx5_flow_validate_item_geneve_opt(items,
6508                                                                  last_item,
6509                                                                  geneve_item,
6510                                                                  dev,
6511                                                                  error);
6512                         if (ret < 0)
6513                                 return ret;
6514                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6515                         break;
6516                 case RTE_FLOW_ITEM_TYPE_MPLS:
6517                         ret = mlx5_flow_validate_item_mpls(dev, items,
6518                                                            item_flags,
6519                                                            last_item, error);
6520                         if (ret < 0)
6521                                 return ret;
6522                         last_item = MLX5_FLOW_LAYER_MPLS;
6523                         break;
6524
6525                 case RTE_FLOW_ITEM_TYPE_MARK:
6526                         ret = flow_dv_validate_item_mark(dev, items, attr,
6527                                                          error);
6528                         if (ret < 0)
6529                                 return ret;
6530                         last_item = MLX5_FLOW_ITEM_MARK;
6531                         break;
6532                 case RTE_FLOW_ITEM_TYPE_META:
6533                         ret = flow_dv_validate_item_meta(dev, items, attr,
6534                                                          error);
6535                         if (ret < 0)
6536                                 return ret;
6537                         last_item = MLX5_FLOW_ITEM_METADATA;
6538                         break;
6539                 case RTE_FLOW_ITEM_TYPE_ICMP:
6540                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6541                                                            next_protocol,
6542                                                            error);
6543                         if (ret < 0)
6544                                 return ret;
6545                         last_item = MLX5_FLOW_LAYER_ICMP;
6546                         break;
6547                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6548                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6549                                                             next_protocol,
6550                                                             error);
6551                         if (ret < 0)
6552                                 return ret;
6553                         item_ipv6_proto = IPPROTO_ICMPV6;
6554                         last_item = MLX5_FLOW_LAYER_ICMP6;
6555                         break;
6556                 case RTE_FLOW_ITEM_TYPE_TAG:
6557                         ret = flow_dv_validate_item_tag(dev, items,
6558                                                         attr, error);
6559                         if (ret < 0)
6560                                 return ret;
6561                         last_item = MLX5_FLOW_ITEM_TAG;
6562                         break;
6563                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6564                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6565                         break;
6566                 case RTE_FLOW_ITEM_TYPE_GTP:
6567                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6568                                                         error);
6569                         if (ret < 0)
6570                                 return ret;
6571                         gtp_item = items;
6572                         last_item = MLX5_FLOW_LAYER_GTP;
6573                         break;
6574                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6575                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6576                                                             gtp_item, attr,
6577                                                             error);
6578                         if (ret < 0)
6579                                 return ret;
6580                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6581                         break;
6582                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6583                         /* Capacity will be checked in the translate stage. */
6584                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6585                                                             last_item,
6586                                                             ether_type,
6587                                                             &nic_ecpri_mask,
6588                                                             error);
6589                         if (ret < 0)
6590                                 return ret;
6591                         last_item = MLX5_FLOW_LAYER_ECPRI;
6592                         break;
6593                 default:
6594                         return rte_flow_error_set(error, ENOTSUP,
6595                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6596                                                   NULL, "item not supported");
6597                 }
6598                 item_flags |= last_item;
6599         }
6600         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6601                 int type = actions->type;
6602
6603                 if (!mlx5_flow_os_action_supported(type))
6604                         return rte_flow_error_set(error, ENOTSUP,
6605                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6606                                                   actions,
6607                                                   "action not supported");
6608                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6609                         return rte_flow_error_set(error, ENOTSUP,
6610                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6611                                                   actions, "too many actions");
6612                 switch (type) {
6613                 case RTE_FLOW_ACTION_TYPE_VOID:
6614                         break;
6615                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6616                         ret = flow_dv_validate_action_port_id(dev,
6617                                                               action_flags,
6618                                                               actions,
6619                                                               attr,
6620                                                               error);
6621                         if (ret)
6622                                 return ret;
6623                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6624                         ++actions_n;
6625                         break;
6626                 case RTE_FLOW_ACTION_TYPE_FLAG:
6627                         ret = flow_dv_validate_action_flag(dev, action_flags,
6628                                                            attr, error);
6629                         if (ret < 0)
6630                                 return ret;
6631                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6632                                 /* Count all modify-header actions as one. */
6633                                 if (!(action_flags &
6634                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6635                                         ++actions_n;
6636                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6637                                                 MLX5_FLOW_ACTION_MARK_EXT;
6638                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6639                                         modify_after_mirror = 1;
6640
6641                         } else {
6642                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6643                                 ++actions_n;
6644                         }
6645                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6646                         break;
6647                 case RTE_FLOW_ACTION_TYPE_MARK:
6648                         ret = flow_dv_validate_action_mark(dev, actions,
6649                                                            action_flags,
6650                                                            attr, error);
6651                         if (ret < 0)
6652                                 return ret;
6653                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6654                                 /* Count all modify-header actions as one. */
6655                                 if (!(action_flags &
6656                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6657                                         ++actions_n;
6658                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6659                                                 MLX5_FLOW_ACTION_MARK_EXT;
6660                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6661                                         modify_after_mirror = 1;
6662                         } else {
6663                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6664                                 ++actions_n;
6665                         }
6666                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6667                         break;
6668                 case RTE_FLOW_ACTION_TYPE_SET_META:
6669                         ret = flow_dv_validate_action_set_meta(dev, actions,
6670                                                                action_flags,
6671                                                                attr, error);
6672                         if (ret < 0)
6673                                 return ret;
6674                         /* Count all modify-header actions as one action. */
6675                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6676                                 ++actions_n;
6677                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6678                                 modify_after_mirror = 1;
6679                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6680                         rw_act_num += MLX5_ACT_NUM_SET_META;
6681                         break;
6682                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6683                         ret = flow_dv_validate_action_set_tag(dev, actions,
6684                                                               action_flags,
6685                                                               attr, error);
6686                         if (ret < 0)
6687                                 return ret;
6688                         /* Count all modify-header actions as one action. */
6689                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6690                                 ++actions_n;
6691                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6692                                 modify_after_mirror = 1;
6693                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6694                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6695                         break;
6696                 case RTE_FLOW_ACTION_TYPE_DROP:
6697                         ret = mlx5_flow_validate_action_drop(action_flags,
6698                                                              attr, error);
6699                         if (ret < 0)
6700                                 return ret;
6701                         action_flags |= MLX5_FLOW_ACTION_DROP;
6702                         ++actions_n;
6703                         break;
6704                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6705                         ret = mlx5_flow_validate_action_queue(actions,
6706                                                               action_flags, dev,
6707                                                               attr, error);
6708                         if (ret < 0)
6709                                 return ret;
6710                         queue_index = ((const struct rte_flow_action_queue *)
6711                                                         (actions->conf))->index;
6712                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6713                         ++actions_n;
6714                         break;
6715                 case RTE_FLOW_ACTION_TYPE_RSS:
6716                         rss = actions->conf;
6717                         ret = mlx5_flow_validate_action_rss(actions,
6718                                                             action_flags, dev,
6719                                                             attr, item_flags,
6720                                                             error);
6721                         if (ret < 0)
6722                                 return ret;
6723                         if (rss && sample_rss &&
6724                             (sample_rss->level != rss->level ||
6725                             sample_rss->types != rss->types))
6726                                 return rte_flow_error_set(error, ENOTSUP,
6727                                         RTE_FLOW_ERROR_TYPE_ACTION,
6728                                         NULL,
6729                                         "Can't use the different RSS types "
6730                                         "or level in the same flow");
6731                         if (rss != NULL && rss->queue_num)
6732                                 queue_index = rss->queue[0];
6733                         action_flags |= MLX5_FLOW_ACTION_RSS;
6734                         ++actions_n;
6735                         break;
6736                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6737                         ret =
6738                         mlx5_flow_validate_action_default_miss(action_flags,
6739                                         attr, error);
6740                         if (ret < 0)
6741                                 return ret;
6742                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6743                         ++actions_n;
6744                         break;
6745                 case RTE_FLOW_ACTION_TYPE_COUNT:
6746                         ret = flow_dv_validate_action_count(dev, actions,
6747                                                             action_flags,
6748                                                             error);
6749                         if (ret < 0)
6750                                 return ret;
6751                         count = actions->conf;
6752                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6753                         ++actions_n;
6754                         break;
6755                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6756                         if (flow_dv_validate_action_pop_vlan(dev,
6757                                                              action_flags,
6758                                                              actions,
6759                                                              item_flags, attr,
6760                                                              error))
6761                                 return -rte_errno;
6762                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6763                                 modify_after_mirror = 1;
6764                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6765                         ++actions_n;
6766                         break;
6767                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6768                         ret = flow_dv_validate_action_push_vlan(dev,
6769                                                                 action_flags,
6770                                                                 vlan_m,
6771                                                                 actions, attr,
6772                                                                 error);
6773                         if (ret < 0)
6774                                 return ret;
6775                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6776                                 modify_after_mirror = 1;
6777                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6778                         ++actions_n;
6779                         break;
6780                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6781                         ret = flow_dv_validate_action_set_vlan_pcp
6782                                                 (action_flags, actions, error);
6783                         if (ret < 0)
6784                                 return ret;
6785                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6786                                 modify_after_mirror = 1;
6787                         /* Count PCP with push_vlan command. */
6788                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6789                         break;
6790                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6791                         ret = flow_dv_validate_action_set_vlan_vid
6792                                                 (item_flags, action_flags,
6793                                                  actions, error);
6794                         if (ret < 0)
6795                                 return ret;
6796                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6797                                 modify_after_mirror = 1;
6798                         /* Count VID with push_vlan command. */
6799                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6800                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6801                         break;
6802                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6803                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6804                         ret = flow_dv_validate_action_l2_encap(dev,
6805                                                                action_flags,
6806                                                                actions, attr,
6807                                                                error);
6808                         if (ret < 0)
6809                                 return ret;
6810                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6811                         ++actions_n;
6812                         break;
6813                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6814                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6815                         ret = flow_dv_validate_action_decap(dev, action_flags,
6816                                                             actions, item_flags,
6817                                                             attr, error);
6818                         if (ret < 0)
6819                                 return ret;
6820                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6821                                 modify_after_mirror = 1;
6822                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6823                         ++actions_n;
6824                         break;
6825                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6826                         ret = flow_dv_validate_action_raw_encap_decap
6827                                 (dev, NULL, actions->conf, attr, &action_flags,
6828                                  &actions_n, actions, item_flags, error);
6829                         if (ret < 0)
6830                                 return ret;
6831                         break;
6832                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6833                         decap = actions->conf;
6834                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6835                                 ;
6836                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6837                                 encap = NULL;
6838                                 actions--;
6839                         } else {
6840                                 encap = actions->conf;
6841                         }
6842                         ret = flow_dv_validate_action_raw_encap_decap
6843                                            (dev,
6844                                             decap ? decap : &empty_decap, encap,
6845                                             attr, &action_flags, &actions_n,
6846                                             actions, item_flags, error);
6847                         if (ret < 0)
6848                                 return ret;
6849                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6850                             (action_flags & MLX5_FLOW_ACTION_DECAP))
6851                                 modify_after_mirror = 1;
6852                         break;
6853                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6854                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6855                         ret = flow_dv_validate_action_modify_mac(action_flags,
6856                                                                  actions,
6857                                                                  item_flags,
6858                                                                  error);
6859                         if (ret < 0)
6860                                 return ret;
6861                         /* Count all modify-header actions as one action. */
6862                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6863                                 ++actions_n;
6864                         action_flags |= actions->type ==
6865                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6866                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6867                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6868                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6869                                 modify_after_mirror = 1;
6870                         /*
6871                          * Even if the source and destination MAC addresses have
6872                          * overlap in the header with 4B alignment, the convert
6873                          * function will handle them separately and 4 SW actions
6874                          * will be created. And 2 actions will be added each
6875                          * time no matter how many bytes of address will be set.
6876                          */
6877                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6878                         break;
6879                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6880                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6881                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6882                                                                   actions,
6883                                                                   item_flags,
6884                                                                   error);
6885                         if (ret < 0)
6886                                 return ret;
6887                         /* Count all modify-header actions as one action. */
6888                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6889                                 ++actions_n;
6890                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6891                                 modify_after_mirror = 1;
6892                         action_flags |= actions->type ==
6893                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6894                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6895                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6896                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6897                         break;
6898                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6899                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6900                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6901                                                                   actions,
6902                                                                   item_flags,
6903                                                                   error);
6904                         if (ret < 0)
6905                                 return ret;
6906                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6907                                 return rte_flow_error_set(error, ENOTSUP,
6908                                         RTE_FLOW_ERROR_TYPE_ACTION,
6909                                         actions,
6910                                         "Can't change header "
6911                                         "with ICMPv6 proto");
6912                         /* Count all modify-header actions as one action. */
6913                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6914                                 ++actions_n;
6915                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6916                                 modify_after_mirror = 1;
6917                         action_flags |= actions->type ==
6918                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6919                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6920                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6921                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6922                         break;
6923                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6924                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6925                         ret = flow_dv_validate_action_modify_tp(action_flags,
6926                                                                 actions,
6927                                                                 item_flags,
6928                                                                 error);
6929                         if (ret < 0)
6930                                 return ret;
6931                         /* Count all modify-header actions as one action. */
6932                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6933                                 ++actions_n;
6934                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6935                                 modify_after_mirror = 1;
6936                         action_flags |= actions->type ==
6937                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6938                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6939                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6940                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6941                         break;
6942                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6943                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6944                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6945                                                                  actions,
6946                                                                  item_flags,
6947                                                                  error);
6948                         if (ret < 0)
6949                                 return ret;
6950                         /* Count all modify-header actions as one action. */
6951                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6952                                 ++actions_n;
6953                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6954                                 modify_after_mirror = 1;
6955                         action_flags |= actions->type ==
6956                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6957                                                 MLX5_FLOW_ACTION_SET_TTL :
6958                                                 MLX5_FLOW_ACTION_DEC_TTL;
6959                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6960                         break;
6961                 case RTE_FLOW_ACTION_TYPE_JUMP:
6962                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6963                                                            action_flags,
6964                                                            attr, external,
6965                                                            error);
6966                         if (ret)
6967                                 return ret;
6968                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6969                             fdb_mirror_limit)
6970                                 return rte_flow_error_set(error, EINVAL,
6971                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6972                                                   NULL,
6973                                                   "sample and jump action combination is not supported");
6974                         ++actions_n;
6975                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6976                         break;
6977                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6978                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6979                         ret = flow_dv_validate_action_modify_tcp_seq
6980                                                                 (action_flags,
6981                                                                  actions,
6982                                                                  item_flags,
6983                                                                  error);
6984                         if (ret < 0)
6985                                 return ret;
6986                         /* Count all modify-header actions as one action. */
6987                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6988                                 ++actions_n;
6989                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6990                                 modify_after_mirror = 1;
6991                         action_flags |= actions->type ==
6992                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6993                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6994                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6995                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6996                         break;
6997                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6998                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6999                         ret = flow_dv_validate_action_modify_tcp_ack
7000                                                                 (action_flags,
7001                                                                  actions,
7002                                                                  item_flags,
7003                                                                  error);
7004                         if (ret < 0)
7005                                 return ret;
7006                         /* Count all modify-header actions as one action. */
7007                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7008                                 ++actions_n;
7009                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7010                                 modify_after_mirror = 1;
7011                         action_flags |= actions->type ==
7012                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7013                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
7014                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7015                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7016                         break;
7017                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7018                         break;
7019                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7020                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7021                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7022                         break;
7023                 case RTE_FLOW_ACTION_TYPE_METER:
7024                         ret = mlx5_flow_validate_action_meter(dev,
7025                                                               action_flags,
7026                                                               actions, attr,
7027                                                               error);
7028                         if (ret < 0)
7029                                 return ret;
7030                         action_flags |= MLX5_FLOW_ACTION_METER;
7031                         ++actions_n;
7032                         /* Meter action will add one more TAG action. */
7033                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7034                         break;
7035                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7036                         if (!attr->transfer && !attr->group)
7037                                 return rte_flow_error_set(error, ENOTSUP,
7038                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7039                                                                            NULL,
7040                           "Shared ASO age action is not supported for group 0");
7041                         action_flags |= MLX5_FLOW_ACTION_AGE;
7042                         ++actions_n;
7043                         break;
7044                 case RTE_FLOW_ACTION_TYPE_AGE:
7045                         ret = flow_dv_validate_action_age(action_flags,
7046                                                           actions, dev,
7047                                                           error);
7048                         if (ret < 0)
7049                                 return ret;
7050                         /*
7051                          * Validate the regular AGE action (using counter)
7052                          * mutual exclusion with share counter actions.
7053                          */
7054                         if (!priv->sh->flow_hit_aso_en) {
7055                                 if (count && count->shared)
7056                                         return rte_flow_error_set
7057                                                 (error, EINVAL,
7058                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7059                                                 NULL,
7060                                                 "old age and shared count combination is not supported");
7061                                 if (sample_count)
7062                                         return rte_flow_error_set
7063                                                 (error, EINVAL,
7064                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7065                                                 NULL,
7066                                                 "old age action and count must be in the same sub flow");
7067                         }
7068                         action_flags |= MLX5_FLOW_ACTION_AGE;
7069                         ++actions_n;
7070                         break;
7071                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7072                         ret = flow_dv_validate_action_modify_ipv4_dscp
7073                                                          (action_flags,
7074                                                           actions,
7075                                                           item_flags,
7076                                                           error);
7077                         if (ret < 0)
7078                                 return ret;
7079                         /* Count all modify-header actions as one action. */
7080                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7081                                 ++actions_n;
7082                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7083                                 modify_after_mirror = 1;
7084                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7085                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7086                         break;
7087                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7088                         ret = flow_dv_validate_action_modify_ipv6_dscp
7089                                                                 (action_flags,
7090                                                                  actions,
7091                                                                  item_flags,
7092                                                                  error);
7093                         if (ret < 0)
7094                                 return ret;
7095                         /* Count all modify-header actions as one action. */
7096                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7097                                 ++actions_n;
7098                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7099                                 modify_after_mirror = 1;
7100                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7101                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7102                         break;
7103                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7104                         ret = flow_dv_validate_action_sample(&action_flags,
7105                                                              actions, dev,
7106                                                              attr, item_flags,
7107                                                              rss, &sample_rss,
7108                                                              &sample_count,
7109                                                              &fdb_mirror_limit,
7110                                                              error);
7111                         if (ret < 0)
7112                                 return ret;
7113                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7114                         ++actions_n;
7115                         break;
7116                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7117                         if (actions[0].type != (typeof(actions[0].type))
7118                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7119                                 return rte_flow_error_set
7120                                                 (error, EINVAL,
7121                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7122                                                 NULL, "MLX5 private action "
7123                                                 "must be the first");
7124
7125                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7126                         break;
7127                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7128                         ret = flow_dv_validate_action_modify_field(dev,
7129                                                                    action_flags,
7130                                                                    actions,
7131                                                                    attr,
7132                                                                    error);
7133                         if (ret < 0)
7134                                 return ret;
7135                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7136                                 modify_after_mirror = 1;
7137                         /* Count all modify-header actions as one action. */
7138                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7139                                 ++actions_n;
7140                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7141                         rw_act_num += ret;
7142                         break;
7143                 default:
7144                         return rte_flow_error_set(error, ENOTSUP,
7145                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7146                                                   actions,
7147                                                   "action not supported");
7148                 }
7149         }
7150         /*
7151          * Validate actions in flow rules
7152          * - Explicit decap action is prohibited by the tunnel offload API.
7153          * - Drop action in tunnel steer rule is prohibited by the API.
7154          * - Application cannot use MARK action because it's value can mask
7155          *   tunnel default miss nitification.
7156          * - JUMP in tunnel match rule has no support in current PMD
7157          *   implementation.
7158          * - TAG & META are reserved for future uses.
7159          */
7160         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7161                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
7162                                             MLX5_FLOW_ACTION_MARK     |
7163                                             MLX5_FLOW_ACTION_SET_TAG  |
7164                                             MLX5_FLOW_ACTION_SET_META |
7165                                             MLX5_FLOW_ACTION_DROP;
7166
7167                 if (action_flags & bad_actions_mask)
7168                         return rte_flow_error_set
7169                                         (error, EINVAL,
7170                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7171                                         "Invalid RTE action in tunnel "
7172                                         "set decap rule");
7173                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7174                         return rte_flow_error_set
7175                                         (error, EINVAL,
7176                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7177                                         "tunnel set decap rule must terminate "
7178                                         "with JUMP");
7179                 if (!attr->ingress)
7180                         return rte_flow_error_set
7181                                         (error, EINVAL,
7182                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7183                                         "tunnel flows for ingress traffic only");
7184         }
7185         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7186                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7187                                             MLX5_FLOW_ACTION_MARK    |
7188                                             MLX5_FLOW_ACTION_SET_TAG |
7189                                             MLX5_FLOW_ACTION_SET_META;
7190
7191                 if (action_flags & bad_actions_mask)
7192                         return rte_flow_error_set
7193                                         (error, EINVAL,
7194                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7195                                         "Invalid RTE action in tunnel "
7196                                         "set match rule");
7197         }
7198         /*
7199          * Validate the drop action mutual exclusion with other actions.
7200          * Drop action is mutually-exclusive with any other action, except for
7201          * Count action.
7202          * Drop action compatibility with tunnel offload was already validated.
7203          */
7204         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7205                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7206         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7207             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7208                 return rte_flow_error_set(error, EINVAL,
7209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7210                                           "Drop action is mutually-exclusive "
7211                                           "with any other action, except for "
7212                                           "Count action");
7213         /* Eswitch has few restrictions on using items and actions */
7214         if (attr->transfer) {
7215                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7216                     action_flags & MLX5_FLOW_ACTION_FLAG)
7217                         return rte_flow_error_set(error, ENOTSUP,
7218                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7219                                                   NULL,
7220                                                   "unsupported action FLAG");
7221                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7222                     action_flags & MLX5_FLOW_ACTION_MARK)
7223                         return rte_flow_error_set(error, ENOTSUP,
7224                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7225                                                   NULL,
7226                                                   "unsupported action MARK");
7227                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7228                         return rte_flow_error_set(error, ENOTSUP,
7229                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7230                                                   NULL,
7231                                                   "unsupported action QUEUE");
7232                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7233                         return rte_flow_error_set(error, ENOTSUP,
7234                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7235                                                   NULL,
7236                                                   "unsupported action RSS");
7237                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7238                         return rte_flow_error_set(error, EINVAL,
7239                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7240                                                   actions,
7241                                                   "no fate action is found");
7242         } else {
7243                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7244                         return rte_flow_error_set(error, EINVAL,
7245                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7246                                                   actions,
7247                                                   "no fate action is found");
7248         }
7249         /*
7250          * Continue validation for Xcap and VLAN actions.
7251          * If hairpin is working in explicit TX rule mode, there is no actions
7252          * splitting and the validation of hairpin ingress flow should be the
7253          * same as other standard flows.
7254          */
7255         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7256                              MLX5_FLOW_VLAN_ACTIONS)) &&
7257             (queue_index == 0xFFFF ||
7258              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7259              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7260              conf->tx_explicit != 0))) {
7261                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7262                     MLX5_FLOW_XCAP_ACTIONS)
7263                         return rte_flow_error_set(error, ENOTSUP,
7264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7265                                                   NULL, "encap and decap "
7266                                                   "combination aren't supported");
7267                 if (!attr->transfer && attr->ingress) {
7268                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7269                                 return rte_flow_error_set
7270                                                 (error, ENOTSUP,
7271                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7272                                                  NULL, "encap is not supported"
7273                                                  " for ingress traffic");
7274                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7275                                 return rte_flow_error_set
7276                                                 (error, ENOTSUP,
7277                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7278                                                  NULL, "push VLAN action not "
7279                                                  "supported for ingress");
7280                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7281                                         MLX5_FLOW_VLAN_ACTIONS)
7282                                 return rte_flow_error_set
7283                                                 (error, ENOTSUP,
7284                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7285                                                  NULL, "no support for "
7286                                                  "multiple VLAN actions");
7287                 }
7288         }
7289         /*
7290          * Hairpin flow will add one more TAG action in TX implicit mode.
7291          * In TX explicit mode, there will be no hairpin flow ID.
7292          */
7293         if (hairpin > 0)
7294                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7295         /* extra metadata enabled: one more TAG action will be add. */
7296         if (dev_conf->dv_flow_en &&
7297             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7298             mlx5_flow_ext_mreg_supported(dev))
7299                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7300         if (rw_act_num >
7301                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7302                 return rte_flow_error_set(error, ENOTSUP,
7303                                           RTE_FLOW_ERROR_TYPE_ACTION,
7304                                           NULL, "too many header modify"
7305                                           " actions to support");
7306         }
7307         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7308         if (fdb_mirror_limit && modify_after_mirror)
7309                 return rte_flow_error_set(error, EINVAL,
7310                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7311                                 "sample before modify action is not supported");
7312         return 0;
7313 }
7314
7315 /**
7316  * Internal preparation function. Allocates the DV flow size,
7317  * this size is constant.
7318  *
7319  * @param[in] dev
7320  *   Pointer to the rte_eth_dev structure.
7321  * @param[in] attr
7322  *   Pointer to the flow attributes.
7323  * @param[in] items
7324  *   Pointer to the list of items.
7325  * @param[in] actions
7326  *   Pointer to the list of actions.
7327  * @param[out] error
7328  *   Pointer to the error structure.
7329  *
7330  * @return
7331  *   Pointer to mlx5_flow object on success,
7332  *   otherwise NULL and rte_errno is set.
7333  */
7334 static struct mlx5_flow *
7335 flow_dv_prepare(struct rte_eth_dev *dev,
7336                 const struct rte_flow_attr *attr __rte_unused,
7337                 const struct rte_flow_item items[] __rte_unused,
7338                 const struct rte_flow_action actions[] __rte_unused,
7339                 struct rte_flow_error *error)
7340 {
7341         uint32_t handle_idx = 0;
7342         struct mlx5_flow *dev_flow;
7343         struct mlx5_flow_handle *dev_handle;
7344         struct mlx5_priv *priv = dev->data->dev_private;
7345         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7346
7347         MLX5_ASSERT(wks);
7348         /* In case of corrupting the memory. */
7349         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7350                 rte_flow_error_set(error, ENOSPC,
7351                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7352                                    "not free temporary device flow");
7353                 return NULL;
7354         }
7355         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7356                                    &handle_idx);
7357         if (!dev_handle) {
7358                 rte_flow_error_set(error, ENOMEM,
7359                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7360                                    "not enough memory to create flow handle");
7361                 return NULL;
7362         }
7363         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7364         dev_flow = &wks->flows[wks->flow_idx++];
7365         memset(dev_flow, 0, sizeof(*dev_flow));
7366         dev_flow->handle = dev_handle;
7367         dev_flow->handle_idx = handle_idx;
7368         /*
7369          * In some old rdma-core releases, before continuing, a check of the
7370          * length of matching parameter will be done at first. It needs to use
7371          * the length without misc4 param. If the flow has misc4 support, then
7372          * the length needs to be adjusted accordingly. Each param member is
7373          * aligned with a 64B boundary naturally.
7374          */
7375         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7376                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7377         dev_flow->ingress = attr->ingress;
7378         dev_flow->dv.transfer = attr->transfer;
7379         return dev_flow;
7380 }
7381
7382 #ifdef RTE_LIBRTE_MLX5_DEBUG
7383 /**
7384  * Sanity check for match mask and value. Similar to check_valid_spec() in
7385  * kernel driver. If unmasked bit is present in value, it returns failure.
7386  *
7387  * @param match_mask
7388  *   pointer to match mask buffer.
7389  * @param match_value
7390  *   pointer to match value buffer.
7391  *
7392  * @return
7393  *   0 if valid, -EINVAL otherwise.
7394  */
7395 static int
7396 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7397 {
7398         uint8_t *m = match_mask;
7399         uint8_t *v = match_value;
7400         unsigned int i;
7401
7402         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7403                 if (v[i] & ~m[i]) {
7404                         DRV_LOG(ERR,
7405                                 "match_value differs from match_criteria"
7406                                 " %p[%u] != %p[%u]",
7407                                 match_value, i, match_mask, i);
7408                         return -EINVAL;
7409                 }
7410         }
7411         return 0;
7412 }
7413 #endif
7414
7415 /**
7416  * Add match of ip_version.
7417  *
7418  * @param[in] group
7419  *   Flow group.
7420  * @param[in] headers_v
7421  *   Values header pointer.
7422  * @param[in] headers_m
7423  *   Masks header pointer.
7424  * @param[in] ip_version
7425  *   The IP version to set.
7426  */
7427 static inline void
7428 flow_dv_set_match_ip_version(uint32_t group,
7429                              void *headers_v,
7430                              void *headers_m,
7431                              uint8_t ip_version)
7432 {
7433         if (group == 0)
7434                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7435         else
7436                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7437                          ip_version);
7438         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7439         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7440         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7441 }
7442
7443 /**
7444  * Add Ethernet item to matcher and to the value.
7445  *
7446  * @param[in, out] matcher
7447  *   Flow matcher.
7448  * @param[in, out] key
7449  *   Flow matcher value.
7450  * @param[in] item
7451  *   Flow pattern to translate.
7452  * @param[in] inner
7453  *   Item is inner pattern.
7454  */
7455 static void
7456 flow_dv_translate_item_eth(void *matcher, void *key,
7457                            const struct rte_flow_item *item, int inner,
7458                            uint32_t group)
7459 {
7460         const struct rte_flow_item_eth *eth_m = item->mask;
7461         const struct rte_flow_item_eth *eth_v = item->spec;
7462         const struct rte_flow_item_eth nic_mask = {
7463                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7464                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7465                 .type = RTE_BE16(0xffff),
7466                 .has_vlan = 0,
7467         };
7468         void *hdrs_m;
7469         void *hdrs_v;
7470         char *l24_v;
7471         unsigned int i;
7472
7473         if (!eth_v)
7474                 return;
7475         if (!eth_m)
7476                 eth_m = &nic_mask;
7477         if (inner) {
7478                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7479                                          inner_headers);
7480                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7481         } else {
7482                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7483                                          outer_headers);
7484                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7485         }
7486         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7487                &eth_m->dst, sizeof(eth_m->dst));
7488         /* The value must be in the range of the mask. */
7489         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7490         for (i = 0; i < sizeof(eth_m->dst); ++i)
7491                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7492         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7493                &eth_m->src, sizeof(eth_m->src));
7494         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7495         /* The value must be in the range of the mask. */
7496         for (i = 0; i < sizeof(eth_m->dst); ++i)
7497                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7498         /*
7499          * HW supports match on one Ethertype, the Ethertype following the last
7500          * VLAN tag of the packet (see PRM).
7501          * Set match on ethertype only if ETH header is not followed by VLAN.
7502          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7503          * ethertype, and use ip_version field instead.
7504          * eCPRI over Ether layer will use type value 0xAEFE.
7505          */
7506         if (eth_m->type == 0xFFFF) {
7507                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7508                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7509                 switch (eth_v->type) {
7510                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7511                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7512                         return;
7513                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7514                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7515                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7516                         return;
7517                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7518                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7519                         return;
7520                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7521                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7522                         return;
7523                 default:
7524                         break;
7525                 }
7526         }
7527         if (eth_m->has_vlan) {
7528                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7529                 if (eth_v->has_vlan) {
7530                         /*
7531                          * Here, when also has_more_vlan field in VLAN item is
7532                          * not set, only single-tagged packets will be matched.
7533                          */
7534                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7535                         return;
7536                 }
7537         }
7538         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7539                  rte_be_to_cpu_16(eth_m->type));
7540         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7541         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7542 }
7543
7544 /**
7545  * Add VLAN item to matcher and to the value.
7546  *
7547  * @param[in, out] dev_flow
7548  *   Flow descriptor.
7549  * @param[in, out] matcher
7550  *   Flow matcher.
7551  * @param[in, out] key
7552  *   Flow matcher value.
7553  * @param[in] item
7554  *   Flow pattern to translate.
7555  * @param[in] inner
7556  *   Item is inner pattern.
7557  */
7558 static void
7559 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7560                             void *matcher, void *key,
7561                             const struct rte_flow_item *item,
7562                             int inner, uint32_t group)
7563 {
7564         const struct rte_flow_item_vlan *vlan_m = item->mask;
7565         const struct rte_flow_item_vlan *vlan_v = item->spec;
7566         void *hdrs_m;
7567         void *hdrs_v;
7568         uint16_t tci_m;
7569         uint16_t tci_v;
7570
7571         if (inner) {
7572                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7573                                          inner_headers);
7574                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7575         } else {
7576                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7577                                          outer_headers);
7578                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7579                 /*
7580                  * This is workaround, masks are not supported,
7581                  * and pre-validated.
7582                  */
7583                 if (vlan_v)
7584                         dev_flow->handle->vf_vlan.tag =
7585                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7586         }
7587         /*
7588          * When VLAN item exists in flow, mark packet as tagged,
7589          * even if TCI is not specified.
7590          */
7591         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7592                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7593                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7594         }
7595         if (!vlan_v)
7596                 return;
7597         if (!vlan_m)
7598                 vlan_m = &rte_flow_item_vlan_mask;
7599         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7600         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7601         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7602         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7603         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7604         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7605         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7606         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7607         /*
7608          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7609          * ethertype, and use ip_version field instead.
7610          */
7611         if (vlan_m->inner_type == 0xFFFF) {
7612                 switch (vlan_v->inner_type) {
7613                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7614                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7615                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7616                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7617                         return;
7618                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7619                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7620                         return;
7621                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7622                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7623                         return;
7624                 default:
7625                         break;
7626                 }
7627         }
7628         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7629                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7630                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7631                 /* Only one vlan_tag bit can be set. */
7632                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7633                 return;
7634         }
7635         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7636                  rte_be_to_cpu_16(vlan_m->inner_type));
7637         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7638                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7639 }
7640
7641 /**
7642  * Add IPV4 item to matcher and to the value.
7643  *
7644  * @param[in, out] matcher
7645  *   Flow matcher.
7646  * @param[in, out] key
7647  *   Flow matcher value.
7648  * @param[in] item
7649  *   Flow pattern to translate.
7650  * @param[in] inner
7651  *   Item is inner pattern.
7652  * @param[in] group
7653  *   The group to insert the rule.
7654  */
7655 static void
7656 flow_dv_translate_item_ipv4(void *matcher, void *key,
7657                             const struct rte_flow_item *item,
7658                             int inner, uint32_t group)
7659 {
7660         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7661         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7662         const struct rte_flow_item_ipv4 nic_mask = {
7663                 .hdr = {
7664                         .src_addr = RTE_BE32(0xffffffff),
7665                         .dst_addr = RTE_BE32(0xffffffff),
7666                         .type_of_service = 0xff,
7667                         .next_proto_id = 0xff,
7668                         .time_to_live = 0xff,
7669                 },
7670         };
7671         void *headers_m;
7672         void *headers_v;
7673         char *l24_m;
7674         char *l24_v;
7675         uint8_t tos;
7676
7677         if (inner) {
7678                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7679                                          inner_headers);
7680                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7681         } else {
7682                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7683                                          outer_headers);
7684                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7685         }
7686         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7687         if (!ipv4_v)
7688                 return;
7689         if (!ipv4_m)
7690                 ipv4_m = &nic_mask;
7691         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7692                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7693         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7694                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7695         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7696         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7697         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7698                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7699         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7700                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7701         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7702         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7703         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7704         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7705                  ipv4_m->hdr.type_of_service);
7706         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7707         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7708                  ipv4_m->hdr.type_of_service >> 2);
7709         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7710         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7711                  ipv4_m->hdr.next_proto_id);
7712         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7713                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7714         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7715                  ipv4_m->hdr.time_to_live);
7716         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7717                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7718         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7719                  !!(ipv4_m->hdr.fragment_offset));
7720         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7721                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7722 }
7723
7724 /**
7725  * Add IPV6 item to matcher and to the value.
7726  *
7727  * @param[in, out] matcher
7728  *   Flow matcher.
7729  * @param[in, out] key
7730  *   Flow matcher value.
7731  * @param[in] item
7732  *   Flow pattern to translate.
7733  * @param[in] inner
7734  *   Item is inner pattern.
7735  * @param[in] group
7736  *   The group to insert the rule.
7737  */
7738 static void
7739 flow_dv_translate_item_ipv6(void *matcher, void *key,
7740                             const struct rte_flow_item *item,
7741                             int inner, uint32_t group)
7742 {
7743         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7744         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7745         const struct rte_flow_item_ipv6 nic_mask = {
7746                 .hdr = {
7747                         .src_addr =
7748                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7749                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7750                         .dst_addr =
7751                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7752                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7753                         .vtc_flow = RTE_BE32(0xffffffff),
7754                         .proto = 0xff,
7755                         .hop_limits = 0xff,
7756                 },
7757         };
7758         void *headers_m;
7759         void *headers_v;
7760         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7761         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7762         char *l24_m;
7763         char *l24_v;
7764         uint32_t vtc_m;
7765         uint32_t vtc_v;
7766         int i;
7767         int size;
7768
7769         if (inner) {
7770                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7771                                          inner_headers);
7772                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7773         } else {
7774                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7775                                          outer_headers);
7776                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7777         }
7778         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7779         if (!ipv6_v)
7780                 return;
7781         if (!ipv6_m)
7782                 ipv6_m = &nic_mask;
7783         size = sizeof(ipv6_m->hdr.dst_addr);
7784         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7785                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7786         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7787                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7788         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7789         for (i = 0; i < size; ++i)
7790                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7791         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7792                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7793         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7794                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7795         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7796         for (i = 0; i < size; ++i)
7797                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7798         /* TOS. */
7799         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7800         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7801         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7802         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7803         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7804         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7805         /* Label. */
7806         if (inner) {
7807                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7808                          vtc_m);
7809                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7810                          vtc_v);
7811         } else {
7812                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7813                          vtc_m);
7814                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7815                          vtc_v);
7816         }
7817         /* Protocol. */
7818         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7819                  ipv6_m->hdr.proto);
7820         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7821                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7822         /* Hop limit. */
7823         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7824                  ipv6_m->hdr.hop_limits);
7825         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7826                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7827         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7828                  !!(ipv6_m->has_frag_ext));
7829         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7830                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7831 }
7832
7833 /**
7834  * Add IPV6 fragment extension item to matcher and to the value.
7835  *
7836  * @param[in, out] matcher
7837  *   Flow matcher.
7838  * @param[in, out] key
7839  *   Flow matcher value.
7840  * @param[in] item
7841  *   Flow pattern to translate.
7842  * @param[in] inner
7843  *   Item is inner pattern.
7844  */
7845 static void
7846 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7847                                      const struct rte_flow_item *item,
7848                                      int inner)
7849 {
7850         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7851         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7852         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7853                 .hdr = {
7854                         .next_header = 0xff,
7855                         .frag_data = RTE_BE16(0xffff),
7856                 },
7857         };
7858         void *headers_m;
7859         void *headers_v;
7860
7861         if (inner) {
7862                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7863                                          inner_headers);
7864                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7865         } else {
7866                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7867                                          outer_headers);
7868                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7869         }
7870         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7871         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7872         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7873         if (!ipv6_frag_ext_v)
7874                 return;
7875         if (!ipv6_frag_ext_m)
7876                 ipv6_frag_ext_m = &nic_mask;
7877         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7878                  ipv6_frag_ext_m->hdr.next_header);
7879         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7880                  ipv6_frag_ext_v->hdr.next_header &
7881                  ipv6_frag_ext_m->hdr.next_header);
7882 }
7883
7884 /**
7885  * Add TCP item to matcher and to the value.
7886  *
7887  * @param[in, out] matcher
7888  *   Flow matcher.
7889  * @param[in, out] key
7890  *   Flow matcher value.
7891  * @param[in] item
7892  *   Flow pattern to translate.
7893  * @param[in] inner
7894  *   Item is inner pattern.
7895  */
7896 static void
7897 flow_dv_translate_item_tcp(void *matcher, void *key,
7898                            const struct rte_flow_item *item,
7899                            int inner)
7900 {
7901         const struct rte_flow_item_tcp *tcp_m = item->mask;
7902         const struct rte_flow_item_tcp *tcp_v = item->spec;
7903         void *headers_m;
7904         void *headers_v;
7905
7906         if (inner) {
7907                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7908                                          inner_headers);
7909                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7910         } else {
7911                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7912                                          outer_headers);
7913                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7914         }
7915         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7916         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7917         if (!tcp_v)
7918                 return;
7919         if (!tcp_m)
7920                 tcp_m = &rte_flow_item_tcp_mask;
7921         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7922                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7923         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7924                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7925         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7926                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7927         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7928                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7929         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7930                  tcp_m->hdr.tcp_flags);
7931         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7932                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7933 }
7934
7935 /**
7936  * Add UDP item to matcher and to the value.
7937  *
7938  * @param[in, out] matcher
7939  *   Flow matcher.
7940  * @param[in, out] key
7941  *   Flow matcher value.
7942  * @param[in] item
7943  *   Flow pattern to translate.
7944  * @param[in] inner
7945  *   Item is inner pattern.
7946  */
7947 static void
7948 flow_dv_translate_item_udp(void *matcher, void *key,
7949                            const struct rte_flow_item *item,
7950                            int inner)
7951 {
7952         const struct rte_flow_item_udp *udp_m = item->mask;
7953         const struct rte_flow_item_udp *udp_v = item->spec;
7954         void *headers_m;
7955         void *headers_v;
7956
7957         if (inner) {
7958                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7959                                          inner_headers);
7960                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7961         } else {
7962                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7963                                          outer_headers);
7964                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7965         }
7966         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7967         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7968         if (!udp_v)
7969                 return;
7970         if (!udp_m)
7971                 udp_m = &rte_flow_item_udp_mask;
7972         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7973                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7974         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7975                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7976         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7977                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7978         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7979                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7980 }
7981
7982 /**
7983  * Add GRE optional Key item to matcher and to the value.
7984  *
7985  * @param[in, out] matcher
7986  *   Flow matcher.
7987  * @param[in, out] key
7988  *   Flow matcher value.
7989  * @param[in] item
7990  *   Flow pattern to translate.
7991  * @param[in] inner
7992  *   Item is inner pattern.
7993  */
7994 static void
7995 flow_dv_translate_item_gre_key(void *matcher, void *key,
7996                                    const struct rte_flow_item *item)
7997 {
7998         const rte_be32_t *key_m = item->mask;
7999         const rte_be32_t *key_v = item->spec;
8000         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8001         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8002         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8003
8004         /* GRE K bit must be on and should already be validated */
8005         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8006         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8007         if (!key_v)
8008                 return;
8009         if (!key_m)
8010                 key_m = &gre_key_default_mask;
8011         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8012                  rte_be_to_cpu_32(*key_m) >> 8);
8013         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8014                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8015         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8016                  rte_be_to_cpu_32(*key_m) & 0xFF);
8017         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8018                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8019 }
8020
8021 /**
8022  * Add GRE item to matcher and to the value.
8023  *
8024  * @param[in, out] matcher
8025  *   Flow matcher.
8026  * @param[in, out] key
8027  *   Flow matcher value.
8028  * @param[in] item
8029  *   Flow pattern to translate.
8030  * @param[in] inner
8031  *   Item is inner pattern.
8032  */
8033 static void
8034 flow_dv_translate_item_gre(void *matcher, void *key,
8035                            const struct rte_flow_item *item,
8036                            int inner)
8037 {
8038         const struct rte_flow_item_gre *gre_m = item->mask;
8039         const struct rte_flow_item_gre *gre_v = item->spec;
8040         void *headers_m;
8041         void *headers_v;
8042         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8043         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8044         struct {
8045                 union {
8046                         __extension__
8047                         struct {
8048                                 uint16_t version:3;
8049                                 uint16_t rsvd0:9;
8050                                 uint16_t s_present:1;
8051                                 uint16_t k_present:1;
8052                                 uint16_t rsvd_bit1:1;
8053                                 uint16_t c_present:1;
8054                         };
8055                         uint16_t value;
8056                 };
8057         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8058
8059         if (inner) {
8060                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8061                                          inner_headers);
8062                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8063         } else {
8064                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8065                                          outer_headers);
8066                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8067         }
8068         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8069         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8070         if (!gre_v)
8071                 return;
8072         if (!gre_m)
8073                 gre_m = &rte_flow_item_gre_mask;
8074         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8075                  rte_be_to_cpu_16(gre_m->protocol));
8076         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8077                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8078         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8079         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8080         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8081                  gre_crks_rsvd0_ver_m.c_present);
8082         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8083                  gre_crks_rsvd0_ver_v.c_present &
8084                  gre_crks_rsvd0_ver_m.c_present);
8085         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8086                  gre_crks_rsvd0_ver_m.k_present);
8087         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8088                  gre_crks_rsvd0_ver_v.k_present &
8089                  gre_crks_rsvd0_ver_m.k_present);
8090         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8091                  gre_crks_rsvd0_ver_m.s_present);
8092         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8093                  gre_crks_rsvd0_ver_v.s_present &
8094                  gre_crks_rsvd0_ver_m.s_present);
8095 }
8096
8097 /**
8098  * Add NVGRE item to matcher and to the value.
8099  *
8100  * @param[in, out] matcher
8101  *   Flow matcher.
8102  * @param[in, out] key
8103  *   Flow matcher value.
8104  * @param[in] item
8105  *   Flow pattern to translate.
8106  * @param[in] inner
8107  *   Item is inner pattern.
8108  */
8109 static void
8110 flow_dv_translate_item_nvgre(void *matcher, void *key,
8111                              const struct rte_flow_item *item,
8112                              int inner)
8113 {
8114         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8115         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8116         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8117         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8118         const char *tni_flow_id_m;
8119         const char *tni_flow_id_v;
8120         char *gre_key_m;
8121         char *gre_key_v;
8122         int size;
8123         int i;
8124
8125         /* For NVGRE, GRE header fields must be set with defined values. */
8126         const struct rte_flow_item_gre gre_spec = {
8127                 .c_rsvd0_ver = RTE_BE16(0x2000),
8128                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8129         };
8130         const struct rte_flow_item_gre gre_mask = {
8131                 .c_rsvd0_ver = RTE_BE16(0xB000),
8132                 .protocol = RTE_BE16(UINT16_MAX),
8133         };
8134         const struct rte_flow_item gre_item = {
8135                 .spec = &gre_spec,
8136                 .mask = &gre_mask,
8137                 .last = NULL,
8138         };
8139         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8140         if (!nvgre_v)
8141                 return;
8142         if (!nvgre_m)
8143                 nvgre_m = &rte_flow_item_nvgre_mask;
8144         tni_flow_id_m = (const char *)nvgre_m->tni;
8145         tni_flow_id_v = (const char *)nvgre_v->tni;
8146         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8147         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8148         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8149         memcpy(gre_key_m, tni_flow_id_m, size);
8150         for (i = 0; i < size; ++i)
8151                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8152 }
8153
8154 /**
8155  * Add VXLAN item to matcher and to the value.
8156  *
8157  * @param[in, out] matcher
8158  *   Flow matcher.
8159  * @param[in, out] key
8160  *   Flow matcher value.
8161  * @param[in] item
8162  *   Flow pattern to translate.
8163  * @param[in] inner
8164  *   Item is inner pattern.
8165  */
8166 static void
8167 flow_dv_translate_item_vxlan(void *matcher, void *key,
8168                              const struct rte_flow_item *item,
8169                              int inner)
8170 {
8171         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8172         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8173         void *headers_m;
8174         void *headers_v;
8175         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8176         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8177         char *vni_m;
8178         char *vni_v;
8179         uint16_t dport;
8180         int size;
8181         int i;
8182
8183         if (inner) {
8184                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8185                                          inner_headers);
8186                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8187         } else {
8188                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8189                                          outer_headers);
8190                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8191         }
8192         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8193                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8194         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8195                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8196                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8197         }
8198         if (!vxlan_v)
8199                 return;
8200         if (!vxlan_m)
8201                 vxlan_m = &rte_flow_item_vxlan_mask;
8202         size = sizeof(vxlan_m->vni);
8203         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8204         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8205         memcpy(vni_m, vxlan_m->vni, size);
8206         for (i = 0; i < size; ++i)
8207                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8208 }
8209
8210 /**
8211  * Add VXLAN-GPE item to matcher and to the value.
8212  *
8213  * @param[in, out] matcher
8214  *   Flow matcher.
8215  * @param[in, out] key
8216  *   Flow matcher value.
8217  * @param[in] item
8218  *   Flow pattern to translate.
8219  * @param[in] inner
8220  *   Item is inner pattern.
8221  */
8222
8223 static void
8224 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8225                                  const struct rte_flow_item *item, int inner)
8226 {
8227         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8228         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8229         void *headers_m;
8230         void *headers_v;
8231         void *misc_m =
8232                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8233         void *misc_v =
8234                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8235         char *vni_m;
8236         char *vni_v;
8237         uint16_t dport;
8238         int size;
8239         int i;
8240         uint8_t flags_m = 0xff;
8241         uint8_t flags_v = 0xc;
8242
8243         if (inner) {
8244                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8245                                          inner_headers);
8246                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8247         } else {
8248                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8249                                          outer_headers);
8250                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8251         }
8252         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8253                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8254         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8255                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8257         }
8258         if (!vxlan_v)
8259                 return;
8260         if (!vxlan_m)
8261                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8262         size = sizeof(vxlan_m->vni);
8263         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8264         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8265         memcpy(vni_m, vxlan_m->vni, size);
8266         for (i = 0; i < size; ++i)
8267                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8268         if (vxlan_m->flags) {
8269                 flags_m = vxlan_m->flags;
8270                 flags_v = vxlan_v->flags;
8271         }
8272         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8273         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8274         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8275                  vxlan_m->protocol);
8276         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8277                  vxlan_v->protocol);
8278 }
8279
8280 /**
8281  * Add Geneve item to matcher and to the value.
8282  *
8283  * @param[in, out] matcher
8284  *   Flow matcher.
8285  * @param[in, out] key
8286  *   Flow matcher value.
8287  * @param[in] item
8288  *   Flow pattern to translate.
8289  * @param[in] inner
8290  *   Item is inner pattern.
8291  */
8292
8293 static void
8294 flow_dv_translate_item_geneve(void *matcher, void *key,
8295                               const struct rte_flow_item *item, int inner)
8296 {
8297         const struct rte_flow_item_geneve *geneve_m = item->mask;
8298         const struct rte_flow_item_geneve *geneve_v = item->spec;
8299         void *headers_m;
8300         void *headers_v;
8301         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8302         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8303         uint16_t dport;
8304         uint16_t gbhdr_m;
8305         uint16_t gbhdr_v;
8306         char *vni_m;
8307         char *vni_v;
8308         size_t size, i;
8309
8310         if (inner) {
8311                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8312                                          inner_headers);
8313                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8314         } else {
8315                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8316                                          outer_headers);
8317                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8318         }
8319         dport = MLX5_UDP_PORT_GENEVE;
8320         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8321                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8322                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8323         }
8324         if (!geneve_v)
8325                 return;
8326         if (!geneve_m)
8327                 geneve_m = &rte_flow_item_geneve_mask;
8328         size = sizeof(geneve_m->vni);
8329         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8330         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8331         memcpy(vni_m, geneve_m->vni, size);
8332         for (i = 0; i < size; ++i)
8333                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8334         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8335                  rte_be_to_cpu_16(geneve_m->protocol));
8336         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8337                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8338         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8339         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8340         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8341                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8342         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8343                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8344         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8345                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8346         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8347                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8348                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8349 }
8350
8351 /**
8352  * Create Geneve TLV option resource.
8353  *
8354  * @param dev[in, out]
8355  *   Pointer to rte_eth_dev structure.
8356  * @param[in, out] tag_be24
8357  *   Tag value in big endian then R-shift 8.
8358  * @parm[in, out] dev_flow
8359  *   Pointer to the dev_flow.
8360  * @param[out] error
8361  *   pointer to error structure.
8362  *
8363  * @return
8364  *   0 on success otherwise -errno and errno is set.
8365  */
8366
8367 int
8368 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8369                                              const struct rte_flow_item *item,
8370                                              struct rte_flow_error *error)
8371 {
8372         struct mlx5_priv *priv = dev->data->dev_private;
8373         struct mlx5_dev_ctx_shared *sh = priv->sh;
8374         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8375                         sh->geneve_tlv_option_resource;
8376         struct mlx5_devx_obj *obj;
8377         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8378         int ret = 0;
8379
8380         if (!geneve_opt_v)
8381                 return -1;
8382         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8383         if (geneve_opt_resource != NULL) {
8384                 if (geneve_opt_resource->option_class ==
8385                         geneve_opt_v->option_class &&
8386                         geneve_opt_resource->option_type ==
8387                         geneve_opt_v->option_type &&
8388                         geneve_opt_resource->length ==
8389                         geneve_opt_v->option_len) {
8390                         /* We already have GENVE TLV option obj allocated. */
8391                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8392                                            __ATOMIC_RELAXED);
8393                 } else {
8394                         ret = rte_flow_error_set(error, ENOMEM,
8395                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8396                                 "Only one GENEVE TLV option supported");
8397                         goto exit;
8398                 }
8399         } else {
8400                 /* Create a GENEVE TLV object and resource. */
8401                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8402                                 geneve_opt_v->option_class,
8403                                 geneve_opt_v->option_type,
8404                                 geneve_opt_v->option_len);
8405                 if (!obj) {
8406                         ret = rte_flow_error_set(error, ENODATA,
8407                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8408                                 "Failed to create GENEVE TLV Devx object");
8409                         goto exit;
8410                 }
8411                 sh->geneve_tlv_option_resource =
8412                                 mlx5_malloc(MLX5_MEM_ZERO,
8413                                                 sizeof(*geneve_opt_resource),
8414                                                 0, SOCKET_ID_ANY);
8415                 if (!sh->geneve_tlv_option_resource) {
8416                         claim_zero(mlx5_devx_cmd_destroy(obj));
8417                         ret = rte_flow_error_set(error, ENOMEM,
8418                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8419                                 "GENEVE TLV object memory allocation failed");
8420                         goto exit;
8421                 }
8422                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8423                 geneve_opt_resource->obj = obj;
8424                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8425                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8426                 geneve_opt_resource->length = geneve_opt_v->option_len;
8427                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8428                                 __ATOMIC_RELAXED);
8429         }
8430 exit:
8431         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8432         return ret;
8433 }
8434
8435 /**
8436  * Add Geneve TLV option item to matcher.
8437  *
8438  * @param[in, out] dev
8439  *   Pointer to rte_eth_dev structure.
8440  * @param[in, out] matcher
8441  *   Flow matcher.
8442  * @param[in, out] key
8443  *   Flow matcher value.
8444  * @param[in] item
8445  *   Flow pattern to translate.
8446  * @param[out] error
8447  *   Pointer to error structure.
8448  */
8449 static int
8450 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8451                                   void *key, const struct rte_flow_item *item,
8452                                   struct rte_flow_error *error)
8453 {
8454         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8455         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8456         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8457         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8458         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8459                         misc_parameters_3);
8460         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8461         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8462         int ret = 0;
8463
8464         if (!geneve_opt_v)
8465                 return -1;
8466         if (!geneve_opt_m)
8467                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8468         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8469                                                            error);
8470         if (ret) {
8471                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8472                 return ret;
8473         }
8474         /*
8475          * Set the option length in GENEVE header if not requested.
8476          * The GENEVE TLV option length is expressed by the option length field
8477          * in the GENEVE header.
8478          * If the option length was not requested but the GENEVE TLV option item
8479          * is present we set the option length field implicitly.
8480          */
8481         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8482                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8483                          MLX5_GENEVE_OPTLEN_MASK);
8484                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8485                          geneve_opt_v->option_len + 1);
8486         }
8487         /* Set the data. */
8488         if (geneve_opt_v->data) {
8489                 memcpy(&opt_data_key, geneve_opt_v->data,
8490                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8491                                 sizeof(opt_data_key)));
8492                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8493                                 sizeof(opt_data_key));
8494                 memcpy(&opt_data_mask, geneve_opt_m->data,
8495                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8496                                 sizeof(opt_data_mask)));
8497                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8498                                 sizeof(opt_data_mask));
8499                 MLX5_SET(fte_match_set_misc3, misc3_m,
8500                                 geneve_tlv_option_0_data,
8501                                 rte_be_to_cpu_32(opt_data_mask));
8502                 MLX5_SET(fte_match_set_misc3, misc3_v,
8503                                 geneve_tlv_option_0_data,
8504                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8505         }
8506         return ret;
8507 }
8508
8509 /**
8510  * Add MPLS item to matcher and to the value.
8511  *
8512  * @param[in, out] matcher
8513  *   Flow matcher.
8514  * @param[in, out] key
8515  *   Flow matcher value.
8516  * @param[in] item
8517  *   Flow pattern to translate.
8518  * @param[in] prev_layer
8519  *   The protocol layer indicated in previous item.
8520  * @param[in] inner
8521  *   Item is inner pattern.
8522  */
8523 static void
8524 flow_dv_translate_item_mpls(void *matcher, void *key,
8525                             const struct rte_flow_item *item,
8526                             uint64_t prev_layer,
8527                             int inner)
8528 {
8529         const uint32_t *in_mpls_m = item->mask;
8530         const uint32_t *in_mpls_v = item->spec;
8531         uint32_t *out_mpls_m = 0;
8532         uint32_t *out_mpls_v = 0;
8533         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8534         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8535         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8536                                      misc_parameters_2);
8537         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8538         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8539         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8540
8541         switch (prev_layer) {
8542         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8543                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8544                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8545                          MLX5_UDP_PORT_MPLS);
8546                 break;
8547         case MLX5_FLOW_LAYER_GRE:
8548                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8549                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8550                          RTE_ETHER_TYPE_MPLS);
8551                 break;
8552         default:
8553                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8554                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8555                          IPPROTO_MPLS);
8556                 break;
8557         }
8558         if (!in_mpls_v)
8559                 return;
8560         if (!in_mpls_m)
8561                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8562         switch (prev_layer) {
8563         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8564                 out_mpls_m =
8565                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8566                                                  outer_first_mpls_over_udp);
8567                 out_mpls_v =
8568                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8569                                                  outer_first_mpls_over_udp);
8570                 break;
8571         case MLX5_FLOW_LAYER_GRE:
8572                 out_mpls_m =
8573                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8574                                                  outer_first_mpls_over_gre);
8575                 out_mpls_v =
8576                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8577                                                  outer_first_mpls_over_gre);
8578                 break;
8579         default:
8580                 /* Inner MPLS not over GRE is not supported. */
8581                 if (!inner) {
8582                         out_mpls_m =
8583                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8584                                                          misc2_m,
8585                                                          outer_first_mpls);
8586                         out_mpls_v =
8587                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8588                                                          misc2_v,
8589                                                          outer_first_mpls);
8590                 }
8591                 break;
8592         }
8593         if (out_mpls_m && out_mpls_v) {
8594                 *out_mpls_m = *in_mpls_m;
8595                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8596         }
8597 }
8598
8599 /**
8600  * Add metadata register item to matcher
8601  *
8602  * @param[in, out] matcher
8603  *   Flow matcher.
8604  * @param[in, out] key
8605  *   Flow matcher value.
8606  * @param[in] reg_type
8607  *   Type of device metadata register
8608  * @param[in] value
8609  *   Register value
8610  * @param[in] mask
8611  *   Register mask
8612  */
8613 static void
8614 flow_dv_match_meta_reg(void *matcher, void *key,
8615                        enum modify_reg reg_type,
8616                        uint32_t data, uint32_t mask)
8617 {
8618         void *misc2_m =
8619                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8620         void *misc2_v =
8621                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8622         uint32_t temp;
8623
8624         data &= mask;
8625         switch (reg_type) {
8626         case REG_A:
8627                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8628                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8629                 break;
8630         case REG_B:
8631                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8632                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8633                 break;
8634         case REG_C_0:
8635                 /*
8636                  * The metadata register C0 field might be divided into
8637                  * source vport index and META item value, we should set
8638                  * this field according to specified mask, not as whole one.
8639                  */
8640                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8641                 temp |= mask;
8642                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8643                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8644                 temp &= ~mask;
8645                 temp |= data;
8646                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8647                 break;
8648         case REG_C_1:
8649                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8650                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8651                 break;
8652         case REG_C_2:
8653                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8654                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8655                 break;
8656         case REG_C_3:
8657                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8658                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8659                 break;
8660         case REG_C_4:
8661                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8662                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8663                 break;
8664         case REG_C_5:
8665                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8666                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8667                 break;
8668         case REG_C_6:
8669                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8670                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8671                 break;
8672         case REG_C_7:
8673                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8674                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8675                 break;
8676         default:
8677                 MLX5_ASSERT(false);
8678                 break;
8679         }
8680 }
8681
8682 /**
8683  * Add MARK item to matcher
8684  *
8685  * @param[in] dev
8686  *   The device to configure through.
8687  * @param[in, out] matcher
8688  *   Flow matcher.
8689  * @param[in, out] key
8690  *   Flow matcher value.
8691  * @param[in] item
8692  *   Flow pattern to translate.
8693  */
8694 static void
8695 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8696                             void *matcher, void *key,
8697                             const struct rte_flow_item *item)
8698 {
8699         struct mlx5_priv *priv = dev->data->dev_private;
8700         const struct rte_flow_item_mark *mark;
8701         uint32_t value;
8702         uint32_t mask;
8703
8704         mark = item->mask ? (const void *)item->mask :
8705                             &rte_flow_item_mark_mask;
8706         mask = mark->id & priv->sh->dv_mark_mask;
8707         mark = (const void *)item->spec;
8708         MLX5_ASSERT(mark);
8709         value = mark->id & priv->sh->dv_mark_mask & mask;
8710         if (mask) {
8711                 enum modify_reg reg;
8712
8713                 /* Get the metadata register index for the mark. */
8714                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8715                 MLX5_ASSERT(reg > 0);
8716                 if (reg == REG_C_0) {
8717                         struct mlx5_priv *priv = dev->data->dev_private;
8718                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8719                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8720
8721                         mask &= msk_c0;
8722                         mask <<= shl_c0;
8723                         value <<= shl_c0;
8724                 }
8725                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8726         }
8727 }
8728
8729 /**
8730  * Add META item to matcher
8731  *
8732  * @param[in] dev
8733  *   The devich to configure through.
8734  * @param[in, out] matcher
8735  *   Flow matcher.
8736  * @param[in, out] key
8737  *   Flow matcher value.
8738  * @param[in] attr
8739  *   Attributes of flow that includes this item.
8740  * @param[in] item
8741  *   Flow pattern to translate.
8742  */
8743 static void
8744 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8745                             void *matcher, void *key,
8746                             const struct rte_flow_attr *attr,
8747                             const struct rte_flow_item *item)
8748 {
8749         const struct rte_flow_item_meta *meta_m;
8750         const struct rte_flow_item_meta *meta_v;
8751
8752         meta_m = (const void *)item->mask;
8753         if (!meta_m)
8754                 meta_m = &rte_flow_item_meta_mask;
8755         meta_v = (const void *)item->spec;
8756         if (meta_v) {
8757                 int reg;
8758                 uint32_t value = meta_v->data;
8759                 uint32_t mask = meta_m->data;
8760
8761                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8762                 if (reg < 0)
8763                         return;
8764                 MLX5_ASSERT(reg != REG_NON);
8765                 /*
8766                  * In datapath code there is no endianness
8767                  * coversions for perfromance reasons, all
8768                  * pattern conversions are done in rte_flow.
8769                  */
8770                 value = rte_cpu_to_be_32(value);
8771                 mask = rte_cpu_to_be_32(mask);
8772                 if (reg == REG_C_0) {
8773                         struct mlx5_priv *priv = dev->data->dev_private;
8774                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8775                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8776 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8777                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8778
8779                         value >>= shr_c0;
8780                         mask >>= shr_c0;
8781 #endif
8782                         value <<= shl_c0;
8783                         mask <<= shl_c0;
8784                         MLX5_ASSERT(msk_c0);
8785                         MLX5_ASSERT(!(~msk_c0 & mask));
8786                 }
8787                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8788         }
8789 }
8790
8791 /**
8792  * Add vport metadata Reg C0 item to matcher
8793  *
8794  * @param[in, out] matcher
8795  *   Flow matcher.
8796  * @param[in, out] key
8797  *   Flow matcher value.
8798  * @param[in] reg
8799  *   Flow pattern to translate.
8800  */
8801 static void
8802 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8803                                   uint32_t value, uint32_t mask)
8804 {
8805         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8806 }
8807
8808 /**
8809  * Add tag item to matcher
8810  *
8811  * @param[in] dev
8812  *   The devich to configure through.
8813  * @param[in, out] matcher
8814  *   Flow matcher.
8815  * @param[in, out] key
8816  *   Flow matcher value.
8817  * @param[in] item
8818  *   Flow pattern to translate.
8819  */
8820 static void
8821 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8822                                 void *matcher, void *key,
8823                                 const struct rte_flow_item *item)
8824 {
8825         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8826         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8827         uint32_t mask, value;
8828
8829         MLX5_ASSERT(tag_v);
8830         value = tag_v->data;
8831         mask = tag_m ? tag_m->data : UINT32_MAX;
8832         if (tag_v->id == REG_C_0) {
8833                 struct mlx5_priv *priv = dev->data->dev_private;
8834                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8835                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8836
8837                 mask &= msk_c0;
8838                 mask <<= shl_c0;
8839                 value <<= shl_c0;
8840         }
8841         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8842 }
8843
8844 /**
8845  * Add TAG item to matcher
8846  *
8847  * @param[in] dev
8848  *   The devich to configure through.
8849  * @param[in, out] matcher
8850  *   Flow matcher.
8851  * @param[in, out] key
8852  *   Flow matcher value.
8853  * @param[in] item
8854  *   Flow pattern to translate.
8855  */
8856 static void
8857 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8858                            void *matcher, void *key,
8859                            const struct rte_flow_item *item)
8860 {
8861         const struct rte_flow_item_tag *tag_v = item->spec;
8862         const struct rte_flow_item_tag *tag_m = item->mask;
8863         enum modify_reg reg;
8864
8865         MLX5_ASSERT(tag_v);
8866         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8867         /* Get the metadata register index for the tag. */
8868         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8869         MLX5_ASSERT(reg > 0);
8870         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8871 }
8872
8873 /**
8874  * Add source vport match to the specified matcher.
8875  *
8876  * @param[in, out] matcher
8877  *   Flow matcher.
8878  * @param[in, out] key
8879  *   Flow matcher value.
8880  * @param[in] port
8881  *   Source vport value to match
8882  * @param[in] mask
8883  *   Mask
8884  */
8885 static void
8886 flow_dv_translate_item_source_vport(void *matcher, void *key,
8887                                     int16_t port, uint16_t mask)
8888 {
8889         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8890         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8891
8892         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8893         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8894 }
8895
8896 /**
8897  * Translate port-id item to eswitch match on  port-id.
8898  *
8899  * @param[in] dev
8900  *   The devich to configure through.
8901  * @param[in, out] matcher
8902  *   Flow matcher.
8903  * @param[in, out] key
8904  *   Flow matcher value.
8905  * @param[in] item
8906  *   Flow pattern to translate.
8907  * @param[in]
8908  *   Flow attributes.
8909  *
8910  * @return
8911  *   0 on success, a negative errno value otherwise.
8912  */
8913 static int
8914 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8915                                void *key, const struct rte_flow_item *item,
8916                                const struct rte_flow_attr *attr)
8917 {
8918         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8919         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8920         struct mlx5_priv *priv;
8921         uint16_t mask, id;
8922
8923         mask = pid_m ? pid_m->id : 0xffff;
8924         id = pid_v ? pid_v->id : dev->data->port_id;
8925         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8926         if (!priv)
8927                 return -rte_errno;
8928         /*
8929          * Translate to vport field or to metadata, depending on mode.
8930          * Kernel can use either misc.source_port or half of C0 metadata
8931          * register.
8932          */
8933         if (priv->vport_meta_mask) {
8934                 /*
8935                  * Provide the hint for SW steering library
8936                  * to insert the flow into ingress domain and
8937                  * save the extra vport match.
8938                  */
8939                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8940                     priv->pf_bond < 0 && attr->transfer)
8941                         flow_dv_translate_item_source_vport
8942                                 (matcher, key, priv->vport_id, mask);
8943                 /*
8944                  * We should always set the vport metadata register,
8945                  * otherwise the SW steering library can drop
8946                  * the rule if wire vport metadata value is not zero,
8947                  * it depends on kernel configuration.
8948                  */
8949                 flow_dv_translate_item_meta_vport(matcher, key,
8950                                                   priv->vport_meta_tag,
8951                                                   priv->vport_meta_mask);
8952         } else {
8953                 flow_dv_translate_item_source_vport(matcher, key,
8954                                                     priv->vport_id, mask);
8955         }
8956         return 0;
8957 }
8958
8959 /**
8960  * Add ICMP6 item to matcher and to the value.
8961  *
8962  * @param[in, out] matcher
8963  *   Flow matcher.
8964  * @param[in, out] key
8965  *   Flow matcher value.
8966  * @param[in] item
8967  *   Flow pattern to translate.
8968  * @param[in] inner
8969  *   Item is inner pattern.
8970  */
8971 static void
8972 flow_dv_translate_item_icmp6(void *matcher, void *key,
8973                               const struct rte_flow_item *item,
8974                               int inner)
8975 {
8976         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8977         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8978         void *headers_m;
8979         void *headers_v;
8980         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8981                                      misc_parameters_3);
8982         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8983         if (inner) {
8984                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8985                                          inner_headers);
8986                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8987         } else {
8988                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8989                                          outer_headers);
8990                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8991         }
8992         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8993         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8994         if (!icmp6_v)
8995                 return;
8996         if (!icmp6_m)
8997                 icmp6_m = &rte_flow_item_icmp6_mask;
8998         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8999         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9000                  icmp6_v->type & icmp6_m->type);
9001         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9002         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9003                  icmp6_v->code & icmp6_m->code);
9004 }
9005
9006 /**
9007  * Add ICMP item to matcher and to the value.
9008  *
9009  * @param[in, out] matcher
9010  *   Flow matcher.
9011  * @param[in, out] key
9012  *   Flow matcher value.
9013  * @param[in] item
9014  *   Flow pattern to translate.
9015  * @param[in] inner
9016  *   Item is inner pattern.
9017  */
9018 static void
9019 flow_dv_translate_item_icmp(void *matcher, void *key,
9020                             const struct rte_flow_item *item,
9021                             int inner)
9022 {
9023         const struct rte_flow_item_icmp *icmp_m = item->mask;
9024         const struct rte_flow_item_icmp *icmp_v = item->spec;
9025         uint32_t icmp_header_data_m = 0;
9026         uint32_t icmp_header_data_v = 0;
9027         void *headers_m;
9028         void *headers_v;
9029         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9030                                      misc_parameters_3);
9031         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9032         if (inner) {
9033                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9034                                          inner_headers);
9035                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9036         } else {
9037                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9038                                          outer_headers);
9039                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9040         }
9041         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9042         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9043         if (!icmp_v)
9044                 return;
9045         if (!icmp_m)
9046                 icmp_m = &rte_flow_item_icmp_mask;
9047         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9048                  icmp_m->hdr.icmp_type);
9049         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9050                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9051         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9052                  icmp_m->hdr.icmp_code);
9053         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9054                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9055         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9056         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9057         if (icmp_header_data_m) {
9058                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9059                 icmp_header_data_v |=
9060                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9061                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9062                          icmp_header_data_m);
9063                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9064                          icmp_header_data_v & icmp_header_data_m);
9065         }
9066 }
9067
9068 /**
9069  * Add GTP item to matcher and to the value.
9070  *
9071  * @param[in, out] matcher
9072  *   Flow matcher.
9073  * @param[in, out] key
9074  *   Flow matcher value.
9075  * @param[in] item
9076  *   Flow pattern to translate.
9077  * @param[in] inner
9078  *   Item is inner pattern.
9079  */
9080 static void
9081 flow_dv_translate_item_gtp(void *matcher, void *key,
9082                            const struct rte_flow_item *item, int inner)
9083 {
9084         const struct rte_flow_item_gtp *gtp_m = item->mask;
9085         const struct rte_flow_item_gtp *gtp_v = item->spec;
9086         void *headers_m;
9087         void *headers_v;
9088         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9089                                      misc_parameters_3);
9090         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9091         uint16_t dport = RTE_GTPU_UDP_PORT;
9092
9093         if (inner) {
9094                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9095                                          inner_headers);
9096                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9097         } else {
9098                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9099                                          outer_headers);
9100                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9101         }
9102         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9103                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9104                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9105         }
9106         if (!gtp_v)
9107                 return;
9108         if (!gtp_m)
9109                 gtp_m = &rte_flow_item_gtp_mask;
9110         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9111                  gtp_m->v_pt_rsv_flags);
9112         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9113                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9114         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9115         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9116                  gtp_v->msg_type & gtp_m->msg_type);
9117         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9118                  rte_be_to_cpu_32(gtp_m->teid));
9119         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9120                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9121 }
9122
9123 /**
9124  * Add GTP PSC item to matcher.
9125  *
9126  * @param[in, out] matcher
9127  *   Flow matcher.
9128  * @param[in, out] key
9129  *   Flow matcher value.
9130  * @param[in] item
9131  *   Flow pattern to translate.
9132  */
9133 static int
9134 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9135                                const struct rte_flow_item *item)
9136 {
9137         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9138         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9139         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9140                         misc_parameters_3);
9141         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9142         union {
9143                 uint32_t w32;
9144                 struct {
9145                         uint16_t seq_num;
9146                         uint8_t npdu_num;
9147                         uint8_t next_ext_header_type;
9148                 };
9149         } dw_2;
9150         uint8_t gtp_flags;
9151
9152         /* Always set E-flag match on one, regardless of GTP item settings. */
9153         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9154         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9155         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9156         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9157         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9158         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9159         /*Set next extension header type. */
9160         dw_2.seq_num = 0;
9161         dw_2.npdu_num = 0;
9162         dw_2.next_ext_header_type = 0xff;
9163         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9164                  rte_cpu_to_be_32(dw_2.w32));
9165         dw_2.seq_num = 0;
9166         dw_2.npdu_num = 0;
9167         dw_2.next_ext_header_type = 0x85;
9168         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9169                  rte_cpu_to_be_32(dw_2.w32));
9170         if (gtp_psc_v) {
9171                 union {
9172                         uint32_t w32;
9173                         struct {
9174                                 uint8_t len;
9175                                 uint8_t type_flags;
9176                                 uint8_t qfi;
9177                                 uint8_t reserved;
9178                         };
9179                 } dw_0;
9180
9181                 /*Set extension header PDU type and Qos. */
9182                 if (!gtp_psc_m)
9183                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9184                 dw_0.w32 = 0;
9185                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9186                 dw_0.qfi = gtp_psc_m->qfi;
9187                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9188                          rte_cpu_to_be_32(dw_0.w32));
9189                 dw_0.w32 = 0;
9190                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9191                                                         gtp_psc_m->pdu_type);
9192                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9193                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9194                          rte_cpu_to_be_32(dw_0.w32));
9195         }
9196         return 0;
9197 }
9198
9199 /**
9200  * Add eCPRI item to matcher and to the value.
9201  *
9202  * @param[in] dev
9203  *   The devich to configure through.
9204  * @param[in, out] matcher
9205  *   Flow matcher.
9206  * @param[in, out] key
9207  *   Flow matcher value.
9208  * @param[in] item
9209  *   Flow pattern to translate.
9210  * @param[in] samples
9211  *   Sample IDs to be used in the matching.
9212  */
9213 static void
9214 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9215                              void *key, const struct rte_flow_item *item)
9216 {
9217         struct mlx5_priv *priv = dev->data->dev_private;
9218         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9219         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9220         struct rte_ecpri_common_hdr common;
9221         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9222                                      misc_parameters_4);
9223         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9224         uint32_t *samples;
9225         void *dw_m;
9226         void *dw_v;
9227
9228         if (!ecpri_v)
9229                 return;
9230         if (!ecpri_m)
9231                 ecpri_m = &rte_flow_item_ecpri_mask;
9232         /*
9233          * Maximal four DW samples are supported in a single matching now.
9234          * Two are used now for a eCPRI matching:
9235          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9236          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9237          *    if any.
9238          */
9239         if (!ecpri_m->hdr.common.u32)
9240                 return;
9241         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9242         /* Need to take the whole DW as the mask to fill the entry. */
9243         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9244                             prog_sample_field_value_0);
9245         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9246                             prog_sample_field_value_0);
9247         /* Already big endian (network order) in the header. */
9248         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9249         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9250         /* Sample#0, used for matching type, offset 0. */
9251         MLX5_SET(fte_match_set_misc4, misc4_m,
9252                  prog_sample_field_id_0, samples[0]);
9253         /* It makes no sense to set the sample ID in the mask field. */
9254         MLX5_SET(fte_match_set_misc4, misc4_v,
9255                  prog_sample_field_id_0, samples[0]);
9256         /*
9257          * Checking if message body part needs to be matched.
9258          * Some wildcard rules only matching type field should be supported.
9259          */
9260         if (ecpri_m->hdr.dummy[0]) {
9261                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9262                 switch (common.type) {
9263                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9264                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9265                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9266                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9267                                             prog_sample_field_value_1);
9268                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9269                                             prog_sample_field_value_1);
9270                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9271                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9272                                             ecpri_m->hdr.dummy[0];
9273                         /* Sample#1, to match message body, offset 4. */
9274                         MLX5_SET(fte_match_set_misc4, misc4_m,
9275                                  prog_sample_field_id_1, samples[1]);
9276                         MLX5_SET(fte_match_set_misc4, misc4_v,
9277                                  prog_sample_field_id_1, samples[1]);
9278                         break;
9279                 default:
9280                         /* Others, do not match any sample ID. */
9281                         break;
9282                 }
9283         }
9284 }
9285
9286 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9287
9288 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9289         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9290                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9291
9292 /**
9293  * Calculate flow matcher enable bitmap.
9294  *
9295  * @param match_criteria
9296  *   Pointer to flow matcher criteria.
9297  *
9298  * @return
9299  *   Bitmap of enabled fields.
9300  */
9301 static uint8_t
9302 flow_dv_matcher_enable(uint32_t *match_criteria)
9303 {
9304         uint8_t match_criteria_enable;
9305
9306         match_criteria_enable =
9307                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9308                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9309         match_criteria_enable |=
9310                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9311                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9312         match_criteria_enable |=
9313                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9314                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9315         match_criteria_enable |=
9316                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9317                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9318         match_criteria_enable |=
9319                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9320                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9321         match_criteria_enable |=
9322                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9323                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9324         return match_criteria_enable;
9325 }
9326
9327 struct mlx5_hlist_entry *
9328 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9329 {
9330         struct mlx5_dev_ctx_shared *sh = list->ctx;
9331         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9332         struct rte_eth_dev *dev = ctx->dev;
9333         struct mlx5_flow_tbl_data_entry *tbl_data;
9334         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9335         struct rte_flow_error *error = ctx->error;
9336         union mlx5_flow_tbl_key key = { .v64 = key64 };
9337         struct mlx5_flow_tbl_resource *tbl;
9338         void *domain;
9339         uint32_t idx = 0;
9340         int ret;
9341
9342         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9343         if (!tbl_data) {
9344                 rte_flow_error_set(error, ENOMEM,
9345                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9346                                    NULL,
9347                                    "cannot allocate flow table data entry");
9348                 return NULL;
9349         }
9350         tbl_data->idx = idx;
9351         tbl_data->tunnel = tt_prm->tunnel;
9352         tbl_data->group_id = tt_prm->group_id;
9353         tbl_data->external = !!tt_prm->external;
9354         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9355         tbl_data->is_egress = !!key.direction;
9356         tbl_data->is_transfer = !!key.domain;
9357         tbl_data->dummy = !!key.dummy;
9358         tbl_data->table_id = key.table_id;
9359         tbl = &tbl_data->tbl;
9360         if (key.dummy)
9361                 return &tbl_data->entry;
9362         if (key.domain)
9363                 domain = sh->fdb_domain;
9364         else if (key.direction)
9365                 domain = sh->tx_domain;
9366         else
9367                 domain = sh->rx_domain;
9368         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9369         if (ret) {
9370                 rte_flow_error_set(error, ENOMEM,
9371                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9372                                    NULL, "cannot create flow table object");
9373                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9374                 return NULL;
9375         }
9376         if (key.table_id) {
9377                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9378                                         (tbl->obj, &tbl_data->jump.action);
9379                 if (ret) {
9380                         rte_flow_error_set(error, ENOMEM,
9381                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9382                                            NULL,
9383                                            "cannot create flow jump action");
9384                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9385                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9386                         return NULL;
9387                 }
9388         }
9389         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9390               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9391               key.table_id);
9392         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9393                              flow_dv_matcher_create_cb,
9394                              flow_dv_matcher_match_cb,
9395                              flow_dv_matcher_remove_cb);
9396         return &tbl_data->entry;
9397 }
9398
9399 int
9400 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9401                      struct mlx5_hlist_entry *entry, uint64_t key64,
9402                      void *cb_ctx __rte_unused)
9403 {
9404         struct mlx5_flow_tbl_data_entry *tbl_data =
9405                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9406         union mlx5_flow_tbl_key key = { .v64 = key64 };
9407
9408         return tbl_data->table_id != key.table_id ||
9409                tbl_data->dummy != key.dummy ||
9410                tbl_data->is_transfer != key.domain ||
9411                tbl_data->is_egress != key.direction;
9412 }
9413
9414 /**
9415  * Get a flow table.
9416  *
9417  * @param[in, out] dev
9418  *   Pointer to rte_eth_dev structure.
9419  * @param[in] table_id
9420  *   Table id to use.
9421  * @param[in] egress
9422  *   Direction of the table.
9423  * @param[in] transfer
9424  *   E-Switch or NIC flow.
9425  * @param[in] dummy
9426  *   Dummy entry for dv API.
9427  * @param[out] error
9428  *   pointer to error structure.
9429  *
9430  * @return
9431  *   Returns tables resource based on the index, NULL in case of failed.
9432  */
9433 struct mlx5_flow_tbl_resource *
9434 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9435                          uint32_t table_id, uint8_t egress,
9436                          uint8_t transfer,
9437                          bool external,
9438                          const struct mlx5_flow_tunnel *tunnel,
9439                          uint32_t group_id, uint8_t dummy,
9440                          struct rte_flow_error *error)
9441 {
9442         struct mlx5_priv *priv = dev->data->dev_private;
9443         union mlx5_flow_tbl_key table_key = {
9444                 {
9445                         .table_id = table_id,
9446                         .dummy = dummy,
9447                         .domain = !!transfer,
9448                         .direction = !!egress,
9449                 }
9450         };
9451         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9452                 .tunnel = tunnel,
9453                 .group_id = group_id,
9454                 .external = external,
9455         };
9456         struct mlx5_flow_cb_ctx ctx = {
9457                 .dev = dev,
9458                 .error = error,
9459                 .data = &tt_prm,
9460         };
9461         struct mlx5_hlist_entry *entry;
9462         struct mlx5_flow_tbl_data_entry *tbl_data;
9463
9464         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9465         if (!entry) {
9466                 rte_flow_error_set(error, ENOMEM,
9467                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9468                                    "cannot get table");
9469                 return NULL;
9470         }
9471         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9472                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9473         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9474         return &tbl_data->tbl;
9475 }
9476
9477 void
9478 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9479                       struct mlx5_hlist_entry *entry)
9480 {
9481         struct mlx5_dev_ctx_shared *sh = list->ctx;
9482         struct mlx5_flow_tbl_data_entry *tbl_data =
9483                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9484
9485         MLX5_ASSERT(entry && sh);
9486         if (tbl_data->jump.action)
9487                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9488         if (tbl_data->tbl.obj)
9489                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9490         if (tbl_data->tunnel_offload && tbl_data->external) {
9491                 struct mlx5_hlist_entry *he;
9492                 struct mlx5_hlist *tunnel_grp_hash;
9493                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9494                 union tunnel_tbl_key tunnel_key = {
9495                         .tunnel_id = tbl_data->tunnel ?
9496                                         tbl_data->tunnel->tunnel_id : 0,
9497                         .group = tbl_data->group_id
9498                 };
9499                 uint32_t table_id = tbl_data->table_id;
9500
9501                 tunnel_grp_hash = tbl_data->tunnel ?
9502                                         tbl_data->tunnel->groups :
9503                                         thub->groups;
9504                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9505                 if (he)
9506                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9507                 DRV_LOG(DEBUG,
9508                         "Table_id %u tunnel %u group %u released.",
9509                         table_id,
9510                         tbl_data->tunnel ?
9511                         tbl_data->tunnel->tunnel_id : 0,
9512                         tbl_data->group_id);
9513         }
9514         mlx5_cache_list_destroy(&tbl_data->matchers);
9515         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9516 }
9517
9518 /**
9519  * Release a flow table.
9520  *
9521  * @param[in] sh
9522  *   Pointer to device shared structure.
9523  * @param[in] tbl
9524  *   Table resource to be released.
9525  *
9526  * @return
9527  *   Returns 0 if table was released, else return 1;
9528  */
9529 static int
9530 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9531                              struct mlx5_flow_tbl_resource *tbl)
9532 {
9533         struct mlx5_flow_tbl_data_entry *tbl_data =
9534                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9535
9536         if (!tbl)
9537                 return 0;
9538         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9539 }
9540
9541 int
9542 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9543                          struct mlx5_cache_entry *entry, void *cb_ctx)
9544 {
9545         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9546         struct mlx5_flow_dv_matcher *ref = ctx->data;
9547         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9548                                                         entry);
9549
9550         return cur->crc != ref->crc ||
9551                cur->priority != ref->priority ||
9552                memcmp((const void *)cur->mask.buf,
9553                       (const void *)ref->mask.buf, ref->mask.size);
9554 }
9555
9556 struct mlx5_cache_entry *
9557 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9558                           struct mlx5_cache_entry *entry __rte_unused,
9559                           void *cb_ctx)
9560 {
9561         struct mlx5_dev_ctx_shared *sh = list->ctx;
9562         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9563         struct mlx5_flow_dv_matcher *ref = ctx->data;
9564         struct mlx5_flow_dv_matcher *cache;
9565         struct mlx5dv_flow_matcher_attr dv_attr = {
9566                 .type = IBV_FLOW_ATTR_NORMAL,
9567                 .match_mask = (void *)&ref->mask,
9568         };
9569         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9570                                                             typeof(*tbl), tbl);
9571         int ret;
9572
9573         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9574         if (!cache) {
9575                 rte_flow_error_set(ctx->error, ENOMEM,
9576                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9577                                    "cannot create matcher");
9578                 return NULL;
9579         }
9580         *cache = *ref;
9581         dv_attr.match_criteria_enable =
9582                 flow_dv_matcher_enable(cache->mask.buf);
9583         dv_attr.priority = ref->priority;
9584         if (tbl->is_egress)
9585                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9586         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9587                                                &cache->matcher_object);
9588         if (ret) {
9589                 mlx5_free(cache);
9590                 rte_flow_error_set(ctx->error, ENOMEM,
9591                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9592                                    "cannot create matcher");
9593                 return NULL;
9594         }
9595         return &cache->entry;
9596 }
9597
9598 /**
9599  * Register the flow matcher.
9600  *
9601  * @param[in, out] dev
9602  *   Pointer to rte_eth_dev structure.
9603  * @param[in, out] matcher
9604  *   Pointer to flow matcher.
9605  * @param[in, out] key
9606  *   Pointer to flow table key.
9607  * @parm[in, out] dev_flow
9608  *   Pointer to the dev_flow.
9609  * @param[out] error
9610  *   pointer to error structure.
9611  *
9612  * @return
9613  *   0 on success otherwise -errno and errno is set.
9614  */
9615 static int
9616 flow_dv_matcher_register(struct rte_eth_dev *dev,
9617                          struct mlx5_flow_dv_matcher *ref,
9618                          union mlx5_flow_tbl_key *key,
9619                          struct mlx5_flow *dev_flow,
9620                          const struct mlx5_flow_tunnel *tunnel,
9621                          uint32_t group_id,
9622                          struct rte_flow_error *error)
9623 {
9624         struct mlx5_cache_entry *entry;
9625         struct mlx5_flow_dv_matcher *cache;
9626         struct mlx5_flow_tbl_resource *tbl;
9627         struct mlx5_flow_tbl_data_entry *tbl_data;
9628         struct mlx5_flow_cb_ctx ctx = {
9629                 .error = error,
9630                 .data = ref,
9631         };
9632
9633         /**
9634          * tunnel offload API requires this registration for cases when
9635          * tunnel match rule was inserted before tunnel set rule.
9636          */
9637         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9638                                        key->direction, key->domain,
9639                                        dev_flow->external, tunnel,
9640                                        group_id, 0, error);
9641         if (!tbl)
9642                 return -rte_errno;      /* No need to refill the error info */
9643         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9644         ref->tbl = tbl;
9645         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9646         if (!entry) {
9647                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9648                 return rte_flow_error_set(error, ENOMEM,
9649                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9650                                           "cannot allocate ref memory");
9651         }
9652         cache = container_of(entry, typeof(*cache), entry);
9653         dev_flow->handle->dvh.matcher = cache;
9654         return 0;
9655 }
9656
9657 struct mlx5_hlist_entry *
9658 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9659 {
9660         struct mlx5_dev_ctx_shared *sh = list->ctx;
9661         struct rte_flow_error *error = ctx;
9662         struct mlx5_flow_dv_tag_resource *entry;
9663         uint32_t idx = 0;
9664         int ret;
9665
9666         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9667         if (!entry) {
9668                 rte_flow_error_set(error, ENOMEM,
9669                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9670                                    "cannot allocate resource memory");
9671                 return NULL;
9672         }
9673         entry->idx = idx;
9674         entry->tag_id = key;
9675         ret = mlx5_flow_os_create_flow_action_tag(key,
9676                                                   &entry->action);
9677         if (ret) {
9678                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9679                 rte_flow_error_set(error, ENOMEM,
9680                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9681                                    NULL, "cannot create action");
9682                 return NULL;
9683         }
9684         return &entry->entry;
9685 }
9686
9687 int
9688 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9689                      struct mlx5_hlist_entry *entry, uint64_t key,
9690                      void *cb_ctx __rte_unused)
9691 {
9692         struct mlx5_flow_dv_tag_resource *tag =
9693                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9694
9695         return key != tag->tag_id;
9696 }
9697
9698 /**
9699  * Find existing tag resource or create and register a new one.
9700  *
9701  * @param dev[in, out]
9702  *   Pointer to rte_eth_dev structure.
9703  * @param[in, out] tag_be24
9704  *   Tag value in big endian then R-shift 8.
9705  * @parm[in, out] dev_flow
9706  *   Pointer to the dev_flow.
9707  * @param[out] error
9708  *   pointer to error structure.
9709  *
9710  * @return
9711  *   0 on success otherwise -errno and errno is set.
9712  */
9713 static int
9714 flow_dv_tag_resource_register
9715                         (struct rte_eth_dev *dev,
9716                          uint32_t tag_be24,
9717                          struct mlx5_flow *dev_flow,
9718                          struct rte_flow_error *error)
9719 {
9720         struct mlx5_priv *priv = dev->data->dev_private;
9721         struct mlx5_flow_dv_tag_resource *cache_resource;
9722         struct mlx5_hlist_entry *entry;
9723
9724         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9725         if (entry) {
9726                 cache_resource = container_of
9727                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9728                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9729                 dev_flow->dv.tag_resource = cache_resource;
9730                 return 0;
9731         }
9732         return -rte_errno;
9733 }
9734
9735 void
9736 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9737                       struct mlx5_hlist_entry *entry)
9738 {
9739         struct mlx5_dev_ctx_shared *sh = list->ctx;
9740         struct mlx5_flow_dv_tag_resource *tag =
9741                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9742
9743         MLX5_ASSERT(tag && sh && tag->action);
9744         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9745         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9746         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9747 }
9748
9749 /**
9750  * Release the tag.
9751  *
9752  * @param dev
9753  *   Pointer to Ethernet device.
9754  * @param tag_idx
9755  *   Tag index.
9756  *
9757  * @return
9758  *   1 while a reference on it exists, 0 when freed.
9759  */
9760 static int
9761 flow_dv_tag_release(struct rte_eth_dev *dev,
9762                     uint32_t tag_idx)
9763 {
9764         struct mlx5_priv *priv = dev->data->dev_private;
9765         struct mlx5_flow_dv_tag_resource *tag;
9766
9767         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9768         if (!tag)
9769                 return 0;
9770         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9771                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9772         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9773 }
9774
9775 /**
9776  * Translate port ID action to vport.
9777  *
9778  * @param[in] dev
9779  *   Pointer to rte_eth_dev structure.
9780  * @param[in] action
9781  *   Pointer to the port ID action.
9782  * @param[out] dst_port_id
9783  *   The target port ID.
9784  * @param[out] error
9785  *   Pointer to the error structure.
9786  *
9787  * @return
9788  *   0 on success, a negative errno value otherwise and rte_errno is set.
9789  */
9790 static int
9791 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9792                                  const struct rte_flow_action *action,
9793                                  uint32_t *dst_port_id,
9794                                  struct rte_flow_error *error)
9795 {
9796         uint32_t port;
9797         struct mlx5_priv *priv;
9798         const struct rte_flow_action_port_id *conf =
9799                         (const struct rte_flow_action_port_id *)action->conf;
9800
9801         port = conf->original ? dev->data->port_id : conf->id;
9802         priv = mlx5_port_to_eswitch_info(port, false);
9803         if (!priv)
9804                 return rte_flow_error_set(error, -rte_errno,
9805                                           RTE_FLOW_ERROR_TYPE_ACTION,
9806                                           NULL,
9807                                           "No eswitch info was found for port");
9808 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9809         /*
9810          * This parameter is transferred to
9811          * mlx5dv_dr_action_create_dest_ib_port().
9812          */
9813         *dst_port_id = priv->dev_port;
9814 #else
9815         /*
9816          * Legacy mode, no LAG configurations is supported.
9817          * This parameter is transferred to
9818          * mlx5dv_dr_action_create_dest_vport().
9819          */
9820         *dst_port_id = priv->vport_id;
9821 #endif
9822         return 0;
9823 }
9824
9825 /**
9826  * Create a counter with aging configuration.
9827  *
9828  * @param[in] dev
9829  *   Pointer to rte_eth_dev structure.
9830  * @param[out] count
9831  *   Pointer to the counter action configuration.
9832  * @param[in] age
9833  *   Pointer to the aging action configuration.
9834  *
9835  * @return
9836  *   Index to flow counter on success, 0 otherwise.
9837  */
9838 static uint32_t
9839 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9840                                 struct mlx5_flow *dev_flow,
9841                                 const struct rte_flow_action_count *count,
9842                                 const struct rte_flow_action_age *age)
9843 {
9844         uint32_t counter;
9845         struct mlx5_age_param *age_param;
9846
9847         if (count && count->shared)
9848                 counter = flow_dv_counter_get_shared(dev, count->id);
9849         else
9850                 counter = flow_dv_counter_alloc(dev, !!age);
9851         if (!counter || age == NULL)
9852                 return counter;
9853         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9854         age_param->context = age->context ? age->context :
9855                 (void *)(uintptr_t)(dev_flow->flow_idx);
9856         age_param->timeout = age->timeout;
9857         age_param->port_id = dev->data->port_id;
9858         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9859         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9860         return counter;
9861 }
9862
9863 /**
9864  * Add Tx queue matcher
9865  *
9866  * @param[in] dev
9867  *   Pointer to the dev struct.
9868  * @param[in, out] matcher
9869  *   Flow matcher.
9870  * @param[in, out] key
9871  *   Flow matcher value.
9872  * @param[in] item
9873  *   Flow pattern to translate.
9874  * @param[in] inner
9875  *   Item is inner pattern.
9876  */
9877 static void
9878 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9879                                 void *matcher, void *key,
9880                                 const struct rte_flow_item *item)
9881 {
9882         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9883         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9884         void *misc_m =
9885                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9886         void *misc_v =
9887                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9888         struct mlx5_txq_ctrl *txq;
9889         uint32_t queue;
9890
9891
9892         queue_m = (const void *)item->mask;
9893         if (!queue_m)
9894                 return;
9895         queue_v = (const void *)item->spec;
9896         if (!queue_v)
9897                 return;
9898         txq = mlx5_txq_get(dev, queue_v->queue);
9899         if (!txq)
9900                 return;
9901         queue = txq->obj->sq->id;
9902         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9903         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9904                  queue & queue_m->queue);
9905         mlx5_txq_release(dev, queue_v->queue);
9906 }
9907
9908 /**
9909  * Set the hash fields according to the @p flow information.
9910  *
9911  * @param[in] dev_flow
9912  *   Pointer to the mlx5_flow.
9913  * @param[in] rss_desc
9914  *   Pointer to the mlx5_flow_rss_desc.
9915  */
9916 static void
9917 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9918                        struct mlx5_flow_rss_desc *rss_desc)
9919 {
9920         uint64_t items = dev_flow->handle->layers;
9921         int rss_inner = 0;
9922         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9923
9924         dev_flow->hash_fields = 0;
9925 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9926         if (rss_desc->level >= 2) {
9927                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9928                 rss_inner = 1;
9929         }
9930 #endif
9931         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9932             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9933                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9934                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9935                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9936                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9937                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9938                         else
9939                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9940                 }
9941         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9942                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9943                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9944                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9945                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9946                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9947                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9948                         else
9949                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9950                 }
9951         }
9952         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9953             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9954                 if (rss_types & ETH_RSS_UDP) {
9955                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9956                                 dev_flow->hash_fields |=
9957                                                 IBV_RX_HASH_SRC_PORT_UDP;
9958                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9959                                 dev_flow->hash_fields |=
9960                                                 IBV_RX_HASH_DST_PORT_UDP;
9961                         else
9962                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9963                 }
9964         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9965                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9966                 if (rss_types & ETH_RSS_TCP) {
9967                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9968                                 dev_flow->hash_fields |=
9969                                                 IBV_RX_HASH_SRC_PORT_TCP;
9970                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9971                                 dev_flow->hash_fields |=
9972                                                 IBV_RX_HASH_DST_PORT_TCP;
9973                         else
9974                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9975                 }
9976         }
9977 }
9978
9979 /**
9980  * Prepare an Rx Hash queue.
9981  *
9982  * @param dev
9983  *   Pointer to Ethernet device.
9984  * @param[in] dev_flow
9985  *   Pointer to the mlx5_flow.
9986  * @param[in] rss_desc
9987  *   Pointer to the mlx5_flow_rss_desc.
9988  * @param[out] hrxq_idx
9989  *   Hash Rx queue index.
9990  *
9991  * @return
9992  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9993  */
9994 static struct mlx5_hrxq *
9995 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9996                      struct mlx5_flow *dev_flow,
9997                      struct mlx5_flow_rss_desc *rss_desc,
9998                      uint32_t *hrxq_idx)
9999 {
10000         struct mlx5_priv *priv = dev->data->dev_private;
10001         struct mlx5_flow_handle *dh = dev_flow->handle;
10002         struct mlx5_hrxq *hrxq;
10003
10004         MLX5_ASSERT(rss_desc->queue_num);
10005         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10006         rss_desc->hash_fields = dev_flow->hash_fields;
10007         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10008         rss_desc->shared_rss = 0;
10009         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10010         if (!*hrxq_idx)
10011                 return NULL;
10012         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10013                               *hrxq_idx);
10014         return hrxq;
10015 }
10016
10017 /**
10018  * Release sample sub action resource.
10019  *
10020  * @param[in, out] dev
10021  *   Pointer to rte_eth_dev structure.
10022  * @param[in] act_res
10023  *   Pointer to sample sub action resource.
10024  */
10025 static void
10026 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10027                                    struct mlx5_flow_sub_actions_idx *act_res)
10028 {
10029         if (act_res->rix_hrxq) {
10030                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10031                 act_res->rix_hrxq = 0;
10032         }
10033         if (act_res->rix_encap_decap) {
10034                 flow_dv_encap_decap_resource_release(dev,
10035                                                      act_res->rix_encap_decap);
10036                 act_res->rix_encap_decap = 0;
10037         }
10038         if (act_res->rix_port_id_action) {
10039                 flow_dv_port_id_action_resource_release(dev,
10040                                                 act_res->rix_port_id_action);
10041                 act_res->rix_port_id_action = 0;
10042         }
10043         if (act_res->rix_tag) {
10044                 flow_dv_tag_release(dev, act_res->rix_tag);
10045                 act_res->rix_tag = 0;
10046         }
10047         if (act_res->rix_jump) {
10048                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10049                 act_res->rix_jump = 0;
10050         }
10051 }
10052
10053 int
10054 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10055                         struct mlx5_cache_entry *entry, void *cb_ctx)
10056 {
10057         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10058         struct rte_eth_dev *dev = ctx->dev;
10059         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10060         struct mlx5_flow_dv_sample_resource *cache_resource =
10061                         container_of(entry, typeof(*cache_resource), entry);
10062
10063         if (resource->ratio == cache_resource->ratio &&
10064             resource->ft_type == cache_resource->ft_type &&
10065             resource->ft_id == cache_resource->ft_id &&
10066             resource->set_action == cache_resource->set_action &&
10067             !memcmp((void *)&resource->sample_act,
10068                     (void *)&cache_resource->sample_act,
10069                     sizeof(struct mlx5_flow_sub_actions_list))) {
10070                 /*
10071                  * Existing sample action should release the prepared
10072                  * sub-actions reference counter.
10073                  */
10074                 flow_dv_sample_sub_actions_release(dev,
10075                                                 &resource->sample_idx);
10076                 return 0;
10077         }
10078         return 1;
10079 }
10080
10081 struct mlx5_cache_entry *
10082 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10083                          struct mlx5_cache_entry *entry __rte_unused,
10084                          void *cb_ctx)
10085 {
10086         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10087         struct rte_eth_dev *dev = ctx->dev;
10088         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10089         void **sample_dv_actions = resource->sub_actions;
10090         struct mlx5_flow_dv_sample_resource *cache_resource;
10091         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10092         struct mlx5_priv *priv = dev->data->dev_private;
10093         struct mlx5_dev_ctx_shared *sh = priv->sh;
10094         struct mlx5_flow_tbl_resource *tbl;
10095         uint32_t idx = 0;
10096         const uint32_t next_ft_step = 1;
10097         uint32_t next_ft_id = resource->ft_id + next_ft_step;
10098         uint8_t is_egress = 0;
10099         uint8_t is_transfer = 0;
10100         struct rte_flow_error *error = ctx->error;
10101
10102         /* Register new sample resource. */
10103         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10104         if (!cache_resource) {
10105                 rte_flow_error_set(error, ENOMEM,
10106                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10107                                           NULL,
10108                                           "cannot allocate resource memory");
10109                 return NULL;
10110         }
10111         *cache_resource = *resource;
10112         /* Create normal path table level */
10113         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10114                 is_transfer = 1;
10115         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10116                 is_egress = 1;
10117         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10118                                         is_egress, is_transfer,
10119                                         true, NULL, 0, 0, error);
10120         if (!tbl) {
10121                 rte_flow_error_set(error, ENOMEM,
10122                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10123                                           NULL,
10124                                           "fail to create normal path table "
10125                                           "for sample");
10126                 goto error;
10127         }
10128         cache_resource->normal_path_tbl = tbl;
10129         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10130                 if (!sh->default_miss_action) {
10131                         rte_flow_error_set(error, ENOMEM,
10132                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10133                                                 NULL,
10134                                                 "default miss action was not "
10135                                                 "created");
10136                         goto error;
10137                 }
10138                 sample_dv_actions[resource->sample_act.actions_num++] =
10139                                                 sh->default_miss_action;
10140         }
10141         /* Create a DR sample action */
10142         sampler_attr.sample_ratio = cache_resource->ratio;
10143         sampler_attr.default_next_table = tbl->obj;
10144         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10145         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10146                                                         &sample_dv_actions[0];
10147         sampler_attr.action = cache_resource->set_action;
10148         if (mlx5_os_flow_dr_create_flow_action_sampler
10149                         (&sampler_attr, &cache_resource->verbs_action)) {
10150                 rte_flow_error_set(error, ENOMEM,
10151                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10152                                         NULL, "cannot create sample action");
10153                 goto error;
10154         }
10155         cache_resource->idx = idx;
10156         cache_resource->dev = dev;
10157         return &cache_resource->entry;
10158 error:
10159         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10160                 flow_dv_sample_sub_actions_release(dev,
10161                                                    &cache_resource->sample_idx);
10162         if (cache_resource->normal_path_tbl)
10163                 flow_dv_tbl_resource_release(MLX5_SH(dev),
10164                                 cache_resource->normal_path_tbl);
10165         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10166         return NULL;
10167
10168 }
10169
10170 /**
10171  * Find existing sample resource or create and register a new one.
10172  *
10173  * @param[in, out] dev
10174  *   Pointer to rte_eth_dev structure.
10175  * @param[in] resource
10176  *   Pointer to sample resource.
10177  * @parm[in, out] dev_flow
10178  *   Pointer to the dev_flow.
10179  * @param[out] error
10180  *   pointer to error structure.
10181  *
10182  * @return
10183  *   0 on success otherwise -errno and errno is set.
10184  */
10185 static int
10186 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10187                          struct mlx5_flow_dv_sample_resource *resource,
10188                          struct mlx5_flow *dev_flow,
10189                          struct rte_flow_error *error)
10190 {
10191         struct mlx5_flow_dv_sample_resource *cache_resource;
10192         struct mlx5_cache_entry *entry;
10193         struct mlx5_priv *priv = dev->data->dev_private;
10194         struct mlx5_flow_cb_ctx ctx = {
10195                 .dev = dev,
10196                 .error = error,
10197                 .data = resource,
10198         };
10199
10200         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10201         if (!entry)
10202                 return -rte_errno;
10203         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10204         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10205         dev_flow->dv.sample_res = cache_resource;
10206         return 0;
10207 }
10208
10209 int
10210 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10211                             struct mlx5_cache_entry *entry, void *cb_ctx)
10212 {
10213         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10214         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10215         struct rte_eth_dev *dev = ctx->dev;
10216         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10217                         container_of(entry, typeof(*cache_resource), entry);
10218         uint32_t idx = 0;
10219
10220         if (resource->num_of_dest == cache_resource->num_of_dest &&
10221             resource->ft_type == cache_resource->ft_type &&
10222             !memcmp((void *)cache_resource->sample_act,
10223                     (void *)resource->sample_act,
10224                    (resource->num_of_dest *
10225                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10226                 /*
10227                  * Existing sample action should release the prepared
10228                  * sub-actions reference counter.
10229                  */
10230                 for (idx = 0; idx < resource->num_of_dest; idx++)
10231                         flow_dv_sample_sub_actions_release(dev,
10232                                         &resource->sample_idx[idx]);
10233                 return 0;
10234         }
10235         return 1;
10236 }
10237
10238 struct mlx5_cache_entry *
10239 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10240                          struct mlx5_cache_entry *entry __rte_unused,
10241                          void *cb_ctx)
10242 {
10243         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10244         struct rte_eth_dev *dev = ctx->dev;
10245         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10246         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10247         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10248         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10249         struct mlx5_priv *priv = dev->data->dev_private;
10250         struct mlx5_dev_ctx_shared *sh = priv->sh;
10251         struct mlx5_flow_sub_actions_list *sample_act;
10252         struct mlx5dv_dr_domain *domain;
10253         uint32_t idx = 0, res_idx = 0;
10254         struct rte_flow_error *error = ctx->error;
10255         uint64_t action_flags;
10256         int ret;
10257
10258         /* Register new destination array resource. */
10259         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10260                                             &res_idx);
10261         if (!cache_resource) {
10262                 rte_flow_error_set(error, ENOMEM,
10263                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10264                                           NULL,
10265                                           "cannot allocate resource memory");
10266                 return NULL;
10267         }
10268         *cache_resource = *resource;
10269         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10270                 domain = sh->fdb_domain;
10271         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10272                 domain = sh->rx_domain;
10273         else
10274                 domain = sh->tx_domain;
10275         for (idx = 0; idx < resource->num_of_dest; idx++) {
10276                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10277                                  mlx5_malloc(MLX5_MEM_ZERO,
10278                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10279                                  0, SOCKET_ID_ANY);
10280                 if (!dest_attr[idx]) {
10281                         rte_flow_error_set(error, ENOMEM,
10282                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10283                                            NULL,
10284                                            "cannot allocate resource memory");
10285                         goto error;
10286                 }
10287                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10288                 sample_act = &resource->sample_act[idx];
10289                 action_flags = sample_act->action_flags;
10290                 switch (action_flags) {
10291                 case MLX5_FLOW_ACTION_QUEUE:
10292                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10293                         break;
10294                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10295                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10296                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10297                         dest_attr[idx]->dest_reformat->reformat =
10298                                         sample_act->dr_encap_action;
10299                         dest_attr[idx]->dest_reformat->dest =
10300                                         sample_act->dr_port_id_action;
10301                         break;
10302                 case MLX5_FLOW_ACTION_PORT_ID:
10303                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10304                         break;
10305                 case MLX5_FLOW_ACTION_JUMP:
10306                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10307                         break;
10308                 default:
10309                         rte_flow_error_set(error, EINVAL,
10310                                            RTE_FLOW_ERROR_TYPE_ACTION,
10311                                            NULL,
10312                                            "unsupported actions type");
10313                         goto error;
10314                 }
10315         }
10316         /* create a dest array actioin */
10317         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10318                                                 (domain,
10319                                                  cache_resource->num_of_dest,
10320                                                  dest_attr,
10321                                                  &cache_resource->action);
10322         if (ret) {
10323                 rte_flow_error_set(error, ENOMEM,
10324                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10325                                    NULL,
10326                                    "cannot create destination array action");
10327                 goto error;
10328         }
10329         cache_resource->idx = res_idx;
10330         cache_resource->dev = dev;
10331         for (idx = 0; idx < resource->num_of_dest; idx++)
10332                 mlx5_free(dest_attr[idx]);
10333         return &cache_resource->entry;
10334 error:
10335         for (idx = 0; idx < resource->num_of_dest; idx++) {
10336                 flow_dv_sample_sub_actions_release(dev,
10337                                 &cache_resource->sample_idx[idx]);
10338                 if (dest_attr[idx])
10339                         mlx5_free(dest_attr[idx]);
10340         }
10341
10342         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10343         return NULL;
10344 }
10345
10346 /**
10347  * Find existing destination array resource or create and register a new one.
10348  *
10349  * @param[in, out] dev
10350  *   Pointer to rte_eth_dev structure.
10351  * @param[in] resource
10352  *   Pointer to destination array resource.
10353  * @parm[in, out] dev_flow
10354  *   Pointer to the dev_flow.
10355  * @param[out] error
10356  *   pointer to error structure.
10357  *
10358  * @return
10359  *   0 on success otherwise -errno and errno is set.
10360  */
10361 static int
10362 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10363                          struct mlx5_flow_dv_dest_array_resource *resource,
10364                          struct mlx5_flow *dev_flow,
10365                          struct rte_flow_error *error)
10366 {
10367         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10368         struct mlx5_priv *priv = dev->data->dev_private;
10369         struct mlx5_cache_entry *entry;
10370         struct mlx5_flow_cb_ctx ctx = {
10371                 .dev = dev,
10372                 .error = error,
10373                 .data = resource,
10374         };
10375
10376         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10377         if (!entry)
10378                 return -rte_errno;
10379         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10380         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10381         dev_flow->dv.dest_array_res = cache_resource;
10382         return 0;
10383 }
10384
10385 /**
10386  * Convert Sample action to DV specification.
10387  *
10388  * @param[in] dev
10389  *   Pointer to rte_eth_dev structure.
10390  * @param[in] action
10391  *   Pointer to sample action structure.
10392  * @param[in, out] dev_flow
10393  *   Pointer to the mlx5_flow.
10394  * @param[in] attr
10395  *   Pointer to the flow attributes.
10396  * @param[in, out] num_of_dest
10397  *   Pointer to the num of destination.
10398  * @param[in, out] sample_actions
10399  *   Pointer to sample actions list.
10400  * @param[in, out] res
10401  *   Pointer to sample resource.
10402  * @param[out] error
10403  *   Pointer to the error structure.
10404  *
10405  * @return
10406  *   0 on success, a negative errno value otherwise and rte_errno is set.
10407  */
10408 static int
10409 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10410                                 const struct rte_flow_action_sample *action,
10411                                 struct mlx5_flow *dev_flow,
10412                                 const struct rte_flow_attr *attr,
10413                                 uint32_t *num_of_dest,
10414                                 void **sample_actions,
10415                                 struct mlx5_flow_dv_sample_resource *res,
10416                                 struct rte_flow_error *error)
10417 {
10418         struct mlx5_priv *priv = dev->data->dev_private;
10419         const struct rte_flow_action *sub_actions;
10420         struct mlx5_flow_sub_actions_list *sample_act;
10421         struct mlx5_flow_sub_actions_idx *sample_idx;
10422         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10423         struct rte_flow *flow = dev_flow->flow;
10424         struct mlx5_flow_rss_desc *rss_desc;
10425         uint64_t action_flags = 0;
10426
10427         MLX5_ASSERT(wks);
10428         rss_desc = &wks->rss_desc;
10429         sample_act = &res->sample_act;
10430         sample_idx = &res->sample_idx;
10431         res->ratio = action->ratio;
10432         sub_actions = action->actions;
10433         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10434                 int type = sub_actions->type;
10435                 uint32_t pre_rix = 0;
10436                 void *pre_r;
10437                 switch (type) {
10438                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10439                 {
10440                         const struct rte_flow_action_queue *queue;
10441                         struct mlx5_hrxq *hrxq;
10442                         uint32_t hrxq_idx;
10443
10444                         queue = sub_actions->conf;
10445                         rss_desc->queue_num = 1;
10446                         rss_desc->queue[0] = queue->index;
10447                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10448                                                     rss_desc, &hrxq_idx);
10449                         if (!hrxq)
10450                                 return rte_flow_error_set
10451                                         (error, rte_errno,
10452                                          RTE_FLOW_ERROR_TYPE_ACTION,
10453                                          NULL,
10454                                          "cannot create fate queue");
10455                         sample_act->dr_queue_action = hrxq->action;
10456                         sample_idx->rix_hrxq = hrxq_idx;
10457                         sample_actions[sample_act->actions_num++] =
10458                                                 hrxq->action;
10459                         (*num_of_dest)++;
10460                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10461                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10462                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10463                         dev_flow->handle->fate_action =
10464                                         MLX5_FLOW_FATE_QUEUE;
10465                         break;
10466                 }
10467                 case RTE_FLOW_ACTION_TYPE_RSS:
10468                 {
10469                         struct mlx5_hrxq *hrxq;
10470                         uint32_t hrxq_idx;
10471                         const struct rte_flow_action_rss *rss;
10472                         const uint8_t *rss_key;
10473
10474                         rss = sub_actions->conf;
10475                         memcpy(rss_desc->queue, rss->queue,
10476                                rss->queue_num * sizeof(uint16_t));
10477                         rss_desc->queue_num = rss->queue_num;
10478                         /* NULL RSS key indicates default RSS key. */
10479                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10480                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10481                         /*
10482                          * rss->level and rss.types should be set in advance
10483                          * when expanding items for RSS.
10484                          */
10485                         flow_dv_hashfields_set(dev_flow, rss_desc);
10486                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10487                                                     rss_desc, &hrxq_idx);
10488                         if (!hrxq)
10489                                 return rte_flow_error_set
10490                                         (error, rte_errno,
10491                                          RTE_FLOW_ERROR_TYPE_ACTION,
10492                                          NULL,
10493                                          "cannot create fate queue");
10494                         sample_act->dr_queue_action = hrxq->action;
10495                         sample_idx->rix_hrxq = hrxq_idx;
10496                         sample_actions[sample_act->actions_num++] =
10497                                                 hrxq->action;
10498                         (*num_of_dest)++;
10499                         action_flags |= MLX5_FLOW_ACTION_RSS;
10500                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10501                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10502                         dev_flow->handle->fate_action =
10503                                         MLX5_FLOW_FATE_QUEUE;
10504                         break;
10505                 }
10506                 case RTE_FLOW_ACTION_TYPE_MARK:
10507                 {
10508                         uint32_t tag_be = mlx5_flow_mark_set
10509                                 (((const struct rte_flow_action_mark *)
10510                                 (sub_actions->conf))->id);
10511
10512                         dev_flow->handle->mark = 1;
10513                         pre_rix = dev_flow->handle->dvh.rix_tag;
10514                         /* Save the mark resource before sample */
10515                         pre_r = dev_flow->dv.tag_resource;
10516                         if (flow_dv_tag_resource_register(dev, tag_be,
10517                                                   dev_flow, error))
10518                                 return -rte_errno;
10519                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10520                         sample_act->dr_tag_action =
10521                                 dev_flow->dv.tag_resource->action;
10522                         sample_idx->rix_tag =
10523                                 dev_flow->handle->dvh.rix_tag;
10524                         sample_actions[sample_act->actions_num++] =
10525                                                 sample_act->dr_tag_action;
10526                         /* Recover the mark resource after sample */
10527                         dev_flow->dv.tag_resource = pre_r;
10528                         dev_flow->handle->dvh.rix_tag = pre_rix;
10529                         action_flags |= MLX5_FLOW_ACTION_MARK;
10530                         break;
10531                 }
10532                 case RTE_FLOW_ACTION_TYPE_COUNT:
10533                 {
10534                         if (!flow->counter) {
10535                                 flow->counter =
10536                                         flow_dv_translate_create_counter(dev,
10537                                                 dev_flow, sub_actions->conf,
10538                                                 0);
10539                                 if (!flow->counter)
10540                                         return rte_flow_error_set
10541                                                 (error, rte_errno,
10542                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10543                                                 NULL,
10544                                                 "cannot create counter"
10545                                                 " object.");
10546                         }
10547                         sample_act->dr_cnt_action =
10548                                   (flow_dv_counter_get_by_idx(dev,
10549                                   flow->counter, NULL))->action;
10550                         sample_actions[sample_act->actions_num++] =
10551                                                 sample_act->dr_cnt_action;
10552                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10553                         break;
10554                 }
10555                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10556                 {
10557                         struct mlx5_flow_dv_port_id_action_resource
10558                                         port_id_resource;
10559                         uint32_t port_id = 0;
10560
10561                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10562                         /* Save the port id resource before sample */
10563                         pre_rix = dev_flow->handle->rix_port_id_action;
10564                         pre_r = dev_flow->dv.port_id_action;
10565                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10566                                                              &port_id, error))
10567                                 return -rte_errno;
10568                         port_id_resource.port_id = port_id;
10569                         if (flow_dv_port_id_action_resource_register
10570                             (dev, &port_id_resource, dev_flow, error))
10571                                 return -rte_errno;
10572                         sample_act->dr_port_id_action =
10573                                 dev_flow->dv.port_id_action->action;
10574                         sample_idx->rix_port_id_action =
10575                                 dev_flow->handle->rix_port_id_action;
10576                         sample_actions[sample_act->actions_num++] =
10577                                                 sample_act->dr_port_id_action;
10578                         /* Recover the port id resource after sample */
10579                         dev_flow->dv.port_id_action = pre_r;
10580                         dev_flow->handle->rix_port_id_action = pre_rix;
10581                         (*num_of_dest)++;
10582                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10583                         break;
10584                 }
10585                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10586                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10587                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10588                         /* Save the encap resource before sample */
10589                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10590                         pre_r = dev_flow->dv.encap_decap;
10591                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10592                                                            dev_flow,
10593                                                            attr->transfer,
10594                                                            error))
10595                                 return -rte_errno;
10596                         sample_act->dr_encap_action =
10597                                 dev_flow->dv.encap_decap->action;
10598                         sample_idx->rix_encap_decap =
10599                                 dev_flow->handle->dvh.rix_encap_decap;
10600                         sample_actions[sample_act->actions_num++] =
10601                                                 sample_act->dr_encap_action;
10602                         /* Recover the encap resource after sample */
10603                         dev_flow->dv.encap_decap = pre_r;
10604                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10605                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10606                         break;
10607                 default:
10608                         return rte_flow_error_set(error, EINVAL,
10609                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10610                                 NULL,
10611                                 "Not support for sampler action");
10612                 }
10613         }
10614         sample_act->action_flags = action_flags;
10615         res->ft_id = dev_flow->dv.group;
10616         if (attr->transfer) {
10617                 union {
10618                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10619                         uint64_t set_action;
10620                 } action_ctx = { .set_action = 0 };
10621
10622                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10623                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10624                          MLX5_MODIFICATION_TYPE_SET);
10625                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10626                          MLX5_MODI_META_REG_C_0);
10627                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10628                          priv->vport_meta_tag);
10629                 res->set_action = action_ctx.set_action;
10630         } else if (attr->ingress) {
10631                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10632         } else {
10633                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10634         }
10635         return 0;
10636 }
10637
10638 /**
10639  * Convert Sample action to DV specification.
10640  *
10641  * @param[in] dev
10642  *   Pointer to rte_eth_dev structure.
10643  * @param[in, out] dev_flow
10644  *   Pointer to the mlx5_flow.
10645  * @param[in] num_of_dest
10646  *   The num of destination.
10647  * @param[in, out] res
10648  *   Pointer to sample resource.
10649  * @param[in, out] mdest_res
10650  *   Pointer to destination array resource.
10651  * @param[in] sample_actions
10652  *   Pointer to sample path actions list.
10653  * @param[in] action_flags
10654  *   Holds the actions detected until now.
10655  * @param[out] error
10656  *   Pointer to the error structure.
10657  *
10658  * @return
10659  *   0 on success, a negative errno value otherwise and rte_errno is set.
10660  */
10661 static int
10662 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10663                              struct mlx5_flow *dev_flow,
10664                              uint32_t num_of_dest,
10665                              struct mlx5_flow_dv_sample_resource *res,
10666                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10667                              void **sample_actions,
10668                              uint64_t action_flags,
10669                              struct rte_flow_error *error)
10670 {
10671         /* update normal path action resource into last index of array */
10672         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10673         struct mlx5_flow_sub_actions_list *sample_act =
10674                                         &mdest_res->sample_act[dest_index];
10675         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10676         struct mlx5_flow_rss_desc *rss_desc;
10677         uint32_t normal_idx = 0;
10678         struct mlx5_hrxq *hrxq;
10679         uint32_t hrxq_idx;
10680
10681         MLX5_ASSERT(wks);
10682         rss_desc = &wks->rss_desc;
10683         if (num_of_dest > 1) {
10684                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10685                         /* Handle QP action for mirroring */
10686                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10687                                                     rss_desc, &hrxq_idx);
10688                         if (!hrxq)
10689                                 return rte_flow_error_set
10690                                      (error, rte_errno,
10691                                       RTE_FLOW_ERROR_TYPE_ACTION,
10692                                       NULL,
10693                                       "cannot create rx queue");
10694                         normal_idx++;
10695                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10696                         sample_act->dr_queue_action = hrxq->action;
10697                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10698                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10699                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10700                 }
10701                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10702                         normal_idx++;
10703                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10704                                 dev_flow->handle->dvh.rix_encap_decap;
10705                         sample_act->dr_encap_action =
10706                                 dev_flow->dv.encap_decap->action;
10707                         dev_flow->handle->dvh.rix_encap_decap = 0;
10708                 }
10709                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10710                         normal_idx++;
10711                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10712                                 dev_flow->handle->rix_port_id_action;
10713                         sample_act->dr_port_id_action =
10714                                 dev_flow->dv.port_id_action->action;
10715                         dev_flow->handle->rix_port_id_action = 0;
10716                 }
10717                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10718                         normal_idx++;
10719                         mdest_res->sample_idx[dest_index].rix_jump =
10720                                 dev_flow->handle->rix_jump;
10721                         sample_act->dr_jump_action =
10722                                 dev_flow->dv.jump->action;
10723                         dev_flow->handle->rix_jump = 0;
10724                 }
10725                 sample_act->actions_num = normal_idx;
10726                 /* update sample action resource into first index of array */
10727                 mdest_res->ft_type = res->ft_type;
10728                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10729                                 sizeof(struct mlx5_flow_sub_actions_idx));
10730                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10731                                 sizeof(struct mlx5_flow_sub_actions_list));
10732                 mdest_res->num_of_dest = num_of_dest;
10733                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10734                                                          dev_flow, error))
10735                         return rte_flow_error_set(error, EINVAL,
10736                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10737                                                   NULL, "can't create sample "
10738                                                   "action");
10739         } else {
10740                 res->sub_actions = sample_actions;
10741                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10742                         return rte_flow_error_set(error, EINVAL,
10743                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10744                                                   NULL,
10745                                                   "can't create sample action");
10746         }
10747         return 0;
10748 }
10749
10750 /**
10751  * Remove an ASO age action from age actions list.
10752  *
10753  * @param[in] dev
10754  *   Pointer to the Ethernet device structure.
10755  * @param[in] age
10756  *   Pointer to the aso age action handler.
10757  */
10758 static void
10759 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10760                                 struct mlx5_aso_age_action *age)
10761 {
10762         struct mlx5_age_info *age_info;
10763         struct mlx5_age_param *age_param = &age->age_params;
10764         struct mlx5_priv *priv = dev->data->dev_private;
10765         uint16_t expected = AGE_CANDIDATE;
10766
10767         age_info = GET_PORT_AGE_INFO(priv);
10768         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10769                                          AGE_FREE, false, __ATOMIC_RELAXED,
10770                                          __ATOMIC_RELAXED)) {
10771                 /**
10772                  * We need the lock even it is age timeout,
10773                  * since age action may still in process.
10774                  */
10775                 rte_spinlock_lock(&age_info->aged_sl);
10776                 LIST_REMOVE(age, next);
10777                 rte_spinlock_unlock(&age_info->aged_sl);
10778                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10779         }
10780 }
10781
10782 /**
10783  * Release an ASO age action.
10784  *
10785  * @param[in] dev
10786  *   Pointer to the Ethernet device structure.
10787  * @param[in] age_idx
10788  *   Index of ASO age action to release.
10789  * @param[in] flow
10790  *   True if the release operation is during flow destroy operation.
10791  *   False if the release operation is during action destroy operation.
10792  *
10793  * @return
10794  *   0 when age action was removed, otherwise the number of references.
10795  */
10796 static int
10797 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10798 {
10799         struct mlx5_priv *priv = dev->data->dev_private;
10800         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10801         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10802         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10803
10804         if (!ret) {
10805                 flow_dv_aso_age_remove_from_age(dev, age);
10806                 rte_spinlock_lock(&mng->free_sl);
10807                 LIST_INSERT_HEAD(&mng->free, age, next);
10808                 rte_spinlock_unlock(&mng->free_sl);
10809         }
10810         return ret;
10811 }
10812
10813 /**
10814  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10815  *
10816  * @param[in] dev
10817  *   Pointer to the Ethernet device structure.
10818  *
10819  * @return
10820  *   0 on success, otherwise negative errno value and rte_errno is set.
10821  */
10822 static int
10823 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10824 {
10825         struct mlx5_priv *priv = dev->data->dev_private;
10826         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10827         void *old_pools = mng->pools;
10828         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10829         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10830         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10831
10832         if (!pools) {
10833                 rte_errno = ENOMEM;
10834                 return -ENOMEM;
10835         }
10836         if (old_pools) {
10837                 memcpy(pools, old_pools,
10838                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10839                 mlx5_free(old_pools);
10840         } else {
10841                 /* First ASO flow hit allocation - starting ASO data-path. */
10842                 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
10843
10844                 if (ret) {
10845                         mlx5_free(pools);
10846                         return ret;
10847                 }
10848         }
10849         mng->n = resize;
10850         mng->pools = pools;
10851         return 0;
10852 }
10853
10854 /**
10855  * Create and initialize a new ASO aging pool.
10856  *
10857  * @param[in] dev
10858  *   Pointer to the Ethernet device structure.
10859  * @param[out] age_free
10860  *   Where to put the pointer of a new age action.
10861  *
10862  * @return
10863  *   The age actions pool pointer and @p age_free is set on success,
10864  *   NULL otherwise and rte_errno is set.
10865  */
10866 static struct mlx5_aso_age_pool *
10867 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10868                         struct mlx5_aso_age_action **age_free)
10869 {
10870         struct mlx5_priv *priv = dev->data->dev_private;
10871         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10872         struct mlx5_aso_age_pool *pool = NULL;
10873         struct mlx5_devx_obj *obj = NULL;
10874         uint32_t i;
10875
10876         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10877                                                     priv->sh->pdn);
10878         if (!obj) {
10879                 rte_errno = ENODATA;
10880                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10881                 return NULL;
10882         }
10883         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10884         if (!pool) {
10885                 claim_zero(mlx5_devx_cmd_destroy(obj));
10886                 rte_errno = ENOMEM;
10887                 return NULL;
10888         }
10889         pool->flow_hit_aso_obj = obj;
10890         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10891         rte_spinlock_lock(&mng->resize_sl);
10892         pool->index = mng->next;
10893         /* Resize pools array if there is no room for the new pool in it. */
10894         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10895                 claim_zero(mlx5_devx_cmd_destroy(obj));
10896                 mlx5_free(pool);
10897                 rte_spinlock_unlock(&mng->resize_sl);
10898                 return NULL;
10899         }
10900         mng->pools[pool->index] = pool;
10901         mng->next++;
10902         rte_spinlock_unlock(&mng->resize_sl);
10903         /* Assign the first action in the new pool, the rest go to free list. */
10904         *age_free = &pool->actions[0];
10905         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10906                 pool->actions[i].offset = i;
10907                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10908         }
10909         return pool;
10910 }
10911
10912 /**
10913  * Allocate a ASO aging bit.
10914  *
10915  * @param[in] dev
10916  *   Pointer to the Ethernet device structure.
10917  * @param[out] error
10918  *   Pointer to the error structure.
10919  *
10920  * @return
10921  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10922  */
10923 static uint32_t
10924 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10925 {
10926         struct mlx5_priv *priv = dev->data->dev_private;
10927         const struct mlx5_aso_age_pool *pool;
10928         struct mlx5_aso_age_action *age_free = NULL;
10929         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10930
10931         MLX5_ASSERT(mng);
10932         /* Try to get the next free age action bit. */
10933         rte_spinlock_lock(&mng->free_sl);
10934         age_free = LIST_FIRST(&mng->free);
10935         if (age_free) {
10936                 LIST_REMOVE(age_free, next);
10937         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10938                 rte_spinlock_unlock(&mng->free_sl);
10939                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10940                                    NULL, "failed to create ASO age pool");
10941                 return 0; /* 0 is an error. */
10942         }
10943         rte_spinlock_unlock(&mng->free_sl);
10944         pool = container_of
10945           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10946                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10947                                                                        actions);
10948         if (!age_free->dr_action) {
10949                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10950                                                  error);
10951
10952                 if (reg_c < 0) {
10953                         rte_flow_error_set(error, rte_errno,
10954                                            RTE_FLOW_ERROR_TYPE_ACTION,
10955                                            NULL, "failed to get reg_c "
10956                                            "for ASO flow hit");
10957                         return 0; /* 0 is an error. */
10958                 }
10959 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10960                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10961                                 (priv->sh->rx_domain,
10962                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10963                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10964                                  (reg_c - REG_C_0));
10965 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10966                 if (!age_free->dr_action) {
10967                         rte_errno = errno;
10968                         rte_spinlock_lock(&mng->free_sl);
10969                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10970                         rte_spinlock_unlock(&mng->free_sl);
10971                         rte_flow_error_set(error, rte_errno,
10972                                            RTE_FLOW_ERROR_TYPE_ACTION,
10973                                            NULL, "failed to create ASO "
10974                                            "flow hit action");
10975                         return 0; /* 0 is an error. */
10976                 }
10977         }
10978         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10979         return pool->index | ((age_free->offset + 1) << 16);
10980 }
10981
10982 /**
10983  * Create a age action using ASO mechanism.
10984  *
10985  * @param[in] dev
10986  *   Pointer to rte_eth_dev structure.
10987  * @param[in] age
10988  *   Pointer to the aging action configuration.
10989  * @param[out] error
10990  *   Pointer to the error structure.
10991  *
10992  * @return
10993  *   Index to flow counter on success, 0 otherwise.
10994  */
10995 static uint32_t
10996 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10997                                  const struct rte_flow_action_age *age,
10998                                  struct rte_flow_error *error)
10999 {
11000         uint32_t age_idx = 0;
11001         struct mlx5_aso_age_action *aso_age;
11002
11003         age_idx = flow_dv_aso_age_alloc(dev, error);
11004         if (!age_idx)
11005                 return 0;
11006         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11007         aso_age->age_params.context = age->context;
11008         aso_age->age_params.timeout = age->timeout;
11009         aso_age->age_params.port_id = dev->data->port_id;
11010         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11011                          __ATOMIC_RELAXED);
11012         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11013                          __ATOMIC_RELAXED);
11014         return age_idx;
11015 }
11016
11017 /**
11018  * Fill the flow with DV spec, lock free
11019  * (mutex should be acquired by caller).
11020  *
11021  * @param[in] dev
11022  *   Pointer to rte_eth_dev structure.
11023  * @param[in, out] dev_flow
11024  *   Pointer to the sub flow.
11025  * @param[in] attr
11026  *   Pointer to the flow attributes.
11027  * @param[in] items
11028  *   Pointer to the list of items.
11029  * @param[in] actions
11030  *   Pointer to the list of actions.
11031  * @param[out] error
11032  *   Pointer to the error structure.
11033  *
11034  * @return
11035  *   0 on success, a negative errno value otherwise and rte_errno is set.
11036  */
11037 static int
11038 flow_dv_translate(struct rte_eth_dev *dev,
11039                   struct mlx5_flow *dev_flow,
11040                   const struct rte_flow_attr *attr,
11041                   const struct rte_flow_item items[],
11042                   const struct rte_flow_action actions[],
11043                   struct rte_flow_error *error)
11044 {
11045         struct mlx5_priv *priv = dev->data->dev_private;
11046         struct mlx5_dev_config *dev_conf = &priv->config;
11047         struct rte_flow *flow = dev_flow->flow;
11048         struct mlx5_flow_handle *handle = dev_flow->handle;
11049         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11050         struct mlx5_flow_rss_desc *rss_desc;
11051         uint64_t item_flags = 0;
11052         uint64_t last_item = 0;
11053         uint64_t action_flags = 0;
11054         struct mlx5_flow_dv_matcher matcher = {
11055                 .mask = {
11056                         .size = sizeof(matcher.mask.buf) -
11057                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11058                 },
11059         };
11060         int actions_n = 0;
11061         bool actions_end = false;
11062         union {
11063                 struct mlx5_flow_dv_modify_hdr_resource res;
11064                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11065                             sizeof(struct mlx5_modification_cmd) *
11066                             (MLX5_MAX_MODIFY_NUM + 1)];
11067         } mhdr_dummy;
11068         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11069         const struct rte_flow_action_count *count = NULL;
11070         const struct rte_flow_action_age *age = NULL;
11071         union flow_dv_attr flow_attr = { .attr = 0 };
11072         uint32_t tag_be;
11073         union mlx5_flow_tbl_key tbl_key;
11074         uint32_t modify_action_position = UINT32_MAX;
11075         void *match_mask = matcher.mask.buf;
11076         void *match_value = dev_flow->dv.value.buf;
11077         uint8_t next_protocol = 0xff;
11078         struct rte_vlan_hdr vlan = { 0 };
11079         struct mlx5_flow_dv_dest_array_resource mdest_res;
11080         struct mlx5_flow_dv_sample_resource sample_res;
11081         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11082         const struct rte_flow_action_sample *sample = NULL;
11083         struct mlx5_flow_sub_actions_list *sample_act;
11084         uint32_t sample_act_pos = UINT32_MAX;
11085         uint32_t num_of_dest = 0;
11086         int tmp_actions_n = 0;
11087         uint32_t table;
11088         int ret = 0;
11089         const struct mlx5_flow_tunnel *tunnel;
11090         struct flow_grp_info grp_info = {
11091                 .external = !!dev_flow->external,
11092                 .transfer = !!attr->transfer,
11093                 .fdb_def_rule = !!priv->fdb_def_rule,
11094                 .skip_scale = dev_flow->skip_scale &
11095                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11096         };
11097
11098         if (!wks)
11099                 return rte_flow_error_set(error, ENOMEM,
11100                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11101                                           NULL,
11102                                           "failed to push flow workspace");
11103         rss_desc = &wks->rss_desc;
11104         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11105         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11106         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11107                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11108         /* update normal path action resource into last index of array */
11109         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11110         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11111                  flow_items_to_tunnel(items) :
11112                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11113                  flow_actions_to_tunnel(actions) :
11114                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
11115         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11116                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11117         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11118                                 (dev, tunnel, attr, items, actions);
11119         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11120                                        &grp_info, error);
11121         if (ret)
11122                 return ret;
11123         dev_flow->dv.group = table;
11124         if (attr->transfer)
11125                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11126         /* number of actions must be set to 0 in case of dirty stack. */
11127         mhdr_res->actions_num = 0;
11128         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11129                 /*
11130                  * do not add decap action if match rule drops packet
11131                  * HW rejects rules with decap & drop
11132                  *
11133                  * if tunnel match rule was inserted before matching tunnel set
11134                  * rule flow table used in the match rule must be registered.
11135                  * current implementation handles that in the
11136                  * flow_dv_match_register() at the function end.
11137                  */
11138                 bool add_decap = true;
11139                 const struct rte_flow_action *ptr = actions;
11140
11141                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11142                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11143                                 add_decap = false;
11144                                 break;
11145                         }
11146                 }
11147                 if (add_decap) {
11148                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11149                                                            attr->transfer,
11150                                                            error))
11151                                 return -rte_errno;
11152                         dev_flow->dv.actions[actions_n++] =
11153                                         dev_flow->dv.encap_decap->action;
11154                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11155                 }
11156         }
11157         for (; !actions_end ; actions++) {
11158                 const struct rte_flow_action_queue *queue;
11159                 const struct rte_flow_action_rss *rss;
11160                 const struct rte_flow_action *action = actions;
11161                 const uint8_t *rss_key;
11162                 struct mlx5_flow_tbl_resource *tbl;
11163                 struct mlx5_aso_age_action *age_act;
11164                 uint32_t port_id = 0;
11165                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11166                 int action_type = actions->type;
11167                 const struct rte_flow_action *found_action = NULL;
11168                 uint32_t jump_group = 0;
11169
11170                 if (!mlx5_flow_os_action_supported(action_type))
11171                         return rte_flow_error_set(error, ENOTSUP,
11172                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11173                                                   actions,
11174                                                   "action not supported");
11175                 switch (action_type) {
11176                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11177                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11178                         break;
11179                 case RTE_FLOW_ACTION_TYPE_VOID:
11180                         break;
11181                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11182                         if (flow_dv_translate_action_port_id(dev, action,
11183                                                              &port_id, error))
11184                                 return -rte_errno;
11185                         port_id_resource.port_id = port_id;
11186                         MLX5_ASSERT(!handle->rix_port_id_action);
11187                         if (flow_dv_port_id_action_resource_register
11188                             (dev, &port_id_resource, dev_flow, error))
11189                                 return -rte_errno;
11190                         dev_flow->dv.actions[actions_n++] =
11191                                         dev_flow->dv.port_id_action->action;
11192                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11193                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11194                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11195                         num_of_dest++;
11196                         break;
11197                 case RTE_FLOW_ACTION_TYPE_FLAG:
11198                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11199                         dev_flow->handle->mark = 1;
11200                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11201                                 struct rte_flow_action_mark mark = {
11202                                         .id = MLX5_FLOW_MARK_DEFAULT,
11203                                 };
11204
11205                                 if (flow_dv_convert_action_mark(dev, &mark,
11206                                                                 mhdr_res,
11207                                                                 error))
11208                                         return -rte_errno;
11209                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11210                                 break;
11211                         }
11212                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11213                         /*
11214                          * Only one FLAG or MARK is supported per device flow
11215                          * right now. So the pointer to the tag resource must be
11216                          * zero before the register process.
11217                          */
11218                         MLX5_ASSERT(!handle->dvh.rix_tag);
11219                         if (flow_dv_tag_resource_register(dev, tag_be,
11220                                                           dev_flow, error))
11221                                 return -rte_errno;
11222                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11223                         dev_flow->dv.actions[actions_n++] =
11224                                         dev_flow->dv.tag_resource->action;
11225                         break;
11226                 case RTE_FLOW_ACTION_TYPE_MARK:
11227                         action_flags |= MLX5_FLOW_ACTION_MARK;
11228                         dev_flow->handle->mark = 1;
11229                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11230                                 const struct rte_flow_action_mark *mark =
11231                                         (const struct rte_flow_action_mark *)
11232                                                 actions->conf;
11233
11234                                 if (flow_dv_convert_action_mark(dev, mark,
11235                                                                 mhdr_res,
11236                                                                 error))
11237                                         return -rte_errno;
11238                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11239                                 break;
11240                         }
11241                         /* Fall-through */
11242                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11243                         /* Legacy (non-extensive) MARK action. */
11244                         tag_be = mlx5_flow_mark_set
11245                               (((const struct rte_flow_action_mark *)
11246                                (actions->conf))->id);
11247                         MLX5_ASSERT(!handle->dvh.rix_tag);
11248                         if (flow_dv_tag_resource_register(dev, tag_be,
11249                                                           dev_flow, error))
11250                                 return -rte_errno;
11251                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11252                         dev_flow->dv.actions[actions_n++] =
11253                                         dev_flow->dv.tag_resource->action;
11254                         break;
11255                 case RTE_FLOW_ACTION_TYPE_SET_META:
11256                         if (flow_dv_convert_action_set_meta
11257                                 (dev, mhdr_res, attr,
11258                                  (const struct rte_flow_action_set_meta *)
11259                                   actions->conf, error))
11260                                 return -rte_errno;
11261                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11262                         break;
11263                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11264                         if (flow_dv_convert_action_set_tag
11265                                 (dev, mhdr_res,
11266                                  (const struct rte_flow_action_set_tag *)
11267                                   actions->conf, error))
11268                                 return -rte_errno;
11269                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11270                         break;
11271                 case RTE_FLOW_ACTION_TYPE_DROP:
11272                         action_flags |= MLX5_FLOW_ACTION_DROP;
11273                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11274                         break;
11275                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11276                         queue = actions->conf;
11277                         rss_desc->queue_num = 1;
11278                         rss_desc->queue[0] = queue->index;
11279                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11280                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11281                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11282                         num_of_dest++;
11283                         break;
11284                 case RTE_FLOW_ACTION_TYPE_RSS:
11285                         rss = actions->conf;
11286                         memcpy(rss_desc->queue, rss->queue,
11287                                rss->queue_num * sizeof(uint16_t));
11288                         rss_desc->queue_num = rss->queue_num;
11289                         /* NULL RSS key indicates default RSS key. */
11290                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11291                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11292                         /*
11293                          * rss->level and rss.types should be set in advance
11294                          * when expanding items for RSS.
11295                          */
11296                         action_flags |= MLX5_FLOW_ACTION_RSS;
11297                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11298                                 MLX5_FLOW_FATE_SHARED_RSS :
11299                                 MLX5_FLOW_FATE_QUEUE;
11300                         break;
11301                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11302                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11303                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11304                         __atomic_fetch_add(&age_act->refcnt, 1,
11305                                            __ATOMIC_RELAXED);
11306                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11307                         action_flags |= MLX5_FLOW_ACTION_AGE;
11308                         break;
11309                 case RTE_FLOW_ACTION_TYPE_AGE:
11310                         if (priv->sh->flow_hit_aso_en && attr->group) {
11311                                 /*
11312                                  * Create one shared age action, to be used
11313                                  * by all sub-flows.
11314                                  */
11315                                 if (!flow->age) {
11316                                         flow->age =
11317                                                 flow_dv_translate_create_aso_age
11318                                                         (dev, action->conf,
11319                                                          error);
11320                                         if (!flow->age)
11321                                                 return rte_flow_error_set
11322                                                 (error, rte_errno,
11323                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11324                                                  NULL,
11325                                                  "can't create ASO age action");
11326                                 }
11327                                 dev_flow->dv.actions[actions_n++] =
11328                                           (flow_aso_age_get_by_idx
11329                                                 (dev, flow->age))->dr_action;
11330                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11331                                 break;
11332                         }
11333                         /* Fall-through */
11334                 case RTE_FLOW_ACTION_TYPE_COUNT:
11335                         if (!dev_conf->devx) {
11336                                 return rte_flow_error_set
11337                                               (error, ENOTSUP,
11338                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11339                                                NULL,
11340                                                "count action not supported");
11341                         }
11342                         /* Save information first, will apply later. */
11343                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11344                                 count = action->conf;
11345                         else
11346                                 age = action->conf;
11347                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11348                         break;
11349                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11350                         dev_flow->dv.actions[actions_n++] =
11351                                                 priv->sh->pop_vlan_action;
11352                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11353                         break;
11354                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11355                         if (!(action_flags &
11356                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11357                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11358                         vlan.eth_proto = rte_be_to_cpu_16
11359                              ((((const struct rte_flow_action_of_push_vlan *)
11360                                                    actions->conf)->ethertype));
11361                         found_action = mlx5_flow_find_action
11362                                         (actions + 1,
11363                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11364                         if (found_action)
11365                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11366                         found_action = mlx5_flow_find_action
11367                                         (actions + 1,
11368                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11369                         if (found_action)
11370                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11371                         if (flow_dv_create_action_push_vlan
11372                                             (dev, attr, &vlan, dev_flow, error))
11373                                 return -rte_errno;
11374                         dev_flow->dv.actions[actions_n++] =
11375                                         dev_flow->dv.push_vlan_res->action;
11376                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11377                         break;
11378                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11379                         /* of_vlan_push action handled this action */
11380                         MLX5_ASSERT(action_flags &
11381                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11382                         break;
11383                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11384                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11385                                 break;
11386                         flow_dev_get_vlan_info_from_items(items, &vlan);
11387                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11388                         /* If no VLAN push - this is a modify header action */
11389                         if (flow_dv_convert_action_modify_vlan_vid
11390                                                 (mhdr_res, actions, error))
11391                                 return -rte_errno;
11392                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11393                         break;
11394                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11395                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11396                         if (flow_dv_create_action_l2_encap(dev, actions,
11397                                                            dev_flow,
11398                                                            attr->transfer,
11399                                                            error))
11400                                 return -rte_errno;
11401                         dev_flow->dv.actions[actions_n++] =
11402                                         dev_flow->dv.encap_decap->action;
11403                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11404                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11405                                 sample_act->action_flags |=
11406                                                         MLX5_FLOW_ACTION_ENCAP;
11407                         break;
11408                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11409                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11410                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11411                                                            attr->transfer,
11412                                                            error))
11413                                 return -rte_errno;
11414                         dev_flow->dv.actions[actions_n++] =
11415                                         dev_flow->dv.encap_decap->action;
11416                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11417                         break;
11418                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11419                         /* Handle encap with preceding decap. */
11420                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11421                                 if (flow_dv_create_action_raw_encap
11422                                         (dev, actions, dev_flow, attr, error))
11423                                         return -rte_errno;
11424                                 dev_flow->dv.actions[actions_n++] =
11425                                         dev_flow->dv.encap_decap->action;
11426                         } else {
11427                                 /* Handle encap without preceding decap. */
11428                                 if (flow_dv_create_action_l2_encap
11429                                     (dev, actions, dev_flow, attr->transfer,
11430                                      error))
11431                                         return -rte_errno;
11432                                 dev_flow->dv.actions[actions_n++] =
11433                                         dev_flow->dv.encap_decap->action;
11434                         }
11435                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11436                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11437                                 sample_act->action_flags |=
11438                                                         MLX5_FLOW_ACTION_ENCAP;
11439                         break;
11440                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11441                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11442                                 ;
11443                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11444                                 if (flow_dv_create_action_l2_decap
11445                                     (dev, dev_flow, attr->transfer, error))
11446                                         return -rte_errno;
11447                                 dev_flow->dv.actions[actions_n++] =
11448                                         dev_flow->dv.encap_decap->action;
11449                         }
11450                         /* If decap is followed by encap, handle it at encap. */
11451                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11452                         break;
11453                 case RTE_FLOW_ACTION_TYPE_JUMP:
11454                         jump_group = ((const struct rte_flow_action_jump *)
11455                                                         action->conf)->group;
11456                         grp_info.std_tbl_fix = 0;
11457                         if (dev_flow->skip_scale &
11458                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11459                                 grp_info.skip_scale = 1;
11460                         else
11461                                 grp_info.skip_scale = 0;
11462                         ret = mlx5_flow_group_to_table(dev, tunnel,
11463                                                        jump_group,
11464                                                        &table,
11465                                                        &grp_info, error);
11466                         if (ret)
11467                                 return ret;
11468                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11469                                                        attr->transfer,
11470                                                        !!dev_flow->external,
11471                                                        tunnel, jump_group, 0,
11472                                                        error);
11473                         if (!tbl)
11474                                 return rte_flow_error_set
11475                                                 (error, errno,
11476                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11477                                                  NULL,
11478                                                  "cannot create jump action.");
11479                         if (flow_dv_jump_tbl_resource_register
11480                             (dev, tbl, dev_flow, error)) {
11481                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11482                                 return rte_flow_error_set
11483                                                 (error, errno,
11484                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11485                                                  NULL,
11486                                                  "cannot create jump action.");
11487                         }
11488                         dev_flow->dv.actions[actions_n++] =
11489                                         dev_flow->dv.jump->action;
11490                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11491                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11492                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11493                         num_of_dest++;
11494                         break;
11495                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11496                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11497                         if (flow_dv_convert_action_modify_mac
11498                                         (mhdr_res, actions, error))
11499                                 return -rte_errno;
11500                         action_flags |= actions->type ==
11501                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11502                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11503                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11504                         break;
11505                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11506                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11507                         if (flow_dv_convert_action_modify_ipv4
11508                                         (mhdr_res, actions, error))
11509                                 return -rte_errno;
11510                         action_flags |= actions->type ==
11511                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11512                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11513                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11514                         break;
11515                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11516                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11517                         if (flow_dv_convert_action_modify_ipv6
11518                                         (mhdr_res, actions, error))
11519                                 return -rte_errno;
11520                         action_flags |= actions->type ==
11521                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11522                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11523                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11524                         break;
11525                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11526                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11527                         if (flow_dv_convert_action_modify_tp
11528                                         (mhdr_res, actions, items,
11529                                          &flow_attr, dev_flow, !!(action_flags &
11530                                          MLX5_FLOW_ACTION_DECAP), error))
11531                                 return -rte_errno;
11532                         action_flags |= actions->type ==
11533                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11534                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11535                                         MLX5_FLOW_ACTION_SET_TP_DST;
11536                         break;
11537                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11538                         if (flow_dv_convert_action_modify_dec_ttl
11539                                         (mhdr_res, items, &flow_attr, dev_flow,
11540                                          !!(action_flags &
11541                                          MLX5_FLOW_ACTION_DECAP), error))
11542                                 return -rte_errno;
11543                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11544                         break;
11545                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11546                         if (flow_dv_convert_action_modify_ttl
11547                                         (mhdr_res, actions, items, &flow_attr,
11548                                          dev_flow, !!(action_flags &
11549                                          MLX5_FLOW_ACTION_DECAP), error))
11550                                 return -rte_errno;
11551                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11552                         break;
11553                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11554                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11555                         if (flow_dv_convert_action_modify_tcp_seq
11556                                         (mhdr_res, actions, error))
11557                                 return -rte_errno;
11558                         action_flags |= actions->type ==
11559                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11560                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11561                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11562                         break;
11563
11564                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11565                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11566                         if (flow_dv_convert_action_modify_tcp_ack
11567                                         (mhdr_res, actions, error))
11568                                 return -rte_errno;
11569                         action_flags |= actions->type ==
11570                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11571                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11572                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11573                         break;
11574                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11575                         if (flow_dv_convert_action_set_reg
11576                                         (mhdr_res, actions, error))
11577                                 return -rte_errno;
11578                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11579                         break;
11580                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11581                         if (flow_dv_convert_action_copy_mreg
11582                                         (dev, mhdr_res, actions, error))
11583                                 return -rte_errno;
11584                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11585                         break;
11586                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11587                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11588                         dev_flow->handle->fate_action =
11589                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11590                         break;
11591                 case RTE_FLOW_ACTION_TYPE_METER:
11592                         if (!wks->fm)
11593                                 return rte_flow_error_set(error, rte_errno,
11594                                         RTE_FLOW_ERROR_TYPE_ACTION,
11595                                         NULL, "Failed to get meter in flow.");
11596                         /* Set the meter action. */
11597                         dev_flow->dv.actions[actions_n++] =
11598                                 wks->fm->mfts->meter_action;
11599                         action_flags |= MLX5_FLOW_ACTION_METER;
11600                         break;
11601                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11602                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11603                                                               actions, error))
11604                                 return -rte_errno;
11605                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11606                         break;
11607                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11608                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11609                                                               actions, error))
11610                                 return -rte_errno;
11611                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11612                         break;
11613                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11614                         sample_act_pos = actions_n;
11615                         sample = (const struct rte_flow_action_sample *)
11616                                  action->conf;
11617                         actions_n++;
11618                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11619                         /* put encap action into group if work with port id */
11620                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11621                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11622                                 sample_act->action_flags |=
11623                                                         MLX5_FLOW_ACTION_ENCAP;
11624                         break;
11625                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11626                         if (flow_dv_convert_action_modify_field
11627                                         (dev, mhdr_res, actions, attr, error))
11628                                 return -rte_errno;
11629                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11630                         break;
11631                 case RTE_FLOW_ACTION_TYPE_END:
11632                         actions_end = true;
11633                         if (mhdr_res->actions_num) {
11634                                 /* create modify action if needed. */
11635                                 if (flow_dv_modify_hdr_resource_register
11636                                         (dev, mhdr_res, dev_flow, error))
11637                                         return -rte_errno;
11638                                 dev_flow->dv.actions[modify_action_position] =
11639                                         handle->dvh.modify_hdr->action;
11640                         }
11641                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11642                                 /*
11643                                  * Create one count action, to be used
11644                                  * by all sub-flows.
11645                                  */
11646                                 if (!flow->counter) {
11647                                         flow->counter =
11648                                                 flow_dv_translate_create_counter
11649                                                         (dev, dev_flow, count,
11650                                                          age);
11651                                         if (!flow->counter)
11652                                                 return rte_flow_error_set
11653                                                 (error, rte_errno,
11654                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11655                                                  NULL, "cannot create counter"
11656                                                  " object.");
11657                                 }
11658                                 dev_flow->dv.actions[actions_n] =
11659                                           (flow_dv_counter_get_by_idx(dev,
11660                                           flow->counter, NULL))->action;
11661                                 actions_n++;
11662                         }
11663                 default:
11664                         break;
11665                 }
11666                 if (mhdr_res->actions_num &&
11667                     modify_action_position == UINT32_MAX)
11668                         modify_action_position = actions_n++;
11669         }
11670         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11671                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11672                 int item_type = items->type;
11673
11674                 if (!mlx5_flow_os_item_supported(item_type))
11675                         return rte_flow_error_set(error, ENOTSUP,
11676                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11677                                                   NULL, "item not supported");
11678                 switch (item_type) {
11679                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11680                         flow_dv_translate_item_port_id
11681                                 (dev, match_mask, match_value, items, attr);
11682                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11683                         break;
11684                 case RTE_FLOW_ITEM_TYPE_ETH:
11685                         flow_dv_translate_item_eth(match_mask, match_value,
11686                                                    items, tunnel,
11687                                                    dev_flow->dv.group);
11688                         matcher.priority = action_flags &
11689                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11690                                         !dev_flow->external ?
11691                                         MLX5_PRIORITY_MAP_L3 :
11692                                         MLX5_PRIORITY_MAP_L2;
11693                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11694                                              MLX5_FLOW_LAYER_OUTER_L2;
11695                         break;
11696                 case RTE_FLOW_ITEM_TYPE_VLAN:
11697                         flow_dv_translate_item_vlan(dev_flow,
11698                                                     match_mask, match_value,
11699                                                     items, tunnel,
11700                                                     dev_flow->dv.group);
11701                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11702                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11703                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11704                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11705                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11706                         break;
11707                 case RTE_FLOW_ITEM_TYPE_IPV4:
11708                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11709                                                   &item_flags, &tunnel);
11710                         flow_dv_translate_item_ipv4(match_mask, match_value,
11711                                                     items, tunnel,
11712                                                     dev_flow->dv.group);
11713                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11714                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11715                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11716                         if (items->mask != NULL &&
11717                             ((const struct rte_flow_item_ipv4 *)
11718                              items->mask)->hdr.next_proto_id) {
11719                                 next_protocol =
11720                                         ((const struct rte_flow_item_ipv4 *)
11721                                          (items->spec))->hdr.next_proto_id;
11722                                 next_protocol &=
11723                                         ((const struct rte_flow_item_ipv4 *)
11724                                          (items->mask))->hdr.next_proto_id;
11725                         } else {
11726                                 /* Reset for inner layer. */
11727                                 next_protocol = 0xff;
11728                         }
11729                         break;
11730                 case RTE_FLOW_ITEM_TYPE_IPV6:
11731                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11732                                                   &item_flags, &tunnel);
11733                         flow_dv_translate_item_ipv6(match_mask, match_value,
11734                                                     items, tunnel,
11735                                                     dev_flow->dv.group);
11736                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11737                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11738                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11739                         if (items->mask != NULL &&
11740                             ((const struct rte_flow_item_ipv6 *)
11741                              items->mask)->hdr.proto) {
11742                                 next_protocol =
11743                                         ((const struct rte_flow_item_ipv6 *)
11744                                          items->spec)->hdr.proto;
11745                                 next_protocol &=
11746                                         ((const struct rte_flow_item_ipv6 *)
11747                                          items->mask)->hdr.proto;
11748                         } else {
11749                                 /* Reset for inner layer. */
11750                                 next_protocol = 0xff;
11751                         }
11752                         break;
11753                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11754                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11755                                                              match_value,
11756                                                              items, tunnel);
11757                         last_item = tunnel ?
11758                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11759                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11760                         if (items->mask != NULL &&
11761                             ((const struct rte_flow_item_ipv6_frag_ext *)
11762                              items->mask)->hdr.next_header) {
11763                                 next_protocol =
11764                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11765                                  items->spec)->hdr.next_header;
11766                                 next_protocol &=
11767                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11768                                  items->mask)->hdr.next_header;
11769                         } else {
11770                                 /* Reset for inner layer. */
11771                                 next_protocol = 0xff;
11772                         }
11773                         break;
11774                 case RTE_FLOW_ITEM_TYPE_TCP:
11775                         flow_dv_translate_item_tcp(match_mask, match_value,
11776                                                    items, tunnel);
11777                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11778                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11779                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11780                         break;
11781                 case RTE_FLOW_ITEM_TYPE_UDP:
11782                         flow_dv_translate_item_udp(match_mask, match_value,
11783                                                    items, tunnel);
11784                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11785                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11786                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11787                         break;
11788                 case RTE_FLOW_ITEM_TYPE_GRE:
11789                         flow_dv_translate_item_gre(match_mask, match_value,
11790                                                    items, tunnel);
11791                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11792                         last_item = MLX5_FLOW_LAYER_GRE;
11793                         break;
11794                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11795                         flow_dv_translate_item_gre_key(match_mask,
11796                                                        match_value, items);
11797                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11798                         break;
11799                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11800                         flow_dv_translate_item_nvgre(match_mask, match_value,
11801                                                      items, tunnel);
11802                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11803                         last_item = MLX5_FLOW_LAYER_GRE;
11804                         break;
11805                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11806                         flow_dv_translate_item_vxlan(match_mask, match_value,
11807                                                      items, tunnel);
11808                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11809                         last_item = MLX5_FLOW_LAYER_VXLAN;
11810                         break;
11811                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11812                         flow_dv_translate_item_vxlan_gpe(match_mask,
11813                                                          match_value, items,
11814                                                          tunnel);
11815                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11816                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11817                         break;
11818                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11819                         flow_dv_translate_item_geneve(match_mask, match_value,
11820                                                       items, tunnel);
11821                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11822                         last_item = MLX5_FLOW_LAYER_GENEVE;
11823                         break;
11824                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11825                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11826                                                           match_value,
11827                                                           items, error);
11828                         if (ret)
11829                                 return rte_flow_error_set(error, -ret,
11830                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11831                                         "cannot create GENEVE TLV option");
11832                         flow->geneve_tlv_option = 1;
11833                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11834                         break;
11835                 case RTE_FLOW_ITEM_TYPE_MPLS:
11836                         flow_dv_translate_item_mpls(match_mask, match_value,
11837                                                     items, last_item, tunnel);
11838                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11839                         last_item = MLX5_FLOW_LAYER_MPLS;
11840                         break;
11841                 case RTE_FLOW_ITEM_TYPE_MARK:
11842                         flow_dv_translate_item_mark(dev, match_mask,
11843                                                     match_value, items);
11844                         last_item = MLX5_FLOW_ITEM_MARK;
11845                         break;
11846                 case RTE_FLOW_ITEM_TYPE_META:
11847                         flow_dv_translate_item_meta(dev, match_mask,
11848                                                     match_value, attr, items);
11849                         last_item = MLX5_FLOW_ITEM_METADATA;
11850                         break;
11851                 case RTE_FLOW_ITEM_TYPE_ICMP:
11852                         flow_dv_translate_item_icmp(match_mask, match_value,
11853                                                     items, tunnel);
11854                         last_item = MLX5_FLOW_LAYER_ICMP;
11855                         break;
11856                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11857                         flow_dv_translate_item_icmp6(match_mask, match_value,
11858                                                       items, tunnel);
11859                         last_item = MLX5_FLOW_LAYER_ICMP6;
11860                         break;
11861                 case RTE_FLOW_ITEM_TYPE_TAG:
11862                         flow_dv_translate_item_tag(dev, match_mask,
11863                                                    match_value, items);
11864                         last_item = MLX5_FLOW_ITEM_TAG;
11865                         break;
11866                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11867                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11868                                                         match_value, items);
11869                         last_item = MLX5_FLOW_ITEM_TAG;
11870                         break;
11871                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11872                         flow_dv_translate_item_tx_queue(dev, match_mask,
11873                                                         match_value,
11874                                                         items);
11875                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11876                         break;
11877                 case RTE_FLOW_ITEM_TYPE_GTP:
11878                         flow_dv_translate_item_gtp(match_mask, match_value,
11879                                                    items, tunnel);
11880                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11881                         last_item = MLX5_FLOW_LAYER_GTP;
11882                         break;
11883                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11884                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11885                                                           match_value,
11886                                                           items);
11887                         if (ret)
11888                                 return rte_flow_error_set(error, -ret,
11889                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11890                                         "cannot create GTP PSC item");
11891                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11892                         break;
11893                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11894                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11895                                 /* Create it only the first time to be used. */
11896                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11897                                 if (ret)
11898                                         return rte_flow_error_set
11899                                                 (error, -ret,
11900                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11901                                                 NULL,
11902                                                 "cannot create eCPRI parser");
11903                         }
11904                         /* Adjust the length matcher and device flow value. */
11905                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11906                         dev_flow->dv.value.size =
11907                                         MLX5_ST_SZ_BYTES(fte_match_param);
11908                         flow_dv_translate_item_ecpri(dev, match_mask,
11909                                                      match_value, items);
11910                         /* No other protocol should follow eCPRI layer. */
11911                         last_item = MLX5_FLOW_LAYER_ECPRI;
11912                         break;
11913                 default:
11914                         break;
11915                 }
11916                 item_flags |= last_item;
11917         }
11918         /*
11919          * When E-Switch mode is enabled, we have two cases where we need to
11920          * set the source port manually.
11921          * The first one, is in case of Nic steering rule, and the second is
11922          * E-Switch rule where no port_id item was found. In both cases
11923          * the source port is set according the current port in use.
11924          */
11925         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11926             (priv->representor || priv->master)) {
11927                 if (flow_dv_translate_item_port_id(dev, match_mask,
11928                                                    match_value, NULL, attr))
11929                         return -rte_errno;
11930         }
11931 #ifdef RTE_LIBRTE_MLX5_DEBUG
11932         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11933                                               dev_flow->dv.value.buf));
11934 #endif
11935         /*
11936          * Layers may be already initialized from prefix flow if this dev_flow
11937          * is the suffix flow.
11938          */
11939         handle->layers |= item_flags;
11940         if (action_flags & MLX5_FLOW_ACTION_RSS)
11941                 flow_dv_hashfields_set(dev_flow, rss_desc);
11942         /* If has RSS action in the sample action, the Sample/Mirror resource
11943          * should be registered after the hash filed be update.
11944          */
11945         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11946                 ret = flow_dv_translate_action_sample(dev,
11947                                                       sample,
11948                                                       dev_flow, attr,
11949                                                       &num_of_dest,
11950                                                       sample_actions,
11951                                                       &sample_res,
11952                                                       error);
11953                 if (ret < 0)
11954                         return ret;
11955                 ret = flow_dv_create_action_sample(dev,
11956                                                    dev_flow,
11957                                                    num_of_dest,
11958                                                    &sample_res,
11959                                                    &mdest_res,
11960                                                    sample_actions,
11961                                                    action_flags,
11962                                                    error);
11963                 if (ret < 0)
11964                         return rte_flow_error_set
11965                                                 (error, rte_errno,
11966                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11967                                                 NULL,
11968                                                 "cannot create sample action");
11969                 if (num_of_dest > 1) {
11970                         dev_flow->dv.actions[sample_act_pos] =
11971                         dev_flow->dv.dest_array_res->action;
11972                 } else {
11973                         dev_flow->dv.actions[sample_act_pos] =
11974                         dev_flow->dv.sample_res->verbs_action;
11975                 }
11976         }
11977         /*
11978          * For multiple destination (sample action with ratio=1), the encap
11979          * action and port id action will be combined into group action.
11980          * So need remove the original these actions in the flow and only
11981          * use the sample action instead of.
11982          */
11983         if (num_of_dest > 1 &&
11984             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11985                 int i;
11986                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11987
11988                 for (i = 0; i < actions_n; i++) {
11989                         if ((sample_act->dr_encap_action &&
11990                                 sample_act->dr_encap_action ==
11991                                 dev_flow->dv.actions[i]) ||
11992                                 (sample_act->dr_port_id_action &&
11993                                 sample_act->dr_port_id_action ==
11994                                 dev_flow->dv.actions[i]) ||
11995                                 (sample_act->dr_jump_action &&
11996                                 sample_act->dr_jump_action ==
11997                                 dev_flow->dv.actions[i]))
11998                                 continue;
11999                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12000                 }
12001                 memcpy((void *)dev_flow->dv.actions,
12002                                 (void *)temp_actions,
12003                                 tmp_actions_n * sizeof(void *));
12004                 actions_n = tmp_actions_n;
12005         }
12006         dev_flow->dv.actions_n = actions_n;
12007         dev_flow->act_flags = action_flags;
12008         /* Register matcher. */
12009         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12010                                     matcher.mask.size);
12011         matcher.priority = mlx5_get_matcher_priority(dev, attr,
12012                                         matcher.priority);
12013         /* reserved field no needs to be set to 0 here. */
12014         tbl_key.domain = attr->transfer;
12015         tbl_key.direction = attr->egress;
12016         tbl_key.table_id = dev_flow->dv.group;
12017         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12018                                      tunnel, attr->group, error))
12019                 return -rte_errno;
12020         return 0;
12021 }
12022
12023 /**
12024  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12025  * and tunnel.
12026  *
12027  * @param[in, out] action
12028  *   Shred RSS action holding hash RX queue objects.
12029  * @param[in] hash_fields
12030  *   Defines combination of packet fields to participate in RX hash.
12031  * @param[in] tunnel
12032  *   Tunnel type
12033  * @param[in] hrxq_idx
12034  *   Hash RX queue index to set.
12035  *
12036  * @return
12037  *   0 on success, otherwise negative errno value.
12038  */
12039 static int
12040 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12041                               const uint64_t hash_fields,
12042                               uint32_t hrxq_idx)
12043 {
12044         uint32_t *hrxqs = action->hrxq;
12045
12046         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12047         case MLX5_RSS_HASH_IPV4:
12048                 /* fall-through. */
12049         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12050                 /* fall-through. */
12051         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12052                 hrxqs[0] = hrxq_idx;
12053                 return 0;
12054         case MLX5_RSS_HASH_IPV4_TCP:
12055                 /* fall-through. */
12056         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12057                 /* fall-through. */
12058         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12059                 hrxqs[1] = hrxq_idx;
12060                 return 0;
12061         case MLX5_RSS_HASH_IPV4_UDP:
12062                 /* fall-through. */
12063         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12064                 /* fall-through. */
12065         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12066                 hrxqs[2] = hrxq_idx;
12067                 return 0;
12068         case MLX5_RSS_HASH_IPV6:
12069                 /* fall-through. */
12070         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12071                 /* fall-through. */
12072         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12073                 hrxqs[3] = hrxq_idx;
12074                 return 0;
12075         case MLX5_RSS_HASH_IPV6_TCP:
12076                 /* fall-through. */
12077         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12078                 /* fall-through. */
12079         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12080                 hrxqs[4] = hrxq_idx;
12081                 return 0;
12082         case MLX5_RSS_HASH_IPV6_UDP:
12083                 /* fall-through. */
12084         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12085                 /* fall-through. */
12086         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12087                 hrxqs[5] = hrxq_idx;
12088                 return 0;
12089         case MLX5_RSS_HASH_NONE:
12090                 hrxqs[6] = hrxq_idx;
12091                 return 0;
12092         default:
12093                 return -1;
12094         }
12095 }
12096
12097 /**
12098  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12099  * and tunnel.
12100  *
12101  * @param[in] dev
12102  *   Pointer to the Ethernet device structure.
12103  * @param[in] idx
12104  *   Shared RSS action ID holding hash RX queue objects.
12105  * @param[in] hash_fields
12106  *   Defines combination of packet fields to participate in RX hash.
12107  * @param[in] tunnel
12108  *   Tunnel type
12109  *
12110  * @return
12111  *   Valid hash RX queue index, otherwise 0.
12112  */
12113 static uint32_t
12114 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12115                                  const uint64_t hash_fields)
12116 {
12117         struct mlx5_priv *priv = dev->data->dev_private;
12118         struct mlx5_shared_action_rss *shared_rss =
12119             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12120         const uint32_t *hrxqs = shared_rss->hrxq;
12121
12122         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12123         case MLX5_RSS_HASH_IPV4:
12124                 /* fall-through. */
12125         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12126                 /* fall-through. */
12127         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12128                 return hrxqs[0];
12129         case MLX5_RSS_HASH_IPV4_TCP:
12130                 /* fall-through. */
12131         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12132                 /* fall-through. */
12133         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12134                 return hrxqs[1];
12135         case MLX5_RSS_HASH_IPV4_UDP:
12136                 /* fall-through. */
12137         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12138                 /* fall-through. */
12139         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12140                 return hrxqs[2];
12141         case MLX5_RSS_HASH_IPV6:
12142                 /* fall-through. */
12143         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12144                 /* fall-through. */
12145         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12146                 return hrxqs[3];
12147         case MLX5_RSS_HASH_IPV6_TCP:
12148                 /* fall-through. */
12149         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12150                 /* fall-through. */
12151         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12152                 return hrxqs[4];
12153         case MLX5_RSS_HASH_IPV6_UDP:
12154                 /* fall-through. */
12155         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12156                 /* fall-through. */
12157         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12158                 return hrxqs[5];
12159         case MLX5_RSS_HASH_NONE:
12160                 return hrxqs[6];
12161         default:
12162                 return 0;
12163         }
12164
12165 }
12166
12167 /**
12168  * Apply the flow to the NIC, lock free,
12169  * (mutex should be acquired by caller).
12170  *
12171  * @param[in] dev
12172  *   Pointer to the Ethernet device structure.
12173  * @param[in, out] flow
12174  *   Pointer to flow structure.
12175  * @param[out] error
12176  *   Pointer to error structure.
12177  *
12178  * @return
12179  *   0 on success, a negative errno value otherwise and rte_errno is set.
12180  */
12181 static int
12182 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12183               struct rte_flow_error *error)
12184 {
12185         struct mlx5_flow_dv_workspace *dv;
12186         struct mlx5_flow_handle *dh;
12187         struct mlx5_flow_handle_dv *dv_h;
12188         struct mlx5_flow *dev_flow;
12189         struct mlx5_priv *priv = dev->data->dev_private;
12190         uint32_t handle_idx;
12191         int n;
12192         int err;
12193         int idx;
12194         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12195         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12196
12197         MLX5_ASSERT(wks);
12198         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12199                 dev_flow = &wks->flows[idx];
12200                 dv = &dev_flow->dv;
12201                 dh = dev_flow->handle;
12202                 dv_h = &dh->dvh;
12203                 n = dv->actions_n;
12204                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12205                         if (dv->transfer) {
12206                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12207                                 dv->actions[n++] = priv->sh->dr_drop_action;
12208                         } else {
12209 #ifdef HAVE_MLX5DV_DR
12210                                 /* DR supports drop action placeholder. */
12211                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12212                                 dv->actions[n++] = priv->sh->dr_drop_action;
12213 #else
12214                                 /* For DV we use the explicit drop queue. */
12215                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12216                                 dv->actions[n++] =
12217                                                 priv->drop_queue.hrxq->action;
12218 #endif
12219                         }
12220                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12221                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12222                         struct mlx5_hrxq *hrxq;
12223                         uint32_t hrxq_idx;
12224
12225                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12226                                                     &hrxq_idx);
12227                         if (!hrxq) {
12228                                 rte_flow_error_set
12229                                         (error, rte_errno,
12230                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12231                                          "cannot get hash queue");
12232                                 goto error;
12233                         }
12234                         dh->rix_hrxq = hrxq_idx;
12235                         dv->actions[n++] = hrxq->action;
12236                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12237                         struct mlx5_hrxq *hrxq = NULL;
12238                         uint32_t hrxq_idx;
12239
12240                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12241                                                 rss_desc->shared_rss,
12242                                                 dev_flow->hash_fields);
12243                         if (hrxq_idx)
12244                                 hrxq = mlx5_ipool_get
12245                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12246                                          hrxq_idx);
12247                         if (!hrxq) {
12248                                 rte_flow_error_set
12249                                         (error, rte_errno,
12250                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12251                                          "cannot get hash queue");
12252                                 goto error;
12253                         }
12254                         dh->rix_srss = rss_desc->shared_rss;
12255                         dv->actions[n++] = hrxq->action;
12256                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12257                         if (!priv->sh->default_miss_action) {
12258                                 rte_flow_error_set
12259                                         (error, rte_errno,
12260                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12261                                          "default miss action not be created.");
12262                                 goto error;
12263                         }
12264                         dv->actions[n++] = priv->sh->default_miss_action;
12265                 }
12266                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12267                                                (void *)&dv->value, n,
12268                                                dv->actions, &dh->drv_flow);
12269                 if (err) {
12270                         rte_flow_error_set(error, errno,
12271                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12272                                            NULL,
12273                                            "hardware refuses to create flow");
12274                         goto error;
12275                 }
12276                 if (priv->vmwa_context &&
12277                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12278                         /*
12279                          * The rule contains the VLAN pattern.
12280                          * For VF we are going to create VLAN
12281                          * interface to make hypervisor set correct
12282                          * e-Switch vport context.
12283                          */
12284                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12285                 }
12286         }
12287         return 0;
12288 error:
12289         err = rte_errno; /* Save rte_errno before cleanup. */
12290         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12291                        handle_idx, dh, next) {
12292                 /* hrxq is union, don't clear it if the flag is not set. */
12293                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12294                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12295                         dh->rix_hrxq = 0;
12296                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12297                         dh->rix_srss = 0;
12298                 }
12299                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12300                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12301         }
12302         rte_errno = err; /* Restore rte_errno. */
12303         return -rte_errno;
12304 }
12305
12306 void
12307 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12308                           struct mlx5_cache_entry *entry)
12309 {
12310         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12311                                                           entry);
12312
12313         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12314         mlx5_free(cache);
12315 }
12316
12317 /**
12318  * Release the flow matcher.
12319  *
12320  * @param dev
12321  *   Pointer to Ethernet device.
12322  * @param port_id
12323  *   Index to port ID action resource.
12324  *
12325  * @return
12326  *   1 while a reference on it exists, 0 when freed.
12327  */
12328 static int
12329 flow_dv_matcher_release(struct rte_eth_dev *dev,
12330                         struct mlx5_flow_handle *handle)
12331 {
12332         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12333         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12334                                                             typeof(*tbl), tbl);
12335         int ret;
12336
12337         MLX5_ASSERT(matcher->matcher_object);
12338         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12339         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12340         return ret;
12341 }
12342
12343 /**
12344  * Release encap_decap resource.
12345  *
12346  * @param list
12347  *   Pointer to the hash list.
12348  * @param entry
12349  *   Pointer to exist resource entry object.
12350  */
12351 void
12352 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12353                               struct mlx5_hlist_entry *entry)
12354 {
12355         struct mlx5_dev_ctx_shared *sh = list->ctx;
12356         struct mlx5_flow_dv_encap_decap_resource *res =
12357                 container_of(entry, typeof(*res), entry);
12358
12359         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12360         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12361 }
12362
12363 /**
12364  * Release an encap/decap resource.
12365  *
12366  * @param dev
12367  *   Pointer to Ethernet device.
12368  * @param encap_decap_idx
12369  *   Index of encap decap resource.
12370  *
12371  * @return
12372  *   1 while a reference on it exists, 0 when freed.
12373  */
12374 static int
12375 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12376                                      uint32_t encap_decap_idx)
12377 {
12378         struct mlx5_priv *priv = dev->data->dev_private;
12379         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12380
12381         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12382                                         encap_decap_idx);
12383         if (!cache_resource)
12384                 return 0;
12385         MLX5_ASSERT(cache_resource->action);
12386         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12387                                      &cache_resource->entry);
12388 }
12389
12390 /**
12391  * Release an jump to table action resource.
12392  *
12393  * @param dev
12394  *   Pointer to Ethernet device.
12395  * @param rix_jump
12396  *   Index to the jump action resource.
12397  *
12398  * @return
12399  *   1 while a reference on it exists, 0 when freed.
12400  */
12401 static int
12402 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12403                                   uint32_t rix_jump)
12404 {
12405         struct mlx5_priv *priv = dev->data->dev_private;
12406         struct mlx5_flow_tbl_data_entry *tbl_data;
12407
12408         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12409                                   rix_jump);
12410         if (!tbl_data)
12411                 return 0;
12412         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12413 }
12414
12415 void
12416 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12417                          struct mlx5_hlist_entry *entry)
12418 {
12419         struct mlx5_flow_dv_modify_hdr_resource *res =
12420                 container_of(entry, typeof(*res), entry);
12421
12422         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12423         mlx5_free(entry);
12424 }
12425
12426 /**
12427  * Release a modify-header resource.
12428  *
12429  * @param dev
12430  *   Pointer to Ethernet device.
12431  * @param handle
12432  *   Pointer to mlx5_flow_handle.
12433  *
12434  * @return
12435  *   1 while a reference on it exists, 0 when freed.
12436  */
12437 static int
12438 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12439                                     struct mlx5_flow_handle *handle)
12440 {
12441         struct mlx5_priv *priv = dev->data->dev_private;
12442         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12443
12444         MLX5_ASSERT(entry->action);
12445         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12446 }
12447
12448 void
12449 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12450                           struct mlx5_cache_entry *entry)
12451 {
12452         struct mlx5_dev_ctx_shared *sh = list->ctx;
12453         struct mlx5_flow_dv_port_id_action_resource *cache =
12454                         container_of(entry, typeof(*cache), entry);
12455
12456         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12457         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12458 }
12459
12460 /**
12461  * Release port ID action resource.
12462  *
12463  * @param dev
12464  *   Pointer to Ethernet device.
12465  * @param handle
12466  *   Pointer to mlx5_flow_handle.
12467  *
12468  * @return
12469  *   1 while a reference on it exists, 0 when freed.
12470  */
12471 static int
12472 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12473                                         uint32_t port_id)
12474 {
12475         struct mlx5_priv *priv = dev->data->dev_private;
12476         struct mlx5_flow_dv_port_id_action_resource *cache;
12477
12478         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12479         if (!cache)
12480                 return 0;
12481         MLX5_ASSERT(cache->action);
12482         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12483                                      &cache->entry);
12484 }
12485
12486 /**
12487  * Release shared RSS action resource.
12488  *
12489  * @param dev
12490  *   Pointer to Ethernet device.
12491  * @param srss
12492  *   Shared RSS action index.
12493  */
12494 static void
12495 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12496 {
12497         struct mlx5_priv *priv = dev->data->dev_private;
12498         struct mlx5_shared_action_rss *shared_rss;
12499
12500         shared_rss = mlx5_ipool_get
12501                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12502         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12503 }
12504
12505 void
12506 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12507                             struct mlx5_cache_entry *entry)
12508 {
12509         struct mlx5_dev_ctx_shared *sh = list->ctx;
12510         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12511                         container_of(entry, typeof(*cache), entry);
12512
12513         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12514         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12515 }
12516
12517 /**
12518  * Release push vlan action resource.
12519  *
12520  * @param dev
12521  *   Pointer to Ethernet device.
12522  * @param handle
12523  *   Pointer to mlx5_flow_handle.
12524  *
12525  * @return
12526  *   1 while a reference on it exists, 0 when freed.
12527  */
12528 static int
12529 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12530                                           struct mlx5_flow_handle *handle)
12531 {
12532         struct mlx5_priv *priv = dev->data->dev_private;
12533         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12534         uint32_t idx = handle->dvh.rix_push_vlan;
12535
12536         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12537         if (!cache)
12538                 return 0;
12539         MLX5_ASSERT(cache->action);
12540         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12541                                      &cache->entry);
12542 }
12543
12544 /**
12545  * Release the fate resource.
12546  *
12547  * @param dev
12548  *   Pointer to Ethernet device.
12549  * @param handle
12550  *   Pointer to mlx5_flow_handle.
12551  */
12552 static void
12553 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12554                                struct mlx5_flow_handle *handle)
12555 {
12556         if (!handle->rix_fate)
12557                 return;
12558         switch (handle->fate_action) {
12559         case MLX5_FLOW_FATE_QUEUE:
12560                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12561                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12562                 break;
12563         case MLX5_FLOW_FATE_JUMP:
12564                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12565                 break;
12566         case MLX5_FLOW_FATE_PORT_ID:
12567                 flow_dv_port_id_action_resource_release(dev,
12568                                 handle->rix_port_id_action);
12569                 break;
12570         default:
12571                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12572                 break;
12573         }
12574         handle->rix_fate = 0;
12575 }
12576
12577 void
12578 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12579                          struct mlx5_cache_entry *entry)
12580 {
12581         struct mlx5_flow_dv_sample_resource *cache_resource =
12582                         container_of(entry, typeof(*cache_resource), entry);
12583         struct rte_eth_dev *dev = cache_resource->dev;
12584         struct mlx5_priv *priv = dev->data->dev_private;
12585
12586         if (cache_resource->verbs_action)
12587                 claim_zero(mlx5_flow_os_destroy_flow_action
12588                                 (cache_resource->verbs_action));
12589         if (cache_resource->normal_path_tbl)
12590                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12591                         cache_resource->normal_path_tbl);
12592         flow_dv_sample_sub_actions_release(dev,
12593                                 &cache_resource->sample_idx);
12594         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12595                         cache_resource->idx);
12596         DRV_LOG(DEBUG, "sample resource %p: removed",
12597                 (void *)cache_resource);
12598 }
12599
12600 /**
12601  * Release an sample resource.
12602  *
12603  * @param dev
12604  *   Pointer to Ethernet device.
12605  * @param handle
12606  *   Pointer to mlx5_flow_handle.
12607  *
12608  * @return
12609  *   1 while a reference on it exists, 0 when freed.
12610  */
12611 static int
12612 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12613                                      struct mlx5_flow_handle *handle)
12614 {
12615         struct mlx5_priv *priv = dev->data->dev_private;
12616         struct mlx5_flow_dv_sample_resource *cache_resource;
12617
12618         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12619                          handle->dvh.rix_sample);
12620         if (!cache_resource)
12621                 return 0;
12622         MLX5_ASSERT(cache_resource->verbs_action);
12623         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12624                                      &cache_resource->entry);
12625 }
12626
12627 void
12628 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12629                              struct mlx5_cache_entry *entry)
12630 {
12631         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12632                         container_of(entry, typeof(*cache_resource), entry);
12633         struct rte_eth_dev *dev = cache_resource->dev;
12634         struct mlx5_priv *priv = dev->data->dev_private;
12635         uint32_t i = 0;
12636
12637         MLX5_ASSERT(cache_resource->action);
12638         if (cache_resource->action)
12639                 claim_zero(mlx5_flow_os_destroy_flow_action
12640                                         (cache_resource->action));
12641         for (; i < cache_resource->num_of_dest; i++)
12642                 flow_dv_sample_sub_actions_release(dev,
12643                                 &cache_resource->sample_idx[i]);
12644         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12645                         cache_resource->idx);
12646         DRV_LOG(DEBUG, "destination array resource %p: removed",
12647                 (void *)cache_resource);
12648 }
12649
12650 /**
12651  * Release an destination array resource.
12652  *
12653  * @param dev
12654  *   Pointer to Ethernet device.
12655  * @param handle
12656  *   Pointer to mlx5_flow_handle.
12657  *
12658  * @return
12659  *   1 while a reference on it exists, 0 when freed.
12660  */
12661 static int
12662 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12663                                     struct mlx5_flow_handle *handle)
12664 {
12665         struct mlx5_priv *priv = dev->data->dev_private;
12666         struct mlx5_flow_dv_dest_array_resource *cache;
12667
12668         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12669                                handle->dvh.rix_dest_array);
12670         if (!cache)
12671                 return 0;
12672         MLX5_ASSERT(cache->action);
12673         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12674                                      &cache->entry);
12675 }
12676
12677 static void
12678 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12679 {
12680         struct mlx5_priv *priv = dev->data->dev_private;
12681         struct mlx5_dev_ctx_shared *sh = priv->sh;
12682         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12683                                 sh->geneve_tlv_option_resource;
12684         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12685         if (geneve_opt_resource) {
12686                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12687                                          __ATOMIC_RELAXED))) {
12688                         claim_zero(mlx5_devx_cmd_destroy
12689                                         (geneve_opt_resource->obj));
12690                         mlx5_free(sh->geneve_tlv_option_resource);
12691                         sh->geneve_tlv_option_resource = NULL;
12692                 }
12693         }
12694         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12695 }
12696
12697 /**
12698  * Remove the flow from the NIC but keeps it in memory.
12699  * Lock free, (mutex should be acquired by caller).
12700  *
12701  * @param[in] dev
12702  *   Pointer to Ethernet device.
12703  * @param[in, out] flow
12704  *   Pointer to flow structure.
12705  */
12706 static void
12707 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12708 {
12709         struct mlx5_flow_handle *dh;
12710         uint32_t handle_idx;
12711         struct mlx5_priv *priv = dev->data->dev_private;
12712
12713         if (!flow)
12714                 return;
12715         handle_idx = flow->dev_handles;
12716         while (handle_idx) {
12717                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12718                                     handle_idx);
12719                 if (!dh)
12720                         return;
12721                 if (dh->drv_flow) {
12722                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12723                         dh->drv_flow = NULL;
12724                 }
12725                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12726                         flow_dv_fate_resource_release(dev, dh);
12727                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12728                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12729                 handle_idx = dh->next.next;
12730         }
12731 }
12732
12733 /**
12734  * Remove the flow from the NIC and the memory.
12735  * Lock free, (mutex should be acquired by caller).
12736  *
12737  * @param[in] dev
12738  *   Pointer to the Ethernet device structure.
12739  * @param[in, out] flow
12740  *   Pointer to flow structure.
12741  */
12742 static void
12743 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12744 {
12745         struct mlx5_flow_handle *dev_handle;
12746         struct mlx5_priv *priv = dev->data->dev_private;
12747         struct mlx5_flow_meter_info *fm = NULL;
12748         uint32_t srss = 0;
12749
12750         if (!flow)
12751                 return;
12752         flow_dv_remove(dev, flow);
12753         if (flow->counter) {
12754                 flow_dv_counter_free(dev, flow->counter);
12755                 flow->counter = 0;
12756         }
12757         if (flow->meter) {
12758                 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12759                 if (fm)
12760                         mlx5_flow_meter_detach(fm);
12761                 flow->meter = 0;
12762         }
12763         if (flow->age)
12764                 flow_dv_aso_age_release(dev, flow->age);
12765         if (flow->geneve_tlv_option) {
12766                 flow_dv_geneve_tlv_option_resource_release(dev);
12767                 flow->geneve_tlv_option = 0;
12768         }
12769         while (flow->dev_handles) {
12770                 uint32_t tmp_idx = flow->dev_handles;
12771
12772                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12773                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12774                 if (!dev_handle)
12775                         return;
12776                 flow->dev_handles = dev_handle->next.next;
12777                 if (dev_handle->dvh.matcher)
12778                         flow_dv_matcher_release(dev, dev_handle);
12779                 if (dev_handle->dvh.rix_sample)
12780                         flow_dv_sample_resource_release(dev, dev_handle);
12781                 if (dev_handle->dvh.rix_dest_array)
12782                         flow_dv_dest_array_resource_release(dev, dev_handle);
12783                 if (dev_handle->dvh.rix_encap_decap)
12784                         flow_dv_encap_decap_resource_release(dev,
12785                                 dev_handle->dvh.rix_encap_decap);
12786                 if (dev_handle->dvh.modify_hdr)
12787                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12788                 if (dev_handle->dvh.rix_push_vlan)
12789                         flow_dv_push_vlan_action_resource_release(dev,
12790                                                                   dev_handle);
12791                 if (dev_handle->dvh.rix_tag)
12792                         flow_dv_tag_release(dev,
12793                                             dev_handle->dvh.rix_tag);
12794                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12795                         flow_dv_fate_resource_release(dev, dev_handle);
12796                 else if (!srss)
12797                         srss = dev_handle->rix_srss;
12798                 if (fm && dev_handle->is_meter_flow_id &&
12799                     dev_handle->split_flow_id)
12800                         mlx5_ipool_free(fm->flow_ipool,
12801                                         dev_handle->split_flow_id);
12802                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12803                            tmp_idx);
12804         }
12805         if (srss)
12806                 flow_dv_shared_rss_action_release(dev, srss);
12807 }
12808
12809 /**
12810  * Release array of hash RX queue objects.
12811  * Helper function.
12812  *
12813  * @param[in] dev
12814  *   Pointer to the Ethernet device structure.
12815  * @param[in, out] hrxqs
12816  *   Array of hash RX queue objects.
12817  *
12818  * @return
12819  *   Total number of references to hash RX queue objects in *hrxqs* array
12820  *   after this operation.
12821  */
12822 static int
12823 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12824                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12825 {
12826         size_t i;
12827         int remaining = 0;
12828
12829         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12830                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12831
12832                 if (!ret)
12833                         (*hrxqs)[i] = 0;
12834                 remaining += ret;
12835         }
12836         return remaining;
12837 }
12838
12839 /**
12840  * Release all hash RX queue objects representing shared RSS action.
12841  *
12842  * @param[in] dev
12843  *   Pointer to the Ethernet device structure.
12844  * @param[in, out] action
12845  *   Shared RSS action to remove hash RX queue objects from.
12846  *
12847  * @return
12848  *   Total number of references to hash RX queue objects stored in *action*
12849  *   after this operation.
12850  *   Expected to be 0 if no external references held.
12851  */
12852 static int
12853 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12854                                  struct mlx5_shared_action_rss *shared_rss)
12855 {
12856         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12857 }
12858
12859 /**
12860  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12861  * user input.
12862  *
12863  * Only one hash value is available for one L3+L4 combination:
12864  * for example:
12865  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12866  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12867  * same slot in mlx5_rss_hash_fields.
12868  *
12869  * @param[in] rss
12870  *   Pointer to the shared action RSS conf.
12871  * @param[in, out] hash_field
12872  *   hash_field variable needed to be adjusted.
12873  *
12874  * @return
12875  *   void
12876  */
12877 static void
12878 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12879                                      uint64_t *hash_field)
12880 {
12881         uint64_t rss_types = rss->origin.types;
12882
12883         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12884         case MLX5_RSS_HASH_IPV4:
12885                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12886                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12887                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12888                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12889                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12890                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12891                         else
12892                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12893                 }
12894                 return;
12895         case MLX5_RSS_HASH_IPV6:
12896                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12897                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12898                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12899                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12900                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12901                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12902                         else
12903                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12904                 }
12905                 return;
12906         case MLX5_RSS_HASH_IPV4_UDP:
12907                 /* fall-through. */
12908         case MLX5_RSS_HASH_IPV6_UDP:
12909                 if (rss_types & ETH_RSS_UDP) {
12910                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12911                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12912                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12913                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12914                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12915                         else
12916                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12917                 }
12918                 return;
12919         case MLX5_RSS_HASH_IPV4_TCP:
12920                 /* fall-through. */
12921         case MLX5_RSS_HASH_IPV6_TCP:
12922                 if (rss_types & ETH_RSS_TCP) {
12923                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12924                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12925                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12926                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12927                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12928                         else
12929                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12930                 }
12931                 return;
12932         default:
12933                 return;
12934         }
12935 }
12936
12937 /**
12938  * Setup shared RSS action.
12939  * Prepare set of hash RX queue objects sufficient to handle all valid
12940  * hash_fields combinations (see enum ibv_rx_hash_fields).
12941  *
12942  * @param[in] dev
12943  *   Pointer to the Ethernet device structure.
12944  * @param[in] action_idx
12945  *   Shared RSS action ipool index.
12946  * @param[in, out] action
12947  *   Partially initialized shared RSS action.
12948  * @param[out] error
12949  *   Perform verbose error reporting if not NULL. Initialized in case of
12950  *   error only.
12951  *
12952  * @return
12953  *   0 on success, otherwise negative errno value.
12954  */
12955 static int
12956 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12957                            uint32_t action_idx,
12958                            struct mlx5_shared_action_rss *shared_rss,
12959                            struct rte_flow_error *error)
12960 {
12961         struct mlx5_flow_rss_desc rss_desc = { 0 };
12962         size_t i;
12963         int err;
12964
12965         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12966                 return rte_flow_error_set(error, rte_errno,
12967                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12968                                           "cannot setup indirection table");
12969         }
12970         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12971         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12972         rss_desc.const_q = shared_rss->origin.queue;
12973         rss_desc.queue_num = shared_rss->origin.queue_num;
12974         /* Set non-zero value to indicate a shared RSS. */
12975         rss_desc.shared_rss = action_idx;
12976         rss_desc.ind_tbl = shared_rss->ind_tbl;
12977         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12978                 uint32_t hrxq_idx;
12979                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12980                 int tunnel = 0;
12981
12982                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12983                 if (shared_rss->origin.level > 1) {
12984                         hash_fields |= IBV_RX_HASH_INNER;
12985                         tunnel = 1;
12986                 }
12987                 rss_desc.tunnel = tunnel;
12988                 rss_desc.hash_fields = hash_fields;
12989                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12990                 if (!hrxq_idx) {
12991                         rte_flow_error_set
12992                                 (error, rte_errno,
12993                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12994                                  "cannot get hash queue");
12995                         goto error_hrxq_new;
12996                 }
12997                 err = __flow_dv_action_rss_hrxq_set
12998                         (shared_rss, hash_fields, hrxq_idx);
12999                 MLX5_ASSERT(!err);
13000         }
13001         return 0;
13002 error_hrxq_new:
13003         err = rte_errno;
13004         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13005         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13006                 shared_rss->ind_tbl = NULL;
13007         rte_errno = err;
13008         return -rte_errno;
13009 }
13010
13011 /**
13012  * Create shared RSS action.
13013  *
13014  * @param[in] dev
13015  *   Pointer to the Ethernet device structure.
13016  * @param[in] conf
13017  *   Shared action configuration.
13018  * @param[in] rss
13019  *   RSS action specification used to create shared action.
13020  * @param[out] error
13021  *   Perform verbose error reporting if not NULL. Initialized in case of
13022  *   error only.
13023  *
13024  * @return
13025  *   A valid shared action ID in case of success, 0 otherwise and
13026  *   rte_errno is set.
13027  */
13028 static uint32_t
13029 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13030                             const struct rte_flow_indir_action_conf *conf,
13031                             const struct rte_flow_action_rss *rss,
13032                             struct rte_flow_error *error)
13033 {
13034         struct mlx5_priv *priv = dev->data->dev_private;
13035         struct mlx5_shared_action_rss *shared_rss = NULL;
13036         void *queue = NULL;
13037         struct rte_flow_action_rss *origin;
13038         const uint8_t *rss_key;
13039         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13040         uint32_t idx;
13041
13042         RTE_SET_USED(conf);
13043         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13044                             0, SOCKET_ID_ANY);
13045         shared_rss = mlx5_ipool_zmalloc
13046                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13047         if (!shared_rss || !queue) {
13048                 rte_flow_error_set(error, ENOMEM,
13049                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13050                                    "cannot allocate resource memory");
13051                 goto error_rss_init;
13052         }
13053         if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13054                 rte_flow_error_set(error, E2BIG,
13055                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13056                                    "rss action number out of range");
13057                 goto error_rss_init;
13058         }
13059         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13060                                           sizeof(*shared_rss->ind_tbl),
13061                                           0, SOCKET_ID_ANY);
13062         if (!shared_rss->ind_tbl) {
13063                 rte_flow_error_set(error, ENOMEM,
13064                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13065                                    "cannot allocate resource memory");
13066                 goto error_rss_init;
13067         }
13068         memcpy(queue, rss->queue, queue_size);
13069         shared_rss->ind_tbl->queues = queue;
13070         shared_rss->ind_tbl->queues_n = rss->queue_num;
13071         origin = &shared_rss->origin;
13072         origin->func = rss->func;
13073         origin->level = rss->level;
13074         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13075         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13076         /* NULL RSS key indicates default RSS key. */
13077         rss_key = !rss->key ? rss_hash_default_key : rss->key;
13078         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13079         origin->key = &shared_rss->key[0];
13080         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13081         origin->queue = queue;
13082         origin->queue_num = rss->queue_num;
13083         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13084                 goto error_rss_init;
13085         rte_spinlock_init(&shared_rss->action_rss_sl);
13086         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13087         rte_spinlock_lock(&priv->shared_act_sl);
13088         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13089                      &priv->rss_shared_actions, idx, shared_rss, next);
13090         rte_spinlock_unlock(&priv->shared_act_sl);
13091         return idx;
13092 error_rss_init:
13093         if (shared_rss) {
13094                 if (shared_rss->ind_tbl)
13095                         mlx5_free(shared_rss->ind_tbl);
13096                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13097                                 idx);
13098         }
13099         if (queue)
13100                 mlx5_free(queue);
13101         return 0;
13102 }
13103
13104 /**
13105  * Destroy the shared RSS action.
13106  * Release related hash RX queue objects.
13107  *
13108  * @param[in] dev
13109  *   Pointer to the Ethernet device structure.
13110  * @param[in] idx
13111  *   The shared RSS action object ID to be removed.
13112  * @param[out] error
13113  *   Perform verbose error reporting if not NULL. Initialized in case of
13114  *   error only.
13115  *
13116  * @return
13117  *   0 on success, otherwise negative errno value.
13118  */
13119 static int
13120 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13121                              struct rte_flow_error *error)
13122 {
13123         struct mlx5_priv *priv = dev->data->dev_private;
13124         struct mlx5_shared_action_rss *shared_rss =
13125             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13126         uint32_t old_refcnt = 1;
13127         int remaining;
13128         uint16_t *queue = NULL;
13129
13130         if (!shared_rss)
13131                 return rte_flow_error_set(error, EINVAL,
13132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13133                                           "invalid shared action");
13134         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13135         if (remaining)
13136                 return rte_flow_error_set(error, EBUSY,
13137                                           RTE_FLOW_ERROR_TYPE_ACTION,
13138                                           NULL,
13139                                           "shared rss hrxq has references");
13140         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13141                                          0, 0, __ATOMIC_ACQUIRE,
13142                                          __ATOMIC_RELAXED))
13143                 return rte_flow_error_set(error, EBUSY,
13144                                           RTE_FLOW_ERROR_TYPE_ACTION,
13145                                           NULL,
13146                                           "shared rss has references");
13147         queue = shared_rss->ind_tbl->queues;
13148         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13149         if (remaining)
13150                 return rte_flow_error_set(error, EBUSY,
13151                                           RTE_FLOW_ERROR_TYPE_ACTION,
13152                                           NULL,
13153                                           "shared rss indirection table has"
13154                                           " references");
13155         mlx5_free(queue);
13156         rte_spinlock_lock(&priv->shared_act_sl);
13157         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13158                      &priv->rss_shared_actions, idx, shared_rss, next);
13159         rte_spinlock_unlock(&priv->shared_act_sl);
13160         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13161                         idx);
13162         return 0;
13163 }
13164
13165 /**
13166  * Create indirect action, lock free,
13167  * (mutex should be acquired by caller).
13168  * Dispatcher for action type specific call.
13169  *
13170  * @param[in] dev
13171  *   Pointer to the Ethernet device structure.
13172  * @param[in] conf
13173  *   Shared action configuration.
13174  * @param[in] action
13175  *   Action specification used to create indirect action.
13176  * @param[out] error
13177  *   Perform verbose error reporting if not NULL. Initialized in case of
13178  *   error only.
13179  *
13180  * @return
13181  *   A valid shared action handle in case of success, NULL otherwise and
13182  *   rte_errno is set.
13183  */
13184 static struct rte_flow_action_handle *
13185 flow_dv_action_create(struct rte_eth_dev *dev,
13186                       const struct rte_flow_indir_action_conf *conf,
13187                       const struct rte_flow_action *action,
13188                       struct rte_flow_error *err)
13189 {
13190         uint32_t idx = 0;
13191         uint32_t ret = 0;
13192
13193         switch (action->type) {
13194         case RTE_FLOW_ACTION_TYPE_RSS:
13195                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13196                 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13197                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13198                 break;
13199         case RTE_FLOW_ACTION_TYPE_AGE:
13200                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13201                 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13202                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13203                 if (ret) {
13204                         struct mlx5_aso_age_action *aso_age =
13205                                               flow_aso_age_get_by_idx(dev, ret);
13206
13207                         if (!aso_age->age_params.context)
13208                                 aso_age->age_params.context =
13209                                                          (void *)(uintptr_t)idx;
13210                 }
13211                 break;
13212         default:
13213                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13214                                    NULL, "action type not supported");
13215                 break;
13216         }
13217         return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13218 }
13219
13220 /**
13221  * Destroy the indirect action.
13222  * Release action related resources on the NIC and the memory.
13223  * Lock free, (mutex should be acquired by caller).
13224  * Dispatcher for action type specific call.
13225  *
13226  * @param[in] dev
13227  *   Pointer to the Ethernet device structure.
13228  * @param[in] handle
13229  *   The indirect action object handle to be removed.
13230  * @param[out] error
13231  *   Perform verbose error reporting if not NULL. Initialized in case of
13232  *   error only.
13233  *
13234  * @return
13235  *   0 on success, otherwise negative errno value.
13236  */
13237 static int
13238 flow_dv_action_destroy(struct rte_eth_dev *dev,
13239                        struct rte_flow_action_handle *handle,
13240                        struct rte_flow_error *error)
13241 {
13242         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13243         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13244         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13245         int ret;
13246
13247         switch (type) {
13248         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13249                 return __flow_dv_action_rss_release(dev, idx, error);
13250         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13251                 ret = flow_dv_aso_age_release(dev, idx);
13252                 if (ret)
13253                         /*
13254                          * In this case, the last flow has a reference will
13255                          * actually release the age action.
13256                          */
13257                         DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13258                                 " released with references %d.", idx, ret);
13259                 return 0;
13260         default:
13261                 return rte_flow_error_set(error, ENOTSUP,
13262                                           RTE_FLOW_ERROR_TYPE_ACTION,
13263                                           NULL,
13264                                           "action type not supported");
13265         }
13266 }
13267
13268 /**
13269  * Updates in place shared RSS action configuration.
13270  *
13271  * @param[in] dev
13272  *   Pointer to the Ethernet device structure.
13273  * @param[in] idx
13274  *   The shared RSS action object ID to be updated.
13275  * @param[in] action_conf
13276  *   RSS action specification used to modify *shared_rss*.
13277  * @param[out] error
13278  *   Perform verbose error reporting if not NULL. Initialized in case of
13279  *   error only.
13280  *
13281  * @return
13282  *   0 on success, otherwise negative errno value.
13283  * @note: currently only support update of RSS queues.
13284  */
13285 static int
13286 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13287                             const struct rte_flow_action_rss *action_conf,
13288                             struct rte_flow_error *error)
13289 {
13290         struct mlx5_priv *priv = dev->data->dev_private;
13291         struct mlx5_shared_action_rss *shared_rss =
13292             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13293         int ret = 0;
13294         void *queue = NULL;
13295         uint16_t *queue_old = NULL;
13296         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13297
13298         if (!shared_rss)
13299                 return rte_flow_error_set(error, EINVAL,
13300                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13301                                           "invalid shared action to update");
13302         if (priv->obj_ops.ind_table_modify == NULL)
13303                 return rte_flow_error_set(error, ENOTSUP,
13304                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13305                                           "cannot modify indirection table");
13306         queue = mlx5_malloc(MLX5_MEM_ZERO,
13307                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13308                             0, SOCKET_ID_ANY);
13309         if (!queue)
13310                 return rte_flow_error_set(error, ENOMEM,
13311                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13312                                           NULL,
13313                                           "cannot allocate resource memory");
13314         memcpy(queue, action_conf->queue, queue_size);
13315         MLX5_ASSERT(shared_rss->ind_tbl);
13316         rte_spinlock_lock(&shared_rss->action_rss_sl);
13317         queue_old = shared_rss->ind_tbl->queues;
13318         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13319                                         queue, action_conf->queue_num, true);
13320         if (ret) {
13321                 mlx5_free(queue);
13322                 ret = rte_flow_error_set(error, rte_errno,
13323                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13324                                           "cannot update indirection table");
13325         } else {
13326                 mlx5_free(queue_old);
13327                 shared_rss->origin.queue = queue;
13328                 shared_rss->origin.queue_num = action_conf->queue_num;
13329         }
13330         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13331         return ret;
13332 }
13333
13334 /**
13335  * Updates in place shared action configuration, lock free,
13336  * (mutex should be acquired by caller).
13337  *
13338  * @param[in] dev
13339  *   Pointer to the Ethernet device structure.
13340  * @param[in] handle
13341  *   The indirect action object handle to be updated.
13342  * @param[in] update
13343  *   Action specification used to modify the action pointed by *handle*.
13344  *   *update* could be of same type with the action pointed by the *handle*
13345  *   handle argument, or some other structures like a wrapper, depending on
13346  *   the indirect action type.
13347  * @param[out] error
13348  *   Perform verbose error reporting if not NULL. Initialized in case of
13349  *   error only.
13350  *
13351  * @return
13352  *   0 on success, otherwise negative errno value.
13353  */
13354 static int
13355 flow_dv_action_update(struct rte_eth_dev *dev,
13356                         struct rte_flow_action_handle *handle,
13357                         const void *update,
13358                         struct rte_flow_error *err)
13359 {
13360         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13361         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13362         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13363         const void *action_conf;
13364
13365         switch (type) {
13366         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13367                 action_conf = ((const struct rte_flow_action *)update)->conf;
13368                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13369         default:
13370                 return rte_flow_error_set(err, ENOTSUP,
13371                                           RTE_FLOW_ERROR_TYPE_ACTION,
13372                                           NULL,
13373                                           "action type update not supported");
13374         }
13375 }
13376
13377 static int
13378 flow_dv_action_query(struct rte_eth_dev *dev,
13379                      const struct rte_flow_action_handle *handle, void *data,
13380                      struct rte_flow_error *error)
13381 {
13382         struct mlx5_age_param *age_param;
13383         struct rte_flow_query_age *resp;
13384         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13385         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13386         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13387
13388         switch (type) {
13389         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13390                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13391                 resp = data;
13392                 resp->aged = __atomic_load_n(&age_param->state,
13393                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13394                                                                           1 : 0;
13395                 resp->sec_since_last_hit_valid = !resp->aged;
13396                 if (resp->sec_since_last_hit_valid)
13397                         resp->sec_since_last_hit = __atomic_load_n
13398                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13399                 return 0;
13400         default:
13401                 return rte_flow_error_set(error, ENOTSUP,
13402                                           RTE_FLOW_ERROR_TYPE_ACTION,
13403                                           NULL,
13404                                           "action type query not supported");
13405         }
13406 }
13407
13408 /**
13409  * Query a dv flow  rule for its statistics via devx.
13410  *
13411  * @param[in] dev
13412  *   Pointer to Ethernet device.
13413  * @param[in] flow
13414  *   Pointer to the sub flow.
13415  * @param[out] data
13416  *   data retrieved by the query.
13417  * @param[out] error
13418  *   Perform verbose error reporting if not NULL.
13419  *
13420  * @return
13421  *   0 on success, a negative errno value otherwise and rte_errno is set.
13422  */
13423 static int
13424 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13425                     void *data, struct rte_flow_error *error)
13426 {
13427         struct mlx5_priv *priv = dev->data->dev_private;
13428         struct rte_flow_query_count *qc = data;
13429
13430         if (!priv->config.devx)
13431                 return rte_flow_error_set(error, ENOTSUP,
13432                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13433                                           NULL,
13434                                           "counters are not supported");
13435         if (flow->counter) {
13436                 uint64_t pkts, bytes;
13437                 struct mlx5_flow_counter *cnt;
13438
13439                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13440                                                  NULL);
13441                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13442                                                &bytes);
13443
13444                 if (err)
13445                         return rte_flow_error_set(error, -err,
13446                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13447                                         NULL, "cannot read counters");
13448                 qc->hits_set = 1;
13449                 qc->bytes_set = 1;
13450                 qc->hits = pkts - cnt->hits;
13451                 qc->bytes = bytes - cnt->bytes;
13452                 if (qc->reset) {
13453                         cnt->hits = pkts;
13454                         cnt->bytes = bytes;
13455                 }
13456                 return 0;
13457         }
13458         return rte_flow_error_set(error, EINVAL,
13459                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13460                                   NULL,
13461                                   "counters are not available");
13462 }
13463
13464 /**
13465  * Query a flow rule AGE action for aging information.
13466  *
13467  * @param[in] dev
13468  *   Pointer to Ethernet device.
13469  * @param[in] flow
13470  *   Pointer to the sub flow.
13471  * @param[out] data
13472  *   data retrieved by the query.
13473  * @param[out] error
13474  *   Perform verbose error reporting if not NULL.
13475  *
13476  * @return
13477  *   0 on success, a negative errno value otherwise and rte_errno is set.
13478  */
13479 static int
13480 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13481                   void *data, struct rte_flow_error *error)
13482 {
13483         struct rte_flow_query_age *resp = data;
13484         struct mlx5_age_param *age_param;
13485
13486         if (flow->age) {
13487                 struct mlx5_aso_age_action *act =
13488                                      flow_aso_age_get_by_idx(dev, flow->age);
13489
13490                 age_param = &act->age_params;
13491         } else if (flow->counter) {
13492                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13493
13494                 if (!age_param || !age_param->timeout)
13495                         return rte_flow_error_set
13496                                         (error, EINVAL,
13497                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13498                                          NULL, "cannot read age data");
13499         } else {
13500                 return rte_flow_error_set(error, EINVAL,
13501                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13502                                           NULL, "age data not available");
13503         }
13504         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13505                                      AGE_TMOUT ? 1 : 0;
13506         resp->sec_since_last_hit_valid = !resp->aged;
13507         if (resp->sec_since_last_hit_valid)
13508                 resp->sec_since_last_hit = __atomic_load_n
13509                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13510         return 0;
13511 }
13512
13513 /**
13514  * Query a flow.
13515  *
13516  * @see rte_flow_query()
13517  * @see rte_flow_ops
13518  */
13519 static int
13520 flow_dv_query(struct rte_eth_dev *dev,
13521               struct rte_flow *flow __rte_unused,
13522               const struct rte_flow_action *actions __rte_unused,
13523               void *data __rte_unused,
13524               struct rte_flow_error *error __rte_unused)
13525 {
13526         int ret = -EINVAL;
13527
13528         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13529                 switch (actions->type) {
13530                 case RTE_FLOW_ACTION_TYPE_VOID:
13531                         break;
13532                 case RTE_FLOW_ACTION_TYPE_COUNT:
13533                         ret = flow_dv_query_count(dev, flow, data, error);
13534                         break;
13535                 case RTE_FLOW_ACTION_TYPE_AGE:
13536                         ret = flow_dv_query_age(dev, flow, data, error);
13537                         break;
13538                 default:
13539                         return rte_flow_error_set(error, ENOTSUP,
13540                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13541                                                   actions,
13542                                                   "action not supported");
13543                 }
13544         }
13545         return ret;
13546 }
13547
13548 /**
13549  * Destroy the meter table set.
13550  * Lock free, (mutex should be acquired by caller).
13551  *
13552  * @param[in] dev
13553  *   Pointer to Ethernet device.
13554  * @param[in] tbl
13555  *   Pointer to the meter table set.
13556  *
13557  * @return
13558  *   Always 0.
13559  */
13560 static int
13561 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13562                         struct mlx5_meter_domains_infos *tbl)
13563 {
13564         struct mlx5_priv *priv = dev->data->dev_private;
13565         struct mlx5_meter_domains_infos *mtd =
13566                                 (struct mlx5_meter_domains_infos *)tbl;
13567
13568         if (!mtd || !priv->config.dv_flow_en)
13569                 return 0;
13570         if (mtd->egress.tbl)
13571                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13572         if (mtd->egress.sfx_tbl)
13573                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13574         if (mtd->ingress.tbl)
13575                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13576         if (mtd->ingress.sfx_tbl)
13577                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13578                                              mtd->ingress.sfx_tbl);
13579         if (mtd->transfer.tbl)
13580                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13581         if (mtd->transfer.sfx_tbl)
13582                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13583                                              mtd->transfer.sfx_tbl);
13584         mlx5_free(mtd);
13585         return 0;
13586 }
13587
13588 /* Number of meter flow actions, count and jump or count and drop. */
13589 #define METER_ACTIONS 2
13590
13591 /**
13592  * Create specify domain meter table and suffix table.
13593  *
13594  * @param[in] dev
13595  *   Pointer to Ethernet device.
13596  * @param[in,out] mtb
13597  *   Pointer to DV meter table set.
13598  * @param[in] egress
13599  *   Table attribute.
13600  * @param[in] transfer
13601  *   Table attribute.
13602  *
13603  * @return
13604  *   0 on success, -1 otherwise.
13605  */
13606 static int
13607 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13608                            struct mlx5_meter_domains_infos *mtb,
13609                            uint8_t egress, uint8_t transfer)
13610 {
13611         struct rte_flow_error error;
13612         struct mlx5_meter_domain_info *dtb;
13613
13614         if (transfer)
13615                 dtb = &mtb->transfer;
13616         else if (egress)
13617                 dtb = &mtb->egress;
13618         else
13619                 dtb = &mtb->ingress;
13620         /* Create the meter table with METER level. */
13621         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13622                                             egress, transfer, false, NULL, 0,
13623                                             0, &error);
13624         if (!dtb->tbl) {
13625                 DRV_LOG(ERR, "Failed to create meter policer table.");
13626                 return -1;
13627         }
13628         /* Create the meter suffix table with SUFFIX level. */
13629         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13630                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13631                                             egress, transfer, false, NULL, 0,
13632                                             0, &error);
13633         if (!dtb->sfx_tbl) {
13634                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13635                 return -1;
13636         }
13637         return 0;
13638 }
13639
13640 /**
13641  * Create the needed meter and suffix tables.
13642  * Lock free, (mutex should be acquired by caller).
13643  *
13644  * @param[in] dev
13645  *   Pointer to Ethernet device.
13646  *
13647  * @return
13648  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13649  */
13650 static struct mlx5_meter_domains_infos *
13651 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13652 {
13653         struct mlx5_priv *priv = dev->data->dev_private;
13654         struct mlx5_meter_domains_infos *mtb;
13655         int ret;
13656
13657         if (!priv->mtr_en) {
13658                 rte_errno = ENOTSUP;
13659                 return NULL;
13660         }
13661         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13662         if (!mtb) {
13663                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13664                 return NULL;
13665         }
13666         /* Egress meter table. */
13667         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13668         if (ret) {
13669                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13670                 goto error_exit;
13671         }
13672         /* Ingress meter table. */
13673         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13674         if (ret) {
13675                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13676                 goto error_exit;
13677         }
13678         /* FDB meter table. */
13679         if (priv->config.dv_esw_en) {
13680                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13681                 if (ret) {
13682                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13683                         goto error_exit;
13684                 }
13685         }
13686         return mtb;
13687 error_exit:
13688         flow_dv_destroy_mtr_tbl(dev, mtb);
13689         return NULL;
13690 }
13691
13692 /**
13693  * Destroy the meter table matchers.
13694  * Lock free, (mutex should be acquired by caller).
13695  *
13696  * @param[in] dev
13697  *   Pointer to Ethernet device.
13698  * @param[in,out] dtb
13699  *   Pointer to DV meter table.
13700  *
13701  * @return
13702  *   Always 0.
13703  */
13704 static int
13705 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13706                              struct mlx5_meter_domain_info *dtb)
13707 {
13708         struct mlx5_priv *priv = dev->data->dev_private;
13709         struct mlx5_flow_tbl_data_entry *tbl;
13710
13711         if (!priv->config.dv_flow_en)
13712                 return 0;
13713         if (dtb->drop_matcher) {
13714                 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13715                 mlx5_cache_unregister(&tbl->matchers,
13716                                       &dtb->drop_matcher->entry);
13717                 dtb->drop_matcher = NULL;
13718         }
13719         if (dtb->color_matcher) {
13720                 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13721                 mlx5_cache_unregister(&tbl->matchers,
13722                                       &dtb->color_matcher->entry);
13723                 dtb->color_matcher = NULL;
13724         }
13725         return 0;
13726 }
13727
13728 /**
13729  * Create the matchers for meter table.
13730  *
13731  * @param[in] dev
13732  *   Pointer to Ethernet device.
13733  * @param[in] color_reg_c_idx
13734  *   Reg C index for color match.
13735  * @param[in] mtr_id_reg_c_idx
13736  *   Reg C index for meter_id match.
13737  * @param[in] mtr_id_mask
13738  *   Mask for meter_id match criteria.
13739  * @param[in,out] dtb
13740  *   Pointer to DV meter table.
13741  * @param[out] error
13742  *   Perform verbose error reporting if not NULL.
13743  *
13744  * @return
13745  *   0 on success, a negative errno value otherwise and rte_errno is set.
13746  */
13747 static int
13748 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13749                              uint32_t color_reg_c_idx,
13750                              uint32_t mtr_id_reg_c_idx,
13751                              uint32_t mtr_id_mask,
13752                              struct mlx5_meter_domain_info *dtb,
13753                              struct rte_flow_error *error)
13754 {
13755         struct mlx5_priv *priv = dev->data->dev_private;
13756         struct mlx5_flow_tbl_data_entry *tbl_data;
13757         struct mlx5_cache_entry *entry;
13758         struct mlx5_flow_dv_matcher matcher = {
13759                 .mask = {
13760                         .size = sizeof(matcher.mask.buf) -
13761                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13762                 },
13763                 .tbl = dtb->tbl,
13764         };
13765         struct mlx5_flow_dv_match_params value = {
13766                 .size = sizeof(value.buf) -
13767                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13768         };
13769         struct mlx5_flow_cb_ctx ctx = {
13770                 .error = error,
13771                 .data = &matcher,
13772         };
13773         uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13774
13775         tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13776         if (!dtb->drop_matcher) {
13777                 /* Create matchers for Drop. */
13778                 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13779                                        mtr_id_reg_c_idx, 0, mtr_id_mask);
13780                 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13781                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13782                                         matcher.mask.size);
13783                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13784                 if (!entry) {
13785                         DRV_LOG(ERR, "Failed to register meter drop matcher.");
13786                         return -1;
13787                 }
13788                 dtb->drop_matcher =
13789                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13790         }
13791         if (!dtb->color_matcher) {
13792                 /* Create matchers for Color + meter_id. */
13793                 if (priv->mtr_reg_share) {
13794                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13795                                         color_reg_c_idx, 0,
13796                                         (mtr_id_mask | color_mask));
13797                 } else {
13798                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13799                                         color_reg_c_idx, 0, color_mask);
13800                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13801                                         mtr_id_reg_c_idx, 0, mtr_id_mask);
13802                 }
13803                 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13804                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13805                                         matcher.mask.size);
13806                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13807                 if (!entry) {
13808                         DRV_LOG(ERR, "Failed to register meter color matcher.");
13809                         return -1;
13810                 }
13811                 dtb->color_matcher =
13812                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13813         }
13814         return 0;
13815 }
13816
13817 /**
13818  * Destroy domain policer rule.
13819  *
13820  * @param[in] dev
13821  *   Pointer to Ethernet device.
13822  * @param[in] dt
13823  *   Pointer to domain table.
13824  */
13825 static void
13826 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13827                                     struct mlx5_meter_domain_info *dt)
13828 {
13829         if (dt->drop_rule) {
13830                 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13831                 dt->drop_rule = NULL;
13832         }
13833         if (dt->green_rule) {
13834                 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13835                 dt->green_rule = NULL;
13836         }
13837         flow_dv_destroy_mtr_matchers(dev, dt);
13838         if (dt->jump_actn) {
13839                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13840                 dt->jump_actn = NULL;
13841         }
13842 }
13843
13844 /**
13845  * Destroy policer rules.
13846  *
13847  * @param[in] dev
13848  *   Pointer to Ethernet device.
13849  * @param[in] fm
13850  *   Pointer to flow meter structure.
13851  * @param[in] attr
13852  *   Pointer to flow attributes.
13853  *
13854  * @return
13855  *   Always 0.
13856  */
13857 static int
13858 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13859                               const struct mlx5_flow_meter_info *fm,
13860                               const struct rte_flow_attr *attr)
13861 {
13862         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13863
13864         if (!mtb)
13865                 return 0;
13866         if (attr->egress)
13867                 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13868         if (attr->ingress)
13869                 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13870         if (attr->transfer)
13871                 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13872         return 0;
13873 }
13874
13875 /**
13876  * Create specify domain meter policer rule.
13877  *
13878  * @param[in] dev
13879  *   Pointer to Ethernet device.
13880  * @param[in] fm
13881  *   Pointer to flow meter structure.
13882  * @param[in] mtr_idx
13883  *   meter index.
13884  * @param[in] mtb
13885  *   Pointer to DV meter table set.
13886  * @param[out] drop_rule
13887  *   The address of pointer saving drop rule.
13888  * @param[out] color_rule
13889  *   The address of pointer saving green rule.
13890  *
13891  * @return
13892  *   0 on success, -1 otherwise.
13893  */
13894 static int
13895 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13896                                     struct mlx5_flow_meter_info *fm,
13897                                     uint32_t mtr_idx,
13898                                     struct mlx5_meter_domain_info *dtb,
13899                                     void **drop_rule,
13900                                     void **green_rule)
13901 {
13902         struct mlx5_priv *priv = dev->data->dev_private;
13903         struct mlx5_flow_dv_match_params matcher = {
13904                 .size = sizeof(matcher.buf) -
13905                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13906         };
13907         struct mlx5_flow_dv_match_params value = {
13908                 .size = sizeof(value.buf) -
13909                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13910         };
13911         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13912         struct rte_flow_error error;
13913         uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13914                                                     0, &error);
13915         uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13916                                                      0, &error);
13917         uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13918         uint32_t mtr_id_mask =
13919                 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13920         void *actions[METER_ACTIONS];
13921         int i;
13922         int ret = 0;
13923
13924         /* Create jump action. */
13925         if (!dtb->jump_actn)
13926                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13927                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13928         if (ret) {
13929                 DRV_LOG(ERR, "Failed to create policer jump action.");
13930                 goto error;
13931         }
13932         /* Prepare matchers. */
13933         if (!dtb->drop_matcher || !dtb->color_matcher) {
13934                 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13935                                                    mtr_id_reg_c, mtr_id_mask,
13936                                                    dtb, &error);
13937                 if (ret) {
13938                         DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13939                         goto error;
13940                 }
13941         }
13942         /* Create Drop flow, matching meter_id only. */
13943         i = 0;
13944         flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13945                                (mtr_idx << mtr_id_offset), UINT32_MAX);
13946         if (mtb->drop_count)
13947                 actions[i++] = mtb->drop_count;
13948         actions[i++] = priv->sh->dr_drop_action;
13949         ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13950                                        (void *)&value, i, actions, drop_rule);
13951         if (ret) {
13952                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13953                 goto error;
13954         }
13955         /* Create flow matching Green color + meter_id. */
13956         i = 0;
13957         if (priv->mtr_reg_share) {
13958                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13959                                        ((mtr_idx << mtr_id_offset) |
13960                                         rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13961                                        UINT32_MAX);
13962         } else {
13963                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13964                                        rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13965                                        UINT32_MAX);
13966                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13967                                        mtr_idx, UINT32_MAX);
13968         }
13969         if (mtb->green_count)
13970                 actions[i++] = mtb->green_count;
13971         actions[i++] = dtb->jump_actn;
13972         ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
13973                                        (void *)&value, i, actions, green_rule);
13974         if (ret) {
13975                 DRV_LOG(ERR, "Failed to create meter policer color rule.");
13976                 goto error;
13977         }
13978         return 0;
13979 error:
13980         rte_errno = errno;
13981         return -1;
13982 }
13983
13984 /**
13985  * Prepare policer rules for all domains.
13986  * If meter already initialized, this will replace all old rules with new ones.
13987  *
13988  * @param[in] dev
13989  *   Pointer to Ethernet device.
13990  * @param[in] fm
13991  *   Pointer to flow meter structure.
13992  * @param[in] attr
13993  *   Pointer to flow attributes.
13994  *
13995  * @return
13996  *   0 on success, -1 otherwise.
13997  */
13998 static int
13999 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
14000                               struct mlx5_flow_meter_info *fm,
14001                               const struct rte_flow_attr *attr)
14002 {
14003         struct mlx5_priv *priv = dev->data->dev_private;
14004         struct mlx5_meter_domains_infos *mtb = fm->mfts;
14005         bool initialized = false;
14006         struct mlx5_flow_counter *cnt;
14007         void *egress_drop_rule = NULL;
14008         void *egress_green_rule = NULL;
14009         void *ingress_drop_rule = NULL;
14010         void *ingress_green_rule = NULL;
14011         void *transfer_drop_rule = NULL;
14012         void *transfer_green_rule = NULL;
14013         uint32_t mtr_idx;
14014         int ret;
14015
14016         /* Get the statistics counters for green/drop. */
14017         if (fm->policer_stats.pass_cnt) {
14018                 cnt = flow_dv_counter_get_by_idx(dev,
14019                                         fm->policer_stats.pass_cnt,
14020                                         NULL);
14021                 mtb->green_count = cnt->action;
14022         } else {
14023                 mtb->green_count = NULL;
14024         }
14025         if (fm->policer_stats.drop_cnt) {
14026                 cnt = flow_dv_counter_get_by_idx(dev,
14027                                         fm->policer_stats.drop_cnt,
14028                                         NULL);
14029                 mtb->drop_count = cnt->action;
14030         } else {
14031                 mtb->drop_count = NULL;
14032         }
14033         /**
14034          * If flow meter has been initialized, all policer rules
14035          * are created. So can get if meter initialized by checking
14036          * any policer rule.
14037          */
14038         if (mtb->egress.drop_rule)
14039                 initialized = true;
14040         if (priv->sh->meter_aso_en) {
14041                 struct mlx5_aso_mtr *aso_mtr = NULL;
14042                 struct mlx5_aso_mtr_pool *pool;
14043
14044                 aso_mtr = container_of(fm, struct mlx5_aso_mtr, fm);
14045                 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
14046                                     mtrs[aso_mtr->offset]);
14047                 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, aso_mtr->offset);
14048         } else {
14049                 struct mlx5_legacy_flow_meter *legacy_fm;
14050
14051                 legacy_fm = container_of(fm, struct mlx5_legacy_flow_meter, fm);
14052                 mtr_idx = legacy_fm->idx;
14053         }
14054         if (attr->egress) {
14055                 ret = flow_dv_create_policer_forward_rule(dev,
14056                                 fm, mtr_idx, &mtb->egress,
14057                                 &egress_drop_rule, &egress_green_rule);
14058                 if (ret) {
14059                         DRV_LOG(ERR, "Failed to create egress policer.");
14060                         goto error;
14061                 }
14062         }
14063         if (attr->ingress) {
14064                 ret = flow_dv_create_policer_forward_rule(dev,
14065                                 fm, mtr_idx, &mtb->ingress,
14066                                 &ingress_drop_rule, &ingress_green_rule);
14067                 if (ret) {
14068                         DRV_LOG(ERR, "Failed to create ingress policer.");
14069                         goto error;
14070                 }
14071         }
14072         if (attr->transfer) {
14073                 ret = flow_dv_create_policer_forward_rule(dev,
14074                                 fm, mtr_idx, &mtb->transfer,
14075                                 &transfer_drop_rule, &transfer_green_rule);
14076                 if (ret) {
14077                         DRV_LOG(ERR, "Failed to create transfer policer.");
14078                         goto error;
14079                 }
14080         }
14081         /* Replace old flows if existing. */
14082         if (mtb->egress.drop_rule)
14083                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
14084         if (mtb->egress.green_rule)
14085                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
14086         if (mtb->ingress.drop_rule)
14087                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
14088         if (mtb->ingress.green_rule)
14089                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
14090         if (mtb->transfer.drop_rule)
14091                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
14092         if (mtb->transfer.green_rule)
14093                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
14094         mtb->egress.drop_rule = egress_drop_rule;
14095         mtb->egress.green_rule = egress_green_rule;
14096         mtb->ingress.drop_rule = ingress_drop_rule;
14097         mtb->ingress.green_rule = ingress_green_rule;
14098         mtb->transfer.drop_rule = transfer_drop_rule;
14099         mtb->transfer.green_rule = transfer_green_rule;
14100         return 0;
14101 error:
14102         if (egress_drop_rule)
14103                 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
14104         if (egress_green_rule)
14105                 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
14106         if (ingress_drop_rule)
14107                 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
14108         if (ingress_green_rule)
14109                 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
14110         if (transfer_drop_rule)
14111                 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
14112         if (transfer_green_rule)
14113                 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
14114         if (!initialized)
14115                 flow_dv_destroy_policer_rules(dev, fm, attr);
14116         return -1;
14117 }
14118
14119 /**
14120  * Validate the batch counter support in root table.
14121  *
14122  * Create a simple flow with invalid counter and drop action on root table to
14123  * validate if batch counter with offset on root table is supported or not.
14124  *
14125  * @param[in] dev
14126  *   Pointer to rte_eth_dev structure.
14127  *
14128  * @return
14129  *   0 on success, a negative errno value otherwise and rte_errno is set.
14130  */
14131 int
14132 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
14133 {
14134         struct mlx5_priv *priv = dev->data->dev_private;
14135         struct mlx5_dev_ctx_shared *sh = priv->sh;
14136         struct mlx5_flow_dv_match_params mask = {
14137                 .size = sizeof(mask.buf),
14138         };
14139         struct mlx5_flow_dv_match_params value = {
14140                 .size = sizeof(value.buf),
14141         };
14142         struct mlx5dv_flow_matcher_attr dv_attr = {
14143                 .type = IBV_FLOW_ATTR_NORMAL,
14144                 .priority = 0,
14145                 .match_criteria_enable = 0,
14146                 .match_mask = (void *)&mask,
14147         };
14148         void *actions[2] = { 0 };
14149         struct mlx5_flow_tbl_resource *tbl = NULL;
14150         struct mlx5_devx_obj *dcs = NULL;
14151         void *matcher = NULL;
14152         void *flow = NULL;
14153         int ret = -1;
14154
14155         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
14156         if (!tbl)
14157                 goto err;
14158         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
14159         if (!dcs)
14160                 goto err;
14161         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
14162                                                     &actions[0]);
14163         if (ret)
14164                 goto err;
14165         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
14166                                           priv->drop_queue.hrxq->action;
14167         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
14168         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
14169                                                &matcher);
14170         if (ret)
14171                 goto err;
14172         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
14173                                        actions, &flow);
14174 err:
14175         /*
14176          * If batch counter with offset is not supported, the driver will not
14177          * validate the invalid offset value, flow create should success.
14178          * In this case, it means batch counter is not supported in root table.
14179          *
14180          * Otherwise, if flow create is failed, counter offset is supported.
14181          */
14182         if (flow) {
14183                 DRV_LOG(INFO, "Batch counter is not supported in root "
14184                               "table. Switch to fallback mode.");
14185                 rte_errno = ENOTSUP;
14186                 ret = -rte_errno;
14187                 claim_zero(mlx5_flow_os_destroy_flow(flow));
14188         } else {
14189                 /* Check matcher to make sure validate fail at flow create. */
14190                 if (!matcher || (matcher && errno != EINVAL))
14191                         DRV_LOG(ERR, "Unexpected error in counter offset "
14192                                      "support detection");
14193                 ret = 0;
14194         }
14195         if (actions[0])
14196                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14197         if (matcher)
14198                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14199         if (tbl)
14200                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14201         if (dcs)
14202                 claim_zero(mlx5_devx_cmd_destroy(dcs));
14203         return ret;
14204 }
14205
14206 /**
14207  * Query a devx counter.
14208  *
14209  * @param[in] dev
14210  *   Pointer to the Ethernet device structure.
14211  * @param[in] cnt
14212  *   Index to the flow counter.
14213  * @param[in] clear
14214  *   Set to clear the counter statistics.
14215  * @param[out] pkts
14216  *   The statistics value of packets.
14217  * @param[out] bytes
14218  *   The statistics value of bytes.
14219  *
14220  * @return
14221  *   0 on success, otherwise return -1.
14222  */
14223 static int
14224 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14225                       uint64_t *pkts, uint64_t *bytes)
14226 {
14227         struct mlx5_priv *priv = dev->data->dev_private;
14228         struct mlx5_flow_counter *cnt;
14229         uint64_t inn_pkts, inn_bytes;
14230         int ret;
14231
14232         if (!priv->config.devx)
14233                 return -1;
14234
14235         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14236         if (ret)
14237                 return -1;
14238         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14239         *pkts = inn_pkts - cnt->hits;
14240         *bytes = inn_bytes - cnt->bytes;
14241         if (clear) {
14242                 cnt->hits = inn_pkts;
14243                 cnt->bytes = inn_bytes;
14244         }
14245         return 0;
14246 }
14247
14248 /**
14249  * Get aged-out flows.
14250  *
14251  * @param[in] dev
14252  *   Pointer to the Ethernet device structure.
14253  * @param[in] context
14254  *   The address of an array of pointers to the aged-out flows contexts.
14255  * @param[in] nb_contexts
14256  *   The length of context array pointers.
14257  * @param[out] error
14258  *   Perform verbose error reporting if not NULL. Initialized in case of
14259  *   error only.
14260  *
14261  * @return
14262  *   how many contexts get in success, otherwise negative errno value.
14263  *   if nb_contexts is 0, return the amount of all aged contexts.
14264  *   if nb_contexts is not 0 , return the amount of aged flows reported
14265  *   in the context array.
14266  * @note: only stub for now
14267  */
14268 static int
14269 flow_get_aged_flows(struct rte_eth_dev *dev,
14270                     void **context,
14271                     uint32_t nb_contexts,
14272                     struct rte_flow_error *error)
14273 {
14274         struct mlx5_priv *priv = dev->data->dev_private;
14275         struct mlx5_age_info *age_info;
14276         struct mlx5_age_param *age_param;
14277         struct mlx5_flow_counter *counter;
14278         struct mlx5_aso_age_action *act;
14279         int nb_flows = 0;
14280
14281         if (nb_contexts && !context)
14282                 return rte_flow_error_set(error, EINVAL,
14283                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14284                                           NULL, "empty context");
14285         age_info = GET_PORT_AGE_INFO(priv);
14286         rte_spinlock_lock(&age_info->aged_sl);
14287         LIST_FOREACH(act, &age_info->aged_aso, next) {
14288                 nb_flows++;
14289                 if (nb_contexts) {
14290                         context[nb_flows - 1] =
14291                                                 act->age_params.context;
14292                         if (!(--nb_contexts))
14293                                 break;
14294                 }
14295         }
14296         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14297                 nb_flows++;
14298                 if (nb_contexts) {
14299                         age_param = MLX5_CNT_TO_AGE(counter);
14300                         context[nb_flows - 1] = age_param->context;
14301                         if (!(--nb_contexts))
14302                                 break;
14303                 }
14304         }
14305         rte_spinlock_unlock(&age_info->aged_sl);
14306         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14307         return nb_flows;
14308 }
14309
14310 /*
14311  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14312  */
14313 static uint32_t
14314 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14315 {
14316         return flow_dv_counter_alloc(dev, 0);
14317 }
14318
14319 /**
14320  * Validate indirect action.
14321  * Dispatcher for action type specific validation.
14322  *
14323  * @param[in] dev
14324  *   Pointer to the Ethernet device structure.
14325  * @param[in] conf
14326  *   Shared action configuration.
14327  * @param[in] action
14328  *   The indirect action object to validate.
14329  * @param[out] error
14330  *   Perform verbose error reporting if not NULL. Initialized in case of
14331  *   error only.
14332  *
14333  * @return
14334  *   0 on success, otherwise negative errno value.
14335  */
14336 static int
14337 flow_dv_action_validate(struct rte_eth_dev *dev,
14338                         const struct rte_flow_indir_action_conf *conf,
14339                         const struct rte_flow_action *action,
14340                         struct rte_flow_error *err)
14341 {
14342         struct mlx5_priv *priv = dev->data->dev_private;
14343
14344         RTE_SET_USED(conf);
14345         switch (action->type) {
14346         case RTE_FLOW_ACTION_TYPE_RSS:
14347                 /*
14348                  * priv->obj_ops is set according to driver capabilities.
14349                  * When DevX capabilities are
14350                  * sufficient, it is set to devx_obj_ops.
14351                  * Otherwise, it is set to ibv_obj_ops.
14352                  * ibv_obj_ops doesn't support ind_table_modify operation.
14353                  * In this case the shared RSS action can't be used.
14354                  */
14355                 if (priv->obj_ops.ind_table_modify == NULL)
14356                         return rte_flow_error_set
14357                                         (err, ENOTSUP,
14358                                          RTE_FLOW_ERROR_TYPE_ACTION,
14359                                          NULL,
14360                                          "shared RSS action not supported");
14361                 return mlx5_validate_action_rss(dev, action, err);
14362         case RTE_FLOW_ACTION_TYPE_AGE:
14363                 if (!priv->sh->aso_age_mng)
14364                         return rte_flow_error_set(err, ENOTSUP,
14365                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14366                                                 NULL,
14367                                              "shared age action not supported");
14368                 return flow_dv_validate_action_age(0, action, dev, err);
14369         default:
14370                 return rte_flow_error_set(err, ENOTSUP,
14371                                           RTE_FLOW_ERROR_TYPE_ACTION,
14372                                           NULL,
14373                                           "action type not supported");
14374         }
14375 }
14376
14377 static int
14378 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14379 {
14380         struct mlx5_priv *priv = dev->data->dev_private;
14381         int ret = 0;
14382
14383         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14384                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14385                                                 flags);
14386                 if (ret != 0)
14387                         return ret;
14388         }
14389         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14390                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14391                 if (ret != 0)
14392                         return ret;
14393         }
14394         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14395                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14396                 if (ret != 0)
14397                         return ret;
14398         }
14399         return 0;
14400 }
14401
14402 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14403         .validate = flow_dv_validate,
14404         .prepare = flow_dv_prepare,
14405         .translate = flow_dv_translate,
14406         .apply = flow_dv_apply,
14407         .remove = flow_dv_remove,
14408         .destroy = flow_dv_destroy,
14409         .query = flow_dv_query,
14410         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14411         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14412         .prepare_policer_rules = flow_dv_prepare_policer_rules,
14413         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14414         .create_meter = flow_dv_mtr_alloc,
14415         .free_meter = flow_dv_aso_mtr_release_to_pool,
14416         .counter_alloc = flow_dv_counter_allocate,
14417         .counter_free = flow_dv_counter_free,
14418         .counter_query = flow_dv_counter_query,
14419         .get_aged_flows = flow_get_aged_flows,
14420         .action_validate = flow_dv_action_validate,
14421         .action_create = flow_dv_action_create,
14422         .action_destroy = flow_dv_action_destroy,
14423         .action_update = flow_dv_action_update,
14424         .action_query = flow_dv_action_query,
14425         .sync_domain = flow_dv_sync_domain,
14426 };
14427
14428 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14429