1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
37 #include "rte_pmd_mlx5.h"
39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 /* VLAN header definitions */
56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
76 struct mlx5_flow_tbl_resource *tbl);
79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
80 uint32_t encap_decap_idx);
83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
93 * Initialize flow attributes structure according to flow items' types.
95 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
96 * mode. For tunnel mode, the items to be modified are the outermost ones.
99 * Pointer to item specification.
101 * Pointer to flow attributes structure.
102 * @param[in] dev_flow
103 * Pointer to the sub flow.
104 * @param[in] tunnel_decap
105 * Whether action is after tunnel decapsulation.
108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
109 struct mlx5_flow *dev_flow, bool tunnel_decap)
111 uint64_t layers = dev_flow->handle->layers;
114 * If layers is already initialized, it means this dev_flow is the
115 * suffix flow, the layers flags is set by the prefix flow. Need to
116 * use the layer flags from prefix flow as the suffix flow may not
117 * have the user defined items as the flow is split.
120 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
122 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
131 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
132 uint8_t next_protocol = 0xff;
133 switch (item->type) {
134 case RTE_FLOW_ITEM_TYPE_GRE:
135 case RTE_FLOW_ITEM_TYPE_NVGRE:
136 case RTE_FLOW_ITEM_TYPE_VXLAN:
137 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
138 case RTE_FLOW_ITEM_TYPE_GENEVE:
139 case RTE_FLOW_ITEM_TYPE_MPLS:
143 case RTE_FLOW_ITEM_TYPE_IPV4:
146 if (item->mask != NULL &&
147 ((const struct rte_flow_item_ipv4 *)
148 item->mask)->hdr.next_proto_id)
150 ((const struct rte_flow_item_ipv4 *)
151 (item->spec))->hdr.next_proto_id &
152 ((const struct rte_flow_item_ipv4 *)
153 (item->mask))->hdr.next_proto_id;
154 if ((next_protocol == IPPROTO_IPIP ||
155 next_protocol == IPPROTO_IPV6) && tunnel_decap)
158 case RTE_FLOW_ITEM_TYPE_IPV6:
161 if (item->mask != NULL &&
162 ((const struct rte_flow_item_ipv6 *)
163 item->mask)->hdr.proto)
165 ((const struct rte_flow_item_ipv6 *)
166 (item->spec))->hdr.proto &
167 ((const struct rte_flow_item_ipv6 *)
168 (item->mask))->hdr.proto;
169 if ((next_protocol == IPPROTO_IPIP ||
170 next_protocol == IPPROTO_IPV6) && tunnel_decap)
173 case RTE_FLOW_ITEM_TYPE_UDP:
177 case RTE_FLOW_ITEM_TYPE_TCP:
189 * Convert rte_mtr_color to mlx5 color.
198 rte_col_2_mlx5_col(enum rte_color rcol)
201 case RTE_COLOR_GREEN:
202 return MLX5_FLOW_COLOR_GREEN;
203 case RTE_COLOR_YELLOW:
204 return MLX5_FLOW_COLOR_YELLOW;
206 return MLX5_FLOW_COLOR_RED;
210 return MLX5_FLOW_COLOR_UNDEFINED;
213 struct field_modify_info {
214 uint32_t size; /* Size of field in protocol header, in bytes. */
215 uint32_t offset; /* Offset of field in protocol header, in bytes. */
216 enum mlx5_modification_field id;
219 struct field_modify_info modify_eth[] = {
220 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
221 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
222 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
223 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
227 struct field_modify_info modify_vlan_out_first_vid[] = {
228 /* Size in bits !!! */
229 {12, 0, MLX5_MODI_OUT_FIRST_VID},
233 struct field_modify_info modify_ipv4[] = {
234 {1, 1, MLX5_MODI_OUT_IP_DSCP},
235 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
236 {4, 12, MLX5_MODI_OUT_SIPV4},
237 {4, 16, MLX5_MODI_OUT_DIPV4},
241 struct field_modify_info modify_ipv6[] = {
242 {1, 0, MLX5_MODI_OUT_IP_DSCP},
243 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
244 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
245 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
246 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
247 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
248 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
249 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
250 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
251 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
255 struct field_modify_info modify_udp[] = {
256 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
257 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
261 struct field_modify_info modify_tcp[] = {
262 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
263 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
264 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
265 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
271 uint8_t next_protocol, uint64_t *item_flags,
274 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
275 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
276 if (next_protocol == IPPROTO_IPIP) {
277 *item_flags |= MLX5_FLOW_LAYER_IPIP;
280 if (next_protocol == IPPROTO_IPV6) {
281 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
286 /* Update VLAN's VID/PCP based on input rte_flow_action.
289 * Pointer to struct rte_flow_action.
291 * Pointer to struct rte_vlan_hdr.
294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
295 struct rte_vlan_hdr *vlan)
298 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
300 ((const struct rte_flow_action_of_set_vlan_pcp *)
301 action->conf)->vlan_pcp;
302 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
303 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
304 vlan->vlan_tci |= vlan_tci;
305 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
306 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
307 vlan->vlan_tci |= rte_be_to_cpu_16
308 (((const struct rte_flow_action_of_set_vlan_vid *)
309 action->conf)->vlan_vid);
314 * Fetch 1, 2, 3 or 4 byte field from the byte array
315 * and return as unsigned integer in host-endian format.
318 * Pointer to data array.
320 * Size of field to extract.
323 * converted field in host endian format.
325 static inline uint32_t
326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
335 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
339 ret = (ret << 8) | *(data + sizeof(uint16_t));
342 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
353 * Convert modify-header action to DV specification.
355 * Data length of each action is determined by provided field description
356 * and the item mask. Data bit offset and width of each action is determined
357 * by provided item mask.
360 * Pointer to item specification.
362 * Pointer to field modification information.
363 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
365 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
367 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
368 * Negative offset value sets the same offset as source offset.
369 * size field is ignored, value is taken from source field.
370 * @param[in,out] resource
371 * Pointer to the modify-header resource.
373 * Type of modification.
375 * Pointer to the error structure.
378 * 0 on success, a negative errno value otherwise and rte_errno is set.
381 flow_dv_convert_modify_action(struct rte_flow_item *item,
382 struct field_modify_info *field,
383 struct field_modify_info *dcopy,
384 struct mlx5_flow_dv_modify_hdr_resource *resource,
385 uint32_t type, struct rte_flow_error *error)
387 uint32_t i = resource->actions_num;
388 struct mlx5_modification_cmd *actions = resource->actions;
391 * The item and mask are provided in big-endian format.
392 * The fields should be presented as in big-endian format either.
393 * Mask must be always present, it defines the actual field width.
395 MLX5_ASSERT(item->mask);
396 MLX5_ASSERT(field->size);
403 if (i >= MLX5_MAX_MODIFY_NUM)
404 return rte_flow_error_set(error, EINVAL,
405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
406 "too many items to modify");
407 /* Fetch variable byte size mask from the array. */
408 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
409 field->offset, field->size);
414 /* Deduce actual data width in bits from mask value. */
415 off_b = rte_bsf32(mask);
416 size_b = sizeof(uint32_t) * CHAR_BIT -
417 off_b - __builtin_clz(mask);
419 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
420 actions[i] = (struct mlx5_modification_cmd) {
426 /* Convert entire record to expected big-endian format. */
427 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
428 if (type == MLX5_MODIFICATION_TYPE_COPY) {
430 actions[i].dst_field = dcopy->id;
431 actions[i].dst_offset =
432 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
433 /* Convert entire record to big-endian format. */
434 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
437 MLX5_ASSERT(item->spec);
438 data = flow_dv_fetch_field((const uint8_t *)item->spec +
439 field->offset, field->size);
440 /* Shift out the trailing masked bits from data. */
441 data = (data & mask) >> off_b;
442 actions[i].data1 = rte_cpu_to_be_32(data);
446 } while (field->size);
447 if (resource->actions_num == i)
448 return rte_flow_error_set(error, EINVAL,
449 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
450 "invalid modification flow item");
451 resource->actions_num = i;
456 * Convert modify-header set IPv4 address action to DV specification.
458 * @param[in,out] resource
459 * Pointer to the modify-header resource.
461 * Pointer to action specification.
463 * Pointer to the error structure.
466 * 0 on success, a negative errno value otherwise and rte_errno is set.
469 flow_dv_convert_action_modify_ipv4
470 (struct mlx5_flow_dv_modify_hdr_resource *resource,
471 const struct rte_flow_action *action,
472 struct rte_flow_error *error)
474 const struct rte_flow_action_set_ipv4 *conf =
475 (const struct rte_flow_action_set_ipv4 *)(action->conf);
476 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
477 struct rte_flow_item_ipv4 ipv4;
478 struct rte_flow_item_ipv4 ipv4_mask;
480 memset(&ipv4, 0, sizeof(ipv4));
481 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
482 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
483 ipv4.hdr.src_addr = conf->ipv4_addr;
484 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
486 ipv4.hdr.dst_addr = conf->ipv4_addr;
487 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
490 item.mask = &ipv4_mask;
491 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
492 MLX5_MODIFICATION_TYPE_SET, error);
496 * Convert modify-header set IPv6 address action to DV specification.
498 * @param[in,out] resource
499 * Pointer to the modify-header resource.
501 * Pointer to action specification.
503 * Pointer to the error structure.
506 * 0 on success, a negative errno value otherwise and rte_errno is set.
509 flow_dv_convert_action_modify_ipv6
510 (struct mlx5_flow_dv_modify_hdr_resource *resource,
511 const struct rte_flow_action *action,
512 struct rte_flow_error *error)
514 const struct rte_flow_action_set_ipv6 *conf =
515 (const struct rte_flow_action_set_ipv6 *)(action->conf);
516 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
517 struct rte_flow_item_ipv6 ipv6;
518 struct rte_flow_item_ipv6 ipv6_mask;
520 memset(&ipv6, 0, sizeof(ipv6));
521 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
522 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
523 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
524 sizeof(ipv6.hdr.src_addr));
525 memcpy(&ipv6_mask.hdr.src_addr,
526 &rte_flow_item_ipv6_mask.hdr.src_addr,
527 sizeof(ipv6.hdr.src_addr));
529 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
530 sizeof(ipv6.hdr.dst_addr));
531 memcpy(&ipv6_mask.hdr.dst_addr,
532 &rte_flow_item_ipv6_mask.hdr.dst_addr,
533 sizeof(ipv6.hdr.dst_addr));
536 item.mask = &ipv6_mask;
537 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
538 MLX5_MODIFICATION_TYPE_SET, error);
542 * Convert modify-header set MAC address action to DV specification.
544 * @param[in,out] resource
545 * Pointer to the modify-header resource.
547 * Pointer to action specification.
549 * Pointer to the error structure.
552 * 0 on success, a negative errno value otherwise and rte_errno is set.
555 flow_dv_convert_action_modify_mac
556 (struct mlx5_flow_dv_modify_hdr_resource *resource,
557 const struct rte_flow_action *action,
558 struct rte_flow_error *error)
560 const struct rte_flow_action_set_mac *conf =
561 (const struct rte_flow_action_set_mac *)(action->conf);
562 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
563 struct rte_flow_item_eth eth;
564 struct rte_flow_item_eth eth_mask;
566 memset(ð, 0, sizeof(eth));
567 memset(ð_mask, 0, sizeof(eth_mask));
568 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
569 memcpy(ð.src.addr_bytes, &conf->mac_addr,
570 sizeof(eth.src.addr_bytes));
571 memcpy(ð_mask.src.addr_bytes,
572 &rte_flow_item_eth_mask.src.addr_bytes,
573 sizeof(eth_mask.src.addr_bytes));
575 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
576 sizeof(eth.dst.addr_bytes));
577 memcpy(ð_mask.dst.addr_bytes,
578 &rte_flow_item_eth_mask.dst.addr_bytes,
579 sizeof(eth_mask.dst.addr_bytes));
582 item.mask = ð_mask;
583 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
584 MLX5_MODIFICATION_TYPE_SET, error);
588 * Convert modify-header set VLAN VID action to DV specification.
590 * @param[in,out] resource
591 * Pointer to the modify-header resource.
593 * Pointer to action specification.
595 * Pointer to the error structure.
598 * 0 on success, a negative errno value otherwise and rte_errno is set.
601 flow_dv_convert_action_modify_vlan_vid
602 (struct mlx5_flow_dv_modify_hdr_resource *resource,
603 const struct rte_flow_action *action,
604 struct rte_flow_error *error)
606 const struct rte_flow_action_of_set_vlan_vid *conf =
607 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
608 int i = resource->actions_num;
609 struct mlx5_modification_cmd *actions = resource->actions;
610 struct field_modify_info *field = modify_vlan_out_first_vid;
612 if (i >= MLX5_MAX_MODIFY_NUM)
613 return rte_flow_error_set(error, EINVAL,
614 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
615 "too many items to modify");
616 actions[i] = (struct mlx5_modification_cmd) {
617 .action_type = MLX5_MODIFICATION_TYPE_SET,
619 .length = field->size,
620 .offset = field->offset,
622 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
623 actions[i].data1 = conf->vlan_vid;
624 actions[i].data1 = actions[i].data1 << 16;
625 resource->actions_num = ++i;
630 * Convert modify-header set TP action to DV specification.
632 * @param[in,out] resource
633 * Pointer to the modify-header resource.
635 * Pointer to action specification.
637 * Pointer to rte_flow_item objects list.
639 * Pointer to flow attributes structure.
640 * @param[in] dev_flow
641 * Pointer to the sub flow.
642 * @param[in] tunnel_decap
643 * Whether action is after tunnel decapsulation.
645 * Pointer to the error structure.
648 * 0 on success, a negative errno value otherwise and rte_errno is set.
651 flow_dv_convert_action_modify_tp
652 (struct mlx5_flow_dv_modify_hdr_resource *resource,
653 const struct rte_flow_action *action,
654 const struct rte_flow_item *items,
655 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
656 bool tunnel_decap, struct rte_flow_error *error)
658 const struct rte_flow_action_set_tp *conf =
659 (const struct rte_flow_action_set_tp *)(action->conf);
660 struct rte_flow_item item;
661 struct rte_flow_item_udp udp;
662 struct rte_flow_item_udp udp_mask;
663 struct rte_flow_item_tcp tcp;
664 struct rte_flow_item_tcp tcp_mask;
665 struct field_modify_info *field;
668 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
670 memset(&udp, 0, sizeof(udp));
671 memset(&udp_mask, 0, sizeof(udp_mask));
672 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
673 udp.hdr.src_port = conf->port;
674 udp_mask.hdr.src_port =
675 rte_flow_item_udp_mask.hdr.src_port;
677 udp.hdr.dst_port = conf->port;
678 udp_mask.hdr.dst_port =
679 rte_flow_item_udp_mask.hdr.dst_port;
681 item.type = RTE_FLOW_ITEM_TYPE_UDP;
683 item.mask = &udp_mask;
686 MLX5_ASSERT(attr->tcp);
687 memset(&tcp, 0, sizeof(tcp));
688 memset(&tcp_mask, 0, sizeof(tcp_mask));
689 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
690 tcp.hdr.src_port = conf->port;
691 tcp_mask.hdr.src_port =
692 rte_flow_item_tcp_mask.hdr.src_port;
694 tcp.hdr.dst_port = conf->port;
695 tcp_mask.hdr.dst_port =
696 rte_flow_item_tcp_mask.hdr.dst_port;
698 item.type = RTE_FLOW_ITEM_TYPE_TCP;
700 item.mask = &tcp_mask;
703 return flow_dv_convert_modify_action(&item, field, NULL, resource,
704 MLX5_MODIFICATION_TYPE_SET, error);
708 * Convert modify-header set TTL action to DV specification.
710 * @param[in,out] resource
711 * Pointer to the modify-header resource.
713 * Pointer to action specification.
715 * Pointer to rte_flow_item objects list.
717 * Pointer to flow attributes structure.
718 * @param[in] dev_flow
719 * Pointer to the sub flow.
720 * @param[in] tunnel_decap
721 * Whether action is after tunnel decapsulation.
723 * Pointer to the error structure.
726 * 0 on success, a negative errno value otherwise and rte_errno is set.
729 flow_dv_convert_action_modify_ttl
730 (struct mlx5_flow_dv_modify_hdr_resource *resource,
731 const struct rte_flow_action *action,
732 const struct rte_flow_item *items,
733 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
734 bool tunnel_decap, struct rte_flow_error *error)
736 const struct rte_flow_action_set_ttl *conf =
737 (const struct rte_flow_action_set_ttl *)(action->conf);
738 struct rte_flow_item item;
739 struct rte_flow_item_ipv4 ipv4;
740 struct rte_flow_item_ipv4 ipv4_mask;
741 struct rte_flow_item_ipv6 ipv6;
742 struct rte_flow_item_ipv6 ipv6_mask;
743 struct field_modify_info *field;
746 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
748 memset(&ipv4, 0, sizeof(ipv4));
749 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
750 ipv4.hdr.time_to_live = conf->ttl_value;
751 ipv4_mask.hdr.time_to_live = 0xFF;
752 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
754 item.mask = &ipv4_mask;
757 MLX5_ASSERT(attr->ipv6);
758 memset(&ipv6, 0, sizeof(ipv6));
759 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
760 ipv6.hdr.hop_limits = conf->ttl_value;
761 ipv6_mask.hdr.hop_limits = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
764 item.mask = &ipv6_mask;
767 return flow_dv_convert_modify_action(&item, field, NULL, resource,
768 MLX5_MODIFICATION_TYPE_SET, error);
772 * Convert modify-header decrement TTL action to DV specification.
774 * @param[in,out] resource
775 * Pointer to the modify-header resource.
777 * Pointer to action specification.
779 * Pointer to rte_flow_item objects list.
781 * Pointer to flow attributes structure.
782 * @param[in] dev_flow
783 * Pointer to the sub flow.
784 * @param[in] tunnel_decap
785 * Whether action is after tunnel decapsulation.
787 * Pointer to the error structure.
790 * 0 on success, a negative errno value otherwise and rte_errno is set.
793 flow_dv_convert_action_modify_dec_ttl
794 (struct mlx5_flow_dv_modify_hdr_resource *resource,
795 const struct rte_flow_item *items,
796 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
797 bool tunnel_decap, struct rte_flow_error *error)
799 struct rte_flow_item item;
800 struct rte_flow_item_ipv4 ipv4;
801 struct rte_flow_item_ipv4 ipv4_mask;
802 struct rte_flow_item_ipv6 ipv6;
803 struct rte_flow_item_ipv6 ipv6_mask;
804 struct field_modify_info *field;
807 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
809 memset(&ipv4, 0, sizeof(ipv4));
810 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
811 ipv4.hdr.time_to_live = 0xFF;
812 ipv4_mask.hdr.time_to_live = 0xFF;
813 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
815 item.mask = &ipv4_mask;
818 MLX5_ASSERT(attr->ipv6);
819 memset(&ipv6, 0, sizeof(ipv6));
820 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
821 ipv6.hdr.hop_limits = 0xFF;
822 ipv6_mask.hdr.hop_limits = 0xFF;
823 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
825 item.mask = &ipv6_mask;
828 return flow_dv_convert_modify_action(&item, field, NULL, resource,
829 MLX5_MODIFICATION_TYPE_ADD, error);
833 * Convert modify-header increment/decrement TCP Sequence number
834 * to DV specification.
836 * @param[in,out] resource
837 * Pointer to the modify-header resource.
839 * Pointer to action specification.
841 * Pointer to the error structure.
844 * 0 on success, a negative errno value otherwise and rte_errno is set.
847 flow_dv_convert_action_modify_tcp_seq
848 (struct mlx5_flow_dv_modify_hdr_resource *resource,
849 const struct rte_flow_action *action,
850 struct rte_flow_error *error)
852 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
853 uint64_t value = rte_be_to_cpu_32(*conf);
854 struct rte_flow_item item;
855 struct rte_flow_item_tcp tcp;
856 struct rte_flow_item_tcp tcp_mask;
858 memset(&tcp, 0, sizeof(tcp));
859 memset(&tcp_mask, 0, sizeof(tcp_mask));
860 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
862 * The HW has no decrement operation, only increment operation.
863 * To simulate decrement X from Y using increment operation
864 * we need to add UINT32_MAX X times to Y.
865 * Each adding of UINT32_MAX decrements Y by 1.
868 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
869 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
870 item.type = RTE_FLOW_ITEM_TYPE_TCP;
872 item.mask = &tcp_mask;
873 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
874 MLX5_MODIFICATION_TYPE_ADD, error);
878 * Convert modify-header increment/decrement TCP Acknowledgment number
879 * to DV specification.
881 * @param[in,out] resource
882 * Pointer to the modify-header resource.
884 * Pointer to action specification.
886 * Pointer to the error structure.
889 * 0 on success, a negative errno value otherwise and rte_errno is set.
892 flow_dv_convert_action_modify_tcp_ack
893 (struct mlx5_flow_dv_modify_hdr_resource *resource,
894 const struct rte_flow_action *action,
895 struct rte_flow_error *error)
897 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
898 uint64_t value = rte_be_to_cpu_32(*conf);
899 struct rte_flow_item item;
900 struct rte_flow_item_tcp tcp;
901 struct rte_flow_item_tcp tcp_mask;
903 memset(&tcp, 0, sizeof(tcp));
904 memset(&tcp_mask, 0, sizeof(tcp_mask));
905 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
907 * The HW has no decrement operation, only increment operation.
908 * To simulate decrement X from Y using increment operation
909 * we need to add UINT32_MAX X times to Y.
910 * Each adding of UINT32_MAX decrements Y by 1.
913 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
914 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
915 item.type = RTE_FLOW_ITEM_TYPE_TCP;
917 item.mask = &tcp_mask;
918 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
919 MLX5_MODIFICATION_TYPE_ADD, error);
922 static enum mlx5_modification_field reg_to_field[] = {
923 [REG_NON] = MLX5_MODI_OUT_NONE,
924 [REG_A] = MLX5_MODI_META_DATA_REG_A,
925 [REG_B] = MLX5_MODI_META_DATA_REG_B,
926 [REG_C_0] = MLX5_MODI_META_REG_C_0,
927 [REG_C_1] = MLX5_MODI_META_REG_C_1,
928 [REG_C_2] = MLX5_MODI_META_REG_C_2,
929 [REG_C_3] = MLX5_MODI_META_REG_C_3,
930 [REG_C_4] = MLX5_MODI_META_REG_C_4,
931 [REG_C_5] = MLX5_MODI_META_REG_C_5,
932 [REG_C_6] = MLX5_MODI_META_REG_C_6,
933 [REG_C_7] = MLX5_MODI_META_REG_C_7,
937 * Convert register set to DV specification.
939 * @param[in,out] resource
940 * Pointer to the modify-header resource.
942 * Pointer to action specification.
944 * Pointer to the error structure.
947 * 0 on success, a negative errno value otherwise and rte_errno is set.
950 flow_dv_convert_action_set_reg
951 (struct mlx5_flow_dv_modify_hdr_resource *resource,
952 const struct rte_flow_action *action,
953 struct rte_flow_error *error)
955 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
956 struct mlx5_modification_cmd *actions = resource->actions;
957 uint32_t i = resource->actions_num;
959 if (i >= MLX5_MAX_MODIFY_NUM)
960 return rte_flow_error_set(error, EINVAL,
961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
962 "too many items to modify");
963 MLX5_ASSERT(conf->id != REG_NON);
964 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
965 actions[i] = (struct mlx5_modification_cmd) {
966 .action_type = MLX5_MODIFICATION_TYPE_SET,
967 .field = reg_to_field[conf->id],
968 .offset = conf->offset,
969 .length = conf->length,
971 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
972 actions[i].data1 = rte_cpu_to_be_32(conf->data);
974 resource->actions_num = i;
979 * Convert SET_TAG action to DV specification.
982 * Pointer to the rte_eth_dev structure.
983 * @param[in,out] resource
984 * Pointer to the modify-header resource.
986 * Pointer to action specification.
988 * Pointer to the error structure.
991 * 0 on success, a negative errno value otherwise and rte_errno is set.
994 flow_dv_convert_action_set_tag
995 (struct rte_eth_dev *dev,
996 struct mlx5_flow_dv_modify_hdr_resource *resource,
997 const struct rte_flow_action_set_tag *conf,
998 struct rte_flow_error *error)
1000 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1001 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1002 struct rte_flow_item item = {
1006 struct field_modify_info reg_c_x[] = {
1009 enum mlx5_modification_field reg_type;
1012 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1015 MLX5_ASSERT(ret != REG_NON);
1016 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1017 reg_type = reg_to_field[ret];
1018 MLX5_ASSERT(reg_type > 0);
1019 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1020 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1021 MLX5_MODIFICATION_TYPE_SET, error);
1025 * Convert internal COPY_REG action to DV specification.
1028 * Pointer to the rte_eth_dev structure.
1029 * @param[in,out] res
1030 * Pointer to the modify-header resource.
1032 * Pointer to action specification.
1034 * Pointer to the error structure.
1037 * 0 on success, a negative errno value otherwise and rte_errno is set.
1040 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1041 struct mlx5_flow_dv_modify_hdr_resource *res,
1042 const struct rte_flow_action *action,
1043 struct rte_flow_error *error)
1045 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1046 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1047 struct rte_flow_item item = {
1051 struct field_modify_info reg_src[] = {
1052 {4, 0, reg_to_field[conf->src]},
1055 struct field_modify_info reg_dst = {
1057 .id = reg_to_field[conf->dst],
1059 /* Adjust reg_c[0] usage according to reported mask. */
1060 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1061 struct mlx5_priv *priv = dev->data->dev_private;
1062 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1064 MLX5_ASSERT(reg_c0);
1065 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1066 if (conf->dst == REG_C_0) {
1067 /* Copy to reg_c[0], within mask only. */
1068 reg_dst.offset = rte_bsf32(reg_c0);
1070 * Mask is ignoring the enianness, because
1071 * there is no conversion in datapath.
1073 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1074 /* Copy from destination lower bits to reg_c[0]. */
1075 mask = reg_c0 >> reg_dst.offset;
1077 /* Copy from destination upper bits to reg_c[0]. */
1078 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1079 rte_fls_u32(reg_c0));
1082 mask = rte_cpu_to_be_32(reg_c0);
1083 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1084 /* Copy from reg_c[0] to destination lower bits. */
1087 /* Copy from reg_c[0] to destination upper bits. */
1088 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1089 (rte_fls_u32(reg_c0) -
1094 return flow_dv_convert_modify_action(&item,
1095 reg_src, ®_dst, res,
1096 MLX5_MODIFICATION_TYPE_COPY,
1101 * Convert MARK action to DV specification. This routine is used
1102 * in extensive metadata only and requires metadata register to be
1103 * handled. In legacy mode hardware tag resource is engaged.
1106 * Pointer to the rte_eth_dev structure.
1108 * Pointer to MARK action specification.
1109 * @param[in,out] resource
1110 * Pointer to the modify-header resource.
1112 * Pointer to the error structure.
1115 * 0 on success, a negative errno value otherwise and rte_errno is set.
1118 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1119 const struct rte_flow_action_mark *conf,
1120 struct mlx5_flow_dv_modify_hdr_resource *resource,
1121 struct rte_flow_error *error)
1123 struct mlx5_priv *priv = dev->data->dev_private;
1124 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1125 priv->sh->dv_mark_mask);
1126 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1127 struct rte_flow_item item = {
1131 struct field_modify_info reg_c_x[] = {
1137 return rte_flow_error_set(error, EINVAL,
1138 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1139 NULL, "zero mark action mask");
1140 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1143 MLX5_ASSERT(reg > 0);
1144 if (reg == REG_C_0) {
1145 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1146 uint32_t shl_c0 = rte_bsf32(msk_c0);
1148 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1149 mask = rte_cpu_to_be_32(mask) & msk_c0;
1150 mask = rte_cpu_to_be_32(mask << shl_c0);
1152 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1153 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1154 MLX5_MODIFICATION_TYPE_SET, error);
1158 * Get metadata register index for specified steering domain.
1161 * Pointer to the rte_eth_dev structure.
1163 * Attributes of flow to determine steering domain.
1165 * Pointer to the error structure.
1168 * positive index on success, a negative errno value otherwise
1169 * and rte_errno is set.
1171 static enum modify_reg
1172 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1173 const struct rte_flow_attr *attr,
1174 struct rte_flow_error *error)
1177 mlx5_flow_get_reg_id(dev, attr->transfer ?
1181 MLX5_METADATA_RX, 0, error);
1183 return rte_flow_error_set(error,
1184 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1185 NULL, "unavailable "
1186 "metadata register");
1191 * Convert SET_META action to DV specification.
1194 * Pointer to the rte_eth_dev structure.
1195 * @param[in,out] resource
1196 * Pointer to the modify-header resource.
1198 * Attributes of flow that includes this item.
1200 * Pointer to action specification.
1202 * Pointer to the error structure.
1205 * 0 on success, a negative errno value otherwise and rte_errno is set.
1208 flow_dv_convert_action_set_meta
1209 (struct rte_eth_dev *dev,
1210 struct mlx5_flow_dv_modify_hdr_resource *resource,
1211 const struct rte_flow_attr *attr,
1212 const struct rte_flow_action_set_meta *conf,
1213 struct rte_flow_error *error)
1215 uint32_t data = conf->data;
1216 uint32_t mask = conf->mask;
1217 struct rte_flow_item item = {
1221 struct field_modify_info reg_c_x[] = {
1224 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1228 MLX5_ASSERT(reg != REG_NON);
1230 * In datapath code there is no endianness
1231 * coversions for perfromance reasons, all
1232 * pattern conversions are done in rte_flow.
1234 if (reg == REG_C_0) {
1235 struct mlx5_priv *priv = dev->data->dev_private;
1236 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1239 MLX5_ASSERT(msk_c0);
1240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1241 shl_c0 = rte_bsf32(msk_c0);
1243 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1247 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1249 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1250 /* The routine expects parameters in memory as big-endian ones. */
1251 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1252 MLX5_MODIFICATION_TYPE_SET, error);
1256 * Convert modify-header set IPv4 DSCP action to DV specification.
1258 * @param[in,out] resource
1259 * Pointer to the modify-header resource.
1261 * Pointer to action specification.
1263 * Pointer to the error structure.
1266 * 0 on success, a negative errno value otherwise and rte_errno is set.
1269 flow_dv_convert_action_modify_ipv4_dscp
1270 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1271 const struct rte_flow_action *action,
1272 struct rte_flow_error *error)
1274 const struct rte_flow_action_set_dscp *conf =
1275 (const struct rte_flow_action_set_dscp *)(action->conf);
1276 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1277 struct rte_flow_item_ipv4 ipv4;
1278 struct rte_flow_item_ipv4 ipv4_mask;
1280 memset(&ipv4, 0, sizeof(ipv4));
1281 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1282 ipv4.hdr.type_of_service = conf->dscp;
1283 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1285 item.mask = &ipv4_mask;
1286 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1287 MLX5_MODIFICATION_TYPE_SET, error);
1291 * Convert modify-header set IPv6 DSCP action to DV specification.
1293 * @param[in,out] resource
1294 * Pointer to the modify-header resource.
1296 * Pointer to action specification.
1298 * Pointer to the error structure.
1301 * 0 on success, a negative errno value otherwise and rte_errno is set.
1304 flow_dv_convert_action_modify_ipv6_dscp
1305 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1306 const struct rte_flow_action *action,
1307 struct rte_flow_error *error)
1309 const struct rte_flow_action_set_dscp *conf =
1310 (const struct rte_flow_action_set_dscp *)(action->conf);
1311 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1312 struct rte_flow_item_ipv6 ipv6;
1313 struct rte_flow_item_ipv6 ipv6_mask;
1315 memset(&ipv6, 0, sizeof(ipv6));
1316 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1318 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1319 * rdma-core only accept the DSCP bits byte aligned start from
1320 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1321 * bits in IPv6 case as rdma-core requires byte aligned value.
1323 ipv6.hdr.vtc_flow = conf->dscp;
1324 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1326 item.mask = &ipv6_mask;
1327 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1328 MLX5_MODIFICATION_TYPE_SET, error);
1332 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1335 case RTE_FLOW_FIELD_START:
1337 case RTE_FLOW_FIELD_MAC_DST:
1338 case RTE_FLOW_FIELD_MAC_SRC:
1340 case RTE_FLOW_FIELD_VLAN_TYPE:
1342 case RTE_FLOW_FIELD_VLAN_ID:
1344 case RTE_FLOW_FIELD_MAC_TYPE:
1346 case RTE_FLOW_FIELD_IPV4_DSCP:
1348 case RTE_FLOW_FIELD_IPV4_TTL:
1350 case RTE_FLOW_FIELD_IPV4_SRC:
1351 case RTE_FLOW_FIELD_IPV4_DST:
1353 case RTE_FLOW_FIELD_IPV6_DSCP:
1355 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1357 case RTE_FLOW_FIELD_IPV6_SRC:
1358 case RTE_FLOW_FIELD_IPV6_DST:
1360 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1361 case RTE_FLOW_FIELD_TCP_PORT_DST:
1363 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1364 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1366 case RTE_FLOW_FIELD_TCP_FLAGS:
1368 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1369 case RTE_FLOW_FIELD_UDP_PORT_DST:
1371 case RTE_FLOW_FIELD_VXLAN_VNI:
1372 case RTE_FLOW_FIELD_GENEVE_VNI:
1374 case RTE_FLOW_FIELD_GTP_TEID:
1375 case RTE_FLOW_FIELD_TAG:
1377 case RTE_FLOW_FIELD_MARK:
1379 case RTE_FLOW_FIELD_META:
1381 case RTE_FLOW_FIELD_POINTER:
1382 case RTE_FLOW_FIELD_VALUE:
1391 mlx5_flow_field_id_to_modify_info
1392 (const struct rte_flow_action_modify_data *data,
1393 struct field_modify_info *info,
1394 uint32_t *mask, uint32_t *value,
1395 uint32_t width, uint32_t dst_width,
1396 struct rte_eth_dev *dev,
1397 const struct rte_flow_attr *attr,
1398 struct rte_flow_error *error)
1402 switch (data->field) {
1403 case RTE_FLOW_FIELD_START:
1404 /* not supported yet */
1407 case RTE_FLOW_FIELD_MAC_DST:
1409 if (data->offset < 32) {
1410 info[idx] = (struct field_modify_info){4, 0,
1411 MLX5_MODI_OUT_DMAC_47_16};
1414 rte_cpu_to_be_32(0xffffffff >>
1418 mask[idx] = RTE_BE32(0xffffffff);
1425 info[idx] = (struct field_modify_info){2, 4 * idx,
1426 MLX5_MODI_OUT_DMAC_15_0};
1427 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1429 if (data->offset < 32)
1430 info[idx++] = (struct field_modify_info){4, 0,
1431 MLX5_MODI_OUT_DMAC_47_16};
1432 info[idx] = (struct field_modify_info){2, 0,
1433 MLX5_MODI_OUT_DMAC_15_0};
1436 case RTE_FLOW_FIELD_MAC_SRC:
1438 if (data->offset < 32) {
1439 info[idx] = (struct field_modify_info){4, 0,
1440 MLX5_MODI_OUT_SMAC_47_16};
1443 rte_cpu_to_be_32(0xffffffff >>
1447 mask[idx] = RTE_BE32(0xffffffff);
1454 info[idx] = (struct field_modify_info){2, 4 * idx,
1455 MLX5_MODI_OUT_SMAC_15_0};
1456 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1458 if (data->offset < 32)
1459 info[idx++] = (struct field_modify_info){4, 0,
1460 MLX5_MODI_OUT_SMAC_47_16};
1461 info[idx] = (struct field_modify_info){2, 0,
1462 MLX5_MODI_OUT_SMAC_15_0};
1465 case RTE_FLOW_FIELD_VLAN_TYPE:
1466 /* not supported yet */
1468 case RTE_FLOW_FIELD_VLAN_ID:
1469 info[idx] = (struct field_modify_info){2, 0,
1470 MLX5_MODI_OUT_FIRST_VID};
1472 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1474 case RTE_FLOW_FIELD_MAC_TYPE:
1475 info[idx] = (struct field_modify_info){2, 0,
1476 MLX5_MODI_OUT_ETHERTYPE};
1478 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1480 case RTE_FLOW_FIELD_IPV4_DSCP:
1481 info[idx] = (struct field_modify_info){1, 0,
1482 MLX5_MODI_OUT_IP_DSCP};
1484 mask[idx] = 0x3f >> (6 - width);
1486 case RTE_FLOW_FIELD_IPV4_TTL:
1487 info[idx] = (struct field_modify_info){1, 0,
1488 MLX5_MODI_OUT_IPV4_TTL};
1490 mask[idx] = 0xff >> (8 - width);
1492 case RTE_FLOW_FIELD_IPV4_SRC:
1493 info[idx] = (struct field_modify_info){4, 0,
1494 MLX5_MODI_OUT_SIPV4};
1496 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1499 case RTE_FLOW_FIELD_IPV4_DST:
1500 info[idx] = (struct field_modify_info){4, 0,
1501 MLX5_MODI_OUT_DIPV4};
1503 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1506 case RTE_FLOW_FIELD_IPV6_DSCP:
1507 info[idx] = (struct field_modify_info){1, 0,
1508 MLX5_MODI_OUT_IP_DSCP};
1510 mask[idx] = 0x3f >> (6 - width);
1512 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1513 info[idx] = (struct field_modify_info){1, 0,
1514 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1516 mask[idx] = 0xff >> (8 - width);
1518 case RTE_FLOW_FIELD_IPV6_SRC:
1520 if (data->offset < 32) {
1521 info[idx] = (struct field_modify_info){4,
1523 MLX5_MODI_OUT_SIPV6_31_0};
1526 rte_cpu_to_be_32(0xffffffff >>
1530 mask[idx] = RTE_BE32(0xffffffff);
1537 if (data->offset < 64) {
1538 info[idx] = (struct field_modify_info){4,
1540 MLX5_MODI_OUT_SIPV6_63_32};
1543 rte_cpu_to_be_32(0xffffffff >>
1547 mask[idx] = RTE_BE32(0xffffffff);
1554 if (data->offset < 96) {
1555 info[idx] = (struct field_modify_info){4,
1557 MLX5_MODI_OUT_SIPV6_95_64};
1560 rte_cpu_to_be_32(0xffffffff >>
1564 mask[idx] = RTE_BE32(0xffffffff);
1571 info[idx] = (struct field_modify_info){4, 4 * idx,
1572 MLX5_MODI_OUT_SIPV6_127_96};
1573 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1576 if (data->offset < 32)
1577 info[idx++] = (struct field_modify_info){4, 0,
1578 MLX5_MODI_OUT_SIPV6_31_0};
1579 if (data->offset < 64)
1580 info[idx++] = (struct field_modify_info){4, 0,
1581 MLX5_MODI_OUT_SIPV6_63_32};
1582 if (data->offset < 96)
1583 info[idx++] = (struct field_modify_info){4, 0,
1584 MLX5_MODI_OUT_SIPV6_95_64};
1585 if (data->offset < 128)
1586 info[idx++] = (struct field_modify_info){4, 0,
1587 MLX5_MODI_OUT_SIPV6_127_96};
1590 case RTE_FLOW_FIELD_IPV6_DST:
1592 if (data->offset < 32) {
1593 info[idx] = (struct field_modify_info){4,
1595 MLX5_MODI_OUT_DIPV6_31_0};
1598 rte_cpu_to_be_32(0xffffffff >>
1602 mask[idx] = RTE_BE32(0xffffffff);
1609 if (data->offset < 64) {
1610 info[idx] = (struct field_modify_info){4,
1612 MLX5_MODI_OUT_DIPV6_63_32};
1615 rte_cpu_to_be_32(0xffffffff >>
1619 mask[idx] = RTE_BE32(0xffffffff);
1626 if (data->offset < 96) {
1627 info[idx] = (struct field_modify_info){4,
1629 MLX5_MODI_OUT_DIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[idx] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 4 * idx,
1644 MLX5_MODI_OUT_DIPV6_127_96};
1645 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1648 if (data->offset < 32)
1649 info[idx++] = (struct field_modify_info){4, 0,
1650 MLX5_MODI_OUT_DIPV6_31_0};
1651 if (data->offset < 64)
1652 info[idx++] = (struct field_modify_info){4, 0,
1653 MLX5_MODI_OUT_DIPV6_63_32};
1654 if (data->offset < 96)
1655 info[idx++] = (struct field_modify_info){4, 0,
1656 MLX5_MODI_OUT_DIPV6_95_64};
1657 if (data->offset < 128)
1658 info[idx++] = (struct field_modify_info){4, 0,
1659 MLX5_MODI_OUT_DIPV6_127_96};
1662 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1663 info[idx] = (struct field_modify_info){2, 0,
1664 MLX5_MODI_OUT_TCP_SPORT};
1666 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1668 case RTE_FLOW_FIELD_TCP_PORT_DST:
1669 info[idx] = (struct field_modify_info){2, 0,
1670 MLX5_MODI_OUT_TCP_DPORT};
1672 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1674 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1675 info[idx] = (struct field_modify_info){4, 0,
1676 MLX5_MODI_OUT_TCP_SEQ_NUM};
1678 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1681 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1682 info[idx] = (struct field_modify_info){4, 0,
1683 MLX5_MODI_OUT_TCP_ACK_NUM};
1685 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1688 case RTE_FLOW_FIELD_TCP_FLAGS:
1689 info[idx] = (struct field_modify_info){1, 0,
1690 MLX5_MODI_OUT_TCP_FLAGS};
1692 mask[idx] = 0x3f >> (6 - width);
1694 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1695 info[idx] = (struct field_modify_info){2, 0,
1696 MLX5_MODI_OUT_UDP_SPORT};
1698 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1700 case RTE_FLOW_FIELD_UDP_PORT_DST:
1701 info[idx] = (struct field_modify_info){2, 0,
1702 MLX5_MODI_OUT_UDP_DPORT};
1704 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1706 case RTE_FLOW_FIELD_VXLAN_VNI:
1707 /* not supported yet */
1709 case RTE_FLOW_FIELD_GENEVE_VNI:
1710 /* not supported yet*/
1712 case RTE_FLOW_FIELD_GTP_TEID:
1713 info[idx] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_GTP_TEID};
1716 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1719 case RTE_FLOW_FIELD_TAG:
1721 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1722 data->level, error);
1725 MLX5_ASSERT(reg != REG_NON);
1726 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1727 info[idx] = (struct field_modify_info){4, 0,
1731 rte_cpu_to_be_32(0xffffffff >>
1735 case RTE_FLOW_FIELD_MARK:
1737 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1741 MLX5_ASSERT(reg != REG_NON);
1742 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1743 info[idx] = (struct field_modify_info){4, 0,
1747 rte_cpu_to_be_32(0xffffffff >>
1751 case RTE_FLOW_FIELD_META:
1753 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1756 MLX5_ASSERT(reg != REG_NON);
1757 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1758 info[idx] = (struct field_modify_info){4, 0,
1762 rte_cpu_to_be_32(0xffffffff >>
1766 case RTE_FLOW_FIELD_POINTER:
1767 case RTE_FLOW_FIELD_VALUE:
1768 if (data->field == RTE_FLOW_FIELD_POINTER)
1769 memcpy(&val, (void *)(uintptr_t)data->value,
1773 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1775 if (dst_width > 16) {
1776 value[idx] = rte_cpu_to_be_32(val);
1778 } else if (dst_width > 8) {
1779 value[idx] = rte_cpu_to_be_16(val);
1782 value[idx] = (uint8_t)val;
1797 * Convert modify_field action to DV specification.
1800 * Pointer to the rte_eth_dev structure.
1801 * @param[in,out] resource
1802 * Pointer to the modify-header resource.
1804 * Pointer to action specification.
1806 * Attributes of flow that includes this item.
1808 * Pointer to the error structure.
1811 * 0 on success, a negative errno value otherwise and rte_errno is set.
1814 flow_dv_convert_action_modify_field
1815 (struct rte_eth_dev *dev,
1816 struct mlx5_flow_dv_modify_hdr_resource *resource,
1817 const struct rte_flow_action *action,
1818 const struct rte_flow_attr *attr,
1819 struct rte_flow_error *error)
1821 const struct rte_flow_action_modify_field *conf =
1822 (const struct rte_flow_action_modify_field *)(action->conf);
1823 struct rte_flow_item item;
1824 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1826 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1828 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1831 uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1833 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1834 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1835 type = MLX5_MODIFICATION_TYPE_SET;
1836 /** For SET fill the destination field (field) first. */
1837 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1838 value, conf->width, dst_width, dev, attr, error);
1839 /** Then copy immediate value from source as per mask. */
1840 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1841 value, conf->width, dst_width, dev, attr, error);
1844 type = MLX5_MODIFICATION_TYPE_COPY;
1845 /** For COPY fill the destination field (dcopy) without mask. */
1846 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1847 value, conf->width, dst_width, dev, attr, error);
1848 /** Then construct the source field (field) with mask. */
1849 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1850 value, conf->width, dst_width, dev, attr, error);
1853 return flow_dv_convert_modify_action(&item,
1854 field, dcopy, resource, type, error);
1858 * Validate MARK item.
1861 * Pointer to the rte_eth_dev structure.
1863 * Item specification.
1865 * Attributes of flow that includes this item.
1867 * Pointer to error structure.
1870 * 0 on success, a negative errno value otherwise and rte_errno is set.
1873 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1874 const struct rte_flow_item *item,
1875 const struct rte_flow_attr *attr __rte_unused,
1876 struct rte_flow_error *error)
1878 struct mlx5_priv *priv = dev->data->dev_private;
1879 struct mlx5_dev_config *config = &priv->config;
1880 const struct rte_flow_item_mark *spec = item->spec;
1881 const struct rte_flow_item_mark *mask = item->mask;
1882 const struct rte_flow_item_mark nic_mask = {
1883 .id = priv->sh->dv_mark_mask,
1887 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1888 return rte_flow_error_set(error, ENOTSUP,
1889 RTE_FLOW_ERROR_TYPE_ITEM, item,
1890 "extended metadata feature"
1892 if (!mlx5_flow_ext_mreg_supported(dev))
1893 return rte_flow_error_set(error, ENOTSUP,
1894 RTE_FLOW_ERROR_TYPE_ITEM, item,
1895 "extended metadata register"
1896 " isn't supported");
1898 return rte_flow_error_set(error, ENOTSUP,
1899 RTE_FLOW_ERROR_TYPE_ITEM, item,
1900 "extended metadata register"
1901 " isn't available");
1902 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1906 return rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1909 "data cannot be empty");
1910 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1911 return rte_flow_error_set(error, EINVAL,
1912 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1914 "mark id exceeds the limit");
1918 return rte_flow_error_set(error, EINVAL,
1919 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1920 "mask cannot be zero");
1922 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1923 (const uint8_t *)&nic_mask,
1924 sizeof(struct rte_flow_item_mark),
1925 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1932 * Validate META item.
1935 * Pointer to the rte_eth_dev structure.
1937 * Item specification.
1939 * Attributes of flow that includes this item.
1941 * Pointer to error structure.
1944 * 0 on success, a negative errno value otherwise and rte_errno is set.
1947 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1948 const struct rte_flow_item *item,
1949 const struct rte_flow_attr *attr,
1950 struct rte_flow_error *error)
1952 struct mlx5_priv *priv = dev->data->dev_private;
1953 struct mlx5_dev_config *config = &priv->config;
1954 const struct rte_flow_item_meta *spec = item->spec;
1955 const struct rte_flow_item_meta *mask = item->mask;
1956 struct rte_flow_item_meta nic_mask = {
1963 return rte_flow_error_set(error, EINVAL,
1964 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1966 "data cannot be empty");
1967 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1968 if (!mlx5_flow_ext_mreg_supported(dev))
1969 return rte_flow_error_set(error, ENOTSUP,
1970 RTE_FLOW_ERROR_TYPE_ITEM, item,
1971 "extended metadata register"
1972 " isn't supported");
1973 reg = flow_dv_get_metadata_reg(dev, attr, error);
1977 return rte_flow_error_set(error, ENOTSUP,
1978 RTE_FLOW_ERROR_TYPE_ITEM, item,
1979 "unavalable extended metadata register");
1981 return rte_flow_error_set(error, ENOTSUP,
1982 RTE_FLOW_ERROR_TYPE_ITEM, item,
1986 nic_mask.data = priv->sh->dv_meta_mask;
1989 return rte_flow_error_set(error, ENOTSUP,
1990 RTE_FLOW_ERROR_TYPE_ITEM, item,
1991 "extended metadata feature "
1992 "should be enabled when "
1993 "meta item is requested "
1994 "with e-switch mode ");
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ITEM, item,
1998 "match on metadata for ingress "
1999 "is not supported in legacy "
2003 mask = &rte_flow_item_meta_mask;
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2007 "mask cannot be zero");
2009 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2010 (const uint8_t *)&nic_mask,
2011 sizeof(struct rte_flow_item_meta),
2012 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2017 * Validate TAG item.
2020 * Pointer to the rte_eth_dev structure.
2022 * Item specification.
2024 * Attributes of flow that includes this item.
2026 * Pointer to error structure.
2029 * 0 on success, a negative errno value otherwise and rte_errno is set.
2032 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2033 const struct rte_flow_item *item,
2034 const struct rte_flow_attr *attr __rte_unused,
2035 struct rte_flow_error *error)
2037 const struct rte_flow_item_tag *spec = item->spec;
2038 const struct rte_flow_item_tag *mask = item->mask;
2039 const struct rte_flow_item_tag nic_mask = {
2040 .data = RTE_BE32(UINT32_MAX),
2045 if (!mlx5_flow_ext_mreg_supported(dev))
2046 return rte_flow_error_set(error, ENOTSUP,
2047 RTE_FLOW_ERROR_TYPE_ITEM, item,
2048 "extensive metadata register"
2049 " isn't supported");
2051 return rte_flow_error_set(error, EINVAL,
2052 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2054 "data cannot be empty");
2056 mask = &rte_flow_item_tag_mask;
2058 return rte_flow_error_set(error, EINVAL,
2059 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2060 "mask cannot be zero");
2062 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2063 (const uint8_t *)&nic_mask,
2064 sizeof(struct rte_flow_item_tag),
2065 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2068 if (mask->index != 0xff)
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2071 "partial mask for tag index"
2072 " is not supported");
2073 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2076 MLX5_ASSERT(ret != REG_NON);
2081 * Validate vport item.
2084 * Pointer to the rte_eth_dev structure.
2086 * Item specification.
2088 * Attributes of flow that includes this item.
2089 * @param[in] item_flags
2090 * Bit-fields that holds the items detected until now.
2092 * Pointer to error structure.
2095 * 0 on success, a negative errno value otherwise and rte_errno is set.
2098 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2099 const struct rte_flow_item *item,
2100 const struct rte_flow_attr *attr,
2101 uint64_t item_flags,
2102 struct rte_flow_error *error)
2104 const struct rte_flow_item_port_id *spec = item->spec;
2105 const struct rte_flow_item_port_id *mask = item->mask;
2106 const struct rte_flow_item_port_id switch_mask = {
2109 struct mlx5_priv *esw_priv;
2110 struct mlx5_priv *dev_priv;
2113 if (!attr->transfer)
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM,
2117 "match on port id is valid only"
2118 " when transfer flag is enabled");
2119 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2120 return rte_flow_error_set(error, ENOTSUP,
2121 RTE_FLOW_ERROR_TYPE_ITEM, item,
2122 "multiple source ports are not"
2125 mask = &switch_mask;
2126 if (mask->id != 0xffffffff)
2127 return rte_flow_error_set(error, ENOTSUP,
2128 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2130 "no support for partial mask on"
2132 ret = mlx5_flow_item_acceptable
2133 (item, (const uint8_t *)mask,
2134 (const uint8_t *)&rte_flow_item_port_id_mask,
2135 sizeof(struct rte_flow_item_port_id),
2136 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2141 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2143 return rte_flow_error_set(error, rte_errno,
2144 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2145 "failed to obtain E-Switch info for"
2147 dev_priv = mlx5_dev_to_eswitch_info(dev);
2149 return rte_flow_error_set(error, rte_errno,
2150 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2152 "failed to obtain E-Switch info");
2153 if (esw_priv->domain_id != dev_priv->domain_id)
2154 return rte_flow_error_set(error, EINVAL,
2155 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2156 "cannot match on a port from a"
2157 " different E-Switch");
2162 * Validate VLAN item.
2165 * Item specification.
2166 * @param[in] item_flags
2167 * Bit-fields that holds the items detected until now.
2169 * Ethernet device flow is being created on.
2171 * Pointer to error structure.
2174 * 0 on success, a negative errno value otherwise and rte_errno is set.
2177 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2178 uint64_t item_flags,
2179 struct rte_eth_dev *dev,
2180 struct rte_flow_error *error)
2182 const struct rte_flow_item_vlan *mask = item->mask;
2183 const struct rte_flow_item_vlan nic_mask = {
2184 .tci = RTE_BE16(UINT16_MAX),
2185 .inner_type = RTE_BE16(UINT16_MAX),
2188 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2190 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2191 MLX5_FLOW_LAYER_INNER_L4) :
2192 (MLX5_FLOW_LAYER_OUTER_L3 |
2193 MLX5_FLOW_LAYER_OUTER_L4);
2194 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2195 MLX5_FLOW_LAYER_OUTER_VLAN;
2197 if (item_flags & vlanm)
2198 return rte_flow_error_set(error, EINVAL,
2199 RTE_FLOW_ERROR_TYPE_ITEM, item,
2200 "multiple VLAN layers not supported");
2201 else if ((item_flags & l34m) != 0)
2202 return rte_flow_error_set(error, EINVAL,
2203 RTE_FLOW_ERROR_TYPE_ITEM, item,
2204 "VLAN cannot follow L3/L4 layer");
2206 mask = &rte_flow_item_vlan_mask;
2207 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2208 (const uint8_t *)&nic_mask,
2209 sizeof(struct rte_flow_item_vlan),
2210 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2213 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2214 struct mlx5_priv *priv = dev->data->dev_private;
2216 if (priv->vmwa_context) {
2218 * Non-NULL context means we have a virtual machine
2219 * and SR-IOV enabled, we have to create VLAN interface
2220 * to make hypervisor to setup E-Switch vport
2221 * context correctly. We avoid creating the multiple
2222 * VLAN interfaces, so we cannot support VLAN tag mask.
2224 return rte_flow_error_set(error, EINVAL,
2225 RTE_FLOW_ERROR_TYPE_ITEM,
2227 "VLAN tag mask is not"
2228 " supported in virtual"
2236 * GTP flags are contained in 1 byte of the format:
2237 * -------------------------------------------
2238 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2239 * |-----------------------------------------|
2240 * | value | Version | PT | Res | E | S | PN |
2241 * -------------------------------------------
2243 * Matching is supported only for GTP flags E, S, PN.
2245 #define MLX5_GTP_FLAGS_MASK 0x07
2248 * Validate GTP item.
2251 * Pointer to the rte_eth_dev structure.
2253 * Item specification.
2254 * @param[in] item_flags
2255 * Bit-fields that holds the items detected until now.
2257 * Pointer to error structure.
2260 * 0 on success, a negative errno value otherwise and rte_errno is set.
2263 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2264 const struct rte_flow_item *item,
2265 uint64_t item_flags,
2266 struct rte_flow_error *error)
2268 struct mlx5_priv *priv = dev->data->dev_private;
2269 const struct rte_flow_item_gtp *spec = item->spec;
2270 const struct rte_flow_item_gtp *mask = item->mask;
2271 const struct rte_flow_item_gtp nic_mask = {
2272 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2274 .teid = RTE_BE32(0xffffffff),
2277 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2278 return rte_flow_error_set(error, ENOTSUP,
2279 RTE_FLOW_ERROR_TYPE_ITEM, item,
2280 "GTP support is not enabled");
2281 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2282 return rte_flow_error_set(error, ENOTSUP,
2283 RTE_FLOW_ERROR_TYPE_ITEM, item,
2284 "multiple tunnel layers not"
2286 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2287 return rte_flow_error_set(error, EINVAL,
2288 RTE_FLOW_ERROR_TYPE_ITEM, item,
2289 "no outer UDP layer found");
2291 mask = &rte_flow_item_gtp_mask;
2292 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2293 return rte_flow_error_set(error, ENOTSUP,
2294 RTE_FLOW_ERROR_TYPE_ITEM, item,
2295 "Match is supported for GTP"
2297 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2298 (const uint8_t *)&nic_mask,
2299 sizeof(struct rte_flow_item_gtp),
2300 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2304 * Validate GTP PSC item.
2307 * Item specification.
2308 * @param[in] last_item
2309 * Previous validated item in the pattern items.
2310 * @param[in] gtp_item
2311 * Previous GTP item specification.
2313 * Pointer to flow attributes.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2323 const struct rte_flow_item *gtp_item,
2324 const struct rte_flow_attr *attr,
2325 struct rte_flow_error *error)
2327 const struct rte_flow_item_gtp *gtp_spec;
2328 const struct rte_flow_item_gtp *gtp_mask;
2329 const struct rte_flow_item_gtp_psc *spec;
2330 const struct rte_flow_item_gtp_psc *mask;
2331 const struct rte_flow_item_gtp_psc nic_mask = {
2336 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2337 return rte_flow_error_set
2338 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2339 "GTP PSC item must be preceded with GTP item");
2340 gtp_spec = gtp_item->spec;
2341 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2342 /* GTP spec and E flag is requested to match zero. */
2344 (gtp_mask->v_pt_rsv_flags &
2345 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2346 return rte_flow_error_set
2347 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2348 "GTP E flag must be 1 to match GTP PSC");
2349 /* Check the flow is not created in group zero. */
2350 if (!attr->transfer && !attr->group)
2351 return rte_flow_error_set
2352 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2353 "GTP PSC is not supported for group 0");
2354 /* GTP spec is here and E flag is requested to match zero. */
2358 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2359 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2360 return rte_flow_error_set
2361 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2362 "PDU type should be smaller than 16");
2363 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2364 (const uint8_t *)&nic_mask,
2365 sizeof(struct rte_flow_item_gtp_psc),
2366 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2370 * Validate IPV4 item.
2371 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2372 * add specific validation of fragment_offset field,
2375 * Item specification.
2376 * @param[in] item_flags
2377 * Bit-fields that holds the items detected until now.
2379 * Pointer to error structure.
2382 * 0 on success, a negative errno value otherwise and rte_errno is set.
2385 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2386 uint64_t item_flags,
2388 uint16_t ether_type,
2389 struct rte_flow_error *error)
2392 const struct rte_flow_item_ipv4 *spec = item->spec;
2393 const struct rte_flow_item_ipv4 *last = item->last;
2394 const struct rte_flow_item_ipv4 *mask = item->mask;
2395 rte_be16_t fragment_offset_spec = 0;
2396 rte_be16_t fragment_offset_last = 0;
2397 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2399 .src_addr = RTE_BE32(0xffffffff),
2400 .dst_addr = RTE_BE32(0xffffffff),
2401 .type_of_service = 0xff,
2402 .fragment_offset = RTE_BE16(0xffff),
2403 .next_proto_id = 0xff,
2404 .time_to_live = 0xff,
2408 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2409 ether_type, &nic_ipv4_mask,
2410 MLX5_ITEM_RANGE_ACCEPTED, error);
2414 fragment_offset_spec = spec->hdr.fragment_offset &
2415 mask->hdr.fragment_offset;
2416 if (!fragment_offset_spec)
2419 * spec and mask are valid, enforce using full mask to make sure the
2420 * complete value is used correctly.
2422 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2424 return rte_flow_error_set(error, EINVAL,
2425 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2426 item, "must use full mask for"
2427 " fragment_offset");
2429 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2430 * indicating this is 1st fragment of fragmented packet.
2431 * This is not yet supported in MLX5, return appropriate error message.
2433 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2434 return rte_flow_error_set(error, ENOTSUP,
2435 RTE_FLOW_ERROR_TYPE_ITEM, item,
2436 "match on first fragment not "
2438 if (fragment_offset_spec && !last)
2439 return rte_flow_error_set(error, ENOTSUP,
2440 RTE_FLOW_ERROR_TYPE_ITEM, item,
2441 "specified value not supported");
2442 /* spec and last are valid, validate the specified range. */
2443 fragment_offset_last = last->hdr.fragment_offset &
2444 mask->hdr.fragment_offset;
2446 * Match on fragment_offset spec 0x2001 and last 0x3fff
2447 * means MF is 1 and frag-offset is > 0.
2448 * This packet is fragment 2nd and onward, excluding last.
2449 * This is not yet supported in MLX5, return appropriate
2452 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2453 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2454 return rte_flow_error_set(error, ENOTSUP,
2455 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2456 last, "match on following "
2457 "fragments not supported");
2459 * Match on fragment_offset spec 0x0001 and last 0x1fff
2460 * means MF is 0 and frag-offset is > 0.
2461 * This packet is last fragment of fragmented packet.
2462 * This is not yet supported in MLX5, return appropriate
2465 if (fragment_offset_spec == RTE_BE16(1) &&
2466 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2467 return rte_flow_error_set(error, ENOTSUP,
2468 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2469 last, "match on last "
2470 "fragment not supported");
2472 * Match on fragment_offset spec 0x0001 and last 0x3fff
2473 * means MF and/or frag-offset is not 0.
2474 * This is a fragmented packet.
2475 * Other range values are invalid and rejected.
2477 if (!(fragment_offset_spec == RTE_BE16(1) &&
2478 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2479 return rte_flow_error_set(error, ENOTSUP,
2480 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2481 "specified range not supported");
2486 * Validate IPV6 fragment extension item.
2489 * Item specification.
2490 * @param[in] item_flags
2491 * Bit-fields that holds the items detected until now.
2493 * Pointer to error structure.
2496 * 0 on success, a negative errno value otherwise and rte_errno is set.
2499 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2500 uint64_t item_flags,
2501 struct rte_flow_error *error)
2503 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2504 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2505 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2506 rte_be16_t frag_data_spec = 0;
2507 rte_be16_t frag_data_last = 0;
2508 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2509 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2510 MLX5_FLOW_LAYER_OUTER_L4;
2512 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2514 .next_header = 0xff,
2515 .frag_data = RTE_BE16(0xffff),
2519 if (item_flags & l4m)
2520 return rte_flow_error_set(error, EINVAL,
2521 RTE_FLOW_ERROR_TYPE_ITEM, item,
2522 "ipv6 fragment extension item cannot "
2524 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2525 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2526 return rte_flow_error_set(error, EINVAL,
2527 RTE_FLOW_ERROR_TYPE_ITEM, item,
2528 "ipv6 fragment extension item must "
2529 "follow ipv6 item");
2531 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2532 if (!frag_data_spec)
2535 * spec and mask are valid, enforce using full mask to make sure the
2536 * complete value is used correctly.
2538 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2539 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2540 return rte_flow_error_set(error, EINVAL,
2541 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2542 item, "must use full mask for"
2545 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2546 * This is 1st fragment of fragmented packet.
2548 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2549 return rte_flow_error_set(error, ENOTSUP,
2550 RTE_FLOW_ERROR_TYPE_ITEM, item,
2551 "match on first fragment not "
2553 if (frag_data_spec && !last)
2554 return rte_flow_error_set(error, EINVAL,
2555 RTE_FLOW_ERROR_TYPE_ITEM, item,
2556 "specified value not supported");
2557 ret = mlx5_flow_item_acceptable
2558 (item, (const uint8_t *)mask,
2559 (const uint8_t *)&nic_mask,
2560 sizeof(struct rte_flow_item_ipv6_frag_ext),
2561 MLX5_ITEM_RANGE_ACCEPTED, error);
2564 /* spec and last are valid, validate the specified range. */
2565 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2567 * Match on frag_data spec 0x0009 and last 0xfff9
2568 * means M is 1 and frag-offset is > 0.
2569 * This packet is fragment 2nd and onward, excluding last.
2570 * This is not yet supported in MLX5, return appropriate
2573 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2574 RTE_IPV6_EHDR_MF_MASK) &&
2575 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2576 return rte_flow_error_set(error, ENOTSUP,
2577 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2578 last, "match on following "
2579 "fragments not supported");
2581 * Match on frag_data spec 0x0008 and last 0xfff8
2582 * means M is 0 and frag-offset is > 0.
2583 * This packet is last fragment of fragmented packet.
2584 * This is not yet supported in MLX5, return appropriate
2587 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2588 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2589 return rte_flow_error_set(error, ENOTSUP,
2590 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2591 last, "match on last "
2592 "fragment not supported");
2593 /* Other range values are invalid and rejected. */
2594 return rte_flow_error_set(error, EINVAL,
2595 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2596 "specified range not supported");
2600 * Validate the pop VLAN action.
2603 * Pointer to the rte_eth_dev structure.
2604 * @param[in] action_flags
2605 * Holds the actions detected until now.
2607 * Pointer to the pop vlan action.
2608 * @param[in] item_flags
2609 * The items found in this flow rule.
2611 * Pointer to flow attributes.
2613 * Pointer to error structure.
2616 * 0 on success, a negative errno value otherwise and rte_errno is set.
2619 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2620 uint64_t action_flags,
2621 const struct rte_flow_action *action,
2622 uint64_t item_flags,
2623 const struct rte_flow_attr *attr,
2624 struct rte_flow_error *error)
2626 const struct mlx5_priv *priv = dev->data->dev_private;
2630 if (!priv->sh->pop_vlan_action)
2631 return rte_flow_error_set(error, ENOTSUP,
2632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2634 "pop vlan action is not supported");
2636 return rte_flow_error_set(error, ENOTSUP,
2637 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2639 "pop vlan action not supported for "
2641 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2642 return rte_flow_error_set(error, ENOTSUP,
2643 RTE_FLOW_ERROR_TYPE_ACTION, action,
2644 "no support for multiple VLAN "
2646 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2647 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2648 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2649 return rte_flow_error_set(error, ENOTSUP,
2650 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2652 "cannot pop vlan after decap without "
2653 "match on inner vlan in the flow");
2654 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2655 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2656 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2657 return rte_flow_error_set(error, ENOTSUP,
2658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2660 "cannot pop vlan without a "
2661 "match on (outer) vlan in the flow");
2662 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2663 return rte_flow_error_set(error, EINVAL,
2664 RTE_FLOW_ERROR_TYPE_ACTION, action,
2665 "wrong action order, port_id should "
2666 "be after pop VLAN action");
2667 if (!attr->transfer && priv->representor)
2668 return rte_flow_error_set(error, ENOTSUP,
2669 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2670 "pop vlan action for VF representor "
2671 "not supported on NIC table");
2676 * Get VLAN default info from vlan match info.
2679 * the list of item specifications.
2681 * pointer VLAN info to fill to.
2684 * 0 on success, a negative errno value otherwise and rte_errno is set.
2687 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2688 struct rte_vlan_hdr *vlan)
2690 const struct rte_flow_item_vlan nic_mask = {
2691 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2692 MLX5DV_FLOW_VLAN_VID_MASK),
2693 .inner_type = RTE_BE16(0xffff),
2698 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2699 int type = items->type;
2701 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2702 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2705 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2706 const struct rte_flow_item_vlan *vlan_m = items->mask;
2707 const struct rte_flow_item_vlan *vlan_v = items->spec;
2709 /* If VLAN item in pattern doesn't contain data, return here. */
2714 /* Only full match values are accepted */
2715 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2716 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2717 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2719 rte_be_to_cpu_16(vlan_v->tci &
2720 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2722 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2723 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2724 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2726 rte_be_to_cpu_16(vlan_v->tci &
2727 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2729 if (vlan_m->inner_type == nic_mask.inner_type)
2730 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2731 vlan_m->inner_type);
2736 * Validate the push VLAN action.
2739 * Pointer to the rte_eth_dev structure.
2740 * @param[in] action_flags
2741 * Holds the actions detected until now.
2742 * @param[in] item_flags
2743 * The items found in this flow rule.
2745 * Pointer to the action structure.
2747 * Pointer to flow attributes
2749 * Pointer to error structure.
2752 * 0 on success, a negative errno value otherwise and rte_errno is set.
2755 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2756 uint64_t action_flags,
2757 const struct rte_flow_item_vlan *vlan_m,
2758 const struct rte_flow_action *action,
2759 const struct rte_flow_attr *attr,
2760 struct rte_flow_error *error)
2762 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2763 const struct mlx5_priv *priv = dev->data->dev_private;
2765 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2766 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2767 return rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ACTION, action,
2769 "invalid vlan ethertype");
2770 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2771 return rte_flow_error_set(error, EINVAL,
2772 RTE_FLOW_ERROR_TYPE_ACTION, action,
2773 "wrong action order, port_id should "
2774 "be after push VLAN");
2775 if (!attr->transfer && priv->representor)
2776 return rte_flow_error_set(error, ENOTSUP,
2777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2778 "push vlan action for VF representor "
2779 "not supported on NIC table");
2781 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2782 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2783 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2784 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2785 !(mlx5_flow_find_action
2786 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2787 return rte_flow_error_set(error, EINVAL,
2788 RTE_FLOW_ERROR_TYPE_ACTION, action,
2789 "not full match mask on VLAN PCP and "
2790 "there is no of_set_vlan_pcp action, "
2791 "push VLAN action cannot figure out "
2794 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2795 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2796 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2797 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2798 !(mlx5_flow_find_action
2799 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2800 return rte_flow_error_set(error, EINVAL,
2801 RTE_FLOW_ERROR_TYPE_ACTION, action,
2802 "not full match mask on VLAN VID and "
2803 "there is no of_set_vlan_vid action, "
2804 "push VLAN action cannot figure out "
2811 * Validate the set VLAN PCP.
2813 * @param[in] action_flags
2814 * Holds the actions detected until now.
2815 * @param[in] actions
2816 * Pointer to the list of actions remaining in the flow rule.
2818 * Pointer to error structure.
2821 * 0 on success, a negative errno value otherwise and rte_errno is set.
2824 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2825 const struct rte_flow_action actions[],
2826 struct rte_flow_error *error)
2828 const struct rte_flow_action *action = actions;
2829 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2831 if (conf->vlan_pcp > 7)
2832 return rte_flow_error_set(error, EINVAL,
2833 RTE_FLOW_ERROR_TYPE_ACTION, action,
2834 "VLAN PCP value is too big");
2835 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2836 return rte_flow_error_set(error, ENOTSUP,
2837 RTE_FLOW_ERROR_TYPE_ACTION, action,
2838 "set VLAN PCP action must follow "
2839 "the push VLAN action");
2840 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2841 return rte_flow_error_set(error, ENOTSUP,
2842 RTE_FLOW_ERROR_TYPE_ACTION, action,
2843 "Multiple VLAN PCP modification are "
2845 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2846 return rte_flow_error_set(error, EINVAL,
2847 RTE_FLOW_ERROR_TYPE_ACTION, action,
2848 "wrong action order, port_id should "
2849 "be after set VLAN PCP");
2854 * Validate the set VLAN VID.
2856 * @param[in] item_flags
2857 * Holds the items detected in this rule.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] actions
2861 * Pointer to the list of actions remaining in the flow rule.
2863 * Pointer to error structure.
2866 * 0 on success, a negative errno value otherwise and rte_errno is set.
2869 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2870 uint64_t action_flags,
2871 const struct rte_flow_action actions[],
2872 struct rte_flow_error *error)
2874 const struct rte_flow_action *action = actions;
2875 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2877 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2878 return rte_flow_error_set(error, EINVAL,
2879 RTE_FLOW_ERROR_TYPE_ACTION, action,
2880 "VLAN VID value is too big");
2881 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2882 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2883 return rte_flow_error_set(error, ENOTSUP,
2884 RTE_FLOW_ERROR_TYPE_ACTION, action,
2885 "set VLAN VID action must follow push"
2886 " VLAN action or match on VLAN item");
2887 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2888 return rte_flow_error_set(error, ENOTSUP,
2889 RTE_FLOW_ERROR_TYPE_ACTION, action,
2890 "Multiple VLAN VID modifications are "
2892 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2893 return rte_flow_error_set(error, EINVAL,
2894 RTE_FLOW_ERROR_TYPE_ACTION, action,
2895 "wrong action order, port_id should "
2896 "be after set VLAN VID");
2901 * Validate the FLAG action.
2904 * Pointer to the rte_eth_dev structure.
2905 * @param[in] action_flags
2906 * Holds the actions detected until now.
2908 * Pointer to flow attributes
2910 * Pointer to error structure.
2913 * 0 on success, a negative errno value otherwise and rte_errno is set.
2916 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2917 uint64_t action_flags,
2918 const struct rte_flow_attr *attr,
2919 struct rte_flow_error *error)
2921 struct mlx5_priv *priv = dev->data->dev_private;
2922 struct mlx5_dev_config *config = &priv->config;
2925 /* Fall back if no extended metadata register support. */
2926 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2927 return mlx5_flow_validate_action_flag(action_flags, attr,
2929 /* Extensive metadata mode requires registers. */
2930 if (!mlx5_flow_ext_mreg_supported(dev))
2931 return rte_flow_error_set(error, ENOTSUP,
2932 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933 "no metadata registers "
2934 "to support flag action");
2935 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2936 return rte_flow_error_set(error, ENOTSUP,
2937 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2938 "extended metadata register"
2939 " isn't available");
2940 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2943 MLX5_ASSERT(ret > 0);
2944 if (action_flags & MLX5_FLOW_ACTION_MARK)
2945 return rte_flow_error_set(error, EINVAL,
2946 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2947 "can't mark and flag in same flow");
2948 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949 return rte_flow_error_set(error, EINVAL,
2950 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2952 " actions in same flow");
2957 * Validate MARK action.
2960 * Pointer to the rte_eth_dev structure.
2962 * Pointer to action.
2963 * @param[in] action_flags
2964 * Holds the actions detected until now.
2966 * Pointer to flow attributes
2968 * Pointer to error structure.
2971 * 0 on success, a negative errno value otherwise and rte_errno is set.
2974 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2975 const struct rte_flow_action *action,
2976 uint64_t action_flags,
2977 const struct rte_flow_attr *attr,
2978 struct rte_flow_error *error)
2980 struct mlx5_priv *priv = dev->data->dev_private;
2981 struct mlx5_dev_config *config = &priv->config;
2982 const struct rte_flow_action_mark *mark = action->conf;
2985 if (is_tunnel_offload_active(dev))
2986 return rte_flow_error_set(error, ENOTSUP,
2987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2989 "if tunnel offload active");
2990 /* Fall back if no extended metadata register support. */
2991 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2992 return mlx5_flow_validate_action_mark(action, action_flags,
2994 /* Extensive metadata mode requires registers. */
2995 if (!mlx5_flow_ext_mreg_supported(dev))
2996 return rte_flow_error_set(error, ENOTSUP,
2997 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2998 "no metadata registers "
2999 "to support mark action");
3000 if (!priv->sh->dv_mark_mask)
3001 return rte_flow_error_set(error, ENOTSUP,
3002 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3003 "extended metadata register"
3004 " isn't available");
3005 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3008 MLX5_ASSERT(ret > 0);
3010 return rte_flow_error_set(error, EINVAL,
3011 RTE_FLOW_ERROR_TYPE_ACTION, action,
3012 "configuration cannot be null");
3013 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3017 "mark id exceeds the limit");
3018 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3019 return rte_flow_error_set(error, EINVAL,
3020 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3021 "can't flag and mark in same flow");
3022 if (action_flags & MLX5_FLOW_ACTION_MARK)
3023 return rte_flow_error_set(error, EINVAL,
3024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025 "can't have 2 mark actions in same"
3031 * Validate SET_META action.
3034 * Pointer to the rte_eth_dev structure.
3036 * Pointer to the action structure.
3037 * @param[in] action_flags
3038 * Holds the actions detected until now.
3040 * Pointer to flow attributes
3042 * Pointer to error structure.
3045 * 0 on success, a negative errno value otherwise and rte_errno is set.
3048 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3049 const struct rte_flow_action *action,
3050 uint64_t action_flags __rte_unused,
3051 const struct rte_flow_attr *attr,
3052 struct rte_flow_error *error)
3054 const struct rte_flow_action_set_meta *conf;
3055 uint32_t nic_mask = UINT32_MAX;
3058 if (!mlx5_flow_ext_mreg_supported(dev))
3059 return rte_flow_error_set(error, ENOTSUP,
3060 RTE_FLOW_ERROR_TYPE_ACTION, action,
3061 "extended metadata register"
3062 " isn't supported");
3063 reg = flow_dv_get_metadata_reg(dev, attr, error);
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, action,
3069 "unavalable extended metadata register");
3070 if (reg != REG_A && reg != REG_B) {
3071 struct mlx5_priv *priv = dev->data->dev_private;
3073 nic_mask = priv->sh->dv_meta_mask;
3075 if (!(action->conf))
3076 return rte_flow_error_set(error, EINVAL,
3077 RTE_FLOW_ERROR_TYPE_ACTION, action,
3078 "configuration cannot be null");
3079 conf = (const struct rte_flow_action_set_meta *)action->conf;
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, action,
3083 "zero mask doesn't have any effect");
3084 if (conf->mask & ~nic_mask)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, action,
3087 "meta data must be within reg C0");
3092 * Validate SET_TAG action.
3095 * Pointer to the rte_eth_dev structure.
3097 * Pointer to the action structure.
3098 * @param[in] action_flags
3099 * Holds the actions detected until now.
3101 * Pointer to flow attributes
3103 * Pointer to error structure.
3106 * 0 on success, a negative errno value otherwise and rte_errno is set.
3109 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3110 const struct rte_flow_action *action,
3111 uint64_t action_flags,
3112 const struct rte_flow_attr *attr,
3113 struct rte_flow_error *error)
3115 const struct rte_flow_action_set_tag *conf;
3116 const uint64_t terminal_action_flags =
3117 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3118 MLX5_FLOW_ACTION_RSS;
3121 if (!mlx5_flow_ext_mreg_supported(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, action,
3124 "extensive metadata register"
3125 " isn't supported");
3126 if (!(action->conf))
3127 return rte_flow_error_set(error, EINVAL,
3128 RTE_FLOW_ERROR_TYPE_ACTION, action,
3129 "configuration cannot be null");
3130 conf = (const struct rte_flow_action_set_tag *)action->conf;
3132 return rte_flow_error_set(error, EINVAL,
3133 RTE_FLOW_ERROR_TYPE_ACTION, action,
3134 "zero mask doesn't have any effect");
3135 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3138 if (!attr->transfer && attr->ingress &&
3139 (action_flags & terminal_action_flags))
3140 return rte_flow_error_set(error, EINVAL,
3141 RTE_FLOW_ERROR_TYPE_ACTION, action,
3142 "set_tag has no effect"
3143 " with terminal actions");
3148 * Validate count action.
3151 * Pointer to rte_eth_dev structure.
3153 * Pointer to the action structure.
3154 * @param[in] action_flags
3155 * Holds the actions detected until now.
3157 * Pointer to error structure.
3160 * 0 on success, a negative errno value otherwise and rte_errno is set.
3163 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3164 const struct rte_flow_action *action,
3165 uint64_t action_flags,
3166 struct rte_flow_error *error)
3168 struct mlx5_priv *priv = dev->data->dev_private;
3169 const struct rte_flow_action_count *count;
3171 if (!priv->config.devx)
3173 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3174 return rte_flow_error_set(error, EINVAL,
3175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3176 "duplicate count actions set");
3177 count = (const struct rte_flow_action_count *)action->conf;
3178 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3179 !priv->sh->flow_hit_aso_en)
3180 return rte_flow_error_set(error, EINVAL,
3181 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3182 "old age and shared count combination is not supported");
3183 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3187 return rte_flow_error_set
3189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3191 "count action not supported");
3195 * Validate the L2 encap action.
3198 * Pointer to the rte_eth_dev structure.
3199 * @param[in] action_flags
3200 * Holds the actions detected until now.
3202 * Pointer to the action structure.
3204 * Pointer to flow attributes.
3206 * Pointer to error structure.
3209 * 0 on success, a negative errno value otherwise and rte_errno is set.
3212 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3213 uint64_t action_flags,
3214 const struct rte_flow_action *action,
3215 const struct rte_flow_attr *attr,
3216 struct rte_flow_error *error)
3218 const struct mlx5_priv *priv = dev->data->dev_private;
3220 if (!(action->conf))
3221 return rte_flow_error_set(error, EINVAL,
3222 RTE_FLOW_ERROR_TYPE_ACTION, action,
3223 "configuration cannot be null");
3224 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3225 return rte_flow_error_set(error, EINVAL,
3226 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3227 "can only have a single encap action "
3229 if (!attr->transfer && priv->representor)
3230 return rte_flow_error_set(error, ENOTSUP,
3231 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3232 "encap action for VF representor "
3233 "not supported on NIC table");
3238 * Validate a decap action.
3241 * Pointer to the rte_eth_dev structure.
3242 * @param[in] action_flags
3243 * Holds the actions detected until now.
3245 * Pointer to the action structure.
3246 * @param[in] item_flags
3247 * Holds the items detected.
3249 * Pointer to flow attributes
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3258 uint64_t action_flags,
3259 const struct rte_flow_action *action,
3260 const uint64_t item_flags,
3261 const struct rte_flow_attr *attr,
3262 struct rte_flow_error *error)
3264 const struct mlx5_priv *priv = dev->data->dev_private;
3266 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3267 !priv->config.decap_en)
3268 return rte_flow_error_set(error, ENOTSUP,
3269 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3270 "decap is not enabled");
3271 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3272 return rte_flow_error_set(error, ENOTSUP,
3273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3275 MLX5_FLOW_ACTION_DECAP ? "can only "
3276 "have a single decap action" : "decap "
3277 "after encap is not supported");
3278 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3281 "can't have decap action after"
3284 return rte_flow_error_set(error, ENOTSUP,
3285 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3287 "decap action not supported for "
3289 if (!attr->transfer && priv->representor)
3290 return rte_flow_error_set(error, ENOTSUP,
3291 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3292 "decap action for VF representor "
3293 "not supported on NIC table");
3294 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3295 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3296 return rte_flow_error_set(error, ENOTSUP,
3297 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3298 "VXLAN item should be present for VXLAN decap");
3302 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3305 * Validate the raw encap and decap actions.
3308 * Pointer to the rte_eth_dev structure.
3310 * Pointer to the decap action.
3312 * Pointer to the encap action.
3314 * Pointer to flow attributes
3315 * @param[in/out] action_flags
3316 * Holds the actions detected until now.
3317 * @param[out] actions_n
3318 * pointer to the number of actions counter.
3320 * Pointer to the action structure.
3321 * @param[in] item_flags
3322 * Holds the items detected.
3324 * Pointer to error structure.
3327 * 0 on success, a negative errno value otherwise and rte_errno is set.
3330 flow_dv_validate_action_raw_encap_decap
3331 (struct rte_eth_dev *dev,
3332 const struct rte_flow_action_raw_decap *decap,
3333 const struct rte_flow_action_raw_encap *encap,
3334 const struct rte_flow_attr *attr, uint64_t *action_flags,
3335 int *actions_n, const struct rte_flow_action *action,
3336 uint64_t item_flags, struct rte_flow_error *error)
3338 const struct mlx5_priv *priv = dev->data->dev_private;
3341 if (encap && (!encap->size || !encap->data))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3344 "raw encap data cannot be empty");
3345 if (decap && encap) {
3346 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3347 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3350 else if (encap->size <=
3351 MLX5_ENCAPSULATION_DECISION_SIZE &&
3353 MLX5_ENCAPSULATION_DECISION_SIZE)
3356 else if (encap->size >
3357 MLX5_ENCAPSULATION_DECISION_SIZE &&
3359 MLX5_ENCAPSULATION_DECISION_SIZE)
3360 /* 2 L2 actions: encap and decap. */
3363 return rte_flow_error_set(error,
3365 RTE_FLOW_ERROR_TYPE_ACTION,
3366 NULL, "unsupported too small "
3367 "raw decap and too small raw "
3368 "encap combination");
3371 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3372 item_flags, attr, error);
3375 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3379 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3380 return rte_flow_error_set(error, ENOTSUP,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "small raw encap size");
3384 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3385 return rte_flow_error_set(error, EINVAL,
3386 RTE_FLOW_ERROR_TYPE_ACTION,
3388 "more than one encap action");
3389 if (!attr->transfer && priv->representor)
3390 return rte_flow_error_set
3392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3393 "encap action for VF representor "
3394 "not supported on NIC table");
3395 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3402 * Match encap_decap resource.
3405 * Pointer to the hash list.
3407 * Pointer to exist resource entry object.
3409 * Key of the new entry.
3411 * Pointer to new encap_decap resource.
3414 * 0 on matching, none-zero otherwise.
3417 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3418 struct mlx5_hlist_entry *entry,
3419 uint64_t key __rte_unused, void *cb_ctx)
3421 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3422 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3423 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3425 cache_resource = container_of(entry,
3426 struct mlx5_flow_dv_encap_decap_resource,
3428 if (resource->reformat_type == cache_resource->reformat_type &&
3429 resource->ft_type == cache_resource->ft_type &&
3430 resource->flags == cache_resource->flags &&
3431 resource->size == cache_resource->size &&
3432 !memcmp((const void *)resource->buf,
3433 (const void *)cache_resource->buf,
3440 * Allocate encap_decap resource.
3443 * Pointer to the hash list.
3445 * Pointer to exist resource entry object.
3447 * Pointer to new encap_decap resource.
3450 * 0 on matching, none-zero otherwise.
3452 struct mlx5_hlist_entry *
3453 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3454 uint64_t key __rte_unused,
3457 struct mlx5_dev_ctx_shared *sh = list->ctx;
3458 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3459 struct mlx5dv_dr_domain *domain;
3460 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3461 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3465 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3466 domain = sh->fdb_domain;
3467 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3468 domain = sh->rx_domain;
3470 domain = sh->tx_domain;
3471 /* Register new encap/decap resource. */
3472 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3474 if (!cache_resource) {
3475 rte_flow_error_set(ctx->error, ENOMEM,
3476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3477 "cannot allocate resource memory");
3480 *cache_resource = *resource;
3481 cache_resource->idx = idx;
3482 ret = mlx5_flow_os_create_flow_action_packet_reformat
3483 (sh->ctx, domain, cache_resource,
3484 &cache_resource->action);
3486 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3487 rte_flow_error_set(ctx->error, ENOMEM,
3488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3489 NULL, "cannot create action");
3493 return &cache_resource->entry;
3497 * Find existing encap/decap resource or create and register a new one.
3499 * @param[in, out] dev
3500 * Pointer to rte_eth_dev structure.
3501 * @param[in, out] resource
3502 * Pointer to encap/decap resource.
3503 * @parm[in, out] dev_flow
3504 * Pointer to the dev_flow.
3506 * pointer to error structure.
3509 * 0 on success otherwise -errno and errno is set.
3512 flow_dv_encap_decap_resource_register
3513 (struct rte_eth_dev *dev,
3514 struct mlx5_flow_dv_encap_decap_resource *resource,
3515 struct mlx5_flow *dev_flow,
3516 struct rte_flow_error *error)
3518 struct mlx5_priv *priv = dev->data->dev_private;
3519 struct mlx5_dev_ctx_shared *sh = priv->sh;
3520 struct mlx5_hlist_entry *entry;
3524 uint32_t refmt_type:8;
3526 * Header reformat actions can be shared between
3527 * non-root tables. One bit to indicate non-root
3531 uint32_t reserve:15;
3534 } encap_decap_key = {
3536 .ft_type = resource->ft_type,
3537 .refmt_type = resource->reformat_type,
3538 .is_root = !!dev_flow->dv.group,
3542 struct mlx5_flow_cb_ctx ctx = {
3548 resource->flags = dev_flow->dv.group ? 0 : 1;
3549 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3550 sizeof(encap_decap_key.v32), 0);
3551 if (resource->reformat_type !=
3552 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3554 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3555 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3558 resource = container_of(entry, typeof(*resource), entry);
3559 dev_flow->dv.encap_decap = resource;
3560 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3565 * Find existing table jump resource or create and register a new one.
3567 * @param[in, out] dev
3568 * Pointer to rte_eth_dev structure.
3569 * @param[in, out] tbl
3570 * Pointer to flow table resource.
3571 * @parm[in, out] dev_flow
3572 * Pointer to the dev_flow.
3574 * pointer to error structure.
3577 * 0 on success otherwise -errno and errno is set.
3580 flow_dv_jump_tbl_resource_register
3581 (struct rte_eth_dev *dev __rte_unused,
3582 struct mlx5_flow_tbl_resource *tbl,
3583 struct mlx5_flow *dev_flow,
3584 struct rte_flow_error *error __rte_unused)
3586 struct mlx5_flow_tbl_data_entry *tbl_data =
3587 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3590 MLX5_ASSERT(tbl_data->jump.action);
3591 dev_flow->handle->rix_jump = tbl_data->idx;
3592 dev_flow->dv.jump = &tbl_data->jump;
3597 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3598 struct mlx5_cache_entry *entry, void *cb_ctx)
3600 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3601 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3602 struct mlx5_flow_dv_port_id_action_resource *res =
3603 container_of(entry, typeof(*res), entry);
3605 return ref->port_id != res->port_id;
3608 struct mlx5_cache_entry *
3609 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3610 struct mlx5_cache_entry *entry __rte_unused,
3613 struct mlx5_dev_ctx_shared *sh = list->ctx;
3614 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3615 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3616 struct mlx5_flow_dv_port_id_action_resource *cache;
3620 /* Register new port id action resource. */
3621 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3623 rte_flow_error_set(ctx->error, ENOMEM,
3624 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3625 "cannot allocate port_id action cache memory");
3629 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3633 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3634 rte_flow_error_set(ctx->error, ENOMEM,
3635 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3636 "cannot create action");
3640 return &cache->entry;
3644 * Find existing table port ID resource or create and register a new one.
3646 * @param[in, out] dev
3647 * Pointer to rte_eth_dev structure.
3648 * @param[in, out] resource
3649 * Pointer to port ID action resource.
3650 * @parm[in, out] dev_flow
3651 * Pointer to the dev_flow.
3653 * pointer to error structure.
3656 * 0 on success otherwise -errno and errno is set.
3659 flow_dv_port_id_action_resource_register
3660 (struct rte_eth_dev *dev,
3661 struct mlx5_flow_dv_port_id_action_resource *resource,
3662 struct mlx5_flow *dev_flow,
3663 struct rte_flow_error *error)
3665 struct mlx5_priv *priv = dev->data->dev_private;
3666 struct mlx5_cache_entry *entry;
3667 struct mlx5_flow_dv_port_id_action_resource *cache;
3668 struct mlx5_flow_cb_ctx ctx = {
3673 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3676 cache = container_of(entry, typeof(*cache), entry);
3677 dev_flow->dv.port_id_action = cache;
3678 dev_flow->handle->rix_port_id_action = cache->idx;
3683 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3684 struct mlx5_cache_entry *entry, void *cb_ctx)
3686 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3687 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3688 struct mlx5_flow_dv_push_vlan_action_resource *res =
3689 container_of(entry, typeof(*res), entry);
3691 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3694 struct mlx5_cache_entry *
3695 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3696 struct mlx5_cache_entry *entry __rte_unused,
3699 struct mlx5_dev_ctx_shared *sh = list->ctx;
3700 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3701 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3702 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3703 struct mlx5dv_dr_domain *domain;
3707 /* Register new port id action resource. */
3708 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3710 rte_flow_error_set(ctx->error, ENOMEM,
3711 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3712 "cannot allocate push_vlan action cache memory");
3716 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3717 domain = sh->fdb_domain;
3718 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3719 domain = sh->rx_domain;
3721 domain = sh->tx_domain;
3722 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3725 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3726 rte_flow_error_set(ctx->error, ENOMEM,
3727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3728 "cannot create push vlan action");
3732 return &cache->entry;
3736 * Find existing push vlan resource or create and register a new one.
3738 * @param [in, out] dev
3739 * Pointer to rte_eth_dev structure.
3740 * @param[in, out] resource
3741 * Pointer to port ID action resource.
3742 * @parm[in, out] dev_flow
3743 * Pointer to the dev_flow.
3745 * pointer to error structure.
3748 * 0 on success otherwise -errno and errno is set.
3751 flow_dv_push_vlan_action_resource_register
3752 (struct rte_eth_dev *dev,
3753 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3754 struct mlx5_flow *dev_flow,
3755 struct rte_flow_error *error)
3757 struct mlx5_priv *priv = dev->data->dev_private;
3758 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3759 struct mlx5_cache_entry *entry;
3760 struct mlx5_flow_cb_ctx ctx = {
3765 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3768 cache = container_of(entry, typeof(*cache), entry);
3770 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3771 dev_flow->dv.push_vlan_res = cache;
3776 * Get the size of specific rte_flow_item_type hdr size
3778 * @param[in] item_type
3779 * Tested rte_flow_item_type.
3782 * sizeof struct item_type, 0 if void or irrelevant.
3785 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3789 switch (item_type) {
3790 case RTE_FLOW_ITEM_TYPE_ETH:
3791 retval = sizeof(struct rte_ether_hdr);
3793 case RTE_FLOW_ITEM_TYPE_VLAN:
3794 retval = sizeof(struct rte_vlan_hdr);
3796 case RTE_FLOW_ITEM_TYPE_IPV4:
3797 retval = sizeof(struct rte_ipv4_hdr);
3799 case RTE_FLOW_ITEM_TYPE_IPV6:
3800 retval = sizeof(struct rte_ipv6_hdr);
3802 case RTE_FLOW_ITEM_TYPE_UDP:
3803 retval = sizeof(struct rte_udp_hdr);
3805 case RTE_FLOW_ITEM_TYPE_TCP:
3806 retval = sizeof(struct rte_tcp_hdr);
3808 case RTE_FLOW_ITEM_TYPE_VXLAN:
3809 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3810 retval = sizeof(struct rte_vxlan_hdr);
3812 case RTE_FLOW_ITEM_TYPE_GRE:
3813 case RTE_FLOW_ITEM_TYPE_NVGRE:
3814 retval = sizeof(struct rte_gre_hdr);
3816 case RTE_FLOW_ITEM_TYPE_MPLS:
3817 retval = sizeof(struct rte_mpls_hdr);
3819 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3827 #define MLX5_ENCAP_IPV4_VERSION 0x40
3828 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3829 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3830 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3831 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3832 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3833 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3836 * Convert the encap action data from list of rte_flow_item to raw buffer
3839 * Pointer to rte_flow_item objects list.
3841 * Pointer to the output buffer.
3843 * Pointer to the output buffer size.
3845 * Pointer to the error structure.
3848 * 0 on success, a negative errno value otherwise and rte_errno is set.
3851 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3852 size_t *size, struct rte_flow_error *error)
3854 struct rte_ether_hdr *eth = NULL;
3855 struct rte_vlan_hdr *vlan = NULL;
3856 struct rte_ipv4_hdr *ipv4 = NULL;
3857 struct rte_ipv6_hdr *ipv6 = NULL;
3858 struct rte_udp_hdr *udp = NULL;
3859 struct rte_vxlan_hdr *vxlan = NULL;
3860 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3861 struct rte_gre_hdr *gre = NULL;
3863 size_t temp_size = 0;
3866 return rte_flow_error_set(error, EINVAL,
3867 RTE_FLOW_ERROR_TYPE_ACTION,
3868 NULL, "invalid empty data");
3869 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3870 len = flow_dv_get_item_hdr_len(items->type);
3871 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3872 return rte_flow_error_set(error, EINVAL,
3873 RTE_FLOW_ERROR_TYPE_ACTION,
3874 (void *)items->type,
3875 "items total size is too big"
3876 " for encap action");
3877 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3878 switch (items->type) {
3879 case RTE_FLOW_ITEM_TYPE_ETH:
3880 eth = (struct rte_ether_hdr *)&buf[temp_size];
3882 case RTE_FLOW_ITEM_TYPE_VLAN:
3883 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3885 return rte_flow_error_set(error, EINVAL,
3886 RTE_FLOW_ERROR_TYPE_ACTION,
3887 (void *)items->type,
3888 "eth header not found");
3889 if (!eth->ether_type)
3890 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3892 case RTE_FLOW_ITEM_TYPE_IPV4:
3893 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3895 return rte_flow_error_set(error, EINVAL,
3896 RTE_FLOW_ERROR_TYPE_ACTION,
3897 (void *)items->type,
3898 "neither eth nor vlan"
3900 if (vlan && !vlan->eth_proto)
3901 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902 else if (eth && !eth->ether_type)
3903 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3904 if (!ipv4->version_ihl)
3905 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3906 MLX5_ENCAP_IPV4_IHL_MIN;
3907 if (!ipv4->time_to_live)
3908 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3910 case RTE_FLOW_ITEM_TYPE_IPV6:
3911 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3913 return rte_flow_error_set(error, EINVAL,
3914 RTE_FLOW_ERROR_TYPE_ACTION,
3915 (void *)items->type,
3916 "neither eth nor vlan"
3918 if (vlan && !vlan->eth_proto)
3919 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920 else if (eth && !eth->ether_type)
3921 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3922 if (!ipv6->vtc_flow)
3924 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3925 if (!ipv6->hop_limits)
3926 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3928 case RTE_FLOW_ITEM_TYPE_UDP:
3929 udp = (struct rte_udp_hdr *)&buf[temp_size];
3931 return rte_flow_error_set(error, EINVAL,
3932 RTE_FLOW_ERROR_TYPE_ACTION,
3933 (void *)items->type,
3934 "ip header not found");
3935 if (ipv4 && !ipv4->next_proto_id)
3936 ipv4->next_proto_id = IPPROTO_UDP;
3937 else if (ipv6 && !ipv6->proto)
3938 ipv6->proto = IPPROTO_UDP;
3940 case RTE_FLOW_ITEM_TYPE_VXLAN:
3941 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3943 return rte_flow_error_set(error, EINVAL,
3944 RTE_FLOW_ERROR_TYPE_ACTION,
3945 (void *)items->type,
3946 "udp header not found");
3948 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3949 if (!vxlan->vx_flags)
3951 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3953 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3954 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3956 return rte_flow_error_set(error, EINVAL,
3957 RTE_FLOW_ERROR_TYPE_ACTION,
3958 (void *)items->type,
3959 "udp header not found");
3960 if (!vxlan_gpe->proto)
3961 return rte_flow_error_set(error, EINVAL,
3962 RTE_FLOW_ERROR_TYPE_ACTION,
3963 (void *)items->type,
3964 "next protocol not found");
3967 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3968 if (!vxlan_gpe->vx_flags)
3969 vxlan_gpe->vx_flags =
3970 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3972 case RTE_FLOW_ITEM_TYPE_GRE:
3973 case RTE_FLOW_ITEM_TYPE_NVGRE:
3974 gre = (struct rte_gre_hdr *)&buf[temp_size];
3976 return rte_flow_error_set(error, EINVAL,
3977 RTE_FLOW_ERROR_TYPE_ACTION,
3978 (void *)items->type,
3979 "next protocol not found");
3981 return rte_flow_error_set(error, EINVAL,
3982 RTE_FLOW_ERROR_TYPE_ACTION,
3983 (void *)items->type,
3984 "ip header not found");
3985 if (ipv4 && !ipv4->next_proto_id)
3986 ipv4->next_proto_id = IPPROTO_GRE;
3987 else if (ipv6 && !ipv6->proto)
3988 ipv6->proto = IPPROTO_GRE;
3990 case RTE_FLOW_ITEM_TYPE_VOID:
3993 return rte_flow_error_set(error, EINVAL,
3994 RTE_FLOW_ERROR_TYPE_ACTION,
3995 (void *)items->type,
3996 "unsupported item type");
4006 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4008 struct rte_ether_hdr *eth = NULL;
4009 struct rte_vlan_hdr *vlan = NULL;
4010 struct rte_ipv6_hdr *ipv6 = NULL;
4011 struct rte_udp_hdr *udp = NULL;
4015 eth = (struct rte_ether_hdr *)data;
4016 next_hdr = (char *)(eth + 1);
4017 proto = RTE_BE16(eth->ether_type);
4020 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4021 vlan = (struct rte_vlan_hdr *)next_hdr;
4022 proto = RTE_BE16(vlan->eth_proto);
4023 next_hdr += sizeof(struct rte_vlan_hdr);
4026 /* HW calculates IPv4 csum. no need to proceed */
4027 if (proto == RTE_ETHER_TYPE_IPV4)
4030 /* non IPv4/IPv6 header. not supported */
4031 if (proto != RTE_ETHER_TYPE_IPV6) {
4032 return rte_flow_error_set(error, ENOTSUP,
4033 RTE_FLOW_ERROR_TYPE_ACTION,
4034 NULL, "Cannot offload non IPv4/IPv6");
4037 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4039 /* ignore non UDP */
4040 if (ipv6->proto != IPPROTO_UDP)
4043 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4044 udp->dgram_cksum = 0;
4050 * Convert L2 encap action to DV specification.
4053 * Pointer to rte_eth_dev structure.
4055 * Pointer to action structure.
4056 * @param[in, out] dev_flow
4057 * Pointer to the mlx5_flow.
4058 * @param[in] transfer
4059 * Mark if the flow is E-Switch flow.
4061 * Pointer to the error structure.
4064 * 0 on success, a negative errno value otherwise and rte_errno is set.
4067 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4068 const struct rte_flow_action *action,
4069 struct mlx5_flow *dev_flow,
4071 struct rte_flow_error *error)
4073 const struct rte_flow_item *encap_data;
4074 const struct rte_flow_action_raw_encap *raw_encap_data;
4075 struct mlx5_flow_dv_encap_decap_resource res = {
4077 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4078 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4079 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4082 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4084 (const struct rte_flow_action_raw_encap *)action->conf;
4085 res.size = raw_encap_data->size;
4086 memcpy(res.buf, raw_encap_data->data, res.size);
4088 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4090 ((const struct rte_flow_action_vxlan_encap *)
4091 action->conf)->definition;
4094 ((const struct rte_flow_action_nvgre_encap *)
4095 action->conf)->definition;
4096 if (flow_dv_convert_encap_data(encap_data, res.buf,
4100 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4102 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4103 return rte_flow_error_set(error, EINVAL,
4104 RTE_FLOW_ERROR_TYPE_ACTION,
4105 NULL, "can't create L2 encap action");
4110 * Convert L2 decap action to DV specification.
4113 * Pointer to rte_eth_dev structure.
4114 * @param[in, out] dev_flow
4115 * Pointer to the mlx5_flow.
4116 * @param[in] transfer
4117 * Mark if the flow is E-Switch flow.
4119 * Pointer to the error structure.
4122 * 0 on success, a negative errno value otherwise and rte_errno is set.
4125 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4126 struct mlx5_flow *dev_flow,
4128 struct rte_flow_error *error)
4130 struct mlx5_flow_dv_encap_decap_resource res = {
4133 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4134 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4135 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4138 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4139 return rte_flow_error_set(error, EINVAL,
4140 RTE_FLOW_ERROR_TYPE_ACTION,
4141 NULL, "can't create L2 decap action");
4146 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4149 * Pointer to rte_eth_dev structure.
4151 * Pointer to action structure.
4152 * @param[in, out] dev_flow
4153 * Pointer to the mlx5_flow.
4155 * Pointer to the flow attributes.
4157 * Pointer to the error structure.
4160 * 0 on success, a negative errno value otherwise and rte_errno is set.
4163 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4164 const struct rte_flow_action *action,
4165 struct mlx5_flow *dev_flow,
4166 const struct rte_flow_attr *attr,
4167 struct rte_flow_error *error)
4169 const struct rte_flow_action_raw_encap *encap_data;
4170 struct mlx5_flow_dv_encap_decap_resource res;
4172 memset(&res, 0, sizeof(res));
4173 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4174 res.size = encap_data->size;
4175 memcpy(res.buf, encap_data->data, res.size);
4176 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4177 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4178 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4180 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4182 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4183 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4184 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4185 return rte_flow_error_set(error, EINVAL,
4186 RTE_FLOW_ERROR_TYPE_ACTION,
4187 NULL, "can't create encap action");
4192 * Create action push VLAN.
4195 * Pointer to rte_eth_dev structure.
4197 * Pointer to the flow attributes.
4199 * Pointer to the vlan to push to the Ethernet header.
4200 * @param[in, out] dev_flow
4201 * Pointer to the mlx5_flow.
4203 * Pointer to the error structure.
4206 * 0 on success, a negative errno value otherwise and rte_errno is set.
4209 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4210 const struct rte_flow_attr *attr,
4211 const struct rte_vlan_hdr *vlan,
4212 struct mlx5_flow *dev_flow,
4213 struct rte_flow_error *error)
4215 struct mlx5_flow_dv_push_vlan_action_resource res;
4217 memset(&res, 0, sizeof(res));
4219 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4222 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4224 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4225 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4226 return flow_dv_push_vlan_action_resource_register
4227 (dev, &res, dev_flow, error);
4231 * Validate the modify-header actions.
4233 * @param[in] action_flags
4234 * Holds the actions detected until now.
4236 * Pointer to the modify action.
4238 * Pointer to error structure.
4241 * 0 on success, a negative errno value otherwise and rte_errno is set.
4244 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4245 const struct rte_flow_action *action,
4246 struct rte_flow_error *error)
4248 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4249 return rte_flow_error_set(error, EINVAL,
4250 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4251 NULL, "action configuration not set");
4252 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4253 return rte_flow_error_set(error, EINVAL,
4254 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4255 "can't have encap action before"
4261 * Validate the modify-header MAC address actions.
4263 * @param[in] action_flags
4264 * Holds the actions detected until now.
4266 * Pointer to the modify action.
4267 * @param[in] item_flags
4268 * Holds the items detected.
4270 * Pointer to error structure.
4273 * 0 on success, a negative errno value otherwise and rte_errno is set.
4276 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4277 const struct rte_flow_action *action,
4278 const uint64_t item_flags,
4279 struct rte_flow_error *error)
4283 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4285 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4286 return rte_flow_error_set(error, EINVAL,
4287 RTE_FLOW_ERROR_TYPE_ACTION,
4289 "no L2 item in pattern");
4295 * Validate the modify-header IPv4 address actions.
4297 * @param[in] action_flags
4298 * Holds the actions detected until now.
4300 * Pointer to the modify action.
4301 * @param[in] item_flags
4302 * Holds the items detected.
4304 * Pointer to error structure.
4307 * 0 on success, a negative errno value otherwise and rte_errno is set.
4310 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4311 const struct rte_flow_action *action,
4312 const uint64_t item_flags,
4313 struct rte_flow_error *error)
4318 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4320 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4321 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4322 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4323 if (!(item_flags & layer))
4324 return rte_flow_error_set(error, EINVAL,
4325 RTE_FLOW_ERROR_TYPE_ACTION,
4327 "no ipv4 item in pattern");
4333 * Validate the modify-header IPv6 address actions.
4335 * @param[in] action_flags
4336 * Holds the actions detected until now.
4338 * Pointer to the modify action.
4339 * @param[in] item_flags
4340 * Holds the items detected.
4342 * Pointer to error structure.
4345 * 0 on success, a negative errno value otherwise and rte_errno is set.
4348 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4349 const struct rte_flow_action *action,
4350 const uint64_t item_flags,
4351 struct rte_flow_error *error)
4356 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4358 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4359 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4360 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4361 if (!(item_flags & layer))
4362 return rte_flow_error_set(error, EINVAL,
4363 RTE_FLOW_ERROR_TYPE_ACTION,
4365 "no ipv6 item in pattern");
4371 * Validate the modify-header TP actions.
4373 * @param[in] action_flags
4374 * Holds the actions detected until now.
4376 * Pointer to the modify action.
4377 * @param[in] item_flags
4378 * Holds the items detected.
4380 * Pointer to error structure.
4383 * 0 on success, a negative errno value otherwise and rte_errno is set.
4386 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4387 const struct rte_flow_action *action,
4388 const uint64_t item_flags,
4389 struct rte_flow_error *error)
4394 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4396 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4397 MLX5_FLOW_LAYER_INNER_L4 :
4398 MLX5_FLOW_LAYER_OUTER_L4;
4399 if (!(item_flags & layer))
4400 return rte_flow_error_set(error, EINVAL,
4401 RTE_FLOW_ERROR_TYPE_ACTION,
4402 NULL, "no transport layer "
4409 * Validate the modify-header actions of increment/decrement
4410 * TCP Sequence-number.
4412 * @param[in] action_flags
4413 * Holds the actions detected until now.
4415 * Pointer to the modify action.
4416 * @param[in] item_flags
4417 * Holds the items detected.
4419 * Pointer to error structure.
4422 * 0 on success, a negative errno value otherwise and rte_errno is set.
4425 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4426 const struct rte_flow_action *action,
4427 const uint64_t item_flags,
4428 struct rte_flow_error *error)
4433 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4435 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4436 MLX5_FLOW_LAYER_INNER_L4_TCP :
4437 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4438 if (!(item_flags & layer))
4439 return rte_flow_error_set(error, EINVAL,
4440 RTE_FLOW_ERROR_TYPE_ACTION,
4441 NULL, "no TCP item in"
4443 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4444 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4445 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4446 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4447 return rte_flow_error_set(error, EINVAL,
4448 RTE_FLOW_ERROR_TYPE_ACTION,
4450 "cannot decrease and increase"
4451 " TCP sequence number"
4452 " at the same time");
4458 * Validate the modify-header actions of increment/decrement
4459 * TCP Acknowledgment number.
4461 * @param[in] action_flags
4462 * Holds the actions detected until now.
4464 * Pointer to the modify action.
4465 * @param[in] item_flags
4466 * Holds the items detected.
4468 * Pointer to error structure.
4471 * 0 on success, a negative errno value otherwise and rte_errno is set.
4474 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4475 const struct rte_flow_action *action,
4476 const uint64_t item_flags,
4477 struct rte_flow_error *error)
4482 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4484 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4485 MLX5_FLOW_LAYER_INNER_L4_TCP :
4486 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4487 if (!(item_flags & layer))
4488 return rte_flow_error_set(error, EINVAL,
4489 RTE_FLOW_ERROR_TYPE_ACTION,
4490 NULL, "no TCP item in"
4492 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4493 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4494 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4495 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4496 return rte_flow_error_set(error, EINVAL,
4497 RTE_FLOW_ERROR_TYPE_ACTION,
4499 "cannot decrease and increase"
4500 " TCP acknowledgment number"
4501 " at the same time");
4507 * Validate the modify-header TTL actions.
4509 * @param[in] action_flags
4510 * Holds the actions detected until now.
4512 * Pointer to the modify action.
4513 * @param[in] item_flags
4514 * Holds the items detected.
4516 * Pointer to error structure.
4519 * 0 on success, a negative errno value otherwise and rte_errno is set.
4522 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4523 const struct rte_flow_action *action,
4524 const uint64_t item_flags,
4525 struct rte_flow_error *error)
4530 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4532 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4533 MLX5_FLOW_LAYER_INNER_L3 :
4534 MLX5_FLOW_LAYER_OUTER_L3;
4535 if (!(item_flags & layer))
4536 return rte_flow_error_set(error, EINVAL,
4537 RTE_FLOW_ERROR_TYPE_ACTION,
4539 "no IP protocol in pattern");
4545 * Validate the generic modify field actions.
4547 * Pointer to the rte_eth_dev structure.
4548 * @param[in] action_flags
4549 * Holds the actions detected until now.
4551 * Pointer to the modify action.
4553 * Pointer to the flow attributes.
4555 * Pointer to error structure.
4558 * Number of header fields to modify (0 or more) on success,
4559 * a negative errno value otherwise and rte_errno is set.
4562 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4563 const uint64_t action_flags,
4564 const struct rte_flow_action *action,
4565 const struct rte_flow_attr *attr,
4566 struct rte_flow_error *error)
4569 struct mlx5_priv *priv = dev->data->dev_private;
4570 struct mlx5_dev_config *config = &priv->config;
4571 const struct rte_flow_action_modify_field *action_modify_field =
4573 uint32_t dst_width =
4574 mlx5_flow_item_field_width(action_modify_field->dst.field);
4575 uint32_t src_width =
4576 mlx5_flow_item_field_width(action_modify_field->src.field);
4578 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4582 if (action_modify_field->width == 0)
4583 return rte_flow_error_set(error, EINVAL,
4584 RTE_FLOW_ERROR_TYPE_ACTION, action,
4585 "no bits are requested to be modified");
4586 else if (action_modify_field->width > dst_width ||
4587 action_modify_field->width > src_width)
4588 return rte_flow_error_set(error, EINVAL,
4589 RTE_FLOW_ERROR_TYPE_ACTION, action,
4590 "cannot modify more bits than"
4591 " the width of a field");
4592 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594 if ((action_modify_field->dst.offset +
4595 action_modify_field->width > dst_width) ||
4596 (action_modify_field->dst.offset % 32))
4597 return rte_flow_error_set(error, EINVAL,
4598 RTE_FLOW_ERROR_TYPE_ACTION, action,
4599 "destination offset is too big"
4600 " or not aligned to 4 bytes");
4601 if (action_modify_field->dst.level &&
4602 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4603 return rte_flow_error_set(error, ENOTSUP,
4604 RTE_FLOW_ERROR_TYPE_ACTION, action,
4605 "inner header fields modification"
4606 " is not supported");
4608 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4609 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4610 if (!attr->transfer && !attr->group)
4611 return rte_flow_error_set(error, ENOTSUP,
4612 RTE_FLOW_ERROR_TYPE_ACTION, action,
4613 "modify field action is not"
4614 " supported for group 0");
4615 if ((action_modify_field->src.offset +
4616 action_modify_field->width > src_width) ||
4617 (action_modify_field->src.offset % 32))
4618 return rte_flow_error_set(error, EINVAL,
4619 RTE_FLOW_ERROR_TYPE_ACTION, action,
4620 "source offset is too big"
4621 " or not aligned to 4 bytes");
4622 if (action_modify_field->src.level &&
4623 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4624 return rte_flow_error_set(error, ENOTSUP,
4625 RTE_FLOW_ERROR_TYPE_ACTION, action,
4626 "inner header fields modification"
4627 " is not supported");
4629 if (action_modify_field->dst.field ==
4630 action_modify_field->src.field)
4631 return rte_flow_error_set(error, EINVAL,
4632 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633 "source and destination fields"
4634 " cannot be the same");
4635 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4636 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4637 return rte_flow_error_set(error, EINVAL,
4638 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639 "immediate value or a pointer to it"
4640 " cannot be used as a destination");
4641 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4642 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4643 return rte_flow_error_set(error, ENOTSUP,
4644 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645 "modifications of an arbitrary"
4646 " place in a packet is not supported");
4647 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4648 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4649 return rte_flow_error_set(error, ENOTSUP,
4650 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651 "modifications of the 802.1Q Tag"
4652 " Identifier is not supported");
4653 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4654 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4655 return rte_flow_error_set(error, ENOTSUP,
4656 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657 "modifications of the VXLAN Network"
4658 " Identifier is not supported");
4659 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4660 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4661 return rte_flow_error_set(error, ENOTSUP,
4662 RTE_FLOW_ERROR_TYPE_ACTION, action,
4663 "modifications of the GENEVE Network"
4664 " Identifier is not supported");
4665 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4666 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4667 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4668 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4669 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4670 !mlx5_flow_ext_mreg_supported(dev))
4671 return rte_flow_error_set(error, ENOTSUP,
4672 RTE_FLOW_ERROR_TYPE_ACTION, action,
4673 "cannot modify mark or metadata without"
4674 " extended metadata register support");
4676 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4677 return rte_flow_error_set(error, ENOTSUP,
4678 RTE_FLOW_ERROR_TYPE_ACTION, action,
4679 "add and sub operations"
4680 " are not supported");
4681 return (action_modify_field->width / 32) +
4682 !!(action_modify_field->width % 32);
4686 * Validate jump action.
4689 * Pointer to the jump action.
4690 * @param[in] action_flags
4691 * Holds the actions detected until now.
4692 * @param[in] attributes
4693 * Pointer to flow attributes
4694 * @param[in] external
4695 * Action belongs to flow rule created by request external to PMD.
4697 * Pointer to error structure.
4700 * 0 on success, a negative errno value otherwise and rte_errno is set.
4703 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4704 const struct mlx5_flow_tunnel *tunnel,
4705 const struct rte_flow_action *action,
4706 uint64_t action_flags,
4707 const struct rte_flow_attr *attributes,
4708 bool external, struct rte_flow_error *error)
4710 uint32_t target_group, table;
4712 struct flow_grp_info grp_info = {
4713 .external = !!external,
4714 .transfer = !!attributes->transfer,
4718 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4719 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4720 return rte_flow_error_set(error, EINVAL,
4721 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4722 "can't have 2 fate actions in"
4724 if (action_flags & MLX5_FLOW_ACTION_METER)
4725 return rte_flow_error_set(error, ENOTSUP,
4726 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4727 "jump with meter not support");
4729 return rte_flow_error_set(error, EINVAL,
4730 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4731 NULL, "action configuration not set");
4733 ((const struct rte_flow_action_jump *)action->conf)->group;
4734 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4738 if (attributes->group == target_group &&
4739 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4740 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4741 return rte_flow_error_set(error, EINVAL,
4742 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4743 "target group must be other than"
4744 " the current flow group");
4749 * Validate the port_id action.
4752 * Pointer to rte_eth_dev structure.
4753 * @param[in] action_flags
4754 * Bit-fields that holds the actions detected until now.
4756 * Port_id RTE action structure.
4758 * Attributes of flow that includes this action.
4760 * Pointer to error structure.
4763 * 0 on success, a negative errno value otherwise and rte_errno is set.
4766 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4767 uint64_t action_flags,
4768 const struct rte_flow_action *action,
4769 const struct rte_flow_attr *attr,
4770 struct rte_flow_error *error)
4772 const struct rte_flow_action_port_id *port_id;
4773 struct mlx5_priv *act_priv;
4774 struct mlx5_priv *dev_priv;
4777 if (!attr->transfer)
4778 return rte_flow_error_set(error, ENOTSUP,
4779 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4781 "port id action is valid in transfer"
4783 if (!action || !action->conf)
4784 return rte_flow_error_set(error, ENOTSUP,
4785 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4787 "port id action parameters must be"
4789 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4790 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4791 return rte_flow_error_set(error, EINVAL,
4792 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4793 "can have only one fate actions in"
4795 dev_priv = mlx5_dev_to_eswitch_info(dev);
4797 return rte_flow_error_set(error, rte_errno,
4798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4800 "failed to obtain E-Switch info");
4801 port_id = action->conf;
4802 port = port_id->original ? dev->data->port_id : port_id->id;
4803 act_priv = mlx5_port_to_eswitch_info(port, false);
4805 return rte_flow_error_set
4807 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4808 "failed to obtain E-Switch port id for port");
4809 if (act_priv->domain_id != dev_priv->domain_id)
4810 return rte_flow_error_set
4812 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4813 "port does not belong to"
4814 " E-Switch being configured");
4819 * Get the maximum number of modify header actions.
4822 * Pointer to rte_eth_dev structure.
4824 * Flags bits to check if root level.
4827 * Max number of modify header actions device can support.
4829 static inline unsigned int
4830 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4834 * There's no way to directly query the max capacity from FW.
4835 * The maximal value on root table should be assumed to be supported.
4837 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4838 return MLX5_MAX_MODIFY_NUM;
4840 return MLX5_ROOT_TBL_MODIFY_NUM;
4844 * Validate the meter action.
4847 * Pointer to rte_eth_dev structure.
4848 * @param[in] action_flags
4849 * Bit-fields that holds the actions detected until now.
4851 * Pointer to the meter action.
4853 * Attributes of flow that includes this action.
4855 * Pointer to error structure.
4858 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4861 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4862 uint64_t action_flags,
4863 const struct rte_flow_action *action,
4864 const struct rte_flow_attr *attr,
4865 struct rte_flow_error *error)
4867 struct mlx5_priv *priv = dev->data->dev_private;
4868 const struct rte_flow_action_meter *am = action->conf;
4869 struct mlx5_flow_meter_info *fm;
4872 return rte_flow_error_set(error, EINVAL,
4873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874 "meter action conf is NULL");
4876 if (action_flags & MLX5_FLOW_ACTION_METER)
4877 return rte_flow_error_set(error, ENOTSUP,
4878 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4879 "meter chaining not support");
4880 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4881 return rte_flow_error_set(error, ENOTSUP,
4882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4883 "meter with jump not support");
4885 return rte_flow_error_set(error, ENOTSUP,
4886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4888 "meter action not supported");
4889 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4891 return rte_flow_error_set(error, EINVAL,
4892 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4894 /* aso meter can always be shared by different domains */
4895 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
4896 !(fm->transfer == attr->transfer ||
4897 (!fm->ingress && !attr->ingress && attr->egress) ||
4898 (!fm->egress && !attr->egress && attr->ingress)))
4899 return rte_flow_error_set(error, EINVAL,
4900 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4901 "Flow attributes are either invalid "
4902 "or have a conflict with current "
4903 "meter attributes");
4908 * Validate the age action.
4910 * @param[in] action_flags
4911 * Holds the actions detected until now.
4913 * Pointer to the age action.
4915 * Pointer to the Ethernet device structure.
4917 * Pointer to error structure.
4920 * 0 on success, a negative errno value otherwise and rte_errno is set.
4923 flow_dv_validate_action_age(uint64_t action_flags,
4924 const struct rte_flow_action *action,
4925 struct rte_eth_dev *dev,
4926 struct rte_flow_error *error)
4928 struct mlx5_priv *priv = dev->data->dev_private;
4929 const struct rte_flow_action_age *age = action->conf;
4931 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4932 !priv->sh->aso_age_mng))
4933 return rte_flow_error_set(error, ENOTSUP,
4934 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4936 "age action not supported");
4937 if (!(action->conf))
4938 return rte_flow_error_set(error, EINVAL,
4939 RTE_FLOW_ERROR_TYPE_ACTION, action,
4940 "configuration cannot be null");
4941 if (!(age->timeout))
4942 return rte_flow_error_set(error, EINVAL,
4943 RTE_FLOW_ERROR_TYPE_ACTION, action,
4944 "invalid timeout value 0");
4945 if (action_flags & MLX5_FLOW_ACTION_AGE)
4946 return rte_flow_error_set(error, EINVAL,
4947 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4948 "duplicate age actions set");
4953 * Validate the modify-header IPv4 DSCP actions.
4955 * @param[in] action_flags
4956 * Holds the actions detected until now.
4958 * Pointer to the modify action.
4959 * @param[in] item_flags
4960 * Holds the items detected.
4962 * Pointer to error structure.
4965 * 0 on success, a negative errno value otherwise and rte_errno is set.
4968 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4969 const struct rte_flow_action *action,
4970 const uint64_t item_flags,
4971 struct rte_flow_error *error)
4975 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4977 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4978 return rte_flow_error_set(error, EINVAL,
4979 RTE_FLOW_ERROR_TYPE_ACTION,
4981 "no ipv4 item in pattern");
4987 * Validate the modify-header IPv6 DSCP actions.
4989 * @param[in] action_flags
4990 * Holds the actions detected until now.
4992 * Pointer to the modify action.
4993 * @param[in] item_flags
4994 * Holds the items detected.
4996 * Pointer to error structure.
4999 * 0 on success, a negative errno value otherwise and rte_errno is set.
5002 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5003 const struct rte_flow_action *action,
5004 const uint64_t item_flags,
5005 struct rte_flow_error *error)
5009 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5011 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION,
5015 "no ipv6 item in pattern");
5021 * Match modify-header resource.
5024 * Pointer to the hash list.
5026 * Pointer to exist resource entry object.
5028 * Key of the new entry.
5030 * Pointer to new modify-header resource.
5033 * 0 on matching, non-zero otherwise.
5036 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5037 struct mlx5_hlist_entry *entry,
5038 uint64_t key __rte_unused, void *cb_ctx)
5040 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5041 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5042 struct mlx5_flow_dv_modify_hdr_resource *resource =
5043 container_of(entry, typeof(*resource), entry);
5044 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5046 key_len += ref->actions_num * sizeof(ref->actions[0]);
5047 return ref->actions_num != resource->actions_num ||
5048 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5051 struct mlx5_hlist_entry *
5052 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5055 struct mlx5_dev_ctx_shared *sh = list->ctx;
5056 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5057 struct mlx5dv_dr_domain *ns;
5058 struct mlx5_flow_dv_modify_hdr_resource *entry;
5059 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5061 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5062 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5064 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5067 rte_flow_error_set(ctx->error, ENOMEM,
5068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5069 "cannot allocate resource memory");
5072 rte_memcpy(&entry->ft_type,
5073 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5074 key_len + data_len);
5075 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5076 ns = sh->fdb_domain;
5077 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5081 ret = mlx5_flow_os_create_flow_action_modify_header
5082 (sh->ctx, ns, entry,
5083 data_len, &entry->action);
5086 rte_flow_error_set(ctx->error, ENOMEM,
5087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5088 NULL, "cannot create modification action");
5091 return &entry->entry;
5095 * Validate the sample action.
5097 * @param[in, out] action_flags
5098 * Holds the actions detected until now.
5100 * Pointer to the sample action.
5102 * Pointer to the Ethernet device structure.
5104 * Attributes of flow that includes this action.
5105 * @param[in] item_flags
5106 * Holds the items detected.
5108 * Pointer to the RSS action.
5109 * @param[out] sample_rss
5110 * Pointer to the RSS action in sample action list.
5112 * Pointer to the COUNT action in sample action list.
5113 * @param[out] fdb_mirror_limit
5114 * Pointer to the FDB mirror limitation flag.
5116 * Pointer to error structure.
5119 * 0 on success, a negative errno value otherwise and rte_errno is set.
5122 flow_dv_validate_action_sample(uint64_t *action_flags,
5123 const struct rte_flow_action *action,
5124 struct rte_eth_dev *dev,
5125 const struct rte_flow_attr *attr,
5126 uint64_t item_flags,
5127 const struct rte_flow_action_rss *rss,
5128 const struct rte_flow_action_rss **sample_rss,
5129 const struct rte_flow_action_count **count,
5130 int *fdb_mirror_limit,
5131 struct rte_flow_error *error)
5133 struct mlx5_priv *priv = dev->data->dev_private;
5134 struct mlx5_dev_config *dev_conf = &priv->config;
5135 const struct rte_flow_action_sample *sample = action->conf;
5136 const struct rte_flow_action *act;
5137 uint64_t sub_action_flags = 0;
5138 uint16_t queue_index = 0xFFFF;
5143 return rte_flow_error_set(error, EINVAL,
5144 RTE_FLOW_ERROR_TYPE_ACTION, action,
5145 "configuration cannot be NULL");
5146 if (sample->ratio == 0)
5147 return rte_flow_error_set(error, EINVAL,
5148 RTE_FLOW_ERROR_TYPE_ACTION, action,
5149 "ratio value starts from 1");
5150 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5151 return rte_flow_error_set(error, ENOTSUP,
5152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5154 "sample action not supported");
5155 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5156 return rte_flow_error_set(error, EINVAL,
5157 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5158 "Multiple sample actions not "
5160 if (*action_flags & MLX5_FLOW_ACTION_METER)
5161 return rte_flow_error_set(error, EINVAL,
5162 RTE_FLOW_ERROR_TYPE_ACTION, action,
5163 "wrong action order, meter should "
5164 "be after sample action");
5165 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5166 return rte_flow_error_set(error, EINVAL,
5167 RTE_FLOW_ERROR_TYPE_ACTION, action,
5168 "wrong action order, jump should "
5169 "be after sample action");
5170 act = sample->actions;
5171 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5172 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5173 return rte_flow_error_set(error, ENOTSUP,
5174 RTE_FLOW_ERROR_TYPE_ACTION,
5175 act, "too many actions");
5176 switch (act->type) {
5177 case RTE_FLOW_ACTION_TYPE_QUEUE:
5178 ret = mlx5_flow_validate_action_queue(act,
5184 queue_index = ((const struct rte_flow_action_queue *)
5185 (act->conf))->index;
5186 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5189 case RTE_FLOW_ACTION_TYPE_RSS:
5190 *sample_rss = act->conf;
5191 ret = mlx5_flow_validate_action_rss(act,
5198 if (rss && *sample_rss &&
5199 ((*sample_rss)->level != rss->level ||
5200 (*sample_rss)->types != rss->types))
5201 return rte_flow_error_set(error, ENOTSUP,
5202 RTE_FLOW_ERROR_TYPE_ACTION,
5204 "Can't use the different RSS types "
5205 "or level in the same flow");
5206 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5207 queue_index = (*sample_rss)->queue[0];
5208 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5211 case RTE_FLOW_ACTION_TYPE_MARK:
5212 ret = flow_dv_validate_action_mark(dev, act,
5217 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5218 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5219 MLX5_FLOW_ACTION_MARK_EXT;
5221 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5224 case RTE_FLOW_ACTION_TYPE_COUNT:
5225 ret = flow_dv_validate_action_count
5227 *action_flags | sub_action_flags,
5232 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5233 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5236 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5237 ret = flow_dv_validate_action_port_id(dev,
5244 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5247 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5248 ret = flow_dv_validate_action_raw_encap_decap
5249 (dev, NULL, act->conf, attr, &sub_action_flags,
5250 &actions_n, action, item_flags, error);
5255 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5256 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5257 ret = flow_dv_validate_action_l2_encap(dev,
5263 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5267 return rte_flow_error_set(error, ENOTSUP,
5268 RTE_FLOW_ERROR_TYPE_ACTION,
5270 "Doesn't support optional "
5274 if (attr->ingress && !attr->transfer) {
5275 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5276 MLX5_FLOW_ACTION_RSS)))
5277 return rte_flow_error_set(error, EINVAL,
5278 RTE_FLOW_ERROR_TYPE_ACTION,
5280 "Ingress must has a dest "
5281 "QUEUE for Sample");
5282 } else if (attr->egress && !attr->transfer) {
5283 return rte_flow_error_set(error, ENOTSUP,
5284 RTE_FLOW_ERROR_TYPE_ACTION,
5286 "Sample Only support Ingress "
5288 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5289 MLX5_ASSERT(attr->transfer);
5290 if (sample->ratio > 1)
5291 return rte_flow_error_set(error, ENOTSUP,
5292 RTE_FLOW_ERROR_TYPE_ACTION,
5294 "E-Switch doesn't support "
5295 "any optional action "
5297 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5298 return rte_flow_error_set(error, ENOTSUP,
5299 RTE_FLOW_ERROR_TYPE_ACTION,
5301 "unsupported action QUEUE");
5302 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5303 return rte_flow_error_set(error, ENOTSUP,
5304 RTE_FLOW_ERROR_TYPE_ACTION,
5306 "unsupported action QUEUE");
5307 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5308 return rte_flow_error_set(error, EINVAL,
5309 RTE_FLOW_ERROR_TYPE_ACTION,
5311 "E-Switch must has a dest "
5312 "port for mirroring");
5313 if (!priv->config.hca_attr.reg_c_preserve &&
5314 priv->representor_id != -1)
5315 *fdb_mirror_limit = 1;
5317 /* Continue validation for Xcap actions.*/
5318 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5319 (queue_index == 0xFFFF ||
5320 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5321 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5322 MLX5_FLOW_XCAP_ACTIONS)
5323 return rte_flow_error_set(error, ENOTSUP,
5324 RTE_FLOW_ERROR_TYPE_ACTION,
5325 NULL, "encap and decap "
5326 "combination aren't "
5328 if (!attr->transfer && attr->ingress && (sub_action_flags &
5329 MLX5_FLOW_ACTION_ENCAP))
5330 return rte_flow_error_set(error, ENOTSUP,
5331 RTE_FLOW_ERROR_TYPE_ACTION,
5332 NULL, "encap is not supported"
5333 " for ingress traffic");
5339 * Find existing modify-header resource or create and register a new one.
5341 * @param dev[in, out]
5342 * Pointer to rte_eth_dev structure.
5343 * @param[in, out] resource
5344 * Pointer to modify-header resource.
5345 * @parm[in, out] dev_flow
5346 * Pointer to the dev_flow.
5348 * pointer to error structure.
5351 * 0 on success otherwise -errno and errno is set.
5354 flow_dv_modify_hdr_resource_register
5355 (struct rte_eth_dev *dev,
5356 struct mlx5_flow_dv_modify_hdr_resource *resource,
5357 struct mlx5_flow *dev_flow,
5358 struct rte_flow_error *error)
5360 struct mlx5_priv *priv = dev->data->dev_private;
5361 struct mlx5_dev_ctx_shared *sh = priv->sh;
5362 uint32_t key_len = sizeof(*resource) -
5363 offsetof(typeof(*resource), ft_type) +
5364 resource->actions_num * sizeof(resource->actions[0]);
5365 struct mlx5_hlist_entry *entry;
5366 struct mlx5_flow_cb_ctx ctx = {
5372 resource->flags = dev_flow->dv.group ? 0 :
5373 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5374 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5376 return rte_flow_error_set(error, EOVERFLOW,
5377 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5378 "too many modify header items");
5379 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5380 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5383 resource = container_of(entry, typeof(*resource), entry);
5384 dev_flow->handle->dvh.modify_hdr = resource;
5389 * Get DV flow counter by index.
5392 * Pointer to the Ethernet device structure.
5394 * mlx5 flow counter index in the container.
5396 * mlx5 flow counter pool in the container,
5399 * Pointer to the counter, NULL otherwise.
5401 static struct mlx5_flow_counter *
5402 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5404 struct mlx5_flow_counter_pool **ppool)
5406 struct mlx5_priv *priv = dev->data->dev_private;
5407 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5408 struct mlx5_flow_counter_pool *pool;
5410 /* Decrease to original index and clear shared bit. */
5411 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5412 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5413 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5417 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5421 * Check the devx counter belongs to the pool.
5424 * Pointer to the counter pool.
5426 * The counter devx ID.
5429 * True if counter belongs to the pool, false otherwise.
5432 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5434 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5435 MLX5_COUNTERS_PER_POOL;
5437 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5443 * Get a pool by devx counter ID.
5446 * Pointer to the counter management.
5448 * The counter devx ID.
5451 * The counter pool pointer if exists, NULL otherwise,
5453 static struct mlx5_flow_counter_pool *
5454 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5457 struct mlx5_flow_counter_pool *pool = NULL;
5459 rte_spinlock_lock(&cmng->pool_update_sl);
5460 /* Check last used pool. */
5461 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5462 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5463 pool = cmng->pools[cmng->last_pool_idx];
5466 /* ID out of range means no suitable pool in the container. */
5467 if (id > cmng->max_id || id < cmng->min_id)
5470 * Find the pool from the end of the container, since mostly counter
5471 * ID is sequence increasing, and the last pool should be the needed
5476 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5478 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5484 rte_spinlock_unlock(&cmng->pool_update_sl);
5489 * Resize a counter container.
5492 * Pointer to the Ethernet device structure.
5495 * 0 on success, otherwise negative errno value and rte_errno is set.
5498 flow_dv_container_resize(struct rte_eth_dev *dev)
5500 struct mlx5_priv *priv = dev->data->dev_private;
5501 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5502 void *old_pools = cmng->pools;
5503 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5504 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5505 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5512 memcpy(pools, old_pools, cmng->n *
5513 sizeof(struct mlx5_flow_counter_pool *));
5515 cmng->pools = pools;
5517 mlx5_free(old_pools);
5522 * Query a devx flow counter.
5525 * Pointer to the Ethernet device structure.
5527 * Index to the flow counter.
5529 * The statistics value of packets.
5531 * The statistics value of bytes.
5534 * 0 on success, otherwise a negative errno value and rte_errno is set.
5537 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5540 struct mlx5_priv *priv = dev->data->dev_private;
5541 struct mlx5_flow_counter_pool *pool = NULL;
5542 struct mlx5_flow_counter *cnt;
5545 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5547 if (priv->sh->cmng.counter_fallback)
5548 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5549 0, pkts, bytes, 0, NULL, NULL, 0);
5550 rte_spinlock_lock(&pool->sl);
5555 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5556 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5557 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5559 rte_spinlock_unlock(&pool->sl);
5564 * Create and initialize a new counter pool.
5567 * Pointer to the Ethernet device structure.
5569 * The devX counter handle.
5571 * Whether the pool is for counter that was allocated for aging.
5572 * @param[in/out] cont_cur
5573 * Pointer to the container pointer, it will be update in pool resize.
5576 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5578 static struct mlx5_flow_counter_pool *
5579 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5582 struct mlx5_priv *priv = dev->data->dev_private;
5583 struct mlx5_flow_counter_pool *pool;
5584 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5585 bool fallback = priv->sh->cmng.counter_fallback;
5586 uint32_t size = sizeof(*pool);
5588 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5589 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5590 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5596 pool->is_aged = !!age;
5597 pool->query_gen = 0;
5598 pool->min_dcs = dcs;
5599 rte_spinlock_init(&pool->sl);
5600 rte_spinlock_init(&pool->csl);
5601 TAILQ_INIT(&pool->counters[0]);
5602 TAILQ_INIT(&pool->counters[1]);
5603 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5604 rte_spinlock_lock(&cmng->pool_update_sl);
5605 pool->index = cmng->n_valid;
5606 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5608 rte_spinlock_unlock(&cmng->pool_update_sl);
5611 cmng->pools[pool->index] = pool;
5613 if (unlikely(fallback)) {
5614 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5616 if (base < cmng->min_id)
5617 cmng->min_id = base;
5618 if (base > cmng->max_id)
5619 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5620 cmng->last_pool_idx = pool->index;
5622 rte_spinlock_unlock(&cmng->pool_update_sl);
5627 * Prepare a new counter and/or a new counter pool.
5630 * Pointer to the Ethernet device structure.
5631 * @param[out] cnt_free
5632 * Where to put the pointer of a new counter.
5634 * Whether the pool is for counter that was allocated for aging.
5637 * The counter pool pointer and @p cnt_free is set on success,
5638 * NULL otherwise and rte_errno is set.
5640 static struct mlx5_flow_counter_pool *
5641 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5642 struct mlx5_flow_counter **cnt_free,
5645 struct mlx5_priv *priv = dev->data->dev_private;
5646 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5647 struct mlx5_flow_counter_pool *pool;
5648 struct mlx5_counters tmp_tq;
5649 struct mlx5_devx_obj *dcs = NULL;
5650 struct mlx5_flow_counter *cnt;
5651 enum mlx5_counter_type cnt_type =
5652 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5653 bool fallback = priv->sh->cmng.counter_fallback;
5657 /* bulk_bitmap must be 0 for single counter allocation. */
5658 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5661 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5663 pool = flow_dv_pool_create(dev, dcs, age);
5665 mlx5_devx_cmd_destroy(dcs);
5669 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5670 cnt = MLX5_POOL_GET_CNT(pool, i);
5672 cnt->dcs_when_free = dcs;
5676 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5678 rte_errno = ENODATA;
5681 pool = flow_dv_pool_create(dev, dcs, age);
5683 mlx5_devx_cmd_destroy(dcs);
5686 TAILQ_INIT(&tmp_tq);
5687 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5688 cnt = MLX5_POOL_GET_CNT(pool, i);
5690 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5692 rte_spinlock_lock(&cmng->csl[cnt_type]);
5693 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5694 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5695 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5696 (*cnt_free)->pool = pool;
5701 * Allocate a flow counter.
5704 * Pointer to the Ethernet device structure.
5706 * Whether the counter was allocated for aging.
5709 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5712 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5714 struct mlx5_priv *priv = dev->data->dev_private;
5715 struct mlx5_flow_counter_pool *pool = NULL;
5716 struct mlx5_flow_counter *cnt_free = NULL;
5717 bool fallback = priv->sh->cmng.counter_fallback;
5718 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5719 enum mlx5_counter_type cnt_type =
5720 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5723 if (!priv->config.devx) {
5724 rte_errno = ENOTSUP;
5727 /* Get free counters from container. */
5728 rte_spinlock_lock(&cmng->csl[cnt_type]);
5729 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5731 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5732 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5733 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5735 pool = cnt_free->pool;
5737 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5738 /* Create a DV counter action only in the first time usage. */
5739 if (!cnt_free->action) {
5741 struct mlx5_devx_obj *dcs;
5745 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5746 dcs = pool->min_dcs;
5749 dcs = cnt_free->dcs_when_free;
5751 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5758 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5759 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5760 /* Update the counter reset values. */
5761 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5764 if (!fallback && !priv->sh->cmng.query_thread_on)
5765 /* Start the asynchronous batch query by the host thread. */
5766 mlx5_set_query_alarm(priv->sh);
5770 cnt_free->pool = pool;
5772 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5773 rte_spinlock_lock(&cmng->csl[cnt_type]);
5774 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5775 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5781 * Allocate a shared flow counter.
5784 * Pointer to the shared counter configuration.
5786 * Pointer to save the allocated counter index.
5789 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5793 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5795 struct mlx5_shared_counter_conf *conf = ctx;
5796 struct rte_eth_dev *dev = conf->dev;
5797 struct mlx5_flow_counter *cnt;
5799 data->dword = flow_dv_counter_alloc(dev, 0);
5800 data->dword |= MLX5_CNT_SHARED_OFFSET;
5801 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5802 cnt->shared_info.id = conf->id;
5807 * Get a shared flow counter.
5810 * Pointer to the Ethernet device structure.
5812 * Counter identifier.
5815 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5818 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5820 struct mlx5_priv *priv = dev->data->dev_private;
5821 struct mlx5_shared_counter_conf conf = {
5825 union mlx5_l3t_data data = {
5829 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5830 flow_dv_counter_alloc_shared_cb, &conf);
5835 * Get age param from counter index.
5838 * Pointer to the Ethernet device structure.
5839 * @param[in] counter
5840 * Index to the counter handler.
5843 * The aging parameter specified for the counter index.
5845 static struct mlx5_age_param*
5846 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5849 struct mlx5_flow_counter *cnt;
5850 struct mlx5_flow_counter_pool *pool = NULL;
5852 flow_dv_counter_get_by_idx(dev, counter, &pool);
5853 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5854 cnt = MLX5_POOL_GET_CNT(pool, counter);
5855 return MLX5_CNT_TO_AGE(cnt);
5859 * Remove a flow counter from aged counter list.
5862 * Pointer to the Ethernet device structure.
5863 * @param[in] counter
5864 * Index to the counter handler.
5866 * Pointer to the counter handler.
5869 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5870 uint32_t counter, struct mlx5_flow_counter *cnt)
5872 struct mlx5_age_info *age_info;
5873 struct mlx5_age_param *age_param;
5874 struct mlx5_priv *priv = dev->data->dev_private;
5875 uint16_t expected = AGE_CANDIDATE;
5877 age_info = GET_PORT_AGE_INFO(priv);
5878 age_param = flow_dv_counter_idx_get_age(dev, counter);
5879 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5880 AGE_FREE, false, __ATOMIC_RELAXED,
5881 __ATOMIC_RELAXED)) {
5883 * We need the lock even it is age timeout,
5884 * since counter may still in process.
5886 rte_spinlock_lock(&age_info->aged_sl);
5887 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5888 rte_spinlock_unlock(&age_info->aged_sl);
5889 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5894 * Release a flow counter.
5897 * Pointer to the Ethernet device structure.
5898 * @param[in] counter
5899 * Index to the counter handler.
5902 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5904 struct mlx5_priv *priv = dev->data->dev_private;
5905 struct mlx5_flow_counter_pool *pool = NULL;
5906 struct mlx5_flow_counter *cnt;
5907 enum mlx5_counter_type cnt_type;
5911 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5913 if (IS_SHARED_CNT(counter) &&
5914 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5917 flow_dv_counter_remove_from_age(dev, counter, cnt);
5920 * Put the counter back to list to be updated in none fallback mode.
5921 * Currently, we are using two list alternately, while one is in query,
5922 * add the freed counter to the other list based on the pool query_gen
5923 * value. After query finishes, add counter the list to the global
5924 * container counter list. The list changes while query starts. In
5925 * this case, lock will not be needed as query callback and release
5926 * function both operate with the different list.
5929 if (!priv->sh->cmng.counter_fallback) {
5930 rte_spinlock_lock(&pool->csl);
5931 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5932 rte_spinlock_unlock(&pool->csl);
5934 cnt->dcs_when_free = cnt->dcs_when_active;
5935 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5936 MLX5_COUNTER_TYPE_ORIGIN;
5937 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5938 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5940 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5945 * Resize a meter id container.
5948 * Pointer to the Ethernet device structure.
5951 * 0 on success, otherwise negative errno value and rte_errno is set.
5954 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5956 struct mlx5_priv *priv = dev->data->dev_private;
5957 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5958 void *old_pools = mtrmng->pools;
5959 uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5960 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5961 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5968 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
5973 memcpy(pools, old_pools, mtrmng->n *
5974 sizeof(struct mlx5_aso_mtr_pool *));
5976 mtrmng->pools = pools;
5978 mlx5_free(old_pools);
5983 * Prepare a new meter and/or a new meter pool.
5986 * Pointer to the Ethernet device structure.
5987 * @param[out] mtr_free
5988 * Where to put the pointer of a new meter.g.
5991 * The meter pool pointer and @mtr_free is set on success,
5992 * NULL otherwise and rte_errno is set.
5994 static struct mlx5_aso_mtr_pool *
5995 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5996 struct mlx5_aso_mtr **mtr_free)
5998 struct mlx5_priv *priv = dev->data->dev_private;
5999 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6000 struct mlx5_aso_mtr_pool *pool = NULL;
6001 struct mlx5_devx_obj *dcs = NULL;
6003 uint32_t log_obj_size;
6005 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6006 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6007 priv->sh->pdn, log_obj_size);
6009 rte_errno = ENODATA;
6012 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6015 claim_zero(mlx5_devx_cmd_destroy(dcs));
6018 pool->devx_obj = dcs;
6019 pool->index = mtrmng->n_valid;
6020 if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
6022 claim_zero(mlx5_devx_cmd_destroy(dcs));
6025 mtrmng->pools[pool->index] = pool;
6027 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6028 pool->mtrs[i].offset = i;
6029 pool->mtrs[i].fm.meter_id = UINT32_MAX;
6030 LIST_INSERT_HEAD(&mtrmng->meters,
6031 &pool->mtrs[i], next);
6033 pool->mtrs[0].offset = 0;
6034 pool->mtrs[0].fm.meter_id = UINT32_MAX;
6035 *mtr_free = &pool->mtrs[0];
6040 * Release a flow meter into pool.
6043 * Pointer to the Ethernet device structure.
6044 * @param[in] mtr_idx
6045 * Index to aso flow meter.
6048 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6050 struct mlx5_priv *priv = dev->data->dev_private;
6051 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6052 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6054 MLX5_ASSERT(aso_mtr);
6055 rte_spinlock_lock(&mtrmng->mtrsl);
6056 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6057 aso_mtr->state = ASO_METER_FREE;
6058 aso_mtr->fm.meter_id = UINT32_MAX;
6059 LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6060 rte_spinlock_unlock(&mtrmng->mtrsl);
6064 * Allocate a aso flow meter.
6067 * Pointer to the Ethernet device structure.
6070 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6073 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6075 struct mlx5_priv *priv = dev->data->dev_private;
6076 struct mlx5_aso_mtr *mtr_free = NULL;
6077 struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6078 struct mlx5_aso_mtr_pool *pool;
6079 uint32_t mtr_idx = 0;
6081 if (!priv->config.devx) {
6082 rte_errno = ENOTSUP;
6085 /* Allocate the flow meter memory. */
6086 /* Get free meters from management. */
6087 rte_spinlock_lock(&mtrmng->mtrsl);
6088 mtr_free = LIST_FIRST(&mtrmng->meters);
6090 LIST_REMOVE(mtr_free, next);
6091 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6092 rte_spinlock_unlock(&mtrmng->mtrsl);
6095 mtr_free->state = ASO_METER_WAIT;
6096 rte_spinlock_unlock(&mtrmng->mtrsl);
6097 pool = container_of(mtr_free,
6098 struct mlx5_aso_mtr_pool,
6099 mtrs[mtr_free->offset]);
6100 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6101 if (!mtr_free->fm.meter_action) {
6102 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6103 struct rte_flow_error error;
6106 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6107 mtr_free->fm.meter_action =
6108 mlx5_glue->dv_create_flow_action_aso
6109 (priv->sh->rx_domain,
6110 pool->devx_obj->obj,
6112 (1 << MLX5_FLOW_COLOR_GREEN),
6114 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6115 if (!mtr_free->fm.meter_action) {
6116 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6124 * Verify the @p attributes will be correctly understood by the NIC and store
6125 * them in the @p flow if everything is correct.
6128 * Pointer to dev struct.
6129 * @param[in] attributes
6130 * Pointer to flow attributes
6131 * @param[in] external
6132 * This flow rule is created by request external to PMD.
6134 * Pointer to error structure.
6137 * - 0 on success and non root table.
6138 * - 1 on success and root table.
6139 * - a negative errno value otherwise and rte_errno is set.
6142 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6143 const struct mlx5_flow_tunnel *tunnel,
6144 const struct rte_flow_attr *attributes,
6145 const struct flow_grp_info *grp_info,
6146 struct rte_flow_error *error)
6148 struct mlx5_priv *priv = dev->data->dev_private;
6149 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6152 #ifndef HAVE_MLX5DV_DR
6153 RTE_SET_USED(tunnel);
6154 RTE_SET_USED(grp_info);
6155 if (attributes->group)
6156 return rte_flow_error_set(error, ENOTSUP,
6157 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6159 "groups are not supported");
6163 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6168 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6170 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6171 attributes->priority > lowest_priority)
6172 return rte_flow_error_set(error, ENOTSUP,
6173 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6175 "priority out of range");
6176 if (attributes->transfer) {
6177 if (!priv->config.dv_esw_en)
6178 return rte_flow_error_set
6180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6181 "E-Switch dr is not supported");
6182 if (!(priv->representor || priv->master))
6183 return rte_flow_error_set
6184 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6185 NULL, "E-Switch configuration can only be"
6186 " done by a master or a representor device");
6187 if (attributes->egress)
6188 return rte_flow_error_set
6190 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6191 "egress is not supported");
6193 if (!(attributes->egress ^ attributes->ingress))
6194 return rte_flow_error_set(error, ENOTSUP,
6195 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6196 "must specify exactly one of "
6197 "ingress or egress");
6202 * Internal validation function. For validating both actions and items.
6205 * Pointer to the rte_eth_dev structure.
6207 * Pointer to the flow attributes.
6209 * Pointer to the list of items.
6210 * @param[in] actions
6211 * Pointer to the list of actions.
6212 * @param[in] external
6213 * This flow rule is created by request external to PMD.
6214 * @param[in] hairpin
6215 * Number of hairpin TX actions, 0 means classic flow.
6217 * Pointer to the error structure.
6220 * 0 on success, a negative errno value otherwise and rte_errno is set.
6223 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6224 const struct rte_flow_item items[],
6225 const struct rte_flow_action actions[],
6226 bool external, int hairpin, struct rte_flow_error *error)
6229 uint64_t action_flags = 0;
6230 uint64_t item_flags = 0;
6231 uint64_t last_item = 0;
6232 uint8_t next_protocol = 0xff;
6233 uint16_t ether_type = 0;
6235 uint8_t item_ipv6_proto = 0;
6236 int fdb_mirror_limit = 0;
6237 int modify_after_mirror = 0;
6238 const struct rte_flow_item *geneve_item = NULL;
6239 const struct rte_flow_item *gre_item = NULL;
6240 const struct rte_flow_item *gtp_item = NULL;
6241 const struct rte_flow_action_raw_decap *decap;
6242 const struct rte_flow_action_raw_encap *encap;
6243 const struct rte_flow_action_rss *rss = NULL;
6244 const struct rte_flow_action_rss *sample_rss = NULL;
6245 const struct rte_flow_action_count *count = NULL;
6246 const struct rte_flow_action_count *sample_count = NULL;
6247 const struct rte_flow_item_tcp nic_tcp_mask = {
6250 .src_port = RTE_BE16(UINT16_MAX),
6251 .dst_port = RTE_BE16(UINT16_MAX),
6254 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6257 "\xff\xff\xff\xff\xff\xff\xff\xff"
6258 "\xff\xff\xff\xff\xff\xff\xff\xff",
6260 "\xff\xff\xff\xff\xff\xff\xff\xff"
6261 "\xff\xff\xff\xff\xff\xff\xff\xff",
6262 .vtc_flow = RTE_BE32(0xffffffff),
6268 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6272 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6276 .dummy[0] = 0xffffffff,
6279 struct mlx5_priv *priv = dev->data->dev_private;
6280 struct mlx5_dev_config *dev_conf = &priv->config;
6281 uint16_t queue_index = 0xFFFF;
6282 const struct rte_flow_item_vlan *vlan_m = NULL;
6283 uint32_t rw_act_num = 0;
6285 const struct mlx5_flow_tunnel *tunnel;
6286 struct flow_grp_info grp_info = {
6287 .external = !!external,
6288 .transfer = !!attr->transfer,
6289 .fdb_def_rule = !!priv->fdb_def_rule,
6291 const struct rte_eth_hairpin_conf *conf;
6295 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6296 tunnel = flow_items_to_tunnel(items);
6297 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6298 MLX5_FLOW_ACTION_DECAP;
6299 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6300 tunnel = flow_actions_to_tunnel(actions);
6301 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6305 if (tunnel && priv->representor)
6306 return rte_flow_error_set(error, ENOTSUP,
6307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6308 "decap not supported "
6309 "for VF representor");
6310 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6311 (dev, tunnel, attr, items, actions);
6312 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6315 is_root = (uint64_t)ret;
6316 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6317 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6318 int type = items->type;
6320 if (!mlx5_flow_os_item_supported(type))
6321 return rte_flow_error_set(error, ENOTSUP,
6322 RTE_FLOW_ERROR_TYPE_ITEM,
6323 NULL, "item not supported");
6325 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6326 if (items[0].type != (typeof(items[0].type))
6327 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6328 return rte_flow_error_set
6330 RTE_FLOW_ERROR_TYPE_ITEM,
6331 NULL, "MLX5 private items "
6332 "must be the first");
6334 case RTE_FLOW_ITEM_TYPE_VOID:
6336 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6337 ret = flow_dv_validate_item_port_id
6338 (dev, items, attr, item_flags, error);
6341 last_item = MLX5_FLOW_ITEM_PORT_ID;
6343 case RTE_FLOW_ITEM_TYPE_ETH:
6344 ret = mlx5_flow_validate_item_eth(items, item_flags,
6348 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6349 MLX5_FLOW_LAYER_OUTER_L2;
6350 if (items->mask != NULL && items->spec != NULL) {
6352 ((const struct rte_flow_item_eth *)
6355 ((const struct rte_flow_item_eth *)
6357 ether_type = rte_be_to_cpu_16(ether_type);
6362 case RTE_FLOW_ITEM_TYPE_VLAN:
6363 ret = flow_dv_validate_item_vlan(items, item_flags,
6367 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6368 MLX5_FLOW_LAYER_OUTER_VLAN;
6369 if (items->mask != NULL && items->spec != NULL) {
6371 ((const struct rte_flow_item_vlan *)
6372 items->spec)->inner_type;
6374 ((const struct rte_flow_item_vlan *)
6375 items->mask)->inner_type;
6376 ether_type = rte_be_to_cpu_16(ether_type);
6380 /* Store outer VLAN mask for of_push_vlan action. */
6382 vlan_m = items->mask;
6384 case RTE_FLOW_ITEM_TYPE_IPV4:
6385 mlx5_flow_tunnel_ip_check(items, next_protocol,
6386 &item_flags, &tunnel);
6387 ret = flow_dv_validate_item_ipv4(items, item_flags,
6388 last_item, ether_type,
6392 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6393 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6394 if (items->mask != NULL &&
6395 ((const struct rte_flow_item_ipv4 *)
6396 items->mask)->hdr.next_proto_id) {
6398 ((const struct rte_flow_item_ipv4 *)
6399 (items->spec))->hdr.next_proto_id;
6401 ((const struct rte_flow_item_ipv4 *)
6402 (items->mask))->hdr.next_proto_id;
6404 /* Reset for inner layer. */
6405 next_protocol = 0xff;
6408 case RTE_FLOW_ITEM_TYPE_IPV6:
6409 mlx5_flow_tunnel_ip_check(items, next_protocol,
6410 &item_flags, &tunnel);
6411 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6418 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6419 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6420 if (items->mask != NULL &&
6421 ((const struct rte_flow_item_ipv6 *)
6422 items->mask)->hdr.proto) {
6424 ((const struct rte_flow_item_ipv6 *)
6425 items->spec)->hdr.proto;
6427 ((const struct rte_flow_item_ipv6 *)
6428 items->spec)->hdr.proto;
6430 ((const struct rte_flow_item_ipv6 *)
6431 items->mask)->hdr.proto;
6433 /* Reset for inner layer. */
6434 next_protocol = 0xff;
6437 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6438 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6443 last_item = tunnel ?
6444 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6445 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6446 if (items->mask != NULL &&
6447 ((const struct rte_flow_item_ipv6_frag_ext *)
6448 items->mask)->hdr.next_header) {
6450 ((const struct rte_flow_item_ipv6_frag_ext *)
6451 items->spec)->hdr.next_header;
6453 ((const struct rte_flow_item_ipv6_frag_ext *)
6454 items->mask)->hdr.next_header;
6456 /* Reset for inner layer. */
6457 next_protocol = 0xff;
6460 case RTE_FLOW_ITEM_TYPE_TCP:
6461 ret = mlx5_flow_validate_item_tcp
6468 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6469 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6471 case RTE_FLOW_ITEM_TYPE_UDP:
6472 ret = mlx5_flow_validate_item_udp(items, item_flags,
6477 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6478 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6480 case RTE_FLOW_ITEM_TYPE_GRE:
6481 ret = mlx5_flow_validate_item_gre(items, item_flags,
6482 next_protocol, error);
6486 last_item = MLX5_FLOW_LAYER_GRE;
6488 case RTE_FLOW_ITEM_TYPE_NVGRE:
6489 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6494 last_item = MLX5_FLOW_LAYER_NVGRE;
6496 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6497 ret = mlx5_flow_validate_item_gre_key
6498 (items, item_flags, gre_item, error);
6501 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6503 case RTE_FLOW_ITEM_TYPE_VXLAN:
6504 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6508 last_item = MLX5_FLOW_LAYER_VXLAN;
6510 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6511 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6516 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6518 case RTE_FLOW_ITEM_TYPE_GENEVE:
6519 ret = mlx5_flow_validate_item_geneve(items,
6524 geneve_item = items;
6525 last_item = MLX5_FLOW_LAYER_GENEVE;
6527 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6528 ret = mlx5_flow_validate_item_geneve_opt(items,
6535 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6537 case RTE_FLOW_ITEM_TYPE_MPLS:
6538 ret = mlx5_flow_validate_item_mpls(dev, items,
6543 last_item = MLX5_FLOW_LAYER_MPLS;
6546 case RTE_FLOW_ITEM_TYPE_MARK:
6547 ret = flow_dv_validate_item_mark(dev, items, attr,
6551 last_item = MLX5_FLOW_ITEM_MARK;
6553 case RTE_FLOW_ITEM_TYPE_META:
6554 ret = flow_dv_validate_item_meta(dev, items, attr,
6558 last_item = MLX5_FLOW_ITEM_METADATA;
6560 case RTE_FLOW_ITEM_TYPE_ICMP:
6561 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6566 last_item = MLX5_FLOW_LAYER_ICMP;
6568 case RTE_FLOW_ITEM_TYPE_ICMP6:
6569 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6574 item_ipv6_proto = IPPROTO_ICMPV6;
6575 last_item = MLX5_FLOW_LAYER_ICMP6;
6577 case RTE_FLOW_ITEM_TYPE_TAG:
6578 ret = flow_dv_validate_item_tag(dev, items,
6582 last_item = MLX5_FLOW_ITEM_TAG;
6584 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6585 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6587 case RTE_FLOW_ITEM_TYPE_GTP:
6588 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6593 last_item = MLX5_FLOW_LAYER_GTP;
6595 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6596 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6601 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6603 case RTE_FLOW_ITEM_TYPE_ECPRI:
6604 /* Capacity will be checked in the translate stage. */
6605 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6612 last_item = MLX5_FLOW_LAYER_ECPRI;
6615 return rte_flow_error_set(error, ENOTSUP,
6616 RTE_FLOW_ERROR_TYPE_ITEM,
6617 NULL, "item not supported");
6619 item_flags |= last_item;
6621 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6622 int type = actions->type;
6624 if (!mlx5_flow_os_action_supported(type))
6625 return rte_flow_error_set(error, ENOTSUP,
6626 RTE_FLOW_ERROR_TYPE_ACTION,
6628 "action not supported");
6629 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6630 return rte_flow_error_set(error, ENOTSUP,
6631 RTE_FLOW_ERROR_TYPE_ACTION,
6632 actions, "too many actions");
6634 case RTE_FLOW_ACTION_TYPE_VOID:
6636 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6637 ret = flow_dv_validate_action_port_id(dev,
6644 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6647 case RTE_FLOW_ACTION_TYPE_FLAG:
6648 ret = flow_dv_validate_action_flag(dev, action_flags,
6652 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6653 /* Count all modify-header actions as one. */
6654 if (!(action_flags &
6655 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6657 action_flags |= MLX5_FLOW_ACTION_FLAG |
6658 MLX5_FLOW_ACTION_MARK_EXT;
6659 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6660 modify_after_mirror = 1;
6663 action_flags |= MLX5_FLOW_ACTION_FLAG;
6666 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6668 case RTE_FLOW_ACTION_TYPE_MARK:
6669 ret = flow_dv_validate_action_mark(dev, actions,
6674 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6675 /* Count all modify-header actions as one. */
6676 if (!(action_flags &
6677 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6679 action_flags |= MLX5_FLOW_ACTION_MARK |
6680 MLX5_FLOW_ACTION_MARK_EXT;
6681 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6682 modify_after_mirror = 1;
6684 action_flags |= MLX5_FLOW_ACTION_MARK;
6687 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6689 case RTE_FLOW_ACTION_TYPE_SET_META:
6690 ret = flow_dv_validate_action_set_meta(dev, actions,
6695 /* Count all modify-header actions as one action. */
6696 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6698 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6699 modify_after_mirror = 1;
6700 action_flags |= MLX5_FLOW_ACTION_SET_META;
6701 rw_act_num += MLX5_ACT_NUM_SET_META;
6703 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6704 ret = flow_dv_validate_action_set_tag(dev, actions,
6709 /* Count all modify-header actions as one action. */
6710 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6712 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6713 modify_after_mirror = 1;
6714 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6715 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6717 case RTE_FLOW_ACTION_TYPE_DROP:
6718 ret = mlx5_flow_validate_action_drop(action_flags,
6722 action_flags |= MLX5_FLOW_ACTION_DROP;
6725 case RTE_FLOW_ACTION_TYPE_QUEUE:
6726 ret = mlx5_flow_validate_action_queue(actions,
6731 queue_index = ((const struct rte_flow_action_queue *)
6732 (actions->conf))->index;
6733 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6736 case RTE_FLOW_ACTION_TYPE_RSS:
6737 rss = actions->conf;
6738 ret = mlx5_flow_validate_action_rss(actions,
6744 if (rss && sample_rss &&
6745 (sample_rss->level != rss->level ||
6746 sample_rss->types != rss->types))
6747 return rte_flow_error_set(error, ENOTSUP,
6748 RTE_FLOW_ERROR_TYPE_ACTION,
6750 "Can't use the different RSS types "
6751 "or level in the same flow");
6752 if (rss != NULL && rss->queue_num)
6753 queue_index = rss->queue[0];
6754 action_flags |= MLX5_FLOW_ACTION_RSS;
6757 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6759 mlx5_flow_validate_action_default_miss(action_flags,
6763 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6766 case RTE_FLOW_ACTION_TYPE_COUNT:
6767 ret = flow_dv_validate_action_count(dev, actions,
6772 count = actions->conf;
6773 action_flags |= MLX5_FLOW_ACTION_COUNT;
6776 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6777 if (flow_dv_validate_action_pop_vlan(dev,
6783 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6784 modify_after_mirror = 1;
6785 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6788 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6789 ret = flow_dv_validate_action_push_vlan(dev,
6796 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6797 modify_after_mirror = 1;
6798 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6801 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6802 ret = flow_dv_validate_action_set_vlan_pcp
6803 (action_flags, actions, error);
6806 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6807 modify_after_mirror = 1;
6808 /* Count PCP with push_vlan command. */
6809 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6811 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6812 ret = flow_dv_validate_action_set_vlan_vid
6813 (item_flags, action_flags,
6817 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6818 modify_after_mirror = 1;
6819 /* Count VID with push_vlan command. */
6820 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6821 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6823 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6824 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6825 ret = flow_dv_validate_action_l2_encap(dev,
6831 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6834 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6835 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6836 ret = flow_dv_validate_action_decap(dev, action_flags,
6837 actions, item_flags,
6841 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6842 modify_after_mirror = 1;
6843 action_flags |= MLX5_FLOW_ACTION_DECAP;
6846 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6847 ret = flow_dv_validate_action_raw_encap_decap
6848 (dev, NULL, actions->conf, attr, &action_flags,
6849 &actions_n, actions, item_flags, error);
6853 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6854 decap = actions->conf;
6855 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6857 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6861 encap = actions->conf;
6863 ret = flow_dv_validate_action_raw_encap_decap
6865 decap ? decap : &empty_decap, encap,
6866 attr, &action_flags, &actions_n,
6867 actions, item_flags, error);
6870 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6871 (action_flags & MLX5_FLOW_ACTION_DECAP))
6872 modify_after_mirror = 1;
6874 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6875 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6876 ret = flow_dv_validate_action_modify_mac(action_flags,
6882 /* Count all modify-header actions as one action. */
6883 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6885 action_flags |= actions->type ==
6886 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6887 MLX5_FLOW_ACTION_SET_MAC_SRC :
6888 MLX5_FLOW_ACTION_SET_MAC_DST;
6889 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6890 modify_after_mirror = 1;
6892 * Even if the source and destination MAC addresses have
6893 * overlap in the header with 4B alignment, the convert
6894 * function will handle them separately and 4 SW actions
6895 * will be created. And 2 actions will be added each
6896 * time no matter how many bytes of address will be set.
6898 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6900 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6901 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6902 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6908 /* Count all modify-header actions as one action. */
6909 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6911 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6912 modify_after_mirror = 1;
6913 action_flags |= actions->type ==
6914 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6915 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6916 MLX5_FLOW_ACTION_SET_IPV4_DST;
6917 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6919 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6920 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6921 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6927 if (item_ipv6_proto == IPPROTO_ICMPV6)
6928 return rte_flow_error_set(error, ENOTSUP,
6929 RTE_FLOW_ERROR_TYPE_ACTION,
6931 "Can't change header "
6932 "with ICMPv6 proto");
6933 /* Count all modify-header actions as one action. */
6934 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6936 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6937 modify_after_mirror = 1;
6938 action_flags |= actions->type ==
6939 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6940 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6941 MLX5_FLOW_ACTION_SET_IPV6_DST;
6942 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6944 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6945 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6946 ret = flow_dv_validate_action_modify_tp(action_flags,
6952 /* Count all modify-header actions as one action. */
6953 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6955 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6956 modify_after_mirror = 1;
6957 action_flags |= actions->type ==
6958 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6959 MLX5_FLOW_ACTION_SET_TP_SRC :
6960 MLX5_FLOW_ACTION_SET_TP_DST;
6961 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6963 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6964 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6965 ret = flow_dv_validate_action_modify_ttl(action_flags,
6971 /* Count all modify-header actions as one action. */
6972 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6974 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6975 modify_after_mirror = 1;
6976 action_flags |= actions->type ==
6977 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6978 MLX5_FLOW_ACTION_SET_TTL :
6979 MLX5_FLOW_ACTION_DEC_TTL;
6980 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6982 case RTE_FLOW_ACTION_TYPE_JUMP:
6983 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6989 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6991 return rte_flow_error_set(error, EINVAL,
6992 RTE_FLOW_ERROR_TYPE_ACTION,
6994 "sample and jump action combination is not supported");
6996 action_flags |= MLX5_FLOW_ACTION_JUMP;
6998 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6999 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7000 ret = flow_dv_validate_action_modify_tcp_seq
7007 /* Count all modify-header actions as one action. */
7008 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7010 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7011 modify_after_mirror = 1;
7012 action_flags |= actions->type ==
7013 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7014 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7015 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7016 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7018 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7019 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7020 ret = flow_dv_validate_action_modify_tcp_ack
7027 /* Count all modify-header actions as one action. */
7028 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7030 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7031 modify_after_mirror = 1;
7032 action_flags |= actions->type ==
7033 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7034 MLX5_FLOW_ACTION_INC_TCP_ACK :
7035 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7036 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7038 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7040 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7041 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7042 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7044 case RTE_FLOW_ACTION_TYPE_METER:
7045 ret = mlx5_flow_validate_action_meter(dev,
7051 action_flags |= MLX5_FLOW_ACTION_METER;
7053 /* Meter action will add one more TAG action. */
7054 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7056 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7057 if (!attr->transfer && !attr->group)
7058 return rte_flow_error_set(error, ENOTSUP,
7059 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7061 "Shared ASO age action is not supported for group 0");
7062 action_flags |= MLX5_FLOW_ACTION_AGE;
7065 case RTE_FLOW_ACTION_TYPE_AGE:
7066 ret = flow_dv_validate_action_age(action_flags,
7072 * Validate the regular AGE action (using counter)
7073 * mutual exclusion with share counter actions.
7075 if (!priv->sh->flow_hit_aso_en) {
7076 if (count && count->shared)
7077 return rte_flow_error_set
7079 RTE_FLOW_ERROR_TYPE_ACTION,
7081 "old age and shared count combination is not supported");
7083 return rte_flow_error_set
7085 RTE_FLOW_ERROR_TYPE_ACTION,
7087 "old age action and count must be in the same sub flow");
7089 action_flags |= MLX5_FLOW_ACTION_AGE;
7092 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7093 ret = flow_dv_validate_action_modify_ipv4_dscp
7100 /* Count all modify-header actions as one action. */
7101 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7103 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7104 modify_after_mirror = 1;
7105 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7106 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7108 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7109 ret = flow_dv_validate_action_modify_ipv6_dscp
7116 /* Count all modify-header actions as one action. */
7117 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7119 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7120 modify_after_mirror = 1;
7121 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7122 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7124 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7125 ret = flow_dv_validate_action_sample(&action_flags,
7134 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7137 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7138 if (actions[0].type != (typeof(actions[0].type))
7139 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7140 return rte_flow_error_set
7142 RTE_FLOW_ERROR_TYPE_ACTION,
7143 NULL, "MLX5 private action "
7144 "must be the first");
7146 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7148 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7149 ret = flow_dv_validate_action_modify_field(dev,
7156 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7157 modify_after_mirror = 1;
7158 /* Count all modify-header actions as one action. */
7159 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7161 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7165 return rte_flow_error_set(error, ENOTSUP,
7166 RTE_FLOW_ERROR_TYPE_ACTION,
7168 "action not supported");
7172 * Validate actions in flow rules
7173 * - Explicit decap action is prohibited by the tunnel offload API.
7174 * - Drop action in tunnel steer rule is prohibited by the API.
7175 * - Application cannot use MARK action because it's value can mask
7176 * tunnel default miss nitification.
7177 * - JUMP in tunnel match rule has no support in current PMD
7179 * - TAG & META are reserved for future uses.
7181 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7182 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7183 MLX5_FLOW_ACTION_MARK |
7184 MLX5_FLOW_ACTION_SET_TAG |
7185 MLX5_FLOW_ACTION_SET_META |
7186 MLX5_FLOW_ACTION_DROP;
7188 if (action_flags & bad_actions_mask)
7189 return rte_flow_error_set
7191 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7192 "Invalid RTE action in tunnel "
7194 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7195 return rte_flow_error_set
7197 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7198 "tunnel set decap rule must terminate "
7201 return rte_flow_error_set
7203 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7204 "tunnel flows for ingress traffic only");
7206 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7207 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7208 MLX5_FLOW_ACTION_MARK |
7209 MLX5_FLOW_ACTION_SET_TAG |
7210 MLX5_FLOW_ACTION_SET_META;
7212 if (action_flags & bad_actions_mask)
7213 return rte_flow_error_set
7215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7216 "Invalid RTE action in tunnel "
7220 * Validate the drop action mutual exclusion with other actions.
7221 * Drop action is mutually-exclusive with any other action, except for
7223 * Drop action compatibility with tunnel offload was already validated.
7225 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7226 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7227 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7228 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7229 return rte_flow_error_set(error, EINVAL,
7230 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7231 "Drop action is mutually-exclusive "
7232 "with any other action, except for "
7234 /* Eswitch has few restrictions on using items and actions */
7235 if (attr->transfer) {
7236 if (!mlx5_flow_ext_mreg_supported(dev) &&
7237 action_flags & MLX5_FLOW_ACTION_FLAG)
7238 return rte_flow_error_set(error, ENOTSUP,
7239 RTE_FLOW_ERROR_TYPE_ACTION,
7241 "unsupported action FLAG");
7242 if (!mlx5_flow_ext_mreg_supported(dev) &&
7243 action_flags & MLX5_FLOW_ACTION_MARK)
7244 return rte_flow_error_set(error, ENOTSUP,
7245 RTE_FLOW_ERROR_TYPE_ACTION,
7247 "unsupported action MARK");
7248 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7249 return rte_flow_error_set(error, ENOTSUP,
7250 RTE_FLOW_ERROR_TYPE_ACTION,
7252 "unsupported action QUEUE");
7253 if (action_flags & MLX5_FLOW_ACTION_RSS)
7254 return rte_flow_error_set(error, ENOTSUP,
7255 RTE_FLOW_ERROR_TYPE_ACTION,
7257 "unsupported action RSS");
7258 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7259 return rte_flow_error_set(error, EINVAL,
7260 RTE_FLOW_ERROR_TYPE_ACTION,
7262 "no fate action is found");
7264 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7265 return rte_flow_error_set(error, EINVAL,
7266 RTE_FLOW_ERROR_TYPE_ACTION,
7268 "no fate action is found");
7271 * Continue validation for Xcap and VLAN actions.
7272 * If hairpin is working in explicit TX rule mode, there is no actions
7273 * splitting and the validation of hairpin ingress flow should be the
7274 * same as other standard flows.
7276 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7277 MLX5_FLOW_VLAN_ACTIONS)) &&
7278 (queue_index == 0xFFFF ||
7279 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7280 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7281 conf->tx_explicit != 0))) {
7282 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7283 MLX5_FLOW_XCAP_ACTIONS)
7284 return rte_flow_error_set(error, ENOTSUP,
7285 RTE_FLOW_ERROR_TYPE_ACTION,
7286 NULL, "encap and decap "
7287 "combination aren't supported");
7288 if (!attr->transfer && attr->ingress) {
7289 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7290 return rte_flow_error_set
7292 RTE_FLOW_ERROR_TYPE_ACTION,
7293 NULL, "encap is not supported"
7294 " for ingress traffic");
7295 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7296 return rte_flow_error_set
7298 RTE_FLOW_ERROR_TYPE_ACTION,
7299 NULL, "push VLAN action not "
7300 "supported for ingress");
7301 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7302 MLX5_FLOW_VLAN_ACTIONS)
7303 return rte_flow_error_set
7305 RTE_FLOW_ERROR_TYPE_ACTION,
7306 NULL, "no support for "
7307 "multiple VLAN actions");
7311 * Hairpin flow will add one more TAG action in TX implicit mode.
7312 * In TX explicit mode, there will be no hairpin flow ID.
7315 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7316 /* extra metadata enabled: one more TAG action will be add. */
7317 if (dev_conf->dv_flow_en &&
7318 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7319 mlx5_flow_ext_mreg_supported(dev))
7320 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7322 flow_dv_modify_hdr_action_max(dev, is_root)) {
7323 return rte_flow_error_set(error, ENOTSUP,
7324 RTE_FLOW_ERROR_TYPE_ACTION,
7325 NULL, "too many header modify"
7326 " actions to support");
7328 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7329 if (fdb_mirror_limit && modify_after_mirror)
7330 return rte_flow_error_set(error, EINVAL,
7331 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7332 "sample before modify action is not supported");
7337 * Internal preparation function. Allocates the DV flow size,
7338 * this size is constant.
7341 * Pointer to the rte_eth_dev structure.
7343 * Pointer to the flow attributes.
7345 * Pointer to the list of items.
7346 * @param[in] actions
7347 * Pointer to the list of actions.
7349 * Pointer to the error structure.
7352 * Pointer to mlx5_flow object on success,
7353 * otherwise NULL and rte_errno is set.
7355 static struct mlx5_flow *
7356 flow_dv_prepare(struct rte_eth_dev *dev,
7357 const struct rte_flow_attr *attr __rte_unused,
7358 const struct rte_flow_item items[] __rte_unused,
7359 const struct rte_flow_action actions[] __rte_unused,
7360 struct rte_flow_error *error)
7362 uint32_t handle_idx = 0;
7363 struct mlx5_flow *dev_flow;
7364 struct mlx5_flow_handle *dev_handle;
7365 struct mlx5_priv *priv = dev->data->dev_private;
7366 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7369 /* In case of corrupting the memory. */
7370 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7371 rte_flow_error_set(error, ENOSPC,
7372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7373 "not free temporary device flow");
7376 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7379 rte_flow_error_set(error, ENOMEM,
7380 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7381 "not enough memory to create flow handle");
7384 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7385 dev_flow = &wks->flows[wks->flow_idx++];
7386 memset(dev_flow, 0, sizeof(*dev_flow));
7387 dev_flow->handle = dev_handle;
7388 dev_flow->handle_idx = handle_idx;
7390 * In some old rdma-core releases, before continuing, a check of the
7391 * length of matching parameter will be done at first. It needs to use
7392 * the length without misc4 param. If the flow has misc4 support, then
7393 * the length needs to be adjusted accordingly. Each param member is
7394 * aligned with a 64B boundary naturally.
7396 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7397 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7398 dev_flow->ingress = attr->ingress;
7399 dev_flow->dv.transfer = attr->transfer;
7403 #ifdef RTE_LIBRTE_MLX5_DEBUG
7405 * Sanity check for match mask and value. Similar to check_valid_spec() in
7406 * kernel driver. If unmasked bit is present in value, it returns failure.
7409 * pointer to match mask buffer.
7410 * @param match_value
7411 * pointer to match value buffer.
7414 * 0 if valid, -EINVAL otherwise.
7417 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7419 uint8_t *m = match_mask;
7420 uint8_t *v = match_value;
7423 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7426 "match_value differs from match_criteria"
7427 " %p[%u] != %p[%u]",
7428 match_value, i, match_mask, i);
7437 * Add match of ip_version.
7441 * @param[in] headers_v
7442 * Values header pointer.
7443 * @param[in] headers_m
7444 * Masks header pointer.
7445 * @param[in] ip_version
7446 * The IP version to set.
7449 flow_dv_set_match_ip_version(uint32_t group,
7455 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7457 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7459 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7460 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7461 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7465 * Add Ethernet item to matcher and to the value.
7467 * @param[in, out] matcher
7469 * @param[in, out] key
7470 * Flow matcher value.
7472 * Flow pattern to translate.
7474 * Item is inner pattern.
7477 flow_dv_translate_item_eth(void *matcher, void *key,
7478 const struct rte_flow_item *item, int inner,
7481 const struct rte_flow_item_eth *eth_m = item->mask;
7482 const struct rte_flow_item_eth *eth_v = item->spec;
7483 const struct rte_flow_item_eth nic_mask = {
7484 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7485 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7486 .type = RTE_BE16(0xffff),
7499 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7501 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7503 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7505 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7507 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7508 ð_m->dst, sizeof(eth_m->dst));
7509 /* The value must be in the range of the mask. */
7510 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7511 for (i = 0; i < sizeof(eth_m->dst); ++i)
7512 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7513 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7514 ð_m->src, sizeof(eth_m->src));
7515 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7516 /* The value must be in the range of the mask. */
7517 for (i = 0; i < sizeof(eth_m->dst); ++i)
7518 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7520 * HW supports match on one Ethertype, the Ethertype following the last
7521 * VLAN tag of the packet (see PRM).
7522 * Set match on ethertype only if ETH header is not followed by VLAN.
7523 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7524 * ethertype, and use ip_version field instead.
7525 * eCPRI over Ether layer will use type value 0xAEFE.
7527 if (eth_m->type == 0xFFFF) {
7528 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7529 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7530 switch (eth_v->type) {
7531 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7532 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7534 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7535 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7536 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7538 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7539 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7541 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7542 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7548 if (eth_m->has_vlan) {
7549 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7550 if (eth_v->has_vlan) {
7552 * Here, when also has_more_vlan field in VLAN item is
7553 * not set, only single-tagged packets will be matched.
7555 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7559 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7560 rte_be_to_cpu_16(eth_m->type));
7561 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7562 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7566 * Add VLAN item to matcher and to the value.
7568 * @param[in, out] dev_flow
7570 * @param[in, out] matcher
7572 * @param[in, out] key
7573 * Flow matcher value.
7575 * Flow pattern to translate.
7577 * Item is inner pattern.
7580 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7581 void *matcher, void *key,
7582 const struct rte_flow_item *item,
7583 int inner, uint32_t group)
7585 const struct rte_flow_item_vlan *vlan_m = item->mask;
7586 const struct rte_flow_item_vlan *vlan_v = item->spec;
7593 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7595 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7597 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7599 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7601 * This is workaround, masks are not supported,
7602 * and pre-validated.
7605 dev_flow->handle->vf_vlan.tag =
7606 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7609 * When VLAN item exists in flow, mark packet as tagged,
7610 * even if TCI is not specified.
7612 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7613 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7614 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7619 vlan_m = &rte_flow_item_vlan_mask;
7620 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7621 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7622 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7623 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7624 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7625 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7626 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7627 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7629 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7630 * ethertype, and use ip_version field instead.
7632 if (vlan_m->inner_type == 0xFFFF) {
7633 switch (vlan_v->inner_type) {
7634 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7635 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7636 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7637 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7639 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7640 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7642 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7643 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7649 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7650 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7651 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7652 /* Only one vlan_tag bit can be set. */
7653 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7656 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7657 rte_be_to_cpu_16(vlan_m->inner_type));
7658 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7659 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7663 * Add IPV4 item to matcher and to the value.
7665 * @param[in, out] matcher
7667 * @param[in, out] key
7668 * Flow matcher value.
7670 * Flow pattern to translate.
7672 * Item is inner pattern.
7674 * The group to insert the rule.
7677 flow_dv_translate_item_ipv4(void *matcher, void *key,
7678 const struct rte_flow_item *item,
7679 int inner, uint32_t group)
7681 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7682 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7683 const struct rte_flow_item_ipv4 nic_mask = {
7685 .src_addr = RTE_BE32(0xffffffff),
7686 .dst_addr = RTE_BE32(0xffffffff),
7687 .type_of_service = 0xff,
7688 .next_proto_id = 0xff,
7689 .time_to_live = 0xff,
7699 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7701 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7703 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7705 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7707 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7712 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7713 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7714 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7715 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7716 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7717 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7718 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7719 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7720 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7721 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7722 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7723 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7724 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7726 ipv4_m->hdr.type_of_service);
7727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7728 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7729 ipv4_m->hdr.type_of_service >> 2);
7730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7732 ipv4_m->hdr.next_proto_id);
7733 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7734 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7735 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7736 ipv4_m->hdr.time_to_live);
7737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7738 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7739 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7740 !!(ipv4_m->hdr.fragment_offset));
7741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7742 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7746 * Add IPV6 item to matcher and to the value.
7748 * @param[in, out] matcher
7750 * @param[in, out] key
7751 * Flow matcher value.
7753 * Flow pattern to translate.
7755 * Item is inner pattern.
7757 * The group to insert the rule.
7760 flow_dv_translate_item_ipv6(void *matcher, void *key,
7761 const struct rte_flow_item *item,
7762 int inner, uint32_t group)
7764 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7765 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7766 const struct rte_flow_item_ipv6 nic_mask = {
7769 "\xff\xff\xff\xff\xff\xff\xff\xff"
7770 "\xff\xff\xff\xff\xff\xff\xff\xff",
7772 "\xff\xff\xff\xff\xff\xff\xff\xff"
7773 "\xff\xff\xff\xff\xff\xff\xff\xff",
7774 .vtc_flow = RTE_BE32(0xffffffff),
7781 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7782 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7791 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7793 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7795 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7797 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7799 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7804 size = sizeof(ipv6_m->hdr.dst_addr);
7805 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7806 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7807 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7808 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7809 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7810 for (i = 0; i < size; ++i)
7811 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7812 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7813 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7814 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7815 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7816 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7817 for (i = 0; i < size; ++i)
7818 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7820 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7821 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7822 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7823 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7824 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7825 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7828 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7830 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7833 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7835 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7839 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7841 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7842 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7844 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7845 ipv6_m->hdr.hop_limits);
7846 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7847 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7848 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7849 !!(ipv6_m->has_frag_ext));
7850 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7851 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7855 * Add IPV6 fragment extension item to matcher and to the value.
7857 * @param[in, out] matcher
7859 * @param[in, out] key
7860 * Flow matcher value.
7862 * Flow pattern to translate.
7864 * Item is inner pattern.
7867 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7868 const struct rte_flow_item *item,
7871 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7872 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7873 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7875 .next_header = 0xff,
7876 .frag_data = RTE_BE16(0xffff),
7883 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7885 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7887 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7889 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7891 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7892 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7893 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7894 if (!ipv6_frag_ext_v)
7896 if (!ipv6_frag_ext_m)
7897 ipv6_frag_ext_m = &nic_mask;
7898 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7899 ipv6_frag_ext_m->hdr.next_header);
7900 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7901 ipv6_frag_ext_v->hdr.next_header &
7902 ipv6_frag_ext_m->hdr.next_header);
7906 * Add TCP item to matcher and to the value.
7908 * @param[in, out] matcher
7910 * @param[in, out] key
7911 * Flow matcher value.
7913 * Flow pattern to translate.
7915 * Item is inner pattern.
7918 flow_dv_translate_item_tcp(void *matcher, void *key,
7919 const struct rte_flow_item *item,
7922 const struct rte_flow_item_tcp *tcp_m = item->mask;
7923 const struct rte_flow_item_tcp *tcp_v = item->spec;
7928 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7930 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7932 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7934 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7936 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7941 tcp_m = &rte_flow_item_tcp_mask;
7942 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7943 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7944 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7945 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7946 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7947 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7948 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7949 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7950 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7951 tcp_m->hdr.tcp_flags);
7952 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7953 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7957 * Add UDP item to matcher and to the value.
7959 * @param[in, out] matcher
7961 * @param[in, out] key
7962 * Flow matcher value.
7964 * Flow pattern to translate.
7966 * Item is inner pattern.
7969 flow_dv_translate_item_udp(void *matcher, void *key,
7970 const struct rte_flow_item *item,
7973 const struct rte_flow_item_udp *udp_m = item->mask;
7974 const struct rte_flow_item_udp *udp_v = item->spec;
7979 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7981 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7983 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7985 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7987 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7988 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7992 udp_m = &rte_flow_item_udp_mask;
7993 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7994 rte_be_to_cpu_16(udp_m->hdr.src_port));
7995 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7996 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7997 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7998 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7999 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8000 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8004 * Add GRE optional Key item to matcher and to the value.
8006 * @param[in, out] matcher
8008 * @param[in, out] key
8009 * Flow matcher value.
8011 * Flow pattern to translate.
8013 * Item is inner pattern.
8016 flow_dv_translate_item_gre_key(void *matcher, void *key,
8017 const struct rte_flow_item *item)
8019 const rte_be32_t *key_m = item->mask;
8020 const rte_be32_t *key_v = item->spec;
8021 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8022 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8023 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8025 /* GRE K bit must be on and should already be validated */
8026 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8027 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8031 key_m = &gre_key_default_mask;
8032 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8033 rte_be_to_cpu_32(*key_m) >> 8);
8034 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8035 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8036 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8037 rte_be_to_cpu_32(*key_m) & 0xFF);
8038 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8039 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8043 * Add GRE item to matcher and to the value.
8045 * @param[in, out] matcher
8047 * @param[in, out] key
8048 * Flow matcher value.
8050 * Flow pattern to translate.
8052 * Item is inner pattern.
8055 flow_dv_translate_item_gre(void *matcher, void *key,
8056 const struct rte_flow_item *item,
8059 const struct rte_flow_item_gre *gre_m = item->mask;
8060 const struct rte_flow_item_gre *gre_v = item->spec;
8063 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8064 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8071 uint16_t s_present:1;
8072 uint16_t k_present:1;
8073 uint16_t rsvd_bit1:1;
8074 uint16_t c_present:1;
8078 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8081 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8083 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8085 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8087 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8089 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8090 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8094 gre_m = &rte_flow_item_gre_mask;
8095 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8096 rte_be_to_cpu_16(gre_m->protocol));
8097 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8098 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8099 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8100 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8101 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8102 gre_crks_rsvd0_ver_m.c_present);
8103 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8104 gre_crks_rsvd0_ver_v.c_present &
8105 gre_crks_rsvd0_ver_m.c_present);
8106 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8107 gre_crks_rsvd0_ver_m.k_present);
8108 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8109 gre_crks_rsvd0_ver_v.k_present &
8110 gre_crks_rsvd0_ver_m.k_present);
8111 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8112 gre_crks_rsvd0_ver_m.s_present);
8113 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8114 gre_crks_rsvd0_ver_v.s_present &
8115 gre_crks_rsvd0_ver_m.s_present);
8119 * Add NVGRE item to matcher and to the value.
8121 * @param[in, out] matcher
8123 * @param[in, out] key
8124 * Flow matcher value.
8126 * Flow pattern to translate.
8128 * Item is inner pattern.
8131 flow_dv_translate_item_nvgre(void *matcher, void *key,
8132 const struct rte_flow_item *item,
8135 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8136 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8137 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8138 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8139 const char *tni_flow_id_m;
8140 const char *tni_flow_id_v;
8146 /* For NVGRE, GRE header fields must be set with defined values. */
8147 const struct rte_flow_item_gre gre_spec = {
8148 .c_rsvd0_ver = RTE_BE16(0x2000),
8149 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8151 const struct rte_flow_item_gre gre_mask = {
8152 .c_rsvd0_ver = RTE_BE16(0xB000),
8153 .protocol = RTE_BE16(UINT16_MAX),
8155 const struct rte_flow_item gre_item = {
8160 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8164 nvgre_m = &rte_flow_item_nvgre_mask;
8165 tni_flow_id_m = (const char *)nvgre_m->tni;
8166 tni_flow_id_v = (const char *)nvgre_v->tni;
8167 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8168 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8169 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8170 memcpy(gre_key_m, tni_flow_id_m, size);
8171 for (i = 0; i < size; ++i)
8172 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8176 * Add VXLAN item to matcher and to the value.
8178 * @param[in, out] matcher
8180 * @param[in, out] key
8181 * Flow matcher value.
8183 * Flow pattern to translate.
8185 * Item is inner pattern.
8188 flow_dv_translate_item_vxlan(void *matcher, void *key,
8189 const struct rte_flow_item *item,
8192 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8193 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8196 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8197 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8205 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8207 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8209 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8211 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8213 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8214 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8215 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8222 vxlan_m = &rte_flow_item_vxlan_mask;
8223 size = sizeof(vxlan_m->vni);
8224 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8225 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8226 memcpy(vni_m, vxlan_m->vni, size);
8227 for (i = 0; i < size; ++i)
8228 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8232 * Add VXLAN-GPE item to matcher and to the value.
8234 * @param[in, out] matcher
8236 * @param[in, out] key
8237 * Flow matcher value.
8239 * Flow pattern to translate.
8241 * Item is inner pattern.
8245 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8246 const struct rte_flow_item *item, int inner)
8248 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8249 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8253 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8255 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8261 uint8_t flags_m = 0xff;
8262 uint8_t flags_v = 0xc;
8265 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8267 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8269 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8271 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8273 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8274 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8275 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8276 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8277 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8282 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8283 size = sizeof(vxlan_m->vni);
8284 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8285 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8286 memcpy(vni_m, vxlan_m->vni, size);
8287 for (i = 0; i < size; ++i)
8288 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8289 if (vxlan_m->flags) {
8290 flags_m = vxlan_m->flags;
8291 flags_v = vxlan_v->flags;
8293 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8294 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8295 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8297 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8302 * Add Geneve item to matcher and to the value.
8304 * @param[in, out] matcher
8306 * @param[in, out] key
8307 * Flow matcher value.
8309 * Flow pattern to translate.
8311 * Item is inner pattern.
8315 flow_dv_translate_item_geneve(void *matcher, void *key,
8316 const struct rte_flow_item *item, int inner)
8318 const struct rte_flow_item_geneve *geneve_m = item->mask;
8319 const struct rte_flow_item_geneve *geneve_v = item->spec;
8322 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8323 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8332 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8334 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8336 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8338 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8340 dport = MLX5_UDP_PORT_GENEVE;
8341 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8342 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8348 geneve_m = &rte_flow_item_geneve_mask;
8349 size = sizeof(geneve_m->vni);
8350 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8351 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8352 memcpy(vni_m, geneve_m->vni, size);
8353 for (i = 0; i < size; ++i)
8354 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8355 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8356 rte_be_to_cpu_16(geneve_m->protocol));
8357 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8358 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8359 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8360 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8361 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8362 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8363 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8364 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8365 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8366 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8367 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8368 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8369 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8373 * Create Geneve TLV option resource.
8375 * @param dev[in, out]
8376 * Pointer to rte_eth_dev structure.
8377 * @param[in, out] tag_be24
8378 * Tag value in big endian then R-shift 8.
8379 * @parm[in, out] dev_flow
8380 * Pointer to the dev_flow.
8382 * pointer to error structure.
8385 * 0 on success otherwise -errno and errno is set.
8389 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8390 const struct rte_flow_item *item,
8391 struct rte_flow_error *error)
8393 struct mlx5_priv *priv = dev->data->dev_private;
8394 struct mlx5_dev_ctx_shared *sh = priv->sh;
8395 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8396 sh->geneve_tlv_option_resource;
8397 struct mlx5_devx_obj *obj;
8398 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8403 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8404 if (geneve_opt_resource != NULL) {
8405 if (geneve_opt_resource->option_class ==
8406 geneve_opt_v->option_class &&
8407 geneve_opt_resource->option_type ==
8408 geneve_opt_v->option_type &&
8409 geneve_opt_resource->length ==
8410 geneve_opt_v->option_len) {
8411 /* We already have GENVE TLV option obj allocated. */
8412 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8415 ret = rte_flow_error_set(error, ENOMEM,
8416 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8417 "Only one GENEVE TLV option supported");
8421 /* Create a GENEVE TLV object and resource. */
8422 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8423 geneve_opt_v->option_class,
8424 geneve_opt_v->option_type,
8425 geneve_opt_v->option_len);
8427 ret = rte_flow_error_set(error, ENODATA,
8428 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8429 "Failed to create GENEVE TLV Devx object");
8432 sh->geneve_tlv_option_resource =
8433 mlx5_malloc(MLX5_MEM_ZERO,
8434 sizeof(*geneve_opt_resource),
8436 if (!sh->geneve_tlv_option_resource) {
8437 claim_zero(mlx5_devx_cmd_destroy(obj));
8438 ret = rte_flow_error_set(error, ENOMEM,
8439 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8440 "GENEVE TLV object memory allocation failed");
8443 geneve_opt_resource = sh->geneve_tlv_option_resource;
8444 geneve_opt_resource->obj = obj;
8445 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8446 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8447 geneve_opt_resource->length = geneve_opt_v->option_len;
8448 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8452 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8457 * Add Geneve TLV option item to matcher.
8459 * @param[in, out] dev
8460 * Pointer to rte_eth_dev structure.
8461 * @param[in, out] matcher
8463 * @param[in, out] key
8464 * Flow matcher value.
8466 * Flow pattern to translate.
8468 * Pointer to error structure.
8471 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8472 void *key, const struct rte_flow_item *item,
8473 struct rte_flow_error *error)
8475 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8476 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8477 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8478 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8479 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8481 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8482 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8488 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8489 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8492 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8496 * Set the option length in GENEVE header if not requested.
8497 * The GENEVE TLV option length is expressed by the option length field
8498 * in the GENEVE header.
8499 * If the option length was not requested but the GENEVE TLV option item
8500 * is present we set the option length field implicitly.
8502 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8503 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8504 MLX5_GENEVE_OPTLEN_MASK);
8505 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8506 geneve_opt_v->option_len + 1);
8509 if (geneve_opt_v->data) {
8510 memcpy(&opt_data_key, geneve_opt_v->data,
8511 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8512 sizeof(opt_data_key)));
8513 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8514 sizeof(opt_data_key));
8515 memcpy(&opt_data_mask, geneve_opt_m->data,
8516 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8517 sizeof(opt_data_mask)));
8518 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8519 sizeof(opt_data_mask));
8520 MLX5_SET(fte_match_set_misc3, misc3_m,
8521 geneve_tlv_option_0_data,
8522 rte_be_to_cpu_32(opt_data_mask));
8523 MLX5_SET(fte_match_set_misc3, misc3_v,
8524 geneve_tlv_option_0_data,
8525 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8531 * Add MPLS item to matcher and to the value.
8533 * @param[in, out] matcher
8535 * @param[in, out] key
8536 * Flow matcher value.
8538 * Flow pattern to translate.
8539 * @param[in] prev_layer
8540 * The protocol layer indicated in previous item.
8542 * Item is inner pattern.
8545 flow_dv_translate_item_mpls(void *matcher, void *key,
8546 const struct rte_flow_item *item,
8547 uint64_t prev_layer,
8550 const uint32_t *in_mpls_m = item->mask;
8551 const uint32_t *in_mpls_v = item->spec;
8552 uint32_t *out_mpls_m = 0;
8553 uint32_t *out_mpls_v = 0;
8554 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8555 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8556 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8558 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8559 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8560 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8562 switch (prev_layer) {
8563 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8564 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8565 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8566 MLX5_UDP_PORT_MPLS);
8568 case MLX5_FLOW_LAYER_GRE:
8569 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8570 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8571 RTE_ETHER_TYPE_MPLS);
8574 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8582 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8583 switch (prev_layer) {
8584 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8586 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8587 outer_first_mpls_over_udp);
8589 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8590 outer_first_mpls_over_udp);
8592 case MLX5_FLOW_LAYER_GRE:
8594 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8595 outer_first_mpls_over_gre);
8597 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8598 outer_first_mpls_over_gre);
8601 /* Inner MPLS not over GRE is not supported. */
8604 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8608 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8614 if (out_mpls_m && out_mpls_v) {
8615 *out_mpls_m = *in_mpls_m;
8616 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8621 * Add metadata register item to matcher
8623 * @param[in, out] matcher
8625 * @param[in, out] key
8626 * Flow matcher value.
8627 * @param[in] reg_type
8628 * Type of device metadata register
8635 flow_dv_match_meta_reg(void *matcher, void *key,
8636 enum modify_reg reg_type,
8637 uint32_t data, uint32_t mask)
8640 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8642 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8648 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8649 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8652 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8653 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8657 * The metadata register C0 field might be divided into
8658 * source vport index and META item value, we should set
8659 * this field according to specified mask, not as whole one.
8661 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8663 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8664 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8667 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8670 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8671 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8674 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8675 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8678 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8679 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8682 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8683 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8686 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8687 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8690 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8691 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8694 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8695 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8704 * Add MARK item to matcher
8707 * The device to configure through.
8708 * @param[in, out] matcher
8710 * @param[in, out] key
8711 * Flow matcher value.
8713 * Flow pattern to translate.
8716 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8717 void *matcher, void *key,
8718 const struct rte_flow_item *item)
8720 struct mlx5_priv *priv = dev->data->dev_private;
8721 const struct rte_flow_item_mark *mark;
8725 mark = item->mask ? (const void *)item->mask :
8726 &rte_flow_item_mark_mask;
8727 mask = mark->id & priv->sh->dv_mark_mask;
8728 mark = (const void *)item->spec;
8730 value = mark->id & priv->sh->dv_mark_mask & mask;
8732 enum modify_reg reg;
8734 /* Get the metadata register index for the mark. */
8735 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8736 MLX5_ASSERT(reg > 0);
8737 if (reg == REG_C_0) {
8738 struct mlx5_priv *priv = dev->data->dev_private;
8739 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8740 uint32_t shl_c0 = rte_bsf32(msk_c0);
8746 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8751 * Add META item to matcher
8754 * The devich to configure through.
8755 * @param[in, out] matcher
8757 * @param[in, out] key
8758 * Flow matcher value.
8760 * Attributes of flow that includes this item.
8762 * Flow pattern to translate.
8765 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8766 void *matcher, void *key,
8767 const struct rte_flow_attr *attr,
8768 const struct rte_flow_item *item)
8770 const struct rte_flow_item_meta *meta_m;
8771 const struct rte_flow_item_meta *meta_v;
8773 meta_m = (const void *)item->mask;
8775 meta_m = &rte_flow_item_meta_mask;
8776 meta_v = (const void *)item->spec;
8779 uint32_t value = meta_v->data;
8780 uint32_t mask = meta_m->data;
8782 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8785 MLX5_ASSERT(reg != REG_NON);
8787 * In datapath code there is no endianness
8788 * coversions for perfromance reasons, all
8789 * pattern conversions are done in rte_flow.
8791 value = rte_cpu_to_be_32(value);
8792 mask = rte_cpu_to_be_32(mask);
8793 if (reg == REG_C_0) {
8794 struct mlx5_priv *priv = dev->data->dev_private;
8795 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8796 uint32_t shl_c0 = rte_bsf32(msk_c0);
8797 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8798 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8805 MLX5_ASSERT(msk_c0);
8806 MLX5_ASSERT(!(~msk_c0 & mask));
8808 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8813 * Add vport metadata Reg C0 item to matcher
8815 * @param[in, out] matcher
8817 * @param[in, out] key
8818 * Flow matcher value.
8820 * Flow pattern to translate.
8823 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8824 uint32_t value, uint32_t mask)
8826 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8830 * Add tag item to matcher
8833 * The devich to configure through.
8834 * @param[in, out] matcher
8836 * @param[in, out] key
8837 * Flow matcher value.
8839 * Flow pattern to translate.
8842 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8843 void *matcher, void *key,
8844 const struct rte_flow_item *item)
8846 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8847 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8848 uint32_t mask, value;
8851 value = tag_v->data;
8852 mask = tag_m ? tag_m->data : UINT32_MAX;
8853 if (tag_v->id == REG_C_0) {
8854 struct mlx5_priv *priv = dev->data->dev_private;
8855 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8856 uint32_t shl_c0 = rte_bsf32(msk_c0);
8862 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8866 * Add TAG item to matcher
8869 * The devich to configure through.
8870 * @param[in, out] matcher
8872 * @param[in, out] key
8873 * Flow matcher value.
8875 * Flow pattern to translate.
8878 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8879 void *matcher, void *key,
8880 const struct rte_flow_item *item)
8882 const struct rte_flow_item_tag *tag_v = item->spec;
8883 const struct rte_flow_item_tag *tag_m = item->mask;
8884 enum modify_reg reg;
8887 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8888 /* Get the metadata register index for the tag. */
8889 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8890 MLX5_ASSERT(reg > 0);
8891 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8895 * Add source vport match to the specified matcher.
8897 * @param[in, out] matcher
8899 * @param[in, out] key
8900 * Flow matcher value.
8902 * Source vport value to match
8907 flow_dv_translate_item_source_vport(void *matcher, void *key,
8908 int16_t port, uint16_t mask)
8910 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8911 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8913 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8914 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8918 * Translate port-id item to eswitch match on port-id.
8921 * The devich to configure through.
8922 * @param[in, out] matcher
8924 * @param[in, out] key
8925 * Flow matcher value.
8927 * Flow pattern to translate.
8932 * 0 on success, a negative errno value otherwise.
8935 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8936 void *key, const struct rte_flow_item *item,
8937 const struct rte_flow_attr *attr)
8939 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8940 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8941 struct mlx5_priv *priv;
8944 mask = pid_m ? pid_m->id : 0xffff;
8945 id = pid_v ? pid_v->id : dev->data->port_id;
8946 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8950 * Translate to vport field or to metadata, depending on mode.
8951 * Kernel can use either misc.source_port or half of C0 metadata
8954 if (priv->vport_meta_mask) {
8956 * Provide the hint for SW steering library
8957 * to insert the flow into ingress domain and
8958 * save the extra vport match.
8960 if (mask == 0xffff && priv->vport_id == 0xffff &&
8961 priv->pf_bond < 0 && attr->transfer)
8962 flow_dv_translate_item_source_vport
8963 (matcher, key, priv->vport_id, mask);
8965 * We should always set the vport metadata register,
8966 * otherwise the SW steering library can drop
8967 * the rule if wire vport metadata value is not zero,
8968 * it depends on kernel configuration.
8970 flow_dv_translate_item_meta_vport(matcher, key,
8971 priv->vport_meta_tag,
8972 priv->vport_meta_mask);
8974 flow_dv_translate_item_source_vport(matcher, key,
8975 priv->vport_id, mask);
8981 * Add ICMP6 item to matcher and to the value.
8983 * @param[in, out] matcher
8985 * @param[in, out] key
8986 * Flow matcher value.
8988 * Flow pattern to translate.
8990 * Item is inner pattern.
8993 flow_dv_translate_item_icmp6(void *matcher, void *key,
8994 const struct rte_flow_item *item,
8997 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8998 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9001 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9003 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9005 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9007 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9009 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9011 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9013 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9014 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9018 icmp6_m = &rte_flow_item_icmp6_mask;
9019 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9020 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9021 icmp6_v->type & icmp6_m->type);
9022 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9023 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9024 icmp6_v->code & icmp6_m->code);
9028 * Add ICMP item to matcher and to the value.
9030 * @param[in, out] matcher
9032 * @param[in, out] key
9033 * Flow matcher value.
9035 * Flow pattern to translate.
9037 * Item is inner pattern.
9040 flow_dv_translate_item_icmp(void *matcher, void *key,
9041 const struct rte_flow_item *item,
9044 const struct rte_flow_item_icmp *icmp_m = item->mask;
9045 const struct rte_flow_item_icmp *icmp_v = item->spec;
9046 uint32_t icmp_header_data_m = 0;
9047 uint32_t icmp_header_data_v = 0;
9050 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9052 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9054 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9056 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9058 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9060 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9062 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9063 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9067 icmp_m = &rte_flow_item_icmp_mask;
9068 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9069 icmp_m->hdr.icmp_type);
9070 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9071 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9072 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9073 icmp_m->hdr.icmp_code);
9074 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9075 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9076 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9077 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9078 if (icmp_header_data_m) {
9079 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9080 icmp_header_data_v |=
9081 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9082 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9083 icmp_header_data_m);
9084 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9085 icmp_header_data_v & icmp_header_data_m);
9090 * Add GTP item to matcher and to the value.
9092 * @param[in, out] matcher
9094 * @param[in, out] key
9095 * Flow matcher value.
9097 * Flow pattern to translate.
9099 * Item is inner pattern.
9102 flow_dv_translate_item_gtp(void *matcher, void *key,
9103 const struct rte_flow_item *item, int inner)
9105 const struct rte_flow_item_gtp *gtp_m = item->mask;
9106 const struct rte_flow_item_gtp *gtp_v = item->spec;
9109 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9111 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9112 uint16_t dport = RTE_GTPU_UDP_PORT;
9115 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9117 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9119 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9121 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9123 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9124 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9125 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9130 gtp_m = &rte_flow_item_gtp_mask;
9131 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9132 gtp_m->v_pt_rsv_flags);
9133 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9134 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9135 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9136 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9137 gtp_v->msg_type & gtp_m->msg_type);
9138 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9139 rte_be_to_cpu_32(gtp_m->teid));
9140 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9141 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9145 * Add GTP PSC item to matcher.
9147 * @param[in, out] matcher
9149 * @param[in, out] key
9150 * Flow matcher value.
9152 * Flow pattern to translate.
9155 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9156 const struct rte_flow_item *item)
9158 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9159 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9160 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9162 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9168 uint8_t next_ext_header_type;
9173 /* Always set E-flag match on one, regardless of GTP item settings. */
9174 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9175 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9176 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9177 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9178 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9179 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9180 /*Set next extension header type. */
9183 dw_2.next_ext_header_type = 0xff;
9184 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9185 rte_cpu_to_be_32(dw_2.w32));
9188 dw_2.next_ext_header_type = 0x85;
9189 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9190 rte_cpu_to_be_32(dw_2.w32));
9202 /*Set extension header PDU type and Qos. */
9204 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9206 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9207 dw_0.qfi = gtp_psc_m->qfi;
9208 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9209 rte_cpu_to_be_32(dw_0.w32));
9211 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9212 gtp_psc_m->pdu_type);
9213 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9214 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9215 rte_cpu_to_be_32(dw_0.w32));
9221 * Add eCPRI item to matcher and to the value.
9224 * The devich to configure through.
9225 * @param[in, out] matcher
9227 * @param[in, out] key
9228 * Flow matcher value.
9230 * Flow pattern to translate.
9231 * @param[in] samples
9232 * Sample IDs to be used in the matching.
9235 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9236 void *key, const struct rte_flow_item *item)
9238 struct mlx5_priv *priv = dev->data->dev_private;
9239 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9240 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9241 struct rte_ecpri_common_hdr common;
9242 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9244 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9252 ecpri_m = &rte_flow_item_ecpri_mask;
9254 * Maximal four DW samples are supported in a single matching now.
9255 * Two are used now for a eCPRI matching:
9256 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9257 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9260 if (!ecpri_m->hdr.common.u32)
9262 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9263 /* Need to take the whole DW as the mask to fill the entry. */
9264 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9265 prog_sample_field_value_0);
9266 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9267 prog_sample_field_value_0);
9268 /* Already big endian (network order) in the header. */
9269 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9270 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9271 /* Sample#0, used for matching type, offset 0. */
9272 MLX5_SET(fte_match_set_misc4, misc4_m,
9273 prog_sample_field_id_0, samples[0]);
9274 /* It makes no sense to set the sample ID in the mask field. */
9275 MLX5_SET(fte_match_set_misc4, misc4_v,
9276 prog_sample_field_id_0, samples[0]);
9278 * Checking if message body part needs to be matched.
9279 * Some wildcard rules only matching type field should be supported.
9281 if (ecpri_m->hdr.dummy[0]) {
9282 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9283 switch (common.type) {
9284 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9285 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9286 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9287 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9288 prog_sample_field_value_1);
9289 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9290 prog_sample_field_value_1);
9291 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9292 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9293 ecpri_m->hdr.dummy[0];
9294 /* Sample#1, to match message body, offset 4. */
9295 MLX5_SET(fte_match_set_misc4, misc4_m,
9296 prog_sample_field_id_1, samples[1]);
9297 MLX5_SET(fte_match_set_misc4, misc4_v,
9298 prog_sample_field_id_1, samples[1]);
9301 /* Others, do not match any sample ID. */
9307 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9309 #define HEADER_IS_ZERO(match_criteria, headers) \
9310 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9311 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9314 * Calculate flow matcher enable bitmap.
9316 * @param match_criteria
9317 * Pointer to flow matcher criteria.
9320 * Bitmap of enabled fields.
9323 flow_dv_matcher_enable(uint32_t *match_criteria)
9325 uint8_t match_criteria_enable;
9327 match_criteria_enable =
9328 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9329 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9330 match_criteria_enable |=
9331 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9332 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9333 match_criteria_enable |=
9334 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9335 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9336 match_criteria_enable |=
9337 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9338 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9339 match_criteria_enable |=
9340 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9341 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9342 match_criteria_enable |=
9343 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9344 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9345 return match_criteria_enable;
9348 struct mlx5_hlist_entry *
9349 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9351 struct mlx5_dev_ctx_shared *sh = list->ctx;
9352 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9353 struct rte_eth_dev *dev = ctx->dev;
9354 struct mlx5_flow_tbl_data_entry *tbl_data;
9355 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9356 struct rte_flow_error *error = ctx->error;
9357 union mlx5_flow_tbl_key key = { .v64 = key64 };
9358 struct mlx5_flow_tbl_resource *tbl;
9363 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9365 rte_flow_error_set(error, ENOMEM,
9366 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9368 "cannot allocate flow table data entry");
9371 tbl_data->idx = idx;
9372 tbl_data->tunnel = tt_prm->tunnel;
9373 tbl_data->group_id = tt_prm->group_id;
9374 tbl_data->external = !!tt_prm->external;
9375 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9376 tbl_data->is_egress = !!key.direction;
9377 tbl_data->is_transfer = !!key.domain;
9378 tbl_data->dummy = !!key.dummy;
9379 tbl_data->table_id = key.table_id;
9380 tbl = &tbl_data->tbl;
9382 return &tbl_data->entry;
9384 domain = sh->fdb_domain;
9385 else if (key.direction)
9386 domain = sh->tx_domain;
9388 domain = sh->rx_domain;
9389 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9391 rte_flow_error_set(error, ENOMEM,
9392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9393 NULL, "cannot create flow table object");
9394 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9398 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9399 (tbl->obj, &tbl_data->jump.action);
9401 rte_flow_error_set(error, ENOMEM,
9402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9404 "cannot create flow jump action");
9405 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9406 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9410 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9411 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9413 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9414 flow_dv_matcher_create_cb,
9415 flow_dv_matcher_match_cb,
9416 flow_dv_matcher_remove_cb);
9417 return &tbl_data->entry;
9421 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9422 struct mlx5_hlist_entry *entry, uint64_t key64,
9423 void *cb_ctx __rte_unused)
9425 struct mlx5_flow_tbl_data_entry *tbl_data =
9426 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9427 union mlx5_flow_tbl_key key = { .v64 = key64 };
9429 return tbl_data->table_id != key.table_id ||
9430 tbl_data->dummy != key.dummy ||
9431 tbl_data->is_transfer != key.domain ||
9432 tbl_data->is_egress != key.direction;
9438 * @param[in, out] dev
9439 * Pointer to rte_eth_dev structure.
9440 * @param[in] table_id
9443 * Direction of the table.
9444 * @param[in] transfer
9445 * E-Switch or NIC flow.
9447 * Dummy entry for dv API.
9449 * pointer to error structure.
9452 * Returns tables resource based on the index, NULL in case of failed.
9454 struct mlx5_flow_tbl_resource *
9455 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9456 uint32_t table_id, uint8_t egress,
9459 const struct mlx5_flow_tunnel *tunnel,
9460 uint32_t group_id, uint8_t dummy,
9461 struct rte_flow_error *error)
9463 struct mlx5_priv *priv = dev->data->dev_private;
9464 union mlx5_flow_tbl_key table_key = {
9466 .table_id = table_id,
9468 .domain = !!transfer,
9469 .direction = !!egress,
9472 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9474 .group_id = group_id,
9475 .external = external,
9477 struct mlx5_flow_cb_ctx ctx = {
9482 struct mlx5_hlist_entry *entry;
9483 struct mlx5_flow_tbl_data_entry *tbl_data;
9485 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9487 rte_flow_error_set(error, ENOMEM,
9488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9489 "cannot get table");
9492 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9493 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9494 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9495 return &tbl_data->tbl;
9499 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9500 struct mlx5_hlist_entry *entry)
9502 struct mlx5_dev_ctx_shared *sh = list->ctx;
9503 struct mlx5_flow_tbl_data_entry *tbl_data =
9504 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9506 MLX5_ASSERT(entry && sh);
9507 if (tbl_data->jump.action)
9508 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9509 if (tbl_data->tbl.obj)
9510 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9511 if (tbl_data->tunnel_offload && tbl_data->external) {
9512 struct mlx5_hlist_entry *he;
9513 struct mlx5_hlist *tunnel_grp_hash;
9514 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9515 union tunnel_tbl_key tunnel_key = {
9516 .tunnel_id = tbl_data->tunnel ?
9517 tbl_data->tunnel->tunnel_id : 0,
9518 .group = tbl_data->group_id
9520 uint32_t table_id = tbl_data->table_id;
9522 tunnel_grp_hash = tbl_data->tunnel ?
9523 tbl_data->tunnel->groups :
9525 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9527 mlx5_hlist_unregister(tunnel_grp_hash, he);
9529 "Table_id %u tunnel %u group %u released.",
9532 tbl_data->tunnel->tunnel_id : 0,
9533 tbl_data->group_id);
9535 mlx5_cache_list_destroy(&tbl_data->matchers);
9536 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9540 * Release a flow table.
9543 * Pointer to device shared structure.
9545 * Table resource to be released.
9548 * Returns 0 if table was released, else return 1;
9551 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9552 struct mlx5_flow_tbl_resource *tbl)
9554 struct mlx5_flow_tbl_data_entry *tbl_data =
9555 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9559 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9563 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9564 struct mlx5_cache_entry *entry, void *cb_ctx)
9566 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9567 struct mlx5_flow_dv_matcher *ref = ctx->data;
9568 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9571 return cur->crc != ref->crc ||
9572 cur->priority != ref->priority ||
9573 memcmp((const void *)cur->mask.buf,
9574 (const void *)ref->mask.buf, ref->mask.size);
9577 struct mlx5_cache_entry *
9578 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9579 struct mlx5_cache_entry *entry __rte_unused,
9582 struct mlx5_dev_ctx_shared *sh = list->ctx;
9583 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9584 struct mlx5_flow_dv_matcher *ref = ctx->data;
9585 struct mlx5_flow_dv_matcher *cache;
9586 struct mlx5dv_flow_matcher_attr dv_attr = {
9587 .type = IBV_FLOW_ATTR_NORMAL,
9588 .match_mask = (void *)&ref->mask,
9590 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9594 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9596 rte_flow_error_set(ctx->error, ENOMEM,
9597 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9598 "cannot create matcher");
9602 dv_attr.match_criteria_enable =
9603 flow_dv_matcher_enable(cache->mask.buf);
9604 dv_attr.priority = ref->priority;
9606 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9607 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9608 &cache->matcher_object);
9611 rte_flow_error_set(ctx->error, ENOMEM,
9612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9613 "cannot create matcher");
9616 return &cache->entry;
9620 * Register the flow matcher.
9622 * @param[in, out] dev
9623 * Pointer to rte_eth_dev structure.
9624 * @param[in, out] matcher
9625 * Pointer to flow matcher.
9626 * @param[in, out] key
9627 * Pointer to flow table key.
9628 * @parm[in, out] dev_flow
9629 * Pointer to the dev_flow.
9631 * pointer to error structure.
9634 * 0 on success otherwise -errno and errno is set.
9637 flow_dv_matcher_register(struct rte_eth_dev *dev,
9638 struct mlx5_flow_dv_matcher *ref,
9639 union mlx5_flow_tbl_key *key,
9640 struct mlx5_flow *dev_flow,
9641 const struct mlx5_flow_tunnel *tunnel,
9643 struct rte_flow_error *error)
9645 struct mlx5_cache_entry *entry;
9646 struct mlx5_flow_dv_matcher *cache;
9647 struct mlx5_flow_tbl_resource *tbl;
9648 struct mlx5_flow_tbl_data_entry *tbl_data;
9649 struct mlx5_flow_cb_ctx ctx = {
9655 * tunnel offload API requires this registration for cases when
9656 * tunnel match rule was inserted before tunnel set rule.
9658 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9659 key->direction, key->domain,
9660 dev_flow->external, tunnel,
9661 group_id, 0, error);
9663 return -rte_errno; /* No need to refill the error info */
9664 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9666 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9668 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9669 return rte_flow_error_set(error, ENOMEM,
9670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9671 "cannot allocate ref memory");
9673 cache = container_of(entry, typeof(*cache), entry);
9674 dev_flow->handle->dvh.matcher = cache;
9678 struct mlx5_hlist_entry *
9679 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9681 struct mlx5_dev_ctx_shared *sh = list->ctx;
9682 struct rte_flow_error *error = ctx;
9683 struct mlx5_flow_dv_tag_resource *entry;
9687 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9689 rte_flow_error_set(error, ENOMEM,
9690 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9691 "cannot allocate resource memory");
9695 entry->tag_id = key;
9696 ret = mlx5_flow_os_create_flow_action_tag(key,
9699 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9700 rte_flow_error_set(error, ENOMEM,
9701 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9702 NULL, "cannot create action");
9705 return &entry->entry;
9709 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9710 struct mlx5_hlist_entry *entry, uint64_t key,
9711 void *cb_ctx __rte_unused)
9713 struct mlx5_flow_dv_tag_resource *tag =
9714 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9716 return key != tag->tag_id;
9720 * Find existing tag resource or create and register a new one.
9722 * @param dev[in, out]
9723 * Pointer to rte_eth_dev structure.
9724 * @param[in, out] tag_be24
9725 * Tag value in big endian then R-shift 8.
9726 * @parm[in, out] dev_flow
9727 * Pointer to the dev_flow.
9729 * pointer to error structure.
9732 * 0 on success otherwise -errno and errno is set.
9735 flow_dv_tag_resource_register
9736 (struct rte_eth_dev *dev,
9738 struct mlx5_flow *dev_flow,
9739 struct rte_flow_error *error)
9741 struct mlx5_priv *priv = dev->data->dev_private;
9742 struct mlx5_flow_dv_tag_resource *cache_resource;
9743 struct mlx5_hlist_entry *entry;
9745 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9747 cache_resource = container_of
9748 (entry, struct mlx5_flow_dv_tag_resource, entry);
9749 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9750 dev_flow->dv.tag_resource = cache_resource;
9757 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9758 struct mlx5_hlist_entry *entry)
9760 struct mlx5_dev_ctx_shared *sh = list->ctx;
9761 struct mlx5_flow_dv_tag_resource *tag =
9762 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9764 MLX5_ASSERT(tag && sh && tag->action);
9765 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9766 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9767 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9774 * Pointer to Ethernet device.
9779 * 1 while a reference on it exists, 0 when freed.
9782 flow_dv_tag_release(struct rte_eth_dev *dev,
9785 struct mlx5_priv *priv = dev->data->dev_private;
9786 struct mlx5_flow_dv_tag_resource *tag;
9788 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9791 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9792 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9793 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9797 * Translate port ID action to vport.
9800 * Pointer to rte_eth_dev structure.
9802 * Pointer to the port ID action.
9803 * @param[out] dst_port_id
9804 * The target port ID.
9806 * Pointer to the error structure.
9809 * 0 on success, a negative errno value otherwise and rte_errno is set.
9812 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9813 const struct rte_flow_action *action,
9814 uint32_t *dst_port_id,
9815 struct rte_flow_error *error)
9818 struct mlx5_priv *priv;
9819 const struct rte_flow_action_port_id *conf =
9820 (const struct rte_flow_action_port_id *)action->conf;
9822 port = conf->original ? dev->data->port_id : conf->id;
9823 priv = mlx5_port_to_eswitch_info(port, false);
9825 return rte_flow_error_set(error, -rte_errno,
9826 RTE_FLOW_ERROR_TYPE_ACTION,
9828 "No eswitch info was found for port");
9829 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9831 * This parameter is transferred to
9832 * mlx5dv_dr_action_create_dest_ib_port().
9834 *dst_port_id = priv->dev_port;
9837 * Legacy mode, no LAG configurations is supported.
9838 * This parameter is transferred to
9839 * mlx5dv_dr_action_create_dest_vport().
9841 *dst_port_id = priv->vport_id;
9847 * Create a counter with aging configuration.
9850 * Pointer to rte_eth_dev structure.
9852 * Pointer to the counter action configuration.
9854 * Pointer to the aging action configuration.
9857 * Index to flow counter on success, 0 otherwise.
9860 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9861 struct mlx5_flow *dev_flow,
9862 const struct rte_flow_action_count *count,
9863 const struct rte_flow_action_age *age)
9866 struct mlx5_age_param *age_param;
9868 if (count && count->shared)
9869 counter = flow_dv_counter_get_shared(dev, count->id);
9871 counter = flow_dv_counter_alloc(dev, !!age);
9872 if (!counter || age == NULL)
9874 age_param = flow_dv_counter_idx_get_age(dev, counter);
9875 age_param->context = age->context ? age->context :
9876 (void *)(uintptr_t)(dev_flow->flow_idx);
9877 age_param->timeout = age->timeout;
9878 age_param->port_id = dev->data->port_id;
9879 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9880 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9885 * Add Tx queue matcher
9888 * Pointer to the dev struct.
9889 * @param[in, out] matcher
9891 * @param[in, out] key
9892 * Flow matcher value.
9894 * Flow pattern to translate.
9896 * Item is inner pattern.
9899 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9900 void *matcher, void *key,
9901 const struct rte_flow_item *item)
9903 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9904 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9906 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9908 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9909 struct mlx5_txq_ctrl *txq;
9913 queue_m = (const void *)item->mask;
9916 queue_v = (const void *)item->spec;
9919 txq = mlx5_txq_get(dev, queue_v->queue);
9922 queue = txq->obj->sq->id;
9923 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9924 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9925 queue & queue_m->queue);
9926 mlx5_txq_release(dev, queue_v->queue);
9930 * Set the hash fields according to the @p flow information.
9932 * @param[in] dev_flow
9933 * Pointer to the mlx5_flow.
9934 * @param[in] rss_desc
9935 * Pointer to the mlx5_flow_rss_desc.
9938 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9939 struct mlx5_flow_rss_desc *rss_desc)
9941 uint64_t items = dev_flow->handle->layers;
9943 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9945 dev_flow->hash_fields = 0;
9946 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9947 if (rss_desc->level >= 2) {
9948 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9952 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9953 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9954 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9955 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9956 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9957 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9958 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9960 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9962 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9963 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9964 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9965 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9966 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9967 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9968 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9970 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9973 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9974 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9975 if (rss_types & ETH_RSS_UDP) {
9976 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9977 dev_flow->hash_fields |=
9978 IBV_RX_HASH_SRC_PORT_UDP;
9979 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9980 dev_flow->hash_fields |=
9981 IBV_RX_HASH_DST_PORT_UDP;
9983 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9985 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9986 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9987 if (rss_types & ETH_RSS_TCP) {
9988 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9989 dev_flow->hash_fields |=
9990 IBV_RX_HASH_SRC_PORT_TCP;
9991 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9992 dev_flow->hash_fields |=
9993 IBV_RX_HASH_DST_PORT_TCP;
9995 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10001 * Prepare an Rx Hash queue.
10004 * Pointer to Ethernet device.
10005 * @param[in] dev_flow
10006 * Pointer to the mlx5_flow.
10007 * @param[in] rss_desc
10008 * Pointer to the mlx5_flow_rss_desc.
10009 * @param[out] hrxq_idx
10010 * Hash Rx queue index.
10013 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10015 static struct mlx5_hrxq *
10016 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10017 struct mlx5_flow *dev_flow,
10018 struct mlx5_flow_rss_desc *rss_desc,
10019 uint32_t *hrxq_idx)
10021 struct mlx5_priv *priv = dev->data->dev_private;
10022 struct mlx5_flow_handle *dh = dev_flow->handle;
10023 struct mlx5_hrxq *hrxq;
10025 MLX5_ASSERT(rss_desc->queue_num);
10026 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10027 rss_desc->hash_fields = dev_flow->hash_fields;
10028 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10029 rss_desc->shared_rss = 0;
10030 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10033 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10039 * Release sample sub action resource.
10041 * @param[in, out] dev
10042 * Pointer to rte_eth_dev structure.
10043 * @param[in] act_res
10044 * Pointer to sample sub action resource.
10047 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10048 struct mlx5_flow_sub_actions_idx *act_res)
10050 if (act_res->rix_hrxq) {
10051 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10052 act_res->rix_hrxq = 0;
10054 if (act_res->rix_encap_decap) {
10055 flow_dv_encap_decap_resource_release(dev,
10056 act_res->rix_encap_decap);
10057 act_res->rix_encap_decap = 0;
10059 if (act_res->rix_port_id_action) {
10060 flow_dv_port_id_action_resource_release(dev,
10061 act_res->rix_port_id_action);
10062 act_res->rix_port_id_action = 0;
10064 if (act_res->rix_tag) {
10065 flow_dv_tag_release(dev, act_res->rix_tag);
10066 act_res->rix_tag = 0;
10068 if (act_res->rix_jump) {
10069 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10070 act_res->rix_jump = 0;
10075 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10076 struct mlx5_cache_entry *entry, void *cb_ctx)
10078 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10079 struct rte_eth_dev *dev = ctx->dev;
10080 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10081 struct mlx5_flow_dv_sample_resource *cache_resource =
10082 container_of(entry, typeof(*cache_resource), entry);
10084 if (resource->ratio == cache_resource->ratio &&
10085 resource->ft_type == cache_resource->ft_type &&
10086 resource->ft_id == cache_resource->ft_id &&
10087 resource->set_action == cache_resource->set_action &&
10088 !memcmp((void *)&resource->sample_act,
10089 (void *)&cache_resource->sample_act,
10090 sizeof(struct mlx5_flow_sub_actions_list))) {
10092 * Existing sample action should release the prepared
10093 * sub-actions reference counter.
10095 flow_dv_sample_sub_actions_release(dev,
10096 &resource->sample_idx);
10102 struct mlx5_cache_entry *
10103 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10104 struct mlx5_cache_entry *entry __rte_unused,
10107 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10108 struct rte_eth_dev *dev = ctx->dev;
10109 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10110 void **sample_dv_actions = resource->sub_actions;
10111 struct mlx5_flow_dv_sample_resource *cache_resource;
10112 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10113 struct mlx5_priv *priv = dev->data->dev_private;
10114 struct mlx5_dev_ctx_shared *sh = priv->sh;
10115 struct mlx5_flow_tbl_resource *tbl;
10117 const uint32_t next_ft_step = 1;
10118 uint32_t next_ft_id = resource->ft_id + next_ft_step;
10119 uint8_t is_egress = 0;
10120 uint8_t is_transfer = 0;
10121 struct rte_flow_error *error = ctx->error;
10123 /* Register new sample resource. */
10124 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10125 if (!cache_resource) {
10126 rte_flow_error_set(error, ENOMEM,
10127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10129 "cannot allocate resource memory");
10132 *cache_resource = *resource;
10133 /* Create normal path table level */
10134 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10136 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10138 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10139 is_egress, is_transfer,
10140 true, NULL, 0, 0, error);
10142 rte_flow_error_set(error, ENOMEM,
10143 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10145 "fail to create normal path table "
10149 cache_resource->normal_path_tbl = tbl;
10150 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10151 if (!sh->default_miss_action) {
10152 rte_flow_error_set(error, ENOMEM,
10153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10155 "default miss action was not "
10159 sample_dv_actions[resource->sample_act.actions_num++] =
10160 sh->default_miss_action;
10162 /* Create a DR sample action */
10163 sampler_attr.sample_ratio = cache_resource->ratio;
10164 sampler_attr.default_next_table = tbl->obj;
10165 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10166 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10167 &sample_dv_actions[0];
10168 sampler_attr.action = cache_resource->set_action;
10169 if (mlx5_os_flow_dr_create_flow_action_sampler
10170 (&sampler_attr, &cache_resource->verbs_action)) {
10171 rte_flow_error_set(error, ENOMEM,
10172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10173 NULL, "cannot create sample action");
10176 cache_resource->idx = idx;
10177 cache_resource->dev = dev;
10178 return &cache_resource->entry;
10180 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10181 flow_dv_sample_sub_actions_release(dev,
10182 &cache_resource->sample_idx);
10183 if (cache_resource->normal_path_tbl)
10184 flow_dv_tbl_resource_release(MLX5_SH(dev),
10185 cache_resource->normal_path_tbl);
10186 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10192 * Find existing sample resource or create and register a new one.
10194 * @param[in, out] dev
10195 * Pointer to rte_eth_dev structure.
10196 * @param[in] resource
10197 * Pointer to sample resource.
10198 * @parm[in, out] dev_flow
10199 * Pointer to the dev_flow.
10200 * @param[out] error
10201 * pointer to error structure.
10204 * 0 on success otherwise -errno and errno is set.
10207 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10208 struct mlx5_flow_dv_sample_resource *resource,
10209 struct mlx5_flow *dev_flow,
10210 struct rte_flow_error *error)
10212 struct mlx5_flow_dv_sample_resource *cache_resource;
10213 struct mlx5_cache_entry *entry;
10214 struct mlx5_priv *priv = dev->data->dev_private;
10215 struct mlx5_flow_cb_ctx ctx = {
10221 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10224 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10225 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10226 dev_flow->dv.sample_res = cache_resource;
10231 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10232 struct mlx5_cache_entry *entry, void *cb_ctx)
10234 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10235 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10236 struct rte_eth_dev *dev = ctx->dev;
10237 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10238 container_of(entry, typeof(*cache_resource), entry);
10241 if (resource->num_of_dest == cache_resource->num_of_dest &&
10242 resource->ft_type == cache_resource->ft_type &&
10243 !memcmp((void *)cache_resource->sample_act,
10244 (void *)resource->sample_act,
10245 (resource->num_of_dest *
10246 sizeof(struct mlx5_flow_sub_actions_list)))) {
10248 * Existing sample action should release the prepared
10249 * sub-actions reference counter.
10251 for (idx = 0; idx < resource->num_of_dest; idx++)
10252 flow_dv_sample_sub_actions_release(dev,
10253 &resource->sample_idx[idx]);
10259 struct mlx5_cache_entry *
10260 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10261 struct mlx5_cache_entry *entry __rte_unused,
10264 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10265 struct rte_eth_dev *dev = ctx->dev;
10266 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10267 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10268 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10269 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10270 struct mlx5_priv *priv = dev->data->dev_private;
10271 struct mlx5_dev_ctx_shared *sh = priv->sh;
10272 struct mlx5_flow_sub_actions_list *sample_act;
10273 struct mlx5dv_dr_domain *domain;
10274 uint32_t idx = 0, res_idx = 0;
10275 struct rte_flow_error *error = ctx->error;
10276 uint64_t action_flags;
10279 /* Register new destination array resource. */
10280 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10282 if (!cache_resource) {
10283 rte_flow_error_set(error, ENOMEM,
10284 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10286 "cannot allocate resource memory");
10289 *cache_resource = *resource;
10290 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10291 domain = sh->fdb_domain;
10292 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10293 domain = sh->rx_domain;
10295 domain = sh->tx_domain;
10296 for (idx = 0; idx < resource->num_of_dest; idx++) {
10297 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10298 mlx5_malloc(MLX5_MEM_ZERO,
10299 sizeof(struct mlx5dv_dr_action_dest_attr),
10301 if (!dest_attr[idx]) {
10302 rte_flow_error_set(error, ENOMEM,
10303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10305 "cannot allocate resource memory");
10308 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10309 sample_act = &resource->sample_act[idx];
10310 action_flags = sample_act->action_flags;
10311 switch (action_flags) {
10312 case MLX5_FLOW_ACTION_QUEUE:
10313 dest_attr[idx]->dest = sample_act->dr_queue_action;
10315 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10316 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10317 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10318 dest_attr[idx]->dest_reformat->reformat =
10319 sample_act->dr_encap_action;
10320 dest_attr[idx]->dest_reformat->dest =
10321 sample_act->dr_port_id_action;
10323 case MLX5_FLOW_ACTION_PORT_ID:
10324 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10326 case MLX5_FLOW_ACTION_JUMP:
10327 dest_attr[idx]->dest = sample_act->dr_jump_action;
10330 rte_flow_error_set(error, EINVAL,
10331 RTE_FLOW_ERROR_TYPE_ACTION,
10333 "unsupported actions type");
10337 /* create a dest array actioin */
10338 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10340 cache_resource->num_of_dest,
10342 &cache_resource->action);
10344 rte_flow_error_set(error, ENOMEM,
10345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10347 "cannot create destination array action");
10350 cache_resource->idx = res_idx;
10351 cache_resource->dev = dev;
10352 for (idx = 0; idx < resource->num_of_dest; idx++)
10353 mlx5_free(dest_attr[idx]);
10354 return &cache_resource->entry;
10356 for (idx = 0; idx < resource->num_of_dest; idx++) {
10357 flow_dv_sample_sub_actions_release(dev,
10358 &cache_resource->sample_idx[idx]);
10359 if (dest_attr[idx])
10360 mlx5_free(dest_attr[idx]);
10363 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10368 * Find existing destination array resource or create and register a new one.
10370 * @param[in, out] dev
10371 * Pointer to rte_eth_dev structure.
10372 * @param[in] resource
10373 * Pointer to destination array resource.
10374 * @parm[in, out] dev_flow
10375 * Pointer to the dev_flow.
10376 * @param[out] error
10377 * pointer to error structure.
10380 * 0 on success otherwise -errno and errno is set.
10383 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10384 struct mlx5_flow_dv_dest_array_resource *resource,
10385 struct mlx5_flow *dev_flow,
10386 struct rte_flow_error *error)
10388 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10389 struct mlx5_priv *priv = dev->data->dev_private;
10390 struct mlx5_cache_entry *entry;
10391 struct mlx5_flow_cb_ctx ctx = {
10397 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10400 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10401 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10402 dev_flow->dv.dest_array_res = cache_resource;
10407 * Convert Sample action to DV specification.
10410 * Pointer to rte_eth_dev structure.
10411 * @param[in] action
10412 * Pointer to sample action structure.
10413 * @param[in, out] dev_flow
10414 * Pointer to the mlx5_flow.
10416 * Pointer to the flow attributes.
10417 * @param[in, out] num_of_dest
10418 * Pointer to the num of destination.
10419 * @param[in, out] sample_actions
10420 * Pointer to sample actions list.
10421 * @param[in, out] res
10422 * Pointer to sample resource.
10423 * @param[out] error
10424 * Pointer to the error structure.
10427 * 0 on success, a negative errno value otherwise and rte_errno is set.
10430 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10431 const struct rte_flow_action_sample *action,
10432 struct mlx5_flow *dev_flow,
10433 const struct rte_flow_attr *attr,
10434 uint32_t *num_of_dest,
10435 void **sample_actions,
10436 struct mlx5_flow_dv_sample_resource *res,
10437 struct rte_flow_error *error)
10439 struct mlx5_priv *priv = dev->data->dev_private;
10440 const struct rte_flow_action *sub_actions;
10441 struct mlx5_flow_sub_actions_list *sample_act;
10442 struct mlx5_flow_sub_actions_idx *sample_idx;
10443 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10444 struct rte_flow *flow = dev_flow->flow;
10445 struct mlx5_flow_rss_desc *rss_desc;
10446 uint64_t action_flags = 0;
10449 rss_desc = &wks->rss_desc;
10450 sample_act = &res->sample_act;
10451 sample_idx = &res->sample_idx;
10452 res->ratio = action->ratio;
10453 sub_actions = action->actions;
10454 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10455 int type = sub_actions->type;
10456 uint32_t pre_rix = 0;
10459 case RTE_FLOW_ACTION_TYPE_QUEUE:
10461 const struct rte_flow_action_queue *queue;
10462 struct mlx5_hrxq *hrxq;
10465 queue = sub_actions->conf;
10466 rss_desc->queue_num = 1;
10467 rss_desc->queue[0] = queue->index;
10468 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10469 rss_desc, &hrxq_idx);
10471 return rte_flow_error_set
10473 RTE_FLOW_ERROR_TYPE_ACTION,
10475 "cannot create fate queue");
10476 sample_act->dr_queue_action = hrxq->action;
10477 sample_idx->rix_hrxq = hrxq_idx;
10478 sample_actions[sample_act->actions_num++] =
10481 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10482 if (action_flags & MLX5_FLOW_ACTION_MARK)
10483 dev_flow->handle->rix_hrxq = hrxq_idx;
10484 dev_flow->handle->fate_action =
10485 MLX5_FLOW_FATE_QUEUE;
10488 case RTE_FLOW_ACTION_TYPE_RSS:
10490 struct mlx5_hrxq *hrxq;
10492 const struct rte_flow_action_rss *rss;
10493 const uint8_t *rss_key;
10495 rss = sub_actions->conf;
10496 memcpy(rss_desc->queue, rss->queue,
10497 rss->queue_num * sizeof(uint16_t));
10498 rss_desc->queue_num = rss->queue_num;
10499 /* NULL RSS key indicates default RSS key. */
10500 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10501 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10503 * rss->level and rss.types should be set in advance
10504 * when expanding items for RSS.
10506 flow_dv_hashfields_set(dev_flow, rss_desc);
10507 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10508 rss_desc, &hrxq_idx);
10510 return rte_flow_error_set
10512 RTE_FLOW_ERROR_TYPE_ACTION,
10514 "cannot create fate queue");
10515 sample_act->dr_queue_action = hrxq->action;
10516 sample_idx->rix_hrxq = hrxq_idx;
10517 sample_actions[sample_act->actions_num++] =
10520 action_flags |= MLX5_FLOW_ACTION_RSS;
10521 if (action_flags & MLX5_FLOW_ACTION_MARK)
10522 dev_flow->handle->rix_hrxq = hrxq_idx;
10523 dev_flow->handle->fate_action =
10524 MLX5_FLOW_FATE_QUEUE;
10527 case RTE_FLOW_ACTION_TYPE_MARK:
10529 uint32_t tag_be = mlx5_flow_mark_set
10530 (((const struct rte_flow_action_mark *)
10531 (sub_actions->conf))->id);
10533 dev_flow->handle->mark = 1;
10534 pre_rix = dev_flow->handle->dvh.rix_tag;
10535 /* Save the mark resource before sample */
10536 pre_r = dev_flow->dv.tag_resource;
10537 if (flow_dv_tag_resource_register(dev, tag_be,
10540 MLX5_ASSERT(dev_flow->dv.tag_resource);
10541 sample_act->dr_tag_action =
10542 dev_flow->dv.tag_resource->action;
10543 sample_idx->rix_tag =
10544 dev_flow->handle->dvh.rix_tag;
10545 sample_actions[sample_act->actions_num++] =
10546 sample_act->dr_tag_action;
10547 /* Recover the mark resource after sample */
10548 dev_flow->dv.tag_resource = pre_r;
10549 dev_flow->handle->dvh.rix_tag = pre_rix;
10550 action_flags |= MLX5_FLOW_ACTION_MARK;
10553 case RTE_FLOW_ACTION_TYPE_COUNT:
10555 if (!flow->counter) {
10557 flow_dv_translate_create_counter(dev,
10558 dev_flow, sub_actions->conf,
10560 if (!flow->counter)
10561 return rte_flow_error_set
10563 RTE_FLOW_ERROR_TYPE_ACTION,
10565 "cannot create counter"
10568 sample_act->dr_cnt_action =
10569 (flow_dv_counter_get_by_idx(dev,
10570 flow->counter, NULL))->action;
10571 sample_actions[sample_act->actions_num++] =
10572 sample_act->dr_cnt_action;
10573 action_flags |= MLX5_FLOW_ACTION_COUNT;
10576 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10578 struct mlx5_flow_dv_port_id_action_resource
10580 uint32_t port_id = 0;
10582 memset(&port_id_resource, 0, sizeof(port_id_resource));
10583 /* Save the port id resource before sample */
10584 pre_rix = dev_flow->handle->rix_port_id_action;
10585 pre_r = dev_flow->dv.port_id_action;
10586 if (flow_dv_translate_action_port_id(dev, sub_actions,
10589 port_id_resource.port_id = port_id;
10590 if (flow_dv_port_id_action_resource_register
10591 (dev, &port_id_resource, dev_flow, error))
10593 sample_act->dr_port_id_action =
10594 dev_flow->dv.port_id_action->action;
10595 sample_idx->rix_port_id_action =
10596 dev_flow->handle->rix_port_id_action;
10597 sample_actions[sample_act->actions_num++] =
10598 sample_act->dr_port_id_action;
10599 /* Recover the port id resource after sample */
10600 dev_flow->dv.port_id_action = pre_r;
10601 dev_flow->handle->rix_port_id_action = pre_rix;
10603 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10606 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10607 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10608 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10609 /* Save the encap resource before sample */
10610 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10611 pre_r = dev_flow->dv.encap_decap;
10612 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10617 sample_act->dr_encap_action =
10618 dev_flow->dv.encap_decap->action;
10619 sample_idx->rix_encap_decap =
10620 dev_flow->handle->dvh.rix_encap_decap;
10621 sample_actions[sample_act->actions_num++] =
10622 sample_act->dr_encap_action;
10623 /* Recover the encap resource after sample */
10624 dev_flow->dv.encap_decap = pre_r;
10625 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10626 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10629 return rte_flow_error_set(error, EINVAL,
10630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10632 "Not support for sampler action");
10635 sample_act->action_flags = action_flags;
10636 res->ft_id = dev_flow->dv.group;
10637 if (attr->transfer) {
10639 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10640 uint64_t set_action;
10641 } action_ctx = { .set_action = 0 };
10643 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10644 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10645 MLX5_MODIFICATION_TYPE_SET);
10646 MLX5_SET(set_action_in, action_ctx.action_in, field,
10647 MLX5_MODI_META_REG_C_0);
10648 MLX5_SET(set_action_in, action_ctx.action_in, data,
10649 priv->vport_meta_tag);
10650 res->set_action = action_ctx.set_action;
10651 } else if (attr->ingress) {
10652 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10654 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10660 * Convert Sample action to DV specification.
10663 * Pointer to rte_eth_dev structure.
10664 * @param[in, out] dev_flow
10665 * Pointer to the mlx5_flow.
10666 * @param[in] num_of_dest
10667 * The num of destination.
10668 * @param[in, out] res
10669 * Pointer to sample resource.
10670 * @param[in, out] mdest_res
10671 * Pointer to destination array resource.
10672 * @param[in] sample_actions
10673 * Pointer to sample path actions list.
10674 * @param[in] action_flags
10675 * Holds the actions detected until now.
10676 * @param[out] error
10677 * Pointer to the error structure.
10680 * 0 on success, a negative errno value otherwise and rte_errno is set.
10683 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10684 struct mlx5_flow *dev_flow,
10685 uint32_t num_of_dest,
10686 struct mlx5_flow_dv_sample_resource *res,
10687 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10688 void **sample_actions,
10689 uint64_t action_flags,
10690 struct rte_flow_error *error)
10692 /* update normal path action resource into last index of array */
10693 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10694 struct mlx5_flow_sub_actions_list *sample_act =
10695 &mdest_res->sample_act[dest_index];
10696 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10697 struct mlx5_flow_rss_desc *rss_desc;
10698 uint32_t normal_idx = 0;
10699 struct mlx5_hrxq *hrxq;
10703 rss_desc = &wks->rss_desc;
10704 if (num_of_dest > 1) {
10705 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10706 /* Handle QP action for mirroring */
10707 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10708 rss_desc, &hrxq_idx);
10710 return rte_flow_error_set
10712 RTE_FLOW_ERROR_TYPE_ACTION,
10714 "cannot create rx queue");
10716 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10717 sample_act->dr_queue_action = hrxq->action;
10718 if (action_flags & MLX5_FLOW_ACTION_MARK)
10719 dev_flow->handle->rix_hrxq = hrxq_idx;
10720 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10722 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10724 mdest_res->sample_idx[dest_index].rix_encap_decap =
10725 dev_flow->handle->dvh.rix_encap_decap;
10726 sample_act->dr_encap_action =
10727 dev_flow->dv.encap_decap->action;
10728 dev_flow->handle->dvh.rix_encap_decap = 0;
10730 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10732 mdest_res->sample_idx[dest_index].rix_port_id_action =
10733 dev_flow->handle->rix_port_id_action;
10734 sample_act->dr_port_id_action =
10735 dev_flow->dv.port_id_action->action;
10736 dev_flow->handle->rix_port_id_action = 0;
10738 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10740 mdest_res->sample_idx[dest_index].rix_jump =
10741 dev_flow->handle->rix_jump;
10742 sample_act->dr_jump_action =
10743 dev_flow->dv.jump->action;
10744 dev_flow->handle->rix_jump = 0;
10746 sample_act->actions_num = normal_idx;
10747 /* update sample action resource into first index of array */
10748 mdest_res->ft_type = res->ft_type;
10749 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10750 sizeof(struct mlx5_flow_sub_actions_idx));
10751 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10752 sizeof(struct mlx5_flow_sub_actions_list));
10753 mdest_res->num_of_dest = num_of_dest;
10754 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10756 return rte_flow_error_set(error, EINVAL,
10757 RTE_FLOW_ERROR_TYPE_ACTION,
10758 NULL, "can't create sample "
10761 res->sub_actions = sample_actions;
10762 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10763 return rte_flow_error_set(error, EINVAL,
10764 RTE_FLOW_ERROR_TYPE_ACTION,
10766 "can't create sample action");
10772 * Remove an ASO age action from age actions list.
10775 * Pointer to the Ethernet device structure.
10777 * Pointer to the aso age action handler.
10780 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10781 struct mlx5_aso_age_action *age)
10783 struct mlx5_age_info *age_info;
10784 struct mlx5_age_param *age_param = &age->age_params;
10785 struct mlx5_priv *priv = dev->data->dev_private;
10786 uint16_t expected = AGE_CANDIDATE;
10788 age_info = GET_PORT_AGE_INFO(priv);
10789 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10790 AGE_FREE, false, __ATOMIC_RELAXED,
10791 __ATOMIC_RELAXED)) {
10793 * We need the lock even it is age timeout,
10794 * since age action may still in process.
10796 rte_spinlock_lock(&age_info->aged_sl);
10797 LIST_REMOVE(age, next);
10798 rte_spinlock_unlock(&age_info->aged_sl);
10799 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10804 * Release an ASO age action.
10807 * Pointer to the Ethernet device structure.
10808 * @param[in] age_idx
10809 * Index of ASO age action to release.
10811 * True if the release operation is during flow destroy operation.
10812 * False if the release operation is during action destroy operation.
10815 * 0 when age action was removed, otherwise the number of references.
10818 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10820 struct mlx5_priv *priv = dev->data->dev_private;
10821 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10822 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10823 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10826 flow_dv_aso_age_remove_from_age(dev, age);
10827 rte_spinlock_lock(&mng->free_sl);
10828 LIST_INSERT_HEAD(&mng->free, age, next);
10829 rte_spinlock_unlock(&mng->free_sl);
10835 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10838 * Pointer to the Ethernet device structure.
10841 * 0 on success, otherwise negative errno value and rte_errno is set.
10844 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10846 struct mlx5_priv *priv = dev->data->dev_private;
10847 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10848 void *old_pools = mng->pools;
10849 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10850 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10851 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10854 rte_errno = ENOMEM;
10858 memcpy(pools, old_pools,
10859 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10860 mlx5_free(old_pools);
10862 /* First ASO flow hit allocation - starting ASO data-path. */
10863 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
10871 mng->pools = pools;
10876 * Create and initialize a new ASO aging pool.
10879 * Pointer to the Ethernet device structure.
10880 * @param[out] age_free
10881 * Where to put the pointer of a new age action.
10884 * The age actions pool pointer and @p age_free is set on success,
10885 * NULL otherwise and rte_errno is set.
10887 static struct mlx5_aso_age_pool *
10888 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10889 struct mlx5_aso_age_action **age_free)
10891 struct mlx5_priv *priv = dev->data->dev_private;
10892 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10893 struct mlx5_aso_age_pool *pool = NULL;
10894 struct mlx5_devx_obj *obj = NULL;
10897 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10900 rte_errno = ENODATA;
10901 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10904 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10906 claim_zero(mlx5_devx_cmd_destroy(obj));
10907 rte_errno = ENOMEM;
10910 pool->flow_hit_aso_obj = obj;
10911 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10912 rte_spinlock_lock(&mng->resize_sl);
10913 pool->index = mng->next;
10914 /* Resize pools array if there is no room for the new pool in it. */
10915 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10916 claim_zero(mlx5_devx_cmd_destroy(obj));
10918 rte_spinlock_unlock(&mng->resize_sl);
10921 mng->pools[pool->index] = pool;
10923 rte_spinlock_unlock(&mng->resize_sl);
10924 /* Assign the first action in the new pool, the rest go to free list. */
10925 *age_free = &pool->actions[0];
10926 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10927 pool->actions[i].offset = i;
10928 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10934 * Allocate a ASO aging bit.
10937 * Pointer to the Ethernet device structure.
10938 * @param[out] error
10939 * Pointer to the error structure.
10942 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10945 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10947 struct mlx5_priv *priv = dev->data->dev_private;
10948 const struct mlx5_aso_age_pool *pool;
10949 struct mlx5_aso_age_action *age_free = NULL;
10950 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10953 /* Try to get the next free age action bit. */
10954 rte_spinlock_lock(&mng->free_sl);
10955 age_free = LIST_FIRST(&mng->free);
10957 LIST_REMOVE(age_free, next);
10958 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10959 rte_spinlock_unlock(&mng->free_sl);
10960 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10961 NULL, "failed to create ASO age pool");
10962 return 0; /* 0 is an error. */
10964 rte_spinlock_unlock(&mng->free_sl);
10965 pool = container_of
10966 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10967 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10969 if (!age_free->dr_action) {
10970 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10974 rte_flow_error_set(error, rte_errno,
10975 RTE_FLOW_ERROR_TYPE_ACTION,
10976 NULL, "failed to get reg_c "
10977 "for ASO flow hit");
10978 return 0; /* 0 is an error. */
10980 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10981 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10982 (priv->sh->rx_domain,
10983 pool->flow_hit_aso_obj->obj, age_free->offset,
10984 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10985 (reg_c - REG_C_0));
10986 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10987 if (!age_free->dr_action) {
10989 rte_spinlock_lock(&mng->free_sl);
10990 LIST_INSERT_HEAD(&mng->free, age_free, next);
10991 rte_spinlock_unlock(&mng->free_sl);
10992 rte_flow_error_set(error, rte_errno,
10993 RTE_FLOW_ERROR_TYPE_ACTION,
10994 NULL, "failed to create ASO "
10995 "flow hit action");
10996 return 0; /* 0 is an error. */
10999 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
11000 return pool->index | ((age_free->offset + 1) << 16);
11004 * Create a age action using ASO mechanism.
11007 * Pointer to rte_eth_dev structure.
11009 * Pointer to the aging action configuration.
11010 * @param[out] error
11011 * Pointer to the error structure.
11014 * Index to flow counter on success, 0 otherwise.
11017 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
11018 const struct rte_flow_action_age *age,
11019 struct rte_flow_error *error)
11021 uint32_t age_idx = 0;
11022 struct mlx5_aso_age_action *aso_age;
11024 age_idx = flow_dv_aso_age_alloc(dev, error);
11027 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11028 aso_age->age_params.context = age->context;
11029 aso_age->age_params.timeout = age->timeout;
11030 aso_age->age_params.port_id = dev->data->port_id;
11031 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11033 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11039 * Fill the flow with DV spec, lock free
11040 * (mutex should be acquired by caller).
11043 * Pointer to rte_eth_dev structure.
11044 * @param[in, out] dev_flow
11045 * Pointer to the sub flow.
11047 * Pointer to the flow attributes.
11049 * Pointer to the list of items.
11050 * @param[in] actions
11051 * Pointer to the list of actions.
11052 * @param[out] error
11053 * Pointer to the error structure.
11056 * 0 on success, a negative errno value otherwise and rte_errno is set.
11059 flow_dv_translate(struct rte_eth_dev *dev,
11060 struct mlx5_flow *dev_flow,
11061 const struct rte_flow_attr *attr,
11062 const struct rte_flow_item items[],
11063 const struct rte_flow_action actions[],
11064 struct rte_flow_error *error)
11066 struct mlx5_priv *priv = dev->data->dev_private;
11067 struct mlx5_dev_config *dev_conf = &priv->config;
11068 struct rte_flow *flow = dev_flow->flow;
11069 struct mlx5_flow_handle *handle = dev_flow->handle;
11070 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11071 struct mlx5_flow_rss_desc *rss_desc;
11072 uint64_t item_flags = 0;
11073 uint64_t last_item = 0;
11074 uint64_t action_flags = 0;
11075 struct mlx5_flow_dv_matcher matcher = {
11077 .size = sizeof(matcher.mask.buf) -
11078 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11082 bool actions_end = false;
11084 struct mlx5_flow_dv_modify_hdr_resource res;
11085 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11086 sizeof(struct mlx5_modification_cmd) *
11087 (MLX5_MAX_MODIFY_NUM + 1)];
11089 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11090 const struct rte_flow_action_count *count = NULL;
11091 const struct rte_flow_action_age *age = NULL;
11092 union flow_dv_attr flow_attr = { .attr = 0 };
11094 union mlx5_flow_tbl_key tbl_key;
11095 uint32_t modify_action_position = UINT32_MAX;
11096 void *match_mask = matcher.mask.buf;
11097 void *match_value = dev_flow->dv.value.buf;
11098 uint8_t next_protocol = 0xff;
11099 struct rte_vlan_hdr vlan = { 0 };
11100 struct mlx5_flow_dv_dest_array_resource mdest_res;
11101 struct mlx5_flow_dv_sample_resource sample_res;
11102 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11103 const struct rte_flow_action_sample *sample = NULL;
11104 struct mlx5_flow_sub_actions_list *sample_act;
11105 uint32_t sample_act_pos = UINT32_MAX;
11106 uint32_t num_of_dest = 0;
11107 int tmp_actions_n = 0;
11110 const struct mlx5_flow_tunnel *tunnel;
11111 struct flow_grp_info grp_info = {
11112 .external = !!dev_flow->external,
11113 .transfer = !!attr->transfer,
11114 .fdb_def_rule = !!priv->fdb_def_rule,
11115 .skip_scale = dev_flow->skip_scale &
11116 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11120 return rte_flow_error_set(error, ENOMEM,
11121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11123 "failed to push flow workspace");
11124 rss_desc = &wks->rss_desc;
11125 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11126 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11127 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11128 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11129 /* update normal path action resource into last index of array */
11130 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11131 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11132 flow_items_to_tunnel(items) :
11133 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11134 flow_actions_to_tunnel(actions) :
11135 dev_flow->tunnel ? dev_flow->tunnel : NULL;
11136 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11137 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11138 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11139 (dev, tunnel, attr, items, actions);
11140 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11144 dev_flow->dv.group = table;
11145 if (attr->transfer)
11146 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11147 /* number of actions must be set to 0 in case of dirty stack. */
11148 mhdr_res->actions_num = 0;
11149 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11151 * do not add decap action if match rule drops packet
11152 * HW rejects rules with decap & drop
11154 * if tunnel match rule was inserted before matching tunnel set
11155 * rule flow table used in the match rule must be registered.
11156 * current implementation handles that in the
11157 * flow_dv_match_register() at the function end.
11159 bool add_decap = true;
11160 const struct rte_flow_action *ptr = actions;
11162 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11163 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11169 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11173 dev_flow->dv.actions[actions_n++] =
11174 dev_flow->dv.encap_decap->action;
11175 action_flags |= MLX5_FLOW_ACTION_DECAP;
11178 for (; !actions_end ; actions++) {
11179 const struct rte_flow_action_queue *queue;
11180 const struct rte_flow_action_rss *rss;
11181 const struct rte_flow_action *action = actions;
11182 const uint8_t *rss_key;
11183 struct mlx5_flow_tbl_resource *tbl;
11184 struct mlx5_aso_age_action *age_act;
11185 uint32_t port_id = 0;
11186 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11187 int action_type = actions->type;
11188 const struct rte_flow_action *found_action = NULL;
11189 uint32_t jump_group = 0;
11191 if (!mlx5_flow_os_action_supported(action_type))
11192 return rte_flow_error_set(error, ENOTSUP,
11193 RTE_FLOW_ERROR_TYPE_ACTION,
11195 "action not supported");
11196 switch (action_type) {
11197 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11198 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11200 case RTE_FLOW_ACTION_TYPE_VOID:
11202 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11203 if (flow_dv_translate_action_port_id(dev, action,
11206 port_id_resource.port_id = port_id;
11207 MLX5_ASSERT(!handle->rix_port_id_action);
11208 if (flow_dv_port_id_action_resource_register
11209 (dev, &port_id_resource, dev_flow, error))
11211 dev_flow->dv.actions[actions_n++] =
11212 dev_flow->dv.port_id_action->action;
11213 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11214 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11215 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11218 case RTE_FLOW_ACTION_TYPE_FLAG:
11219 action_flags |= MLX5_FLOW_ACTION_FLAG;
11220 dev_flow->handle->mark = 1;
11221 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11222 struct rte_flow_action_mark mark = {
11223 .id = MLX5_FLOW_MARK_DEFAULT,
11226 if (flow_dv_convert_action_mark(dev, &mark,
11230 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11233 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11235 * Only one FLAG or MARK is supported per device flow
11236 * right now. So the pointer to the tag resource must be
11237 * zero before the register process.
11239 MLX5_ASSERT(!handle->dvh.rix_tag);
11240 if (flow_dv_tag_resource_register(dev, tag_be,
11243 MLX5_ASSERT(dev_flow->dv.tag_resource);
11244 dev_flow->dv.actions[actions_n++] =
11245 dev_flow->dv.tag_resource->action;
11247 case RTE_FLOW_ACTION_TYPE_MARK:
11248 action_flags |= MLX5_FLOW_ACTION_MARK;
11249 dev_flow->handle->mark = 1;
11250 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11251 const struct rte_flow_action_mark *mark =
11252 (const struct rte_flow_action_mark *)
11255 if (flow_dv_convert_action_mark(dev, mark,
11259 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11263 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11264 /* Legacy (non-extensive) MARK action. */
11265 tag_be = mlx5_flow_mark_set
11266 (((const struct rte_flow_action_mark *)
11267 (actions->conf))->id);
11268 MLX5_ASSERT(!handle->dvh.rix_tag);
11269 if (flow_dv_tag_resource_register(dev, tag_be,
11272 MLX5_ASSERT(dev_flow->dv.tag_resource);
11273 dev_flow->dv.actions[actions_n++] =
11274 dev_flow->dv.tag_resource->action;
11276 case RTE_FLOW_ACTION_TYPE_SET_META:
11277 if (flow_dv_convert_action_set_meta
11278 (dev, mhdr_res, attr,
11279 (const struct rte_flow_action_set_meta *)
11280 actions->conf, error))
11282 action_flags |= MLX5_FLOW_ACTION_SET_META;
11284 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11285 if (flow_dv_convert_action_set_tag
11287 (const struct rte_flow_action_set_tag *)
11288 actions->conf, error))
11290 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11292 case RTE_FLOW_ACTION_TYPE_DROP:
11293 action_flags |= MLX5_FLOW_ACTION_DROP;
11294 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11296 case RTE_FLOW_ACTION_TYPE_QUEUE:
11297 queue = actions->conf;
11298 rss_desc->queue_num = 1;
11299 rss_desc->queue[0] = queue->index;
11300 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11301 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11302 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11305 case RTE_FLOW_ACTION_TYPE_RSS:
11306 rss = actions->conf;
11307 memcpy(rss_desc->queue, rss->queue,
11308 rss->queue_num * sizeof(uint16_t));
11309 rss_desc->queue_num = rss->queue_num;
11310 /* NULL RSS key indicates default RSS key. */
11311 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11312 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11314 * rss->level and rss.types should be set in advance
11315 * when expanding items for RSS.
11317 action_flags |= MLX5_FLOW_ACTION_RSS;
11318 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11319 MLX5_FLOW_FATE_SHARED_RSS :
11320 MLX5_FLOW_FATE_QUEUE;
11322 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11323 flow->age = (uint32_t)(uintptr_t)(action->conf);
11324 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11325 __atomic_fetch_add(&age_act->refcnt, 1,
11327 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11328 action_flags |= MLX5_FLOW_ACTION_AGE;
11330 case RTE_FLOW_ACTION_TYPE_AGE:
11331 if (priv->sh->flow_hit_aso_en && attr->group) {
11333 * Create one shared age action, to be used
11334 * by all sub-flows.
11338 flow_dv_translate_create_aso_age
11339 (dev, action->conf,
11342 return rte_flow_error_set
11344 RTE_FLOW_ERROR_TYPE_ACTION,
11346 "can't create ASO age action");
11348 dev_flow->dv.actions[actions_n++] =
11349 (flow_aso_age_get_by_idx
11350 (dev, flow->age))->dr_action;
11351 action_flags |= MLX5_FLOW_ACTION_AGE;
11355 case RTE_FLOW_ACTION_TYPE_COUNT:
11356 if (!dev_conf->devx) {
11357 return rte_flow_error_set
11359 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11361 "count action not supported");
11363 /* Save information first, will apply later. */
11364 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11365 count = action->conf;
11367 age = action->conf;
11368 action_flags |= MLX5_FLOW_ACTION_COUNT;
11370 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11371 dev_flow->dv.actions[actions_n++] =
11372 priv->sh->pop_vlan_action;
11373 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11375 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11376 if (!(action_flags &
11377 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11378 flow_dev_get_vlan_info_from_items(items, &vlan);
11379 vlan.eth_proto = rte_be_to_cpu_16
11380 ((((const struct rte_flow_action_of_push_vlan *)
11381 actions->conf)->ethertype));
11382 found_action = mlx5_flow_find_action
11384 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11386 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11387 found_action = mlx5_flow_find_action
11389 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11391 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11392 if (flow_dv_create_action_push_vlan
11393 (dev, attr, &vlan, dev_flow, error))
11395 dev_flow->dv.actions[actions_n++] =
11396 dev_flow->dv.push_vlan_res->action;
11397 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11399 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11400 /* of_vlan_push action handled this action */
11401 MLX5_ASSERT(action_flags &
11402 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11404 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11405 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11407 flow_dev_get_vlan_info_from_items(items, &vlan);
11408 mlx5_update_vlan_vid_pcp(actions, &vlan);
11409 /* If no VLAN push - this is a modify header action */
11410 if (flow_dv_convert_action_modify_vlan_vid
11411 (mhdr_res, actions, error))
11413 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11415 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11416 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11417 if (flow_dv_create_action_l2_encap(dev, actions,
11422 dev_flow->dv.actions[actions_n++] =
11423 dev_flow->dv.encap_decap->action;
11424 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11425 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11426 sample_act->action_flags |=
11427 MLX5_FLOW_ACTION_ENCAP;
11429 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11430 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11431 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11435 dev_flow->dv.actions[actions_n++] =
11436 dev_flow->dv.encap_decap->action;
11437 action_flags |= MLX5_FLOW_ACTION_DECAP;
11439 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11440 /* Handle encap with preceding decap. */
11441 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11442 if (flow_dv_create_action_raw_encap
11443 (dev, actions, dev_flow, attr, error))
11445 dev_flow->dv.actions[actions_n++] =
11446 dev_flow->dv.encap_decap->action;
11448 /* Handle encap without preceding decap. */
11449 if (flow_dv_create_action_l2_encap
11450 (dev, actions, dev_flow, attr->transfer,
11453 dev_flow->dv.actions[actions_n++] =
11454 dev_flow->dv.encap_decap->action;
11456 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11457 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11458 sample_act->action_flags |=
11459 MLX5_FLOW_ACTION_ENCAP;
11461 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11462 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11464 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11465 if (flow_dv_create_action_l2_decap
11466 (dev, dev_flow, attr->transfer, error))
11468 dev_flow->dv.actions[actions_n++] =
11469 dev_flow->dv.encap_decap->action;
11471 /* If decap is followed by encap, handle it at encap. */
11472 action_flags |= MLX5_FLOW_ACTION_DECAP;
11474 case RTE_FLOW_ACTION_TYPE_JUMP:
11475 jump_group = ((const struct rte_flow_action_jump *)
11476 action->conf)->group;
11477 grp_info.std_tbl_fix = 0;
11478 if (dev_flow->skip_scale &
11479 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11480 grp_info.skip_scale = 1;
11482 grp_info.skip_scale = 0;
11483 ret = mlx5_flow_group_to_table(dev, tunnel,
11489 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11491 !!dev_flow->external,
11492 tunnel, jump_group, 0,
11495 return rte_flow_error_set
11497 RTE_FLOW_ERROR_TYPE_ACTION,
11499 "cannot create jump action.");
11500 if (flow_dv_jump_tbl_resource_register
11501 (dev, tbl, dev_flow, error)) {
11502 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11503 return rte_flow_error_set
11505 RTE_FLOW_ERROR_TYPE_ACTION,
11507 "cannot create jump action.");
11509 dev_flow->dv.actions[actions_n++] =
11510 dev_flow->dv.jump->action;
11511 action_flags |= MLX5_FLOW_ACTION_JUMP;
11512 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11513 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11516 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11517 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11518 if (flow_dv_convert_action_modify_mac
11519 (mhdr_res, actions, error))
11521 action_flags |= actions->type ==
11522 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11523 MLX5_FLOW_ACTION_SET_MAC_SRC :
11524 MLX5_FLOW_ACTION_SET_MAC_DST;
11526 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11527 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11528 if (flow_dv_convert_action_modify_ipv4
11529 (mhdr_res, actions, error))
11531 action_flags |= actions->type ==
11532 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11533 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11534 MLX5_FLOW_ACTION_SET_IPV4_DST;
11536 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11537 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11538 if (flow_dv_convert_action_modify_ipv6
11539 (mhdr_res, actions, error))
11541 action_flags |= actions->type ==
11542 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11543 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11544 MLX5_FLOW_ACTION_SET_IPV6_DST;
11546 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11547 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11548 if (flow_dv_convert_action_modify_tp
11549 (mhdr_res, actions, items,
11550 &flow_attr, dev_flow, !!(action_flags &
11551 MLX5_FLOW_ACTION_DECAP), error))
11553 action_flags |= actions->type ==
11554 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11555 MLX5_FLOW_ACTION_SET_TP_SRC :
11556 MLX5_FLOW_ACTION_SET_TP_DST;
11558 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11559 if (flow_dv_convert_action_modify_dec_ttl
11560 (mhdr_res, items, &flow_attr, dev_flow,
11562 MLX5_FLOW_ACTION_DECAP), error))
11564 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11566 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11567 if (flow_dv_convert_action_modify_ttl
11568 (mhdr_res, actions, items, &flow_attr,
11569 dev_flow, !!(action_flags &
11570 MLX5_FLOW_ACTION_DECAP), error))
11572 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11574 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11575 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11576 if (flow_dv_convert_action_modify_tcp_seq
11577 (mhdr_res, actions, error))
11579 action_flags |= actions->type ==
11580 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11581 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11582 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11585 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11586 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11587 if (flow_dv_convert_action_modify_tcp_ack
11588 (mhdr_res, actions, error))
11590 action_flags |= actions->type ==
11591 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11592 MLX5_FLOW_ACTION_INC_TCP_ACK :
11593 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11595 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11596 if (flow_dv_convert_action_set_reg
11597 (mhdr_res, actions, error))
11599 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11601 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11602 if (flow_dv_convert_action_copy_mreg
11603 (dev, mhdr_res, actions, error))
11605 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11607 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11608 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11609 dev_flow->handle->fate_action =
11610 MLX5_FLOW_FATE_DEFAULT_MISS;
11612 case RTE_FLOW_ACTION_TYPE_METER:
11614 return rte_flow_error_set(error, rte_errno,
11615 RTE_FLOW_ERROR_TYPE_ACTION,
11616 NULL, "Failed to get meter in flow.");
11617 /* Set the meter action. */
11618 dev_flow->dv.actions[actions_n++] =
11619 wks->fm->meter_action;
11620 action_flags |= MLX5_FLOW_ACTION_METER;
11622 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11623 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11626 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11628 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11629 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11632 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11634 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11635 sample_act_pos = actions_n;
11636 sample = (const struct rte_flow_action_sample *)
11639 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11640 /* put encap action into group if work with port id */
11641 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11642 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11643 sample_act->action_flags |=
11644 MLX5_FLOW_ACTION_ENCAP;
11646 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11647 if (flow_dv_convert_action_modify_field
11648 (dev, mhdr_res, actions, attr, error))
11650 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11652 case RTE_FLOW_ACTION_TYPE_END:
11653 actions_end = true;
11654 if (mhdr_res->actions_num) {
11655 /* create modify action if needed. */
11656 if (flow_dv_modify_hdr_resource_register
11657 (dev, mhdr_res, dev_flow, error))
11659 dev_flow->dv.actions[modify_action_position] =
11660 handle->dvh.modify_hdr->action;
11662 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11664 * Create one count action, to be used
11665 * by all sub-flows.
11667 if (!flow->counter) {
11669 flow_dv_translate_create_counter
11670 (dev, dev_flow, count,
11672 if (!flow->counter)
11673 return rte_flow_error_set
11675 RTE_FLOW_ERROR_TYPE_ACTION,
11676 NULL, "cannot create counter"
11679 dev_flow->dv.actions[actions_n] =
11680 (flow_dv_counter_get_by_idx(dev,
11681 flow->counter, NULL))->action;
11687 if (mhdr_res->actions_num &&
11688 modify_action_position == UINT32_MAX)
11689 modify_action_position = actions_n++;
11691 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11692 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11693 int item_type = items->type;
11695 if (!mlx5_flow_os_item_supported(item_type))
11696 return rte_flow_error_set(error, ENOTSUP,
11697 RTE_FLOW_ERROR_TYPE_ITEM,
11698 NULL, "item not supported");
11699 switch (item_type) {
11700 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11701 flow_dv_translate_item_port_id
11702 (dev, match_mask, match_value, items, attr);
11703 last_item = MLX5_FLOW_ITEM_PORT_ID;
11705 case RTE_FLOW_ITEM_TYPE_ETH:
11706 flow_dv_translate_item_eth(match_mask, match_value,
11708 dev_flow->dv.group);
11709 matcher.priority = action_flags &
11710 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11711 !dev_flow->external ?
11712 MLX5_PRIORITY_MAP_L3 :
11713 MLX5_PRIORITY_MAP_L2;
11714 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11715 MLX5_FLOW_LAYER_OUTER_L2;
11717 case RTE_FLOW_ITEM_TYPE_VLAN:
11718 flow_dv_translate_item_vlan(dev_flow,
11719 match_mask, match_value,
11721 dev_flow->dv.group);
11722 matcher.priority = MLX5_PRIORITY_MAP_L2;
11723 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11724 MLX5_FLOW_LAYER_INNER_VLAN) :
11725 (MLX5_FLOW_LAYER_OUTER_L2 |
11726 MLX5_FLOW_LAYER_OUTER_VLAN);
11728 case RTE_FLOW_ITEM_TYPE_IPV4:
11729 mlx5_flow_tunnel_ip_check(items, next_protocol,
11730 &item_flags, &tunnel);
11731 flow_dv_translate_item_ipv4(match_mask, match_value,
11733 dev_flow->dv.group);
11734 matcher.priority = MLX5_PRIORITY_MAP_L3;
11735 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11736 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11737 if (items->mask != NULL &&
11738 ((const struct rte_flow_item_ipv4 *)
11739 items->mask)->hdr.next_proto_id) {
11741 ((const struct rte_flow_item_ipv4 *)
11742 (items->spec))->hdr.next_proto_id;
11744 ((const struct rte_flow_item_ipv4 *)
11745 (items->mask))->hdr.next_proto_id;
11747 /* Reset for inner layer. */
11748 next_protocol = 0xff;
11751 case RTE_FLOW_ITEM_TYPE_IPV6:
11752 mlx5_flow_tunnel_ip_check(items, next_protocol,
11753 &item_flags, &tunnel);
11754 flow_dv_translate_item_ipv6(match_mask, match_value,
11756 dev_flow->dv.group);
11757 matcher.priority = MLX5_PRIORITY_MAP_L3;
11758 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11759 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11760 if (items->mask != NULL &&
11761 ((const struct rte_flow_item_ipv6 *)
11762 items->mask)->hdr.proto) {
11764 ((const struct rte_flow_item_ipv6 *)
11765 items->spec)->hdr.proto;
11767 ((const struct rte_flow_item_ipv6 *)
11768 items->mask)->hdr.proto;
11770 /* Reset for inner layer. */
11771 next_protocol = 0xff;
11774 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11775 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11778 last_item = tunnel ?
11779 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11780 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11781 if (items->mask != NULL &&
11782 ((const struct rte_flow_item_ipv6_frag_ext *)
11783 items->mask)->hdr.next_header) {
11785 ((const struct rte_flow_item_ipv6_frag_ext *)
11786 items->spec)->hdr.next_header;
11788 ((const struct rte_flow_item_ipv6_frag_ext *)
11789 items->mask)->hdr.next_header;
11791 /* Reset for inner layer. */
11792 next_protocol = 0xff;
11795 case RTE_FLOW_ITEM_TYPE_TCP:
11796 flow_dv_translate_item_tcp(match_mask, match_value,
11798 matcher.priority = MLX5_PRIORITY_MAP_L4;
11799 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11800 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11802 case RTE_FLOW_ITEM_TYPE_UDP:
11803 flow_dv_translate_item_udp(match_mask, match_value,
11805 matcher.priority = MLX5_PRIORITY_MAP_L4;
11806 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11807 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11809 case RTE_FLOW_ITEM_TYPE_GRE:
11810 flow_dv_translate_item_gre(match_mask, match_value,
11812 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11813 last_item = MLX5_FLOW_LAYER_GRE;
11815 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11816 flow_dv_translate_item_gre_key(match_mask,
11817 match_value, items);
11818 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11820 case RTE_FLOW_ITEM_TYPE_NVGRE:
11821 flow_dv_translate_item_nvgre(match_mask, match_value,
11823 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11824 last_item = MLX5_FLOW_LAYER_GRE;
11826 case RTE_FLOW_ITEM_TYPE_VXLAN:
11827 flow_dv_translate_item_vxlan(match_mask, match_value,
11829 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11830 last_item = MLX5_FLOW_LAYER_VXLAN;
11832 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11833 flow_dv_translate_item_vxlan_gpe(match_mask,
11834 match_value, items,
11836 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11837 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11839 case RTE_FLOW_ITEM_TYPE_GENEVE:
11840 flow_dv_translate_item_geneve(match_mask, match_value,
11842 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11843 last_item = MLX5_FLOW_LAYER_GENEVE;
11845 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11846 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11850 return rte_flow_error_set(error, -ret,
11851 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11852 "cannot create GENEVE TLV option");
11853 flow->geneve_tlv_option = 1;
11854 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11856 case RTE_FLOW_ITEM_TYPE_MPLS:
11857 flow_dv_translate_item_mpls(match_mask, match_value,
11858 items, last_item, tunnel);
11859 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11860 last_item = MLX5_FLOW_LAYER_MPLS;
11862 case RTE_FLOW_ITEM_TYPE_MARK:
11863 flow_dv_translate_item_mark(dev, match_mask,
11864 match_value, items);
11865 last_item = MLX5_FLOW_ITEM_MARK;
11867 case RTE_FLOW_ITEM_TYPE_META:
11868 flow_dv_translate_item_meta(dev, match_mask,
11869 match_value, attr, items);
11870 last_item = MLX5_FLOW_ITEM_METADATA;
11872 case RTE_FLOW_ITEM_TYPE_ICMP:
11873 flow_dv_translate_item_icmp(match_mask, match_value,
11875 last_item = MLX5_FLOW_LAYER_ICMP;
11877 case RTE_FLOW_ITEM_TYPE_ICMP6:
11878 flow_dv_translate_item_icmp6(match_mask, match_value,
11880 last_item = MLX5_FLOW_LAYER_ICMP6;
11882 case RTE_FLOW_ITEM_TYPE_TAG:
11883 flow_dv_translate_item_tag(dev, match_mask,
11884 match_value, items);
11885 last_item = MLX5_FLOW_ITEM_TAG;
11887 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11888 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11889 match_value, items);
11890 last_item = MLX5_FLOW_ITEM_TAG;
11892 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11893 flow_dv_translate_item_tx_queue(dev, match_mask,
11896 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11898 case RTE_FLOW_ITEM_TYPE_GTP:
11899 flow_dv_translate_item_gtp(match_mask, match_value,
11901 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11902 last_item = MLX5_FLOW_LAYER_GTP;
11904 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11905 ret = flow_dv_translate_item_gtp_psc(match_mask,
11909 return rte_flow_error_set(error, -ret,
11910 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11911 "cannot create GTP PSC item");
11912 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11914 case RTE_FLOW_ITEM_TYPE_ECPRI:
11915 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11916 /* Create it only the first time to be used. */
11917 ret = mlx5_flex_parser_ecpri_alloc(dev);
11919 return rte_flow_error_set
11921 RTE_FLOW_ERROR_TYPE_ITEM,
11923 "cannot create eCPRI parser");
11925 /* Adjust the length matcher and device flow value. */
11926 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11927 dev_flow->dv.value.size =
11928 MLX5_ST_SZ_BYTES(fte_match_param);
11929 flow_dv_translate_item_ecpri(dev, match_mask,
11930 match_value, items);
11931 /* No other protocol should follow eCPRI layer. */
11932 last_item = MLX5_FLOW_LAYER_ECPRI;
11937 item_flags |= last_item;
11940 * When E-Switch mode is enabled, we have two cases where we need to
11941 * set the source port manually.
11942 * The first one, is in case of Nic steering rule, and the second is
11943 * E-Switch rule where no port_id item was found. In both cases
11944 * the source port is set according the current port in use.
11946 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11947 (priv->representor || priv->master)) {
11948 if (flow_dv_translate_item_port_id(dev, match_mask,
11949 match_value, NULL, attr))
11952 #ifdef RTE_LIBRTE_MLX5_DEBUG
11953 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11954 dev_flow->dv.value.buf));
11957 * Layers may be already initialized from prefix flow if this dev_flow
11958 * is the suffix flow.
11960 handle->layers |= item_flags;
11961 if (action_flags & MLX5_FLOW_ACTION_RSS)
11962 flow_dv_hashfields_set(dev_flow, rss_desc);
11963 /* If has RSS action in the sample action, the Sample/Mirror resource
11964 * should be registered after the hash filed be update.
11966 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11967 ret = flow_dv_translate_action_sample(dev,
11976 ret = flow_dv_create_action_sample(dev,
11985 return rte_flow_error_set
11987 RTE_FLOW_ERROR_TYPE_ACTION,
11989 "cannot create sample action");
11990 if (num_of_dest > 1) {
11991 dev_flow->dv.actions[sample_act_pos] =
11992 dev_flow->dv.dest_array_res->action;
11994 dev_flow->dv.actions[sample_act_pos] =
11995 dev_flow->dv.sample_res->verbs_action;
11999 * For multiple destination (sample action with ratio=1), the encap
12000 * action and port id action will be combined into group action.
12001 * So need remove the original these actions in the flow and only
12002 * use the sample action instead of.
12004 if (num_of_dest > 1 &&
12005 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
12007 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12009 for (i = 0; i < actions_n; i++) {
12010 if ((sample_act->dr_encap_action &&
12011 sample_act->dr_encap_action ==
12012 dev_flow->dv.actions[i]) ||
12013 (sample_act->dr_port_id_action &&
12014 sample_act->dr_port_id_action ==
12015 dev_flow->dv.actions[i]) ||
12016 (sample_act->dr_jump_action &&
12017 sample_act->dr_jump_action ==
12018 dev_flow->dv.actions[i]))
12020 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12022 memcpy((void *)dev_flow->dv.actions,
12023 (void *)temp_actions,
12024 tmp_actions_n * sizeof(void *));
12025 actions_n = tmp_actions_n;
12027 dev_flow->dv.actions_n = actions_n;
12028 dev_flow->act_flags = action_flags;
12029 /* Register matcher. */
12030 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12031 matcher.mask.size);
12032 matcher.priority = mlx5_get_matcher_priority(dev, attr,
12034 /* reserved field no needs to be set to 0 here. */
12035 tbl_key.domain = attr->transfer;
12036 tbl_key.direction = attr->egress;
12037 tbl_key.table_id = dev_flow->dv.group;
12038 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12039 tunnel, attr->group, error))
12045 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12048 * @param[in, out] action
12049 * Shred RSS action holding hash RX queue objects.
12050 * @param[in] hash_fields
12051 * Defines combination of packet fields to participate in RX hash.
12052 * @param[in] tunnel
12054 * @param[in] hrxq_idx
12055 * Hash RX queue index to set.
12058 * 0 on success, otherwise negative errno value.
12061 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12062 const uint64_t hash_fields,
12065 uint32_t *hrxqs = action->hrxq;
12067 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12068 case MLX5_RSS_HASH_IPV4:
12069 /* fall-through. */
12070 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12071 /* fall-through. */
12072 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12073 hrxqs[0] = hrxq_idx;
12075 case MLX5_RSS_HASH_IPV4_TCP:
12076 /* fall-through. */
12077 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12078 /* fall-through. */
12079 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12080 hrxqs[1] = hrxq_idx;
12082 case MLX5_RSS_HASH_IPV4_UDP:
12083 /* fall-through. */
12084 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12085 /* fall-through. */
12086 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12087 hrxqs[2] = hrxq_idx;
12089 case MLX5_RSS_HASH_IPV6:
12090 /* fall-through. */
12091 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12092 /* fall-through. */
12093 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12094 hrxqs[3] = hrxq_idx;
12096 case MLX5_RSS_HASH_IPV6_TCP:
12097 /* fall-through. */
12098 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12099 /* fall-through. */
12100 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12101 hrxqs[4] = hrxq_idx;
12103 case MLX5_RSS_HASH_IPV6_UDP:
12104 /* fall-through. */
12105 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12106 /* fall-through. */
12107 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12108 hrxqs[5] = hrxq_idx;
12110 case MLX5_RSS_HASH_NONE:
12111 hrxqs[6] = hrxq_idx;
12119 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12123 * Pointer to the Ethernet device structure.
12125 * Shared RSS action ID holding hash RX queue objects.
12126 * @param[in] hash_fields
12127 * Defines combination of packet fields to participate in RX hash.
12128 * @param[in] tunnel
12132 * Valid hash RX queue index, otherwise 0.
12135 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12136 const uint64_t hash_fields)
12138 struct mlx5_priv *priv = dev->data->dev_private;
12139 struct mlx5_shared_action_rss *shared_rss =
12140 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12141 const uint32_t *hrxqs = shared_rss->hrxq;
12143 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12144 case MLX5_RSS_HASH_IPV4:
12145 /* fall-through. */
12146 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12147 /* fall-through. */
12148 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12150 case MLX5_RSS_HASH_IPV4_TCP:
12151 /* fall-through. */
12152 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12153 /* fall-through. */
12154 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12156 case MLX5_RSS_HASH_IPV4_UDP:
12157 /* fall-through. */
12158 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12159 /* fall-through. */
12160 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12162 case MLX5_RSS_HASH_IPV6:
12163 /* fall-through. */
12164 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12165 /* fall-through. */
12166 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12168 case MLX5_RSS_HASH_IPV6_TCP:
12169 /* fall-through. */
12170 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12171 /* fall-through. */
12172 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12174 case MLX5_RSS_HASH_IPV6_UDP:
12175 /* fall-through. */
12176 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12177 /* fall-through. */
12178 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12180 case MLX5_RSS_HASH_NONE:
12189 * Apply the flow to the NIC, lock free,
12190 * (mutex should be acquired by caller).
12193 * Pointer to the Ethernet device structure.
12194 * @param[in, out] flow
12195 * Pointer to flow structure.
12196 * @param[out] error
12197 * Pointer to error structure.
12200 * 0 on success, a negative errno value otherwise and rte_errno is set.
12203 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12204 struct rte_flow_error *error)
12206 struct mlx5_flow_dv_workspace *dv;
12207 struct mlx5_flow_handle *dh;
12208 struct mlx5_flow_handle_dv *dv_h;
12209 struct mlx5_flow *dev_flow;
12210 struct mlx5_priv *priv = dev->data->dev_private;
12211 uint32_t handle_idx;
12215 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12216 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12219 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12220 dev_flow = &wks->flows[idx];
12221 dv = &dev_flow->dv;
12222 dh = dev_flow->handle;
12225 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12226 if (dv->transfer) {
12227 MLX5_ASSERT(priv->sh->dr_drop_action);
12228 dv->actions[n++] = priv->sh->dr_drop_action;
12230 #ifdef HAVE_MLX5DV_DR
12231 /* DR supports drop action placeholder. */
12232 MLX5_ASSERT(priv->sh->dr_drop_action);
12233 dv->actions[n++] = priv->sh->dr_drop_action;
12235 /* For DV we use the explicit drop queue. */
12236 MLX5_ASSERT(priv->drop_queue.hrxq);
12238 priv->drop_queue.hrxq->action;
12241 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12242 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12243 struct mlx5_hrxq *hrxq;
12246 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12251 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12252 "cannot get hash queue");
12255 dh->rix_hrxq = hrxq_idx;
12256 dv->actions[n++] = hrxq->action;
12257 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12258 struct mlx5_hrxq *hrxq = NULL;
12261 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12262 rss_desc->shared_rss,
12263 dev_flow->hash_fields);
12265 hrxq = mlx5_ipool_get
12266 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12271 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12272 "cannot get hash queue");
12275 dh->rix_srss = rss_desc->shared_rss;
12276 dv->actions[n++] = hrxq->action;
12277 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12278 if (!priv->sh->default_miss_action) {
12281 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12282 "default miss action not be created.");
12285 dv->actions[n++] = priv->sh->default_miss_action;
12287 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12288 (void *)&dv->value, n,
12289 dv->actions, &dh->drv_flow);
12291 rte_flow_error_set(error, errno,
12292 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12294 "hardware refuses to create flow");
12297 if (priv->vmwa_context &&
12298 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12300 * The rule contains the VLAN pattern.
12301 * For VF we are going to create VLAN
12302 * interface to make hypervisor set correct
12303 * e-Switch vport context.
12305 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12310 err = rte_errno; /* Save rte_errno before cleanup. */
12311 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12312 handle_idx, dh, next) {
12313 /* hrxq is union, don't clear it if the flag is not set. */
12314 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12315 mlx5_hrxq_release(dev, dh->rix_hrxq);
12317 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12320 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12321 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12323 rte_errno = err; /* Restore rte_errno. */
12328 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12329 struct mlx5_cache_entry *entry)
12331 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12334 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12339 * Release the flow matcher.
12342 * Pointer to Ethernet device.
12344 * Index to port ID action resource.
12347 * 1 while a reference on it exists, 0 when freed.
12350 flow_dv_matcher_release(struct rte_eth_dev *dev,
12351 struct mlx5_flow_handle *handle)
12353 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12354 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12355 typeof(*tbl), tbl);
12358 MLX5_ASSERT(matcher->matcher_object);
12359 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12360 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12365 * Release encap_decap resource.
12368 * Pointer to the hash list.
12370 * Pointer to exist resource entry object.
12373 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12374 struct mlx5_hlist_entry *entry)
12376 struct mlx5_dev_ctx_shared *sh = list->ctx;
12377 struct mlx5_flow_dv_encap_decap_resource *res =
12378 container_of(entry, typeof(*res), entry);
12380 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12381 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12385 * Release an encap/decap resource.
12388 * Pointer to Ethernet device.
12389 * @param encap_decap_idx
12390 * Index of encap decap resource.
12393 * 1 while a reference on it exists, 0 when freed.
12396 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12397 uint32_t encap_decap_idx)
12399 struct mlx5_priv *priv = dev->data->dev_private;
12400 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12402 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12404 if (!cache_resource)
12406 MLX5_ASSERT(cache_resource->action);
12407 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12408 &cache_resource->entry);
12412 * Release an jump to table action resource.
12415 * Pointer to Ethernet device.
12417 * Index to the jump action resource.
12420 * 1 while a reference on it exists, 0 when freed.
12423 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12426 struct mlx5_priv *priv = dev->data->dev_private;
12427 struct mlx5_flow_tbl_data_entry *tbl_data;
12429 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12433 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12437 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12438 struct mlx5_hlist_entry *entry)
12440 struct mlx5_flow_dv_modify_hdr_resource *res =
12441 container_of(entry, typeof(*res), entry);
12443 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12448 * Release a modify-header resource.
12451 * Pointer to Ethernet device.
12453 * Pointer to mlx5_flow_handle.
12456 * 1 while a reference on it exists, 0 when freed.
12459 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12460 struct mlx5_flow_handle *handle)
12462 struct mlx5_priv *priv = dev->data->dev_private;
12463 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12465 MLX5_ASSERT(entry->action);
12466 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12470 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12471 struct mlx5_cache_entry *entry)
12473 struct mlx5_dev_ctx_shared *sh = list->ctx;
12474 struct mlx5_flow_dv_port_id_action_resource *cache =
12475 container_of(entry, typeof(*cache), entry);
12477 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12478 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12482 * Release port ID action resource.
12485 * Pointer to Ethernet device.
12487 * Pointer to mlx5_flow_handle.
12490 * 1 while a reference on it exists, 0 when freed.
12493 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12496 struct mlx5_priv *priv = dev->data->dev_private;
12497 struct mlx5_flow_dv_port_id_action_resource *cache;
12499 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12502 MLX5_ASSERT(cache->action);
12503 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12508 * Release shared RSS action resource.
12511 * Pointer to Ethernet device.
12513 * Shared RSS action index.
12516 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12518 struct mlx5_priv *priv = dev->data->dev_private;
12519 struct mlx5_shared_action_rss *shared_rss;
12521 shared_rss = mlx5_ipool_get
12522 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12523 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12527 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12528 struct mlx5_cache_entry *entry)
12530 struct mlx5_dev_ctx_shared *sh = list->ctx;
12531 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12532 container_of(entry, typeof(*cache), entry);
12534 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12535 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12539 * Release push vlan action resource.
12542 * Pointer to Ethernet device.
12544 * Pointer to mlx5_flow_handle.
12547 * 1 while a reference on it exists, 0 when freed.
12550 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12551 struct mlx5_flow_handle *handle)
12553 struct mlx5_priv *priv = dev->data->dev_private;
12554 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12555 uint32_t idx = handle->dvh.rix_push_vlan;
12557 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12560 MLX5_ASSERT(cache->action);
12561 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12566 * Release the fate resource.
12569 * Pointer to Ethernet device.
12571 * Pointer to mlx5_flow_handle.
12574 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12575 struct mlx5_flow_handle *handle)
12577 if (!handle->rix_fate)
12579 switch (handle->fate_action) {
12580 case MLX5_FLOW_FATE_QUEUE:
12581 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12582 mlx5_hrxq_release(dev, handle->rix_hrxq);
12584 case MLX5_FLOW_FATE_JUMP:
12585 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12587 case MLX5_FLOW_FATE_PORT_ID:
12588 flow_dv_port_id_action_resource_release(dev,
12589 handle->rix_port_id_action);
12592 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12595 handle->rix_fate = 0;
12599 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12600 struct mlx5_cache_entry *entry)
12602 struct mlx5_flow_dv_sample_resource *cache_resource =
12603 container_of(entry, typeof(*cache_resource), entry);
12604 struct rte_eth_dev *dev = cache_resource->dev;
12605 struct mlx5_priv *priv = dev->data->dev_private;
12607 if (cache_resource->verbs_action)
12608 claim_zero(mlx5_flow_os_destroy_flow_action
12609 (cache_resource->verbs_action));
12610 if (cache_resource->normal_path_tbl)
12611 flow_dv_tbl_resource_release(MLX5_SH(dev),
12612 cache_resource->normal_path_tbl);
12613 flow_dv_sample_sub_actions_release(dev,
12614 &cache_resource->sample_idx);
12615 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12616 cache_resource->idx);
12617 DRV_LOG(DEBUG, "sample resource %p: removed",
12618 (void *)cache_resource);
12622 * Release an sample resource.
12625 * Pointer to Ethernet device.
12627 * Pointer to mlx5_flow_handle.
12630 * 1 while a reference on it exists, 0 when freed.
12633 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12634 struct mlx5_flow_handle *handle)
12636 struct mlx5_priv *priv = dev->data->dev_private;
12637 struct mlx5_flow_dv_sample_resource *cache_resource;
12639 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12640 handle->dvh.rix_sample);
12641 if (!cache_resource)
12643 MLX5_ASSERT(cache_resource->verbs_action);
12644 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12645 &cache_resource->entry);
12649 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12650 struct mlx5_cache_entry *entry)
12652 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12653 container_of(entry, typeof(*cache_resource), entry);
12654 struct rte_eth_dev *dev = cache_resource->dev;
12655 struct mlx5_priv *priv = dev->data->dev_private;
12658 MLX5_ASSERT(cache_resource->action);
12659 if (cache_resource->action)
12660 claim_zero(mlx5_flow_os_destroy_flow_action
12661 (cache_resource->action));
12662 for (; i < cache_resource->num_of_dest; i++)
12663 flow_dv_sample_sub_actions_release(dev,
12664 &cache_resource->sample_idx[i]);
12665 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12666 cache_resource->idx);
12667 DRV_LOG(DEBUG, "destination array resource %p: removed",
12668 (void *)cache_resource);
12672 * Release an destination array resource.
12675 * Pointer to Ethernet device.
12677 * Pointer to mlx5_flow_handle.
12680 * 1 while a reference on it exists, 0 when freed.
12683 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12684 struct mlx5_flow_handle *handle)
12686 struct mlx5_priv *priv = dev->data->dev_private;
12687 struct mlx5_flow_dv_dest_array_resource *cache;
12689 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12690 handle->dvh.rix_dest_array);
12693 MLX5_ASSERT(cache->action);
12694 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12699 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12701 struct mlx5_priv *priv = dev->data->dev_private;
12702 struct mlx5_dev_ctx_shared *sh = priv->sh;
12703 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12704 sh->geneve_tlv_option_resource;
12705 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12706 if (geneve_opt_resource) {
12707 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12708 __ATOMIC_RELAXED))) {
12709 claim_zero(mlx5_devx_cmd_destroy
12710 (geneve_opt_resource->obj));
12711 mlx5_free(sh->geneve_tlv_option_resource);
12712 sh->geneve_tlv_option_resource = NULL;
12715 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12719 * Remove the flow from the NIC but keeps it in memory.
12720 * Lock free, (mutex should be acquired by caller).
12723 * Pointer to Ethernet device.
12724 * @param[in, out] flow
12725 * Pointer to flow structure.
12728 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12730 struct mlx5_flow_handle *dh;
12731 uint32_t handle_idx;
12732 struct mlx5_priv *priv = dev->data->dev_private;
12736 handle_idx = flow->dev_handles;
12737 while (handle_idx) {
12738 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12742 if (dh->drv_flow) {
12743 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12744 dh->drv_flow = NULL;
12746 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12747 flow_dv_fate_resource_release(dev, dh);
12748 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12749 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12750 handle_idx = dh->next.next;
12755 * Remove the flow from the NIC and the memory.
12756 * Lock free, (mutex should be acquired by caller).
12759 * Pointer to the Ethernet device structure.
12760 * @param[in, out] flow
12761 * Pointer to flow structure.
12764 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12766 struct mlx5_flow_handle *dev_handle;
12767 struct mlx5_priv *priv = dev->data->dev_private;
12768 struct mlx5_flow_meter_info *fm = NULL;
12773 flow_dv_remove(dev, flow);
12774 if (flow->counter) {
12775 flow_dv_counter_free(dev, flow->counter);
12779 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12781 mlx5_flow_meter_detach(priv, fm);
12785 flow_dv_aso_age_release(dev, flow->age);
12786 if (flow->geneve_tlv_option) {
12787 flow_dv_geneve_tlv_option_resource_release(dev);
12788 flow->geneve_tlv_option = 0;
12790 while (flow->dev_handles) {
12791 uint32_t tmp_idx = flow->dev_handles;
12793 dev_handle = mlx5_ipool_get(priv->sh->ipool
12794 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12797 flow->dev_handles = dev_handle->next.next;
12798 if (dev_handle->dvh.matcher)
12799 flow_dv_matcher_release(dev, dev_handle);
12800 if (dev_handle->dvh.rix_sample)
12801 flow_dv_sample_resource_release(dev, dev_handle);
12802 if (dev_handle->dvh.rix_dest_array)
12803 flow_dv_dest_array_resource_release(dev, dev_handle);
12804 if (dev_handle->dvh.rix_encap_decap)
12805 flow_dv_encap_decap_resource_release(dev,
12806 dev_handle->dvh.rix_encap_decap);
12807 if (dev_handle->dvh.modify_hdr)
12808 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12809 if (dev_handle->dvh.rix_push_vlan)
12810 flow_dv_push_vlan_action_resource_release(dev,
12812 if (dev_handle->dvh.rix_tag)
12813 flow_dv_tag_release(dev,
12814 dev_handle->dvh.rix_tag);
12815 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12816 flow_dv_fate_resource_release(dev, dev_handle);
12818 srss = dev_handle->rix_srss;
12819 if (fm && dev_handle->is_meter_flow_id &&
12820 dev_handle->split_flow_id)
12821 mlx5_ipool_free(fm->flow_ipool,
12822 dev_handle->split_flow_id);
12823 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12827 flow_dv_shared_rss_action_release(dev, srss);
12831 * Release array of hash RX queue objects.
12835 * Pointer to the Ethernet device structure.
12836 * @param[in, out] hrxqs
12837 * Array of hash RX queue objects.
12840 * Total number of references to hash RX queue objects in *hrxqs* array
12841 * after this operation.
12844 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12845 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12850 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12851 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12861 * Release all hash RX queue objects representing shared RSS action.
12864 * Pointer to the Ethernet device structure.
12865 * @param[in, out] action
12866 * Shared RSS action to remove hash RX queue objects from.
12869 * Total number of references to hash RX queue objects stored in *action*
12870 * after this operation.
12871 * Expected to be 0 if no external references held.
12874 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12875 struct mlx5_shared_action_rss *shared_rss)
12877 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12881 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12884 * Only one hash value is available for one L3+L4 combination:
12886 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12887 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12888 * same slot in mlx5_rss_hash_fields.
12891 * Pointer to the shared action RSS conf.
12892 * @param[in, out] hash_field
12893 * hash_field variable needed to be adjusted.
12899 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12900 uint64_t *hash_field)
12902 uint64_t rss_types = rss->origin.types;
12904 switch (*hash_field & ~IBV_RX_HASH_INNER) {
12905 case MLX5_RSS_HASH_IPV4:
12906 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12907 *hash_field &= ~MLX5_RSS_HASH_IPV4;
12908 if (rss_types & ETH_RSS_L3_DST_ONLY)
12909 *hash_field |= IBV_RX_HASH_DST_IPV4;
12910 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12911 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12913 *hash_field |= MLX5_RSS_HASH_IPV4;
12916 case MLX5_RSS_HASH_IPV6:
12917 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12918 *hash_field &= ~MLX5_RSS_HASH_IPV6;
12919 if (rss_types & ETH_RSS_L3_DST_ONLY)
12920 *hash_field |= IBV_RX_HASH_DST_IPV6;
12921 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12922 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12924 *hash_field |= MLX5_RSS_HASH_IPV6;
12927 case MLX5_RSS_HASH_IPV4_UDP:
12928 /* fall-through. */
12929 case MLX5_RSS_HASH_IPV6_UDP:
12930 if (rss_types & ETH_RSS_UDP) {
12931 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12932 if (rss_types & ETH_RSS_L4_DST_ONLY)
12933 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12934 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12935 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12937 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12940 case MLX5_RSS_HASH_IPV4_TCP:
12941 /* fall-through. */
12942 case MLX5_RSS_HASH_IPV6_TCP:
12943 if (rss_types & ETH_RSS_TCP) {
12944 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12945 if (rss_types & ETH_RSS_L4_DST_ONLY)
12946 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12947 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12948 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12950 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12959 * Setup shared RSS action.
12960 * Prepare set of hash RX queue objects sufficient to handle all valid
12961 * hash_fields combinations (see enum ibv_rx_hash_fields).
12964 * Pointer to the Ethernet device structure.
12965 * @param[in] action_idx
12966 * Shared RSS action ipool index.
12967 * @param[in, out] action
12968 * Partially initialized shared RSS action.
12969 * @param[out] error
12970 * Perform verbose error reporting if not NULL. Initialized in case of
12974 * 0 on success, otherwise negative errno value.
12977 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12978 uint32_t action_idx,
12979 struct mlx5_shared_action_rss *shared_rss,
12980 struct rte_flow_error *error)
12982 struct mlx5_flow_rss_desc rss_desc = { 0 };
12986 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12987 return rte_flow_error_set(error, rte_errno,
12988 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12989 "cannot setup indirection table");
12991 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12992 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12993 rss_desc.const_q = shared_rss->origin.queue;
12994 rss_desc.queue_num = shared_rss->origin.queue_num;
12995 /* Set non-zero value to indicate a shared RSS. */
12996 rss_desc.shared_rss = action_idx;
12997 rss_desc.ind_tbl = shared_rss->ind_tbl;
12998 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
13000 uint64_t hash_fields = mlx5_rss_hash_fields[i];
13003 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
13004 if (shared_rss->origin.level > 1) {
13005 hash_fields |= IBV_RX_HASH_INNER;
13008 rss_desc.tunnel = tunnel;
13009 rss_desc.hash_fields = hash_fields;
13010 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
13014 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13015 "cannot get hash queue");
13016 goto error_hrxq_new;
13018 err = __flow_dv_action_rss_hrxq_set
13019 (shared_rss, hash_fields, hrxq_idx);
13025 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13026 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13027 shared_rss->ind_tbl = NULL;
13033 * Create shared RSS action.
13036 * Pointer to the Ethernet device structure.
13038 * Shared action configuration.
13040 * RSS action specification used to create shared action.
13041 * @param[out] error
13042 * Perform verbose error reporting if not NULL. Initialized in case of
13046 * A valid shared action ID in case of success, 0 otherwise and
13047 * rte_errno is set.
13050 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13051 const struct rte_flow_indir_action_conf *conf,
13052 const struct rte_flow_action_rss *rss,
13053 struct rte_flow_error *error)
13055 struct mlx5_priv *priv = dev->data->dev_private;
13056 struct mlx5_shared_action_rss *shared_rss = NULL;
13057 void *queue = NULL;
13058 struct rte_flow_action_rss *origin;
13059 const uint8_t *rss_key;
13060 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13063 RTE_SET_USED(conf);
13064 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13066 shared_rss = mlx5_ipool_zmalloc
13067 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13068 if (!shared_rss || !queue) {
13069 rte_flow_error_set(error, ENOMEM,
13070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13071 "cannot allocate resource memory");
13072 goto error_rss_init;
13074 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13075 rte_flow_error_set(error, E2BIG,
13076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13077 "rss action number out of range");
13078 goto error_rss_init;
13080 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13081 sizeof(*shared_rss->ind_tbl),
13083 if (!shared_rss->ind_tbl) {
13084 rte_flow_error_set(error, ENOMEM,
13085 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13086 "cannot allocate resource memory");
13087 goto error_rss_init;
13089 memcpy(queue, rss->queue, queue_size);
13090 shared_rss->ind_tbl->queues = queue;
13091 shared_rss->ind_tbl->queues_n = rss->queue_num;
13092 origin = &shared_rss->origin;
13093 origin->func = rss->func;
13094 origin->level = rss->level;
13095 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13096 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13097 /* NULL RSS key indicates default RSS key. */
13098 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13099 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13100 origin->key = &shared_rss->key[0];
13101 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13102 origin->queue = queue;
13103 origin->queue_num = rss->queue_num;
13104 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13105 goto error_rss_init;
13106 rte_spinlock_init(&shared_rss->action_rss_sl);
13107 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13108 rte_spinlock_lock(&priv->shared_act_sl);
13109 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13110 &priv->rss_shared_actions, idx, shared_rss, next);
13111 rte_spinlock_unlock(&priv->shared_act_sl);
13115 if (shared_rss->ind_tbl)
13116 mlx5_free(shared_rss->ind_tbl);
13117 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13126 * Destroy the shared RSS action.
13127 * Release related hash RX queue objects.
13130 * Pointer to the Ethernet device structure.
13132 * The shared RSS action object ID to be removed.
13133 * @param[out] error
13134 * Perform verbose error reporting if not NULL. Initialized in case of
13138 * 0 on success, otherwise negative errno value.
13141 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13142 struct rte_flow_error *error)
13144 struct mlx5_priv *priv = dev->data->dev_private;
13145 struct mlx5_shared_action_rss *shared_rss =
13146 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13147 uint32_t old_refcnt = 1;
13149 uint16_t *queue = NULL;
13152 return rte_flow_error_set(error, EINVAL,
13153 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13154 "invalid shared action");
13155 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13157 return rte_flow_error_set(error, EBUSY,
13158 RTE_FLOW_ERROR_TYPE_ACTION,
13160 "shared rss hrxq has references");
13161 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13162 0, 0, __ATOMIC_ACQUIRE,
13164 return rte_flow_error_set(error, EBUSY,
13165 RTE_FLOW_ERROR_TYPE_ACTION,
13167 "shared rss has references");
13168 queue = shared_rss->ind_tbl->queues;
13169 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13171 return rte_flow_error_set(error, EBUSY,
13172 RTE_FLOW_ERROR_TYPE_ACTION,
13174 "shared rss indirection table has"
13177 rte_spinlock_lock(&priv->shared_act_sl);
13178 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13179 &priv->rss_shared_actions, idx, shared_rss, next);
13180 rte_spinlock_unlock(&priv->shared_act_sl);
13181 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13187 * Create indirect action, lock free,
13188 * (mutex should be acquired by caller).
13189 * Dispatcher for action type specific call.
13192 * Pointer to the Ethernet device structure.
13194 * Shared action configuration.
13195 * @param[in] action
13196 * Action specification used to create indirect action.
13197 * @param[out] error
13198 * Perform verbose error reporting if not NULL. Initialized in case of
13202 * A valid shared action handle in case of success, NULL otherwise and
13203 * rte_errno is set.
13205 static struct rte_flow_action_handle *
13206 flow_dv_action_create(struct rte_eth_dev *dev,
13207 const struct rte_flow_indir_action_conf *conf,
13208 const struct rte_flow_action *action,
13209 struct rte_flow_error *err)
13214 switch (action->type) {
13215 case RTE_FLOW_ACTION_TYPE_RSS:
13216 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13217 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13218 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13220 case RTE_FLOW_ACTION_TYPE_AGE:
13221 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13222 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13223 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13225 struct mlx5_aso_age_action *aso_age =
13226 flow_aso_age_get_by_idx(dev, ret);
13228 if (!aso_age->age_params.context)
13229 aso_age->age_params.context =
13230 (void *)(uintptr_t)idx;
13234 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13235 NULL, "action type not supported");
13238 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13242 * Destroy the indirect action.
13243 * Release action related resources on the NIC and the memory.
13244 * Lock free, (mutex should be acquired by caller).
13245 * Dispatcher for action type specific call.
13248 * Pointer to the Ethernet device structure.
13249 * @param[in] handle
13250 * The indirect action object handle to be removed.
13251 * @param[out] error
13252 * Perform verbose error reporting if not NULL. Initialized in case of
13256 * 0 on success, otherwise negative errno value.
13259 flow_dv_action_destroy(struct rte_eth_dev *dev,
13260 struct rte_flow_action_handle *handle,
13261 struct rte_flow_error *error)
13263 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13264 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13265 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13269 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13270 return __flow_dv_action_rss_release(dev, idx, error);
13271 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13272 ret = flow_dv_aso_age_release(dev, idx);
13275 * In this case, the last flow has a reference will
13276 * actually release the age action.
13278 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13279 " released with references %d.", idx, ret);
13282 return rte_flow_error_set(error, ENOTSUP,
13283 RTE_FLOW_ERROR_TYPE_ACTION,
13285 "action type not supported");
13290 * Updates in place shared RSS action configuration.
13293 * Pointer to the Ethernet device structure.
13295 * The shared RSS action object ID to be updated.
13296 * @param[in] action_conf
13297 * RSS action specification used to modify *shared_rss*.
13298 * @param[out] error
13299 * Perform verbose error reporting if not NULL. Initialized in case of
13303 * 0 on success, otherwise negative errno value.
13304 * @note: currently only support update of RSS queues.
13307 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13308 const struct rte_flow_action_rss *action_conf,
13309 struct rte_flow_error *error)
13311 struct mlx5_priv *priv = dev->data->dev_private;
13312 struct mlx5_shared_action_rss *shared_rss =
13313 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13315 void *queue = NULL;
13316 uint16_t *queue_old = NULL;
13317 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13320 return rte_flow_error_set(error, EINVAL,
13321 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13322 "invalid shared action to update");
13323 if (priv->obj_ops.ind_table_modify == NULL)
13324 return rte_flow_error_set(error, ENOTSUP,
13325 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13326 "cannot modify indirection table");
13327 queue = mlx5_malloc(MLX5_MEM_ZERO,
13328 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13331 return rte_flow_error_set(error, ENOMEM,
13332 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13334 "cannot allocate resource memory");
13335 memcpy(queue, action_conf->queue, queue_size);
13336 MLX5_ASSERT(shared_rss->ind_tbl);
13337 rte_spinlock_lock(&shared_rss->action_rss_sl);
13338 queue_old = shared_rss->ind_tbl->queues;
13339 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13340 queue, action_conf->queue_num, true);
13343 ret = rte_flow_error_set(error, rte_errno,
13344 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13345 "cannot update indirection table");
13347 mlx5_free(queue_old);
13348 shared_rss->origin.queue = queue;
13349 shared_rss->origin.queue_num = action_conf->queue_num;
13351 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13356 * Updates in place shared action configuration, lock free,
13357 * (mutex should be acquired by caller).
13360 * Pointer to the Ethernet device structure.
13361 * @param[in] handle
13362 * The indirect action object handle to be updated.
13363 * @param[in] update
13364 * Action specification used to modify the action pointed by *handle*.
13365 * *update* could be of same type with the action pointed by the *handle*
13366 * handle argument, or some other structures like a wrapper, depending on
13367 * the indirect action type.
13368 * @param[out] error
13369 * Perform verbose error reporting if not NULL. Initialized in case of
13373 * 0 on success, otherwise negative errno value.
13376 flow_dv_action_update(struct rte_eth_dev *dev,
13377 struct rte_flow_action_handle *handle,
13378 const void *update,
13379 struct rte_flow_error *err)
13381 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13382 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13383 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13384 const void *action_conf;
13387 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13388 action_conf = ((const struct rte_flow_action *)update)->conf;
13389 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13391 return rte_flow_error_set(err, ENOTSUP,
13392 RTE_FLOW_ERROR_TYPE_ACTION,
13394 "action type update not supported");
13399 flow_dv_action_query(struct rte_eth_dev *dev,
13400 const struct rte_flow_action_handle *handle, void *data,
13401 struct rte_flow_error *error)
13403 struct mlx5_age_param *age_param;
13404 struct rte_flow_query_age *resp;
13405 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13406 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13407 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13410 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13411 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13413 resp->aged = __atomic_load_n(&age_param->state,
13414 __ATOMIC_RELAXED) == AGE_TMOUT ?
13416 resp->sec_since_last_hit_valid = !resp->aged;
13417 if (resp->sec_since_last_hit_valid)
13418 resp->sec_since_last_hit = __atomic_load_n
13419 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13422 return rte_flow_error_set(error, ENOTSUP,
13423 RTE_FLOW_ERROR_TYPE_ACTION,
13425 "action type query not supported");
13430 * Query a dv flow rule for its statistics via devx.
13433 * Pointer to Ethernet device.
13435 * Pointer to the sub flow.
13437 * data retrieved by the query.
13438 * @param[out] error
13439 * Perform verbose error reporting if not NULL.
13442 * 0 on success, a negative errno value otherwise and rte_errno is set.
13445 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13446 void *data, struct rte_flow_error *error)
13448 struct mlx5_priv *priv = dev->data->dev_private;
13449 struct rte_flow_query_count *qc = data;
13451 if (!priv->config.devx)
13452 return rte_flow_error_set(error, ENOTSUP,
13453 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13455 "counters are not supported");
13456 if (flow->counter) {
13457 uint64_t pkts, bytes;
13458 struct mlx5_flow_counter *cnt;
13460 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13462 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13466 return rte_flow_error_set(error, -err,
13467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13468 NULL, "cannot read counters");
13471 qc->hits = pkts - cnt->hits;
13472 qc->bytes = bytes - cnt->bytes;
13475 cnt->bytes = bytes;
13479 return rte_flow_error_set(error, EINVAL,
13480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13482 "counters are not available");
13486 * Query a flow rule AGE action for aging information.
13489 * Pointer to Ethernet device.
13491 * Pointer to the sub flow.
13493 * data retrieved by the query.
13494 * @param[out] error
13495 * Perform verbose error reporting if not NULL.
13498 * 0 on success, a negative errno value otherwise and rte_errno is set.
13501 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13502 void *data, struct rte_flow_error *error)
13504 struct rte_flow_query_age *resp = data;
13505 struct mlx5_age_param *age_param;
13508 struct mlx5_aso_age_action *act =
13509 flow_aso_age_get_by_idx(dev, flow->age);
13511 age_param = &act->age_params;
13512 } else if (flow->counter) {
13513 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13515 if (!age_param || !age_param->timeout)
13516 return rte_flow_error_set
13518 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13519 NULL, "cannot read age data");
13521 return rte_flow_error_set(error, EINVAL,
13522 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13523 NULL, "age data not available");
13525 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13527 resp->sec_since_last_hit_valid = !resp->aged;
13528 if (resp->sec_since_last_hit_valid)
13529 resp->sec_since_last_hit = __atomic_load_n
13530 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13537 * @see rte_flow_query()
13538 * @see rte_flow_ops
13541 flow_dv_query(struct rte_eth_dev *dev,
13542 struct rte_flow *flow __rte_unused,
13543 const struct rte_flow_action *actions __rte_unused,
13544 void *data __rte_unused,
13545 struct rte_flow_error *error __rte_unused)
13549 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13550 switch (actions->type) {
13551 case RTE_FLOW_ACTION_TYPE_VOID:
13553 case RTE_FLOW_ACTION_TYPE_COUNT:
13554 ret = flow_dv_query_count(dev, flow, data, error);
13556 case RTE_FLOW_ACTION_TYPE_AGE:
13557 ret = flow_dv_query_age(dev, flow, data, error);
13560 return rte_flow_error_set(error, ENOTSUP,
13561 RTE_FLOW_ERROR_TYPE_ACTION,
13563 "action not supported");
13570 * Destroy the meter table set.
13571 * Lock free, (mutex should be acquired by caller).
13574 * Pointer to Ethernet device.
13576 * Pointer to the meter table set.
13582 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13583 struct mlx5_meter_domains_infos *tbl)
13585 struct mlx5_priv *priv = dev->data->dev_private;
13586 struct mlx5_meter_domains_infos *mtd =
13587 (struct mlx5_meter_domains_infos *)tbl;
13589 if (!mtd || !priv->config.dv_flow_en)
13591 if (mtd->egress.tbl)
13592 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13593 if (mtd->egress.sfx_tbl)
13594 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13595 if (mtd->ingress.tbl)
13596 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13597 if (mtd->ingress.sfx_tbl)
13598 flow_dv_tbl_resource_release(MLX5_SH(dev),
13599 mtd->ingress.sfx_tbl);
13600 if (mtd->transfer.tbl)
13601 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13602 if (mtd->transfer.sfx_tbl)
13603 flow_dv_tbl_resource_release(MLX5_SH(dev),
13604 mtd->transfer.sfx_tbl);
13609 /* Number of meter flow actions, count and jump or count and drop. */
13610 #define METER_ACTIONS 2
13613 * Create specify domain meter table and suffix table.
13616 * Pointer to Ethernet device.
13617 * @param[in,out] mtb
13618 * Pointer to DV meter table set.
13619 * @param[in] egress
13621 * @param[in] transfer
13625 * 0 on success, -1 otherwise.
13628 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13629 struct mlx5_meter_domains_infos *mtb,
13630 uint8_t egress, uint8_t transfer)
13632 struct rte_flow_error error;
13633 struct mlx5_meter_domain_info *dtb;
13636 dtb = &mtb->transfer;
13638 dtb = &mtb->egress;
13640 dtb = &mtb->ingress;
13641 /* Create the meter table with METER level. */
13642 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13643 egress, transfer, false, NULL, 0,
13646 DRV_LOG(ERR, "Failed to create meter policer table.");
13649 /* Create the meter suffix table with SUFFIX level. */
13650 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13651 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13652 egress, transfer, false, NULL, 0,
13654 if (!dtb->sfx_tbl) {
13655 DRV_LOG(ERR, "Failed to create meter suffix table.");
13662 * Create the needed meter and suffix tables.
13663 * Lock free, (mutex should be acquired by caller).
13666 * Pointer to Ethernet device.
13669 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13671 static struct mlx5_meter_domains_infos *
13672 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13674 struct mlx5_priv *priv = dev->data->dev_private;
13675 struct mlx5_meter_domains_infos *mtb;
13678 if (!priv->mtr_en) {
13679 rte_errno = ENOTSUP;
13682 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13684 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13687 /* Egress meter table. */
13688 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13690 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13693 /* Ingress meter table. */
13694 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13696 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13699 /* FDB meter table. */
13700 if (priv->config.dv_esw_en) {
13701 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13703 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13709 flow_dv_destroy_mtr_tbl(dev, mtb);
13714 * Destroy the meter table matchers.
13715 * Lock free, (mutex should be acquired by caller).
13718 * Pointer to Ethernet device.
13719 * @param[in,out] dtb
13720 * Pointer to DV meter table.
13726 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13727 struct mlx5_meter_domain_info *dtb)
13729 struct mlx5_priv *priv = dev->data->dev_private;
13730 struct mlx5_flow_tbl_data_entry *tbl;
13732 if (!priv->config.dv_flow_en)
13734 if (dtb->drop_matcher) {
13735 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13736 mlx5_cache_unregister(&tbl->matchers,
13737 &dtb->drop_matcher->entry);
13738 dtb->drop_matcher = NULL;
13740 if (dtb->color_matcher) {
13741 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13742 mlx5_cache_unregister(&tbl->matchers,
13743 &dtb->color_matcher->entry);
13744 dtb->color_matcher = NULL;
13750 * Create the matchers for meter table.
13753 * Pointer to Ethernet device.
13754 * @param[in] color_reg_c_idx
13755 * Reg C index for color match.
13756 * @param[in] mtr_id_reg_c_idx
13757 * Reg C index for meter_id match.
13758 * @param[in] mtr_id_mask
13759 * Mask for meter_id match criteria.
13760 * @param[in,out] dtb
13761 * Pointer to DV meter table.
13762 * @param[out] error
13763 * Perform verbose error reporting if not NULL.
13766 * 0 on success, a negative errno value otherwise and rte_errno is set.
13769 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13770 uint32_t color_reg_c_idx,
13771 uint32_t mtr_id_reg_c_idx,
13772 uint32_t mtr_id_mask,
13773 struct mlx5_meter_domain_info *dtb,
13774 struct rte_flow_error *error)
13776 struct mlx5_priv *priv = dev->data->dev_private;
13777 struct mlx5_flow_tbl_data_entry *tbl_data;
13778 struct mlx5_cache_entry *entry;
13779 struct mlx5_flow_dv_matcher matcher = {
13781 .size = sizeof(matcher.mask.buf) -
13782 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13786 struct mlx5_flow_dv_match_params value = {
13787 .size = sizeof(value.buf) -
13788 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13790 struct mlx5_flow_cb_ctx ctx = {
13794 uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13796 tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13797 if (!dtb->drop_matcher) {
13798 /* Create matchers for Drop. */
13799 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13800 mtr_id_reg_c_idx, 0, mtr_id_mask);
13801 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13802 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13803 matcher.mask.size);
13804 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13806 DRV_LOG(ERR, "Failed to register meter drop matcher.");
13809 dtb->drop_matcher =
13810 container_of(entry, struct mlx5_flow_dv_matcher, entry);
13812 if (!dtb->color_matcher) {
13813 /* Create matchers for Color + meter_id. */
13814 if (priv->mtr_reg_share) {
13815 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13816 color_reg_c_idx, 0,
13817 (mtr_id_mask | color_mask));
13819 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13820 color_reg_c_idx, 0, color_mask);
13821 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13822 mtr_id_reg_c_idx, 0, mtr_id_mask);
13824 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13825 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13826 matcher.mask.size);
13827 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13829 DRV_LOG(ERR, "Failed to register meter color matcher.");
13832 dtb->color_matcher =
13833 container_of(entry, struct mlx5_flow_dv_matcher, entry);
13839 * Destroy domain policer rule.
13842 * Pointer to Ethernet device.
13844 * Pointer to domain table.
13847 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13848 struct mlx5_meter_domain_info *dt)
13850 if (dt->drop_rule) {
13851 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13852 dt->drop_rule = NULL;
13854 if (dt->green_rule) {
13855 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13856 dt->green_rule = NULL;
13858 flow_dv_destroy_mtr_matchers(dev, dt);
13859 if (dt->jump_actn) {
13860 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13861 dt->jump_actn = NULL;
13866 * Destroy policer rules.
13869 * Pointer to Ethernet device.
13871 * Pointer to flow meter structure.
13873 * Pointer to flow attributes.
13879 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13880 const struct mlx5_flow_meter_info *fm,
13881 const struct rte_flow_attr *attr)
13883 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13888 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13890 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13891 if (attr->transfer)
13892 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13897 * Create specify domain meter policer rule.
13900 * Pointer to Ethernet device.
13902 * Pointer to flow meter structure.
13903 * @param[in] mtr_idx
13906 * Pointer to DV meter table set.
13907 * @param[out] drop_rule
13908 * The address of pointer saving drop rule.
13909 * @param[out] color_rule
13910 * The address of pointer saving green rule.
13913 * 0 on success, -1 otherwise.
13916 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13917 struct mlx5_flow_meter_info *fm,
13919 struct mlx5_meter_domain_info *dtb,
13923 struct mlx5_priv *priv = dev->data->dev_private;
13924 struct mlx5_flow_dv_match_params matcher = {
13925 .size = sizeof(matcher.buf) -
13926 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13928 struct mlx5_flow_dv_match_params value = {
13929 .size = sizeof(value.buf) -
13930 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13932 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13933 struct rte_flow_error error;
13934 uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13936 uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13938 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13939 uint32_t mtr_id_mask =
13940 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13941 void *actions[METER_ACTIONS];
13945 /* Create jump action. */
13946 if (!dtb->jump_actn)
13947 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13948 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13950 DRV_LOG(ERR, "Failed to create policer jump action.");
13953 /* Prepare matchers. */
13954 if (!dtb->drop_matcher || !dtb->color_matcher) {
13955 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13956 mtr_id_reg_c, mtr_id_mask,
13959 DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13963 /* Create Drop flow, matching meter_id only. */
13965 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13966 (mtr_idx << mtr_id_offset), UINT32_MAX);
13967 if (mtb->drop_count)
13968 actions[i++] = mtb->drop_count;
13969 actions[i++] = priv->sh->dr_drop_action;
13970 ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13971 (void *)&value, i, actions, drop_rule);
13973 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13976 /* Create flow matching Green color + meter_id. */
13978 if (priv->mtr_reg_share) {
13979 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13980 ((mtr_idx << mtr_id_offset) |
13981 rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13984 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13985 rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13987 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13988 mtr_idx, UINT32_MAX);
13990 if (mtb->green_count)
13991 actions[i++] = mtb->green_count;
13992 actions[i++] = dtb->jump_actn;
13993 ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
13994 (void *)&value, i, actions, green_rule);
13996 DRV_LOG(ERR, "Failed to create meter policer color rule.");
14006 * Prepare policer rules for all domains.
14007 * If meter already initialized, this will replace all old rules with new ones.
14010 * Pointer to Ethernet device.
14012 * Pointer to flow meter structure.
14014 * Pointer to flow attributes.
14017 * 0 on success, -1 otherwise.
14020 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
14021 struct mlx5_flow_meter_info *fm,
14022 const struct rte_flow_attr *attr)
14024 struct mlx5_priv *priv = dev->data->dev_private;
14025 struct mlx5_meter_domains_infos *mtb = fm->mfts;
14026 bool initialized = false;
14027 struct mlx5_flow_counter *cnt;
14028 void *egress_drop_rule = NULL;
14029 void *egress_green_rule = NULL;
14030 void *ingress_drop_rule = NULL;
14031 void *ingress_green_rule = NULL;
14032 void *transfer_drop_rule = NULL;
14033 void *transfer_green_rule = NULL;
14037 /* Get the statistics counters for green/drop. */
14038 if (fm->policer_stats.pass_cnt) {
14039 cnt = flow_dv_counter_get_by_idx(dev,
14040 fm->policer_stats.pass_cnt,
14042 mtb->green_count = cnt->action;
14044 mtb->green_count = NULL;
14046 if (fm->policer_stats.drop_cnt) {
14047 cnt = flow_dv_counter_get_by_idx(dev,
14048 fm->policer_stats.drop_cnt,
14050 mtb->drop_count = cnt->action;
14052 mtb->drop_count = NULL;
14055 * If flow meter has been initialized, all policer rules
14056 * are created. So can get if meter initialized by checking
14057 * any policer rule.
14059 if (mtb->egress.drop_rule)
14060 initialized = true;
14061 if (priv->sh->meter_aso_en) {
14062 struct mlx5_aso_mtr *aso_mtr = NULL;
14063 struct mlx5_aso_mtr_pool *pool;
14065 aso_mtr = container_of(fm, struct mlx5_aso_mtr, fm);
14066 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
14067 mtrs[aso_mtr->offset]);
14068 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, aso_mtr->offset);
14070 struct mlx5_legacy_flow_meter *legacy_fm;
14072 legacy_fm = container_of(fm, struct mlx5_legacy_flow_meter, fm);
14073 mtr_idx = legacy_fm->idx;
14075 if (attr->egress) {
14076 ret = flow_dv_create_policer_forward_rule(dev,
14077 fm, mtr_idx, &mtb->egress,
14078 &egress_drop_rule, &egress_green_rule);
14080 DRV_LOG(ERR, "Failed to create egress policer.");
14084 if (attr->ingress) {
14085 ret = flow_dv_create_policer_forward_rule(dev,
14086 fm, mtr_idx, &mtb->ingress,
14087 &ingress_drop_rule, &ingress_green_rule);
14089 DRV_LOG(ERR, "Failed to create ingress policer.");
14093 if (attr->transfer) {
14094 ret = flow_dv_create_policer_forward_rule(dev,
14095 fm, mtr_idx, &mtb->transfer,
14096 &transfer_drop_rule, &transfer_green_rule);
14098 DRV_LOG(ERR, "Failed to create transfer policer.");
14102 /* Replace old flows if existing. */
14103 if (mtb->egress.drop_rule)
14104 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
14105 if (mtb->egress.green_rule)
14106 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
14107 if (mtb->ingress.drop_rule)
14108 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
14109 if (mtb->ingress.green_rule)
14110 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
14111 if (mtb->transfer.drop_rule)
14112 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
14113 if (mtb->transfer.green_rule)
14114 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
14115 mtb->egress.drop_rule = egress_drop_rule;
14116 mtb->egress.green_rule = egress_green_rule;
14117 mtb->ingress.drop_rule = ingress_drop_rule;
14118 mtb->ingress.green_rule = ingress_green_rule;
14119 mtb->transfer.drop_rule = transfer_drop_rule;
14120 mtb->transfer.green_rule = transfer_green_rule;
14123 if (egress_drop_rule)
14124 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
14125 if (egress_green_rule)
14126 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
14127 if (ingress_drop_rule)
14128 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
14129 if (ingress_green_rule)
14130 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
14131 if (transfer_drop_rule)
14132 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
14133 if (transfer_green_rule)
14134 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
14136 flow_dv_destroy_policer_rules(dev, fm, attr);
14141 * Validate the batch counter support in root table.
14143 * Create a simple flow with invalid counter and drop action on root table to
14144 * validate if batch counter with offset on root table is supported or not.
14147 * Pointer to rte_eth_dev structure.
14150 * 0 on success, a negative errno value otherwise and rte_errno is set.
14153 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
14155 struct mlx5_priv *priv = dev->data->dev_private;
14156 struct mlx5_dev_ctx_shared *sh = priv->sh;
14157 struct mlx5_flow_dv_match_params mask = {
14158 .size = sizeof(mask.buf),
14160 struct mlx5_flow_dv_match_params value = {
14161 .size = sizeof(value.buf),
14163 struct mlx5dv_flow_matcher_attr dv_attr = {
14164 .type = IBV_FLOW_ATTR_NORMAL,
14166 .match_criteria_enable = 0,
14167 .match_mask = (void *)&mask,
14169 void *actions[2] = { 0 };
14170 struct mlx5_flow_tbl_resource *tbl = NULL;
14171 struct mlx5_devx_obj *dcs = NULL;
14172 void *matcher = NULL;
14176 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
14179 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
14182 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
14186 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
14187 priv->drop_queue.hrxq->action;
14188 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
14189 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
14193 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
14197 * If batch counter with offset is not supported, the driver will not
14198 * validate the invalid offset value, flow create should success.
14199 * In this case, it means batch counter is not supported in root table.
14201 * Otherwise, if flow create is failed, counter offset is supported.
14204 DRV_LOG(INFO, "Batch counter is not supported in root "
14205 "table. Switch to fallback mode.");
14206 rte_errno = ENOTSUP;
14208 claim_zero(mlx5_flow_os_destroy_flow(flow));
14210 /* Check matcher to make sure validate fail at flow create. */
14211 if (!matcher || (matcher && errno != EINVAL))
14212 DRV_LOG(ERR, "Unexpected error in counter offset "
14213 "support detection");
14217 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14219 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14221 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14223 claim_zero(mlx5_devx_cmd_destroy(dcs));
14228 * Query a devx counter.
14231 * Pointer to the Ethernet device structure.
14233 * Index to the flow counter.
14235 * Set to clear the counter statistics.
14237 * The statistics value of packets.
14238 * @param[out] bytes
14239 * The statistics value of bytes.
14242 * 0 on success, otherwise return -1.
14245 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14246 uint64_t *pkts, uint64_t *bytes)
14248 struct mlx5_priv *priv = dev->data->dev_private;
14249 struct mlx5_flow_counter *cnt;
14250 uint64_t inn_pkts, inn_bytes;
14253 if (!priv->config.devx)
14256 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14259 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14260 *pkts = inn_pkts - cnt->hits;
14261 *bytes = inn_bytes - cnt->bytes;
14263 cnt->hits = inn_pkts;
14264 cnt->bytes = inn_bytes;
14270 * Get aged-out flows.
14273 * Pointer to the Ethernet device structure.
14274 * @param[in] context
14275 * The address of an array of pointers to the aged-out flows contexts.
14276 * @param[in] nb_contexts
14277 * The length of context array pointers.
14278 * @param[out] error
14279 * Perform verbose error reporting if not NULL. Initialized in case of
14283 * how many contexts get in success, otherwise negative errno value.
14284 * if nb_contexts is 0, return the amount of all aged contexts.
14285 * if nb_contexts is not 0 , return the amount of aged flows reported
14286 * in the context array.
14287 * @note: only stub for now
14290 flow_get_aged_flows(struct rte_eth_dev *dev,
14292 uint32_t nb_contexts,
14293 struct rte_flow_error *error)
14295 struct mlx5_priv *priv = dev->data->dev_private;
14296 struct mlx5_age_info *age_info;
14297 struct mlx5_age_param *age_param;
14298 struct mlx5_flow_counter *counter;
14299 struct mlx5_aso_age_action *act;
14302 if (nb_contexts && !context)
14303 return rte_flow_error_set(error, EINVAL,
14304 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14305 NULL, "empty context");
14306 age_info = GET_PORT_AGE_INFO(priv);
14307 rte_spinlock_lock(&age_info->aged_sl);
14308 LIST_FOREACH(act, &age_info->aged_aso, next) {
14311 context[nb_flows - 1] =
14312 act->age_params.context;
14313 if (!(--nb_contexts))
14317 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14320 age_param = MLX5_CNT_TO_AGE(counter);
14321 context[nb_flows - 1] = age_param->context;
14322 if (!(--nb_contexts))
14326 rte_spinlock_unlock(&age_info->aged_sl);
14327 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14332 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14335 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14337 return flow_dv_counter_alloc(dev, 0);
14341 * Validate indirect action.
14342 * Dispatcher for action type specific validation.
14345 * Pointer to the Ethernet device structure.
14347 * Shared action configuration.
14348 * @param[in] action
14349 * The indirect action object to validate.
14350 * @param[out] error
14351 * Perform verbose error reporting if not NULL. Initialized in case of
14355 * 0 on success, otherwise negative errno value.
14358 flow_dv_action_validate(struct rte_eth_dev *dev,
14359 const struct rte_flow_indir_action_conf *conf,
14360 const struct rte_flow_action *action,
14361 struct rte_flow_error *err)
14363 struct mlx5_priv *priv = dev->data->dev_private;
14365 RTE_SET_USED(conf);
14366 switch (action->type) {
14367 case RTE_FLOW_ACTION_TYPE_RSS:
14369 * priv->obj_ops is set according to driver capabilities.
14370 * When DevX capabilities are
14371 * sufficient, it is set to devx_obj_ops.
14372 * Otherwise, it is set to ibv_obj_ops.
14373 * ibv_obj_ops doesn't support ind_table_modify operation.
14374 * In this case the shared RSS action can't be used.
14376 if (priv->obj_ops.ind_table_modify == NULL)
14377 return rte_flow_error_set
14379 RTE_FLOW_ERROR_TYPE_ACTION,
14381 "shared RSS action not supported");
14382 return mlx5_validate_action_rss(dev, action, err);
14383 case RTE_FLOW_ACTION_TYPE_AGE:
14384 if (!priv->sh->aso_age_mng)
14385 return rte_flow_error_set(err, ENOTSUP,
14386 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14388 "shared age action not supported");
14389 return flow_dv_validate_action_age(0, action, dev, err);
14391 return rte_flow_error_set(err, ENOTSUP,
14392 RTE_FLOW_ERROR_TYPE_ACTION,
14394 "action type not supported");
14399 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14401 struct mlx5_priv *priv = dev->data->dev_private;
14404 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14405 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14410 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14411 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14415 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14416 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14423 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14424 .validate = flow_dv_validate,
14425 .prepare = flow_dv_prepare,
14426 .translate = flow_dv_translate,
14427 .apply = flow_dv_apply,
14428 .remove = flow_dv_remove,
14429 .destroy = flow_dv_destroy,
14430 .query = flow_dv_query,
14431 .create_mtr_tbls = flow_dv_create_mtr_tbl,
14432 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14433 .prepare_policer_rules = flow_dv_prepare_policer_rules,
14434 .destroy_policer_rules = flow_dv_destroy_policer_rules,
14435 .create_meter = flow_dv_mtr_alloc,
14436 .free_meter = flow_dv_aso_mtr_release_to_pool,
14437 .counter_alloc = flow_dv_counter_allocate,
14438 .counter_free = flow_dv_counter_free,
14439 .counter_query = flow_dv_counter_query,
14440 .get_aged_flows = flow_get_aged_flows,
14441 .action_validate = flow_dv_action_validate,
14442 .action_create = flow_dv_action_create,
14443 .action_destroy = flow_dv_action_destroy,
14444 .action_update = flow_dv_action_update,
14445 .action_query = flow_dv_action_query,
14446 .sync_domain = flow_dv_sync_domain,
14449 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */