1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
78 struct mlx5_flow_tbl_resource *tbl);
81 * Initialize flow attributes structure according to flow items' types.
83 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
84 * mode. For tunnel mode, the items to be modified are the outermost ones.
87 * Pointer to item specification.
89 * Pointer to flow attributes structure.
91 * Pointer to the sub flow.
92 * @param[in] tunnel_decap
93 * Whether action is after tunnel decapsulation.
96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
97 struct mlx5_flow *dev_flow, bool tunnel_decap)
99 uint64_t layers = dev_flow->handle->layers;
102 * If layers is already initialized, it means this dev_flow is the
103 * suffix flow, the layers flags is set by the prefix flow. Need to
104 * use the layer flags from prefix flow as the suffix flow may not
105 * have the user defined items as the flow is split.
108 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
112 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
114 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
119 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
120 uint8_t next_protocol = 0xff;
121 switch (item->type) {
122 case RTE_FLOW_ITEM_TYPE_GRE:
123 case RTE_FLOW_ITEM_TYPE_NVGRE:
124 case RTE_FLOW_ITEM_TYPE_VXLAN:
125 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
126 case RTE_FLOW_ITEM_TYPE_GENEVE:
127 case RTE_FLOW_ITEM_TYPE_MPLS:
131 case RTE_FLOW_ITEM_TYPE_IPV4:
134 if (item->mask != NULL &&
135 ((const struct rte_flow_item_ipv4 *)
136 item->mask)->hdr.next_proto_id)
138 ((const struct rte_flow_item_ipv4 *)
139 (item->spec))->hdr.next_proto_id &
140 ((const struct rte_flow_item_ipv4 *)
141 (item->mask))->hdr.next_proto_id;
142 if ((next_protocol == IPPROTO_IPIP ||
143 next_protocol == IPPROTO_IPV6) && tunnel_decap)
146 case RTE_FLOW_ITEM_TYPE_IPV6:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv6 *)
151 item->mask)->hdr.proto)
153 ((const struct rte_flow_item_ipv6 *)
154 (item->spec))->hdr.proto &
155 ((const struct rte_flow_item_ipv6 *)
156 (item->mask))->hdr.proto;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_UDP:
165 case RTE_FLOW_ITEM_TYPE_TCP:
177 * Convert rte_mtr_color to mlx5 color.
186 rte_col_2_mlx5_col(enum rte_color rcol)
189 case RTE_COLOR_GREEN:
190 return MLX5_FLOW_COLOR_GREEN;
191 case RTE_COLOR_YELLOW:
192 return MLX5_FLOW_COLOR_YELLOW;
194 return MLX5_FLOW_COLOR_RED;
198 return MLX5_FLOW_COLOR_UNDEFINED;
201 struct field_modify_info {
202 uint32_t size; /* Size of field in protocol header, in bytes. */
203 uint32_t offset; /* Offset of field in protocol header, in bytes. */
204 enum mlx5_modification_field id;
207 struct field_modify_info modify_eth[] = {
208 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
209 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
210 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
211 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
215 struct field_modify_info modify_vlan_out_first_vid[] = {
216 /* Size in bits !!! */
217 {12, 0, MLX5_MODI_OUT_FIRST_VID},
221 struct field_modify_info modify_ipv4[] = {
222 {1, 1, MLX5_MODI_OUT_IP_DSCP},
223 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
224 {4, 12, MLX5_MODI_OUT_SIPV4},
225 {4, 16, MLX5_MODI_OUT_DIPV4},
229 struct field_modify_info modify_ipv6[] = {
230 {1, 0, MLX5_MODI_OUT_IP_DSCP},
231 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
232 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
233 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
234 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
235 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
236 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
237 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
238 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
239 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
243 struct field_modify_info modify_udp[] = {
244 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
245 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
249 struct field_modify_info modify_tcp[] = {
250 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
251 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
252 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
253 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
259 uint8_t next_protocol, uint64_t *item_flags,
262 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
263 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
264 if (next_protocol == IPPROTO_IPIP) {
265 *item_flags |= MLX5_FLOW_LAYER_IPIP;
268 if (next_protocol == IPPROTO_IPV6) {
269 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
275 * Acquire the synchronizing object to protect multithreaded access
276 * to shared dv context. Lock occurs only if context is actually
277 * shared, i.e. we have multiport IB device and representors are
281 * Pointer to the rte_eth_dev structure.
284 flow_dv_shared_lock(struct rte_eth_dev *dev)
286 struct mlx5_priv *priv = dev->data->dev_private;
287 struct mlx5_ibv_shared *sh = priv->sh;
289 if (sh->dv_refcnt > 1) {
292 ret = pthread_mutex_lock(&sh->dv_mutex);
299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
301 struct mlx5_priv *priv = dev->data->dev_private;
302 struct mlx5_ibv_shared *sh = priv->sh;
304 if (sh->dv_refcnt > 1) {
307 ret = pthread_mutex_unlock(&sh->dv_mutex);
313 /* Update VLAN's VID/PCP based on input rte_flow_action.
316 * Pointer to struct rte_flow_action.
318 * Pointer to struct rte_vlan_hdr.
321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
322 struct rte_vlan_hdr *vlan)
325 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
327 ((const struct rte_flow_action_of_set_vlan_pcp *)
328 action->conf)->vlan_pcp;
329 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
330 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
331 vlan->vlan_tci |= vlan_tci;
332 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
333 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
334 vlan->vlan_tci |= rte_be_to_cpu_16
335 (((const struct rte_flow_action_of_set_vlan_vid *)
336 action->conf)->vlan_vid);
341 * Fetch 1, 2, 3 or 4 byte field from the byte array
342 * and return as unsigned integer in host-endian format.
345 * Pointer to data array.
347 * Size of field to extract.
350 * converted field in host endian format.
352 static inline uint32_t
353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
362 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = (ret << 8) | *(data + sizeof(uint16_t));
369 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
380 * Convert modify-header action to DV specification.
382 * Data length of each action is determined by provided field description
383 * and the item mask. Data bit offset and width of each action is determined
384 * by provided item mask.
387 * Pointer to item specification.
389 * Pointer to field modification information.
390 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
394 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
395 * Negative offset value sets the same offset as source offset.
396 * size field is ignored, value is taken from source field.
397 * @param[in,out] resource
398 * Pointer to the modify-header resource.
400 * Type of modification.
402 * Pointer to the error structure.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 flow_dv_convert_modify_action(struct rte_flow_item *item,
409 struct field_modify_info *field,
410 struct field_modify_info *dcopy,
411 struct mlx5_flow_dv_modify_hdr_resource *resource,
412 uint32_t type, struct rte_flow_error *error)
414 uint32_t i = resource->actions_num;
415 struct mlx5_modification_cmd *actions = resource->actions;
418 * The item and mask are provided in big-endian format.
419 * The fields should be presented as in big-endian format either.
420 * Mask must be always present, it defines the actual field width.
422 MLX5_ASSERT(item->mask);
423 MLX5_ASSERT(field->size);
430 if (i >= MLX5_MAX_MODIFY_NUM)
431 return rte_flow_error_set(error, EINVAL,
432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
433 "too many items to modify");
434 /* Fetch variable byte size mask from the array. */
435 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
436 field->offset, field->size);
441 /* Deduce actual data width in bits from mask value. */
442 off_b = rte_bsf32(mask);
443 size_b = sizeof(uint32_t) * CHAR_BIT -
444 off_b - __builtin_clz(mask);
446 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
447 actions[i] = (struct mlx5_modification_cmd) {
453 /* Convert entire record to expected big-endian format. */
454 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
455 if (type == MLX5_MODIFICATION_TYPE_COPY) {
457 actions[i].dst_field = dcopy->id;
458 actions[i].dst_offset =
459 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
460 /* Convert entire record to big-endian format. */
461 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
463 MLX5_ASSERT(item->spec);
464 data = flow_dv_fetch_field((const uint8_t *)item->spec +
465 field->offset, field->size);
466 /* Shift out the trailing masked bits from data. */
467 data = (data & mask) >> off_b;
468 actions[i].data1 = rte_cpu_to_be_32(data);
472 } while (field->size);
473 if (resource->actions_num == i)
474 return rte_flow_error_set(error, EINVAL,
475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
476 "invalid modification flow item");
477 resource->actions_num = i;
482 * Convert modify-header set IPv4 address action to DV specification.
484 * @param[in,out] resource
485 * Pointer to the modify-header resource.
487 * Pointer to action specification.
489 * Pointer to the error structure.
492 * 0 on success, a negative errno value otherwise and rte_errno is set.
495 flow_dv_convert_action_modify_ipv4
496 (struct mlx5_flow_dv_modify_hdr_resource *resource,
497 const struct rte_flow_action *action,
498 struct rte_flow_error *error)
500 const struct rte_flow_action_set_ipv4 *conf =
501 (const struct rte_flow_action_set_ipv4 *)(action->conf);
502 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
503 struct rte_flow_item_ipv4 ipv4;
504 struct rte_flow_item_ipv4 ipv4_mask;
506 memset(&ipv4, 0, sizeof(ipv4));
507 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
508 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
509 ipv4.hdr.src_addr = conf->ipv4_addr;
510 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
512 ipv4.hdr.dst_addr = conf->ipv4_addr;
513 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
516 item.mask = &ipv4_mask;
517 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
518 MLX5_MODIFICATION_TYPE_SET, error);
522 * Convert modify-header set IPv6 address action to DV specification.
524 * @param[in,out] resource
525 * Pointer to the modify-header resource.
527 * Pointer to action specification.
529 * Pointer to the error structure.
532 * 0 on success, a negative errno value otherwise and rte_errno is set.
535 flow_dv_convert_action_modify_ipv6
536 (struct mlx5_flow_dv_modify_hdr_resource *resource,
537 const struct rte_flow_action *action,
538 struct rte_flow_error *error)
540 const struct rte_flow_action_set_ipv6 *conf =
541 (const struct rte_flow_action_set_ipv6 *)(action->conf);
542 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
543 struct rte_flow_item_ipv6 ipv6;
544 struct rte_flow_item_ipv6 ipv6_mask;
546 memset(&ipv6, 0, sizeof(ipv6));
547 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
548 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
549 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6_mask.hdr.src_addr,
552 &rte_flow_item_ipv6_mask.hdr.src_addr,
553 sizeof(ipv6.hdr.src_addr));
555 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
556 sizeof(ipv6.hdr.dst_addr));
557 memcpy(&ipv6_mask.hdr.dst_addr,
558 &rte_flow_item_ipv6_mask.hdr.dst_addr,
559 sizeof(ipv6.hdr.dst_addr));
562 item.mask = &ipv6_mask;
563 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
564 MLX5_MODIFICATION_TYPE_SET, error);
568 * Convert modify-header set MAC address action to DV specification.
570 * @param[in,out] resource
571 * Pointer to the modify-header resource.
573 * Pointer to action specification.
575 * Pointer to the error structure.
578 * 0 on success, a negative errno value otherwise and rte_errno is set.
581 flow_dv_convert_action_modify_mac
582 (struct mlx5_flow_dv_modify_hdr_resource *resource,
583 const struct rte_flow_action *action,
584 struct rte_flow_error *error)
586 const struct rte_flow_action_set_mac *conf =
587 (const struct rte_flow_action_set_mac *)(action->conf);
588 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
589 struct rte_flow_item_eth eth;
590 struct rte_flow_item_eth eth_mask;
592 memset(ð, 0, sizeof(eth));
593 memset(ð_mask, 0, sizeof(eth_mask));
594 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
595 memcpy(ð.src.addr_bytes, &conf->mac_addr,
596 sizeof(eth.src.addr_bytes));
597 memcpy(ð_mask.src.addr_bytes,
598 &rte_flow_item_eth_mask.src.addr_bytes,
599 sizeof(eth_mask.src.addr_bytes));
601 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
602 sizeof(eth.dst.addr_bytes));
603 memcpy(ð_mask.dst.addr_bytes,
604 &rte_flow_item_eth_mask.dst.addr_bytes,
605 sizeof(eth_mask.dst.addr_bytes));
608 item.mask = ð_mask;
609 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
610 MLX5_MODIFICATION_TYPE_SET, error);
614 * Convert modify-header set VLAN VID action to DV specification.
616 * @param[in,out] resource
617 * Pointer to the modify-header resource.
619 * Pointer to action specification.
621 * Pointer to the error structure.
624 * 0 on success, a negative errno value otherwise and rte_errno is set.
627 flow_dv_convert_action_modify_vlan_vid
628 (struct mlx5_flow_dv_modify_hdr_resource *resource,
629 const struct rte_flow_action *action,
630 struct rte_flow_error *error)
632 const struct rte_flow_action_of_set_vlan_vid *conf =
633 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
634 int i = resource->actions_num;
635 struct mlx5_modification_cmd *actions = resource->actions;
636 struct field_modify_info *field = modify_vlan_out_first_vid;
638 if (i >= MLX5_MAX_MODIFY_NUM)
639 return rte_flow_error_set(error, EINVAL,
640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
641 "too many items to modify");
642 actions[i] = (struct mlx5_modification_cmd) {
643 .action_type = MLX5_MODIFICATION_TYPE_SET,
645 .length = field->size,
646 .offset = field->offset,
648 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
649 actions[i].data1 = conf->vlan_vid;
650 actions[i].data1 = actions[i].data1 << 16;
651 resource->actions_num = ++i;
656 * Convert modify-header set TP action to DV specification.
658 * @param[in,out] resource
659 * Pointer to the modify-header resource.
661 * Pointer to action specification.
663 * Pointer to rte_flow_item objects list.
665 * Pointer to flow attributes structure.
666 * @param[in] dev_flow
667 * Pointer to the sub flow.
668 * @param[in] tunnel_decap
669 * Whether action is after tunnel decapsulation.
671 * Pointer to the error structure.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 flow_dv_convert_action_modify_tp
678 (struct mlx5_flow_dv_modify_hdr_resource *resource,
679 const struct rte_flow_action *action,
680 const struct rte_flow_item *items,
681 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
682 bool tunnel_decap, struct rte_flow_error *error)
684 const struct rte_flow_action_set_tp *conf =
685 (const struct rte_flow_action_set_tp *)(action->conf);
686 struct rte_flow_item item;
687 struct rte_flow_item_udp udp;
688 struct rte_flow_item_udp udp_mask;
689 struct rte_flow_item_tcp tcp;
690 struct rte_flow_item_tcp tcp_mask;
691 struct field_modify_info *field;
694 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
696 memset(&udp, 0, sizeof(udp));
697 memset(&udp_mask, 0, sizeof(udp_mask));
698 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
699 udp.hdr.src_port = conf->port;
700 udp_mask.hdr.src_port =
701 rte_flow_item_udp_mask.hdr.src_port;
703 udp.hdr.dst_port = conf->port;
704 udp_mask.hdr.dst_port =
705 rte_flow_item_udp_mask.hdr.dst_port;
707 item.type = RTE_FLOW_ITEM_TYPE_UDP;
709 item.mask = &udp_mask;
712 MLX5_ASSERT(attr->tcp);
713 memset(&tcp, 0, sizeof(tcp));
714 memset(&tcp_mask, 0, sizeof(tcp_mask));
715 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
716 tcp.hdr.src_port = conf->port;
717 tcp_mask.hdr.src_port =
718 rte_flow_item_tcp_mask.hdr.src_port;
720 tcp.hdr.dst_port = conf->port;
721 tcp_mask.hdr.dst_port =
722 rte_flow_item_tcp_mask.hdr.dst_port;
724 item.type = RTE_FLOW_ITEM_TYPE_TCP;
726 item.mask = &tcp_mask;
729 return flow_dv_convert_modify_action(&item, field, NULL, resource,
730 MLX5_MODIFICATION_TYPE_SET, error);
734 * Convert modify-header set TTL action to DV specification.
736 * @param[in,out] resource
737 * Pointer to the modify-header resource.
739 * Pointer to action specification.
741 * Pointer to rte_flow_item objects list.
743 * Pointer to flow attributes structure.
744 * @param[in] dev_flow
745 * Pointer to the sub flow.
746 * @param[in] tunnel_decap
747 * Whether action is after tunnel decapsulation.
749 * Pointer to the error structure.
752 * 0 on success, a negative errno value otherwise and rte_errno is set.
755 flow_dv_convert_action_modify_ttl
756 (struct mlx5_flow_dv_modify_hdr_resource *resource,
757 const struct rte_flow_action *action,
758 const struct rte_flow_item *items,
759 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
760 bool tunnel_decap, struct rte_flow_error *error)
762 const struct rte_flow_action_set_ttl *conf =
763 (const struct rte_flow_action_set_ttl *)(action->conf);
764 struct rte_flow_item item;
765 struct rte_flow_item_ipv4 ipv4;
766 struct rte_flow_item_ipv4 ipv4_mask;
767 struct rte_flow_item_ipv6 ipv6;
768 struct rte_flow_item_ipv6 ipv6_mask;
769 struct field_modify_info *field;
772 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
774 memset(&ipv4, 0, sizeof(ipv4));
775 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
776 ipv4.hdr.time_to_live = conf->ttl_value;
777 ipv4_mask.hdr.time_to_live = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
780 item.mask = &ipv4_mask;
783 MLX5_ASSERT(attr->ipv6);
784 memset(&ipv6, 0, sizeof(ipv6));
785 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
786 ipv6.hdr.hop_limits = conf->ttl_value;
787 ipv6_mask.hdr.hop_limits = 0xFF;
788 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
790 item.mask = &ipv6_mask;
793 return flow_dv_convert_modify_action(&item, field, NULL, resource,
794 MLX5_MODIFICATION_TYPE_SET, error);
798 * Convert modify-header decrement TTL action to DV specification.
800 * @param[in,out] resource
801 * Pointer to the modify-header resource.
803 * Pointer to action specification.
805 * Pointer to rte_flow_item objects list.
807 * Pointer to flow attributes structure.
808 * @param[in] dev_flow
809 * Pointer to the sub flow.
810 * @param[in] tunnel_decap
811 * Whether action is after tunnel decapsulation.
813 * Pointer to the error structure.
816 * 0 on success, a negative errno value otherwise and rte_errno is set.
819 flow_dv_convert_action_modify_dec_ttl
820 (struct mlx5_flow_dv_modify_hdr_resource *resource,
821 const struct rte_flow_item *items,
822 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
823 bool tunnel_decap, struct rte_flow_error *error)
825 struct rte_flow_item item;
826 struct rte_flow_item_ipv4 ipv4;
827 struct rte_flow_item_ipv4 ipv4_mask;
828 struct rte_flow_item_ipv6 ipv6;
829 struct rte_flow_item_ipv6 ipv6_mask;
830 struct field_modify_info *field;
833 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
835 memset(&ipv4, 0, sizeof(ipv4));
836 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
837 ipv4.hdr.time_to_live = 0xFF;
838 ipv4_mask.hdr.time_to_live = 0xFF;
839 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
841 item.mask = &ipv4_mask;
844 MLX5_ASSERT(attr->ipv6);
845 memset(&ipv6, 0, sizeof(ipv6));
846 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
847 ipv6.hdr.hop_limits = 0xFF;
848 ipv6_mask.hdr.hop_limits = 0xFF;
849 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
851 item.mask = &ipv6_mask;
854 return flow_dv_convert_modify_action(&item, field, NULL, resource,
855 MLX5_MODIFICATION_TYPE_ADD, error);
859 * Convert modify-header increment/decrement TCP Sequence number
860 * to DV specification.
862 * @param[in,out] resource
863 * Pointer to the modify-header resource.
865 * Pointer to action specification.
867 * Pointer to the error structure.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 flow_dv_convert_action_modify_tcp_seq
874 (struct mlx5_flow_dv_modify_hdr_resource *resource,
875 const struct rte_flow_action *action,
876 struct rte_flow_error *error)
878 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
879 uint64_t value = rte_be_to_cpu_32(*conf);
880 struct rte_flow_item item;
881 struct rte_flow_item_tcp tcp;
882 struct rte_flow_item_tcp tcp_mask;
884 memset(&tcp, 0, sizeof(tcp));
885 memset(&tcp_mask, 0, sizeof(tcp_mask));
886 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
888 * The HW has no decrement operation, only increment operation.
889 * To simulate decrement X from Y using increment operation
890 * we need to add UINT32_MAX X times to Y.
891 * Each adding of UINT32_MAX decrements Y by 1.
894 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
895 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
896 item.type = RTE_FLOW_ITEM_TYPE_TCP;
898 item.mask = &tcp_mask;
899 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
900 MLX5_MODIFICATION_TYPE_ADD, error);
904 * Convert modify-header increment/decrement TCP Acknowledgment number
905 * to DV specification.
907 * @param[in,out] resource
908 * Pointer to the modify-header resource.
910 * Pointer to action specification.
912 * Pointer to the error structure.
915 * 0 on success, a negative errno value otherwise and rte_errno is set.
918 flow_dv_convert_action_modify_tcp_ack
919 (struct mlx5_flow_dv_modify_hdr_resource *resource,
920 const struct rte_flow_action *action,
921 struct rte_flow_error *error)
923 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
924 uint64_t value = rte_be_to_cpu_32(*conf);
925 struct rte_flow_item item;
926 struct rte_flow_item_tcp tcp;
927 struct rte_flow_item_tcp tcp_mask;
929 memset(&tcp, 0, sizeof(tcp));
930 memset(&tcp_mask, 0, sizeof(tcp_mask));
931 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
933 * The HW has no decrement operation, only increment operation.
934 * To simulate decrement X from Y using increment operation
935 * we need to add UINT32_MAX X times to Y.
936 * Each adding of UINT32_MAX decrements Y by 1.
939 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
940 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
941 item.type = RTE_FLOW_ITEM_TYPE_TCP;
943 item.mask = &tcp_mask;
944 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
945 MLX5_MODIFICATION_TYPE_ADD, error);
948 static enum mlx5_modification_field reg_to_field[] = {
949 [REG_NONE] = MLX5_MODI_OUT_NONE,
950 [REG_A] = MLX5_MODI_META_DATA_REG_A,
951 [REG_B] = MLX5_MODI_META_DATA_REG_B,
952 [REG_C_0] = MLX5_MODI_META_REG_C_0,
953 [REG_C_1] = MLX5_MODI_META_REG_C_1,
954 [REG_C_2] = MLX5_MODI_META_REG_C_2,
955 [REG_C_3] = MLX5_MODI_META_REG_C_3,
956 [REG_C_4] = MLX5_MODI_META_REG_C_4,
957 [REG_C_5] = MLX5_MODI_META_REG_C_5,
958 [REG_C_6] = MLX5_MODI_META_REG_C_6,
959 [REG_C_7] = MLX5_MODI_META_REG_C_7,
963 * Convert register set to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_set_reg
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
982 struct mlx5_modification_cmd *actions = resource->actions;
983 uint32_t i = resource->actions_num;
985 if (i >= MLX5_MAX_MODIFY_NUM)
986 return rte_flow_error_set(error, EINVAL,
987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
988 "too many items to modify");
989 MLX5_ASSERT(conf->id != REG_NONE);
990 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
991 actions[i] = (struct mlx5_modification_cmd) {
992 .action_type = MLX5_MODIFICATION_TYPE_SET,
993 .field = reg_to_field[conf->id],
995 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
996 actions[i].data1 = rte_cpu_to_be_32(conf->data);
998 resource->actions_num = i;
1003 * Convert SET_TAG action to DV specification.
1006 * Pointer to the rte_eth_dev structure.
1007 * @param[in,out] resource
1008 * Pointer to the modify-header resource.
1010 * Pointer to action specification.
1012 * Pointer to the error structure.
1015 * 0 on success, a negative errno value otherwise and rte_errno is set.
1018 flow_dv_convert_action_set_tag
1019 (struct rte_eth_dev *dev,
1020 struct mlx5_flow_dv_modify_hdr_resource *resource,
1021 const struct rte_flow_action_set_tag *conf,
1022 struct rte_flow_error *error)
1024 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026 struct rte_flow_item item = {
1030 struct field_modify_info reg_c_x[] = {
1033 enum mlx5_modification_field reg_type;
1036 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1039 MLX5_ASSERT(ret != REG_NONE);
1040 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041 reg_type = reg_to_field[ret];
1042 MLX5_ASSERT(reg_type > 0);
1043 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045 MLX5_MODIFICATION_TYPE_SET, error);
1049 * Convert internal COPY_REG action to DV specification.
1052 * Pointer to the rte_eth_dev structure.
1053 * @param[in,out] res
1054 * Pointer to the modify-header resource.
1056 * Pointer to action specification.
1058 * Pointer to the error structure.
1061 * 0 on success, a negative errno value otherwise and rte_errno is set.
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065 struct mlx5_flow_dv_modify_hdr_resource *res,
1066 const struct rte_flow_action *action,
1067 struct rte_flow_error *error)
1069 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071 struct rte_flow_item item = {
1075 struct field_modify_info reg_src[] = {
1076 {4, 0, reg_to_field[conf->src]},
1079 struct field_modify_info reg_dst = {
1081 .id = reg_to_field[conf->dst],
1083 /* Adjust reg_c[0] usage according to reported mask. */
1084 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085 struct mlx5_priv *priv = dev->data->dev_private;
1086 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088 MLX5_ASSERT(reg_c0);
1089 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090 if (conf->dst == REG_C_0) {
1091 /* Copy to reg_c[0], within mask only. */
1092 reg_dst.offset = rte_bsf32(reg_c0);
1094 * Mask is ignoring the enianness, because
1095 * there is no conversion in datapath.
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098 /* Copy from destination lower bits to reg_c[0]. */
1099 mask = reg_c0 >> reg_dst.offset;
1101 /* Copy from destination upper bits to reg_c[0]. */
1102 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103 rte_fls_u32(reg_c0));
1106 mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108 /* Copy from reg_c[0] to destination lower bits. */
1111 /* Copy from reg_c[0] to destination upper bits. */
1112 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113 (rte_fls_u32(reg_c0) -
1118 return flow_dv_convert_modify_action(&item,
1119 reg_src, ®_dst, res,
1120 MLX5_MODIFICATION_TYPE_COPY,
1125 * Convert MARK action to DV specification. This routine is used
1126 * in extensive metadata only and requires metadata register to be
1127 * handled. In legacy mode hardware tag resource is engaged.
1130 * Pointer to the rte_eth_dev structure.
1132 * Pointer to MARK action specification.
1133 * @param[in,out] resource
1134 * Pointer to the modify-header resource.
1136 * Pointer to the error structure.
1139 * 0 on success, a negative errno value otherwise and rte_errno is set.
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143 const struct rte_flow_action_mark *conf,
1144 struct mlx5_flow_dv_modify_hdr_resource *resource,
1145 struct rte_flow_error *error)
1147 struct mlx5_priv *priv = dev->data->dev_private;
1148 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149 priv->sh->dv_mark_mask);
1150 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151 struct rte_flow_item item = {
1155 struct field_modify_info reg_c_x[] = {
1156 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1162 return rte_flow_error_set(error, EINVAL,
1163 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164 NULL, "zero mark action mask");
1165 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1168 MLX5_ASSERT(reg > 0);
1169 if (reg == REG_C_0) {
1170 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175 mask = rte_cpu_to_be_32(mask << shl_c0);
1177 reg_c_x[0].id = reg_to_field[reg];
1178 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179 MLX5_MODIFICATION_TYPE_SET, error);
1183 * Get metadata register index for specified steering domain.
1186 * Pointer to the rte_eth_dev structure.
1188 * Attributes of flow to determine steering domain.
1190 * Pointer to the error structure.
1193 * positive index on success, a negative errno value otherwise
1194 * and rte_errno is set.
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198 const struct rte_flow_attr *attr,
1199 struct rte_flow_error *error)
1202 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206 MLX5_METADATA_RX, 0, error);
1208 return rte_flow_error_set(error,
1209 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210 NULL, "unavailable "
1211 "metadata register");
1216 * Convert SET_META action to DV specification.
1219 * Pointer to the rte_eth_dev structure.
1220 * @param[in,out] resource
1221 * Pointer to the modify-header resource.
1223 * Attributes of flow that includes this item.
1225 * Pointer to action specification.
1227 * Pointer to the error structure.
1230 * 0 on success, a negative errno value otherwise and rte_errno is set.
1233 flow_dv_convert_action_set_meta
1234 (struct rte_eth_dev *dev,
1235 struct mlx5_flow_dv_modify_hdr_resource *resource,
1236 const struct rte_flow_attr *attr,
1237 const struct rte_flow_action_set_meta *conf,
1238 struct rte_flow_error *error)
1240 uint32_t data = conf->data;
1241 uint32_t mask = conf->mask;
1242 struct rte_flow_item item = {
1246 struct field_modify_info reg_c_x[] = {
1249 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254 * In datapath code there is no endianness
1255 * coversions for perfromance reasons, all
1256 * pattern conversions are done in rte_flow.
1258 if (reg == REG_C_0) {
1259 struct mlx5_priv *priv = dev->data->dev_private;
1260 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1263 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265 shl_c0 = rte_bsf32(msk_c0);
1267 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274 /* The routine expects parameters in memory as big-endian ones. */
1275 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276 MLX5_MODIFICATION_TYPE_SET, error);
1280 * Convert modify-header set IPv4 DSCP action to DV specification.
1282 * @param[in,out] resource
1283 * Pointer to the modify-header resource.
1285 * Pointer to action specification.
1287 * Pointer to the error structure.
1290 * 0 on success, a negative errno value otherwise and rte_errno is set.
1293 flow_dv_convert_action_modify_ipv4_dscp
1294 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295 const struct rte_flow_action *action,
1296 struct rte_flow_error *error)
1298 const struct rte_flow_action_set_dscp *conf =
1299 (const struct rte_flow_action_set_dscp *)(action->conf);
1300 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301 struct rte_flow_item_ipv4 ipv4;
1302 struct rte_flow_item_ipv4 ipv4_mask;
1304 memset(&ipv4, 0, sizeof(ipv4));
1305 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306 ipv4.hdr.type_of_service = conf->dscp;
1307 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309 item.mask = &ipv4_mask;
1310 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311 MLX5_MODIFICATION_TYPE_SET, error);
1315 * Convert modify-header set IPv6 DSCP action to DV specification.
1317 * @param[in,out] resource
1318 * Pointer to the modify-header resource.
1320 * Pointer to action specification.
1322 * Pointer to the error structure.
1325 * 0 on success, a negative errno value otherwise and rte_errno is set.
1328 flow_dv_convert_action_modify_ipv6_dscp
1329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330 const struct rte_flow_action *action,
1331 struct rte_flow_error *error)
1333 const struct rte_flow_action_set_dscp *conf =
1334 (const struct rte_flow_action_set_dscp *)(action->conf);
1335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336 struct rte_flow_item_ipv6 ipv6;
1337 struct rte_flow_item_ipv6 ipv6_mask;
1339 memset(&ipv6, 0, sizeof(ipv6));
1340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343 * rdma-core only accept the DSCP bits byte aligned start from
1344 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345 * bits in IPv6 case as rdma-core requires byte aligned value.
1347 ipv6.hdr.vtc_flow = conf->dscp;
1348 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350 item.mask = &ipv6_mask;
1351 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352 MLX5_MODIFICATION_TYPE_SET, error);
1356 * Validate MARK item.
1359 * Pointer to the rte_eth_dev structure.
1361 * Item specification.
1363 * Attributes of flow that includes this item.
1365 * Pointer to error structure.
1368 * 0 on success, a negative errno value otherwise and rte_errno is set.
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372 const struct rte_flow_item *item,
1373 const struct rte_flow_attr *attr __rte_unused,
1374 struct rte_flow_error *error)
1376 struct mlx5_priv *priv = dev->data->dev_private;
1377 struct mlx5_dev_config *config = &priv->config;
1378 const struct rte_flow_item_mark *spec = item->spec;
1379 const struct rte_flow_item_mark *mask = item->mask;
1380 const struct rte_flow_item_mark nic_mask = {
1381 .id = priv->sh->dv_mark_mask,
1385 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386 return rte_flow_error_set(error, ENOTSUP,
1387 RTE_FLOW_ERROR_TYPE_ITEM, item,
1388 "extended metadata feature"
1390 if (!mlx5_flow_ext_mreg_supported(dev))
1391 return rte_flow_error_set(error, ENOTSUP,
1392 RTE_FLOW_ERROR_TYPE_ITEM, item,
1393 "extended metadata register"
1394 " isn't supported");
1396 return rte_flow_error_set(error, ENOTSUP,
1397 RTE_FLOW_ERROR_TYPE_ITEM, item,
1398 "extended metadata register"
1399 " isn't available");
1400 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404 return rte_flow_error_set(error, EINVAL,
1405 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407 "data cannot be empty");
1408 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409 return rte_flow_error_set(error, EINVAL,
1410 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412 "mark id exceeds the limit");
1416 return rte_flow_error_set(error, EINVAL,
1417 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418 "mask cannot be zero");
1420 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421 (const uint8_t *)&nic_mask,
1422 sizeof(struct rte_flow_item_mark),
1430 * Validate META item.
1433 * Pointer to the rte_eth_dev structure.
1435 * Item specification.
1437 * Attributes of flow that includes this item.
1439 * Pointer to error structure.
1442 * 0 on success, a negative errno value otherwise and rte_errno is set.
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446 const struct rte_flow_item *item,
1447 const struct rte_flow_attr *attr,
1448 struct rte_flow_error *error)
1450 struct mlx5_priv *priv = dev->data->dev_private;
1451 struct mlx5_dev_config *config = &priv->config;
1452 const struct rte_flow_item_meta *spec = item->spec;
1453 const struct rte_flow_item_meta *mask = item->mask;
1454 struct rte_flow_item_meta nic_mask = {
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464 "data cannot be empty");
1465 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466 if (!mlx5_flow_ext_mreg_supported(dev))
1467 return rte_flow_error_set(error, ENOTSUP,
1468 RTE_FLOW_ERROR_TYPE_ITEM, item,
1469 "extended metadata register"
1470 " isn't supported");
1471 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475 return rte_flow_error_set(error, ENOTSUP,
1476 RTE_FLOW_ERROR_TYPE_ITEM, item,
1480 nic_mask.data = priv->sh->dv_meta_mask;
1483 mask = &rte_flow_item_meta_mask;
1485 return rte_flow_error_set(error, EINVAL,
1486 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487 "mask cannot be zero");
1489 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490 (const uint8_t *)&nic_mask,
1491 sizeof(struct rte_flow_item_meta),
1497 * Validate TAG item.
1500 * Pointer to the rte_eth_dev structure.
1502 * Item specification.
1504 * Attributes of flow that includes this item.
1506 * Pointer to error structure.
1509 * 0 on success, a negative errno value otherwise and rte_errno is set.
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513 const struct rte_flow_item *item,
1514 const struct rte_flow_attr *attr __rte_unused,
1515 struct rte_flow_error *error)
1517 const struct rte_flow_item_tag *spec = item->spec;
1518 const struct rte_flow_item_tag *mask = item->mask;
1519 const struct rte_flow_item_tag nic_mask = {
1520 .data = RTE_BE32(UINT32_MAX),
1525 if (!mlx5_flow_ext_mreg_supported(dev))
1526 return rte_flow_error_set(error, ENOTSUP,
1527 RTE_FLOW_ERROR_TYPE_ITEM, item,
1528 "extensive metadata register"
1529 " isn't supported");
1531 return rte_flow_error_set(error, EINVAL,
1532 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534 "data cannot be empty");
1536 mask = &rte_flow_item_tag_mask;
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540 "mask cannot be zero");
1542 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543 (const uint8_t *)&nic_mask,
1544 sizeof(struct rte_flow_item_tag),
1548 if (mask->index != 0xff)
1549 return rte_flow_error_set(error, EINVAL,
1550 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551 "partial mask for tag index"
1552 " is not supported");
1553 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1556 MLX5_ASSERT(ret != REG_NONE);
1561 * Validate vport item.
1564 * Pointer to the rte_eth_dev structure.
1566 * Item specification.
1568 * Attributes of flow that includes this item.
1569 * @param[in] item_flags
1570 * Bit-fields that holds the items detected until now.
1572 * Pointer to error structure.
1575 * 0 on success, a negative errno value otherwise and rte_errno is set.
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579 const struct rte_flow_item *item,
1580 const struct rte_flow_attr *attr,
1581 uint64_t item_flags,
1582 struct rte_flow_error *error)
1584 const struct rte_flow_item_port_id *spec = item->spec;
1585 const struct rte_flow_item_port_id *mask = item->mask;
1586 const struct rte_flow_item_port_id switch_mask = {
1589 struct mlx5_priv *esw_priv;
1590 struct mlx5_priv *dev_priv;
1593 if (!attr->transfer)
1594 return rte_flow_error_set(error, EINVAL,
1595 RTE_FLOW_ERROR_TYPE_ITEM,
1597 "match on port id is valid only"
1598 " when transfer flag is enabled");
1599 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600 return rte_flow_error_set(error, ENOTSUP,
1601 RTE_FLOW_ERROR_TYPE_ITEM, item,
1602 "multiple source ports are not"
1605 mask = &switch_mask;
1606 if (mask->id != 0xffffffff)
1607 return rte_flow_error_set(error, ENOTSUP,
1608 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610 "no support for partial mask on"
1612 ret = mlx5_flow_item_acceptable
1613 (item, (const uint8_t *)mask,
1614 (const uint8_t *)&rte_flow_item_port_id_mask,
1615 sizeof(struct rte_flow_item_port_id),
1621 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623 return rte_flow_error_set(error, rte_errno,
1624 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625 "failed to obtain E-Switch info for"
1627 dev_priv = mlx5_dev_to_eswitch_info(dev);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632 "failed to obtain E-Switch info");
1633 if (esw_priv->domain_id != dev_priv->domain_id)
1634 return rte_flow_error_set(error, EINVAL,
1635 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636 "cannot match on a port from a"
1637 " different E-Switch");
1642 * Validate GTP item.
1645 * Pointer to the rte_eth_dev structure.
1647 * Item specification.
1648 * @param[in] item_flags
1649 * Bit-fields that holds the items detected until now.
1651 * Pointer to error structure.
1654 * 0 on success, a negative errno value otherwise and rte_errno is set.
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658 const struct rte_flow_item *item,
1659 uint64_t item_flags,
1660 struct rte_flow_error *error)
1662 struct mlx5_priv *priv = dev->data->dev_private;
1663 const struct rte_flow_item_gtp *mask = item->mask;
1664 const struct rte_flow_item_gtp nic_mask = {
1666 .teid = RTE_BE32(0xffffffff),
1669 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "GTP support is not enabled");
1673 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674 return rte_flow_error_set(error, ENOTSUP,
1675 RTE_FLOW_ERROR_TYPE_ITEM, item,
1676 "multiple tunnel layers not"
1678 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679 return rte_flow_error_set(error, EINVAL,
1680 RTE_FLOW_ERROR_TYPE_ITEM, item,
1681 "no outer UDP layer found");
1683 mask = &rte_flow_item_gtp_mask;
1684 return mlx5_flow_item_acceptable
1685 (item, (const uint8_t *)mask,
1686 (const uint8_t *)&nic_mask,
1687 sizeof(struct rte_flow_item_gtp),
1692 * Validate the pop VLAN action.
1695 * Pointer to the rte_eth_dev structure.
1696 * @param[in] action_flags
1697 * Holds the actions detected until now.
1699 * Pointer to the pop vlan action.
1700 * @param[in] item_flags
1701 * The items found in this flow rule.
1703 * Pointer to flow attributes.
1705 * Pointer to error structure.
1708 * 0 on success, a negative errno value otherwise and rte_errno is set.
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712 uint64_t action_flags,
1713 const struct rte_flow_action *action,
1714 uint64_t item_flags,
1715 const struct rte_flow_attr *attr,
1716 struct rte_flow_error *error)
1718 const struct mlx5_priv *priv = dev->data->dev_private;
1722 if (!priv->sh->pop_vlan_action)
1723 return rte_flow_error_set(error, ENOTSUP,
1724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726 "pop vlan action is not supported");
1728 return rte_flow_error_set(error, ENOTSUP,
1729 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731 "pop vlan action not supported for "
1733 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734 return rte_flow_error_set(error, ENOTSUP,
1735 RTE_FLOW_ERROR_TYPE_ACTION, action,
1736 "no support for multiple VLAN "
1738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739 return rte_flow_error_set(error, ENOTSUP,
1740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742 "cannot pop vlan without a "
1743 "match on (outer) vlan in the flow");
1744 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745 return rte_flow_error_set(error, EINVAL,
1746 RTE_FLOW_ERROR_TYPE_ACTION, action,
1747 "wrong action order, port_id should "
1748 "be after pop VLAN action");
1749 if (!attr->transfer && priv->representor)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752 "pop vlan action for VF representor "
1753 "not supported on NIC table");
1758 * Get VLAN default info from vlan match info.
1761 * the list of item specifications.
1763 * pointer VLAN info to fill to.
1766 * 0 on success, a negative errno value otherwise and rte_errno is set.
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770 struct rte_vlan_hdr *vlan)
1772 const struct rte_flow_item_vlan nic_mask = {
1773 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774 MLX5DV_FLOW_VLAN_VID_MASK),
1775 .inner_type = RTE_BE16(0xffff),
1780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781 int type = items->type;
1783 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1787 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793 /* Only full match values are accepted */
1794 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798 rte_be_to_cpu_16(vlan_v->tci &
1799 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805 rte_be_to_cpu_16(vlan_v->tci &
1806 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808 if (vlan_m->inner_type == nic_mask.inner_type)
1809 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810 vlan_m->inner_type);
1815 * Validate the push VLAN action.
1818 * Pointer to the rte_eth_dev structure.
1819 * @param[in] action_flags
1820 * Holds the actions detected until now.
1821 * @param[in] item_flags
1822 * The items found in this flow rule.
1824 * Pointer to the action structure.
1826 * Pointer to flow attributes
1828 * Pointer to error structure.
1831 * 0 on success, a negative errno value otherwise and rte_errno is set.
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835 uint64_t action_flags,
1836 const struct rte_flow_item_vlan *vlan_m,
1837 const struct rte_flow_action *action,
1838 const struct rte_flow_attr *attr,
1839 struct rte_flow_error *error)
1841 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842 const struct mlx5_priv *priv = dev->data->dev_private;
1844 if (!attr->transfer && attr->ingress)
1845 return rte_flow_error_set(error, ENOTSUP,
1846 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848 "push VLAN action not supported for "
1850 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "invalid vlan ethertype");
1855 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856 return rte_flow_error_set(error, ENOTSUP,
1857 RTE_FLOW_ERROR_TYPE_ACTION, action,
1858 "no support for multiple VLAN "
1860 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861 return rte_flow_error_set(error, EINVAL,
1862 RTE_FLOW_ERROR_TYPE_ACTION, action,
1863 "wrong action order, port_id should "
1864 "be after push VLAN");
1865 if (!attr->transfer && priv->representor)
1866 return rte_flow_error_set(error, ENOTSUP,
1867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868 "push vlan action for VF representor "
1869 "not supported on NIC table");
1871 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875 !(mlx5_flow_find_action
1876 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877 return rte_flow_error_set(error, EINVAL,
1878 RTE_FLOW_ERROR_TYPE_ACTION, action,
1879 "not full match mask on VLAN PCP and "
1880 "there is no of_set_vlan_pcp action, "
1881 "push VLAN action cannot figure out "
1884 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888 !(mlx5_flow_find_action
1889 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890 return rte_flow_error_set(error, EINVAL,
1891 RTE_FLOW_ERROR_TYPE_ACTION, action,
1892 "not full match mask on VLAN VID and "
1893 "there is no of_set_vlan_vid action, "
1894 "push VLAN action cannot figure out "
1901 * Validate the set VLAN PCP.
1903 * @param[in] action_flags
1904 * Holds the actions detected until now.
1905 * @param[in] actions
1906 * Pointer to the list of actions remaining in the flow rule.
1908 * Pointer to error structure.
1911 * 0 on success, a negative errno value otherwise and rte_errno is set.
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915 const struct rte_flow_action actions[],
1916 struct rte_flow_error *error)
1918 const struct rte_flow_action *action = actions;
1919 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921 if (conf->vlan_pcp > 7)
1922 return rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ACTION, action,
1924 "VLAN PCP value is too big");
1925 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926 return rte_flow_error_set(error, ENOTSUP,
1927 RTE_FLOW_ERROR_TYPE_ACTION, action,
1928 "set VLAN PCP action must follow "
1929 "the push VLAN action");
1930 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931 return rte_flow_error_set(error, ENOTSUP,
1932 RTE_FLOW_ERROR_TYPE_ACTION, action,
1933 "Multiple VLAN PCP modification are "
1935 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936 return rte_flow_error_set(error, EINVAL,
1937 RTE_FLOW_ERROR_TYPE_ACTION, action,
1938 "wrong action order, port_id should "
1939 "be after set VLAN PCP");
1944 * Validate the set VLAN VID.
1946 * @param[in] item_flags
1947 * Holds the items detected in this rule.
1948 * @param[in] action_flags
1949 * Holds the actions detected until now.
1950 * @param[in] actions
1951 * Pointer to the list of actions remaining in the flow rule.
1953 * Pointer to error structure.
1956 * 0 on success, a negative errno value otherwise and rte_errno is set.
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960 uint64_t action_flags,
1961 const struct rte_flow_action actions[],
1962 struct rte_flow_error *error)
1964 const struct rte_flow_action *action = actions;
1965 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967 if (conf->vlan_vid > RTE_BE16(0xFFE))
1968 return rte_flow_error_set(error, EINVAL,
1969 RTE_FLOW_ERROR_TYPE_ACTION, action,
1970 "VLAN VID value is too big");
1971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973 return rte_flow_error_set(error, ENOTSUP,
1974 RTE_FLOW_ERROR_TYPE_ACTION, action,
1975 "set VLAN VID action must follow push"
1976 " VLAN action or match on VLAN item");
1977 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978 return rte_flow_error_set(error, ENOTSUP,
1979 RTE_FLOW_ERROR_TYPE_ACTION, action,
1980 "Multiple VLAN VID modifications are "
1982 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ACTION, action,
1985 "wrong action order, port_id should "
1986 "be after set VLAN VID");
1991 * Validate the FLAG action.
1994 * Pointer to the rte_eth_dev structure.
1995 * @param[in] action_flags
1996 * Holds the actions detected until now.
1998 * Pointer to flow attributes
2000 * Pointer to error structure.
2003 * 0 on success, a negative errno value otherwise and rte_errno is set.
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007 uint64_t action_flags,
2008 const struct rte_flow_attr *attr,
2009 struct rte_flow_error *error)
2011 struct mlx5_priv *priv = dev->data->dev_private;
2012 struct mlx5_dev_config *config = &priv->config;
2015 /* Fall back if no extended metadata register support. */
2016 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017 return mlx5_flow_validate_action_flag(action_flags, attr,
2019 /* Extensive metadata mode requires registers. */
2020 if (!mlx5_flow_ext_mreg_supported(dev))
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023 "no metadata registers "
2024 "to support flag action");
2025 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028 "extended metadata register"
2029 " isn't available");
2030 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2033 MLX5_ASSERT(ret > 0);
2034 if (action_flags & MLX5_FLOW_ACTION_MARK)
2035 return rte_flow_error_set(error, EINVAL,
2036 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037 "can't mark and flag in same flow");
2038 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039 return rte_flow_error_set(error, EINVAL,
2040 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042 " actions in same flow");
2047 * Validate MARK action.
2050 * Pointer to the rte_eth_dev structure.
2052 * Pointer to action.
2053 * @param[in] action_flags
2054 * Holds the actions detected until now.
2056 * Pointer to flow attributes
2058 * Pointer to error structure.
2061 * 0 on success, a negative errno value otherwise and rte_errno is set.
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065 const struct rte_flow_action *action,
2066 uint64_t action_flags,
2067 const struct rte_flow_attr *attr,
2068 struct rte_flow_error *error)
2070 struct mlx5_priv *priv = dev->data->dev_private;
2071 struct mlx5_dev_config *config = &priv->config;
2072 const struct rte_flow_action_mark *mark = action->conf;
2075 /* Fall back if no extended metadata register support. */
2076 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077 return mlx5_flow_validate_action_mark(action, action_flags,
2079 /* Extensive metadata mode requires registers. */
2080 if (!mlx5_flow_ext_mreg_supported(dev))
2081 return rte_flow_error_set(error, ENOTSUP,
2082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083 "no metadata registers "
2084 "to support mark action");
2085 if (!priv->sh->dv_mark_mask)
2086 return rte_flow_error_set(error, ENOTSUP,
2087 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088 "extended metadata register"
2089 " isn't available");
2090 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2093 MLX5_ASSERT(ret > 0);
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ACTION, action,
2097 "configuration cannot be null");
2098 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102 "mark id exceeds the limit");
2103 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104 return rte_flow_error_set(error, EINVAL,
2105 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106 "can't flag and mark in same flow");
2107 if (action_flags & MLX5_FLOW_ACTION_MARK)
2108 return rte_flow_error_set(error, EINVAL,
2109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110 "can't have 2 mark actions in same"
2116 * Validate SET_META action.
2119 * Pointer to the rte_eth_dev structure.
2121 * Pointer to the action structure.
2122 * @param[in] action_flags
2123 * Holds the actions detected until now.
2125 * Pointer to flow attributes
2127 * Pointer to error structure.
2130 * 0 on success, a negative errno value otherwise and rte_errno is set.
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134 const struct rte_flow_action *action,
2135 uint64_t action_flags __rte_unused,
2136 const struct rte_flow_attr *attr,
2137 struct rte_flow_error *error)
2139 const struct rte_flow_action_set_meta *conf;
2140 uint32_t nic_mask = UINT32_MAX;
2143 if (!mlx5_flow_ext_mreg_supported(dev))
2144 return rte_flow_error_set(error, ENOTSUP,
2145 RTE_FLOW_ERROR_TYPE_ACTION, action,
2146 "extended metadata register"
2147 " isn't supported");
2148 reg = flow_dv_get_metadata_reg(dev, attr, error);
2151 if (reg != REG_A && reg != REG_B) {
2152 struct mlx5_priv *priv = dev->data->dev_private;
2154 nic_mask = priv->sh->dv_meta_mask;
2156 if (!(action->conf))
2157 return rte_flow_error_set(error, EINVAL,
2158 RTE_FLOW_ERROR_TYPE_ACTION, action,
2159 "configuration cannot be null");
2160 conf = (const struct rte_flow_action_set_meta *)action->conf;
2162 return rte_flow_error_set(error, EINVAL,
2163 RTE_FLOW_ERROR_TYPE_ACTION, action,
2164 "zero mask doesn't have any effect");
2165 if (conf->mask & ~nic_mask)
2166 return rte_flow_error_set(error, EINVAL,
2167 RTE_FLOW_ERROR_TYPE_ACTION, action,
2168 "meta data must be within reg C0");
2173 * Validate SET_TAG action.
2176 * Pointer to the rte_eth_dev structure.
2178 * Pointer to the action structure.
2179 * @param[in] action_flags
2180 * Holds the actions detected until now.
2182 * Pointer to flow attributes
2184 * Pointer to error structure.
2187 * 0 on success, a negative errno value otherwise and rte_errno is set.
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191 const struct rte_flow_action *action,
2192 uint64_t action_flags,
2193 const struct rte_flow_attr *attr,
2194 struct rte_flow_error *error)
2196 const struct rte_flow_action_set_tag *conf;
2197 const uint64_t terminal_action_flags =
2198 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199 MLX5_FLOW_ACTION_RSS;
2202 if (!mlx5_flow_ext_mreg_supported(dev))
2203 return rte_flow_error_set(error, ENOTSUP,
2204 RTE_FLOW_ERROR_TYPE_ACTION, action,
2205 "extensive metadata register"
2206 " isn't supported");
2207 if (!(action->conf))
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, action,
2210 "configuration cannot be null");
2211 conf = (const struct rte_flow_action_set_tag *)action->conf;
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION, action,
2215 "zero mask doesn't have any effect");
2216 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2219 if (!attr->transfer && attr->ingress &&
2220 (action_flags & terminal_action_flags))
2221 return rte_flow_error_set(error, EINVAL,
2222 RTE_FLOW_ERROR_TYPE_ACTION, action,
2223 "set_tag has no effect"
2224 " with terminal actions");
2229 * Validate count action.
2232 * Pointer to rte_eth_dev structure.
2234 * Pointer to error structure.
2237 * 0 on success, a negative errno value otherwise and rte_errno is set.
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241 struct rte_flow_error *error)
2243 struct mlx5_priv *priv = dev->data->dev_private;
2245 if (!priv->config.devx)
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2251 return rte_flow_error_set
2253 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255 "count action not supported");
2259 * Validate the L2 encap action.
2262 * Pointer to the rte_eth_dev structure.
2263 * @param[in] action_flags
2264 * Holds the actions detected until now.
2266 * Pointer to the action structure.
2268 * Pointer to flow attributes.
2270 * Pointer to error structure.
2273 * 0 on success, a negative errno value otherwise and rte_errno is set.
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277 uint64_t action_flags,
2278 const struct rte_flow_action *action,
2279 const struct rte_flow_attr *attr,
2280 struct rte_flow_error *error)
2282 const struct mlx5_priv *priv = dev->data->dev_private;
2284 if (!(action->conf))
2285 return rte_flow_error_set(error, EINVAL,
2286 RTE_FLOW_ERROR_TYPE_ACTION, action,
2287 "configuration cannot be null");
2288 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289 return rte_flow_error_set(error, EINVAL,
2290 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291 "can only have a single encap action "
2293 if (!attr->transfer && priv->representor)
2294 return rte_flow_error_set(error, ENOTSUP,
2295 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296 "encap action for VF representor "
2297 "not supported on NIC table");
2302 * Validate a decap action.
2305 * Pointer to the rte_eth_dev structure.
2306 * @param[in] action_flags
2307 * Holds the actions detected until now.
2309 * Pointer to flow attributes
2311 * Pointer to error structure.
2314 * 0 on success, a negative errno value otherwise and rte_errno is set.
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318 uint64_t action_flags,
2319 const struct rte_flow_attr *attr,
2320 struct rte_flow_error *error)
2322 const struct mlx5_priv *priv = dev->data->dev_private;
2324 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325 return rte_flow_error_set(error, ENOTSUP,
2326 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328 MLX5_FLOW_ACTION_DECAP ? "can only "
2329 "have a single decap action" : "decap "
2330 "after encap is not supported");
2331 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332 return rte_flow_error_set(error, EINVAL,
2333 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334 "can't have decap action after"
2337 return rte_flow_error_set(error, ENOTSUP,
2338 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340 "decap action not supported for "
2342 if (!attr->transfer && priv->representor)
2343 return rte_flow_error_set(error, ENOTSUP,
2344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345 "decap action for VF representor "
2346 "not supported on NIC table");
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2353 * Validate the raw encap and decap actions.
2356 * Pointer to the rte_eth_dev structure.
2358 * Pointer to the decap action.
2360 * Pointer to the encap action.
2362 * Pointer to flow attributes
2363 * @param[in/out] action_flags
2364 * Holds the actions detected until now.
2365 * @param[out] actions_n
2366 * pointer to the number of actions counter.
2368 * Pointer to error structure.
2371 * 0 on success, a negative errno value otherwise and rte_errno is set.
2374 flow_dv_validate_action_raw_encap_decap
2375 (struct rte_eth_dev *dev,
2376 const struct rte_flow_action_raw_decap *decap,
2377 const struct rte_flow_action_raw_encap *encap,
2378 const struct rte_flow_attr *attr, uint64_t *action_flags,
2379 int *actions_n, struct rte_flow_error *error)
2381 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (encap && (!encap->size || !encap->data))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387 "raw encap data cannot be empty");
2388 if (decap && encap) {
2389 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2393 else if (encap->size <=
2394 MLX5_ENCAPSULATION_DECISION_SIZE &&
2396 MLX5_ENCAPSULATION_DECISION_SIZE)
2399 else if (encap->size >
2400 MLX5_ENCAPSULATION_DECISION_SIZE &&
2402 MLX5_ENCAPSULATION_DECISION_SIZE)
2403 /* 2 L2 actions: encap and decap. */
2406 return rte_flow_error_set(error,
2408 RTE_FLOW_ERROR_TYPE_ACTION,
2409 NULL, "unsupported too small "
2410 "raw decap and too small raw "
2411 "encap combination");
2414 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2418 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2422 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423 return rte_flow_error_set(error, ENOTSUP,
2424 RTE_FLOW_ERROR_TYPE_ACTION,
2426 "small raw encap size");
2427 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428 return rte_flow_error_set(error, EINVAL,
2429 RTE_FLOW_ERROR_TYPE_ACTION,
2431 "more than one encap action");
2432 if (!attr->transfer && priv->representor)
2433 return rte_flow_error_set
2435 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436 "encap action for VF representor "
2437 "not supported on NIC table");
2438 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2445 * Find existing encap/decap resource or create and register a new one.
2447 * @param[in, out] dev
2448 * Pointer to rte_eth_dev structure.
2449 * @param[in, out] resource
2450 * Pointer to encap/decap resource.
2451 * @parm[in, out] dev_flow
2452 * Pointer to the dev_flow.
2454 * pointer to error structure.
2457 * 0 on success otherwise -errno and errno is set.
2460 flow_dv_encap_decap_resource_register
2461 (struct rte_eth_dev *dev,
2462 struct mlx5_flow_dv_encap_decap_resource *resource,
2463 struct mlx5_flow *dev_flow,
2464 struct rte_flow_error *error)
2466 struct mlx5_priv *priv = dev->data->dev_private;
2467 struct mlx5_ibv_shared *sh = priv->sh;
2468 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469 struct mlx5dv_dr_domain *domain;
2471 resource->flags = dev_flow->dv.group ? 0 : 1;
2472 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2473 domain = sh->fdb_domain;
2474 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2475 domain = sh->rx_domain;
2477 domain = sh->tx_domain;
2478 /* Lookup a matching resource from cache. */
2479 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2480 if (resource->reformat_type == cache_resource->reformat_type &&
2481 resource->ft_type == cache_resource->ft_type &&
2482 resource->flags == cache_resource->flags &&
2483 resource->size == cache_resource->size &&
2484 !memcmp((const void *)resource->buf,
2485 (const void *)cache_resource->buf,
2487 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2488 (void *)cache_resource,
2489 rte_atomic32_read(&cache_resource->refcnt));
2490 rte_atomic32_inc(&cache_resource->refcnt);
2491 dev_flow->handle->dvh.encap_decap = cache_resource;
2495 /* Register new encap/decap resource. */
2496 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2497 if (!cache_resource)
2498 return rte_flow_error_set(error, ENOMEM,
2499 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2500 "cannot allocate resource memory");
2501 *cache_resource = *resource;
2502 cache_resource->verbs_action =
2503 mlx5_glue->dv_create_flow_action_packet_reformat
2504 (sh->ctx, cache_resource->reformat_type,
2505 cache_resource->ft_type, domain, cache_resource->flags,
2506 cache_resource->size,
2507 (cache_resource->size ? cache_resource->buf : NULL));
2508 if (!cache_resource->verbs_action) {
2509 rte_free(cache_resource);
2510 return rte_flow_error_set(error, ENOMEM,
2511 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2512 NULL, "cannot create action");
2514 rte_atomic32_init(&cache_resource->refcnt);
2515 rte_atomic32_inc(&cache_resource->refcnt);
2516 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2517 dev_flow->handle->dvh.encap_decap = cache_resource;
2518 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2519 (void *)cache_resource,
2520 rte_atomic32_read(&cache_resource->refcnt));
2525 * Find existing table jump resource or create and register a new one.
2527 * @param[in, out] dev
2528 * Pointer to rte_eth_dev structure.
2529 * @param[in, out] tbl
2530 * Pointer to flow table resource.
2531 * @parm[in, out] dev_flow
2532 * Pointer to the dev_flow.
2534 * pointer to error structure.
2537 * 0 on success otherwise -errno and errno is set.
2540 flow_dv_jump_tbl_resource_register
2541 (struct rte_eth_dev *dev __rte_unused,
2542 struct mlx5_flow_tbl_resource *tbl,
2543 struct mlx5_flow *dev_flow,
2544 struct rte_flow_error *error)
2546 struct mlx5_flow_tbl_data_entry *tbl_data =
2547 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2551 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2553 tbl_data->jump.action =
2554 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2556 if (!tbl_data->jump.action)
2557 return rte_flow_error_set(error, ENOMEM,
2558 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2559 NULL, "cannot create jump action");
2560 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2561 (void *)&tbl_data->jump, cnt);
2563 /* old jump should not make the table ref++. */
2564 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2565 MLX5_ASSERT(tbl_data->jump.action);
2566 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2567 (void *)&tbl_data->jump, cnt);
2569 rte_atomic32_inc(&tbl_data->jump.refcnt);
2570 dev_flow->handle->dvh.jump = &tbl_data->jump;
2575 * Find existing table port ID resource or create and register a new one.
2577 * @param[in, out] dev
2578 * Pointer to rte_eth_dev structure.
2579 * @param[in, out] resource
2580 * Pointer to port ID action resource.
2581 * @parm[in, out] dev_flow
2582 * Pointer to the dev_flow.
2584 * pointer to error structure.
2587 * 0 on success otherwise -errno and errno is set.
2590 flow_dv_port_id_action_resource_register
2591 (struct rte_eth_dev *dev,
2592 struct mlx5_flow_dv_port_id_action_resource *resource,
2593 struct mlx5_flow *dev_flow,
2594 struct rte_flow_error *error)
2596 struct mlx5_priv *priv = dev->data->dev_private;
2597 struct mlx5_ibv_shared *sh = priv->sh;
2598 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2600 /* Lookup a matching resource from cache. */
2601 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2602 if (resource->port_id == cache_resource->port_id) {
2603 DRV_LOG(DEBUG, "port id action resource resource %p: "
2605 (void *)cache_resource,
2606 rte_atomic32_read(&cache_resource->refcnt));
2607 rte_atomic32_inc(&cache_resource->refcnt);
2608 dev_flow->handle->dvh.port_id_action = cache_resource;
2612 /* Register new port id action resource. */
2613 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2614 if (!cache_resource)
2615 return rte_flow_error_set(error, ENOMEM,
2616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2617 "cannot allocate resource memory");
2618 *cache_resource = *resource;
2620 * Depending on rdma_core version the glue routine calls
2621 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2622 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2624 cache_resource->action =
2625 mlx5_glue->dr_create_flow_action_dest_port
2626 (priv->sh->fdb_domain, resource->port_id);
2627 if (!cache_resource->action) {
2628 rte_free(cache_resource);
2629 return rte_flow_error_set(error, ENOMEM,
2630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2631 NULL, "cannot create action");
2633 rte_atomic32_init(&cache_resource->refcnt);
2634 rte_atomic32_inc(&cache_resource->refcnt);
2635 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2636 dev_flow->handle->dvh.port_id_action = cache_resource;
2637 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2638 (void *)cache_resource,
2639 rte_atomic32_read(&cache_resource->refcnt));
2644 * Find existing push vlan resource or create and register a new one.
2646 * @param [in, out] dev
2647 * Pointer to rte_eth_dev structure.
2648 * @param[in, out] resource
2649 * Pointer to port ID action resource.
2650 * @parm[in, out] dev_flow
2651 * Pointer to the dev_flow.
2653 * pointer to error structure.
2656 * 0 on success otherwise -errno and errno is set.
2659 flow_dv_push_vlan_action_resource_register
2660 (struct rte_eth_dev *dev,
2661 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2662 struct mlx5_flow *dev_flow,
2663 struct rte_flow_error *error)
2665 struct mlx5_priv *priv = dev->data->dev_private;
2666 struct mlx5_ibv_shared *sh = priv->sh;
2667 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2668 struct mlx5dv_dr_domain *domain;
2670 /* Lookup a matching resource from cache. */
2671 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2672 if (resource->vlan_tag == cache_resource->vlan_tag &&
2673 resource->ft_type == cache_resource->ft_type) {
2674 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2676 (void *)cache_resource,
2677 rte_atomic32_read(&cache_resource->refcnt));
2678 rte_atomic32_inc(&cache_resource->refcnt);
2679 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2683 /* Register new push_vlan action resource. */
2684 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2685 if (!cache_resource)
2686 return rte_flow_error_set(error, ENOMEM,
2687 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2688 "cannot allocate resource memory");
2689 *cache_resource = *resource;
2690 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2691 domain = sh->fdb_domain;
2692 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2693 domain = sh->rx_domain;
2695 domain = sh->tx_domain;
2696 cache_resource->action =
2697 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2698 resource->vlan_tag);
2699 if (!cache_resource->action) {
2700 rte_free(cache_resource);
2701 return rte_flow_error_set(error, ENOMEM,
2702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2703 NULL, "cannot create action");
2705 rte_atomic32_init(&cache_resource->refcnt);
2706 rte_atomic32_inc(&cache_resource->refcnt);
2707 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2708 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2709 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2710 (void *)cache_resource,
2711 rte_atomic32_read(&cache_resource->refcnt));
2715 * Get the size of specific rte_flow_item_type
2717 * @param[in] item_type
2718 * Tested rte_flow_item_type.
2721 * sizeof struct item_type, 0 if void or irrelevant.
2724 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2728 switch (item_type) {
2729 case RTE_FLOW_ITEM_TYPE_ETH:
2730 retval = sizeof(struct rte_flow_item_eth);
2732 case RTE_FLOW_ITEM_TYPE_VLAN:
2733 retval = sizeof(struct rte_flow_item_vlan);
2735 case RTE_FLOW_ITEM_TYPE_IPV4:
2736 retval = sizeof(struct rte_flow_item_ipv4);
2738 case RTE_FLOW_ITEM_TYPE_IPV6:
2739 retval = sizeof(struct rte_flow_item_ipv6);
2741 case RTE_FLOW_ITEM_TYPE_UDP:
2742 retval = sizeof(struct rte_flow_item_udp);
2744 case RTE_FLOW_ITEM_TYPE_TCP:
2745 retval = sizeof(struct rte_flow_item_tcp);
2747 case RTE_FLOW_ITEM_TYPE_VXLAN:
2748 retval = sizeof(struct rte_flow_item_vxlan);
2750 case RTE_FLOW_ITEM_TYPE_GRE:
2751 retval = sizeof(struct rte_flow_item_gre);
2753 case RTE_FLOW_ITEM_TYPE_NVGRE:
2754 retval = sizeof(struct rte_flow_item_nvgre);
2756 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2757 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2759 case RTE_FLOW_ITEM_TYPE_MPLS:
2760 retval = sizeof(struct rte_flow_item_mpls);
2762 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2770 #define MLX5_ENCAP_IPV4_VERSION 0x40
2771 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2772 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2773 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2774 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2775 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2776 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2779 * Convert the encap action data from list of rte_flow_item to raw buffer
2782 * Pointer to rte_flow_item objects list.
2784 * Pointer to the output buffer.
2786 * Pointer to the output buffer size.
2788 * Pointer to the error structure.
2791 * 0 on success, a negative errno value otherwise and rte_errno is set.
2794 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2795 size_t *size, struct rte_flow_error *error)
2797 struct rte_ether_hdr *eth = NULL;
2798 struct rte_vlan_hdr *vlan = NULL;
2799 struct rte_ipv4_hdr *ipv4 = NULL;
2800 struct rte_ipv6_hdr *ipv6 = NULL;
2801 struct rte_udp_hdr *udp = NULL;
2802 struct rte_vxlan_hdr *vxlan = NULL;
2803 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2804 struct rte_gre_hdr *gre = NULL;
2806 size_t temp_size = 0;
2809 return rte_flow_error_set(error, EINVAL,
2810 RTE_FLOW_ERROR_TYPE_ACTION,
2811 NULL, "invalid empty data");
2812 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2813 len = flow_dv_get_item_len(items->type);
2814 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2815 return rte_flow_error_set(error, EINVAL,
2816 RTE_FLOW_ERROR_TYPE_ACTION,
2817 (void *)items->type,
2818 "items total size is too big"
2819 " for encap action");
2820 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2821 switch (items->type) {
2822 case RTE_FLOW_ITEM_TYPE_ETH:
2823 eth = (struct rte_ether_hdr *)&buf[temp_size];
2825 case RTE_FLOW_ITEM_TYPE_VLAN:
2826 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2828 return rte_flow_error_set(error, EINVAL,
2829 RTE_FLOW_ERROR_TYPE_ACTION,
2830 (void *)items->type,
2831 "eth header not found");
2832 if (!eth->ether_type)
2833 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2835 case RTE_FLOW_ITEM_TYPE_IPV4:
2836 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2838 return rte_flow_error_set(error, EINVAL,
2839 RTE_FLOW_ERROR_TYPE_ACTION,
2840 (void *)items->type,
2841 "neither eth nor vlan"
2843 if (vlan && !vlan->eth_proto)
2844 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2845 else if (eth && !eth->ether_type)
2846 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2847 if (!ipv4->version_ihl)
2848 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2849 MLX5_ENCAP_IPV4_IHL_MIN;
2850 if (!ipv4->time_to_live)
2851 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2853 case RTE_FLOW_ITEM_TYPE_IPV6:
2854 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2856 return rte_flow_error_set(error, EINVAL,
2857 RTE_FLOW_ERROR_TYPE_ACTION,
2858 (void *)items->type,
2859 "neither eth nor vlan"
2861 if (vlan && !vlan->eth_proto)
2862 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2863 else if (eth && !eth->ether_type)
2864 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2865 if (!ipv6->vtc_flow)
2867 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2868 if (!ipv6->hop_limits)
2869 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2871 case RTE_FLOW_ITEM_TYPE_UDP:
2872 udp = (struct rte_udp_hdr *)&buf[temp_size];
2874 return rte_flow_error_set(error, EINVAL,
2875 RTE_FLOW_ERROR_TYPE_ACTION,
2876 (void *)items->type,
2877 "ip header not found");
2878 if (ipv4 && !ipv4->next_proto_id)
2879 ipv4->next_proto_id = IPPROTO_UDP;
2880 else if (ipv6 && !ipv6->proto)
2881 ipv6->proto = IPPROTO_UDP;
2883 case RTE_FLOW_ITEM_TYPE_VXLAN:
2884 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2886 return rte_flow_error_set(error, EINVAL,
2887 RTE_FLOW_ERROR_TYPE_ACTION,
2888 (void *)items->type,
2889 "udp header not found");
2891 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2892 if (!vxlan->vx_flags)
2894 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2896 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2897 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2899 return rte_flow_error_set(error, EINVAL,
2900 RTE_FLOW_ERROR_TYPE_ACTION,
2901 (void *)items->type,
2902 "udp header not found");
2903 if (!vxlan_gpe->proto)
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 (void *)items->type,
2907 "next protocol not found");
2910 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2911 if (!vxlan_gpe->vx_flags)
2912 vxlan_gpe->vx_flags =
2913 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2915 case RTE_FLOW_ITEM_TYPE_GRE:
2916 case RTE_FLOW_ITEM_TYPE_NVGRE:
2917 gre = (struct rte_gre_hdr *)&buf[temp_size];
2919 return rte_flow_error_set(error, EINVAL,
2920 RTE_FLOW_ERROR_TYPE_ACTION,
2921 (void *)items->type,
2922 "next protocol not found");
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION,
2926 (void *)items->type,
2927 "ip header not found");
2928 if (ipv4 && !ipv4->next_proto_id)
2929 ipv4->next_proto_id = IPPROTO_GRE;
2930 else if (ipv6 && !ipv6->proto)
2931 ipv6->proto = IPPROTO_GRE;
2933 case RTE_FLOW_ITEM_TYPE_VOID:
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION,
2938 (void *)items->type,
2939 "unsupported item type");
2949 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2951 struct rte_ether_hdr *eth = NULL;
2952 struct rte_vlan_hdr *vlan = NULL;
2953 struct rte_ipv6_hdr *ipv6 = NULL;
2954 struct rte_udp_hdr *udp = NULL;
2958 eth = (struct rte_ether_hdr *)data;
2959 next_hdr = (char *)(eth + 1);
2960 proto = RTE_BE16(eth->ether_type);
2963 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2964 vlan = (struct rte_vlan_hdr *)next_hdr;
2965 proto = RTE_BE16(vlan->eth_proto);
2966 next_hdr += sizeof(struct rte_vlan_hdr);
2969 /* HW calculates IPv4 csum. no need to proceed */
2970 if (proto == RTE_ETHER_TYPE_IPV4)
2973 /* non IPv4/IPv6 header. not supported */
2974 if (proto != RTE_ETHER_TYPE_IPV6) {
2975 return rte_flow_error_set(error, ENOTSUP,
2976 RTE_FLOW_ERROR_TYPE_ACTION,
2977 NULL, "Cannot offload non IPv4/IPv6");
2980 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2982 /* ignore non UDP */
2983 if (ipv6->proto != IPPROTO_UDP)
2986 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2987 udp->dgram_cksum = 0;
2993 * Convert L2 encap action to DV specification.
2996 * Pointer to rte_eth_dev structure.
2998 * Pointer to action structure.
2999 * @param[in, out] dev_flow
3000 * Pointer to the mlx5_flow.
3001 * @param[in] transfer
3002 * Mark if the flow is E-Switch flow.
3004 * Pointer to the error structure.
3007 * 0 on success, a negative errno value otherwise and rte_errno is set.
3010 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3011 const struct rte_flow_action *action,
3012 struct mlx5_flow *dev_flow,
3014 struct rte_flow_error *error)
3016 const struct rte_flow_item *encap_data;
3017 const struct rte_flow_action_raw_encap *raw_encap_data;
3018 struct mlx5_flow_dv_encap_decap_resource res = {
3020 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3021 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3022 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3025 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3027 (const struct rte_flow_action_raw_encap *)action->conf;
3028 res.size = raw_encap_data->size;
3029 memcpy(res.buf, raw_encap_data->data, res.size);
3031 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3033 ((const struct rte_flow_action_vxlan_encap *)
3034 action->conf)->definition;
3037 ((const struct rte_flow_action_nvgre_encap *)
3038 action->conf)->definition;
3039 if (flow_dv_convert_encap_data(encap_data, res.buf,
3043 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3045 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3046 return rte_flow_error_set(error, EINVAL,
3047 RTE_FLOW_ERROR_TYPE_ACTION,
3048 NULL, "can't create L2 encap action");
3053 * Convert L2 decap action to DV specification.
3056 * Pointer to rte_eth_dev structure.
3057 * @param[in, out] dev_flow
3058 * Pointer to the mlx5_flow.
3059 * @param[in] transfer
3060 * Mark if the flow is E-Switch flow.
3062 * Pointer to the error structure.
3065 * 0 on success, a negative errno value otherwise and rte_errno is set.
3068 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3069 struct mlx5_flow *dev_flow,
3071 struct rte_flow_error *error)
3073 struct mlx5_flow_dv_encap_decap_resource res = {
3076 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3077 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3078 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3081 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3082 return rte_flow_error_set(error, EINVAL,
3083 RTE_FLOW_ERROR_TYPE_ACTION,
3084 NULL, "can't create L2 decap action");
3089 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3092 * Pointer to rte_eth_dev structure.
3094 * Pointer to action structure.
3095 * @param[in, out] dev_flow
3096 * Pointer to the mlx5_flow.
3098 * Pointer to the flow attributes.
3100 * Pointer to the error structure.
3103 * 0 on success, a negative errno value otherwise and rte_errno is set.
3106 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3107 const struct rte_flow_action *action,
3108 struct mlx5_flow *dev_flow,
3109 const struct rte_flow_attr *attr,
3110 struct rte_flow_error *error)
3112 const struct rte_flow_action_raw_encap *encap_data;
3113 struct mlx5_flow_dv_encap_decap_resource res;
3115 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3116 res.size = encap_data->size;
3117 memcpy(res.buf, encap_data->data, res.size);
3118 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3119 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3120 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3122 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3124 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3125 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3126 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3127 return rte_flow_error_set(error, EINVAL,
3128 RTE_FLOW_ERROR_TYPE_ACTION,
3129 NULL, "can't create encap action");
3134 * Create action push VLAN.
3137 * Pointer to rte_eth_dev structure.
3139 * Pointer to the flow attributes.
3141 * Pointer to the vlan to push to the Ethernet header.
3142 * @param[in, out] dev_flow
3143 * Pointer to the mlx5_flow.
3145 * Pointer to the error structure.
3148 * 0 on success, a negative errno value otherwise and rte_errno is set.
3151 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3152 const struct rte_flow_attr *attr,
3153 const struct rte_vlan_hdr *vlan,
3154 struct mlx5_flow *dev_flow,
3155 struct rte_flow_error *error)
3157 struct mlx5_flow_dv_push_vlan_action_resource res;
3160 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3163 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3165 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3166 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3167 return flow_dv_push_vlan_action_resource_register
3168 (dev, &res, dev_flow, error);
3172 * Validate the modify-header actions.
3174 * @param[in] action_flags
3175 * Holds the actions detected until now.
3177 * Pointer to the modify action.
3179 * Pointer to error structure.
3182 * 0 on success, a negative errno value otherwise and rte_errno is set.
3185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3186 const struct rte_flow_action *action,
3187 struct rte_flow_error *error)
3189 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3190 return rte_flow_error_set(error, EINVAL,
3191 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3192 NULL, "action configuration not set");
3193 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3194 return rte_flow_error_set(error, EINVAL,
3195 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3196 "can't have encap action before"
3202 * Validate the modify-header MAC address actions.
3204 * @param[in] action_flags
3205 * Holds the actions detected until now.
3207 * Pointer to the modify action.
3208 * @param[in] item_flags
3209 * Holds the items detected.
3211 * Pointer to error structure.
3214 * 0 on success, a negative errno value otherwise and rte_errno is set.
3217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3218 const struct rte_flow_action *action,
3219 const uint64_t item_flags,
3220 struct rte_flow_error *error)
3224 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3226 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3227 return rte_flow_error_set(error, EINVAL,
3228 RTE_FLOW_ERROR_TYPE_ACTION,
3230 "no L2 item in pattern");
3236 * Validate the modify-header IPv4 address actions.
3238 * @param[in] action_flags
3239 * Holds the actions detected until now.
3241 * Pointer to the modify action.
3242 * @param[in] item_flags
3243 * Holds the items detected.
3245 * Pointer to error structure.
3248 * 0 on success, a negative errno value otherwise and rte_errno is set.
3251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3252 const struct rte_flow_action *action,
3253 const uint64_t item_flags,
3254 struct rte_flow_error *error)
3259 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3261 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3262 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3263 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3264 if (!(item_flags & layer))
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION,
3268 "no ipv4 item in pattern");
3274 * Validate the modify-header IPv6 address actions.
3276 * @param[in] action_flags
3277 * Holds the actions detected until now.
3279 * Pointer to the modify action.
3280 * @param[in] item_flags
3281 * Holds the items detected.
3283 * Pointer to error structure.
3286 * 0 on success, a negative errno value otherwise and rte_errno is set.
3289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3290 const struct rte_flow_action *action,
3291 const uint64_t item_flags,
3292 struct rte_flow_error *error)
3297 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3299 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3300 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3301 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3302 if (!(item_flags & layer))
3303 return rte_flow_error_set(error, EINVAL,
3304 RTE_FLOW_ERROR_TYPE_ACTION,
3306 "no ipv6 item in pattern");
3312 * Validate the modify-header TP actions.
3314 * @param[in] action_flags
3315 * Holds the actions detected until now.
3317 * Pointer to the modify action.
3318 * @param[in] item_flags
3319 * Holds the items detected.
3321 * Pointer to error structure.
3324 * 0 on success, a negative errno value otherwise and rte_errno is set.
3327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3328 const struct rte_flow_action *action,
3329 const uint64_t item_flags,
3330 struct rte_flow_error *error)
3335 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3337 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3338 MLX5_FLOW_LAYER_INNER_L4 :
3339 MLX5_FLOW_LAYER_OUTER_L4;
3340 if (!(item_flags & layer))
3341 return rte_flow_error_set(error, EINVAL,
3342 RTE_FLOW_ERROR_TYPE_ACTION,
3343 NULL, "no transport layer "
3350 * Validate the modify-header actions of increment/decrement
3351 * TCP Sequence-number.
3353 * @param[in] action_flags
3354 * Holds the actions detected until now.
3356 * Pointer to the modify action.
3357 * @param[in] item_flags
3358 * Holds the items detected.
3360 * Pointer to error structure.
3363 * 0 on success, a negative errno value otherwise and rte_errno is set.
3366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3367 const struct rte_flow_action *action,
3368 const uint64_t item_flags,
3369 struct rte_flow_error *error)
3374 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3376 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3377 MLX5_FLOW_LAYER_INNER_L4_TCP :
3378 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3379 if (!(item_flags & layer))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3382 NULL, "no TCP item in"
3384 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3385 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3386 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3387 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3388 return rte_flow_error_set(error, EINVAL,
3389 RTE_FLOW_ERROR_TYPE_ACTION,
3391 "cannot decrease and increase"
3392 " TCP sequence number"
3393 " at the same time");
3399 * Validate the modify-header actions of increment/decrement
3400 * TCP Acknowledgment number.
3402 * @param[in] action_flags
3403 * Holds the actions detected until now.
3405 * Pointer to the modify action.
3406 * @param[in] item_flags
3407 * Holds the items detected.
3409 * Pointer to error structure.
3412 * 0 on success, a negative errno value otherwise and rte_errno is set.
3415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3416 const struct rte_flow_action *action,
3417 const uint64_t item_flags,
3418 struct rte_flow_error *error)
3423 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3425 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3426 MLX5_FLOW_LAYER_INNER_L4_TCP :
3427 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3428 if (!(item_flags & layer))
3429 return rte_flow_error_set(error, EINVAL,
3430 RTE_FLOW_ERROR_TYPE_ACTION,
3431 NULL, "no TCP item in"
3433 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3434 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3435 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3436 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3437 return rte_flow_error_set(error, EINVAL,
3438 RTE_FLOW_ERROR_TYPE_ACTION,
3440 "cannot decrease and increase"
3441 " TCP acknowledgment number"
3442 " at the same time");
3448 * Validate the modify-header TTL actions.
3450 * @param[in] action_flags
3451 * Holds the actions detected until now.
3453 * Pointer to the modify action.
3454 * @param[in] item_flags
3455 * Holds the items detected.
3457 * Pointer to error structure.
3460 * 0 on success, a negative errno value otherwise and rte_errno is set.
3463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3464 const struct rte_flow_action *action,
3465 const uint64_t item_flags,
3466 struct rte_flow_error *error)
3471 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3473 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3474 MLX5_FLOW_LAYER_INNER_L3 :
3475 MLX5_FLOW_LAYER_OUTER_L3;
3476 if (!(item_flags & layer))
3477 return rte_flow_error_set(error, EINVAL,
3478 RTE_FLOW_ERROR_TYPE_ACTION,
3480 "no IP protocol in pattern");
3486 * Validate jump action.
3489 * Pointer to the jump action.
3490 * @param[in] action_flags
3491 * Holds the actions detected until now.
3492 * @param[in] attributes
3493 * Pointer to flow attributes
3494 * @param[in] external
3495 * Action belongs to flow rule created by request external to PMD.
3497 * Pointer to error structure.
3500 * 0 on success, a negative errno value otherwise and rte_errno is set.
3503 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3504 uint64_t action_flags,
3505 const struct rte_flow_attr *attributes,
3506 bool external, struct rte_flow_error *error)
3508 uint32_t target_group, table;
3511 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3512 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3513 return rte_flow_error_set(error, EINVAL,
3514 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3515 "can't have 2 fate actions in"
3517 if (action_flags & MLX5_FLOW_ACTION_METER)
3518 return rte_flow_error_set(error, ENOTSUP,
3519 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3520 "jump with meter not support");
3522 return rte_flow_error_set(error, EINVAL,
3523 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3524 NULL, "action configuration not set");
3526 ((const struct rte_flow_action_jump *)action->conf)->group;
3527 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3528 true, &table, error);
3531 if (attributes->group == target_group)
3532 return rte_flow_error_set(error, EINVAL,
3533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3534 "target group must be other than"
3535 " the current flow group");
3540 * Validate the port_id action.
3543 * Pointer to rte_eth_dev structure.
3544 * @param[in] action_flags
3545 * Bit-fields that holds the actions detected until now.
3547 * Port_id RTE action structure.
3549 * Attributes of flow that includes this action.
3551 * Pointer to error structure.
3554 * 0 on success, a negative errno value otherwise and rte_errno is set.
3557 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3558 uint64_t action_flags,
3559 const struct rte_flow_action *action,
3560 const struct rte_flow_attr *attr,
3561 struct rte_flow_error *error)
3563 const struct rte_flow_action_port_id *port_id;
3564 struct mlx5_priv *act_priv;
3565 struct mlx5_priv *dev_priv;
3568 if (!attr->transfer)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3572 "port id action is valid in transfer"
3574 if (!action || !action->conf)
3575 return rte_flow_error_set(error, ENOTSUP,
3576 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3578 "port id action parameters must be"
3580 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3581 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3584 "can have only one fate actions in"
3586 dev_priv = mlx5_dev_to_eswitch_info(dev);
3588 return rte_flow_error_set(error, rte_errno,
3589 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3591 "failed to obtain E-Switch info");
3592 port_id = action->conf;
3593 port = port_id->original ? dev->data->port_id : port_id->id;
3594 act_priv = mlx5_port_to_eswitch_info(port, false);
3596 return rte_flow_error_set
3598 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3599 "failed to obtain E-Switch port id for port");
3600 if (act_priv->domain_id != dev_priv->domain_id)
3601 return rte_flow_error_set
3603 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3604 "port does not belong to"
3605 " E-Switch being configured");
3610 * Get the maximum number of modify header actions.
3613 * Pointer to rte_eth_dev structure.
3615 * Flags bits to check if root level.
3618 * Max number of modify header actions device can support.
3621 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3624 * There's no way to directly query the max cap. Although it has to be
3625 * acquried by iterative trial, it is a safe assumption that more
3626 * actions are supported by FW if extensive metadata register is
3627 * supported. (Only in the root table)
3629 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3630 return MLX5_MAX_MODIFY_NUM;
3632 return mlx5_flow_ext_mreg_supported(dev) ?
3633 MLX5_ROOT_TBL_MODIFY_NUM :
3634 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3638 * Validate the meter action.
3641 * Pointer to rte_eth_dev structure.
3642 * @param[in] action_flags
3643 * Bit-fields that holds the actions detected until now.
3645 * Pointer to the meter action.
3647 * Attributes of flow that includes this action.
3649 * Pointer to error structure.
3652 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3655 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3656 uint64_t action_flags,
3657 const struct rte_flow_action *action,
3658 const struct rte_flow_attr *attr,
3659 struct rte_flow_error *error)
3661 struct mlx5_priv *priv = dev->data->dev_private;
3662 const struct rte_flow_action_meter *am = action->conf;
3663 struct mlx5_flow_meter *fm;
3666 return rte_flow_error_set(error, EINVAL,
3667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668 "meter action conf is NULL");
3670 if (action_flags & MLX5_FLOW_ACTION_METER)
3671 return rte_flow_error_set(error, ENOTSUP,
3672 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673 "meter chaining not support");
3674 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3675 return rte_flow_error_set(error, ENOTSUP,
3676 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3677 "meter with jump not support");
3679 return rte_flow_error_set(error, ENOTSUP,
3680 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3682 "meter action not supported");
3683 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3685 return rte_flow_error_set(error, EINVAL,
3686 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3688 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3689 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3690 (!fm->attr.egress && !attr->egress && attr->ingress))))
3691 return rte_flow_error_set(error, EINVAL,
3692 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693 "Flow attributes are either invalid "
3694 "or have a conflict with current "
3695 "meter attributes");
3700 * Validate the modify-header IPv4 DSCP actions.
3702 * @param[in] action_flags
3703 * Holds the actions detected until now.
3705 * Pointer to the modify action.
3706 * @param[in] item_flags
3707 * Holds the items detected.
3709 * Pointer to error structure.
3712 * 0 on success, a negative errno value otherwise and rte_errno is set.
3715 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3716 const struct rte_flow_action *action,
3717 const uint64_t item_flags,
3718 struct rte_flow_error *error)
3722 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3724 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3725 return rte_flow_error_set(error, EINVAL,
3726 RTE_FLOW_ERROR_TYPE_ACTION,
3728 "no ipv4 item in pattern");
3734 * Validate the modify-header IPv6 DSCP actions.
3736 * @param[in] action_flags
3737 * Holds the actions detected until now.
3739 * Pointer to the modify action.
3740 * @param[in] item_flags
3741 * Holds the items detected.
3743 * Pointer to error structure.
3746 * 0 on success, a negative errno value otherwise and rte_errno is set.
3749 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3750 const struct rte_flow_action *action,
3751 const uint64_t item_flags,
3752 struct rte_flow_error *error)
3756 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3758 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3759 return rte_flow_error_set(error, EINVAL,
3760 RTE_FLOW_ERROR_TYPE_ACTION,
3762 "no ipv6 item in pattern");
3768 * Find existing modify-header resource or create and register a new one.
3770 * @param dev[in, out]
3771 * Pointer to rte_eth_dev structure.
3772 * @param[in, out] resource
3773 * Pointer to modify-header resource.
3774 * @parm[in, out] dev_flow
3775 * Pointer to the dev_flow.
3777 * pointer to error structure.
3780 * 0 on success otherwise -errno and errno is set.
3783 flow_dv_modify_hdr_resource_register
3784 (struct rte_eth_dev *dev,
3785 struct mlx5_flow_dv_modify_hdr_resource *resource,
3786 struct mlx5_flow *dev_flow,
3787 struct rte_flow_error *error)
3789 struct mlx5_priv *priv = dev->data->dev_private;
3790 struct mlx5_ibv_shared *sh = priv->sh;
3791 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3792 struct mlx5dv_dr_domain *ns;
3793 uint32_t actions_len;
3795 resource->flags = dev_flow->dv.group ? 0 :
3796 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3797 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3799 return rte_flow_error_set(error, EOVERFLOW,
3800 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3801 "too many modify header items");
3802 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3803 ns = sh->fdb_domain;
3804 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3808 /* Lookup a matching resource from cache. */
3809 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3810 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3811 if (resource->ft_type == cache_resource->ft_type &&
3812 resource->actions_num == cache_resource->actions_num &&
3813 resource->flags == cache_resource->flags &&
3814 !memcmp((const void *)resource->actions,
3815 (const void *)cache_resource->actions,
3817 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3818 (void *)cache_resource,
3819 rte_atomic32_read(&cache_resource->refcnt));
3820 rte_atomic32_inc(&cache_resource->refcnt);
3821 dev_flow->handle->dvh.modify_hdr = cache_resource;
3825 /* Register new modify-header resource. */
3826 cache_resource = rte_calloc(__func__, 1,
3827 sizeof(*cache_resource) + actions_len, 0);
3828 if (!cache_resource)
3829 return rte_flow_error_set(error, ENOMEM,
3830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3831 "cannot allocate resource memory");
3832 *cache_resource = *resource;
3833 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3834 cache_resource->verbs_action =
3835 mlx5_glue->dv_create_flow_action_modify_header
3836 (sh->ctx, cache_resource->ft_type, ns,
3837 cache_resource->flags, actions_len,
3838 (uint64_t *)cache_resource->actions);
3839 if (!cache_resource->verbs_action) {
3840 rte_free(cache_resource);
3841 return rte_flow_error_set(error, ENOMEM,
3842 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3843 NULL, "cannot create action");
3845 rte_atomic32_init(&cache_resource->refcnt);
3846 rte_atomic32_inc(&cache_resource->refcnt);
3847 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3848 dev_flow->handle->dvh.modify_hdr = cache_resource;
3849 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3850 (void *)cache_resource,
3851 rte_atomic32_read(&cache_resource->refcnt));
3856 * Get DV flow counter by index.
3859 * Pointer to the Ethernet device structure.
3861 * mlx5 flow counter index in the container.
3863 * mlx5 flow counter pool in the container,
3866 * Pointer to the counter, NULL otherwise.
3868 static struct mlx5_flow_counter *
3869 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3871 struct mlx5_flow_counter_pool **ppool)
3873 struct mlx5_priv *priv = dev->data->dev_private;
3874 struct mlx5_pools_container *cont;
3875 struct mlx5_flow_counter_pool *pool;
3879 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3880 idx -= MLX5_CNT_BATCH_OFFSET;
3883 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3884 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3885 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3889 return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3893 * Get a pool by devx counter ID.
3896 * Pointer to the counter container.
3898 * The counter devx ID.
3901 * The counter pool pointer if exists, NULL otherwise,
3903 static struct mlx5_flow_counter_pool *
3904 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3907 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3909 for (i = 0; i < n_valid; i++) {
3910 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3911 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3912 MLX5_COUNTERS_PER_POOL;
3914 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3916 * Move the pool to the head, as counter allocate
3917 * always gets the first pool in the container.
3919 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3920 TAILQ_REMOVE(&cont->pool_list, pool, next);
3921 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3930 * Allocate a new memory for the counter values wrapped by all the needed
3934 * Pointer to the Ethernet device structure.
3936 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3939 * The new memory management pointer on success, otherwise NULL and rte_errno
3942 static struct mlx5_counter_stats_mem_mng *
3943 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3945 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3946 (dev->data->dev_private))->sh;
3947 struct mlx5_devx_mkey_attr mkey_attr;
3948 struct mlx5_counter_stats_mem_mng *mem_mng;
3949 volatile struct flow_counter_stats *raw_data;
3950 int size = (sizeof(struct flow_counter_stats) *
3951 MLX5_COUNTERS_PER_POOL +
3952 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3953 sizeof(struct mlx5_counter_stats_mem_mng);
3954 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3961 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3962 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3963 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3964 IBV_ACCESS_LOCAL_WRITE);
3965 if (!mem_mng->umem) {
3970 mkey_attr.addr = (uintptr_t)mem;
3971 mkey_attr.size = size;
3972 mkey_attr.umem_id = mem_mng->umem->umem_id;
3973 mkey_attr.pd = sh->pdn;
3974 mkey_attr.log_entity_size = 0;
3975 mkey_attr.pg_access = 0;
3976 mkey_attr.klm_array = NULL;
3977 mkey_attr.klm_num = 0;
3978 mkey_attr.relaxed_ordering = 1;
3979 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3981 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3986 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3987 raw_data = (volatile struct flow_counter_stats *)mem;
3988 for (i = 0; i < raws_n; ++i) {
3989 mem_mng->raws[i].mem_mng = mem_mng;
3990 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3992 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3997 * Resize a counter container.
4000 * Pointer to the Ethernet device structure.
4002 * Whether the pool is for counter that was allocated by batch command.
4005 * The new container pointer on success, otherwise NULL and rte_errno is set.
4007 static struct mlx5_pools_container *
4008 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4010 struct mlx5_priv *priv = dev->data->dev_private;
4011 struct mlx5_pools_container *cont =
4012 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4013 struct mlx5_pools_container *new_cont =
4014 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4015 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4016 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4017 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4020 /* Fallback mode has no background thread. Skip the check. */
4021 if (!priv->counter_fallback &&
4022 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4023 /* The last resize still hasn't detected by the host thread. */
4027 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4028 if (!new_cont->pools) {
4033 memcpy(new_cont->pools, cont->pools, cont->n *
4034 sizeof(struct mlx5_flow_counter_pool *));
4036 * Fallback mode query the counter directly, no background query
4037 * resources are needed.
4039 if (!priv->counter_fallback) {
4040 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4041 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4043 rte_free(new_cont->pools);
4046 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4047 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4049 MLX5_CNT_CONTAINER_RESIZE +
4053 * Release the old container pools directly as no background
4054 * thread helps that.
4056 rte_free(cont->pools);
4058 new_cont->n = resize;
4059 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4060 TAILQ_INIT(&new_cont->pool_list);
4061 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4062 new_cont->init_mem_mng = mem_mng;
4064 /* Flip the master container. */
4065 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4070 * Query a devx flow counter.
4073 * Pointer to the Ethernet device structure.
4075 * Index to the flow counter.
4077 * The statistics value of packets.
4079 * The statistics value of bytes.
4082 * 0 on success, otherwise a negative errno value and rte_errno is set.
4085 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4088 struct mlx5_priv *priv = dev->data->dev_private;
4089 struct mlx5_flow_counter_pool *pool = NULL;
4090 struct mlx5_flow_counter *cnt;
4091 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4094 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4096 if (counter < MLX5_CNT_BATCH_OFFSET) {
4097 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4098 if (priv->counter_fallback)
4099 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4100 0, pkts, bytes, 0, NULL, NULL, 0);
4103 rte_spinlock_lock(&pool->sl);
4105 * The single counters allocation may allocate smaller ID than the
4106 * current allocated in parallel to the host reading.
4107 * In this case the new counter values must be reported as 0.
4109 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4113 offset = cnt - &pool->counters_raw[0];
4114 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4115 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4117 rte_spinlock_unlock(&pool->sl);
4122 * Create and initialize a new counter pool.
4125 * Pointer to the Ethernet device structure.
4127 * The devX counter handle.
4129 * Whether the pool is for counter that was allocated by batch command.
4130 * @param[in/out] cont_cur
4131 * Pointer to the container pointer, it will be update in pool resize.
4134 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4136 static struct mlx5_pools_container *
4137 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4140 struct mlx5_priv *priv = dev->data->dev_private;
4141 struct mlx5_flow_counter_pool *pool;
4142 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4144 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4147 if (cont->n == n_valid) {
4148 cont = flow_dv_container_resize(dev, batch);
4152 size = sizeof(*pool);
4154 size += MLX5_COUNTERS_PER_POOL *
4155 sizeof(struct mlx5_flow_counter_ext);
4156 pool = rte_calloc(__func__, 1, size, 0);
4161 pool->min_dcs = dcs;
4162 if (!priv->counter_fallback)
4163 pool->raw = cont->init_mem_mng->raws + n_valid %
4164 MLX5_CNT_CONTAINER_RESIZE;
4165 pool->raw_hw = NULL;
4166 rte_spinlock_init(&pool->sl);
4168 * The generation of the new allocated counters in this pool is 0, 2 in
4169 * the pool generation makes all the counters valid for allocation.
4170 * The start and end query generation protect the counters be released
4171 * between the query and update gap period will not be reallocated
4172 * without the last query finished and stats updated to the memory.
4174 rte_atomic64_set(&pool->start_query_gen, 0x2);
4176 * There's no background query thread for fallback mode, set the
4177 * end_query_gen to the maximum value since no need to wait for
4178 * statistics update.
4180 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4182 TAILQ_INIT(&pool->counters);
4183 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4184 pool->index = n_valid;
4185 cont->pools[n_valid] = pool;
4186 /* Pool initialization must be updated before host thread access. */
4188 rte_atomic16_add(&cont->n_valid, 1);
4193 * Prepare a new counter and/or a new counter pool.
4196 * Pointer to the Ethernet device structure.
4197 * @param[out] cnt_free
4198 * Where to put the pointer of a new counter.
4200 * Whether the pool is for counter that was allocated by batch command.
4203 * The counter container pointer and @p cnt_free is set on success,
4204 * NULL otherwise and rte_errno is set.
4206 static struct mlx5_pools_container *
4207 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4208 struct mlx5_flow_counter **cnt_free,
4211 struct mlx5_priv *priv = dev->data->dev_private;
4212 struct mlx5_pools_container *cont;
4213 struct mlx5_flow_counter_pool *pool;
4214 struct mlx5_devx_obj *dcs = NULL;
4215 struct mlx5_flow_counter *cnt;
4218 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4220 /* bulk_bitmap must be 0 for single counter allocation. */
4221 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4224 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4226 cont = flow_dv_pool_create(dev, dcs, batch);
4228 mlx5_devx_cmd_destroy(dcs);
4231 pool = TAILQ_FIRST(&cont->pool_list);
4232 } else if (dcs->id < pool->min_dcs->id) {
4233 rte_atomic64_set(&pool->a64_dcs,
4234 (int64_t)(uintptr_t)dcs);
4236 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4237 cnt = &pool->counters_raw[i];
4238 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4239 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4243 /* bulk_bitmap is in 128 counters units. */
4244 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4245 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4247 rte_errno = ENODATA;
4250 cont = flow_dv_pool_create(dev, dcs, batch);
4252 mlx5_devx_cmd_destroy(dcs);
4255 pool = TAILQ_FIRST(&cont->pool_list);
4256 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4257 cnt = &pool->counters_raw[i];
4258 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4260 *cnt_free = &pool->counters_raw[0];
4265 * Search for existed shared counter.
4268 * Pointer to the relevant counter pool container.
4270 * The shared counter ID to search.
4272 * mlx5 flow counter pool in the container,
4275 * NULL if not existed, otherwise pointer to the shared extend counter.
4277 static struct mlx5_flow_counter_ext *
4278 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4279 struct mlx5_flow_counter_pool **ppool)
4281 static struct mlx5_flow_counter_ext *cnt;
4282 struct mlx5_flow_counter_pool *pool;
4284 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4286 for (i = 0; i < n_valid; i++) {
4287 pool = cont->pools[i];
4288 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4289 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4290 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4292 *ppool = cont->pools[i];
4301 * Allocate a flow counter.
4304 * Pointer to the Ethernet device structure.
4306 * Indicate if this counter is shared with other flows.
4308 * Counter identifier.
4310 * Counter flow group.
4313 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4316 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4319 struct mlx5_priv *priv = dev->data->dev_private;
4320 struct mlx5_flow_counter_pool *pool = NULL;
4321 struct mlx5_flow_counter *cnt_free = NULL;
4322 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4324 * Currently group 0 flow counter cannot be assigned to a flow if it is
4325 * not the first one in the batch counter allocation, so it is better
4326 * to allocate counters one by one for these flows in a separate
4328 * A counter can be shared between different groups so need to take
4329 * shared counters from the single container.
4331 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4332 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4336 if (!priv->config.devx) {
4337 rte_errno = ENOTSUP;
4341 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4343 if (cnt_ext->ref_cnt + 1 == 0) {
4348 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4349 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4354 /* Pools which has a free counters are in the start. */
4355 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4357 * The free counter reset values must be updated between the
4358 * counter release to the counter allocation, so, at least one
4359 * query must be done in this time. ensure it by saving the
4360 * query generation in the release time.
4361 * The free list is sorted according to the generation - so if
4362 * the first one is not updated, all the others are not
4365 cnt_free = TAILQ_FIRST(&pool->counters);
4366 if (cnt_free && cnt_free->query_gen <
4367 rte_atomic64_read(&pool->end_query_gen))
4372 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4375 pool = TAILQ_FIRST(&cont->pool_list);
4378 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4379 /* Create a DV counter action only in the first time usage. */
4380 if (!cnt_free->action) {
4382 struct mlx5_devx_obj *dcs;
4385 offset = cnt_free - &pool->counters_raw[0];
4386 dcs = pool->min_dcs;
4391 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4393 if (!cnt_free->action) {
4398 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4399 (cnt_free - pool->counters_raw));
4400 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4401 /* Update the counter reset values. */
4402 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4406 cnt_ext->shared = shared;
4407 cnt_ext->ref_cnt = 1;
4410 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4411 /* Start the asynchronous batch query by the host thread. */
4412 mlx5_set_query_alarm(priv->sh);
4413 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4414 if (TAILQ_EMPTY(&pool->counters)) {
4415 /* Move the pool to the end of the container pool list. */
4416 TAILQ_REMOVE(&cont->pool_list, pool, next);
4417 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4423 * Release a flow counter.
4426 * Pointer to the Ethernet device structure.
4427 * @param[in] counter
4428 * Index to the counter handler.
4431 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4433 struct mlx5_flow_counter_pool *pool = NULL;
4434 struct mlx5_flow_counter *cnt;
4435 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4439 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4441 if (counter < MLX5_CNT_BATCH_OFFSET) {
4442 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4443 if (cnt_ext && --cnt_ext->ref_cnt)
4446 /* Put the counter in the end - the last updated one. */
4447 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4449 * Counters released between query trigger and handler need
4450 * to wait the next round of query. Since the packets arrive
4451 * in the gap period will not be taken into account to the
4454 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4458 * Verify the @p attributes will be correctly understood by the NIC and store
4459 * them in the @p flow if everything is correct.
4462 * Pointer to dev struct.
4463 * @param[in] attributes
4464 * Pointer to flow attributes
4465 * @param[in] external
4466 * This flow rule is created by request external to PMD.
4468 * Pointer to error structure.
4471 * 0 on success, a negative errno value otherwise and rte_errno is set.
4474 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4475 const struct rte_flow_attr *attributes,
4476 bool external __rte_unused,
4477 struct rte_flow_error *error)
4479 struct mlx5_priv *priv = dev->data->dev_private;
4480 uint32_t priority_max = priv->config.flow_prio - 1;
4482 #ifndef HAVE_MLX5DV_DR
4483 if (attributes->group)
4484 return rte_flow_error_set(error, ENOTSUP,
4485 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4487 "groups are not supported");
4492 ret = mlx5_flow_group_to_table(attributes, external,
4493 attributes->group, !!priv->fdb_def_rule,
4498 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4499 attributes->priority >= priority_max)
4500 return rte_flow_error_set(error, ENOTSUP,
4501 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4503 "priority out of range");
4504 if (attributes->transfer) {
4505 if (!priv->config.dv_esw_en)
4506 return rte_flow_error_set
4508 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4509 "E-Switch dr is not supported");
4510 if (!(priv->representor || priv->master))
4511 return rte_flow_error_set
4512 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4513 NULL, "E-Switch configuration can only be"
4514 " done by a master or a representor device");
4515 if (attributes->egress)
4516 return rte_flow_error_set
4518 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4519 "egress is not supported");
4521 if (!(attributes->egress ^ attributes->ingress))
4522 return rte_flow_error_set(error, ENOTSUP,
4523 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4524 "must specify exactly one of "
4525 "ingress or egress");
4530 * Internal validation function. For validating both actions and items.
4533 * Pointer to the rte_eth_dev structure.
4535 * Pointer to the flow attributes.
4537 * Pointer to the list of items.
4538 * @param[in] actions
4539 * Pointer to the list of actions.
4540 * @param[in] external
4541 * This flow rule is created by request external to PMD.
4543 * Pointer to the error structure.
4546 * 0 on success, a negative errno value otherwise and rte_errno is set.
4549 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4550 const struct rte_flow_item items[],
4551 const struct rte_flow_action actions[],
4552 bool external, struct rte_flow_error *error)
4555 uint64_t action_flags = 0;
4556 uint64_t item_flags = 0;
4557 uint64_t last_item = 0;
4558 uint8_t next_protocol = 0xff;
4559 uint16_t ether_type = 0;
4561 uint8_t item_ipv6_proto = 0;
4562 const struct rte_flow_item *gre_item = NULL;
4563 const struct rte_flow_action_raw_decap *decap;
4564 const struct rte_flow_action_raw_encap *encap;
4565 const struct rte_flow_action_rss *rss;
4566 const struct rte_flow_item_tcp nic_tcp_mask = {
4569 .src_port = RTE_BE16(UINT16_MAX),
4570 .dst_port = RTE_BE16(UINT16_MAX),
4573 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4575 .src_addr = RTE_BE32(0xffffffff),
4576 .dst_addr = RTE_BE32(0xffffffff),
4577 .type_of_service = 0xff,
4578 .next_proto_id = 0xff,
4579 .time_to_live = 0xff,
4582 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4585 "\xff\xff\xff\xff\xff\xff\xff\xff"
4586 "\xff\xff\xff\xff\xff\xff\xff\xff",
4588 "\xff\xff\xff\xff\xff\xff\xff\xff"
4589 "\xff\xff\xff\xff\xff\xff\xff\xff",
4590 .vtc_flow = RTE_BE32(0xffffffff),
4595 struct mlx5_priv *priv = dev->data->dev_private;
4596 struct mlx5_dev_config *dev_conf = &priv->config;
4597 uint16_t queue_index = 0xFFFF;
4598 const struct rte_flow_item_vlan *vlan_m = NULL;
4602 ret = flow_dv_validate_attributes(dev, attr, external, error);
4605 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4606 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4607 int type = items->type;
4610 case RTE_FLOW_ITEM_TYPE_VOID:
4612 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4613 ret = flow_dv_validate_item_port_id
4614 (dev, items, attr, item_flags, error);
4617 last_item = MLX5_FLOW_ITEM_PORT_ID;
4619 case RTE_FLOW_ITEM_TYPE_ETH:
4620 ret = mlx5_flow_validate_item_eth(items, item_flags,
4624 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4625 MLX5_FLOW_LAYER_OUTER_L2;
4626 if (items->mask != NULL && items->spec != NULL) {
4628 ((const struct rte_flow_item_eth *)
4631 ((const struct rte_flow_item_eth *)
4633 ether_type = rte_be_to_cpu_16(ether_type);
4638 case RTE_FLOW_ITEM_TYPE_VLAN:
4639 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4643 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4644 MLX5_FLOW_LAYER_OUTER_VLAN;
4645 if (items->mask != NULL && items->spec != NULL) {
4647 ((const struct rte_flow_item_vlan *)
4648 items->spec)->inner_type;
4650 ((const struct rte_flow_item_vlan *)
4651 items->mask)->inner_type;
4652 ether_type = rte_be_to_cpu_16(ether_type);
4656 /* Store outer VLAN mask for of_push_vlan action. */
4658 vlan_m = items->mask;
4660 case RTE_FLOW_ITEM_TYPE_IPV4:
4661 mlx5_flow_tunnel_ip_check(items, next_protocol,
4662 &item_flags, &tunnel);
4663 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4670 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4671 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4672 if (items->mask != NULL &&
4673 ((const struct rte_flow_item_ipv4 *)
4674 items->mask)->hdr.next_proto_id) {
4676 ((const struct rte_flow_item_ipv4 *)
4677 (items->spec))->hdr.next_proto_id;
4679 ((const struct rte_flow_item_ipv4 *)
4680 (items->mask))->hdr.next_proto_id;
4682 /* Reset for inner layer. */
4683 next_protocol = 0xff;
4686 case RTE_FLOW_ITEM_TYPE_IPV6:
4687 mlx5_flow_tunnel_ip_check(items, next_protocol,
4688 &item_flags, &tunnel);
4689 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4696 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4697 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4698 if (items->mask != NULL &&
4699 ((const struct rte_flow_item_ipv6 *)
4700 items->mask)->hdr.proto) {
4702 ((const struct rte_flow_item_ipv6 *)
4703 items->spec)->hdr.proto;
4705 ((const struct rte_flow_item_ipv6 *)
4706 items->spec)->hdr.proto;
4708 ((const struct rte_flow_item_ipv6 *)
4709 items->mask)->hdr.proto;
4711 /* Reset for inner layer. */
4712 next_protocol = 0xff;
4715 case RTE_FLOW_ITEM_TYPE_TCP:
4716 ret = mlx5_flow_validate_item_tcp
4723 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4724 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4726 case RTE_FLOW_ITEM_TYPE_UDP:
4727 ret = mlx5_flow_validate_item_udp(items, item_flags,
4732 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4733 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4735 case RTE_FLOW_ITEM_TYPE_GRE:
4736 ret = mlx5_flow_validate_item_gre(items, item_flags,
4737 next_protocol, error);
4741 last_item = MLX5_FLOW_LAYER_GRE;
4743 case RTE_FLOW_ITEM_TYPE_NVGRE:
4744 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4749 last_item = MLX5_FLOW_LAYER_NVGRE;
4751 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4752 ret = mlx5_flow_validate_item_gre_key
4753 (items, item_flags, gre_item, error);
4756 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4758 case RTE_FLOW_ITEM_TYPE_VXLAN:
4759 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4763 last_item = MLX5_FLOW_LAYER_VXLAN;
4765 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4766 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4771 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4773 case RTE_FLOW_ITEM_TYPE_GENEVE:
4774 ret = mlx5_flow_validate_item_geneve(items,
4779 last_item = MLX5_FLOW_LAYER_GENEVE;
4781 case RTE_FLOW_ITEM_TYPE_MPLS:
4782 ret = mlx5_flow_validate_item_mpls(dev, items,
4787 last_item = MLX5_FLOW_LAYER_MPLS;
4790 case RTE_FLOW_ITEM_TYPE_MARK:
4791 ret = flow_dv_validate_item_mark(dev, items, attr,
4795 last_item = MLX5_FLOW_ITEM_MARK;
4797 case RTE_FLOW_ITEM_TYPE_META:
4798 ret = flow_dv_validate_item_meta(dev, items, attr,
4802 last_item = MLX5_FLOW_ITEM_METADATA;
4804 case RTE_FLOW_ITEM_TYPE_ICMP:
4805 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4810 last_item = MLX5_FLOW_LAYER_ICMP;
4812 case RTE_FLOW_ITEM_TYPE_ICMP6:
4813 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4818 item_ipv6_proto = IPPROTO_ICMPV6;
4819 last_item = MLX5_FLOW_LAYER_ICMP6;
4821 case RTE_FLOW_ITEM_TYPE_TAG:
4822 ret = flow_dv_validate_item_tag(dev, items,
4826 last_item = MLX5_FLOW_ITEM_TAG;
4828 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4829 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4831 case RTE_FLOW_ITEM_TYPE_GTP:
4832 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4836 last_item = MLX5_FLOW_LAYER_GTP;
4839 return rte_flow_error_set(error, ENOTSUP,
4840 RTE_FLOW_ERROR_TYPE_ITEM,
4841 NULL, "item not supported");
4843 item_flags |= last_item;
4845 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4846 int type = actions->type;
4847 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4848 return rte_flow_error_set(error, ENOTSUP,
4849 RTE_FLOW_ERROR_TYPE_ACTION,
4850 actions, "too many actions");
4852 case RTE_FLOW_ACTION_TYPE_VOID:
4854 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4855 ret = flow_dv_validate_action_port_id(dev,
4862 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4865 case RTE_FLOW_ACTION_TYPE_FLAG:
4866 ret = flow_dv_validate_action_flag(dev, action_flags,
4870 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4871 /* Count all modify-header actions as one. */
4872 if (!(action_flags &
4873 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4875 action_flags |= MLX5_FLOW_ACTION_FLAG |
4876 MLX5_FLOW_ACTION_MARK_EXT;
4878 action_flags |= MLX5_FLOW_ACTION_FLAG;
4882 case RTE_FLOW_ACTION_TYPE_MARK:
4883 ret = flow_dv_validate_action_mark(dev, actions,
4888 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4889 /* Count all modify-header actions as one. */
4890 if (!(action_flags &
4891 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4893 action_flags |= MLX5_FLOW_ACTION_MARK |
4894 MLX5_FLOW_ACTION_MARK_EXT;
4896 action_flags |= MLX5_FLOW_ACTION_MARK;
4900 case RTE_FLOW_ACTION_TYPE_SET_META:
4901 ret = flow_dv_validate_action_set_meta(dev, actions,
4906 /* Count all modify-header actions as one action. */
4907 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4909 action_flags |= MLX5_FLOW_ACTION_SET_META;
4911 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4912 ret = flow_dv_validate_action_set_tag(dev, actions,
4917 /* Count all modify-header actions as one action. */
4918 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4920 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4922 case RTE_FLOW_ACTION_TYPE_DROP:
4923 ret = mlx5_flow_validate_action_drop(action_flags,
4927 action_flags |= MLX5_FLOW_ACTION_DROP;
4930 case RTE_FLOW_ACTION_TYPE_QUEUE:
4931 ret = mlx5_flow_validate_action_queue(actions,
4936 queue_index = ((const struct rte_flow_action_queue *)
4937 (actions->conf))->index;
4938 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4941 case RTE_FLOW_ACTION_TYPE_RSS:
4942 rss = actions->conf;
4943 ret = mlx5_flow_validate_action_rss(actions,
4949 if (rss != NULL && rss->queue_num)
4950 queue_index = rss->queue[0];
4951 action_flags |= MLX5_FLOW_ACTION_RSS;
4954 case RTE_FLOW_ACTION_TYPE_COUNT:
4955 ret = flow_dv_validate_action_count(dev, error);
4958 action_flags |= MLX5_FLOW_ACTION_COUNT;
4961 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4962 if (flow_dv_validate_action_pop_vlan(dev,
4968 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4971 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4972 ret = flow_dv_validate_action_push_vlan(dev,
4979 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4982 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4983 ret = flow_dv_validate_action_set_vlan_pcp
4984 (action_flags, actions, error);
4987 /* Count PCP with push_vlan command. */
4988 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4990 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4991 ret = flow_dv_validate_action_set_vlan_vid
4992 (item_flags, action_flags,
4996 /* Count VID with push_vlan command. */
4997 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4999 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5000 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5001 ret = flow_dv_validate_action_l2_encap(dev,
5007 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5010 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5011 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5012 ret = flow_dv_validate_action_decap(dev, action_flags,
5016 action_flags |= MLX5_FLOW_ACTION_DECAP;
5019 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5020 ret = flow_dv_validate_action_raw_encap_decap
5021 (dev, NULL, actions->conf, attr, &action_flags,
5026 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5027 decap = actions->conf;
5028 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5030 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5034 encap = actions->conf;
5036 ret = flow_dv_validate_action_raw_encap_decap
5038 decap ? decap : &empty_decap, encap,
5039 attr, &action_flags, &actions_n,
5044 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5045 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5046 ret = flow_dv_validate_action_modify_mac(action_flags,
5052 /* Count all modify-header actions as one action. */
5053 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5055 action_flags |= actions->type ==
5056 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5057 MLX5_FLOW_ACTION_SET_MAC_SRC :
5058 MLX5_FLOW_ACTION_SET_MAC_DST;
5061 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5062 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5063 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5069 /* Count all modify-header actions as one action. */
5070 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5072 action_flags |= actions->type ==
5073 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5074 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5075 MLX5_FLOW_ACTION_SET_IPV4_DST;
5077 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5078 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5079 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5085 if (item_ipv6_proto == IPPROTO_ICMPV6)
5086 return rte_flow_error_set(error, ENOTSUP,
5087 RTE_FLOW_ERROR_TYPE_ACTION,
5089 "Can't change header "
5090 "with ICMPv6 proto");
5091 /* Count all modify-header actions as one action. */
5092 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5094 action_flags |= actions->type ==
5095 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5096 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5097 MLX5_FLOW_ACTION_SET_IPV6_DST;
5099 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5100 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5101 ret = flow_dv_validate_action_modify_tp(action_flags,
5107 /* Count all modify-header actions as one action. */
5108 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5110 action_flags |= actions->type ==
5111 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5112 MLX5_FLOW_ACTION_SET_TP_SRC :
5113 MLX5_FLOW_ACTION_SET_TP_DST;
5115 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5116 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5117 ret = flow_dv_validate_action_modify_ttl(action_flags,
5123 /* Count all modify-header actions as one action. */
5124 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5126 action_flags |= actions->type ==
5127 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5128 MLX5_FLOW_ACTION_SET_TTL :
5129 MLX5_FLOW_ACTION_DEC_TTL;
5131 case RTE_FLOW_ACTION_TYPE_JUMP:
5132 ret = flow_dv_validate_action_jump(actions,
5139 action_flags |= MLX5_FLOW_ACTION_JUMP;
5141 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5142 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5143 ret = flow_dv_validate_action_modify_tcp_seq
5150 /* Count all modify-header actions as one action. */
5151 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5153 action_flags |= actions->type ==
5154 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5155 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5156 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5158 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5159 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5160 ret = flow_dv_validate_action_modify_tcp_ack
5167 /* Count all modify-header actions as one action. */
5168 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5170 action_flags |= actions->type ==
5171 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5172 MLX5_FLOW_ACTION_INC_TCP_ACK :
5173 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5175 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5176 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5177 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5179 case RTE_FLOW_ACTION_TYPE_METER:
5180 ret = mlx5_flow_validate_action_meter(dev,
5186 action_flags |= MLX5_FLOW_ACTION_METER;
5189 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5190 ret = flow_dv_validate_action_modify_ipv4_dscp
5197 /* Count all modify-header actions as one action. */
5198 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5200 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5202 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5203 ret = flow_dv_validate_action_modify_ipv6_dscp
5210 /* Count all modify-header actions as one action. */
5211 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5213 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5216 return rte_flow_error_set(error, ENOTSUP,
5217 RTE_FLOW_ERROR_TYPE_ACTION,
5219 "action not supported");
5223 * Validate the drop action mutual exclusion with other actions.
5224 * Drop action is mutually-exclusive with any other action, except for
5227 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5228 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5229 return rte_flow_error_set(error, EINVAL,
5230 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5231 "Drop action is mutually-exclusive "
5232 "with any other action, except for "
5234 /* Eswitch has few restrictions on using items and actions */
5235 if (attr->transfer) {
5236 if (!mlx5_flow_ext_mreg_supported(dev) &&
5237 action_flags & MLX5_FLOW_ACTION_FLAG)
5238 return rte_flow_error_set(error, ENOTSUP,
5239 RTE_FLOW_ERROR_TYPE_ACTION,
5241 "unsupported action FLAG");
5242 if (!mlx5_flow_ext_mreg_supported(dev) &&
5243 action_flags & MLX5_FLOW_ACTION_MARK)
5244 return rte_flow_error_set(error, ENOTSUP,
5245 RTE_FLOW_ERROR_TYPE_ACTION,
5247 "unsupported action MARK");
5248 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5249 return rte_flow_error_set(error, ENOTSUP,
5250 RTE_FLOW_ERROR_TYPE_ACTION,
5252 "unsupported action QUEUE");
5253 if (action_flags & MLX5_FLOW_ACTION_RSS)
5254 return rte_flow_error_set(error, ENOTSUP,
5255 RTE_FLOW_ERROR_TYPE_ACTION,
5257 "unsupported action RSS");
5258 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5259 return rte_flow_error_set(error, EINVAL,
5260 RTE_FLOW_ERROR_TYPE_ACTION,
5262 "no fate action is found");
5264 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5265 return rte_flow_error_set(error, EINVAL,
5266 RTE_FLOW_ERROR_TYPE_ACTION,
5268 "no fate action is found");
5270 /* Continue validation for Xcap actions.*/
5271 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5272 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5273 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5274 MLX5_FLOW_XCAP_ACTIONS)
5275 return rte_flow_error_set(error, ENOTSUP,
5276 RTE_FLOW_ERROR_TYPE_ACTION,
5277 NULL, "encap and decap "
5278 "combination aren't supported");
5279 if (!attr->transfer && attr->ingress && (action_flags &
5280 MLX5_FLOW_ACTION_ENCAP))
5281 return rte_flow_error_set(error, ENOTSUP,
5282 RTE_FLOW_ERROR_TYPE_ACTION,
5283 NULL, "encap is not supported"
5284 " for ingress traffic");
5290 * Internal preparation function. Allocates the DV flow size,
5291 * this size is constant.
5294 * Pointer to the rte_eth_dev structure.
5296 * Pointer to the flow attributes.
5298 * Pointer to the list of items.
5299 * @param[in] actions
5300 * Pointer to the list of actions.
5302 * Pointer to the error structure.
5305 * Pointer to mlx5_flow object on success,
5306 * otherwise NULL and rte_errno is set.
5308 static struct mlx5_flow *
5309 flow_dv_prepare(struct rte_eth_dev *dev,
5310 const struct rte_flow_attr *attr __rte_unused,
5311 const struct rte_flow_item items[] __rte_unused,
5312 const struct rte_flow_action actions[] __rte_unused,
5313 struct rte_flow_error *error)
5315 size_t size = sizeof(struct mlx5_flow_handle);
5316 struct mlx5_flow *dev_flow;
5317 struct mlx5_flow_handle *dev_handle;
5318 struct mlx5_priv *priv = dev->data->dev_private;
5320 /* In case of corrupting the memory. */
5321 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5322 rte_flow_error_set(error, ENOSPC,
5323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5324 "not free temporary device flow");
5327 dev_handle = rte_calloc(__func__, 1, size, 0);
5329 rte_flow_error_set(error, ENOMEM,
5330 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5331 "not enough memory to create flow handle");
5334 /* No multi-thread supporting. */
5335 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5336 dev_flow->handle = dev_handle;
5337 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5339 * The matching value needs to be cleared to 0 before using. In the
5340 * past, it will be automatically cleared when using rte_*alloc
5341 * API. The time consumption will be almost the same as before.
5343 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5344 dev_flow->ingress = attr->ingress;
5345 dev_flow->dv.transfer = attr->transfer;
5349 #ifdef RTE_LIBRTE_MLX5_DEBUG
5351 * Sanity check for match mask and value. Similar to check_valid_spec() in
5352 * kernel driver. If unmasked bit is present in value, it returns failure.
5355 * pointer to match mask buffer.
5356 * @param match_value
5357 * pointer to match value buffer.
5360 * 0 if valid, -EINVAL otherwise.
5363 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5365 uint8_t *m = match_mask;
5366 uint8_t *v = match_value;
5369 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5372 "match_value differs from match_criteria"
5373 " %p[%u] != %p[%u]",
5374 match_value, i, match_mask, i);
5383 * Add Ethernet item to matcher and to the value.
5385 * @param[in, out] matcher
5387 * @param[in, out] key
5388 * Flow matcher value.
5390 * Flow pattern to translate.
5392 * Item is inner pattern.
5395 flow_dv_translate_item_eth(void *matcher, void *key,
5396 const struct rte_flow_item *item, int inner)
5398 const struct rte_flow_item_eth *eth_m = item->mask;
5399 const struct rte_flow_item_eth *eth_v = item->spec;
5400 const struct rte_flow_item_eth nic_mask = {
5401 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5402 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5403 .type = RTE_BE16(0xffff),
5415 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5417 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5419 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5421 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5423 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5424 ð_m->dst, sizeof(eth_m->dst));
5425 /* The value must be in the range of the mask. */
5426 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5427 for (i = 0; i < sizeof(eth_m->dst); ++i)
5428 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5429 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5430 ð_m->src, sizeof(eth_m->src));
5431 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5432 /* The value must be in the range of the mask. */
5433 for (i = 0; i < sizeof(eth_m->dst); ++i)
5434 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5436 /* When ethertype is present set mask for tagged VLAN. */
5437 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5438 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5439 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5440 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5441 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5443 /* Return here to avoid setting match on ethertype. */
5448 * HW supports match on one Ethertype, the Ethertype following the last
5449 * VLAN tag of the packet (see PRM).
5450 * Set match on ethertype only if ETH header is not followed by VLAN.
5452 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5453 rte_be_to_cpu_16(eth_m->type));
5454 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5455 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5459 * Add VLAN item to matcher and to the value.
5461 * @param[in, out] dev_flow
5463 * @param[in, out] matcher
5465 * @param[in, out] key
5466 * Flow matcher value.
5468 * Flow pattern to translate.
5470 * Item is inner pattern.
5473 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5474 void *matcher, void *key,
5475 const struct rte_flow_item *item,
5478 const struct rte_flow_item_vlan *vlan_m = item->mask;
5479 const struct rte_flow_item_vlan *vlan_v = item->spec;
5488 vlan_m = &rte_flow_item_vlan_mask;
5490 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5492 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5494 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5496 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5498 * This is workaround, masks are not supported,
5499 * and pre-validated.
5501 dev_flow->handle->vf_vlan.tag =
5502 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5504 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5505 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5506 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5508 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5509 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5510 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5512 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5513 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5514 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5515 rte_be_to_cpu_16(vlan_m->inner_type));
5516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5517 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5521 * Add IPV4 item to matcher and to the value.
5523 * @param[in, out] matcher
5525 * @param[in, out] key
5526 * Flow matcher value.
5528 * Flow pattern to translate.
5529 * @param[in] item_flags
5530 * Bit-fields that holds the items detected until now.
5532 * Item is inner pattern.
5534 * The group to insert the rule.
5537 flow_dv_translate_item_ipv4(void *matcher, void *key,
5538 const struct rte_flow_item *item,
5539 const uint64_t item_flags,
5540 int inner, uint32_t group)
5542 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5543 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5544 const struct rte_flow_item_ipv4 nic_mask = {
5546 .src_addr = RTE_BE32(0xffffffff),
5547 .dst_addr = RTE_BE32(0xffffffff),
5548 .type_of_service = 0xff,
5549 .next_proto_id = 0xff,
5550 .time_to_live = 0xff,
5560 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5562 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5564 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5566 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5571 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5572 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5574 * On outer header (which must contains L2), or inner header with L2,
5575 * set cvlan_tag mask bit to mark this packet as untagged.
5576 * This should be done even if item->spec is empty.
5578 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5579 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5584 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5585 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5586 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5587 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5588 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5589 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5590 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5591 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5592 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5593 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5594 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5595 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5596 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5597 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5598 ipv4_m->hdr.type_of_service);
5599 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5600 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5601 ipv4_m->hdr.type_of_service >> 2);
5602 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5603 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5604 ipv4_m->hdr.next_proto_id);
5605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5606 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5607 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5608 ipv4_m->hdr.time_to_live);
5609 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5610 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5614 * Add IPV6 item to matcher and to the value.
5616 * @param[in, out] matcher
5618 * @param[in, out] key
5619 * Flow matcher value.
5621 * Flow pattern to translate.
5622 * @param[in] item_flags
5623 * Bit-fields that holds the items detected until now.
5625 * Item is inner pattern.
5627 * The group to insert the rule.
5630 flow_dv_translate_item_ipv6(void *matcher, void *key,
5631 const struct rte_flow_item *item,
5632 const uint64_t item_flags,
5633 int inner, uint32_t group)
5635 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5636 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5637 const struct rte_flow_item_ipv6 nic_mask = {
5640 "\xff\xff\xff\xff\xff\xff\xff\xff"
5641 "\xff\xff\xff\xff\xff\xff\xff\xff",
5643 "\xff\xff\xff\xff\xff\xff\xff\xff"
5644 "\xff\xff\xff\xff\xff\xff\xff\xff",
5645 .vtc_flow = RTE_BE32(0xffffffff),
5652 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5653 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5662 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5664 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5666 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5668 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5671 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5673 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5674 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5676 * On outer header (which must contains L2), or inner header with L2,
5677 * set cvlan_tag mask bit to mark this packet as untagged.
5678 * This should be done even if item->spec is empty.
5680 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5681 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5686 size = sizeof(ipv6_m->hdr.dst_addr);
5687 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5688 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5689 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5690 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5691 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5692 for (i = 0; i < size; ++i)
5693 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5694 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5695 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5696 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5697 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5698 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5699 for (i = 0; i < size; ++i)
5700 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5702 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5703 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5704 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5705 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5706 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5707 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5710 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5712 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5715 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5717 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5721 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5723 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5724 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5727 ipv6_m->hdr.hop_limits);
5728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5729 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5733 * Add TCP item to matcher and to the value.
5735 * @param[in, out] matcher
5737 * @param[in, out] key
5738 * Flow matcher value.
5740 * Flow pattern to translate.
5742 * Item is inner pattern.
5745 flow_dv_translate_item_tcp(void *matcher, void *key,
5746 const struct rte_flow_item *item,
5749 const struct rte_flow_item_tcp *tcp_m = item->mask;
5750 const struct rte_flow_item_tcp *tcp_v = item->spec;
5755 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5757 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5759 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5761 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5763 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5764 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5768 tcp_m = &rte_flow_item_tcp_mask;
5769 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5770 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5771 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5772 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5773 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5774 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5776 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5778 tcp_m->hdr.tcp_flags);
5779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5780 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5784 * Add UDP item to matcher and to the value.
5786 * @param[in, out] matcher
5788 * @param[in, out] key
5789 * Flow matcher value.
5791 * Flow pattern to translate.
5793 * Item is inner pattern.
5796 flow_dv_translate_item_udp(void *matcher, void *key,
5797 const struct rte_flow_item *item,
5800 const struct rte_flow_item_udp *udp_m = item->mask;
5801 const struct rte_flow_item_udp *udp_v = item->spec;
5806 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5808 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5810 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5812 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5814 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5815 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5819 udp_m = &rte_flow_item_udp_mask;
5820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5821 rte_be_to_cpu_16(udp_m->hdr.src_port));
5822 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5823 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5824 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5825 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5826 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5827 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5831 * Add GRE optional Key item to matcher and to the value.
5833 * @param[in, out] matcher
5835 * @param[in, out] key
5836 * Flow matcher value.
5838 * Flow pattern to translate.
5840 * Item is inner pattern.
5843 flow_dv_translate_item_gre_key(void *matcher, void *key,
5844 const struct rte_flow_item *item)
5846 const rte_be32_t *key_m = item->mask;
5847 const rte_be32_t *key_v = item->spec;
5848 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5849 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5850 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5852 /* GRE K bit must be on and should already be validated */
5853 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5854 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5858 key_m = &gre_key_default_mask;
5859 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5860 rte_be_to_cpu_32(*key_m) >> 8);
5861 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5862 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5863 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5864 rte_be_to_cpu_32(*key_m) & 0xFF);
5865 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5866 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5870 * Add GRE item to matcher and to the value.
5872 * @param[in, out] matcher
5874 * @param[in, out] key
5875 * Flow matcher value.
5877 * Flow pattern to translate.
5879 * Item is inner pattern.
5882 flow_dv_translate_item_gre(void *matcher, void *key,
5883 const struct rte_flow_item *item,
5886 const struct rte_flow_item_gre *gre_m = item->mask;
5887 const struct rte_flow_item_gre *gre_v = item->spec;
5890 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5891 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5898 uint16_t s_present:1;
5899 uint16_t k_present:1;
5900 uint16_t rsvd_bit1:1;
5901 uint16_t c_present:1;
5905 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5908 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5910 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5912 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5914 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5916 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5921 gre_m = &rte_flow_item_gre_mask;
5922 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5923 rte_be_to_cpu_16(gre_m->protocol));
5924 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5925 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5926 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5927 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5928 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5929 gre_crks_rsvd0_ver_m.c_present);
5930 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5931 gre_crks_rsvd0_ver_v.c_present &
5932 gre_crks_rsvd0_ver_m.c_present);
5933 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5934 gre_crks_rsvd0_ver_m.k_present);
5935 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5936 gre_crks_rsvd0_ver_v.k_present &
5937 gre_crks_rsvd0_ver_m.k_present);
5938 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5939 gre_crks_rsvd0_ver_m.s_present);
5940 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5941 gre_crks_rsvd0_ver_v.s_present &
5942 gre_crks_rsvd0_ver_m.s_present);
5946 * Add NVGRE item to matcher and to the value.
5948 * @param[in, out] matcher
5950 * @param[in, out] key
5951 * Flow matcher value.
5953 * Flow pattern to translate.
5955 * Item is inner pattern.
5958 flow_dv_translate_item_nvgre(void *matcher, void *key,
5959 const struct rte_flow_item *item,
5962 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5963 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5964 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5965 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5966 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5967 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5973 /* For NVGRE, GRE header fields must be set with defined values. */
5974 const struct rte_flow_item_gre gre_spec = {
5975 .c_rsvd0_ver = RTE_BE16(0x2000),
5976 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5978 const struct rte_flow_item_gre gre_mask = {
5979 .c_rsvd0_ver = RTE_BE16(0xB000),
5980 .protocol = RTE_BE16(UINT16_MAX),
5982 const struct rte_flow_item gre_item = {
5987 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5991 nvgre_m = &rte_flow_item_nvgre_mask;
5992 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5993 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5994 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5995 memcpy(gre_key_m, tni_flow_id_m, size);
5996 for (i = 0; i < size; ++i)
5997 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6001 * Add VXLAN item to matcher and to the value.
6003 * @param[in, out] matcher
6005 * @param[in, out] key
6006 * Flow matcher value.
6008 * Flow pattern to translate.
6010 * Item is inner pattern.
6013 flow_dv_translate_item_vxlan(void *matcher, void *key,
6014 const struct rte_flow_item *item,
6017 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6018 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6021 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6022 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6030 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6032 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6034 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6036 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6038 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6039 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6040 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6041 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6042 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6047 vxlan_m = &rte_flow_item_vxlan_mask;
6048 size = sizeof(vxlan_m->vni);
6049 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6050 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6051 memcpy(vni_m, vxlan_m->vni, size);
6052 for (i = 0; i < size; ++i)
6053 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6057 * Add VXLAN-GPE item to matcher and to the value.
6059 * @param[in, out] matcher
6061 * @param[in, out] key
6062 * Flow matcher value.
6064 * Flow pattern to translate.
6066 * Item is inner pattern.
6070 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6071 const struct rte_flow_item *item, int inner)
6073 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6074 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6078 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6080 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6086 uint8_t flags_m = 0xff;
6087 uint8_t flags_v = 0xc;
6090 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6092 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6094 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6096 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6098 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6099 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6100 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6101 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6102 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6107 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6108 size = sizeof(vxlan_m->vni);
6109 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6110 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6111 memcpy(vni_m, vxlan_m->vni, size);
6112 for (i = 0; i < size; ++i)
6113 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6114 if (vxlan_m->flags) {
6115 flags_m = vxlan_m->flags;
6116 flags_v = vxlan_v->flags;
6118 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6119 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6120 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6122 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6127 * Add Geneve item to matcher and to the value.
6129 * @param[in, out] matcher
6131 * @param[in, out] key
6132 * Flow matcher value.
6134 * Flow pattern to translate.
6136 * Item is inner pattern.
6140 flow_dv_translate_item_geneve(void *matcher, void *key,
6141 const struct rte_flow_item *item, int inner)
6143 const struct rte_flow_item_geneve *geneve_m = item->mask;
6144 const struct rte_flow_item_geneve *geneve_v = item->spec;
6147 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6148 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6157 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6159 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6161 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6163 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6165 dport = MLX5_UDP_PORT_GENEVE;
6166 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6167 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6168 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6173 geneve_m = &rte_flow_item_geneve_mask;
6174 size = sizeof(geneve_m->vni);
6175 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6176 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6177 memcpy(vni_m, geneve_m->vni, size);
6178 for (i = 0; i < size; ++i)
6179 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6180 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6181 rte_be_to_cpu_16(geneve_m->protocol));
6182 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6183 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6184 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6185 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6186 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6187 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6188 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6189 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6190 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6191 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6192 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6193 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6194 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6198 * Add MPLS item to matcher and to the value.
6200 * @param[in, out] matcher
6202 * @param[in, out] key
6203 * Flow matcher value.
6205 * Flow pattern to translate.
6206 * @param[in] prev_layer
6207 * The protocol layer indicated in previous item.
6209 * Item is inner pattern.
6212 flow_dv_translate_item_mpls(void *matcher, void *key,
6213 const struct rte_flow_item *item,
6214 uint64_t prev_layer,
6217 const uint32_t *in_mpls_m = item->mask;
6218 const uint32_t *in_mpls_v = item->spec;
6219 uint32_t *out_mpls_m = 0;
6220 uint32_t *out_mpls_v = 0;
6221 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6222 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6223 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6225 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6226 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6227 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6229 switch (prev_layer) {
6230 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6231 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6232 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6233 MLX5_UDP_PORT_MPLS);
6235 case MLX5_FLOW_LAYER_GRE:
6236 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6237 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6238 RTE_ETHER_TYPE_MPLS);
6241 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6242 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6249 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6250 switch (prev_layer) {
6251 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6253 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6254 outer_first_mpls_over_udp);
6256 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6257 outer_first_mpls_over_udp);
6259 case MLX5_FLOW_LAYER_GRE:
6261 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6262 outer_first_mpls_over_gre);
6264 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6265 outer_first_mpls_over_gre);
6268 /* Inner MPLS not over GRE is not supported. */
6271 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6275 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6281 if (out_mpls_m && out_mpls_v) {
6282 *out_mpls_m = *in_mpls_m;
6283 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6288 * Add metadata register item to matcher
6290 * @param[in, out] matcher
6292 * @param[in, out] key
6293 * Flow matcher value.
6294 * @param[in] reg_type
6295 * Type of device metadata register
6302 flow_dv_match_meta_reg(void *matcher, void *key,
6303 enum modify_reg reg_type,
6304 uint32_t data, uint32_t mask)
6307 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6309 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6315 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6316 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6319 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6320 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6324 * The metadata register C0 field might be divided into
6325 * source vport index and META item value, we should set
6326 * this field according to specified mask, not as whole one.
6328 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6330 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6331 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6334 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6337 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6338 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6341 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6342 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6345 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6346 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6349 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6350 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6353 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6354 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6357 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6358 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6361 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6362 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6371 * Add MARK item to matcher
6374 * The device to configure through.
6375 * @param[in, out] matcher
6377 * @param[in, out] key
6378 * Flow matcher value.
6380 * Flow pattern to translate.
6383 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6384 void *matcher, void *key,
6385 const struct rte_flow_item *item)
6387 struct mlx5_priv *priv = dev->data->dev_private;
6388 const struct rte_flow_item_mark *mark;
6392 mark = item->mask ? (const void *)item->mask :
6393 &rte_flow_item_mark_mask;
6394 mask = mark->id & priv->sh->dv_mark_mask;
6395 mark = (const void *)item->spec;
6397 value = mark->id & priv->sh->dv_mark_mask & mask;
6399 enum modify_reg reg;
6401 /* Get the metadata register index for the mark. */
6402 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6403 MLX5_ASSERT(reg > 0);
6404 if (reg == REG_C_0) {
6405 struct mlx5_priv *priv = dev->data->dev_private;
6406 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6407 uint32_t shl_c0 = rte_bsf32(msk_c0);
6413 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6418 * Add META item to matcher
6421 * The devich to configure through.
6422 * @param[in, out] matcher
6424 * @param[in, out] key
6425 * Flow matcher value.
6427 * Attributes of flow that includes this item.
6429 * Flow pattern to translate.
6432 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6433 void *matcher, void *key,
6434 const struct rte_flow_attr *attr,
6435 const struct rte_flow_item *item)
6437 const struct rte_flow_item_meta *meta_m;
6438 const struct rte_flow_item_meta *meta_v;
6440 meta_m = (const void *)item->mask;
6442 meta_m = &rte_flow_item_meta_mask;
6443 meta_v = (const void *)item->spec;
6446 uint32_t value = meta_v->data;
6447 uint32_t mask = meta_m->data;
6449 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6453 * In datapath code there is no endianness
6454 * coversions for perfromance reasons, all
6455 * pattern conversions are done in rte_flow.
6457 value = rte_cpu_to_be_32(value);
6458 mask = rte_cpu_to_be_32(mask);
6459 if (reg == REG_C_0) {
6460 struct mlx5_priv *priv = dev->data->dev_private;
6461 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6462 uint32_t shl_c0 = rte_bsf32(msk_c0);
6463 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6464 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6471 MLX5_ASSERT(msk_c0);
6472 MLX5_ASSERT(!(~msk_c0 & mask));
6474 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6479 * Add vport metadata Reg C0 item to matcher
6481 * @param[in, out] matcher
6483 * @param[in, out] key
6484 * Flow matcher value.
6486 * Flow pattern to translate.
6489 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6490 uint32_t value, uint32_t mask)
6492 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6496 * Add tag item to matcher
6499 * The devich to configure through.
6500 * @param[in, out] matcher
6502 * @param[in, out] key
6503 * Flow matcher value.
6505 * Flow pattern to translate.
6508 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6509 void *matcher, void *key,
6510 const struct rte_flow_item *item)
6512 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6513 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6514 uint32_t mask, value;
6517 value = tag_v->data;
6518 mask = tag_m ? tag_m->data : UINT32_MAX;
6519 if (tag_v->id == REG_C_0) {
6520 struct mlx5_priv *priv = dev->data->dev_private;
6521 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6522 uint32_t shl_c0 = rte_bsf32(msk_c0);
6528 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6532 * Add TAG item to matcher
6535 * The devich to configure through.
6536 * @param[in, out] matcher
6538 * @param[in, out] key
6539 * Flow matcher value.
6541 * Flow pattern to translate.
6544 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6545 void *matcher, void *key,
6546 const struct rte_flow_item *item)
6548 const struct rte_flow_item_tag *tag_v = item->spec;
6549 const struct rte_flow_item_tag *tag_m = item->mask;
6550 enum modify_reg reg;
6553 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6554 /* Get the metadata register index for the tag. */
6555 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6556 MLX5_ASSERT(reg > 0);
6557 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6561 * Add source vport match to the specified matcher.
6563 * @param[in, out] matcher
6565 * @param[in, out] key
6566 * Flow matcher value.
6568 * Source vport value to match
6573 flow_dv_translate_item_source_vport(void *matcher, void *key,
6574 int16_t port, uint16_t mask)
6576 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6577 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6579 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6580 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6584 * Translate port-id item to eswitch match on port-id.
6587 * The devich to configure through.
6588 * @param[in, out] matcher
6590 * @param[in, out] key
6591 * Flow matcher value.
6593 * Flow pattern to translate.
6596 * 0 on success, a negative errno value otherwise.
6599 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6600 void *key, const struct rte_flow_item *item)
6602 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6603 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6604 struct mlx5_priv *priv;
6607 mask = pid_m ? pid_m->id : 0xffff;
6608 id = pid_v ? pid_v->id : dev->data->port_id;
6609 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6612 /* Translate to vport field or to metadata, depending on mode. */
6613 if (priv->vport_meta_mask)
6614 flow_dv_translate_item_meta_vport(matcher, key,
6615 priv->vport_meta_tag,
6616 priv->vport_meta_mask);
6618 flow_dv_translate_item_source_vport(matcher, key,
6619 priv->vport_id, mask);
6624 * Add ICMP6 item to matcher and to the value.
6626 * @param[in, out] matcher
6628 * @param[in, out] key
6629 * Flow matcher value.
6631 * Flow pattern to translate.
6633 * Item is inner pattern.
6636 flow_dv_translate_item_icmp6(void *matcher, void *key,
6637 const struct rte_flow_item *item,
6640 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6641 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6644 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6646 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6648 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6650 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6652 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6654 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6657 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6661 icmp6_m = &rte_flow_item_icmp6_mask;
6663 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6664 * If only the protocol is specified, no need to match the frag.
6666 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6668 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6669 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6670 icmp6_v->type & icmp6_m->type);
6671 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6672 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6673 icmp6_v->code & icmp6_m->code);
6677 * Add ICMP item to matcher and to the value.
6679 * @param[in, out] matcher
6681 * @param[in, out] key
6682 * Flow matcher value.
6684 * Flow pattern to translate.
6686 * Item is inner pattern.
6689 flow_dv_translate_item_icmp(void *matcher, void *key,
6690 const struct rte_flow_item *item,
6693 const struct rte_flow_item_icmp *icmp_m = item->mask;
6694 const struct rte_flow_item_icmp *icmp_v = item->spec;
6697 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6699 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6701 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6703 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6705 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6707 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6709 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6710 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6714 icmp_m = &rte_flow_item_icmp_mask;
6716 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6717 * If only the protocol is specified, no need to match the frag.
6719 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6720 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6721 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6722 icmp_m->hdr.icmp_type);
6723 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6724 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6725 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6726 icmp_m->hdr.icmp_code);
6727 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6728 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6732 * Add GTP item to matcher and to the value.
6734 * @param[in, out] matcher
6736 * @param[in, out] key
6737 * Flow matcher value.
6739 * Flow pattern to translate.
6741 * Item is inner pattern.
6744 flow_dv_translate_item_gtp(void *matcher, void *key,
6745 const struct rte_flow_item *item, int inner)
6747 const struct rte_flow_item_gtp *gtp_m = item->mask;
6748 const struct rte_flow_item_gtp *gtp_v = item->spec;
6751 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6753 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6754 uint16_t dport = RTE_GTPU_UDP_PORT;
6757 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6759 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6761 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6763 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6765 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6766 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6767 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6772 gtp_m = &rte_flow_item_gtp_mask;
6773 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6774 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6775 gtp_v->msg_type & gtp_m->msg_type);
6776 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6777 rte_be_to_cpu_32(gtp_m->teid));
6778 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6779 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6782 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6784 #define HEADER_IS_ZERO(match_criteria, headers) \
6785 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6786 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6789 * Calculate flow matcher enable bitmap.
6791 * @param match_criteria
6792 * Pointer to flow matcher criteria.
6795 * Bitmap of enabled fields.
6798 flow_dv_matcher_enable(uint32_t *match_criteria)
6800 uint8_t match_criteria_enable;
6802 match_criteria_enable =
6803 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6804 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6805 match_criteria_enable |=
6806 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6807 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6808 match_criteria_enable |=
6809 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6810 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6811 match_criteria_enable |=
6812 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6813 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6814 match_criteria_enable |=
6815 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6816 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6817 return match_criteria_enable;
6824 * @param[in, out] dev
6825 * Pointer to rte_eth_dev structure.
6826 * @param[in] table_id
6829 * Direction of the table.
6830 * @param[in] transfer
6831 * E-Switch or NIC flow.
6833 * pointer to error structure.
6836 * Returns tables resource based on the index, NULL in case of failed.
6838 static struct mlx5_flow_tbl_resource *
6839 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6840 uint32_t table_id, uint8_t egress,
6842 struct rte_flow_error *error)
6844 struct mlx5_priv *priv = dev->data->dev_private;
6845 struct mlx5_ibv_shared *sh = priv->sh;
6846 struct mlx5_flow_tbl_resource *tbl;
6847 union mlx5_flow_tbl_key table_key = {
6849 .table_id = table_id,
6851 .domain = !!transfer,
6852 .direction = !!egress,
6855 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6857 struct mlx5_flow_tbl_data_entry *tbl_data;
6862 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6864 tbl = &tbl_data->tbl;
6865 rte_atomic32_inc(&tbl->refcnt);
6868 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6870 rte_flow_error_set(error, ENOMEM,
6871 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6873 "cannot allocate flow table data entry");
6876 tbl = &tbl_data->tbl;
6877 pos = &tbl_data->entry;
6879 domain = sh->fdb_domain;
6881 domain = sh->tx_domain;
6883 domain = sh->rx_domain;
6884 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6886 rte_flow_error_set(error, ENOMEM,
6887 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6888 NULL, "cannot create flow table object");
6893 * No multi-threads now, but still better to initialize the reference
6894 * count before insert it into the hash list.
6896 rte_atomic32_init(&tbl->refcnt);
6897 /* Jump action reference count is initialized here. */
6898 rte_atomic32_init(&tbl_data->jump.refcnt);
6899 pos->key = table_key.v64;
6900 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6902 rte_flow_error_set(error, -ret,
6903 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6904 "cannot insert flow table data entry");
6905 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6908 rte_atomic32_inc(&tbl->refcnt);
6913 * Release a flow table.
6916 * Pointer to rte_eth_dev structure.
6918 * Table resource to be released.
6921 * Returns 0 if table was released, else return 1;
6924 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6925 struct mlx5_flow_tbl_resource *tbl)
6927 struct mlx5_priv *priv = dev->data->dev_private;
6928 struct mlx5_ibv_shared *sh = priv->sh;
6929 struct mlx5_flow_tbl_data_entry *tbl_data =
6930 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6934 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6935 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6937 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6939 /* remove the entry from the hash list and free memory. */
6940 mlx5_hlist_remove(sh->flow_tbls, pos);
6948 * Register the flow matcher.
6950 * @param[in, out] dev
6951 * Pointer to rte_eth_dev structure.
6952 * @param[in, out] matcher
6953 * Pointer to flow matcher.
6954 * @param[in, out] key
6955 * Pointer to flow table key.
6956 * @parm[in, out] dev_flow
6957 * Pointer to the dev_flow.
6959 * pointer to error structure.
6962 * 0 on success otherwise -errno and errno is set.
6965 flow_dv_matcher_register(struct rte_eth_dev *dev,
6966 struct mlx5_flow_dv_matcher *matcher,
6967 union mlx5_flow_tbl_key *key,
6968 struct mlx5_flow *dev_flow,
6969 struct rte_flow_error *error)
6971 struct mlx5_priv *priv = dev->data->dev_private;
6972 struct mlx5_ibv_shared *sh = priv->sh;
6973 struct mlx5_flow_dv_matcher *cache_matcher;
6974 struct mlx5dv_flow_matcher_attr dv_attr = {
6975 .type = IBV_FLOW_ATTR_NORMAL,
6976 .match_mask = (void *)&matcher->mask,
6978 struct mlx5_flow_tbl_resource *tbl;
6979 struct mlx5_flow_tbl_data_entry *tbl_data;
6981 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6982 key->domain, error);
6984 return -rte_errno; /* No need to refill the error info */
6985 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6986 /* Lookup from cache. */
6987 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6988 if (matcher->crc == cache_matcher->crc &&
6989 matcher->priority == cache_matcher->priority &&
6990 !memcmp((const void *)matcher->mask.buf,
6991 (const void *)cache_matcher->mask.buf,
6992 cache_matcher->mask.size)) {
6994 "%s group %u priority %hd use %s "
6995 "matcher %p: refcnt %d++",
6996 key->domain ? "FDB" : "NIC", key->table_id,
6997 cache_matcher->priority,
6998 key->direction ? "tx" : "rx",
6999 (void *)cache_matcher,
7000 rte_atomic32_read(&cache_matcher->refcnt));
7001 rte_atomic32_inc(&cache_matcher->refcnt);
7002 dev_flow->handle->dvh.matcher = cache_matcher;
7003 /* old matcher should not make the table ref++. */
7004 flow_dv_tbl_resource_release(dev, tbl);
7008 /* Register new matcher. */
7009 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7010 if (!cache_matcher) {
7011 flow_dv_tbl_resource_release(dev, tbl);
7012 return rte_flow_error_set(error, ENOMEM,
7013 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7014 "cannot allocate matcher memory");
7016 *cache_matcher = *matcher;
7017 dv_attr.match_criteria_enable =
7018 flow_dv_matcher_enable(cache_matcher->mask.buf);
7019 dv_attr.priority = matcher->priority;
7021 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7022 cache_matcher->matcher_object =
7023 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7024 if (!cache_matcher->matcher_object) {
7025 rte_free(cache_matcher);
7026 #ifdef HAVE_MLX5DV_DR
7027 flow_dv_tbl_resource_release(dev, tbl);
7029 return rte_flow_error_set(error, ENOMEM,
7030 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7031 NULL, "cannot create matcher");
7033 /* Save the table information */
7034 cache_matcher->tbl = tbl;
7035 rte_atomic32_init(&cache_matcher->refcnt);
7036 /* only matcher ref++, table ref++ already done above in get API. */
7037 rte_atomic32_inc(&cache_matcher->refcnt);
7038 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7039 dev_flow->handle->dvh.matcher = cache_matcher;
7040 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7041 key->domain ? "FDB" : "NIC", key->table_id,
7042 cache_matcher->priority,
7043 key->direction ? "tx" : "rx", (void *)cache_matcher,
7044 rte_atomic32_read(&cache_matcher->refcnt));
7049 * Find existing tag resource or create and register a new one.
7051 * @param dev[in, out]
7052 * Pointer to rte_eth_dev structure.
7053 * @param[in, out] tag_be24
7054 * Tag value in big endian then R-shift 8.
7055 * @parm[in, out] dev_flow
7056 * Pointer to the dev_flow.
7058 * pointer to error structure.
7061 * 0 on success otherwise -errno and errno is set.
7064 flow_dv_tag_resource_register
7065 (struct rte_eth_dev *dev,
7067 struct mlx5_flow *dev_flow,
7068 struct rte_flow_error *error)
7070 struct mlx5_priv *priv = dev->data->dev_private;
7071 struct mlx5_ibv_shared *sh = priv->sh;
7072 struct mlx5_flow_dv_tag_resource *cache_resource;
7073 struct mlx5_hlist_entry *entry;
7075 /* Lookup a matching resource from cache. */
7076 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7078 cache_resource = container_of
7079 (entry, struct mlx5_flow_dv_tag_resource, entry);
7080 rte_atomic32_inc(&cache_resource->refcnt);
7081 dev_flow->handle->dvh.tag_resource = cache_resource;
7082 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7083 (void *)cache_resource,
7084 rte_atomic32_read(&cache_resource->refcnt));
7087 /* Register new resource. */
7088 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7089 if (!cache_resource)
7090 return rte_flow_error_set(error, ENOMEM,
7091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7092 "cannot allocate resource memory");
7093 cache_resource->entry.key = (uint64_t)tag_be24;
7094 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7095 if (!cache_resource->action) {
7096 rte_free(cache_resource);
7097 return rte_flow_error_set(error, ENOMEM,
7098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7099 NULL, "cannot create action");
7101 rte_atomic32_init(&cache_resource->refcnt);
7102 rte_atomic32_inc(&cache_resource->refcnt);
7103 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7104 mlx5_glue->destroy_flow_action(cache_resource->action);
7105 rte_free(cache_resource);
7106 return rte_flow_error_set(error, EEXIST,
7107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7108 NULL, "cannot insert tag");
7110 dev_flow->handle->dvh.tag_resource = cache_resource;
7111 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7112 (void *)cache_resource,
7113 rte_atomic32_read(&cache_resource->refcnt));
7121 * Pointer to Ethernet device.
7123 * Pointer to mlx5_flow.
7126 * 1 while a reference on it exists, 0 when freed.
7129 flow_dv_tag_release(struct rte_eth_dev *dev,
7130 struct mlx5_flow_dv_tag_resource *tag)
7132 struct mlx5_priv *priv = dev->data->dev_private;
7133 struct mlx5_ibv_shared *sh = priv->sh;
7136 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7137 dev->data->port_id, (void *)tag,
7138 rte_atomic32_read(&tag->refcnt));
7139 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7140 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7141 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7142 DRV_LOG(DEBUG, "port %u tag %p: removed",
7143 dev->data->port_id, (void *)tag);
7151 * Translate port ID action to vport.
7154 * Pointer to rte_eth_dev structure.
7156 * Pointer to the port ID action.
7157 * @param[out] dst_port_id
7158 * The target port ID.
7160 * Pointer to the error structure.
7163 * 0 on success, a negative errno value otherwise and rte_errno is set.
7166 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7167 const struct rte_flow_action *action,
7168 uint32_t *dst_port_id,
7169 struct rte_flow_error *error)
7172 struct mlx5_priv *priv;
7173 const struct rte_flow_action_port_id *conf =
7174 (const struct rte_flow_action_port_id *)action->conf;
7176 port = conf->original ? dev->data->port_id : conf->id;
7177 priv = mlx5_port_to_eswitch_info(port, false);
7179 return rte_flow_error_set(error, -rte_errno,
7180 RTE_FLOW_ERROR_TYPE_ACTION,
7182 "No eswitch info was found for port");
7183 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7185 * This parameter is transferred to
7186 * mlx5dv_dr_action_create_dest_ib_port().
7188 *dst_port_id = priv->ibv_port;
7191 * Legacy mode, no LAG configurations is supported.
7192 * This parameter is transferred to
7193 * mlx5dv_dr_action_create_dest_vport().
7195 *dst_port_id = priv->vport_id;
7201 * Add Tx queue matcher
7204 * Pointer to the dev struct.
7205 * @param[in, out] matcher
7207 * @param[in, out] key
7208 * Flow matcher value.
7210 * Flow pattern to translate.
7212 * Item is inner pattern.
7215 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7216 void *matcher, void *key,
7217 const struct rte_flow_item *item)
7219 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7220 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7222 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7224 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7225 struct mlx5_txq_ctrl *txq;
7229 queue_m = (const void *)item->mask;
7232 queue_v = (const void *)item->spec;
7235 txq = mlx5_txq_get(dev, queue_v->queue);
7238 queue = txq->obj->sq->id;
7239 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7240 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7241 queue & queue_m->queue);
7242 mlx5_txq_release(dev, queue_v->queue);
7246 * Set the hash fields according to the @p flow information.
7248 * @param[in] dev_flow
7249 * Pointer to the mlx5_flow.
7252 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7254 struct rte_flow *flow = dev_flow->flow;
7255 uint64_t items = dev_flow->handle->layers;
7257 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7259 dev_flow->hash_fields = 0;
7260 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7261 if (flow->rss.level >= 2) {
7262 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7266 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7267 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7268 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7269 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7270 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7271 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7272 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7274 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7276 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7277 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7278 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7279 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7280 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7281 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7282 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7284 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7287 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7288 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7289 if (rss_types & ETH_RSS_UDP) {
7290 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7291 dev_flow->hash_fields |=
7292 IBV_RX_HASH_SRC_PORT_UDP;
7293 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7294 dev_flow->hash_fields |=
7295 IBV_RX_HASH_DST_PORT_UDP;
7297 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7299 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7300 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7301 if (rss_types & ETH_RSS_TCP) {
7302 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7303 dev_flow->hash_fields |=
7304 IBV_RX_HASH_SRC_PORT_TCP;
7305 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7306 dev_flow->hash_fields |=
7307 IBV_RX_HASH_DST_PORT_TCP;
7309 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7315 * Fill the flow with DV spec, lock free
7316 * (mutex should be acquired by caller).
7319 * Pointer to rte_eth_dev structure.
7320 * @param[in, out] dev_flow
7321 * Pointer to the sub flow.
7323 * Pointer to the flow attributes.
7325 * Pointer to the list of items.
7326 * @param[in] actions
7327 * Pointer to the list of actions.
7329 * Pointer to the error structure.
7332 * 0 on success, a negative errno value otherwise and rte_errno is set.
7335 __flow_dv_translate(struct rte_eth_dev *dev,
7336 struct mlx5_flow *dev_flow,
7337 const struct rte_flow_attr *attr,
7338 const struct rte_flow_item items[],
7339 const struct rte_flow_action actions[],
7340 struct rte_flow_error *error)
7342 struct mlx5_priv *priv = dev->data->dev_private;
7343 struct mlx5_dev_config *dev_conf = &priv->config;
7344 struct rte_flow *flow = dev_flow->flow;
7345 struct mlx5_flow_handle *handle = dev_flow->handle;
7346 uint64_t item_flags = 0;
7347 uint64_t last_item = 0;
7348 uint64_t action_flags = 0;
7349 uint64_t priority = attr->priority;
7350 struct mlx5_flow_dv_matcher matcher = {
7352 .size = sizeof(matcher.mask.buf),
7356 bool actions_end = false;
7358 struct mlx5_flow_dv_modify_hdr_resource res;
7359 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7360 sizeof(struct mlx5_modification_cmd) *
7361 (MLX5_MAX_MODIFY_NUM + 1)];
7363 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7364 union flow_dv_attr flow_attr = { .attr = 0 };
7366 union mlx5_flow_tbl_key tbl_key;
7367 uint32_t modify_action_position = UINT32_MAX;
7368 void *match_mask = matcher.mask.buf;
7369 void *match_value = dev_flow->dv.value.buf;
7370 uint8_t next_protocol = 0xff;
7371 struct rte_vlan_hdr vlan = { 0 };
7375 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7376 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7377 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7378 !!priv->fdb_def_rule, &table, error);
7381 dev_flow->dv.group = table;
7383 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7384 if (priority == MLX5_FLOW_PRIO_RSVD)
7385 priority = dev_conf->flow_prio - 1;
7386 /* number of actions must be set to 0 in case of dirty stack. */
7387 mhdr_res->actions_num = 0;
7388 for (; !actions_end ; actions++) {
7389 const struct rte_flow_action_queue *queue;
7390 const struct rte_flow_action_rss *rss;
7391 const struct rte_flow_action *action = actions;
7392 const struct rte_flow_action_count *count = action->conf;
7393 const uint8_t *rss_key;
7394 const struct rte_flow_action_jump *jump_data;
7395 const struct rte_flow_action_meter *mtr;
7396 struct mlx5_flow_tbl_resource *tbl;
7397 uint32_t port_id = 0;
7398 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7399 int action_type = actions->type;
7400 const struct rte_flow_action *found_action = NULL;
7402 switch (action_type) {
7403 case RTE_FLOW_ACTION_TYPE_VOID:
7405 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7406 if (flow_dv_translate_action_port_id(dev, action,
7409 port_id_resource.port_id = port_id;
7410 if (flow_dv_port_id_action_resource_register
7411 (dev, &port_id_resource, dev_flow, error))
7413 dev_flow->dv.actions[actions_n++] =
7414 handle->dvh.port_id_action->action;
7415 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7417 case RTE_FLOW_ACTION_TYPE_FLAG:
7418 action_flags |= MLX5_FLOW_ACTION_FLAG;
7419 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7420 struct rte_flow_action_mark mark = {
7421 .id = MLX5_FLOW_MARK_DEFAULT,
7424 if (flow_dv_convert_action_mark(dev, &mark,
7428 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7431 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7433 * Only one FLAG or MARK is supported per device flow
7434 * right now. So the pointer to the tag resource must be
7435 * zero before the register process.
7437 MLX5_ASSERT(!handle->dvh.tag_resource);
7438 if (flow_dv_tag_resource_register(dev, tag_be,
7441 dev_flow->dv.actions[actions_n++] =
7442 handle->dvh.tag_resource->action;
7444 case RTE_FLOW_ACTION_TYPE_MARK:
7445 action_flags |= MLX5_FLOW_ACTION_MARK;
7446 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7447 const struct rte_flow_action_mark *mark =
7448 (const struct rte_flow_action_mark *)
7451 if (flow_dv_convert_action_mark(dev, mark,
7455 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7459 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7460 /* Legacy (non-extensive) MARK action. */
7461 tag_be = mlx5_flow_mark_set
7462 (((const struct rte_flow_action_mark *)
7463 (actions->conf))->id);
7464 MLX5_ASSERT(!handle->dvh.tag_resource);
7465 if (flow_dv_tag_resource_register(dev, tag_be,
7468 dev_flow->dv.actions[actions_n++] =
7469 handle->dvh.tag_resource->action;
7471 case RTE_FLOW_ACTION_TYPE_SET_META:
7472 if (flow_dv_convert_action_set_meta
7473 (dev, mhdr_res, attr,
7474 (const struct rte_flow_action_set_meta *)
7475 actions->conf, error))
7477 action_flags |= MLX5_FLOW_ACTION_SET_META;
7479 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7480 if (flow_dv_convert_action_set_tag
7482 (const struct rte_flow_action_set_tag *)
7483 actions->conf, error))
7485 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7487 case RTE_FLOW_ACTION_TYPE_DROP:
7488 action_flags |= MLX5_FLOW_ACTION_DROP;
7490 case RTE_FLOW_ACTION_TYPE_QUEUE:
7491 MLX5_ASSERT(flow->rss.queue);
7492 queue = actions->conf;
7493 flow->rss.queue_num = 1;
7494 (*flow->rss.queue)[0] = queue->index;
7495 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7497 case RTE_FLOW_ACTION_TYPE_RSS:
7498 MLX5_ASSERT(flow->rss.queue);
7499 rss = actions->conf;
7500 if (flow->rss.queue)
7501 memcpy((*flow->rss.queue), rss->queue,
7502 rss->queue_num * sizeof(uint16_t));
7503 flow->rss.queue_num = rss->queue_num;
7504 /* NULL RSS key indicates default RSS key. */
7505 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7506 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7508 * rss->level and rss.types should be set in advance
7509 * when expanding items for RSS.
7511 action_flags |= MLX5_FLOW_ACTION_RSS;
7513 case RTE_FLOW_ACTION_TYPE_COUNT:
7514 if (!dev_conf->devx) {
7515 rte_errno = ENOTSUP;
7518 flow->counter = flow_dv_counter_alloc(dev,
7521 dev_flow->dv.group);
7524 dev_flow->dv.actions[actions_n++] =
7525 (flow_dv_counter_get_by_idx(dev,
7526 flow->counter, NULL))->action;
7527 action_flags |= MLX5_FLOW_ACTION_COUNT;
7530 if (rte_errno == ENOTSUP)
7531 return rte_flow_error_set
7533 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7535 "count action not supported");
7537 return rte_flow_error_set
7539 RTE_FLOW_ERROR_TYPE_ACTION,
7541 "cannot create counter"
7544 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7545 dev_flow->dv.actions[actions_n++] =
7546 priv->sh->pop_vlan_action;
7547 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7549 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7550 if (!(action_flags &
7551 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7552 flow_dev_get_vlan_info_from_items(items, &vlan);
7553 vlan.eth_proto = rte_be_to_cpu_16
7554 ((((const struct rte_flow_action_of_push_vlan *)
7555 actions->conf)->ethertype));
7556 found_action = mlx5_flow_find_action
7558 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7560 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7561 found_action = mlx5_flow_find_action
7563 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7565 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7566 if (flow_dv_create_action_push_vlan
7567 (dev, attr, &vlan, dev_flow, error))
7569 dev_flow->dv.actions[actions_n++] =
7570 handle->dvh.push_vlan_res->action;
7571 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7573 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7574 /* of_vlan_push action handled this action */
7575 MLX5_ASSERT(action_flags &
7576 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7578 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7579 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7581 flow_dev_get_vlan_info_from_items(items, &vlan);
7582 mlx5_update_vlan_vid_pcp(actions, &vlan);
7583 /* If no VLAN push - this is a modify header action */
7584 if (flow_dv_convert_action_modify_vlan_vid
7585 (mhdr_res, actions, error))
7587 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7589 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7590 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7591 if (flow_dv_create_action_l2_encap(dev, actions,
7596 dev_flow->dv.actions[actions_n++] =
7597 handle->dvh.encap_decap->verbs_action;
7598 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7600 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7601 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7602 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7606 dev_flow->dv.actions[actions_n++] =
7607 handle->dvh.encap_decap->verbs_action;
7608 action_flags |= MLX5_FLOW_ACTION_DECAP;
7610 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7611 /* Handle encap with preceding decap. */
7612 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7613 if (flow_dv_create_action_raw_encap
7614 (dev, actions, dev_flow, attr, error))
7616 dev_flow->dv.actions[actions_n++] =
7617 handle->dvh.encap_decap->verbs_action;
7619 /* Handle encap without preceding decap. */
7620 if (flow_dv_create_action_l2_encap
7621 (dev, actions, dev_flow, attr->transfer,
7624 dev_flow->dv.actions[actions_n++] =
7625 handle->dvh.encap_decap->verbs_action;
7627 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7629 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7630 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7632 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7633 if (flow_dv_create_action_l2_decap
7634 (dev, dev_flow, attr->transfer, error))
7636 dev_flow->dv.actions[actions_n++] =
7637 handle->dvh.encap_decap->verbs_action;
7639 /* If decap is followed by encap, handle it at encap. */
7640 action_flags |= MLX5_FLOW_ACTION_DECAP;
7642 case RTE_FLOW_ACTION_TYPE_JUMP:
7643 jump_data = action->conf;
7644 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7646 !!priv->fdb_def_rule,
7650 tbl = flow_dv_tbl_resource_get(dev, table,
7652 attr->transfer, error);
7654 return rte_flow_error_set
7656 RTE_FLOW_ERROR_TYPE_ACTION,
7658 "cannot create jump action.");
7659 if (flow_dv_jump_tbl_resource_register
7660 (dev, tbl, dev_flow, error)) {
7661 flow_dv_tbl_resource_release(dev, tbl);
7662 return rte_flow_error_set
7664 RTE_FLOW_ERROR_TYPE_ACTION,
7666 "cannot create jump action.");
7668 dev_flow->dv.actions[actions_n++] =
7669 handle->dvh.jump->action;
7670 action_flags |= MLX5_FLOW_ACTION_JUMP;
7672 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7673 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7674 if (flow_dv_convert_action_modify_mac
7675 (mhdr_res, actions, error))
7677 action_flags |= actions->type ==
7678 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7679 MLX5_FLOW_ACTION_SET_MAC_SRC :
7680 MLX5_FLOW_ACTION_SET_MAC_DST;
7682 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7683 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7684 if (flow_dv_convert_action_modify_ipv4
7685 (mhdr_res, actions, error))
7687 action_flags |= actions->type ==
7688 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7689 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7690 MLX5_FLOW_ACTION_SET_IPV4_DST;
7692 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7693 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7694 if (flow_dv_convert_action_modify_ipv6
7695 (mhdr_res, actions, error))
7697 action_flags |= actions->type ==
7698 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7699 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7700 MLX5_FLOW_ACTION_SET_IPV6_DST;
7702 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7703 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7704 if (flow_dv_convert_action_modify_tp
7705 (mhdr_res, actions, items,
7706 &flow_attr, dev_flow, !!(action_flags &
7707 MLX5_FLOW_ACTION_DECAP), error))
7709 action_flags |= actions->type ==
7710 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7711 MLX5_FLOW_ACTION_SET_TP_SRC :
7712 MLX5_FLOW_ACTION_SET_TP_DST;
7714 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7715 if (flow_dv_convert_action_modify_dec_ttl
7716 (mhdr_res, items, &flow_attr, dev_flow,
7718 MLX5_FLOW_ACTION_DECAP), error))
7720 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7722 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7723 if (flow_dv_convert_action_modify_ttl
7724 (mhdr_res, actions, items, &flow_attr,
7725 dev_flow, !!(action_flags &
7726 MLX5_FLOW_ACTION_DECAP), error))
7728 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7730 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7731 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7732 if (flow_dv_convert_action_modify_tcp_seq
7733 (mhdr_res, actions, error))
7735 action_flags |= actions->type ==
7736 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7737 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7738 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7741 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7742 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7743 if (flow_dv_convert_action_modify_tcp_ack
7744 (mhdr_res, actions, error))
7746 action_flags |= actions->type ==
7747 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7748 MLX5_FLOW_ACTION_INC_TCP_ACK :
7749 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7751 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7752 if (flow_dv_convert_action_set_reg
7753 (mhdr_res, actions, error))
7755 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7757 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7758 if (flow_dv_convert_action_copy_mreg
7759 (dev, mhdr_res, actions, error))
7761 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7763 case RTE_FLOW_ACTION_TYPE_METER:
7764 mtr = actions->conf;
7766 flow->meter = mlx5_flow_meter_attach(priv,
7770 return rte_flow_error_set(error,
7772 RTE_FLOW_ERROR_TYPE_ACTION,
7775 "or invalid parameters");
7777 /* Set the meter action. */
7778 dev_flow->dv.actions[actions_n++] =
7779 flow->meter->mfts->meter_action;
7780 action_flags |= MLX5_FLOW_ACTION_METER;
7782 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7783 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7786 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7788 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7789 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7792 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7794 case RTE_FLOW_ACTION_TYPE_END:
7796 if (mhdr_res->actions_num) {
7797 /* create modify action if needed. */
7798 if (flow_dv_modify_hdr_resource_register
7799 (dev, mhdr_res, dev_flow, error))
7801 dev_flow->dv.actions[modify_action_position] =
7802 handle->dvh.modify_hdr->verbs_action;
7808 if (mhdr_res->actions_num &&
7809 modify_action_position == UINT32_MAX)
7810 modify_action_position = actions_n++;
7812 dev_flow->dv.actions_n = actions_n;
7813 handle->act_flags = action_flags;
7814 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7815 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7816 int item_type = items->type;
7818 switch (item_type) {
7819 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7820 flow_dv_translate_item_port_id(dev, match_mask,
7821 match_value, items);
7822 last_item = MLX5_FLOW_ITEM_PORT_ID;
7824 case RTE_FLOW_ITEM_TYPE_ETH:
7825 flow_dv_translate_item_eth(match_mask, match_value,
7827 matcher.priority = MLX5_PRIORITY_MAP_L2;
7828 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7829 MLX5_FLOW_LAYER_OUTER_L2;
7831 case RTE_FLOW_ITEM_TYPE_VLAN:
7832 flow_dv_translate_item_vlan(dev_flow,
7833 match_mask, match_value,
7835 matcher.priority = MLX5_PRIORITY_MAP_L2;
7836 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7837 MLX5_FLOW_LAYER_INNER_VLAN) :
7838 (MLX5_FLOW_LAYER_OUTER_L2 |
7839 MLX5_FLOW_LAYER_OUTER_VLAN);
7841 case RTE_FLOW_ITEM_TYPE_IPV4:
7842 mlx5_flow_tunnel_ip_check(items, next_protocol,
7843 &item_flags, &tunnel);
7844 flow_dv_translate_item_ipv4(match_mask, match_value,
7845 items, item_flags, tunnel,
7846 dev_flow->dv.group);
7847 matcher.priority = MLX5_PRIORITY_MAP_L3;
7848 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7849 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7850 if (items->mask != NULL &&
7851 ((const struct rte_flow_item_ipv4 *)
7852 items->mask)->hdr.next_proto_id) {
7854 ((const struct rte_flow_item_ipv4 *)
7855 (items->spec))->hdr.next_proto_id;
7857 ((const struct rte_flow_item_ipv4 *)
7858 (items->mask))->hdr.next_proto_id;
7860 /* Reset for inner layer. */
7861 next_protocol = 0xff;
7864 case RTE_FLOW_ITEM_TYPE_IPV6:
7865 mlx5_flow_tunnel_ip_check(items, next_protocol,
7866 &item_flags, &tunnel);
7867 flow_dv_translate_item_ipv6(match_mask, match_value,
7868 items, item_flags, tunnel,
7869 dev_flow->dv.group);
7870 matcher.priority = MLX5_PRIORITY_MAP_L3;
7871 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7872 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7873 if (items->mask != NULL &&
7874 ((const struct rte_flow_item_ipv6 *)
7875 items->mask)->hdr.proto) {
7877 ((const struct rte_flow_item_ipv6 *)
7878 items->spec)->hdr.proto;
7880 ((const struct rte_flow_item_ipv6 *)
7881 items->mask)->hdr.proto;
7883 /* Reset for inner layer. */
7884 next_protocol = 0xff;
7887 case RTE_FLOW_ITEM_TYPE_TCP:
7888 flow_dv_translate_item_tcp(match_mask, match_value,
7890 matcher.priority = MLX5_PRIORITY_MAP_L4;
7891 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7892 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7894 case RTE_FLOW_ITEM_TYPE_UDP:
7895 flow_dv_translate_item_udp(match_mask, match_value,
7897 matcher.priority = MLX5_PRIORITY_MAP_L4;
7898 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7899 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7901 case RTE_FLOW_ITEM_TYPE_GRE:
7902 flow_dv_translate_item_gre(match_mask, match_value,
7904 matcher.priority = flow->rss.level >= 2 ?
7905 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7906 last_item = MLX5_FLOW_LAYER_GRE;
7908 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7909 flow_dv_translate_item_gre_key(match_mask,
7910 match_value, items);
7911 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7913 case RTE_FLOW_ITEM_TYPE_NVGRE:
7914 flow_dv_translate_item_nvgre(match_mask, match_value,
7916 matcher.priority = flow->rss.level >= 2 ?
7917 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7918 last_item = MLX5_FLOW_LAYER_GRE;
7920 case RTE_FLOW_ITEM_TYPE_VXLAN:
7921 flow_dv_translate_item_vxlan(match_mask, match_value,
7923 matcher.priority = flow->rss.level >= 2 ?
7924 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7925 last_item = MLX5_FLOW_LAYER_VXLAN;
7927 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7928 flow_dv_translate_item_vxlan_gpe(match_mask,
7931 matcher.priority = flow->rss.level >= 2 ?
7932 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7933 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7935 case RTE_FLOW_ITEM_TYPE_GENEVE:
7936 flow_dv_translate_item_geneve(match_mask, match_value,
7938 matcher.priority = flow->rss.level >= 2 ?
7939 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7940 last_item = MLX5_FLOW_LAYER_GENEVE;
7942 case RTE_FLOW_ITEM_TYPE_MPLS:
7943 flow_dv_translate_item_mpls(match_mask, match_value,
7944 items, last_item, tunnel);
7945 matcher.priority = flow->rss.level >= 2 ?
7946 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7947 last_item = MLX5_FLOW_LAYER_MPLS;
7949 case RTE_FLOW_ITEM_TYPE_MARK:
7950 flow_dv_translate_item_mark(dev, match_mask,
7951 match_value, items);
7952 last_item = MLX5_FLOW_ITEM_MARK;
7954 case RTE_FLOW_ITEM_TYPE_META:
7955 flow_dv_translate_item_meta(dev, match_mask,
7956 match_value, attr, items);
7957 last_item = MLX5_FLOW_ITEM_METADATA;
7959 case RTE_FLOW_ITEM_TYPE_ICMP:
7960 flow_dv_translate_item_icmp(match_mask, match_value,
7962 last_item = MLX5_FLOW_LAYER_ICMP;
7964 case RTE_FLOW_ITEM_TYPE_ICMP6:
7965 flow_dv_translate_item_icmp6(match_mask, match_value,
7967 last_item = MLX5_FLOW_LAYER_ICMP6;
7969 case RTE_FLOW_ITEM_TYPE_TAG:
7970 flow_dv_translate_item_tag(dev, match_mask,
7971 match_value, items);
7972 last_item = MLX5_FLOW_ITEM_TAG;
7974 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7975 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7976 match_value, items);
7977 last_item = MLX5_FLOW_ITEM_TAG;
7979 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7980 flow_dv_translate_item_tx_queue(dev, match_mask,
7983 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7985 case RTE_FLOW_ITEM_TYPE_GTP:
7986 flow_dv_translate_item_gtp(match_mask, match_value,
7988 matcher.priority = flow->rss.level >= 2 ?
7989 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7990 last_item = MLX5_FLOW_LAYER_GTP;
7995 item_flags |= last_item;
7998 * When E-Switch mode is enabled, we have two cases where we need to
7999 * set the source port manually.
8000 * The first one, is in case of Nic steering rule, and the second is
8001 * E-Switch rule where no port_id item was found. In both cases
8002 * the source port is set according the current port in use.
8004 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8005 (priv->representor || priv->master)) {
8006 if (flow_dv_translate_item_port_id(dev, match_mask,
8010 #ifdef RTE_LIBRTE_MLX5_DEBUG
8011 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8012 dev_flow->dv.value.buf));
8015 * Layers may be already initialized from prefix flow if this dev_flow
8016 * is the suffix flow.
8018 handle->layers |= item_flags;
8019 if (action_flags & MLX5_FLOW_ACTION_RSS)
8020 flow_dv_hashfields_set(dev_flow);
8021 /* Register matcher. */
8022 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8024 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8026 /* reserved field no needs to be set to 0 here. */
8027 tbl_key.domain = attr->transfer;
8028 tbl_key.direction = attr->egress;
8029 tbl_key.table_id = dev_flow->dv.group;
8030 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8036 * Apply the flow to the NIC, lock free,
8037 * (mutex should be acquired by caller).
8040 * Pointer to the Ethernet device structure.
8041 * @param[in, out] flow
8042 * Pointer to flow structure.
8044 * Pointer to error structure.
8047 * 0 on success, a negative errno value otherwise and rte_errno is set.
8050 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8051 struct rte_flow_error *error)
8053 struct mlx5_flow_dv_workspace *dv;
8054 struct mlx5_flow_handle *dh;
8055 struct mlx5_flow_handle_dv *dv_h;
8056 struct mlx5_flow *dev_flow;
8057 struct mlx5_priv *priv = dev->data->dev_private;
8062 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8063 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8065 dh = dev_flow->handle;
8068 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8070 dv->actions[n++] = priv->sh->esw_drop_action;
8072 dh->hrxq = mlx5_hrxq_drop_new(dev);
8076 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8078 "cannot get drop hash queue");
8081 dv->actions[n++] = dh->hrxq->action;
8083 } else if (dh->act_flags &
8084 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8085 struct mlx5_hrxq *hrxq;
8087 MLX5_ASSERT(flow->rss.queue);
8088 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8089 MLX5_RSS_HASH_KEY_LEN,
8090 dev_flow->hash_fields,
8092 flow->rss.queue_num);
8094 hrxq = mlx5_hrxq_new
8095 (dev, flow->rss.key,
8096 MLX5_RSS_HASH_KEY_LEN,
8097 dev_flow->hash_fields,
8099 flow->rss.queue_num,
8101 MLX5_FLOW_LAYER_TUNNEL));
8106 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8107 "cannot get hash queue");
8111 dv->actions[n++] = dh->hrxq->action;
8114 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8115 (void *)&dv->value, n,
8118 rte_flow_error_set(error, errno,
8119 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8121 "hardware refuses to create flow");
8124 if (priv->vmwa_context &&
8125 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8127 * The rule contains the VLAN pattern.
8128 * For VF we are going to create VLAN
8129 * interface to make hypervisor set correct
8130 * e-Switch vport context.
8132 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8137 err = rte_errno; /* Save rte_errno before cleanup. */
8138 LIST_FOREACH(dh, &flow->dev_handles, next) {
8140 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8141 mlx5_hrxq_drop_release(dev);
8143 mlx5_hrxq_release(dev, dh->hrxq);
8146 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8147 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8149 rte_errno = err; /* Restore rte_errno. */
8154 * Release the flow matcher.
8157 * Pointer to Ethernet device.
8159 * Pointer to mlx5_flow_handle.
8162 * 1 while a reference on it exists, 0 when freed.
8165 flow_dv_matcher_release(struct rte_eth_dev *dev,
8166 struct mlx5_flow_handle *handle)
8168 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8170 MLX5_ASSERT(matcher->matcher_object);
8171 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8172 dev->data->port_id, (void *)matcher,
8173 rte_atomic32_read(&matcher->refcnt));
8174 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8175 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8176 (matcher->matcher_object));
8177 LIST_REMOVE(matcher, next);
8178 /* table ref-- in release interface. */
8179 flow_dv_tbl_resource_release(dev, matcher->tbl);
8181 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8182 dev->data->port_id, (void *)matcher);
8189 * Release an encap/decap resource.
8192 * Pointer to mlx5_flow_handle.
8195 * 1 while a reference on it exists, 0 when freed.
8198 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8200 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8201 handle->dvh.encap_decap;
8203 MLX5_ASSERT(cache_resource->verbs_action);
8204 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8205 (void *)cache_resource,
8206 rte_atomic32_read(&cache_resource->refcnt));
8207 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8208 claim_zero(mlx5_glue->destroy_flow_action
8209 (cache_resource->verbs_action));
8210 LIST_REMOVE(cache_resource, next);
8211 rte_free(cache_resource);
8212 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8213 (void *)cache_resource);
8220 * Release an jump to table action resource.
8223 * Pointer to Ethernet device.
8225 * Pointer to mlx5_flow_handle.
8228 * 1 while a reference on it exists, 0 when freed.
8231 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8232 struct mlx5_flow_handle *handle)
8234 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8236 struct mlx5_flow_tbl_data_entry *tbl_data =
8237 container_of(cache_resource,
8238 struct mlx5_flow_tbl_data_entry, jump);
8240 MLX5_ASSERT(cache_resource->action);
8241 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8242 (void *)cache_resource,
8243 rte_atomic32_read(&cache_resource->refcnt));
8244 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8245 claim_zero(mlx5_glue->destroy_flow_action
8246 (cache_resource->action));
8247 /* jump action memory free is inside the table release. */
8248 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8249 DRV_LOG(DEBUG, "jump table resource %p: removed",
8250 (void *)cache_resource);
8257 * Release a modify-header resource.
8260 * Pointer to mlx5_flow_handle.
8263 * 1 while a reference on it exists, 0 when freed.
8266 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8268 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8269 handle->dvh.modify_hdr;
8271 MLX5_ASSERT(cache_resource->verbs_action);
8272 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8273 (void *)cache_resource,
8274 rte_atomic32_read(&cache_resource->refcnt));
8275 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8276 claim_zero(mlx5_glue->destroy_flow_action
8277 (cache_resource->verbs_action));
8278 LIST_REMOVE(cache_resource, next);
8279 rte_free(cache_resource);
8280 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8281 (void *)cache_resource);
8288 * Release port ID action resource.
8291 * Pointer to mlx5_flow_handle.
8294 * 1 while a reference on it exists, 0 when freed.
8297 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8299 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8300 handle->dvh.port_id_action;
8302 MLX5_ASSERT(cache_resource->action);
8303 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8304 (void *)cache_resource,
8305 rte_atomic32_read(&cache_resource->refcnt));
8306 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8307 claim_zero(mlx5_glue->destroy_flow_action
8308 (cache_resource->action));
8309 LIST_REMOVE(cache_resource, next);
8310 rte_free(cache_resource);
8311 DRV_LOG(DEBUG, "port id action resource %p: removed",
8312 (void *)cache_resource);
8319 * Release push vlan action resource.
8322 * Pointer to mlx5_flow_handle.
8325 * 1 while a reference on it exists, 0 when freed.
8328 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8330 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8331 handle->dvh.push_vlan_res;
8333 MLX5_ASSERT(cache_resource->action);
8334 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8335 (void *)cache_resource,
8336 rte_atomic32_read(&cache_resource->refcnt));
8337 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8338 claim_zero(mlx5_glue->destroy_flow_action
8339 (cache_resource->action));
8340 LIST_REMOVE(cache_resource, next);
8341 rte_free(cache_resource);
8342 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8343 (void *)cache_resource);
8350 * Remove the flow from the NIC but keeps it in memory.
8351 * Lock free, (mutex should be acquired by caller).
8354 * Pointer to Ethernet device.
8355 * @param[in, out] flow
8356 * Pointer to flow structure.
8359 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8361 struct mlx5_flow_handle *dh;
8365 LIST_FOREACH(dh, &flow->dev_handles, next) {
8367 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8371 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8372 mlx5_hrxq_drop_release(dev);
8374 mlx5_hrxq_release(dev, dh->hrxq);
8377 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8378 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8383 * Remove the flow from the NIC and the memory.
8384 * Lock free, (mutex should be acquired by caller).
8387 * Pointer to the Ethernet device structure.
8388 * @param[in, out] flow
8389 * Pointer to flow structure.
8392 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8394 struct mlx5_flow_handle *dev_handle;
8398 __flow_dv_remove(dev, flow);
8399 if (flow->counter) {
8400 flow_dv_counter_release(dev, flow->counter);
8404 mlx5_flow_meter_detach(flow->meter);
8407 while (!LIST_EMPTY(&flow->dev_handles)) {
8408 dev_handle = LIST_FIRST(&flow->dev_handles);
8409 LIST_REMOVE(dev_handle, next);
8410 if (dev_handle->dvh.matcher)
8411 flow_dv_matcher_release(dev, dev_handle);
8412 if (dev_handle->dvh.encap_decap)
8413 flow_dv_encap_decap_resource_release(dev_handle);
8414 if (dev_handle->dvh.modify_hdr)
8415 flow_dv_modify_hdr_resource_release(dev_handle);
8416 if (dev_handle->dvh.jump)
8417 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8418 if (dev_handle->dvh.port_id_action)
8419 flow_dv_port_id_action_resource_release(dev_handle);
8420 if (dev_handle->dvh.push_vlan_res)
8421 flow_dv_push_vlan_action_resource_release(dev_handle);
8422 if (dev_handle->dvh.tag_resource)
8423 flow_dv_tag_release(dev,
8424 dev_handle->dvh.tag_resource);
8425 rte_free(dev_handle);
8430 * Query a dv flow rule for its statistics via devx.
8433 * Pointer to Ethernet device.
8435 * Pointer to the sub flow.
8437 * data retrieved by the query.
8439 * Perform verbose error reporting if not NULL.
8442 * 0 on success, a negative errno value otherwise and rte_errno is set.
8445 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8446 void *data, struct rte_flow_error *error)
8448 struct mlx5_priv *priv = dev->data->dev_private;
8449 struct rte_flow_query_count *qc = data;
8451 if (!priv->config.devx)
8452 return rte_flow_error_set(error, ENOTSUP,
8453 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8455 "counters are not supported");
8456 if (flow->counter) {
8457 uint64_t pkts, bytes;
8458 struct mlx5_flow_counter *cnt;
8460 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8462 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8466 return rte_flow_error_set(error, -err,
8467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8468 NULL, "cannot read counters");
8471 qc->hits = pkts - cnt->hits;
8472 qc->bytes = bytes - cnt->bytes;
8479 return rte_flow_error_set(error, EINVAL,
8480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8482 "counters are not available");
8488 * @see rte_flow_query()
8492 flow_dv_query(struct rte_eth_dev *dev,
8493 struct rte_flow *flow __rte_unused,
8494 const struct rte_flow_action *actions __rte_unused,
8495 void *data __rte_unused,
8496 struct rte_flow_error *error __rte_unused)
8500 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8501 switch (actions->type) {
8502 case RTE_FLOW_ACTION_TYPE_VOID:
8504 case RTE_FLOW_ACTION_TYPE_COUNT:
8505 ret = flow_dv_query_count(dev, flow, data, error);
8508 return rte_flow_error_set(error, ENOTSUP,
8509 RTE_FLOW_ERROR_TYPE_ACTION,
8511 "action not supported");
8518 * Destroy the meter table set.
8519 * Lock free, (mutex should be acquired by caller).
8522 * Pointer to Ethernet device.
8524 * Pointer to the meter table set.
8530 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8531 struct mlx5_meter_domains_infos *tbl)
8533 struct mlx5_priv *priv = dev->data->dev_private;
8534 struct mlx5_meter_domains_infos *mtd =
8535 (struct mlx5_meter_domains_infos *)tbl;
8537 if (!mtd || !priv->config.dv_flow_en)
8539 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8540 claim_zero(mlx5_glue->dv_destroy_flow
8541 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8542 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8543 claim_zero(mlx5_glue->dv_destroy_flow
8544 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8545 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8546 claim_zero(mlx5_glue->dv_destroy_flow
8547 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8548 if (mtd->egress.color_matcher)
8549 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8550 (mtd->egress.color_matcher));
8551 if (mtd->egress.any_matcher)
8552 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8553 (mtd->egress.any_matcher));
8554 if (mtd->egress.tbl)
8555 claim_zero(flow_dv_tbl_resource_release(dev,
8557 if (mtd->egress.sfx_tbl)
8558 claim_zero(flow_dv_tbl_resource_release(dev,
8559 mtd->egress.sfx_tbl));
8560 if (mtd->ingress.color_matcher)
8561 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8562 (mtd->ingress.color_matcher));
8563 if (mtd->ingress.any_matcher)
8564 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8565 (mtd->ingress.any_matcher));
8566 if (mtd->ingress.tbl)
8567 claim_zero(flow_dv_tbl_resource_release(dev,
8569 if (mtd->ingress.sfx_tbl)
8570 claim_zero(flow_dv_tbl_resource_release(dev,
8571 mtd->ingress.sfx_tbl));
8572 if (mtd->transfer.color_matcher)
8573 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8574 (mtd->transfer.color_matcher));
8575 if (mtd->transfer.any_matcher)
8576 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8577 (mtd->transfer.any_matcher));
8578 if (mtd->transfer.tbl)
8579 claim_zero(flow_dv_tbl_resource_release(dev,
8580 mtd->transfer.tbl));
8581 if (mtd->transfer.sfx_tbl)
8582 claim_zero(flow_dv_tbl_resource_release(dev,
8583 mtd->transfer.sfx_tbl));
8585 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8590 /* Number of meter flow actions, count and jump or count and drop. */
8591 #define METER_ACTIONS 2
8594 * Create specify domain meter table and suffix table.
8597 * Pointer to Ethernet device.
8598 * @param[in,out] mtb
8599 * Pointer to DV meter table set.
8602 * @param[in] transfer
8604 * @param[in] color_reg_c_idx
8605 * Reg C index for color match.
8608 * 0 on success, -1 otherwise and rte_errno is set.
8611 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8612 struct mlx5_meter_domains_infos *mtb,
8613 uint8_t egress, uint8_t transfer,
8614 uint32_t color_reg_c_idx)
8616 struct mlx5_priv *priv = dev->data->dev_private;
8617 struct mlx5_ibv_shared *sh = priv->sh;
8618 struct mlx5_flow_dv_match_params mask = {
8619 .size = sizeof(mask.buf),
8621 struct mlx5_flow_dv_match_params value = {
8622 .size = sizeof(value.buf),
8624 struct mlx5dv_flow_matcher_attr dv_attr = {
8625 .type = IBV_FLOW_ATTR_NORMAL,
8627 .match_criteria_enable = 0,
8628 .match_mask = (void *)&mask,
8630 void *actions[METER_ACTIONS];
8631 struct mlx5_meter_domain_info *dtb;
8632 struct rte_flow_error error;
8636 dtb = &mtb->transfer;
8640 dtb = &mtb->ingress;
8641 /* Create the meter table with METER level. */
8642 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8643 egress, transfer, &error);
8645 DRV_LOG(ERR, "Failed to create meter policer table.");
8648 /* Create the meter suffix table with SUFFIX level. */
8649 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8650 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8651 egress, transfer, &error);
8652 if (!dtb->sfx_tbl) {
8653 DRV_LOG(ERR, "Failed to create meter suffix table.");
8656 /* Create matchers, Any and Color. */
8657 dv_attr.priority = 3;
8658 dv_attr.match_criteria_enable = 0;
8659 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8662 if (!dtb->any_matcher) {
8663 DRV_LOG(ERR, "Failed to create meter"
8664 " policer default matcher.");
8667 dv_attr.priority = 0;
8668 dv_attr.match_criteria_enable =
8669 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8670 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8671 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8672 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8675 if (!dtb->color_matcher) {
8676 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8679 if (mtb->count_actns[RTE_MTR_DROPPED])
8680 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8681 actions[i++] = mtb->drop_actn;
8682 /* Default rule: lowest priority, match any, actions: drop. */
8683 dtb->policer_rules[RTE_MTR_DROPPED] =
8684 mlx5_glue->dv_create_flow(dtb->any_matcher,
8685 (void *)&value, i, actions);
8686 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8687 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8696 * Create the needed meter and suffix tables.
8697 * Lock free, (mutex should be acquired by caller).
8700 * Pointer to Ethernet device.
8702 * Pointer to the flow meter.
8705 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8707 static struct mlx5_meter_domains_infos *
8708 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8709 const struct mlx5_flow_meter *fm)
8711 struct mlx5_priv *priv = dev->data->dev_private;
8712 struct mlx5_meter_domains_infos *mtb;
8716 if (!priv->mtr_en) {
8717 rte_errno = ENOTSUP;
8720 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8722 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8725 /* Create meter count actions */
8726 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8727 struct mlx5_flow_counter *cnt;
8728 if (!fm->policer_stats.cnt[i])
8730 cnt = flow_dv_counter_get_by_idx(dev,
8731 fm->policer_stats.cnt[i], NULL);
8732 mtb->count_actns[i] = cnt->action;
8734 /* Create drop action. */
8735 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8736 if (!mtb->drop_actn) {
8737 DRV_LOG(ERR, "Failed to create drop action.");
8740 /* Egress meter table. */
8741 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8743 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8746 /* Ingress meter table. */
8747 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8749 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8752 /* FDB meter table. */
8753 if (priv->config.dv_esw_en) {
8754 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8755 priv->mtr_color_reg);
8757 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8763 flow_dv_destroy_mtr_tbl(dev, mtb);
8768 * Destroy domain policer rule.
8771 * Pointer to domain table.
8774 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8778 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8779 if (dt->policer_rules[i]) {
8780 claim_zero(mlx5_glue->dv_destroy_flow
8781 (dt->policer_rules[i]));
8782 dt->policer_rules[i] = NULL;
8785 if (dt->jump_actn) {
8786 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8787 dt->jump_actn = NULL;
8792 * Destroy policer rules.
8795 * Pointer to Ethernet device.
8797 * Pointer to flow meter structure.
8799 * Pointer to flow attributes.
8805 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8806 const struct mlx5_flow_meter *fm,
8807 const struct rte_flow_attr *attr)
8809 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8814 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8816 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8818 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8823 * Create specify domain meter policer rule.
8826 * Pointer to flow meter structure.
8828 * Pointer to DV meter table set.
8829 * @param[in] mtr_reg_c
8830 * Color match REG_C.
8833 * 0 on success, -1 otherwise.
8836 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8837 struct mlx5_meter_domain_info *dtb,
8840 struct mlx5_flow_dv_match_params matcher = {
8841 .size = sizeof(matcher.buf),
8843 struct mlx5_flow_dv_match_params value = {
8844 .size = sizeof(value.buf),
8846 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8847 void *actions[METER_ACTIONS];
8850 /* Create jump action. */
8851 if (!dtb->jump_actn)
8853 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8854 (dtb->sfx_tbl->obj);
8855 if (!dtb->jump_actn) {
8856 DRV_LOG(ERR, "Failed to create policer jump action.");
8859 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8862 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8863 rte_col_2_mlx5_col(i), UINT8_MAX);
8864 if (mtb->count_actns[i])
8865 actions[j++] = mtb->count_actns[i];
8866 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8867 actions[j++] = mtb->drop_actn;
8869 actions[j++] = dtb->jump_actn;
8870 dtb->policer_rules[i] =
8871 mlx5_glue->dv_create_flow(dtb->color_matcher,
8874 if (!dtb->policer_rules[i]) {
8875 DRV_LOG(ERR, "Failed to create policer rule.");
8886 * Create policer rules.
8889 * Pointer to Ethernet device.
8891 * Pointer to flow meter structure.
8893 * Pointer to flow attributes.
8896 * 0 on success, -1 otherwise.
8899 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8900 struct mlx5_flow_meter *fm,
8901 const struct rte_flow_attr *attr)
8903 struct mlx5_priv *priv = dev->data->dev_private;
8904 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8908 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8909 priv->mtr_color_reg);
8911 DRV_LOG(ERR, "Failed to create egress policer.");
8915 if (attr->ingress) {
8916 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8917 priv->mtr_color_reg);
8919 DRV_LOG(ERR, "Failed to create ingress policer.");
8923 if (attr->transfer) {
8924 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8925 priv->mtr_color_reg);
8927 DRV_LOG(ERR, "Failed to create transfer policer.");
8933 flow_dv_destroy_policer_rules(dev, fm, attr);
8938 * Query a devx counter.
8941 * Pointer to the Ethernet device structure.
8943 * Index to the flow counter.
8945 * Set to clear the counter statistics.
8947 * The statistics value of packets.
8949 * The statistics value of bytes.
8952 * 0 on success, otherwise return -1.
8955 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
8956 uint64_t *pkts, uint64_t *bytes)
8958 struct mlx5_priv *priv = dev->data->dev_private;
8959 struct mlx5_flow_counter *cnt;
8960 uint64_t inn_pkts, inn_bytes;
8963 if (!priv->config.devx)
8966 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
8969 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
8970 *pkts = inn_pkts - cnt->hits;
8971 *bytes = inn_bytes - cnt->bytes;
8973 cnt->hits = inn_pkts;
8974 cnt->bytes = inn_bytes;
8980 * Mutex-protected thunk to lock-free __flow_dv_translate().
8983 flow_dv_translate(struct rte_eth_dev *dev,
8984 struct mlx5_flow *dev_flow,
8985 const struct rte_flow_attr *attr,
8986 const struct rte_flow_item items[],
8987 const struct rte_flow_action actions[],
8988 struct rte_flow_error *error)
8992 flow_dv_shared_lock(dev);
8993 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8994 flow_dv_shared_unlock(dev);
8999 * Mutex-protected thunk to lock-free __flow_dv_apply().
9002 flow_dv_apply(struct rte_eth_dev *dev,
9003 struct rte_flow *flow,
9004 struct rte_flow_error *error)
9008 flow_dv_shared_lock(dev);
9009 ret = __flow_dv_apply(dev, flow, error);
9010 flow_dv_shared_unlock(dev);
9015 * Mutex-protected thunk to lock-free __flow_dv_remove().
9018 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9020 flow_dv_shared_lock(dev);
9021 __flow_dv_remove(dev, flow);
9022 flow_dv_shared_unlock(dev);
9026 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9029 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9031 flow_dv_shared_lock(dev);
9032 __flow_dv_destroy(dev, flow);
9033 flow_dv_shared_unlock(dev);
9037 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9040 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9044 flow_dv_shared_lock(dev);
9045 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9046 flow_dv_shared_unlock(dev);
9051 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9054 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9056 flow_dv_shared_lock(dev);
9057 flow_dv_counter_release(dev, cnt);
9058 flow_dv_shared_unlock(dev);
9061 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9062 .validate = flow_dv_validate,
9063 .prepare = flow_dv_prepare,
9064 .translate = flow_dv_translate,
9065 .apply = flow_dv_apply,
9066 .remove = flow_dv_remove,
9067 .destroy = flow_dv_destroy,
9068 .query = flow_dv_query,
9069 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9070 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9071 .create_policer_rules = flow_dv_create_policer_rules,
9072 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9073 .counter_alloc = flow_dv_counter_allocate,
9074 .counter_free = flow_dv_counter_free,
9075 .counter_query = flow_dv_counter_query,
9078 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */