1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
101 if (priv->pci_dev == NULL)
103 switch (priv->pci_dev->id.device_id) {
104 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
105 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
106 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
107 return (int16_t)0xfffe;
114 * Initialize flow attributes structure according to flow items' types.
116 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
117 * mode. For tunnel mode, the items to be modified are the outermost ones.
120 * Pointer to item specification.
122 * Pointer to flow attributes structure.
123 * @param[in] dev_flow
124 * Pointer to the sub flow.
125 * @param[in] tunnel_decap
126 * Whether action is after tunnel decapsulation.
129 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
130 struct mlx5_flow *dev_flow, bool tunnel_decap)
132 uint64_t layers = dev_flow->handle->layers;
135 * If layers is already initialized, it means this dev_flow is the
136 * suffix flow, the layers flags is set by the prefix flow. Need to
137 * use the layer flags from prefix flow as the suffix flow may not
138 * have the user defined items as the flow is split.
141 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
143 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
145 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
153 uint8_t next_protocol = 0xff;
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_GRE:
156 case RTE_FLOW_ITEM_TYPE_NVGRE:
157 case RTE_FLOW_ITEM_TYPE_VXLAN:
158 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
159 case RTE_FLOW_ITEM_TYPE_GENEVE:
160 case RTE_FLOW_ITEM_TYPE_MPLS:
164 case RTE_FLOW_ITEM_TYPE_IPV4:
167 if (item->mask != NULL &&
168 ((const struct rte_flow_item_ipv4 *)
169 item->mask)->hdr.next_proto_id)
171 ((const struct rte_flow_item_ipv4 *)
172 (item->spec))->hdr.next_proto_id &
173 ((const struct rte_flow_item_ipv4 *)
174 (item->mask))->hdr.next_proto_id;
175 if ((next_protocol == IPPROTO_IPIP ||
176 next_protocol == IPPROTO_IPV6) && tunnel_decap)
179 case RTE_FLOW_ITEM_TYPE_IPV6:
182 if (item->mask != NULL &&
183 ((const struct rte_flow_item_ipv6 *)
184 item->mask)->hdr.proto)
186 ((const struct rte_flow_item_ipv6 *)
187 (item->spec))->hdr.proto &
188 ((const struct rte_flow_item_ipv6 *)
189 (item->mask))->hdr.proto;
190 if ((next_protocol == IPPROTO_IPIP ||
191 next_protocol == IPPROTO_IPV6) && tunnel_decap)
194 case RTE_FLOW_ITEM_TYPE_UDP:
198 case RTE_FLOW_ITEM_TYPE_TCP:
210 * Convert rte_mtr_color to mlx5 color.
219 rte_col_2_mlx5_col(enum rte_color rcol)
222 case RTE_COLOR_GREEN:
223 return MLX5_FLOW_COLOR_GREEN;
224 case RTE_COLOR_YELLOW:
225 return MLX5_FLOW_COLOR_YELLOW;
227 return MLX5_FLOW_COLOR_RED;
231 return MLX5_FLOW_COLOR_UNDEFINED;
234 struct field_modify_info {
235 uint32_t size; /* Size of field in protocol header, in bytes. */
236 uint32_t offset; /* Offset of field in protocol header, in bytes. */
237 enum mlx5_modification_field id;
240 struct field_modify_info modify_eth[] = {
241 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
242 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
243 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
244 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
248 struct field_modify_info modify_vlan_out_first_vid[] = {
249 /* Size in bits !!! */
250 {12, 0, MLX5_MODI_OUT_FIRST_VID},
254 struct field_modify_info modify_ipv4[] = {
255 {1, 1, MLX5_MODI_OUT_IP_DSCP},
256 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
257 {4, 12, MLX5_MODI_OUT_SIPV4},
258 {4, 16, MLX5_MODI_OUT_DIPV4},
262 struct field_modify_info modify_ipv6[] = {
263 {1, 0, MLX5_MODI_OUT_IP_DSCP},
264 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
265 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
266 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
267 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
268 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
269 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
270 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
271 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
272 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
276 struct field_modify_info modify_udp[] = {
277 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
278 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
282 struct field_modify_info modify_tcp[] = {
283 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
284 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
285 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
286 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
291 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
292 uint8_t next_protocol, uint64_t *item_flags,
295 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
296 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
297 if (next_protocol == IPPROTO_IPIP) {
298 *item_flags |= MLX5_FLOW_LAYER_IPIP;
301 if (next_protocol == IPPROTO_IPV6) {
302 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
307 static inline struct mlx5_hlist *
308 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
309 const char *name, uint32_t size, bool direct_key,
310 bool lcores_share, void *ctx,
311 mlx5_list_create_cb cb_create,
312 mlx5_list_match_cb cb_match,
313 mlx5_list_remove_cb cb_remove,
314 mlx5_list_clone_cb cb_clone,
315 mlx5_list_clone_free_cb cb_clone_free)
317 struct mlx5_hlist *hl;
318 struct mlx5_hlist *expected = NULL;
319 char s[MLX5_NAME_SIZE];
321 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
324 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
325 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
326 ctx, cb_create, cb_match, cb_remove, cb_clone,
329 DRV_LOG(ERR, "%s hash creation failed", name);
333 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
336 mlx5_hlist_destroy(hl);
337 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
342 /* Update VLAN's VID/PCP based on input rte_flow_action.
345 * Pointer to struct rte_flow_action.
347 * Pointer to struct rte_vlan_hdr.
350 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
351 struct rte_vlan_hdr *vlan)
354 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
356 ((const struct rte_flow_action_of_set_vlan_pcp *)
357 action->conf)->vlan_pcp;
358 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
359 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
360 vlan->vlan_tci |= vlan_tci;
361 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
362 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
363 vlan->vlan_tci |= rte_be_to_cpu_16
364 (((const struct rte_flow_action_of_set_vlan_vid *)
365 action->conf)->vlan_vid);
370 * Fetch 1, 2, 3 or 4 byte field from the byte array
371 * and return as unsigned integer in host-endian format.
374 * Pointer to data array.
376 * Size of field to extract.
379 * converted field in host endian format.
381 static inline uint32_t
382 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
391 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
394 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
395 ret = (ret << 8) | *(data + sizeof(uint16_t));
398 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
409 * Convert modify-header action to DV specification.
411 * Data length of each action is determined by provided field description
412 * and the item mask. Data bit offset and width of each action is determined
413 * by provided item mask.
416 * Pointer to item specification.
418 * Pointer to field modification information.
419 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
420 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
421 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
423 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
424 * Negative offset value sets the same offset as source offset.
425 * size field is ignored, value is taken from source field.
426 * @param[in,out] resource
427 * Pointer to the modify-header resource.
429 * Type of modification.
431 * Pointer to the error structure.
434 * 0 on success, a negative errno value otherwise and rte_errno is set.
437 flow_dv_convert_modify_action(struct rte_flow_item *item,
438 struct field_modify_info *field,
439 struct field_modify_info *dcopy,
440 struct mlx5_flow_dv_modify_hdr_resource *resource,
441 uint32_t type, struct rte_flow_error *error)
443 uint32_t i = resource->actions_num;
444 struct mlx5_modification_cmd *actions = resource->actions;
445 uint32_t carry_b = 0;
448 * The item and mask are provided in big-endian format.
449 * The fields should be presented as in big-endian format either.
450 * Mask must be always present, it defines the actual field width.
452 MLX5_ASSERT(item->mask);
453 MLX5_ASSERT(field->size);
459 bool next_field = true;
460 bool next_dcopy = true;
462 if (i >= MLX5_MAX_MODIFY_NUM)
463 return rte_flow_error_set(error, EINVAL,
464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
465 "too many items to modify");
466 /* Fetch variable byte size mask from the array. */
467 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
468 field->offset, field->size);
473 /* Deduce actual data width in bits from mask value. */
474 off_b = rte_bsf32(mask) + carry_b;
475 size_b = sizeof(uint32_t) * CHAR_BIT -
476 off_b - __builtin_clz(mask);
478 actions[i] = (struct mlx5_modification_cmd) {
482 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
485 if (type == MLX5_MODIFICATION_TYPE_COPY) {
487 actions[i].dst_field = dcopy->id;
488 actions[i].dst_offset =
489 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
490 /* Convert entire record to big-endian format. */
491 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
493 * Destination field overflow. Copy leftovers of
494 * a source field to the next destination field.
497 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
500 dcopy->size * CHAR_BIT - dcopy->offset;
501 carry_b = actions[i].length;
505 * Not enough bits in a source filed to fill a
506 * destination field. Switch to the next source.
508 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
509 (size_b == field->size * CHAR_BIT - off_b)) {
511 field->size * CHAR_BIT - off_b;
512 dcopy->offset += actions[i].length;
518 MLX5_ASSERT(item->spec);
519 data = flow_dv_fetch_field((const uint8_t *)item->spec +
520 field->offset, field->size);
521 /* Shift out the trailing masked bits from data. */
522 data = (data & mask) >> off_b;
523 actions[i].data1 = rte_cpu_to_be_32(data);
525 /* Convert entire record to expected big-endian format. */
526 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
530 } while (field->size);
531 if (resource->actions_num == i)
532 return rte_flow_error_set(error, EINVAL,
533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
534 "invalid modification flow item");
535 resource->actions_num = i;
540 * Convert modify-header set IPv4 address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_ipv4
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_ipv4 *conf =
559 (const struct rte_flow_action_set_ipv4 *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
561 struct rte_flow_item_ipv4 ipv4;
562 struct rte_flow_item_ipv4 ipv4_mask;
564 memset(&ipv4, 0, sizeof(ipv4));
565 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
567 ipv4.hdr.src_addr = conf->ipv4_addr;
568 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
570 ipv4.hdr.dst_addr = conf->ipv4_addr;
571 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
574 item.mask = &ipv4_mask;
575 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
576 MLX5_MODIFICATION_TYPE_SET, error);
580 * Convert modify-header set IPv6 address action to DV specification.
582 * @param[in,out] resource
583 * Pointer to the modify-header resource.
585 * Pointer to action specification.
587 * Pointer to the error structure.
590 * 0 on success, a negative errno value otherwise and rte_errno is set.
593 flow_dv_convert_action_modify_ipv6
594 (struct mlx5_flow_dv_modify_hdr_resource *resource,
595 const struct rte_flow_action *action,
596 struct rte_flow_error *error)
598 const struct rte_flow_action_set_ipv6 *conf =
599 (const struct rte_flow_action_set_ipv6 *)(action->conf);
600 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
601 struct rte_flow_item_ipv6 ipv6;
602 struct rte_flow_item_ipv6 ipv6_mask;
604 memset(&ipv6, 0, sizeof(ipv6));
605 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
606 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
607 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
608 sizeof(ipv6.hdr.src_addr));
609 memcpy(&ipv6_mask.hdr.src_addr,
610 &rte_flow_item_ipv6_mask.hdr.src_addr,
611 sizeof(ipv6.hdr.src_addr));
613 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
614 sizeof(ipv6.hdr.dst_addr));
615 memcpy(&ipv6_mask.hdr.dst_addr,
616 &rte_flow_item_ipv6_mask.hdr.dst_addr,
617 sizeof(ipv6.hdr.dst_addr));
620 item.mask = &ipv6_mask;
621 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
622 MLX5_MODIFICATION_TYPE_SET, error);
626 * Convert modify-header set MAC address action to DV specification.
628 * @param[in,out] resource
629 * Pointer to the modify-header resource.
631 * Pointer to action specification.
633 * Pointer to the error structure.
636 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 flow_dv_convert_action_modify_mac
640 (struct mlx5_flow_dv_modify_hdr_resource *resource,
641 const struct rte_flow_action *action,
642 struct rte_flow_error *error)
644 const struct rte_flow_action_set_mac *conf =
645 (const struct rte_flow_action_set_mac *)(action->conf);
646 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
647 struct rte_flow_item_eth eth;
648 struct rte_flow_item_eth eth_mask;
650 memset(ð, 0, sizeof(eth));
651 memset(ð_mask, 0, sizeof(eth_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
653 memcpy(ð.src.addr_bytes, &conf->mac_addr,
654 sizeof(eth.src.addr_bytes));
655 memcpy(ð_mask.src.addr_bytes,
656 &rte_flow_item_eth_mask.src.addr_bytes,
657 sizeof(eth_mask.src.addr_bytes));
659 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
660 sizeof(eth.dst.addr_bytes));
661 memcpy(ð_mask.dst.addr_bytes,
662 &rte_flow_item_eth_mask.dst.addr_bytes,
663 sizeof(eth_mask.dst.addr_bytes));
666 item.mask = ð_mask;
667 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
668 MLX5_MODIFICATION_TYPE_SET, error);
672 * Convert modify-header set VLAN VID action to DV specification.
674 * @param[in,out] resource
675 * Pointer to the modify-header resource.
677 * Pointer to action specification.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_vlan_vid
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 struct rte_flow_error *error)
690 const struct rte_flow_action_of_set_vlan_vid *conf =
691 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
692 int i = resource->actions_num;
693 struct mlx5_modification_cmd *actions = resource->actions;
694 struct field_modify_info *field = modify_vlan_out_first_vid;
696 if (i >= MLX5_MAX_MODIFY_NUM)
697 return rte_flow_error_set(error, EINVAL,
698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
699 "too many items to modify");
700 actions[i] = (struct mlx5_modification_cmd) {
701 .action_type = MLX5_MODIFICATION_TYPE_SET,
703 .length = field->size,
704 .offset = field->offset,
706 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
707 actions[i].data1 = conf->vlan_vid;
708 actions[i].data1 = actions[i].data1 << 16;
709 resource->actions_num = ++i;
714 * Convert modify-header set TP action to DV specification.
716 * @param[in,out] resource
717 * Pointer to the modify-header resource.
719 * Pointer to action specification.
721 * Pointer to rte_flow_item objects list.
723 * Pointer to flow attributes structure.
724 * @param[in] dev_flow
725 * Pointer to the sub flow.
726 * @param[in] tunnel_decap
727 * Whether action is after tunnel decapsulation.
729 * Pointer to the error structure.
732 * 0 on success, a negative errno value otherwise and rte_errno is set.
735 flow_dv_convert_action_modify_tp
736 (struct mlx5_flow_dv_modify_hdr_resource *resource,
737 const struct rte_flow_action *action,
738 const struct rte_flow_item *items,
739 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
740 bool tunnel_decap, struct rte_flow_error *error)
742 const struct rte_flow_action_set_tp *conf =
743 (const struct rte_flow_action_set_tp *)(action->conf);
744 struct rte_flow_item item;
745 struct rte_flow_item_udp udp;
746 struct rte_flow_item_udp udp_mask;
747 struct rte_flow_item_tcp tcp;
748 struct rte_flow_item_tcp tcp_mask;
749 struct field_modify_info *field;
752 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
754 memset(&udp, 0, sizeof(udp));
755 memset(&udp_mask, 0, sizeof(udp_mask));
756 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
757 udp.hdr.src_port = conf->port;
758 udp_mask.hdr.src_port =
759 rte_flow_item_udp_mask.hdr.src_port;
761 udp.hdr.dst_port = conf->port;
762 udp_mask.hdr.dst_port =
763 rte_flow_item_udp_mask.hdr.dst_port;
765 item.type = RTE_FLOW_ITEM_TYPE_UDP;
767 item.mask = &udp_mask;
770 MLX5_ASSERT(attr->tcp);
771 memset(&tcp, 0, sizeof(tcp));
772 memset(&tcp_mask, 0, sizeof(tcp_mask));
773 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
774 tcp.hdr.src_port = conf->port;
775 tcp_mask.hdr.src_port =
776 rte_flow_item_tcp_mask.hdr.src_port;
778 tcp.hdr.dst_port = conf->port;
779 tcp_mask.hdr.dst_port =
780 rte_flow_item_tcp_mask.hdr.dst_port;
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header set TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_action *action,
816 const struct rte_flow_item *items,
817 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
818 bool tunnel_decap, struct rte_flow_error *error)
820 const struct rte_flow_action_set_ttl *conf =
821 (const struct rte_flow_action_set_ttl *)(action->conf);
822 struct rte_flow_item item;
823 struct rte_flow_item_ipv4 ipv4;
824 struct rte_flow_item_ipv4 ipv4_mask;
825 struct rte_flow_item_ipv6 ipv6;
826 struct rte_flow_item_ipv6 ipv6_mask;
827 struct field_modify_info *field;
830 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
832 memset(&ipv4, 0, sizeof(ipv4));
833 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
834 ipv4.hdr.time_to_live = conf->ttl_value;
835 ipv4_mask.hdr.time_to_live = 0xFF;
836 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
838 item.mask = &ipv4_mask;
841 MLX5_ASSERT(attr->ipv6);
842 memset(&ipv6, 0, sizeof(ipv6));
843 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
844 ipv6.hdr.hop_limits = conf->ttl_value;
845 ipv6_mask.hdr.hop_limits = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
848 item.mask = &ipv6_mask;
851 return flow_dv_convert_modify_action(&item, field, NULL, resource,
852 MLX5_MODIFICATION_TYPE_SET, error);
856 * Convert modify-header decrement TTL action to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to rte_flow_item objects list.
865 * Pointer to flow attributes structure.
866 * @param[in] dev_flow
867 * Pointer to the sub flow.
868 * @param[in] tunnel_decap
869 * Whether action is after tunnel decapsulation.
871 * Pointer to the error structure.
874 * 0 on success, a negative errno value otherwise and rte_errno is set.
877 flow_dv_convert_action_modify_dec_ttl
878 (struct mlx5_flow_dv_modify_hdr_resource *resource,
879 const struct rte_flow_item *items,
880 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
881 bool tunnel_decap, struct rte_flow_error *error)
883 struct rte_flow_item item;
884 struct rte_flow_item_ipv4 ipv4;
885 struct rte_flow_item_ipv4 ipv4_mask;
886 struct rte_flow_item_ipv6 ipv6;
887 struct rte_flow_item_ipv6 ipv6_mask;
888 struct field_modify_info *field;
891 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
893 memset(&ipv4, 0, sizeof(ipv4));
894 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
895 ipv4.hdr.time_to_live = 0xFF;
896 ipv4_mask.hdr.time_to_live = 0xFF;
897 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
899 item.mask = &ipv4_mask;
902 MLX5_ASSERT(attr->ipv6);
903 memset(&ipv6, 0, sizeof(ipv6));
904 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
905 ipv6.hdr.hop_limits = 0xFF;
906 ipv6_mask.hdr.hop_limits = 0xFF;
907 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
909 item.mask = &ipv6_mask;
912 return flow_dv_convert_modify_action(&item, field, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
917 * Convert modify-header increment/decrement TCP Sequence number
918 * to DV specification.
920 * @param[in,out] resource
921 * Pointer to the modify-header resource.
923 * Pointer to action specification.
925 * Pointer to the error structure.
928 * 0 on success, a negative errno value otherwise and rte_errno is set.
931 flow_dv_convert_action_modify_tcp_seq
932 (struct mlx5_flow_dv_modify_hdr_resource *resource,
933 const struct rte_flow_action *action,
934 struct rte_flow_error *error)
936 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
937 uint64_t value = rte_be_to_cpu_32(*conf);
938 struct rte_flow_item item;
939 struct rte_flow_item_tcp tcp;
940 struct rte_flow_item_tcp tcp_mask;
942 memset(&tcp, 0, sizeof(tcp));
943 memset(&tcp_mask, 0, sizeof(tcp_mask));
944 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
946 * The HW has no decrement operation, only increment operation.
947 * To simulate decrement X from Y using increment operation
948 * we need to add UINT32_MAX X times to Y.
949 * Each adding of UINT32_MAX decrements Y by 1.
952 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
953 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
954 item.type = RTE_FLOW_ITEM_TYPE_TCP;
956 item.mask = &tcp_mask;
957 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
958 MLX5_MODIFICATION_TYPE_ADD, error);
962 * Convert modify-header increment/decrement TCP Acknowledgment number
963 * to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_modify_tcp_ack
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
982 uint64_t value = rte_be_to_cpu_32(*conf);
983 struct rte_flow_item item;
984 struct rte_flow_item_tcp tcp;
985 struct rte_flow_item_tcp tcp_mask;
987 memset(&tcp, 0, sizeof(tcp));
988 memset(&tcp_mask, 0, sizeof(tcp_mask));
989 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
991 * The HW has no decrement operation, only increment operation.
992 * To simulate decrement X from Y using increment operation
993 * we need to add UINT32_MAX X times to Y.
994 * Each adding of UINT32_MAX decrements Y by 1.
997 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
998 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
999 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1001 item.mask = &tcp_mask;
1002 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1003 MLX5_MODIFICATION_TYPE_ADD, error);
1006 static enum mlx5_modification_field reg_to_field[] = {
1007 [REG_NON] = MLX5_MODI_OUT_NONE,
1008 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1009 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1010 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1011 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1012 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1013 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1014 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1015 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1016 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1017 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1021 * Convert register set to DV specification.
1023 * @param[in,out] resource
1024 * Pointer to the modify-header resource.
1026 * Pointer to action specification.
1028 * Pointer to the error structure.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 flow_dv_convert_action_set_reg
1035 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1036 const struct rte_flow_action *action,
1037 struct rte_flow_error *error)
1039 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1040 struct mlx5_modification_cmd *actions = resource->actions;
1041 uint32_t i = resource->actions_num;
1043 if (i >= MLX5_MAX_MODIFY_NUM)
1044 return rte_flow_error_set(error, EINVAL,
1045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1046 "too many items to modify");
1047 MLX5_ASSERT(conf->id != REG_NON);
1048 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1049 actions[i] = (struct mlx5_modification_cmd) {
1050 .action_type = MLX5_MODIFICATION_TYPE_SET,
1051 .field = reg_to_field[conf->id],
1052 .offset = conf->offset,
1053 .length = conf->length,
1055 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1056 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1058 resource->actions_num = i;
1063 * Convert SET_TAG action to DV specification.
1066 * Pointer to the rte_eth_dev structure.
1067 * @param[in,out] resource
1068 * Pointer to the modify-header resource.
1070 * Pointer to action specification.
1072 * Pointer to the error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_convert_action_set_tag
1079 (struct rte_eth_dev *dev,
1080 struct mlx5_flow_dv_modify_hdr_resource *resource,
1081 const struct rte_flow_action_set_tag *conf,
1082 struct rte_flow_error *error)
1084 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1085 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1086 struct rte_flow_item item = {
1090 struct field_modify_info reg_c_x[] = {
1093 enum mlx5_modification_field reg_type;
1096 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1099 MLX5_ASSERT(ret != REG_NON);
1100 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1101 reg_type = reg_to_field[ret];
1102 MLX5_ASSERT(reg_type > 0);
1103 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1104 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1105 MLX5_MODIFICATION_TYPE_SET, error);
1109 * Convert internal COPY_REG action to DV specification.
1112 * Pointer to the rte_eth_dev structure.
1113 * @param[in,out] res
1114 * Pointer to the modify-header resource.
1116 * Pointer to action specification.
1118 * Pointer to the error structure.
1121 * 0 on success, a negative errno value otherwise and rte_errno is set.
1124 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1125 struct mlx5_flow_dv_modify_hdr_resource *res,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error)
1129 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1130 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1131 struct rte_flow_item item = {
1135 struct field_modify_info reg_src[] = {
1136 {4, 0, reg_to_field[conf->src]},
1139 struct field_modify_info reg_dst = {
1141 .id = reg_to_field[conf->dst],
1143 /* Adjust reg_c[0] usage according to reported mask. */
1144 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1148 MLX5_ASSERT(reg_c0);
1149 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1150 if (conf->dst == REG_C_0) {
1151 /* Copy to reg_c[0], within mask only. */
1152 reg_dst.offset = rte_bsf32(reg_c0);
1153 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1156 mask = rte_cpu_to_be_32(reg_c0);
1159 return flow_dv_convert_modify_action(&item,
1160 reg_src, ®_dst, res,
1161 MLX5_MODIFICATION_TYPE_COPY,
1166 * Convert MARK action to DV specification. This routine is used
1167 * in extensive metadata only and requires metadata register to be
1168 * handled. In legacy mode hardware tag resource is engaged.
1171 * Pointer to the rte_eth_dev structure.
1173 * Pointer to MARK action specification.
1174 * @param[in,out] resource
1175 * Pointer to the modify-header resource.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1184 const struct rte_flow_action_mark *conf,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 struct rte_flow_error *error)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1190 priv->sh->dv_mark_mask);
1191 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1202 return rte_flow_error_set(error, EINVAL,
1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1204 NULL, "zero mark action mask");
1205 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1208 MLX5_ASSERT(reg > 0);
1209 if (reg == REG_C_0) {
1210 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1211 uint32_t shl_c0 = rte_bsf32(msk_c0);
1213 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1214 mask = rte_cpu_to_be_32(mask) & msk_c0;
1215 mask = rte_cpu_to_be_32(mask << shl_c0);
1217 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1218 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1219 MLX5_MODIFICATION_TYPE_SET, error);
1223 * Get metadata register index for specified steering domain.
1226 * Pointer to the rte_eth_dev structure.
1228 * Attributes of flow to determine steering domain.
1230 * Pointer to the error structure.
1233 * positive index on success, a negative errno value otherwise
1234 * and rte_errno is set.
1236 static enum modify_reg
1237 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1238 const struct rte_flow_attr *attr,
1239 struct rte_flow_error *error)
1242 mlx5_flow_get_reg_id(dev, attr->transfer ?
1246 MLX5_METADATA_RX, 0, error);
1248 return rte_flow_error_set(error,
1249 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1250 NULL, "unavailable "
1251 "metadata register");
1256 * Convert SET_META action to DV specification.
1259 * Pointer to the rte_eth_dev structure.
1260 * @param[in,out] resource
1261 * Pointer to the modify-header resource.
1263 * Attributes of flow that includes this item.
1265 * Pointer to action specification.
1267 * Pointer to the error structure.
1270 * 0 on success, a negative errno value otherwise and rte_errno is set.
1273 flow_dv_convert_action_set_meta
1274 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_dv_modify_hdr_resource *resource,
1276 const struct rte_flow_attr *attr,
1277 const struct rte_flow_action_set_meta *conf,
1278 struct rte_flow_error *error)
1280 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1281 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1282 struct rte_flow_item item = {
1286 struct field_modify_info reg_c_x[] = {
1289 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1293 MLX5_ASSERT(reg != REG_NON);
1294 if (reg == REG_C_0) {
1295 struct mlx5_priv *priv = dev->data->dev_private;
1296 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1297 uint32_t shl_c0 = rte_bsf32(msk_c0);
1299 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1300 mask = rte_cpu_to_be_32(mask) & msk_c0;
1301 mask = rte_cpu_to_be_32(mask << shl_c0);
1303 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1304 /* The routine expects parameters in memory as big-endian ones. */
1305 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1306 MLX5_MODIFICATION_TYPE_SET, error);
1310 * Convert modify-header set IPv4 DSCP action to DV specification.
1312 * @param[in,out] resource
1313 * Pointer to the modify-header resource.
1315 * Pointer to action specification.
1317 * Pointer to the error structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 flow_dv_convert_action_modify_ipv4_dscp
1324 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error)
1328 const struct rte_flow_action_set_dscp *conf =
1329 (const struct rte_flow_action_set_dscp *)(action->conf);
1330 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1331 struct rte_flow_item_ipv4 ipv4;
1332 struct rte_flow_item_ipv4 ipv4_mask;
1334 memset(&ipv4, 0, sizeof(ipv4));
1335 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1336 ipv4.hdr.type_of_service = conf->dscp;
1337 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1339 item.mask = &ipv4_mask;
1340 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1341 MLX5_MODIFICATION_TYPE_SET, error);
1345 * Convert modify-header set IPv6 DSCP action to DV specification.
1347 * @param[in,out] resource
1348 * Pointer to the modify-header resource.
1350 * Pointer to action specification.
1352 * Pointer to the error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_convert_action_modify_ipv6_dscp
1359 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1360 const struct rte_flow_action *action,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_set_dscp *conf =
1364 (const struct rte_flow_action_set_dscp *)(action->conf);
1365 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1366 struct rte_flow_item_ipv6 ipv6;
1367 struct rte_flow_item_ipv6 ipv6_mask;
1369 memset(&ipv6, 0, sizeof(ipv6));
1370 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1372 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1373 * rdma-core only accept the DSCP bits byte aligned start from
1374 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1375 * bits in IPv6 case as rdma-core requires byte aligned value.
1377 ipv6.hdr.vtc_flow = conf->dscp;
1378 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1380 item.mask = &ipv6_mask;
1381 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1382 MLX5_MODIFICATION_TYPE_SET, error);
1386 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1387 enum rte_flow_field_id field, int inherit,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1394 case RTE_FLOW_FIELD_START:
1396 case RTE_FLOW_FIELD_MAC_DST:
1397 case RTE_FLOW_FIELD_MAC_SRC:
1399 case RTE_FLOW_FIELD_VLAN_TYPE:
1401 case RTE_FLOW_FIELD_VLAN_ID:
1403 case RTE_FLOW_FIELD_MAC_TYPE:
1405 case RTE_FLOW_FIELD_IPV4_DSCP:
1407 case RTE_FLOW_FIELD_IPV4_TTL:
1409 case RTE_FLOW_FIELD_IPV4_SRC:
1410 case RTE_FLOW_FIELD_IPV4_DST:
1412 case RTE_FLOW_FIELD_IPV6_DSCP:
1414 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1416 case RTE_FLOW_FIELD_IPV6_SRC:
1417 case RTE_FLOW_FIELD_IPV6_DST:
1419 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1420 case RTE_FLOW_FIELD_TCP_PORT_DST:
1422 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1423 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1425 case RTE_FLOW_FIELD_TCP_FLAGS:
1427 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1428 case RTE_FLOW_FIELD_UDP_PORT_DST:
1430 case RTE_FLOW_FIELD_VXLAN_VNI:
1431 case RTE_FLOW_FIELD_GENEVE_VNI:
1433 case RTE_FLOW_FIELD_GTP_TEID:
1434 case RTE_FLOW_FIELD_TAG:
1436 case RTE_FLOW_FIELD_MARK:
1437 return __builtin_popcount(priv->sh->dv_mark_mask);
1438 case RTE_FLOW_FIELD_META:
1439 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1440 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1441 case RTE_FLOW_FIELD_POINTER:
1442 case RTE_FLOW_FIELD_VALUE:
1443 return inherit < 0 ? 0 : inherit;
1451 mlx5_flow_field_id_to_modify_info
1452 (const struct rte_flow_action_modify_data *data,
1453 struct field_modify_info *info, uint32_t *mask,
1454 uint32_t width, struct rte_eth_dev *dev,
1455 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1461 switch (data->field) {
1462 case RTE_FLOW_FIELD_START:
1463 /* not supported yet */
1466 case RTE_FLOW_FIELD_MAC_DST:
1467 off = data->offset > 16 ? data->offset - 16 : 0;
1469 if (data->offset < 16) {
1470 info[idx] = (struct field_modify_info){2, 4,
1471 MLX5_MODI_OUT_DMAC_15_0};
1473 mask[1] = rte_cpu_to_be_16(0xffff >>
1477 mask[1] = RTE_BE16(0xffff);
1484 info[idx] = (struct field_modify_info){4, 0,
1485 MLX5_MODI_OUT_DMAC_47_16};
1486 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1487 (32 - width)) << off);
1489 if (data->offset < 16)
1490 info[idx++] = (struct field_modify_info){2, 0,
1491 MLX5_MODI_OUT_DMAC_15_0};
1492 info[idx] = (struct field_modify_info){4, off,
1493 MLX5_MODI_OUT_DMAC_47_16};
1496 case RTE_FLOW_FIELD_MAC_SRC:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 4,
1501 MLX5_MODI_OUT_SMAC_15_0};
1503 mask[1] = rte_cpu_to_be_16(0xffff >>
1507 mask[1] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 0,
1515 MLX5_MODI_OUT_SMAC_47_16};
1516 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 0,
1521 MLX5_MODI_OUT_SMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, off,
1523 MLX5_MODI_OUT_SMAC_47_16};
1526 case RTE_FLOW_FIELD_VLAN_TYPE:
1527 /* not supported yet */
1529 case RTE_FLOW_FIELD_VLAN_ID:
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_FIRST_VID};
1533 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1535 case RTE_FLOW_FIELD_MAC_TYPE:
1536 info[idx] = (struct field_modify_info){2, 0,
1537 MLX5_MODI_OUT_ETHERTYPE};
1539 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1541 case RTE_FLOW_FIELD_IPV4_DSCP:
1542 info[idx] = (struct field_modify_info){1, 0,
1543 MLX5_MODI_OUT_IP_DSCP};
1545 mask[idx] = 0x3f >> (6 - width);
1547 case RTE_FLOW_FIELD_IPV4_TTL:
1548 info[idx] = (struct field_modify_info){1, 0,
1549 MLX5_MODI_OUT_IPV4_TTL};
1551 mask[idx] = 0xff >> (8 - width);
1553 case RTE_FLOW_FIELD_IPV4_SRC:
1554 info[idx] = (struct field_modify_info){4, 0,
1555 MLX5_MODI_OUT_SIPV4};
1557 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1560 case RTE_FLOW_FIELD_IPV4_DST:
1561 info[idx] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_DIPV4};
1564 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1567 case RTE_FLOW_FIELD_IPV6_DSCP:
1568 info[idx] = (struct field_modify_info){1, 0,
1569 MLX5_MODI_OUT_IP_DSCP};
1571 mask[idx] = 0x3f >> (6 - width);
1573 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1574 info[idx] = (struct field_modify_info){1, 0,
1575 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1577 mask[idx] = 0xff >> (8 - width);
1579 case RTE_FLOW_FIELD_IPV6_SRC:
1581 if (data->offset < 32) {
1582 info[idx] = (struct field_modify_info){4, 12,
1583 MLX5_MODI_OUT_SIPV6_31_0};
1586 rte_cpu_to_be_32(0xffffffff >>
1590 mask[3] = RTE_BE32(0xffffffff);
1597 if (data->offset < 64) {
1598 info[idx] = (struct field_modify_info){4, 8,
1599 MLX5_MODI_OUT_SIPV6_63_32};
1602 rte_cpu_to_be_32(0xffffffff >>
1606 mask[2] = RTE_BE32(0xffffffff);
1613 if (data->offset < 96) {
1614 info[idx] = (struct field_modify_info){4, 4,
1615 MLX5_MODI_OUT_SIPV6_95_64};
1618 rte_cpu_to_be_32(0xffffffff >>
1622 mask[1] = RTE_BE32(0xffffffff);
1629 info[idx] = (struct field_modify_info){4, 0,
1630 MLX5_MODI_OUT_SIPV6_127_96};
1631 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1633 if (data->offset < 32)
1634 info[idx++] = (struct field_modify_info){4, 0,
1635 MLX5_MODI_OUT_SIPV6_31_0};
1636 if (data->offset < 64)
1637 info[idx++] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_SIPV6_63_32};
1639 if (data->offset < 96)
1640 info[idx++] = (struct field_modify_info){4, 0,
1641 MLX5_MODI_OUT_SIPV6_95_64};
1642 if (data->offset < 128)
1643 info[idx++] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1647 case RTE_FLOW_FIELD_IPV6_DST:
1649 if (data->offset < 32) {
1650 info[idx] = (struct field_modify_info){4, 12,
1651 MLX5_MODI_OUT_DIPV6_31_0};
1654 rte_cpu_to_be_32(0xffffffff >>
1658 mask[3] = RTE_BE32(0xffffffff);
1665 if (data->offset < 64) {
1666 info[idx] = (struct field_modify_info){4, 8,
1667 MLX5_MODI_OUT_DIPV6_63_32};
1670 rte_cpu_to_be_32(0xffffffff >>
1674 mask[2] = RTE_BE32(0xffffffff);
1681 if (data->offset < 96) {
1682 info[idx] = (struct field_modify_info){4, 4,
1683 MLX5_MODI_OUT_DIPV6_95_64};
1686 rte_cpu_to_be_32(0xffffffff >>
1690 mask[1] = RTE_BE32(0xffffffff);
1697 info[idx] = (struct field_modify_info){4, 0,
1698 MLX5_MODI_OUT_DIPV6_127_96};
1699 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1701 if (data->offset < 32)
1702 info[idx++] = (struct field_modify_info){4, 0,
1703 MLX5_MODI_OUT_DIPV6_31_0};
1704 if (data->offset < 64)
1705 info[idx++] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_63_32};
1707 if (data->offset < 96)
1708 info[idx++] = (struct field_modify_info){4, 0,
1709 MLX5_MODI_OUT_DIPV6_95_64};
1710 if (data->offset < 128)
1711 info[idx++] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1715 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1716 info[idx] = (struct field_modify_info){2, 0,
1717 MLX5_MODI_OUT_TCP_SPORT};
1719 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1721 case RTE_FLOW_FIELD_TCP_PORT_DST:
1722 info[idx] = (struct field_modify_info){2, 0,
1723 MLX5_MODI_OUT_TCP_DPORT};
1725 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1727 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1728 info[idx] = (struct field_modify_info){4, 0,
1729 MLX5_MODI_OUT_TCP_SEQ_NUM};
1731 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1734 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1735 info[idx] = (struct field_modify_info){4, 0,
1736 MLX5_MODI_OUT_TCP_ACK_NUM};
1738 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1741 case RTE_FLOW_FIELD_TCP_FLAGS:
1742 info[idx] = (struct field_modify_info){2, 0,
1743 MLX5_MODI_OUT_TCP_FLAGS};
1745 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1747 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1748 info[idx] = (struct field_modify_info){2, 0,
1749 MLX5_MODI_OUT_UDP_SPORT};
1751 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1753 case RTE_FLOW_FIELD_UDP_PORT_DST:
1754 info[idx] = (struct field_modify_info){2, 0,
1755 MLX5_MODI_OUT_UDP_DPORT};
1757 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1759 case RTE_FLOW_FIELD_VXLAN_VNI:
1760 /* not supported yet */
1762 case RTE_FLOW_FIELD_GENEVE_VNI:
1763 /* not supported yet*/
1765 case RTE_FLOW_FIELD_GTP_TEID:
1766 info[idx] = (struct field_modify_info){4, 0,
1767 MLX5_MODI_GTP_TEID};
1769 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1772 case RTE_FLOW_FIELD_TAG:
1774 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1775 data->level, error);
1778 MLX5_ASSERT(reg != REG_NON);
1779 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1780 info[idx] = (struct field_modify_info){4, 0,
1784 rte_cpu_to_be_32(0xffffffff >>
1788 case RTE_FLOW_FIELD_MARK:
1790 uint32_t mark_mask = priv->sh->dv_mark_mask;
1791 uint32_t mark_count = __builtin_popcount(mark_mask);
1792 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1796 MLX5_ASSERT(reg != REG_NON);
1797 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1798 info[idx] = (struct field_modify_info){4, 0,
1801 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1802 (mark_count - width)) & mark_mask);
1805 case RTE_FLOW_FIELD_META:
1807 uint32_t meta_mask = priv->sh->dv_meta_mask;
1808 uint32_t meta_count = __builtin_popcount(meta_mask);
1809 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1812 MLX5_ASSERT(reg != REG_NON);
1813 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1814 info[idx] = (struct field_modify_info){4, 0,
1817 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1818 (meta_count - width)) & meta_mask);
1821 case RTE_FLOW_FIELD_POINTER:
1822 case RTE_FLOW_FIELD_VALUE:
1830 * Convert modify_field action to DV specification.
1833 * Pointer to the rte_eth_dev structure.
1834 * @param[in,out] resource
1835 * Pointer to the modify-header resource.
1837 * Pointer to action specification.
1839 * Attributes of flow that includes this item.
1841 * Pointer to the error structure.
1844 * 0 on success, a negative errno value otherwise and rte_errno is set.
1847 flow_dv_convert_action_modify_field
1848 (struct rte_eth_dev *dev,
1849 struct mlx5_flow_dv_modify_hdr_resource *resource,
1850 const struct rte_flow_action *action,
1851 const struct rte_flow_attr *attr,
1852 struct rte_flow_error *error)
1854 const struct rte_flow_action_modify_field *conf =
1855 (const struct rte_flow_action_modify_field *)(action->conf);
1856 struct rte_flow_item item = {
1860 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1862 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1864 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1865 uint32_t type, meta = 0;
1867 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1868 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1869 type = MLX5_MODIFICATION_TYPE_SET;
1870 /** For SET fill the destination field (field) first. */
1871 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1874 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1875 (void *)(uintptr_t)conf->src.pvalue :
1876 (void *)(uintptr_t)&conf->src.value;
1877 if (conf->dst.field == RTE_FLOW_FIELD_META) {
1878 meta = *(const unaligned_uint32_t *)item.spec;
1879 meta = rte_cpu_to_be_32(meta);
1883 type = MLX5_MODIFICATION_TYPE_COPY;
1884 /** For COPY fill the destination field (dcopy) without mask. */
1885 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1888 /** Then construct the source field (field) with mask. */
1889 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1894 return flow_dv_convert_modify_action(&item,
1895 field, dcopy, resource, type, error);
1899 * Validate MARK item.
1902 * Pointer to the rte_eth_dev structure.
1904 * Item specification.
1906 * Attributes of flow that includes this item.
1908 * Pointer to error structure.
1911 * 0 on success, a negative errno value otherwise and rte_errno is set.
1914 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1915 const struct rte_flow_item *item,
1916 const struct rte_flow_attr *attr __rte_unused,
1917 struct rte_flow_error *error)
1919 struct mlx5_priv *priv = dev->data->dev_private;
1920 struct mlx5_dev_config *config = &priv->config;
1921 const struct rte_flow_item_mark *spec = item->spec;
1922 const struct rte_flow_item_mark *mask = item->mask;
1923 const struct rte_flow_item_mark nic_mask = {
1924 .id = priv->sh->dv_mark_mask,
1928 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1929 return rte_flow_error_set(error, ENOTSUP,
1930 RTE_FLOW_ERROR_TYPE_ITEM, item,
1931 "extended metadata feature"
1933 if (!mlx5_flow_ext_mreg_supported(dev))
1934 return rte_flow_error_set(error, ENOTSUP,
1935 RTE_FLOW_ERROR_TYPE_ITEM, item,
1936 "extended metadata register"
1937 " isn't supported");
1939 return rte_flow_error_set(error, ENOTSUP,
1940 RTE_FLOW_ERROR_TYPE_ITEM, item,
1941 "extended metadata register"
1942 " isn't available");
1943 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1947 return rte_flow_error_set(error, EINVAL,
1948 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1950 "data cannot be empty");
1951 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1952 return rte_flow_error_set(error, EINVAL,
1953 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1955 "mark id exceeds the limit");
1959 return rte_flow_error_set(error, EINVAL,
1960 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1961 "mask cannot be zero");
1963 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1964 (const uint8_t *)&nic_mask,
1965 sizeof(struct rte_flow_item_mark),
1966 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1973 * Validate META item.
1976 * Pointer to the rte_eth_dev structure.
1978 * Item specification.
1980 * Attributes of flow that includes this item.
1982 * Pointer to error structure.
1985 * 0 on success, a negative errno value otherwise and rte_errno is set.
1988 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1989 const struct rte_flow_item *item,
1990 const struct rte_flow_attr *attr,
1991 struct rte_flow_error *error)
1993 struct mlx5_priv *priv = dev->data->dev_private;
1994 struct mlx5_dev_config *config = &priv->config;
1995 const struct rte_flow_item_meta *spec = item->spec;
1996 const struct rte_flow_item_meta *mask = item->mask;
1997 struct rte_flow_item_meta nic_mask = {
2004 return rte_flow_error_set(error, EINVAL,
2005 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2007 "data cannot be empty");
2008 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2009 if (!mlx5_flow_ext_mreg_supported(dev))
2010 return rte_flow_error_set(error, ENOTSUP,
2011 RTE_FLOW_ERROR_TYPE_ITEM, item,
2012 "extended metadata register"
2013 " isn't supported");
2014 reg = flow_dv_get_metadata_reg(dev, attr, error);
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ITEM, item,
2020 "unavailable extended metadata register");
2022 return rte_flow_error_set(error, ENOTSUP,
2023 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 nic_mask.data = priv->sh->dv_meta_mask;
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_ITEM, item,
2032 "extended metadata feature "
2033 "should be enabled when "
2034 "meta item is requested "
2035 "with e-switch mode ");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2039 "match on metadata for ingress "
2040 "is not supported in legacy "
2044 mask = &rte_flow_item_meta_mask;
2046 return rte_flow_error_set(error, EINVAL,
2047 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2048 "mask cannot be zero");
2050 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2051 (const uint8_t *)&nic_mask,
2052 sizeof(struct rte_flow_item_meta),
2053 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2058 * Validate TAG item.
2061 * Pointer to the rte_eth_dev structure.
2063 * Item specification.
2065 * Attributes of flow that includes this item.
2067 * Pointer to error structure.
2070 * 0 on success, a negative errno value otherwise and rte_errno is set.
2073 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2074 const struct rte_flow_item *item,
2075 const struct rte_flow_attr *attr __rte_unused,
2076 struct rte_flow_error *error)
2078 const struct rte_flow_item_tag *spec = item->spec;
2079 const struct rte_flow_item_tag *mask = item->mask;
2080 const struct rte_flow_item_tag nic_mask = {
2081 .data = RTE_BE32(UINT32_MAX),
2086 if (!mlx5_flow_ext_mreg_supported(dev))
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ITEM, item,
2089 "extensive metadata register"
2090 " isn't supported");
2092 return rte_flow_error_set(error, EINVAL,
2093 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2095 "data cannot be empty");
2097 mask = &rte_flow_item_tag_mask;
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2101 "mask cannot be zero");
2103 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2104 (const uint8_t *)&nic_mask,
2105 sizeof(struct rte_flow_item_tag),
2106 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2109 if (mask->index != 0xff)
2110 return rte_flow_error_set(error, EINVAL,
2111 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2112 "partial mask for tag index"
2113 " is not supported");
2114 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2117 MLX5_ASSERT(ret != REG_NON);
2122 * Validate vport item.
2125 * Pointer to the rte_eth_dev structure.
2127 * Item specification.
2129 * Attributes of flow that includes this item.
2130 * @param[in] item_flags
2131 * Bit-fields that holds the items detected until now.
2133 * Pointer to error structure.
2136 * 0 on success, a negative errno value otherwise and rte_errno is set.
2139 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2140 const struct rte_flow_item *item,
2141 const struct rte_flow_attr *attr,
2142 uint64_t item_flags,
2143 struct rte_flow_error *error)
2145 const struct rte_flow_item_port_id *spec = item->spec;
2146 const struct rte_flow_item_port_id *mask = item->mask;
2147 const struct rte_flow_item_port_id switch_mask = {
2150 struct mlx5_priv *esw_priv;
2151 struct mlx5_priv *dev_priv;
2154 if (!attr->transfer)
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ITEM,
2158 "match on port id is valid only"
2159 " when transfer flag is enabled");
2160 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2161 return rte_flow_error_set(error, ENOTSUP,
2162 RTE_FLOW_ERROR_TYPE_ITEM, item,
2163 "multiple source ports are not"
2166 mask = &switch_mask;
2167 if (mask->id != 0xffffffff)
2168 return rte_flow_error_set(error, ENOTSUP,
2169 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2171 "no support for partial mask on"
2173 ret = mlx5_flow_item_acceptable
2174 (item, (const uint8_t *)mask,
2175 (const uint8_t *)&rte_flow_item_port_id_mask,
2176 sizeof(struct rte_flow_item_port_id),
2177 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2182 if (spec->id == MLX5_PORT_ESW_MGR)
2184 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2186 return rte_flow_error_set(error, rte_errno,
2187 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2188 "failed to obtain E-Switch info for"
2190 dev_priv = mlx5_dev_to_eswitch_info(dev);
2192 return rte_flow_error_set(error, rte_errno,
2193 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2195 "failed to obtain E-Switch info");
2196 if (esw_priv->domain_id != dev_priv->domain_id)
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2199 "cannot match on a port from a"
2200 " different E-Switch");
2205 * Validate VLAN item.
2208 * Item specification.
2209 * @param[in] item_flags
2210 * Bit-fields that holds the items detected until now.
2212 * Ethernet device flow is being created on.
2214 * Pointer to error structure.
2217 * 0 on success, a negative errno value otherwise and rte_errno is set.
2220 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2221 uint64_t item_flags,
2222 struct rte_eth_dev *dev,
2223 struct rte_flow_error *error)
2225 const struct rte_flow_item_vlan *mask = item->mask;
2226 const struct rte_flow_item_vlan nic_mask = {
2227 .tci = RTE_BE16(UINT16_MAX),
2228 .inner_type = RTE_BE16(UINT16_MAX),
2231 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2233 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2234 MLX5_FLOW_LAYER_INNER_L4) :
2235 (MLX5_FLOW_LAYER_OUTER_L3 |
2236 MLX5_FLOW_LAYER_OUTER_L4);
2237 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2238 MLX5_FLOW_LAYER_OUTER_VLAN;
2240 if (item_flags & vlanm)
2241 return rte_flow_error_set(error, EINVAL,
2242 RTE_FLOW_ERROR_TYPE_ITEM, item,
2243 "multiple VLAN layers not supported");
2244 else if ((item_flags & l34m) != 0)
2245 return rte_flow_error_set(error, EINVAL,
2246 RTE_FLOW_ERROR_TYPE_ITEM, item,
2247 "VLAN cannot follow L3/L4 layer");
2249 mask = &rte_flow_item_vlan_mask;
2250 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2251 (const uint8_t *)&nic_mask,
2252 sizeof(struct rte_flow_item_vlan),
2253 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2256 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2257 struct mlx5_priv *priv = dev->data->dev_private;
2259 if (priv->vmwa_context) {
2261 * Non-NULL context means we have a virtual machine
2262 * and SR-IOV enabled, we have to create VLAN interface
2263 * to make hypervisor to setup E-Switch vport
2264 * context correctly. We avoid creating the multiple
2265 * VLAN interfaces, so we cannot support VLAN tag mask.
2267 return rte_flow_error_set(error, EINVAL,
2268 RTE_FLOW_ERROR_TYPE_ITEM,
2270 "VLAN tag mask is not"
2271 " supported in virtual"
2279 * GTP flags are contained in 1 byte of the format:
2280 * -------------------------------------------
2281 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2282 * |-----------------------------------------|
2283 * | value | Version | PT | Res | E | S | PN |
2284 * -------------------------------------------
2286 * Matching is supported only for GTP flags E, S, PN.
2288 #define MLX5_GTP_FLAGS_MASK 0x07
2291 * Validate GTP item.
2294 * Pointer to the rte_eth_dev structure.
2296 * Item specification.
2297 * @param[in] item_flags
2298 * Bit-fields that holds the items detected until now.
2300 * Pointer to error structure.
2303 * 0 on success, a negative errno value otherwise and rte_errno is set.
2306 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2307 const struct rte_flow_item *item,
2308 uint64_t item_flags,
2309 struct rte_flow_error *error)
2311 struct mlx5_priv *priv = dev->data->dev_private;
2312 const struct rte_flow_item_gtp *spec = item->spec;
2313 const struct rte_flow_item_gtp *mask = item->mask;
2314 const struct rte_flow_item_gtp nic_mask = {
2315 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2317 .teid = RTE_BE32(0xffffffff),
2320 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_gtp)
2321 return rte_flow_error_set(error, ENOTSUP,
2322 RTE_FLOW_ERROR_TYPE_ITEM, item,
2323 "GTP support is not enabled");
2324 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2325 return rte_flow_error_set(error, ENOTSUP,
2326 RTE_FLOW_ERROR_TYPE_ITEM, item,
2327 "multiple tunnel layers not"
2329 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2330 return rte_flow_error_set(error, EINVAL,
2331 RTE_FLOW_ERROR_TYPE_ITEM, item,
2332 "no outer UDP layer found");
2334 mask = &rte_flow_item_gtp_mask;
2335 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "Match is supported for GTP"
2340 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2341 (const uint8_t *)&nic_mask,
2342 sizeof(struct rte_flow_item_gtp),
2343 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2347 * Validate GTP PSC item.
2350 * Item specification.
2351 * @param[in] last_item
2352 * Previous validated item in the pattern items.
2353 * @param[in] gtp_item
2354 * Previous GTP item specification.
2356 * Pointer to flow attributes.
2358 * Pointer to error structure.
2361 * 0 on success, a negative errno value otherwise and rte_errno is set.
2364 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2366 const struct rte_flow_item *gtp_item,
2367 const struct rte_flow_attr *attr,
2368 struct rte_flow_error *error)
2370 const struct rte_flow_item_gtp *gtp_spec;
2371 const struct rte_flow_item_gtp *gtp_mask;
2372 const struct rte_flow_item_gtp_psc *mask;
2373 const struct rte_flow_item_gtp_psc nic_mask = {
2378 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2379 return rte_flow_error_set
2380 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2381 "GTP PSC item must be preceded with GTP item");
2382 gtp_spec = gtp_item->spec;
2383 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2384 /* GTP spec and E flag is requested to match zero. */
2386 (gtp_mask->v_pt_rsv_flags &
2387 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2388 return rte_flow_error_set
2389 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2390 "GTP E flag must be 1 to match GTP PSC");
2391 /* Check the flow is not created in group zero. */
2392 if (!attr->transfer && !attr->group)
2393 return rte_flow_error_set
2394 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2395 "GTP PSC is not supported for group 0");
2396 /* GTP spec is here and E flag is requested to match zero. */
2399 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2400 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2401 (const uint8_t *)&nic_mask,
2402 sizeof(struct rte_flow_item_gtp_psc),
2403 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2407 * Validate IPV4 item.
2408 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2409 * add specific validation of fragment_offset field,
2412 * Item specification.
2413 * @param[in] item_flags
2414 * Bit-fields that holds the items detected until now.
2416 * Pointer to error structure.
2419 * 0 on success, a negative errno value otherwise and rte_errno is set.
2422 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2423 const struct rte_flow_item *item,
2424 uint64_t item_flags, uint64_t last_item,
2425 uint16_t ether_type, struct rte_flow_error *error)
2428 struct mlx5_priv *priv = dev->data->dev_private;
2429 struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
2430 const struct rte_flow_item_ipv4 *spec = item->spec;
2431 const struct rte_flow_item_ipv4 *last = item->last;
2432 const struct rte_flow_item_ipv4 *mask = item->mask;
2433 rte_be16_t fragment_offset_spec = 0;
2434 rte_be16_t fragment_offset_last = 0;
2435 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2437 .src_addr = RTE_BE32(0xffffffff),
2438 .dst_addr = RTE_BE32(0xffffffff),
2439 .type_of_service = 0xff,
2440 .fragment_offset = RTE_BE16(0xffff),
2441 .next_proto_id = 0xff,
2442 .time_to_live = 0xff,
2446 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2447 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2448 bool ihl_cap = !tunnel ?
2449 attr->outer_ipv4_ihl : attr->inner_ipv4_ihl;
2451 return rte_flow_error_set(error, ENOTSUP,
2452 RTE_FLOW_ERROR_TYPE_ITEM,
2454 "IPV4 ihl offload not supported");
2455 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2457 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2458 ether_type, &nic_ipv4_mask,
2459 MLX5_ITEM_RANGE_ACCEPTED, error);
2463 fragment_offset_spec = spec->hdr.fragment_offset &
2464 mask->hdr.fragment_offset;
2465 if (!fragment_offset_spec)
2468 * spec and mask are valid, enforce using full mask to make sure the
2469 * complete value is used correctly.
2471 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2472 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2473 return rte_flow_error_set(error, EINVAL,
2474 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2475 item, "must use full mask for"
2476 " fragment_offset");
2478 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2479 * indicating this is 1st fragment of fragmented packet.
2480 * This is not yet supported in MLX5, return appropriate error message.
2482 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2483 return rte_flow_error_set(error, ENOTSUP,
2484 RTE_FLOW_ERROR_TYPE_ITEM, item,
2485 "match on first fragment not "
2487 if (fragment_offset_spec && !last)
2488 return rte_flow_error_set(error, ENOTSUP,
2489 RTE_FLOW_ERROR_TYPE_ITEM, item,
2490 "specified value not supported");
2491 /* spec and last are valid, validate the specified range. */
2492 fragment_offset_last = last->hdr.fragment_offset &
2493 mask->hdr.fragment_offset;
2495 * Match on fragment_offset spec 0x2001 and last 0x3fff
2496 * means MF is 1 and frag-offset is > 0.
2497 * This packet is fragment 2nd and onward, excluding last.
2498 * This is not yet supported in MLX5, return appropriate
2501 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2502 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2503 return rte_flow_error_set(error, ENOTSUP,
2504 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2505 last, "match on following "
2506 "fragments not supported");
2508 * Match on fragment_offset spec 0x0001 and last 0x1fff
2509 * means MF is 0 and frag-offset is > 0.
2510 * This packet is last fragment of fragmented packet.
2511 * This is not yet supported in MLX5, return appropriate
2514 if (fragment_offset_spec == RTE_BE16(1) &&
2515 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2516 return rte_flow_error_set(error, ENOTSUP,
2517 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2518 last, "match on last "
2519 "fragment not supported");
2521 * Match on fragment_offset spec 0x0001 and last 0x3fff
2522 * means MF and/or frag-offset is not 0.
2523 * This is a fragmented packet.
2524 * Other range values are invalid and rejected.
2526 if (!(fragment_offset_spec == RTE_BE16(1) &&
2527 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2530 "specified range not supported");
2535 * Validate IPV6 fragment extension item.
2538 * Item specification.
2539 * @param[in] item_flags
2540 * Bit-fields that holds the items detected until now.
2542 * Pointer to error structure.
2545 * 0 on success, a negative errno value otherwise and rte_errno is set.
2548 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2549 uint64_t item_flags,
2550 struct rte_flow_error *error)
2552 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2553 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2554 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2555 rte_be16_t frag_data_spec = 0;
2556 rte_be16_t frag_data_last = 0;
2557 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2558 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2559 MLX5_FLOW_LAYER_OUTER_L4;
2561 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2563 .next_header = 0xff,
2564 .frag_data = RTE_BE16(0xffff),
2568 if (item_flags & l4m)
2569 return rte_flow_error_set(error, EINVAL,
2570 RTE_FLOW_ERROR_TYPE_ITEM, item,
2571 "ipv6 fragment extension item cannot "
2573 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2574 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2575 return rte_flow_error_set(error, EINVAL,
2576 RTE_FLOW_ERROR_TYPE_ITEM, item,
2577 "ipv6 fragment extension item must "
2578 "follow ipv6 item");
2580 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2581 if (!frag_data_spec)
2584 * spec and mask are valid, enforce using full mask to make sure the
2585 * complete value is used correctly.
2587 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2588 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2591 item, "must use full mask for"
2594 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2595 * This is 1st fragment of fragmented packet.
2597 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2598 return rte_flow_error_set(error, ENOTSUP,
2599 RTE_FLOW_ERROR_TYPE_ITEM, item,
2600 "match on first fragment not "
2602 if (frag_data_spec && !last)
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM, item,
2605 "specified value not supported");
2606 ret = mlx5_flow_item_acceptable
2607 (item, (const uint8_t *)mask,
2608 (const uint8_t *)&nic_mask,
2609 sizeof(struct rte_flow_item_ipv6_frag_ext),
2610 MLX5_ITEM_RANGE_ACCEPTED, error);
2613 /* spec and last are valid, validate the specified range. */
2614 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2616 * Match on frag_data spec 0x0009 and last 0xfff9
2617 * means M is 1 and frag-offset is > 0.
2618 * This packet is fragment 2nd and onward, excluding last.
2619 * This is not yet supported in MLX5, return appropriate
2622 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2623 RTE_IPV6_EHDR_MF_MASK) &&
2624 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2625 return rte_flow_error_set(error, ENOTSUP,
2626 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2627 last, "match on following "
2628 "fragments not supported");
2630 * Match on frag_data spec 0x0008 and last 0xfff8
2631 * means M is 0 and frag-offset is > 0.
2632 * This packet is last fragment of fragmented packet.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2637 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2638 return rte_flow_error_set(error, ENOTSUP,
2639 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2640 last, "match on last "
2641 "fragment not supported");
2642 /* Other range values are invalid and rejected. */
2643 return rte_flow_error_set(error, EINVAL,
2644 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2645 "specified range not supported");
2649 * Validate ASO CT item.
2652 * Pointer to the rte_eth_dev structure.
2654 * Item specification.
2655 * @param[in] item_flags
2656 * Pointer to bit-fields that holds the items detected until now.
2658 * Pointer to error structure.
2661 * 0 on success, a negative errno value otherwise and rte_errno is set.
2664 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2665 const struct rte_flow_item *item,
2666 uint64_t *item_flags,
2667 struct rte_flow_error *error)
2669 const struct rte_flow_item_conntrack *spec = item->spec;
2670 const struct rte_flow_item_conntrack *mask = item->mask;
2674 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2675 return rte_flow_error_set(error, EINVAL,
2676 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2677 "Only one CT is supported");
2679 mask = &rte_flow_item_conntrack_mask;
2680 flags = spec->flags & mask->flags;
2681 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2682 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2683 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2684 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2685 return rte_flow_error_set(error, EINVAL,
2686 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2687 "Conflict status bits");
2688 /* State change also needs to be considered. */
2689 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2694 * Validate the pop VLAN action.
2697 * Pointer to the rte_eth_dev structure.
2698 * @param[in] action_flags
2699 * Holds the actions detected until now.
2701 * Pointer to the pop vlan action.
2702 * @param[in] item_flags
2703 * The items found in this flow rule.
2705 * Pointer to flow attributes.
2707 * Pointer to error structure.
2710 * 0 on success, a negative errno value otherwise and rte_errno is set.
2713 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2714 uint64_t action_flags,
2715 const struct rte_flow_action *action,
2716 uint64_t item_flags,
2717 const struct rte_flow_attr *attr,
2718 struct rte_flow_error *error)
2720 const struct mlx5_priv *priv = dev->data->dev_private;
2721 struct mlx5_dev_ctx_shared *sh = priv->sh;
2722 bool direction_error = false;
2724 if (!priv->sh->pop_vlan_action)
2725 return rte_flow_error_set(error, ENOTSUP,
2726 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2728 "pop vlan action is not supported");
2729 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2730 if (attr->transfer) {
2731 bool fdb_tx = priv->representor_id != UINT16_MAX;
2732 bool is_cx5 = sh->steering_format_version ==
2733 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2735 if (fdb_tx && is_cx5)
2736 direction_error = true;
2737 } else if (attr->egress) {
2738 direction_error = true;
2740 if (direction_error)
2741 return rte_flow_error_set(error, ENOTSUP,
2742 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2744 "pop vlan action not supported for egress");
2745 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2746 return rte_flow_error_set(error, ENOTSUP,
2747 RTE_FLOW_ERROR_TYPE_ACTION, action,
2748 "no support for multiple VLAN "
2750 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2751 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2752 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2753 return rte_flow_error_set(error, ENOTSUP,
2754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2756 "cannot pop vlan after decap without "
2757 "match on inner vlan in the flow");
2758 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2759 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2760 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2761 return rte_flow_error_set(error, ENOTSUP,
2762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2764 "cannot pop vlan without a "
2765 "match on (outer) vlan in the flow");
2766 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2767 return rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ACTION, action,
2769 "wrong action order, port_id should "
2770 "be after pop VLAN action");
2771 if (!attr->transfer && priv->representor)
2772 return rte_flow_error_set(error, ENOTSUP,
2773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2774 "pop vlan action for VF representor "
2775 "not supported on NIC table");
2780 * Get VLAN default info from vlan match info.
2783 * the list of item specifications.
2785 * pointer VLAN info to fill to.
2788 * 0 on success, a negative errno value otherwise and rte_errno is set.
2791 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2792 struct rte_vlan_hdr *vlan)
2794 const struct rte_flow_item_vlan nic_mask = {
2795 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2796 MLX5DV_FLOW_VLAN_VID_MASK),
2797 .inner_type = RTE_BE16(0xffff),
2802 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2803 int type = items->type;
2805 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2806 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2809 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2810 const struct rte_flow_item_vlan *vlan_m = items->mask;
2811 const struct rte_flow_item_vlan *vlan_v = items->spec;
2813 /* If VLAN item in pattern doesn't contain data, return here. */
2818 /* Only full match values are accepted */
2819 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2820 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2821 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2823 rte_be_to_cpu_16(vlan_v->tci &
2824 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2826 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2827 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2828 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2830 rte_be_to_cpu_16(vlan_v->tci &
2831 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2833 if (vlan_m->inner_type == nic_mask.inner_type)
2834 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2835 vlan_m->inner_type);
2840 * Validate the push VLAN action.
2843 * Pointer to the rte_eth_dev structure.
2844 * @param[in] action_flags
2845 * Holds the actions detected until now.
2846 * @param[in] item_flags
2847 * The items found in this flow rule.
2849 * Pointer to the action structure.
2851 * Pointer to flow attributes
2853 * Pointer to error structure.
2856 * 0 on success, a negative errno value otherwise and rte_errno is set.
2859 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2860 uint64_t action_flags,
2861 const struct rte_flow_item_vlan *vlan_m,
2862 const struct rte_flow_action *action,
2863 const struct rte_flow_attr *attr,
2864 struct rte_flow_error *error)
2866 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2867 const struct mlx5_priv *priv = dev->data->dev_private;
2868 struct mlx5_dev_ctx_shared *sh = priv->sh;
2869 bool direction_error = false;
2871 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2872 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2873 return rte_flow_error_set(error, EINVAL,
2874 RTE_FLOW_ERROR_TYPE_ACTION, action,
2875 "invalid vlan ethertype");
2876 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2877 return rte_flow_error_set(error, EINVAL,
2878 RTE_FLOW_ERROR_TYPE_ACTION, action,
2879 "wrong action order, port_id should "
2880 "be after push VLAN");
2881 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2882 if (attr->transfer) {
2883 bool fdb_tx = priv->representor_id != UINT16_MAX;
2884 bool is_cx5 = sh->steering_format_version ==
2885 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2887 if (!fdb_tx && is_cx5)
2888 direction_error = true;
2889 } else if (attr->ingress) {
2890 direction_error = true;
2892 if (direction_error)
2893 return rte_flow_error_set(error, ENOTSUP,
2894 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2896 "push vlan action not supported for ingress");
2897 if (!attr->transfer && priv->representor)
2898 return rte_flow_error_set(error, ENOTSUP,
2899 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2900 "push vlan action for VF representor "
2901 "not supported on NIC table");
2903 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2904 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2905 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2906 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2907 !(mlx5_flow_find_action
2908 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2909 return rte_flow_error_set(error, EINVAL,
2910 RTE_FLOW_ERROR_TYPE_ACTION, action,
2911 "not full match mask on VLAN PCP and "
2912 "there is no of_set_vlan_pcp action, "
2913 "push VLAN action cannot figure out "
2916 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2918 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2919 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2920 !(mlx5_flow_find_action
2921 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2922 return rte_flow_error_set(error, EINVAL,
2923 RTE_FLOW_ERROR_TYPE_ACTION, action,
2924 "not full match mask on VLAN VID and "
2925 "there is no of_set_vlan_vid action, "
2926 "push VLAN action cannot figure out "
2933 * Validate the set VLAN PCP.
2935 * @param[in] action_flags
2936 * Holds the actions detected until now.
2937 * @param[in] actions
2938 * Pointer to the list of actions remaining in the flow rule.
2940 * Pointer to error structure.
2943 * 0 on success, a negative errno value otherwise and rte_errno is set.
2946 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2947 const struct rte_flow_action actions[],
2948 struct rte_flow_error *error)
2950 const struct rte_flow_action *action = actions;
2951 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2953 if (conf->vlan_pcp > 7)
2954 return rte_flow_error_set(error, EINVAL,
2955 RTE_FLOW_ERROR_TYPE_ACTION, action,
2956 "VLAN PCP value is too big");
2957 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2958 return rte_flow_error_set(error, ENOTSUP,
2959 RTE_FLOW_ERROR_TYPE_ACTION, action,
2960 "set VLAN PCP action must follow "
2961 "the push VLAN action");
2962 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2963 return rte_flow_error_set(error, ENOTSUP,
2964 RTE_FLOW_ERROR_TYPE_ACTION, action,
2965 "Multiple VLAN PCP modification are "
2967 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "wrong action order, port_id should "
2971 "be after set VLAN PCP");
2976 * Validate the set VLAN VID.
2978 * @param[in] item_flags
2979 * Holds the items detected in this rule.
2980 * @param[in] action_flags
2981 * Holds the actions detected until now.
2982 * @param[in] actions
2983 * Pointer to the list of actions remaining in the flow rule.
2985 * Pointer to error structure.
2988 * 0 on success, a negative errno value otherwise and rte_errno is set.
2991 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2992 uint64_t action_flags,
2993 const struct rte_flow_action actions[],
2994 struct rte_flow_error *error)
2996 const struct rte_flow_action *action = actions;
2997 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2999 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3000 return rte_flow_error_set(error, EINVAL,
3001 RTE_FLOW_ERROR_TYPE_ACTION, action,
3002 "VLAN VID value is too big");
3003 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3004 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3005 return rte_flow_error_set(error, ENOTSUP,
3006 RTE_FLOW_ERROR_TYPE_ACTION, action,
3007 "set VLAN VID action must follow push"
3008 " VLAN action or match on VLAN item");
3009 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3010 return rte_flow_error_set(error, ENOTSUP,
3011 RTE_FLOW_ERROR_TYPE_ACTION, action,
3012 "Multiple VLAN VID modifications are "
3014 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3015 return rte_flow_error_set(error, EINVAL,
3016 RTE_FLOW_ERROR_TYPE_ACTION, action,
3017 "wrong action order, port_id should "
3018 "be after set VLAN VID");
3023 * Validate the FLAG action.
3026 * Pointer to the rte_eth_dev structure.
3027 * @param[in] action_flags
3028 * Holds the actions detected until now.
3030 * Pointer to flow attributes
3032 * Pointer to error structure.
3035 * 0 on success, a negative errno value otherwise and rte_errno is set.
3038 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3039 uint64_t action_flags,
3040 const struct rte_flow_attr *attr,
3041 struct rte_flow_error *error)
3043 struct mlx5_priv *priv = dev->data->dev_private;
3044 struct mlx5_dev_config *config = &priv->config;
3047 /* Fall back if no extended metadata register support. */
3048 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3049 return mlx5_flow_validate_action_flag(action_flags, attr,
3051 /* Extensive metadata mode requires registers. */
3052 if (!mlx5_flow_ext_mreg_supported(dev))
3053 return rte_flow_error_set(error, ENOTSUP,
3054 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3055 "no metadata registers "
3056 "to support flag action");
3057 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3058 return rte_flow_error_set(error, ENOTSUP,
3059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3060 "extended metadata register"
3061 " isn't available");
3062 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3065 MLX5_ASSERT(ret > 0);
3066 if (action_flags & MLX5_FLOW_ACTION_MARK)
3067 return rte_flow_error_set(error, EINVAL,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "can't mark and flag in same flow");
3070 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3071 return rte_flow_error_set(error, EINVAL,
3072 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 " actions in same flow");
3079 * Validate MARK action.
3082 * Pointer to the rte_eth_dev structure.
3084 * Pointer to action.
3085 * @param[in] action_flags
3086 * Holds the actions detected until now.
3088 * Pointer to flow attributes
3090 * Pointer to error structure.
3093 * 0 on success, a negative errno value otherwise and rte_errno is set.
3096 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3097 const struct rte_flow_action *action,
3098 uint64_t action_flags,
3099 const struct rte_flow_attr *attr,
3100 struct rte_flow_error *error)
3102 struct mlx5_priv *priv = dev->data->dev_private;
3103 struct mlx5_dev_config *config = &priv->config;
3104 const struct rte_flow_action_mark *mark = action->conf;
3107 if (is_tunnel_offload_active(dev))
3108 return rte_flow_error_set(error, ENOTSUP,
3109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3111 "if tunnel offload active");
3112 /* Fall back if no extended metadata register support. */
3113 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3114 return mlx5_flow_validate_action_mark(action, action_flags,
3116 /* Extensive metadata mode requires registers. */
3117 if (!mlx5_flow_ext_mreg_supported(dev))
3118 return rte_flow_error_set(error, ENOTSUP,
3119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3120 "no metadata registers "
3121 "to support mark action");
3122 if (!priv->sh->dv_mark_mask)
3123 return rte_flow_error_set(error, ENOTSUP,
3124 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "extended metadata register"
3126 " isn't available");
3127 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3130 MLX5_ASSERT(ret > 0);
3132 return rte_flow_error_set(error, EINVAL,
3133 RTE_FLOW_ERROR_TYPE_ACTION, action,
3134 "configuration cannot be null");
3135 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3136 return rte_flow_error_set(error, EINVAL,
3137 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3139 "mark id exceeds the limit");
3140 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3141 return rte_flow_error_set(error, EINVAL,
3142 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3143 "can't flag and mark in same flow");
3144 if (action_flags & MLX5_FLOW_ACTION_MARK)
3145 return rte_flow_error_set(error, EINVAL,
3146 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3147 "can't have 2 mark actions in same"
3153 * Validate SET_META action.
3156 * Pointer to the rte_eth_dev structure.
3158 * Pointer to the action structure.
3159 * @param[in] action_flags
3160 * Holds the actions detected until now.
3162 * Pointer to flow attributes
3164 * Pointer to error structure.
3167 * 0 on success, a negative errno value otherwise and rte_errno is set.
3170 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3171 const struct rte_flow_action *action,
3172 uint64_t action_flags __rte_unused,
3173 const struct rte_flow_attr *attr,
3174 struct rte_flow_error *error)
3176 struct mlx5_priv *priv = dev->data->dev_private;
3177 struct mlx5_dev_config *config = &priv->config;
3178 const struct rte_flow_action_set_meta *conf;
3179 uint32_t nic_mask = UINT32_MAX;
3182 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3183 !mlx5_flow_ext_mreg_supported(dev))
3184 return rte_flow_error_set(error, ENOTSUP,
3185 RTE_FLOW_ERROR_TYPE_ACTION, action,
3186 "extended metadata register"
3187 " isn't supported");
3188 reg = flow_dv_get_metadata_reg(dev, attr, error);
3192 return rte_flow_error_set(error, ENOTSUP,
3193 RTE_FLOW_ERROR_TYPE_ACTION, action,
3194 "unavailable extended metadata register");
3195 if (reg != REG_A && reg != REG_B) {
3196 struct mlx5_priv *priv = dev->data->dev_private;
3198 nic_mask = priv->sh->dv_meta_mask;
3200 if (!(action->conf))
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION, action,
3203 "configuration cannot be null");
3204 conf = (const struct rte_flow_action_set_meta *)action->conf;
3206 return rte_flow_error_set(error, EINVAL,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "zero mask doesn't have any effect");
3209 if (conf->mask & ~nic_mask)
3210 return rte_flow_error_set(error, EINVAL,
3211 RTE_FLOW_ERROR_TYPE_ACTION, action,
3212 "meta data must be within reg C0");
3217 * Validate SET_TAG action.
3220 * Pointer to the rte_eth_dev structure.
3222 * Pointer to the action structure.
3223 * @param[in] action_flags
3224 * Holds the actions detected until now.
3226 * Pointer to flow attributes
3228 * Pointer to error structure.
3231 * 0 on success, a negative errno value otherwise and rte_errno is set.
3234 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3235 const struct rte_flow_action *action,
3236 uint64_t action_flags,
3237 const struct rte_flow_attr *attr,
3238 struct rte_flow_error *error)
3240 const struct rte_flow_action_set_tag *conf;
3241 const uint64_t terminal_action_flags =
3242 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3243 MLX5_FLOW_ACTION_RSS;
3246 if (!mlx5_flow_ext_mreg_supported(dev))
3247 return rte_flow_error_set(error, ENOTSUP,
3248 RTE_FLOW_ERROR_TYPE_ACTION, action,
3249 "extensive metadata register"
3250 " isn't supported");
3251 if (!(action->conf))
3252 return rte_flow_error_set(error, EINVAL,
3253 RTE_FLOW_ERROR_TYPE_ACTION, action,
3254 "configuration cannot be null");
3255 conf = (const struct rte_flow_action_set_tag *)action->conf;
3257 return rte_flow_error_set(error, EINVAL,
3258 RTE_FLOW_ERROR_TYPE_ACTION, action,
3259 "zero mask doesn't have any effect");
3260 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3263 if (!attr->transfer && attr->ingress &&
3264 (action_flags & terminal_action_flags))
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION, action,
3267 "set_tag has no effect"
3268 " with terminal actions");
3273 * Validate count action.
3276 * Pointer to rte_eth_dev structure.
3278 * Indicator if action is shared.
3279 * @param[in] action_flags
3280 * Holds the actions detected until now.
3282 * Pointer to error structure.
3285 * 0 on success, a negative errno value otherwise and rte_errno is set.
3288 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3289 uint64_t action_flags,
3290 struct rte_flow_error *error)
3292 struct mlx5_priv *priv = dev->data->dev_private;
3294 if (!priv->sh->devx)
3296 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3297 return rte_flow_error_set(error, EINVAL,
3298 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3299 "duplicate count actions set");
3300 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3301 !priv->sh->flow_hit_aso_en)
3302 return rte_flow_error_set(error, EINVAL,
3303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3304 "old age and shared count combination is not supported");
3305 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3309 return rte_flow_error_set
3311 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3313 "count action not supported");
3317 * Validate the L2 encap action.
3320 * Pointer to the rte_eth_dev structure.
3321 * @param[in] action_flags
3322 * Holds the actions detected until now.
3324 * Pointer to the action structure.
3326 * Pointer to flow attributes.
3328 * Pointer to error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3335 uint64_t action_flags,
3336 const struct rte_flow_action *action,
3337 const struct rte_flow_attr *attr,
3338 struct rte_flow_error *error)
3340 const struct mlx5_priv *priv = dev->data->dev_private;
3342 if (!(action->conf))
3343 return rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ACTION, action,
3345 "configuration cannot be null");
3346 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can only have a single encap action "
3351 if (!attr->transfer && priv->representor)
3352 return rte_flow_error_set(error, ENOTSUP,
3353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3354 "encap action for VF representor "
3355 "not supported on NIC table");
3360 * Validate a decap action.
3363 * Pointer to the rte_eth_dev structure.
3364 * @param[in] action_flags
3365 * Holds the actions detected until now.
3367 * Pointer to the action structure.
3368 * @param[in] item_flags
3369 * Holds the items detected.
3371 * Pointer to flow attributes
3373 * Pointer to error structure.
3376 * 0 on success, a negative errno value otherwise and rte_errno is set.
3379 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3380 uint64_t action_flags,
3381 const struct rte_flow_action *action,
3382 const uint64_t item_flags,
3383 const struct rte_flow_attr *attr,
3384 struct rte_flow_error *error)
3386 const struct mlx5_priv *priv = dev->data->dev_private;
3388 if (priv->sh->cdev->config.hca_attr.scatter_fcs_w_decap_disable &&
3389 !priv->config.decap_en)
3390 return rte_flow_error_set(error, ENOTSUP,
3391 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3392 "decap is not enabled");
3393 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3394 return rte_flow_error_set(error, ENOTSUP,
3395 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3397 MLX5_FLOW_ACTION_DECAP ? "can only "
3398 "have a single decap action" : "decap "
3399 "after encap is not supported");
3400 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3401 return rte_flow_error_set(error, EINVAL,
3402 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3403 "can't have decap action after"
3406 return rte_flow_error_set(error, ENOTSUP,
3407 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3409 "decap action not supported for "
3411 if (!attr->transfer && priv->representor)
3412 return rte_flow_error_set(error, ENOTSUP,
3413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3414 "decap action for VF representor "
3415 "not supported on NIC table");
3416 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3417 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3418 return rte_flow_error_set(error, ENOTSUP,
3419 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3420 "VXLAN item should be present for VXLAN decap");
3424 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3427 * Validate the raw encap and decap actions.
3430 * Pointer to the rte_eth_dev structure.
3432 * Pointer to the decap action.
3434 * Pointer to the encap action.
3436 * Pointer to flow attributes
3437 * @param[in/out] action_flags
3438 * Holds the actions detected until now.
3439 * @param[out] actions_n
3440 * pointer to the number of actions counter.
3442 * Pointer to the action structure.
3443 * @param[in] item_flags
3444 * Holds the items detected.
3446 * Pointer to error structure.
3449 * 0 on success, a negative errno value otherwise and rte_errno is set.
3452 flow_dv_validate_action_raw_encap_decap
3453 (struct rte_eth_dev *dev,
3454 const struct rte_flow_action_raw_decap *decap,
3455 const struct rte_flow_action_raw_encap *encap,
3456 const struct rte_flow_attr *attr, uint64_t *action_flags,
3457 int *actions_n, const struct rte_flow_action *action,
3458 uint64_t item_flags, struct rte_flow_error *error)
3460 const struct mlx5_priv *priv = dev->data->dev_private;
3463 if (encap && (!encap->size || !encap->data))
3464 return rte_flow_error_set(error, EINVAL,
3465 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3466 "raw encap data cannot be empty");
3467 if (decap && encap) {
3468 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3469 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3472 else if (encap->size <=
3473 MLX5_ENCAPSULATION_DECISION_SIZE &&
3475 MLX5_ENCAPSULATION_DECISION_SIZE)
3478 else if (encap->size >
3479 MLX5_ENCAPSULATION_DECISION_SIZE &&
3481 MLX5_ENCAPSULATION_DECISION_SIZE)
3482 /* 2 L2 actions: encap and decap. */
3485 return rte_flow_error_set(error,
3487 RTE_FLOW_ERROR_TYPE_ACTION,
3488 NULL, "unsupported too small "
3489 "raw decap and too small raw "
3490 "encap combination");
3493 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3494 item_flags, attr, error);
3497 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3501 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3502 return rte_flow_error_set(error, ENOTSUP,
3503 RTE_FLOW_ERROR_TYPE_ACTION,
3505 "small raw encap size");
3506 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3507 return rte_flow_error_set(error, EINVAL,
3508 RTE_FLOW_ERROR_TYPE_ACTION,
3510 "more than one encap action");
3511 if (!attr->transfer && priv->representor)
3512 return rte_flow_error_set
3514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3515 "encap action for VF representor "
3516 "not supported on NIC table");
3517 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3524 * Validate the ASO CT action.
3527 * Pointer to the rte_eth_dev structure.
3528 * @param[in] action_flags
3529 * Holds the actions detected until now.
3530 * @param[in] item_flags
3531 * The items found in this flow rule.
3533 * Pointer to flow attributes.
3535 * Pointer to error structure.
3538 * 0 on success, a negative errno value otherwise and rte_errno is set.
3541 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3542 uint64_t action_flags,
3543 uint64_t item_flags,
3544 const struct rte_flow_attr *attr,
3545 struct rte_flow_error *error)
3549 if (attr->group == 0 && !attr->transfer)
3550 return rte_flow_error_set(error, ENOTSUP,
3551 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3553 "Only support non-root table");
3554 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3555 return rte_flow_error_set(error, ENOTSUP,
3556 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557 "CT cannot follow a fate action");
3558 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3559 (action_flags & MLX5_FLOW_ACTION_AGE))
3560 return rte_flow_error_set(error, EINVAL,
3561 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3562 "Only one ASO action is supported");
3563 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3564 return rte_flow_error_set(error, EINVAL,
3565 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3566 "Encap cannot exist before CT");
3567 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3568 return rte_flow_error_set(error, EINVAL,
3569 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3570 "Not a outer TCP packet");
3575 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3576 struct mlx5_list_entry *entry, void *cb_ctx)
3578 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3579 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3580 struct mlx5_flow_dv_encap_decap_resource *resource;
3582 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3584 if (resource->reformat_type == ctx_resource->reformat_type &&
3585 resource->ft_type == ctx_resource->ft_type &&
3586 resource->flags == ctx_resource->flags &&
3587 resource->size == ctx_resource->size &&
3588 !memcmp((const void *)resource->buf,
3589 (const void *)ctx_resource->buf,
3595 struct mlx5_list_entry *
3596 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3598 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3599 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3600 struct mlx5dv_dr_domain *domain;
3601 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3602 struct mlx5_flow_dv_encap_decap_resource *resource;
3606 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3607 domain = sh->fdb_domain;
3608 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3609 domain = sh->rx_domain;
3611 domain = sh->tx_domain;
3612 /* Register new encap/decap resource. */
3613 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3615 rte_flow_error_set(ctx->error, ENOMEM,
3616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3617 "cannot allocate resource memory");
3620 *resource = *ctx_resource;
3621 resource->idx = idx;
3622 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3626 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3627 rte_flow_error_set(ctx->error, ENOMEM,
3628 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3629 NULL, "cannot create action");
3633 return &resource->entry;
3636 struct mlx5_list_entry *
3637 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3640 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3641 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3645 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3647 if (!cache_resource) {
3648 rte_flow_error_set(ctx->error, ENOMEM,
3649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3650 "cannot allocate resource memory");
3653 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3654 cache_resource->idx = idx;
3655 return &cache_resource->entry;
3659 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3661 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3662 struct mlx5_flow_dv_encap_decap_resource *res =
3663 container_of(entry, typeof(*res), entry);
3665 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3669 * Find existing encap/decap resource or create and register a new one.
3671 * @param[in, out] dev
3672 * Pointer to rte_eth_dev structure.
3673 * @param[in, out] resource
3674 * Pointer to encap/decap resource.
3675 * @parm[in, out] dev_flow
3676 * Pointer to the dev_flow.
3678 * pointer to error structure.
3681 * 0 on success otherwise -errno and errno is set.
3684 flow_dv_encap_decap_resource_register
3685 (struct rte_eth_dev *dev,
3686 struct mlx5_flow_dv_encap_decap_resource *resource,
3687 struct mlx5_flow *dev_flow,
3688 struct rte_flow_error *error)
3690 struct mlx5_priv *priv = dev->data->dev_private;
3691 struct mlx5_dev_ctx_shared *sh = priv->sh;
3692 struct mlx5_list_entry *entry;
3696 uint32_t refmt_type:8;
3698 * Header reformat actions can be shared between
3699 * non-root tables. One bit to indicate non-root
3703 uint32_t reserve:15;
3706 } encap_decap_key = {
3708 .ft_type = resource->ft_type,
3709 .refmt_type = resource->reformat_type,
3710 .is_root = !!dev_flow->dv.group,
3714 struct mlx5_flow_cb_ctx ctx = {
3718 struct mlx5_hlist *encaps_decaps;
3721 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3723 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3725 flow_dv_encap_decap_create_cb,
3726 flow_dv_encap_decap_match_cb,
3727 flow_dv_encap_decap_remove_cb,
3728 flow_dv_encap_decap_clone_cb,
3729 flow_dv_encap_decap_clone_free_cb);
3730 if (unlikely(!encaps_decaps))
3732 resource->flags = dev_flow->dv.group ? 0 : 1;
3733 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3734 sizeof(encap_decap_key.v32), 0);
3735 if (resource->reformat_type !=
3736 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3738 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3739 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3742 resource = container_of(entry, typeof(*resource), entry);
3743 dev_flow->dv.encap_decap = resource;
3744 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3749 * Find existing table jump resource or create and register a new one.
3751 * @param[in, out] dev
3752 * Pointer to rte_eth_dev structure.
3753 * @param[in, out] tbl
3754 * Pointer to flow table resource.
3755 * @parm[in, out] dev_flow
3756 * Pointer to the dev_flow.
3758 * pointer to error structure.
3761 * 0 on success otherwise -errno and errno is set.
3764 flow_dv_jump_tbl_resource_register
3765 (struct rte_eth_dev *dev __rte_unused,
3766 struct mlx5_flow_tbl_resource *tbl,
3767 struct mlx5_flow *dev_flow,
3768 struct rte_flow_error *error __rte_unused)
3770 struct mlx5_flow_tbl_data_entry *tbl_data =
3771 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3774 MLX5_ASSERT(tbl_data->jump.action);
3775 dev_flow->handle->rix_jump = tbl_data->idx;
3776 dev_flow->dv.jump = &tbl_data->jump;
3781 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3782 struct mlx5_list_entry *entry, void *cb_ctx)
3784 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3785 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3786 struct mlx5_flow_dv_port_id_action_resource *res =
3787 container_of(entry, typeof(*res), entry);
3789 return ref->port_id != res->port_id;
3792 struct mlx5_list_entry *
3793 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3795 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3796 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3797 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3798 struct mlx5_flow_dv_port_id_action_resource *resource;
3802 /* Register new port id action resource. */
3803 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3805 rte_flow_error_set(ctx->error, ENOMEM,
3806 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3807 "cannot allocate port_id action memory");
3811 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3815 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3816 rte_flow_error_set(ctx->error, ENOMEM,
3817 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3818 "cannot create action");
3821 resource->idx = idx;
3822 return &resource->entry;
3825 struct mlx5_list_entry *
3826 flow_dv_port_id_clone_cb(void *tool_ctx,
3827 struct mlx5_list_entry *entry __rte_unused,
3830 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3831 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3832 struct mlx5_flow_dv_port_id_action_resource *resource;
3835 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3837 rte_flow_error_set(ctx->error, ENOMEM,
3838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3839 "cannot allocate port_id action memory");
3842 memcpy(resource, entry, sizeof(*resource));
3843 resource->idx = idx;
3844 return &resource->entry;
3848 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3850 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3851 struct mlx5_flow_dv_port_id_action_resource *resource =
3852 container_of(entry, typeof(*resource), entry);
3854 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3858 * Find existing table port ID resource or create and register a new one.
3860 * @param[in, out] dev
3861 * Pointer to rte_eth_dev structure.
3862 * @param[in, out] ref
3863 * Pointer to port ID action resource reference.
3864 * @parm[in, out] dev_flow
3865 * Pointer to the dev_flow.
3867 * pointer to error structure.
3870 * 0 on success otherwise -errno and errno is set.
3873 flow_dv_port_id_action_resource_register
3874 (struct rte_eth_dev *dev,
3875 struct mlx5_flow_dv_port_id_action_resource *ref,
3876 struct mlx5_flow *dev_flow,
3877 struct rte_flow_error *error)
3879 struct mlx5_priv *priv = dev->data->dev_private;
3880 struct mlx5_list_entry *entry;
3881 struct mlx5_flow_dv_port_id_action_resource *resource;
3882 struct mlx5_flow_cb_ctx ctx = {
3887 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3890 resource = container_of(entry, typeof(*resource), entry);
3891 dev_flow->dv.port_id_action = resource;
3892 dev_flow->handle->rix_port_id_action = resource->idx;
3897 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3898 struct mlx5_list_entry *entry, void *cb_ctx)
3900 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3901 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3902 struct mlx5_flow_dv_push_vlan_action_resource *res =
3903 container_of(entry, typeof(*res), entry);
3905 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3908 struct mlx5_list_entry *
3909 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3911 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3912 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3913 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3914 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3915 struct mlx5dv_dr_domain *domain;
3919 /* Register new port id action resource. */
3920 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3922 rte_flow_error_set(ctx->error, ENOMEM,
3923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3924 "cannot allocate push_vlan action memory");
3928 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3929 domain = sh->fdb_domain;
3930 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3931 domain = sh->rx_domain;
3933 domain = sh->tx_domain;
3934 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3937 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3938 rte_flow_error_set(ctx->error, ENOMEM,
3939 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3940 "cannot create push vlan action");
3943 resource->idx = idx;
3944 return &resource->entry;
3947 struct mlx5_list_entry *
3948 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3949 struct mlx5_list_entry *entry __rte_unused,
3952 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3953 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3954 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3957 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3959 rte_flow_error_set(ctx->error, ENOMEM,
3960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3961 "cannot allocate push_vlan action memory");
3964 memcpy(resource, entry, sizeof(*resource));
3965 resource->idx = idx;
3966 return &resource->entry;
3970 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3972 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3973 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3974 container_of(entry, typeof(*resource), entry);
3976 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3980 * Find existing push vlan resource or create and register a new one.
3982 * @param [in, out] dev
3983 * Pointer to rte_eth_dev structure.
3984 * @param[in, out] ref
3985 * Pointer to port ID action resource reference.
3986 * @parm[in, out] dev_flow
3987 * Pointer to the dev_flow.
3989 * pointer to error structure.
3992 * 0 on success otherwise -errno and errno is set.
3995 flow_dv_push_vlan_action_resource_register
3996 (struct rte_eth_dev *dev,
3997 struct mlx5_flow_dv_push_vlan_action_resource *ref,
3998 struct mlx5_flow *dev_flow,
3999 struct rte_flow_error *error)
4001 struct mlx5_priv *priv = dev->data->dev_private;
4002 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4003 struct mlx5_list_entry *entry;
4004 struct mlx5_flow_cb_ctx ctx = {
4009 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4012 resource = container_of(entry, typeof(*resource), entry);
4014 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4015 dev_flow->dv.push_vlan_res = resource;
4020 * Get the size of specific rte_flow_item_type hdr size
4022 * @param[in] item_type
4023 * Tested rte_flow_item_type.
4026 * sizeof struct item_type, 0 if void or irrelevant.
4029 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4033 switch (item_type) {
4034 case RTE_FLOW_ITEM_TYPE_ETH:
4035 retval = sizeof(struct rte_ether_hdr);
4037 case RTE_FLOW_ITEM_TYPE_VLAN:
4038 retval = sizeof(struct rte_vlan_hdr);
4040 case RTE_FLOW_ITEM_TYPE_IPV4:
4041 retval = sizeof(struct rte_ipv4_hdr);
4043 case RTE_FLOW_ITEM_TYPE_IPV6:
4044 retval = sizeof(struct rte_ipv6_hdr);
4046 case RTE_FLOW_ITEM_TYPE_UDP:
4047 retval = sizeof(struct rte_udp_hdr);
4049 case RTE_FLOW_ITEM_TYPE_TCP:
4050 retval = sizeof(struct rte_tcp_hdr);
4052 case RTE_FLOW_ITEM_TYPE_VXLAN:
4053 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4054 retval = sizeof(struct rte_vxlan_hdr);
4056 case RTE_FLOW_ITEM_TYPE_GRE:
4057 case RTE_FLOW_ITEM_TYPE_NVGRE:
4058 retval = sizeof(struct rte_gre_hdr);
4060 case RTE_FLOW_ITEM_TYPE_MPLS:
4061 retval = sizeof(struct rte_mpls_hdr);
4063 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4071 #define MLX5_ENCAP_IPV4_VERSION 0x40
4072 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4073 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4074 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4075 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4076 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4077 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4080 * Convert the encap action data from list of rte_flow_item to raw buffer
4083 * Pointer to rte_flow_item objects list.
4085 * Pointer to the output buffer.
4087 * Pointer to the output buffer size.
4089 * Pointer to the error structure.
4092 * 0 on success, a negative errno value otherwise and rte_errno is set.
4095 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4096 size_t *size, struct rte_flow_error *error)
4098 struct rte_ether_hdr *eth = NULL;
4099 struct rte_vlan_hdr *vlan = NULL;
4100 struct rte_ipv4_hdr *ipv4 = NULL;
4101 struct rte_ipv6_hdr *ipv6 = NULL;
4102 struct rte_udp_hdr *udp = NULL;
4103 struct rte_vxlan_hdr *vxlan = NULL;
4104 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4105 struct rte_gre_hdr *gre = NULL;
4107 size_t temp_size = 0;
4110 return rte_flow_error_set(error, EINVAL,
4111 RTE_FLOW_ERROR_TYPE_ACTION,
4112 NULL, "invalid empty data");
4113 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4114 len = flow_dv_get_item_hdr_len(items->type);
4115 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4116 return rte_flow_error_set(error, EINVAL,
4117 RTE_FLOW_ERROR_TYPE_ACTION,
4118 (void *)items->type,
4119 "items total size is too big"
4120 " for encap action");
4121 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4122 switch (items->type) {
4123 case RTE_FLOW_ITEM_TYPE_ETH:
4124 eth = (struct rte_ether_hdr *)&buf[temp_size];
4126 case RTE_FLOW_ITEM_TYPE_VLAN:
4127 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4129 return rte_flow_error_set(error, EINVAL,
4130 RTE_FLOW_ERROR_TYPE_ACTION,
4131 (void *)items->type,
4132 "eth header not found");
4133 if (!eth->ether_type)
4134 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4136 case RTE_FLOW_ITEM_TYPE_IPV4:
4137 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4139 return rte_flow_error_set(error, EINVAL,
4140 RTE_FLOW_ERROR_TYPE_ACTION,
4141 (void *)items->type,
4142 "neither eth nor vlan"
4144 if (vlan && !vlan->eth_proto)
4145 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4146 else if (eth && !eth->ether_type)
4147 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4148 if (!ipv4->version_ihl)
4149 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4150 MLX5_ENCAP_IPV4_IHL_MIN;
4151 if (!ipv4->time_to_live)
4152 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4154 case RTE_FLOW_ITEM_TYPE_IPV6:
4155 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4157 return rte_flow_error_set(error, EINVAL,
4158 RTE_FLOW_ERROR_TYPE_ACTION,
4159 (void *)items->type,
4160 "neither eth nor vlan"
4162 if (vlan && !vlan->eth_proto)
4163 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4164 else if (eth && !eth->ether_type)
4165 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4166 if (!ipv6->vtc_flow)
4168 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4169 if (!ipv6->hop_limits)
4170 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4172 case RTE_FLOW_ITEM_TYPE_UDP:
4173 udp = (struct rte_udp_hdr *)&buf[temp_size];
4175 return rte_flow_error_set(error, EINVAL,
4176 RTE_FLOW_ERROR_TYPE_ACTION,
4177 (void *)items->type,
4178 "ip header not found");
4179 if (ipv4 && !ipv4->next_proto_id)
4180 ipv4->next_proto_id = IPPROTO_UDP;
4181 else if (ipv6 && !ipv6->proto)
4182 ipv6->proto = IPPROTO_UDP;
4184 case RTE_FLOW_ITEM_TYPE_VXLAN:
4185 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4187 return rte_flow_error_set(error, EINVAL,
4188 RTE_FLOW_ERROR_TYPE_ACTION,
4189 (void *)items->type,
4190 "udp header not found");
4192 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4193 if (!vxlan->vx_flags)
4195 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4197 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4198 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4200 return rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION,
4202 (void *)items->type,
4203 "udp header not found");
4204 if (!vxlan_gpe->proto)
4205 return rte_flow_error_set(error, EINVAL,
4206 RTE_FLOW_ERROR_TYPE_ACTION,
4207 (void *)items->type,
4208 "next protocol not found");
4211 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4212 if (!vxlan_gpe->vx_flags)
4213 vxlan_gpe->vx_flags =
4214 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4216 case RTE_FLOW_ITEM_TYPE_GRE:
4217 case RTE_FLOW_ITEM_TYPE_NVGRE:
4218 gre = (struct rte_gre_hdr *)&buf[temp_size];
4220 return rte_flow_error_set(error, EINVAL,
4221 RTE_FLOW_ERROR_TYPE_ACTION,
4222 (void *)items->type,
4223 "next protocol not found");
4225 return rte_flow_error_set(error, EINVAL,
4226 RTE_FLOW_ERROR_TYPE_ACTION,
4227 (void *)items->type,
4228 "ip header not found");
4229 if (ipv4 && !ipv4->next_proto_id)
4230 ipv4->next_proto_id = IPPROTO_GRE;
4231 else if (ipv6 && !ipv6->proto)
4232 ipv6->proto = IPPROTO_GRE;
4234 case RTE_FLOW_ITEM_TYPE_VOID:
4237 return rte_flow_error_set(error, EINVAL,
4238 RTE_FLOW_ERROR_TYPE_ACTION,
4239 (void *)items->type,
4240 "unsupported item type");
4250 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4252 struct rte_ether_hdr *eth = NULL;
4253 struct rte_vlan_hdr *vlan = NULL;
4254 struct rte_ipv6_hdr *ipv6 = NULL;
4255 struct rte_udp_hdr *udp = NULL;
4259 eth = (struct rte_ether_hdr *)data;
4260 next_hdr = (char *)(eth + 1);
4261 proto = RTE_BE16(eth->ether_type);
4264 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4265 vlan = (struct rte_vlan_hdr *)next_hdr;
4266 proto = RTE_BE16(vlan->eth_proto);
4267 next_hdr += sizeof(struct rte_vlan_hdr);
4270 /* HW calculates IPv4 csum. no need to proceed */
4271 if (proto == RTE_ETHER_TYPE_IPV4)
4274 /* non IPv4/IPv6 header. not supported */
4275 if (proto != RTE_ETHER_TYPE_IPV6) {
4276 return rte_flow_error_set(error, ENOTSUP,
4277 RTE_FLOW_ERROR_TYPE_ACTION,
4278 NULL, "Cannot offload non IPv4/IPv6");
4281 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4283 /* ignore non UDP */
4284 if (ipv6->proto != IPPROTO_UDP)
4287 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4288 udp->dgram_cksum = 0;
4294 * Convert L2 encap action to DV specification.
4297 * Pointer to rte_eth_dev structure.
4299 * Pointer to action structure.
4300 * @param[in, out] dev_flow
4301 * Pointer to the mlx5_flow.
4302 * @param[in] transfer
4303 * Mark if the flow is E-Switch flow.
4305 * Pointer to the error structure.
4308 * 0 on success, a negative errno value otherwise and rte_errno is set.
4311 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4312 const struct rte_flow_action *action,
4313 struct mlx5_flow *dev_flow,
4315 struct rte_flow_error *error)
4317 const struct rte_flow_item *encap_data;
4318 const struct rte_flow_action_raw_encap *raw_encap_data;
4319 struct mlx5_flow_dv_encap_decap_resource res = {
4321 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4322 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4323 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4326 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4328 (const struct rte_flow_action_raw_encap *)action->conf;
4329 res.size = raw_encap_data->size;
4330 memcpy(res.buf, raw_encap_data->data, res.size);
4332 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4334 ((const struct rte_flow_action_vxlan_encap *)
4335 action->conf)->definition;
4338 ((const struct rte_flow_action_nvgre_encap *)
4339 action->conf)->definition;
4340 if (flow_dv_convert_encap_data(encap_data, res.buf,
4344 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4346 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4347 return rte_flow_error_set(error, EINVAL,
4348 RTE_FLOW_ERROR_TYPE_ACTION,
4349 NULL, "can't create L2 encap action");
4354 * Convert L2 decap action to DV specification.
4357 * Pointer to rte_eth_dev structure.
4358 * @param[in, out] dev_flow
4359 * Pointer to the mlx5_flow.
4360 * @param[in] transfer
4361 * Mark if the flow is E-Switch flow.
4363 * Pointer to the error structure.
4366 * 0 on success, a negative errno value otherwise and rte_errno is set.
4369 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4370 struct mlx5_flow *dev_flow,
4372 struct rte_flow_error *error)
4374 struct mlx5_flow_dv_encap_decap_resource res = {
4377 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4378 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4379 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4382 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4383 return rte_flow_error_set(error, EINVAL,
4384 RTE_FLOW_ERROR_TYPE_ACTION,
4385 NULL, "can't create L2 decap action");
4390 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4393 * Pointer to rte_eth_dev structure.
4395 * Pointer to action structure.
4396 * @param[in, out] dev_flow
4397 * Pointer to the mlx5_flow.
4399 * Pointer to the flow attributes.
4401 * Pointer to the error structure.
4404 * 0 on success, a negative errno value otherwise and rte_errno is set.
4407 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4408 const struct rte_flow_action *action,
4409 struct mlx5_flow *dev_flow,
4410 const struct rte_flow_attr *attr,
4411 struct rte_flow_error *error)
4413 const struct rte_flow_action_raw_encap *encap_data;
4414 struct mlx5_flow_dv_encap_decap_resource res;
4416 memset(&res, 0, sizeof(res));
4417 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4418 res.size = encap_data->size;
4419 memcpy(res.buf, encap_data->data, res.size);
4420 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4421 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4422 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4424 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4426 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4427 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4428 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4429 return rte_flow_error_set(error, EINVAL,
4430 RTE_FLOW_ERROR_TYPE_ACTION,
4431 NULL, "can't create encap action");
4436 * Create action push VLAN.
4439 * Pointer to rte_eth_dev structure.
4441 * Pointer to the flow attributes.
4443 * Pointer to the vlan to push to the Ethernet header.
4444 * @param[in, out] dev_flow
4445 * Pointer to the mlx5_flow.
4447 * Pointer to the error structure.
4450 * 0 on success, a negative errno value otherwise and rte_errno is set.
4453 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4454 const struct rte_flow_attr *attr,
4455 const struct rte_vlan_hdr *vlan,
4456 struct mlx5_flow *dev_flow,
4457 struct rte_flow_error *error)
4459 struct mlx5_flow_dv_push_vlan_action_resource res;
4461 memset(&res, 0, sizeof(res));
4463 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4466 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4468 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4469 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4470 return flow_dv_push_vlan_action_resource_register
4471 (dev, &res, dev_flow, error);
4475 * Validate the modify-header actions.
4477 * @param[in] action_flags
4478 * Holds the actions detected until now.
4480 * Pointer to the modify action.
4482 * Pointer to error structure.
4485 * 0 on success, a negative errno value otherwise and rte_errno is set.
4488 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4489 const struct rte_flow_action *action,
4490 struct rte_flow_error *error)
4492 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4493 return rte_flow_error_set(error, EINVAL,
4494 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4495 NULL, "action configuration not set");
4496 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4497 return rte_flow_error_set(error, EINVAL,
4498 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4499 "can't have encap action before"
4505 * Validate the modify-header MAC address actions.
4507 * @param[in] action_flags
4508 * Holds the actions detected until now.
4510 * Pointer to the modify action.
4511 * @param[in] item_flags
4512 * Holds the items detected.
4514 * Pointer to error structure.
4517 * 0 on success, a negative errno value otherwise and rte_errno is set.
4520 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4521 const struct rte_flow_action *action,
4522 const uint64_t item_flags,
4523 struct rte_flow_error *error)
4527 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4529 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4530 return rte_flow_error_set(error, EINVAL,
4531 RTE_FLOW_ERROR_TYPE_ACTION,
4533 "no L2 item in pattern");
4539 * Validate the modify-header IPv4 address actions.
4541 * @param[in] action_flags
4542 * Holds the actions detected until now.
4544 * Pointer to the modify action.
4545 * @param[in] item_flags
4546 * Holds the items detected.
4548 * Pointer to error structure.
4551 * 0 on success, a negative errno value otherwise and rte_errno is set.
4554 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4555 const struct rte_flow_action *action,
4556 const uint64_t item_flags,
4557 struct rte_flow_error *error)
4562 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4564 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4565 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4566 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4567 if (!(item_flags & layer))
4568 return rte_flow_error_set(error, EINVAL,
4569 RTE_FLOW_ERROR_TYPE_ACTION,
4571 "no ipv4 item in pattern");
4577 * Validate the modify-header IPv6 address actions.
4579 * @param[in] action_flags
4580 * Holds the actions detected until now.
4582 * Pointer to the modify action.
4583 * @param[in] item_flags
4584 * Holds the items detected.
4586 * Pointer to error structure.
4589 * 0 on success, a negative errno value otherwise and rte_errno is set.
4592 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4593 const struct rte_flow_action *action,
4594 const uint64_t item_flags,
4595 struct rte_flow_error *error)
4600 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4602 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4603 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4604 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4605 if (!(item_flags & layer))
4606 return rte_flow_error_set(error, EINVAL,
4607 RTE_FLOW_ERROR_TYPE_ACTION,
4609 "no ipv6 item in pattern");
4615 * Validate the modify-header TP actions.
4617 * @param[in] action_flags
4618 * Holds the actions detected until now.
4620 * Pointer to the modify action.
4621 * @param[in] item_flags
4622 * Holds the items detected.
4624 * Pointer to error structure.
4627 * 0 on success, a negative errno value otherwise and rte_errno is set.
4630 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4631 const struct rte_flow_action *action,
4632 const uint64_t item_flags,
4633 struct rte_flow_error *error)
4638 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4640 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4641 MLX5_FLOW_LAYER_INNER_L4 :
4642 MLX5_FLOW_LAYER_OUTER_L4;
4643 if (!(item_flags & layer))
4644 return rte_flow_error_set(error, EINVAL,
4645 RTE_FLOW_ERROR_TYPE_ACTION,
4646 NULL, "no transport layer "
4653 * Validate the modify-header actions of increment/decrement
4654 * TCP Sequence-number.
4656 * @param[in] action_flags
4657 * Holds the actions detected until now.
4659 * Pointer to the modify action.
4660 * @param[in] item_flags
4661 * Holds the items detected.
4663 * Pointer to error structure.
4666 * 0 on success, a negative errno value otherwise and rte_errno is set.
4669 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4670 const struct rte_flow_action *action,
4671 const uint64_t item_flags,
4672 struct rte_flow_error *error)
4677 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4679 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4680 MLX5_FLOW_LAYER_INNER_L4_TCP :
4681 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4682 if (!(item_flags & layer))
4683 return rte_flow_error_set(error, EINVAL,
4684 RTE_FLOW_ERROR_TYPE_ACTION,
4685 NULL, "no TCP item in"
4687 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4688 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4689 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4690 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4691 return rte_flow_error_set(error, EINVAL,
4692 RTE_FLOW_ERROR_TYPE_ACTION,
4694 "cannot decrease and increase"
4695 " TCP sequence number"
4696 " at the same time");
4702 * Validate the modify-header actions of increment/decrement
4703 * TCP Acknowledgment number.
4705 * @param[in] action_flags
4706 * Holds the actions detected until now.
4708 * Pointer to the modify action.
4709 * @param[in] item_flags
4710 * Holds the items detected.
4712 * Pointer to error structure.
4715 * 0 on success, a negative errno value otherwise and rte_errno is set.
4718 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4719 const struct rte_flow_action *action,
4720 const uint64_t item_flags,
4721 struct rte_flow_error *error)
4726 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4728 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4729 MLX5_FLOW_LAYER_INNER_L4_TCP :
4730 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4731 if (!(item_flags & layer))
4732 return rte_flow_error_set(error, EINVAL,
4733 RTE_FLOW_ERROR_TYPE_ACTION,
4734 NULL, "no TCP item in"
4736 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4737 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4738 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4739 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4740 return rte_flow_error_set(error, EINVAL,
4741 RTE_FLOW_ERROR_TYPE_ACTION,
4743 "cannot decrease and increase"
4744 " TCP acknowledgment number"
4745 " at the same time");
4751 * Validate the modify-header TTL actions.
4753 * @param[in] action_flags
4754 * Holds the actions detected until now.
4756 * Pointer to the modify action.
4757 * @param[in] item_flags
4758 * Holds the items detected.
4760 * Pointer to error structure.
4763 * 0 on success, a negative errno value otherwise and rte_errno is set.
4766 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4767 const struct rte_flow_action *action,
4768 const uint64_t item_flags,
4769 struct rte_flow_error *error)
4774 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4776 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4777 MLX5_FLOW_LAYER_INNER_L3 :
4778 MLX5_FLOW_LAYER_OUTER_L3;
4779 if (!(item_flags & layer))
4780 return rte_flow_error_set(error, EINVAL,
4781 RTE_FLOW_ERROR_TYPE_ACTION,
4783 "no IP protocol in pattern");
4789 * Validate the generic modify field actions.
4791 * Pointer to the rte_eth_dev structure.
4792 * @param[in] action_flags
4793 * Holds the actions detected until now.
4795 * Pointer to the modify action.
4797 * Pointer to the flow attributes.
4799 * Pointer to error structure.
4802 * Number of header fields to modify (0 or more) on success,
4803 * a negative errno value otherwise and rte_errno is set.
4806 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4807 const uint64_t action_flags,
4808 const struct rte_flow_action *action,
4809 const struct rte_flow_attr *attr,
4810 struct rte_flow_error *error)
4813 struct mlx5_priv *priv = dev->data->dev_private;
4814 struct mlx5_dev_config *config = &priv->config;
4815 const struct rte_flow_action_modify_field *action_modify_field =
4817 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4818 action_modify_field->dst.field,
4820 uint32_t src_width = mlx5_flow_item_field_width(dev,
4821 action_modify_field->src.field,
4822 dst_width, attr, error);
4824 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4828 if (action_modify_field->width == 0)
4829 return rte_flow_error_set(error, EINVAL,
4830 RTE_FLOW_ERROR_TYPE_ACTION, action,
4831 "no bits are requested to be modified");
4832 else if (action_modify_field->width > dst_width ||
4833 action_modify_field->width > src_width)
4834 return rte_flow_error_set(error, EINVAL,
4835 RTE_FLOW_ERROR_TYPE_ACTION, action,
4836 "cannot modify more bits than"
4837 " the width of a field");
4838 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4839 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4840 if ((action_modify_field->dst.offset +
4841 action_modify_field->width > dst_width) ||
4842 (action_modify_field->dst.offset % 32))
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "destination offset is too big"
4846 " or not aligned to 4 bytes");
4847 if (action_modify_field->dst.level &&
4848 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4849 return rte_flow_error_set(error, ENOTSUP,
4850 RTE_FLOW_ERROR_TYPE_ACTION, action,
4851 "inner header fields modification"
4852 " is not supported");
4854 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4855 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4856 if (!attr->transfer && !attr->group)
4857 return rte_flow_error_set(error, ENOTSUP,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "modify field action is not"
4860 " supported for group 0");
4861 if ((action_modify_field->src.offset +
4862 action_modify_field->width > src_width) ||
4863 (action_modify_field->src.offset % 32))
4864 return rte_flow_error_set(error, EINVAL,
4865 RTE_FLOW_ERROR_TYPE_ACTION, action,
4866 "source offset is too big"
4867 " or not aligned to 4 bytes");
4868 if (action_modify_field->src.level &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4870 return rte_flow_error_set(error, ENOTSUP,
4871 RTE_FLOW_ERROR_TYPE_ACTION, action,
4872 "inner header fields modification"
4873 " is not supported");
4875 if ((action_modify_field->dst.field ==
4876 action_modify_field->src.field) &&
4877 (action_modify_field->dst.level ==
4878 action_modify_field->src.level))
4879 return rte_flow_error_set(error, EINVAL,
4880 RTE_FLOW_ERROR_TYPE_ACTION, action,
4881 "source and destination fields"
4882 " cannot be the same");
4883 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4884 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4885 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4886 return rte_flow_error_set(error, EINVAL,
4887 RTE_FLOW_ERROR_TYPE_ACTION, action,
4888 "mark, immediate value or a pointer to it"
4889 " cannot be used as a destination");
4890 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4891 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4892 return rte_flow_error_set(error, ENOTSUP,
4893 RTE_FLOW_ERROR_TYPE_ACTION, action,
4894 "modifications of an arbitrary"
4895 " place in a packet is not supported");
4896 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4897 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4898 return rte_flow_error_set(error, ENOTSUP,
4899 RTE_FLOW_ERROR_TYPE_ACTION, action,
4900 "modifications of the 802.1Q Tag"
4901 " Identifier is not supported");
4902 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4903 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4904 return rte_flow_error_set(error, ENOTSUP,
4905 RTE_FLOW_ERROR_TYPE_ACTION, action,
4906 "modifications of the VXLAN Network"
4907 " Identifier is not supported");
4908 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4909 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4910 return rte_flow_error_set(error, ENOTSUP,
4911 RTE_FLOW_ERROR_TYPE_ACTION, action,
4912 "modifications of the GENEVE Network"
4913 " Identifier is not supported");
4914 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4915 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4916 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4917 !mlx5_flow_ext_mreg_supported(dev))
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "cannot modify mark in legacy mode"
4921 " or without extensive registers");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4924 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4925 !mlx5_flow_ext_mreg_supported(dev))
4926 return rte_flow_error_set(error, ENOTSUP,
4927 RTE_FLOW_ERROR_TYPE_ACTION, action,
4928 "cannot modify meta without"
4929 " extensive registers support");
4930 ret = flow_dv_get_metadata_reg(dev, attr, error);
4931 if (ret < 0 || ret == REG_NON)
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify meta without"
4935 " extensive registers available");
4937 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4938 return rte_flow_error_set(error, ENOTSUP,
4939 RTE_FLOW_ERROR_TYPE_ACTION, action,
4940 "add and sub operations"
4941 " are not supported");
4942 return (action_modify_field->width / 32) +
4943 !!(action_modify_field->width % 32);
4947 * Validate jump action.
4950 * Pointer to the jump action.
4951 * @param[in] action_flags
4952 * Holds the actions detected until now.
4953 * @param[in] attributes
4954 * Pointer to flow attributes
4955 * @param[in] external
4956 * Action belongs to flow rule created by request external to PMD.
4958 * Pointer to error structure.
4961 * 0 on success, a negative errno value otherwise and rte_errno is set.
4964 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4965 const struct mlx5_flow_tunnel *tunnel,
4966 const struct rte_flow_action *action,
4967 uint64_t action_flags,
4968 const struct rte_flow_attr *attributes,
4969 bool external, struct rte_flow_error *error)
4971 uint32_t target_group, table = 0;
4973 struct flow_grp_info grp_info = {
4974 .external = !!external,
4975 .transfer = !!attributes->transfer,
4979 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4980 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4981 return rte_flow_error_set(error, EINVAL,
4982 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4983 "can't have 2 fate actions in"
4986 return rte_flow_error_set(error, EINVAL,
4987 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4988 NULL, "action configuration not set");
4990 ((const struct rte_flow_action_jump *)action->conf)->group;
4991 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4995 if (attributes->group == target_group &&
4996 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4997 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4998 return rte_flow_error_set(error, EINVAL,
4999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5000 "target group must be other than"
5001 " the current flow group");
5003 return rte_flow_error_set(error, EINVAL,
5004 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5005 NULL, "root table shouldn't be destination");
5010 * Validate action PORT_ID / REPRESENTED_PORT.
5013 * Pointer to rte_eth_dev structure.
5014 * @param[in] action_flags
5015 * Bit-fields that holds the actions detected until now.
5017 * PORT_ID / REPRESENTED_PORT action structure.
5019 * Attributes of flow that includes this action.
5021 * Pointer to error structure.
5024 * 0 on success, a negative errno value otherwise and rte_errno is set.
5027 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5028 uint64_t action_flags,
5029 const struct rte_flow_action *action,
5030 const struct rte_flow_attr *attr,
5031 struct rte_flow_error *error)
5033 const struct rte_flow_action_port_id *port_id;
5034 const struct rte_flow_action_ethdev *ethdev;
5035 struct mlx5_priv *act_priv;
5036 struct mlx5_priv *dev_priv;
5039 if (!attr->transfer)
5040 return rte_flow_error_set(error, ENOTSUP,
5041 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5043 "port action is valid in transfer"
5045 if (!action || !action->conf)
5046 return rte_flow_error_set(error, ENOTSUP,
5047 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5049 "port action parameters must be"
5051 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5052 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5053 return rte_flow_error_set(error, EINVAL,
5054 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5055 "can have only one fate actions in"
5057 dev_priv = mlx5_dev_to_eswitch_info(dev);
5059 return rte_flow_error_set(error, rte_errno,
5060 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5062 "failed to obtain E-Switch info");
5063 switch (action->type) {
5064 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5065 port_id = action->conf;
5066 port = port_id->original ? dev->data->port_id : port_id->id;
5068 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5069 ethdev = action->conf;
5070 port = ethdev->port_id;
5074 return rte_flow_error_set
5076 RTE_FLOW_ERROR_TYPE_ACTION, action,
5077 "unknown E-Switch action");
5079 act_priv = mlx5_port_to_eswitch_info(port, false);
5081 return rte_flow_error_set
5083 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5084 "failed to obtain E-Switch port id for port");
5085 if (act_priv->domain_id != dev_priv->domain_id)
5086 return rte_flow_error_set
5088 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5089 "port does not belong to"
5090 " E-Switch being configured");
5095 * Get the maximum number of modify header actions.
5098 * Pointer to rte_eth_dev structure.
5100 * Whether action is on root table.
5103 * Max number of modify header actions device can support.
5105 static inline unsigned int
5106 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5110 * There's no way to directly query the max capacity from FW.
5111 * The maximal value on root table should be assumed to be supported.
5114 return MLX5_MAX_MODIFY_NUM;
5116 return MLX5_ROOT_TBL_MODIFY_NUM;
5120 * Validate the meter action.
5123 * Pointer to rte_eth_dev structure.
5124 * @param[in] action_flags
5125 * Bit-fields that holds the actions detected until now.
5126 * @param[in] item_flags
5127 * Holds the items detected.
5129 * Pointer to the meter action.
5131 * Attributes of flow that includes this action.
5132 * @param[in] port_id_item
5133 * Pointer to item indicating port id.
5135 * Pointer to error structure.
5138 * 0 on success, a negative errno value otherwise and rte_errno is set.
5141 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5142 uint64_t action_flags, uint64_t item_flags,
5143 const struct rte_flow_action *action,
5144 const struct rte_flow_attr *attr,
5145 const struct rte_flow_item *port_id_item,
5147 struct rte_flow_error *error)
5149 struct mlx5_priv *priv = dev->data->dev_private;
5150 const struct rte_flow_action_meter *am = action->conf;
5151 struct mlx5_flow_meter_info *fm;
5152 struct mlx5_flow_meter_policy *mtr_policy;
5153 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5156 return rte_flow_error_set(error, EINVAL,
5157 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5158 "meter action conf is NULL");
5160 if (action_flags & MLX5_FLOW_ACTION_METER)
5161 return rte_flow_error_set(error, ENOTSUP,
5162 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5163 "meter chaining not support");
5164 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5165 return rte_flow_error_set(error, ENOTSUP,
5166 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5167 "meter with jump not support");
5169 return rte_flow_error_set(error, ENOTSUP,
5170 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5172 "meter action not supported");
5173 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5175 return rte_flow_error_set(error, EINVAL,
5176 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5178 /* aso meter can always be shared by different domains */
5179 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5180 !(fm->transfer == attr->transfer ||
5181 (!fm->ingress && !attr->ingress && attr->egress) ||
5182 (!fm->egress && !attr->egress && attr->ingress)))
5183 return rte_flow_error_set(error, EINVAL,
5184 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5185 "Flow attributes domain are either invalid "
5186 "or have a domain conflict with current "
5187 "meter attributes");
5188 if (fm->def_policy) {
5189 if (!((attr->transfer &&
5190 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5192 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5194 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5195 return rte_flow_error_set(error, EINVAL,
5196 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5197 "Flow attributes domain "
5198 "have a conflict with current "
5199 "meter domain attributes");
5202 mtr_policy = mlx5_flow_meter_policy_find(dev,
5203 fm->policy_id, NULL);
5205 return rte_flow_error_set(error, EINVAL,
5206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5207 "Invalid policy id for meter ");
5208 if (!((attr->transfer && mtr_policy->transfer) ||
5209 (attr->egress && mtr_policy->egress) ||
5210 (attr->ingress && mtr_policy->ingress)))
5211 return rte_flow_error_set(error, EINVAL,
5212 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5213 "Flow attributes domain "
5214 "have a conflict with current "
5215 "meter domain attributes");
5216 if (attr->transfer && mtr_policy->dev) {
5218 * When policy has fate action of port_id,
5219 * the flow should have the same src port as policy.
5221 struct mlx5_priv *policy_port_priv =
5222 mtr_policy->dev->data->dev_private;
5223 int32_t flow_src_port = priv->representor_id;
5226 const struct rte_flow_item_port_id *spec =
5228 struct mlx5_priv *port_priv =
5229 mlx5_port_to_eswitch_info(spec->id,
5232 return rte_flow_error_set(error,
5234 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5236 "Failed to get port info.");
5237 flow_src_port = port_priv->representor_id;
5239 if (flow_src_port != policy_port_priv->representor_id)
5240 return rte_flow_error_set(error,
5242 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5244 "Flow and meter policy "
5245 "have different src port.");
5246 } else if (mtr_policy->is_rss) {
5247 struct mlx5_flow_meter_policy *fp;
5248 struct mlx5_meter_policy_action_container *acg;
5249 struct mlx5_meter_policy_action_container *acy;
5250 const struct rte_flow_action *rss_act;
5253 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5256 return rte_flow_error_set(error, EINVAL,
5257 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5258 "Unable to get the final "
5259 "policy in the hierarchy");
5260 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5261 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5262 MLX5_ASSERT(acg->fate_action ==
5263 MLX5_FLOW_FATE_SHARED_RSS ||
5265 MLX5_FLOW_FATE_SHARED_RSS);
5266 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5270 ret = mlx5_flow_validate_action_rss(rss_act,
5271 action_flags, dev, attr,
5276 *def_policy = false;
5282 * Validate the age action.
5284 * @param[in] action_flags
5285 * Holds the actions detected until now.
5287 * Pointer to the age action.
5289 * Pointer to the Ethernet device structure.
5291 * Pointer to error structure.
5294 * 0 on success, a negative errno value otherwise and rte_errno is set.
5297 flow_dv_validate_action_age(uint64_t action_flags,
5298 const struct rte_flow_action *action,
5299 struct rte_eth_dev *dev,
5300 struct rte_flow_error *error)
5302 struct mlx5_priv *priv = dev->data->dev_private;
5303 const struct rte_flow_action_age *age = action->conf;
5305 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5306 !priv->sh->aso_age_mng))
5307 return rte_flow_error_set(error, ENOTSUP,
5308 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5310 "age action not supported");
5311 if (!(action->conf))
5312 return rte_flow_error_set(error, EINVAL,
5313 RTE_FLOW_ERROR_TYPE_ACTION, action,
5314 "configuration cannot be null");
5315 if (!(age->timeout))
5316 return rte_flow_error_set(error, EINVAL,
5317 RTE_FLOW_ERROR_TYPE_ACTION, action,
5318 "invalid timeout value 0");
5319 if (action_flags & MLX5_FLOW_ACTION_AGE)
5320 return rte_flow_error_set(error, EINVAL,
5321 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5322 "duplicate age actions set");
5327 * Validate the modify-header IPv4 DSCP actions.
5329 * @param[in] action_flags
5330 * Holds the actions detected until now.
5332 * Pointer to the modify action.
5333 * @param[in] item_flags
5334 * Holds the items detected.
5336 * Pointer to error structure.
5339 * 0 on success, a negative errno value otherwise and rte_errno is set.
5342 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5343 const struct rte_flow_action *action,
5344 const uint64_t item_flags,
5345 struct rte_flow_error *error)
5349 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5351 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5352 return rte_flow_error_set(error, EINVAL,
5353 RTE_FLOW_ERROR_TYPE_ACTION,
5355 "no ipv4 item in pattern");
5361 * Validate the modify-header IPv6 DSCP actions.
5363 * @param[in] action_flags
5364 * Holds the actions detected until now.
5366 * Pointer to the modify action.
5367 * @param[in] item_flags
5368 * Holds the items detected.
5370 * Pointer to error structure.
5373 * 0 on success, a negative errno value otherwise and rte_errno is set.
5376 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5377 const struct rte_flow_action *action,
5378 const uint64_t item_flags,
5379 struct rte_flow_error *error)
5383 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5385 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5386 return rte_flow_error_set(error, EINVAL,
5387 RTE_FLOW_ERROR_TYPE_ACTION,
5389 "no ipv6 item in pattern");
5395 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5396 struct mlx5_list_entry *entry, void *cb_ctx)
5398 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5399 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5400 struct mlx5_flow_dv_modify_hdr_resource *resource =
5401 container_of(entry, typeof(*resource), entry);
5402 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5404 key_len += ref->actions_num * sizeof(ref->actions[0]);
5405 return ref->actions_num != resource->actions_num ||
5406 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5409 static struct mlx5_indexed_pool *
5410 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5412 struct mlx5_indexed_pool *ipool = __atomic_load_n
5413 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5416 struct mlx5_indexed_pool *expected = NULL;
5417 struct mlx5_indexed_pool_config cfg =
5418 (struct mlx5_indexed_pool_config) {
5419 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5421 sizeof(struct mlx5_modification_cmd),
5426 .release_mem_en = !!sh->reclaim_mode,
5427 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5428 .malloc = mlx5_malloc,
5430 .type = "mlx5_modify_action_resource",
5433 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5434 ipool = mlx5_ipool_create(&cfg);
5437 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5438 &expected, ipool, false,
5440 __ATOMIC_SEQ_CST)) {
5441 mlx5_ipool_destroy(ipool);
5442 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5449 struct mlx5_list_entry *
5450 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5452 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5453 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5454 struct mlx5dv_dr_domain *ns;
5455 struct mlx5_flow_dv_modify_hdr_resource *entry;
5456 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5457 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5458 ref->actions_num - 1);
5460 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5461 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5464 if (unlikely(!ipool)) {
5465 rte_flow_error_set(ctx->error, ENOMEM,
5466 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5467 NULL, "cannot allocate modify ipool");
5470 entry = mlx5_ipool_zmalloc(ipool, &idx);
5472 rte_flow_error_set(ctx->error, ENOMEM,
5473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5474 "cannot allocate resource memory");
5477 rte_memcpy(&entry->ft_type,
5478 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5479 key_len + data_len);
5480 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5481 ns = sh->fdb_domain;
5482 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5486 ret = mlx5_flow_os_create_flow_action_modify_header
5487 (sh->cdev->ctx, ns, entry,
5488 data_len, &entry->action);
5490 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5491 rte_flow_error_set(ctx->error, ENOMEM,
5492 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5493 NULL, "cannot create modification action");
5497 return &entry->entry;
5500 struct mlx5_list_entry *
5501 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5504 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5505 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5506 struct mlx5_flow_dv_modify_hdr_resource *entry;
5507 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5508 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5511 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5514 rte_flow_error_set(ctx->error, ENOMEM,
5515 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5516 "cannot allocate resource memory");
5519 memcpy(entry, oentry, sizeof(*entry) + data_len);
5521 return &entry->entry;
5525 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5527 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5528 struct mlx5_flow_dv_modify_hdr_resource *res =
5529 container_of(entry, typeof(*res), entry);
5531 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5535 * Validate the sample action.
5537 * @param[in, out] action_flags
5538 * Holds the actions detected until now.
5540 * Pointer to the sample action.
5542 * Pointer to the Ethernet device structure.
5544 * Attributes of flow that includes this action.
5545 * @param[in] item_flags
5546 * Holds the items detected.
5548 * Pointer to the RSS action.
5549 * @param[out] sample_rss
5550 * Pointer to the RSS action in sample action list.
5552 * Pointer to the COUNT action in sample action list.
5553 * @param[out] fdb_mirror_limit
5554 * Pointer to the FDB mirror limitation flag.
5556 * Pointer to error structure.
5559 * 0 on success, a negative errno value otherwise and rte_errno is set.
5562 flow_dv_validate_action_sample(uint64_t *action_flags,
5563 const struct rte_flow_action *action,
5564 struct rte_eth_dev *dev,
5565 const struct rte_flow_attr *attr,
5566 uint64_t item_flags,
5567 const struct rte_flow_action_rss *rss,
5568 const struct rte_flow_action_rss **sample_rss,
5569 const struct rte_flow_action_count **count,
5570 int *fdb_mirror_limit,
5571 struct rte_flow_error *error)
5573 struct mlx5_priv *priv = dev->data->dev_private;
5574 struct mlx5_dev_config *dev_conf = &priv->config;
5575 const struct rte_flow_action_sample *sample = action->conf;
5576 const struct rte_flow_action *act;
5577 uint64_t sub_action_flags = 0;
5578 uint16_t queue_index = 0xFFFF;
5583 return rte_flow_error_set(error, EINVAL,
5584 RTE_FLOW_ERROR_TYPE_ACTION, action,
5585 "configuration cannot be NULL");
5586 if (sample->ratio == 0)
5587 return rte_flow_error_set(error, EINVAL,
5588 RTE_FLOW_ERROR_TYPE_ACTION, action,
5589 "ratio value starts from 1");
5590 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5591 return rte_flow_error_set(error, ENOTSUP,
5592 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5594 "sample action not supported");
5595 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5596 return rte_flow_error_set(error, EINVAL,
5597 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5598 "Multiple sample actions not "
5600 if (*action_flags & MLX5_FLOW_ACTION_METER)
5601 return rte_flow_error_set(error, EINVAL,
5602 RTE_FLOW_ERROR_TYPE_ACTION, action,
5603 "wrong action order, meter should "
5604 "be after sample action");
5605 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5606 return rte_flow_error_set(error, EINVAL,
5607 RTE_FLOW_ERROR_TYPE_ACTION, action,
5608 "wrong action order, jump should "
5609 "be after sample action");
5610 if (*action_flags & MLX5_FLOW_ACTION_CT)
5611 return rte_flow_error_set(error, EINVAL,
5612 RTE_FLOW_ERROR_TYPE_ACTION, action,
5613 "Sample after CT not supported");
5614 act = sample->actions;
5615 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5616 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5617 return rte_flow_error_set(error, ENOTSUP,
5618 RTE_FLOW_ERROR_TYPE_ACTION,
5619 act, "too many actions");
5620 switch (act->type) {
5621 case RTE_FLOW_ACTION_TYPE_QUEUE:
5622 ret = mlx5_flow_validate_action_queue(act,
5628 queue_index = ((const struct rte_flow_action_queue *)
5629 (act->conf))->index;
5630 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5633 case RTE_FLOW_ACTION_TYPE_RSS:
5634 *sample_rss = act->conf;
5635 ret = mlx5_flow_validate_action_rss(act,
5642 if (rss && *sample_rss &&
5643 ((*sample_rss)->level != rss->level ||
5644 (*sample_rss)->types != rss->types))
5645 return rte_flow_error_set(error, ENOTSUP,
5646 RTE_FLOW_ERROR_TYPE_ACTION,
5648 "Can't use the different RSS types "
5649 "or level in the same flow");
5650 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5651 queue_index = (*sample_rss)->queue[0];
5652 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5655 case RTE_FLOW_ACTION_TYPE_MARK:
5656 ret = flow_dv_validate_action_mark(dev, act,
5661 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5662 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5663 MLX5_FLOW_ACTION_MARK_EXT;
5665 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5668 case RTE_FLOW_ACTION_TYPE_COUNT:
5669 ret = flow_dv_validate_action_count
5670 (dev, false, *action_flags | sub_action_flags,
5675 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5676 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5679 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5680 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5681 ret = flow_dv_validate_action_port_id(dev,
5688 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5691 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5692 ret = flow_dv_validate_action_raw_encap_decap
5693 (dev, NULL, act->conf, attr, &sub_action_flags,
5694 &actions_n, action, item_flags, error);
5699 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5700 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5701 ret = flow_dv_validate_action_l2_encap(dev,
5707 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5711 return rte_flow_error_set(error, ENOTSUP,
5712 RTE_FLOW_ERROR_TYPE_ACTION,
5714 "Doesn't support optional "
5718 if (attr->ingress && !attr->transfer) {
5719 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5720 MLX5_FLOW_ACTION_RSS)))
5721 return rte_flow_error_set(error, EINVAL,
5722 RTE_FLOW_ERROR_TYPE_ACTION,
5724 "Ingress must has a dest "
5725 "QUEUE for Sample");
5726 } else if (attr->egress && !attr->transfer) {
5727 return rte_flow_error_set(error, ENOTSUP,
5728 RTE_FLOW_ERROR_TYPE_ACTION,
5730 "Sample Only support Ingress "
5732 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5733 MLX5_ASSERT(attr->transfer);
5734 if (sample->ratio > 1)
5735 return rte_flow_error_set(error, ENOTSUP,
5736 RTE_FLOW_ERROR_TYPE_ACTION,
5738 "E-Switch doesn't support "
5739 "any optional action "
5741 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5742 return rte_flow_error_set(error, ENOTSUP,
5743 RTE_FLOW_ERROR_TYPE_ACTION,
5745 "unsupported action QUEUE");
5746 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5747 return rte_flow_error_set(error, ENOTSUP,
5748 RTE_FLOW_ERROR_TYPE_ACTION,
5750 "unsupported action QUEUE");
5751 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5752 return rte_flow_error_set(error, EINVAL,
5753 RTE_FLOW_ERROR_TYPE_ACTION,
5755 "E-Switch must has a dest "
5756 "port for mirroring");
5757 if (!priv->sh->cdev->config.hca_attr.reg_c_preserve &&
5758 priv->representor_id != UINT16_MAX)
5759 *fdb_mirror_limit = 1;
5761 /* Continue validation for Xcap actions.*/
5762 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5763 (queue_index == 0xFFFF ||
5764 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5765 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5766 MLX5_FLOW_XCAP_ACTIONS)
5767 return rte_flow_error_set(error, ENOTSUP,
5768 RTE_FLOW_ERROR_TYPE_ACTION,
5769 NULL, "encap and decap "
5770 "combination aren't "
5772 if (!attr->transfer && attr->ingress && (sub_action_flags &
5773 MLX5_FLOW_ACTION_ENCAP))
5774 return rte_flow_error_set(error, ENOTSUP,
5775 RTE_FLOW_ERROR_TYPE_ACTION,
5776 NULL, "encap is not supported"
5777 " for ingress traffic");
5783 * Find existing modify-header resource or create and register a new one.
5785 * @param dev[in, out]
5786 * Pointer to rte_eth_dev structure.
5787 * @param[in, out] resource
5788 * Pointer to modify-header resource.
5789 * @parm[in, out] dev_flow
5790 * Pointer to the dev_flow.
5792 * pointer to error structure.
5795 * 0 on success otherwise -errno and errno is set.
5798 flow_dv_modify_hdr_resource_register
5799 (struct rte_eth_dev *dev,
5800 struct mlx5_flow_dv_modify_hdr_resource *resource,
5801 struct mlx5_flow *dev_flow,
5802 struct rte_flow_error *error)
5804 struct mlx5_priv *priv = dev->data->dev_private;
5805 struct mlx5_dev_ctx_shared *sh = priv->sh;
5806 uint32_t key_len = sizeof(*resource) -
5807 offsetof(typeof(*resource), ft_type) +
5808 resource->actions_num * sizeof(resource->actions[0]);
5809 struct mlx5_list_entry *entry;
5810 struct mlx5_flow_cb_ctx ctx = {
5814 struct mlx5_hlist *modify_cmds;
5817 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5819 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5821 flow_dv_modify_create_cb,
5822 flow_dv_modify_match_cb,
5823 flow_dv_modify_remove_cb,
5824 flow_dv_modify_clone_cb,
5825 flow_dv_modify_clone_free_cb);
5826 if (unlikely(!modify_cmds))
5828 resource->root = !dev_flow->dv.group;
5829 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5831 return rte_flow_error_set(error, EOVERFLOW,
5832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5833 "too many modify header items");
5834 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5835 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5838 resource = container_of(entry, typeof(*resource), entry);
5839 dev_flow->handle->dvh.modify_hdr = resource;
5844 * Get DV flow counter by index.
5847 * Pointer to the Ethernet device structure.
5849 * mlx5 flow counter index in the container.
5851 * mlx5 flow counter pool in the container.
5854 * Pointer to the counter, NULL otherwise.
5856 static struct mlx5_flow_counter *
5857 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5859 struct mlx5_flow_counter_pool **ppool)
5861 struct mlx5_priv *priv = dev->data->dev_private;
5862 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5863 struct mlx5_flow_counter_pool *pool;
5865 /* Decrease to original index and clear shared bit. */
5866 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5867 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5868 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5872 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5876 * Check the devx counter belongs to the pool.
5879 * Pointer to the counter pool.
5881 * The counter devx ID.
5884 * True if counter belongs to the pool, false otherwise.
5887 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5889 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5890 MLX5_COUNTERS_PER_POOL;
5892 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5898 * Get a pool by devx counter ID.
5901 * Pointer to the counter management.
5903 * The counter devx ID.
5906 * The counter pool pointer if exists, NULL otherwise,
5908 static struct mlx5_flow_counter_pool *
5909 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5912 struct mlx5_flow_counter_pool *pool = NULL;
5914 rte_spinlock_lock(&cmng->pool_update_sl);
5915 /* Check last used pool. */
5916 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5917 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5918 pool = cmng->pools[cmng->last_pool_idx];
5921 /* ID out of range means no suitable pool in the container. */
5922 if (id > cmng->max_id || id < cmng->min_id)
5925 * Find the pool from the end of the container, since mostly counter
5926 * ID is sequence increasing, and the last pool should be the needed
5931 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5933 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5939 rte_spinlock_unlock(&cmng->pool_update_sl);
5944 * Resize a counter container.
5947 * Pointer to the Ethernet device structure.
5950 * 0 on success, otherwise negative errno value and rte_errno is set.
5953 flow_dv_container_resize(struct rte_eth_dev *dev)
5955 struct mlx5_priv *priv = dev->data->dev_private;
5956 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5957 void *old_pools = cmng->pools;
5958 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5959 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5960 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5967 memcpy(pools, old_pools, cmng->n *
5968 sizeof(struct mlx5_flow_counter_pool *));
5970 cmng->pools = pools;
5972 mlx5_free(old_pools);
5977 * Query a devx flow counter.
5980 * Pointer to the Ethernet device structure.
5981 * @param[in] counter
5982 * Index to the flow counter.
5984 * The statistics value of packets.
5986 * The statistics value of bytes.
5989 * 0 on success, otherwise a negative errno value and rte_errno is set.
5992 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5995 struct mlx5_priv *priv = dev->data->dev_private;
5996 struct mlx5_flow_counter_pool *pool = NULL;
5997 struct mlx5_flow_counter *cnt;
6000 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6002 if (priv->sh->cmng.counter_fallback)
6003 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6004 0, pkts, bytes, 0, NULL, NULL, 0);
6005 rte_spinlock_lock(&pool->sl);
6010 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6011 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6012 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6014 rte_spinlock_unlock(&pool->sl);
6019 * Create and initialize a new counter pool.
6022 * Pointer to the Ethernet device structure.
6024 * The devX counter handle.
6026 * Whether the pool is for counter that was allocated for aging.
6027 * @param[in/out] cont_cur
6028 * Pointer to the container pointer, it will be update in pool resize.
6031 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6033 static struct mlx5_flow_counter_pool *
6034 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6037 struct mlx5_priv *priv = dev->data->dev_private;
6038 struct mlx5_flow_counter_pool *pool;
6039 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6040 bool fallback = priv->sh->cmng.counter_fallback;
6041 uint32_t size = sizeof(*pool);
6043 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6044 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6045 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6051 pool->is_aged = !!age;
6052 pool->query_gen = 0;
6053 pool->min_dcs = dcs;
6054 rte_spinlock_init(&pool->sl);
6055 rte_spinlock_init(&pool->csl);
6056 TAILQ_INIT(&pool->counters[0]);
6057 TAILQ_INIT(&pool->counters[1]);
6058 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6059 rte_spinlock_lock(&cmng->pool_update_sl);
6060 pool->index = cmng->n_valid;
6061 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6063 rte_spinlock_unlock(&cmng->pool_update_sl);
6066 cmng->pools[pool->index] = pool;
6068 if (unlikely(fallback)) {
6069 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6071 if (base < cmng->min_id)
6072 cmng->min_id = base;
6073 if (base > cmng->max_id)
6074 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6075 cmng->last_pool_idx = pool->index;
6077 rte_spinlock_unlock(&cmng->pool_update_sl);
6082 * Prepare a new counter and/or a new counter pool.
6085 * Pointer to the Ethernet device structure.
6086 * @param[out] cnt_free
6087 * Where to put the pointer of a new counter.
6089 * Whether the pool is for counter that was allocated for aging.
6092 * The counter pool pointer and @p cnt_free is set on success,
6093 * NULL otherwise and rte_errno is set.
6095 static struct mlx5_flow_counter_pool *
6096 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6097 struct mlx5_flow_counter **cnt_free,
6100 struct mlx5_priv *priv = dev->data->dev_private;
6101 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6102 struct mlx5_flow_counter_pool *pool;
6103 struct mlx5_counters tmp_tq;
6104 struct mlx5_devx_obj *dcs = NULL;
6105 struct mlx5_flow_counter *cnt;
6106 enum mlx5_counter_type cnt_type =
6107 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6108 bool fallback = priv->sh->cmng.counter_fallback;
6112 /* bulk_bitmap must be 0 for single counter allocation. */
6113 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6116 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6118 pool = flow_dv_pool_create(dev, dcs, age);
6120 mlx5_devx_cmd_destroy(dcs);
6124 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6125 cnt = MLX5_POOL_GET_CNT(pool, i);
6127 cnt->dcs_when_free = dcs;
6131 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6133 rte_errno = ENODATA;
6136 pool = flow_dv_pool_create(dev, dcs, age);
6138 mlx5_devx_cmd_destroy(dcs);
6141 TAILQ_INIT(&tmp_tq);
6142 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6143 cnt = MLX5_POOL_GET_CNT(pool, i);
6145 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6147 rte_spinlock_lock(&cmng->csl[cnt_type]);
6148 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6149 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6150 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6151 (*cnt_free)->pool = pool;
6156 * Allocate a flow counter.
6159 * Pointer to the Ethernet device structure.
6161 * Whether the counter was allocated for aging.
6164 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6167 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6169 struct mlx5_priv *priv = dev->data->dev_private;
6170 struct mlx5_flow_counter_pool *pool = NULL;
6171 struct mlx5_flow_counter *cnt_free = NULL;
6172 bool fallback = priv->sh->cmng.counter_fallback;
6173 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6174 enum mlx5_counter_type cnt_type =
6175 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6178 if (!priv->sh->devx) {
6179 rte_errno = ENOTSUP;
6182 /* Get free counters from container. */
6183 rte_spinlock_lock(&cmng->csl[cnt_type]);
6184 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6186 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6187 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6188 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6190 pool = cnt_free->pool;
6192 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6193 /* Create a DV counter action only in the first time usage. */
6194 if (!cnt_free->action) {
6196 struct mlx5_devx_obj *dcs;
6200 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6201 dcs = pool->min_dcs;
6204 dcs = cnt_free->dcs_when_free;
6206 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6213 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6214 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6215 /* Update the counter reset values. */
6216 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6219 if (!fallback && !priv->sh->cmng.query_thread_on)
6220 /* Start the asynchronous batch query by the host thread. */
6221 mlx5_set_query_alarm(priv->sh);
6223 * When the count action isn't shared (by ID), shared_info field is
6224 * used for indirect action API's refcnt.
6225 * When the counter action is not shared neither by ID nor by indirect
6226 * action API, shared info must be 1.
6228 cnt_free->shared_info.refcnt = 1;
6232 cnt_free->pool = pool;
6234 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6235 rte_spinlock_lock(&cmng->csl[cnt_type]);
6236 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6237 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6243 * Get age param from counter index.
6246 * Pointer to the Ethernet device structure.
6247 * @param[in] counter
6248 * Index to the counter handler.
6251 * The aging parameter specified for the counter index.
6253 static struct mlx5_age_param*
6254 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6257 struct mlx5_flow_counter *cnt;
6258 struct mlx5_flow_counter_pool *pool = NULL;
6260 flow_dv_counter_get_by_idx(dev, counter, &pool);
6261 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6262 cnt = MLX5_POOL_GET_CNT(pool, counter);
6263 return MLX5_CNT_TO_AGE(cnt);
6267 * Remove a flow counter from aged counter list.
6270 * Pointer to the Ethernet device structure.
6271 * @param[in] counter
6272 * Index to the counter handler.
6274 * Pointer to the counter handler.
6277 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6278 uint32_t counter, struct mlx5_flow_counter *cnt)
6280 struct mlx5_age_info *age_info;
6281 struct mlx5_age_param *age_param;
6282 struct mlx5_priv *priv = dev->data->dev_private;
6283 uint16_t expected = AGE_CANDIDATE;
6285 age_info = GET_PORT_AGE_INFO(priv);
6286 age_param = flow_dv_counter_idx_get_age(dev, counter);
6287 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6288 AGE_FREE, false, __ATOMIC_RELAXED,
6289 __ATOMIC_RELAXED)) {
6291 * We need the lock even it is age timeout,
6292 * since counter may still in process.
6294 rte_spinlock_lock(&age_info->aged_sl);
6295 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6296 rte_spinlock_unlock(&age_info->aged_sl);
6297 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6302 * Release a flow counter.
6305 * Pointer to the Ethernet device structure.
6306 * @param[in] counter
6307 * Index to the counter handler.
6310 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6312 struct mlx5_priv *priv = dev->data->dev_private;
6313 struct mlx5_flow_counter_pool *pool = NULL;
6314 struct mlx5_flow_counter *cnt;
6315 enum mlx5_counter_type cnt_type;
6319 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6321 if (pool->is_aged) {
6322 flow_dv_counter_remove_from_age(dev, counter, cnt);
6325 * If the counter action is shared by indirect action API,
6326 * the atomic function reduces its references counter.
6327 * If after the reduction the action is still referenced, the
6328 * function returns here and does not release it.
6329 * When the counter action is not shared by
6330 * indirect action API, shared info is 1 before the reduction,
6331 * so this condition is failed and function doesn't return here.
6333 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6339 * Put the counter back to list to be updated in none fallback mode.
6340 * Currently, we are using two list alternately, while one is in query,
6341 * add the freed counter to the other list based on the pool query_gen
6342 * value. After query finishes, add counter the list to the global
6343 * container counter list. The list changes while query starts. In
6344 * this case, lock will not be needed as query callback and release
6345 * function both operate with the different list.
6347 if (!priv->sh->cmng.counter_fallback) {
6348 rte_spinlock_lock(&pool->csl);
6349 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6350 rte_spinlock_unlock(&pool->csl);
6352 cnt->dcs_when_free = cnt->dcs_when_active;
6353 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6354 MLX5_COUNTER_TYPE_ORIGIN;
6355 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6356 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6358 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6363 * Resize a meter id container.
6366 * Pointer to the Ethernet device structure.
6369 * 0 on success, otherwise negative errno value and rte_errno is set.
6372 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6374 struct mlx5_priv *priv = dev->data->dev_private;
6375 struct mlx5_aso_mtr_pools_mng *pools_mng =
6376 &priv->sh->mtrmng->pools_mng;
6377 void *old_pools = pools_mng->pools;
6378 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6379 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6380 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6387 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6392 memcpy(pools, old_pools, pools_mng->n *
6393 sizeof(struct mlx5_aso_mtr_pool *));
6394 pools_mng->n = resize;
6395 pools_mng->pools = pools;
6397 mlx5_free(old_pools);
6402 * Prepare a new meter and/or a new meter pool.
6405 * Pointer to the Ethernet device structure.
6406 * @param[out] mtr_free
6407 * Where to put the pointer of a new meter.g.
6410 * The meter pool pointer and @mtr_free is set on success,
6411 * NULL otherwise and rte_errno is set.
6413 static struct mlx5_aso_mtr_pool *
6414 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6416 struct mlx5_priv *priv = dev->data->dev_private;
6417 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6418 struct mlx5_aso_mtr_pool *pool = NULL;
6419 struct mlx5_devx_obj *dcs = NULL;
6421 uint32_t log_obj_size;
6423 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6424 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6425 priv->sh->cdev->pdn,
6428 rte_errno = ENODATA;
6431 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6434 claim_zero(mlx5_devx_cmd_destroy(dcs));
6437 pool->devx_obj = dcs;
6438 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6439 pool->index = pools_mng->n_valid;
6440 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6442 claim_zero(mlx5_devx_cmd_destroy(dcs));
6443 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6446 pools_mng->pools[pool->index] = pool;
6447 pools_mng->n_valid++;
6448 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6449 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6450 pool->mtrs[i].offset = i;
6451 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6453 pool->mtrs[0].offset = 0;
6454 *mtr_free = &pool->mtrs[0];
6459 * Release a flow meter into pool.
6462 * Pointer to the Ethernet device structure.
6463 * @param[in] mtr_idx
6464 * Index to aso flow meter.
6467 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6469 struct mlx5_priv *priv = dev->data->dev_private;
6470 struct mlx5_aso_mtr_pools_mng *pools_mng =
6471 &priv->sh->mtrmng->pools_mng;
6472 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6474 MLX5_ASSERT(aso_mtr);
6475 rte_spinlock_lock(&pools_mng->mtrsl);
6476 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6477 aso_mtr->state = ASO_METER_FREE;
6478 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6479 rte_spinlock_unlock(&pools_mng->mtrsl);
6483 * Allocate a aso flow meter.
6486 * Pointer to the Ethernet device structure.
6489 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6492 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6494 struct mlx5_priv *priv = dev->data->dev_private;
6495 struct mlx5_aso_mtr *mtr_free = NULL;
6496 struct mlx5_aso_mtr_pools_mng *pools_mng =
6497 &priv->sh->mtrmng->pools_mng;
6498 struct mlx5_aso_mtr_pool *pool;
6499 uint32_t mtr_idx = 0;
6501 if (!priv->sh->devx) {
6502 rte_errno = ENOTSUP;
6505 /* Allocate the flow meter memory. */
6506 /* Get free meters from management. */
6507 rte_spinlock_lock(&pools_mng->mtrsl);
6508 mtr_free = LIST_FIRST(&pools_mng->meters);
6510 LIST_REMOVE(mtr_free, next);
6511 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6512 rte_spinlock_unlock(&pools_mng->mtrsl);
6515 mtr_free->state = ASO_METER_WAIT;
6516 rte_spinlock_unlock(&pools_mng->mtrsl);
6517 pool = container_of(mtr_free,
6518 struct mlx5_aso_mtr_pool,
6519 mtrs[mtr_free->offset]);
6520 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6521 if (!mtr_free->fm.meter_action) {
6522 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6523 struct rte_flow_error error;
6526 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6527 mtr_free->fm.meter_action =
6528 mlx5_glue->dv_create_flow_action_aso
6529 (priv->sh->rx_domain,
6530 pool->devx_obj->obj,
6532 (1 << MLX5_FLOW_COLOR_GREEN),
6534 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6535 if (!mtr_free->fm.meter_action) {
6536 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6544 * Verify the @p attributes will be correctly understood by the NIC and store
6545 * them in the @p flow if everything is correct.
6548 * Pointer to dev struct.
6549 * @param[in] attributes
6550 * Pointer to flow attributes
6551 * @param[in] external
6552 * This flow rule is created by request external to PMD.
6554 * Pointer to error structure.
6557 * - 0 on success and non root table.
6558 * - 1 on success and root table.
6559 * - a negative errno value otherwise and rte_errno is set.
6562 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6563 const struct mlx5_flow_tunnel *tunnel,
6564 const struct rte_flow_attr *attributes,
6565 const struct flow_grp_info *grp_info,
6566 struct rte_flow_error *error)
6568 struct mlx5_priv *priv = dev->data->dev_private;
6569 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6572 #ifndef HAVE_MLX5DV_DR
6573 RTE_SET_USED(tunnel);
6574 RTE_SET_USED(grp_info);
6575 if (attributes->group)
6576 return rte_flow_error_set(error, ENOTSUP,
6577 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6579 "groups are not supported");
6583 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6588 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6590 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6591 attributes->priority > lowest_priority)
6592 return rte_flow_error_set(error, ENOTSUP,
6593 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6595 "priority out of range");
6596 if (attributes->transfer) {
6597 if (!priv->config.dv_esw_en)
6598 return rte_flow_error_set
6600 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6601 "E-Switch dr is not supported");
6602 if (!(priv->representor || priv->master))
6603 return rte_flow_error_set
6604 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6605 NULL, "E-Switch configuration can only be"
6606 " done by a master or a representor device");
6607 if (attributes->egress)
6608 return rte_flow_error_set
6610 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6611 "egress is not supported");
6613 if (!(attributes->egress ^ attributes->ingress))
6614 return rte_flow_error_set(error, ENOTSUP,
6615 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6616 "must specify exactly one of "
6617 "ingress or egress");
6622 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6623 int64_t pattern_flags, uint64_t l3_flags,
6624 uint64_t l4_flags, uint64_t ip4_flag,
6625 struct rte_flow_error *error)
6627 if (mask->l3_ok && !(pattern_flags & l3_flags))
6628 return rte_flow_error_set(error, EINVAL,
6629 RTE_FLOW_ERROR_TYPE_ITEM,
6630 NULL, "missing L3 protocol");
6632 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6633 return rte_flow_error_set(error, EINVAL,
6634 RTE_FLOW_ERROR_TYPE_ITEM,
6635 NULL, "missing IPv4 protocol");
6637 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6638 return rte_flow_error_set(error, EINVAL,
6639 RTE_FLOW_ERROR_TYPE_ITEM,
6640 NULL, "missing L4 protocol");
6646 flow_dv_validate_item_integrity_post(const struct
6647 rte_flow_item *integrity_items[2],
6648 int64_t pattern_flags,
6649 struct rte_flow_error *error)
6651 const struct rte_flow_item_integrity *mask;
6654 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6655 mask = (typeof(mask))integrity_items[0]->mask;
6656 ret = validate_integrity_bits(mask, pattern_flags,
6657 MLX5_FLOW_LAYER_OUTER_L3,
6658 MLX5_FLOW_LAYER_OUTER_L4,
6659 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6664 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6665 mask = (typeof(mask))integrity_items[1]->mask;
6666 ret = validate_integrity_bits(mask, pattern_flags,
6667 MLX5_FLOW_LAYER_INNER_L3,
6668 MLX5_FLOW_LAYER_INNER_L4,
6669 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6678 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6679 const struct rte_flow_item *integrity_item,
6680 uint64_t pattern_flags, uint64_t *last_item,
6681 const struct rte_flow_item *integrity_items[2],
6682 struct rte_flow_error *error)
6684 struct mlx5_priv *priv = dev->data->dev_private;
6685 const struct rte_flow_item_integrity *mask = (typeof(mask))
6686 integrity_item->mask;
6687 const struct rte_flow_item_integrity *spec = (typeof(spec))
6688 integrity_item->spec;
6690 if (!priv->sh->cdev->config.hca_attr.pkt_integrity_match)
6691 return rte_flow_error_set(error, ENOTSUP,
6692 RTE_FLOW_ERROR_TYPE_ITEM,
6694 "packet integrity integrity_item not supported");
6696 return rte_flow_error_set(error, ENOTSUP,
6697 RTE_FLOW_ERROR_TYPE_ITEM,
6699 "no spec for integrity item");
6701 mask = &rte_flow_item_integrity_mask;
6702 if (!mlx5_validate_integrity_item(mask))
6703 return rte_flow_error_set(error, ENOTSUP,
6704 RTE_FLOW_ERROR_TYPE_ITEM,
6706 "unsupported integrity filter");
6707 if (spec->level > 1) {
6708 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6709 return rte_flow_error_set
6711 RTE_FLOW_ERROR_TYPE_ITEM,
6712 NULL, "multiple inner integrity items not supported");
6713 integrity_items[1] = integrity_item;
6714 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6716 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6717 return rte_flow_error_set
6719 RTE_FLOW_ERROR_TYPE_ITEM,
6720 NULL, "multiple outer integrity items not supported");
6721 integrity_items[0] = integrity_item;
6722 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6728 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6729 const struct rte_flow_item *item,
6730 uint64_t item_flags,
6731 uint64_t *last_item,
6733 struct rte_flow_error *error)
6735 const struct rte_flow_item_flex *flow_spec = item->spec;
6736 const struct rte_flow_item_flex *flow_mask = item->mask;
6737 struct mlx5_flex_item *flex;
6740 return rte_flow_error_set(error, EINVAL,
6741 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6742 "flex flow item spec cannot be NULL");
6744 return rte_flow_error_set(error, EINVAL,
6745 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6746 "flex flow item mask cannot be NULL");
6748 return rte_flow_error_set(error, ENOTSUP,
6749 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6750 "flex flow item last not supported");
6751 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6752 return rte_flow_error_set(error, EINVAL,
6753 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6754 "invalid flex flow item handle");
6755 flex = (struct mlx5_flex_item *)flow_spec->handle;
6756 switch (flex->tunnel_mode) {
6757 case FLEX_TUNNEL_MODE_SINGLE:
6759 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6760 rte_flow_error_set(error, EINVAL,
6761 RTE_FLOW_ERROR_TYPE_ITEM,
6762 NULL, "multiple flex items not supported");
6764 case FLEX_TUNNEL_MODE_OUTER:
6766 rte_flow_error_set(error, EINVAL,
6767 RTE_FLOW_ERROR_TYPE_ITEM,
6768 NULL, "inner flex item was not configured");
6769 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6770 rte_flow_error_set(error, ENOTSUP,
6771 RTE_FLOW_ERROR_TYPE_ITEM,
6772 NULL, "multiple flex items not supported");
6774 case FLEX_TUNNEL_MODE_INNER:
6776 rte_flow_error_set(error, EINVAL,
6777 RTE_FLOW_ERROR_TYPE_ITEM,
6778 NULL, "outer flex item was not configured");
6779 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6780 rte_flow_error_set(error, EINVAL,
6781 RTE_FLOW_ERROR_TYPE_ITEM,
6782 NULL, "multiple flex items not supported");
6784 case FLEX_TUNNEL_MODE_MULTI:
6785 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6786 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6787 rte_flow_error_set(error, EINVAL,
6788 RTE_FLOW_ERROR_TYPE_ITEM,
6789 NULL, "multiple flex items not supported");
6792 case FLEX_TUNNEL_MODE_TUNNEL:
6793 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6794 rte_flow_error_set(error, EINVAL,
6795 RTE_FLOW_ERROR_TYPE_ITEM,
6796 NULL, "multiple flex tunnel items not supported");
6799 rte_flow_error_set(error, EINVAL,
6800 RTE_FLOW_ERROR_TYPE_ITEM,
6801 NULL, "invalid flex item configuration");
6803 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6804 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6805 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6810 * Internal validation function. For validating both actions and items.
6813 * Pointer to the rte_eth_dev structure.
6815 * Pointer to the flow attributes.
6817 * Pointer to the list of items.
6818 * @param[in] actions
6819 * Pointer to the list of actions.
6820 * @param[in] external
6821 * This flow rule is created by request external to PMD.
6822 * @param[in] hairpin
6823 * Number of hairpin TX actions, 0 means classic flow.
6825 * Pointer to the error structure.
6828 * 0 on success, a negative errno value otherwise and rte_errno is set.
6831 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6832 const struct rte_flow_item items[],
6833 const struct rte_flow_action actions[],
6834 bool external, int hairpin, struct rte_flow_error *error)
6837 uint64_t action_flags = 0;
6838 uint64_t item_flags = 0;
6839 uint64_t last_item = 0;
6840 uint8_t next_protocol = 0xff;
6841 uint16_t ether_type = 0;
6843 uint8_t item_ipv6_proto = 0;
6844 int fdb_mirror_limit = 0;
6845 int modify_after_mirror = 0;
6846 const struct rte_flow_item *geneve_item = NULL;
6847 const struct rte_flow_item *gre_item = NULL;
6848 const struct rte_flow_item *gtp_item = NULL;
6849 const struct rte_flow_action_raw_decap *decap;
6850 const struct rte_flow_action_raw_encap *encap;
6851 const struct rte_flow_action_rss *rss = NULL;
6852 const struct rte_flow_action_rss *sample_rss = NULL;
6853 const struct rte_flow_action_count *sample_count = NULL;
6854 const struct rte_flow_item_tcp nic_tcp_mask = {
6857 .src_port = RTE_BE16(UINT16_MAX),
6858 .dst_port = RTE_BE16(UINT16_MAX),
6861 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6864 "\xff\xff\xff\xff\xff\xff\xff\xff"
6865 "\xff\xff\xff\xff\xff\xff\xff\xff",
6867 "\xff\xff\xff\xff\xff\xff\xff\xff"
6868 "\xff\xff\xff\xff\xff\xff\xff\xff",
6869 .vtc_flow = RTE_BE32(0xffffffff),
6875 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6879 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6883 .dummy[0] = 0xffffffff,
6886 struct mlx5_priv *priv = dev->data->dev_private;
6887 struct mlx5_dev_config *dev_conf = &priv->config;
6888 uint16_t queue_index = 0xFFFF;
6889 const struct rte_flow_item_vlan *vlan_m = NULL;
6890 uint32_t rw_act_num = 0;
6892 const struct mlx5_flow_tunnel *tunnel;
6893 enum mlx5_tof_rule_type tof_rule_type;
6894 struct flow_grp_info grp_info = {
6895 .external = !!external,
6896 .transfer = !!attr->transfer,
6897 .fdb_def_rule = !!priv->fdb_def_rule,
6898 .std_tbl_fix = true,
6900 const struct rte_eth_hairpin_conf *conf;
6901 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6902 const struct rte_flow_item *port_id_item = NULL;
6903 bool def_policy = false;
6904 uint16_t udp_dport = 0;
6908 tunnel = is_tunnel_offload_active(dev) ?
6909 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6911 if (!priv->config.dv_flow_en)
6912 return rte_flow_error_set
6914 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6915 NULL, "tunnel offload requires DV flow interface");
6916 if (priv->representor)
6917 return rte_flow_error_set
6919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6920 NULL, "decap not supported for VF representor");
6921 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6922 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6923 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6924 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6925 MLX5_FLOW_ACTION_DECAP;
6926 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6927 (dev, attr, tunnel, tof_rule_type);
6929 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6932 is_root = (uint64_t)ret;
6933 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6934 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6935 int type = items->type;
6937 if (!mlx5_flow_os_item_supported(type))
6938 return rte_flow_error_set(error, ENOTSUP,
6939 RTE_FLOW_ERROR_TYPE_ITEM,
6940 NULL, "item not supported");
6942 case RTE_FLOW_ITEM_TYPE_VOID:
6944 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6945 ret = flow_dv_validate_item_port_id
6946 (dev, items, attr, item_flags, error);
6949 last_item = MLX5_FLOW_ITEM_PORT_ID;
6950 port_id_item = items;
6952 case RTE_FLOW_ITEM_TYPE_ETH:
6953 ret = mlx5_flow_validate_item_eth(items, item_flags,
6957 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6958 MLX5_FLOW_LAYER_OUTER_L2;
6959 if (items->mask != NULL && items->spec != NULL) {
6961 ((const struct rte_flow_item_eth *)
6964 ((const struct rte_flow_item_eth *)
6966 ether_type = rte_be_to_cpu_16(ether_type);
6971 case RTE_FLOW_ITEM_TYPE_VLAN:
6972 ret = flow_dv_validate_item_vlan(items, item_flags,
6976 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6977 MLX5_FLOW_LAYER_OUTER_VLAN;
6978 if (items->mask != NULL && items->spec != NULL) {
6980 ((const struct rte_flow_item_vlan *)
6981 items->spec)->inner_type;
6983 ((const struct rte_flow_item_vlan *)
6984 items->mask)->inner_type;
6985 ether_type = rte_be_to_cpu_16(ether_type);
6989 /* Store outer VLAN mask for of_push_vlan action. */
6991 vlan_m = items->mask;
6993 case RTE_FLOW_ITEM_TYPE_IPV4:
6994 mlx5_flow_tunnel_ip_check(items, next_protocol,
6995 &item_flags, &tunnel);
6996 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6997 last_item, ether_type,
7001 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7002 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7003 if (items->mask != NULL &&
7004 ((const struct rte_flow_item_ipv4 *)
7005 items->mask)->hdr.next_proto_id) {
7007 ((const struct rte_flow_item_ipv4 *)
7008 (items->spec))->hdr.next_proto_id;
7010 ((const struct rte_flow_item_ipv4 *)
7011 (items->mask))->hdr.next_proto_id;
7013 /* Reset for inner layer. */
7014 next_protocol = 0xff;
7017 case RTE_FLOW_ITEM_TYPE_IPV6:
7018 mlx5_flow_tunnel_ip_check(items, next_protocol,
7019 &item_flags, &tunnel);
7020 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7027 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7028 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7029 if (items->mask != NULL &&
7030 ((const struct rte_flow_item_ipv6 *)
7031 items->mask)->hdr.proto) {
7033 ((const struct rte_flow_item_ipv6 *)
7034 items->spec)->hdr.proto;
7036 ((const struct rte_flow_item_ipv6 *)
7037 items->spec)->hdr.proto;
7039 ((const struct rte_flow_item_ipv6 *)
7040 items->mask)->hdr.proto;
7042 /* Reset for inner layer. */
7043 next_protocol = 0xff;
7046 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7047 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7052 last_item = tunnel ?
7053 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7054 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7055 if (items->mask != NULL &&
7056 ((const struct rte_flow_item_ipv6_frag_ext *)
7057 items->mask)->hdr.next_header) {
7059 ((const struct rte_flow_item_ipv6_frag_ext *)
7060 items->spec)->hdr.next_header;
7062 ((const struct rte_flow_item_ipv6_frag_ext *)
7063 items->mask)->hdr.next_header;
7065 /* Reset for inner layer. */
7066 next_protocol = 0xff;
7069 case RTE_FLOW_ITEM_TYPE_TCP:
7070 ret = mlx5_flow_validate_item_tcp
7077 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7078 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7080 case RTE_FLOW_ITEM_TYPE_UDP:
7081 ret = mlx5_flow_validate_item_udp(items, item_flags,
7084 const struct rte_flow_item_udp *spec = items->spec;
7085 const struct rte_flow_item_udp *mask = items->mask;
7087 mask = &rte_flow_item_udp_mask;
7089 udp_dport = rte_be_to_cpu_16
7090 (spec->hdr.dst_port &
7091 mask->hdr.dst_port);
7094 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7095 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7097 case RTE_FLOW_ITEM_TYPE_GRE:
7098 ret = mlx5_flow_validate_item_gre(items, item_flags,
7099 next_protocol, error);
7103 last_item = MLX5_FLOW_LAYER_GRE;
7105 case RTE_FLOW_ITEM_TYPE_NVGRE:
7106 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7111 last_item = MLX5_FLOW_LAYER_NVGRE;
7113 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7114 ret = mlx5_flow_validate_item_gre_key
7115 (items, item_flags, gre_item, error);
7118 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7120 case RTE_FLOW_ITEM_TYPE_VXLAN:
7121 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7126 last_item = MLX5_FLOW_LAYER_VXLAN;
7128 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7129 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7134 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7136 case RTE_FLOW_ITEM_TYPE_GENEVE:
7137 ret = mlx5_flow_validate_item_geneve(items,
7142 geneve_item = items;
7143 last_item = MLX5_FLOW_LAYER_GENEVE;
7145 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7146 ret = mlx5_flow_validate_item_geneve_opt(items,
7153 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7155 case RTE_FLOW_ITEM_TYPE_MPLS:
7156 ret = mlx5_flow_validate_item_mpls(dev, items,
7161 last_item = MLX5_FLOW_LAYER_MPLS;
7164 case RTE_FLOW_ITEM_TYPE_MARK:
7165 ret = flow_dv_validate_item_mark(dev, items, attr,
7169 last_item = MLX5_FLOW_ITEM_MARK;
7171 case RTE_FLOW_ITEM_TYPE_META:
7172 ret = flow_dv_validate_item_meta(dev, items, attr,
7176 last_item = MLX5_FLOW_ITEM_METADATA;
7178 case RTE_FLOW_ITEM_TYPE_ICMP:
7179 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7184 last_item = MLX5_FLOW_LAYER_ICMP;
7186 case RTE_FLOW_ITEM_TYPE_ICMP6:
7187 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7192 item_ipv6_proto = IPPROTO_ICMPV6;
7193 last_item = MLX5_FLOW_LAYER_ICMP6;
7195 case RTE_FLOW_ITEM_TYPE_TAG:
7196 ret = flow_dv_validate_item_tag(dev, items,
7200 last_item = MLX5_FLOW_ITEM_TAG;
7202 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7203 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7205 case RTE_FLOW_ITEM_TYPE_GTP:
7206 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7211 last_item = MLX5_FLOW_LAYER_GTP;
7213 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7214 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7219 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7221 case RTE_FLOW_ITEM_TYPE_ECPRI:
7222 /* Capacity will be checked in the translate stage. */
7223 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7230 last_item = MLX5_FLOW_LAYER_ECPRI;
7232 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7233 ret = flow_dv_validate_item_integrity(dev, items,
7241 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7242 ret = flow_dv_validate_item_aso_ct(dev, items,
7243 &item_flags, error);
7247 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7248 /* tunnel offload item was processed before
7249 * list it here as a supported type
7252 case RTE_FLOW_ITEM_TYPE_FLEX:
7253 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7255 tunnel != 0, error);
7260 return rte_flow_error_set(error, ENOTSUP,
7261 RTE_FLOW_ERROR_TYPE_ITEM,
7262 NULL, "item not supported");
7264 item_flags |= last_item;
7266 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7267 ret = flow_dv_validate_item_integrity_post(integrity_items,
7272 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7273 int type = actions->type;
7274 bool shared_count = false;
7276 if (!mlx5_flow_os_action_supported(type))
7277 return rte_flow_error_set(error, ENOTSUP,
7278 RTE_FLOW_ERROR_TYPE_ACTION,
7280 "action not supported");
7281 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7282 return rte_flow_error_set(error, ENOTSUP,
7283 RTE_FLOW_ERROR_TYPE_ACTION,
7284 actions, "too many actions");
7286 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7287 return rte_flow_error_set(error, ENOTSUP,
7288 RTE_FLOW_ERROR_TYPE_ACTION,
7289 NULL, "meter action with policy "
7290 "must be the last action");
7292 case RTE_FLOW_ACTION_TYPE_VOID:
7294 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7295 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7296 ret = flow_dv_validate_action_port_id(dev,
7303 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7306 case RTE_FLOW_ACTION_TYPE_FLAG:
7307 ret = flow_dv_validate_action_flag(dev, action_flags,
7311 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7312 /* Count all modify-header actions as one. */
7313 if (!(action_flags &
7314 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7316 action_flags |= MLX5_FLOW_ACTION_FLAG |
7317 MLX5_FLOW_ACTION_MARK_EXT;
7318 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7319 modify_after_mirror = 1;
7322 action_flags |= MLX5_FLOW_ACTION_FLAG;
7325 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7327 case RTE_FLOW_ACTION_TYPE_MARK:
7328 ret = flow_dv_validate_action_mark(dev, actions,
7333 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7334 /* Count all modify-header actions as one. */
7335 if (!(action_flags &
7336 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7338 action_flags |= MLX5_FLOW_ACTION_MARK |
7339 MLX5_FLOW_ACTION_MARK_EXT;
7340 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7341 modify_after_mirror = 1;
7343 action_flags |= MLX5_FLOW_ACTION_MARK;
7346 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7348 case RTE_FLOW_ACTION_TYPE_SET_META:
7349 ret = flow_dv_validate_action_set_meta(dev, actions,
7354 /* Count all modify-header actions as one action. */
7355 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7357 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7358 modify_after_mirror = 1;
7359 action_flags |= MLX5_FLOW_ACTION_SET_META;
7360 rw_act_num += MLX5_ACT_NUM_SET_META;
7362 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7363 ret = flow_dv_validate_action_set_tag(dev, actions,
7368 /* Count all modify-header actions as one action. */
7369 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7371 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7372 modify_after_mirror = 1;
7373 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7374 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7376 case RTE_FLOW_ACTION_TYPE_DROP:
7377 ret = mlx5_flow_validate_action_drop(action_flags,
7381 action_flags |= MLX5_FLOW_ACTION_DROP;
7384 case RTE_FLOW_ACTION_TYPE_QUEUE:
7385 ret = mlx5_flow_validate_action_queue(actions,
7390 queue_index = ((const struct rte_flow_action_queue *)
7391 (actions->conf))->index;
7392 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7395 case RTE_FLOW_ACTION_TYPE_RSS:
7396 rss = actions->conf;
7397 ret = mlx5_flow_validate_action_rss(actions,
7403 if (rss && sample_rss &&
7404 (sample_rss->level != rss->level ||
7405 sample_rss->types != rss->types))
7406 return rte_flow_error_set(error, ENOTSUP,
7407 RTE_FLOW_ERROR_TYPE_ACTION,
7409 "Can't use the different RSS types "
7410 "or level in the same flow");
7411 if (rss != NULL && rss->queue_num)
7412 queue_index = rss->queue[0];
7413 action_flags |= MLX5_FLOW_ACTION_RSS;
7416 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7418 mlx5_flow_validate_action_default_miss(action_flags,
7422 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7425 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7426 shared_count = true;
7428 case RTE_FLOW_ACTION_TYPE_COUNT:
7429 ret = flow_dv_validate_action_count(dev, shared_count,
7434 action_flags |= MLX5_FLOW_ACTION_COUNT;
7437 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7438 if (flow_dv_validate_action_pop_vlan(dev,
7444 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7445 modify_after_mirror = 1;
7446 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7449 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7450 ret = flow_dv_validate_action_push_vlan(dev,
7457 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7458 modify_after_mirror = 1;
7459 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7462 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7463 ret = flow_dv_validate_action_set_vlan_pcp
7464 (action_flags, actions, error);
7467 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7468 modify_after_mirror = 1;
7469 /* Count PCP with push_vlan command. */
7470 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7472 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7473 ret = flow_dv_validate_action_set_vlan_vid
7474 (item_flags, action_flags,
7478 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7479 modify_after_mirror = 1;
7480 /* Count VID with push_vlan command. */
7481 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7482 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7484 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7485 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7486 ret = flow_dv_validate_action_l2_encap(dev,
7492 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7495 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7496 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7497 ret = flow_dv_validate_action_decap(dev, action_flags,
7498 actions, item_flags,
7502 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7503 modify_after_mirror = 1;
7504 action_flags |= MLX5_FLOW_ACTION_DECAP;
7507 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7508 ret = flow_dv_validate_action_raw_encap_decap
7509 (dev, NULL, actions->conf, attr, &action_flags,
7510 &actions_n, actions, item_flags, error);
7514 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7515 decap = actions->conf;
7516 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7518 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7522 encap = actions->conf;
7524 ret = flow_dv_validate_action_raw_encap_decap
7526 decap ? decap : &empty_decap, encap,
7527 attr, &action_flags, &actions_n,
7528 actions, item_flags, error);
7531 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7532 (action_flags & MLX5_FLOW_ACTION_DECAP))
7533 modify_after_mirror = 1;
7535 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7536 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7537 ret = flow_dv_validate_action_modify_mac(action_flags,
7543 /* Count all modify-header actions as one action. */
7544 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7546 action_flags |= actions->type ==
7547 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7548 MLX5_FLOW_ACTION_SET_MAC_SRC :
7549 MLX5_FLOW_ACTION_SET_MAC_DST;
7550 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7551 modify_after_mirror = 1;
7553 * Even if the source and destination MAC addresses have
7554 * overlap in the header with 4B alignment, the convert
7555 * function will handle them separately and 4 SW actions
7556 * will be created. And 2 actions will be added each
7557 * time no matter how many bytes of address will be set.
7559 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7561 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7562 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7563 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7569 /* Count all modify-header actions as one action. */
7570 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7572 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7573 modify_after_mirror = 1;
7574 action_flags |= actions->type ==
7575 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7576 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7577 MLX5_FLOW_ACTION_SET_IPV4_DST;
7578 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7580 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7581 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7582 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7588 if (item_ipv6_proto == IPPROTO_ICMPV6)
7589 return rte_flow_error_set(error, ENOTSUP,
7590 RTE_FLOW_ERROR_TYPE_ACTION,
7592 "Can't change header "
7593 "with ICMPv6 proto");
7594 /* Count all modify-header actions as one action. */
7595 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7597 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7598 modify_after_mirror = 1;
7599 action_flags |= actions->type ==
7600 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7601 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7602 MLX5_FLOW_ACTION_SET_IPV6_DST;
7603 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7605 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7606 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7607 ret = flow_dv_validate_action_modify_tp(action_flags,
7613 /* Count all modify-header actions as one action. */
7614 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7616 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7617 modify_after_mirror = 1;
7618 action_flags |= actions->type ==
7619 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7620 MLX5_FLOW_ACTION_SET_TP_SRC :
7621 MLX5_FLOW_ACTION_SET_TP_DST;
7622 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7624 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7625 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7626 ret = flow_dv_validate_action_modify_ttl(action_flags,
7632 /* Count all modify-header actions as one action. */
7633 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7635 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7636 modify_after_mirror = 1;
7637 action_flags |= actions->type ==
7638 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7639 MLX5_FLOW_ACTION_SET_TTL :
7640 MLX5_FLOW_ACTION_DEC_TTL;
7641 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7643 case RTE_FLOW_ACTION_TYPE_JUMP:
7644 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7650 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7652 return rte_flow_error_set(error, EINVAL,
7653 RTE_FLOW_ERROR_TYPE_ACTION,
7655 "sample and jump action combination is not supported");
7657 action_flags |= MLX5_FLOW_ACTION_JUMP;
7659 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7660 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7661 ret = flow_dv_validate_action_modify_tcp_seq
7668 /* Count all modify-header actions as one action. */
7669 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7671 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7672 modify_after_mirror = 1;
7673 action_flags |= actions->type ==
7674 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7675 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7676 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7677 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7679 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7680 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7681 ret = flow_dv_validate_action_modify_tcp_ack
7688 /* Count all modify-header actions as one action. */
7689 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7691 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7692 modify_after_mirror = 1;
7693 action_flags |= actions->type ==
7694 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7695 MLX5_FLOW_ACTION_INC_TCP_ACK :
7696 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7697 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7699 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7701 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7702 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7703 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7705 case RTE_FLOW_ACTION_TYPE_METER:
7706 ret = mlx5_flow_validate_action_meter(dev,
7715 action_flags |= MLX5_FLOW_ACTION_METER;
7718 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7720 /* Meter action will add one more TAG action. */
7721 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7723 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7724 if (!attr->transfer && !attr->group)
7725 return rte_flow_error_set(error, ENOTSUP,
7726 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7728 "Shared ASO age action is not supported for group 0");
7729 if (action_flags & MLX5_FLOW_ACTION_AGE)
7730 return rte_flow_error_set
7732 RTE_FLOW_ERROR_TYPE_ACTION,
7734 "duplicate age actions set");
7735 action_flags |= MLX5_FLOW_ACTION_AGE;
7738 case RTE_FLOW_ACTION_TYPE_AGE:
7739 ret = flow_dv_validate_action_age(action_flags,
7745 * Validate the regular AGE action (using counter)
7746 * mutual exclusion with share counter actions.
7748 if (!priv->sh->flow_hit_aso_en) {
7750 return rte_flow_error_set
7752 RTE_FLOW_ERROR_TYPE_ACTION,
7754 "old age and shared count combination is not supported");
7756 return rte_flow_error_set
7758 RTE_FLOW_ERROR_TYPE_ACTION,
7760 "old age action and count must be in the same sub flow");
7762 action_flags |= MLX5_FLOW_ACTION_AGE;
7765 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7766 ret = flow_dv_validate_action_modify_ipv4_dscp
7773 /* Count all modify-header actions as one action. */
7774 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7776 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7777 modify_after_mirror = 1;
7778 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7779 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7781 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7782 ret = flow_dv_validate_action_modify_ipv6_dscp
7789 /* Count all modify-header actions as one action. */
7790 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7792 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7793 modify_after_mirror = 1;
7794 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7795 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7797 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7798 ret = flow_dv_validate_action_sample(&action_flags,
7807 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7810 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7811 ret = flow_dv_validate_action_modify_field(dev,
7818 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7819 modify_after_mirror = 1;
7820 /* Count all modify-header actions as one action. */
7821 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7823 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7826 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7827 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7832 action_flags |= MLX5_FLOW_ACTION_CT;
7834 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7835 /* tunnel offload action was processed before
7836 * list it here as a supported type
7840 return rte_flow_error_set(error, ENOTSUP,
7841 RTE_FLOW_ERROR_TYPE_ACTION,
7843 "action not supported");
7847 * Validate actions in flow rules
7848 * - Explicit decap action is prohibited by the tunnel offload API.
7849 * - Drop action in tunnel steer rule is prohibited by the API.
7850 * - Application cannot use MARK action because it's value can mask
7851 * tunnel default miss notification.
7852 * - JUMP in tunnel match rule has no support in current PMD
7854 * - TAG & META are reserved for future uses.
7856 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7857 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7858 MLX5_FLOW_ACTION_MARK |
7859 MLX5_FLOW_ACTION_SET_TAG |
7860 MLX5_FLOW_ACTION_SET_META |
7861 MLX5_FLOW_ACTION_DROP;
7863 if (action_flags & bad_actions_mask)
7864 return rte_flow_error_set
7866 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7867 "Invalid RTE action in tunnel "
7869 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7870 return rte_flow_error_set
7872 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7873 "tunnel set decap rule must terminate "
7876 return rte_flow_error_set
7878 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7879 "tunnel flows for ingress traffic only");
7881 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7882 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7883 MLX5_FLOW_ACTION_MARK |
7884 MLX5_FLOW_ACTION_SET_TAG |
7885 MLX5_FLOW_ACTION_SET_META;
7887 if (action_flags & bad_actions_mask)
7888 return rte_flow_error_set
7890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7891 "Invalid RTE action in tunnel "
7895 * Validate the drop action mutual exclusion with other actions.
7896 * Drop action is mutually-exclusive with any other action, except for
7898 * Drop action compatibility with tunnel offload was already validated.
7900 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7901 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7902 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7903 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7904 return rte_flow_error_set(error, EINVAL,
7905 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7906 "Drop action is mutually-exclusive "
7907 "with any other action, except for "
7909 /* Eswitch has few restrictions on using items and actions */
7910 if (attr->transfer) {
7911 if (!mlx5_flow_ext_mreg_supported(dev) &&
7912 action_flags & MLX5_FLOW_ACTION_FLAG)
7913 return rte_flow_error_set(error, ENOTSUP,
7914 RTE_FLOW_ERROR_TYPE_ACTION,
7916 "unsupported action FLAG");
7917 if (!mlx5_flow_ext_mreg_supported(dev) &&
7918 action_flags & MLX5_FLOW_ACTION_MARK)
7919 return rte_flow_error_set(error, ENOTSUP,
7920 RTE_FLOW_ERROR_TYPE_ACTION,
7922 "unsupported action MARK");
7923 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7924 return rte_flow_error_set(error, ENOTSUP,
7925 RTE_FLOW_ERROR_TYPE_ACTION,
7927 "unsupported action QUEUE");
7928 if (action_flags & MLX5_FLOW_ACTION_RSS)
7929 return rte_flow_error_set(error, ENOTSUP,
7930 RTE_FLOW_ERROR_TYPE_ACTION,
7932 "unsupported action RSS");
7933 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7934 return rte_flow_error_set(error, EINVAL,
7935 RTE_FLOW_ERROR_TYPE_ACTION,
7937 "no fate action is found");
7939 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7940 return rte_flow_error_set(error, EINVAL,
7941 RTE_FLOW_ERROR_TYPE_ACTION,
7943 "no fate action is found");
7946 * Continue validation for Xcap and VLAN actions.
7947 * If hairpin is working in explicit TX rule mode, there is no actions
7948 * splitting and the validation of hairpin ingress flow should be the
7949 * same as other standard flows.
7951 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7952 MLX5_FLOW_VLAN_ACTIONS)) &&
7953 (queue_index == 0xFFFF ||
7954 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7955 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7956 conf->tx_explicit != 0))) {
7957 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7958 MLX5_FLOW_XCAP_ACTIONS)
7959 return rte_flow_error_set(error, ENOTSUP,
7960 RTE_FLOW_ERROR_TYPE_ACTION,
7961 NULL, "encap and decap "
7962 "combination aren't supported");
7963 if (!attr->transfer && attr->ingress) {
7964 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7965 return rte_flow_error_set
7967 RTE_FLOW_ERROR_TYPE_ACTION,
7968 NULL, "encap is not supported"
7969 " for ingress traffic");
7970 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7971 return rte_flow_error_set
7973 RTE_FLOW_ERROR_TYPE_ACTION,
7974 NULL, "push VLAN action not "
7975 "supported for ingress");
7976 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7977 MLX5_FLOW_VLAN_ACTIONS)
7978 return rte_flow_error_set
7980 RTE_FLOW_ERROR_TYPE_ACTION,
7981 NULL, "no support for "
7982 "multiple VLAN actions");
7985 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7986 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7987 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7989 return rte_flow_error_set
7991 RTE_FLOW_ERROR_TYPE_ACTION,
7992 NULL, "fate action not supported for "
7993 "meter with policy");
7995 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7996 return rte_flow_error_set
7998 RTE_FLOW_ERROR_TYPE_ACTION,
7999 NULL, "modify header action in egress "
8000 "cannot be done before meter action");
8001 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8002 return rte_flow_error_set
8004 RTE_FLOW_ERROR_TYPE_ACTION,
8005 NULL, "encap action in egress "
8006 "cannot be done before meter action");
8007 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8008 return rte_flow_error_set
8010 RTE_FLOW_ERROR_TYPE_ACTION,
8011 NULL, "push vlan action in egress "
8012 "cannot be done before meter action");
8016 * Hairpin flow will add one more TAG action in TX implicit mode.
8017 * In TX explicit mode, there will be no hairpin flow ID.
8020 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8021 /* extra metadata enabled: one more TAG action will be add. */
8022 if (dev_conf->dv_flow_en &&
8023 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8024 mlx5_flow_ext_mreg_supported(dev))
8025 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8027 flow_dv_modify_hdr_action_max(dev, is_root)) {
8028 return rte_flow_error_set(error, ENOTSUP,
8029 RTE_FLOW_ERROR_TYPE_ACTION,
8030 NULL, "too many header modify"
8031 " actions to support");
8033 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8034 if (fdb_mirror_limit && modify_after_mirror)
8035 return rte_flow_error_set(error, EINVAL,
8036 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8037 "sample before modify action is not supported");
8042 * Internal preparation function. Allocates the DV flow size,
8043 * this size is constant.
8046 * Pointer to the rte_eth_dev structure.
8048 * Pointer to the flow attributes.
8050 * Pointer to the list of items.
8051 * @param[in] actions
8052 * Pointer to the list of actions.
8054 * Pointer to the error structure.
8057 * Pointer to mlx5_flow object on success,
8058 * otherwise NULL and rte_errno is set.
8060 static struct mlx5_flow *
8061 flow_dv_prepare(struct rte_eth_dev *dev,
8062 const struct rte_flow_attr *attr __rte_unused,
8063 const struct rte_flow_item items[] __rte_unused,
8064 const struct rte_flow_action actions[] __rte_unused,
8065 struct rte_flow_error *error)
8067 uint32_t handle_idx = 0;
8068 struct mlx5_flow *dev_flow;
8069 struct mlx5_flow_handle *dev_handle;
8070 struct mlx5_priv *priv = dev->data->dev_private;
8071 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8074 wks->skip_matcher_reg = 0;
8076 wks->final_policy = NULL;
8077 /* In case of corrupting the memory. */
8078 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8079 rte_flow_error_set(error, ENOSPC,
8080 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8081 "not free temporary device flow");
8084 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8087 rte_flow_error_set(error, ENOMEM,
8088 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8089 "not enough memory to create flow handle");
8092 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8093 dev_flow = &wks->flows[wks->flow_idx++];
8094 memset(dev_flow, 0, sizeof(*dev_flow));
8095 dev_flow->handle = dev_handle;
8096 dev_flow->handle_idx = handle_idx;
8097 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8098 dev_flow->ingress = attr->ingress;
8099 dev_flow->dv.transfer = attr->transfer;
8103 #ifdef RTE_LIBRTE_MLX5_DEBUG
8105 * Sanity check for match mask and value. Similar to check_valid_spec() in
8106 * kernel driver. If unmasked bit is present in value, it returns failure.
8109 * pointer to match mask buffer.
8110 * @param match_value
8111 * pointer to match value buffer.
8114 * 0 if valid, -EINVAL otherwise.
8117 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8119 uint8_t *m = match_mask;
8120 uint8_t *v = match_value;
8123 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8126 "match_value differs from match_criteria"
8127 " %p[%u] != %p[%u]",
8128 match_value, i, match_mask, i);
8137 * Add match of ip_version.
8141 * @param[in] headers_v
8142 * Values header pointer.
8143 * @param[in] headers_m
8144 * Masks header pointer.
8145 * @param[in] ip_version
8146 * The IP version to set.
8149 flow_dv_set_match_ip_version(uint32_t group,
8155 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8157 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8159 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8160 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8161 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8165 * Add Ethernet item to matcher and to the value.
8167 * @param[in, out] matcher
8169 * @param[in, out] key
8170 * Flow matcher value.
8172 * Flow pattern to translate.
8174 * Item is inner pattern.
8177 flow_dv_translate_item_eth(void *matcher, void *key,
8178 const struct rte_flow_item *item, int inner,
8181 const struct rte_flow_item_eth *eth_m = item->mask;
8182 const struct rte_flow_item_eth *eth_v = item->spec;
8183 const struct rte_flow_item_eth nic_mask = {
8184 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8185 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8186 .type = RTE_BE16(0xffff),
8199 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8201 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8203 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8205 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8207 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8208 ð_m->dst, sizeof(eth_m->dst));
8209 /* The value must be in the range of the mask. */
8210 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8211 for (i = 0; i < sizeof(eth_m->dst); ++i)
8212 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8213 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8214 ð_m->src, sizeof(eth_m->src));
8215 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8216 /* The value must be in the range of the mask. */
8217 for (i = 0; i < sizeof(eth_m->dst); ++i)
8218 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8220 * HW supports match on one Ethertype, the Ethertype following the last
8221 * VLAN tag of the packet (see PRM).
8222 * Set match on ethertype only if ETH header is not followed by VLAN.
8223 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8224 * ethertype, and use ip_version field instead.
8225 * eCPRI over Ether layer will use type value 0xAEFE.
8227 if (eth_m->type == 0xFFFF) {
8228 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8229 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8230 switch (eth_v->type) {
8231 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8232 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8234 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8235 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8236 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8238 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8239 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8241 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8242 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8248 if (eth_m->has_vlan) {
8249 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8250 if (eth_v->has_vlan) {
8252 * Here, when also has_more_vlan field in VLAN item is
8253 * not set, only single-tagged packets will be matched.
8255 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8259 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8260 rte_be_to_cpu_16(eth_m->type));
8261 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8262 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8266 * Add VLAN item to matcher and to the value.
8268 * @param[in, out] dev_flow
8270 * @param[in, out] matcher
8272 * @param[in, out] key
8273 * Flow matcher value.
8275 * Flow pattern to translate.
8277 * Item is inner pattern.
8280 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8281 void *matcher, void *key,
8282 const struct rte_flow_item *item,
8283 int inner, uint32_t group)
8285 const struct rte_flow_item_vlan *vlan_m = item->mask;
8286 const struct rte_flow_item_vlan *vlan_v = item->spec;
8293 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8295 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8297 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8299 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8301 * This is workaround, masks are not supported,
8302 * and pre-validated.
8305 dev_flow->handle->vf_vlan.tag =
8306 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8309 * When VLAN item exists in flow, mark packet as tagged,
8310 * even if TCI is not specified.
8312 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8313 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8314 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8319 vlan_m = &rte_flow_item_vlan_mask;
8320 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8321 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8322 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8323 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8325 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8326 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8327 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8329 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8330 * ethertype, and use ip_version field instead.
8332 if (vlan_m->inner_type == 0xFFFF) {
8333 switch (vlan_v->inner_type) {
8334 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8335 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8339 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8340 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8342 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8343 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8349 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8350 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8351 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8352 /* Only one vlan_tag bit can be set. */
8353 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8356 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8357 rte_be_to_cpu_16(vlan_m->inner_type));
8358 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8359 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8363 * Add IPV4 item to matcher and to the value.
8365 * @param[in, out] matcher
8367 * @param[in, out] key
8368 * Flow matcher value.
8370 * Flow pattern to translate.
8372 * Item is inner pattern.
8374 * The group to insert the rule.
8377 flow_dv_translate_item_ipv4(void *matcher, void *key,
8378 const struct rte_flow_item *item,
8379 int inner, uint32_t group)
8381 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8382 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8383 const struct rte_flow_item_ipv4 nic_mask = {
8385 .src_addr = RTE_BE32(0xffffffff),
8386 .dst_addr = RTE_BE32(0xffffffff),
8387 .type_of_service = 0xff,
8388 .next_proto_id = 0xff,
8389 .time_to_live = 0xff,
8396 uint8_t tos, ihl_m, ihl_v;
8399 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8401 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8403 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8405 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8407 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8412 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8413 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8414 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8415 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8416 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8417 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8418 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8419 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8420 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8421 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8422 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8423 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8424 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8425 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8426 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8428 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8429 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8430 ipv4_m->hdr.type_of_service);
8431 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8432 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8433 ipv4_m->hdr.type_of_service >> 2);
8434 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8435 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8436 ipv4_m->hdr.next_proto_id);
8437 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8438 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8439 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8440 ipv4_m->hdr.time_to_live);
8441 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8442 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8443 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8444 !!(ipv4_m->hdr.fragment_offset));
8445 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8446 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8450 * Add IPV6 item to matcher and to the value.
8452 * @param[in, out] matcher
8454 * @param[in, out] key
8455 * Flow matcher value.
8457 * Flow pattern to translate.
8459 * Item is inner pattern.
8461 * The group to insert the rule.
8464 flow_dv_translate_item_ipv6(void *matcher, void *key,
8465 const struct rte_flow_item *item,
8466 int inner, uint32_t group)
8468 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8469 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8470 const struct rte_flow_item_ipv6 nic_mask = {
8473 "\xff\xff\xff\xff\xff\xff\xff\xff"
8474 "\xff\xff\xff\xff\xff\xff\xff\xff",
8476 "\xff\xff\xff\xff\xff\xff\xff\xff"
8477 "\xff\xff\xff\xff\xff\xff\xff\xff",
8478 .vtc_flow = RTE_BE32(0xffffffff),
8485 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8486 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8495 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8497 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8499 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8501 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8503 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8508 size = sizeof(ipv6_m->hdr.dst_addr);
8509 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8510 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8511 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8512 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8513 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8514 for (i = 0; i < size; ++i)
8515 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8516 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8517 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8518 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8519 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8520 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8521 for (i = 0; i < size; ++i)
8522 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8524 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8525 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8526 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8527 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8532 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8534 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8537 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8539 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8543 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8545 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8546 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8548 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8549 ipv6_m->hdr.hop_limits);
8550 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8551 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8552 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8553 !!(ipv6_m->has_frag_ext));
8554 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8555 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8559 * Add IPV6 fragment extension item to matcher and to the value.
8561 * @param[in, out] matcher
8563 * @param[in, out] key
8564 * Flow matcher value.
8566 * Flow pattern to translate.
8568 * Item is inner pattern.
8571 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8572 const struct rte_flow_item *item,
8575 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8576 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8577 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8579 .next_header = 0xff,
8580 .frag_data = RTE_BE16(0xffff),
8587 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8589 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8591 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8593 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8595 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8596 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8597 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8598 if (!ipv6_frag_ext_v)
8600 if (!ipv6_frag_ext_m)
8601 ipv6_frag_ext_m = &nic_mask;
8602 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8603 ipv6_frag_ext_m->hdr.next_header);
8604 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8605 ipv6_frag_ext_v->hdr.next_header &
8606 ipv6_frag_ext_m->hdr.next_header);
8610 * Add TCP item to matcher and to the value.
8612 * @param[in, out] matcher
8614 * @param[in, out] key
8615 * Flow matcher value.
8617 * Flow pattern to translate.
8619 * Item is inner pattern.
8622 flow_dv_translate_item_tcp(void *matcher, void *key,
8623 const struct rte_flow_item *item,
8626 const struct rte_flow_item_tcp *tcp_m = item->mask;
8627 const struct rte_flow_item_tcp *tcp_v = item->spec;
8632 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8634 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8636 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8638 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8640 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8641 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8645 tcp_m = &rte_flow_item_tcp_mask;
8646 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8647 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8648 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8649 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8651 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8652 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8653 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8654 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8655 tcp_m->hdr.tcp_flags);
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8657 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8661 * Add UDP item to matcher and to the value.
8663 * @param[in, out] matcher
8665 * @param[in, out] key
8666 * Flow matcher value.
8668 * Flow pattern to translate.
8670 * Item is inner pattern.
8673 flow_dv_translate_item_udp(void *matcher, void *key,
8674 const struct rte_flow_item *item,
8677 const struct rte_flow_item_udp *udp_m = item->mask;
8678 const struct rte_flow_item_udp *udp_v = item->spec;
8683 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8685 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8687 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8689 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8691 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8692 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8696 udp_m = &rte_flow_item_udp_mask;
8697 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8698 rte_be_to_cpu_16(udp_m->hdr.src_port));
8699 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8700 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8701 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8702 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8703 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8704 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8708 * Add GRE optional Key item to matcher and to the value.
8710 * @param[in, out] matcher
8712 * @param[in, out] key
8713 * Flow matcher value.
8715 * Flow pattern to translate.
8717 * Item is inner pattern.
8720 flow_dv_translate_item_gre_key(void *matcher, void *key,
8721 const struct rte_flow_item *item)
8723 const rte_be32_t *key_m = item->mask;
8724 const rte_be32_t *key_v = item->spec;
8725 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8726 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8727 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8729 /* GRE K bit must be on and should already be validated */
8730 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8731 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8735 key_m = &gre_key_default_mask;
8736 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8737 rte_be_to_cpu_32(*key_m) >> 8);
8738 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8739 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8740 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8741 rte_be_to_cpu_32(*key_m) & 0xFF);
8742 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8743 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8747 * Add GRE item to matcher and to the value.
8749 * @param[in, out] matcher
8751 * @param[in, out] key
8752 * Flow matcher value.
8754 * Flow pattern to translate.
8755 * @param[in] pattern_flags
8756 * Accumulated pattern flags.
8759 flow_dv_translate_item_gre(void *matcher, void *key,
8760 const struct rte_flow_item *item,
8761 uint64_t pattern_flags)
8763 static const struct rte_flow_item_gre empty_gre = {0,};
8764 const struct rte_flow_item_gre *gre_m = item->mask;
8765 const struct rte_flow_item_gre *gre_v = item->spec;
8766 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8767 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8768 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8769 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8776 uint16_t s_present:1;
8777 uint16_t k_present:1;
8778 uint16_t rsvd_bit1:1;
8779 uint16_t c_present:1;
8783 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8784 uint16_t protocol_m, protocol_v;
8786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8793 gre_m = &rte_flow_item_gre_mask;
8795 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8796 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8797 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8798 gre_crks_rsvd0_ver_m.c_present);
8799 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8800 gre_crks_rsvd0_ver_v.c_present &
8801 gre_crks_rsvd0_ver_m.c_present);
8802 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8803 gre_crks_rsvd0_ver_m.k_present);
8804 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8805 gre_crks_rsvd0_ver_v.k_present &
8806 gre_crks_rsvd0_ver_m.k_present);
8807 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8808 gre_crks_rsvd0_ver_m.s_present);
8809 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8810 gre_crks_rsvd0_ver_v.s_present &
8811 gre_crks_rsvd0_ver_m.s_present);
8812 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8813 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8815 /* Force next protocol to prevent matchers duplication */
8816 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8818 protocol_m = 0xFFFF;
8820 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8821 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8822 protocol_m & protocol_v);
8826 * Add NVGRE item to matcher and to the value.
8828 * @param[in, out] matcher
8830 * @param[in, out] key
8831 * Flow matcher value.
8833 * Flow pattern to translate.
8834 * @param[in] pattern_flags
8835 * Accumulated pattern flags.
8838 flow_dv_translate_item_nvgre(void *matcher, void *key,
8839 const struct rte_flow_item *item,
8840 unsigned long pattern_flags)
8842 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8843 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8844 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8845 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8846 const char *tni_flow_id_m;
8847 const char *tni_flow_id_v;
8853 /* For NVGRE, GRE header fields must be set with defined values. */
8854 const struct rte_flow_item_gre gre_spec = {
8855 .c_rsvd0_ver = RTE_BE16(0x2000),
8856 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8858 const struct rte_flow_item_gre gre_mask = {
8859 .c_rsvd0_ver = RTE_BE16(0xB000),
8860 .protocol = RTE_BE16(UINT16_MAX),
8862 const struct rte_flow_item gre_item = {
8867 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8871 nvgre_m = &rte_flow_item_nvgre_mask;
8872 tni_flow_id_m = (const char *)nvgre_m->tni;
8873 tni_flow_id_v = (const char *)nvgre_v->tni;
8874 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8875 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8876 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8877 memcpy(gre_key_m, tni_flow_id_m, size);
8878 for (i = 0; i < size; ++i)
8879 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8883 * Add VXLAN item to matcher and to the value.
8886 * Pointer to the Ethernet device structure.
8888 * Flow rule attributes.
8889 * @param[in, out] matcher
8891 * @param[in, out] key
8892 * Flow matcher value.
8894 * Flow pattern to translate.
8896 * Item is inner pattern.
8899 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8900 const struct rte_flow_attr *attr,
8901 void *matcher, void *key,
8902 const struct rte_flow_item *item,
8905 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8906 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8911 uint32_t *tunnel_header_v;
8912 uint32_t *tunnel_header_m;
8914 struct mlx5_priv *priv = dev->data->dev_private;
8915 const struct rte_flow_item_vxlan nic_mask = {
8916 .vni = "\xff\xff\xff",
8921 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8923 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8925 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8927 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8929 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8930 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8931 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8932 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8933 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8935 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8939 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8940 (attr->group && !priv->sh->misc5_cap))
8941 vxlan_m = &rte_flow_item_vxlan_mask;
8943 vxlan_m = &nic_mask;
8945 if ((priv->sh->steering_format_version ==
8946 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8947 dport != MLX5_UDP_PORT_VXLAN) ||
8948 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8949 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8956 misc_m = MLX5_ADDR_OF(fte_match_param,
8957 matcher, misc_parameters);
8958 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8959 size = sizeof(vxlan_m->vni);
8960 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8961 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8962 memcpy(vni_m, vxlan_m->vni, size);
8963 for (i = 0; i < size; ++i)
8964 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8967 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8968 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8969 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8972 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8975 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8976 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8977 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8978 if (*tunnel_header_v)
8979 *tunnel_header_m = vxlan_m->vni[0] |
8980 vxlan_m->vni[1] << 8 |
8981 vxlan_m->vni[2] << 16;
8983 *tunnel_header_m = 0x0;
8984 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8985 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8986 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8990 * Add VXLAN-GPE item to matcher and to the value.
8992 * @param[in, out] matcher
8994 * @param[in, out] key
8995 * Flow matcher value.
8997 * Flow pattern to translate.
8999 * Item is inner pattern.
9003 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9004 const struct rte_flow_item *item,
9005 const uint64_t pattern_flags)
9007 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9008 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9009 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9010 /* The item was validated to be on the outer side */
9011 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9012 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9014 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9016 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9018 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9020 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9021 int i, size = sizeof(vxlan_m->vni);
9022 uint8_t flags_m = 0xff;
9023 uint8_t flags_v = 0xc;
9024 uint8_t m_protocol, v_protocol;
9026 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9027 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9028 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9029 MLX5_UDP_PORT_VXLAN_GPE);
9032 vxlan_v = &dummy_vxlan_gpe_hdr;
9033 vxlan_m = &dummy_vxlan_gpe_hdr;
9036 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9038 memcpy(vni_m, vxlan_m->vni, size);
9039 for (i = 0; i < size; ++i)
9040 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9041 if (vxlan_m->flags) {
9042 flags_m = vxlan_m->flags;
9043 flags_v = vxlan_v->flags;
9045 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9046 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9047 m_protocol = vxlan_m->protocol;
9048 v_protocol = vxlan_v->protocol;
9050 /* Force next protocol to ensure next headers parsing. */
9051 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9052 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9053 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9054 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9055 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9056 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9060 MLX5_SET(fte_match_set_misc3, misc_m,
9061 outer_vxlan_gpe_next_protocol, m_protocol);
9062 MLX5_SET(fte_match_set_misc3, misc_v,
9063 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9067 * Add Geneve item to matcher and to the value.
9069 * @param[in, out] matcher
9071 * @param[in, out] key
9072 * Flow matcher value.
9074 * Flow pattern to translate.
9076 * Item is inner pattern.
9080 flow_dv_translate_item_geneve(void *matcher, void *key,
9081 const struct rte_flow_item *item,
9082 uint64_t pattern_flags)
9084 static const struct rte_flow_item_geneve empty_geneve = {0,};
9085 const struct rte_flow_item_geneve *geneve_m = item->mask;
9086 const struct rte_flow_item_geneve *geneve_v = item->spec;
9087 /* GENEVE flow item validation allows single tunnel item */
9088 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9089 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9090 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9091 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9094 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9095 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9096 size_t size = sizeof(geneve_m->vni), i;
9097 uint16_t protocol_m, protocol_v;
9099 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9101 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9102 MLX5_UDP_PORT_GENEVE);
9105 geneve_v = &empty_geneve;
9106 geneve_m = &empty_geneve;
9109 geneve_m = &rte_flow_item_geneve_mask;
9111 memcpy(vni_m, geneve_m->vni, size);
9112 for (i = 0; i < size; ++i)
9113 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9114 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9115 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9116 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9117 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9118 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9119 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9120 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9121 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9122 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9123 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9124 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9125 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9126 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9128 /* Force next protocol to prevent matchers duplication */
9129 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9131 protocol_m = 0xFFFF;
9133 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9134 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9135 protocol_m & protocol_v);
9139 * Create Geneve TLV option resource.
9141 * @param dev[in, out]
9142 * Pointer to rte_eth_dev structure.
9143 * @param[in, out] tag_be24
9144 * Tag value in big endian then R-shift 8.
9145 * @parm[in, out] dev_flow
9146 * Pointer to the dev_flow.
9148 * pointer to error structure.
9151 * 0 on success otherwise -errno and errno is set.
9155 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9156 const struct rte_flow_item *item,
9157 struct rte_flow_error *error)
9159 struct mlx5_priv *priv = dev->data->dev_private;
9160 struct mlx5_dev_ctx_shared *sh = priv->sh;
9161 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9162 sh->geneve_tlv_option_resource;
9163 struct mlx5_devx_obj *obj;
9164 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9169 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9170 if (geneve_opt_resource != NULL) {
9171 if (geneve_opt_resource->option_class ==
9172 geneve_opt_v->option_class &&
9173 geneve_opt_resource->option_type ==
9174 geneve_opt_v->option_type &&
9175 geneve_opt_resource->length ==
9176 geneve_opt_v->option_len) {
9177 /* We already have GENEVE TLV option obj allocated. */
9178 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9181 ret = rte_flow_error_set(error, ENOMEM,
9182 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9183 "Only one GENEVE TLV option supported");
9187 /* Create a GENEVE TLV object and resource. */
9188 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9189 geneve_opt_v->option_class,
9190 geneve_opt_v->option_type,
9191 geneve_opt_v->option_len);
9193 ret = rte_flow_error_set(error, ENODATA,
9194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9195 "Failed to create GENEVE TLV Devx object");
9198 sh->geneve_tlv_option_resource =
9199 mlx5_malloc(MLX5_MEM_ZERO,
9200 sizeof(*geneve_opt_resource),
9202 if (!sh->geneve_tlv_option_resource) {
9203 claim_zero(mlx5_devx_cmd_destroy(obj));
9204 ret = rte_flow_error_set(error, ENOMEM,
9205 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9206 "GENEVE TLV object memory allocation failed");
9209 geneve_opt_resource = sh->geneve_tlv_option_resource;
9210 geneve_opt_resource->obj = obj;
9211 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9212 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9213 geneve_opt_resource->length = geneve_opt_v->option_len;
9214 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9218 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9223 * Add Geneve TLV option item to matcher.
9225 * @param[in, out] dev
9226 * Pointer to rte_eth_dev structure.
9227 * @param[in, out] matcher
9229 * @param[in, out] key
9230 * Flow matcher value.
9232 * Flow pattern to translate.
9234 * Pointer to error structure.
9237 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9238 void *key, const struct rte_flow_item *item,
9239 struct rte_flow_error *error)
9241 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9242 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9243 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9244 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9245 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9247 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9248 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9254 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9255 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9258 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9262 * Set the option length in GENEVE header if not requested.
9263 * The GENEVE TLV option length is expressed by the option length field
9264 * in the GENEVE header.
9265 * If the option length was not requested but the GENEVE TLV option item
9266 * is present we set the option length field implicitly.
9268 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9269 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9270 MLX5_GENEVE_OPTLEN_MASK);
9271 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9272 geneve_opt_v->option_len + 1);
9274 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9275 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9277 if (geneve_opt_v->data) {
9278 memcpy(&opt_data_key, geneve_opt_v->data,
9279 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9280 sizeof(opt_data_key)));
9281 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9282 sizeof(opt_data_key));
9283 memcpy(&opt_data_mask, geneve_opt_m->data,
9284 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9285 sizeof(opt_data_mask)));
9286 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9287 sizeof(opt_data_mask));
9288 MLX5_SET(fte_match_set_misc3, misc3_m,
9289 geneve_tlv_option_0_data,
9290 rte_be_to_cpu_32(opt_data_mask));
9291 MLX5_SET(fte_match_set_misc3, misc3_v,
9292 geneve_tlv_option_0_data,
9293 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9299 * Add MPLS item to matcher and to the value.
9301 * @param[in, out] matcher
9303 * @param[in, out] key
9304 * Flow matcher value.
9306 * Flow pattern to translate.
9307 * @param[in] prev_layer
9308 * The protocol layer indicated in previous item.
9310 * Item is inner pattern.
9313 flow_dv_translate_item_mpls(void *matcher, void *key,
9314 const struct rte_flow_item *item,
9315 uint64_t prev_layer,
9318 const uint32_t *in_mpls_m = item->mask;
9319 const uint32_t *in_mpls_v = item->spec;
9320 uint32_t *out_mpls_m = 0;
9321 uint32_t *out_mpls_v = 0;
9322 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9323 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9324 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9326 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9327 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9328 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9330 switch (prev_layer) {
9331 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9332 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9333 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9336 MLX5_UDP_PORT_MPLS);
9339 case MLX5_FLOW_LAYER_GRE:
9341 case MLX5_FLOW_LAYER_GRE_KEY:
9342 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9343 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9345 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9346 RTE_ETHER_TYPE_MPLS);
9355 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9356 switch (prev_layer) {
9357 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9359 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9360 outer_first_mpls_over_udp);
9362 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9363 outer_first_mpls_over_udp);
9365 case MLX5_FLOW_LAYER_GRE:
9367 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9368 outer_first_mpls_over_gre);
9370 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9371 outer_first_mpls_over_gre);
9374 /* Inner MPLS not over GRE is not supported. */
9377 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9381 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9387 if (out_mpls_m && out_mpls_v) {
9388 *out_mpls_m = *in_mpls_m;
9389 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9394 * Add metadata register item to matcher
9396 * @param[in, out] matcher
9398 * @param[in, out] key
9399 * Flow matcher value.
9400 * @param[in] reg_type
9401 * Type of device metadata register
9408 flow_dv_match_meta_reg(void *matcher, void *key,
9409 enum modify_reg reg_type,
9410 uint32_t data, uint32_t mask)
9413 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9415 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9421 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9422 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9425 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9426 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9430 * The metadata register C0 field might be divided into
9431 * source vport index and META item value, we should set
9432 * this field according to specified mask, not as whole one.
9434 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9436 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9437 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9440 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9443 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9444 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9447 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9448 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9451 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9452 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9455 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9456 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9459 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9460 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9463 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9464 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9467 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9468 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9477 * Add MARK item to matcher
9480 * The device to configure through.
9481 * @param[in, out] matcher
9483 * @param[in, out] key
9484 * Flow matcher value.
9486 * Flow pattern to translate.
9489 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9490 void *matcher, void *key,
9491 const struct rte_flow_item *item)
9493 struct mlx5_priv *priv = dev->data->dev_private;
9494 const struct rte_flow_item_mark *mark;
9498 mark = item->mask ? (const void *)item->mask :
9499 &rte_flow_item_mark_mask;
9500 mask = mark->id & priv->sh->dv_mark_mask;
9501 mark = (const void *)item->spec;
9503 value = mark->id & priv->sh->dv_mark_mask & mask;
9505 enum modify_reg reg;
9507 /* Get the metadata register index for the mark. */
9508 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9509 MLX5_ASSERT(reg > 0);
9510 if (reg == REG_C_0) {
9511 struct mlx5_priv *priv = dev->data->dev_private;
9512 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9513 uint32_t shl_c0 = rte_bsf32(msk_c0);
9519 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9524 * Add META item to matcher
9527 * The devich to configure through.
9528 * @param[in, out] matcher
9530 * @param[in, out] key
9531 * Flow matcher value.
9533 * Attributes of flow that includes this item.
9535 * Flow pattern to translate.
9538 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9539 void *matcher, void *key,
9540 const struct rte_flow_attr *attr,
9541 const struct rte_flow_item *item)
9543 const struct rte_flow_item_meta *meta_m;
9544 const struct rte_flow_item_meta *meta_v;
9546 meta_m = (const void *)item->mask;
9548 meta_m = &rte_flow_item_meta_mask;
9549 meta_v = (const void *)item->spec;
9552 uint32_t value = meta_v->data;
9553 uint32_t mask = meta_m->data;
9555 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9558 MLX5_ASSERT(reg != REG_NON);
9559 if (reg == REG_C_0) {
9560 struct mlx5_priv *priv = dev->data->dev_private;
9561 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9562 uint32_t shl_c0 = rte_bsf32(msk_c0);
9568 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9573 * Add vport metadata Reg C0 item to matcher
9575 * @param[in, out] matcher
9577 * @param[in, out] key
9578 * Flow matcher value.
9580 * Flow pattern to translate.
9583 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9584 uint32_t value, uint32_t mask)
9586 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9590 * Add tag item to matcher
9593 * The devich to configure through.
9594 * @param[in, out] matcher
9596 * @param[in, out] key
9597 * Flow matcher value.
9599 * Flow pattern to translate.
9602 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9603 void *matcher, void *key,
9604 const struct rte_flow_item *item)
9606 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9607 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9608 uint32_t mask, value;
9611 value = tag_v->data;
9612 mask = tag_m ? tag_m->data : UINT32_MAX;
9613 if (tag_v->id == REG_C_0) {
9614 struct mlx5_priv *priv = dev->data->dev_private;
9615 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9616 uint32_t shl_c0 = rte_bsf32(msk_c0);
9622 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9626 * Add TAG item to matcher
9629 * The devich to configure through.
9630 * @param[in, out] matcher
9632 * @param[in, out] key
9633 * Flow matcher value.
9635 * Flow pattern to translate.
9638 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9639 void *matcher, void *key,
9640 const struct rte_flow_item *item)
9642 const struct rte_flow_item_tag *tag_v = item->spec;
9643 const struct rte_flow_item_tag *tag_m = item->mask;
9644 enum modify_reg reg;
9647 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9648 /* Get the metadata register index for the tag. */
9649 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9650 MLX5_ASSERT(reg > 0);
9651 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9655 * Add source vport match to the specified matcher.
9657 * @param[in, out] matcher
9659 * @param[in, out] key
9660 * Flow matcher value.
9662 * Source vport value to match
9667 flow_dv_translate_item_source_vport(void *matcher, void *key,
9668 int16_t port, uint16_t mask)
9670 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9671 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9673 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9674 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9678 * Translate port-id item to eswitch match on port-id.
9681 * The devich to configure through.
9682 * @param[in, out] matcher
9684 * @param[in, out] key
9685 * Flow matcher value.
9687 * Flow pattern to translate.
9692 * 0 on success, a negative errno value otherwise.
9695 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9696 void *key, const struct rte_flow_item *item,
9697 const struct rte_flow_attr *attr)
9699 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9700 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9701 struct mlx5_priv *priv;
9704 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9705 flow_dv_translate_item_source_vport(matcher, key,
9706 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9709 mask = pid_m ? pid_m->id : 0xffff;
9710 id = pid_v ? pid_v->id : dev->data->port_id;
9711 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9715 * Translate to vport field or to metadata, depending on mode.
9716 * Kernel can use either misc.source_port or half of C0 metadata
9719 if (priv->vport_meta_mask) {
9721 * Provide the hint for SW steering library
9722 * to insert the flow into ingress domain and
9723 * save the extra vport match.
9725 if (mask == 0xffff && priv->vport_id == 0xffff &&
9726 priv->pf_bond < 0 && attr->transfer)
9727 flow_dv_translate_item_source_vport
9728 (matcher, key, priv->vport_id, mask);
9730 * We should always set the vport metadata register,
9731 * otherwise the SW steering library can drop
9732 * the rule if wire vport metadata value is not zero,
9733 * it depends on kernel configuration.
9735 flow_dv_translate_item_meta_vport(matcher, key,
9736 priv->vport_meta_tag,
9737 priv->vport_meta_mask);
9739 flow_dv_translate_item_source_vport(matcher, key,
9740 priv->vport_id, mask);
9746 * Add ICMP6 item to matcher and to the value.
9748 * @param[in, out] matcher
9750 * @param[in, out] key
9751 * Flow matcher value.
9753 * Flow pattern to translate.
9755 * Item is inner pattern.
9758 flow_dv_translate_item_icmp6(void *matcher, void *key,
9759 const struct rte_flow_item *item,
9762 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9763 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9766 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9768 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9772 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9774 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9776 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9778 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9783 icmp6_m = &rte_flow_item_icmp6_mask;
9784 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9785 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9786 icmp6_v->type & icmp6_m->type);
9787 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9788 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9789 icmp6_v->code & icmp6_m->code);
9793 * Add ICMP item to matcher and to the value.
9795 * @param[in, out] matcher
9797 * @param[in, out] key
9798 * Flow matcher value.
9800 * Flow pattern to translate.
9802 * Item is inner pattern.
9805 flow_dv_translate_item_icmp(void *matcher, void *key,
9806 const struct rte_flow_item *item,
9809 const struct rte_flow_item_icmp *icmp_m = item->mask;
9810 const struct rte_flow_item_icmp *icmp_v = item->spec;
9811 uint32_t icmp_header_data_m = 0;
9812 uint32_t icmp_header_data_v = 0;
9815 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9817 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9819 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9821 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9823 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9825 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9827 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9832 icmp_m = &rte_flow_item_icmp_mask;
9833 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9834 icmp_m->hdr.icmp_type);
9835 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9836 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9837 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9838 icmp_m->hdr.icmp_code);
9839 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9840 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9841 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9842 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9843 if (icmp_header_data_m) {
9844 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9845 icmp_header_data_v |=
9846 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9847 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9848 icmp_header_data_m);
9849 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9850 icmp_header_data_v & icmp_header_data_m);
9855 * Add GTP item to matcher and to the value.
9857 * @param[in, out] matcher
9859 * @param[in, out] key
9860 * Flow matcher value.
9862 * Flow pattern to translate.
9864 * Item is inner pattern.
9867 flow_dv_translate_item_gtp(void *matcher, void *key,
9868 const struct rte_flow_item *item, int inner)
9870 const struct rte_flow_item_gtp *gtp_m = item->mask;
9871 const struct rte_flow_item_gtp *gtp_v = item->spec;
9874 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9876 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9877 uint16_t dport = RTE_GTPU_UDP_PORT;
9880 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9882 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9884 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9886 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9888 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9889 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9890 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9895 gtp_m = &rte_flow_item_gtp_mask;
9896 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9897 gtp_m->v_pt_rsv_flags);
9898 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9899 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9900 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9901 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9902 gtp_v->msg_type & gtp_m->msg_type);
9903 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9904 rte_be_to_cpu_32(gtp_m->teid));
9905 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9906 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9910 * Add GTP PSC item to matcher.
9912 * @param[in, out] matcher
9914 * @param[in, out] key
9915 * Flow matcher value.
9917 * Flow pattern to translate.
9920 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9921 const struct rte_flow_item *item)
9923 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9924 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9925 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9927 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9933 uint8_t next_ext_header_type;
9938 /* Always set E-flag match on one, regardless of GTP item settings. */
9939 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9940 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9941 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9942 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9943 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9944 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9945 /*Set next extension header type. */
9948 dw_2.next_ext_header_type = 0xff;
9949 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9950 rte_cpu_to_be_32(dw_2.w32));
9953 dw_2.next_ext_header_type = 0x85;
9954 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9955 rte_cpu_to_be_32(dw_2.w32));
9967 /*Set extension header PDU type and Qos. */
9969 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9971 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9972 dw_0.qfi = gtp_psc_m->hdr.qfi;
9973 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9974 rte_cpu_to_be_32(dw_0.w32));
9976 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9977 gtp_psc_m->hdr.type);
9978 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9979 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9980 rte_cpu_to_be_32(dw_0.w32));
9986 * Add eCPRI item to matcher and to the value.
9989 * The devich to configure through.
9990 * @param[in, out] matcher
9992 * @param[in, out] key
9993 * Flow matcher value.
9995 * Flow pattern to translate.
9996 * @param[in] last_item
10000 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10001 void *key, const struct rte_flow_item *item,
10002 uint64_t last_item)
10004 struct mlx5_priv *priv = dev->data->dev_private;
10005 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10006 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10007 struct rte_ecpri_common_hdr common;
10008 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10009 misc_parameters_4);
10010 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10016 * In case of eCPRI over Ethernet, if EtherType is not specified,
10017 * match on eCPRI EtherType implicitly.
10019 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10020 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10022 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10023 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10024 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10025 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10026 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10027 *(uint16_t *)l2m = UINT16_MAX;
10028 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10034 ecpri_m = &rte_flow_item_ecpri_mask;
10036 * Maximal four DW samples are supported in a single matching now.
10037 * Two are used now for a eCPRI matching:
10038 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10039 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10042 if (!ecpri_m->hdr.common.u32)
10044 samples = priv->sh->ecpri_parser.ids;
10045 /* Need to take the whole DW as the mask to fill the entry. */
10046 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10047 prog_sample_field_value_0);
10048 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10049 prog_sample_field_value_0);
10050 /* Already big endian (network order) in the header. */
10051 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10052 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10053 /* Sample#0, used for matching type, offset 0. */
10054 MLX5_SET(fte_match_set_misc4, misc4_m,
10055 prog_sample_field_id_0, samples[0]);
10056 /* It makes no sense to set the sample ID in the mask field. */
10057 MLX5_SET(fte_match_set_misc4, misc4_v,
10058 prog_sample_field_id_0, samples[0]);
10060 * Checking if message body part needs to be matched.
10061 * Some wildcard rules only matching type field should be supported.
10063 if (ecpri_m->hdr.dummy[0]) {
10064 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10065 switch (common.type) {
10066 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10067 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10068 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10069 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10070 prog_sample_field_value_1);
10071 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10072 prog_sample_field_value_1);
10073 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10074 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10075 ecpri_m->hdr.dummy[0];
10076 /* Sample#1, to match message body, offset 4. */
10077 MLX5_SET(fte_match_set_misc4, misc4_m,
10078 prog_sample_field_id_1, samples[1]);
10079 MLX5_SET(fte_match_set_misc4, misc4_v,
10080 prog_sample_field_id_1, samples[1]);
10083 /* Others, do not match any sample ID. */
10090 * Add connection tracking status item to matcher
10093 * The devich to configure through.
10094 * @param[in, out] matcher
10096 * @param[in, out] key
10097 * Flow matcher value.
10099 * Flow pattern to translate.
10102 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10103 void *matcher, void *key,
10104 const struct rte_flow_item *item)
10106 uint32_t reg_value = 0;
10108 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10109 uint32_t reg_mask = 0;
10110 const struct rte_flow_item_conntrack *spec = item->spec;
10111 const struct rte_flow_item_conntrack *mask = item->mask;
10113 struct rte_flow_error error;
10116 mask = &rte_flow_item_conntrack_mask;
10117 if (!spec || !mask->flags)
10119 flags = spec->flags & mask->flags;
10120 /* The conflict should be checked in the validation. */
10121 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10122 reg_value |= MLX5_CT_SYNDROME_VALID;
10123 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10124 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10125 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10126 reg_value |= MLX5_CT_SYNDROME_INVALID;
10127 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10128 reg_value |= MLX5_CT_SYNDROME_TRAP;
10129 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10130 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10131 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10132 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10133 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10135 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10136 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10137 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10138 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10139 /* The REG_C_x value could be saved during startup. */
10140 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10141 if (reg_id == REG_NON)
10143 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10144 reg_value, reg_mask);
10148 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10149 const struct rte_flow_item *item,
10150 struct mlx5_flow *dev_flow, bool is_inner)
10152 const struct rte_flow_item_flex *spec =
10153 (const struct rte_flow_item_flex *)item->spec;
10154 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10156 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10159 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10160 /* Don't count both inner and outer flex items in one rule. */
10161 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10162 MLX5_ASSERT(false);
10163 dev_flow->handle->flex_item |= RTE_BIT32(index);
10165 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10168 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10170 #define HEADER_IS_ZERO(match_criteria, headers) \
10171 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10172 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10175 * Calculate flow matcher enable bitmap.
10177 * @param match_criteria
10178 * Pointer to flow matcher criteria.
10181 * Bitmap of enabled fields.
10184 flow_dv_matcher_enable(uint32_t *match_criteria)
10186 uint8_t match_criteria_enable;
10188 match_criteria_enable =
10189 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10190 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10191 match_criteria_enable |=
10192 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10193 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10194 match_criteria_enable |=
10195 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10196 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10197 match_criteria_enable |=
10198 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10199 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10200 match_criteria_enable |=
10201 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10202 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10203 match_criteria_enable |=
10204 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10205 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10206 match_criteria_enable |=
10207 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10208 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10209 return match_criteria_enable;
10213 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10216 * Check flow matching criteria first, subtract misc5/4 length if flow
10217 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10218 * misc5/4 are not supported, and matcher creation failure is expected
10219 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10220 * misc5 is right after misc4.
10222 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10223 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10224 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10225 if (!(match_criteria & (1 <<
10226 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10227 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10232 static struct mlx5_list_entry *
10233 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10234 struct mlx5_list_entry *entry, void *cb_ctx)
10236 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10237 struct mlx5_flow_dv_matcher *ref = ctx->data;
10238 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10239 typeof(*tbl), tbl);
10240 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10245 rte_flow_error_set(ctx->error, ENOMEM,
10246 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10247 "cannot create matcher");
10250 memcpy(resource, entry, sizeof(*resource));
10251 resource->tbl = &tbl->tbl;
10252 return &resource->entry;
10256 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10257 struct mlx5_list_entry *entry)
10262 struct mlx5_list_entry *
10263 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10265 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10266 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10267 struct rte_eth_dev *dev = ctx->dev;
10268 struct mlx5_flow_tbl_data_entry *tbl_data;
10269 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10270 struct rte_flow_error *error = ctx->error;
10271 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10272 struct mlx5_flow_tbl_resource *tbl;
10277 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10279 rte_flow_error_set(error, ENOMEM,
10280 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10282 "cannot allocate flow table data entry");
10285 tbl_data->idx = idx;
10286 tbl_data->tunnel = tt_prm->tunnel;
10287 tbl_data->group_id = tt_prm->group_id;
10288 tbl_data->external = !!tt_prm->external;
10289 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10290 tbl_data->is_egress = !!key.is_egress;
10291 tbl_data->is_transfer = !!key.is_fdb;
10292 tbl_data->dummy = !!key.dummy;
10293 tbl_data->level = key.level;
10294 tbl_data->id = key.id;
10295 tbl = &tbl_data->tbl;
10297 return &tbl_data->entry;
10299 domain = sh->fdb_domain;
10300 else if (key.is_egress)
10301 domain = sh->tx_domain;
10303 domain = sh->rx_domain;
10304 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10306 rte_flow_error_set(error, ENOMEM,
10307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10308 NULL, "cannot create flow table object");
10309 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10312 if (key.level != 0) {
10313 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10314 (tbl->obj, &tbl_data->jump.action);
10316 rte_flow_error_set(error, ENOMEM,
10317 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10319 "cannot create flow jump action");
10320 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10321 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10325 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10326 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10327 key.level, key.id);
10328 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10329 flow_dv_matcher_create_cb,
10330 flow_dv_matcher_match_cb,
10331 flow_dv_matcher_remove_cb,
10332 flow_dv_matcher_clone_cb,
10333 flow_dv_matcher_clone_free_cb);
10334 if (!tbl_data->matchers) {
10335 rte_flow_error_set(error, ENOMEM,
10336 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10338 "cannot create tbl matcher list");
10339 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10340 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10341 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10344 return &tbl_data->entry;
10348 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10351 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10352 struct mlx5_flow_tbl_data_entry *tbl_data =
10353 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10354 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10356 return tbl_data->level != key.level ||
10357 tbl_data->id != key.id ||
10358 tbl_data->dummy != key.dummy ||
10359 tbl_data->is_transfer != !!key.is_fdb ||
10360 tbl_data->is_egress != !!key.is_egress;
10363 struct mlx5_list_entry *
10364 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10367 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10368 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10369 struct mlx5_flow_tbl_data_entry *tbl_data;
10370 struct rte_flow_error *error = ctx->error;
10373 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10375 rte_flow_error_set(error, ENOMEM,
10376 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10378 "cannot allocate flow table data entry");
10381 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10382 tbl_data->idx = idx;
10383 return &tbl_data->entry;
10387 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10389 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10390 struct mlx5_flow_tbl_data_entry *tbl_data =
10391 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10393 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10397 * Get a flow table.
10399 * @param[in, out] dev
10400 * Pointer to rte_eth_dev structure.
10401 * @param[in] table_level
10402 * Table level to use.
10403 * @param[in] egress
10404 * Direction of the table.
10405 * @param[in] transfer
10406 * E-Switch or NIC flow.
10408 * Dummy entry for dv API.
10409 * @param[in] table_id
10411 * @param[out] error
10412 * pointer to error structure.
10415 * Returns tables resource based on the index, NULL in case of failed.
10417 struct mlx5_flow_tbl_resource *
10418 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10419 uint32_t table_level, uint8_t egress,
10422 const struct mlx5_flow_tunnel *tunnel,
10423 uint32_t group_id, uint8_t dummy,
10425 struct rte_flow_error *error)
10427 struct mlx5_priv *priv = dev->data->dev_private;
10428 union mlx5_flow_tbl_key table_key = {
10430 .level = table_level,
10434 .is_fdb = !!transfer,
10435 .is_egress = !!egress,
10438 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10440 .group_id = group_id,
10441 .external = external,
10443 struct mlx5_flow_cb_ctx ctx = {
10446 .data = &table_key.v64,
10449 struct mlx5_list_entry *entry;
10450 struct mlx5_flow_tbl_data_entry *tbl_data;
10452 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10454 rte_flow_error_set(error, ENOMEM,
10455 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10456 "cannot get table");
10459 DRV_LOG(DEBUG, "table_level %u table_id %u "
10460 "tunnel %u group %u registered.",
10461 table_level, table_id,
10462 tunnel ? tunnel->tunnel_id : 0, group_id);
10463 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10464 return &tbl_data->tbl;
10468 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10470 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10471 struct mlx5_flow_tbl_data_entry *tbl_data =
10472 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10474 MLX5_ASSERT(entry && sh);
10475 if (tbl_data->jump.action)
10476 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10477 if (tbl_data->tbl.obj)
10478 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10479 if (tbl_data->tunnel_offload && tbl_data->external) {
10480 struct mlx5_list_entry *he;
10481 struct mlx5_hlist *tunnel_grp_hash;
10482 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10483 union tunnel_tbl_key tunnel_key = {
10484 .tunnel_id = tbl_data->tunnel ?
10485 tbl_data->tunnel->tunnel_id : 0,
10486 .group = tbl_data->group_id
10488 uint32_t table_level = tbl_data->level;
10489 struct mlx5_flow_cb_ctx ctx = {
10490 .data = (void *)&tunnel_key.val,
10493 tunnel_grp_hash = tbl_data->tunnel ?
10494 tbl_data->tunnel->groups :
10496 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10498 mlx5_hlist_unregister(tunnel_grp_hash, he);
10500 "table_level %u id %u tunnel %u group %u released.",
10504 tbl_data->tunnel->tunnel_id : 0,
10505 tbl_data->group_id);
10507 mlx5_list_destroy(tbl_data->matchers);
10508 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10512 * Release a flow table.
10515 * Pointer to device shared structure.
10517 * Table resource to be released.
10520 * Returns 0 if table was released, else return 1;
10523 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10524 struct mlx5_flow_tbl_resource *tbl)
10526 struct mlx5_flow_tbl_data_entry *tbl_data =
10527 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10531 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10535 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10536 struct mlx5_list_entry *entry, void *cb_ctx)
10538 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10539 struct mlx5_flow_dv_matcher *ref = ctx->data;
10540 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10543 return cur->crc != ref->crc ||
10544 cur->priority != ref->priority ||
10545 memcmp((const void *)cur->mask.buf,
10546 (const void *)ref->mask.buf, ref->mask.size);
10549 struct mlx5_list_entry *
10550 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10552 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10553 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10554 struct mlx5_flow_dv_matcher *ref = ctx->data;
10555 struct mlx5_flow_dv_matcher *resource;
10556 struct mlx5dv_flow_matcher_attr dv_attr = {
10557 .type = IBV_FLOW_ATTR_NORMAL,
10558 .match_mask = (void *)&ref->mask,
10560 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10561 typeof(*tbl), tbl);
10564 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10567 rte_flow_error_set(ctx->error, ENOMEM,
10568 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10569 "cannot create matcher");
10573 dv_attr.match_criteria_enable =
10574 flow_dv_matcher_enable(resource->mask.buf);
10575 __flow_dv_adjust_buf_size(&ref->mask.size,
10576 dv_attr.match_criteria_enable);
10577 dv_attr.priority = ref->priority;
10578 if (tbl->is_egress)
10579 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10580 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10582 &resource->matcher_object);
10584 mlx5_free(resource);
10585 rte_flow_error_set(ctx->error, ENOMEM,
10586 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10587 "cannot create matcher");
10590 return &resource->entry;
10594 * Register the flow matcher.
10596 * @param[in, out] dev
10597 * Pointer to rte_eth_dev structure.
10598 * @param[in, out] matcher
10599 * Pointer to flow matcher.
10600 * @param[in, out] key
10601 * Pointer to flow table key.
10602 * @parm[in, out] dev_flow
10603 * Pointer to the dev_flow.
10604 * @param[out] error
10605 * pointer to error structure.
10608 * 0 on success otherwise -errno and errno is set.
10611 flow_dv_matcher_register(struct rte_eth_dev *dev,
10612 struct mlx5_flow_dv_matcher *ref,
10613 union mlx5_flow_tbl_key *key,
10614 struct mlx5_flow *dev_flow,
10615 const struct mlx5_flow_tunnel *tunnel,
10617 struct rte_flow_error *error)
10619 struct mlx5_list_entry *entry;
10620 struct mlx5_flow_dv_matcher *resource;
10621 struct mlx5_flow_tbl_resource *tbl;
10622 struct mlx5_flow_tbl_data_entry *tbl_data;
10623 struct mlx5_flow_cb_ctx ctx = {
10628 * tunnel offload API requires this registration for cases when
10629 * tunnel match rule was inserted before tunnel set rule.
10631 tbl = flow_dv_tbl_resource_get(dev, key->level,
10632 key->is_egress, key->is_fdb,
10633 dev_flow->external, tunnel,
10634 group_id, 0, key->id, error);
10636 return -rte_errno; /* No need to refill the error info */
10637 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10639 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10641 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10642 return rte_flow_error_set(error, ENOMEM,
10643 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10644 "cannot allocate ref memory");
10646 resource = container_of(entry, typeof(*resource), entry);
10647 dev_flow->handle->dvh.matcher = resource;
10651 struct mlx5_list_entry *
10652 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10656 struct mlx5_flow_dv_tag_resource *entry;
10660 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10662 rte_flow_error_set(ctx->error, ENOMEM,
10663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10664 "cannot allocate resource memory");
10668 entry->tag_id = *(uint32_t *)(ctx->data);
10669 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10672 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10673 rte_flow_error_set(ctx->error, ENOMEM,
10674 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10675 NULL, "cannot create action");
10678 return &entry->entry;
10682 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10685 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10686 struct mlx5_flow_dv_tag_resource *tag =
10687 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10689 return *(uint32_t *)(ctx->data) != tag->tag_id;
10692 struct mlx5_list_entry *
10693 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10696 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10697 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10698 struct mlx5_flow_dv_tag_resource *entry;
10701 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10703 rte_flow_error_set(ctx->error, ENOMEM,
10704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10705 "cannot allocate tag resource memory");
10708 memcpy(entry, oentry, sizeof(*entry));
10710 return &entry->entry;
10714 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10716 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10717 struct mlx5_flow_dv_tag_resource *tag =
10718 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10720 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10724 * Find existing tag resource or create and register a new one.
10726 * @param dev[in, out]
10727 * Pointer to rte_eth_dev structure.
10728 * @param[in, out] tag_be24
10729 * Tag value in big endian then R-shift 8.
10730 * @parm[in, out] dev_flow
10731 * Pointer to the dev_flow.
10732 * @param[out] error
10733 * pointer to error structure.
10736 * 0 on success otherwise -errno and errno is set.
10739 flow_dv_tag_resource_register
10740 (struct rte_eth_dev *dev,
10742 struct mlx5_flow *dev_flow,
10743 struct rte_flow_error *error)
10745 struct mlx5_priv *priv = dev->data->dev_private;
10746 struct mlx5_flow_dv_tag_resource *resource;
10747 struct mlx5_list_entry *entry;
10748 struct mlx5_flow_cb_ctx ctx = {
10752 struct mlx5_hlist *tag_table;
10754 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10756 MLX5_TAGS_HLIST_ARRAY_SIZE,
10757 false, false, priv->sh,
10758 flow_dv_tag_create_cb,
10759 flow_dv_tag_match_cb,
10760 flow_dv_tag_remove_cb,
10761 flow_dv_tag_clone_cb,
10762 flow_dv_tag_clone_free_cb);
10763 if (unlikely(!tag_table))
10765 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10767 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10769 dev_flow->handle->dvh.rix_tag = resource->idx;
10770 dev_flow->dv.tag_resource = resource;
10777 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10779 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10780 struct mlx5_flow_dv_tag_resource *tag =
10781 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10783 MLX5_ASSERT(tag && sh && tag->action);
10784 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10785 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10786 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10793 * Pointer to Ethernet device.
10798 * 1 while a reference on it exists, 0 when freed.
10801 flow_dv_tag_release(struct rte_eth_dev *dev,
10804 struct mlx5_priv *priv = dev->data->dev_private;
10805 struct mlx5_flow_dv_tag_resource *tag;
10807 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10810 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10811 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10812 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10816 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10819 * Pointer to rte_eth_dev structure.
10820 * @param[in] action
10821 * Pointer to action PORT_ID / REPRESENTED_PORT.
10822 * @param[out] dst_port_id
10823 * The target port ID.
10824 * @param[out] error
10825 * Pointer to the error structure.
10828 * 0 on success, a negative errno value otherwise and rte_errno is set.
10831 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10832 const struct rte_flow_action *action,
10833 uint32_t *dst_port_id,
10834 struct rte_flow_error *error)
10837 struct mlx5_priv *priv;
10839 switch (action->type) {
10840 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10841 const struct rte_flow_action_port_id *conf;
10843 conf = (const struct rte_flow_action_port_id *)action->conf;
10844 port = conf->original ? dev->data->port_id : conf->id;
10847 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10848 const struct rte_flow_action_ethdev *ethdev;
10850 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10851 port = ethdev->port_id;
10855 MLX5_ASSERT(false);
10856 return rte_flow_error_set(error, EINVAL,
10857 RTE_FLOW_ERROR_TYPE_ACTION, action,
10858 "unknown E-Switch action");
10861 priv = mlx5_port_to_eswitch_info(port, false);
10863 return rte_flow_error_set(error, -rte_errno,
10864 RTE_FLOW_ERROR_TYPE_ACTION,
10866 "No eswitch info was found for port");
10867 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10869 * This parameter is transferred to
10870 * mlx5dv_dr_action_create_dest_ib_port().
10872 *dst_port_id = priv->dev_port;
10875 * Legacy mode, no LAG configurations is supported.
10876 * This parameter is transferred to
10877 * mlx5dv_dr_action_create_dest_vport().
10879 *dst_port_id = priv->vport_id;
10885 * Create a counter with aging configuration.
10888 * Pointer to rte_eth_dev structure.
10889 * @param[in] dev_flow
10890 * Pointer to the mlx5_flow.
10891 * @param[out] count
10892 * Pointer to the counter action configuration.
10894 * Pointer to the aging action configuration.
10897 * Index to flow counter on success, 0 otherwise.
10900 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10901 struct mlx5_flow *dev_flow,
10902 const struct rte_flow_action_count *count
10904 const struct rte_flow_action_age *age)
10907 struct mlx5_age_param *age_param;
10909 counter = flow_dv_counter_alloc(dev, !!age);
10910 if (!counter || age == NULL)
10912 age_param = flow_dv_counter_idx_get_age(dev, counter);
10913 age_param->context = age->context ? age->context :
10914 (void *)(uintptr_t)(dev_flow->flow_idx);
10915 age_param->timeout = age->timeout;
10916 age_param->port_id = dev->data->port_id;
10917 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10918 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10923 * Add Tx queue matcher
10926 * Pointer to the dev struct.
10927 * @param[in, out] matcher
10929 * @param[in, out] key
10930 * Flow matcher value.
10932 * Flow pattern to translate.
10934 * Item is inner pattern.
10937 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10938 void *matcher, void *key,
10939 const struct rte_flow_item *item)
10941 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10942 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10944 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10946 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10947 struct mlx5_txq_ctrl *txq;
10948 uint32_t queue, mask;
10950 queue_m = (const void *)item->mask;
10951 queue_v = (const void *)item->spec;
10954 txq = mlx5_txq_get(dev, queue_v->queue);
10957 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10958 queue = txq->obj->sq->id;
10960 queue = txq->obj->sq_obj.sq->id;
10961 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10962 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10963 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10964 mlx5_txq_release(dev, queue_v->queue);
10968 * Set the hash fields according to the @p flow information.
10970 * @param[in] dev_flow
10971 * Pointer to the mlx5_flow.
10972 * @param[in] rss_desc
10973 * Pointer to the mlx5_flow_rss_desc.
10976 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10977 struct mlx5_flow_rss_desc *rss_desc)
10979 uint64_t items = dev_flow->handle->layers;
10981 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10983 dev_flow->hash_fields = 0;
10984 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10985 if (rss_desc->level >= 2)
10988 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10989 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10990 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10991 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10992 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10993 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10994 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10996 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10998 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10999 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
11000 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11001 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11002 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
11003 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11004 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
11006 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
11009 if (dev_flow->hash_fields == 0)
11011 * There is no match between the RSS types and the
11012 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11015 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11016 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
11017 if (rss_types & RTE_ETH_RSS_UDP) {
11018 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11019 dev_flow->hash_fields |=
11020 IBV_RX_HASH_SRC_PORT_UDP;
11021 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11022 dev_flow->hash_fields |=
11023 IBV_RX_HASH_DST_PORT_UDP;
11025 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
11027 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11028 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
11029 if (rss_types & RTE_ETH_RSS_TCP) {
11030 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11031 dev_flow->hash_fields |=
11032 IBV_RX_HASH_SRC_PORT_TCP;
11033 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11034 dev_flow->hash_fields |=
11035 IBV_RX_HASH_DST_PORT_TCP;
11037 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11041 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11045 * Prepare an Rx Hash queue.
11048 * Pointer to Ethernet device.
11049 * @param[in] dev_flow
11050 * Pointer to the mlx5_flow.
11051 * @param[in] rss_desc
11052 * Pointer to the mlx5_flow_rss_desc.
11053 * @param[out] hrxq_idx
11054 * Hash Rx queue index.
11057 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11059 static struct mlx5_hrxq *
11060 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11061 struct mlx5_flow *dev_flow,
11062 struct mlx5_flow_rss_desc *rss_desc,
11063 uint32_t *hrxq_idx)
11065 struct mlx5_priv *priv = dev->data->dev_private;
11066 struct mlx5_flow_handle *dh = dev_flow->handle;
11067 struct mlx5_hrxq *hrxq;
11069 MLX5_ASSERT(rss_desc->queue_num);
11070 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11071 rss_desc->hash_fields = dev_flow->hash_fields;
11072 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11073 rss_desc->shared_rss = 0;
11074 if (rss_desc->hash_fields == 0)
11075 rss_desc->queue_num = 1;
11076 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11079 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11085 * Release sample sub action resource.
11087 * @param[in, out] dev
11088 * Pointer to rte_eth_dev structure.
11089 * @param[in] act_res
11090 * Pointer to sample sub action resource.
11093 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11094 struct mlx5_flow_sub_actions_idx *act_res)
11096 if (act_res->rix_hrxq) {
11097 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11098 act_res->rix_hrxq = 0;
11100 if (act_res->rix_encap_decap) {
11101 flow_dv_encap_decap_resource_release(dev,
11102 act_res->rix_encap_decap);
11103 act_res->rix_encap_decap = 0;
11105 if (act_res->rix_port_id_action) {
11106 flow_dv_port_id_action_resource_release(dev,
11107 act_res->rix_port_id_action);
11108 act_res->rix_port_id_action = 0;
11110 if (act_res->rix_tag) {
11111 flow_dv_tag_release(dev, act_res->rix_tag);
11112 act_res->rix_tag = 0;
11114 if (act_res->rix_jump) {
11115 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11116 act_res->rix_jump = 0;
11121 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11122 struct mlx5_list_entry *entry, void *cb_ctx)
11124 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11125 struct rte_eth_dev *dev = ctx->dev;
11126 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11127 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11131 if (ctx_resource->ratio == resource->ratio &&
11132 ctx_resource->ft_type == resource->ft_type &&
11133 ctx_resource->ft_id == resource->ft_id &&
11134 ctx_resource->set_action == resource->set_action &&
11135 !memcmp((void *)&ctx_resource->sample_act,
11136 (void *)&resource->sample_act,
11137 sizeof(struct mlx5_flow_sub_actions_list))) {
11139 * Existing sample action should release the prepared
11140 * sub-actions reference counter.
11142 flow_dv_sample_sub_actions_release(dev,
11143 &ctx_resource->sample_idx);
11149 struct mlx5_list_entry *
11150 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11152 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11153 struct rte_eth_dev *dev = ctx->dev;
11154 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11155 void **sample_dv_actions = ctx_resource->sub_actions;
11156 struct mlx5_flow_dv_sample_resource *resource;
11157 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11158 struct mlx5_priv *priv = dev->data->dev_private;
11159 struct mlx5_dev_ctx_shared *sh = priv->sh;
11160 struct mlx5_flow_tbl_resource *tbl;
11162 const uint32_t next_ft_step = 1;
11163 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11164 uint8_t is_egress = 0;
11165 uint8_t is_transfer = 0;
11166 struct rte_flow_error *error = ctx->error;
11168 /* Register new sample resource. */
11169 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11171 rte_flow_error_set(error, ENOMEM,
11172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11174 "cannot allocate resource memory");
11177 *resource = *ctx_resource;
11178 /* Create normal path table level */
11179 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11181 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11183 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11184 is_egress, is_transfer,
11185 true, NULL, 0, 0, 0, error);
11187 rte_flow_error_set(error, ENOMEM,
11188 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11190 "fail to create normal path table "
11194 resource->normal_path_tbl = tbl;
11195 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11196 if (!sh->default_miss_action) {
11197 rte_flow_error_set(error, ENOMEM,
11198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11200 "default miss action was not "
11204 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11205 sh->default_miss_action;
11207 /* Create a DR sample action */
11208 sampler_attr.sample_ratio = resource->ratio;
11209 sampler_attr.default_next_table = tbl->obj;
11210 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11211 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11212 &sample_dv_actions[0];
11213 sampler_attr.action = resource->set_action;
11214 if (mlx5_os_flow_dr_create_flow_action_sampler
11215 (&sampler_attr, &resource->verbs_action)) {
11216 rte_flow_error_set(error, ENOMEM,
11217 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11218 NULL, "cannot create sample action");
11221 resource->idx = idx;
11222 resource->dev = dev;
11223 return &resource->entry;
11225 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11226 flow_dv_sample_sub_actions_release(dev,
11227 &resource->sample_idx);
11228 if (resource->normal_path_tbl)
11229 flow_dv_tbl_resource_release(MLX5_SH(dev),
11230 resource->normal_path_tbl);
11231 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11236 struct mlx5_list_entry *
11237 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11238 struct mlx5_list_entry *entry __rte_unused,
11241 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11242 struct rte_eth_dev *dev = ctx->dev;
11243 struct mlx5_flow_dv_sample_resource *resource;
11244 struct mlx5_priv *priv = dev->data->dev_private;
11245 struct mlx5_dev_ctx_shared *sh = priv->sh;
11248 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11250 rte_flow_error_set(ctx->error, ENOMEM,
11251 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11253 "cannot allocate resource memory");
11256 memcpy(resource, entry, sizeof(*resource));
11257 resource->idx = idx;
11258 resource->dev = dev;
11259 return &resource->entry;
11263 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11264 struct mlx5_list_entry *entry)
11266 struct mlx5_flow_dv_sample_resource *resource =
11267 container_of(entry, typeof(*resource), entry);
11268 struct rte_eth_dev *dev = resource->dev;
11269 struct mlx5_priv *priv = dev->data->dev_private;
11271 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11275 * Find existing sample resource or create and register a new one.
11277 * @param[in, out] dev
11278 * Pointer to rte_eth_dev structure.
11280 * Pointer to sample resource reference.
11281 * @parm[in, out] dev_flow
11282 * Pointer to the dev_flow.
11283 * @param[out] error
11284 * pointer to error structure.
11287 * 0 on success otherwise -errno and errno is set.
11290 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11291 struct mlx5_flow_dv_sample_resource *ref,
11292 struct mlx5_flow *dev_flow,
11293 struct rte_flow_error *error)
11295 struct mlx5_flow_dv_sample_resource *resource;
11296 struct mlx5_list_entry *entry;
11297 struct mlx5_priv *priv = dev->data->dev_private;
11298 struct mlx5_flow_cb_ctx ctx = {
11304 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11307 resource = container_of(entry, typeof(*resource), entry);
11308 dev_flow->handle->dvh.rix_sample = resource->idx;
11309 dev_flow->dv.sample_res = resource;
11314 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11315 struct mlx5_list_entry *entry, void *cb_ctx)
11317 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11318 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11319 struct rte_eth_dev *dev = ctx->dev;
11320 struct mlx5_flow_dv_dest_array_resource *resource =
11321 container_of(entry, typeof(*resource), entry);
11324 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11325 ctx_resource->ft_type == resource->ft_type &&
11326 !memcmp((void *)resource->sample_act,
11327 (void *)ctx_resource->sample_act,
11328 (ctx_resource->num_of_dest *
11329 sizeof(struct mlx5_flow_sub_actions_list)))) {
11331 * Existing sample action should release the prepared
11332 * sub-actions reference counter.
11334 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11335 flow_dv_sample_sub_actions_release(dev,
11336 &ctx_resource->sample_idx[idx]);
11342 struct mlx5_list_entry *
11343 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11345 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11346 struct rte_eth_dev *dev = ctx->dev;
11347 struct mlx5_flow_dv_dest_array_resource *resource;
11348 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11349 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11350 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11351 struct mlx5_priv *priv = dev->data->dev_private;
11352 struct mlx5_dev_ctx_shared *sh = priv->sh;
11353 struct mlx5_flow_sub_actions_list *sample_act;
11354 struct mlx5dv_dr_domain *domain;
11355 uint32_t idx = 0, res_idx = 0;
11356 struct rte_flow_error *error = ctx->error;
11357 uint64_t action_flags;
11360 /* Register new destination array resource. */
11361 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11364 rte_flow_error_set(error, ENOMEM,
11365 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11367 "cannot allocate resource memory");
11370 *resource = *ctx_resource;
11371 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11372 domain = sh->fdb_domain;
11373 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11374 domain = sh->rx_domain;
11376 domain = sh->tx_domain;
11377 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11378 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11379 mlx5_malloc(MLX5_MEM_ZERO,
11380 sizeof(struct mlx5dv_dr_action_dest_attr),
11382 if (!dest_attr[idx]) {
11383 rte_flow_error_set(error, ENOMEM,
11384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11386 "cannot allocate resource memory");
11389 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11390 sample_act = &ctx_resource->sample_act[idx];
11391 action_flags = sample_act->action_flags;
11392 switch (action_flags) {
11393 case MLX5_FLOW_ACTION_QUEUE:
11394 dest_attr[idx]->dest = sample_act->dr_queue_action;
11396 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11397 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11398 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11399 dest_attr[idx]->dest_reformat->reformat =
11400 sample_act->dr_encap_action;
11401 dest_attr[idx]->dest_reformat->dest =
11402 sample_act->dr_port_id_action;
11404 case MLX5_FLOW_ACTION_PORT_ID:
11405 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11407 case MLX5_FLOW_ACTION_JUMP:
11408 dest_attr[idx]->dest = sample_act->dr_jump_action;
11411 rte_flow_error_set(error, EINVAL,
11412 RTE_FLOW_ERROR_TYPE_ACTION,
11414 "unsupported actions type");
11418 /* create a dest array action */
11419 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11421 resource->num_of_dest,
11423 &resource->action);
11425 rte_flow_error_set(error, ENOMEM,
11426 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11428 "cannot create destination array action");
11431 resource->idx = res_idx;
11432 resource->dev = dev;
11433 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11434 mlx5_free(dest_attr[idx]);
11435 return &resource->entry;
11437 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11438 flow_dv_sample_sub_actions_release(dev,
11439 &resource->sample_idx[idx]);
11440 if (dest_attr[idx])
11441 mlx5_free(dest_attr[idx]);
11443 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11447 struct mlx5_list_entry *
11448 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11449 struct mlx5_list_entry *entry __rte_unused,
11452 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11453 struct rte_eth_dev *dev = ctx->dev;
11454 struct mlx5_flow_dv_dest_array_resource *resource;
11455 struct mlx5_priv *priv = dev->data->dev_private;
11456 struct mlx5_dev_ctx_shared *sh = priv->sh;
11457 uint32_t res_idx = 0;
11458 struct rte_flow_error *error = ctx->error;
11460 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11463 rte_flow_error_set(error, ENOMEM,
11464 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11466 "cannot allocate dest-array memory");
11469 memcpy(resource, entry, sizeof(*resource));
11470 resource->idx = res_idx;
11471 resource->dev = dev;
11472 return &resource->entry;
11476 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11477 struct mlx5_list_entry *entry)
11479 struct mlx5_flow_dv_dest_array_resource *resource =
11480 container_of(entry, typeof(*resource), entry);
11481 struct rte_eth_dev *dev = resource->dev;
11482 struct mlx5_priv *priv = dev->data->dev_private;
11484 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11488 * Find existing destination array resource or create and register a new one.
11490 * @param[in, out] dev
11491 * Pointer to rte_eth_dev structure.
11493 * Pointer to destination array resource reference.
11494 * @parm[in, out] dev_flow
11495 * Pointer to the dev_flow.
11496 * @param[out] error
11497 * pointer to error structure.
11500 * 0 on success otherwise -errno and errno is set.
11503 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11504 struct mlx5_flow_dv_dest_array_resource *ref,
11505 struct mlx5_flow *dev_flow,
11506 struct rte_flow_error *error)
11508 struct mlx5_flow_dv_dest_array_resource *resource;
11509 struct mlx5_priv *priv = dev->data->dev_private;
11510 struct mlx5_list_entry *entry;
11511 struct mlx5_flow_cb_ctx ctx = {
11517 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11520 resource = container_of(entry, typeof(*resource), entry);
11521 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11522 dev_flow->dv.dest_array_res = resource;
11527 * Convert Sample action to DV specification.
11530 * Pointer to rte_eth_dev structure.
11531 * @param[in] action
11532 * Pointer to sample action structure.
11533 * @param[in, out] dev_flow
11534 * Pointer to the mlx5_flow.
11536 * Pointer to the flow attributes.
11537 * @param[in, out] num_of_dest
11538 * Pointer to the num of destination.
11539 * @param[in, out] sample_actions
11540 * Pointer to sample actions list.
11541 * @param[in, out] res
11542 * Pointer to sample resource.
11543 * @param[out] error
11544 * Pointer to the error structure.
11547 * 0 on success, a negative errno value otherwise and rte_errno is set.
11550 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11551 const struct rte_flow_action_sample *action,
11552 struct mlx5_flow *dev_flow,
11553 const struct rte_flow_attr *attr,
11554 uint32_t *num_of_dest,
11555 void **sample_actions,
11556 struct mlx5_flow_dv_sample_resource *res,
11557 struct rte_flow_error *error)
11559 struct mlx5_priv *priv = dev->data->dev_private;
11560 const struct rte_flow_action *sub_actions;
11561 struct mlx5_flow_sub_actions_list *sample_act;
11562 struct mlx5_flow_sub_actions_idx *sample_idx;
11563 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11564 struct rte_flow *flow = dev_flow->flow;
11565 struct mlx5_flow_rss_desc *rss_desc;
11566 uint64_t action_flags = 0;
11569 rss_desc = &wks->rss_desc;
11570 sample_act = &res->sample_act;
11571 sample_idx = &res->sample_idx;
11572 res->ratio = action->ratio;
11573 sub_actions = action->actions;
11574 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11575 int type = sub_actions->type;
11576 uint32_t pre_rix = 0;
11579 case RTE_FLOW_ACTION_TYPE_QUEUE:
11581 const struct rte_flow_action_queue *queue;
11582 struct mlx5_hrxq *hrxq;
11585 queue = sub_actions->conf;
11586 rss_desc->queue_num = 1;
11587 rss_desc->queue[0] = queue->index;
11588 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11589 rss_desc, &hrxq_idx);
11591 return rte_flow_error_set
11593 RTE_FLOW_ERROR_TYPE_ACTION,
11595 "cannot create fate queue");
11596 sample_act->dr_queue_action = hrxq->action;
11597 sample_idx->rix_hrxq = hrxq_idx;
11598 sample_actions[sample_act->actions_num++] =
11601 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11602 if (action_flags & MLX5_FLOW_ACTION_MARK)
11603 dev_flow->handle->rix_hrxq = hrxq_idx;
11604 dev_flow->handle->fate_action =
11605 MLX5_FLOW_FATE_QUEUE;
11608 case RTE_FLOW_ACTION_TYPE_RSS:
11610 struct mlx5_hrxq *hrxq;
11612 const struct rte_flow_action_rss *rss;
11613 const uint8_t *rss_key;
11615 rss = sub_actions->conf;
11616 memcpy(rss_desc->queue, rss->queue,
11617 rss->queue_num * sizeof(uint16_t));
11618 rss_desc->queue_num = rss->queue_num;
11619 /* NULL RSS key indicates default RSS key. */
11620 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11621 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11623 * rss->level and rss.types should be set in advance
11624 * when expanding items for RSS.
11626 flow_dv_hashfields_set(dev_flow, rss_desc);
11627 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11628 rss_desc, &hrxq_idx);
11630 return rte_flow_error_set
11632 RTE_FLOW_ERROR_TYPE_ACTION,
11634 "cannot create fate queue");
11635 sample_act->dr_queue_action = hrxq->action;
11636 sample_idx->rix_hrxq = hrxq_idx;
11637 sample_actions[sample_act->actions_num++] =
11640 action_flags |= MLX5_FLOW_ACTION_RSS;
11641 if (action_flags & MLX5_FLOW_ACTION_MARK)
11642 dev_flow->handle->rix_hrxq = hrxq_idx;
11643 dev_flow->handle->fate_action =
11644 MLX5_FLOW_FATE_QUEUE;
11647 case RTE_FLOW_ACTION_TYPE_MARK:
11649 uint32_t tag_be = mlx5_flow_mark_set
11650 (((const struct rte_flow_action_mark *)
11651 (sub_actions->conf))->id);
11654 pre_rix = dev_flow->handle->dvh.rix_tag;
11655 /* Save the mark resource before sample */
11656 pre_r = dev_flow->dv.tag_resource;
11657 if (flow_dv_tag_resource_register(dev, tag_be,
11660 MLX5_ASSERT(dev_flow->dv.tag_resource);
11661 sample_act->dr_tag_action =
11662 dev_flow->dv.tag_resource->action;
11663 sample_idx->rix_tag =
11664 dev_flow->handle->dvh.rix_tag;
11665 sample_actions[sample_act->actions_num++] =
11666 sample_act->dr_tag_action;
11667 /* Recover the mark resource after sample */
11668 dev_flow->dv.tag_resource = pre_r;
11669 dev_flow->handle->dvh.rix_tag = pre_rix;
11670 action_flags |= MLX5_FLOW_ACTION_MARK;
11673 case RTE_FLOW_ACTION_TYPE_COUNT:
11675 if (!flow->counter) {
11677 flow_dv_translate_create_counter(dev,
11678 dev_flow, sub_actions->conf,
11680 if (!flow->counter)
11681 return rte_flow_error_set
11683 RTE_FLOW_ERROR_TYPE_ACTION,
11685 "cannot create counter"
11688 sample_act->dr_cnt_action =
11689 (flow_dv_counter_get_by_idx(dev,
11690 flow->counter, NULL))->action;
11691 sample_actions[sample_act->actions_num++] =
11692 sample_act->dr_cnt_action;
11693 action_flags |= MLX5_FLOW_ACTION_COUNT;
11696 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11697 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11699 struct mlx5_flow_dv_port_id_action_resource
11701 uint32_t port_id = 0;
11703 memset(&port_id_resource, 0, sizeof(port_id_resource));
11704 /* Save the port id resource before sample */
11705 pre_rix = dev_flow->handle->rix_port_id_action;
11706 pre_r = dev_flow->dv.port_id_action;
11707 if (flow_dv_translate_action_port_id(dev, sub_actions,
11710 port_id_resource.port_id = port_id;
11711 if (flow_dv_port_id_action_resource_register
11712 (dev, &port_id_resource, dev_flow, error))
11714 sample_act->dr_port_id_action =
11715 dev_flow->dv.port_id_action->action;
11716 sample_idx->rix_port_id_action =
11717 dev_flow->handle->rix_port_id_action;
11718 sample_actions[sample_act->actions_num++] =
11719 sample_act->dr_port_id_action;
11720 /* Recover the port id resource after sample */
11721 dev_flow->dv.port_id_action = pre_r;
11722 dev_flow->handle->rix_port_id_action = pre_rix;
11724 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11727 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11728 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11729 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11730 /* Save the encap resource before sample */
11731 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11732 pre_r = dev_flow->dv.encap_decap;
11733 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11738 sample_act->dr_encap_action =
11739 dev_flow->dv.encap_decap->action;
11740 sample_idx->rix_encap_decap =
11741 dev_flow->handle->dvh.rix_encap_decap;
11742 sample_actions[sample_act->actions_num++] =
11743 sample_act->dr_encap_action;
11744 /* Recover the encap resource after sample */
11745 dev_flow->dv.encap_decap = pre_r;
11746 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11747 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11750 return rte_flow_error_set(error, EINVAL,
11751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11753 "Not support for sampler action");
11756 sample_act->action_flags = action_flags;
11757 res->ft_id = dev_flow->dv.group;
11758 if (attr->transfer) {
11760 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11761 uint64_t set_action;
11762 } action_ctx = { .set_action = 0 };
11764 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11765 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11766 MLX5_MODIFICATION_TYPE_SET);
11767 MLX5_SET(set_action_in, action_ctx.action_in, field,
11768 MLX5_MODI_META_REG_C_0);
11769 MLX5_SET(set_action_in, action_ctx.action_in, data,
11770 priv->vport_meta_tag);
11771 res->set_action = action_ctx.set_action;
11772 } else if (attr->ingress) {
11773 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11775 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11781 * Convert Sample action to DV specification.
11784 * Pointer to rte_eth_dev structure.
11785 * @param[in, out] dev_flow
11786 * Pointer to the mlx5_flow.
11787 * @param[in] num_of_dest
11788 * The num of destination.
11789 * @param[in, out] res
11790 * Pointer to sample resource.
11791 * @param[in, out] mdest_res
11792 * Pointer to destination array resource.
11793 * @param[in] sample_actions
11794 * Pointer to sample path actions list.
11795 * @param[in] action_flags
11796 * Holds the actions detected until now.
11797 * @param[out] error
11798 * Pointer to the error structure.
11801 * 0 on success, a negative errno value otherwise and rte_errno is set.
11804 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11805 struct mlx5_flow *dev_flow,
11806 uint32_t num_of_dest,
11807 struct mlx5_flow_dv_sample_resource *res,
11808 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11809 void **sample_actions,
11810 uint64_t action_flags,
11811 struct rte_flow_error *error)
11813 /* update normal path action resource into last index of array */
11814 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11815 struct mlx5_flow_sub_actions_list *sample_act =
11816 &mdest_res->sample_act[dest_index];
11817 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11818 struct mlx5_flow_rss_desc *rss_desc;
11819 uint32_t normal_idx = 0;
11820 struct mlx5_hrxq *hrxq;
11824 rss_desc = &wks->rss_desc;
11825 if (num_of_dest > 1) {
11826 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11827 /* Handle QP action for mirroring */
11828 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11829 rss_desc, &hrxq_idx);
11831 return rte_flow_error_set
11833 RTE_FLOW_ERROR_TYPE_ACTION,
11835 "cannot create rx queue");
11837 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11838 sample_act->dr_queue_action = hrxq->action;
11839 if (action_flags & MLX5_FLOW_ACTION_MARK)
11840 dev_flow->handle->rix_hrxq = hrxq_idx;
11841 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11843 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11845 mdest_res->sample_idx[dest_index].rix_encap_decap =
11846 dev_flow->handle->dvh.rix_encap_decap;
11847 sample_act->dr_encap_action =
11848 dev_flow->dv.encap_decap->action;
11849 dev_flow->handle->dvh.rix_encap_decap = 0;
11851 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11853 mdest_res->sample_idx[dest_index].rix_port_id_action =
11854 dev_flow->handle->rix_port_id_action;
11855 sample_act->dr_port_id_action =
11856 dev_flow->dv.port_id_action->action;
11857 dev_flow->handle->rix_port_id_action = 0;
11859 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11861 mdest_res->sample_idx[dest_index].rix_jump =
11862 dev_flow->handle->rix_jump;
11863 sample_act->dr_jump_action =
11864 dev_flow->dv.jump->action;
11865 dev_flow->handle->rix_jump = 0;
11867 sample_act->actions_num = normal_idx;
11868 /* update sample action resource into first index of array */
11869 mdest_res->ft_type = res->ft_type;
11870 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11871 sizeof(struct mlx5_flow_sub_actions_idx));
11872 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11873 sizeof(struct mlx5_flow_sub_actions_list));
11874 mdest_res->num_of_dest = num_of_dest;
11875 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11877 return rte_flow_error_set(error, EINVAL,
11878 RTE_FLOW_ERROR_TYPE_ACTION,
11879 NULL, "can't create sample "
11882 res->sub_actions = sample_actions;
11883 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11884 return rte_flow_error_set(error, EINVAL,
11885 RTE_FLOW_ERROR_TYPE_ACTION,
11887 "can't create sample action");
11893 * Remove an ASO age action from age actions list.
11896 * Pointer to the Ethernet device structure.
11898 * Pointer to the aso age action handler.
11901 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11902 struct mlx5_aso_age_action *age)
11904 struct mlx5_age_info *age_info;
11905 struct mlx5_age_param *age_param = &age->age_params;
11906 struct mlx5_priv *priv = dev->data->dev_private;
11907 uint16_t expected = AGE_CANDIDATE;
11909 age_info = GET_PORT_AGE_INFO(priv);
11910 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11911 AGE_FREE, false, __ATOMIC_RELAXED,
11912 __ATOMIC_RELAXED)) {
11914 * We need the lock even it is age timeout,
11915 * since age action may still in process.
11917 rte_spinlock_lock(&age_info->aged_sl);
11918 LIST_REMOVE(age, next);
11919 rte_spinlock_unlock(&age_info->aged_sl);
11920 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11925 * Release an ASO age action.
11928 * Pointer to the Ethernet device structure.
11929 * @param[in] age_idx
11930 * Index of ASO age action to release.
11932 * True if the release operation is during flow destroy operation.
11933 * False if the release operation is during action destroy operation.
11936 * 0 when age action was removed, otherwise the number of references.
11939 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11941 struct mlx5_priv *priv = dev->data->dev_private;
11942 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11943 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11944 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11947 flow_dv_aso_age_remove_from_age(dev, age);
11948 rte_spinlock_lock(&mng->free_sl);
11949 LIST_INSERT_HEAD(&mng->free, age, next);
11950 rte_spinlock_unlock(&mng->free_sl);
11956 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11959 * Pointer to the Ethernet device structure.
11962 * 0 on success, otherwise negative errno value and rte_errno is set.
11965 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11967 struct mlx5_priv *priv = dev->data->dev_private;
11968 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11969 void *old_pools = mng->pools;
11970 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11971 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11972 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11975 rte_errno = ENOMEM;
11979 memcpy(pools, old_pools,
11980 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11981 mlx5_free(old_pools);
11983 /* First ASO flow hit allocation - starting ASO data-path. */
11984 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11992 mng->pools = pools;
11997 * Create and initialize a new ASO aging pool.
12000 * Pointer to the Ethernet device structure.
12001 * @param[out] age_free
12002 * Where to put the pointer of a new age action.
12005 * The age actions pool pointer and @p age_free is set on success,
12006 * NULL otherwise and rte_errno is set.
12008 static struct mlx5_aso_age_pool *
12009 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12010 struct mlx5_aso_age_action **age_free)
12012 struct mlx5_priv *priv = dev->data->dev_private;
12013 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12014 struct mlx5_aso_age_pool *pool = NULL;
12015 struct mlx5_devx_obj *obj = NULL;
12018 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12019 priv->sh->cdev->pdn);
12021 rte_errno = ENODATA;
12022 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12025 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12027 claim_zero(mlx5_devx_cmd_destroy(obj));
12028 rte_errno = ENOMEM;
12031 pool->flow_hit_aso_obj = obj;
12032 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12033 rte_rwlock_write_lock(&mng->resize_rwl);
12034 pool->index = mng->next;
12035 /* Resize pools array if there is no room for the new pool in it. */
12036 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12037 claim_zero(mlx5_devx_cmd_destroy(obj));
12039 rte_rwlock_write_unlock(&mng->resize_rwl);
12042 mng->pools[pool->index] = pool;
12044 rte_rwlock_write_unlock(&mng->resize_rwl);
12045 /* Assign the first action in the new pool, the rest go to free list. */
12046 *age_free = &pool->actions[0];
12047 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12048 pool->actions[i].offset = i;
12049 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12055 * Allocate a ASO aging bit.
12058 * Pointer to the Ethernet device structure.
12059 * @param[out] error
12060 * Pointer to the error structure.
12063 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12066 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12068 struct mlx5_priv *priv = dev->data->dev_private;
12069 const struct mlx5_aso_age_pool *pool;
12070 struct mlx5_aso_age_action *age_free = NULL;
12071 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12074 /* Try to get the next free age action bit. */
12075 rte_spinlock_lock(&mng->free_sl);
12076 age_free = LIST_FIRST(&mng->free);
12078 LIST_REMOVE(age_free, next);
12079 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12080 rte_spinlock_unlock(&mng->free_sl);
12081 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12082 NULL, "failed to create ASO age pool");
12083 return 0; /* 0 is an error. */
12085 rte_spinlock_unlock(&mng->free_sl);
12086 pool = container_of
12087 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12088 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12090 if (!age_free->dr_action) {
12091 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12095 rte_flow_error_set(error, rte_errno,
12096 RTE_FLOW_ERROR_TYPE_ACTION,
12097 NULL, "failed to get reg_c "
12098 "for ASO flow hit");
12099 return 0; /* 0 is an error. */
12101 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12102 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12103 (priv->sh->rx_domain,
12104 pool->flow_hit_aso_obj->obj, age_free->offset,
12105 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12106 (reg_c - REG_C_0));
12107 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12108 if (!age_free->dr_action) {
12110 rte_spinlock_lock(&mng->free_sl);
12111 LIST_INSERT_HEAD(&mng->free, age_free, next);
12112 rte_spinlock_unlock(&mng->free_sl);
12113 rte_flow_error_set(error, rte_errno,
12114 RTE_FLOW_ERROR_TYPE_ACTION,
12115 NULL, "failed to create ASO "
12116 "flow hit action");
12117 return 0; /* 0 is an error. */
12120 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12121 return pool->index | ((age_free->offset + 1) << 16);
12125 * Initialize flow ASO age parameters.
12128 * Pointer to rte_eth_dev structure.
12129 * @param[in] age_idx
12130 * Index of ASO age action.
12131 * @param[in] context
12132 * Pointer to flow counter age context.
12133 * @param[in] timeout
12134 * Aging timeout in seconds.
12138 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12143 struct mlx5_aso_age_action *aso_age;
12145 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12146 MLX5_ASSERT(aso_age);
12147 aso_age->age_params.context = context;
12148 aso_age->age_params.timeout = timeout;
12149 aso_age->age_params.port_id = dev->data->port_id;
12150 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12152 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12157 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12158 const struct rte_flow_item_integrity *value,
12159 void *headers_m, void *headers_v)
12162 /* RTE l4_ok filter aggregates hardware l4_ok and
12163 * l4_checksum_ok filters.
12164 * Positive RTE l4_ok match requires hardware match on both L4
12165 * hardware integrity bits.
12166 * For negative match, check hardware l4_checksum_ok bit only,
12167 * because hardware sets that bit to 0 for all packets
12170 if (value->l4_ok) {
12171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12174 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12175 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12178 if (mask->l4_csum_ok) {
12179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12180 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12181 value->l4_csum_ok);
12186 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12187 const struct rte_flow_item_integrity *value,
12188 void *headers_m, void *headers_v, bool is_ipv4)
12191 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12192 * ipv4_csum_ok filters.
12193 * Positive RTE l3_ok match requires hardware match on both L3
12194 * hardware integrity bits.
12195 * For negative match, check hardware l3_csum_ok bit only,
12196 * because hardware sets that bit to 0 for all packets
12200 if (value->l3_ok) {
12201 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12203 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12206 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12207 ipv4_checksum_ok, 1);
12208 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12209 ipv4_checksum_ok, !!value->l3_ok);
12211 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12212 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12216 if (mask->ipv4_csum_ok) {
12217 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12219 value->ipv4_csum_ok);
12224 set_integrity_bits(void *headers_m, void *headers_v,
12225 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12227 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12228 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12230 /* Integrity bits validation cleared spec pointer */
12231 MLX5_ASSERT(spec != NULL);
12233 mask = &rte_flow_item_integrity_mask;
12234 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12236 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12240 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12242 struct rte_flow_item *integrity_items[2],
12243 uint64_t pattern_flags)
12245 void *headers_m, *headers_v;
12248 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12249 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12251 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12252 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12254 set_integrity_bits(headers_m, headers_v,
12255 integrity_items[1], is_l3_ip4);
12257 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12258 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12260 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12261 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12263 set_integrity_bits(headers_m, headers_v,
12264 integrity_items[0], is_l3_ip4);
12269 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12270 const struct rte_flow_item *integrity_items[2],
12271 uint64_t *last_item)
12273 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12275 /* integrity bits validation cleared spec pointer */
12276 MLX5_ASSERT(spec != NULL);
12277 if (spec->level > 1) {
12278 integrity_items[1] = item;
12279 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12281 integrity_items[0] = item;
12282 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12287 * Prepares DV flow counter with aging configuration.
12288 * Gets it by index when exists, creates a new one when doesn't.
12291 * Pointer to rte_eth_dev structure.
12292 * @param[in] dev_flow
12293 * Pointer to the mlx5_flow.
12294 * @param[in, out] flow
12295 * Pointer to the sub flow.
12297 * Pointer to the counter action configuration.
12299 * Pointer to the aging action configuration.
12300 * @param[out] error
12301 * Pointer to the error structure.
12304 * Pointer to the counter, NULL otherwise.
12306 static struct mlx5_flow_counter *
12307 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12308 struct mlx5_flow *dev_flow,
12309 struct rte_flow *flow,
12310 const struct rte_flow_action_count *count,
12311 const struct rte_flow_action_age *age,
12312 struct rte_flow_error *error)
12314 if (!flow->counter) {
12315 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12317 if (!flow->counter) {
12318 rte_flow_error_set(error, rte_errno,
12319 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12320 "cannot create counter object.");
12324 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12328 * Release an ASO CT action by its own device.
12331 * Pointer to the Ethernet device structure.
12333 * Index of ASO CT action to release.
12336 * 0 when CT action was removed, otherwise the number of references.
12339 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12341 struct mlx5_priv *priv = dev->data->dev_private;
12342 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12344 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12345 enum mlx5_aso_ct_state state =
12346 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12348 /* Cannot release when CT is in the ASO SQ. */
12349 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12351 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12353 if (ct->dr_action_orig) {
12354 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12355 claim_zero(mlx5_glue->destroy_flow_action
12356 (ct->dr_action_orig));
12358 ct->dr_action_orig = NULL;
12360 if (ct->dr_action_rply) {
12361 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12362 claim_zero(mlx5_glue->destroy_flow_action
12363 (ct->dr_action_rply));
12365 ct->dr_action_rply = NULL;
12367 /* Clear the state to free, no need in 1st allocation. */
12368 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12369 rte_spinlock_lock(&mng->ct_sl);
12370 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12371 rte_spinlock_unlock(&mng->ct_sl);
12377 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12378 struct rte_flow_error *error)
12380 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12381 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12382 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12385 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12386 if (dev->data->dev_started != 1)
12387 return rte_flow_error_set(error, EAGAIN,
12388 RTE_FLOW_ERROR_TYPE_ACTION,
12390 "Indirect CT action cannot be destroyed when the port is stopped");
12391 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12393 return rte_flow_error_set(error, EAGAIN,
12394 RTE_FLOW_ERROR_TYPE_ACTION,
12396 "Current state prevents indirect CT action from being destroyed");
12401 * Resize the ASO CT pools array by 64 pools.
12404 * Pointer to the Ethernet device structure.
12407 * 0 on success, otherwise negative errno value and rte_errno is set.
12410 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12412 struct mlx5_priv *priv = dev->data->dev_private;
12413 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12414 void *old_pools = mng->pools;
12415 /* Magic number now, need a macro. */
12416 uint32_t resize = mng->n + 64;
12417 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12418 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12421 rte_errno = ENOMEM;
12424 rte_rwlock_write_lock(&mng->resize_rwl);
12425 /* ASO SQ/QP was already initialized in the startup. */
12427 /* Realloc could be an alternative choice. */
12428 rte_memcpy(pools, old_pools,
12429 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12430 mlx5_free(old_pools);
12433 mng->pools = pools;
12434 rte_rwlock_write_unlock(&mng->resize_rwl);
12439 * Create and initialize a new ASO CT pool.
12442 * Pointer to the Ethernet device structure.
12443 * @param[out] ct_free
12444 * Where to put the pointer of a new CT action.
12447 * The CT actions pool pointer and @p ct_free is set on success,
12448 * NULL otherwise and rte_errno is set.
12450 static struct mlx5_aso_ct_pool *
12451 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12452 struct mlx5_aso_ct_action **ct_free)
12454 struct mlx5_priv *priv = dev->data->dev_private;
12455 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12456 struct mlx5_aso_ct_pool *pool = NULL;
12457 struct mlx5_devx_obj *obj = NULL;
12459 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12461 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12462 priv->sh->cdev->pdn,
12465 rte_errno = ENODATA;
12466 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12469 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12471 rte_errno = ENOMEM;
12472 claim_zero(mlx5_devx_cmd_destroy(obj));
12475 pool->devx_obj = obj;
12476 pool->index = mng->next;
12477 /* Resize pools array if there is no room for the new pool in it. */
12478 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12479 claim_zero(mlx5_devx_cmd_destroy(obj));
12483 mng->pools[pool->index] = pool;
12485 /* Assign the first action in the new pool, the rest go to free list. */
12486 *ct_free = &pool->actions[0];
12487 /* Lock outside, the list operation is safe here. */
12488 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12489 /* refcnt is 0 when allocating the memory. */
12490 pool->actions[i].offset = i;
12491 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12497 * Allocate a ASO CT action from free list.
12500 * Pointer to the Ethernet device structure.
12501 * @param[out] error
12502 * Pointer to the error structure.
12505 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12508 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12510 struct mlx5_priv *priv = dev->data->dev_private;
12511 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12512 struct mlx5_aso_ct_action *ct = NULL;
12513 struct mlx5_aso_ct_pool *pool;
12518 if (!priv->sh->devx) {
12519 rte_errno = ENOTSUP;
12522 /* Get a free CT action, if no, a new pool will be created. */
12523 rte_spinlock_lock(&mng->ct_sl);
12524 ct = LIST_FIRST(&mng->free_cts);
12526 LIST_REMOVE(ct, next);
12527 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12528 rte_spinlock_unlock(&mng->ct_sl);
12529 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12530 NULL, "failed to create ASO CT pool");
12533 rte_spinlock_unlock(&mng->ct_sl);
12534 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12535 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12536 /* 0: inactive, 1: created, 2+: used by flows. */
12537 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12538 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12539 if (!ct->dr_action_orig) {
12540 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12541 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12542 (priv->sh->rx_domain, pool->devx_obj->obj,
12544 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12547 RTE_SET_USED(reg_c);
12549 if (!ct->dr_action_orig) {
12550 flow_dv_aso_ct_dev_release(dev, ct_idx);
12551 rte_flow_error_set(error, rte_errno,
12552 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12553 "failed to create ASO CT action");
12557 if (!ct->dr_action_rply) {
12558 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12559 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12560 (priv->sh->rx_domain, pool->devx_obj->obj,
12562 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12565 if (!ct->dr_action_rply) {
12566 flow_dv_aso_ct_dev_release(dev, ct_idx);
12567 rte_flow_error_set(error, rte_errno,
12568 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12569 "failed to create ASO CT action");
12577 * Create a conntrack object with context and actions by using ASO mechanism.
12580 * Pointer to rte_eth_dev structure.
12582 * Pointer to conntrack information profile.
12583 * @param[out] error
12584 * Pointer to the error structure.
12587 * Index to conntrack object on success, 0 otherwise.
12590 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12591 const struct rte_flow_action_conntrack *pro,
12592 struct rte_flow_error *error)
12594 struct mlx5_priv *priv = dev->data->dev_private;
12595 struct mlx5_dev_ctx_shared *sh = priv->sh;
12596 struct mlx5_aso_ct_action *ct;
12599 if (!sh->ct_aso_en)
12600 return rte_flow_error_set(error, ENOTSUP,
12601 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12602 "Connection is not supported");
12603 idx = flow_dv_aso_ct_alloc(dev, error);
12605 return rte_flow_error_set(error, rte_errno,
12606 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12607 "Failed to allocate CT object");
12608 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12609 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12610 return rte_flow_error_set(error, EBUSY,
12611 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12612 "Failed to update CT");
12613 ct->is_original = !!pro->is_original_dir;
12614 ct->peer = pro->peer_port;
12619 * Fill the flow with DV spec, lock free
12620 * (mutex should be acquired by caller).
12623 * Pointer to rte_eth_dev structure.
12624 * @param[in, out] dev_flow
12625 * Pointer to the sub flow.
12627 * Pointer to the flow attributes.
12629 * Pointer to the list of items.
12630 * @param[in] actions
12631 * Pointer to the list of actions.
12632 * @param[out] error
12633 * Pointer to the error structure.
12636 * 0 on success, a negative errno value otherwise and rte_errno is set.
12639 flow_dv_translate(struct rte_eth_dev *dev,
12640 struct mlx5_flow *dev_flow,
12641 const struct rte_flow_attr *attr,
12642 const struct rte_flow_item items[],
12643 const struct rte_flow_action actions[],
12644 struct rte_flow_error *error)
12646 struct mlx5_priv *priv = dev->data->dev_private;
12647 struct mlx5_dev_config *dev_conf = &priv->config;
12648 struct rte_flow *flow = dev_flow->flow;
12649 struct mlx5_flow_handle *handle = dev_flow->handle;
12650 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12651 struct mlx5_flow_rss_desc *rss_desc;
12652 uint64_t item_flags = 0;
12653 uint64_t last_item = 0;
12654 uint64_t action_flags = 0;
12655 struct mlx5_flow_dv_matcher matcher = {
12657 .size = sizeof(matcher.mask.buf),
12661 bool actions_end = false;
12663 struct mlx5_flow_dv_modify_hdr_resource res;
12664 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12665 sizeof(struct mlx5_modification_cmd) *
12666 (MLX5_MAX_MODIFY_NUM + 1)];
12668 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12669 const struct rte_flow_action_count *count = NULL;
12670 const struct rte_flow_action_age *non_shared_age = NULL;
12671 union flow_dv_attr flow_attr = { .attr = 0 };
12673 union mlx5_flow_tbl_key tbl_key;
12674 uint32_t modify_action_position = UINT32_MAX;
12675 void *match_mask = matcher.mask.buf;
12676 void *match_value = dev_flow->dv.value.buf;
12677 uint8_t next_protocol = 0xff;
12678 struct rte_vlan_hdr vlan = { 0 };
12679 struct mlx5_flow_dv_dest_array_resource mdest_res;
12680 struct mlx5_flow_dv_sample_resource sample_res;
12681 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12682 const struct rte_flow_action_sample *sample = NULL;
12683 struct mlx5_flow_sub_actions_list *sample_act;
12684 uint32_t sample_act_pos = UINT32_MAX;
12685 uint32_t age_act_pos = UINT32_MAX;
12686 uint32_t num_of_dest = 0;
12687 int tmp_actions_n = 0;
12690 const struct mlx5_flow_tunnel *tunnel = NULL;
12691 struct flow_grp_info grp_info = {
12692 .external = !!dev_flow->external,
12693 .transfer = !!attr->transfer,
12694 .fdb_def_rule = !!priv->fdb_def_rule,
12695 .skip_scale = dev_flow->skip_scale &
12696 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12697 .std_tbl_fix = true,
12699 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12700 const struct rte_flow_item *tunnel_item = NULL;
12703 return rte_flow_error_set(error, ENOMEM,
12704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12706 "failed to push flow workspace");
12707 rss_desc = &wks->rss_desc;
12708 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12709 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12710 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12711 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12712 /* update normal path action resource into last index of array */
12713 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12714 if (is_tunnel_offload_active(dev)) {
12715 if (dev_flow->tunnel) {
12716 RTE_VERIFY(dev_flow->tof_type ==
12717 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12718 tunnel = dev_flow->tunnel;
12720 tunnel = mlx5_get_tof(items, actions,
12721 &dev_flow->tof_type);
12722 dev_flow->tunnel = tunnel;
12724 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12725 (dev, attr, tunnel, dev_flow->tof_type);
12727 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12728 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12729 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12733 dev_flow->dv.group = table;
12734 if (attr->transfer)
12735 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12736 /* number of actions must be set to 0 in case of dirty stack. */
12737 mhdr_res->actions_num = 0;
12738 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12740 * do not add decap action if match rule drops packet
12741 * HW rejects rules with decap & drop
12743 * if tunnel match rule was inserted before matching tunnel set
12744 * rule flow table used in the match rule must be registered.
12745 * current implementation handles that in the
12746 * flow_dv_match_register() at the function end.
12748 bool add_decap = true;
12749 const struct rte_flow_action *ptr = actions;
12751 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12752 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12758 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12762 dev_flow->dv.actions[actions_n++] =
12763 dev_flow->dv.encap_decap->action;
12764 action_flags |= MLX5_FLOW_ACTION_DECAP;
12767 for (; !actions_end ; actions++) {
12768 const struct rte_flow_action_queue *queue;
12769 const struct rte_flow_action_rss *rss;
12770 const struct rte_flow_action *action = actions;
12771 const uint8_t *rss_key;
12772 struct mlx5_flow_tbl_resource *tbl;
12773 struct mlx5_aso_age_action *age_act;
12774 struct mlx5_flow_counter *cnt_act;
12775 uint32_t port_id = 0;
12776 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12777 int action_type = actions->type;
12778 const struct rte_flow_action *found_action = NULL;
12779 uint32_t jump_group = 0;
12780 uint32_t owner_idx;
12781 struct mlx5_aso_ct_action *ct;
12783 if (!mlx5_flow_os_action_supported(action_type))
12784 return rte_flow_error_set(error, ENOTSUP,
12785 RTE_FLOW_ERROR_TYPE_ACTION,
12787 "action not supported");
12788 switch (action_type) {
12789 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12790 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12792 case RTE_FLOW_ACTION_TYPE_VOID:
12794 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12795 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12796 if (flow_dv_translate_action_port_id(dev, action,
12799 port_id_resource.port_id = port_id;
12800 MLX5_ASSERT(!handle->rix_port_id_action);
12801 if (flow_dv_port_id_action_resource_register
12802 (dev, &port_id_resource, dev_flow, error))
12804 dev_flow->dv.actions[actions_n++] =
12805 dev_flow->dv.port_id_action->action;
12806 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12807 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12808 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12811 case RTE_FLOW_ACTION_TYPE_FLAG:
12812 action_flags |= MLX5_FLOW_ACTION_FLAG;
12814 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12815 struct rte_flow_action_mark mark = {
12816 .id = MLX5_FLOW_MARK_DEFAULT,
12819 if (flow_dv_convert_action_mark(dev, &mark,
12823 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12826 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12828 * Only one FLAG or MARK is supported per device flow
12829 * right now. So the pointer to the tag resource must be
12830 * zero before the register process.
12832 MLX5_ASSERT(!handle->dvh.rix_tag);
12833 if (flow_dv_tag_resource_register(dev, tag_be,
12836 MLX5_ASSERT(dev_flow->dv.tag_resource);
12837 dev_flow->dv.actions[actions_n++] =
12838 dev_flow->dv.tag_resource->action;
12840 case RTE_FLOW_ACTION_TYPE_MARK:
12841 action_flags |= MLX5_FLOW_ACTION_MARK;
12843 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12844 const struct rte_flow_action_mark *mark =
12845 (const struct rte_flow_action_mark *)
12848 if (flow_dv_convert_action_mark(dev, mark,
12852 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12856 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12857 /* Legacy (non-extensive) MARK action. */
12858 tag_be = mlx5_flow_mark_set
12859 (((const struct rte_flow_action_mark *)
12860 (actions->conf))->id);
12861 MLX5_ASSERT(!handle->dvh.rix_tag);
12862 if (flow_dv_tag_resource_register(dev, tag_be,
12865 MLX5_ASSERT(dev_flow->dv.tag_resource);
12866 dev_flow->dv.actions[actions_n++] =
12867 dev_flow->dv.tag_resource->action;
12869 case RTE_FLOW_ACTION_TYPE_SET_META:
12870 if (flow_dv_convert_action_set_meta
12871 (dev, mhdr_res, attr,
12872 (const struct rte_flow_action_set_meta *)
12873 actions->conf, error))
12875 action_flags |= MLX5_FLOW_ACTION_SET_META;
12877 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12878 if (flow_dv_convert_action_set_tag
12880 (const struct rte_flow_action_set_tag *)
12881 actions->conf, error))
12883 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12885 case RTE_FLOW_ACTION_TYPE_DROP:
12886 action_flags |= MLX5_FLOW_ACTION_DROP;
12887 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12889 case RTE_FLOW_ACTION_TYPE_QUEUE:
12890 queue = actions->conf;
12891 rss_desc->queue_num = 1;
12892 rss_desc->queue[0] = queue->index;
12893 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12894 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12895 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12898 case RTE_FLOW_ACTION_TYPE_RSS:
12899 rss = actions->conf;
12900 memcpy(rss_desc->queue, rss->queue,
12901 rss->queue_num * sizeof(uint16_t));
12902 rss_desc->queue_num = rss->queue_num;
12903 /* NULL RSS key indicates default RSS key. */
12904 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12905 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12907 * rss->level and rss.types should be set in advance
12908 * when expanding items for RSS.
12910 action_flags |= MLX5_FLOW_ACTION_RSS;
12911 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12912 MLX5_FLOW_FATE_SHARED_RSS :
12913 MLX5_FLOW_FATE_QUEUE;
12915 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12916 owner_idx = (uint32_t)(uintptr_t)action->conf;
12917 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12918 if (flow->age == 0) {
12919 flow->age = owner_idx;
12920 __atomic_fetch_add(&age_act->refcnt, 1,
12923 age_act_pos = actions_n++;
12924 action_flags |= MLX5_FLOW_ACTION_AGE;
12926 case RTE_FLOW_ACTION_TYPE_AGE:
12927 non_shared_age = action->conf;
12928 age_act_pos = actions_n++;
12929 action_flags |= MLX5_FLOW_ACTION_AGE;
12931 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12932 owner_idx = (uint32_t)(uintptr_t)action->conf;
12933 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12935 MLX5_ASSERT(cnt_act != NULL);
12937 * When creating meter drop flow in drop table, the
12938 * counter should not overwrite the rte flow counter.
12940 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12941 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12942 dev_flow->dv.actions[actions_n++] =
12945 if (flow->counter == 0) {
12946 flow->counter = owner_idx;
12948 (&cnt_act->shared_info.refcnt,
12949 1, __ATOMIC_RELAXED);
12951 /* Save information first, will apply later. */
12952 action_flags |= MLX5_FLOW_ACTION_COUNT;
12955 case RTE_FLOW_ACTION_TYPE_COUNT:
12956 if (!priv->sh->devx) {
12957 return rte_flow_error_set
12959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12961 "count action not supported");
12963 /* Save information first, will apply later. */
12964 count = action->conf;
12965 action_flags |= MLX5_FLOW_ACTION_COUNT;
12967 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12968 dev_flow->dv.actions[actions_n++] =
12969 priv->sh->pop_vlan_action;
12970 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12972 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12973 if (!(action_flags &
12974 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12975 flow_dev_get_vlan_info_from_items(items, &vlan);
12976 vlan.eth_proto = rte_be_to_cpu_16
12977 ((((const struct rte_flow_action_of_push_vlan *)
12978 actions->conf)->ethertype));
12979 found_action = mlx5_flow_find_action
12981 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12983 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12984 found_action = mlx5_flow_find_action
12986 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12988 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12989 if (flow_dv_create_action_push_vlan
12990 (dev, attr, &vlan, dev_flow, error))
12992 dev_flow->dv.actions[actions_n++] =
12993 dev_flow->dv.push_vlan_res->action;
12994 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12996 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12997 /* of_vlan_push action handled this action */
12998 MLX5_ASSERT(action_flags &
12999 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13001 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13002 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13004 flow_dev_get_vlan_info_from_items(items, &vlan);
13005 mlx5_update_vlan_vid_pcp(actions, &vlan);
13006 /* If no VLAN push - this is a modify header action */
13007 if (flow_dv_convert_action_modify_vlan_vid
13008 (mhdr_res, actions, error))
13010 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13012 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13013 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13014 if (flow_dv_create_action_l2_encap(dev, actions,
13019 dev_flow->dv.actions[actions_n++] =
13020 dev_flow->dv.encap_decap->action;
13021 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13022 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13023 sample_act->action_flags |=
13024 MLX5_FLOW_ACTION_ENCAP;
13026 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13027 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13028 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13032 dev_flow->dv.actions[actions_n++] =
13033 dev_flow->dv.encap_decap->action;
13034 action_flags |= MLX5_FLOW_ACTION_DECAP;
13036 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13037 /* Handle encap with preceding decap. */
13038 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13039 if (flow_dv_create_action_raw_encap
13040 (dev, actions, dev_flow, attr, error))
13042 dev_flow->dv.actions[actions_n++] =
13043 dev_flow->dv.encap_decap->action;
13045 /* Handle encap without preceding decap. */
13046 if (flow_dv_create_action_l2_encap
13047 (dev, actions, dev_flow, attr->transfer,
13050 dev_flow->dv.actions[actions_n++] =
13051 dev_flow->dv.encap_decap->action;
13053 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13054 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13055 sample_act->action_flags |=
13056 MLX5_FLOW_ACTION_ENCAP;
13058 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13059 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13061 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13062 if (flow_dv_create_action_l2_decap
13063 (dev, dev_flow, attr->transfer, error))
13065 dev_flow->dv.actions[actions_n++] =
13066 dev_flow->dv.encap_decap->action;
13068 /* If decap is followed by encap, handle it at encap. */
13069 action_flags |= MLX5_FLOW_ACTION_DECAP;
13071 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13072 dev_flow->dv.actions[actions_n++] =
13073 (void *)(uintptr_t)action->conf;
13074 action_flags |= MLX5_FLOW_ACTION_JUMP;
13076 case RTE_FLOW_ACTION_TYPE_JUMP:
13077 jump_group = ((const struct rte_flow_action_jump *)
13078 action->conf)->group;
13079 grp_info.std_tbl_fix = 0;
13080 if (dev_flow->skip_scale &
13081 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13082 grp_info.skip_scale = 1;
13084 grp_info.skip_scale = 0;
13085 ret = mlx5_flow_group_to_table(dev, tunnel,
13091 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13093 !!dev_flow->external,
13094 tunnel, jump_group, 0,
13097 return rte_flow_error_set
13099 RTE_FLOW_ERROR_TYPE_ACTION,
13101 "cannot create jump action.");
13102 if (flow_dv_jump_tbl_resource_register
13103 (dev, tbl, dev_flow, error)) {
13104 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13105 return rte_flow_error_set
13107 RTE_FLOW_ERROR_TYPE_ACTION,
13109 "cannot create jump action.");
13111 dev_flow->dv.actions[actions_n++] =
13112 dev_flow->dv.jump->action;
13113 action_flags |= MLX5_FLOW_ACTION_JUMP;
13114 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13115 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13118 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13119 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13120 if (flow_dv_convert_action_modify_mac
13121 (mhdr_res, actions, error))
13123 action_flags |= actions->type ==
13124 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13125 MLX5_FLOW_ACTION_SET_MAC_SRC :
13126 MLX5_FLOW_ACTION_SET_MAC_DST;
13128 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13129 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13130 if (flow_dv_convert_action_modify_ipv4
13131 (mhdr_res, actions, error))
13133 action_flags |= actions->type ==
13134 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13135 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13136 MLX5_FLOW_ACTION_SET_IPV4_DST;
13138 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13139 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13140 if (flow_dv_convert_action_modify_ipv6
13141 (mhdr_res, actions, error))
13143 action_flags |= actions->type ==
13144 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13145 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13146 MLX5_FLOW_ACTION_SET_IPV6_DST;
13148 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13149 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13150 if (flow_dv_convert_action_modify_tp
13151 (mhdr_res, actions, items,
13152 &flow_attr, dev_flow, !!(action_flags &
13153 MLX5_FLOW_ACTION_DECAP), error))
13155 action_flags |= actions->type ==
13156 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13157 MLX5_FLOW_ACTION_SET_TP_SRC :
13158 MLX5_FLOW_ACTION_SET_TP_DST;
13160 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13161 if (flow_dv_convert_action_modify_dec_ttl
13162 (mhdr_res, items, &flow_attr, dev_flow,
13164 MLX5_FLOW_ACTION_DECAP), error))
13166 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13168 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13169 if (flow_dv_convert_action_modify_ttl
13170 (mhdr_res, actions, items, &flow_attr,
13171 dev_flow, !!(action_flags &
13172 MLX5_FLOW_ACTION_DECAP), error))
13174 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13176 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13177 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13178 if (flow_dv_convert_action_modify_tcp_seq
13179 (mhdr_res, actions, error))
13181 action_flags |= actions->type ==
13182 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13183 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13184 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13187 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13188 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13189 if (flow_dv_convert_action_modify_tcp_ack
13190 (mhdr_res, actions, error))
13192 action_flags |= actions->type ==
13193 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13194 MLX5_FLOW_ACTION_INC_TCP_ACK :
13195 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13197 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13198 if (flow_dv_convert_action_set_reg
13199 (mhdr_res, actions, error))
13201 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13203 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13204 if (flow_dv_convert_action_copy_mreg
13205 (dev, mhdr_res, actions, error))
13207 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13209 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13210 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13211 dev_flow->handle->fate_action =
13212 MLX5_FLOW_FATE_DEFAULT_MISS;
13214 case RTE_FLOW_ACTION_TYPE_METER:
13216 return rte_flow_error_set(error, rte_errno,
13217 RTE_FLOW_ERROR_TYPE_ACTION,
13218 NULL, "Failed to get meter in flow.");
13219 /* Set the meter action. */
13220 dev_flow->dv.actions[actions_n++] =
13221 wks->fm->meter_action;
13222 action_flags |= MLX5_FLOW_ACTION_METER;
13224 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13225 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13228 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13230 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13231 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13234 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13236 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13237 sample_act_pos = actions_n;
13238 sample = (const struct rte_flow_action_sample *)
13241 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13242 /* put encap action into group if work with port id */
13243 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13244 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13245 sample_act->action_flags |=
13246 MLX5_FLOW_ACTION_ENCAP;
13248 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13249 if (flow_dv_convert_action_modify_field
13250 (dev, mhdr_res, actions, attr, error))
13252 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13254 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13255 owner_idx = (uint32_t)(uintptr_t)action->conf;
13256 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13258 return rte_flow_error_set(error, EINVAL,
13259 RTE_FLOW_ERROR_TYPE_ACTION,
13261 "Failed to get CT object.");
13262 if (mlx5_aso_ct_available(priv->sh, ct))
13263 return rte_flow_error_set(error, rte_errno,
13264 RTE_FLOW_ERROR_TYPE_ACTION,
13266 "CT is unavailable.");
13267 if (ct->is_original)
13268 dev_flow->dv.actions[actions_n] =
13269 ct->dr_action_orig;
13271 dev_flow->dv.actions[actions_n] =
13272 ct->dr_action_rply;
13273 if (flow->ct == 0) {
13274 flow->indirect_type =
13275 MLX5_INDIRECT_ACTION_TYPE_CT;
13276 flow->ct = owner_idx;
13277 __atomic_fetch_add(&ct->refcnt, 1,
13281 action_flags |= MLX5_FLOW_ACTION_CT;
13283 case RTE_FLOW_ACTION_TYPE_END:
13284 actions_end = true;
13285 if (mhdr_res->actions_num) {
13286 /* create modify action if needed. */
13287 if (flow_dv_modify_hdr_resource_register
13288 (dev, mhdr_res, dev_flow, error))
13290 dev_flow->dv.actions[modify_action_position] =
13291 handle->dvh.modify_hdr->action;
13294 * Handle AGE and COUNT action by single HW counter
13295 * when they are not shared.
13297 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13298 if ((non_shared_age && count) ||
13299 !(priv->sh->flow_hit_aso_en &&
13300 (attr->group || attr->transfer))) {
13301 /* Creates age by counters. */
13302 cnt_act = flow_dv_prepare_counter
13309 dev_flow->dv.actions[age_act_pos] =
13313 if (!flow->age && non_shared_age) {
13314 flow->age = flow_dv_aso_age_alloc
13318 flow_dv_aso_age_params_init
13320 non_shared_age->context ?
13321 non_shared_age->context :
13322 (void *)(uintptr_t)
13323 (dev_flow->flow_idx),
13324 non_shared_age->timeout);
13326 age_act = flow_aso_age_get_by_idx(dev,
13328 dev_flow->dv.actions[age_act_pos] =
13329 age_act->dr_action;
13331 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13333 * Create one count action, to be used
13334 * by all sub-flows.
13336 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13341 dev_flow->dv.actions[actions_n++] =
13347 if (mhdr_res->actions_num &&
13348 modify_action_position == UINT32_MAX)
13349 modify_action_position = actions_n++;
13351 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13352 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13353 int item_type = items->type;
13355 if (!mlx5_flow_os_item_supported(item_type))
13356 return rte_flow_error_set(error, ENOTSUP,
13357 RTE_FLOW_ERROR_TYPE_ITEM,
13358 NULL, "item not supported");
13359 switch (item_type) {
13360 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13361 flow_dv_translate_item_port_id
13362 (dev, match_mask, match_value, items, attr);
13363 last_item = MLX5_FLOW_ITEM_PORT_ID;
13365 case RTE_FLOW_ITEM_TYPE_ETH:
13366 flow_dv_translate_item_eth(match_mask, match_value,
13368 dev_flow->dv.group);
13369 matcher.priority = action_flags &
13370 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13371 !dev_flow->external ?
13372 MLX5_PRIORITY_MAP_L3 :
13373 MLX5_PRIORITY_MAP_L2;
13374 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13375 MLX5_FLOW_LAYER_OUTER_L2;
13377 case RTE_FLOW_ITEM_TYPE_VLAN:
13378 flow_dv_translate_item_vlan(dev_flow,
13379 match_mask, match_value,
13381 dev_flow->dv.group);
13382 matcher.priority = MLX5_PRIORITY_MAP_L2;
13383 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13384 MLX5_FLOW_LAYER_INNER_VLAN) :
13385 (MLX5_FLOW_LAYER_OUTER_L2 |
13386 MLX5_FLOW_LAYER_OUTER_VLAN);
13388 case RTE_FLOW_ITEM_TYPE_IPV4:
13389 mlx5_flow_tunnel_ip_check(items, next_protocol,
13390 &item_flags, &tunnel);
13391 flow_dv_translate_item_ipv4(match_mask, match_value,
13393 dev_flow->dv.group);
13394 matcher.priority = MLX5_PRIORITY_MAP_L3;
13395 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13396 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13397 if (items->mask != NULL &&
13398 ((const struct rte_flow_item_ipv4 *)
13399 items->mask)->hdr.next_proto_id) {
13401 ((const struct rte_flow_item_ipv4 *)
13402 (items->spec))->hdr.next_proto_id;
13404 ((const struct rte_flow_item_ipv4 *)
13405 (items->mask))->hdr.next_proto_id;
13407 /* Reset for inner layer. */
13408 next_protocol = 0xff;
13411 case RTE_FLOW_ITEM_TYPE_IPV6:
13412 mlx5_flow_tunnel_ip_check(items, next_protocol,
13413 &item_flags, &tunnel);
13414 flow_dv_translate_item_ipv6(match_mask, match_value,
13416 dev_flow->dv.group);
13417 matcher.priority = MLX5_PRIORITY_MAP_L3;
13418 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13419 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13420 if (items->mask != NULL &&
13421 ((const struct rte_flow_item_ipv6 *)
13422 items->mask)->hdr.proto) {
13424 ((const struct rte_flow_item_ipv6 *)
13425 items->spec)->hdr.proto;
13427 ((const struct rte_flow_item_ipv6 *)
13428 items->mask)->hdr.proto;
13430 /* Reset for inner layer. */
13431 next_protocol = 0xff;
13434 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13435 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13438 last_item = tunnel ?
13439 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13440 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13441 if (items->mask != NULL &&
13442 ((const struct rte_flow_item_ipv6_frag_ext *)
13443 items->mask)->hdr.next_header) {
13445 ((const struct rte_flow_item_ipv6_frag_ext *)
13446 items->spec)->hdr.next_header;
13448 ((const struct rte_flow_item_ipv6_frag_ext *)
13449 items->mask)->hdr.next_header;
13451 /* Reset for inner layer. */
13452 next_protocol = 0xff;
13455 case RTE_FLOW_ITEM_TYPE_TCP:
13456 flow_dv_translate_item_tcp(match_mask, match_value,
13458 matcher.priority = MLX5_PRIORITY_MAP_L4;
13459 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13460 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13462 case RTE_FLOW_ITEM_TYPE_UDP:
13463 flow_dv_translate_item_udp(match_mask, match_value,
13465 matcher.priority = MLX5_PRIORITY_MAP_L4;
13466 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13467 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13469 case RTE_FLOW_ITEM_TYPE_GRE:
13470 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13471 last_item = MLX5_FLOW_LAYER_GRE;
13472 tunnel_item = items;
13474 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13475 flow_dv_translate_item_gre_key(match_mask,
13476 match_value, items);
13477 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13479 case RTE_FLOW_ITEM_TYPE_NVGRE:
13480 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13481 last_item = MLX5_FLOW_LAYER_GRE;
13482 tunnel_item = items;
13484 case RTE_FLOW_ITEM_TYPE_VXLAN:
13485 flow_dv_translate_item_vxlan(dev, attr,
13486 match_mask, match_value,
13488 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13489 last_item = MLX5_FLOW_LAYER_VXLAN;
13491 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13492 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13493 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13494 tunnel_item = items;
13496 case RTE_FLOW_ITEM_TYPE_GENEVE:
13497 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13498 last_item = MLX5_FLOW_LAYER_GENEVE;
13499 tunnel_item = items;
13501 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13502 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13506 return rte_flow_error_set(error, -ret,
13507 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13508 "cannot create GENEVE TLV option");
13509 flow->geneve_tlv_option = 1;
13510 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13512 case RTE_FLOW_ITEM_TYPE_MPLS:
13513 flow_dv_translate_item_mpls(match_mask, match_value,
13514 items, last_item, tunnel);
13515 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13516 last_item = MLX5_FLOW_LAYER_MPLS;
13518 case RTE_FLOW_ITEM_TYPE_MARK:
13519 flow_dv_translate_item_mark(dev, match_mask,
13520 match_value, items);
13521 last_item = MLX5_FLOW_ITEM_MARK;
13523 case RTE_FLOW_ITEM_TYPE_META:
13524 flow_dv_translate_item_meta(dev, match_mask,
13525 match_value, attr, items);
13526 last_item = MLX5_FLOW_ITEM_METADATA;
13528 case RTE_FLOW_ITEM_TYPE_ICMP:
13529 flow_dv_translate_item_icmp(match_mask, match_value,
13531 last_item = MLX5_FLOW_LAYER_ICMP;
13533 case RTE_FLOW_ITEM_TYPE_ICMP6:
13534 flow_dv_translate_item_icmp6(match_mask, match_value,
13536 last_item = MLX5_FLOW_LAYER_ICMP6;
13538 case RTE_FLOW_ITEM_TYPE_TAG:
13539 flow_dv_translate_item_tag(dev, match_mask,
13540 match_value, items);
13541 last_item = MLX5_FLOW_ITEM_TAG;
13543 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13544 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13545 match_value, items);
13546 last_item = MLX5_FLOW_ITEM_TAG;
13548 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13549 flow_dv_translate_item_tx_queue(dev, match_mask,
13552 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13554 case RTE_FLOW_ITEM_TYPE_GTP:
13555 flow_dv_translate_item_gtp(match_mask, match_value,
13557 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13558 last_item = MLX5_FLOW_LAYER_GTP;
13560 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13561 ret = flow_dv_translate_item_gtp_psc(match_mask,
13565 return rte_flow_error_set(error, -ret,
13566 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13567 "cannot create GTP PSC item");
13568 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13570 case RTE_FLOW_ITEM_TYPE_ECPRI:
13571 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13572 /* Create it only the first time to be used. */
13573 ret = mlx5_flex_parser_ecpri_alloc(dev);
13575 return rte_flow_error_set
13577 RTE_FLOW_ERROR_TYPE_ITEM,
13579 "cannot create eCPRI parser");
13581 flow_dv_translate_item_ecpri(dev, match_mask,
13582 match_value, items,
13584 /* No other protocol should follow eCPRI layer. */
13585 last_item = MLX5_FLOW_LAYER_ECPRI;
13587 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13588 flow_dv_translate_item_integrity(items, integrity_items,
13591 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13592 flow_dv_translate_item_aso_ct(dev, match_mask,
13593 match_value, items);
13595 case RTE_FLOW_ITEM_TYPE_FLEX:
13596 flow_dv_translate_item_flex(dev, match_mask,
13597 match_value, items,
13598 dev_flow, tunnel != 0);
13599 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13600 MLX5_FLOW_ITEM_OUTER_FLEX;
13605 item_flags |= last_item;
13608 * When E-Switch mode is enabled, we have two cases where we need to
13609 * set the source port manually.
13610 * The first one, is in case of Nic steering rule, and the second is
13611 * E-Switch rule where no port_id item was found. In both cases
13612 * the source port is set according the current port in use.
13614 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13615 (priv->representor || priv->master)) {
13616 if (flow_dv_translate_item_port_id(dev, match_mask,
13617 match_value, NULL, attr))
13620 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13621 flow_dv_translate_item_integrity_post(match_mask, match_value,
13625 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13626 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13627 tunnel_item, item_flags);
13628 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13629 flow_dv_translate_item_geneve(match_mask, match_value,
13630 tunnel_item, item_flags);
13631 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13632 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13633 flow_dv_translate_item_gre(match_mask, match_value,
13634 tunnel_item, item_flags);
13635 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13636 flow_dv_translate_item_nvgre(match_mask, match_value,
13637 tunnel_item, item_flags);
13639 MLX5_ASSERT(false);
13641 #ifdef RTE_LIBRTE_MLX5_DEBUG
13642 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13643 dev_flow->dv.value.buf));
13646 * Layers may be already initialized from prefix flow if this dev_flow
13647 * is the suffix flow.
13649 handle->layers |= item_flags;
13650 if (action_flags & MLX5_FLOW_ACTION_RSS)
13651 flow_dv_hashfields_set(dev_flow, rss_desc);
13652 /* If has RSS action in the sample action, the Sample/Mirror resource
13653 * should be registered after the hash filed be update.
13655 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13656 ret = flow_dv_translate_action_sample(dev,
13665 ret = flow_dv_create_action_sample(dev,
13674 return rte_flow_error_set
13676 RTE_FLOW_ERROR_TYPE_ACTION,
13678 "cannot create sample action");
13679 if (num_of_dest > 1) {
13680 dev_flow->dv.actions[sample_act_pos] =
13681 dev_flow->dv.dest_array_res->action;
13683 dev_flow->dv.actions[sample_act_pos] =
13684 dev_flow->dv.sample_res->verbs_action;
13688 * For multiple destination (sample action with ratio=1), the encap
13689 * action and port id action will be combined into group action.
13690 * So need remove the original these actions in the flow and only
13691 * use the sample action instead of.
13693 if (num_of_dest > 1 &&
13694 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13696 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13698 for (i = 0; i < actions_n; i++) {
13699 if ((sample_act->dr_encap_action &&
13700 sample_act->dr_encap_action ==
13701 dev_flow->dv.actions[i]) ||
13702 (sample_act->dr_port_id_action &&
13703 sample_act->dr_port_id_action ==
13704 dev_flow->dv.actions[i]) ||
13705 (sample_act->dr_jump_action &&
13706 sample_act->dr_jump_action ==
13707 dev_flow->dv.actions[i]))
13709 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13711 memcpy((void *)dev_flow->dv.actions,
13712 (void *)temp_actions,
13713 tmp_actions_n * sizeof(void *));
13714 actions_n = tmp_actions_n;
13716 dev_flow->dv.actions_n = actions_n;
13717 dev_flow->act_flags = action_flags;
13718 if (wks->skip_matcher_reg)
13720 /* Register matcher. */
13721 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13722 matcher.mask.size);
13723 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13725 dev_flow->external);
13727 * When creating meter drop flow in drop table, using original
13728 * 5-tuple match, the matcher priority should be lower than
13731 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13732 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13733 matcher.priority <= MLX5_REG_BITS)
13734 matcher.priority += MLX5_REG_BITS;
13735 /* reserved field no needs to be set to 0 here. */
13736 tbl_key.is_fdb = attr->transfer;
13737 tbl_key.is_egress = attr->egress;
13738 tbl_key.level = dev_flow->dv.group;
13739 tbl_key.id = dev_flow->dv.table_id;
13740 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13741 tunnel, attr->group, error))
13747 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13750 * @param[in, out] action
13751 * Shred RSS action holding hash RX queue objects.
13752 * @param[in] hash_fields
13753 * Defines combination of packet fields to participate in RX hash.
13754 * @param[in] tunnel
13756 * @param[in] hrxq_idx
13757 * Hash RX queue index to set.
13760 * 0 on success, otherwise negative errno value.
13763 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13764 const uint64_t hash_fields,
13767 uint32_t *hrxqs = action->hrxq;
13769 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13770 case MLX5_RSS_HASH_IPV4:
13771 /* fall-through. */
13772 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13773 /* fall-through. */
13774 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13775 hrxqs[0] = hrxq_idx;
13777 case MLX5_RSS_HASH_IPV4_TCP:
13778 /* fall-through. */
13779 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13780 /* fall-through. */
13781 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13782 hrxqs[1] = hrxq_idx;
13784 case MLX5_RSS_HASH_IPV4_UDP:
13785 /* fall-through. */
13786 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13787 /* fall-through. */
13788 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13789 hrxqs[2] = hrxq_idx;
13791 case MLX5_RSS_HASH_IPV6:
13792 /* fall-through. */
13793 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13794 /* fall-through. */
13795 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13796 hrxqs[3] = hrxq_idx;
13798 case MLX5_RSS_HASH_IPV6_TCP:
13799 /* fall-through. */
13800 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13801 /* fall-through. */
13802 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13803 hrxqs[4] = hrxq_idx;
13805 case MLX5_RSS_HASH_IPV6_UDP:
13806 /* fall-through. */
13807 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13808 /* fall-through. */
13809 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13810 hrxqs[5] = hrxq_idx;
13812 case MLX5_RSS_HASH_NONE:
13813 hrxqs[6] = hrxq_idx;
13821 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13825 * Pointer to the Ethernet device structure.
13827 * Shared RSS action ID holding hash RX queue objects.
13828 * @param[in] hash_fields
13829 * Defines combination of packet fields to participate in RX hash.
13830 * @param[in] tunnel
13834 * Valid hash RX queue index, otherwise 0.
13837 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13838 const uint64_t hash_fields)
13840 struct mlx5_priv *priv = dev->data->dev_private;
13841 struct mlx5_shared_action_rss *shared_rss =
13842 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13843 const uint32_t *hrxqs = shared_rss->hrxq;
13845 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13846 case MLX5_RSS_HASH_IPV4:
13847 /* fall-through. */
13848 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13849 /* fall-through. */
13850 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13852 case MLX5_RSS_HASH_IPV4_TCP:
13853 /* fall-through. */
13854 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13855 /* fall-through. */
13856 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13858 case MLX5_RSS_HASH_IPV4_UDP:
13859 /* fall-through. */
13860 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13861 /* fall-through. */
13862 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13864 case MLX5_RSS_HASH_IPV6:
13865 /* fall-through. */
13866 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13867 /* fall-through. */
13868 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13870 case MLX5_RSS_HASH_IPV6_TCP:
13871 /* fall-through. */
13872 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13873 /* fall-through. */
13874 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13876 case MLX5_RSS_HASH_IPV6_UDP:
13877 /* fall-through. */
13878 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13879 /* fall-through. */
13880 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13882 case MLX5_RSS_HASH_NONE:
13891 * Apply the flow to the NIC, lock free,
13892 * (mutex should be acquired by caller).
13895 * Pointer to the Ethernet device structure.
13896 * @param[in, out] flow
13897 * Pointer to flow structure.
13898 * @param[out] error
13899 * Pointer to error structure.
13902 * 0 on success, a negative errno value otherwise and rte_errno is set.
13905 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13906 struct rte_flow_error *error)
13908 struct mlx5_flow_dv_workspace *dv;
13909 struct mlx5_flow_handle *dh;
13910 struct mlx5_flow_handle_dv *dv_h;
13911 struct mlx5_flow *dev_flow;
13912 struct mlx5_priv *priv = dev->data->dev_private;
13913 uint32_t handle_idx;
13917 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13918 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13922 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13923 dev_flow = &wks->flows[idx];
13924 dv = &dev_flow->dv;
13925 dh = dev_flow->handle;
13928 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13929 if (dv->transfer) {
13930 MLX5_ASSERT(priv->sh->dr_drop_action);
13931 dv->actions[n++] = priv->sh->dr_drop_action;
13933 #ifdef HAVE_MLX5DV_DR
13934 /* DR supports drop action placeholder. */
13935 MLX5_ASSERT(priv->sh->dr_drop_action);
13936 dv->actions[n++] = dv->group ?
13937 priv->sh->dr_drop_action :
13938 priv->root_drop_action;
13940 /* For DV we use the explicit drop queue. */
13941 MLX5_ASSERT(priv->drop_queue.hrxq);
13943 priv->drop_queue.hrxq->action;
13946 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13947 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13948 struct mlx5_hrxq *hrxq;
13951 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13956 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13957 "cannot get hash queue");
13960 dh->rix_hrxq = hrxq_idx;
13961 dv->actions[n++] = hrxq->action;
13962 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13963 struct mlx5_hrxq *hrxq = NULL;
13966 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13967 rss_desc->shared_rss,
13968 dev_flow->hash_fields);
13970 hrxq = mlx5_ipool_get
13971 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13976 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13977 "cannot get hash queue");
13980 dh->rix_srss = rss_desc->shared_rss;
13981 dv->actions[n++] = hrxq->action;
13982 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13983 if (!priv->sh->default_miss_action) {
13986 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13987 "default miss action not be created.");
13990 dv->actions[n++] = priv->sh->default_miss_action;
13992 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13993 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13994 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13995 (void *)&dv->value, n,
13996 dv->actions, &dh->drv_flow);
14000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14002 (!priv->config.allow_duplicate_pattern &&
14004 "duplicating pattern is not allowed" :
14005 "hardware refuses to create flow");
14008 if (priv->vmwa_context &&
14009 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14011 * The rule contains the VLAN pattern.
14012 * For VF we are going to create VLAN
14013 * interface to make hypervisor set correct
14014 * e-Switch vport context.
14016 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14021 err = rte_errno; /* Save rte_errno before cleanup. */
14022 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14023 handle_idx, dh, next) {
14024 /* hrxq is union, don't clear it if the flag is not set. */
14025 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14026 mlx5_hrxq_release(dev, dh->rix_hrxq);
14028 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14031 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14032 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14034 rte_errno = err; /* Restore rte_errno. */
14039 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14040 struct mlx5_list_entry *entry)
14042 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14046 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14047 mlx5_free(resource);
14051 * Release the flow matcher.
14054 * Pointer to Ethernet device.
14056 * Index to port ID action resource.
14059 * 1 while a reference on it exists, 0 when freed.
14062 flow_dv_matcher_release(struct rte_eth_dev *dev,
14063 struct mlx5_flow_handle *handle)
14065 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14066 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14067 typeof(*tbl), tbl);
14070 MLX5_ASSERT(matcher->matcher_object);
14071 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14072 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14077 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14079 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14080 struct mlx5_flow_dv_encap_decap_resource *res =
14081 container_of(entry, typeof(*res), entry);
14083 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14084 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14088 * Release an encap/decap resource.
14091 * Pointer to Ethernet device.
14092 * @param encap_decap_idx
14093 * Index of encap decap resource.
14096 * 1 while a reference on it exists, 0 when freed.
14099 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14100 uint32_t encap_decap_idx)
14102 struct mlx5_priv *priv = dev->data->dev_private;
14103 struct mlx5_flow_dv_encap_decap_resource *resource;
14105 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14109 MLX5_ASSERT(resource->action);
14110 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14114 * Release an jump to table action resource.
14117 * Pointer to Ethernet device.
14119 * Index to the jump action resource.
14122 * 1 while a reference on it exists, 0 when freed.
14125 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14128 struct mlx5_priv *priv = dev->data->dev_private;
14129 struct mlx5_flow_tbl_data_entry *tbl_data;
14131 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14135 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14139 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14141 struct mlx5_flow_dv_modify_hdr_resource *res =
14142 container_of(entry, typeof(*res), entry);
14143 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14145 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14146 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14150 * Release a modify-header resource.
14153 * Pointer to Ethernet device.
14155 * Pointer to mlx5_flow_handle.
14158 * 1 while a reference on it exists, 0 when freed.
14161 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14162 struct mlx5_flow_handle *handle)
14164 struct mlx5_priv *priv = dev->data->dev_private;
14165 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14167 MLX5_ASSERT(entry->action);
14168 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14172 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14174 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14175 struct mlx5_flow_dv_port_id_action_resource *resource =
14176 container_of(entry, typeof(*resource), entry);
14178 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14179 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14183 * Release port ID action resource.
14186 * Pointer to Ethernet device.
14188 * Pointer to mlx5_flow_handle.
14191 * 1 while a reference on it exists, 0 when freed.
14194 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14197 struct mlx5_priv *priv = dev->data->dev_private;
14198 struct mlx5_flow_dv_port_id_action_resource *resource;
14200 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14203 MLX5_ASSERT(resource->action);
14204 return mlx5_list_unregister(priv->sh->port_id_action_list,
14209 * Release shared RSS action resource.
14212 * Pointer to Ethernet device.
14214 * Shared RSS action index.
14217 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14219 struct mlx5_priv *priv = dev->data->dev_private;
14220 struct mlx5_shared_action_rss *shared_rss;
14222 shared_rss = mlx5_ipool_get
14223 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14224 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14228 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14230 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14231 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14232 container_of(entry, typeof(*resource), entry);
14234 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14235 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14239 * Release push vlan action resource.
14242 * Pointer to Ethernet device.
14244 * Pointer to mlx5_flow_handle.
14247 * 1 while a reference on it exists, 0 when freed.
14250 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14251 struct mlx5_flow_handle *handle)
14253 struct mlx5_priv *priv = dev->data->dev_private;
14254 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14255 uint32_t idx = handle->dvh.rix_push_vlan;
14257 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14260 MLX5_ASSERT(resource->action);
14261 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14266 * Release the fate resource.
14269 * Pointer to Ethernet device.
14271 * Pointer to mlx5_flow_handle.
14274 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14275 struct mlx5_flow_handle *handle)
14277 if (!handle->rix_fate)
14279 switch (handle->fate_action) {
14280 case MLX5_FLOW_FATE_QUEUE:
14281 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14282 mlx5_hrxq_release(dev, handle->rix_hrxq);
14284 case MLX5_FLOW_FATE_JUMP:
14285 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14287 case MLX5_FLOW_FATE_PORT_ID:
14288 flow_dv_port_id_action_resource_release(dev,
14289 handle->rix_port_id_action);
14292 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14295 handle->rix_fate = 0;
14299 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14300 struct mlx5_list_entry *entry)
14302 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14305 struct rte_eth_dev *dev = resource->dev;
14306 struct mlx5_priv *priv = dev->data->dev_private;
14308 if (resource->verbs_action)
14309 claim_zero(mlx5_flow_os_destroy_flow_action
14310 (resource->verbs_action));
14311 if (resource->normal_path_tbl)
14312 flow_dv_tbl_resource_release(MLX5_SH(dev),
14313 resource->normal_path_tbl);
14314 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14315 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14316 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14320 * Release an sample resource.
14323 * Pointer to Ethernet device.
14325 * Pointer to mlx5_flow_handle.
14328 * 1 while a reference on it exists, 0 when freed.
14331 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14332 struct mlx5_flow_handle *handle)
14334 struct mlx5_priv *priv = dev->data->dev_private;
14335 struct mlx5_flow_dv_sample_resource *resource;
14337 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14338 handle->dvh.rix_sample);
14341 MLX5_ASSERT(resource->verbs_action);
14342 return mlx5_list_unregister(priv->sh->sample_action_list,
14347 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14348 struct mlx5_list_entry *entry)
14350 struct mlx5_flow_dv_dest_array_resource *resource =
14351 container_of(entry, typeof(*resource), entry);
14352 struct rte_eth_dev *dev = resource->dev;
14353 struct mlx5_priv *priv = dev->data->dev_private;
14356 MLX5_ASSERT(resource->action);
14357 if (resource->action)
14358 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14359 for (; i < resource->num_of_dest; i++)
14360 flow_dv_sample_sub_actions_release(dev,
14361 &resource->sample_idx[i]);
14362 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14363 DRV_LOG(DEBUG, "destination array resource %p: removed",
14368 * Release an destination array resource.
14371 * Pointer to Ethernet device.
14373 * Pointer to mlx5_flow_handle.
14376 * 1 while a reference on it exists, 0 when freed.
14379 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14380 struct mlx5_flow_handle *handle)
14382 struct mlx5_priv *priv = dev->data->dev_private;
14383 struct mlx5_flow_dv_dest_array_resource *resource;
14385 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14386 handle->dvh.rix_dest_array);
14389 MLX5_ASSERT(resource->action);
14390 return mlx5_list_unregister(priv->sh->dest_array_list,
14395 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14397 struct mlx5_priv *priv = dev->data->dev_private;
14398 struct mlx5_dev_ctx_shared *sh = priv->sh;
14399 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14400 sh->geneve_tlv_option_resource;
14401 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14402 if (geneve_opt_resource) {
14403 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14404 __ATOMIC_RELAXED))) {
14405 claim_zero(mlx5_devx_cmd_destroy
14406 (geneve_opt_resource->obj));
14407 mlx5_free(sh->geneve_tlv_option_resource);
14408 sh->geneve_tlv_option_resource = NULL;
14411 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14415 * Remove the flow from the NIC but keeps it in memory.
14416 * Lock free, (mutex should be acquired by caller).
14419 * Pointer to Ethernet device.
14420 * @param[in, out] flow
14421 * Pointer to flow structure.
14424 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14426 struct mlx5_flow_handle *dh;
14427 uint32_t handle_idx;
14428 struct mlx5_priv *priv = dev->data->dev_private;
14432 handle_idx = flow->dev_handles;
14433 while (handle_idx) {
14434 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14438 if (dh->drv_flow) {
14439 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14440 dh->drv_flow = NULL;
14442 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14443 flow_dv_fate_resource_release(dev, dh);
14444 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14445 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14446 handle_idx = dh->next.next;
14451 * Remove the flow from the NIC and the memory.
14452 * Lock free, (mutex should be acquired by caller).
14455 * Pointer to the Ethernet device structure.
14456 * @param[in, out] flow
14457 * Pointer to flow structure.
14460 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14462 struct mlx5_flow_handle *dev_handle;
14463 struct mlx5_priv *priv = dev->data->dev_private;
14464 struct mlx5_flow_meter_info *fm = NULL;
14469 flow_dv_remove(dev, flow);
14470 if (flow->counter) {
14471 flow_dv_counter_free(dev, flow->counter);
14475 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14477 mlx5_flow_meter_detach(priv, fm);
14480 /* Keep the current age handling by default. */
14481 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14482 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14483 else if (flow->age)
14484 flow_dv_aso_age_release(dev, flow->age);
14485 if (flow->geneve_tlv_option) {
14486 flow_dv_geneve_tlv_option_resource_release(dev);
14487 flow->geneve_tlv_option = 0;
14489 while (flow->dev_handles) {
14490 uint32_t tmp_idx = flow->dev_handles;
14492 dev_handle = mlx5_ipool_get(priv->sh->ipool
14493 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14496 flow->dev_handles = dev_handle->next.next;
14497 while (dev_handle->flex_item) {
14498 int index = rte_bsf32(dev_handle->flex_item);
14500 mlx5_flex_release_index(dev, index);
14501 dev_handle->flex_item &= ~RTE_BIT32(index);
14503 if (dev_handle->dvh.matcher)
14504 flow_dv_matcher_release(dev, dev_handle);
14505 if (dev_handle->dvh.rix_sample)
14506 flow_dv_sample_resource_release(dev, dev_handle);
14507 if (dev_handle->dvh.rix_dest_array)
14508 flow_dv_dest_array_resource_release(dev, dev_handle);
14509 if (dev_handle->dvh.rix_encap_decap)
14510 flow_dv_encap_decap_resource_release(dev,
14511 dev_handle->dvh.rix_encap_decap);
14512 if (dev_handle->dvh.modify_hdr)
14513 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14514 if (dev_handle->dvh.rix_push_vlan)
14515 flow_dv_push_vlan_action_resource_release(dev,
14517 if (dev_handle->dvh.rix_tag)
14518 flow_dv_tag_release(dev,
14519 dev_handle->dvh.rix_tag);
14520 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14521 flow_dv_fate_resource_release(dev, dev_handle);
14523 srss = dev_handle->rix_srss;
14524 if (fm && dev_handle->is_meter_flow_id &&
14525 dev_handle->split_flow_id)
14526 mlx5_ipool_free(fm->flow_ipool,
14527 dev_handle->split_flow_id);
14528 else if (dev_handle->split_flow_id &&
14529 !dev_handle->is_meter_flow_id)
14530 mlx5_ipool_free(priv->sh->ipool
14531 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14532 dev_handle->split_flow_id);
14533 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14537 flow_dv_shared_rss_action_release(dev, srss);
14541 * Release array of hash RX queue objects.
14545 * Pointer to the Ethernet device structure.
14546 * @param[in, out] hrxqs
14547 * Array of hash RX queue objects.
14550 * Total number of references to hash RX queue objects in *hrxqs* array
14551 * after this operation.
14554 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14555 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14560 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14561 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14571 * Release all hash RX queue objects representing shared RSS action.
14574 * Pointer to the Ethernet device structure.
14575 * @param[in, out] action
14576 * Shared RSS action to remove hash RX queue objects from.
14579 * Total number of references to hash RX queue objects stored in *action*
14580 * after this operation.
14581 * Expected to be 0 if no external references held.
14584 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14585 struct mlx5_shared_action_rss *shared_rss)
14587 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14591 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14594 * Only one hash value is available for one L3+L4 combination:
14596 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14597 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14598 * same slot in mlx5_rss_hash_fields.
14601 * Pointer to the shared action RSS conf.
14602 * @param[in, out] hash_field
14603 * hash_field variable needed to be adjusted.
14609 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14610 uint64_t *hash_field)
14612 uint64_t rss_types = rss->origin.types;
14614 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14615 case MLX5_RSS_HASH_IPV4:
14616 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14617 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14618 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14619 *hash_field |= IBV_RX_HASH_DST_IPV4;
14620 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14621 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14623 *hash_field |= MLX5_RSS_HASH_IPV4;
14626 case MLX5_RSS_HASH_IPV6:
14627 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14628 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14629 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14630 *hash_field |= IBV_RX_HASH_DST_IPV6;
14631 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14632 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14634 *hash_field |= MLX5_RSS_HASH_IPV6;
14637 case MLX5_RSS_HASH_IPV4_UDP:
14638 /* fall-through. */
14639 case MLX5_RSS_HASH_IPV6_UDP:
14640 if (rss_types & RTE_ETH_RSS_UDP) {
14641 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14642 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14643 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14644 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14645 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14647 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14650 case MLX5_RSS_HASH_IPV4_TCP:
14651 /* fall-through. */
14652 case MLX5_RSS_HASH_IPV6_TCP:
14653 if (rss_types & RTE_ETH_RSS_TCP) {
14654 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14655 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14656 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14657 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14658 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14660 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14669 * Setup shared RSS action.
14670 * Prepare set of hash RX queue objects sufficient to handle all valid
14671 * hash_fields combinations (see enum ibv_rx_hash_fields).
14674 * Pointer to the Ethernet device structure.
14675 * @param[in] action_idx
14676 * Shared RSS action ipool index.
14677 * @param[in, out] action
14678 * Partially initialized shared RSS action.
14679 * @param[out] error
14680 * Perform verbose error reporting if not NULL. Initialized in case of
14684 * 0 on success, otherwise negative errno value.
14687 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14688 uint32_t action_idx,
14689 struct mlx5_shared_action_rss *shared_rss,
14690 struct rte_flow_error *error)
14692 struct mlx5_flow_rss_desc rss_desc = { 0 };
14696 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl,
14697 !!dev->data->dev_started)) {
14698 return rte_flow_error_set(error, rte_errno,
14699 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14700 "cannot setup indirection table");
14702 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14703 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14704 rss_desc.const_q = shared_rss->origin.queue;
14705 rss_desc.queue_num = shared_rss->origin.queue_num;
14706 /* Set non-zero value to indicate a shared RSS. */
14707 rss_desc.shared_rss = action_idx;
14708 rss_desc.ind_tbl = shared_rss->ind_tbl;
14709 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14711 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14714 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14715 if (shared_rss->origin.level > 1) {
14716 hash_fields |= IBV_RX_HASH_INNER;
14719 rss_desc.tunnel = tunnel;
14720 rss_desc.hash_fields = hash_fields;
14721 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14726 "cannot get hash queue");
14727 goto error_hrxq_new;
14729 err = __flow_dv_action_rss_hrxq_set
14730 (shared_rss, hash_fields, hrxq_idx);
14736 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14737 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true, true))
14738 shared_rss->ind_tbl = NULL;
14744 * Create shared RSS action.
14747 * Pointer to the Ethernet device structure.
14749 * Shared action configuration.
14751 * RSS action specification used to create shared action.
14752 * @param[out] error
14753 * Perform verbose error reporting if not NULL. Initialized in case of
14757 * A valid shared action ID in case of success, 0 otherwise and
14758 * rte_errno is set.
14761 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14762 const struct rte_flow_indir_action_conf *conf,
14763 const struct rte_flow_action_rss *rss,
14764 struct rte_flow_error *error)
14766 struct mlx5_priv *priv = dev->data->dev_private;
14767 struct mlx5_shared_action_rss *shared_rss = NULL;
14768 void *queue = NULL;
14769 struct rte_flow_action_rss *origin;
14770 const uint8_t *rss_key;
14771 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14774 RTE_SET_USED(conf);
14775 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14777 shared_rss = mlx5_ipool_zmalloc
14778 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14779 if (!shared_rss || !queue) {
14780 rte_flow_error_set(error, ENOMEM,
14781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14782 "cannot allocate resource memory");
14783 goto error_rss_init;
14785 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14786 rte_flow_error_set(error, E2BIG,
14787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14788 "rss action number out of range");
14789 goto error_rss_init;
14791 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14792 sizeof(*shared_rss->ind_tbl),
14794 if (!shared_rss->ind_tbl) {
14795 rte_flow_error_set(error, ENOMEM,
14796 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14797 "cannot allocate resource memory");
14798 goto error_rss_init;
14800 memcpy(queue, rss->queue, queue_size);
14801 shared_rss->ind_tbl->queues = queue;
14802 shared_rss->ind_tbl->queues_n = rss->queue_num;
14803 origin = &shared_rss->origin;
14804 origin->func = rss->func;
14805 origin->level = rss->level;
14806 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14807 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14808 /* NULL RSS key indicates default RSS key. */
14809 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14810 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14811 origin->key = &shared_rss->key[0];
14812 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14813 origin->queue = queue;
14814 origin->queue_num = rss->queue_num;
14815 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14816 goto error_rss_init;
14817 rte_spinlock_init(&shared_rss->action_rss_sl);
14818 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14819 rte_spinlock_lock(&priv->shared_act_sl);
14820 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14821 &priv->rss_shared_actions, idx, shared_rss, next);
14822 rte_spinlock_unlock(&priv->shared_act_sl);
14826 if (shared_rss->ind_tbl)
14827 mlx5_free(shared_rss->ind_tbl);
14828 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14837 * Destroy the shared RSS action.
14838 * Release related hash RX queue objects.
14841 * Pointer to the Ethernet device structure.
14843 * The shared RSS action object ID to be removed.
14844 * @param[out] error
14845 * Perform verbose error reporting if not NULL. Initialized in case of
14849 * 0 on success, otherwise negative errno value.
14852 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14853 struct rte_flow_error *error)
14855 struct mlx5_priv *priv = dev->data->dev_private;
14856 struct mlx5_shared_action_rss *shared_rss =
14857 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14858 uint32_t old_refcnt = 1;
14860 uint16_t *queue = NULL;
14863 return rte_flow_error_set(error, EINVAL,
14864 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14865 "invalid shared action");
14866 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14867 0, 0, __ATOMIC_ACQUIRE,
14869 return rte_flow_error_set(error, EBUSY,
14870 RTE_FLOW_ERROR_TYPE_ACTION,
14872 "shared rss has references");
14873 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14875 return rte_flow_error_set(error, EBUSY,
14876 RTE_FLOW_ERROR_TYPE_ACTION,
14878 "shared rss hrxq has references");
14879 queue = shared_rss->ind_tbl->queues;
14880 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true,
14881 !!dev->data->dev_started);
14883 return rte_flow_error_set(error, EBUSY,
14884 RTE_FLOW_ERROR_TYPE_ACTION,
14886 "shared rss indirection table has"
14889 rte_spinlock_lock(&priv->shared_act_sl);
14890 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14891 &priv->rss_shared_actions, idx, shared_rss, next);
14892 rte_spinlock_unlock(&priv->shared_act_sl);
14893 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14899 * Create indirect action, lock free,
14900 * (mutex should be acquired by caller).
14901 * Dispatcher for action type specific call.
14904 * Pointer to the Ethernet device structure.
14906 * Shared action configuration.
14907 * @param[in] action
14908 * Action specification used to create indirect action.
14909 * @param[out] error
14910 * Perform verbose error reporting if not NULL. Initialized in case of
14914 * A valid shared action handle in case of success, NULL otherwise and
14915 * rte_errno is set.
14917 static struct rte_flow_action_handle *
14918 flow_dv_action_create(struct rte_eth_dev *dev,
14919 const struct rte_flow_indir_action_conf *conf,
14920 const struct rte_flow_action *action,
14921 struct rte_flow_error *err)
14923 struct mlx5_priv *priv = dev->data->dev_private;
14924 uint32_t age_idx = 0;
14928 switch (action->type) {
14929 case RTE_FLOW_ACTION_TYPE_RSS:
14930 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14931 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14932 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14934 case RTE_FLOW_ACTION_TYPE_AGE:
14935 age_idx = flow_dv_aso_age_alloc(dev, err);
14940 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14941 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14942 flow_dv_aso_age_params_init(dev, age_idx,
14943 ((const struct rte_flow_action_age *)
14944 action->conf)->context ?
14945 ((const struct rte_flow_action_age *)
14946 action->conf)->context :
14947 (void *)(uintptr_t)idx,
14948 ((const struct rte_flow_action_age *)
14949 action->conf)->timeout);
14952 case RTE_FLOW_ACTION_TYPE_COUNT:
14953 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14954 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14955 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14957 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14958 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14960 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14963 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14964 NULL, "action type not supported");
14967 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14971 * Destroy the indirect action.
14972 * Release action related resources on the NIC and the memory.
14973 * Lock free, (mutex should be acquired by caller).
14974 * Dispatcher for action type specific call.
14977 * Pointer to the Ethernet device structure.
14978 * @param[in] handle
14979 * The indirect action object handle to be removed.
14980 * @param[out] error
14981 * Perform verbose error reporting if not NULL. Initialized in case of
14985 * 0 on success, otherwise negative errno value.
14988 flow_dv_action_destroy(struct rte_eth_dev *dev,
14989 struct rte_flow_action_handle *handle,
14990 struct rte_flow_error *error)
14992 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14993 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14994 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14995 struct mlx5_flow_counter *cnt;
14996 uint32_t no_flow_refcnt = 1;
15000 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15001 return __flow_dv_action_rss_release(dev, idx, error);
15002 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15003 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15004 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15005 &no_flow_refcnt, 1, false,
15008 return rte_flow_error_set(error, EBUSY,
15009 RTE_FLOW_ERROR_TYPE_ACTION,
15011 "Indirect count action has references");
15012 flow_dv_counter_free(dev, idx);
15014 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15015 ret = flow_dv_aso_age_release(dev, idx);
15018 * In this case, the last flow has a reference will
15019 * actually release the age action.
15021 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15022 " released with references %d.", idx, ret);
15024 case MLX5_INDIRECT_ACTION_TYPE_CT:
15025 ret = flow_dv_aso_ct_release(dev, idx, error);
15029 DRV_LOG(DEBUG, "Connection tracking object %u still "
15030 "has references %d.", idx, ret);
15033 return rte_flow_error_set(error, ENOTSUP,
15034 RTE_FLOW_ERROR_TYPE_ACTION,
15036 "action type not supported");
15041 * Updates in place shared RSS action configuration.
15044 * Pointer to the Ethernet device structure.
15046 * The shared RSS action object ID to be updated.
15047 * @param[in] action_conf
15048 * RSS action specification used to modify *shared_rss*.
15049 * @param[out] error
15050 * Perform verbose error reporting if not NULL. Initialized in case of
15054 * 0 on success, otherwise negative errno value.
15055 * @note: currently only support update of RSS queues.
15058 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15059 const struct rte_flow_action_rss *action_conf,
15060 struct rte_flow_error *error)
15062 struct mlx5_priv *priv = dev->data->dev_private;
15063 struct mlx5_shared_action_rss *shared_rss =
15064 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15066 void *queue = NULL;
15067 uint16_t *queue_old = NULL;
15068 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15069 bool dev_started = !!dev->data->dev_started;
15072 return rte_flow_error_set(error, EINVAL,
15073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15074 "invalid shared action to update");
15075 if (priv->obj_ops.ind_table_modify == NULL)
15076 return rte_flow_error_set(error, ENOTSUP,
15077 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15078 "cannot modify indirection table");
15079 queue = mlx5_malloc(MLX5_MEM_ZERO,
15080 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15083 return rte_flow_error_set(error, ENOMEM,
15084 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15086 "cannot allocate resource memory");
15087 memcpy(queue, action_conf->queue, queue_size);
15088 MLX5_ASSERT(shared_rss->ind_tbl);
15089 rte_spinlock_lock(&shared_rss->action_rss_sl);
15090 queue_old = shared_rss->ind_tbl->queues;
15091 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15092 queue, action_conf->queue_num,
15093 true /* standalone */,
15094 dev_started /* ref_new_qs */,
15095 dev_started /* deref_old_qs */);
15098 ret = rte_flow_error_set(error, rte_errno,
15099 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15100 "cannot update indirection table");
15102 mlx5_free(queue_old);
15103 shared_rss->origin.queue = queue;
15104 shared_rss->origin.queue_num = action_conf->queue_num;
15106 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15111 * Updates in place conntrack context or direction.
15112 * Context update should be synchronized.
15115 * Pointer to the Ethernet device structure.
15117 * The conntrack object ID to be updated.
15118 * @param[in] update
15119 * Pointer to the structure of information to update.
15120 * @param[out] error
15121 * Perform verbose error reporting if not NULL. Initialized in case of
15125 * 0 on success, otherwise negative errno value.
15128 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15129 const struct rte_flow_modify_conntrack *update,
15130 struct rte_flow_error *error)
15132 struct mlx5_priv *priv = dev->data->dev_private;
15133 struct mlx5_aso_ct_action *ct;
15134 const struct rte_flow_action_conntrack *new_prf;
15136 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15139 if (PORT_ID(priv) != owner)
15140 return rte_flow_error_set(error, EACCES,
15141 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15143 "CT object owned by another port");
15144 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15145 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15147 return rte_flow_error_set(error, ENOMEM,
15148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15150 "CT object is inactive");
15151 new_prf = &update->new_ct;
15152 if (update->direction)
15153 ct->is_original = !!new_prf->is_original_dir;
15154 if (update->state) {
15155 /* Only validate the profile when it needs to be updated. */
15156 ret = mlx5_validate_action_ct(dev, new_prf, error);
15159 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15161 return rte_flow_error_set(error, EIO,
15162 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15164 "Failed to send CT context update WQE");
15165 /* Block until ready or a failure. */
15166 ret = mlx5_aso_ct_available(priv->sh, ct);
15168 rte_flow_error_set(error, rte_errno,
15169 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15171 "Timeout to get the CT update");
15177 * Updates in place shared action configuration, lock free,
15178 * (mutex should be acquired by caller).
15181 * Pointer to the Ethernet device structure.
15182 * @param[in] handle
15183 * The indirect action object handle to be updated.
15184 * @param[in] update
15185 * Action specification used to modify the action pointed by *handle*.
15186 * *update* could be of same type with the action pointed by the *handle*
15187 * handle argument, or some other structures like a wrapper, depending on
15188 * the indirect action type.
15189 * @param[out] error
15190 * Perform verbose error reporting if not NULL. Initialized in case of
15194 * 0 on success, otherwise negative errno value.
15197 flow_dv_action_update(struct rte_eth_dev *dev,
15198 struct rte_flow_action_handle *handle,
15199 const void *update,
15200 struct rte_flow_error *err)
15202 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15203 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15204 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15205 const void *action_conf;
15208 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15209 action_conf = ((const struct rte_flow_action *)update)->conf;
15210 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15211 case MLX5_INDIRECT_ACTION_TYPE_CT:
15212 return __flow_dv_action_ct_update(dev, idx, update, err);
15214 return rte_flow_error_set(err, ENOTSUP,
15215 RTE_FLOW_ERROR_TYPE_ACTION,
15217 "action type update not supported");
15222 * Destroy the meter sub policy table rules.
15223 * Lock free, (mutex should be acquired by caller).
15226 * Pointer to Ethernet device.
15227 * @param[in] sub_policy
15228 * Pointer to meter sub policy table.
15231 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15232 struct mlx5_flow_meter_sub_policy *sub_policy)
15234 struct mlx5_priv *priv = dev->data->dev_private;
15235 struct mlx5_flow_tbl_data_entry *tbl;
15236 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15237 struct mlx5_flow_meter_info *next_fm;
15238 struct mlx5_sub_policy_color_rule *color_rule;
15242 for (i = 0; i < RTE_COLORS; i++) {
15244 if (i == RTE_COLOR_GREEN && policy &&
15245 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15246 next_fm = mlx5_flow_meter_find(priv,
15247 policy->act_cnt[i].next_mtr_id, NULL);
15248 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15250 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15251 tbl = container_of(color_rule->matcher->tbl,
15252 typeof(*tbl), tbl);
15253 mlx5_list_unregister(tbl->matchers,
15254 &color_rule->matcher->entry);
15255 TAILQ_REMOVE(&sub_policy->color_rules[i],
15256 color_rule, next_port);
15257 mlx5_free(color_rule);
15259 mlx5_flow_meter_detach(priv, next_fm);
15262 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15263 if (sub_policy->rix_hrxq[i]) {
15264 if (policy && !policy->is_hierarchy)
15265 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15266 sub_policy->rix_hrxq[i] = 0;
15268 if (sub_policy->jump_tbl[i]) {
15269 flow_dv_tbl_resource_release(MLX5_SH(dev),
15270 sub_policy->jump_tbl[i]);
15271 sub_policy->jump_tbl[i] = NULL;
15274 if (sub_policy->tbl_rsc) {
15275 flow_dv_tbl_resource_release(MLX5_SH(dev),
15276 sub_policy->tbl_rsc);
15277 sub_policy->tbl_rsc = NULL;
15282 * Destroy policy rules, lock free,
15283 * (mutex should be acquired by caller).
15284 * Dispatcher for action type specific call.
15287 * Pointer to the Ethernet device structure.
15288 * @param[in] mtr_policy
15289 * Meter policy struct.
15292 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15293 struct mlx5_flow_meter_policy *mtr_policy)
15296 struct mlx5_flow_meter_sub_policy *sub_policy;
15297 uint16_t sub_policy_num;
15299 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15300 sub_policy_num = (mtr_policy->sub_policy_num >>
15301 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15302 MLX5_MTR_SUB_POLICY_NUM_MASK;
15303 for (j = 0; j < sub_policy_num; j++) {
15304 sub_policy = mtr_policy->sub_policys[i][j];
15306 __flow_dv_destroy_sub_policy_rules(dev,
15313 * Destroy policy action, lock free,
15314 * (mutex should be acquired by caller).
15315 * Dispatcher for action type specific call.
15318 * Pointer to the Ethernet device structure.
15319 * @param[in] mtr_policy
15320 * Meter policy struct.
15323 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15324 struct mlx5_flow_meter_policy *mtr_policy)
15326 struct rte_flow_action *rss_action;
15327 struct mlx5_flow_handle dev_handle;
15330 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15331 if (mtr_policy->act_cnt[i].rix_mark) {
15332 flow_dv_tag_release(dev,
15333 mtr_policy->act_cnt[i].rix_mark);
15334 mtr_policy->act_cnt[i].rix_mark = 0;
15336 if (mtr_policy->act_cnt[i].modify_hdr) {
15337 dev_handle.dvh.modify_hdr =
15338 mtr_policy->act_cnt[i].modify_hdr;
15339 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15341 switch (mtr_policy->act_cnt[i].fate_action) {
15342 case MLX5_FLOW_FATE_SHARED_RSS:
15343 rss_action = mtr_policy->act_cnt[i].rss;
15344 mlx5_free(rss_action);
15346 case MLX5_FLOW_FATE_PORT_ID:
15347 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15348 flow_dv_port_id_action_resource_release(dev,
15349 mtr_policy->act_cnt[i].rix_port_id_action);
15350 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15353 case MLX5_FLOW_FATE_DROP:
15354 case MLX5_FLOW_FATE_JUMP:
15355 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15356 mtr_policy->act_cnt[i].dr_jump_action[j] =
15360 /*Queue action do nothing*/
15364 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15365 mtr_policy->dr_drop_action[j] = NULL;
15369 * Create policy action per domain, lock free,
15370 * (mutex should be acquired by caller).
15371 * Dispatcher for action type specific call.
15374 * Pointer to the Ethernet device structure.
15375 * @param[in] mtr_policy
15376 * Meter policy struct.
15377 * @param[in] action
15378 * Action specification used to create meter actions.
15379 * @param[out] error
15380 * Perform verbose error reporting if not NULL. Initialized in case of
15384 * 0 on success, otherwise negative errno value.
15387 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15388 struct mlx5_flow_meter_policy *mtr_policy,
15389 const struct rte_flow_action *actions[RTE_COLORS],
15390 enum mlx5_meter_domain domain,
15391 struct rte_mtr_error *error)
15393 struct mlx5_priv *priv = dev->data->dev_private;
15394 struct rte_flow_error flow_err;
15395 const struct rte_flow_action *act;
15396 uint64_t action_flags;
15397 struct mlx5_flow_handle dh;
15398 struct mlx5_flow dev_flow;
15399 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15401 uint8_t egress, transfer;
15402 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15404 struct mlx5_flow_dv_modify_hdr_resource res;
15405 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15406 sizeof(struct mlx5_modification_cmd) *
15407 (MLX5_MAX_MODIFY_NUM + 1)];
15409 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15410 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
15413 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15414 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15415 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15416 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15417 memset(&port_id_action, 0,
15418 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15419 memset(mhdr_res, 0, sizeof(*mhdr_res));
15420 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15421 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15422 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15423 dev_flow.handle = &dh;
15424 dev_flow.dv.port_id_action = &port_id_action;
15425 dev_flow.external = true;
15426 for (i = 0; i < RTE_COLORS; i++) {
15427 if (i < MLX5_MTR_RTE_COLORS)
15428 act_cnt = &mtr_policy->act_cnt[i];
15429 /* Skip the color policy actions creation. */
15430 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15431 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15434 for (act = actions[i];
15435 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15436 switch (act->type) {
15437 case RTE_FLOW_ACTION_TYPE_MARK:
15439 uint32_t tag_be = mlx5_flow_mark_set
15440 (((const struct rte_flow_action_mark *)
15443 if (i >= MLX5_MTR_RTE_COLORS)
15444 return -rte_mtr_error_set(error,
15446 RTE_MTR_ERROR_TYPE_METER_POLICY,
15448 "cannot create policy "
15449 "mark action for this color");
15451 if (flow_dv_tag_resource_register(dev, tag_be,
15452 &dev_flow, &flow_err))
15453 return -rte_mtr_error_set(error,
15455 RTE_MTR_ERROR_TYPE_METER_POLICY,
15457 "cannot setup policy mark action");
15458 MLX5_ASSERT(dev_flow.dv.tag_resource);
15459 act_cnt->rix_mark =
15460 dev_flow.handle->dvh.rix_tag;
15461 action_flags |= MLX5_FLOW_ACTION_MARK;
15464 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15465 if (i >= MLX5_MTR_RTE_COLORS)
15466 return -rte_mtr_error_set(error,
15468 RTE_MTR_ERROR_TYPE_METER_POLICY,
15470 "cannot create policy "
15471 "set tag action for this color");
15472 if (flow_dv_convert_action_set_tag
15474 (const struct rte_flow_action_set_tag *)
15475 act->conf, &flow_err))
15476 return -rte_mtr_error_set(error,
15478 RTE_MTR_ERROR_TYPE_METER_POLICY,
15479 NULL, "cannot convert policy "
15481 if (!mhdr_res->actions_num)
15482 return -rte_mtr_error_set(error,
15484 RTE_MTR_ERROR_TYPE_METER_POLICY,
15485 NULL, "cannot find policy "
15487 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15489 case RTE_FLOW_ACTION_TYPE_DROP:
15491 struct mlx5_flow_mtr_mng *mtrmng =
15493 struct mlx5_flow_tbl_data_entry *tbl_data;
15496 * Create the drop table with
15497 * METER DROP level.
15499 if (!mtrmng->drop_tbl[domain]) {
15500 mtrmng->drop_tbl[domain] =
15501 flow_dv_tbl_resource_get(dev,
15502 MLX5_FLOW_TABLE_LEVEL_METER,
15503 egress, transfer, false, NULL, 0,
15504 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15505 if (!mtrmng->drop_tbl[domain])
15506 return -rte_mtr_error_set
15508 RTE_MTR_ERROR_TYPE_METER_POLICY,
15510 "Failed to create meter drop table");
15512 tbl_data = container_of
15513 (mtrmng->drop_tbl[domain],
15514 struct mlx5_flow_tbl_data_entry, tbl);
15515 if (i < MLX5_MTR_RTE_COLORS) {
15516 act_cnt->dr_jump_action[domain] =
15517 tbl_data->jump.action;
15518 act_cnt->fate_action =
15519 MLX5_FLOW_FATE_DROP;
15521 if (i == RTE_COLOR_RED)
15522 mtr_policy->dr_drop_action[domain] =
15523 tbl_data->jump.action;
15524 action_flags |= MLX5_FLOW_ACTION_DROP;
15527 case RTE_FLOW_ACTION_TYPE_QUEUE:
15529 if (i >= MLX5_MTR_RTE_COLORS)
15530 return -rte_mtr_error_set(error,
15532 RTE_MTR_ERROR_TYPE_METER_POLICY,
15533 NULL, "cannot create policy "
15534 "fate queue for this color");
15536 ((const struct rte_flow_action_queue *)
15537 (act->conf))->index;
15538 act_cnt->fate_action =
15539 MLX5_FLOW_FATE_QUEUE;
15540 dev_flow.handle->fate_action =
15541 MLX5_FLOW_FATE_QUEUE;
15542 mtr_policy->is_queue = 1;
15543 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15546 case RTE_FLOW_ACTION_TYPE_RSS:
15550 if (i >= MLX5_MTR_RTE_COLORS)
15551 return -rte_mtr_error_set(error,
15553 RTE_MTR_ERROR_TYPE_METER_POLICY,
15555 "cannot create policy "
15556 "rss action for this color");
15558 * Save RSS conf into policy struct
15559 * for translate stage.
15561 rss_size = (int)rte_flow_conv
15562 (RTE_FLOW_CONV_OP_ACTION,
15563 NULL, 0, act, &flow_err);
15565 return -rte_mtr_error_set(error,
15567 RTE_MTR_ERROR_TYPE_METER_POLICY,
15568 NULL, "Get the wrong "
15569 "rss action struct size");
15570 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15571 rss_size, 0, SOCKET_ID_ANY);
15573 return -rte_mtr_error_set(error,
15575 RTE_MTR_ERROR_TYPE_METER_POLICY,
15577 "Fail to malloc rss action memory");
15578 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15579 act_cnt->rss, rss_size,
15582 return -rte_mtr_error_set(error,
15584 RTE_MTR_ERROR_TYPE_METER_POLICY,
15585 NULL, "Fail to save "
15586 "rss action into policy struct");
15587 act_cnt->fate_action =
15588 MLX5_FLOW_FATE_SHARED_RSS;
15589 action_flags |= MLX5_FLOW_ACTION_RSS;
15592 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15593 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15595 struct mlx5_flow_dv_port_id_action_resource
15597 uint32_t port_id = 0;
15599 if (i >= MLX5_MTR_RTE_COLORS)
15600 return -rte_mtr_error_set(error,
15602 RTE_MTR_ERROR_TYPE_METER_POLICY,
15603 NULL, "cannot create policy "
15604 "port action for this color");
15605 memset(&port_id_resource, 0,
15606 sizeof(port_id_resource));
15607 if (flow_dv_translate_action_port_id(dev, act,
15608 &port_id, &flow_err))
15609 return -rte_mtr_error_set(error,
15611 RTE_MTR_ERROR_TYPE_METER_POLICY,
15612 NULL, "cannot translate "
15613 "policy port action");
15614 port_id_resource.port_id = port_id;
15615 if (flow_dv_port_id_action_resource_register
15616 (dev, &port_id_resource,
15617 &dev_flow, &flow_err))
15618 return -rte_mtr_error_set(error,
15620 RTE_MTR_ERROR_TYPE_METER_POLICY,
15621 NULL, "cannot setup "
15622 "policy port action");
15623 act_cnt->rix_port_id_action =
15624 dev_flow.handle->rix_port_id_action;
15625 act_cnt->fate_action =
15626 MLX5_FLOW_FATE_PORT_ID;
15627 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15630 case RTE_FLOW_ACTION_TYPE_JUMP:
15632 uint32_t jump_group = 0;
15633 uint32_t table = 0;
15634 struct mlx5_flow_tbl_data_entry *tbl_data;
15635 struct flow_grp_info grp_info = {
15636 .external = !!dev_flow.external,
15637 .transfer = !!transfer,
15638 .fdb_def_rule = !!priv->fdb_def_rule,
15640 .skip_scale = dev_flow.skip_scale &
15641 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15643 struct mlx5_flow_meter_sub_policy *sub_policy =
15644 mtr_policy->sub_policys[domain][0];
15646 if (i >= MLX5_MTR_RTE_COLORS)
15647 return -rte_mtr_error_set(error,
15649 RTE_MTR_ERROR_TYPE_METER_POLICY,
15651 "cannot create policy "
15652 "jump action for this color");
15654 ((const struct rte_flow_action_jump *)
15656 if (mlx5_flow_group_to_table(dev, NULL,
15659 &grp_info, &flow_err))
15660 return -rte_mtr_error_set(error,
15662 RTE_MTR_ERROR_TYPE_METER_POLICY,
15663 NULL, "cannot setup "
15664 "policy jump action");
15665 sub_policy->jump_tbl[i] =
15666 flow_dv_tbl_resource_get(dev,
15669 !!dev_flow.external,
15670 NULL, jump_group, 0,
15673 (!sub_policy->jump_tbl[i])
15674 return -rte_mtr_error_set(error,
15676 RTE_MTR_ERROR_TYPE_METER_POLICY,
15677 NULL, "cannot create jump action.");
15678 tbl_data = container_of
15679 (sub_policy->jump_tbl[i],
15680 struct mlx5_flow_tbl_data_entry, tbl);
15681 act_cnt->dr_jump_action[domain] =
15682 tbl_data->jump.action;
15683 act_cnt->fate_action =
15684 MLX5_FLOW_FATE_JUMP;
15685 action_flags |= MLX5_FLOW_ACTION_JUMP;
15689 * No need to check meter hierarchy for Y or R colors
15690 * here since it is done in the validation stage.
15692 case RTE_FLOW_ACTION_TYPE_METER:
15694 const struct rte_flow_action_meter *mtr;
15695 struct mlx5_flow_meter_info *next_fm;
15696 struct mlx5_flow_meter_policy *next_policy;
15697 struct rte_flow_action tag_action;
15698 struct mlx5_rte_flow_action_set_tag set_tag;
15699 uint32_t next_mtr_idx = 0;
15702 next_fm = mlx5_flow_meter_find(priv,
15706 return -rte_mtr_error_set(error, EINVAL,
15707 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15708 "Fail to find next meter.");
15709 if (next_fm->def_policy)
15710 return -rte_mtr_error_set(error, EINVAL,
15711 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15712 "Hierarchy only supports termination meter.");
15713 next_policy = mlx5_flow_meter_policy_find(dev,
15714 next_fm->policy_id, NULL);
15715 MLX5_ASSERT(next_policy);
15716 if (next_fm->drop_cnt) {
15719 mlx5_flow_get_reg_id(dev,
15722 (struct rte_flow_error *)error);
15723 set_tag.offset = (priv->mtr_reg_share ?
15724 MLX5_MTR_COLOR_BITS : 0);
15725 set_tag.length = (priv->mtr_reg_share ?
15726 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15728 set_tag.data = next_mtr_idx;
15730 (enum rte_flow_action_type)
15731 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15732 tag_action.conf = &set_tag;
15733 if (flow_dv_convert_action_set_reg
15734 (mhdr_res, &tag_action,
15735 (struct rte_flow_error *)error))
15738 MLX5_FLOW_ACTION_SET_TAG;
15740 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15741 act_cnt->next_mtr_id = next_fm->meter_id;
15742 act_cnt->next_sub_policy = NULL;
15743 mtr_policy->is_hierarchy = 1;
15744 mtr_policy->dev = next_policy->dev;
15746 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15750 return -rte_mtr_error_set(error, ENOTSUP,
15751 RTE_MTR_ERROR_TYPE_METER_POLICY,
15752 NULL, "action type not supported");
15754 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15755 /* create modify action if needed. */
15756 dev_flow.dv.group = 1;
15757 if (flow_dv_modify_hdr_resource_register
15758 (dev, mhdr_res, &dev_flow, &flow_err))
15759 return -rte_mtr_error_set(error,
15761 RTE_MTR_ERROR_TYPE_METER_POLICY,
15762 NULL, "cannot register policy "
15764 act_cnt->modify_hdr =
15765 dev_flow.handle->dvh.modify_hdr;
15773 * Create policy action per domain, lock free,
15774 * (mutex should be acquired by caller).
15775 * Dispatcher for action type specific call.
15778 * Pointer to the Ethernet device structure.
15779 * @param[in] mtr_policy
15780 * Meter policy struct.
15781 * @param[in] action
15782 * Action specification used to create meter actions.
15783 * @param[out] error
15784 * Perform verbose error reporting if not NULL. Initialized in case of
15788 * 0 on success, otherwise negative errno value.
15791 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15792 struct mlx5_flow_meter_policy *mtr_policy,
15793 const struct rte_flow_action *actions[RTE_COLORS],
15794 struct rte_mtr_error *error)
15797 uint16_t sub_policy_num;
15799 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15800 sub_policy_num = (mtr_policy->sub_policy_num >>
15801 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15802 MLX5_MTR_SUB_POLICY_NUM_MASK;
15803 if (sub_policy_num) {
15804 ret = __flow_dv_create_domain_policy_acts(dev,
15805 mtr_policy, actions,
15806 (enum mlx5_meter_domain)i, error);
15807 /* Cleaning resource is done in the caller level. */
15816 * Query a DV flow rule for its statistics via DevX.
15819 * Pointer to Ethernet device.
15820 * @param[in] cnt_idx
15821 * Index to the flow counter.
15823 * Data retrieved by the query.
15824 * @param[out] error
15825 * Perform verbose error reporting if not NULL.
15828 * 0 on success, a negative errno value otherwise and rte_errno is set.
15831 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15832 struct rte_flow_error *error)
15834 struct mlx5_priv *priv = dev->data->dev_private;
15835 struct rte_flow_query_count *qc = data;
15837 if (!priv->sh->devx)
15838 return rte_flow_error_set(error, ENOTSUP,
15839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15841 "counters are not supported");
15843 uint64_t pkts, bytes;
15844 struct mlx5_flow_counter *cnt;
15845 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15848 return rte_flow_error_set(error, -err,
15849 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15850 NULL, "cannot read counters");
15851 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15854 qc->hits = pkts - cnt->hits;
15855 qc->bytes = bytes - cnt->bytes;
15858 cnt->bytes = bytes;
15862 return rte_flow_error_set(error, EINVAL,
15863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15865 "counters are not available");
15870 * Query counter's action pointer for a DV flow rule via DevX.
15873 * Pointer to Ethernet device.
15874 * @param[in] cnt_idx
15875 * Index to the flow counter.
15876 * @param[out] action_ptr
15877 * Action pointer for counter.
15878 * @param[out] error
15879 * Perform verbose error reporting if not NULL.
15882 * 0 on success, a negative errno value otherwise and rte_errno is set.
15885 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15886 void **action_ptr, struct rte_flow_error *error)
15888 struct mlx5_priv *priv = dev->data->dev_private;
15890 if (!priv->sh->devx || !action_ptr)
15891 return rte_flow_error_set(error, ENOTSUP,
15892 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15894 "counters are not supported");
15897 struct mlx5_flow_counter *cnt = NULL;
15898 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15900 *action_ptr = cnt->action;
15904 return rte_flow_error_set(error, EINVAL,
15905 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15907 "counters are not available");
15911 flow_dv_action_query(struct rte_eth_dev *dev,
15912 const struct rte_flow_action_handle *handle, void *data,
15913 struct rte_flow_error *error)
15915 struct mlx5_age_param *age_param;
15916 struct rte_flow_query_age *resp;
15917 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15918 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15919 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15920 struct mlx5_priv *priv = dev->data->dev_private;
15921 struct mlx5_aso_ct_action *ct;
15926 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15927 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15929 resp->aged = __atomic_load_n(&age_param->state,
15930 __ATOMIC_RELAXED) == AGE_TMOUT ?
15932 resp->sec_since_last_hit_valid = !resp->aged;
15933 if (resp->sec_since_last_hit_valid)
15934 resp->sec_since_last_hit = __atomic_load_n
15935 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15937 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15938 return flow_dv_query_count(dev, idx, data, error);
15939 case MLX5_INDIRECT_ACTION_TYPE_CT:
15940 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15941 if (owner != PORT_ID(priv))
15942 return rte_flow_error_set(error, EACCES,
15943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15945 "CT object owned by another port");
15946 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15947 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15950 return rte_flow_error_set(error, EFAULT,
15951 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15953 "CT object is inactive");
15954 ((struct rte_flow_action_conntrack *)data)->peer_port =
15956 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15958 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15959 return rte_flow_error_set(error, EIO,
15960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15962 "Failed to query CT context");
15965 return rte_flow_error_set(error, ENOTSUP,
15966 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15967 "action type query not supported");
15972 * Query a flow rule AGE action for aging information.
15975 * Pointer to Ethernet device.
15977 * Pointer to the sub flow.
15979 * data retrieved by the query.
15980 * @param[out] error
15981 * Perform verbose error reporting if not NULL.
15984 * 0 on success, a negative errno value otherwise and rte_errno is set.
15987 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15988 void *data, struct rte_flow_error *error)
15990 struct rte_flow_query_age *resp = data;
15991 struct mlx5_age_param *age_param;
15994 struct mlx5_aso_age_action *act =
15995 flow_aso_age_get_by_idx(dev, flow->age);
15997 age_param = &act->age_params;
15998 } else if (flow->counter) {
15999 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16001 if (!age_param || !age_param->timeout)
16002 return rte_flow_error_set
16004 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16005 NULL, "cannot read age data");
16007 return rte_flow_error_set(error, EINVAL,
16008 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16009 NULL, "age data not available");
16011 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16013 resp->sec_since_last_hit_valid = !resp->aged;
16014 if (resp->sec_since_last_hit_valid)
16015 resp->sec_since_last_hit = __atomic_load_n
16016 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16023 * @see rte_flow_query()
16024 * @see rte_flow_ops
16027 flow_dv_query(struct rte_eth_dev *dev,
16028 struct rte_flow *flow __rte_unused,
16029 const struct rte_flow_action *actions __rte_unused,
16030 void *data __rte_unused,
16031 struct rte_flow_error *error __rte_unused)
16035 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16036 switch (actions->type) {
16037 case RTE_FLOW_ACTION_TYPE_VOID:
16039 case RTE_FLOW_ACTION_TYPE_COUNT:
16040 ret = flow_dv_query_count(dev, flow->counter, data,
16043 case RTE_FLOW_ACTION_TYPE_AGE:
16044 ret = flow_dv_query_age(dev, flow, data, error);
16047 return rte_flow_error_set(error, ENOTSUP,
16048 RTE_FLOW_ERROR_TYPE_ACTION,
16050 "action not supported");
16057 * Destroy the meter table set.
16058 * Lock free, (mutex should be acquired by caller).
16061 * Pointer to Ethernet device.
16063 * Meter information table.
16066 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16067 struct mlx5_flow_meter_info *fm)
16069 struct mlx5_priv *priv = dev->data->dev_private;
16072 if (!fm || !priv->config.dv_flow_en)
16074 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16075 if (fm->drop_rule[i]) {
16076 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16077 fm->drop_rule[i] = NULL;
16083 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16085 struct mlx5_priv *priv = dev->data->dev_private;
16086 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16087 struct mlx5_flow_tbl_data_entry *tbl;
16090 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16091 if (mtrmng->def_rule[i]) {
16092 claim_zero(mlx5_flow_os_destroy_flow
16093 (mtrmng->def_rule[i]));
16094 mtrmng->def_rule[i] = NULL;
16096 if (mtrmng->def_matcher[i]) {
16097 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16098 struct mlx5_flow_tbl_data_entry, tbl);
16099 mlx5_list_unregister(tbl->matchers,
16100 &mtrmng->def_matcher[i]->entry);
16101 mtrmng->def_matcher[i] = NULL;
16103 for (j = 0; j < MLX5_REG_BITS; j++) {
16104 if (mtrmng->drop_matcher[i][j]) {
16106 container_of(mtrmng->drop_matcher[i][j]->tbl,
16107 struct mlx5_flow_tbl_data_entry,
16109 mlx5_list_unregister(tbl->matchers,
16110 &mtrmng->drop_matcher[i][j]->entry);
16111 mtrmng->drop_matcher[i][j] = NULL;
16114 if (mtrmng->drop_tbl[i]) {
16115 flow_dv_tbl_resource_release(MLX5_SH(dev),
16116 mtrmng->drop_tbl[i]);
16117 mtrmng->drop_tbl[i] = NULL;
16122 /* Number of meter flow actions, count and jump or count and drop. */
16123 #define METER_ACTIONS 2
16126 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16127 enum mlx5_meter_domain domain)
16129 struct mlx5_priv *priv = dev->data->dev_private;
16130 struct mlx5_flow_meter_def_policy *def_policy =
16131 priv->sh->mtrmng->def_policy[domain];
16133 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16134 mlx5_free(def_policy);
16135 priv->sh->mtrmng->def_policy[domain] = NULL;
16139 * Destroy the default policy table set.
16142 * Pointer to Ethernet device.
16145 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16147 struct mlx5_priv *priv = dev->data->dev_private;
16150 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16151 if (priv->sh->mtrmng->def_policy[i])
16152 __flow_dv_destroy_domain_def_policy(dev,
16153 (enum mlx5_meter_domain)i);
16154 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16158 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16159 uint32_t color_reg_c_idx,
16160 enum rte_color color, void *matcher_object,
16161 int actions_n, void *actions,
16162 bool match_src_port, const struct rte_flow_item *item,
16163 void **rule, const struct rte_flow_attr *attr)
16166 struct mlx5_flow_dv_match_params value = {
16167 .size = sizeof(value.buf),
16169 struct mlx5_flow_dv_match_params matcher = {
16170 .size = sizeof(matcher.buf),
16172 struct mlx5_priv *priv = dev->data->dev_private;
16175 if (match_src_port && (priv->representor || priv->master)) {
16176 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16177 value.buf, item, attr)) {
16178 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16179 " value with port.", color);
16183 flow_dv_match_meta_reg(matcher.buf, value.buf,
16184 (enum modify_reg)color_reg_c_idx,
16185 rte_col_2_mlx5_col(color), UINT32_MAX);
16186 misc_mask = flow_dv_matcher_enable(value.buf);
16187 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16188 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16189 actions_n, actions, rule);
16191 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16198 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16199 uint32_t color_reg_c_idx,
16201 struct mlx5_flow_meter_sub_policy *sub_policy,
16202 const struct rte_flow_attr *attr,
16203 bool match_src_port,
16204 const struct rte_flow_item *item,
16205 struct mlx5_flow_dv_matcher **policy_matcher,
16206 struct rte_flow_error *error)
16208 struct mlx5_list_entry *entry;
16209 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16210 struct mlx5_flow_dv_matcher matcher = {
16212 .size = sizeof(matcher.mask.buf),
16216 struct mlx5_flow_dv_match_params value = {
16217 .size = sizeof(value.buf),
16219 struct mlx5_flow_cb_ctx ctx = {
16223 struct mlx5_flow_tbl_data_entry *tbl_data;
16224 struct mlx5_priv *priv = dev->data->dev_private;
16225 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16227 if (match_src_port && (priv->representor || priv->master)) {
16228 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16229 value.buf, item, attr)) {
16230 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16231 " with port.", priority);
16235 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16236 if (priority < RTE_COLOR_RED)
16237 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16238 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16239 matcher.priority = priority;
16240 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16241 matcher.mask.size);
16242 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16244 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16248 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16253 * Create the policy rules per domain.
16256 * Pointer to Ethernet device.
16257 * @param[in] sub_policy
16258 * Pointer to sub policy table..
16259 * @param[in] egress
16260 * Direction of the table.
16261 * @param[in] transfer
16262 * E-Switch or NIC flow.
16264 * Pointer to policy action list per color.
16267 * 0 on success, -1 otherwise.
16270 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16271 struct mlx5_flow_meter_sub_policy *sub_policy,
16272 uint8_t egress, uint8_t transfer, bool match_src_port,
16273 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16275 struct mlx5_priv *priv = dev->data->dev_private;
16276 struct rte_flow_error flow_err;
16277 uint32_t color_reg_c_idx;
16278 struct rte_flow_attr attr = {
16279 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16282 .egress = !!egress,
16283 .transfer = !!transfer,
16287 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16288 struct mlx5_sub_policy_color_rule *color_rule;
16290 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16294 /* Create policy table with POLICY level. */
16295 if (!sub_policy->tbl_rsc)
16296 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16297 MLX5_FLOW_TABLE_LEVEL_POLICY,
16298 egress, transfer, false, NULL, 0, 0,
16299 sub_policy->idx, &flow_err);
16300 if (!sub_policy->tbl_rsc) {
16302 "Failed to create meter sub policy table.");
16305 /* Prepare matchers. */
16306 color_reg_c_idx = ret;
16307 for (i = 0; i < RTE_COLORS; i++) {
16308 TAILQ_INIT(&sub_policy->color_rules[i]);
16309 if (!acts[i].actions_n)
16311 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16312 sizeof(struct mlx5_sub_policy_color_rule),
16315 DRV_LOG(ERR, "No memory to create color rule.");
16318 tmp_rules[i] = color_rule;
16319 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16320 color_rule, next_port);
16321 color_rule->src_port = priv->representor_id;
16324 /* Create matchers for colors. */
16325 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16326 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16327 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16328 &attr, svport_match, NULL,
16329 &color_rule->matcher, &flow_err)) {
16330 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16333 /* Create flow, matching color. */
16334 if (__flow_dv_create_policy_flow(dev,
16335 color_reg_c_idx, (enum rte_color)i,
16336 color_rule->matcher->matcher_object,
16337 acts[i].actions_n, acts[i].dv_actions,
16338 svport_match, NULL, &color_rule->rule,
16340 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16346 /* All the policy rules will be cleared. */
16348 color_rule = tmp_rules[i];
16350 if (color_rule->rule)
16351 mlx5_flow_os_destroy_flow(color_rule->rule);
16352 if (color_rule->matcher) {
16353 struct mlx5_flow_tbl_data_entry *tbl =
16354 container_of(color_rule->matcher->tbl,
16355 typeof(*tbl), tbl);
16356 mlx5_list_unregister(tbl->matchers,
16357 &color_rule->matcher->entry);
16359 TAILQ_REMOVE(&sub_policy->color_rules[i],
16360 color_rule, next_port);
16361 mlx5_free(color_rule);
16368 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16369 struct mlx5_flow_meter_policy *mtr_policy,
16370 struct mlx5_flow_meter_sub_policy *sub_policy,
16373 struct mlx5_priv *priv = dev->data->dev_private;
16374 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16375 struct mlx5_flow_dv_tag_resource *tag;
16376 struct mlx5_flow_dv_port_id_action_resource *port_action;
16377 struct mlx5_hrxq *hrxq;
16378 struct mlx5_flow_meter_info *next_fm = NULL;
16379 struct mlx5_flow_meter_policy *next_policy;
16380 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16381 struct mlx5_flow_tbl_data_entry *tbl_data;
16382 struct rte_flow_error error;
16383 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16384 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16385 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16386 bool match_src_port = false;
16389 /* If RSS or Queue, no previous actions / rules is created. */
16390 for (i = 0; i < RTE_COLORS; i++) {
16391 acts[i].actions_n = 0;
16392 if (i == RTE_COLOR_RED) {
16393 /* Only support drop on red. */
16394 acts[i].dv_actions[0] =
16395 mtr_policy->dr_drop_action[domain];
16396 acts[i].actions_n = 1;
16399 if (i == RTE_COLOR_GREEN &&
16400 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16401 struct rte_flow_attr attr = {
16402 .transfer = transfer
16405 next_fm = mlx5_flow_meter_find(priv,
16406 mtr_policy->act_cnt[i].next_mtr_id,
16410 "Failed to get next hierarchy meter.");
16413 if (mlx5_flow_meter_attach(priv, next_fm,
16415 DRV_LOG(ERR, "%s", error.message);
16419 /* Meter action must be the first for TX. */
16421 acts[i].dv_actions[acts[i].actions_n] =
16422 next_fm->meter_action;
16423 acts[i].actions_n++;
16426 if (mtr_policy->act_cnt[i].rix_mark) {
16427 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16428 mtr_policy->act_cnt[i].rix_mark);
16430 DRV_LOG(ERR, "Failed to find "
16431 "mark action for policy.");
16434 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16435 acts[i].actions_n++;
16437 if (mtr_policy->act_cnt[i].modify_hdr) {
16438 acts[i].dv_actions[acts[i].actions_n] =
16439 mtr_policy->act_cnt[i].modify_hdr->action;
16440 acts[i].actions_n++;
16442 if (mtr_policy->act_cnt[i].fate_action) {
16443 switch (mtr_policy->act_cnt[i].fate_action) {
16444 case MLX5_FLOW_FATE_PORT_ID:
16445 port_action = mlx5_ipool_get
16446 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16447 mtr_policy->act_cnt[i].rix_port_id_action);
16448 if (!port_action) {
16449 DRV_LOG(ERR, "Failed to find "
16450 "port action for policy.");
16453 acts[i].dv_actions[acts[i].actions_n] =
16454 port_action->action;
16455 acts[i].actions_n++;
16456 mtr_policy->dev = dev;
16457 match_src_port = true;
16459 case MLX5_FLOW_FATE_DROP:
16460 case MLX5_FLOW_FATE_JUMP:
16461 acts[i].dv_actions[acts[i].actions_n] =
16462 mtr_policy->act_cnt[i].dr_jump_action[domain];
16463 acts[i].actions_n++;
16465 case MLX5_FLOW_FATE_SHARED_RSS:
16466 case MLX5_FLOW_FATE_QUEUE:
16467 hrxq = mlx5_ipool_get
16468 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16469 sub_policy->rix_hrxq[i]);
16471 DRV_LOG(ERR, "Failed to find "
16472 "queue action for policy.");
16475 acts[i].dv_actions[acts[i].actions_n] =
16477 acts[i].actions_n++;
16479 case MLX5_FLOW_FATE_MTR:
16482 "No next hierarchy meter.");
16486 acts[i].dv_actions[acts[i].actions_n] =
16487 next_fm->meter_action;
16488 acts[i].actions_n++;
16490 if (mtr_policy->act_cnt[i].next_sub_policy) {
16492 mtr_policy->act_cnt[i].next_sub_policy;
16495 mlx5_flow_meter_policy_find(dev,
16496 next_fm->policy_id, NULL);
16497 MLX5_ASSERT(next_policy);
16499 next_policy->sub_policys[domain][0];
16502 container_of(next_sub_policy->tbl_rsc,
16503 struct mlx5_flow_tbl_data_entry, tbl);
16504 acts[i].dv_actions[acts[i].actions_n++] =
16505 tbl_data->jump.action;
16506 if (mtr_policy->act_cnt[i].modify_hdr)
16507 match_src_port = !!transfer;
16510 /*Queue action do nothing*/
16515 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16516 egress, transfer, match_src_port, acts)) {
16518 "Failed to create policy rules per domain.");
16524 mlx5_flow_meter_detach(priv, next_fm);
16529 * Create the policy rules.
16532 * Pointer to Ethernet device.
16533 * @param[in,out] mtr_policy
16534 * Pointer to meter policy table.
16537 * 0 on success, -1 otherwise.
16540 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16541 struct mlx5_flow_meter_policy *mtr_policy)
16544 uint16_t sub_policy_num;
16546 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16547 sub_policy_num = (mtr_policy->sub_policy_num >>
16548 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16549 MLX5_MTR_SUB_POLICY_NUM_MASK;
16550 if (!sub_policy_num)
16552 /* Prepare actions list and create policy rules. */
16553 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16554 mtr_policy->sub_policys[i][0], i)) {
16555 DRV_LOG(ERR, "Failed to create policy action "
16556 "list per domain.");
16564 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16566 struct mlx5_priv *priv = dev->data->dev_private;
16567 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16568 struct mlx5_flow_meter_def_policy *def_policy;
16569 struct mlx5_flow_tbl_resource *jump_tbl;
16570 struct mlx5_flow_tbl_data_entry *tbl_data;
16571 uint8_t egress, transfer;
16572 struct rte_flow_error error;
16573 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16576 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16577 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16578 def_policy = mtrmng->def_policy[domain];
16580 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16581 sizeof(struct mlx5_flow_meter_def_policy),
16582 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16584 DRV_LOG(ERR, "Failed to alloc default policy table.");
16585 goto def_policy_error;
16587 mtrmng->def_policy[domain] = def_policy;
16588 /* Create the meter suffix table with SUFFIX level. */
16589 jump_tbl = flow_dv_tbl_resource_get(dev,
16590 MLX5_FLOW_TABLE_LEVEL_METER,
16591 egress, transfer, false, NULL, 0,
16592 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16595 "Failed to create meter suffix table.");
16596 goto def_policy_error;
16598 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16599 tbl_data = container_of(jump_tbl,
16600 struct mlx5_flow_tbl_data_entry, tbl);
16601 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16602 tbl_data->jump.action;
16603 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16604 acts[RTE_COLOR_GREEN].actions_n = 1;
16606 * YELLOW has the same default policy as GREEN does.
16607 * G & Y share the same table and action. The 2nd time of table
16608 * resource getting is just to update the reference count for
16609 * the releasing stage.
16611 jump_tbl = flow_dv_tbl_resource_get(dev,
16612 MLX5_FLOW_TABLE_LEVEL_METER,
16613 egress, transfer, false, NULL, 0,
16614 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16617 "Failed to get meter suffix table.");
16618 goto def_policy_error;
16620 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16621 tbl_data = container_of(jump_tbl,
16622 struct mlx5_flow_tbl_data_entry, tbl);
16623 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16624 tbl_data->jump.action;
16625 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16626 acts[RTE_COLOR_YELLOW].actions_n = 1;
16627 /* Create jump action to the drop table. */
16628 if (!mtrmng->drop_tbl[domain]) {
16629 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16630 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16631 egress, transfer, false, NULL, 0,
16632 0, MLX5_MTR_TABLE_ID_DROP, &error);
16633 if (!mtrmng->drop_tbl[domain]) {
16634 DRV_LOG(ERR, "Failed to create meter "
16635 "drop table for default policy.");
16636 goto def_policy_error;
16639 /* all RED: unique Drop table for jump action. */
16640 tbl_data = container_of(mtrmng->drop_tbl[domain],
16641 struct mlx5_flow_tbl_data_entry, tbl);
16642 def_policy->dr_jump_action[RTE_COLOR_RED] =
16643 tbl_data->jump.action;
16644 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16645 acts[RTE_COLOR_RED].actions_n = 1;
16646 /* Create default policy rules. */
16647 ret = __flow_dv_create_domain_policy_rules(dev,
16648 &def_policy->sub_policy,
16649 egress, transfer, false, acts);
16651 DRV_LOG(ERR, "Failed to create default policy rules.");
16652 goto def_policy_error;
16657 __flow_dv_destroy_domain_def_policy(dev,
16658 (enum mlx5_meter_domain)domain);
16663 * Create the default policy table set.
16666 * Pointer to Ethernet device.
16668 * 0 on success, -1 otherwise.
16671 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16673 struct mlx5_priv *priv = dev->data->dev_private;
16676 /* Non-termination policy table. */
16677 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16678 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16680 if (__flow_dv_create_domain_def_policy(dev, i)) {
16681 DRV_LOG(ERR, "Failed to create default policy");
16682 /* Rollback the created default policies for others. */
16683 flow_dv_destroy_def_policy(dev);
16691 * Create the needed meter tables.
16692 * Lock free, (mutex should be acquired by caller).
16695 * Pointer to Ethernet device.
16697 * Meter information table.
16698 * @param[in] mtr_idx
16700 * @param[in] domain_bitmap
16703 * 0 on success, -1 otherwise.
16706 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16707 struct mlx5_flow_meter_info *fm,
16709 uint8_t domain_bitmap)
16711 struct mlx5_priv *priv = dev->data->dev_private;
16712 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16713 struct rte_flow_error error;
16714 struct mlx5_flow_tbl_data_entry *tbl_data;
16715 uint8_t egress, transfer;
16716 void *actions[METER_ACTIONS];
16717 int domain, ret, i;
16718 struct mlx5_flow_counter *cnt;
16719 struct mlx5_flow_dv_match_params value = {
16720 .size = sizeof(value.buf),
16722 struct mlx5_flow_dv_match_params matcher_para = {
16723 .size = sizeof(matcher_para.buf),
16725 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16727 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16728 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16729 struct mlx5_list_entry *entry;
16730 struct mlx5_flow_dv_matcher matcher = {
16732 .size = sizeof(matcher.mask.buf),
16735 struct mlx5_flow_dv_matcher *drop_matcher;
16736 struct mlx5_flow_cb_ctx ctx = {
16742 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16743 rte_errno = ENOTSUP;
16746 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16747 if (!(domain_bitmap & (1 << domain)) ||
16748 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16750 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16751 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16752 /* Create the drop table with METER DROP level. */
16753 if (!mtrmng->drop_tbl[domain]) {
16754 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16755 MLX5_FLOW_TABLE_LEVEL_METER,
16756 egress, transfer, false, NULL, 0,
16757 0, MLX5_MTR_TABLE_ID_DROP, &error);
16758 if (!mtrmng->drop_tbl[domain]) {
16759 DRV_LOG(ERR, "Failed to create meter drop table.");
16763 /* Create default matcher in drop table. */
16764 matcher.tbl = mtrmng->drop_tbl[domain],
16765 tbl_data = container_of(mtrmng->drop_tbl[domain],
16766 struct mlx5_flow_tbl_data_entry, tbl);
16767 if (!mtrmng->def_matcher[domain]) {
16768 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16769 (enum modify_reg)mtr_id_reg_c,
16771 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16772 matcher.crc = rte_raw_cksum
16773 ((const void *)matcher.mask.buf,
16774 matcher.mask.size);
16775 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16777 DRV_LOG(ERR, "Failed to register meter "
16778 "drop default matcher.");
16781 mtrmng->def_matcher[domain] = container_of(entry,
16782 struct mlx5_flow_dv_matcher, entry);
16784 /* Create default rule in drop table. */
16785 if (!mtrmng->def_rule[domain]) {
16787 actions[i++] = priv->sh->dr_drop_action;
16788 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16789 (enum modify_reg)mtr_id_reg_c, 0, 0);
16790 misc_mask = flow_dv_matcher_enable(value.buf);
16791 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16792 ret = mlx5_flow_os_create_flow
16793 (mtrmng->def_matcher[domain]->matcher_object,
16794 (void *)&value, i, actions,
16795 &mtrmng->def_rule[domain]);
16797 DRV_LOG(ERR, "Failed to create meter "
16798 "default drop rule for drop table.");
16804 MLX5_ASSERT(mtrmng->max_mtr_bits);
16805 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16806 /* Create matchers for Drop. */
16807 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16808 (enum modify_reg)mtr_id_reg_c, 0,
16809 (mtr_id_mask << mtr_id_offset));
16810 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16811 matcher.crc = rte_raw_cksum
16812 ((const void *)matcher.mask.buf,
16813 matcher.mask.size);
16814 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16817 "Failed to register meter drop matcher.");
16820 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16821 container_of(entry, struct mlx5_flow_dv_matcher,
16825 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16826 /* Create drop rule, matching meter_id only. */
16827 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16828 (enum modify_reg)mtr_id_reg_c,
16829 (mtr_idx << mtr_id_offset), UINT32_MAX);
16831 cnt = flow_dv_counter_get_by_idx(dev,
16832 fm->drop_cnt, NULL);
16833 actions[i++] = cnt->action;
16834 actions[i++] = priv->sh->dr_drop_action;
16835 misc_mask = flow_dv_matcher_enable(value.buf);
16836 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16837 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16838 (void *)&value, i, actions,
16839 &fm->drop_rule[domain]);
16841 DRV_LOG(ERR, "Failed to create meter "
16842 "drop rule for drop table.");
16848 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16849 if (fm->drop_rule[i]) {
16850 claim_zero(mlx5_flow_os_destroy_flow
16851 (fm->drop_rule[i]));
16852 fm->drop_rule[i] = NULL;
16858 static struct mlx5_flow_meter_sub_policy *
16859 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16860 struct mlx5_flow_meter_policy *mtr_policy,
16861 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16862 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16865 struct mlx5_priv *priv = dev->data->dev_private;
16866 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16867 uint32_t sub_policy_idx = 0;
16868 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16870 struct mlx5_hrxq *hrxq;
16871 struct mlx5_flow_handle dh;
16872 struct mlx5_meter_policy_action_container *act_cnt;
16873 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16874 uint16_t sub_policy_num;
16875 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
16878 rte_spinlock_lock(&mtr_policy->sl);
16879 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16882 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16883 if (!hrxq_idx[i]) {
16884 rte_spinlock_unlock(&mtr_policy->sl);
16888 sub_policy_num = (mtr_policy->sub_policy_num >>
16889 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16890 MLX5_MTR_SUB_POLICY_NUM_MASK;
16891 for (j = 0; j < sub_policy_num; j++) {
16892 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16895 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16898 if (i >= MLX5_MTR_RTE_COLORS) {
16900 * Found the sub policy table with
16901 * the same queue per color.
16903 rte_spinlock_unlock(&mtr_policy->sl);
16904 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16905 mlx5_hrxq_release(dev, hrxq_idx[i]);
16907 return mtr_policy->sub_policys[domain][j];
16910 /* Create sub policy. */
16911 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16912 /* Reuse the first pre-allocated sub_policy. */
16913 sub_policy = mtr_policy->sub_policys[domain][0];
16914 sub_policy_idx = sub_policy->idx;
16916 sub_policy = mlx5_ipool_zmalloc
16917 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16920 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16921 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16922 mlx5_hrxq_release(dev, hrxq_idx[i]);
16923 goto rss_sub_policy_error;
16925 sub_policy->idx = sub_policy_idx;
16926 sub_policy->main_policy = mtr_policy;
16928 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16931 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16932 if (mtr_policy->is_hierarchy) {
16933 act_cnt = &mtr_policy->act_cnt[i];
16934 act_cnt->next_sub_policy = next_sub_policy;
16935 mlx5_hrxq_release(dev, hrxq_idx[i]);
16938 * Overwrite the last action from
16939 * RSS action to Queue action.
16941 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16944 DRV_LOG(ERR, "Failed to get policy hrxq");
16945 goto rss_sub_policy_error;
16947 act_cnt = &mtr_policy->act_cnt[i];
16948 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16949 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16950 if (act_cnt->rix_mark)
16952 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16953 dh.rix_hrxq = hrxq_idx[i];
16954 flow_drv_rxq_flags_set(dev, &dh);
16958 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16959 sub_policy, domain)) {
16960 DRV_LOG(ERR, "Failed to create policy "
16961 "rules for ingress domain.");
16962 goto rss_sub_policy_error;
16964 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16965 i = (mtr_policy->sub_policy_num >>
16966 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16967 MLX5_MTR_SUB_POLICY_NUM_MASK;
16968 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16969 DRV_LOG(ERR, "No free sub-policy slot.");
16970 goto rss_sub_policy_error;
16972 mtr_policy->sub_policys[domain][i] = sub_policy;
16974 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16975 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16976 mtr_policy->sub_policy_num |=
16977 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16978 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16980 rte_spinlock_unlock(&mtr_policy->sl);
16983 rss_sub_policy_error:
16985 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16986 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16987 i = (mtr_policy->sub_policy_num >>
16988 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16989 MLX5_MTR_SUB_POLICY_NUM_MASK;
16990 mtr_policy->sub_policys[domain][i] = NULL;
16991 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16995 rte_spinlock_unlock(&mtr_policy->sl);
17000 * Find the policy table for prefix table with RSS.
17003 * Pointer to Ethernet device.
17004 * @param[in] mtr_policy
17005 * Pointer to meter policy table.
17006 * @param[in] rss_desc
17007 * Pointer to rss_desc
17009 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17011 static struct mlx5_flow_meter_sub_policy *
17012 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17013 struct mlx5_flow_meter_policy *mtr_policy,
17014 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17016 struct mlx5_priv *priv = dev->data->dev_private;
17017 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17018 struct mlx5_flow_meter_info *next_fm;
17019 struct mlx5_flow_meter_policy *next_policy;
17020 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17021 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17022 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17023 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17024 bool reuse_sub_policy;
17029 /* Iterate hierarchy to get all policies in this hierarchy. */
17030 policies[i++] = mtr_policy;
17031 if (!mtr_policy->is_hierarchy)
17033 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17034 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17037 next_fm = mlx5_flow_meter_find(priv,
17038 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17040 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17044 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17046 MLX5_ASSERT(next_policy);
17047 mtr_policy = next_policy;
17051 * From last policy to the first one in hierarchy,
17052 * create / get the sub policy for each of them.
17054 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17058 &reuse_sub_policy);
17060 DRV_LOG(ERR, "Failed to get the sub policy.");
17063 if (!reuse_sub_policy)
17064 sub_policies[j++] = sub_policy;
17065 next_sub_policy = sub_policy;
17070 uint16_t sub_policy_num;
17072 sub_policy = sub_policies[--j];
17073 mtr_policy = sub_policy->main_policy;
17074 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17075 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17076 sub_policy_num = (mtr_policy->sub_policy_num >>
17077 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17078 MLX5_MTR_SUB_POLICY_NUM_MASK;
17079 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17082 mtr_policy->sub_policy_num &=
17083 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17084 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17085 mtr_policy->sub_policy_num |=
17086 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17087 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17088 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17096 * Create the sub policy tag rule for all meters in hierarchy.
17099 * Pointer to Ethernet device.
17101 * Meter information table.
17102 * @param[in] src_port
17103 * The src port this extra rule should use.
17105 * The src port match item.
17106 * @param[out] error
17107 * Perform verbose error reporting if not NULL.
17109 * 0 on success, a negative errno value otherwise and rte_errno is set.
17112 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17113 struct mlx5_flow_meter_info *fm,
17115 const struct rte_flow_item *item,
17116 struct rte_flow_error *error)
17118 struct mlx5_priv *priv = dev->data->dev_private;
17119 struct mlx5_flow_meter_policy *mtr_policy;
17120 struct mlx5_flow_meter_sub_policy *sub_policy;
17121 struct mlx5_flow_meter_info *next_fm = NULL;
17122 struct mlx5_flow_meter_policy *next_policy;
17123 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17124 struct mlx5_flow_tbl_data_entry *tbl_data;
17125 struct mlx5_sub_policy_color_rule *color_rule;
17126 struct mlx5_meter_policy_acts acts;
17127 uint32_t color_reg_c_idx;
17128 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17129 struct rte_flow_attr attr = {
17130 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17137 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17140 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17141 MLX5_ASSERT(mtr_policy);
17142 if (!mtr_policy->is_hierarchy)
17144 next_fm = mlx5_flow_meter_find(priv,
17145 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17147 return rte_flow_error_set(error, EINVAL,
17148 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17149 "Failed to find next meter in hierarchy.");
17151 if (!next_fm->drop_cnt)
17153 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17154 sub_policy = mtr_policy->sub_policys[domain][0];
17155 for (i = 0; i < RTE_COLORS; i++) {
17156 bool rule_exist = false;
17157 struct mlx5_meter_policy_action_container *act_cnt;
17159 if (i >= RTE_COLOR_YELLOW)
17161 TAILQ_FOREACH(color_rule,
17162 &sub_policy->color_rules[i], next_port)
17163 if (color_rule->src_port == src_port) {
17169 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17170 sizeof(struct mlx5_sub_policy_color_rule),
17173 return rte_flow_error_set(error, ENOMEM,
17174 RTE_FLOW_ERROR_TYPE_ACTION,
17175 NULL, "No memory to create tag color rule.");
17176 color_rule->src_port = src_port;
17178 next_policy = mlx5_flow_meter_policy_find(dev,
17179 next_fm->policy_id, NULL);
17180 MLX5_ASSERT(next_policy);
17181 next_sub_policy = next_policy->sub_policys[domain][0];
17182 tbl_data = container_of(next_sub_policy->tbl_rsc,
17183 struct mlx5_flow_tbl_data_entry, tbl);
17184 act_cnt = &mtr_policy->act_cnt[i];
17186 acts.dv_actions[0] = next_fm->meter_action;
17187 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17189 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17190 acts.dv_actions[1] = next_fm->meter_action;
17192 acts.dv_actions[2] = tbl_data->jump.action;
17193 acts.actions_n = 3;
17194 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17198 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17199 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17201 &color_rule->matcher, error)) {
17202 rte_flow_error_set(error, errno,
17203 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17204 "Failed to create hierarchy meter matcher.");
17207 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17209 color_rule->matcher->matcher_object,
17210 acts.actions_n, acts.dv_actions,
17212 &color_rule->rule, &attr)) {
17213 rte_flow_error_set(error, errno,
17214 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17215 "Failed to create hierarchy meter rule.");
17218 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17219 color_rule, next_port);
17223 * Recursive call to iterate all meters in hierarchy and
17224 * create needed rules.
17226 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17227 src_port, item, error);
17230 if (color_rule->rule)
17231 mlx5_flow_os_destroy_flow(color_rule->rule);
17232 if (color_rule->matcher) {
17233 struct mlx5_flow_tbl_data_entry *tbl =
17234 container_of(color_rule->matcher->tbl,
17235 typeof(*tbl), tbl);
17236 mlx5_list_unregister(tbl->matchers,
17237 &color_rule->matcher->entry);
17239 mlx5_free(color_rule);
17242 mlx5_flow_meter_detach(priv, next_fm);
17247 * Destroy the sub policy table with RX queue.
17250 * Pointer to Ethernet device.
17251 * @param[in] mtr_policy
17252 * Pointer to meter policy table.
17255 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17256 struct mlx5_flow_meter_policy *mtr_policy)
17258 struct mlx5_priv *priv = dev->data->dev_private;
17259 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17260 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17262 uint16_t sub_policy_num, new_policy_num;
17264 rte_spinlock_lock(&mtr_policy->sl);
17265 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17266 switch (mtr_policy->act_cnt[i].fate_action) {
17267 case MLX5_FLOW_FATE_SHARED_RSS:
17268 sub_policy_num = (mtr_policy->sub_policy_num >>
17269 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17270 MLX5_MTR_SUB_POLICY_NUM_MASK;
17271 new_policy_num = sub_policy_num;
17272 for (j = 0; j < sub_policy_num; j++) {
17274 mtr_policy->sub_policys[domain][j];
17276 __flow_dv_destroy_sub_policy_rules(dev,
17279 mtr_policy->sub_policys[domain][0]) {
17280 mtr_policy->sub_policys[domain][j] =
17283 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17289 if (new_policy_num != sub_policy_num) {
17290 mtr_policy->sub_policy_num &=
17291 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17292 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17293 mtr_policy->sub_policy_num |=
17295 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17296 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17299 case MLX5_FLOW_FATE_QUEUE:
17300 sub_policy = mtr_policy->sub_policys[domain][0];
17301 __flow_dv_destroy_sub_policy_rules(dev,
17305 /*Other actions without queue and do nothing*/
17309 rte_spinlock_unlock(&mtr_policy->sl);
17312 * Check whether the DR drop action is supported on the root table or not.
17314 * Create a simple flow with DR drop action on root table to validate
17315 * if DR drop action on root table is supported or not.
17318 * Pointer to rte_eth_dev structure.
17321 * 0 on success, a negative errno value otherwise and rte_errno is set.
17324 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17326 struct mlx5_priv *priv = dev->data->dev_private;
17327 struct mlx5_dev_ctx_shared *sh = priv->sh;
17328 struct mlx5_flow_dv_match_params mask = {
17329 .size = sizeof(mask.buf),
17331 struct mlx5_flow_dv_match_params value = {
17332 .size = sizeof(value.buf),
17334 struct mlx5dv_flow_matcher_attr dv_attr = {
17335 .type = IBV_FLOW_ATTR_NORMAL,
17337 .match_criteria_enable = 0,
17338 .match_mask = (void *)&mask,
17340 struct mlx5_flow_tbl_resource *tbl = NULL;
17341 void *matcher = NULL;
17345 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17349 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17350 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17351 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17352 tbl->obj, &matcher);
17355 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17356 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17357 &sh->dr_drop_action, &flow);
17360 * If DR drop action is not supported on root table, flow create will
17361 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17365 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17366 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17368 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17371 claim_zero(mlx5_flow_os_destroy_flow(flow));
17374 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17376 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17381 * Validate the batch counter support in root table.
17383 * Create a simple flow with invalid counter and drop action on root table to
17384 * validate if batch counter with offset on root table is supported or not.
17387 * Pointer to rte_eth_dev structure.
17390 * 0 on success, a negative errno value otherwise and rte_errno is set.
17393 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17395 struct mlx5_priv *priv = dev->data->dev_private;
17396 struct mlx5_dev_ctx_shared *sh = priv->sh;
17397 struct mlx5_flow_dv_match_params mask = {
17398 .size = sizeof(mask.buf),
17400 struct mlx5_flow_dv_match_params value = {
17401 .size = sizeof(value.buf),
17403 struct mlx5dv_flow_matcher_attr dv_attr = {
17404 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17406 .match_criteria_enable = 0,
17407 .match_mask = (void *)&mask,
17409 void *actions[2] = { 0 };
17410 struct mlx5_flow_tbl_resource *tbl = NULL;
17411 struct mlx5_devx_obj *dcs = NULL;
17412 void *matcher = NULL;
17416 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17420 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17423 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17427 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17428 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17429 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17430 tbl->obj, &matcher);
17433 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17434 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17438 * If batch counter with offset is not supported, the driver will not
17439 * validate the invalid offset value, flow create should success.
17440 * In this case, it means batch counter is not supported in root table.
17442 * Otherwise, if flow create is failed, counter offset is supported.
17445 DRV_LOG(INFO, "Batch counter is not supported in root "
17446 "table. Switch to fallback mode.");
17447 rte_errno = ENOTSUP;
17449 claim_zero(mlx5_flow_os_destroy_flow(flow));
17451 /* Check matcher to make sure validate fail at flow create. */
17452 if (!matcher || (matcher && errno != EINVAL))
17453 DRV_LOG(ERR, "Unexpected error in counter offset "
17454 "support detection");
17458 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17460 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17462 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17464 claim_zero(mlx5_devx_cmd_destroy(dcs));
17469 * Query a devx counter.
17472 * Pointer to the Ethernet device structure.
17474 * Index to the flow counter.
17476 * Set to clear the counter statistics.
17478 * The statistics value of packets.
17479 * @param[out] bytes
17480 * The statistics value of bytes.
17483 * 0 on success, otherwise return -1.
17486 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17487 uint64_t *pkts, uint64_t *bytes)
17489 struct mlx5_priv *priv = dev->data->dev_private;
17490 struct mlx5_flow_counter *cnt;
17491 uint64_t inn_pkts, inn_bytes;
17494 if (!priv->sh->devx)
17497 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17500 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17501 *pkts = inn_pkts - cnt->hits;
17502 *bytes = inn_bytes - cnt->bytes;
17504 cnt->hits = inn_pkts;
17505 cnt->bytes = inn_bytes;
17511 * Get aged-out flows.
17514 * Pointer to the Ethernet device structure.
17515 * @param[in] context
17516 * The address of an array of pointers to the aged-out flows contexts.
17517 * @param[in] nb_contexts
17518 * The length of context array pointers.
17519 * @param[out] error
17520 * Perform verbose error reporting if not NULL. Initialized in case of
17524 * how many contexts get in success, otherwise negative errno value.
17525 * if nb_contexts is 0, return the amount of all aged contexts.
17526 * if nb_contexts is not 0 , return the amount of aged flows reported
17527 * in the context array.
17528 * @note: only stub for now
17531 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17533 uint32_t nb_contexts,
17534 struct rte_flow_error *error)
17536 struct mlx5_priv *priv = dev->data->dev_private;
17537 struct mlx5_age_info *age_info;
17538 struct mlx5_age_param *age_param;
17539 struct mlx5_flow_counter *counter;
17540 struct mlx5_aso_age_action *act;
17543 if (nb_contexts && !context)
17544 return rte_flow_error_set(error, EINVAL,
17545 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17546 NULL, "empty context");
17547 age_info = GET_PORT_AGE_INFO(priv);
17548 rte_spinlock_lock(&age_info->aged_sl);
17549 LIST_FOREACH(act, &age_info->aged_aso, next) {
17552 context[nb_flows - 1] =
17553 act->age_params.context;
17554 if (!(--nb_contexts))
17558 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17561 age_param = MLX5_CNT_TO_AGE(counter);
17562 context[nb_flows - 1] = age_param->context;
17563 if (!(--nb_contexts))
17567 rte_spinlock_unlock(&age_info->aged_sl);
17568 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17573 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17576 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17578 return flow_dv_counter_alloc(dev, 0);
17582 * Validate indirect action.
17583 * Dispatcher for action type specific validation.
17586 * Pointer to the Ethernet device structure.
17588 * Indirect action configuration.
17589 * @param[in] action
17590 * The indirect action object to validate.
17591 * @param[out] error
17592 * Perform verbose error reporting if not NULL. Initialized in case of
17596 * 0 on success, otherwise negative errno value.
17599 flow_dv_action_validate(struct rte_eth_dev *dev,
17600 const struct rte_flow_indir_action_conf *conf,
17601 const struct rte_flow_action *action,
17602 struct rte_flow_error *err)
17604 struct mlx5_priv *priv = dev->data->dev_private;
17606 RTE_SET_USED(conf);
17607 switch (action->type) {
17608 case RTE_FLOW_ACTION_TYPE_RSS:
17610 * priv->obj_ops is set according to driver capabilities.
17611 * When DevX capabilities are
17612 * sufficient, it is set to devx_obj_ops.
17613 * Otherwise, it is set to ibv_obj_ops.
17614 * ibv_obj_ops doesn't support ind_table_modify operation.
17615 * In this case the indirect RSS action can't be used.
17617 if (priv->obj_ops.ind_table_modify == NULL)
17618 return rte_flow_error_set
17620 RTE_FLOW_ERROR_TYPE_ACTION,
17622 "Indirect RSS action not supported");
17623 return mlx5_validate_action_rss(dev, action, err);
17624 case RTE_FLOW_ACTION_TYPE_AGE:
17625 if (!priv->sh->aso_age_mng)
17626 return rte_flow_error_set(err, ENOTSUP,
17627 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17629 "Indirect age action not supported");
17630 return flow_dv_validate_action_age(0, action, dev, err);
17631 case RTE_FLOW_ACTION_TYPE_COUNT:
17632 return flow_dv_validate_action_count(dev, true, 0, err);
17633 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17634 if (!priv->sh->ct_aso_en)
17635 return rte_flow_error_set(err, ENOTSUP,
17636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17637 "ASO CT is not supported");
17638 return mlx5_validate_action_ct(dev, action->conf, err);
17640 return rte_flow_error_set(err, ENOTSUP,
17641 RTE_FLOW_ERROR_TYPE_ACTION,
17643 "action type not supported");
17648 * Check if the RSS configurations for colors of a meter policy match
17649 * each other, except the queues.
17652 * Pointer to the first RSS flow action.
17654 * Pointer to the second RSS flow action.
17657 * 0 on match, 1 on conflict.
17660 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17661 const struct rte_flow_action_rss *r2)
17663 if (r1 == NULL || r2 == NULL)
17665 if (!(r1->level <= 1 && r2->level <= 1) &&
17666 !(r1->level > 1 && r2->level > 1))
17668 if (r1->types != r2->types &&
17669 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17670 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17672 if (r1->key || r2->key) {
17673 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17674 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17676 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17683 * Validate the meter hierarchy chain for meter policy.
17686 * Pointer to the Ethernet device structure.
17687 * @param[in] meter_id
17689 * @param[in] action_flags
17690 * Holds the actions detected until now.
17691 * @param[out] is_rss
17693 * @param[out] hierarchy_domain
17694 * The domain bitmap for hierarchy policy.
17695 * @param[out] error
17696 * Perform verbose error reporting if not NULL. Initialized in case of
17700 * 0 on success, otherwise negative errno value with error set.
17703 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17705 uint64_t action_flags,
17707 uint8_t *hierarchy_domain,
17708 struct rte_mtr_error *error)
17710 struct mlx5_priv *priv = dev->data->dev_private;
17711 struct mlx5_flow_meter_info *fm;
17712 struct mlx5_flow_meter_policy *policy;
17715 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17716 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17717 return -rte_mtr_error_set(error, EINVAL,
17718 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17720 "Multiple fate actions not supported.");
17721 *hierarchy_domain = 0;
17723 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17725 return -rte_mtr_error_set(error, EINVAL,
17726 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17727 "Meter not found in meter hierarchy.");
17728 if (fm->def_policy)
17729 return -rte_mtr_error_set(error, EINVAL,
17730 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17731 "Non termination meter not supported in hierarchy.");
17732 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17733 MLX5_ASSERT(policy);
17735 * Only inherit the supported domains of the first meter in
17737 * One meter supports at least one domain.
17739 if (!*hierarchy_domain) {
17740 if (policy->transfer)
17741 *hierarchy_domain |=
17742 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17743 if (policy->ingress)
17744 *hierarchy_domain |=
17745 MLX5_MTR_DOMAIN_INGRESS_BIT;
17746 if (policy->egress)
17747 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17749 if (!policy->is_hierarchy) {
17750 *is_rss = policy->is_rss;
17753 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17754 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17755 return -rte_mtr_error_set(error, EINVAL,
17756 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17757 "Exceed max hierarchy meter number.");
17763 * Validate meter policy actions.
17764 * Dispatcher for action type specific validation.
17767 * Pointer to the Ethernet device structure.
17768 * @param[in] action
17769 * The meter policy action object to validate.
17771 * Attributes of flow to determine steering domain.
17772 * @param[out] error
17773 * Perform verbose error reporting if not NULL. Initialized in case of
17777 * 0 on success, otherwise negative errno value.
17780 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17781 const struct rte_flow_action *actions[RTE_COLORS],
17782 struct rte_flow_attr *attr,
17784 uint8_t *domain_bitmap,
17785 uint8_t *policy_mode,
17786 struct rte_mtr_error *error)
17788 struct mlx5_priv *priv = dev->data->dev_private;
17789 struct mlx5_dev_config *dev_conf = &priv->config;
17790 const struct rte_flow_action *act;
17791 uint64_t action_flags[RTE_COLORS] = {0};
17794 struct rte_flow_error flow_err;
17795 uint8_t domain_color[RTE_COLORS] = {0};
17796 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17797 uint8_t hierarchy_domain = 0;
17798 const struct rte_flow_action_meter *mtr;
17799 bool def_green = false;
17800 bool def_yellow = false;
17801 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17803 if (!priv->config.dv_esw_en)
17804 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17805 *domain_bitmap = def_domain;
17806 /* Red color could only support DROP action. */
17807 if (!actions[RTE_COLOR_RED] ||
17808 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17809 return -rte_mtr_error_set(error, ENOTSUP,
17810 RTE_MTR_ERROR_TYPE_METER_POLICY,
17811 NULL, "Red color only supports drop action.");
17813 * Check default policy actions:
17814 * Green / Yellow: no action, Red: drop action
17815 * Either G or Y will trigger default policy actions to be created.
17817 if (!actions[RTE_COLOR_GREEN] ||
17818 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17820 if (!actions[RTE_COLOR_YELLOW] ||
17821 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17823 if (def_green && def_yellow) {
17824 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17826 } else if (!def_green && def_yellow) {
17827 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17828 } else if (def_green && !def_yellow) {
17829 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17831 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17833 /* Set to empty string in case of NULL pointer access by user. */
17834 flow_err.message = "";
17835 for (i = 0; i < RTE_COLORS; i++) {
17837 for (action_flags[i] = 0, actions_n = 0;
17838 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17840 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17841 return -rte_mtr_error_set(error, ENOTSUP,
17842 RTE_MTR_ERROR_TYPE_METER_POLICY,
17843 NULL, "too many actions");
17844 switch (act->type) {
17845 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17846 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17847 if (!priv->config.dv_esw_en)
17848 return -rte_mtr_error_set(error,
17850 RTE_MTR_ERROR_TYPE_METER_POLICY,
17851 NULL, "PORT action validate check"
17852 " fail for ESW disable");
17853 ret = flow_dv_validate_action_port_id(dev,
17855 act, attr, &flow_err);
17857 return -rte_mtr_error_set(error,
17859 RTE_MTR_ERROR_TYPE_METER_POLICY,
17860 NULL, flow_err.message ?
17862 "PORT action validate check fail");
17864 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17866 case RTE_FLOW_ACTION_TYPE_MARK:
17867 ret = flow_dv_validate_action_mark(dev, act,
17871 return -rte_mtr_error_set(error,
17873 RTE_MTR_ERROR_TYPE_METER_POLICY,
17874 NULL, flow_err.message ?
17876 "Mark action validate check fail");
17877 if (dev_conf->dv_xmeta_en !=
17878 MLX5_XMETA_MODE_LEGACY)
17879 return -rte_mtr_error_set(error,
17881 RTE_MTR_ERROR_TYPE_METER_POLICY,
17882 NULL, "Extend MARK action is "
17883 "not supported. Please try use "
17884 "default policy for meter.");
17885 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17888 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17889 ret = flow_dv_validate_action_set_tag(dev,
17890 act, action_flags[i],
17893 return -rte_mtr_error_set(error,
17895 RTE_MTR_ERROR_TYPE_METER_POLICY,
17896 NULL, flow_err.message ?
17898 "Set tag action validate check fail");
17899 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17902 case RTE_FLOW_ACTION_TYPE_DROP:
17903 ret = mlx5_flow_validate_action_drop
17904 (action_flags[i], attr, &flow_err);
17906 return -rte_mtr_error_set(error,
17908 RTE_MTR_ERROR_TYPE_METER_POLICY,
17909 NULL, flow_err.message ?
17911 "Drop action validate check fail");
17912 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17915 case RTE_FLOW_ACTION_TYPE_QUEUE:
17917 * Check whether extensive
17918 * metadata feature is engaged.
17920 if (dev_conf->dv_flow_en &&
17921 (dev_conf->dv_xmeta_en !=
17922 MLX5_XMETA_MODE_LEGACY) &&
17923 mlx5_flow_ext_mreg_supported(dev))
17924 return -rte_mtr_error_set(error,
17926 RTE_MTR_ERROR_TYPE_METER_POLICY,
17927 NULL, "Queue action with meta "
17928 "is not supported. Please try use "
17929 "default policy for meter.");
17930 ret = mlx5_flow_validate_action_queue(act,
17931 action_flags[i], dev,
17934 return -rte_mtr_error_set(error,
17936 RTE_MTR_ERROR_TYPE_METER_POLICY,
17937 NULL, flow_err.message ?
17939 "Queue action validate check fail");
17940 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17943 case RTE_FLOW_ACTION_TYPE_RSS:
17944 if (dev_conf->dv_flow_en &&
17945 (dev_conf->dv_xmeta_en !=
17946 MLX5_XMETA_MODE_LEGACY) &&
17947 mlx5_flow_ext_mreg_supported(dev))
17948 return -rte_mtr_error_set(error,
17950 RTE_MTR_ERROR_TYPE_METER_POLICY,
17951 NULL, "RSS action with meta "
17952 "is not supported. Please try use "
17953 "default policy for meter.");
17954 ret = mlx5_validate_action_rss(dev, act,
17957 return -rte_mtr_error_set(error,
17959 RTE_MTR_ERROR_TYPE_METER_POLICY,
17960 NULL, flow_err.message ?
17962 "RSS action validate check fail");
17963 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17965 /* Either G or Y will set the RSS. */
17966 rss_color[i] = act->conf;
17968 case RTE_FLOW_ACTION_TYPE_JUMP:
17969 ret = flow_dv_validate_action_jump(dev,
17970 NULL, act, action_flags[i],
17971 attr, true, &flow_err);
17973 return -rte_mtr_error_set(error,
17975 RTE_MTR_ERROR_TYPE_METER_POLICY,
17976 NULL, flow_err.message ?
17978 "Jump action validate check fail");
17980 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17983 * Only the last meter in the hierarchy will support
17984 * the YELLOW color steering. Then in the meter policy
17985 * actions list, there should be no other meter inside.
17987 case RTE_FLOW_ACTION_TYPE_METER:
17988 if (i != RTE_COLOR_GREEN)
17989 return -rte_mtr_error_set(error,
17991 RTE_MTR_ERROR_TYPE_METER_POLICY,
17993 "Meter hierarchy only supports GREEN color.");
17994 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17995 return -rte_mtr_error_set(error,
17997 RTE_MTR_ERROR_TYPE_METER_POLICY,
17999 "No yellow policy should be provided in meter hierarchy.");
18001 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18011 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18014 return -rte_mtr_error_set(error, ENOTSUP,
18015 RTE_MTR_ERROR_TYPE_METER_POLICY,
18017 "Doesn't support optional action");
18020 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18021 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18022 } else if ((action_flags[i] &
18023 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18024 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18026 * Only support MLX5_XMETA_MODE_LEGACY
18027 * so MARK action is only in ingress domain.
18029 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18031 domain_color[i] = def_domain;
18032 if (action_flags[i] &&
18033 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18035 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18037 if (action_flags[i] &
18038 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18039 domain_color[i] &= hierarchy_domain;
18041 * Non-termination actions only support NIC Tx domain.
18042 * The adjustion should be skipped when there is no
18043 * action or only END is provided. The default domains
18044 * bit-mask is set to find the MIN intersection.
18045 * The action flags checking should also be skipped.
18047 if ((def_green && i == RTE_COLOR_GREEN) ||
18048 (def_yellow && i == RTE_COLOR_YELLOW))
18051 * Validate the drop action mutual exclusion
18052 * with other actions. Drop action is mutually-exclusive
18053 * with any other action, except for Count action.
18055 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18056 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18057 return -rte_mtr_error_set(error, ENOTSUP,
18058 RTE_MTR_ERROR_TYPE_METER_POLICY,
18059 NULL, "Drop action is mutually-exclusive "
18060 "with any other action");
18062 /* Eswitch has few restrictions on using items and actions */
18063 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18064 if (!mlx5_flow_ext_mreg_supported(dev) &&
18065 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18066 return -rte_mtr_error_set(error, ENOTSUP,
18067 RTE_MTR_ERROR_TYPE_METER_POLICY,
18068 NULL, "unsupported action MARK");
18069 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18070 return -rte_mtr_error_set(error, ENOTSUP,
18071 RTE_MTR_ERROR_TYPE_METER_POLICY,
18072 NULL, "unsupported action QUEUE");
18073 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18074 return -rte_mtr_error_set(error, ENOTSUP,
18075 RTE_MTR_ERROR_TYPE_METER_POLICY,
18076 NULL, "unsupported action RSS");
18077 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18078 return -rte_mtr_error_set(error, ENOTSUP,
18079 RTE_MTR_ERROR_TYPE_METER_POLICY,
18080 NULL, "no fate action is found");
18082 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18083 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18084 if ((domain_color[i] &
18085 MLX5_MTR_DOMAIN_EGRESS_BIT))
18087 MLX5_MTR_DOMAIN_EGRESS_BIT;
18089 return -rte_mtr_error_set(error,
18091 RTE_MTR_ERROR_TYPE_METER_POLICY,
18093 "no fate action is found");
18097 /* If both colors have RSS, the attributes should be the same. */
18098 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18099 rss_color[RTE_COLOR_YELLOW]))
18100 return -rte_mtr_error_set(error, EINVAL,
18101 RTE_MTR_ERROR_TYPE_METER_POLICY,
18102 NULL, "policy RSS attr conflict");
18103 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18105 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18106 if (!def_green && !def_yellow &&
18107 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18108 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18109 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18110 return -rte_mtr_error_set(error, EINVAL,
18111 RTE_MTR_ERROR_TYPE_METER_POLICY,
18112 NULL, "policy domains conflict");
18114 * At least one color policy is listed in the actions, the domains
18115 * to be supported should be the intersection.
18117 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18118 domain_color[RTE_COLOR_YELLOW];
18123 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18125 struct mlx5_priv *priv = dev->data->dev_private;
18128 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18129 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18134 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18135 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18139 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18140 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18148 * Discover the number of available flow priorities
18149 * by trying to create a flow with the highest priority value
18150 * for each possible number.
18155 * List of possible number of available priorities.
18156 * @param[in] vprio_n
18157 * Size of @p vprio array.
18159 * On success, number of available flow priorities.
18160 * On failure, a negative errno-style code and rte_errno is set.
18163 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18164 const uint16_t *vprio, int vprio_n)
18166 struct mlx5_priv *priv = dev->data->dev_private;
18167 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18168 struct rte_flow_item_eth eth;
18169 struct rte_flow_item item = {
18170 .type = RTE_FLOW_ITEM_TYPE_ETH,
18174 struct mlx5_flow_dv_matcher matcher = {
18176 .size = sizeof(matcher.mask.buf),
18179 union mlx5_flow_tbl_key tbl_key;
18180 struct mlx5_flow flow;
18182 struct rte_flow_error error;
18184 int i, err, ret = -ENOTSUP;
18187 * Prepare a flow with a catch-all pattern and a drop action.
18188 * Use drop queue, because shared drop action may be unavailable.
18190 action = priv->drop_queue.hrxq->action;
18191 if (action == NULL) {
18192 DRV_LOG(ERR, "Priority discovery requires a drop action");
18193 rte_errno = ENOTSUP;
18196 memset(&flow, 0, sizeof(flow));
18197 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18198 if (flow.handle == NULL) {
18199 DRV_LOG(ERR, "Cannot create flow handle");
18200 rte_errno = ENOMEM;
18203 flow.ingress = true;
18204 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18205 flow.dv.actions[0] = action;
18206 flow.dv.actions_n = 1;
18207 memset(ð, 0, sizeof(eth));
18208 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18209 &item, /* inner */ false, /* group */ 0);
18210 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18211 for (i = 0; i < vprio_n; i++) {
18212 /* Configure the next proposed maximum priority. */
18213 matcher.priority = vprio[i] - 1;
18214 memset(&tbl_key, 0, sizeof(tbl_key));
18215 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18220 /* This action is pure SW and must always succeed. */
18221 DRV_LOG(ERR, "Cannot register matcher");
18225 /* Try to apply the flow to HW. */
18226 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18227 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18228 err = mlx5_flow_os_create_flow
18229 (flow.handle->dvh.matcher->matcher_object,
18230 (void *)&flow.dv.value, flow.dv.actions_n,
18231 flow.dv.actions, &flow.handle->drv_flow);
18233 claim_zero(mlx5_flow_os_destroy_flow
18234 (flow.handle->drv_flow));
18235 flow.handle->drv_flow = NULL;
18237 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18242 mlx5_ipool_free(pool, flow.handle_idx);
18243 /* Set rte_errno if no expected priority value matched. */
18249 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18250 .validate = flow_dv_validate,
18251 .prepare = flow_dv_prepare,
18252 .translate = flow_dv_translate,
18253 .apply = flow_dv_apply,
18254 .remove = flow_dv_remove,
18255 .destroy = flow_dv_destroy,
18256 .query = flow_dv_query,
18257 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18258 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18259 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18260 .create_meter = flow_dv_mtr_alloc,
18261 .free_meter = flow_dv_aso_mtr_release_to_pool,
18262 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18263 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18264 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18265 .create_policy_rules = flow_dv_create_policy_rules,
18266 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18267 .create_def_policy = flow_dv_create_def_policy,
18268 .destroy_def_policy = flow_dv_destroy_def_policy,
18269 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18270 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18271 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18272 .counter_alloc = flow_dv_counter_allocate,
18273 .counter_free = flow_dv_counter_free,
18274 .counter_query = flow_dv_counter_query,
18275 .get_aged_flows = flow_dv_get_aged_flows,
18276 .action_validate = flow_dv_action_validate,
18277 .action_create = flow_dv_action_create,
18278 .action_destroy = flow_dv_action_destroy,
18279 .action_update = flow_dv_action_update,
18280 .action_query = flow_dv_action_query,
18281 .sync_domain = flow_dv_sync_domain,
18282 .discover_priorities = flow_dv_discover_priorities,
18283 .item_create = flow_dv_item_create,
18284 .item_release = flow_dv_item_release,
18287 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */