1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Convert modify-header action to DV specification.
246 * Pointer to item specification.
248 * Pointer to field modification information.
249 * @param[in,out] resource
250 * Pointer to the modify-header resource.
252 * Type of modification.
254 * Pointer to the error structure.
257 * 0 on success, a negative errno value otherwise and rte_errno is set.
260 flow_dv_convert_modify_action(struct rte_flow_item *item,
261 struct field_modify_info *field,
262 struct mlx5_flow_dv_modify_hdr_resource *resource,
264 struct rte_flow_error *error)
266 uint32_t i = resource->actions_num;
267 struct mlx5_modification_cmd *actions = resource->actions;
268 const uint8_t *spec = item->spec;
269 const uint8_t *mask = item->mask;
272 while (field->size) {
274 /* Generate modify command for each mask segment. */
275 memcpy(&set, &mask[field->offset], field->size);
277 if (i >= MLX5_MODIFY_NUM)
278 return rte_flow_error_set(error, EINVAL,
279 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
280 "too many items to modify");
281 actions[i].action_type = type;
282 actions[i].field = field->id;
283 actions[i].length = field->size ==
284 4 ? 0 : field->size * 8;
285 rte_memcpy(&actions[i].data[4 - field->size],
286 &spec[field->offset], field->size);
287 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
290 if (resource->actions_num != i)
291 resource->actions_num = i;
294 if (!resource->actions_num)
295 return rte_flow_error_set(error, EINVAL,
296 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
297 "invalid modification flow item");
302 * Convert modify-header set IPv4 address action to DV specification.
304 * @param[in,out] resource
305 * Pointer to the modify-header resource.
307 * Pointer to action specification.
309 * Pointer to the error structure.
312 * 0 on success, a negative errno value otherwise and rte_errno is set.
315 flow_dv_convert_action_modify_ipv4
316 (struct mlx5_flow_dv_modify_hdr_resource *resource,
317 const struct rte_flow_action *action,
318 struct rte_flow_error *error)
320 const struct rte_flow_action_set_ipv4 *conf =
321 (const struct rte_flow_action_set_ipv4 *)(action->conf);
322 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
323 struct rte_flow_item_ipv4 ipv4;
324 struct rte_flow_item_ipv4 ipv4_mask;
326 memset(&ipv4, 0, sizeof(ipv4));
327 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
328 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
329 ipv4.hdr.src_addr = conf->ipv4_addr;
330 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
332 ipv4.hdr.dst_addr = conf->ipv4_addr;
333 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
336 item.mask = &ipv4_mask;
337 return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
338 MLX5_MODIFICATION_TYPE_SET, error);
342 * Convert modify-header set IPv6 address action to DV specification.
344 * @param[in,out] resource
345 * Pointer to the modify-header resource.
347 * Pointer to action specification.
349 * Pointer to the error structure.
352 * 0 on success, a negative errno value otherwise and rte_errno is set.
355 flow_dv_convert_action_modify_ipv6
356 (struct mlx5_flow_dv_modify_hdr_resource *resource,
357 const struct rte_flow_action *action,
358 struct rte_flow_error *error)
360 const struct rte_flow_action_set_ipv6 *conf =
361 (const struct rte_flow_action_set_ipv6 *)(action->conf);
362 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
363 struct rte_flow_item_ipv6 ipv6;
364 struct rte_flow_item_ipv6 ipv6_mask;
366 memset(&ipv6, 0, sizeof(ipv6));
367 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
368 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
369 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
370 sizeof(ipv6.hdr.src_addr));
371 memcpy(&ipv6_mask.hdr.src_addr,
372 &rte_flow_item_ipv6_mask.hdr.src_addr,
373 sizeof(ipv6.hdr.src_addr));
375 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
376 sizeof(ipv6.hdr.dst_addr));
377 memcpy(&ipv6_mask.hdr.dst_addr,
378 &rte_flow_item_ipv6_mask.hdr.dst_addr,
379 sizeof(ipv6.hdr.dst_addr));
382 item.mask = &ipv6_mask;
383 return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
384 MLX5_MODIFICATION_TYPE_SET, error);
388 * Convert modify-header set MAC address action to DV specification.
390 * @param[in,out] resource
391 * Pointer to the modify-header resource.
393 * Pointer to action specification.
395 * Pointer to the error structure.
398 * 0 on success, a negative errno value otherwise and rte_errno is set.
401 flow_dv_convert_action_modify_mac
402 (struct mlx5_flow_dv_modify_hdr_resource *resource,
403 const struct rte_flow_action *action,
404 struct rte_flow_error *error)
406 const struct rte_flow_action_set_mac *conf =
407 (const struct rte_flow_action_set_mac *)(action->conf);
408 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
409 struct rte_flow_item_eth eth;
410 struct rte_flow_item_eth eth_mask;
412 memset(ð, 0, sizeof(eth));
413 memset(ð_mask, 0, sizeof(eth_mask));
414 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
415 memcpy(ð.src.addr_bytes, &conf->mac_addr,
416 sizeof(eth.src.addr_bytes));
417 memcpy(ð_mask.src.addr_bytes,
418 &rte_flow_item_eth_mask.src.addr_bytes,
419 sizeof(eth_mask.src.addr_bytes));
421 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
422 sizeof(eth.dst.addr_bytes));
423 memcpy(ð_mask.dst.addr_bytes,
424 &rte_flow_item_eth_mask.dst.addr_bytes,
425 sizeof(eth_mask.dst.addr_bytes));
428 item.mask = ð_mask;
429 return flow_dv_convert_modify_action(&item, modify_eth, resource,
430 MLX5_MODIFICATION_TYPE_SET, error);
434 * Convert modify-header set VLAN VID action to DV specification.
436 * @param[in,out] resource
437 * Pointer to the modify-header resource.
439 * Pointer to action specification.
441 * Pointer to the error structure.
444 * 0 on success, a negative errno value otherwise and rte_errno is set.
447 flow_dv_convert_action_modify_vlan_vid
448 (struct mlx5_flow_dv_modify_hdr_resource *resource,
449 const struct rte_flow_action *action,
450 struct rte_flow_error *error)
452 const struct rte_flow_action_of_set_vlan_vid *conf =
453 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
454 int i = resource->actions_num;
455 struct mlx5_modification_cmd *actions = &resource->actions[i];
456 struct field_modify_info *field = modify_vlan_out_first_vid;
458 if (i >= MLX5_MODIFY_NUM)
459 return rte_flow_error_set(error, EINVAL,
460 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
461 "too many items to modify");
462 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
463 actions[i].field = field->id;
464 actions[i].length = field->size;
465 actions[i].offset = field->offset;
466 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
467 actions[i].data1 = conf->vlan_vid;
468 actions[i].data1 = actions[i].data1 << 16;
469 resource->actions_num = ++i;
474 * Convert modify-header set TP action to DV specification.
476 * @param[in,out] resource
477 * Pointer to the modify-header resource.
479 * Pointer to action specification.
481 * Pointer to rte_flow_item objects list.
483 * Pointer to flow attributes structure.
485 * Pointer to the error structure.
488 * 0 on success, a negative errno value otherwise and rte_errno is set.
491 flow_dv_convert_action_modify_tp
492 (struct mlx5_flow_dv_modify_hdr_resource *resource,
493 const struct rte_flow_action *action,
494 const struct rte_flow_item *items,
495 union flow_dv_attr *attr,
496 struct rte_flow_error *error)
498 const struct rte_flow_action_set_tp *conf =
499 (const struct rte_flow_action_set_tp *)(action->conf);
500 struct rte_flow_item item;
501 struct rte_flow_item_udp udp;
502 struct rte_flow_item_udp udp_mask;
503 struct rte_flow_item_tcp tcp;
504 struct rte_flow_item_tcp tcp_mask;
505 struct field_modify_info *field;
508 flow_dv_attr_init(items, attr);
510 memset(&udp, 0, sizeof(udp));
511 memset(&udp_mask, 0, sizeof(udp_mask));
512 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
513 udp.hdr.src_port = conf->port;
514 udp_mask.hdr.src_port =
515 rte_flow_item_udp_mask.hdr.src_port;
517 udp.hdr.dst_port = conf->port;
518 udp_mask.hdr.dst_port =
519 rte_flow_item_udp_mask.hdr.dst_port;
521 item.type = RTE_FLOW_ITEM_TYPE_UDP;
523 item.mask = &udp_mask;
527 memset(&tcp, 0, sizeof(tcp));
528 memset(&tcp_mask, 0, sizeof(tcp_mask));
529 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
530 tcp.hdr.src_port = conf->port;
531 tcp_mask.hdr.src_port =
532 rte_flow_item_tcp_mask.hdr.src_port;
534 tcp.hdr.dst_port = conf->port;
535 tcp_mask.hdr.dst_port =
536 rte_flow_item_tcp_mask.hdr.dst_port;
538 item.type = RTE_FLOW_ITEM_TYPE_TCP;
540 item.mask = &tcp_mask;
543 return flow_dv_convert_modify_action(&item, field, resource,
544 MLX5_MODIFICATION_TYPE_SET, error);
548 * Convert modify-header set TTL action to DV specification.
550 * @param[in,out] resource
551 * Pointer to the modify-header resource.
553 * Pointer to action specification.
555 * Pointer to rte_flow_item objects list.
557 * Pointer to flow attributes structure.
559 * Pointer to the error structure.
562 * 0 on success, a negative errno value otherwise and rte_errno is set.
565 flow_dv_convert_action_modify_ttl
566 (struct mlx5_flow_dv_modify_hdr_resource *resource,
567 const struct rte_flow_action *action,
568 const struct rte_flow_item *items,
569 union flow_dv_attr *attr,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ttl *conf =
573 (const struct rte_flow_action_set_ttl *)(action->conf);
574 struct rte_flow_item item;
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
577 struct rte_flow_item_ipv6 ipv6;
578 struct rte_flow_item_ipv6 ipv6_mask;
579 struct field_modify_info *field;
582 flow_dv_attr_init(items, attr);
584 memset(&ipv4, 0, sizeof(ipv4));
585 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
586 ipv4.hdr.time_to_live = conf->ttl_value;
587 ipv4_mask.hdr.time_to_live = 0xFF;
588 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
590 item.mask = &ipv4_mask;
594 memset(&ipv6, 0, sizeof(ipv6));
595 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
596 ipv6.hdr.hop_limits = conf->ttl_value;
597 ipv6_mask.hdr.hop_limits = 0xFF;
598 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
600 item.mask = &ipv6_mask;
603 return flow_dv_convert_modify_action(&item, field, resource,
604 MLX5_MODIFICATION_TYPE_SET, error);
608 * Convert modify-header decrement TTL action to DV specification.
610 * @param[in,out] resource
611 * Pointer to the modify-header resource.
613 * Pointer to action specification.
615 * Pointer to rte_flow_item objects list.
617 * Pointer to flow attributes structure.
619 * Pointer to the error structure.
622 * 0 on success, a negative errno value otherwise and rte_errno is set.
625 flow_dv_convert_action_modify_dec_ttl
626 (struct mlx5_flow_dv_modify_hdr_resource *resource,
627 const struct rte_flow_item *items,
628 union flow_dv_attr *attr,
629 struct rte_flow_error *error)
631 struct rte_flow_item item;
632 struct rte_flow_item_ipv4 ipv4;
633 struct rte_flow_item_ipv4 ipv4_mask;
634 struct rte_flow_item_ipv6 ipv6;
635 struct rte_flow_item_ipv6 ipv6_mask;
636 struct field_modify_info *field;
639 flow_dv_attr_init(items, attr);
641 memset(&ipv4, 0, sizeof(ipv4));
642 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
643 ipv4.hdr.time_to_live = 0xFF;
644 ipv4_mask.hdr.time_to_live = 0xFF;
645 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
647 item.mask = &ipv4_mask;
651 memset(&ipv6, 0, sizeof(ipv6));
652 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
653 ipv6.hdr.hop_limits = 0xFF;
654 ipv6_mask.hdr.hop_limits = 0xFF;
655 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
657 item.mask = &ipv6_mask;
660 return flow_dv_convert_modify_action(&item, field, resource,
661 MLX5_MODIFICATION_TYPE_ADD, error);
665 * Convert modify-header increment/decrement TCP Sequence number
666 * to DV specification.
668 * @param[in,out] resource
669 * Pointer to the modify-header resource.
671 * Pointer to action specification.
673 * Pointer to the error structure.
676 * 0 on success, a negative errno value otherwise and rte_errno is set.
679 flow_dv_convert_action_modify_tcp_seq
680 (struct mlx5_flow_dv_modify_hdr_resource *resource,
681 const struct rte_flow_action *action,
682 struct rte_flow_error *error)
684 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
685 uint64_t value = rte_be_to_cpu_32(*conf);
686 struct rte_flow_item item;
687 struct rte_flow_item_tcp tcp;
688 struct rte_flow_item_tcp tcp_mask;
690 memset(&tcp, 0, sizeof(tcp));
691 memset(&tcp_mask, 0, sizeof(tcp_mask));
692 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
694 * The HW has no decrement operation, only increment operation.
695 * To simulate decrement X from Y using increment operation
696 * we need to add UINT32_MAX X times to Y.
697 * Each adding of UINT32_MAX decrements Y by 1.
700 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
701 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
702 item.type = RTE_FLOW_ITEM_TYPE_TCP;
704 item.mask = &tcp_mask;
705 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
706 MLX5_MODIFICATION_TYPE_ADD, error);
710 * Convert modify-header increment/decrement TCP Acknowledgment number
711 * to DV specification.
713 * @param[in,out] resource
714 * Pointer to the modify-header resource.
716 * Pointer to action specification.
718 * Pointer to the error structure.
721 * 0 on success, a negative errno value otherwise and rte_errno is set.
724 flow_dv_convert_action_modify_tcp_ack
725 (struct mlx5_flow_dv_modify_hdr_resource *resource,
726 const struct rte_flow_action *action,
727 struct rte_flow_error *error)
729 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
730 uint64_t value = rte_be_to_cpu_32(*conf);
731 struct rte_flow_item item;
732 struct rte_flow_item_tcp tcp;
733 struct rte_flow_item_tcp tcp_mask;
735 memset(&tcp, 0, sizeof(tcp));
736 memset(&tcp_mask, 0, sizeof(tcp_mask));
737 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
739 * The HW has no decrement operation, only increment operation.
740 * To simulate decrement X from Y using increment operation
741 * we need to add UINT32_MAX X times to Y.
742 * Each adding of UINT32_MAX decrements Y by 1.
745 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
746 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
747 item.type = RTE_FLOW_ITEM_TYPE_TCP;
749 item.mask = &tcp_mask;
750 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
751 MLX5_MODIFICATION_TYPE_ADD, error);
754 static enum mlx5_modification_field reg_to_field[] = {
755 [REG_A] = MLX5_MODI_META_DATA_REG_A,
756 [REG_B] = MLX5_MODI_META_DATA_REG_B,
757 [REG_C_0] = MLX5_MODI_META_REG_C_0,
758 [REG_C_1] = MLX5_MODI_META_REG_C_1,
759 [REG_C_2] = MLX5_MODI_META_REG_C_2,
760 [REG_C_3] = MLX5_MODI_META_REG_C_3,
761 [REG_C_4] = MLX5_MODI_META_REG_C_4,
762 [REG_C_5] = MLX5_MODI_META_REG_C_5,
763 [REG_C_6] = MLX5_MODI_META_REG_C_6,
764 [REG_C_7] = MLX5_MODI_META_REG_C_7,
768 * Convert register set to DV specification.
770 * @param[in,out] resource
771 * Pointer to the modify-header resource.
773 * Pointer to action specification.
775 * Pointer to the error structure.
778 * 0 on success, a negative errno value otherwise and rte_errno is set.
781 flow_dv_convert_action_set_reg
782 (struct mlx5_flow_dv_modify_hdr_resource *resource,
783 const struct rte_flow_action *action,
784 struct rte_flow_error *error)
786 const struct mlx5_rte_flow_action_set_tag *conf = (action->conf);
787 struct mlx5_modification_cmd *actions = resource->actions;
788 uint32_t i = resource->actions_num;
790 if (i >= MLX5_MODIFY_NUM)
791 return rte_flow_error_set(error, EINVAL,
792 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
793 "too many items to modify");
794 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
795 actions[i].field = reg_to_field[conf->id];
796 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
797 actions[i].data1 = conf->data;
799 resource->actions_num = i;
800 if (!resource->actions_num)
801 return rte_flow_error_set(error, EINVAL,
802 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
803 "invalid modification flow item");
808 * Validate META item.
811 * Pointer to the rte_eth_dev structure.
813 * Item specification.
815 * Attributes of flow that includes this item.
817 * Pointer to error structure.
820 * 0 on success, a negative errno value otherwise and rte_errno is set.
823 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
824 const struct rte_flow_item *item,
825 const struct rte_flow_attr *attr,
826 struct rte_flow_error *error)
828 const struct rte_flow_item_meta *spec = item->spec;
829 const struct rte_flow_item_meta *mask = item->mask;
830 const struct rte_flow_item_meta nic_mask = {
831 .data = RTE_BE32(UINT32_MAX)
834 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
836 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
837 return rte_flow_error_set(error, EPERM,
838 RTE_FLOW_ERROR_TYPE_ITEM,
840 "match on metadata offload "
841 "configuration is off for this port");
843 return rte_flow_error_set(error, EINVAL,
844 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
846 "data cannot be empty");
848 return rte_flow_error_set(error, EINVAL,
849 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
851 "data cannot be zero");
853 mask = &rte_flow_item_meta_mask;
854 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
855 (const uint8_t *)&nic_mask,
856 sizeof(struct rte_flow_item_meta),
861 return rte_flow_error_set(error, ENOTSUP,
862 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
864 "pattern not supported for ingress");
869 * Validate vport item.
872 * Pointer to the rte_eth_dev structure.
874 * Item specification.
876 * Attributes of flow that includes this item.
877 * @param[in] item_flags
878 * Bit-fields that holds the items detected until now.
880 * Pointer to error structure.
883 * 0 on success, a negative errno value otherwise and rte_errno is set.
886 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
887 const struct rte_flow_item *item,
888 const struct rte_flow_attr *attr,
890 struct rte_flow_error *error)
892 const struct rte_flow_item_port_id *spec = item->spec;
893 const struct rte_flow_item_port_id *mask = item->mask;
894 const struct rte_flow_item_port_id switch_mask = {
897 struct mlx5_priv *esw_priv;
898 struct mlx5_priv *dev_priv;
902 return rte_flow_error_set(error, EINVAL,
903 RTE_FLOW_ERROR_TYPE_ITEM,
905 "match on port id is valid only"
906 " when transfer flag is enabled");
907 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
908 return rte_flow_error_set(error, ENOTSUP,
909 RTE_FLOW_ERROR_TYPE_ITEM, item,
910 "multiple source ports are not"
914 if (mask->id != 0xffffffff)
915 return rte_flow_error_set(error, ENOTSUP,
916 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
918 "no support for partial mask on"
920 ret = mlx5_flow_item_acceptable
921 (item, (const uint8_t *)mask,
922 (const uint8_t *)&rte_flow_item_port_id_mask,
923 sizeof(struct rte_flow_item_port_id),
929 esw_priv = mlx5_port_to_eswitch_info(spec->id);
931 return rte_flow_error_set(error, rte_errno,
932 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
933 "failed to obtain E-Switch info for"
935 dev_priv = mlx5_dev_to_eswitch_info(dev);
937 return rte_flow_error_set(error, rte_errno,
938 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
940 "failed to obtain E-Switch info");
941 if (esw_priv->domain_id != dev_priv->domain_id)
942 return rte_flow_error_set(error, EINVAL,
943 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
944 "cannot match on a port from a"
945 " different E-Switch");
950 * Validate the pop VLAN action.
953 * Pointer to the rte_eth_dev structure.
954 * @param[in] action_flags
955 * Holds the actions detected until now.
957 * Pointer to the pop vlan action.
958 * @param[in] item_flags
959 * The items found in this flow rule.
961 * Pointer to flow attributes.
963 * Pointer to error structure.
966 * 0 on success, a negative errno value otherwise and rte_errno is set.
969 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
970 uint64_t action_flags,
971 const struct rte_flow_action *action,
973 const struct rte_flow_attr *attr,
974 struct rte_flow_error *error)
976 struct mlx5_priv *priv = dev->data->dev_private;
980 if (!priv->sh->pop_vlan_action)
981 return rte_flow_error_set(error, ENOTSUP,
982 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
984 "pop vlan action is not supported");
986 * Check for inconsistencies:
987 * fail strip_vlan in a flow that matches packets without VLAN tags.
988 * fail strip_vlan in a flow that matches packets without explicitly a
989 * matching on VLAN tag ?
991 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
992 return rte_flow_error_set(error, ENOTSUP,
993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
995 "no support for multiple vlan pop "
997 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
998 return rte_flow_error_set(error, ENOTSUP,
999 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1001 "cannot pop vlan without a "
1002 "match on (outer) vlan in the flow");
1003 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1004 return rte_flow_error_set(error, EINVAL,
1005 RTE_FLOW_ERROR_TYPE_ACTION, action,
1006 "wrong action order, port_id should "
1007 "be after pop VLAN action");
1012 * Get VLAN default info from vlan match info.
1015 * Pointer to the rte_eth_dev structure.
1017 * the list of item specifications.
1019 * pointer VLAN info to fill to.
1021 * Pointer to error structure.
1024 * 0 on success, a negative errno value otherwise and rte_errno is set.
1027 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1028 struct rte_vlan_hdr *vlan)
1030 const struct rte_flow_item_vlan nic_mask = {
1031 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1032 MLX5DV_FLOW_VLAN_VID_MASK),
1033 .inner_type = RTE_BE16(0xffff),
1038 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1039 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1041 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1042 const struct rte_flow_item_vlan *vlan_m = items->mask;
1043 const struct rte_flow_item_vlan *vlan_v = items->spec;
1047 /* Only full match values are accepted */
1048 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1049 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1050 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1052 rte_be_to_cpu_16(vlan_v->tci &
1053 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1055 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1056 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1057 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1059 rte_be_to_cpu_16(vlan_v->tci &
1060 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1062 if (vlan_m->inner_type == nic_mask.inner_type)
1063 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1064 vlan_m->inner_type);
1069 * Validate the push VLAN action.
1071 * @param[in] action_flags
1072 * Holds the actions detected until now.
1074 * Pointer to the encap action.
1076 * Pointer to flow attributes
1078 * Pointer to error structure.
1081 * 0 on success, a negative errno value otherwise and rte_errno is set.
1084 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1085 uint64_t item_flags,
1086 const struct rte_flow_action *action,
1087 const struct rte_flow_attr *attr,
1088 struct rte_flow_error *error)
1090 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1092 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1093 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1094 return rte_flow_error_set(error, EINVAL,
1095 RTE_FLOW_ERROR_TYPE_ACTION, action,
1096 "invalid vlan ethertype");
1098 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1099 return rte_flow_error_set(error, ENOTSUP,
1100 RTE_FLOW_ERROR_TYPE_ACTION, action,
1101 "no support for multiple VLAN "
1103 if (!mlx5_flow_find_action
1104 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1105 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1106 return rte_flow_error_set(error, ENOTSUP,
1107 RTE_FLOW_ERROR_TYPE_ACTION, action,
1108 "push VLAN needs to match on VLAN in order to "
1109 "get VLAN VID information because there is "
1110 "no followed set VLAN VID action");
1111 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1112 return rte_flow_error_set(error, EINVAL,
1113 RTE_FLOW_ERROR_TYPE_ACTION, action,
1114 "wrong action order, port_id should "
1115 "be after push VLAN");
1121 * Validate the set VLAN PCP.
1123 * @param[in] action_flags
1124 * Holds the actions detected until now.
1125 * @param[in] actions
1126 * Pointer to the list of actions remaining in the flow rule.
1128 * Pointer to flow attributes
1130 * Pointer to error structure.
1133 * 0 on success, a negative errno value otherwise and rte_errno is set.
1136 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1137 const struct rte_flow_action actions[],
1138 struct rte_flow_error *error)
1140 const struct rte_flow_action *action = actions;
1141 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1143 if (conf->vlan_pcp > 7)
1144 return rte_flow_error_set(error, EINVAL,
1145 RTE_FLOW_ERROR_TYPE_ACTION, action,
1146 "VLAN PCP value is too big");
1147 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1148 return rte_flow_error_set(error, ENOTSUP,
1149 RTE_FLOW_ERROR_TYPE_ACTION, action,
1150 "set VLAN PCP action must follow "
1151 "the push VLAN action");
1152 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1153 return rte_flow_error_set(error, ENOTSUP,
1154 RTE_FLOW_ERROR_TYPE_ACTION, action,
1155 "Multiple VLAN PCP modification are "
1157 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1158 return rte_flow_error_set(error, EINVAL,
1159 RTE_FLOW_ERROR_TYPE_ACTION, action,
1160 "wrong action order, port_id should "
1161 "be after set VLAN PCP");
1166 * Validate the set VLAN VID.
1168 * @param[in] item_flags
1169 * Holds the items detected in this rule.
1170 * @param[in] actions
1171 * Pointer to the list of actions remaining in the flow rule.
1173 * Pointer to flow attributes
1175 * Pointer to error structure.
1178 * 0 on success, a negative errno value otherwise and rte_errno is set.
1181 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1182 uint64_t action_flags,
1183 const struct rte_flow_action actions[],
1184 struct rte_flow_error *error)
1186 const struct rte_flow_action *action = actions;
1187 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1189 if (conf->vlan_vid > RTE_BE16(0xFFE))
1190 return rte_flow_error_set(error, EINVAL,
1191 RTE_FLOW_ERROR_TYPE_ACTION, action,
1192 "VLAN VID value is too big");
1193 /* there is an of_push_vlan action before us */
1194 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1195 if (mlx5_flow_find_action(actions + 1,
1196 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1197 return rte_flow_error_set(error, ENOTSUP,
1198 RTE_FLOW_ERROR_TYPE_ACTION, action,
1199 "Multiple VLAN VID modifications are "
1206 * Action is on an existing VLAN header:
1207 * Need to verify this is a single modify CID action.
1208 * Rule mast include a match on outer VLAN.
1210 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1211 return rte_flow_error_set(error, ENOTSUP,
1212 RTE_FLOW_ERROR_TYPE_ACTION, action,
1213 "Multiple VLAN VID modifications are "
1215 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION, action,
1218 "match on VLAN is required in order "
1220 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1221 return rte_flow_error_set(error, EINVAL,
1222 RTE_FLOW_ERROR_TYPE_ACTION, action,
1223 "wrong action order, port_id should "
1224 "be after set VLAN VID");
1229 * Validate count action.
1234 * Pointer to error structure.
1237 * 0 on success, a negative errno value otherwise and rte_errno is set.
1240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1241 struct rte_flow_error *error)
1243 struct mlx5_priv *priv = dev->data->dev_private;
1245 if (!priv->config.devx)
1247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1251 return rte_flow_error_set
1253 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1255 "count action not supported");
1259 * Validate the L2 encap action.
1261 * @param[in] action_flags
1262 * Holds the actions detected until now.
1264 * Pointer to the encap action.
1266 * Pointer to flow attributes
1268 * Pointer to error structure.
1271 * 0 on success, a negative errno value otherwise and rte_errno is set.
1274 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1275 const struct rte_flow_action *action,
1276 const struct rte_flow_attr *attr,
1277 struct rte_flow_error *error)
1279 if (!(action->conf))
1280 return rte_flow_error_set(error, EINVAL,
1281 RTE_FLOW_ERROR_TYPE_ACTION, action,
1282 "configuration cannot be null");
1283 if (action_flags & MLX5_FLOW_ACTION_DROP)
1284 return rte_flow_error_set(error, EINVAL,
1285 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1286 "can't drop and encap in same flow");
1287 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1288 return rte_flow_error_set(error, EINVAL,
1289 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1290 "can only have a single encap or"
1291 " decap action in a flow");
1292 if (!attr->transfer && attr->ingress)
1293 return rte_flow_error_set(error, ENOTSUP,
1294 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1296 "encap action not supported for "
1302 * Validate the L2 decap action.
1304 * @param[in] action_flags
1305 * Holds the actions detected until now.
1307 * Pointer to flow attributes
1309 * Pointer to error structure.
1312 * 0 on success, a negative errno value otherwise and rte_errno is set.
1315 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1316 const struct rte_flow_attr *attr,
1317 struct rte_flow_error *error)
1319 if (action_flags & MLX5_FLOW_ACTION_DROP)
1320 return rte_flow_error_set(error, EINVAL,
1321 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1322 "can't drop and decap in same flow");
1323 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1324 return rte_flow_error_set(error, EINVAL,
1325 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1326 "can only have a single encap or"
1327 " decap action in a flow");
1328 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1329 return rte_flow_error_set(error, EINVAL,
1330 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1331 "can't have decap action after"
1334 return rte_flow_error_set(error, ENOTSUP,
1335 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1337 "decap action not supported for "
1343 * Validate the raw encap action.
1345 * @param[in] action_flags
1346 * Holds the actions detected until now.
1348 * Pointer to the encap action.
1350 * Pointer to flow attributes
1352 * Pointer to error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1359 const struct rte_flow_action *action,
1360 const struct rte_flow_attr *attr,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_raw_encap *raw_encap =
1364 (const struct rte_flow_action_raw_encap *)action->conf;
1365 if (!(action->conf))
1366 return rte_flow_error_set(error, EINVAL,
1367 RTE_FLOW_ERROR_TYPE_ACTION, action,
1368 "configuration cannot be null");
1369 if (action_flags & MLX5_FLOW_ACTION_DROP)
1370 return rte_flow_error_set(error, EINVAL,
1371 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1372 "can't drop and encap in same flow");
1373 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1374 return rte_flow_error_set(error, EINVAL,
1375 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1376 "can only have a single encap"
1377 " action in a flow");
1378 /* encap without preceding decap is not supported for ingress */
1379 if (!attr->transfer && attr->ingress &&
1380 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1381 return rte_flow_error_set(error, ENOTSUP,
1382 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1384 "encap action not supported for "
1386 if (!raw_encap->size || !raw_encap->data)
1387 return rte_flow_error_set(error, EINVAL,
1388 RTE_FLOW_ERROR_TYPE_ACTION, action,
1389 "raw encap data cannot be empty");
1394 * Validate the raw decap action.
1396 * @param[in] action_flags
1397 * Holds the actions detected until now.
1399 * Pointer to the encap action.
1401 * Pointer to flow attributes
1403 * Pointer to error structure.
1406 * 0 on success, a negative errno value otherwise and rte_errno is set.
1409 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1410 const struct rte_flow_action *action,
1411 const struct rte_flow_attr *attr,
1412 struct rte_flow_error *error)
1414 if (action_flags & MLX5_FLOW_ACTION_DROP)
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1417 "can't drop and decap in same flow");
1418 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1419 return rte_flow_error_set(error, EINVAL,
1420 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1421 "can't have encap action before"
1423 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1424 return rte_flow_error_set(error, EINVAL,
1425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1426 "can only have a single decap"
1427 " action in a flow");
1428 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1429 return rte_flow_error_set(error, EINVAL,
1430 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1431 "can't have decap action after"
1433 /* decap action is valid on egress only if it is followed by encap */
1435 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1436 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1439 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1440 return rte_flow_error_set
1442 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1443 NULL, "decap action not supported"
1450 * Find existing encap/decap resource or create and register a new one.
1452 * @param dev[in, out]
1453 * Pointer to rte_eth_dev structure.
1454 * @param[in, out] resource
1455 * Pointer to encap/decap resource.
1456 * @parm[in, out] dev_flow
1457 * Pointer to the dev_flow.
1459 * pointer to error structure.
1462 * 0 on success otherwise -errno and errno is set.
1465 flow_dv_encap_decap_resource_register
1466 (struct rte_eth_dev *dev,
1467 struct mlx5_flow_dv_encap_decap_resource *resource,
1468 struct mlx5_flow *dev_flow,
1469 struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1472 struct mlx5_ibv_shared *sh = priv->sh;
1473 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1474 struct rte_flow *flow = dev_flow->flow;
1475 struct mlx5dv_dr_domain *domain;
1477 resource->flags = flow->group ? 0 : 1;
1478 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1479 domain = sh->fdb_domain;
1480 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1481 domain = sh->rx_domain;
1483 domain = sh->tx_domain;
1485 /* Lookup a matching resource from cache. */
1486 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1487 if (resource->reformat_type == cache_resource->reformat_type &&
1488 resource->ft_type == cache_resource->ft_type &&
1489 resource->flags == cache_resource->flags &&
1490 resource->size == cache_resource->size &&
1491 !memcmp((const void *)resource->buf,
1492 (const void *)cache_resource->buf,
1494 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1495 (void *)cache_resource,
1496 rte_atomic32_read(&cache_resource->refcnt));
1497 rte_atomic32_inc(&cache_resource->refcnt);
1498 dev_flow->dv.encap_decap = cache_resource;
1502 /* Register new encap/decap resource. */
1503 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1504 if (!cache_resource)
1505 return rte_flow_error_set(error, ENOMEM,
1506 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1507 "cannot allocate resource memory");
1508 *cache_resource = *resource;
1509 cache_resource->verbs_action =
1510 mlx5_glue->dv_create_flow_action_packet_reformat
1511 (sh->ctx, cache_resource->reformat_type,
1512 cache_resource->ft_type, domain, cache_resource->flags,
1513 cache_resource->size,
1514 (cache_resource->size ? cache_resource->buf : NULL));
1515 if (!cache_resource->verbs_action) {
1516 rte_free(cache_resource);
1517 return rte_flow_error_set(error, ENOMEM,
1518 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1519 NULL, "cannot create action");
1521 rte_atomic32_init(&cache_resource->refcnt);
1522 rte_atomic32_inc(&cache_resource->refcnt);
1523 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1524 dev_flow->dv.encap_decap = cache_resource;
1525 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1526 (void *)cache_resource,
1527 rte_atomic32_read(&cache_resource->refcnt));
1532 * Find existing table jump resource or create and register a new one.
1534 * @param dev[in, out]
1535 * Pointer to rte_eth_dev structure.
1536 * @param[in, out] resource
1537 * Pointer to jump table resource.
1538 * @parm[in, out] dev_flow
1539 * Pointer to the dev_flow.
1541 * pointer to error structure.
1544 * 0 on success otherwise -errno and errno is set.
1547 flow_dv_jump_tbl_resource_register
1548 (struct rte_eth_dev *dev,
1549 struct mlx5_flow_dv_jump_tbl_resource *resource,
1550 struct mlx5_flow *dev_flow,
1551 struct rte_flow_error *error)
1553 struct mlx5_priv *priv = dev->data->dev_private;
1554 struct mlx5_ibv_shared *sh = priv->sh;
1555 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1557 /* Lookup a matching resource from cache. */
1558 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1559 if (resource->tbl == cache_resource->tbl) {
1560 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1561 (void *)cache_resource,
1562 rte_atomic32_read(&cache_resource->refcnt));
1563 rte_atomic32_inc(&cache_resource->refcnt);
1564 dev_flow->dv.jump = cache_resource;
1568 /* Register new jump table resource. */
1569 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1570 if (!cache_resource)
1571 return rte_flow_error_set(error, ENOMEM,
1572 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1573 "cannot allocate resource memory");
1574 *cache_resource = *resource;
1575 cache_resource->action =
1576 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1577 (resource->tbl->obj);
1578 if (!cache_resource->action) {
1579 rte_free(cache_resource);
1580 return rte_flow_error_set(error, ENOMEM,
1581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1582 NULL, "cannot create action");
1584 rte_atomic32_init(&cache_resource->refcnt);
1585 rte_atomic32_inc(&cache_resource->refcnt);
1586 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1587 dev_flow->dv.jump = cache_resource;
1588 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1589 (void *)cache_resource,
1590 rte_atomic32_read(&cache_resource->refcnt));
1595 * Find existing table port ID resource or create and register a new one.
1597 * @param dev[in, out]
1598 * Pointer to rte_eth_dev structure.
1599 * @param[in, out] resource
1600 * Pointer to port ID action resource.
1601 * @parm[in, out] dev_flow
1602 * Pointer to the dev_flow.
1604 * pointer to error structure.
1607 * 0 on success otherwise -errno and errno is set.
1610 flow_dv_port_id_action_resource_register
1611 (struct rte_eth_dev *dev,
1612 struct mlx5_flow_dv_port_id_action_resource *resource,
1613 struct mlx5_flow *dev_flow,
1614 struct rte_flow_error *error)
1616 struct mlx5_priv *priv = dev->data->dev_private;
1617 struct mlx5_ibv_shared *sh = priv->sh;
1618 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1620 /* Lookup a matching resource from cache. */
1621 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1622 if (resource->port_id == cache_resource->port_id) {
1623 DRV_LOG(DEBUG, "port id action resource resource %p: "
1625 (void *)cache_resource,
1626 rte_atomic32_read(&cache_resource->refcnt));
1627 rte_atomic32_inc(&cache_resource->refcnt);
1628 dev_flow->dv.port_id_action = cache_resource;
1632 /* Register new port id action resource. */
1633 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1634 if (!cache_resource)
1635 return rte_flow_error_set(error, ENOMEM,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1637 "cannot allocate resource memory");
1638 *cache_resource = *resource;
1639 cache_resource->action =
1640 mlx5_glue->dr_create_flow_action_dest_vport
1641 (priv->sh->fdb_domain, resource->port_id);
1642 if (!cache_resource->action) {
1643 rte_free(cache_resource);
1644 return rte_flow_error_set(error, ENOMEM,
1645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1646 NULL, "cannot create action");
1648 rte_atomic32_init(&cache_resource->refcnt);
1649 rte_atomic32_inc(&cache_resource->refcnt);
1650 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1651 dev_flow->dv.port_id_action = cache_resource;
1652 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1653 (void *)cache_resource,
1654 rte_atomic32_read(&cache_resource->refcnt));
1659 * Find existing push vlan resource or create and register a new one.
1661 * @param dev[in, out]
1662 * Pointer to rte_eth_dev structure.
1663 * @param[in, out] resource
1664 * Pointer to port ID action resource.
1665 * @parm[in, out] dev_flow
1666 * Pointer to the dev_flow.
1668 * pointer to error structure.
1671 * 0 on success otherwise -errno and errno is set.
1674 flow_dv_push_vlan_action_resource_register
1675 (struct rte_eth_dev *dev,
1676 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1677 struct mlx5_flow *dev_flow,
1678 struct rte_flow_error *error)
1680 struct mlx5_priv *priv = dev->data->dev_private;
1681 struct mlx5_ibv_shared *sh = priv->sh;
1682 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1683 struct mlx5dv_dr_domain *domain;
1685 /* Lookup a matching resource from cache. */
1686 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1687 if (resource->vlan_tag == cache_resource->vlan_tag &&
1688 resource->ft_type == cache_resource->ft_type) {
1689 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1691 (void *)cache_resource,
1692 rte_atomic32_read(&cache_resource->refcnt));
1693 rte_atomic32_inc(&cache_resource->refcnt);
1694 dev_flow->dv.push_vlan_res = cache_resource;
1698 /* Register new push_vlan action resource. */
1699 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1700 if (!cache_resource)
1701 return rte_flow_error_set(error, ENOMEM,
1702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1703 "cannot allocate resource memory");
1704 *cache_resource = *resource;
1705 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1706 domain = sh->fdb_domain;
1707 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1708 domain = sh->rx_domain;
1710 domain = sh->tx_domain;
1711 cache_resource->action =
1712 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1713 resource->vlan_tag);
1714 if (!cache_resource->action) {
1715 rte_free(cache_resource);
1716 return rte_flow_error_set(error, ENOMEM,
1717 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1718 NULL, "cannot create action");
1720 rte_atomic32_init(&cache_resource->refcnt);
1721 rte_atomic32_inc(&cache_resource->refcnt);
1722 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1723 dev_flow->dv.push_vlan_res = cache_resource;
1724 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1725 (void *)cache_resource,
1726 rte_atomic32_read(&cache_resource->refcnt));
1730 * Get the size of specific rte_flow_item_type
1732 * @param[in] item_type
1733 * Tested rte_flow_item_type.
1736 * sizeof struct item_type, 0 if void or irrelevant.
1739 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1743 switch (item_type) {
1744 case RTE_FLOW_ITEM_TYPE_ETH:
1745 retval = sizeof(struct rte_flow_item_eth);
1747 case RTE_FLOW_ITEM_TYPE_VLAN:
1748 retval = sizeof(struct rte_flow_item_vlan);
1750 case RTE_FLOW_ITEM_TYPE_IPV4:
1751 retval = sizeof(struct rte_flow_item_ipv4);
1753 case RTE_FLOW_ITEM_TYPE_IPV6:
1754 retval = sizeof(struct rte_flow_item_ipv6);
1756 case RTE_FLOW_ITEM_TYPE_UDP:
1757 retval = sizeof(struct rte_flow_item_udp);
1759 case RTE_FLOW_ITEM_TYPE_TCP:
1760 retval = sizeof(struct rte_flow_item_tcp);
1762 case RTE_FLOW_ITEM_TYPE_VXLAN:
1763 retval = sizeof(struct rte_flow_item_vxlan);
1765 case RTE_FLOW_ITEM_TYPE_GRE:
1766 retval = sizeof(struct rte_flow_item_gre);
1768 case RTE_FLOW_ITEM_TYPE_NVGRE:
1769 retval = sizeof(struct rte_flow_item_nvgre);
1771 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1772 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1774 case RTE_FLOW_ITEM_TYPE_MPLS:
1775 retval = sizeof(struct rte_flow_item_mpls);
1777 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1785 #define MLX5_ENCAP_IPV4_VERSION 0x40
1786 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1787 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1788 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1789 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1790 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1791 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1794 * Convert the encap action data from list of rte_flow_item to raw buffer
1797 * Pointer to rte_flow_item objects list.
1799 * Pointer to the output buffer.
1801 * Pointer to the output buffer size.
1803 * Pointer to the error structure.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1810 size_t *size, struct rte_flow_error *error)
1812 struct rte_ether_hdr *eth = NULL;
1813 struct rte_vlan_hdr *vlan = NULL;
1814 struct rte_ipv4_hdr *ipv4 = NULL;
1815 struct rte_ipv6_hdr *ipv6 = NULL;
1816 struct rte_udp_hdr *udp = NULL;
1817 struct rte_vxlan_hdr *vxlan = NULL;
1818 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1819 struct rte_gre_hdr *gre = NULL;
1821 size_t temp_size = 0;
1824 return rte_flow_error_set(error, EINVAL,
1825 RTE_FLOW_ERROR_TYPE_ACTION,
1826 NULL, "invalid empty data");
1827 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1828 len = flow_dv_get_item_len(items->type);
1829 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1830 return rte_flow_error_set(error, EINVAL,
1831 RTE_FLOW_ERROR_TYPE_ACTION,
1832 (void *)items->type,
1833 "items total size is too big"
1834 " for encap action");
1835 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1836 switch (items->type) {
1837 case RTE_FLOW_ITEM_TYPE_ETH:
1838 eth = (struct rte_ether_hdr *)&buf[temp_size];
1840 case RTE_FLOW_ITEM_TYPE_VLAN:
1841 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1843 return rte_flow_error_set(error, EINVAL,
1844 RTE_FLOW_ERROR_TYPE_ACTION,
1845 (void *)items->type,
1846 "eth header not found");
1847 if (!eth->ether_type)
1848 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1850 case RTE_FLOW_ITEM_TYPE_IPV4:
1851 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION,
1855 (void *)items->type,
1856 "neither eth nor vlan"
1858 if (vlan && !vlan->eth_proto)
1859 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1860 else if (eth && !eth->ether_type)
1861 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1862 if (!ipv4->version_ihl)
1863 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1864 MLX5_ENCAP_IPV4_IHL_MIN;
1865 if (!ipv4->time_to_live)
1866 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1868 case RTE_FLOW_ITEM_TYPE_IPV6:
1869 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1871 return rte_flow_error_set(error, EINVAL,
1872 RTE_FLOW_ERROR_TYPE_ACTION,
1873 (void *)items->type,
1874 "neither eth nor vlan"
1876 if (vlan && !vlan->eth_proto)
1877 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1878 else if (eth && !eth->ether_type)
1879 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1880 if (!ipv6->vtc_flow)
1882 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1883 if (!ipv6->hop_limits)
1884 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1886 case RTE_FLOW_ITEM_TYPE_UDP:
1887 udp = (struct rte_udp_hdr *)&buf[temp_size];
1889 return rte_flow_error_set(error, EINVAL,
1890 RTE_FLOW_ERROR_TYPE_ACTION,
1891 (void *)items->type,
1892 "ip header not found");
1893 if (ipv4 && !ipv4->next_proto_id)
1894 ipv4->next_proto_id = IPPROTO_UDP;
1895 else if (ipv6 && !ipv6->proto)
1896 ipv6->proto = IPPROTO_UDP;
1898 case RTE_FLOW_ITEM_TYPE_VXLAN:
1899 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1901 return rte_flow_error_set(error, EINVAL,
1902 RTE_FLOW_ERROR_TYPE_ACTION,
1903 (void *)items->type,
1904 "udp header not found");
1906 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1907 if (!vxlan->vx_flags)
1909 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1911 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1912 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1914 return rte_flow_error_set(error, EINVAL,
1915 RTE_FLOW_ERROR_TYPE_ACTION,
1916 (void *)items->type,
1917 "udp header not found");
1918 if (!vxlan_gpe->proto)
1919 return rte_flow_error_set(error, EINVAL,
1920 RTE_FLOW_ERROR_TYPE_ACTION,
1921 (void *)items->type,
1922 "next protocol not found");
1925 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1926 if (!vxlan_gpe->vx_flags)
1927 vxlan_gpe->vx_flags =
1928 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1930 case RTE_FLOW_ITEM_TYPE_GRE:
1931 case RTE_FLOW_ITEM_TYPE_NVGRE:
1932 gre = (struct rte_gre_hdr *)&buf[temp_size];
1934 return rte_flow_error_set(error, EINVAL,
1935 RTE_FLOW_ERROR_TYPE_ACTION,
1936 (void *)items->type,
1937 "next protocol not found");
1939 return rte_flow_error_set(error, EINVAL,
1940 RTE_FLOW_ERROR_TYPE_ACTION,
1941 (void *)items->type,
1942 "ip header not found");
1943 if (ipv4 && !ipv4->next_proto_id)
1944 ipv4->next_proto_id = IPPROTO_GRE;
1945 else if (ipv6 && !ipv6->proto)
1946 ipv6->proto = IPPROTO_GRE;
1948 case RTE_FLOW_ITEM_TYPE_VOID:
1951 return rte_flow_error_set(error, EINVAL,
1952 RTE_FLOW_ERROR_TYPE_ACTION,
1953 (void *)items->type,
1954 "unsupported item type");
1964 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1966 struct rte_ether_hdr *eth = NULL;
1967 struct rte_vlan_hdr *vlan = NULL;
1968 struct rte_ipv6_hdr *ipv6 = NULL;
1969 struct rte_udp_hdr *udp = NULL;
1973 eth = (struct rte_ether_hdr *)data;
1974 next_hdr = (char *)(eth + 1);
1975 proto = RTE_BE16(eth->ether_type);
1978 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1979 vlan = (struct rte_vlan_hdr *)next_hdr;
1980 proto = RTE_BE16(vlan->eth_proto);
1981 next_hdr += sizeof(struct rte_vlan_hdr);
1984 /* HW calculates IPv4 csum. no need to proceed */
1985 if (proto == RTE_ETHER_TYPE_IPV4)
1988 /* non IPv4/IPv6 header. not supported */
1989 if (proto != RTE_ETHER_TYPE_IPV6) {
1990 return rte_flow_error_set(error, ENOTSUP,
1991 RTE_FLOW_ERROR_TYPE_ACTION,
1992 NULL, "Cannot offload non IPv4/IPv6");
1995 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1997 /* ignore non UDP */
1998 if (ipv6->proto != IPPROTO_UDP)
2001 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2002 udp->dgram_cksum = 0;
2008 * Convert L2 encap action to DV specification.
2011 * Pointer to rte_eth_dev structure.
2013 * Pointer to action structure.
2014 * @param[in, out] dev_flow
2015 * Pointer to the mlx5_flow.
2016 * @param[in] transfer
2017 * Mark if the flow is E-Switch flow.
2019 * Pointer to the error structure.
2022 * 0 on success, a negative errno value otherwise and rte_errno is set.
2025 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2026 const struct rte_flow_action *action,
2027 struct mlx5_flow *dev_flow,
2029 struct rte_flow_error *error)
2031 const struct rte_flow_item *encap_data;
2032 const struct rte_flow_action_raw_encap *raw_encap_data;
2033 struct mlx5_flow_dv_encap_decap_resource res = {
2035 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2036 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2037 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2040 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2042 (const struct rte_flow_action_raw_encap *)action->conf;
2043 res.size = raw_encap_data->size;
2044 memcpy(res.buf, raw_encap_data->data, res.size);
2045 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2048 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2050 ((const struct rte_flow_action_vxlan_encap *)
2051 action->conf)->definition;
2054 ((const struct rte_flow_action_nvgre_encap *)
2055 action->conf)->definition;
2056 if (flow_dv_convert_encap_data(encap_data, res.buf,
2060 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ACTION,
2063 NULL, "can't create L2 encap action");
2068 * Convert L2 decap action to DV specification.
2071 * Pointer to rte_eth_dev structure.
2072 * @param[in, out] dev_flow
2073 * Pointer to the mlx5_flow.
2074 * @param[in] transfer
2075 * Mark if the flow is E-Switch flow.
2077 * Pointer to the error structure.
2080 * 0 on success, a negative errno value otherwise and rte_errno is set.
2083 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2084 struct mlx5_flow *dev_flow,
2086 struct rte_flow_error *error)
2088 struct mlx5_flow_dv_encap_decap_resource res = {
2091 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2092 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2093 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2096 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2097 return rte_flow_error_set(error, EINVAL,
2098 RTE_FLOW_ERROR_TYPE_ACTION,
2099 NULL, "can't create L2 decap action");
2104 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2107 * Pointer to rte_eth_dev structure.
2109 * Pointer to action structure.
2110 * @param[in, out] dev_flow
2111 * Pointer to the mlx5_flow.
2113 * Pointer to the flow attributes.
2115 * Pointer to the error structure.
2118 * 0 on success, a negative errno value otherwise and rte_errno is set.
2121 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2122 const struct rte_flow_action *action,
2123 struct mlx5_flow *dev_flow,
2124 const struct rte_flow_attr *attr,
2125 struct rte_flow_error *error)
2127 const struct rte_flow_action_raw_encap *encap_data;
2128 struct mlx5_flow_dv_encap_decap_resource res;
2130 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2131 res.size = encap_data->size;
2132 memcpy(res.buf, encap_data->data, res.size);
2133 res.reformat_type = attr->egress ?
2134 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2135 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2137 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2139 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2140 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2141 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2142 return rte_flow_error_set(error, EINVAL,
2143 RTE_FLOW_ERROR_TYPE_ACTION,
2144 NULL, "can't create encap action");
2149 * Create action push VLAN.
2152 * Pointer to rte_eth_dev structure.
2153 * @param[in] vlan_tag
2154 * the vlan tag to push to the Ethernet header.
2155 * @param[in, out] dev_flow
2156 * Pointer to the mlx5_flow.
2158 * Pointer to the flow attributes.
2160 * Pointer to the error structure.
2163 * 0 on success, a negative errno value otherwise and rte_errno is set.
2166 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2167 const struct rte_flow_attr *attr,
2168 const struct rte_vlan_hdr *vlan,
2169 struct mlx5_flow *dev_flow,
2170 struct rte_flow_error *error)
2172 struct mlx5_flow_dv_push_vlan_action_resource res;
2175 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2178 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2180 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2181 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2182 return flow_dv_push_vlan_action_resource_register
2183 (dev, &res, dev_flow, error);
2187 * Validate the modify-header actions.
2189 * @param[in] action_flags
2190 * Holds the actions detected until now.
2192 * Pointer to the modify action.
2194 * Pointer to error structure.
2197 * 0 on success, a negative errno value otherwise and rte_errno is set.
2200 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2201 const struct rte_flow_action *action,
2202 struct rte_flow_error *error)
2204 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2205 return rte_flow_error_set(error, EINVAL,
2206 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2207 NULL, "action configuration not set");
2208 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2209 return rte_flow_error_set(error, EINVAL,
2210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2211 "can't have encap action before"
2217 * Validate the modify-header MAC address actions.
2219 * @param[in] action_flags
2220 * Holds the actions detected until now.
2222 * Pointer to the modify action.
2223 * @param[in] item_flags
2224 * Holds the items detected.
2226 * Pointer to error structure.
2229 * 0 on success, a negative errno value otherwise and rte_errno is set.
2232 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2233 const struct rte_flow_action *action,
2234 const uint64_t item_flags,
2235 struct rte_flow_error *error)
2239 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2241 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2242 return rte_flow_error_set(error, EINVAL,
2243 RTE_FLOW_ERROR_TYPE_ACTION,
2245 "no L2 item in pattern");
2251 * Validate the modify-header IPv4 address actions.
2253 * @param[in] action_flags
2254 * Holds the actions detected until now.
2256 * Pointer to the modify action.
2257 * @param[in] item_flags
2258 * Holds the items detected.
2260 * Pointer to error structure.
2263 * 0 on success, a negative errno value otherwise and rte_errno is set.
2266 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2267 const struct rte_flow_action *action,
2268 const uint64_t item_flags,
2269 struct rte_flow_error *error)
2273 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2275 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2276 return rte_flow_error_set(error, EINVAL,
2277 RTE_FLOW_ERROR_TYPE_ACTION,
2279 "no ipv4 item in pattern");
2285 * Validate the modify-header IPv6 address actions.
2287 * @param[in] action_flags
2288 * Holds the actions detected until now.
2290 * Pointer to the modify action.
2291 * @param[in] item_flags
2292 * Holds the items detected.
2294 * Pointer to error structure.
2297 * 0 on success, a negative errno value otherwise and rte_errno is set.
2300 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2301 const struct rte_flow_action *action,
2302 const uint64_t item_flags,
2303 struct rte_flow_error *error)
2307 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2309 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2310 return rte_flow_error_set(error, EINVAL,
2311 RTE_FLOW_ERROR_TYPE_ACTION,
2313 "no ipv6 item in pattern");
2319 * Validate the modify-header TP actions.
2321 * @param[in] action_flags
2322 * Holds the actions detected until now.
2324 * Pointer to the modify action.
2325 * @param[in] item_flags
2326 * Holds the items detected.
2328 * Pointer to error structure.
2331 * 0 on success, a negative errno value otherwise and rte_errno is set.
2334 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2335 const struct rte_flow_action *action,
2336 const uint64_t item_flags,
2337 struct rte_flow_error *error)
2341 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2343 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2344 return rte_flow_error_set(error, EINVAL,
2345 RTE_FLOW_ERROR_TYPE_ACTION,
2346 NULL, "no transport layer "
2353 * Validate the modify-header actions of increment/decrement
2354 * TCP Sequence-number.
2356 * @param[in] action_flags
2357 * Holds the actions detected until now.
2359 * Pointer to the modify action.
2360 * @param[in] item_flags
2361 * Holds the items detected.
2363 * Pointer to error structure.
2366 * 0 on success, a negative errno value otherwise and rte_errno is set.
2369 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2370 const struct rte_flow_action *action,
2371 const uint64_t item_flags,
2372 struct rte_flow_error *error)
2376 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2378 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2379 return rte_flow_error_set(error, EINVAL,
2380 RTE_FLOW_ERROR_TYPE_ACTION,
2381 NULL, "no TCP item in"
2383 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2384 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2385 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2386 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2387 return rte_flow_error_set(error, EINVAL,
2388 RTE_FLOW_ERROR_TYPE_ACTION,
2390 "cannot decrease and increase"
2391 " TCP sequence number"
2392 " at the same time");
2398 * Validate the modify-header actions of increment/decrement
2399 * TCP Acknowledgment number.
2401 * @param[in] action_flags
2402 * Holds the actions detected until now.
2404 * Pointer to the modify action.
2405 * @param[in] item_flags
2406 * Holds the items detected.
2408 * Pointer to error structure.
2411 * 0 on success, a negative errno value otherwise and rte_errno is set.
2414 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2415 const struct rte_flow_action *action,
2416 const uint64_t item_flags,
2417 struct rte_flow_error *error)
2421 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2423 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2424 return rte_flow_error_set(error, EINVAL,
2425 RTE_FLOW_ERROR_TYPE_ACTION,
2426 NULL, "no TCP item in"
2428 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2429 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2430 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2431 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2432 return rte_flow_error_set(error, EINVAL,
2433 RTE_FLOW_ERROR_TYPE_ACTION,
2435 "cannot decrease and increase"
2436 " TCP acknowledgment number"
2437 " at the same time");
2443 * Validate the modify-header TTL actions.
2445 * @param[in] action_flags
2446 * Holds the actions detected until now.
2448 * Pointer to the modify action.
2449 * @param[in] item_flags
2450 * Holds the items detected.
2452 * Pointer to error structure.
2455 * 0 on success, a negative errno value otherwise and rte_errno is set.
2458 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2459 const struct rte_flow_action *action,
2460 const uint64_t item_flags,
2461 struct rte_flow_error *error)
2465 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2467 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2468 return rte_flow_error_set(error, EINVAL,
2469 RTE_FLOW_ERROR_TYPE_ACTION,
2471 "no IP protocol in pattern");
2477 * Validate jump action.
2480 * Pointer to the jump action.
2481 * @param[in] action_flags
2482 * Holds the actions detected until now.
2483 * @param[in] attributes
2484 * Pointer to flow attributes
2485 * @param[in] external
2486 * Action belongs to flow rule created by request external to PMD.
2488 * Pointer to error structure.
2491 * 0 on success, a negative errno value otherwise and rte_errno is set.
2494 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2495 uint64_t action_flags,
2496 const struct rte_flow_attr *attributes,
2497 bool external, struct rte_flow_error *error)
2499 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2501 uint32_t target_group, table;
2504 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2505 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2506 return rte_flow_error_set(error, EINVAL,
2507 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2508 "can't have 2 fate actions in"
2511 return rte_flow_error_set(error, EINVAL,
2512 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2513 NULL, "action configuration not set");
2515 ((const struct rte_flow_action_jump *)action->conf)->group;
2516 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2520 if (table >= max_group)
2521 return rte_flow_error_set(error, EINVAL,
2522 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2523 "target group index out of range");
2524 if (attributes->group >= target_group)
2525 return rte_flow_error_set(error, EINVAL,
2526 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2527 "target group must be higher than"
2528 " the current flow group");
2533 * Validate the port_id action.
2536 * Pointer to rte_eth_dev structure.
2537 * @param[in] action_flags
2538 * Bit-fields that holds the actions detected until now.
2540 * Port_id RTE action structure.
2542 * Attributes of flow that includes this action.
2544 * Pointer to error structure.
2547 * 0 on success, a negative errno value otherwise and rte_errno is set.
2550 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2551 uint64_t action_flags,
2552 const struct rte_flow_action *action,
2553 const struct rte_flow_attr *attr,
2554 struct rte_flow_error *error)
2556 const struct rte_flow_action_port_id *port_id;
2557 struct mlx5_priv *act_priv;
2558 struct mlx5_priv *dev_priv;
2561 if (!attr->transfer)
2562 return rte_flow_error_set(error, ENOTSUP,
2563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2565 "port id action is valid in transfer"
2567 if (!action || !action->conf)
2568 return rte_flow_error_set(error, ENOTSUP,
2569 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2571 "port id action parameters must be"
2573 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2574 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2575 return rte_flow_error_set(error, EINVAL,
2576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2577 "can have only one fate actions in"
2579 dev_priv = mlx5_dev_to_eswitch_info(dev);
2581 return rte_flow_error_set(error, rte_errno,
2582 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2584 "failed to obtain E-Switch info");
2585 port_id = action->conf;
2586 port = port_id->original ? dev->data->port_id : port_id->id;
2587 act_priv = mlx5_port_to_eswitch_info(port);
2589 return rte_flow_error_set
2591 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2592 "failed to obtain E-Switch port id for port");
2593 if (act_priv->domain_id != dev_priv->domain_id)
2594 return rte_flow_error_set
2596 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2597 "port does not belong to"
2598 " E-Switch being configured");
2603 * Find existing modify-header resource or create and register a new one.
2605 * @param dev[in, out]
2606 * Pointer to rte_eth_dev structure.
2607 * @param[in, out] resource
2608 * Pointer to modify-header resource.
2609 * @parm[in, out] dev_flow
2610 * Pointer to the dev_flow.
2612 * pointer to error structure.
2615 * 0 on success otherwise -errno and errno is set.
2618 flow_dv_modify_hdr_resource_register
2619 (struct rte_eth_dev *dev,
2620 struct mlx5_flow_dv_modify_hdr_resource *resource,
2621 struct mlx5_flow *dev_flow,
2622 struct rte_flow_error *error)
2624 struct mlx5_priv *priv = dev->data->dev_private;
2625 struct mlx5_ibv_shared *sh = priv->sh;
2626 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2627 struct mlx5dv_dr_domain *ns;
2629 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2630 ns = sh->fdb_domain;
2631 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2636 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2637 /* Lookup a matching resource from cache. */
2638 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2639 if (resource->ft_type == cache_resource->ft_type &&
2640 resource->actions_num == cache_resource->actions_num &&
2641 resource->flags == cache_resource->flags &&
2642 !memcmp((const void *)resource->actions,
2643 (const void *)cache_resource->actions,
2644 (resource->actions_num *
2645 sizeof(resource->actions[0])))) {
2646 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2647 (void *)cache_resource,
2648 rte_atomic32_read(&cache_resource->refcnt));
2649 rte_atomic32_inc(&cache_resource->refcnt);
2650 dev_flow->dv.modify_hdr = cache_resource;
2654 /* Register new modify-header resource. */
2655 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2656 if (!cache_resource)
2657 return rte_flow_error_set(error, ENOMEM,
2658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2659 "cannot allocate resource memory");
2660 *cache_resource = *resource;
2661 cache_resource->verbs_action =
2662 mlx5_glue->dv_create_flow_action_modify_header
2663 (sh->ctx, cache_resource->ft_type,
2664 ns, cache_resource->flags,
2665 cache_resource->actions_num *
2666 sizeof(cache_resource->actions[0]),
2667 (uint64_t *)cache_resource->actions);
2668 if (!cache_resource->verbs_action) {
2669 rte_free(cache_resource);
2670 return rte_flow_error_set(error, ENOMEM,
2671 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2672 NULL, "cannot create action");
2674 rte_atomic32_init(&cache_resource->refcnt);
2675 rte_atomic32_inc(&cache_resource->refcnt);
2676 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2677 dev_flow->dv.modify_hdr = cache_resource;
2678 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2679 (void *)cache_resource,
2680 rte_atomic32_read(&cache_resource->refcnt));
2684 #define MLX5_CNT_CONTAINER_RESIZE 64
2687 * Get or create a flow counter.
2690 * Pointer to the Ethernet device structure.
2692 * Indicate if this counter is shared with other flows.
2694 * Counter identifier.
2697 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2699 static struct mlx5_flow_counter *
2700 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2703 struct mlx5_priv *priv = dev->data->dev_private;
2704 struct mlx5_flow_counter *cnt = NULL;
2705 struct mlx5_devx_obj *dcs = NULL;
2707 if (!priv->config.devx) {
2708 rte_errno = ENOTSUP;
2712 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2713 if (cnt->shared && cnt->id == id) {
2719 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2722 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2724 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2728 struct mlx5_flow_counter tmpl = {
2734 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2736 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2742 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2747 * Release a flow counter.
2750 * Pointer to the Ethernet device structure.
2751 * @param[in] counter
2752 * Pointer to the counter handler.
2755 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2756 struct mlx5_flow_counter *counter)
2758 struct mlx5_priv *priv = dev->data->dev_private;
2762 if (--counter->ref_cnt == 0) {
2763 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2764 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2770 * Query a devx flow counter.
2773 * Pointer to the Ethernet device structure.
2775 * Pointer to the flow counter.
2777 * The statistics value of packets.
2779 * The statistics value of bytes.
2782 * 0 on success, otherwise a negative errno value and rte_errno is set.
2785 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2786 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2789 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2794 * Get a pool by a counter.
2797 * Pointer to the counter.
2802 static struct mlx5_flow_counter_pool *
2803 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2806 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2807 return (struct mlx5_flow_counter_pool *)cnt - 1;
2813 * Get a pool by devx counter ID.
2816 * Pointer to the counter container.
2818 * The counter devx ID.
2821 * The counter pool pointer if exists, NULL otherwise,
2823 static struct mlx5_flow_counter_pool *
2824 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2826 struct mlx5_flow_counter_pool *pool;
2828 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2829 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2830 MLX5_COUNTERS_PER_POOL;
2832 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2839 * Allocate a new memory for the counter values wrapped by all the needed
2843 * Pointer to the Ethernet device structure.
2845 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2848 * The new memory management pointer on success, otherwise NULL and rte_errno
2851 static struct mlx5_counter_stats_mem_mng *
2852 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2854 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2855 (dev->data->dev_private))->sh;
2856 struct mlx5_devx_mkey_attr mkey_attr;
2857 struct mlx5_counter_stats_mem_mng *mem_mng;
2858 volatile struct flow_counter_stats *raw_data;
2859 int size = (sizeof(struct flow_counter_stats) *
2860 MLX5_COUNTERS_PER_POOL +
2861 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2862 sizeof(struct mlx5_counter_stats_mem_mng);
2863 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2870 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2871 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2872 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2873 IBV_ACCESS_LOCAL_WRITE);
2874 if (!mem_mng->umem) {
2879 mkey_attr.addr = (uintptr_t)mem;
2880 mkey_attr.size = size;
2881 mkey_attr.umem_id = mem_mng->umem->umem_id;
2882 mkey_attr.pd = sh->pdn;
2883 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2885 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2890 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2891 raw_data = (volatile struct flow_counter_stats *)mem;
2892 for (i = 0; i < raws_n; ++i) {
2893 mem_mng->raws[i].mem_mng = mem_mng;
2894 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2896 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2901 * Resize a counter container.
2904 * Pointer to the Ethernet device structure.
2906 * Whether the pool is for counter that was allocated by batch command.
2909 * The new container pointer on success, otherwise NULL and rte_errno is set.
2911 static struct mlx5_pools_container *
2912 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2914 struct mlx5_priv *priv = dev->data->dev_private;
2915 struct mlx5_pools_container *cont =
2916 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2917 struct mlx5_pools_container *new_cont =
2918 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2919 struct mlx5_counter_stats_mem_mng *mem_mng;
2920 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2921 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2924 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2925 /* The last resize still hasn't detected by the host thread. */
2929 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2930 if (!new_cont->pools) {
2935 memcpy(new_cont->pools, cont->pools, cont->n *
2936 sizeof(struct mlx5_flow_counter_pool *));
2937 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2938 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2940 rte_free(new_cont->pools);
2943 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2944 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2945 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2947 new_cont->n = resize;
2948 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2949 TAILQ_INIT(&new_cont->pool_list);
2950 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2951 new_cont->init_mem_mng = mem_mng;
2953 /* Flip the master container. */
2954 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2959 * Query a devx flow counter.
2962 * Pointer to the Ethernet device structure.
2964 * Pointer to the flow counter.
2966 * The statistics value of packets.
2968 * The statistics value of bytes.
2971 * 0 on success, otherwise a negative errno value and rte_errno is set.
2974 _flow_dv_query_count(struct rte_eth_dev *dev,
2975 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2978 struct mlx5_priv *priv = dev->data->dev_private;
2979 struct mlx5_flow_counter_pool *pool =
2980 flow_dv_counter_pool_get(cnt);
2981 int offset = cnt - &pool->counters_raw[0];
2983 if (priv->counter_fallback)
2984 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2986 rte_spinlock_lock(&pool->sl);
2988 * The single counters allocation may allocate smaller ID than the
2989 * current allocated in parallel to the host reading.
2990 * In this case the new counter values must be reported as 0.
2992 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2996 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2997 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2999 rte_spinlock_unlock(&pool->sl);
3004 * Create and initialize a new counter pool.
3007 * Pointer to the Ethernet device structure.
3009 * The devX counter handle.
3011 * Whether the pool is for counter that was allocated by batch command.
3014 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3016 static struct mlx5_flow_counter_pool *
3017 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3020 struct mlx5_priv *priv = dev->data->dev_private;
3021 struct mlx5_flow_counter_pool *pool;
3022 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3024 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3027 if (cont->n == n_valid) {
3028 cont = flow_dv_container_resize(dev, batch);
3032 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3033 sizeof(struct mlx5_flow_counter);
3034 pool = rte_calloc(__func__, 1, size, 0);
3039 pool->min_dcs = dcs;
3040 pool->raw = cont->init_mem_mng->raws + n_valid %
3041 MLX5_CNT_CONTAINER_RESIZE;
3042 pool->raw_hw = NULL;
3043 rte_spinlock_init(&pool->sl);
3045 * The generation of the new allocated counters in this pool is 0, 2 in
3046 * the pool generation makes all the counters valid for allocation.
3048 rte_atomic64_set(&pool->query_gen, 0x2);
3049 TAILQ_INIT(&pool->counters);
3050 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3051 cont->pools[n_valid] = pool;
3052 /* Pool initialization must be updated before host thread access. */
3054 rte_atomic16_add(&cont->n_valid, 1);
3059 * Prepare a new counter and/or a new counter pool.
3062 * Pointer to the Ethernet device structure.
3063 * @param[out] cnt_free
3064 * Where to put the pointer of a new counter.
3066 * Whether the pool is for counter that was allocated by batch command.
3069 * The free counter pool pointer and @p cnt_free is set on success,
3070 * NULL otherwise and rte_errno is set.
3072 static struct mlx5_flow_counter_pool *
3073 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3074 struct mlx5_flow_counter **cnt_free,
3077 struct mlx5_priv *priv = dev->data->dev_private;
3078 struct mlx5_flow_counter_pool *pool;
3079 struct mlx5_devx_obj *dcs = NULL;
3080 struct mlx5_flow_counter *cnt;
3084 /* bulk_bitmap must be 0 for single counter allocation. */
3085 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3088 pool = flow_dv_find_pool_by_id
3089 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3091 pool = flow_dv_pool_create(dev, dcs, batch);
3093 mlx5_devx_cmd_destroy(dcs);
3096 } else if (dcs->id < pool->min_dcs->id) {
3097 rte_atomic64_set(&pool->a64_dcs,
3098 (int64_t)(uintptr_t)dcs);
3100 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3101 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3106 /* bulk_bitmap is in 128 counters units. */
3107 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3108 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3110 rte_errno = ENODATA;
3113 pool = flow_dv_pool_create(dev, dcs, batch);
3115 mlx5_devx_cmd_destroy(dcs);
3118 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3119 cnt = &pool->counters_raw[i];
3121 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3123 *cnt_free = &pool->counters_raw[0];
3128 * Search for existed shared counter.
3131 * Pointer to the relevant counter pool container.
3133 * The shared counter ID to search.
3136 * NULL if not existed, otherwise pointer to the shared counter.
3138 static struct mlx5_flow_counter *
3139 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3142 static struct mlx5_flow_counter *cnt;
3143 struct mlx5_flow_counter_pool *pool;
3146 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3147 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3148 cnt = &pool->counters_raw[i];
3149 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3157 * Allocate a flow counter.
3160 * Pointer to the Ethernet device structure.
3162 * Indicate if this counter is shared with other flows.
3164 * Counter identifier.
3166 * Counter flow group.
3169 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3171 static struct mlx5_flow_counter *
3172 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3175 struct mlx5_priv *priv = dev->data->dev_private;
3176 struct mlx5_flow_counter_pool *pool = NULL;
3177 struct mlx5_flow_counter *cnt_free = NULL;
3179 * Currently group 0 flow counter cannot be assigned to a flow if it is
3180 * not the first one in the batch counter allocation, so it is better
3181 * to allocate counters one by one for these flows in a separate
3183 * A counter can be shared between different groups so need to take
3184 * shared counters from the single container.
3186 uint32_t batch = (group && !shared) ? 1 : 0;
3187 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3190 if (priv->counter_fallback)
3191 return flow_dv_counter_alloc_fallback(dev, shared, id);
3192 if (!priv->config.devx) {
3193 rte_errno = ENOTSUP;
3197 cnt_free = flow_dv_counter_shared_search(cont, id);
3199 if (cnt_free->ref_cnt + 1 == 0) {
3203 cnt_free->ref_cnt++;
3207 /* Pools which has a free counters are in the start. */
3208 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3210 * The free counter reset values must be updated between the
3211 * counter release to the counter allocation, so, at least one
3212 * query must be done in this time. ensure it by saving the
3213 * query generation in the release time.
3214 * The free list is sorted according to the generation - so if
3215 * the first one is not updated, all the others are not
3218 cnt_free = TAILQ_FIRST(&pool->counters);
3219 if (cnt_free && cnt_free->query_gen + 1 <
3220 rte_atomic64_read(&pool->query_gen))
3225 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3229 cnt_free->batch = batch;
3230 /* Create a DV counter action only in the first time usage. */
3231 if (!cnt_free->action) {
3233 struct mlx5_devx_obj *dcs;
3236 offset = cnt_free - &pool->counters_raw[0];
3237 dcs = pool->min_dcs;
3240 dcs = cnt_free->dcs;
3242 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3244 if (!cnt_free->action) {
3249 /* Update the counter reset values. */
3250 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3253 cnt_free->shared = shared;
3254 cnt_free->ref_cnt = 1;
3256 if (!priv->sh->cmng.query_thread_on)
3257 /* Start the asynchronous batch query by the host thread. */
3258 mlx5_set_query_alarm(priv->sh);
3259 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3260 if (TAILQ_EMPTY(&pool->counters)) {
3261 /* Move the pool to the end of the container pool list. */
3262 TAILQ_REMOVE(&cont->pool_list, pool, next);
3263 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3269 * Release a flow counter.
3272 * Pointer to the Ethernet device structure.
3273 * @param[in] counter
3274 * Pointer to the counter handler.
3277 flow_dv_counter_release(struct rte_eth_dev *dev,
3278 struct mlx5_flow_counter *counter)
3280 struct mlx5_priv *priv = dev->data->dev_private;
3284 if (priv->counter_fallback) {
3285 flow_dv_counter_release_fallback(dev, counter);
3288 if (--counter->ref_cnt == 0) {
3289 struct mlx5_flow_counter_pool *pool =
3290 flow_dv_counter_pool_get(counter);
3292 /* Put the counter in the end - the last updated one. */
3293 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3294 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3299 * Verify the @p attributes will be correctly understood by the NIC and store
3300 * them in the @p flow if everything is correct.
3303 * Pointer to dev struct.
3304 * @param[in] attributes
3305 * Pointer to flow attributes
3306 * @param[in] external
3307 * This flow rule is created by request external to PMD.
3309 * Pointer to error structure.
3312 * 0 on success, a negative errno value otherwise and rte_errno is set.
3315 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3316 const struct rte_flow_attr *attributes,
3317 bool external __rte_unused,
3318 struct rte_flow_error *error)
3320 struct mlx5_priv *priv = dev->data->dev_private;
3321 uint32_t priority_max = priv->config.flow_prio - 1;
3323 #ifndef HAVE_MLX5DV_DR
3324 if (attributes->group)
3325 return rte_flow_error_set(error, ENOTSUP,
3326 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3328 "groups are not supported");
3330 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3335 ret = mlx5_flow_group_to_table(attributes, external,
3340 if (table >= max_group)
3341 return rte_flow_error_set(error, EINVAL,
3342 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3343 "group index out of range");
3345 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3346 attributes->priority >= priority_max)
3347 return rte_flow_error_set(error, ENOTSUP,
3348 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3350 "priority out of range");
3351 if (attributes->transfer) {
3352 if (!priv->config.dv_esw_en)
3353 return rte_flow_error_set
3355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3356 "E-Switch dr is not supported");
3357 if (!(priv->representor || priv->master))
3358 return rte_flow_error_set
3359 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3360 NULL, "E-Switch configuration can only be"
3361 " done by a master or a representor device");
3362 if (attributes->egress)
3363 return rte_flow_error_set
3365 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3366 "egress is not supported");
3368 if (!(attributes->egress ^ attributes->ingress))
3369 return rte_flow_error_set(error, ENOTSUP,
3370 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3371 "must specify exactly one of "
3372 "ingress or egress");
3377 * Internal validation function. For validating both actions and items.
3380 * Pointer to the rte_eth_dev structure.
3382 * Pointer to the flow attributes.
3384 * Pointer to the list of items.
3385 * @param[in] actions
3386 * Pointer to the list of actions.
3387 * @param[in] external
3388 * This flow rule is created by request external to PMD.
3390 * Pointer to the error structure.
3393 * 0 on success, a negative errno value otherwise and rte_errno is set.
3396 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3397 const struct rte_flow_item items[],
3398 const struct rte_flow_action actions[],
3399 bool external, struct rte_flow_error *error)
3402 uint64_t action_flags = 0;
3403 uint64_t item_flags = 0;
3404 uint64_t last_item = 0;
3405 uint8_t next_protocol = 0xff;
3407 const struct rte_flow_item *gre_item = NULL;
3408 struct rte_flow_item_tcp nic_tcp_mask = {
3411 .src_port = RTE_BE16(UINT16_MAX),
3412 .dst_port = RTE_BE16(UINT16_MAX),
3418 ret = flow_dv_validate_attributes(dev, attr, external, error);
3421 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3422 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3423 int type = items->type;
3426 case RTE_FLOW_ITEM_TYPE_VOID:
3428 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3429 ret = flow_dv_validate_item_port_id
3430 (dev, items, attr, item_flags, error);
3433 last_item = MLX5_FLOW_ITEM_PORT_ID;
3435 case RTE_FLOW_ITEM_TYPE_ETH:
3436 ret = mlx5_flow_validate_item_eth(items, item_flags,
3440 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3441 MLX5_FLOW_LAYER_OUTER_L2;
3443 case RTE_FLOW_ITEM_TYPE_VLAN:
3444 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3448 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3449 MLX5_FLOW_LAYER_OUTER_VLAN;
3451 case RTE_FLOW_ITEM_TYPE_IPV4:
3452 mlx5_flow_tunnel_ip_check(items, next_protocol,
3453 &item_flags, &tunnel);
3454 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3458 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3459 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3460 if (items->mask != NULL &&
3461 ((const struct rte_flow_item_ipv4 *)
3462 items->mask)->hdr.next_proto_id) {
3464 ((const struct rte_flow_item_ipv4 *)
3465 (items->spec))->hdr.next_proto_id;
3467 ((const struct rte_flow_item_ipv4 *)
3468 (items->mask))->hdr.next_proto_id;
3470 /* Reset for inner layer. */
3471 next_protocol = 0xff;
3474 case RTE_FLOW_ITEM_TYPE_IPV6:
3475 mlx5_flow_tunnel_ip_check(items, next_protocol,
3476 &item_flags, &tunnel);
3477 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3481 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3482 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3483 if (items->mask != NULL &&
3484 ((const struct rte_flow_item_ipv6 *)
3485 items->mask)->hdr.proto) {
3487 ((const struct rte_flow_item_ipv6 *)
3488 items->spec)->hdr.proto;
3490 ((const struct rte_flow_item_ipv6 *)
3491 items->mask)->hdr.proto;
3493 /* Reset for inner layer. */
3494 next_protocol = 0xff;
3497 case RTE_FLOW_ITEM_TYPE_TCP:
3498 ret = mlx5_flow_validate_item_tcp
3505 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3506 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3508 case RTE_FLOW_ITEM_TYPE_UDP:
3509 ret = mlx5_flow_validate_item_udp(items, item_flags,
3514 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3515 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3517 case RTE_FLOW_ITEM_TYPE_GRE:
3518 ret = mlx5_flow_validate_item_gre(items, item_flags,
3519 next_protocol, error);
3523 last_item = MLX5_FLOW_LAYER_GRE;
3525 case RTE_FLOW_ITEM_TYPE_NVGRE:
3526 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3531 last_item = MLX5_FLOW_LAYER_NVGRE;
3533 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3534 ret = mlx5_flow_validate_item_gre_key
3535 (items, item_flags, gre_item, error);
3538 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3540 case RTE_FLOW_ITEM_TYPE_VXLAN:
3541 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3545 last_item = MLX5_FLOW_LAYER_VXLAN;
3547 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3548 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3553 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3555 case RTE_FLOW_ITEM_TYPE_GENEVE:
3556 ret = mlx5_flow_validate_item_geneve(items,
3561 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3563 case RTE_FLOW_ITEM_TYPE_MPLS:
3564 ret = mlx5_flow_validate_item_mpls(dev, items,
3569 last_item = MLX5_FLOW_LAYER_MPLS;
3571 case RTE_FLOW_ITEM_TYPE_META:
3572 ret = flow_dv_validate_item_meta(dev, items, attr,
3576 last_item = MLX5_FLOW_ITEM_METADATA;
3578 case RTE_FLOW_ITEM_TYPE_ICMP:
3579 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3584 last_item = MLX5_FLOW_LAYER_ICMP;
3586 case RTE_FLOW_ITEM_TYPE_ICMP6:
3587 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3592 last_item = MLX5_FLOW_LAYER_ICMP6;
3594 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3595 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3598 return rte_flow_error_set(error, ENOTSUP,
3599 RTE_FLOW_ERROR_TYPE_ITEM,
3600 NULL, "item not supported");
3602 item_flags |= last_item;
3604 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3605 int type = actions->type;
3606 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3607 return rte_flow_error_set(error, ENOTSUP,
3608 RTE_FLOW_ERROR_TYPE_ACTION,
3609 actions, "too many actions");
3611 case RTE_FLOW_ACTION_TYPE_VOID:
3613 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3614 ret = flow_dv_validate_action_port_id(dev,
3621 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3624 case RTE_FLOW_ACTION_TYPE_FLAG:
3625 ret = mlx5_flow_validate_action_flag(action_flags,
3629 action_flags |= MLX5_FLOW_ACTION_FLAG;
3632 case RTE_FLOW_ACTION_TYPE_MARK:
3633 ret = mlx5_flow_validate_action_mark(actions,
3638 action_flags |= MLX5_FLOW_ACTION_MARK;
3641 case RTE_FLOW_ACTION_TYPE_DROP:
3642 ret = mlx5_flow_validate_action_drop(action_flags,
3646 action_flags |= MLX5_FLOW_ACTION_DROP;
3649 case RTE_FLOW_ACTION_TYPE_QUEUE:
3650 ret = mlx5_flow_validate_action_queue(actions,
3655 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3658 case RTE_FLOW_ACTION_TYPE_RSS:
3659 ret = mlx5_flow_validate_action_rss(actions,
3665 action_flags |= MLX5_FLOW_ACTION_RSS;
3668 case RTE_FLOW_ACTION_TYPE_COUNT:
3669 ret = flow_dv_validate_action_count(dev, error);
3672 action_flags |= MLX5_FLOW_ACTION_COUNT;
3675 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3676 if (flow_dv_validate_action_pop_vlan(dev,
3682 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3685 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3686 ret = flow_dv_validate_action_push_vlan(action_flags,
3692 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3695 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3696 ret = flow_dv_validate_action_set_vlan_pcp
3697 (action_flags, actions, error);
3700 /* Count PCP with push_vlan command. */
3701 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3703 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3704 ret = flow_dv_validate_action_set_vlan_vid
3705 (item_flags, action_flags,
3709 /* Count VID with push_vlan command. */
3710 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3712 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3713 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3714 ret = flow_dv_validate_action_l2_encap(action_flags,
3719 action_flags |= actions->type ==
3720 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3721 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3722 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3725 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3726 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3727 ret = flow_dv_validate_action_l2_decap(action_flags,
3731 action_flags |= actions->type ==
3732 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3733 MLX5_FLOW_ACTION_VXLAN_DECAP :
3734 MLX5_FLOW_ACTION_NVGRE_DECAP;
3737 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3738 ret = flow_dv_validate_action_raw_encap(action_flags,
3743 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3746 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3747 ret = flow_dv_validate_action_raw_decap(action_flags,
3752 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3755 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3756 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3757 ret = flow_dv_validate_action_modify_mac(action_flags,
3763 /* Count all modify-header actions as one action. */
3764 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3766 action_flags |= actions->type ==
3767 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3768 MLX5_FLOW_ACTION_SET_MAC_SRC :
3769 MLX5_FLOW_ACTION_SET_MAC_DST;
3772 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3773 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3774 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3780 /* Count all modify-header actions as one action. */
3781 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3783 action_flags |= actions->type ==
3784 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3785 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3786 MLX5_FLOW_ACTION_SET_IPV4_DST;
3788 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3789 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3790 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3796 /* Count all modify-header actions as one action. */
3797 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3799 action_flags |= actions->type ==
3800 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3801 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3802 MLX5_FLOW_ACTION_SET_IPV6_DST;
3804 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3805 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3806 ret = flow_dv_validate_action_modify_tp(action_flags,
3812 /* Count all modify-header actions as one action. */
3813 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3815 action_flags |= actions->type ==
3816 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3817 MLX5_FLOW_ACTION_SET_TP_SRC :
3818 MLX5_FLOW_ACTION_SET_TP_DST;
3820 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3821 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3822 ret = flow_dv_validate_action_modify_ttl(action_flags,
3828 /* Count all modify-header actions as one action. */
3829 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3831 action_flags |= actions->type ==
3832 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3833 MLX5_FLOW_ACTION_SET_TTL :
3834 MLX5_FLOW_ACTION_DEC_TTL;
3836 case RTE_FLOW_ACTION_TYPE_JUMP:
3837 ret = flow_dv_validate_action_jump(actions,
3844 action_flags |= MLX5_FLOW_ACTION_JUMP;
3846 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3847 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3848 ret = flow_dv_validate_action_modify_tcp_seq
3855 /* Count all modify-header actions as one action. */
3856 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3858 action_flags |= actions->type ==
3859 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3860 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3861 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3863 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3864 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3865 ret = flow_dv_validate_action_modify_tcp_ack
3872 /* Count all modify-header actions as one action. */
3873 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3875 action_flags |= actions->type ==
3876 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3877 MLX5_FLOW_ACTION_INC_TCP_ACK :
3878 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3880 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
3883 return rte_flow_error_set(error, ENOTSUP,
3884 RTE_FLOW_ERROR_TYPE_ACTION,
3886 "action not supported");
3889 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3890 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3891 return rte_flow_error_set(error, ENOTSUP,
3892 RTE_FLOW_ERROR_TYPE_ACTION,
3894 "can't have vxlan and vlan"
3895 " actions in the same rule");
3896 /* Eswitch has few restrictions on using items and actions */
3897 if (attr->transfer) {
3898 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3899 return rte_flow_error_set(error, ENOTSUP,
3900 RTE_FLOW_ERROR_TYPE_ACTION,
3902 "unsupported action FLAG");
3903 if (action_flags & MLX5_FLOW_ACTION_MARK)
3904 return rte_flow_error_set(error, ENOTSUP,
3905 RTE_FLOW_ERROR_TYPE_ACTION,
3907 "unsupported action MARK");
3908 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3909 return rte_flow_error_set(error, ENOTSUP,
3910 RTE_FLOW_ERROR_TYPE_ACTION,
3912 "unsupported action QUEUE");
3913 if (action_flags & MLX5_FLOW_ACTION_RSS)
3914 return rte_flow_error_set(error, ENOTSUP,
3915 RTE_FLOW_ERROR_TYPE_ACTION,
3917 "unsupported action RSS");
3918 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3919 return rte_flow_error_set(error, EINVAL,
3920 RTE_FLOW_ERROR_TYPE_ACTION,
3922 "no fate action is found");
3924 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3925 return rte_flow_error_set(error, EINVAL,
3926 RTE_FLOW_ERROR_TYPE_ACTION,
3928 "no fate action is found");
3934 * Internal preparation function. Allocates the DV flow size,
3935 * this size is constant.
3938 * Pointer to the flow attributes.
3940 * Pointer to the list of items.
3941 * @param[in] actions
3942 * Pointer to the list of actions.
3944 * Pointer to the error structure.
3947 * Pointer to mlx5_flow object on success,
3948 * otherwise NULL and rte_errno is set.
3950 static struct mlx5_flow *
3951 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3952 const struct rte_flow_item items[] __rte_unused,
3953 const struct rte_flow_action actions[] __rte_unused,
3954 struct rte_flow_error *error)
3956 uint32_t size = sizeof(struct mlx5_flow);
3957 struct mlx5_flow *flow;
3959 flow = rte_calloc(__func__, 1, size, 0);
3961 rte_flow_error_set(error, ENOMEM,
3962 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3963 "not enough memory to create flow");
3966 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3972 * Sanity check for match mask and value. Similar to check_valid_spec() in
3973 * kernel driver. If unmasked bit is present in value, it returns failure.
3976 * pointer to match mask buffer.
3977 * @param match_value
3978 * pointer to match value buffer.
3981 * 0 if valid, -EINVAL otherwise.
3984 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3986 uint8_t *m = match_mask;
3987 uint8_t *v = match_value;
3990 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3993 "match_value differs from match_criteria"
3994 " %p[%u] != %p[%u]",
3995 match_value, i, match_mask, i);
4004 * Add Ethernet item to matcher and to the value.
4006 * @param[in, out] matcher
4008 * @param[in, out] key
4009 * Flow matcher value.
4011 * Flow pattern to translate.
4013 * Item is inner pattern.
4016 flow_dv_translate_item_eth(void *matcher, void *key,
4017 const struct rte_flow_item *item, int inner)
4019 const struct rte_flow_item_eth *eth_m = item->mask;
4020 const struct rte_flow_item_eth *eth_v = item->spec;
4021 const struct rte_flow_item_eth nic_mask = {
4022 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4023 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4024 .type = RTE_BE16(0xffff),
4036 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4038 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4040 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4042 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4044 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4045 ð_m->dst, sizeof(eth_m->dst));
4046 /* The value must be in the range of the mask. */
4047 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4048 for (i = 0; i < sizeof(eth_m->dst); ++i)
4049 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4050 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4051 ð_m->src, sizeof(eth_m->src));
4052 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4053 /* The value must be in the range of the mask. */
4054 for (i = 0; i < sizeof(eth_m->dst); ++i)
4055 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4056 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4057 rte_be_to_cpu_16(eth_m->type));
4058 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4059 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4063 * Add VLAN item to matcher and to the value.
4065 * @param[in, out] dev_flow
4067 * @param[in, out] matcher
4069 * @param[in, out] key
4070 * Flow matcher value.
4072 * Flow pattern to translate.
4074 * Item is inner pattern.
4077 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4078 void *matcher, void *key,
4079 const struct rte_flow_item *item,
4082 const struct rte_flow_item_vlan *vlan_m = item->mask;
4083 const struct rte_flow_item_vlan *vlan_v = item->spec;
4092 vlan_m = &rte_flow_item_vlan_mask;
4094 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4096 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4098 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4100 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4102 * This is workaround, masks are not supported,
4103 * and pre-validated.
4105 dev_flow->dv.vf_vlan.tag =
4106 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4108 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4109 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4110 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4111 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4112 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4113 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4114 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4115 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4116 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4117 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4118 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4119 rte_be_to_cpu_16(vlan_m->inner_type));
4120 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4121 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4125 * Add IPV4 item to matcher and to the value.
4127 * @param[in, out] matcher
4129 * @param[in, out] key
4130 * Flow matcher value.
4132 * Flow pattern to translate.
4134 * Item is inner pattern.
4136 * The group to insert the rule.
4139 flow_dv_translate_item_ipv4(void *matcher, void *key,
4140 const struct rte_flow_item *item,
4141 int inner, uint32_t group)
4143 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4144 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4145 const struct rte_flow_item_ipv4 nic_mask = {
4147 .src_addr = RTE_BE32(0xffffffff),
4148 .dst_addr = RTE_BE32(0xffffffff),
4149 .type_of_service = 0xff,
4150 .next_proto_id = 0xff,
4160 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4162 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4164 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4166 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4169 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4177 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4178 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4179 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4180 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4181 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4182 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4183 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4184 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4185 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4186 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4187 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4188 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4189 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4190 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4191 ipv4_m->hdr.type_of_service);
4192 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4193 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4194 ipv4_m->hdr.type_of_service >> 2);
4195 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4196 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4197 ipv4_m->hdr.next_proto_id);
4198 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4199 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4203 * Add IPV6 item to matcher and to the value.
4205 * @param[in, out] matcher
4207 * @param[in, out] key
4208 * Flow matcher value.
4210 * Flow pattern to translate.
4212 * Item is inner pattern.
4214 * The group to insert the rule.
4217 flow_dv_translate_item_ipv6(void *matcher, void *key,
4218 const struct rte_flow_item *item,
4219 int inner, uint32_t group)
4221 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4222 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4223 const struct rte_flow_item_ipv6 nic_mask = {
4226 "\xff\xff\xff\xff\xff\xff\xff\xff"
4227 "\xff\xff\xff\xff\xff\xff\xff\xff",
4229 "\xff\xff\xff\xff\xff\xff\xff\xff"
4230 "\xff\xff\xff\xff\xff\xff\xff\xff",
4231 .vtc_flow = RTE_BE32(0xffffffff),
4238 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4239 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4248 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4250 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4252 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4254 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4257 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4259 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4260 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4265 size = sizeof(ipv6_m->hdr.dst_addr);
4266 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4267 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4268 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4269 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4270 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4271 for (i = 0; i < size; ++i)
4272 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4273 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4274 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4275 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4276 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4277 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4278 for (i = 0; i < size; ++i)
4279 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4281 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4282 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4283 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4289 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4291 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4294 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4296 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4300 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4302 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4303 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4307 * Add TCP item to matcher and to the value.
4309 * @param[in, out] matcher
4311 * @param[in, out] key
4312 * Flow matcher value.
4314 * Flow pattern to translate.
4316 * Item is inner pattern.
4319 flow_dv_translate_item_tcp(void *matcher, void *key,
4320 const struct rte_flow_item *item,
4323 const struct rte_flow_item_tcp *tcp_m = item->mask;
4324 const struct rte_flow_item_tcp *tcp_v = item->spec;
4329 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4331 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4333 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4335 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4337 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4338 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4342 tcp_m = &rte_flow_item_tcp_mask;
4343 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4344 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4346 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4347 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4348 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4349 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4350 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4351 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4352 tcp_m->hdr.tcp_flags);
4353 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4354 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4358 * Add UDP item to matcher and to the value.
4360 * @param[in, out] matcher
4362 * @param[in, out] key
4363 * Flow matcher value.
4365 * Flow pattern to translate.
4367 * Item is inner pattern.
4370 flow_dv_translate_item_udp(void *matcher, void *key,
4371 const struct rte_flow_item *item,
4374 const struct rte_flow_item_udp *udp_m = item->mask;
4375 const struct rte_flow_item_udp *udp_v = item->spec;
4380 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4382 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4384 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4386 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4388 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4389 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4393 udp_m = &rte_flow_item_udp_mask;
4394 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4395 rte_be_to_cpu_16(udp_m->hdr.src_port));
4396 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4397 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4398 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4399 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4400 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4401 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4405 * Add GRE optional Key item to matcher and to the value.
4407 * @param[in, out] matcher
4409 * @param[in, out] key
4410 * Flow matcher value.
4412 * Flow pattern to translate.
4414 * Item is inner pattern.
4417 flow_dv_translate_item_gre_key(void *matcher, void *key,
4418 const struct rte_flow_item *item)
4420 const rte_be32_t *key_m = item->mask;
4421 const rte_be32_t *key_v = item->spec;
4422 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4423 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4424 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4429 key_m = &gre_key_default_mask;
4430 /* GRE K bit must be on and should already be validated */
4431 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4432 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4433 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4434 rte_be_to_cpu_32(*key_m) >> 8);
4435 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4436 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4437 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4438 rte_be_to_cpu_32(*key_m) & 0xFF);
4439 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4440 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4444 * Add GRE item to matcher and to the value.
4446 * @param[in, out] matcher
4448 * @param[in, out] key
4449 * Flow matcher value.
4451 * Flow pattern to translate.
4453 * Item is inner pattern.
4456 flow_dv_translate_item_gre(void *matcher, void *key,
4457 const struct rte_flow_item *item,
4460 const struct rte_flow_item_gre *gre_m = item->mask;
4461 const struct rte_flow_item_gre *gre_v = item->spec;
4464 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4465 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4472 uint16_t s_present:1;
4473 uint16_t k_present:1;
4474 uint16_t rsvd_bit1:1;
4475 uint16_t c_present:1;
4479 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4482 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4484 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4486 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4488 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4490 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4495 gre_m = &rte_flow_item_gre_mask;
4496 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4497 rte_be_to_cpu_16(gre_m->protocol));
4498 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4499 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4500 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4501 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4502 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4503 gre_crks_rsvd0_ver_m.c_present);
4504 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4505 gre_crks_rsvd0_ver_v.c_present &
4506 gre_crks_rsvd0_ver_m.c_present);
4507 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4508 gre_crks_rsvd0_ver_m.k_present);
4509 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4510 gre_crks_rsvd0_ver_v.k_present &
4511 gre_crks_rsvd0_ver_m.k_present);
4512 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4513 gre_crks_rsvd0_ver_m.s_present);
4514 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4515 gre_crks_rsvd0_ver_v.s_present &
4516 gre_crks_rsvd0_ver_m.s_present);
4520 * Add NVGRE item to matcher and to the value.
4522 * @param[in, out] matcher
4524 * @param[in, out] key
4525 * Flow matcher value.
4527 * Flow pattern to translate.
4529 * Item is inner pattern.
4532 flow_dv_translate_item_nvgre(void *matcher, void *key,
4533 const struct rte_flow_item *item,
4536 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4537 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4538 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4539 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4540 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4541 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4547 /* For NVGRE, GRE header fields must be set with defined values. */
4548 const struct rte_flow_item_gre gre_spec = {
4549 .c_rsvd0_ver = RTE_BE16(0x2000),
4550 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4552 const struct rte_flow_item_gre gre_mask = {
4553 .c_rsvd0_ver = RTE_BE16(0xB000),
4554 .protocol = RTE_BE16(UINT16_MAX),
4556 const struct rte_flow_item gre_item = {
4561 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4565 nvgre_m = &rte_flow_item_nvgre_mask;
4566 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4567 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4568 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4569 memcpy(gre_key_m, tni_flow_id_m, size);
4570 for (i = 0; i < size; ++i)
4571 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4575 * Add VXLAN item to matcher and to the value.
4577 * @param[in, out] matcher
4579 * @param[in, out] key
4580 * Flow matcher value.
4582 * Flow pattern to translate.
4584 * Item is inner pattern.
4587 flow_dv_translate_item_vxlan(void *matcher, void *key,
4588 const struct rte_flow_item *item,
4591 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4592 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4595 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4596 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4604 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4606 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4608 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4610 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4612 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4613 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4614 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4615 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4621 vxlan_m = &rte_flow_item_vxlan_mask;
4622 size = sizeof(vxlan_m->vni);
4623 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4624 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4625 memcpy(vni_m, vxlan_m->vni, size);
4626 for (i = 0; i < size; ++i)
4627 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4631 * Add Geneve item to matcher and to the value.
4633 * @param[in, out] matcher
4635 * @param[in, out] key
4636 * Flow matcher value.
4638 * Flow pattern to translate.
4640 * Item is inner pattern.
4644 flow_dv_translate_item_geneve(void *matcher, void *key,
4645 const struct rte_flow_item *item, int inner)
4647 const struct rte_flow_item_geneve *geneve_m = item->mask;
4648 const struct rte_flow_item_geneve *geneve_v = item->spec;
4651 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4652 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4661 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4663 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4667 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4669 dport = MLX5_UDP_PORT_GENEVE;
4670 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4671 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4672 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4677 geneve_m = &rte_flow_item_geneve_mask;
4678 size = sizeof(geneve_m->vni);
4679 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4680 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4681 memcpy(vni_m, geneve_m->vni, size);
4682 for (i = 0; i < size; ++i)
4683 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4684 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4685 rte_be_to_cpu_16(geneve_m->protocol));
4686 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4687 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4688 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4689 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4690 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4691 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4692 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4693 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4694 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4695 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4696 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4697 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4698 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4702 * Add MPLS item to matcher and to the value.
4704 * @param[in, out] matcher
4706 * @param[in, out] key
4707 * Flow matcher value.
4709 * Flow pattern to translate.
4710 * @param[in] prev_layer
4711 * The protocol layer indicated in previous item.
4713 * Item is inner pattern.
4716 flow_dv_translate_item_mpls(void *matcher, void *key,
4717 const struct rte_flow_item *item,
4718 uint64_t prev_layer,
4721 const uint32_t *in_mpls_m = item->mask;
4722 const uint32_t *in_mpls_v = item->spec;
4723 uint32_t *out_mpls_m = 0;
4724 uint32_t *out_mpls_v = 0;
4725 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4726 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4727 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4729 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4730 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4731 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4733 switch (prev_layer) {
4734 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4735 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4737 MLX5_UDP_PORT_MPLS);
4739 case MLX5_FLOW_LAYER_GRE:
4740 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4741 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4742 RTE_ETHER_TYPE_MPLS);
4745 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4753 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4754 switch (prev_layer) {
4755 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4757 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4758 outer_first_mpls_over_udp);
4760 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4761 outer_first_mpls_over_udp);
4763 case MLX5_FLOW_LAYER_GRE:
4765 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4766 outer_first_mpls_over_gre);
4768 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4769 outer_first_mpls_over_gre);
4772 /* Inner MPLS not over GRE is not supported. */
4775 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4779 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4785 if (out_mpls_m && out_mpls_v) {
4786 *out_mpls_m = *in_mpls_m;
4787 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4792 * Add META item to matcher
4794 * @param[in, out] matcher
4796 * @param[in, out] key
4797 * Flow matcher value.
4799 * Flow pattern to translate.
4801 * Item is inner pattern.
4804 flow_dv_translate_item_meta(void *matcher, void *key,
4805 const struct rte_flow_item *item)
4807 const struct rte_flow_item_meta *meta_m;
4808 const struct rte_flow_item_meta *meta_v;
4810 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4812 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4814 meta_m = (const void *)item->mask;
4816 meta_m = &rte_flow_item_meta_mask;
4817 meta_v = (const void *)item->spec;
4819 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4820 rte_be_to_cpu_32(meta_m->data));
4821 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4822 rte_be_to_cpu_32(meta_v->data & meta_m->data));
4827 * Add vport metadata Reg C0 item to matcher
4829 * @param[in, out] matcher
4831 * @param[in, out] key
4832 * Flow matcher value.
4834 * Flow pattern to translate.
4837 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4838 uint32_t value, uint32_t mask)
4841 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4843 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4845 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4846 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4850 * Add tag item to matcher
4852 * @param[in, out] matcher
4854 * @param[in, out] key
4855 * Flow matcher value.
4857 * Flow pattern to translate.
4860 flow_dv_translate_item_tag(void *matcher, void *key,
4861 const struct rte_flow_item *item)
4864 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4866 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4867 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
4868 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
4869 enum modify_reg reg = tag_v->id;
4870 rte_be32_t value = tag_v->data;
4871 rte_be32_t mask = tag_m->data;
4875 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4876 rte_be_to_cpu_32(mask));
4877 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4878 rte_be_to_cpu_32(value));
4881 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
4882 rte_be_to_cpu_32(mask));
4883 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
4884 rte_be_to_cpu_32(value));
4887 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
4888 rte_be_to_cpu_32(mask));
4889 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
4890 rte_be_to_cpu_32(value));
4893 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
4894 rte_be_to_cpu_32(mask));
4895 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
4896 rte_be_to_cpu_32(value));
4899 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
4900 rte_be_to_cpu_32(mask));
4901 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
4902 rte_be_to_cpu_32(value));
4905 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
4906 rte_be_to_cpu_32(mask));
4907 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
4908 rte_be_to_cpu_32(value));
4911 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
4912 rte_be_to_cpu_32(mask));
4913 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
4914 rte_be_to_cpu_32(value));
4917 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
4918 rte_be_to_cpu_32(mask));
4919 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
4920 rte_be_to_cpu_32(value));
4923 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
4924 rte_be_to_cpu_32(mask));
4925 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
4926 rte_be_to_cpu_32(value));
4929 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
4930 rte_be_to_cpu_32(mask));
4931 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
4932 rte_be_to_cpu_32(value));
4938 * Add source vport match to the specified matcher.
4940 * @param[in, out] matcher
4942 * @param[in, out] key
4943 * Flow matcher value.
4945 * Source vport value to match
4950 flow_dv_translate_item_source_vport(void *matcher, void *key,
4951 int16_t port, uint16_t mask)
4953 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4954 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4956 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4957 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4961 * Translate port-id item to eswitch match on port-id.
4964 * The devich to configure through.
4965 * @param[in, out] matcher
4967 * @param[in, out] key
4968 * Flow matcher value.
4970 * Flow pattern to translate.
4973 * 0 on success, a negative errno value otherwise.
4976 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4977 void *key, const struct rte_flow_item *item)
4979 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4980 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4981 struct mlx5_priv *priv;
4984 mask = pid_m ? pid_m->id : 0xffff;
4985 id = pid_v ? pid_v->id : dev->data->port_id;
4986 priv = mlx5_port_to_eswitch_info(id);
4989 /* Translate to vport field or to metadata, depending on mode. */
4990 if (priv->vport_meta_mask)
4991 flow_dv_translate_item_meta_vport(matcher, key,
4992 priv->vport_meta_tag,
4993 priv->vport_meta_mask);
4995 flow_dv_translate_item_source_vport(matcher, key,
4996 priv->vport_id, mask);
5001 * Add ICMP6 item to matcher and to the value.
5003 * @param[in, out] matcher
5005 * @param[in, out] key
5006 * Flow matcher value.
5008 * Flow pattern to translate.
5010 * Item is inner pattern.
5013 flow_dv_translate_item_icmp6(void *matcher, void *key,
5014 const struct rte_flow_item *item,
5017 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5018 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5021 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5023 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5025 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5027 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5029 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5031 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5033 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5034 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5038 icmp6_m = &rte_flow_item_icmp6_mask;
5039 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5040 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5041 icmp6_v->type & icmp6_m->type);
5042 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5043 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5044 icmp6_v->code & icmp6_m->code);
5048 * Add ICMP item to matcher and to the value.
5050 * @param[in, out] matcher
5052 * @param[in, out] key
5053 * Flow matcher value.
5055 * Flow pattern to translate.
5057 * Item is inner pattern.
5060 flow_dv_translate_item_icmp(void *matcher, void *key,
5061 const struct rte_flow_item *item,
5064 const struct rte_flow_item_icmp *icmp_m = item->mask;
5065 const struct rte_flow_item_icmp *icmp_v = item->spec;
5068 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5070 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5072 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5074 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5076 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5078 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5080 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5081 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5085 icmp_m = &rte_flow_item_icmp_mask;
5086 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5087 icmp_m->hdr.icmp_type);
5088 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5089 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5090 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5091 icmp_m->hdr.icmp_code);
5092 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5093 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5096 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5098 #define HEADER_IS_ZERO(match_criteria, headers) \
5099 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5100 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5103 * Calculate flow matcher enable bitmap.
5105 * @param match_criteria
5106 * Pointer to flow matcher criteria.
5109 * Bitmap of enabled fields.
5112 flow_dv_matcher_enable(uint32_t *match_criteria)
5114 uint8_t match_criteria_enable;
5116 match_criteria_enable =
5117 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5118 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5119 match_criteria_enable |=
5120 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5121 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5122 match_criteria_enable |=
5123 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5124 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5125 match_criteria_enable |=
5126 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5127 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5128 match_criteria_enable |=
5129 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5130 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5131 return match_criteria_enable;
5138 * @param dev[in, out]
5139 * Pointer to rte_eth_dev structure.
5140 * @param[in] table_id
5143 * Direction of the table.
5144 * @param[in] transfer
5145 * E-Switch or NIC flow.
5147 * pointer to error structure.
5150 * Returns tables resource based on the index, NULL in case of failed.
5152 static struct mlx5_flow_tbl_resource *
5153 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5154 uint32_t table_id, uint8_t egress,
5156 struct rte_flow_error *error)
5158 struct mlx5_priv *priv = dev->data->dev_private;
5159 struct mlx5_ibv_shared *sh = priv->sh;
5160 struct mlx5_flow_tbl_resource *tbl;
5162 #ifdef HAVE_MLX5DV_DR
5164 tbl = &sh->fdb_tbl[table_id];
5166 tbl->obj = mlx5_glue->dr_create_flow_tbl
5167 (sh->fdb_domain, table_id);
5168 } else if (egress) {
5169 tbl = &sh->tx_tbl[table_id];
5171 tbl->obj = mlx5_glue->dr_create_flow_tbl
5172 (sh->tx_domain, table_id);
5174 tbl = &sh->rx_tbl[table_id];
5176 tbl->obj = mlx5_glue->dr_create_flow_tbl
5177 (sh->rx_domain, table_id);
5180 rte_flow_error_set(error, ENOMEM,
5181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5182 NULL, "cannot create table");
5185 rte_atomic32_inc(&tbl->refcnt);
5191 return &sh->fdb_tbl[table_id];
5193 return &sh->tx_tbl[table_id];
5195 return &sh->rx_tbl[table_id];
5200 * Release a flow table.
5203 * Table resource to be released.
5206 * Returns 0 if table was released, else return 1;
5209 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5213 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5214 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5222 * Register the flow matcher.
5224 * @param dev[in, out]
5225 * Pointer to rte_eth_dev structure.
5226 * @param[in, out] matcher
5227 * Pointer to flow matcher.
5228 * @parm[in, out] dev_flow
5229 * Pointer to the dev_flow.
5231 * pointer to error structure.
5234 * 0 on success otherwise -errno and errno is set.
5237 flow_dv_matcher_register(struct rte_eth_dev *dev,
5238 struct mlx5_flow_dv_matcher *matcher,
5239 struct mlx5_flow *dev_flow,
5240 struct rte_flow_error *error)
5242 struct mlx5_priv *priv = dev->data->dev_private;
5243 struct mlx5_ibv_shared *sh = priv->sh;
5244 struct mlx5_flow_dv_matcher *cache_matcher;
5245 struct mlx5dv_flow_matcher_attr dv_attr = {
5246 .type = IBV_FLOW_ATTR_NORMAL,
5247 .match_mask = (void *)&matcher->mask,
5249 struct mlx5_flow_tbl_resource *tbl = NULL;
5251 /* Lookup from cache. */
5252 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5253 if (matcher->crc == cache_matcher->crc &&
5254 matcher->priority == cache_matcher->priority &&
5255 matcher->egress == cache_matcher->egress &&
5256 matcher->group == cache_matcher->group &&
5257 matcher->transfer == cache_matcher->transfer &&
5258 !memcmp((const void *)matcher->mask.buf,
5259 (const void *)cache_matcher->mask.buf,
5260 cache_matcher->mask.size)) {
5262 "priority %hd use %s matcher %p: refcnt %d++",
5263 cache_matcher->priority,
5264 cache_matcher->egress ? "tx" : "rx",
5265 (void *)cache_matcher,
5266 rte_atomic32_read(&cache_matcher->refcnt));
5267 rte_atomic32_inc(&cache_matcher->refcnt);
5268 dev_flow->dv.matcher = cache_matcher;
5272 /* Register new matcher. */
5273 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5275 return rte_flow_error_set(error, ENOMEM,
5276 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5277 "cannot allocate matcher memory");
5278 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5279 matcher->egress, matcher->transfer,
5282 rte_free(cache_matcher);
5283 return rte_flow_error_set(error, ENOMEM,
5284 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5285 NULL, "cannot create table");
5287 *cache_matcher = *matcher;
5288 dv_attr.match_criteria_enable =
5289 flow_dv_matcher_enable(cache_matcher->mask.buf);
5290 dv_attr.priority = matcher->priority;
5291 if (matcher->egress)
5292 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5293 cache_matcher->matcher_object =
5294 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5295 if (!cache_matcher->matcher_object) {
5296 rte_free(cache_matcher);
5297 #ifdef HAVE_MLX5DV_DR
5298 flow_dv_tbl_resource_release(tbl);
5300 return rte_flow_error_set(error, ENOMEM,
5301 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5302 NULL, "cannot create matcher");
5304 rte_atomic32_inc(&cache_matcher->refcnt);
5305 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5306 dev_flow->dv.matcher = cache_matcher;
5307 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5308 cache_matcher->priority,
5309 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5310 rte_atomic32_read(&cache_matcher->refcnt));
5311 rte_atomic32_inc(&tbl->refcnt);
5316 * Find existing tag resource or create and register a new one.
5318 * @param dev[in, out]
5319 * Pointer to rte_eth_dev structure.
5320 * @param[in, out] resource
5321 * Pointer to tag resource.
5322 * @parm[in, out] dev_flow
5323 * Pointer to the dev_flow.
5325 * pointer to error structure.
5328 * 0 on success otherwise -errno and errno is set.
5331 flow_dv_tag_resource_register
5332 (struct rte_eth_dev *dev,
5333 struct mlx5_flow_dv_tag_resource *resource,
5334 struct mlx5_flow *dev_flow,
5335 struct rte_flow_error *error)
5337 struct mlx5_priv *priv = dev->data->dev_private;
5338 struct mlx5_ibv_shared *sh = priv->sh;
5339 struct mlx5_flow_dv_tag_resource *cache_resource;
5341 /* Lookup a matching resource from cache. */
5342 LIST_FOREACH(cache_resource, &sh->tags, next) {
5343 if (resource->tag == cache_resource->tag) {
5344 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5345 (void *)cache_resource,
5346 rte_atomic32_read(&cache_resource->refcnt));
5347 rte_atomic32_inc(&cache_resource->refcnt);
5348 dev_flow->flow->tag_resource = cache_resource;
5352 /* Register new resource. */
5353 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5354 if (!cache_resource)
5355 return rte_flow_error_set(error, ENOMEM,
5356 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5357 "cannot allocate resource memory");
5358 *cache_resource = *resource;
5359 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5361 if (!cache_resource->action) {
5362 rte_free(cache_resource);
5363 return rte_flow_error_set(error, ENOMEM,
5364 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5365 NULL, "cannot create action");
5367 rte_atomic32_init(&cache_resource->refcnt);
5368 rte_atomic32_inc(&cache_resource->refcnt);
5369 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5370 dev_flow->flow->tag_resource = cache_resource;
5371 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5372 (void *)cache_resource,
5373 rte_atomic32_read(&cache_resource->refcnt));
5381 * Pointer to Ethernet device.
5383 * Pointer to mlx5_flow.
5386 * 1 while a reference on it exists, 0 when freed.
5389 flow_dv_tag_release(struct rte_eth_dev *dev,
5390 struct mlx5_flow_dv_tag_resource *tag)
5393 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5394 dev->data->port_id, (void *)tag,
5395 rte_atomic32_read(&tag->refcnt));
5396 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5397 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5398 LIST_REMOVE(tag, next);
5399 DRV_LOG(DEBUG, "port %u tag %p: removed",
5400 dev->data->port_id, (void *)tag);
5408 * Translate port ID action to vport.
5411 * Pointer to rte_eth_dev structure.
5413 * Pointer to the port ID action.
5414 * @param[out] dst_port_id
5415 * The target port ID.
5417 * Pointer to the error structure.
5420 * 0 on success, a negative errno value otherwise and rte_errno is set.
5423 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5424 const struct rte_flow_action *action,
5425 uint32_t *dst_port_id,
5426 struct rte_flow_error *error)
5429 struct mlx5_priv *priv;
5430 const struct rte_flow_action_port_id *conf =
5431 (const struct rte_flow_action_port_id *)action->conf;
5433 port = conf->original ? dev->data->port_id : conf->id;
5434 priv = mlx5_port_to_eswitch_info(port);
5436 return rte_flow_error_set(error, -rte_errno,
5437 RTE_FLOW_ERROR_TYPE_ACTION,
5439 "No eswitch info was found for port");
5440 if (priv->vport_meta_mask)
5441 *dst_port_id = priv->vport_meta_tag;
5443 *dst_port_id = priv->vport_id;
5448 * Add Tx queue matcher
5451 * Pointer to the dev struct.
5452 * @param[in, out] matcher
5454 * @param[in, out] key
5455 * Flow matcher value.
5457 * Flow pattern to translate.
5459 * Item is inner pattern.
5462 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5463 void *matcher, void *key,
5464 const struct rte_flow_item *item)
5466 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5467 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5469 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5471 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5472 struct mlx5_txq_ctrl *txq;
5476 queue_m = (const void *)item->mask;
5479 queue_v = (const void *)item->spec;
5482 txq = mlx5_txq_get(dev, queue_v->queue);
5485 queue = txq->obj->sq->id;
5486 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5487 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5488 queue & queue_m->queue);
5489 mlx5_txq_release(dev, queue_v->queue);
5493 * Fill the flow with DV spec.
5496 * Pointer to rte_eth_dev structure.
5497 * @param[in, out] dev_flow
5498 * Pointer to the sub flow.
5500 * Pointer to the flow attributes.
5502 * Pointer to the list of items.
5503 * @param[in] actions
5504 * Pointer to the list of actions.
5506 * Pointer to the error structure.
5509 * 0 on success, a negative errno value otherwise and rte_errno is set.
5512 flow_dv_translate(struct rte_eth_dev *dev,
5513 struct mlx5_flow *dev_flow,
5514 const struct rte_flow_attr *attr,
5515 const struct rte_flow_item items[],
5516 const struct rte_flow_action actions[],
5517 struct rte_flow_error *error)
5519 struct mlx5_priv *priv = dev->data->dev_private;
5520 struct rte_flow *flow = dev_flow->flow;
5521 uint64_t item_flags = 0;
5522 uint64_t last_item = 0;
5523 uint64_t action_flags = 0;
5524 uint64_t priority = attr->priority;
5525 struct mlx5_flow_dv_matcher matcher = {
5527 .size = sizeof(matcher.mask.buf),
5531 bool actions_end = false;
5532 struct mlx5_flow_dv_modify_hdr_resource res = {
5533 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5534 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5536 union flow_dv_attr flow_attr = { .attr = 0 };
5537 struct mlx5_flow_dv_tag_resource tag_resource;
5538 uint32_t modify_action_position = UINT32_MAX;
5539 void *match_mask = matcher.mask.buf;
5540 void *match_value = dev_flow->dv.value.buf;
5541 uint8_t next_protocol = 0xff;
5542 struct rte_vlan_hdr vlan = { 0 };
5546 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5550 flow->group = table;
5552 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5553 if (priority == MLX5_FLOW_PRIO_RSVD)
5554 priority = priv->config.flow_prio - 1;
5555 for (; !actions_end ; actions++) {
5556 const struct rte_flow_action_queue *queue;
5557 const struct rte_flow_action_rss *rss;
5558 const struct rte_flow_action *action = actions;
5559 const struct rte_flow_action_count *count = action->conf;
5560 const uint8_t *rss_key;
5561 const struct rte_flow_action_jump *jump_data;
5562 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5563 struct mlx5_flow_tbl_resource *tbl;
5564 uint32_t port_id = 0;
5565 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5566 int action_type = actions->type;
5567 const struct rte_flow_action *found_action = NULL;
5569 switch (action_type) {
5570 case RTE_FLOW_ACTION_TYPE_VOID:
5572 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5573 if (flow_dv_translate_action_port_id(dev, action,
5576 port_id_resource.port_id = port_id;
5577 if (flow_dv_port_id_action_resource_register
5578 (dev, &port_id_resource, dev_flow, error))
5580 dev_flow->dv.actions[actions_n++] =
5581 dev_flow->dv.port_id_action->action;
5582 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5584 case RTE_FLOW_ACTION_TYPE_FLAG:
5586 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5587 if (!flow->tag_resource)
5588 if (flow_dv_tag_resource_register
5589 (dev, &tag_resource, dev_flow, error))
5591 dev_flow->dv.actions[actions_n++] =
5592 flow->tag_resource->action;
5593 action_flags |= MLX5_FLOW_ACTION_FLAG;
5595 case RTE_FLOW_ACTION_TYPE_MARK:
5596 tag_resource.tag = mlx5_flow_mark_set
5597 (((const struct rte_flow_action_mark *)
5598 (actions->conf))->id);
5599 if (!flow->tag_resource)
5600 if (flow_dv_tag_resource_register
5601 (dev, &tag_resource, dev_flow, error))
5603 dev_flow->dv.actions[actions_n++] =
5604 flow->tag_resource->action;
5605 action_flags |= MLX5_FLOW_ACTION_MARK;
5607 case RTE_FLOW_ACTION_TYPE_DROP:
5608 action_flags |= MLX5_FLOW_ACTION_DROP;
5610 case RTE_FLOW_ACTION_TYPE_QUEUE:
5611 queue = actions->conf;
5612 flow->rss.queue_num = 1;
5613 (*flow->queue)[0] = queue->index;
5614 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5616 case RTE_FLOW_ACTION_TYPE_RSS:
5617 rss = actions->conf;
5619 memcpy((*flow->queue), rss->queue,
5620 rss->queue_num * sizeof(uint16_t));
5621 flow->rss.queue_num = rss->queue_num;
5622 /* NULL RSS key indicates default RSS key. */
5623 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5624 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5625 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5626 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5627 flow->rss.level = rss->level;
5628 action_flags |= MLX5_FLOW_ACTION_RSS;
5630 case RTE_FLOW_ACTION_TYPE_COUNT:
5631 if (!priv->config.devx) {
5632 rte_errno = ENOTSUP;
5635 flow->counter = flow_dv_counter_alloc(dev,
5639 if (flow->counter == NULL)
5641 dev_flow->dv.actions[actions_n++] =
5642 flow->counter->action;
5643 action_flags |= MLX5_FLOW_ACTION_COUNT;
5646 if (rte_errno == ENOTSUP)
5647 return rte_flow_error_set
5649 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5651 "count action not supported");
5653 return rte_flow_error_set
5655 RTE_FLOW_ERROR_TYPE_ACTION,
5657 "cannot create counter"
5660 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5661 dev_flow->dv.actions[actions_n++] =
5662 priv->sh->pop_vlan_action;
5663 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5665 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5666 flow_dev_get_vlan_info_from_items(items, &vlan);
5667 vlan.eth_proto = rte_be_to_cpu_16
5668 ((((const struct rte_flow_action_of_push_vlan *)
5669 actions->conf)->ethertype));
5670 found_action = mlx5_flow_find_action
5672 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5674 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5675 found_action = mlx5_flow_find_action
5677 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5679 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5680 if (flow_dv_create_action_push_vlan
5681 (dev, attr, &vlan, dev_flow, error))
5683 dev_flow->dv.actions[actions_n++] =
5684 dev_flow->dv.push_vlan_res->action;
5685 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5687 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5688 /* of_vlan_push action handled this action */
5689 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5691 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5692 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5694 flow_dev_get_vlan_info_from_items(items, &vlan);
5695 mlx5_update_vlan_vid_pcp(actions, &vlan);
5696 /* If no VLAN push - this is a modify header action */
5697 if (flow_dv_convert_action_modify_vlan_vid
5698 (&res, actions, error))
5700 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5702 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5703 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5704 if (flow_dv_create_action_l2_encap(dev, actions,
5709 dev_flow->dv.actions[actions_n++] =
5710 dev_flow->dv.encap_decap->verbs_action;
5711 action_flags |= actions->type ==
5712 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5713 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5714 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5716 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5717 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5718 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5722 dev_flow->dv.actions[actions_n++] =
5723 dev_flow->dv.encap_decap->verbs_action;
5724 action_flags |= actions->type ==
5725 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5726 MLX5_FLOW_ACTION_VXLAN_DECAP :
5727 MLX5_FLOW_ACTION_NVGRE_DECAP;
5729 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5730 /* Handle encap with preceding decap. */
5731 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5732 if (flow_dv_create_action_raw_encap
5733 (dev, actions, dev_flow, attr, error))
5735 dev_flow->dv.actions[actions_n++] =
5736 dev_flow->dv.encap_decap->verbs_action;
5738 /* Handle encap without preceding decap. */
5739 if (flow_dv_create_action_l2_encap
5740 (dev, actions, dev_flow, attr->transfer,
5743 dev_flow->dv.actions[actions_n++] =
5744 dev_flow->dv.encap_decap->verbs_action;
5746 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5748 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5749 /* Check if this decap is followed by encap. */
5750 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5751 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5754 /* Handle decap only if it isn't followed by encap. */
5755 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5756 if (flow_dv_create_action_l2_decap
5757 (dev, dev_flow, attr->transfer, error))
5759 dev_flow->dv.actions[actions_n++] =
5760 dev_flow->dv.encap_decap->verbs_action;
5762 /* If decap is followed by encap, handle it at encap. */
5763 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5765 case RTE_FLOW_ACTION_TYPE_JUMP:
5766 jump_data = action->conf;
5767 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5768 jump_data->group, &table,
5772 tbl = flow_dv_tbl_resource_get(dev, table,
5774 attr->transfer, error);
5776 return rte_flow_error_set
5778 RTE_FLOW_ERROR_TYPE_ACTION,
5780 "cannot create jump action.");
5781 jump_tbl_resource.tbl = tbl;
5782 if (flow_dv_jump_tbl_resource_register
5783 (dev, &jump_tbl_resource, dev_flow, error)) {
5784 flow_dv_tbl_resource_release(tbl);
5785 return rte_flow_error_set
5787 RTE_FLOW_ERROR_TYPE_ACTION,
5789 "cannot create jump action.");
5791 dev_flow->dv.actions[actions_n++] =
5792 dev_flow->dv.jump->action;
5793 action_flags |= MLX5_FLOW_ACTION_JUMP;
5795 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5796 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5797 if (flow_dv_convert_action_modify_mac(&res, actions,
5800 action_flags |= actions->type ==
5801 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5802 MLX5_FLOW_ACTION_SET_MAC_SRC :
5803 MLX5_FLOW_ACTION_SET_MAC_DST;
5805 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5806 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5807 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5810 action_flags |= actions->type ==
5811 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5812 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5813 MLX5_FLOW_ACTION_SET_IPV4_DST;
5815 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5816 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5817 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5820 action_flags |= actions->type ==
5821 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5822 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5823 MLX5_FLOW_ACTION_SET_IPV6_DST;
5825 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5826 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5827 if (flow_dv_convert_action_modify_tp(&res, actions,
5831 action_flags |= actions->type ==
5832 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5833 MLX5_FLOW_ACTION_SET_TP_SRC :
5834 MLX5_FLOW_ACTION_SET_TP_DST;
5836 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5837 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5841 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5843 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5844 if (flow_dv_convert_action_modify_ttl(&res, actions,
5848 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5850 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5851 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5852 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5855 action_flags |= actions->type ==
5856 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5857 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5858 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5861 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5862 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5863 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5866 action_flags |= actions->type ==
5867 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5868 MLX5_FLOW_ACTION_INC_TCP_ACK :
5869 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5871 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5872 if (flow_dv_convert_action_set_reg(&res, actions,
5875 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5877 case RTE_FLOW_ACTION_TYPE_END:
5879 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5880 /* create modify action if needed. */
5881 if (flow_dv_modify_hdr_resource_register
5886 dev_flow->dv.actions[modify_action_position] =
5887 dev_flow->dv.modify_hdr->verbs_action;
5893 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5894 modify_action_position == UINT32_MAX)
5895 modify_action_position = actions_n++;
5897 dev_flow->dv.actions_n = actions_n;
5898 dev_flow->actions = action_flags;
5899 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5900 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5901 int item_type = items->type;
5903 switch (item_type) {
5904 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5905 flow_dv_translate_item_port_id(dev, match_mask,
5906 match_value, items);
5907 last_item = MLX5_FLOW_ITEM_PORT_ID;
5909 case RTE_FLOW_ITEM_TYPE_ETH:
5910 flow_dv_translate_item_eth(match_mask, match_value,
5912 matcher.priority = MLX5_PRIORITY_MAP_L2;
5913 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5914 MLX5_FLOW_LAYER_OUTER_L2;
5916 case RTE_FLOW_ITEM_TYPE_VLAN:
5917 flow_dv_translate_item_vlan(dev_flow,
5918 match_mask, match_value,
5920 matcher.priority = MLX5_PRIORITY_MAP_L2;
5921 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5922 MLX5_FLOW_LAYER_INNER_VLAN) :
5923 (MLX5_FLOW_LAYER_OUTER_L2 |
5924 MLX5_FLOW_LAYER_OUTER_VLAN);
5926 case RTE_FLOW_ITEM_TYPE_IPV4:
5927 mlx5_flow_tunnel_ip_check(items, next_protocol,
5928 &item_flags, &tunnel);
5929 flow_dv_translate_item_ipv4(match_mask, match_value,
5930 items, tunnel, flow->group);
5931 matcher.priority = MLX5_PRIORITY_MAP_L3;
5932 dev_flow->dv.hash_fields |=
5933 mlx5_flow_hashfields_adjust
5935 MLX5_IPV4_LAYER_TYPES,
5936 MLX5_IPV4_IBV_RX_HASH);
5937 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5938 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5939 if (items->mask != NULL &&
5940 ((const struct rte_flow_item_ipv4 *)
5941 items->mask)->hdr.next_proto_id) {
5943 ((const struct rte_flow_item_ipv4 *)
5944 (items->spec))->hdr.next_proto_id;
5946 ((const struct rte_flow_item_ipv4 *)
5947 (items->mask))->hdr.next_proto_id;
5949 /* Reset for inner layer. */
5950 next_protocol = 0xff;
5953 case RTE_FLOW_ITEM_TYPE_IPV6:
5954 mlx5_flow_tunnel_ip_check(items, next_protocol,
5955 &item_flags, &tunnel);
5956 flow_dv_translate_item_ipv6(match_mask, match_value,
5957 items, tunnel, flow->group);
5958 matcher.priority = MLX5_PRIORITY_MAP_L3;
5959 dev_flow->dv.hash_fields |=
5960 mlx5_flow_hashfields_adjust
5962 MLX5_IPV6_LAYER_TYPES,
5963 MLX5_IPV6_IBV_RX_HASH);
5964 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5965 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5966 if (items->mask != NULL &&
5967 ((const struct rte_flow_item_ipv6 *)
5968 items->mask)->hdr.proto) {
5970 ((const struct rte_flow_item_ipv6 *)
5971 items->spec)->hdr.proto;
5973 ((const struct rte_flow_item_ipv6 *)
5974 items->mask)->hdr.proto;
5976 /* Reset for inner layer. */
5977 next_protocol = 0xff;
5980 case RTE_FLOW_ITEM_TYPE_TCP:
5981 flow_dv_translate_item_tcp(match_mask, match_value,
5983 matcher.priority = MLX5_PRIORITY_MAP_L4;
5984 dev_flow->dv.hash_fields |=
5985 mlx5_flow_hashfields_adjust
5986 (dev_flow, tunnel, ETH_RSS_TCP,
5987 IBV_RX_HASH_SRC_PORT_TCP |
5988 IBV_RX_HASH_DST_PORT_TCP);
5989 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5990 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5992 case RTE_FLOW_ITEM_TYPE_UDP:
5993 flow_dv_translate_item_udp(match_mask, match_value,
5995 matcher.priority = MLX5_PRIORITY_MAP_L4;
5996 dev_flow->dv.hash_fields |=
5997 mlx5_flow_hashfields_adjust
5998 (dev_flow, tunnel, ETH_RSS_UDP,
5999 IBV_RX_HASH_SRC_PORT_UDP |
6000 IBV_RX_HASH_DST_PORT_UDP);
6001 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6002 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6004 case RTE_FLOW_ITEM_TYPE_GRE:
6005 flow_dv_translate_item_gre(match_mask, match_value,
6007 last_item = MLX5_FLOW_LAYER_GRE;
6009 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6010 flow_dv_translate_item_gre_key(match_mask,
6011 match_value, items);
6012 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6014 case RTE_FLOW_ITEM_TYPE_NVGRE:
6015 flow_dv_translate_item_nvgre(match_mask, match_value,
6017 last_item = MLX5_FLOW_LAYER_GRE;
6019 case RTE_FLOW_ITEM_TYPE_VXLAN:
6020 flow_dv_translate_item_vxlan(match_mask, match_value,
6022 last_item = MLX5_FLOW_LAYER_VXLAN;
6024 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6025 flow_dv_translate_item_vxlan(match_mask, match_value,
6027 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6029 case RTE_FLOW_ITEM_TYPE_GENEVE:
6030 flow_dv_translate_item_geneve(match_mask, match_value,
6032 last_item = MLX5_FLOW_LAYER_GENEVE;
6034 case RTE_FLOW_ITEM_TYPE_MPLS:
6035 flow_dv_translate_item_mpls(match_mask, match_value,
6036 items, last_item, tunnel);
6037 last_item = MLX5_FLOW_LAYER_MPLS;
6039 case RTE_FLOW_ITEM_TYPE_META:
6040 flow_dv_translate_item_meta(match_mask, match_value,
6042 last_item = MLX5_FLOW_ITEM_METADATA;
6044 case RTE_FLOW_ITEM_TYPE_ICMP:
6045 flow_dv_translate_item_icmp(match_mask, match_value,
6047 last_item = MLX5_FLOW_LAYER_ICMP;
6049 case RTE_FLOW_ITEM_TYPE_ICMP6:
6050 flow_dv_translate_item_icmp6(match_mask, match_value,
6052 last_item = MLX5_FLOW_LAYER_ICMP6;
6054 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6055 flow_dv_translate_item_tag(match_mask, match_value,
6057 last_item = MLX5_FLOW_ITEM_TAG;
6059 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6060 flow_dv_translate_item_tx_queue(dev, match_mask,
6063 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6068 item_flags |= last_item;
6071 * In case of ingress traffic when E-Switch mode is enabled,
6072 * we have two cases where we need to set the source port manually.
6073 * The first one, is in case of Nic steering rule, and the second is
6074 * E-Switch rule where no port_id item was found. In both cases
6075 * the source port is set according the current port in use.
6077 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6078 (priv->representor || priv->master)) {
6079 if (flow_dv_translate_item_port_id(dev, match_mask,
6083 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6084 dev_flow->dv.value.buf));
6085 dev_flow->layers = item_flags;
6086 /* Register matcher. */
6087 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6089 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6091 matcher.egress = attr->egress;
6092 matcher.group = flow->group;
6093 matcher.transfer = attr->transfer;
6094 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6100 * Apply the flow to the NIC.
6103 * Pointer to the Ethernet device structure.
6104 * @param[in, out] flow
6105 * Pointer to flow structure.
6107 * Pointer to error structure.
6110 * 0 on success, a negative errno value otherwise and rte_errno is set.
6113 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6114 struct rte_flow_error *error)
6116 struct mlx5_flow_dv *dv;
6117 struct mlx5_flow *dev_flow;
6118 struct mlx5_priv *priv = dev->data->dev_private;
6122 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6125 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6126 if (flow->transfer) {
6127 dv->actions[n++] = priv->sh->esw_drop_action;
6129 dv->hrxq = mlx5_hrxq_drop_new(dev);
6133 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6135 "cannot get drop hash queue");
6138 dv->actions[n++] = dv->hrxq->action;
6140 } else if (dev_flow->actions &
6141 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6142 struct mlx5_hrxq *hrxq;
6144 hrxq = mlx5_hrxq_get(dev, flow->key,
6145 MLX5_RSS_HASH_KEY_LEN,
6148 flow->rss.queue_num);
6150 hrxq = mlx5_hrxq_new
6151 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6152 dv->hash_fields, (*flow->queue),
6153 flow->rss.queue_num,
6154 !!(dev_flow->layers &
6155 MLX5_FLOW_LAYER_TUNNEL));
6160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6161 "cannot get hash queue");
6165 dv->actions[n++] = dv->hrxq->action;
6168 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6169 (void *)&dv->value, n,
6172 rte_flow_error_set(error, errno,
6173 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6175 "hardware refuses to create flow");
6178 if (priv->vmwa_context &&
6179 dev_flow->dv.vf_vlan.tag &&
6180 !dev_flow->dv.vf_vlan.created) {
6182 * The rule contains the VLAN pattern.
6183 * For VF we are going to create VLAN
6184 * interface to make hypervisor set correct
6185 * e-Switch vport context.
6187 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6192 err = rte_errno; /* Save rte_errno before cleanup. */
6193 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6194 struct mlx5_flow_dv *dv = &dev_flow->dv;
6196 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6197 mlx5_hrxq_drop_release(dev);
6199 mlx5_hrxq_release(dev, dv->hrxq);
6202 if (dev_flow->dv.vf_vlan.tag &&
6203 dev_flow->dv.vf_vlan.created)
6204 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6206 rte_errno = err; /* Restore rte_errno. */
6211 * Release the flow matcher.
6214 * Pointer to Ethernet device.
6216 * Pointer to mlx5_flow.
6219 * 1 while a reference on it exists, 0 when freed.
6222 flow_dv_matcher_release(struct rte_eth_dev *dev,
6223 struct mlx5_flow *flow)
6225 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6226 struct mlx5_priv *priv = dev->data->dev_private;
6227 struct mlx5_ibv_shared *sh = priv->sh;
6228 struct mlx5_flow_tbl_resource *tbl;
6230 assert(matcher->matcher_object);
6231 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6232 dev->data->port_id, (void *)matcher,
6233 rte_atomic32_read(&matcher->refcnt));
6234 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6235 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6236 (matcher->matcher_object));
6237 LIST_REMOVE(matcher, next);
6238 if (matcher->egress)
6239 tbl = &sh->tx_tbl[matcher->group];
6241 tbl = &sh->rx_tbl[matcher->group];
6242 flow_dv_tbl_resource_release(tbl);
6244 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6245 dev->data->port_id, (void *)matcher);
6252 * Release an encap/decap resource.
6255 * Pointer to mlx5_flow.
6258 * 1 while a reference on it exists, 0 when freed.
6261 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6263 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6264 flow->dv.encap_decap;
6266 assert(cache_resource->verbs_action);
6267 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6268 (void *)cache_resource,
6269 rte_atomic32_read(&cache_resource->refcnt));
6270 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6271 claim_zero(mlx5_glue->destroy_flow_action
6272 (cache_resource->verbs_action));
6273 LIST_REMOVE(cache_resource, next);
6274 rte_free(cache_resource);
6275 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6276 (void *)cache_resource);
6283 * Release an jump to table action resource.
6286 * Pointer to mlx5_flow.
6289 * 1 while a reference on it exists, 0 when freed.
6292 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6294 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6297 assert(cache_resource->action);
6298 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6299 (void *)cache_resource,
6300 rte_atomic32_read(&cache_resource->refcnt));
6301 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6302 claim_zero(mlx5_glue->destroy_flow_action
6303 (cache_resource->action));
6304 LIST_REMOVE(cache_resource, next);
6305 flow_dv_tbl_resource_release(cache_resource->tbl);
6306 rte_free(cache_resource);
6307 DRV_LOG(DEBUG, "jump table resource %p: removed",
6308 (void *)cache_resource);
6315 * Release a modify-header resource.
6318 * Pointer to mlx5_flow.
6321 * 1 while a reference on it exists, 0 when freed.
6324 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6326 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6327 flow->dv.modify_hdr;
6329 assert(cache_resource->verbs_action);
6330 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6331 (void *)cache_resource,
6332 rte_atomic32_read(&cache_resource->refcnt));
6333 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6334 claim_zero(mlx5_glue->destroy_flow_action
6335 (cache_resource->verbs_action));
6336 LIST_REMOVE(cache_resource, next);
6337 rte_free(cache_resource);
6338 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6339 (void *)cache_resource);
6346 * Release port ID action resource.
6349 * Pointer to mlx5_flow.
6352 * 1 while a reference on it exists, 0 when freed.
6355 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6357 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6358 flow->dv.port_id_action;
6360 assert(cache_resource->action);
6361 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6362 (void *)cache_resource,
6363 rte_atomic32_read(&cache_resource->refcnt));
6364 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6365 claim_zero(mlx5_glue->destroy_flow_action
6366 (cache_resource->action));
6367 LIST_REMOVE(cache_resource, next);
6368 rte_free(cache_resource);
6369 DRV_LOG(DEBUG, "port id action resource %p: removed",
6370 (void *)cache_resource);
6377 * Release push vlan action resource.
6380 * Pointer to mlx5_flow.
6383 * 1 while a reference on it exists, 0 when freed.
6386 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6388 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6389 flow->dv.push_vlan_res;
6391 assert(cache_resource->action);
6392 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6393 (void *)cache_resource,
6394 rte_atomic32_read(&cache_resource->refcnt));
6395 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6396 claim_zero(mlx5_glue->destroy_flow_action
6397 (cache_resource->action));
6398 LIST_REMOVE(cache_resource, next);
6399 rte_free(cache_resource);
6400 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6401 (void *)cache_resource);
6408 * Remove the flow from the NIC but keeps it in memory.
6411 * Pointer to Ethernet device.
6412 * @param[in, out] flow
6413 * Pointer to flow structure.
6416 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6418 struct mlx5_flow_dv *dv;
6419 struct mlx5_flow *dev_flow;
6423 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6426 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6430 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6431 mlx5_hrxq_drop_release(dev);
6433 mlx5_hrxq_release(dev, dv->hrxq);
6436 if (dev_flow->dv.vf_vlan.tag &&
6437 dev_flow->dv.vf_vlan.created)
6438 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6443 * Remove the flow from the NIC and the memory.
6446 * Pointer to the Ethernet device structure.
6447 * @param[in, out] flow
6448 * Pointer to flow structure.
6451 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6453 struct mlx5_flow *dev_flow;
6457 flow_dv_remove(dev, flow);
6458 if (flow->counter) {
6459 flow_dv_counter_release(dev, flow->counter);
6460 flow->counter = NULL;
6462 if (flow->tag_resource) {
6463 flow_dv_tag_release(dev, flow->tag_resource);
6464 flow->tag_resource = NULL;
6466 while (!LIST_EMPTY(&flow->dev_flows)) {
6467 dev_flow = LIST_FIRST(&flow->dev_flows);
6468 LIST_REMOVE(dev_flow, next);
6469 if (dev_flow->dv.matcher)
6470 flow_dv_matcher_release(dev, dev_flow);
6471 if (dev_flow->dv.encap_decap)
6472 flow_dv_encap_decap_resource_release(dev_flow);
6473 if (dev_flow->dv.modify_hdr)
6474 flow_dv_modify_hdr_resource_release(dev_flow);
6475 if (dev_flow->dv.jump)
6476 flow_dv_jump_tbl_resource_release(dev_flow);
6477 if (dev_flow->dv.port_id_action)
6478 flow_dv_port_id_action_resource_release(dev_flow);
6479 if (dev_flow->dv.push_vlan_res)
6480 flow_dv_push_vlan_action_resource_release(dev_flow);
6486 * Query a dv flow rule for its statistics via devx.
6489 * Pointer to Ethernet device.
6491 * Pointer to the sub flow.
6493 * data retrieved by the query.
6495 * Perform verbose error reporting if not NULL.
6498 * 0 on success, a negative errno value otherwise and rte_errno is set.
6501 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6502 void *data, struct rte_flow_error *error)
6504 struct mlx5_priv *priv = dev->data->dev_private;
6505 struct rte_flow_query_count *qc = data;
6507 if (!priv->config.devx)
6508 return rte_flow_error_set(error, ENOTSUP,
6509 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6511 "counters are not supported");
6512 if (flow->counter) {
6513 uint64_t pkts, bytes;
6514 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6518 return rte_flow_error_set(error, -err,
6519 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6520 NULL, "cannot read counters");
6523 qc->hits = pkts - flow->counter->hits;
6524 qc->bytes = bytes - flow->counter->bytes;
6526 flow->counter->hits = pkts;
6527 flow->counter->bytes = bytes;
6531 return rte_flow_error_set(error, EINVAL,
6532 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6534 "counters are not available");
6540 * @see rte_flow_query()
6544 flow_dv_query(struct rte_eth_dev *dev,
6545 struct rte_flow *flow __rte_unused,
6546 const struct rte_flow_action *actions __rte_unused,
6547 void *data __rte_unused,
6548 struct rte_flow_error *error __rte_unused)
6552 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6553 switch (actions->type) {
6554 case RTE_FLOW_ACTION_TYPE_VOID:
6556 case RTE_FLOW_ACTION_TYPE_COUNT:
6557 ret = flow_dv_query_count(dev, flow, data, error);
6560 return rte_flow_error_set(error, ENOTSUP,
6561 RTE_FLOW_ERROR_TYPE_ACTION,
6563 "action not supported");
6570 * Mutex-protected thunk to flow_dv_translate().
6573 flow_d_translate(struct rte_eth_dev *dev,
6574 struct mlx5_flow *dev_flow,
6575 const struct rte_flow_attr *attr,
6576 const struct rte_flow_item items[],
6577 const struct rte_flow_action actions[],
6578 struct rte_flow_error *error)
6582 flow_d_shared_lock(dev);
6583 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6584 flow_d_shared_unlock(dev);
6589 * Mutex-protected thunk to flow_dv_apply().
6592 flow_d_apply(struct rte_eth_dev *dev,
6593 struct rte_flow *flow,
6594 struct rte_flow_error *error)
6598 flow_d_shared_lock(dev);
6599 ret = flow_dv_apply(dev, flow, error);
6600 flow_d_shared_unlock(dev);
6605 * Mutex-protected thunk to flow_dv_remove().
6608 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6610 flow_d_shared_lock(dev);
6611 flow_dv_remove(dev, flow);
6612 flow_d_shared_unlock(dev);
6616 * Mutex-protected thunk to flow_dv_destroy().
6619 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6621 flow_d_shared_lock(dev);
6622 flow_dv_destroy(dev, flow);
6623 flow_d_shared_unlock(dev);
6626 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6627 .validate = flow_dv_validate,
6628 .prepare = flow_dv_prepare,
6629 .translate = flow_d_translate,
6630 .apply = flow_d_apply,
6631 .remove = flow_d_remove,
6632 .destroy = flow_d_destroy,
6633 .query = flow_dv_query,
6636 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */