1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
58 sizeof(struct rte_flow_item_ipv4))
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 * Initialize flow attributes structure according to flow items' types.
81 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
82 * mode. For tunnel mode, the items to be modified are the outermost ones.
85 * Pointer to item specification.
87 * Pointer to flow attributes structure.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
95 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
96 uint8_t next_protocol = 0xff;
99 case RTE_FLOW_ITEM_TYPE_GRE:
100 case RTE_FLOW_ITEM_TYPE_NVGRE:
101 case RTE_FLOW_ITEM_TYPE_VXLAN:
102 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
103 case RTE_FLOW_ITEM_TYPE_GENEVE:
104 case RTE_FLOW_ITEM_TYPE_MPLS:
108 case RTE_FLOW_ITEM_TYPE_IPV4:
111 if (item->mask != NULL &&
112 ((const struct rte_flow_item_ipv4 *)
113 item->mask)->hdr.next_proto_id)
115 ((const struct rte_flow_item_ipv4 *)
116 (item->spec))->hdr.next_proto_id &
117 ((const struct rte_flow_item_ipv4 *)
118 (item->mask))->hdr.next_proto_id;
119 if ((next_protocol == IPPROTO_IPIP ||
120 next_protocol == IPPROTO_IPV6) && tunnel_decap)
123 case RTE_FLOW_ITEM_TYPE_IPV6:
126 if (item->mask != NULL &&
127 ((const struct rte_flow_item_ipv6 *)
128 item->mask)->hdr.proto)
130 ((const struct rte_flow_item_ipv6 *)
131 (item->spec))->hdr.proto &
132 ((const struct rte_flow_item_ipv6 *)
133 (item->mask))->hdr.proto;
134 if ((next_protocol == IPPROTO_IPIP ||
135 next_protocol == IPPROTO_IPV6) && tunnel_decap)
138 case RTE_FLOW_ITEM_TYPE_UDP:
142 case RTE_FLOW_ITEM_TYPE_TCP:
154 * Convert rte_mtr_color to mlx5 color.
163 rte_col_2_mlx5_col(enum rte_color rcol)
166 case RTE_COLOR_GREEN:
167 return MLX5_FLOW_COLOR_GREEN;
168 case RTE_COLOR_YELLOW:
169 return MLX5_FLOW_COLOR_YELLOW;
171 return MLX5_FLOW_COLOR_RED;
175 return MLX5_FLOW_COLOR_UNDEFINED;
178 struct field_modify_info {
179 uint32_t size; /* Size of field in protocol header, in bytes. */
180 uint32_t offset; /* Offset of field in protocol header, in bytes. */
181 enum mlx5_modification_field id;
184 struct field_modify_info modify_eth[] = {
185 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
186 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
187 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
188 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
192 struct field_modify_info modify_vlan_out_first_vid[] = {
193 /* Size in bits !!! */
194 {12, 0, MLX5_MODI_OUT_FIRST_VID},
198 struct field_modify_info modify_ipv4[] = {
199 {1, 1, MLX5_MODI_OUT_IP_DSCP},
200 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
201 {4, 12, MLX5_MODI_OUT_SIPV4},
202 {4, 16, MLX5_MODI_OUT_DIPV4},
206 struct field_modify_info modify_ipv6[] = {
207 {1, 0, MLX5_MODI_OUT_IP_DSCP},
208 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
209 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
210 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
211 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
212 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
213 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
214 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
215 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
216 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
220 struct field_modify_info modify_udp[] = {
221 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
222 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
226 struct field_modify_info modify_tcp[] = {
227 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
228 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
229 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
230 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
235 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
236 uint8_t next_protocol, uint64_t *item_flags,
239 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
240 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
241 if (next_protocol == IPPROTO_IPIP) {
242 *item_flags |= MLX5_FLOW_LAYER_IPIP;
245 if (next_protocol == IPPROTO_IPV6) {
246 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
252 * Acquire the synchronizing object to protect multithreaded access
253 * to shared dv context. Lock occurs only if context is actually
254 * shared, i.e. we have multiport IB device and representors are
258 * Pointer to the rte_eth_dev structure.
261 flow_dv_shared_lock(struct rte_eth_dev *dev)
263 struct mlx5_priv *priv = dev->data->dev_private;
264 struct mlx5_ibv_shared *sh = priv->sh;
266 if (sh->dv_refcnt > 1) {
269 ret = pthread_mutex_lock(&sh->dv_mutex);
276 flow_dv_shared_unlock(struct rte_eth_dev *dev)
278 struct mlx5_priv *priv = dev->data->dev_private;
279 struct mlx5_ibv_shared *sh = priv->sh;
281 if (sh->dv_refcnt > 1) {
284 ret = pthread_mutex_unlock(&sh->dv_mutex);
290 /* Update VLAN's VID/PCP based on input rte_flow_action.
293 * Pointer to struct rte_flow_action.
295 * Pointer to struct rte_vlan_hdr.
298 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
299 struct rte_vlan_hdr *vlan)
302 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
304 ((const struct rte_flow_action_of_set_vlan_pcp *)
305 action->conf)->vlan_pcp;
306 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
307 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
308 vlan->vlan_tci |= vlan_tci;
309 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
310 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
311 vlan->vlan_tci |= rte_be_to_cpu_16
312 (((const struct rte_flow_action_of_set_vlan_vid *)
313 action->conf)->vlan_vid);
318 * Fetch 1, 2, 3 or 4 byte field from the byte array
319 * and return as unsigned integer in host-endian format.
322 * Pointer to data array.
324 * Size of field to extract.
327 * converted field in host endian format.
329 static inline uint32_t
330 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
339 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
342 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
343 ret = (ret << 8) | *(data + sizeof(uint16_t));
346 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
357 * Convert modify-header action to DV specification.
359 * Data length of each action is determined by provided field description
360 * and the item mask. Data bit offset and width of each action is determined
361 * by provided item mask.
364 * Pointer to item specification.
366 * Pointer to field modification information.
367 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
368 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
369 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
371 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
372 * Negative offset value sets the same offset as source offset.
373 * size field is ignored, value is taken from source field.
374 * @param[in,out] resource
375 * Pointer to the modify-header resource.
377 * Type of modification.
379 * Pointer to the error structure.
382 * 0 on success, a negative errno value otherwise and rte_errno is set.
385 flow_dv_convert_modify_action(struct rte_flow_item *item,
386 struct field_modify_info *field,
387 struct field_modify_info *dcopy,
388 struct mlx5_flow_dv_modify_hdr_resource *resource,
389 uint32_t type, struct rte_flow_error *error)
391 uint32_t i = resource->actions_num;
392 struct mlx5_modification_cmd *actions = resource->actions;
395 * The item and mask are provided in big-endian format.
396 * The fields should be presented as in big-endian format either.
397 * Mask must be always present, it defines the actual field width.
399 MLX5_ASSERT(item->mask);
400 MLX5_ASSERT(field->size);
407 if (i >= MLX5_MAX_MODIFY_NUM)
408 return rte_flow_error_set(error, EINVAL,
409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
410 "too many items to modify");
411 /* Fetch variable byte size mask from the array. */
412 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
413 field->offset, field->size);
418 /* Deduce actual data width in bits from mask value. */
419 off_b = rte_bsf32(mask);
420 size_b = sizeof(uint32_t) * CHAR_BIT -
421 off_b - __builtin_clz(mask);
423 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
424 actions[i] = (struct mlx5_modification_cmd) {
430 /* Convert entire record to expected big-endian format. */
431 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
432 if (type == MLX5_MODIFICATION_TYPE_COPY) {
434 actions[i].dst_field = dcopy->id;
435 actions[i].dst_offset =
436 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
437 /* Convert entire record to big-endian format. */
438 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
440 MLX5_ASSERT(item->spec);
441 data = flow_dv_fetch_field((const uint8_t *)item->spec +
442 field->offset, field->size);
443 /* Shift out the trailing masked bits from data. */
444 data = (data & mask) >> off_b;
445 actions[i].data1 = rte_cpu_to_be_32(data);
449 } while (field->size);
450 if (resource->actions_num == i)
451 return rte_flow_error_set(error, EINVAL,
452 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
453 "invalid modification flow item");
454 resource->actions_num = i;
459 * Convert modify-header set IPv4 address action to DV specification.
461 * @param[in,out] resource
462 * Pointer to the modify-header resource.
464 * Pointer to action specification.
466 * Pointer to the error structure.
469 * 0 on success, a negative errno value otherwise and rte_errno is set.
472 flow_dv_convert_action_modify_ipv4
473 (struct mlx5_flow_dv_modify_hdr_resource *resource,
474 const struct rte_flow_action *action,
475 struct rte_flow_error *error)
477 const struct rte_flow_action_set_ipv4 *conf =
478 (const struct rte_flow_action_set_ipv4 *)(action->conf);
479 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
480 struct rte_flow_item_ipv4 ipv4;
481 struct rte_flow_item_ipv4 ipv4_mask;
483 memset(&ipv4, 0, sizeof(ipv4));
484 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
486 ipv4.hdr.src_addr = conf->ipv4_addr;
487 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
489 ipv4.hdr.dst_addr = conf->ipv4_addr;
490 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
493 item.mask = &ipv4_mask;
494 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
495 MLX5_MODIFICATION_TYPE_SET, error);
499 * Convert modify-header set IPv6 address action to DV specification.
501 * @param[in,out] resource
502 * Pointer to the modify-header resource.
504 * Pointer to action specification.
506 * Pointer to the error structure.
509 * 0 on success, a negative errno value otherwise and rte_errno is set.
512 flow_dv_convert_action_modify_ipv6
513 (struct mlx5_flow_dv_modify_hdr_resource *resource,
514 const struct rte_flow_action *action,
515 struct rte_flow_error *error)
517 const struct rte_flow_action_set_ipv6 *conf =
518 (const struct rte_flow_action_set_ipv6 *)(action->conf);
519 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
520 struct rte_flow_item_ipv6 ipv6;
521 struct rte_flow_item_ipv6 ipv6_mask;
523 memset(&ipv6, 0, sizeof(ipv6));
524 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
525 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
526 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
527 sizeof(ipv6.hdr.src_addr));
528 memcpy(&ipv6_mask.hdr.src_addr,
529 &rte_flow_item_ipv6_mask.hdr.src_addr,
530 sizeof(ipv6.hdr.src_addr));
532 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
533 sizeof(ipv6.hdr.dst_addr));
534 memcpy(&ipv6_mask.hdr.dst_addr,
535 &rte_flow_item_ipv6_mask.hdr.dst_addr,
536 sizeof(ipv6.hdr.dst_addr));
539 item.mask = &ipv6_mask;
540 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
541 MLX5_MODIFICATION_TYPE_SET, error);
545 * Convert modify-header set MAC address action to DV specification.
547 * @param[in,out] resource
548 * Pointer to the modify-header resource.
550 * Pointer to action specification.
552 * Pointer to the error structure.
555 * 0 on success, a negative errno value otherwise and rte_errno is set.
558 flow_dv_convert_action_modify_mac
559 (struct mlx5_flow_dv_modify_hdr_resource *resource,
560 const struct rte_flow_action *action,
561 struct rte_flow_error *error)
563 const struct rte_flow_action_set_mac *conf =
564 (const struct rte_flow_action_set_mac *)(action->conf);
565 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
566 struct rte_flow_item_eth eth;
567 struct rte_flow_item_eth eth_mask;
569 memset(ð, 0, sizeof(eth));
570 memset(ð_mask, 0, sizeof(eth_mask));
571 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
572 memcpy(ð.src.addr_bytes, &conf->mac_addr,
573 sizeof(eth.src.addr_bytes));
574 memcpy(ð_mask.src.addr_bytes,
575 &rte_flow_item_eth_mask.src.addr_bytes,
576 sizeof(eth_mask.src.addr_bytes));
578 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
579 sizeof(eth.dst.addr_bytes));
580 memcpy(ð_mask.dst.addr_bytes,
581 &rte_flow_item_eth_mask.dst.addr_bytes,
582 sizeof(eth_mask.dst.addr_bytes));
585 item.mask = ð_mask;
586 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
587 MLX5_MODIFICATION_TYPE_SET, error);
591 * Convert modify-header set VLAN VID action to DV specification.
593 * @param[in,out] resource
594 * Pointer to the modify-header resource.
596 * Pointer to action specification.
598 * Pointer to the error structure.
601 * 0 on success, a negative errno value otherwise and rte_errno is set.
604 flow_dv_convert_action_modify_vlan_vid
605 (struct mlx5_flow_dv_modify_hdr_resource *resource,
606 const struct rte_flow_action *action,
607 struct rte_flow_error *error)
609 const struct rte_flow_action_of_set_vlan_vid *conf =
610 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
611 int i = resource->actions_num;
612 struct mlx5_modification_cmd *actions = resource->actions;
613 struct field_modify_info *field = modify_vlan_out_first_vid;
615 if (i >= MLX5_MAX_MODIFY_NUM)
616 return rte_flow_error_set(error, EINVAL,
617 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
618 "too many items to modify");
619 actions[i] = (struct mlx5_modification_cmd) {
620 .action_type = MLX5_MODIFICATION_TYPE_SET,
622 .length = field->size,
623 .offset = field->offset,
625 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
626 actions[i].data1 = conf->vlan_vid;
627 actions[i].data1 = actions[i].data1 << 16;
628 resource->actions_num = ++i;
633 * Convert modify-header set TP action to DV specification.
635 * @param[in,out] resource
636 * Pointer to the modify-header resource.
638 * Pointer to action specification.
640 * Pointer to rte_flow_item objects list.
642 * Pointer to flow attributes structure.
643 * @param[in] tunnel_decap
644 * Whether action is after tunnel decapsulation.
646 * Pointer to the error structure.
649 * 0 on success, a negative errno value otherwise and rte_errno is set.
652 flow_dv_convert_action_modify_tp
653 (struct mlx5_flow_dv_modify_hdr_resource *resource,
654 const struct rte_flow_action *action,
655 const struct rte_flow_item *items,
656 union flow_dv_attr *attr, bool tunnel_decap,
657 struct rte_flow_error *error)
659 const struct rte_flow_action_set_tp *conf =
660 (const struct rte_flow_action_set_tp *)(action->conf);
661 struct rte_flow_item item;
662 struct rte_flow_item_udp udp;
663 struct rte_flow_item_udp udp_mask;
664 struct rte_flow_item_tcp tcp;
665 struct rte_flow_item_tcp tcp_mask;
666 struct field_modify_info *field;
669 flow_dv_attr_init(items, attr, tunnel_decap);
671 memset(&udp, 0, sizeof(udp));
672 memset(&udp_mask, 0, sizeof(udp_mask));
673 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
674 udp.hdr.src_port = conf->port;
675 udp_mask.hdr.src_port =
676 rte_flow_item_udp_mask.hdr.src_port;
678 udp.hdr.dst_port = conf->port;
679 udp_mask.hdr.dst_port =
680 rte_flow_item_udp_mask.hdr.dst_port;
682 item.type = RTE_FLOW_ITEM_TYPE_UDP;
684 item.mask = &udp_mask;
688 memset(&tcp, 0, sizeof(tcp));
689 memset(&tcp_mask, 0, sizeof(tcp_mask));
690 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
691 tcp.hdr.src_port = conf->port;
692 tcp_mask.hdr.src_port =
693 rte_flow_item_tcp_mask.hdr.src_port;
695 tcp.hdr.dst_port = conf->port;
696 tcp_mask.hdr.dst_port =
697 rte_flow_item_tcp_mask.hdr.dst_port;
699 item.type = RTE_FLOW_ITEM_TYPE_TCP;
701 item.mask = &tcp_mask;
704 return flow_dv_convert_modify_action(&item, field, NULL, resource,
705 MLX5_MODIFICATION_TYPE_SET, error);
709 * Convert modify-header set TTL action to DV specification.
711 * @param[in,out] resource
712 * Pointer to the modify-header resource.
714 * Pointer to action specification.
716 * Pointer to rte_flow_item objects list.
718 * Pointer to flow attributes structure.
719 * @param[in] tunnel_decap
720 * Whether action is after tunnel decapsulation.
722 * Pointer to the error structure.
725 * 0 on success, a negative errno value otherwise and rte_errno is set.
728 flow_dv_convert_action_modify_ttl
729 (struct mlx5_flow_dv_modify_hdr_resource *resource,
730 const struct rte_flow_action *action,
731 const struct rte_flow_item *items,
732 union flow_dv_attr *attr, bool tunnel_decap,
733 struct rte_flow_error *error)
735 const struct rte_flow_action_set_ttl *conf =
736 (const struct rte_flow_action_set_ttl *)(action->conf);
737 struct rte_flow_item item;
738 struct rte_flow_item_ipv4 ipv4;
739 struct rte_flow_item_ipv4 ipv4_mask;
740 struct rte_flow_item_ipv6 ipv6;
741 struct rte_flow_item_ipv6 ipv6_mask;
742 struct field_modify_info *field;
745 flow_dv_attr_init(items, attr, tunnel_decap);
747 memset(&ipv4, 0, sizeof(ipv4));
748 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
749 ipv4.hdr.time_to_live = conf->ttl_value;
750 ipv4_mask.hdr.time_to_live = 0xFF;
751 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
753 item.mask = &ipv4_mask;
757 memset(&ipv6, 0, sizeof(ipv6));
758 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
759 ipv6.hdr.hop_limits = conf->ttl_value;
760 ipv6_mask.hdr.hop_limits = 0xFF;
761 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
763 item.mask = &ipv6_mask;
766 return flow_dv_convert_modify_action(&item, field, NULL, resource,
767 MLX5_MODIFICATION_TYPE_SET, error);
771 * Convert modify-header decrement TTL action to DV specification.
773 * @param[in,out] resource
774 * Pointer to the modify-header resource.
776 * Pointer to action specification.
778 * Pointer to rte_flow_item objects list.
780 * Pointer to flow attributes structure.
781 * @param[in] tunnel_decap
782 * Whether action is after tunnel decapsulation.
784 * Pointer to the error structure.
787 * 0 on success, a negative errno value otherwise and rte_errno is set.
790 flow_dv_convert_action_modify_dec_ttl
791 (struct mlx5_flow_dv_modify_hdr_resource *resource,
792 const struct rte_flow_item *items,
793 union flow_dv_attr *attr, bool tunnel_decap,
794 struct rte_flow_error *error)
796 struct rte_flow_item item;
797 struct rte_flow_item_ipv4 ipv4;
798 struct rte_flow_item_ipv4 ipv4_mask;
799 struct rte_flow_item_ipv6 ipv6;
800 struct rte_flow_item_ipv6 ipv6_mask;
801 struct field_modify_info *field;
804 flow_dv_attr_init(items, attr, tunnel_decap);
806 memset(&ipv4, 0, sizeof(ipv4));
807 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
808 ipv4.hdr.time_to_live = 0xFF;
809 ipv4_mask.hdr.time_to_live = 0xFF;
810 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
812 item.mask = &ipv4_mask;
816 memset(&ipv6, 0, sizeof(ipv6));
817 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
818 ipv6.hdr.hop_limits = 0xFF;
819 ipv6_mask.hdr.hop_limits = 0xFF;
820 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
822 item.mask = &ipv6_mask;
825 return flow_dv_convert_modify_action(&item, field, NULL, resource,
826 MLX5_MODIFICATION_TYPE_ADD, error);
830 * Convert modify-header increment/decrement TCP Sequence number
831 * to DV specification.
833 * @param[in,out] resource
834 * Pointer to the modify-header resource.
836 * Pointer to action specification.
838 * Pointer to the error structure.
841 * 0 on success, a negative errno value otherwise and rte_errno is set.
844 flow_dv_convert_action_modify_tcp_seq
845 (struct mlx5_flow_dv_modify_hdr_resource *resource,
846 const struct rte_flow_action *action,
847 struct rte_flow_error *error)
849 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
850 uint64_t value = rte_be_to_cpu_32(*conf);
851 struct rte_flow_item item;
852 struct rte_flow_item_tcp tcp;
853 struct rte_flow_item_tcp tcp_mask;
855 memset(&tcp, 0, sizeof(tcp));
856 memset(&tcp_mask, 0, sizeof(tcp_mask));
857 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
859 * The HW has no decrement operation, only increment operation.
860 * To simulate decrement X from Y using increment operation
861 * we need to add UINT32_MAX X times to Y.
862 * Each adding of UINT32_MAX decrements Y by 1.
865 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
866 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
867 item.type = RTE_FLOW_ITEM_TYPE_TCP;
869 item.mask = &tcp_mask;
870 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
871 MLX5_MODIFICATION_TYPE_ADD, error);
875 * Convert modify-header increment/decrement TCP Acknowledgment number
876 * to DV specification.
878 * @param[in,out] resource
879 * Pointer to the modify-header resource.
881 * Pointer to action specification.
883 * Pointer to the error structure.
886 * 0 on success, a negative errno value otherwise and rte_errno is set.
889 flow_dv_convert_action_modify_tcp_ack
890 (struct mlx5_flow_dv_modify_hdr_resource *resource,
891 const struct rte_flow_action *action,
892 struct rte_flow_error *error)
894 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
895 uint64_t value = rte_be_to_cpu_32(*conf);
896 struct rte_flow_item item;
897 struct rte_flow_item_tcp tcp;
898 struct rte_flow_item_tcp tcp_mask;
900 memset(&tcp, 0, sizeof(tcp));
901 memset(&tcp_mask, 0, sizeof(tcp_mask));
902 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
904 * The HW has no decrement operation, only increment operation.
905 * To simulate decrement X from Y using increment operation
906 * we need to add UINT32_MAX X times to Y.
907 * Each adding of UINT32_MAX decrements Y by 1.
910 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
911 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
912 item.type = RTE_FLOW_ITEM_TYPE_TCP;
914 item.mask = &tcp_mask;
915 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
916 MLX5_MODIFICATION_TYPE_ADD, error);
919 static enum mlx5_modification_field reg_to_field[] = {
920 [REG_NONE] = MLX5_MODI_OUT_NONE,
921 [REG_A] = MLX5_MODI_META_DATA_REG_A,
922 [REG_B] = MLX5_MODI_META_DATA_REG_B,
923 [REG_C_0] = MLX5_MODI_META_REG_C_0,
924 [REG_C_1] = MLX5_MODI_META_REG_C_1,
925 [REG_C_2] = MLX5_MODI_META_REG_C_2,
926 [REG_C_3] = MLX5_MODI_META_REG_C_3,
927 [REG_C_4] = MLX5_MODI_META_REG_C_4,
928 [REG_C_5] = MLX5_MODI_META_REG_C_5,
929 [REG_C_6] = MLX5_MODI_META_REG_C_6,
930 [REG_C_7] = MLX5_MODI_META_REG_C_7,
934 * Convert register set to DV specification.
936 * @param[in,out] resource
937 * Pointer to the modify-header resource.
939 * Pointer to action specification.
941 * Pointer to the error structure.
944 * 0 on success, a negative errno value otherwise and rte_errno is set.
947 flow_dv_convert_action_set_reg
948 (struct mlx5_flow_dv_modify_hdr_resource *resource,
949 const struct rte_flow_action *action,
950 struct rte_flow_error *error)
952 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
953 struct mlx5_modification_cmd *actions = resource->actions;
954 uint32_t i = resource->actions_num;
956 if (i >= MLX5_MAX_MODIFY_NUM)
957 return rte_flow_error_set(error, EINVAL,
958 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
959 "too many items to modify");
960 MLX5_ASSERT(conf->id != REG_NONE);
961 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
962 actions[i] = (struct mlx5_modification_cmd) {
963 .action_type = MLX5_MODIFICATION_TYPE_SET,
964 .field = reg_to_field[conf->id],
966 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
967 actions[i].data1 = rte_cpu_to_be_32(conf->data);
969 resource->actions_num = i;
974 * Convert SET_TAG action to DV specification.
977 * Pointer to the rte_eth_dev structure.
978 * @param[in,out] resource
979 * Pointer to the modify-header resource.
981 * Pointer to action specification.
983 * Pointer to the error structure.
986 * 0 on success, a negative errno value otherwise and rte_errno is set.
989 flow_dv_convert_action_set_tag
990 (struct rte_eth_dev *dev,
991 struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action_set_tag *conf,
993 struct rte_flow_error *error)
995 rte_be32_t data = rte_cpu_to_be_32(conf->data);
996 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
997 struct rte_flow_item item = {
1001 struct field_modify_info reg_c_x[] = {
1004 enum mlx5_modification_field reg_type;
1007 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010 MLX5_ASSERT(ret != REG_NONE);
1011 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1012 reg_type = reg_to_field[ret];
1013 MLX5_ASSERT(reg_type > 0);
1014 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1015 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1016 MLX5_MODIFICATION_TYPE_SET, error);
1020 * Convert internal COPY_REG action to DV specification.
1023 * Pointer to the rte_eth_dev structure.
1024 * @param[in,out] res
1025 * Pointer to the modify-header resource.
1027 * Pointer to action specification.
1029 * Pointer to the error structure.
1032 * 0 on success, a negative errno value otherwise and rte_errno is set.
1035 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1036 struct mlx5_flow_dv_modify_hdr_resource *res,
1037 const struct rte_flow_action *action,
1038 struct rte_flow_error *error)
1040 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1041 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1042 struct rte_flow_item item = {
1046 struct field_modify_info reg_src[] = {
1047 {4, 0, reg_to_field[conf->src]},
1050 struct field_modify_info reg_dst = {
1052 .id = reg_to_field[conf->dst],
1054 /* Adjust reg_c[0] usage according to reported mask. */
1055 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1056 struct mlx5_priv *priv = dev->data->dev_private;
1057 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1059 MLX5_ASSERT(reg_c0);
1060 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1061 if (conf->dst == REG_C_0) {
1062 /* Copy to reg_c[0], within mask only. */
1063 reg_dst.offset = rte_bsf32(reg_c0);
1065 * Mask is ignoring the enianness, because
1066 * there is no conversion in datapath.
1068 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1069 /* Copy from destination lower bits to reg_c[0]. */
1070 mask = reg_c0 >> reg_dst.offset;
1072 /* Copy from destination upper bits to reg_c[0]. */
1073 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1074 rte_fls_u32(reg_c0));
1077 mask = rte_cpu_to_be_32(reg_c0);
1078 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1079 /* Copy from reg_c[0] to destination lower bits. */
1082 /* Copy from reg_c[0] to destination upper bits. */
1083 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1084 (rte_fls_u32(reg_c0) -
1089 return flow_dv_convert_modify_action(&item,
1090 reg_src, ®_dst, res,
1091 MLX5_MODIFICATION_TYPE_COPY,
1096 * Convert MARK action to DV specification. This routine is used
1097 * in extensive metadata only and requires metadata register to be
1098 * handled. In legacy mode hardware tag resource is engaged.
1101 * Pointer to the rte_eth_dev structure.
1103 * Pointer to MARK action specification.
1104 * @param[in,out] resource
1105 * Pointer to the modify-header resource.
1107 * Pointer to the error structure.
1110 * 0 on success, a negative errno value otherwise and rte_errno is set.
1113 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1114 const struct rte_flow_action_mark *conf,
1115 struct mlx5_flow_dv_modify_hdr_resource *resource,
1116 struct rte_flow_error *error)
1118 struct mlx5_priv *priv = dev->data->dev_private;
1119 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1120 priv->sh->dv_mark_mask);
1121 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1122 struct rte_flow_item item = {
1126 struct field_modify_info reg_c_x[] = {
1127 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1133 return rte_flow_error_set(error, EINVAL,
1134 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1135 NULL, "zero mark action mask");
1136 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1139 MLX5_ASSERT(reg > 0);
1140 if (reg == REG_C_0) {
1141 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1142 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1145 mask = rte_cpu_to_be_32(mask) & msk_c0;
1146 mask = rte_cpu_to_be_32(mask << shl_c0);
1148 reg_c_x[0].id = reg_to_field[reg];
1149 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1150 MLX5_MODIFICATION_TYPE_SET, error);
1154 * Get metadata register index for specified steering domain.
1157 * Pointer to the rte_eth_dev structure.
1159 * Attributes of flow to determine steering domain.
1161 * Pointer to the error structure.
1164 * positive index on success, a negative errno value otherwise
1165 * and rte_errno is set.
1167 static enum modify_reg
1168 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1169 const struct rte_flow_attr *attr,
1170 struct rte_flow_error *error)
1173 mlx5_flow_get_reg_id(dev, attr->transfer ?
1177 MLX5_METADATA_RX, 0, error);
1179 return rte_flow_error_set(error,
1180 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1181 NULL, "unavailable "
1182 "metadata register");
1187 * Convert SET_META action to DV specification.
1190 * Pointer to the rte_eth_dev structure.
1191 * @param[in,out] resource
1192 * Pointer to the modify-header resource.
1194 * Attributes of flow that includes this item.
1196 * Pointer to action specification.
1198 * Pointer to the error structure.
1201 * 0 on success, a negative errno value otherwise and rte_errno is set.
1204 flow_dv_convert_action_set_meta
1205 (struct rte_eth_dev *dev,
1206 struct mlx5_flow_dv_modify_hdr_resource *resource,
1207 const struct rte_flow_attr *attr,
1208 const struct rte_flow_action_set_meta *conf,
1209 struct rte_flow_error *error)
1211 uint32_t data = conf->data;
1212 uint32_t mask = conf->mask;
1213 struct rte_flow_item item = {
1217 struct field_modify_info reg_c_x[] = {
1220 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225 * In datapath code there is no endianness
1226 * coversions for perfromance reasons, all
1227 * pattern conversions are done in rte_flow.
1229 if (reg == REG_C_0) {
1230 struct mlx5_priv *priv = dev->data->dev_private;
1231 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234 MLX5_ASSERT(msk_c0);
1235 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1236 shl_c0 = rte_bsf32(msk_c0);
1238 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1242 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1244 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1245 /* The routine expects parameters in memory as big-endian ones. */
1246 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1247 MLX5_MODIFICATION_TYPE_SET, error);
1251 * Convert modify-header set IPv4 DSCP action to DV specification.
1253 * @param[in,out] resource
1254 * Pointer to the modify-header resource.
1256 * Pointer to action specification.
1258 * Pointer to the error structure.
1261 * 0 on success, a negative errno value otherwise and rte_errno is set.
1264 flow_dv_convert_action_modify_ipv4_dscp
1265 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1266 const struct rte_flow_action *action,
1267 struct rte_flow_error *error)
1269 const struct rte_flow_action_set_dscp *conf =
1270 (const struct rte_flow_action_set_dscp *)(action->conf);
1271 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1272 struct rte_flow_item_ipv4 ipv4;
1273 struct rte_flow_item_ipv4 ipv4_mask;
1275 memset(&ipv4, 0, sizeof(ipv4));
1276 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1277 ipv4.hdr.type_of_service = conf->dscp;
1278 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1280 item.mask = &ipv4_mask;
1281 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1282 MLX5_MODIFICATION_TYPE_SET, error);
1286 * Convert modify-header set IPv6 DSCP action to DV specification.
1288 * @param[in,out] resource
1289 * Pointer to the modify-header resource.
1291 * Pointer to action specification.
1293 * Pointer to the error structure.
1296 * 0 on success, a negative errno value otherwise and rte_errno is set.
1299 flow_dv_convert_action_modify_ipv6_dscp
1300 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1301 const struct rte_flow_action *action,
1302 struct rte_flow_error *error)
1304 const struct rte_flow_action_set_dscp *conf =
1305 (const struct rte_flow_action_set_dscp *)(action->conf);
1306 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1307 struct rte_flow_item_ipv6 ipv6;
1308 struct rte_flow_item_ipv6 ipv6_mask;
1310 memset(&ipv6, 0, sizeof(ipv6));
1311 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1313 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1314 * rdma-core only accept the DSCP bits byte aligned start from
1315 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1316 * bits in IPv6 case as rdma-core requires byte aligned value.
1318 ipv6.hdr.vtc_flow = conf->dscp;
1319 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1321 item.mask = &ipv6_mask;
1322 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1323 MLX5_MODIFICATION_TYPE_SET, error);
1327 * Validate MARK item.
1330 * Pointer to the rte_eth_dev structure.
1332 * Item specification.
1334 * Attributes of flow that includes this item.
1336 * Pointer to error structure.
1339 * 0 on success, a negative errno value otherwise and rte_errno is set.
1342 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1343 const struct rte_flow_item *item,
1344 const struct rte_flow_attr *attr __rte_unused,
1345 struct rte_flow_error *error)
1347 struct mlx5_priv *priv = dev->data->dev_private;
1348 struct mlx5_dev_config *config = &priv->config;
1349 const struct rte_flow_item_mark *spec = item->spec;
1350 const struct rte_flow_item_mark *mask = item->mask;
1351 const struct rte_flow_item_mark nic_mask = {
1352 .id = priv->sh->dv_mark_mask,
1356 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1357 return rte_flow_error_set(error, ENOTSUP,
1358 RTE_FLOW_ERROR_TYPE_ITEM, item,
1359 "extended metadata feature"
1361 if (!mlx5_flow_ext_mreg_supported(dev))
1362 return rte_flow_error_set(error, ENOTSUP,
1363 RTE_FLOW_ERROR_TYPE_ITEM, item,
1364 "extended metadata register"
1365 " isn't supported");
1367 return rte_flow_error_set(error, ENOTSUP,
1368 RTE_FLOW_ERROR_TYPE_ITEM, item,
1369 "extended metadata register"
1370 " isn't available");
1371 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1375 return rte_flow_error_set(error, EINVAL,
1376 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1378 "data cannot be empty");
1379 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1380 return rte_flow_error_set(error, EINVAL,
1381 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1383 "mark id exceeds the limit");
1386 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1387 (const uint8_t *)&nic_mask,
1388 sizeof(struct rte_flow_item_mark),
1396 * Validate META item.
1399 * Pointer to the rte_eth_dev structure.
1401 * Item specification.
1403 * Attributes of flow that includes this item.
1405 * Pointer to error structure.
1408 * 0 on success, a negative errno value otherwise and rte_errno is set.
1411 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1412 const struct rte_flow_item *item,
1413 const struct rte_flow_attr *attr,
1414 struct rte_flow_error *error)
1416 struct mlx5_priv *priv = dev->data->dev_private;
1417 struct mlx5_dev_config *config = &priv->config;
1418 const struct rte_flow_item_meta *spec = item->spec;
1419 const struct rte_flow_item_meta *mask = item->mask;
1420 struct rte_flow_item_meta nic_mask = {
1427 return rte_flow_error_set(error, EINVAL,
1428 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1430 "data cannot be empty");
1432 return rte_flow_error_set(error, EINVAL,
1433 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1434 "data cannot be zero");
1435 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1436 if (!mlx5_flow_ext_mreg_supported(dev))
1437 return rte_flow_error_set(error, ENOTSUP,
1438 RTE_FLOW_ERROR_TYPE_ITEM, item,
1439 "extended metadata register"
1440 " isn't supported");
1441 reg = flow_dv_get_metadata_reg(dev, attr, error);
1445 return rte_flow_error_set(error, ENOTSUP,
1446 RTE_FLOW_ERROR_TYPE_ITEM, item,
1450 nic_mask.data = priv->sh->dv_meta_mask;
1453 mask = &rte_flow_item_meta_mask;
1454 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1455 (const uint8_t *)&nic_mask,
1456 sizeof(struct rte_flow_item_meta),
1462 * Validate TAG item.
1465 * Pointer to the rte_eth_dev structure.
1467 * Item specification.
1469 * Attributes of flow that includes this item.
1471 * Pointer to error structure.
1474 * 0 on success, a negative errno value otherwise and rte_errno is set.
1477 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1478 const struct rte_flow_item *item,
1479 const struct rte_flow_attr *attr __rte_unused,
1480 struct rte_flow_error *error)
1482 const struct rte_flow_item_tag *spec = item->spec;
1483 const struct rte_flow_item_tag *mask = item->mask;
1484 const struct rte_flow_item_tag nic_mask = {
1485 .data = RTE_BE32(UINT32_MAX),
1490 if (!mlx5_flow_ext_mreg_supported(dev))
1491 return rte_flow_error_set(error, ENOTSUP,
1492 RTE_FLOW_ERROR_TYPE_ITEM, item,
1493 "extensive metadata register"
1494 " isn't supported");
1496 return rte_flow_error_set(error, EINVAL,
1497 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1499 "data cannot be empty");
1501 mask = &rte_flow_item_tag_mask;
1502 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1503 (const uint8_t *)&nic_mask,
1504 sizeof(struct rte_flow_item_tag),
1508 if (mask->index != 0xff)
1509 return rte_flow_error_set(error, EINVAL,
1510 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1511 "partial mask for tag index"
1512 " is not supported");
1513 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1516 MLX5_ASSERT(ret != REG_NONE);
1521 * Validate vport item.
1524 * Pointer to the rte_eth_dev structure.
1526 * Item specification.
1528 * Attributes of flow that includes this item.
1529 * @param[in] item_flags
1530 * Bit-fields that holds the items detected until now.
1532 * Pointer to error structure.
1535 * 0 on success, a negative errno value otherwise and rte_errno is set.
1538 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1539 const struct rte_flow_item *item,
1540 const struct rte_flow_attr *attr,
1541 uint64_t item_flags,
1542 struct rte_flow_error *error)
1544 const struct rte_flow_item_port_id *spec = item->spec;
1545 const struct rte_flow_item_port_id *mask = item->mask;
1546 const struct rte_flow_item_port_id switch_mask = {
1549 struct mlx5_priv *esw_priv;
1550 struct mlx5_priv *dev_priv;
1553 if (!attr->transfer)
1554 return rte_flow_error_set(error, EINVAL,
1555 RTE_FLOW_ERROR_TYPE_ITEM,
1557 "match on port id is valid only"
1558 " when transfer flag is enabled");
1559 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1560 return rte_flow_error_set(error, ENOTSUP,
1561 RTE_FLOW_ERROR_TYPE_ITEM, item,
1562 "multiple source ports are not"
1565 mask = &switch_mask;
1566 if (mask->id != 0xffffffff)
1567 return rte_flow_error_set(error, ENOTSUP,
1568 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1570 "no support for partial mask on"
1572 ret = mlx5_flow_item_acceptable
1573 (item, (const uint8_t *)mask,
1574 (const uint8_t *)&rte_flow_item_port_id_mask,
1575 sizeof(struct rte_flow_item_port_id),
1581 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1583 return rte_flow_error_set(error, rte_errno,
1584 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1585 "failed to obtain E-Switch info for"
1587 dev_priv = mlx5_dev_to_eswitch_info(dev);
1589 return rte_flow_error_set(error, rte_errno,
1590 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1592 "failed to obtain E-Switch info");
1593 if (esw_priv->domain_id != dev_priv->domain_id)
1594 return rte_flow_error_set(error, EINVAL,
1595 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1596 "cannot match on a port from a"
1597 " different E-Switch");
1602 * Validate GTP item.
1605 * Pointer to the rte_eth_dev structure.
1607 * Item specification.
1608 * @param[in] item_flags
1609 * Bit-fields that holds the items detected until now.
1611 * Pointer to error structure.
1614 * 0 on success, a negative errno value otherwise and rte_errno is set.
1617 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1618 const struct rte_flow_item *item,
1619 uint64_t item_flags,
1620 struct rte_flow_error *error)
1622 struct mlx5_priv *priv = dev->data->dev_private;
1623 const struct rte_flow_item_gtp *mask = item->mask;
1624 const struct rte_flow_item_gtp nic_mask = {
1626 .teid = RTE_BE32(0xffffffff),
1629 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1630 return rte_flow_error_set(error, ENOTSUP,
1631 RTE_FLOW_ERROR_TYPE_ITEM, item,
1632 "GTP support is not enabled");
1633 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1634 return rte_flow_error_set(error, ENOTSUP,
1635 RTE_FLOW_ERROR_TYPE_ITEM, item,
1636 "multiple tunnel layers not"
1638 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1639 return rte_flow_error_set(error, EINVAL,
1640 RTE_FLOW_ERROR_TYPE_ITEM, item,
1641 "no outer UDP layer found");
1643 mask = &rte_flow_item_gtp_mask;
1644 return mlx5_flow_item_acceptable
1645 (item, (const uint8_t *)mask,
1646 (const uint8_t *)&nic_mask,
1647 sizeof(struct rte_flow_item_gtp),
1652 * Validate the pop VLAN action.
1655 * Pointer to the rte_eth_dev structure.
1656 * @param[in] action_flags
1657 * Holds the actions detected until now.
1659 * Pointer to the pop vlan action.
1660 * @param[in] item_flags
1661 * The items found in this flow rule.
1663 * Pointer to flow attributes.
1665 * Pointer to error structure.
1668 * 0 on success, a negative errno value otherwise and rte_errno is set.
1671 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1672 uint64_t action_flags,
1673 const struct rte_flow_action *action,
1674 uint64_t item_flags,
1675 const struct rte_flow_attr *attr,
1676 struct rte_flow_error *error)
1678 struct mlx5_priv *priv = dev->data->dev_private;
1682 if (!priv->sh->pop_vlan_action)
1683 return rte_flow_error_set(error, ENOTSUP,
1684 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1686 "pop vlan action is not supported");
1688 return rte_flow_error_set(error, ENOTSUP,
1689 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1691 "pop vlan action not supported for "
1693 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1694 return rte_flow_error_set(error, ENOTSUP,
1695 RTE_FLOW_ERROR_TYPE_ACTION, action,
1696 "no support for multiple VLAN "
1698 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1699 return rte_flow_error_set(error, ENOTSUP,
1700 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1702 "cannot pop vlan without a "
1703 "match on (outer) vlan in the flow");
1704 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1705 return rte_flow_error_set(error, EINVAL,
1706 RTE_FLOW_ERROR_TYPE_ACTION, action,
1707 "wrong action order, port_id should "
1708 "be after pop VLAN action");
1713 * Get VLAN default info from vlan match info.
1716 * the list of item specifications.
1718 * pointer VLAN info to fill to.
1721 * 0 on success, a negative errno value otherwise and rte_errno is set.
1724 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1725 struct rte_vlan_hdr *vlan)
1727 const struct rte_flow_item_vlan nic_mask = {
1728 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1729 MLX5DV_FLOW_VLAN_VID_MASK),
1730 .inner_type = RTE_BE16(0xffff),
1735 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1736 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1738 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1739 const struct rte_flow_item_vlan *vlan_m = items->mask;
1740 const struct rte_flow_item_vlan *vlan_v = items->spec;
1744 /* Only full match values are accepted */
1745 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1746 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1747 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1749 rte_be_to_cpu_16(vlan_v->tci &
1750 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1752 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1753 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1754 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1756 rte_be_to_cpu_16(vlan_v->tci &
1757 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1759 if (vlan_m->inner_type == nic_mask.inner_type)
1760 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1761 vlan_m->inner_type);
1766 * Validate the push VLAN action.
1768 * @param[in] action_flags
1769 * Holds the actions detected until now.
1770 * @param[in] item_flags
1771 * The items found in this flow rule.
1773 * Pointer to the action structure.
1775 * Pointer to flow attributes
1777 * Pointer to error structure.
1780 * 0 on success, a negative errno value otherwise and rte_errno is set.
1783 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1784 uint64_t item_flags __rte_unused,
1785 const struct rte_flow_action *action,
1786 const struct rte_flow_attr *attr,
1787 struct rte_flow_error *error)
1789 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1791 if (!attr->transfer && attr->ingress)
1792 return rte_flow_error_set(error, ENOTSUP,
1793 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1795 "push VLAN action not supported for "
1797 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1798 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1799 return rte_flow_error_set(error, EINVAL,
1800 RTE_FLOW_ERROR_TYPE_ACTION, action,
1801 "invalid vlan ethertype");
1802 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1803 return rte_flow_error_set(error, ENOTSUP,
1804 RTE_FLOW_ERROR_TYPE_ACTION, action,
1805 "no support for multiple VLAN "
1807 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1808 return rte_flow_error_set(error, EINVAL,
1809 RTE_FLOW_ERROR_TYPE_ACTION, action,
1810 "wrong action order, port_id should "
1811 "be after push VLAN");
1817 * Validate the set VLAN PCP.
1819 * @param[in] action_flags
1820 * Holds the actions detected until now.
1821 * @param[in] actions
1822 * Pointer to the list of actions remaining in the flow rule.
1824 * Pointer to error structure.
1827 * 0 on success, a negative errno value otherwise and rte_errno is set.
1830 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1831 const struct rte_flow_action actions[],
1832 struct rte_flow_error *error)
1834 const struct rte_flow_action *action = actions;
1835 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1837 if (conf->vlan_pcp > 7)
1838 return rte_flow_error_set(error, EINVAL,
1839 RTE_FLOW_ERROR_TYPE_ACTION, action,
1840 "VLAN PCP value is too big");
1841 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1842 return rte_flow_error_set(error, ENOTSUP,
1843 RTE_FLOW_ERROR_TYPE_ACTION, action,
1844 "set VLAN PCP action must follow "
1845 "the push VLAN action");
1846 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_ACTION, action,
1849 "Multiple VLAN PCP modification are "
1851 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "wrong action order, port_id should "
1855 "be after set VLAN PCP");
1860 * Validate the set VLAN VID.
1862 * @param[in] item_flags
1863 * Holds the items detected in this rule.
1864 * @param[in] action_flags
1865 * Holds the actions detected until now.
1866 * @param[in] actions
1867 * Pointer to the list of actions remaining in the flow rule.
1869 * Pointer to error structure.
1872 * 0 on success, a negative errno value otherwise and rte_errno is set.
1875 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1876 uint64_t action_flags,
1877 const struct rte_flow_action actions[],
1878 struct rte_flow_error *error)
1880 const struct rte_flow_action *action = actions;
1881 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1883 if (conf->vlan_vid > RTE_BE16(0xFFE))
1884 return rte_flow_error_set(error, EINVAL,
1885 RTE_FLOW_ERROR_TYPE_ACTION, action,
1886 "VLAN VID value is too big");
1887 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1888 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1889 return rte_flow_error_set(error, ENOTSUP,
1890 RTE_FLOW_ERROR_TYPE_ACTION, action,
1891 "set VLAN VID action must follow push"
1892 " VLAN action or match on VLAN item");
1893 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1894 return rte_flow_error_set(error, ENOTSUP,
1895 RTE_FLOW_ERROR_TYPE_ACTION, action,
1896 "Multiple VLAN VID modifications are "
1898 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1899 return rte_flow_error_set(error, EINVAL,
1900 RTE_FLOW_ERROR_TYPE_ACTION, action,
1901 "wrong action order, port_id should "
1902 "be after set VLAN VID");
1907 * Validate the FLAG action.
1910 * Pointer to the rte_eth_dev structure.
1911 * @param[in] action_flags
1912 * Holds the actions detected until now.
1914 * Pointer to flow attributes
1916 * Pointer to error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1923 uint64_t action_flags,
1924 const struct rte_flow_attr *attr,
1925 struct rte_flow_error *error)
1927 struct mlx5_priv *priv = dev->data->dev_private;
1928 struct mlx5_dev_config *config = &priv->config;
1931 /* Fall back if no extended metadata register support. */
1932 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1933 return mlx5_flow_validate_action_flag(action_flags, attr,
1935 /* Extensive metadata mode requires registers. */
1936 if (!mlx5_flow_ext_mreg_supported(dev))
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1939 "no metadata registers "
1940 "to support flag action");
1941 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1944 "extended metadata register"
1945 " isn't available");
1946 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1949 MLX5_ASSERT(ret > 0);
1950 if (action_flags & MLX5_FLOW_ACTION_MARK)
1951 return rte_flow_error_set(error, EINVAL,
1952 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1953 "can't mark and flag in same flow");
1954 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1958 " actions in same flow");
1963 * Validate MARK action.
1966 * Pointer to the rte_eth_dev structure.
1968 * Pointer to action.
1969 * @param[in] action_flags
1970 * Holds the actions detected until now.
1972 * Pointer to flow attributes
1974 * Pointer to error structure.
1977 * 0 on success, a negative errno value otherwise and rte_errno is set.
1980 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1981 const struct rte_flow_action *action,
1982 uint64_t action_flags,
1983 const struct rte_flow_attr *attr,
1984 struct rte_flow_error *error)
1986 struct mlx5_priv *priv = dev->data->dev_private;
1987 struct mlx5_dev_config *config = &priv->config;
1988 const struct rte_flow_action_mark *mark = action->conf;
1991 /* Fall back if no extended metadata register support. */
1992 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1993 return mlx5_flow_validate_action_mark(action, action_flags,
1995 /* Extensive metadata mode requires registers. */
1996 if (!mlx5_flow_ext_mreg_supported(dev))
1997 return rte_flow_error_set(error, ENOTSUP,
1998 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1999 "no metadata registers "
2000 "to support mark action");
2001 if (!priv->sh->dv_mark_mask)
2002 return rte_flow_error_set(error, ENOTSUP,
2003 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2004 "extended metadata register"
2005 " isn't available");
2006 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2009 MLX5_ASSERT(ret > 0);
2011 return rte_flow_error_set(error, EINVAL,
2012 RTE_FLOW_ERROR_TYPE_ACTION, action,
2013 "configuration cannot be null");
2014 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2015 return rte_flow_error_set(error, EINVAL,
2016 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2018 "mark id exceeds the limit");
2019 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2020 return rte_flow_error_set(error, EINVAL,
2021 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2022 "can't flag and mark in same flow");
2023 if (action_flags & MLX5_FLOW_ACTION_MARK)
2024 return rte_flow_error_set(error, EINVAL,
2025 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2026 "can't have 2 mark actions in same"
2032 * Validate SET_META action.
2035 * Pointer to the rte_eth_dev structure.
2037 * Pointer to the action structure.
2038 * @param[in] action_flags
2039 * Holds the actions detected until now.
2041 * Pointer to flow attributes
2043 * Pointer to error structure.
2046 * 0 on success, a negative errno value otherwise and rte_errno is set.
2049 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2050 const struct rte_flow_action *action,
2051 uint64_t action_flags __rte_unused,
2052 const struct rte_flow_attr *attr,
2053 struct rte_flow_error *error)
2055 const struct rte_flow_action_set_meta *conf;
2056 uint32_t nic_mask = UINT32_MAX;
2059 if (!mlx5_flow_ext_mreg_supported(dev))
2060 return rte_flow_error_set(error, ENOTSUP,
2061 RTE_FLOW_ERROR_TYPE_ACTION, action,
2062 "extended metadata register"
2063 " isn't supported");
2064 reg = flow_dv_get_metadata_reg(dev, attr, error);
2067 if (reg != REG_A && reg != REG_B) {
2068 struct mlx5_priv *priv = dev->data->dev_private;
2070 nic_mask = priv->sh->dv_meta_mask;
2072 if (!(action->conf))
2073 return rte_flow_error_set(error, EINVAL,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "configuration cannot be null");
2076 conf = (const struct rte_flow_action_set_meta *)action->conf;
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "zero mask doesn't have any effect");
2081 if (conf->mask & ~nic_mask)
2082 return rte_flow_error_set(error, EINVAL,
2083 RTE_FLOW_ERROR_TYPE_ACTION, action,
2084 "meta data must be within reg C0");
2085 if (!(conf->data & conf->mask))
2086 return rte_flow_error_set(error, EINVAL,
2087 RTE_FLOW_ERROR_TYPE_ACTION, action,
2088 "zero value has no effect");
2093 * Validate SET_TAG action.
2096 * Pointer to the rte_eth_dev structure.
2098 * Pointer to the action structure.
2099 * @param[in] action_flags
2100 * Holds the actions detected until now.
2102 * Pointer to flow attributes
2104 * Pointer to error structure.
2107 * 0 on success, a negative errno value otherwise and rte_errno is set.
2110 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2111 const struct rte_flow_action *action,
2112 uint64_t action_flags,
2113 const struct rte_flow_attr *attr,
2114 struct rte_flow_error *error)
2116 const struct rte_flow_action_set_tag *conf;
2117 const uint64_t terminal_action_flags =
2118 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2119 MLX5_FLOW_ACTION_RSS;
2122 if (!mlx5_flow_ext_mreg_supported(dev))
2123 return rte_flow_error_set(error, ENOTSUP,
2124 RTE_FLOW_ERROR_TYPE_ACTION, action,
2125 "extensive metadata register"
2126 " isn't supported");
2127 if (!(action->conf))
2128 return rte_flow_error_set(error, EINVAL,
2129 RTE_FLOW_ERROR_TYPE_ACTION, action,
2130 "configuration cannot be null");
2131 conf = (const struct rte_flow_action_set_tag *)action->conf;
2133 return rte_flow_error_set(error, EINVAL,
2134 RTE_FLOW_ERROR_TYPE_ACTION, action,
2135 "zero mask doesn't have any effect");
2136 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2139 if (!attr->transfer && attr->ingress &&
2140 (action_flags & terminal_action_flags))
2141 return rte_flow_error_set(error, EINVAL,
2142 RTE_FLOW_ERROR_TYPE_ACTION, action,
2143 "set_tag has no effect"
2144 " with terminal actions");
2149 * Validate count action.
2152 * Pointer to rte_eth_dev structure.
2154 * Pointer to error structure.
2157 * 0 on success, a negative errno value otherwise and rte_errno is set.
2160 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2161 struct rte_flow_error *error)
2163 struct mlx5_priv *priv = dev->data->dev_private;
2165 if (!priv->config.devx)
2167 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2171 return rte_flow_error_set
2173 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2175 "count action not supported");
2179 * Validate the L2 encap action.
2181 * @param[in] action_flags
2182 * Holds the actions detected until now.
2184 * Pointer to the action structure.
2186 * Pointer to error structure.
2189 * 0 on success, a negative errno value otherwise and rte_errno is set.
2192 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2193 const struct rte_flow_action *action,
2194 struct rte_flow_error *error)
2196 if (!(action->conf))
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ACTION, action,
2199 "configuration cannot be null");
2200 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2201 return rte_flow_error_set(error, EINVAL,
2202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2203 "can only have a single encap action "
2209 * Validate a decap action.
2211 * @param[in] action_flags
2212 * Holds the actions detected until now.
2214 * Pointer to flow attributes
2216 * Pointer to error structure.
2219 * 0 on success, a negative errno value otherwise and rte_errno is set.
2222 flow_dv_validate_action_decap(uint64_t action_flags,
2223 const struct rte_flow_attr *attr,
2224 struct rte_flow_error *error)
2226 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2227 return rte_flow_error_set(error, ENOTSUP,
2228 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2230 MLX5_FLOW_ACTION_DECAP ? "can only "
2231 "have a single decap action" : "decap "
2232 "after encap is not supported");
2233 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2234 return rte_flow_error_set(error, EINVAL,
2235 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2236 "can't have decap action after"
2239 return rte_flow_error_set(error, ENOTSUP,
2240 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2242 "decap action not supported for "
2247 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2250 * Validate the raw encap and decap actions.
2253 * Pointer to the decap action.
2255 * Pointer to the encap action.
2257 * Pointer to flow attributes
2258 * @param[in/out] action_flags
2259 * Holds the actions detected until now.
2260 * @param[out] actions_n
2261 * pointer to the number of actions counter.
2263 * Pointer to error structure.
2266 * 0 on success, a negative errno value otherwise and rte_errno is set.
2269 flow_dv_validate_action_raw_encap_decap
2270 (const struct rte_flow_action_raw_decap *decap,
2271 const struct rte_flow_action_raw_encap *encap,
2272 const struct rte_flow_attr *attr, uint64_t *action_flags,
2273 int *actions_n, struct rte_flow_error *error)
2277 if (encap && (!encap->size || !encap->data))
2278 return rte_flow_error_set(error, EINVAL,
2279 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2280 "raw encap data cannot be empty");
2281 if (decap && encap) {
2282 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2283 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2286 else if (encap->size <=
2287 MLX5_ENCAPSULATION_DECISION_SIZE &&
2289 MLX5_ENCAPSULATION_DECISION_SIZE)
2292 else if (encap->size >
2293 MLX5_ENCAPSULATION_DECISION_SIZE &&
2295 MLX5_ENCAPSULATION_DECISION_SIZE)
2296 /* 2 L2 actions: encap and decap. */
2299 return rte_flow_error_set(error,
2301 RTE_FLOW_ERROR_TYPE_ACTION,
2302 NULL, "unsupported too small "
2303 "raw decap and too small raw "
2304 "encap combination");
2307 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2310 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2314 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2315 return rte_flow_error_set(error, ENOTSUP,
2316 RTE_FLOW_ERROR_TYPE_ACTION,
2318 "small raw encap size");
2319 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2320 return rte_flow_error_set(error, EINVAL,
2321 RTE_FLOW_ERROR_TYPE_ACTION,
2323 "more than one encap action");
2324 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2331 * Find existing encap/decap resource or create and register a new one.
2333 * @param[in, out] dev
2334 * Pointer to rte_eth_dev structure.
2335 * @param[in, out] resource
2336 * Pointer to encap/decap resource.
2337 * @parm[in, out] dev_flow
2338 * Pointer to the dev_flow.
2340 * pointer to error structure.
2343 * 0 on success otherwise -errno and errno is set.
2346 flow_dv_encap_decap_resource_register
2347 (struct rte_eth_dev *dev,
2348 struct mlx5_flow_dv_encap_decap_resource *resource,
2349 struct mlx5_flow *dev_flow,
2350 struct rte_flow_error *error)
2352 struct mlx5_priv *priv = dev->data->dev_private;
2353 struct mlx5_ibv_shared *sh = priv->sh;
2354 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2355 struct mlx5dv_dr_domain *domain;
2357 resource->flags = dev_flow->group ? 0 : 1;
2358 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2359 domain = sh->fdb_domain;
2360 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2361 domain = sh->rx_domain;
2363 domain = sh->tx_domain;
2364 /* Lookup a matching resource from cache. */
2365 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2366 if (resource->reformat_type == cache_resource->reformat_type &&
2367 resource->ft_type == cache_resource->ft_type &&
2368 resource->flags == cache_resource->flags &&
2369 resource->size == cache_resource->size &&
2370 !memcmp((const void *)resource->buf,
2371 (const void *)cache_resource->buf,
2373 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2374 (void *)cache_resource,
2375 rte_atomic32_read(&cache_resource->refcnt));
2376 rte_atomic32_inc(&cache_resource->refcnt);
2377 dev_flow->dv.encap_decap = cache_resource;
2381 /* Register new encap/decap resource. */
2382 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2383 if (!cache_resource)
2384 return rte_flow_error_set(error, ENOMEM,
2385 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2386 "cannot allocate resource memory");
2387 *cache_resource = *resource;
2388 cache_resource->verbs_action =
2389 mlx5_glue->dv_create_flow_action_packet_reformat
2390 (sh->ctx, cache_resource->reformat_type,
2391 cache_resource->ft_type, domain, cache_resource->flags,
2392 cache_resource->size,
2393 (cache_resource->size ? cache_resource->buf : NULL));
2394 if (!cache_resource->verbs_action) {
2395 rte_free(cache_resource);
2396 return rte_flow_error_set(error, ENOMEM,
2397 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2398 NULL, "cannot create action");
2400 rte_atomic32_init(&cache_resource->refcnt);
2401 rte_atomic32_inc(&cache_resource->refcnt);
2402 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2403 dev_flow->dv.encap_decap = cache_resource;
2404 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2405 (void *)cache_resource,
2406 rte_atomic32_read(&cache_resource->refcnt));
2411 * Find existing table jump resource or create and register a new one.
2413 * @param[in, out] dev
2414 * Pointer to rte_eth_dev structure.
2415 * @param[in, out] tbl
2416 * Pointer to flow table resource.
2417 * @parm[in, out] dev_flow
2418 * Pointer to the dev_flow.
2420 * pointer to error structure.
2423 * 0 on success otherwise -errno and errno is set.
2426 flow_dv_jump_tbl_resource_register
2427 (struct rte_eth_dev *dev __rte_unused,
2428 struct mlx5_flow_tbl_resource *tbl,
2429 struct mlx5_flow *dev_flow,
2430 struct rte_flow_error *error)
2432 struct mlx5_flow_tbl_data_entry *tbl_data =
2433 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2437 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2439 tbl_data->jump.action =
2440 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2442 if (!tbl_data->jump.action)
2443 return rte_flow_error_set(error, ENOMEM,
2444 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2445 NULL, "cannot create jump action");
2446 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2447 (void *)&tbl_data->jump, cnt);
2449 MLX5_ASSERT(tbl_data->jump.action);
2450 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2451 (void *)&tbl_data->jump, cnt);
2453 rte_atomic32_inc(&tbl_data->jump.refcnt);
2454 dev_flow->dv.jump = &tbl_data->jump;
2459 * Find existing table port ID resource or create and register a new one.
2461 * @param[in, out] dev
2462 * Pointer to rte_eth_dev structure.
2463 * @param[in, out] resource
2464 * Pointer to port ID action resource.
2465 * @parm[in, out] dev_flow
2466 * Pointer to the dev_flow.
2468 * pointer to error structure.
2471 * 0 on success otherwise -errno and errno is set.
2474 flow_dv_port_id_action_resource_register
2475 (struct rte_eth_dev *dev,
2476 struct mlx5_flow_dv_port_id_action_resource *resource,
2477 struct mlx5_flow *dev_flow,
2478 struct rte_flow_error *error)
2480 struct mlx5_priv *priv = dev->data->dev_private;
2481 struct mlx5_ibv_shared *sh = priv->sh;
2482 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2484 /* Lookup a matching resource from cache. */
2485 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2486 if (resource->port_id == cache_resource->port_id) {
2487 DRV_LOG(DEBUG, "port id action resource resource %p: "
2489 (void *)cache_resource,
2490 rte_atomic32_read(&cache_resource->refcnt));
2491 rte_atomic32_inc(&cache_resource->refcnt);
2492 dev_flow->dv.port_id_action = cache_resource;
2496 /* Register new port id action resource. */
2497 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2498 if (!cache_resource)
2499 return rte_flow_error_set(error, ENOMEM,
2500 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2501 "cannot allocate resource memory");
2502 *cache_resource = *resource;
2504 * Depending on rdma_core version the glue routine calls
2505 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2506 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2508 cache_resource->action =
2509 mlx5_glue->dr_create_flow_action_dest_port
2510 (priv->sh->fdb_domain, resource->port_id);
2511 if (!cache_resource->action) {
2512 rte_free(cache_resource);
2513 return rte_flow_error_set(error, ENOMEM,
2514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2515 NULL, "cannot create action");
2517 rte_atomic32_init(&cache_resource->refcnt);
2518 rte_atomic32_inc(&cache_resource->refcnt);
2519 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2520 dev_flow->dv.port_id_action = cache_resource;
2521 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2522 (void *)cache_resource,
2523 rte_atomic32_read(&cache_resource->refcnt));
2528 * Find existing push vlan resource or create and register a new one.
2530 * @param [in, out] dev
2531 * Pointer to rte_eth_dev structure.
2532 * @param[in, out] resource
2533 * Pointer to port ID action resource.
2534 * @parm[in, out] dev_flow
2535 * Pointer to the dev_flow.
2537 * pointer to error structure.
2540 * 0 on success otherwise -errno and errno is set.
2543 flow_dv_push_vlan_action_resource_register
2544 (struct rte_eth_dev *dev,
2545 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2546 struct mlx5_flow *dev_flow,
2547 struct rte_flow_error *error)
2549 struct mlx5_priv *priv = dev->data->dev_private;
2550 struct mlx5_ibv_shared *sh = priv->sh;
2551 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2552 struct mlx5dv_dr_domain *domain;
2554 /* Lookup a matching resource from cache. */
2555 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2556 if (resource->vlan_tag == cache_resource->vlan_tag &&
2557 resource->ft_type == cache_resource->ft_type) {
2558 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2560 (void *)cache_resource,
2561 rte_atomic32_read(&cache_resource->refcnt));
2562 rte_atomic32_inc(&cache_resource->refcnt);
2563 dev_flow->dv.push_vlan_res = cache_resource;
2567 /* Register new push_vlan action resource. */
2568 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2569 if (!cache_resource)
2570 return rte_flow_error_set(error, ENOMEM,
2571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2572 "cannot allocate resource memory");
2573 *cache_resource = *resource;
2574 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2575 domain = sh->fdb_domain;
2576 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2577 domain = sh->rx_domain;
2579 domain = sh->tx_domain;
2580 cache_resource->action =
2581 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2582 resource->vlan_tag);
2583 if (!cache_resource->action) {
2584 rte_free(cache_resource);
2585 return rte_flow_error_set(error, ENOMEM,
2586 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2587 NULL, "cannot create action");
2589 rte_atomic32_init(&cache_resource->refcnt);
2590 rte_atomic32_inc(&cache_resource->refcnt);
2591 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2592 dev_flow->dv.push_vlan_res = cache_resource;
2593 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2594 (void *)cache_resource,
2595 rte_atomic32_read(&cache_resource->refcnt));
2599 * Get the size of specific rte_flow_item_type
2601 * @param[in] item_type
2602 * Tested rte_flow_item_type.
2605 * sizeof struct item_type, 0 if void or irrelevant.
2608 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2612 switch (item_type) {
2613 case RTE_FLOW_ITEM_TYPE_ETH:
2614 retval = sizeof(struct rte_flow_item_eth);
2616 case RTE_FLOW_ITEM_TYPE_VLAN:
2617 retval = sizeof(struct rte_flow_item_vlan);
2619 case RTE_FLOW_ITEM_TYPE_IPV4:
2620 retval = sizeof(struct rte_flow_item_ipv4);
2622 case RTE_FLOW_ITEM_TYPE_IPV6:
2623 retval = sizeof(struct rte_flow_item_ipv6);
2625 case RTE_FLOW_ITEM_TYPE_UDP:
2626 retval = sizeof(struct rte_flow_item_udp);
2628 case RTE_FLOW_ITEM_TYPE_TCP:
2629 retval = sizeof(struct rte_flow_item_tcp);
2631 case RTE_FLOW_ITEM_TYPE_VXLAN:
2632 retval = sizeof(struct rte_flow_item_vxlan);
2634 case RTE_FLOW_ITEM_TYPE_GRE:
2635 retval = sizeof(struct rte_flow_item_gre);
2637 case RTE_FLOW_ITEM_TYPE_NVGRE:
2638 retval = sizeof(struct rte_flow_item_nvgre);
2640 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2641 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2643 case RTE_FLOW_ITEM_TYPE_MPLS:
2644 retval = sizeof(struct rte_flow_item_mpls);
2646 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2654 #define MLX5_ENCAP_IPV4_VERSION 0x40
2655 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2656 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2657 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2658 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2659 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2660 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2663 * Convert the encap action data from list of rte_flow_item to raw buffer
2666 * Pointer to rte_flow_item objects list.
2668 * Pointer to the output buffer.
2670 * Pointer to the output buffer size.
2672 * Pointer to the error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2679 size_t *size, struct rte_flow_error *error)
2681 struct rte_ether_hdr *eth = NULL;
2682 struct rte_vlan_hdr *vlan = NULL;
2683 struct rte_ipv4_hdr *ipv4 = NULL;
2684 struct rte_ipv6_hdr *ipv6 = NULL;
2685 struct rte_udp_hdr *udp = NULL;
2686 struct rte_vxlan_hdr *vxlan = NULL;
2687 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2688 struct rte_gre_hdr *gre = NULL;
2690 size_t temp_size = 0;
2693 return rte_flow_error_set(error, EINVAL,
2694 RTE_FLOW_ERROR_TYPE_ACTION,
2695 NULL, "invalid empty data");
2696 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2697 len = flow_dv_get_item_len(items->type);
2698 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ACTION,
2701 (void *)items->type,
2702 "items total size is too big"
2703 " for encap action");
2704 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2705 switch (items->type) {
2706 case RTE_FLOW_ITEM_TYPE_ETH:
2707 eth = (struct rte_ether_hdr *)&buf[temp_size];
2709 case RTE_FLOW_ITEM_TYPE_VLAN:
2710 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2712 return rte_flow_error_set(error, EINVAL,
2713 RTE_FLOW_ERROR_TYPE_ACTION,
2714 (void *)items->type,
2715 "eth header not found");
2716 if (!eth->ether_type)
2717 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2719 case RTE_FLOW_ITEM_TYPE_IPV4:
2720 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2722 return rte_flow_error_set(error, EINVAL,
2723 RTE_FLOW_ERROR_TYPE_ACTION,
2724 (void *)items->type,
2725 "neither eth nor vlan"
2727 if (vlan && !vlan->eth_proto)
2728 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2729 else if (eth && !eth->ether_type)
2730 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2731 if (!ipv4->version_ihl)
2732 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2733 MLX5_ENCAP_IPV4_IHL_MIN;
2734 if (!ipv4->time_to_live)
2735 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2737 case RTE_FLOW_ITEM_TYPE_IPV6:
2738 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2740 return rte_flow_error_set(error, EINVAL,
2741 RTE_FLOW_ERROR_TYPE_ACTION,
2742 (void *)items->type,
2743 "neither eth nor vlan"
2745 if (vlan && !vlan->eth_proto)
2746 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2747 else if (eth && !eth->ether_type)
2748 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2749 if (!ipv6->vtc_flow)
2751 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2752 if (!ipv6->hop_limits)
2753 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2755 case RTE_FLOW_ITEM_TYPE_UDP:
2756 udp = (struct rte_udp_hdr *)&buf[temp_size];
2758 return rte_flow_error_set(error, EINVAL,
2759 RTE_FLOW_ERROR_TYPE_ACTION,
2760 (void *)items->type,
2761 "ip header not found");
2762 if (ipv4 && !ipv4->next_proto_id)
2763 ipv4->next_proto_id = IPPROTO_UDP;
2764 else if (ipv6 && !ipv6->proto)
2765 ipv6->proto = IPPROTO_UDP;
2767 case RTE_FLOW_ITEM_TYPE_VXLAN:
2768 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2770 return rte_flow_error_set(error, EINVAL,
2771 RTE_FLOW_ERROR_TYPE_ACTION,
2772 (void *)items->type,
2773 "udp header not found");
2775 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2776 if (!vxlan->vx_flags)
2778 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2780 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2781 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION,
2785 (void *)items->type,
2786 "udp header not found");
2787 if (!vxlan_gpe->proto)
2788 return rte_flow_error_set(error, EINVAL,
2789 RTE_FLOW_ERROR_TYPE_ACTION,
2790 (void *)items->type,
2791 "next protocol not found");
2794 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2795 if (!vxlan_gpe->vx_flags)
2796 vxlan_gpe->vx_flags =
2797 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2799 case RTE_FLOW_ITEM_TYPE_GRE:
2800 case RTE_FLOW_ITEM_TYPE_NVGRE:
2801 gre = (struct rte_gre_hdr *)&buf[temp_size];
2803 return rte_flow_error_set(error, EINVAL,
2804 RTE_FLOW_ERROR_TYPE_ACTION,
2805 (void *)items->type,
2806 "next protocol not found");
2808 return rte_flow_error_set(error, EINVAL,
2809 RTE_FLOW_ERROR_TYPE_ACTION,
2810 (void *)items->type,
2811 "ip header not found");
2812 if (ipv4 && !ipv4->next_proto_id)
2813 ipv4->next_proto_id = IPPROTO_GRE;
2814 else if (ipv6 && !ipv6->proto)
2815 ipv6->proto = IPPROTO_GRE;
2817 case RTE_FLOW_ITEM_TYPE_VOID:
2820 return rte_flow_error_set(error, EINVAL,
2821 RTE_FLOW_ERROR_TYPE_ACTION,
2822 (void *)items->type,
2823 "unsupported item type");
2833 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2835 struct rte_ether_hdr *eth = NULL;
2836 struct rte_vlan_hdr *vlan = NULL;
2837 struct rte_ipv6_hdr *ipv6 = NULL;
2838 struct rte_udp_hdr *udp = NULL;
2842 eth = (struct rte_ether_hdr *)data;
2843 next_hdr = (char *)(eth + 1);
2844 proto = RTE_BE16(eth->ether_type);
2847 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2848 vlan = (struct rte_vlan_hdr *)next_hdr;
2849 proto = RTE_BE16(vlan->eth_proto);
2850 next_hdr += sizeof(struct rte_vlan_hdr);
2853 /* HW calculates IPv4 csum. no need to proceed */
2854 if (proto == RTE_ETHER_TYPE_IPV4)
2857 /* non IPv4/IPv6 header. not supported */
2858 if (proto != RTE_ETHER_TYPE_IPV6) {
2859 return rte_flow_error_set(error, ENOTSUP,
2860 RTE_FLOW_ERROR_TYPE_ACTION,
2861 NULL, "Cannot offload non IPv4/IPv6");
2864 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2866 /* ignore non UDP */
2867 if (ipv6->proto != IPPROTO_UDP)
2870 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2871 udp->dgram_cksum = 0;
2877 * Convert L2 encap action to DV specification.
2880 * Pointer to rte_eth_dev structure.
2882 * Pointer to action structure.
2883 * @param[in, out] dev_flow
2884 * Pointer to the mlx5_flow.
2885 * @param[in] transfer
2886 * Mark if the flow is E-Switch flow.
2888 * Pointer to the error structure.
2891 * 0 on success, a negative errno value otherwise and rte_errno is set.
2894 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2895 const struct rte_flow_action *action,
2896 struct mlx5_flow *dev_flow,
2898 struct rte_flow_error *error)
2900 const struct rte_flow_item *encap_data;
2901 const struct rte_flow_action_raw_encap *raw_encap_data;
2902 struct mlx5_flow_dv_encap_decap_resource res = {
2904 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2905 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2906 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2909 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2911 (const struct rte_flow_action_raw_encap *)action->conf;
2912 res.size = raw_encap_data->size;
2913 memcpy(res.buf, raw_encap_data->data, res.size);
2915 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2917 ((const struct rte_flow_action_vxlan_encap *)
2918 action->conf)->definition;
2921 ((const struct rte_flow_action_nvgre_encap *)
2922 action->conf)->definition;
2923 if (flow_dv_convert_encap_data(encap_data, res.buf,
2927 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2929 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2930 return rte_flow_error_set(error, EINVAL,
2931 RTE_FLOW_ERROR_TYPE_ACTION,
2932 NULL, "can't create L2 encap action");
2937 * Convert L2 decap action to DV specification.
2940 * Pointer to rte_eth_dev structure.
2941 * @param[in, out] dev_flow
2942 * Pointer to the mlx5_flow.
2943 * @param[in] transfer
2944 * Mark if the flow is E-Switch flow.
2946 * Pointer to the error structure.
2949 * 0 on success, a negative errno value otherwise and rte_errno is set.
2952 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2953 struct mlx5_flow *dev_flow,
2955 struct rte_flow_error *error)
2957 struct mlx5_flow_dv_encap_decap_resource res = {
2960 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2961 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2962 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2965 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 NULL, "can't create L2 decap action");
2973 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2976 * Pointer to rte_eth_dev structure.
2978 * Pointer to action structure.
2979 * @param[in, out] dev_flow
2980 * Pointer to the mlx5_flow.
2982 * Pointer to the flow attributes.
2984 * Pointer to the error structure.
2987 * 0 on success, a negative errno value otherwise and rte_errno is set.
2990 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2991 const struct rte_flow_action *action,
2992 struct mlx5_flow *dev_flow,
2993 const struct rte_flow_attr *attr,
2994 struct rte_flow_error *error)
2996 const struct rte_flow_action_raw_encap *encap_data;
2997 struct mlx5_flow_dv_encap_decap_resource res;
2999 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3000 res.size = encap_data->size;
3001 memcpy(res.buf, encap_data->data, res.size);
3002 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3003 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3004 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3006 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3008 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3009 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3010 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3011 return rte_flow_error_set(error, EINVAL,
3012 RTE_FLOW_ERROR_TYPE_ACTION,
3013 NULL, "can't create encap action");
3018 * Create action push VLAN.
3021 * Pointer to rte_eth_dev structure.
3023 * Pointer to the flow attributes.
3025 * Pointer to the vlan to push to the Ethernet header.
3026 * @param[in, out] dev_flow
3027 * Pointer to the mlx5_flow.
3029 * Pointer to the error structure.
3032 * 0 on success, a negative errno value otherwise and rte_errno is set.
3035 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3036 const struct rte_flow_attr *attr,
3037 const struct rte_vlan_hdr *vlan,
3038 struct mlx5_flow *dev_flow,
3039 struct rte_flow_error *error)
3041 struct mlx5_flow_dv_push_vlan_action_resource res;
3044 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3047 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3049 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3050 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3051 return flow_dv_push_vlan_action_resource_register
3052 (dev, &res, dev_flow, error);
3056 * Validate the modify-header actions.
3058 * @param[in] action_flags
3059 * Holds the actions detected until now.
3061 * Pointer to the modify action.
3063 * Pointer to error structure.
3066 * 0 on success, a negative errno value otherwise and rte_errno is set.
3069 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3070 const struct rte_flow_action *action,
3071 struct rte_flow_error *error)
3073 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3074 return rte_flow_error_set(error, EINVAL,
3075 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3076 NULL, "action configuration not set");
3077 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3078 return rte_flow_error_set(error, EINVAL,
3079 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3080 "can't have encap action before"
3086 * Validate the modify-header MAC address actions.
3088 * @param[in] action_flags
3089 * Holds the actions detected until now.
3091 * Pointer to the modify action.
3092 * @param[in] item_flags
3093 * Holds the items detected.
3095 * Pointer to error structure.
3098 * 0 on success, a negative errno value otherwise and rte_errno is set.
3101 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3102 const struct rte_flow_action *action,
3103 const uint64_t item_flags,
3104 struct rte_flow_error *error)
3108 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3110 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3111 return rte_flow_error_set(error, EINVAL,
3112 RTE_FLOW_ERROR_TYPE_ACTION,
3114 "no L2 item in pattern");
3120 * Validate the modify-header IPv4 address actions.
3122 * @param[in] action_flags
3123 * Holds the actions detected until now.
3125 * Pointer to the modify action.
3126 * @param[in] item_flags
3127 * Holds the items detected.
3129 * Pointer to error structure.
3132 * 0 on success, a negative errno value otherwise and rte_errno is set.
3135 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3136 const struct rte_flow_action *action,
3137 const uint64_t item_flags,
3138 struct rte_flow_error *error)
3143 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3145 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3146 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3147 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3148 if (!(item_flags & layer))
3149 return rte_flow_error_set(error, EINVAL,
3150 RTE_FLOW_ERROR_TYPE_ACTION,
3152 "no ipv4 item in pattern");
3158 * Validate the modify-header IPv6 address actions.
3160 * @param[in] action_flags
3161 * Holds the actions detected until now.
3163 * Pointer to the modify action.
3164 * @param[in] item_flags
3165 * Holds the items detected.
3167 * Pointer to error structure.
3170 * 0 on success, a negative errno value otherwise and rte_errno is set.
3173 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3174 const struct rte_flow_action *action,
3175 const uint64_t item_flags,
3176 struct rte_flow_error *error)
3181 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3183 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3184 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3185 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3186 if (!(item_flags & layer))
3187 return rte_flow_error_set(error, EINVAL,
3188 RTE_FLOW_ERROR_TYPE_ACTION,
3190 "no ipv6 item in pattern");
3196 * Validate the modify-header TP actions.
3198 * @param[in] action_flags
3199 * Holds the actions detected until now.
3201 * Pointer to the modify action.
3202 * @param[in] item_flags
3203 * Holds the items detected.
3205 * Pointer to error structure.
3208 * 0 on success, a negative errno value otherwise and rte_errno is set.
3211 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3212 const struct rte_flow_action *action,
3213 const uint64_t item_flags,
3214 struct rte_flow_error *error)
3219 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3221 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3222 MLX5_FLOW_LAYER_INNER_L4 :
3223 MLX5_FLOW_LAYER_OUTER_L4;
3224 if (!(item_flags & layer))
3225 return rte_flow_error_set(error, EINVAL,
3226 RTE_FLOW_ERROR_TYPE_ACTION,
3227 NULL, "no transport layer "
3234 * Validate the modify-header actions of increment/decrement
3235 * TCP Sequence-number.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to the modify action.
3241 * @param[in] item_flags
3242 * Holds the items detected.
3244 * Pointer to error structure.
3247 * 0 on success, a negative errno value otherwise and rte_errno is set.
3250 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3251 const struct rte_flow_action *action,
3252 const uint64_t item_flags,
3253 struct rte_flow_error *error)
3258 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3260 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3261 MLX5_FLOW_LAYER_INNER_L4_TCP :
3262 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3263 if (!(item_flags & layer))
3264 return rte_flow_error_set(error, EINVAL,
3265 RTE_FLOW_ERROR_TYPE_ACTION,
3266 NULL, "no TCP item in"
3268 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3269 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3270 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3271 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3272 return rte_flow_error_set(error, EINVAL,
3273 RTE_FLOW_ERROR_TYPE_ACTION,
3275 "cannot decrease and increase"
3276 " TCP sequence number"
3277 " at the same time");
3283 * Validate the modify-header actions of increment/decrement
3284 * TCP Acknowledgment number.
3286 * @param[in] action_flags
3287 * Holds the actions detected until now.
3289 * Pointer to the modify action.
3290 * @param[in] item_flags
3291 * Holds the items detected.
3293 * Pointer to error structure.
3296 * 0 on success, a negative errno value otherwise and rte_errno is set.
3299 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3300 const struct rte_flow_action *action,
3301 const uint64_t item_flags,
3302 struct rte_flow_error *error)
3307 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3309 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3310 MLX5_FLOW_LAYER_INNER_L4_TCP :
3311 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3312 if (!(item_flags & layer))
3313 return rte_flow_error_set(error, EINVAL,
3314 RTE_FLOW_ERROR_TYPE_ACTION,
3315 NULL, "no TCP item in"
3317 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3318 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3319 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3320 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3321 return rte_flow_error_set(error, EINVAL,
3322 RTE_FLOW_ERROR_TYPE_ACTION,
3324 "cannot decrease and increase"
3325 " TCP acknowledgment number"
3326 " at the same time");
3332 * Validate the modify-header TTL actions.
3334 * @param[in] action_flags
3335 * Holds the actions detected until now.
3337 * Pointer to the modify action.
3338 * @param[in] item_flags
3339 * Holds the items detected.
3341 * Pointer to error structure.
3344 * 0 on success, a negative errno value otherwise and rte_errno is set.
3347 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3348 const struct rte_flow_action *action,
3349 const uint64_t item_flags,
3350 struct rte_flow_error *error)
3355 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3357 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3358 MLX5_FLOW_LAYER_INNER_L3 :
3359 MLX5_FLOW_LAYER_OUTER_L3;
3360 if (!(item_flags & layer))
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION,
3364 "no IP protocol in pattern");
3370 * Validate jump action.
3373 * Pointer to the jump action.
3374 * @param[in] action_flags
3375 * Holds the actions detected until now.
3376 * @param[in] attributes
3377 * Pointer to flow attributes
3378 * @param[in] external
3379 * Action belongs to flow rule created by request external to PMD.
3381 * Pointer to error structure.
3384 * 0 on success, a negative errno value otherwise and rte_errno is set.
3387 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3388 uint64_t action_flags,
3389 const struct rte_flow_attr *attributes,
3390 bool external, struct rte_flow_error *error)
3392 uint32_t target_group, table;
3395 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3396 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3397 return rte_flow_error_set(error, EINVAL,
3398 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3399 "can't have 2 fate actions in"
3401 if (action_flags & MLX5_FLOW_ACTION_METER)
3402 return rte_flow_error_set(error, ENOTSUP,
3403 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3404 "jump with meter not support");
3406 return rte_flow_error_set(error, EINVAL,
3407 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3408 NULL, "action configuration not set");
3410 ((const struct rte_flow_action_jump *)action->conf)->group;
3411 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3412 true, &table, error);
3415 if (attributes->group == target_group)
3416 return rte_flow_error_set(error, EINVAL,
3417 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3418 "target group must be other than"
3419 " the current flow group");
3424 * Validate the port_id action.
3427 * Pointer to rte_eth_dev structure.
3428 * @param[in] action_flags
3429 * Bit-fields that holds the actions detected until now.
3431 * Port_id RTE action structure.
3433 * Attributes of flow that includes this action.
3435 * Pointer to error structure.
3438 * 0 on success, a negative errno value otherwise and rte_errno is set.
3441 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3442 uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const struct rte_flow_attr *attr,
3445 struct rte_flow_error *error)
3447 const struct rte_flow_action_port_id *port_id;
3448 struct mlx5_priv *act_priv;
3449 struct mlx5_priv *dev_priv;
3452 if (!attr->transfer)
3453 return rte_flow_error_set(error, ENOTSUP,
3454 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3456 "port id action is valid in transfer"
3458 if (!action || !action->conf)
3459 return rte_flow_error_set(error, ENOTSUP,
3460 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3462 "port id action parameters must be"
3464 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3465 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3466 return rte_flow_error_set(error, EINVAL,
3467 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3468 "can have only one fate actions in"
3470 dev_priv = mlx5_dev_to_eswitch_info(dev);
3472 return rte_flow_error_set(error, rte_errno,
3473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3475 "failed to obtain E-Switch info");
3476 port_id = action->conf;
3477 port = port_id->original ? dev->data->port_id : port_id->id;
3478 act_priv = mlx5_port_to_eswitch_info(port, false);
3480 return rte_flow_error_set
3482 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3483 "failed to obtain E-Switch port id for port");
3484 if (act_priv->domain_id != dev_priv->domain_id)
3485 return rte_flow_error_set
3487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3488 "port does not belong to"
3489 " E-Switch being configured");
3494 * Get the maximum number of modify header actions.
3497 * Pointer to rte_eth_dev structure.
3499 * Flags bits to check if root level.
3502 * Max number of modify header actions device can support.
3505 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3508 * There's no way to directly query the max cap. Although it has to be
3509 * acquried by iterative trial, it is a safe assumption that more
3510 * actions are supported by FW if extensive metadata register is
3511 * supported. (Only in the root table)
3513 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3514 return MLX5_MAX_MODIFY_NUM;
3516 return mlx5_flow_ext_mreg_supported(dev) ?
3517 MLX5_ROOT_TBL_MODIFY_NUM :
3518 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3522 * Validate the meter action.
3525 * Pointer to rte_eth_dev structure.
3526 * @param[in] action_flags
3527 * Bit-fields that holds the actions detected until now.
3529 * Pointer to the meter action.
3531 * Attributes of flow that includes this action.
3533 * Pointer to error structure.
3536 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3539 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3540 uint64_t action_flags,
3541 const struct rte_flow_action *action,
3542 const struct rte_flow_attr *attr,
3543 struct rte_flow_error *error)
3545 struct mlx5_priv *priv = dev->data->dev_private;
3546 const struct rte_flow_action_meter *am = action->conf;
3547 struct mlx5_flow_meter *fm;
3550 return rte_flow_error_set(error, EINVAL,
3551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3552 "meter action conf is NULL");
3554 if (action_flags & MLX5_FLOW_ACTION_METER)
3555 return rte_flow_error_set(error, ENOTSUP,
3556 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557 "meter chaining not support");
3558 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3559 return rte_flow_error_set(error, ENOTSUP,
3560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3561 "meter with jump not support");
3563 return rte_flow_error_set(error, ENOTSUP,
3564 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3566 "meter action not supported");
3567 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3569 return rte_flow_error_set(error, EINVAL,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3572 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3573 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3574 (!fm->attr.egress && !attr->egress && attr->ingress))))
3575 return rte_flow_error_set(error, EINVAL,
3576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3577 "Flow attributes are either invalid "
3578 "or have a conflict with current "
3579 "meter attributes");
3584 * Validate the modify-header IPv4 DSCP actions.
3586 * @param[in] action_flags
3587 * Holds the actions detected until now.
3589 * Pointer to the modify action.
3590 * @param[in] item_flags
3591 * Holds the items detected.
3593 * Pointer to error structure.
3596 * 0 on success, a negative errno value otherwise and rte_errno is set.
3599 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3600 const struct rte_flow_action *action,
3601 const uint64_t item_flags,
3602 struct rte_flow_error *error)
3606 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3608 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3609 return rte_flow_error_set(error, EINVAL,
3610 RTE_FLOW_ERROR_TYPE_ACTION,
3612 "no ipv4 item in pattern");
3618 * Validate the modify-header IPv6 DSCP actions.
3620 * @param[in] action_flags
3621 * Holds the actions detected until now.
3623 * Pointer to the modify action.
3624 * @param[in] item_flags
3625 * Holds the items detected.
3627 * Pointer to error structure.
3630 * 0 on success, a negative errno value otherwise and rte_errno is set.
3633 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3634 const struct rte_flow_action *action,
3635 const uint64_t item_flags,
3636 struct rte_flow_error *error)
3640 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3642 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3643 return rte_flow_error_set(error, EINVAL,
3644 RTE_FLOW_ERROR_TYPE_ACTION,
3646 "no ipv6 item in pattern");
3652 * Find existing modify-header resource or create and register a new one.
3654 * @param dev[in, out]
3655 * Pointer to rte_eth_dev structure.
3656 * @param[in, out] resource
3657 * Pointer to modify-header resource.
3658 * @parm[in, out] dev_flow
3659 * Pointer to the dev_flow.
3661 * pointer to error structure.
3664 * 0 on success otherwise -errno and errno is set.
3667 flow_dv_modify_hdr_resource_register
3668 (struct rte_eth_dev *dev,
3669 struct mlx5_flow_dv_modify_hdr_resource *resource,
3670 struct mlx5_flow *dev_flow,
3671 struct rte_flow_error *error)
3673 struct mlx5_priv *priv = dev->data->dev_private;
3674 struct mlx5_ibv_shared *sh = priv->sh;
3675 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3676 struct mlx5dv_dr_domain *ns;
3677 uint32_t actions_len;
3680 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3681 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3683 return rte_flow_error_set(error, EOVERFLOW,
3684 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3685 "too many modify header items");
3686 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3687 ns = sh->fdb_domain;
3688 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3692 /* Lookup a matching resource from cache. */
3693 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3694 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3695 if (resource->ft_type == cache_resource->ft_type &&
3696 resource->actions_num == cache_resource->actions_num &&
3697 resource->flags == cache_resource->flags &&
3698 !memcmp((const void *)resource->actions,
3699 (const void *)cache_resource->actions,
3701 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3702 (void *)cache_resource,
3703 rte_atomic32_read(&cache_resource->refcnt));
3704 rte_atomic32_inc(&cache_resource->refcnt);
3705 dev_flow->dv.modify_hdr = cache_resource;
3709 /* Register new modify-header resource. */
3710 cache_resource = rte_calloc(__func__, 1,
3711 sizeof(*cache_resource) + actions_len, 0);
3712 if (!cache_resource)
3713 return rte_flow_error_set(error, ENOMEM,
3714 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3715 "cannot allocate resource memory");
3716 *cache_resource = *resource;
3717 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3718 cache_resource->verbs_action =
3719 mlx5_glue->dv_create_flow_action_modify_header
3720 (sh->ctx, cache_resource->ft_type, ns,
3721 cache_resource->flags, actions_len,
3722 (uint64_t *)cache_resource->actions);
3723 if (!cache_resource->verbs_action) {
3724 rte_free(cache_resource);
3725 return rte_flow_error_set(error, ENOMEM,
3726 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3727 NULL, "cannot create action");
3729 rte_atomic32_init(&cache_resource->refcnt);
3730 rte_atomic32_inc(&cache_resource->refcnt);
3731 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3732 dev_flow->dv.modify_hdr = cache_resource;
3733 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3734 (void *)cache_resource,
3735 rte_atomic32_read(&cache_resource->refcnt));
3739 #define MLX5_CNT_CONTAINER_RESIZE 64
3742 * Get or create a flow counter.
3745 * Pointer to the Ethernet device structure.
3747 * Indicate if this counter is shared with other flows.
3749 * Counter identifier.
3752 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3754 static struct mlx5_flow_counter *
3755 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3758 struct mlx5_priv *priv = dev->data->dev_private;
3759 struct mlx5_flow_counter *cnt = NULL;
3760 struct mlx5_devx_obj *dcs = NULL;
3762 if (!priv->config.devx) {
3763 rte_errno = ENOTSUP;
3767 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3768 if (cnt->shared && cnt->id == id) {
3774 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3777 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3779 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3783 struct mlx5_flow_counter tmpl = {
3789 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3791 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3797 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3802 * Release a flow counter.
3805 * Pointer to the Ethernet device structure.
3806 * @param[in] counter
3807 * Pointer to the counter handler.
3810 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3811 struct mlx5_flow_counter *counter)
3813 struct mlx5_priv *priv = dev->data->dev_private;
3817 if (--counter->ref_cnt == 0) {
3818 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3819 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3825 * Query a devx flow counter.
3828 * Pointer to the Ethernet device structure.
3830 * Pointer to the flow counter.
3832 * The statistics value of packets.
3834 * The statistics value of bytes.
3837 * 0 on success, otherwise a negative errno value and rte_errno is set.
3840 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3841 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3844 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3849 * Get a pool by a counter.
3852 * Pointer to the counter.
3857 static struct mlx5_flow_counter_pool *
3858 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3861 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3862 return (struct mlx5_flow_counter_pool *)cnt - 1;
3868 * Get a pool by devx counter ID.
3871 * Pointer to the counter container.
3873 * The counter devx ID.
3876 * The counter pool pointer if exists, NULL otherwise,
3878 static struct mlx5_flow_counter_pool *
3879 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3881 struct mlx5_flow_counter_pool *pool;
3883 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3884 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3885 MLX5_COUNTERS_PER_POOL;
3887 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3894 * Allocate a new memory for the counter values wrapped by all the needed
3898 * Pointer to the Ethernet device structure.
3900 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3903 * The new memory management pointer on success, otherwise NULL and rte_errno
3906 static struct mlx5_counter_stats_mem_mng *
3907 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3909 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3910 (dev->data->dev_private))->sh;
3911 struct mlx5_devx_mkey_attr mkey_attr;
3912 struct mlx5_counter_stats_mem_mng *mem_mng;
3913 volatile struct flow_counter_stats *raw_data;
3914 int size = (sizeof(struct flow_counter_stats) *
3915 MLX5_COUNTERS_PER_POOL +
3916 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3917 sizeof(struct mlx5_counter_stats_mem_mng);
3918 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3925 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3926 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3927 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3928 IBV_ACCESS_LOCAL_WRITE);
3929 if (!mem_mng->umem) {
3934 mkey_attr.addr = (uintptr_t)mem;
3935 mkey_attr.size = size;
3936 mkey_attr.umem_id = mem_mng->umem->umem_id;
3937 mkey_attr.pd = sh->pdn;
3938 mkey_attr.log_entity_size = 0;
3939 mkey_attr.pg_access = 0;
3940 mkey_attr.klm_array = NULL;
3941 mkey_attr.klm_num = 0;
3942 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3944 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3949 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3950 raw_data = (volatile struct flow_counter_stats *)mem;
3951 for (i = 0; i < raws_n; ++i) {
3952 mem_mng->raws[i].mem_mng = mem_mng;
3953 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3955 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3960 * Resize a counter container.
3963 * Pointer to the Ethernet device structure.
3965 * Whether the pool is for counter that was allocated by batch command.
3968 * The new container pointer on success, otherwise NULL and rte_errno is set.
3970 static struct mlx5_pools_container *
3971 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3973 struct mlx5_priv *priv = dev->data->dev_private;
3974 struct mlx5_pools_container *cont =
3975 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3976 struct mlx5_pools_container *new_cont =
3977 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3978 struct mlx5_counter_stats_mem_mng *mem_mng;
3979 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3980 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3983 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3984 /* The last resize still hasn't detected by the host thread. */
3988 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3989 if (!new_cont->pools) {
3994 memcpy(new_cont->pools, cont->pools, cont->n *
3995 sizeof(struct mlx5_flow_counter_pool *));
3996 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3997 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3999 rte_free(new_cont->pools);
4002 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4003 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4004 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4006 new_cont->n = resize;
4007 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4008 TAILQ_INIT(&new_cont->pool_list);
4009 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4010 new_cont->init_mem_mng = mem_mng;
4012 /* Flip the master container. */
4013 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4018 * Query a devx flow counter.
4021 * Pointer to the Ethernet device structure.
4023 * Pointer to the flow counter.
4025 * The statistics value of packets.
4027 * The statistics value of bytes.
4030 * 0 on success, otherwise a negative errno value and rte_errno is set.
4033 _flow_dv_query_count(struct rte_eth_dev *dev,
4034 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4037 struct mlx5_priv *priv = dev->data->dev_private;
4038 struct mlx5_flow_counter_pool *pool =
4039 flow_dv_counter_pool_get(cnt);
4040 int offset = cnt - &pool->counters_raw[0];
4042 if (priv->counter_fallback)
4043 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4045 rte_spinlock_lock(&pool->sl);
4047 * The single counters allocation may allocate smaller ID than the
4048 * current allocated in parallel to the host reading.
4049 * In this case the new counter values must be reported as 0.
4051 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4055 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4056 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4058 rte_spinlock_unlock(&pool->sl);
4063 * Create and initialize a new counter pool.
4066 * Pointer to the Ethernet device structure.
4068 * The devX counter handle.
4070 * Whether the pool is for counter that was allocated by batch command.
4073 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4075 static struct mlx5_flow_counter_pool *
4076 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4079 struct mlx5_priv *priv = dev->data->dev_private;
4080 struct mlx5_flow_counter_pool *pool;
4081 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4083 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4086 if (cont->n == n_valid) {
4087 cont = flow_dv_container_resize(dev, batch);
4091 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4092 sizeof(struct mlx5_flow_counter);
4093 pool = rte_calloc(__func__, 1, size, 0);
4098 pool->min_dcs = dcs;
4099 pool->raw = cont->init_mem_mng->raws + n_valid %
4100 MLX5_CNT_CONTAINER_RESIZE;
4101 pool->raw_hw = NULL;
4102 rte_spinlock_init(&pool->sl);
4104 * The generation of the new allocated counters in this pool is 0, 2 in
4105 * the pool generation makes all the counters valid for allocation.
4107 rte_atomic64_set(&pool->query_gen, 0x2);
4108 TAILQ_INIT(&pool->counters);
4109 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4110 cont->pools[n_valid] = pool;
4111 /* Pool initialization must be updated before host thread access. */
4113 rte_atomic16_add(&cont->n_valid, 1);
4118 * Prepare a new counter and/or a new counter pool.
4121 * Pointer to the Ethernet device structure.
4122 * @param[out] cnt_free
4123 * Where to put the pointer of a new counter.
4125 * Whether the pool is for counter that was allocated by batch command.
4128 * The free counter pool pointer and @p cnt_free is set on success,
4129 * NULL otherwise and rte_errno is set.
4131 static struct mlx5_flow_counter_pool *
4132 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4133 struct mlx5_flow_counter **cnt_free,
4136 struct mlx5_priv *priv = dev->data->dev_private;
4137 struct mlx5_flow_counter_pool *pool;
4138 struct mlx5_devx_obj *dcs = NULL;
4139 struct mlx5_flow_counter *cnt;
4143 /* bulk_bitmap must be 0 for single counter allocation. */
4144 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4147 pool = flow_dv_find_pool_by_id
4148 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4150 pool = flow_dv_pool_create(dev, dcs, batch);
4152 mlx5_devx_cmd_destroy(dcs);
4155 } else if (dcs->id < pool->min_dcs->id) {
4156 rte_atomic64_set(&pool->a64_dcs,
4157 (int64_t)(uintptr_t)dcs);
4159 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4160 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4165 /* bulk_bitmap is in 128 counters units. */
4166 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4167 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4169 rte_errno = ENODATA;
4172 pool = flow_dv_pool_create(dev, dcs, batch);
4174 mlx5_devx_cmd_destroy(dcs);
4177 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4178 cnt = &pool->counters_raw[i];
4180 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4182 *cnt_free = &pool->counters_raw[0];
4187 * Search for existed shared counter.
4190 * Pointer to the relevant counter pool container.
4192 * The shared counter ID to search.
4195 * NULL if not existed, otherwise pointer to the shared counter.
4197 static struct mlx5_flow_counter *
4198 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4201 static struct mlx5_flow_counter *cnt;
4202 struct mlx5_flow_counter_pool *pool;
4205 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4206 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4207 cnt = &pool->counters_raw[i];
4208 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4216 * Allocate a flow counter.
4219 * Pointer to the Ethernet device structure.
4221 * Indicate if this counter is shared with other flows.
4223 * Counter identifier.
4225 * Counter flow group.
4228 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4230 static struct mlx5_flow_counter *
4231 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4234 struct mlx5_priv *priv = dev->data->dev_private;
4235 struct mlx5_flow_counter_pool *pool = NULL;
4236 struct mlx5_flow_counter *cnt_free = NULL;
4238 * Currently group 0 flow counter cannot be assigned to a flow if it is
4239 * not the first one in the batch counter allocation, so it is better
4240 * to allocate counters one by one for these flows in a separate
4242 * A counter can be shared between different groups so need to take
4243 * shared counters from the single container.
4245 uint32_t batch = (group && !shared) ? 1 : 0;
4246 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4249 if (priv->counter_fallback)
4250 return flow_dv_counter_alloc_fallback(dev, shared, id);
4251 if (!priv->config.devx) {
4252 rte_errno = ENOTSUP;
4256 cnt_free = flow_dv_counter_shared_search(cont, id);
4258 if (cnt_free->ref_cnt + 1 == 0) {
4262 cnt_free->ref_cnt++;
4266 /* Pools which has a free counters are in the start. */
4267 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4269 * The free counter reset values must be updated between the
4270 * counter release to the counter allocation, so, at least one
4271 * query must be done in this time. ensure it by saving the
4272 * query generation in the release time.
4273 * The free list is sorted according to the generation - so if
4274 * the first one is not updated, all the others are not
4277 cnt_free = TAILQ_FIRST(&pool->counters);
4278 if (cnt_free && cnt_free->query_gen + 1 <
4279 rte_atomic64_read(&pool->query_gen))
4284 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4288 cnt_free->batch = batch;
4289 /* Create a DV counter action only in the first time usage. */
4290 if (!cnt_free->action) {
4292 struct mlx5_devx_obj *dcs;
4295 offset = cnt_free - &pool->counters_raw[0];
4296 dcs = pool->min_dcs;
4299 dcs = cnt_free->dcs;
4301 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4303 if (!cnt_free->action) {
4308 /* Update the counter reset values. */
4309 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4312 cnt_free->shared = shared;
4313 cnt_free->ref_cnt = 1;
4315 if (!priv->sh->cmng.query_thread_on)
4316 /* Start the asynchronous batch query by the host thread. */
4317 mlx5_set_query_alarm(priv->sh);
4318 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4319 if (TAILQ_EMPTY(&pool->counters)) {
4320 /* Move the pool to the end of the container pool list. */
4321 TAILQ_REMOVE(&cont->pool_list, pool, next);
4322 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4328 * Release a flow counter.
4331 * Pointer to the Ethernet device structure.
4332 * @param[in] counter
4333 * Pointer to the counter handler.
4336 flow_dv_counter_release(struct rte_eth_dev *dev,
4337 struct mlx5_flow_counter *counter)
4339 struct mlx5_priv *priv = dev->data->dev_private;
4343 if (priv->counter_fallback) {
4344 flow_dv_counter_release_fallback(dev, counter);
4347 if (--counter->ref_cnt == 0) {
4348 struct mlx5_flow_counter_pool *pool =
4349 flow_dv_counter_pool_get(counter);
4351 /* Put the counter in the end - the last updated one. */
4352 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4353 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4358 * Verify the @p attributes will be correctly understood by the NIC and store
4359 * them in the @p flow if everything is correct.
4362 * Pointer to dev struct.
4363 * @param[in] attributes
4364 * Pointer to flow attributes
4365 * @param[in] external
4366 * This flow rule is created by request external to PMD.
4368 * Pointer to error structure.
4371 * 0 on success, a negative errno value otherwise and rte_errno is set.
4374 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4375 const struct rte_flow_attr *attributes,
4376 bool external __rte_unused,
4377 struct rte_flow_error *error)
4379 struct mlx5_priv *priv = dev->data->dev_private;
4380 uint32_t priority_max = priv->config.flow_prio - 1;
4382 #ifndef HAVE_MLX5DV_DR
4383 if (attributes->group)
4384 return rte_flow_error_set(error, ENOTSUP,
4385 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4387 "groups are not supported");
4392 ret = mlx5_flow_group_to_table(attributes, external,
4393 attributes->group, !!priv->fdb_def_rule,
4398 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4399 attributes->priority >= priority_max)
4400 return rte_flow_error_set(error, ENOTSUP,
4401 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4403 "priority out of range");
4404 if (attributes->transfer) {
4405 if (!priv->config.dv_esw_en)
4406 return rte_flow_error_set
4408 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4409 "E-Switch dr is not supported");
4410 if (!(priv->representor || priv->master))
4411 return rte_flow_error_set
4412 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4413 NULL, "E-Switch configuration can only be"
4414 " done by a master or a representor device");
4415 if (attributes->egress)
4416 return rte_flow_error_set
4418 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4419 "egress is not supported");
4421 if (!(attributes->egress ^ attributes->ingress))
4422 return rte_flow_error_set(error, ENOTSUP,
4423 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4424 "must specify exactly one of "
4425 "ingress or egress");
4430 * Internal validation function. For validating both actions and items.
4433 * Pointer to the rte_eth_dev structure.
4435 * Pointer to the flow attributes.
4437 * Pointer to the list of items.
4438 * @param[in] actions
4439 * Pointer to the list of actions.
4440 * @param[in] external
4441 * This flow rule is created by request external to PMD.
4443 * Pointer to the error structure.
4446 * 0 on success, a negative errno value otherwise and rte_errno is set.
4449 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4450 const struct rte_flow_item items[],
4451 const struct rte_flow_action actions[],
4452 bool external, struct rte_flow_error *error)
4455 uint64_t action_flags = 0;
4456 uint64_t item_flags = 0;
4457 uint64_t last_item = 0;
4458 uint8_t next_protocol = 0xff;
4459 uint16_t ether_type = 0;
4461 uint8_t item_ipv6_proto = 0;
4462 const struct rte_flow_item *gre_item = NULL;
4463 const struct rte_flow_action_raw_decap *decap;
4464 const struct rte_flow_action_raw_encap *encap;
4465 const struct rte_flow_action_rss *rss;
4466 struct rte_flow_item_tcp nic_tcp_mask = {
4469 .src_port = RTE_BE16(UINT16_MAX),
4470 .dst_port = RTE_BE16(UINT16_MAX),
4473 struct mlx5_priv *priv = dev->data->dev_private;
4474 struct mlx5_dev_config *dev_conf = &priv->config;
4475 uint16_t queue_index = 0xFFFF;
4479 ret = flow_dv_validate_attributes(dev, attr, external, error);
4482 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4483 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4484 int type = items->type;
4487 case RTE_FLOW_ITEM_TYPE_VOID:
4489 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4490 ret = flow_dv_validate_item_port_id
4491 (dev, items, attr, item_flags, error);
4494 last_item = MLX5_FLOW_ITEM_PORT_ID;
4496 case RTE_FLOW_ITEM_TYPE_ETH:
4497 ret = mlx5_flow_validate_item_eth(items, item_flags,
4501 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4502 MLX5_FLOW_LAYER_OUTER_L2;
4503 if (items->mask != NULL && items->spec != NULL) {
4505 ((const struct rte_flow_item_eth *)
4508 ((const struct rte_flow_item_eth *)
4510 ether_type = rte_be_to_cpu_16(ether_type);
4515 case RTE_FLOW_ITEM_TYPE_VLAN:
4516 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4520 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4521 MLX5_FLOW_LAYER_OUTER_VLAN;
4522 if (items->mask != NULL && items->spec != NULL) {
4524 ((const struct rte_flow_item_vlan *)
4525 items->spec)->inner_type;
4527 ((const struct rte_flow_item_vlan *)
4528 items->mask)->inner_type;
4529 ether_type = rte_be_to_cpu_16(ether_type);
4534 case RTE_FLOW_ITEM_TYPE_IPV4:
4535 mlx5_flow_tunnel_ip_check(items, next_protocol,
4536 &item_flags, &tunnel);
4537 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4543 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4544 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4545 if (items->mask != NULL &&
4546 ((const struct rte_flow_item_ipv4 *)
4547 items->mask)->hdr.next_proto_id) {
4549 ((const struct rte_flow_item_ipv4 *)
4550 (items->spec))->hdr.next_proto_id;
4552 ((const struct rte_flow_item_ipv4 *)
4553 (items->mask))->hdr.next_proto_id;
4555 /* Reset for inner layer. */
4556 next_protocol = 0xff;
4559 case RTE_FLOW_ITEM_TYPE_IPV6:
4560 mlx5_flow_tunnel_ip_check(items, next_protocol,
4561 &item_flags, &tunnel);
4562 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4568 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4569 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4570 if (items->mask != NULL &&
4571 ((const struct rte_flow_item_ipv6 *)
4572 items->mask)->hdr.proto) {
4574 ((const struct rte_flow_item_ipv6 *)
4575 items->spec)->hdr.proto;
4577 ((const struct rte_flow_item_ipv6 *)
4578 items->spec)->hdr.proto;
4580 ((const struct rte_flow_item_ipv6 *)
4581 items->mask)->hdr.proto;
4583 /* Reset for inner layer. */
4584 next_protocol = 0xff;
4587 case RTE_FLOW_ITEM_TYPE_TCP:
4588 ret = mlx5_flow_validate_item_tcp
4595 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4596 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4598 case RTE_FLOW_ITEM_TYPE_UDP:
4599 ret = mlx5_flow_validate_item_udp(items, item_flags,
4604 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4605 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4607 case RTE_FLOW_ITEM_TYPE_GRE:
4608 ret = mlx5_flow_validate_item_gre(items, item_flags,
4609 next_protocol, error);
4613 last_item = MLX5_FLOW_LAYER_GRE;
4615 case RTE_FLOW_ITEM_TYPE_NVGRE:
4616 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4621 last_item = MLX5_FLOW_LAYER_NVGRE;
4623 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4624 ret = mlx5_flow_validate_item_gre_key
4625 (items, item_flags, gre_item, error);
4628 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4630 case RTE_FLOW_ITEM_TYPE_VXLAN:
4631 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4635 last_item = MLX5_FLOW_LAYER_VXLAN;
4637 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4638 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4643 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4645 case RTE_FLOW_ITEM_TYPE_GENEVE:
4646 ret = mlx5_flow_validate_item_geneve(items,
4651 last_item = MLX5_FLOW_LAYER_GENEVE;
4653 case RTE_FLOW_ITEM_TYPE_MPLS:
4654 ret = mlx5_flow_validate_item_mpls(dev, items,
4659 last_item = MLX5_FLOW_LAYER_MPLS;
4662 case RTE_FLOW_ITEM_TYPE_MARK:
4663 ret = flow_dv_validate_item_mark(dev, items, attr,
4667 last_item = MLX5_FLOW_ITEM_MARK;
4669 case RTE_FLOW_ITEM_TYPE_META:
4670 ret = flow_dv_validate_item_meta(dev, items, attr,
4674 last_item = MLX5_FLOW_ITEM_METADATA;
4676 case RTE_FLOW_ITEM_TYPE_ICMP:
4677 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4682 last_item = MLX5_FLOW_LAYER_ICMP;
4684 case RTE_FLOW_ITEM_TYPE_ICMP6:
4685 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4690 item_ipv6_proto = IPPROTO_ICMPV6;
4691 last_item = MLX5_FLOW_LAYER_ICMP6;
4693 case RTE_FLOW_ITEM_TYPE_TAG:
4694 ret = flow_dv_validate_item_tag(dev, items,
4698 last_item = MLX5_FLOW_ITEM_TAG;
4700 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4701 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4703 case RTE_FLOW_ITEM_TYPE_GTP:
4704 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4708 last_item = MLX5_FLOW_LAYER_GTP;
4711 return rte_flow_error_set(error, ENOTSUP,
4712 RTE_FLOW_ERROR_TYPE_ITEM,
4713 NULL, "item not supported");
4715 item_flags |= last_item;
4717 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4718 int type = actions->type;
4719 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4720 return rte_flow_error_set(error, ENOTSUP,
4721 RTE_FLOW_ERROR_TYPE_ACTION,
4722 actions, "too many actions");
4724 case RTE_FLOW_ACTION_TYPE_VOID:
4726 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4727 ret = flow_dv_validate_action_port_id(dev,
4734 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4737 case RTE_FLOW_ACTION_TYPE_FLAG:
4738 ret = flow_dv_validate_action_flag(dev, action_flags,
4742 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4743 /* Count all modify-header actions as one. */
4744 if (!(action_flags &
4745 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4747 action_flags |= MLX5_FLOW_ACTION_FLAG |
4748 MLX5_FLOW_ACTION_MARK_EXT;
4750 action_flags |= MLX5_FLOW_ACTION_FLAG;
4754 case RTE_FLOW_ACTION_TYPE_MARK:
4755 ret = flow_dv_validate_action_mark(dev, actions,
4760 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4761 /* Count all modify-header actions as one. */
4762 if (!(action_flags &
4763 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4765 action_flags |= MLX5_FLOW_ACTION_MARK |
4766 MLX5_FLOW_ACTION_MARK_EXT;
4768 action_flags |= MLX5_FLOW_ACTION_MARK;
4772 case RTE_FLOW_ACTION_TYPE_SET_META:
4773 ret = flow_dv_validate_action_set_meta(dev, actions,
4778 /* Count all modify-header actions as one action. */
4779 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4781 action_flags |= MLX5_FLOW_ACTION_SET_META;
4783 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4784 ret = flow_dv_validate_action_set_tag(dev, actions,
4789 /* Count all modify-header actions as one action. */
4790 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4792 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4794 case RTE_FLOW_ACTION_TYPE_DROP:
4795 ret = mlx5_flow_validate_action_drop(action_flags,
4799 action_flags |= MLX5_FLOW_ACTION_DROP;
4802 case RTE_FLOW_ACTION_TYPE_QUEUE:
4803 ret = mlx5_flow_validate_action_queue(actions,
4808 queue_index = ((const struct rte_flow_action_queue *)
4809 (actions->conf))->index;
4810 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4813 case RTE_FLOW_ACTION_TYPE_RSS:
4814 rss = actions->conf;
4815 ret = mlx5_flow_validate_action_rss(actions,
4821 if (rss != NULL && rss->queue_num)
4822 queue_index = rss->queue[0];
4823 action_flags |= MLX5_FLOW_ACTION_RSS;
4826 case RTE_FLOW_ACTION_TYPE_COUNT:
4827 ret = flow_dv_validate_action_count(dev, error);
4830 action_flags |= MLX5_FLOW_ACTION_COUNT;
4833 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4834 if (flow_dv_validate_action_pop_vlan(dev,
4840 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4843 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4844 ret = flow_dv_validate_action_push_vlan(action_flags,
4850 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4853 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4854 ret = flow_dv_validate_action_set_vlan_pcp
4855 (action_flags, actions, error);
4858 /* Count PCP with push_vlan command. */
4859 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4861 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4862 ret = flow_dv_validate_action_set_vlan_vid
4863 (item_flags, action_flags,
4867 /* Count VID with push_vlan command. */
4868 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4870 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4871 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4872 ret = flow_dv_validate_action_l2_encap(action_flags,
4876 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4879 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4880 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4881 ret = flow_dv_validate_action_decap(action_flags, attr,
4885 action_flags |= MLX5_FLOW_ACTION_DECAP;
4888 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4889 ret = flow_dv_validate_action_raw_encap_decap
4890 (NULL, actions->conf, attr, &action_flags,
4895 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4896 decap = actions->conf;
4897 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4899 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4903 encap = actions->conf;
4905 ret = flow_dv_validate_action_raw_encap_decap
4906 (decap ? decap : &empty_decap, encap,
4907 attr, &action_flags, &actions_n,
4912 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4913 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4914 ret = flow_dv_validate_action_modify_mac(action_flags,
4920 /* Count all modify-header actions as one action. */
4921 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4923 action_flags |= actions->type ==
4924 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4925 MLX5_FLOW_ACTION_SET_MAC_SRC :
4926 MLX5_FLOW_ACTION_SET_MAC_DST;
4929 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4930 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4931 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4937 /* Count all modify-header actions as one action. */
4938 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4940 action_flags |= actions->type ==
4941 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4942 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4943 MLX5_FLOW_ACTION_SET_IPV4_DST;
4945 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4946 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4947 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4953 if (item_ipv6_proto == IPPROTO_ICMPV6)
4954 return rte_flow_error_set(error, ENOTSUP,
4955 RTE_FLOW_ERROR_TYPE_ACTION,
4957 "Can't change header "
4958 "with ICMPv6 proto");
4959 /* Count all modify-header actions as one action. */
4960 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4962 action_flags |= actions->type ==
4963 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4964 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4965 MLX5_FLOW_ACTION_SET_IPV6_DST;
4967 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4968 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4969 ret = flow_dv_validate_action_modify_tp(action_flags,
4975 /* Count all modify-header actions as one action. */
4976 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4978 action_flags |= actions->type ==
4979 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4980 MLX5_FLOW_ACTION_SET_TP_SRC :
4981 MLX5_FLOW_ACTION_SET_TP_DST;
4983 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4984 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4985 ret = flow_dv_validate_action_modify_ttl(action_flags,
4991 /* Count all modify-header actions as one action. */
4992 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4994 action_flags |= actions->type ==
4995 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4996 MLX5_FLOW_ACTION_SET_TTL :
4997 MLX5_FLOW_ACTION_DEC_TTL;
4999 case RTE_FLOW_ACTION_TYPE_JUMP:
5000 ret = flow_dv_validate_action_jump(actions,
5007 action_flags |= MLX5_FLOW_ACTION_JUMP;
5009 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5010 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5011 ret = flow_dv_validate_action_modify_tcp_seq
5018 /* Count all modify-header actions as one action. */
5019 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5021 action_flags |= actions->type ==
5022 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5023 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5024 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5026 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5027 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5028 ret = flow_dv_validate_action_modify_tcp_ack
5035 /* Count all modify-header actions as one action. */
5036 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5038 action_flags |= actions->type ==
5039 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5040 MLX5_FLOW_ACTION_INC_TCP_ACK :
5041 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5043 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5044 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5045 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5047 case RTE_FLOW_ACTION_TYPE_METER:
5048 ret = mlx5_flow_validate_action_meter(dev,
5054 action_flags |= MLX5_FLOW_ACTION_METER;
5057 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5058 ret = flow_dv_validate_action_modify_ipv4_dscp
5065 /* Count all modify-header actions as one action. */
5066 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5068 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5070 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5071 ret = flow_dv_validate_action_modify_ipv6_dscp
5078 /* Count all modify-header actions as one action. */
5079 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5081 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5084 return rte_flow_error_set(error, ENOTSUP,
5085 RTE_FLOW_ERROR_TYPE_ACTION,
5087 "action not supported");
5091 * Validate the drop action mutual exclusion with other actions.
5092 * Drop action is mutually-exclusive with any other action, except for
5095 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5096 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5097 return rte_flow_error_set(error, EINVAL,
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "Drop action is mutually-exclusive "
5100 "with any other action, except for "
5102 /* Eswitch has few restrictions on using items and actions */
5103 if (attr->transfer) {
5104 if (!mlx5_flow_ext_mreg_supported(dev) &&
5105 action_flags & MLX5_FLOW_ACTION_FLAG)
5106 return rte_flow_error_set(error, ENOTSUP,
5107 RTE_FLOW_ERROR_TYPE_ACTION,
5109 "unsupported action FLAG");
5110 if (!mlx5_flow_ext_mreg_supported(dev) &&
5111 action_flags & MLX5_FLOW_ACTION_MARK)
5112 return rte_flow_error_set(error, ENOTSUP,
5113 RTE_FLOW_ERROR_TYPE_ACTION,
5115 "unsupported action MARK");
5116 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5117 return rte_flow_error_set(error, ENOTSUP,
5118 RTE_FLOW_ERROR_TYPE_ACTION,
5120 "unsupported action QUEUE");
5121 if (action_flags & MLX5_FLOW_ACTION_RSS)
5122 return rte_flow_error_set(error, ENOTSUP,
5123 RTE_FLOW_ERROR_TYPE_ACTION,
5125 "unsupported action RSS");
5126 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5127 return rte_flow_error_set(error, EINVAL,
5128 RTE_FLOW_ERROR_TYPE_ACTION,
5130 "no fate action is found");
5132 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5133 return rte_flow_error_set(error, EINVAL,
5134 RTE_FLOW_ERROR_TYPE_ACTION,
5136 "no fate action is found");
5138 /* Continue validation for Xcap actions.*/
5139 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5140 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5141 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5142 MLX5_FLOW_XCAP_ACTIONS)
5143 return rte_flow_error_set(error, ENOTSUP,
5144 RTE_FLOW_ERROR_TYPE_ACTION,
5145 NULL, "encap and decap "
5146 "combination aren't supported");
5147 if (!attr->transfer && attr->ingress && (action_flags &
5148 MLX5_FLOW_ACTION_ENCAP))
5149 return rte_flow_error_set(error, ENOTSUP,
5150 RTE_FLOW_ERROR_TYPE_ACTION,
5151 NULL, "encap is not supported"
5152 " for ingress traffic");
5158 * Internal preparation function. Allocates the DV flow size,
5159 * this size is constant.
5162 * Pointer to the flow attributes.
5164 * Pointer to the list of items.
5165 * @param[in] actions
5166 * Pointer to the list of actions.
5168 * Pointer to the error structure.
5171 * Pointer to mlx5_flow object on success,
5172 * otherwise NULL and rte_errno is set.
5174 static struct mlx5_flow *
5175 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5176 const struct rte_flow_item items[] __rte_unused,
5177 const struct rte_flow_action actions[] __rte_unused,
5178 struct rte_flow_error *error)
5180 size_t size = sizeof(struct mlx5_flow);
5181 struct mlx5_flow *dev_flow;
5183 dev_flow = rte_calloc(__func__, 1, size, 0);
5185 rte_flow_error_set(error, ENOMEM,
5186 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5187 "not enough memory to create flow");
5190 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5191 dev_flow->ingress = attr->ingress;
5192 dev_flow->transfer = attr->transfer;
5196 #ifdef RTE_LIBRTE_MLX5_DEBUG
5198 * Sanity check for match mask and value. Similar to check_valid_spec() in
5199 * kernel driver. If unmasked bit is present in value, it returns failure.
5202 * pointer to match mask buffer.
5203 * @param match_value
5204 * pointer to match value buffer.
5207 * 0 if valid, -EINVAL otherwise.
5210 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5212 uint8_t *m = match_mask;
5213 uint8_t *v = match_value;
5216 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5219 "match_value differs from match_criteria"
5220 " %p[%u] != %p[%u]",
5221 match_value, i, match_mask, i);
5230 * Add Ethernet item to matcher and to the value.
5232 * @param[in, out] matcher
5234 * @param[in, out] key
5235 * Flow matcher value.
5237 * Flow pattern to translate.
5239 * Item is inner pattern.
5242 flow_dv_translate_item_eth(void *matcher, void *key,
5243 const struct rte_flow_item *item, int inner)
5245 const struct rte_flow_item_eth *eth_m = item->mask;
5246 const struct rte_flow_item_eth *eth_v = item->spec;
5247 const struct rte_flow_item_eth nic_mask = {
5248 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5249 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5250 .type = RTE_BE16(0xffff),
5262 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5264 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5266 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5268 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5270 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5271 ð_m->dst, sizeof(eth_m->dst));
5272 /* The value must be in the range of the mask. */
5273 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5274 for (i = 0; i < sizeof(eth_m->dst); ++i)
5275 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5276 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5277 ð_m->src, sizeof(eth_m->src));
5278 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5279 /* The value must be in the range of the mask. */
5280 for (i = 0; i < sizeof(eth_m->dst); ++i)
5281 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5282 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5283 rte_be_to_cpu_16(eth_m->type));
5284 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5285 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5287 /* When ethertype is present set mask for tagged VLAN. */
5288 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5289 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5290 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5291 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ))
5292 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5298 * Add VLAN item to matcher and to the value.
5300 * @param[in, out] dev_flow
5302 * @param[in, out] matcher
5304 * @param[in, out] key
5305 * Flow matcher value.
5307 * Flow pattern to translate.
5309 * Item is inner pattern.
5312 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5313 void *matcher, void *key,
5314 const struct rte_flow_item *item,
5317 const struct rte_flow_item_vlan *vlan_m = item->mask;
5318 const struct rte_flow_item_vlan *vlan_v = item->spec;
5327 vlan_m = &rte_flow_item_vlan_mask;
5329 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5331 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5333 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5335 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5337 * This is workaround, masks are not supported,
5338 * and pre-validated.
5340 dev_flow->dv.vf_vlan.tag =
5341 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5343 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5344 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5345 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5346 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5347 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5348 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5349 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5350 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5351 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5353 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5354 rte_be_to_cpu_16(vlan_m->inner_type));
5355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5356 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5360 * Add IPV4 item to matcher and to the value.
5362 * @param[in, out] matcher
5364 * @param[in, out] key
5365 * Flow matcher value.
5367 * Flow pattern to translate.
5369 * Item is inner pattern.
5371 * The group to insert the rule.
5374 flow_dv_translate_item_ipv4(void *matcher, void *key,
5375 const struct rte_flow_item *item,
5376 int inner, uint32_t group)
5378 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5379 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5380 const struct rte_flow_item_ipv4 nic_mask = {
5382 .src_addr = RTE_BE32(0xffffffff),
5383 .dst_addr = RTE_BE32(0xffffffff),
5384 .type_of_service = 0xff,
5385 .next_proto_id = 0xff,
5395 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5397 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5399 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5401 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5404 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5406 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5412 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5413 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5414 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5415 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5416 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5417 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5418 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5419 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5420 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5421 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5422 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5423 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5424 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5425 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5426 ipv4_m->hdr.type_of_service);
5427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5429 ipv4_m->hdr.type_of_service >> 2);
5430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5431 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5432 ipv4_m->hdr.next_proto_id);
5433 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5434 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5435 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5439 * Add IPV6 item to matcher and to the value.
5441 * @param[in, out] matcher
5443 * @param[in, out] key
5444 * Flow matcher value.
5446 * Flow pattern to translate.
5448 * Item is inner pattern.
5450 * The group to insert the rule.
5453 flow_dv_translate_item_ipv6(void *matcher, void *key,
5454 const struct rte_flow_item *item,
5455 int inner, uint32_t group)
5457 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5458 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5459 const struct rte_flow_item_ipv6 nic_mask = {
5462 "\xff\xff\xff\xff\xff\xff\xff\xff"
5463 "\xff\xff\xff\xff\xff\xff\xff\xff",
5465 "\xff\xff\xff\xff\xff\xff\xff\xff"
5466 "\xff\xff\xff\xff\xff\xff\xff\xff",
5467 .vtc_flow = RTE_BE32(0xffffffff),
5474 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5475 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5484 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5486 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5488 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5490 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5501 size = sizeof(ipv6_m->hdr.dst_addr);
5502 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5503 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5504 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5505 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5506 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5507 for (i = 0; i < size; ++i)
5508 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5509 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5510 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5511 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5512 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5513 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5514 for (i = 0; i < size; ++i)
5515 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5517 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5518 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5519 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5520 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5521 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5522 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5525 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5527 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5530 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5532 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5538 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5539 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5540 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5544 * Add TCP item to matcher and to the value.
5546 * @param[in, out] matcher
5548 * @param[in, out] key
5549 * Flow matcher value.
5551 * Flow pattern to translate.
5553 * Item is inner pattern.
5556 flow_dv_translate_item_tcp(void *matcher, void *key,
5557 const struct rte_flow_item *item,
5560 const struct rte_flow_item_tcp *tcp_m = item->mask;
5561 const struct rte_flow_item_tcp *tcp_v = item->spec;
5566 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5568 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5570 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5572 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5574 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5579 tcp_m = &rte_flow_item_tcp_mask;
5580 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5581 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5582 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5583 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5584 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5585 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5586 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5587 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5588 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5589 tcp_m->hdr.tcp_flags);
5590 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5591 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5595 * Add UDP item to matcher and to the value.
5597 * @param[in, out] matcher
5599 * @param[in, out] key
5600 * Flow matcher value.
5602 * Flow pattern to translate.
5604 * Item is inner pattern.
5607 flow_dv_translate_item_udp(void *matcher, void *key,
5608 const struct rte_flow_item *item,
5611 const struct rte_flow_item_udp *udp_m = item->mask;
5612 const struct rte_flow_item_udp *udp_v = item->spec;
5617 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5619 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5621 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5623 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5625 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5626 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5630 udp_m = &rte_flow_item_udp_mask;
5631 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5632 rte_be_to_cpu_16(udp_m->hdr.src_port));
5633 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5634 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5635 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5636 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5637 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5638 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5642 * Add GRE optional Key item to matcher and to the value.
5644 * @param[in, out] matcher
5646 * @param[in, out] key
5647 * Flow matcher value.
5649 * Flow pattern to translate.
5651 * Item is inner pattern.
5654 flow_dv_translate_item_gre_key(void *matcher, void *key,
5655 const struct rte_flow_item *item)
5657 const rte_be32_t *key_m = item->mask;
5658 const rte_be32_t *key_v = item->spec;
5659 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5660 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5661 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5663 /* GRE K bit must be on and should already be validated */
5664 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5665 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5669 key_m = &gre_key_default_mask;
5670 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5671 rte_be_to_cpu_32(*key_m) >> 8);
5672 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5673 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5674 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5675 rte_be_to_cpu_32(*key_m) & 0xFF);
5676 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5677 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5681 * Add GRE item to matcher and to the value.
5683 * @param[in, out] matcher
5685 * @param[in, out] key
5686 * Flow matcher value.
5688 * Flow pattern to translate.
5690 * Item is inner pattern.
5693 flow_dv_translate_item_gre(void *matcher, void *key,
5694 const struct rte_flow_item *item,
5697 const struct rte_flow_item_gre *gre_m = item->mask;
5698 const struct rte_flow_item_gre *gre_v = item->spec;
5701 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5702 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5709 uint16_t s_present:1;
5710 uint16_t k_present:1;
5711 uint16_t rsvd_bit1:1;
5712 uint16_t c_present:1;
5716 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5719 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5721 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5723 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5725 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5732 gre_m = &rte_flow_item_gre_mask;
5733 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5734 rte_be_to_cpu_16(gre_m->protocol));
5735 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5736 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5737 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5738 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5739 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5740 gre_crks_rsvd0_ver_m.c_present);
5741 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5742 gre_crks_rsvd0_ver_v.c_present &
5743 gre_crks_rsvd0_ver_m.c_present);
5744 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5745 gre_crks_rsvd0_ver_m.k_present);
5746 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5747 gre_crks_rsvd0_ver_v.k_present &
5748 gre_crks_rsvd0_ver_m.k_present);
5749 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5750 gre_crks_rsvd0_ver_m.s_present);
5751 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5752 gre_crks_rsvd0_ver_v.s_present &
5753 gre_crks_rsvd0_ver_m.s_present);
5757 * Add NVGRE item to matcher and to the value.
5759 * @param[in, out] matcher
5761 * @param[in, out] key
5762 * Flow matcher value.
5764 * Flow pattern to translate.
5766 * Item is inner pattern.
5769 flow_dv_translate_item_nvgre(void *matcher, void *key,
5770 const struct rte_flow_item *item,
5773 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5774 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5775 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5776 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5777 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5778 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5784 /* For NVGRE, GRE header fields must be set with defined values. */
5785 const struct rte_flow_item_gre gre_spec = {
5786 .c_rsvd0_ver = RTE_BE16(0x2000),
5787 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5789 const struct rte_flow_item_gre gre_mask = {
5790 .c_rsvd0_ver = RTE_BE16(0xB000),
5791 .protocol = RTE_BE16(UINT16_MAX),
5793 const struct rte_flow_item gre_item = {
5798 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5802 nvgre_m = &rte_flow_item_nvgre_mask;
5803 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5804 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5805 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5806 memcpy(gre_key_m, tni_flow_id_m, size);
5807 for (i = 0; i < size; ++i)
5808 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5812 * Add VXLAN item to matcher and to the value.
5814 * @param[in, out] matcher
5816 * @param[in, out] key
5817 * Flow matcher value.
5819 * Flow pattern to translate.
5821 * Item is inner pattern.
5824 flow_dv_translate_item_vxlan(void *matcher, void *key,
5825 const struct rte_flow_item *item,
5828 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5829 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5832 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5833 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5841 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5843 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5845 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5847 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5849 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5850 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5851 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5852 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5853 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5858 vxlan_m = &rte_flow_item_vxlan_mask;
5859 size = sizeof(vxlan_m->vni);
5860 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5861 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5862 memcpy(vni_m, vxlan_m->vni, size);
5863 for (i = 0; i < size; ++i)
5864 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5868 * Add VXLAN-GPE item to matcher and to the value.
5870 * @param[in, out] matcher
5872 * @param[in, out] key
5873 * Flow matcher value.
5875 * Flow pattern to translate.
5877 * Item is inner pattern.
5881 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5882 const struct rte_flow_item *item, int inner)
5884 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5885 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5889 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5891 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5897 uint8_t flags_m = 0xff;
5898 uint8_t flags_v = 0xc;
5901 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5903 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5905 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5907 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5909 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5910 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5911 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5912 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5913 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5918 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
5919 size = sizeof(vxlan_m->vni);
5920 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
5921 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
5922 memcpy(vni_m, vxlan_m->vni, size);
5923 for (i = 0; i < size; ++i)
5924 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5925 if (vxlan_m->flags) {
5926 flags_m = vxlan_m->flags;
5927 flags_v = vxlan_v->flags;
5929 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
5930 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
5931 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
5933 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
5938 * Add Geneve item to matcher and to the value.
5940 * @param[in, out] matcher
5942 * @param[in, out] key
5943 * Flow matcher value.
5945 * Flow pattern to translate.
5947 * Item is inner pattern.
5951 flow_dv_translate_item_geneve(void *matcher, void *key,
5952 const struct rte_flow_item *item, int inner)
5954 const struct rte_flow_item_geneve *geneve_m = item->mask;
5955 const struct rte_flow_item_geneve *geneve_v = item->spec;
5958 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5959 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5968 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5970 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5972 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5974 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5976 dport = MLX5_UDP_PORT_GENEVE;
5977 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5978 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5979 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5984 geneve_m = &rte_flow_item_geneve_mask;
5985 size = sizeof(geneve_m->vni);
5986 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5987 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5988 memcpy(vni_m, geneve_m->vni, size);
5989 for (i = 0; i < size; ++i)
5990 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5991 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5992 rte_be_to_cpu_16(geneve_m->protocol));
5993 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5994 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5995 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5996 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5997 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5998 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5999 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6000 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6001 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6002 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6003 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6004 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6005 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6009 * Add MPLS item to matcher and to the value.
6011 * @param[in, out] matcher
6013 * @param[in, out] key
6014 * Flow matcher value.
6016 * Flow pattern to translate.
6017 * @param[in] prev_layer
6018 * The protocol layer indicated in previous item.
6020 * Item is inner pattern.
6023 flow_dv_translate_item_mpls(void *matcher, void *key,
6024 const struct rte_flow_item *item,
6025 uint64_t prev_layer,
6028 const uint32_t *in_mpls_m = item->mask;
6029 const uint32_t *in_mpls_v = item->spec;
6030 uint32_t *out_mpls_m = 0;
6031 uint32_t *out_mpls_v = 0;
6032 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6033 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6034 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6036 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6037 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6038 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6040 switch (prev_layer) {
6041 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6042 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6043 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6044 MLX5_UDP_PORT_MPLS);
6046 case MLX5_FLOW_LAYER_GRE:
6047 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6048 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6049 RTE_ETHER_TYPE_MPLS);
6052 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6053 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6060 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6061 switch (prev_layer) {
6062 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6064 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6065 outer_first_mpls_over_udp);
6067 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6068 outer_first_mpls_over_udp);
6070 case MLX5_FLOW_LAYER_GRE:
6072 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6073 outer_first_mpls_over_gre);
6075 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6076 outer_first_mpls_over_gre);
6079 /* Inner MPLS not over GRE is not supported. */
6082 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6086 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6092 if (out_mpls_m && out_mpls_v) {
6093 *out_mpls_m = *in_mpls_m;
6094 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6099 * Add metadata register item to matcher
6101 * @param[in, out] matcher
6103 * @param[in, out] key
6104 * Flow matcher value.
6105 * @param[in] reg_type
6106 * Type of device metadata register
6113 flow_dv_match_meta_reg(void *matcher, void *key,
6114 enum modify_reg reg_type,
6115 uint32_t data, uint32_t mask)
6118 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6120 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6126 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6127 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6130 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6131 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6135 * The metadata register C0 field might be divided into
6136 * source vport index and META item value, we should set
6137 * this field according to specified mask, not as whole one.
6139 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6141 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6142 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6145 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6148 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6149 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6152 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6153 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6156 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6157 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6160 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6161 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6164 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6165 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6168 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6169 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6172 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6173 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6182 * Add MARK item to matcher
6185 * The device to configure through.
6186 * @param[in, out] matcher
6188 * @param[in, out] key
6189 * Flow matcher value.
6191 * Flow pattern to translate.
6194 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6195 void *matcher, void *key,
6196 const struct rte_flow_item *item)
6198 struct mlx5_priv *priv = dev->data->dev_private;
6199 const struct rte_flow_item_mark *mark;
6203 mark = item->mask ? (const void *)item->mask :
6204 &rte_flow_item_mark_mask;
6205 mask = mark->id & priv->sh->dv_mark_mask;
6206 mark = (const void *)item->spec;
6208 value = mark->id & priv->sh->dv_mark_mask & mask;
6210 enum modify_reg reg;
6212 /* Get the metadata register index for the mark. */
6213 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6214 MLX5_ASSERT(reg > 0);
6215 if (reg == REG_C_0) {
6216 struct mlx5_priv *priv = dev->data->dev_private;
6217 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6218 uint32_t shl_c0 = rte_bsf32(msk_c0);
6224 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6229 * Add META item to matcher
6232 * The devich to configure through.
6233 * @param[in, out] matcher
6235 * @param[in, out] key
6236 * Flow matcher value.
6238 * Attributes of flow that includes this item.
6240 * Flow pattern to translate.
6243 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6244 void *matcher, void *key,
6245 const struct rte_flow_attr *attr,
6246 const struct rte_flow_item *item)
6248 const struct rte_flow_item_meta *meta_m;
6249 const struct rte_flow_item_meta *meta_v;
6251 meta_m = (const void *)item->mask;
6253 meta_m = &rte_flow_item_meta_mask;
6254 meta_v = (const void *)item->spec;
6257 uint32_t value = meta_v->data;
6258 uint32_t mask = meta_m->data;
6260 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6264 * In datapath code there is no endianness
6265 * coversions for perfromance reasons, all
6266 * pattern conversions are done in rte_flow.
6268 value = rte_cpu_to_be_32(value);
6269 mask = rte_cpu_to_be_32(mask);
6270 if (reg == REG_C_0) {
6271 struct mlx5_priv *priv = dev->data->dev_private;
6272 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6273 uint32_t shl_c0 = rte_bsf32(msk_c0);
6274 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6275 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6282 MLX5_ASSERT(msk_c0);
6283 MLX5_ASSERT(!(~msk_c0 & mask));
6285 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6290 * Add vport metadata Reg C0 item to matcher
6292 * @param[in, out] matcher
6294 * @param[in, out] key
6295 * Flow matcher value.
6297 * Flow pattern to translate.
6300 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6301 uint32_t value, uint32_t mask)
6303 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6307 * Add tag item to matcher
6310 * The devich to configure through.
6311 * @param[in, out] matcher
6313 * @param[in, out] key
6314 * Flow matcher value.
6316 * Flow pattern to translate.
6319 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6320 void *matcher, void *key,
6321 const struct rte_flow_item *item)
6323 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6324 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6325 uint32_t mask, value;
6328 value = tag_v->data;
6329 mask = tag_m ? tag_m->data : UINT32_MAX;
6330 if (tag_v->id == REG_C_0) {
6331 struct mlx5_priv *priv = dev->data->dev_private;
6332 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6333 uint32_t shl_c0 = rte_bsf32(msk_c0);
6339 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6343 * Add TAG item to matcher
6346 * The devich to configure through.
6347 * @param[in, out] matcher
6349 * @param[in, out] key
6350 * Flow matcher value.
6352 * Flow pattern to translate.
6355 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6356 void *matcher, void *key,
6357 const struct rte_flow_item *item)
6359 const struct rte_flow_item_tag *tag_v = item->spec;
6360 const struct rte_flow_item_tag *tag_m = item->mask;
6361 enum modify_reg reg;
6364 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6365 /* Get the metadata register index for the tag. */
6366 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6367 MLX5_ASSERT(reg > 0);
6368 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6372 * Add source vport match to the specified matcher.
6374 * @param[in, out] matcher
6376 * @param[in, out] key
6377 * Flow matcher value.
6379 * Source vport value to match
6384 flow_dv_translate_item_source_vport(void *matcher, void *key,
6385 int16_t port, uint16_t mask)
6387 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6388 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6390 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6391 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6395 * Translate port-id item to eswitch match on port-id.
6398 * The devich to configure through.
6399 * @param[in, out] matcher
6401 * @param[in, out] key
6402 * Flow matcher value.
6404 * Flow pattern to translate.
6407 * 0 on success, a negative errno value otherwise.
6410 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6411 void *key, const struct rte_flow_item *item)
6413 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6414 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6415 struct mlx5_priv *priv;
6418 mask = pid_m ? pid_m->id : 0xffff;
6419 id = pid_v ? pid_v->id : dev->data->port_id;
6420 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6423 /* Translate to vport field or to metadata, depending on mode. */
6424 if (priv->vport_meta_mask)
6425 flow_dv_translate_item_meta_vport(matcher, key,
6426 priv->vport_meta_tag,
6427 priv->vport_meta_mask);
6429 flow_dv_translate_item_source_vport(matcher, key,
6430 priv->vport_id, mask);
6435 * Add ICMP6 item to matcher and to the value.
6437 * @param[in, out] matcher
6439 * @param[in, out] key
6440 * Flow matcher value.
6442 * Flow pattern to translate.
6444 * Item is inner pattern.
6447 flow_dv_translate_item_icmp6(void *matcher, void *key,
6448 const struct rte_flow_item *item,
6451 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6452 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6455 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6457 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6459 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6461 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6463 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6465 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6467 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6468 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6472 icmp6_m = &rte_flow_item_icmp6_mask;
6474 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6475 * If only the protocol is specified, no need to match the frag.
6477 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6478 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6479 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6480 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6481 icmp6_v->type & icmp6_m->type);
6482 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6483 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6484 icmp6_v->code & icmp6_m->code);
6488 * Add ICMP item to matcher and to the value.
6490 * @param[in, out] matcher
6492 * @param[in, out] key
6493 * Flow matcher value.
6495 * Flow pattern to translate.
6497 * Item is inner pattern.
6500 flow_dv_translate_item_icmp(void *matcher, void *key,
6501 const struct rte_flow_item *item,
6504 const struct rte_flow_item_icmp *icmp_m = item->mask;
6505 const struct rte_flow_item_icmp *icmp_v = item->spec;
6508 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6510 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6512 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6514 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6516 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6518 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6520 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6521 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6525 icmp_m = &rte_flow_item_icmp_mask;
6527 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6528 * If only the protocol is specified, no need to match the frag.
6530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6532 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6533 icmp_m->hdr.icmp_type);
6534 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6535 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6536 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6537 icmp_m->hdr.icmp_code);
6538 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6539 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6543 * Add GTP item to matcher and to the value.
6545 * @param[in, out] matcher
6547 * @param[in, out] key
6548 * Flow matcher value.
6550 * Flow pattern to translate.
6552 * Item is inner pattern.
6555 flow_dv_translate_item_gtp(void *matcher, void *key,
6556 const struct rte_flow_item *item, int inner)
6558 const struct rte_flow_item_gtp *gtp_m = item->mask;
6559 const struct rte_flow_item_gtp *gtp_v = item->spec;
6562 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6564 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6565 uint16_t dport = RTE_GTPU_UDP_PORT;
6568 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6570 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6572 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6574 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6576 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6577 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6583 gtp_m = &rte_flow_item_gtp_mask;
6584 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6585 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6586 gtp_v->msg_type & gtp_m->msg_type);
6587 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6588 rte_be_to_cpu_32(gtp_m->teid));
6589 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6590 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6593 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6595 #define HEADER_IS_ZERO(match_criteria, headers) \
6596 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6597 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6600 * Calculate flow matcher enable bitmap.
6602 * @param match_criteria
6603 * Pointer to flow matcher criteria.
6606 * Bitmap of enabled fields.
6609 flow_dv_matcher_enable(uint32_t *match_criteria)
6611 uint8_t match_criteria_enable;
6613 match_criteria_enable =
6614 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6615 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6616 match_criteria_enable |=
6617 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6618 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6619 match_criteria_enable |=
6620 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6621 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6622 match_criteria_enable |=
6623 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6624 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6625 match_criteria_enable |=
6626 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6627 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6628 return match_criteria_enable;
6635 * @param[in, out] dev
6636 * Pointer to rte_eth_dev structure.
6637 * @param[in] table_id
6640 * Direction of the table.
6641 * @param[in] transfer
6642 * E-Switch or NIC flow.
6644 * pointer to error structure.
6647 * Returns tables resource based on the index, NULL in case of failed.
6649 static struct mlx5_flow_tbl_resource *
6650 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6651 uint32_t table_id, uint8_t egress,
6653 struct rte_flow_error *error)
6655 struct mlx5_priv *priv = dev->data->dev_private;
6656 struct mlx5_ibv_shared *sh = priv->sh;
6657 struct mlx5_flow_tbl_resource *tbl;
6658 union mlx5_flow_tbl_key table_key = {
6660 .table_id = table_id,
6662 .domain = !!transfer,
6663 .direction = !!egress,
6666 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6668 struct mlx5_flow_tbl_data_entry *tbl_data;
6673 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6675 tbl = &tbl_data->tbl;
6676 rte_atomic32_inc(&tbl->refcnt);
6679 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6681 rte_flow_error_set(error, ENOMEM,
6682 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6684 "cannot allocate flow table data entry");
6687 tbl = &tbl_data->tbl;
6688 pos = &tbl_data->entry;
6690 domain = sh->fdb_domain;
6692 domain = sh->tx_domain;
6694 domain = sh->rx_domain;
6695 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6697 rte_flow_error_set(error, ENOMEM,
6698 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6699 NULL, "cannot create flow table object");
6704 * No multi-threads now, but still better to initialize the reference
6705 * count before insert it into the hash list.
6707 rte_atomic32_init(&tbl->refcnt);
6708 /* Jump action reference count is initialized here. */
6709 rte_atomic32_init(&tbl_data->jump.refcnt);
6710 pos->key = table_key.v64;
6711 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6713 rte_flow_error_set(error, -ret,
6714 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6715 "cannot insert flow table data entry");
6716 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6719 rte_atomic32_inc(&tbl->refcnt);
6724 * Release a flow table.
6727 * Pointer to rte_eth_dev structure.
6729 * Table resource to be released.
6732 * Returns 0 if table was released, else return 1;
6735 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6736 struct mlx5_flow_tbl_resource *tbl)
6738 struct mlx5_priv *priv = dev->data->dev_private;
6739 struct mlx5_ibv_shared *sh = priv->sh;
6740 struct mlx5_flow_tbl_data_entry *tbl_data =
6741 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6745 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6746 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6748 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6750 /* remove the entry from the hash list and free memory. */
6751 mlx5_hlist_remove(sh->flow_tbls, pos);
6759 * Register the flow matcher.
6761 * @param[in, out] dev
6762 * Pointer to rte_eth_dev structure.
6763 * @param[in, out] matcher
6764 * Pointer to flow matcher.
6765 * @param[in, out] key
6766 * Pointer to flow table key.
6767 * @parm[in, out] dev_flow
6768 * Pointer to the dev_flow.
6770 * pointer to error structure.
6773 * 0 on success otherwise -errno and errno is set.
6776 flow_dv_matcher_register(struct rte_eth_dev *dev,
6777 struct mlx5_flow_dv_matcher *matcher,
6778 union mlx5_flow_tbl_key *key,
6779 struct mlx5_flow *dev_flow,
6780 struct rte_flow_error *error)
6782 struct mlx5_priv *priv = dev->data->dev_private;
6783 struct mlx5_ibv_shared *sh = priv->sh;
6784 struct mlx5_flow_dv_matcher *cache_matcher;
6785 struct mlx5dv_flow_matcher_attr dv_attr = {
6786 .type = IBV_FLOW_ATTR_NORMAL,
6787 .match_mask = (void *)&matcher->mask,
6789 struct mlx5_flow_tbl_resource *tbl;
6790 struct mlx5_flow_tbl_data_entry *tbl_data;
6792 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6793 key->domain, error);
6795 return -rte_errno; /* No need to refill the error info */
6796 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6797 /* Lookup from cache. */
6798 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6799 if (matcher->crc == cache_matcher->crc &&
6800 matcher->priority == cache_matcher->priority &&
6801 !memcmp((const void *)matcher->mask.buf,
6802 (const void *)cache_matcher->mask.buf,
6803 cache_matcher->mask.size)) {
6805 "%s group %u priority %hd use %s "
6806 "matcher %p: refcnt %d++",
6807 key->domain ? "FDB" : "NIC", key->table_id,
6808 cache_matcher->priority,
6809 key->direction ? "tx" : "rx",
6810 (void *)cache_matcher,
6811 rte_atomic32_read(&cache_matcher->refcnt));
6812 rte_atomic32_inc(&cache_matcher->refcnt);
6813 dev_flow->dv.matcher = cache_matcher;
6814 /* old matcher should not make the table ref++. */
6815 flow_dv_tbl_resource_release(dev, tbl);
6819 /* Register new matcher. */
6820 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6821 if (!cache_matcher) {
6822 flow_dv_tbl_resource_release(dev, tbl);
6823 return rte_flow_error_set(error, ENOMEM,
6824 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6825 "cannot allocate matcher memory");
6827 *cache_matcher = *matcher;
6828 dv_attr.match_criteria_enable =
6829 flow_dv_matcher_enable(cache_matcher->mask.buf);
6830 dv_attr.priority = matcher->priority;
6832 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6833 cache_matcher->matcher_object =
6834 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6835 if (!cache_matcher->matcher_object) {
6836 rte_free(cache_matcher);
6837 #ifdef HAVE_MLX5DV_DR
6838 flow_dv_tbl_resource_release(dev, tbl);
6840 return rte_flow_error_set(error, ENOMEM,
6841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6842 NULL, "cannot create matcher");
6844 /* Save the table information */
6845 cache_matcher->tbl = tbl;
6846 rte_atomic32_init(&cache_matcher->refcnt);
6847 /* only matcher ref++, table ref++ already done above in get API. */
6848 rte_atomic32_inc(&cache_matcher->refcnt);
6849 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6850 dev_flow->dv.matcher = cache_matcher;
6851 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6852 key->domain ? "FDB" : "NIC", key->table_id,
6853 cache_matcher->priority,
6854 key->direction ? "tx" : "rx", (void *)cache_matcher,
6855 rte_atomic32_read(&cache_matcher->refcnt));
6860 * Find existing tag resource or create and register a new one.
6862 * @param dev[in, out]
6863 * Pointer to rte_eth_dev structure.
6864 * @param[in, out] tag_be24
6865 * Tag value in big endian then R-shift 8.
6866 * @parm[in, out] dev_flow
6867 * Pointer to the dev_flow.
6869 * pointer to error structure.
6872 * 0 on success otherwise -errno and errno is set.
6875 flow_dv_tag_resource_register
6876 (struct rte_eth_dev *dev,
6878 struct mlx5_flow *dev_flow,
6879 struct rte_flow_error *error)
6881 struct mlx5_priv *priv = dev->data->dev_private;
6882 struct mlx5_ibv_shared *sh = priv->sh;
6883 struct mlx5_flow_dv_tag_resource *cache_resource;
6884 struct mlx5_hlist_entry *entry;
6886 /* Lookup a matching resource from cache. */
6887 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6889 cache_resource = container_of
6890 (entry, struct mlx5_flow_dv_tag_resource, entry);
6891 rte_atomic32_inc(&cache_resource->refcnt);
6892 dev_flow->dv.tag_resource = cache_resource;
6893 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6894 (void *)cache_resource,
6895 rte_atomic32_read(&cache_resource->refcnt));
6898 /* Register new resource. */
6899 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6900 if (!cache_resource)
6901 return rte_flow_error_set(error, ENOMEM,
6902 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6903 "cannot allocate resource memory");
6904 cache_resource->entry.key = (uint64_t)tag_be24;
6905 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6906 if (!cache_resource->action) {
6907 rte_free(cache_resource);
6908 return rte_flow_error_set(error, ENOMEM,
6909 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6910 NULL, "cannot create action");
6912 rte_atomic32_init(&cache_resource->refcnt);
6913 rte_atomic32_inc(&cache_resource->refcnt);
6914 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6915 mlx5_glue->destroy_flow_action(cache_resource->action);
6916 rte_free(cache_resource);
6917 return rte_flow_error_set(error, EEXIST,
6918 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6919 NULL, "cannot insert tag");
6921 dev_flow->dv.tag_resource = cache_resource;
6922 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6923 (void *)cache_resource,
6924 rte_atomic32_read(&cache_resource->refcnt));
6932 * Pointer to Ethernet device.
6934 * Pointer to mlx5_flow.
6937 * 1 while a reference on it exists, 0 when freed.
6940 flow_dv_tag_release(struct rte_eth_dev *dev,
6941 struct mlx5_flow_dv_tag_resource *tag)
6943 struct mlx5_priv *priv = dev->data->dev_private;
6944 struct mlx5_ibv_shared *sh = priv->sh;
6947 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6948 dev->data->port_id, (void *)tag,
6949 rte_atomic32_read(&tag->refcnt));
6950 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6951 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6952 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6953 DRV_LOG(DEBUG, "port %u tag %p: removed",
6954 dev->data->port_id, (void *)tag);
6962 * Translate port ID action to vport.
6965 * Pointer to rte_eth_dev structure.
6967 * Pointer to the port ID action.
6968 * @param[out] dst_port_id
6969 * The target port ID.
6971 * Pointer to the error structure.
6974 * 0 on success, a negative errno value otherwise and rte_errno is set.
6977 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6978 const struct rte_flow_action *action,
6979 uint32_t *dst_port_id,
6980 struct rte_flow_error *error)
6983 struct mlx5_priv *priv;
6984 const struct rte_flow_action_port_id *conf =
6985 (const struct rte_flow_action_port_id *)action->conf;
6987 port = conf->original ? dev->data->port_id : conf->id;
6988 priv = mlx5_port_to_eswitch_info(port, false);
6990 return rte_flow_error_set(error, -rte_errno,
6991 RTE_FLOW_ERROR_TYPE_ACTION,
6993 "No eswitch info was found for port");
6994 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6996 * This parameter is transferred to
6997 * mlx5dv_dr_action_create_dest_ib_port().
6999 *dst_port_id = priv->ibv_port;
7002 * Legacy mode, no LAG configurations is supported.
7003 * This parameter is transferred to
7004 * mlx5dv_dr_action_create_dest_vport().
7006 *dst_port_id = priv->vport_id;
7012 * Add Tx queue matcher
7015 * Pointer to the dev struct.
7016 * @param[in, out] matcher
7018 * @param[in, out] key
7019 * Flow matcher value.
7021 * Flow pattern to translate.
7023 * Item is inner pattern.
7026 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7027 void *matcher, void *key,
7028 const struct rte_flow_item *item)
7030 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7031 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7033 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7035 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7036 struct mlx5_txq_ctrl *txq;
7040 queue_m = (const void *)item->mask;
7043 queue_v = (const void *)item->spec;
7046 txq = mlx5_txq_get(dev, queue_v->queue);
7049 queue = txq->obj->sq->id;
7050 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7051 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7052 queue & queue_m->queue);
7053 mlx5_txq_release(dev, queue_v->queue);
7057 * Set the hash fields according to the @p flow information.
7059 * @param[in] dev_flow
7060 * Pointer to the mlx5_flow.
7063 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7065 struct rte_flow *flow = dev_flow->flow;
7066 uint64_t items = dev_flow->layers;
7068 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7070 dev_flow->hash_fields = 0;
7071 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7072 if (flow->rss.level >= 2) {
7073 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7077 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7078 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7079 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7080 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7081 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7082 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7083 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7085 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7087 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7088 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7089 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7090 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7091 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7092 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7093 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7095 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7098 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7099 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7100 if (rss_types & ETH_RSS_UDP) {
7101 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7102 dev_flow->hash_fields |=
7103 IBV_RX_HASH_SRC_PORT_UDP;
7104 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7105 dev_flow->hash_fields |=
7106 IBV_RX_HASH_DST_PORT_UDP;
7108 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7110 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7111 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7112 if (rss_types & ETH_RSS_TCP) {
7113 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7114 dev_flow->hash_fields |=
7115 IBV_RX_HASH_SRC_PORT_TCP;
7116 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7117 dev_flow->hash_fields |=
7118 IBV_RX_HASH_DST_PORT_TCP;
7120 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7126 * Fill the flow with DV spec, lock free
7127 * (mutex should be acquired by caller).
7130 * Pointer to rte_eth_dev structure.
7131 * @param[in, out] dev_flow
7132 * Pointer to the sub flow.
7134 * Pointer to the flow attributes.
7136 * Pointer to the list of items.
7137 * @param[in] actions
7138 * Pointer to the list of actions.
7140 * Pointer to the error structure.
7143 * 0 on success, a negative errno value otherwise and rte_errno is set.
7146 __flow_dv_translate(struct rte_eth_dev *dev,
7147 struct mlx5_flow *dev_flow,
7148 const struct rte_flow_attr *attr,
7149 const struct rte_flow_item items[],
7150 const struct rte_flow_action actions[],
7151 struct rte_flow_error *error)
7153 struct mlx5_priv *priv = dev->data->dev_private;
7154 struct mlx5_dev_config *dev_conf = &priv->config;
7155 struct rte_flow *flow = dev_flow->flow;
7156 uint64_t item_flags = 0;
7157 uint64_t last_item = 0;
7158 uint64_t action_flags = 0;
7159 uint64_t priority = attr->priority;
7160 struct mlx5_flow_dv_matcher matcher = {
7162 .size = sizeof(matcher.mask.buf),
7166 bool actions_end = false;
7168 struct mlx5_flow_dv_modify_hdr_resource res;
7169 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7170 sizeof(struct mlx5_modification_cmd) *
7171 (MLX5_MAX_MODIFY_NUM + 1)];
7173 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7174 union flow_dv_attr flow_attr = { .attr = 0 };
7176 union mlx5_flow_tbl_key tbl_key;
7177 uint32_t modify_action_position = UINT32_MAX;
7178 void *match_mask = matcher.mask.buf;
7179 void *match_value = dev_flow->dv.value.buf;
7180 uint8_t next_protocol = 0xff;
7181 struct rte_vlan_hdr vlan = { 0 };
7185 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7186 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7187 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7188 !!priv->fdb_def_rule, &table, error);
7191 dev_flow->group = table;
7193 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7194 if (priority == MLX5_FLOW_PRIO_RSVD)
7195 priority = dev_conf->flow_prio - 1;
7196 /* number of actions must be set to 0 in case of dirty stack. */
7197 mhdr_res->actions_num = 0;
7198 for (; !actions_end ; actions++) {
7199 const struct rte_flow_action_queue *queue;
7200 const struct rte_flow_action_rss *rss;
7201 const struct rte_flow_action *action = actions;
7202 const struct rte_flow_action_count *count = action->conf;
7203 const uint8_t *rss_key;
7204 const struct rte_flow_action_jump *jump_data;
7205 const struct rte_flow_action_meter *mtr;
7206 struct mlx5_flow_tbl_resource *tbl;
7207 uint32_t port_id = 0;
7208 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7209 int action_type = actions->type;
7210 const struct rte_flow_action *found_action = NULL;
7212 switch (action_type) {
7213 case RTE_FLOW_ACTION_TYPE_VOID:
7215 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7216 if (flow_dv_translate_action_port_id(dev, action,
7219 port_id_resource.port_id = port_id;
7220 if (flow_dv_port_id_action_resource_register
7221 (dev, &port_id_resource, dev_flow, error))
7223 dev_flow->dv.actions[actions_n++] =
7224 dev_flow->dv.port_id_action->action;
7225 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7227 case RTE_FLOW_ACTION_TYPE_FLAG:
7228 action_flags |= MLX5_FLOW_ACTION_FLAG;
7229 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7230 struct rte_flow_action_mark mark = {
7231 .id = MLX5_FLOW_MARK_DEFAULT,
7234 if (flow_dv_convert_action_mark(dev, &mark,
7238 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7241 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7242 if (!dev_flow->dv.tag_resource)
7243 if (flow_dv_tag_resource_register
7244 (dev, tag_be, dev_flow, error))
7246 dev_flow->dv.actions[actions_n++] =
7247 dev_flow->dv.tag_resource->action;
7249 case RTE_FLOW_ACTION_TYPE_MARK:
7250 action_flags |= MLX5_FLOW_ACTION_MARK;
7251 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7252 const struct rte_flow_action_mark *mark =
7253 (const struct rte_flow_action_mark *)
7256 if (flow_dv_convert_action_mark(dev, mark,
7260 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7264 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7265 /* Legacy (non-extensive) MARK action. */
7266 tag_be = mlx5_flow_mark_set
7267 (((const struct rte_flow_action_mark *)
7268 (actions->conf))->id);
7269 if (!dev_flow->dv.tag_resource)
7270 if (flow_dv_tag_resource_register
7271 (dev, tag_be, dev_flow, error))
7273 dev_flow->dv.actions[actions_n++] =
7274 dev_flow->dv.tag_resource->action;
7276 case RTE_FLOW_ACTION_TYPE_SET_META:
7277 if (flow_dv_convert_action_set_meta
7278 (dev, mhdr_res, attr,
7279 (const struct rte_flow_action_set_meta *)
7280 actions->conf, error))
7282 action_flags |= MLX5_FLOW_ACTION_SET_META;
7284 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7285 if (flow_dv_convert_action_set_tag
7287 (const struct rte_flow_action_set_tag *)
7288 actions->conf, error))
7290 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7292 case RTE_FLOW_ACTION_TYPE_DROP:
7293 action_flags |= MLX5_FLOW_ACTION_DROP;
7295 case RTE_FLOW_ACTION_TYPE_QUEUE:
7296 MLX5_ASSERT(flow->rss.queue);
7297 queue = actions->conf;
7298 flow->rss.queue_num = 1;
7299 (*flow->rss.queue)[0] = queue->index;
7300 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7302 case RTE_FLOW_ACTION_TYPE_RSS:
7303 MLX5_ASSERT(flow->rss.queue);
7304 rss = actions->conf;
7305 if (flow->rss.queue)
7306 memcpy((*flow->rss.queue), rss->queue,
7307 rss->queue_num * sizeof(uint16_t));
7308 flow->rss.queue_num = rss->queue_num;
7309 /* NULL RSS key indicates default RSS key. */
7310 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7311 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7313 * rss->level and rss.types should be set in advance
7314 * when expanding items for RSS.
7316 action_flags |= MLX5_FLOW_ACTION_RSS;
7318 case RTE_FLOW_ACTION_TYPE_COUNT:
7319 if (!dev_conf->devx) {
7320 rte_errno = ENOTSUP;
7323 flow->counter = flow_dv_counter_alloc(dev,
7327 if (flow->counter == NULL)
7329 dev_flow->dv.actions[actions_n++] =
7330 flow->counter->action;
7331 action_flags |= MLX5_FLOW_ACTION_COUNT;
7334 if (rte_errno == ENOTSUP)
7335 return rte_flow_error_set
7337 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7339 "count action not supported");
7341 return rte_flow_error_set
7343 RTE_FLOW_ERROR_TYPE_ACTION,
7345 "cannot create counter"
7348 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7349 dev_flow->dv.actions[actions_n++] =
7350 priv->sh->pop_vlan_action;
7351 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7353 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7354 flow_dev_get_vlan_info_from_items(items, &vlan);
7355 vlan.eth_proto = rte_be_to_cpu_16
7356 ((((const struct rte_flow_action_of_push_vlan *)
7357 actions->conf)->ethertype));
7358 found_action = mlx5_flow_find_action
7360 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7362 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7363 found_action = mlx5_flow_find_action
7365 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7367 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7368 if (flow_dv_create_action_push_vlan
7369 (dev, attr, &vlan, dev_flow, error))
7371 dev_flow->dv.actions[actions_n++] =
7372 dev_flow->dv.push_vlan_res->action;
7373 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7375 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7376 /* of_vlan_push action handled this action */
7377 MLX5_ASSERT(action_flags &
7378 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7380 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7381 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7383 flow_dev_get_vlan_info_from_items(items, &vlan);
7384 mlx5_update_vlan_vid_pcp(actions, &vlan);
7385 /* If no VLAN push - this is a modify header action */
7386 if (flow_dv_convert_action_modify_vlan_vid
7387 (mhdr_res, actions, error))
7389 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7391 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7392 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7393 if (flow_dv_create_action_l2_encap(dev, actions,
7398 dev_flow->dv.actions[actions_n++] =
7399 dev_flow->dv.encap_decap->verbs_action;
7400 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7402 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7403 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7404 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7408 dev_flow->dv.actions[actions_n++] =
7409 dev_flow->dv.encap_decap->verbs_action;
7410 action_flags |= MLX5_FLOW_ACTION_DECAP;
7412 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7413 /* Handle encap with preceding decap. */
7414 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7415 if (flow_dv_create_action_raw_encap
7416 (dev, actions, dev_flow, attr, error))
7418 dev_flow->dv.actions[actions_n++] =
7419 dev_flow->dv.encap_decap->verbs_action;
7421 /* Handle encap without preceding decap. */
7422 if (flow_dv_create_action_l2_encap
7423 (dev, actions, dev_flow, attr->transfer,
7426 dev_flow->dv.actions[actions_n++] =
7427 dev_flow->dv.encap_decap->verbs_action;
7429 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7431 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7432 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7434 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7435 if (flow_dv_create_action_l2_decap
7436 (dev, dev_flow, attr->transfer, error))
7438 dev_flow->dv.actions[actions_n++] =
7439 dev_flow->dv.encap_decap->verbs_action;
7441 /* If decap is followed by encap, handle it at encap. */
7442 action_flags |= MLX5_FLOW_ACTION_DECAP;
7444 case RTE_FLOW_ACTION_TYPE_JUMP:
7445 jump_data = action->conf;
7446 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7448 !!priv->fdb_def_rule,
7452 tbl = flow_dv_tbl_resource_get(dev, table,
7454 attr->transfer, error);
7456 return rte_flow_error_set
7458 RTE_FLOW_ERROR_TYPE_ACTION,
7460 "cannot create jump action.");
7461 if (flow_dv_jump_tbl_resource_register
7462 (dev, tbl, dev_flow, error)) {
7463 flow_dv_tbl_resource_release(dev, tbl);
7464 return rte_flow_error_set
7466 RTE_FLOW_ERROR_TYPE_ACTION,
7468 "cannot create jump action.");
7470 dev_flow->dv.actions[actions_n++] =
7471 dev_flow->dv.jump->action;
7472 action_flags |= MLX5_FLOW_ACTION_JUMP;
7474 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7475 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7476 if (flow_dv_convert_action_modify_mac
7477 (mhdr_res, actions, error))
7479 action_flags |= actions->type ==
7480 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7481 MLX5_FLOW_ACTION_SET_MAC_SRC :
7482 MLX5_FLOW_ACTION_SET_MAC_DST;
7484 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7485 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7486 if (flow_dv_convert_action_modify_ipv4
7487 (mhdr_res, actions, error))
7489 action_flags |= actions->type ==
7490 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7491 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7492 MLX5_FLOW_ACTION_SET_IPV4_DST;
7494 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7495 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7496 if (flow_dv_convert_action_modify_ipv6
7497 (mhdr_res, actions, error))
7499 action_flags |= actions->type ==
7500 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7501 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7502 MLX5_FLOW_ACTION_SET_IPV6_DST;
7504 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7505 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7506 if (flow_dv_convert_action_modify_tp
7507 (mhdr_res, actions, items,
7508 &flow_attr, !!(action_flags &
7509 MLX5_FLOW_ACTION_DECAP), error))
7511 action_flags |= actions->type ==
7512 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7513 MLX5_FLOW_ACTION_SET_TP_SRC :
7514 MLX5_FLOW_ACTION_SET_TP_DST;
7516 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7517 if (flow_dv_convert_action_modify_dec_ttl
7518 (mhdr_res, items, &flow_attr,
7520 MLX5_FLOW_ACTION_DECAP), error))
7522 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7524 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7525 if (flow_dv_convert_action_modify_ttl
7526 (mhdr_res, actions, items, &flow_attr,
7528 MLX5_FLOW_ACTION_DECAP), error))
7530 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7532 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7533 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7534 if (flow_dv_convert_action_modify_tcp_seq
7535 (mhdr_res, actions, error))
7537 action_flags |= actions->type ==
7538 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7539 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7540 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7543 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7544 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7545 if (flow_dv_convert_action_modify_tcp_ack
7546 (mhdr_res, actions, error))
7548 action_flags |= actions->type ==
7549 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7550 MLX5_FLOW_ACTION_INC_TCP_ACK :
7551 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7553 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7554 if (flow_dv_convert_action_set_reg
7555 (mhdr_res, actions, error))
7557 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7559 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7560 if (flow_dv_convert_action_copy_mreg
7561 (dev, mhdr_res, actions, error))
7563 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7565 case RTE_FLOW_ACTION_TYPE_METER:
7566 mtr = actions->conf;
7568 flow->meter = mlx5_flow_meter_attach(priv,
7572 return rte_flow_error_set(error,
7574 RTE_FLOW_ERROR_TYPE_ACTION,
7577 "or invalid parameters");
7579 /* Set the meter action. */
7580 dev_flow->dv.actions[actions_n++] =
7581 flow->meter->mfts->meter_action;
7582 action_flags |= MLX5_FLOW_ACTION_METER;
7584 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7585 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7588 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7590 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7591 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7594 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7596 case RTE_FLOW_ACTION_TYPE_END:
7598 if (mhdr_res->actions_num) {
7599 /* create modify action if needed. */
7600 if (flow_dv_modify_hdr_resource_register
7601 (dev, mhdr_res, dev_flow, error))
7603 dev_flow->dv.actions[modify_action_position] =
7604 dev_flow->dv.modify_hdr->verbs_action;
7610 if (mhdr_res->actions_num &&
7611 modify_action_position == UINT32_MAX)
7612 modify_action_position = actions_n++;
7614 dev_flow->dv.actions_n = actions_n;
7615 dev_flow->actions = action_flags;
7616 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7617 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7618 int item_type = items->type;
7620 switch (item_type) {
7621 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7622 flow_dv_translate_item_port_id(dev, match_mask,
7623 match_value, items);
7624 last_item = MLX5_FLOW_ITEM_PORT_ID;
7626 case RTE_FLOW_ITEM_TYPE_ETH:
7627 flow_dv_translate_item_eth(match_mask, match_value,
7629 matcher.priority = MLX5_PRIORITY_MAP_L2;
7630 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7631 MLX5_FLOW_LAYER_OUTER_L2;
7633 case RTE_FLOW_ITEM_TYPE_VLAN:
7634 flow_dv_translate_item_vlan(dev_flow,
7635 match_mask, match_value,
7637 matcher.priority = MLX5_PRIORITY_MAP_L2;
7638 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7639 MLX5_FLOW_LAYER_INNER_VLAN) :
7640 (MLX5_FLOW_LAYER_OUTER_L2 |
7641 MLX5_FLOW_LAYER_OUTER_VLAN);
7643 case RTE_FLOW_ITEM_TYPE_IPV4:
7644 mlx5_flow_tunnel_ip_check(items, next_protocol,
7645 &item_flags, &tunnel);
7646 flow_dv_translate_item_ipv4(match_mask, match_value,
7649 matcher.priority = MLX5_PRIORITY_MAP_L3;
7650 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7651 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7652 if (items->mask != NULL &&
7653 ((const struct rte_flow_item_ipv4 *)
7654 items->mask)->hdr.next_proto_id) {
7656 ((const struct rte_flow_item_ipv4 *)
7657 (items->spec))->hdr.next_proto_id;
7659 ((const struct rte_flow_item_ipv4 *)
7660 (items->mask))->hdr.next_proto_id;
7662 /* Reset for inner layer. */
7663 next_protocol = 0xff;
7666 case RTE_FLOW_ITEM_TYPE_IPV6:
7667 mlx5_flow_tunnel_ip_check(items, next_protocol,
7668 &item_flags, &tunnel);
7669 flow_dv_translate_item_ipv6(match_mask, match_value,
7672 matcher.priority = MLX5_PRIORITY_MAP_L3;
7673 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7674 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7675 if (items->mask != NULL &&
7676 ((const struct rte_flow_item_ipv6 *)
7677 items->mask)->hdr.proto) {
7679 ((const struct rte_flow_item_ipv6 *)
7680 items->spec)->hdr.proto;
7682 ((const struct rte_flow_item_ipv6 *)
7683 items->mask)->hdr.proto;
7685 /* Reset for inner layer. */
7686 next_protocol = 0xff;
7689 case RTE_FLOW_ITEM_TYPE_TCP:
7690 flow_dv_translate_item_tcp(match_mask, match_value,
7692 matcher.priority = MLX5_PRIORITY_MAP_L4;
7693 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7694 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7696 case RTE_FLOW_ITEM_TYPE_UDP:
7697 flow_dv_translate_item_udp(match_mask, match_value,
7699 matcher.priority = MLX5_PRIORITY_MAP_L4;
7700 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7701 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7703 case RTE_FLOW_ITEM_TYPE_GRE:
7704 flow_dv_translate_item_gre(match_mask, match_value,
7706 matcher.priority = flow->rss.level >= 2 ?
7707 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7708 last_item = MLX5_FLOW_LAYER_GRE;
7710 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7711 flow_dv_translate_item_gre_key(match_mask,
7712 match_value, items);
7713 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7715 case RTE_FLOW_ITEM_TYPE_NVGRE:
7716 flow_dv_translate_item_nvgre(match_mask, match_value,
7718 matcher.priority = flow->rss.level >= 2 ?
7719 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7720 last_item = MLX5_FLOW_LAYER_GRE;
7722 case RTE_FLOW_ITEM_TYPE_VXLAN:
7723 flow_dv_translate_item_vxlan(match_mask, match_value,
7725 matcher.priority = flow->rss.level >= 2 ?
7726 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7727 last_item = MLX5_FLOW_LAYER_VXLAN;
7729 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7730 flow_dv_translate_item_vxlan_gpe(match_mask,
7733 matcher.priority = flow->rss.level >= 2 ?
7734 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7735 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7737 case RTE_FLOW_ITEM_TYPE_GENEVE:
7738 flow_dv_translate_item_geneve(match_mask, match_value,
7740 matcher.priority = flow->rss.level >= 2 ?
7741 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7742 last_item = MLX5_FLOW_LAYER_GENEVE;
7744 case RTE_FLOW_ITEM_TYPE_MPLS:
7745 flow_dv_translate_item_mpls(match_mask, match_value,
7746 items, last_item, tunnel);
7747 matcher.priority = flow->rss.level >= 2 ?
7748 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7749 last_item = MLX5_FLOW_LAYER_MPLS;
7751 case RTE_FLOW_ITEM_TYPE_MARK:
7752 flow_dv_translate_item_mark(dev, match_mask,
7753 match_value, items);
7754 last_item = MLX5_FLOW_ITEM_MARK;
7756 case RTE_FLOW_ITEM_TYPE_META:
7757 flow_dv_translate_item_meta(dev, match_mask,
7758 match_value, attr, items);
7759 last_item = MLX5_FLOW_ITEM_METADATA;
7761 case RTE_FLOW_ITEM_TYPE_ICMP:
7762 flow_dv_translate_item_icmp(match_mask, match_value,
7764 last_item = MLX5_FLOW_LAYER_ICMP;
7766 case RTE_FLOW_ITEM_TYPE_ICMP6:
7767 flow_dv_translate_item_icmp6(match_mask, match_value,
7769 last_item = MLX5_FLOW_LAYER_ICMP6;
7771 case RTE_FLOW_ITEM_TYPE_TAG:
7772 flow_dv_translate_item_tag(dev, match_mask,
7773 match_value, items);
7774 last_item = MLX5_FLOW_ITEM_TAG;
7776 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7777 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7778 match_value, items);
7779 last_item = MLX5_FLOW_ITEM_TAG;
7781 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7782 flow_dv_translate_item_tx_queue(dev, match_mask,
7785 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7787 case RTE_FLOW_ITEM_TYPE_GTP:
7788 flow_dv_translate_item_gtp(match_mask, match_value,
7790 matcher.priority = flow->rss.level >= 2 ?
7791 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7792 last_item = MLX5_FLOW_LAYER_GTP;
7797 item_flags |= last_item;
7800 * When E-Switch mode is enabled, we have two cases where we need to
7801 * set the source port manually.
7802 * The first one, is in case of Nic steering rule, and the second is
7803 * E-Switch rule where no port_id item was found. In both cases
7804 * the source port is set according the current port in use.
7806 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7807 (priv->representor || priv->master)) {
7808 if (flow_dv_translate_item_port_id(dev, match_mask,
7812 #ifdef RTE_LIBRTE_MLX5_DEBUG
7813 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7814 dev_flow->dv.value.buf));
7816 dev_flow->layers = item_flags;
7817 if (action_flags & MLX5_FLOW_ACTION_RSS)
7818 flow_dv_hashfields_set(dev_flow);
7819 /* Register matcher. */
7820 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7822 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7824 /* reserved field no needs to be set to 0 here. */
7825 tbl_key.domain = attr->transfer;
7826 tbl_key.direction = attr->egress;
7827 tbl_key.table_id = dev_flow->group;
7828 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7834 * Apply the flow to the NIC, lock free,
7835 * (mutex should be acquired by caller).
7838 * Pointer to the Ethernet device structure.
7839 * @param[in, out] flow
7840 * Pointer to flow structure.
7842 * Pointer to error structure.
7845 * 0 on success, a negative errno value otherwise and rte_errno is set.
7848 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7849 struct rte_flow_error *error)
7851 struct mlx5_flow_dv *dv;
7852 struct mlx5_flow *dev_flow;
7853 struct mlx5_priv *priv = dev->data->dev_private;
7857 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7860 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7861 if (dev_flow->transfer) {
7862 dv->actions[n++] = priv->sh->esw_drop_action;
7864 dv->hrxq = mlx5_hrxq_drop_new(dev);
7868 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7870 "cannot get drop hash queue");
7873 dv->actions[n++] = dv->hrxq->action;
7875 } else if (dev_flow->actions &
7876 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7877 struct mlx5_hrxq *hrxq;
7879 MLX5_ASSERT(flow->rss.queue);
7880 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7881 MLX5_RSS_HASH_KEY_LEN,
7882 dev_flow->hash_fields,
7884 flow->rss.queue_num);
7886 hrxq = mlx5_hrxq_new
7887 (dev, flow->rss.key,
7888 MLX5_RSS_HASH_KEY_LEN,
7889 dev_flow->hash_fields,
7891 flow->rss.queue_num,
7892 !!(dev_flow->layers &
7893 MLX5_FLOW_LAYER_TUNNEL));
7898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7899 "cannot get hash queue");
7903 dv->actions[n++] = dv->hrxq->action;
7906 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7907 (void *)&dv->value, n,
7910 rte_flow_error_set(error, errno,
7911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7913 "hardware refuses to create flow");
7916 if (priv->vmwa_context &&
7917 dev_flow->dv.vf_vlan.tag &&
7918 !dev_flow->dv.vf_vlan.created) {
7920 * The rule contains the VLAN pattern.
7921 * For VF we are going to create VLAN
7922 * interface to make hypervisor set correct
7923 * e-Switch vport context.
7925 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7930 err = rte_errno; /* Save rte_errno before cleanup. */
7931 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7932 struct mlx5_flow_dv *dv = &dev_flow->dv;
7934 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7935 mlx5_hrxq_drop_release(dev);
7937 mlx5_hrxq_release(dev, dv->hrxq);
7940 if (dev_flow->dv.vf_vlan.tag &&
7941 dev_flow->dv.vf_vlan.created)
7942 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7944 rte_errno = err; /* Restore rte_errno. */
7949 * Release the flow matcher.
7952 * Pointer to Ethernet device.
7954 * Pointer to mlx5_flow.
7957 * 1 while a reference on it exists, 0 when freed.
7960 flow_dv_matcher_release(struct rte_eth_dev *dev,
7961 struct mlx5_flow *flow)
7963 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7965 MLX5_ASSERT(matcher->matcher_object);
7966 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7967 dev->data->port_id, (void *)matcher,
7968 rte_atomic32_read(&matcher->refcnt));
7969 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7970 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7971 (matcher->matcher_object));
7972 LIST_REMOVE(matcher, next);
7973 /* table ref-- in release interface. */
7974 flow_dv_tbl_resource_release(dev, matcher->tbl);
7976 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7977 dev->data->port_id, (void *)matcher);
7984 * Release an encap/decap resource.
7987 * Pointer to mlx5_flow.
7990 * 1 while a reference on it exists, 0 when freed.
7993 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7995 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7996 flow->dv.encap_decap;
7998 MLX5_ASSERT(cache_resource->verbs_action);
7999 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8000 (void *)cache_resource,
8001 rte_atomic32_read(&cache_resource->refcnt));
8002 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8003 claim_zero(mlx5_glue->destroy_flow_action
8004 (cache_resource->verbs_action));
8005 LIST_REMOVE(cache_resource, next);
8006 rte_free(cache_resource);
8007 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8008 (void *)cache_resource);
8015 * Release an jump to table action resource.
8018 * Pointer to Ethernet device.
8020 * Pointer to mlx5_flow.
8023 * 1 while a reference on it exists, 0 when freed.
8026 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8027 struct mlx5_flow *flow)
8029 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
8030 struct mlx5_flow_tbl_data_entry *tbl_data =
8031 container_of(cache_resource,
8032 struct mlx5_flow_tbl_data_entry, jump);
8034 MLX5_ASSERT(cache_resource->action);
8035 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8036 (void *)cache_resource,
8037 rte_atomic32_read(&cache_resource->refcnt));
8038 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8039 claim_zero(mlx5_glue->destroy_flow_action
8040 (cache_resource->action));
8041 /* jump action memory free is inside the table release. */
8042 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8043 DRV_LOG(DEBUG, "jump table resource %p: removed",
8044 (void *)cache_resource);
8051 * Release a modify-header resource.
8054 * Pointer to mlx5_flow.
8057 * 1 while a reference on it exists, 0 when freed.
8060 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8062 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8063 flow->dv.modify_hdr;
8065 MLX5_ASSERT(cache_resource->verbs_action);
8066 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8067 (void *)cache_resource,
8068 rte_atomic32_read(&cache_resource->refcnt));
8069 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8070 claim_zero(mlx5_glue->destroy_flow_action
8071 (cache_resource->verbs_action));
8072 LIST_REMOVE(cache_resource, next);
8073 rte_free(cache_resource);
8074 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8075 (void *)cache_resource);
8082 * Release port ID action resource.
8085 * Pointer to mlx5_flow.
8088 * 1 while a reference on it exists, 0 when freed.
8091 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8093 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8094 flow->dv.port_id_action;
8096 MLX5_ASSERT(cache_resource->action);
8097 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8098 (void *)cache_resource,
8099 rte_atomic32_read(&cache_resource->refcnt));
8100 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8101 claim_zero(mlx5_glue->destroy_flow_action
8102 (cache_resource->action));
8103 LIST_REMOVE(cache_resource, next);
8104 rte_free(cache_resource);
8105 DRV_LOG(DEBUG, "port id action resource %p: removed",
8106 (void *)cache_resource);
8113 * Release push vlan action resource.
8116 * Pointer to mlx5_flow.
8119 * 1 while a reference on it exists, 0 when freed.
8122 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8124 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8125 flow->dv.push_vlan_res;
8127 MLX5_ASSERT(cache_resource->action);
8128 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8129 (void *)cache_resource,
8130 rte_atomic32_read(&cache_resource->refcnt));
8131 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8132 claim_zero(mlx5_glue->destroy_flow_action
8133 (cache_resource->action));
8134 LIST_REMOVE(cache_resource, next);
8135 rte_free(cache_resource);
8136 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8137 (void *)cache_resource);
8144 * Remove the flow from the NIC but keeps it in memory.
8145 * Lock free, (mutex should be acquired by caller).
8148 * Pointer to Ethernet device.
8149 * @param[in, out] flow
8150 * Pointer to flow structure.
8153 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8155 struct mlx5_flow_dv *dv;
8156 struct mlx5_flow *dev_flow;
8160 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8163 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8167 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8168 mlx5_hrxq_drop_release(dev);
8170 mlx5_hrxq_release(dev, dv->hrxq);
8173 if (dev_flow->dv.vf_vlan.tag &&
8174 dev_flow->dv.vf_vlan.created)
8175 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8180 * Remove the flow from the NIC and the memory.
8181 * Lock free, (mutex should be acquired by caller).
8184 * Pointer to the Ethernet device structure.
8185 * @param[in, out] flow
8186 * Pointer to flow structure.
8189 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8191 struct mlx5_flow *dev_flow;
8195 __flow_dv_remove(dev, flow);
8196 if (flow->counter) {
8197 flow_dv_counter_release(dev, flow->counter);
8198 flow->counter = NULL;
8201 mlx5_flow_meter_detach(flow->meter);
8204 while (!LIST_EMPTY(&flow->dev_flows)) {
8205 dev_flow = LIST_FIRST(&flow->dev_flows);
8206 LIST_REMOVE(dev_flow, next);
8207 if (dev_flow->dv.matcher)
8208 flow_dv_matcher_release(dev, dev_flow);
8209 if (dev_flow->dv.encap_decap)
8210 flow_dv_encap_decap_resource_release(dev_flow);
8211 if (dev_flow->dv.modify_hdr)
8212 flow_dv_modify_hdr_resource_release(dev_flow);
8213 if (dev_flow->dv.jump)
8214 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8215 if (dev_flow->dv.port_id_action)
8216 flow_dv_port_id_action_resource_release(dev_flow);
8217 if (dev_flow->dv.push_vlan_res)
8218 flow_dv_push_vlan_action_resource_release(dev_flow);
8219 if (dev_flow->dv.tag_resource)
8220 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8226 * Query a dv flow rule for its statistics via devx.
8229 * Pointer to Ethernet device.
8231 * Pointer to the sub flow.
8233 * data retrieved by the query.
8235 * Perform verbose error reporting if not NULL.
8238 * 0 on success, a negative errno value otherwise and rte_errno is set.
8241 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8242 void *data, struct rte_flow_error *error)
8244 struct mlx5_priv *priv = dev->data->dev_private;
8245 struct rte_flow_query_count *qc = data;
8247 if (!priv->config.devx)
8248 return rte_flow_error_set(error, ENOTSUP,
8249 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8251 "counters are not supported");
8252 if (flow->counter) {
8253 uint64_t pkts, bytes;
8254 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8258 return rte_flow_error_set(error, -err,
8259 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8260 NULL, "cannot read counters");
8263 qc->hits = pkts - flow->counter->hits;
8264 qc->bytes = bytes - flow->counter->bytes;
8266 flow->counter->hits = pkts;
8267 flow->counter->bytes = bytes;
8271 return rte_flow_error_set(error, EINVAL,
8272 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8274 "counters are not available");
8280 * @see rte_flow_query()
8284 flow_dv_query(struct rte_eth_dev *dev,
8285 struct rte_flow *flow __rte_unused,
8286 const struct rte_flow_action *actions __rte_unused,
8287 void *data __rte_unused,
8288 struct rte_flow_error *error __rte_unused)
8292 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8293 switch (actions->type) {
8294 case RTE_FLOW_ACTION_TYPE_VOID:
8296 case RTE_FLOW_ACTION_TYPE_COUNT:
8297 ret = flow_dv_query_count(dev, flow, data, error);
8300 return rte_flow_error_set(error, ENOTSUP,
8301 RTE_FLOW_ERROR_TYPE_ACTION,
8303 "action not supported");
8310 * Destroy the meter table set.
8311 * Lock free, (mutex should be acquired by caller).
8314 * Pointer to Ethernet device.
8316 * Pointer to the meter table set.
8322 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8323 struct mlx5_meter_domains_infos *tbl)
8325 struct mlx5_priv *priv = dev->data->dev_private;
8326 struct mlx5_meter_domains_infos *mtd =
8327 (struct mlx5_meter_domains_infos *)tbl;
8329 if (!mtd || !priv->config.dv_flow_en)
8331 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8332 claim_zero(mlx5_glue->dv_destroy_flow
8333 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8334 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8335 claim_zero(mlx5_glue->dv_destroy_flow
8336 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8337 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8338 claim_zero(mlx5_glue->dv_destroy_flow
8339 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8340 if (mtd->egress.color_matcher)
8341 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8342 (mtd->egress.color_matcher));
8343 if (mtd->egress.any_matcher)
8344 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8345 (mtd->egress.any_matcher));
8346 if (mtd->egress.tbl)
8347 claim_zero(flow_dv_tbl_resource_release(dev,
8349 if (mtd->ingress.color_matcher)
8350 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8351 (mtd->ingress.color_matcher));
8352 if (mtd->ingress.any_matcher)
8353 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8354 (mtd->ingress.any_matcher));
8355 if (mtd->ingress.tbl)
8356 claim_zero(flow_dv_tbl_resource_release(dev,
8358 if (mtd->transfer.color_matcher)
8359 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8360 (mtd->transfer.color_matcher));
8361 if (mtd->transfer.any_matcher)
8362 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8363 (mtd->transfer.any_matcher));
8364 if (mtd->transfer.tbl)
8365 claim_zero(flow_dv_tbl_resource_release(dev,
8366 mtd->transfer.tbl));
8368 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8373 /* Number of meter flow actions, count and jump or count and drop. */
8374 #define METER_ACTIONS 2
8377 * Create specify domain meter table and suffix table.
8380 * Pointer to Ethernet device.
8381 * @param[in,out] mtb
8382 * Pointer to DV meter table set.
8385 * @param[in] transfer
8387 * @param[in] color_reg_c_idx
8388 * Reg C index for color match.
8391 * 0 on success, -1 otherwise and rte_errno is set.
8394 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8395 struct mlx5_meter_domains_infos *mtb,
8396 uint8_t egress, uint8_t transfer,
8397 uint32_t color_reg_c_idx)
8399 struct mlx5_priv *priv = dev->data->dev_private;
8400 struct mlx5_ibv_shared *sh = priv->sh;
8401 struct mlx5_flow_dv_match_params mask = {
8402 .size = sizeof(mask.buf),
8404 struct mlx5_flow_dv_match_params value = {
8405 .size = sizeof(value.buf),
8407 struct mlx5dv_flow_matcher_attr dv_attr = {
8408 .type = IBV_FLOW_ATTR_NORMAL,
8410 .match_criteria_enable = 0,
8411 .match_mask = (void *)&mask,
8413 void *actions[METER_ACTIONS];
8414 struct mlx5_flow_tbl_resource **sfx_tbl;
8415 struct mlx5_meter_domain_info *dtb;
8416 struct rte_flow_error error;
8420 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8421 dtb = &mtb->transfer;
8422 } else if (egress) {
8423 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8426 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8427 dtb = &mtb->ingress;
8429 /* If the suffix table in missing, create it. */
8431 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8432 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8433 egress, transfer, &error);
8435 DRV_LOG(ERR, "Failed to create meter suffix table.");
8439 /* Create the meter table with METER level. */
8440 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8441 egress, transfer, &error);
8443 DRV_LOG(ERR, "Failed to create meter policer table.");
8446 /* Create matchers, Any and Color. */
8447 dv_attr.priority = 3;
8448 dv_attr.match_criteria_enable = 0;
8449 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8452 if (!dtb->any_matcher) {
8453 DRV_LOG(ERR, "Failed to create meter"
8454 " policer default matcher.");
8457 dv_attr.priority = 0;
8458 dv_attr.match_criteria_enable =
8459 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8460 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8461 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8462 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8465 if (!dtb->color_matcher) {
8466 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8469 if (mtb->count_actns[RTE_MTR_DROPPED])
8470 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8471 actions[i++] = mtb->drop_actn;
8472 /* Default rule: lowest priority, match any, actions: drop. */
8473 dtb->policer_rules[RTE_MTR_DROPPED] =
8474 mlx5_glue->dv_create_flow(dtb->any_matcher,
8475 (void *)&value, i, actions);
8476 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8477 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8486 * Create the needed meter and suffix tables.
8487 * Lock free, (mutex should be acquired by caller).
8490 * Pointer to Ethernet device.
8492 * Pointer to the flow meter.
8495 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8497 static struct mlx5_meter_domains_infos *
8498 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8499 const struct mlx5_flow_meter *fm)
8501 struct mlx5_priv *priv = dev->data->dev_private;
8502 struct mlx5_meter_domains_infos *mtb;
8506 if (!priv->mtr_en) {
8507 rte_errno = ENOTSUP;
8510 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8512 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8515 /* Create meter count actions */
8516 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8517 if (!fm->policer_stats.cnt[i])
8519 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8521 /* Create drop action. */
8522 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8523 if (!mtb->drop_actn) {
8524 DRV_LOG(ERR, "Failed to create drop action.");
8527 /* Egress meter table. */
8528 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8530 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8533 /* Ingress meter table. */
8534 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8536 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8539 /* FDB meter table. */
8540 if (priv->config.dv_esw_en) {
8541 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8542 priv->mtr_color_reg);
8544 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8550 flow_dv_destroy_mtr_tbl(dev, mtb);
8555 * Destroy domain policer rule.
8558 * Pointer to domain table.
8561 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8565 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8566 if (dt->policer_rules[i]) {
8567 claim_zero(mlx5_glue->dv_destroy_flow
8568 (dt->policer_rules[i]));
8569 dt->policer_rules[i] = NULL;
8572 if (dt->jump_actn) {
8573 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8574 dt->jump_actn = NULL;
8579 * Destroy policer rules.
8582 * Pointer to Ethernet device.
8584 * Pointer to flow meter structure.
8586 * Pointer to flow attributes.
8592 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8593 const struct mlx5_flow_meter *fm,
8594 const struct rte_flow_attr *attr)
8596 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8601 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8603 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8605 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8610 * Create specify domain meter policer rule.
8613 * Pointer to flow meter structure.
8615 * Pointer to DV meter table set.
8617 * Pointer to suffix table.
8618 * @param[in] mtr_reg_c
8619 * Color match REG_C.
8622 * 0 on success, -1 otherwise.
8625 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8626 struct mlx5_meter_domain_info *dtb,
8627 struct mlx5_flow_tbl_resource *sfx_tb,
8630 struct mlx5_flow_dv_match_params matcher = {
8631 .size = sizeof(matcher.buf),
8633 struct mlx5_flow_dv_match_params value = {
8634 .size = sizeof(value.buf),
8636 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8637 void *actions[METER_ACTIONS];
8640 /* Create jump action. */
8643 if (!dtb->jump_actn)
8645 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8647 if (!dtb->jump_actn) {
8648 DRV_LOG(ERR, "Failed to create policer jump action.");
8651 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8654 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8655 rte_col_2_mlx5_col(i), UINT8_MAX);
8656 if (mtb->count_actns[i])
8657 actions[j++] = mtb->count_actns[i];
8658 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8659 actions[j++] = mtb->drop_actn;
8661 actions[j++] = dtb->jump_actn;
8662 dtb->policer_rules[i] =
8663 mlx5_glue->dv_create_flow(dtb->color_matcher,
8666 if (!dtb->policer_rules[i]) {
8667 DRV_LOG(ERR, "Failed to create policer rule.");
8678 * Create policer rules.
8681 * Pointer to Ethernet device.
8683 * Pointer to flow meter structure.
8685 * Pointer to flow attributes.
8688 * 0 on success, -1 otherwise.
8691 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8692 struct mlx5_flow_meter *fm,
8693 const struct rte_flow_attr *attr)
8695 struct mlx5_priv *priv = dev->data->dev_private;
8696 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8700 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8701 priv->sh->tx_mtr_sfx_tbl,
8702 priv->mtr_color_reg);
8704 DRV_LOG(ERR, "Failed to create egress policer.");
8708 if (attr->ingress) {
8709 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8710 priv->sh->rx_mtr_sfx_tbl,
8711 priv->mtr_color_reg);
8713 DRV_LOG(ERR, "Failed to create ingress policer.");
8717 if (attr->transfer) {
8718 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8719 priv->sh->fdb_mtr_sfx_tbl,
8720 priv->mtr_color_reg);
8722 DRV_LOG(ERR, "Failed to create transfer policer.");
8728 flow_dv_destroy_policer_rules(dev, fm, attr);
8733 * Query a devx counter.
8736 * Pointer to the Ethernet device structure.
8738 * Pointer to the flow counter.
8740 * Set to clear the counter statistics.
8742 * The statistics value of packets.
8744 * The statistics value of bytes.
8747 * 0 on success, otherwise return -1.
8750 flow_dv_counter_query(struct rte_eth_dev *dev,
8751 struct mlx5_flow_counter *cnt, bool clear,
8752 uint64_t *pkts, uint64_t *bytes)
8754 struct mlx5_priv *priv = dev->data->dev_private;
8755 uint64_t inn_pkts, inn_bytes;
8758 if (!priv->config.devx)
8760 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8763 *pkts = inn_pkts - cnt->hits;
8764 *bytes = inn_bytes - cnt->bytes;
8766 cnt->hits = inn_pkts;
8767 cnt->bytes = inn_bytes;
8773 * Mutex-protected thunk to lock-free __flow_dv_translate().
8776 flow_dv_translate(struct rte_eth_dev *dev,
8777 struct mlx5_flow *dev_flow,
8778 const struct rte_flow_attr *attr,
8779 const struct rte_flow_item items[],
8780 const struct rte_flow_action actions[],
8781 struct rte_flow_error *error)
8785 flow_dv_shared_lock(dev);
8786 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8787 flow_dv_shared_unlock(dev);
8792 * Mutex-protected thunk to lock-free __flow_dv_apply().
8795 flow_dv_apply(struct rte_eth_dev *dev,
8796 struct rte_flow *flow,
8797 struct rte_flow_error *error)
8801 flow_dv_shared_lock(dev);
8802 ret = __flow_dv_apply(dev, flow, error);
8803 flow_dv_shared_unlock(dev);
8808 * Mutex-protected thunk to lock-free __flow_dv_remove().
8811 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8813 flow_dv_shared_lock(dev);
8814 __flow_dv_remove(dev, flow);
8815 flow_dv_shared_unlock(dev);
8819 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8822 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8824 flow_dv_shared_lock(dev);
8825 __flow_dv_destroy(dev, flow);
8826 flow_dv_shared_unlock(dev);
8830 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8832 static struct mlx5_flow_counter *
8833 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8835 struct mlx5_flow_counter *cnt;
8837 flow_dv_shared_lock(dev);
8838 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8839 flow_dv_shared_unlock(dev);
8844 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8847 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8849 flow_dv_shared_lock(dev);
8850 flow_dv_counter_release(dev, cnt);
8851 flow_dv_shared_unlock(dev);
8854 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8855 .validate = flow_dv_validate,
8856 .prepare = flow_dv_prepare,
8857 .translate = flow_dv_translate,
8858 .apply = flow_dv_apply,
8859 .remove = flow_dv_remove,
8860 .destroy = flow_dv_destroy,
8861 .query = flow_dv_query,
8862 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8863 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8864 .create_policer_rules = flow_dv_create_policer_rules,
8865 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8866 .counter_alloc = flow_dv_counter_allocate,
8867 .counter_free = flow_dv_counter_free,
8868 .counter_query = flow_dv_counter_query,
8871 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */