1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/verbs.h>
17 #pragma GCC diagnostic error "-Wpedantic"
20 #include <rte_common.h>
21 #include <rte_ether.h>
22 #include <rte_eth_ctrl.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
31 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
42 * Pointer to the rte_eth_dev structure.
46 * Attributes of flow that includes this item.
48 * Pointer to error structure.
51 * 0 on success, a negative errno value otherwise and rte_errno is set.
54 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
55 const struct rte_flow_item *item,
56 const struct rte_flow_attr *attr,
57 struct rte_flow_error *error)
59 const struct rte_flow_item_meta *spec = item->spec;
60 const struct rte_flow_item_meta *mask = item->mask;
61 const struct rte_flow_item_meta nic_mask = {
62 .data = RTE_BE32(UINT32_MAX)
65 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
67 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
68 return rte_flow_error_set(error, EPERM,
69 RTE_FLOW_ERROR_TYPE_ITEM,
71 "match on metadata offload "
72 "configuration is off for this port");
74 return rte_flow_error_set(error, EINVAL,
75 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
77 "data cannot be empty");
79 return rte_flow_error_set(error, EINVAL,
80 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
82 "data cannot be zero");
84 mask = &rte_flow_item_meta_mask;
85 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
86 (const uint8_t *)&nic_mask,
87 sizeof(struct rte_flow_item_meta),
92 return rte_flow_error_set(error, ENOTSUP,
93 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
95 "pattern not supported for ingress");
100 * Validate the L2 encap action.
102 * @param[in] action_flags
103 * Holds the actions detected until now.
105 * Pointer to the encap action.
107 * Pointer to flow attributes
109 * Pointer to error structure.
112 * 0 on success, a negative errno value otherwise and rte_errno is set.
115 flow_dv_validate_action_l2_encap(uint64_t action_flags,
116 const struct rte_flow_action *action,
117 const struct rte_flow_attr *attr,
118 struct rte_flow_error *error)
121 return rte_flow_error_set(error, EINVAL,
122 RTE_FLOW_ERROR_TYPE_ACTION, action,
123 "configuration cannot be null");
124 if (action_flags & MLX5_FLOW_ACTION_DROP)
125 return rte_flow_error_set(error, EINVAL,
126 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
127 "can't drop and encap in same flow");
128 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
129 return rte_flow_error_set(error, EINVAL,
130 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
131 "can only have a single encap or"
132 " decap action in a flow");
134 return rte_flow_error_set(error, ENOTSUP,
135 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
137 "encap action not supported for "
143 * Validate the L2 decap action.
145 * @param[in] action_flags
146 * Holds the actions detected until now.
148 * Pointer to flow attributes
150 * Pointer to error structure.
153 * 0 on success, a negative errno value otherwise and rte_errno is set.
156 flow_dv_validate_action_l2_decap(uint64_t action_flags,
157 const struct rte_flow_attr *attr,
158 struct rte_flow_error *error)
160 if (action_flags & MLX5_FLOW_ACTION_DROP)
161 return rte_flow_error_set(error, EINVAL,
162 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
163 "can't drop and decap in same flow");
164 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
165 return rte_flow_error_set(error, EINVAL,
166 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
167 "can only have a single encap or"
168 " decap action in a flow");
170 return rte_flow_error_set(error, ENOTSUP,
171 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
173 "decap action not supported for "
179 * Validate the raw encap action.
181 * @param[in] action_flags
182 * Holds the actions detected until now.
184 * Pointer to the encap action.
186 * Pointer to flow attributes
188 * Pointer to error structure.
191 * 0 on success, a negative errno value otherwise and rte_errno is set.
194 flow_dv_validate_action_raw_encap(uint64_t action_flags,
195 const struct rte_flow_action *action,
196 const struct rte_flow_attr *attr,
197 struct rte_flow_error *error)
200 return rte_flow_error_set(error, EINVAL,
201 RTE_FLOW_ERROR_TYPE_ACTION, action,
202 "configuration cannot be null");
203 if (action_flags & MLX5_FLOW_ACTION_DROP)
204 return rte_flow_error_set(error, EINVAL,
205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
206 "can't drop and encap in same flow");
207 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
208 return rte_flow_error_set(error, EINVAL,
209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
210 "can only have a single encap"
211 " action in a flow");
212 /* encap without preceding decap is not supported for ingress */
213 if (attr->ingress && !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
214 return rte_flow_error_set(error, ENOTSUP,
215 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
217 "encap action not supported for "
223 * Validate the raw decap action.
225 * @param[in] action_flags
226 * Holds the actions detected until now.
228 * Pointer to the encap action.
230 * Pointer to flow attributes
232 * Pointer to error structure.
235 * 0 on success, a negative errno value otherwise and rte_errno is set.
238 flow_dv_validate_action_raw_decap(uint64_t action_flags,
239 const struct rte_flow_action *action,
240 const struct rte_flow_attr *attr,
241 struct rte_flow_error *error)
243 if (action_flags & MLX5_FLOW_ACTION_DROP)
244 return rte_flow_error_set(error, EINVAL,
245 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
246 "can't drop and decap in same flow");
247 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
248 return rte_flow_error_set(error, EINVAL,
249 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
250 "can't have encap action before"
252 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
253 return rte_flow_error_set(error, EINVAL,
254 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
255 "can only have a single decap"
256 " action in a flow");
257 /* decap action is valid on egress only if it is followed by encap */
259 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
260 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
263 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
264 return rte_flow_error_set
266 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
267 NULL, "decap action not supported"
275 * Find existing encap/decap resource or create and register a new one.
277 * @param dev[in, out]
278 * Pointer to rte_eth_dev structure.
279 * @param[in, out] resource
280 * Pointer to encap/decap resource.
281 * @parm[in, out] dev_flow
282 * Pointer to the dev_flow.
284 * pointer to error structure.
287 * 0 on success otherwise -errno and errno is set.
290 flow_dv_encap_decap_resource_register
291 (struct rte_eth_dev *dev,
292 struct mlx5_flow_dv_encap_decap_resource *resource,
293 struct mlx5_flow *dev_flow,
294 struct rte_flow_error *error)
296 struct priv *priv = dev->data->dev_private;
297 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
299 /* Lookup a matching resource from cache. */
300 LIST_FOREACH(cache_resource, &priv->encaps_decaps, next) {
301 if (resource->reformat_type == cache_resource->reformat_type &&
302 resource->ft_type == cache_resource->ft_type &&
303 resource->size == cache_resource->size &&
304 !memcmp((const void *)resource->buf,
305 (const void *)cache_resource->buf,
307 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
308 (void *)cache_resource,
309 rte_atomic32_read(&cache_resource->refcnt));
310 rte_atomic32_inc(&cache_resource->refcnt);
311 dev_flow->dv.encap_decap = cache_resource;
315 /* Register new encap/decap resource. */
316 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
318 return rte_flow_error_set(error, ENOMEM,
319 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
320 "cannot allocate resource memory");
321 *cache_resource = *resource;
322 cache_resource->verbs_action =
323 mlx5_glue->dv_create_flow_action_packet_reformat
324 (priv->ctx, cache_resource->size,
325 (cache_resource->size ? cache_resource->buf : NULL),
326 cache_resource->reformat_type,
327 cache_resource->ft_type);
328 if (!cache_resource->verbs_action) {
329 rte_free(cache_resource);
330 return rte_flow_error_set(error, ENOMEM,
331 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
332 NULL, "cannot create action");
334 rte_atomic32_init(&cache_resource->refcnt);
335 rte_atomic32_inc(&cache_resource->refcnt);
336 LIST_INSERT_HEAD(&priv->encaps_decaps, cache_resource, next);
337 dev_flow->dv.encap_decap = cache_resource;
338 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
339 (void *)cache_resource,
340 rte_atomic32_read(&cache_resource->refcnt));
345 * Get the size of specific rte_flow_item_type
347 * @param[in] item_type
348 * Tested rte_flow_item_type.
351 * sizeof struct item_type, 0 if void or irrelevant.
354 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
359 case RTE_FLOW_ITEM_TYPE_ETH:
360 retval = sizeof(struct rte_flow_item_eth);
362 case RTE_FLOW_ITEM_TYPE_VLAN:
363 retval = sizeof(struct rte_flow_item_vlan);
365 case RTE_FLOW_ITEM_TYPE_IPV4:
366 retval = sizeof(struct rte_flow_item_ipv4);
368 case RTE_FLOW_ITEM_TYPE_IPV6:
369 retval = sizeof(struct rte_flow_item_ipv6);
371 case RTE_FLOW_ITEM_TYPE_UDP:
372 retval = sizeof(struct rte_flow_item_udp);
374 case RTE_FLOW_ITEM_TYPE_TCP:
375 retval = sizeof(struct rte_flow_item_tcp);
377 case RTE_FLOW_ITEM_TYPE_VXLAN:
378 retval = sizeof(struct rte_flow_item_vxlan);
380 case RTE_FLOW_ITEM_TYPE_GRE:
381 retval = sizeof(struct rte_flow_item_gre);
383 case RTE_FLOW_ITEM_TYPE_NVGRE:
384 retval = sizeof(struct rte_flow_item_nvgre);
386 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
387 retval = sizeof(struct rte_flow_item_vxlan_gpe);
389 case RTE_FLOW_ITEM_TYPE_MPLS:
390 retval = sizeof(struct rte_flow_item_mpls);
392 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
400 #define MLX5_ENCAP_IPV4_VERSION 0x40
401 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
402 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
403 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
404 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
405 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
406 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
409 * Convert the encap action data from list of rte_flow_item to raw buffer
412 * Pointer to rte_flow_item objects list.
414 * Pointer to the output buffer.
416 * Pointer to the output buffer size.
418 * Pointer to the error structure.
421 * 0 on success, a negative errno value otherwise and rte_errno is set.
424 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
425 size_t *size, struct rte_flow_error *error)
427 struct ether_hdr *eth = NULL;
428 struct vlan_hdr *vlan = NULL;
429 struct ipv4_hdr *ipv4 = NULL;
430 struct ipv6_hdr *ipv6 = NULL;
431 struct udp_hdr *udp = NULL;
432 struct vxlan_hdr *vxlan = NULL;
433 struct vxlan_gpe_hdr *vxlan_gpe = NULL;
434 struct gre_hdr *gre = NULL;
436 size_t temp_size = 0;
439 return rte_flow_error_set(error, EINVAL,
440 RTE_FLOW_ERROR_TYPE_ACTION,
441 NULL, "invalid empty data");
442 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
443 len = flow_dv_get_item_len(items->type);
444 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
445 return rte_flow_error_set(error, EINVAL,
446 RTE_FLOW_ERROR_TYPE_ACTION,
448 "items total size is too big"
449 " for encap action");
450 rte_memcpy((void *)&buf[temp_size], items->spec, len);
451 switch (items->type) {
452 case RTE_FLOW_ITEM_TYPE_ETH:
453 eth = (struct ether_hdr *)&buf[temp_size];
455 case RTE_FLOW_ITEM_TYPE_VLAN:
456 vlan = (struct vlan_hdr *)&buf[temp_size];
458 return rte_flow_error_set(error, EINVAL,
459 RTE_FLOW_ERROR_TYPE_ACTION,
461 "eth header not found");
462 if (!eth->ether_type)
463 eth->ether_type = RTE_BE16(ETHER_TYPE_VLAN);
465 case RTE_FLOW_ITEM_TYPE_IPV4:
466 ipv4 = (struct ipv4_hdr *)&buf[temp_size];
468 return rte_flow_error_set(error, EINVAL,
469 RTE_FLOW_ERROR_TYPE_ACTION,
471 "neither eth nor vlan"
473 if (vlan && !vlan->eth_proto)
474 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv4);
475 else if (eth && !eth->ether_type)
476 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv4);
477 if (!ipv4->version_ihl)
478 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
479 MLX5_ENCAP_IPV4_IHL_MIN;
480 if (!ipv4->time_to_live)
481 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
483 case RTE_FLOW_ITEM_TYPE_IPV6:
484 ipv6 = (struct ipv6_hdr *)&buf[temp_size];
486 return rte_flow_error_set(error, EINVAL,
487 RTE_FLOW_ERROR_TYPE_ACTION,
489 "neither eth nor vlan"
491 if (vlan && !vlan->eth_proto)
492 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv6);
493 else if (eth && !eth->ether_type)
494 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv6);
497 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
498 if (!ipv6->hop_limits)
499 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
501 case RTE_FLOW_ITEM_TYPE_UDP:
502 udp = (struct udp_hdr *)&buf[temp_size];
504 return rte_flow_error_set(error, EINVAL,
505 RTE_FLOW_ERROR_TYPE_ACTION,
507 "ip header not found");
508 if (ipv4 && !ipv4->next_proto_id)
509 ipv4->next_proto_id = IPPROTO_UDP;
510 else if (ipv6 && !ipv6->proto)
511 ipv6->proto = IPPROTO_UDP;
513 case RTE_FLOW_ITEM_TYPE_VXLAN:
514 vxlan = (struct vxlan_hdr *)&buf[temp_size];
516 return rte_flow_error_set(error, EINVAL,
517 RTE_FLOW_ERROR_TYPE_ACTION,
519 "udp header not found");
521 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
522 if (!vxlan->vx_flags)
524 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
526 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
527 vxlan_gpe = (struct vxlan_gpe_hdr *)&buf[temp_size];
529 return rte_flow_error_set(error, EINVAL,
530 RTE_FLOW_ERROR_TYPE_ACTION,
532 "udp header not found");
533 if (!vxlan_gpe->proto)
534 return rte_flow_error_set(error, EINVAL,
535 RTE_FLOW_ERROR_TYPE_ACTION,
537 "next protocol not found");
540 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
541 if (!vxlan_gpe->vx_flags)
542 vxlan_gpe->vx_flags =
543 MLX5_ENCAP_VXLAN_GPE_FLAGS;
545 case RTE_FLOW_ITEM_TYPE_GRE:
546 case RTE_FLOW_ITEM_TYPE_NVGRE:
547 gre = (struct gre_hdr *)&buf[temp_size];
549 return rte_flow_error_set(error, EINVAL,
550 RTE_FLOW_ERROR_TYPE_ACTION,
552 "next protocol not found");
554 return rte_flow_error_set(error, EINVAL,
555 RTE_FLOW_ERROR_TYPE_ACTION,
557 "ip header not found");
558 if (ipv4 && !ipv4->next_proto_id)
559 ipv4->next_proto_id = IPPROTO_GRE;
560 else if (ipv6 && !ipv6->proto)
561 ipv6->proto = IPPROTO_GRE;
563 case RTE_FLOW_ITEM_TYPE_VOID:
566 return rte_flow_error_set(error, EINVAL,
567 RTE_FLOW_ERROR_TYPE_ACTION,
569 "unsupported item type");
579 * Convert L2 encap action to DV specification.
582 * Pointer to rte_eth_dev structure.
584 * Pointer to action structure.
585 * @param[in, out] dev_flow
586 * Pointer to the mlx5_flow.
588 * Pointer to the error structure.
591 * 0 on success, a negative errno value otherwise and rte_errno is set.
594 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
595 const struct rte_flow_action *action,
596 struct mlx5_flow *dev_flow,
597 struct rte_flow_error *error)
599 const struct rte_flow_item *encap_data;
600 const struct rte_flow_action_raw_encap *raw_encap_data;
601 struct mlx5_flow_dv_encap_decap_resource res = {
603 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
604 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
607 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
609 (const struct rte_flow_action_raw_encap *)action->conf;
610 res.size = raw_encap_data->size;
611 memcpy(res.buf, raw_encap_data->data, res.size);
613 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
615 ((const struct rte_flow_action_vxlan_encap *)
616 action->conf)->definition;
619 ((const struct rte_flow_action_nvgre_encap *)
620 action->conf)->definition;
621 if (flow_dv_convert_encap_data(encap_data, res.buf,
625 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
626 return rte_flow_error_set(error, EINVAL,
627 RTE_FLOW_ERROR_TYPE_ACTION,
628 NULL, "can't create L2 encap action");
633 * Convert L2 decap action to DV specification.
636 * Pointer to rte_eth_dev structure.
637 * @param[in, out] dev_flow
638 * Pointer to the mlx5_flow.
640 * Pointer to the error structure.
643 * 0 on success, a negative errno value otherwise and rte_errno is set.
646 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
647 struct mlx5_flow *dev_flow,
648 struct rte_flow_error *error)
650 struct mlx5_flow_dv_encap_decap_resource res = {
653 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
654 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
657 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
658 return rte_flow_error_set(error, EINVAL,
659 RTE_FLOW_ERROR_TYPE_ACTION,
660 NULL, "can't create L2 decap action");
665 * Convert raw decap/encap (L3 tunnel) action to DV specification.
668 * Pointer to rte_eth_dev structure.
670 * Pointer to action structure.
671 * @param[in, out] dev_flow
672 * Pointer to the mlx5_flow.
674 * Pointer to the flow attributes.
676 * Pointer to the error structure.
679 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
683 const struct rte_flow_action *action,
684 struct mlx5_flow *dev_flow,
685 const struct rte_flow_attr *attr,
686 struct rte_flow_error *error)
688 const struct rte_flow_action_raw_encap *encap_data;
689 struct mlx5_flow_dv_encap_decap_resource res;
691 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
692 res.size = encap_data->size;
693 memcpy(res.buf, encap_data->data, res.size);
694 res.reformat_type = attr->egress ?
695 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
696 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
697 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
698 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
699 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
700 return rte_flow_error_set(error, EINVAL,
701 RTE_FLOW_ERROR_TYPE_ACTION,
702 NULL, "can't create encap action");
707 * Verify the @p attributes will be correctly understood by the NIC and store
708 * them in the @p flow if everything is correct.
711 * Pointer to dev struct.
712 * @param[in] attributes
713 * Pointer to flow attributes
715 * Pointer to error structure.
718 * 0 on success, a negative errno value otherwise and rte_errno is set.
721 flow_dv_validate_attributes(struct rte_eth_dev *dev,
722 const struct rte_flow_attr *attributes,
723 struct rte_flow_error *error)
725 struct priv *priv = dev->data->dev_private;
726 uint32_t priority_max = priv->config.flow_prio - 1;
728 if (attributes->group)
729 return rte_flow_error_set(error, ENOTSUP,
730 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
732 "groups is not supported");
733 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
734 attributes->priority >= priority_max)
735 return rte_flow_error_set(error, ENOTSUP,
736 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
738 "priority out of range");
739 if (attributes->transfer)
740 return rte_flow_error_set(error, ENOTSUP,
741 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
743 "transfer is not supported");
744 if (!(attributes->egress ^ attributes->ingress))
745 return rte_flow_error_set(error, ENOTSUP,
746 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
747 "must specify exactly one of "
748 "ingress or egress");
753 * Internal validation function. For validating both actions and items.
756 * Pointer to the rte_eth_dev structure.
758 * Pointer to the flow attributes.
760 * Pointer to the list of items.
762 * Pointer to the list of actions.
764 * Pointer to the error structure.
767 * 0 on success, a negative errno value otherwise and rte_ernno is set.
770 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
771 const struct rte_flow_item items[],
772 const struct rte_flow_action actions[],
773 struct rte_flow_error *error)
776 uint64_t action_flags = 0;
777 uint64_t item_flags = 0;
779 uint8_t next_protocol = 0xff;
784 ret = flow_dv_validate_attributes(dev, attr, error);
787 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
788 tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
789 switch (items->type) {
790 case RTE_FLOW_ITEM_TYPE_VOID:
792 case RTE_FLOW_ITEM_TYPE_ETH:
793 ret = mlx5_flow_validate_item_eth(items, item_flags,
797 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
798 MLX5_FLOW_LAYER_OUTER_L2;
800 case RTE_FLOW_ITEM_TYPE_VLAN:
801 ret = mlx5_flow_validate_item_vlan(items, item_flags,
805 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
806 MLX5_FLOW_LAYER_OUTER_VLAN;
808 case RTE_FLOW_ITEM_TYPE_IPV4:
809 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
813 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
814 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
815 if (items->mask != NULL &&
816 ((const struct rte_flow_item_ipv4 *)
817 items->mask)->hdr.next_proto_id) {
819 ((const struct rte_flow_item_ipv4 *)
820 (items->spec))->hdr.next_proto_id;
822 ((const struct rte_flow_item_ipv4 *)
823 (items->mask))->hdr.next_proto_id;
825 /* Reset for inner layer. */
826 next_protocol = 0xff;
829 case RTE_FLOW_ITEM_TYPE_IPV6:
830 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
834 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
835 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
836 if (items->mask != NULL &&
837 ((const struct rte_flow_item_ipv6 *)
838 items->mask)->hdr.proto) {
840 ((const struct rte_flow_item_ipv6 *)
841 items->spec)->hdr.proto;
843 ((const struct rte_flow_item_ipv6 *)
844 items->mask)->hdr.proto;
846 /* Reset for inner layer. */
847 next_protocol = 0xff;
850 case RTE_FLOW_ITEM_TYPE_TCP:
851 ret = mlx5_flow_validate_item_tcp
854 &rte_flow_item_tcp_mask,
858 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
859 MLX5_FLOW_LAYER_OUTER_L4_TCP;
861 case RTE_FLOW_ITEM_TYPE_UDP:
862 ret = mlx5_flow_validate_item_udp(items, item_flags,
867 item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
868 MLX5_FLOW_LAYER_OUTER_L4_UDP;
870 case RTE_FLOW_ITEM_TYPE_GRE:
871 case RTE_FLOW_ITEM_TYPE_NVGRE:
872 ret = mlx5_flow_validate_item_gre(items, item_flags,
873 next_protocol, error);
876 item_flags |= MLX5_FLOW_LAYER_GRE;
878 case RTE_FLOW_ITEM_TYPE_VXLAN:
879 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
883 item_flags |= MLX5_FLOW_LAYER_VXLAN;
885 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
886 ret = mlx5_flow_validate_item_vxlan_gpe(items,
891 item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
893 case RTE_FLOW_ITEM_TYPE_MPLS:
894 ret = mlx5_flow_validate_item_mpls(items, item_flags,
899 item_flags |= MLX5_FLOW_LAYER_MPLS;
901 case RTE_FLOW_ITEM_TYPE_META:
902 ret = flow_dv_validate_item_meta(dev, items, attr,
906 item_flags |= MLX5_FLOW_ITEM_METADATA;
909 return rte_flow_error_set(error, ENOTSUP,
910 RTE_FLOW_ERROR_TYPE_ITEM,
911 NULL, "item not supported");
914 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
915 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
916 return rte_flow_error_set(error, ENOTSUP,
917 RTE_FLOW_ERROR_TYPE_ACTION,
918 actions, "too many actions");
919 switch (actions->type) {
920 case RTE_FLOW_ACTION_TYPE_VOID:
922 case RTE_FLOW_ACTION_TYPE_FLAG:
923 ret = mlx5_flow_validate_action_flag(action_flags,
927 action_flags |= MLX5_FLOW_ACTION_FLAG;
930 case RTE_FLOW_ACTION_TYPE_MARK:
931 ret = mlx5_flow_validate_action_mark(actions,
936 action_flags |= MLX5_FLOW_ACTION_MARK;
939 case RTE_FLOW_ACTION_TYPE_DROP:
940 ret = mlx5_flow_validate_action_drop(action_flags,
944 action_flags |= MLX5_FLOW_ACTION_DROP;
947 case RTE_FLOW_ACTION_TYPE_QUEUE:
948 ret = mlx5_flow_validate_action_queue(actions,
953 action_flags |= MLX5_FLOW_ACTION_QUEUE;
956 case RTE_FLOW_ACTION_TYPE_RSS:
957 ret = mlx5_flow_validate_action_rss(actions,
962 action_flags |= MLX5_FLOW_ACTION_RSS;
965 case RTE_FLOW_ACTION_TYPE_COUNT:
966 ret = mlx5_flow_validate_action_count(dev, attr, error);
969 action_flags |= MLX5_FLOW_ACTION_COUNT;
972 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
973 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
974 ret = flow_dv_validate_action_l2_encap(action_flags,
979 action_flags |= actions->type ==
980 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
981 MLX5_FLOW_ACTION_VXLAN_ENCAP :
982 MLX5_FLOW_ACTION_NVGRE_ENCAP;
985 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
986 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
987 ret = flow_dv_validate_action_l2_decap(action_flags,
991 action_flags |= actions->type ==
992 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
993 MLX5_FLOW_ACTION_VXLAN_DECAP :
994 MLX5_FLOW_ACTION_NVGRE_DECAP;
997 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
998 ret = flow_dv_validate_action_raw_encap(action_flags,
1003 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
1006 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
1007 ret = flow_dv_validate_action_raw_decap(action_flags,
1012 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
1016 return rte_flow_error_set(error, ENOTSUP,
1017 RTE_FLOW_ERROR_TYPE_ACTION,
1019 "action not supported");
1022 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
1023 return rte_flow_error_set(error, EINVAL,
1024 RTE_FLOW_ERROR_TYPE_ACTION, actions,
1025 "no fate action is found");
1030 * Internal preparation function. Allocates the DV flow size,
1031 * this size is constant.
1034 * Pointer to the flow attributes.
1036 * Pointer to the list of items.
1037 * @param[in] actions
1038 * Pointer to the list of actions.
1040 * Pointer to the error structure.
1043 * Pointer to mlx5_flow object on success,
1044 * otherwise NULL and rte_ernno is set.
1046 static struct mlx5_flow *
1047 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
1048 const struct rte_flow_item items[] __rte_unused,
1049 const struct rte_flow_action actions[] __rte_unused,
1050 struct rte_flow_error *error)
1052 uint32_t size = sizeof(struct mlx5_flow);
1053 struct mlx5_flow *flow;
1055 flow = rte_calloc(__func__, 1, size, 0);
1057 rte_flow_error_set(error, ENOMEM,
1058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1059 "not enough memory to create flow");
1062 flow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);
1068 * Sanity check for match mask and value. Similar to check_valid_spec() in
1069 * kernel driver. If unmasked bit is present in value, it returns failure.
1072 * pointer to match mask buffer.
1073 * @param match_value
1074 * pointer to match value buffer.
1077 * 0 if valid, -EINVAL otherwise.
1080 flow_dv_check_valid_spec(void *match_mask, void *match_value)
1082 uint8_t *m = match_mask;
1083 uint8_t *v = match_value;
1086 for (i = 0; i < MLX5_ST_SZ_DB(fte_match_param); ++i) {
1089 "match_value differs from match_criteria"
1090 " %p[%u] != %p[%u]",
1091 match_value, i, match_mask, i);
1100 * Add Ethernet item to matcher and to the value.
1102 * @param[in, out] matcher
1104 * @param[in, out] key
1105 * Flow matcher value.
1107 * Flow pattern to translate.
1109 * Item is inner pattern.
1112 flow_dv_translate_item_eth(void *matcher, void *key,
1113 const struct rte_flow_item *item, int inner)
1115 const struct rte_flow_item_eth *eth_m = item->mask;
1116 const struct rte_flow_item_eth *eth_v = item->spec;
1117 const struct rte_flow_item_eth nic_mask = {
1118 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1119 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1120 .type = RTE_BE16(0xffff),
1132 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1134 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1136 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1138 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1140 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
1141 ð_m->dst, sizeof(eth_m->dst));
1142 /* The value must be in the range of the mask. */
1143 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
1144 for (i = 0; i < sizeof(eth_m->dst); ++i)
1145 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
1146 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
1147 ð_m->src, sizeof(eth_m->src));
1148 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
1149 /* The value must be in the range of the mask. */
1150 for (i = 0; i < sizeof(eth_m->dst); ++i)
1151 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
1152 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
1153 rte_be_to_cpu_16(eth_m->type));
1154 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
1155 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
1159 * Add VLAN item to matcher and to the value.
1161 * @param[in, out] matcher
1163 * @param[in, out] key
1164 * Flow matcher value.
1166 * Flow pattern to translate.
1168 * Item is inner pattern.
1171 flow_dv_translate_item_vlan(void *matcher, void *key,
1172 const struct rte_flow_item *item,
1175 const struct rte_flow_item_vlan *vlan_m = item->mask;
1176 const struct rte_flow_item_vlan *vlan_v = item->spec;
1177 const struct rte_flow_item_vlan nic_mask = {
1178 .tci = RTE_BE16(0x0fff),
1179 .inner_type = RTE_BE16(0xffff),
1191 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1193 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1195 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1197 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1199 tci_m = rte_be_to_cpu_16(vlan_m->tci);
1200 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
1201 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
1202 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
1203 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
1204 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
1205 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
1206 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
1207 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
1208 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
1212 * Add IPV4 item to matcher and to the value.
1214 * @param[in, out] matcher
1216 * @param[in, out] key
1217 * Flow matcher value.
1219 * Flow pattern to translate.
1221 * Item is inner pattern.
1224 flow_dv_translate_item_ipv4(void *matcher, void *key,
1225 const struct rte_flow_item *item,
1228 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
1229 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
1230 const struct rte_flow_item_ipv4 nic_mask = {
1232 .src_addr = RTE_BE32(0xffffffff),
1233 .dst_addr = RTE_BE32(0xffffffff),
1234 .type_of_service = 0xff,
1235 .next_proto_id = 0xff,
1245 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1247 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1249 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1251 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1253 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1254 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
1259 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1260 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1261 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1262 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1263 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
1264 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
1265 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1266 src_ipv4_src_ipv6.ipv4_layout.ipv4);
1267 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1268 src_ipv4_src_ipv6.ipv4_layout.ipv4);
1269 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
1270 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
1271 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
1272 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
1273 ipv4_m->hdr.type_of_service);
1274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
1275 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
1276 ipv4_m->hdr.type_of_service >> 2);
1277 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
1278 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1279 ipv4_m->hdr.next_proto_id);
1280 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1281 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
1285 * Add IPV6 item to matcher and to the value.
1287 * @param[in, out] matcher
1289 * @param[in, out] key
1290 * Flow matcher value.
1292 * Flow pattern to translate.
1294 * Item is inner pattern.
1297 flow_dv_translate_item_ipv6(void *matcher, void *key,
1298 const struct rte_flow_item *item,
1301 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
1302 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
1303 const struct rte_flow_item_ipv6 nic_mask = {
1306 "\xff\xff\xff\xff\xff\xff\xff\xff"
1307 "\xff\xff\xff\xff\xff\xff\xff\xff",
1309 "\xff\xff\xff\xff\xff\xff\xff\xff"
1310 "\xff\xff\xff\xff\xff\xff\xff\xff",
1311 .vtc_flow = RTE_BE32(0xffffffff),
1318 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1319 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1328 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1330 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1332 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1334 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1336 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
1342 size = sizeof(ipv6_m->hdr.dst_addr);
1343 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1344 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1345 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1346 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1347 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
1348 for (i = 0; i < size; ++i)
1349 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
1350 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1351 src_ipv4_src_ipv6.ipv6_layout.ipv6);
1352 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1353 src_ipv4_src_ipv6.ipv6_layout.ipv6);
1354 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
1355 for (i = 0; i < size; ++i)
1356 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
1358 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
1359 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
1360 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
1361 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
1362 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
1363 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
1366 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
1368 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
1371 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
1373 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
1377 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1380 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
1384 * Add TCP item to matcher and to the value.
1386 * @param[in, out] matcher
1388 * @param[in, out] key
1389 * Flow matcher value.
1391 * Flow pattern to translate.
1393 * Item is inner pattern.
1396 flow_dv_translate_item_tcp(void *matcher, void *key,
1397 const struct rte_flow_item *item,
1400 const struct rte_flow_item_tcp *tcp_m = item->mask;
1401 const struct rte_flow_item_tcp *tcp_v = item->spec;
1406 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1408 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1410 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1412 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1414 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1415 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
1419 tcp_m = &rte_flow_item_tcp_mask;
1420 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
1421 rte_be_to_cpu_16(tcp_m->hdr.src_port));
1422 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1423 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
1424 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
1425 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
1426 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1427 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
1431 * Add UDP item to matcher and to the value.
1433 * @param[in, out] matcher
1435 * @param[in, out] key
1436 * Flow matcher value.
1438 * Flow pattern to translate.
1440 * Item is inner pattern.
1443 flow_dv_translate_item_udp(void *matcher, void *key,
1444 const struct rte_flow_item *item,
1447 const struct rte_flow_item_udp *udp_m = item->mask;
1448 const struct rte_flow_item_udp *udp_v = item->spec;
1453 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1455 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1457 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1459 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1461 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1462 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1466 udp_m = &rte_flow_item_udp_mask;
1467 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
1468 rte_be_to_cpu_16(udp_m->hdr.src_port));
1469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1470 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
1471 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
1472 rte_be_to_cpu_16(udp_m->hdr.dst_port));
1473 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1474 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
1478 * Add GRE item to matcher and to the value.
1480 * @param[in, out] matcher
1482 * @param[in, out] key
1483 * Flow matcher value.
1485 * Flow pattern to translate.
1487 * Item is inner pattern.
1490 flow_dv_translate_item_gre(void *matcher, void *key,
1491 const struct rte_flow_item *item,
1494 const struct rte_flow_item_gre *gre_m = item->mask;
1495 const struct rte_flow_item_gre *gre_v = item->spec;
1498 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1499 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1502 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1504 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1506 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1508 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1510 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1511 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
1515 gre_m = &rte_flow_item_gre_mask;
1516 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
1517 rte_be_to_cpu_16(gre_m->protocol));
1518 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
1519 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
1523 * Add NVGRE item to matcher and to the value.
1525 * @param[in, out] matcher
1527 * @param[in, out] key
1528 * Flow matcher value.
1530 * Flow pattern to translate.
1532 * Item is inner pattern.
1535 flow_dv_translate_item_nvgre(void *matcher, void *key,
1536 const struct rte_flow_item *item,
1539 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
1540 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
1541 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1542 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1543 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
1544 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
1550 flow_dv_translate_item_gre(matcher, key, item, inner);
1554 nvgre_m = &rte_flow_item_nvgre_mask;
1555 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
1556 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
1557 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
1558 memcpy(gre_key_m, tni_flow_id_m, size);
1559 for (i = 0; i < size; ++i)
1560 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
1564 * Add VXLAN item to matcher and to the value.
1566 * @param[in, out] matcher
1568 * @param[in, out] key
1569 * Flow matcher value.
1571 * Flow pattern to translate.
1573 * Item is inner pattern.
1576 flow_dv_translate_item_vxlan(void *matcher, void *key,
1577 const struct rte_flow_item *item,
1580 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
1581 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
1584 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1585 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1593 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1595 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1599 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1601 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
1602 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
1603 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
1604 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
1605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
1610 vxlan_m = &rte_flow_item_vxlan_mask;
1611 size = sizeof(vxlan_m->vni);
1612 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
1613 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
1614 memcpy(vni_m, vxlan_m->vni, size);
1615 for (i = 0; i < size; ++i)
1616 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
1620 * Add MPLS item to matcher and to the value.
1622 * @param[in, out] matcher
1624 * @param[in, out] key
1625 * Flow matcher value.
1627 * Flow pattern to translate.
1628 * @param[in] prev_layer
1629 * The protocol layer indicated in previous item.
1631 * Item is inner pattern.
1634 flow_dv_translate_item_mpls(void *matcher, void *key,
1635 const struct rte_flow_item *item,
1636 uint64_t prev_layer,
1639 const uint32_t *in_mpls_m = item->mask;
1640 const uint32_t *in_mpls_v = item->spec;
1641 uint32_t *out_mpls_m = 0;
1642 uint32_t *out_mpls_v = 0;
1643 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1644 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1645 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
1647 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
1648 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
1649 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1651 switch (prev_layer) {
1652 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
1653 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
1654 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1655 MLX5_UDP_PORT_MPLS);
1657 case MLX5_FLOW_LAYER_GRE:
1658 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
1659 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
1663 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1664 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1671 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
1672 switch (prev_layer) {
1673 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
1675 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
1676 outer_first_mpls_over_udp);
1678 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
1679 outer_first_mpls_over_udp);
1681 case MLX5_FLOW_LAYER_GRE:
1683 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
1684 outer_first_mpls_over_gre);
1686 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
1687 outer_first_mpls_over_gre);
1690 /* Inner MPLS not over GRE is not supported. */
1693 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
1697 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
1703 if (out_mpls_m && out_mpls_v) {
1704 *out_mpls_m = *in_mpls_m;
1705 *out_mpls_v = *in_mpls_v & *in_mpls_m;
1710 * Add META item to matcher
1712 * @param[in, out] matcher
1714 * @param[in, out] key
1715 * Flow matcher value.
1717 * Flow pattern to translate.
1719 * Item is inner pattern.
1722 flow_dv_translate_item_meta(void *matcher, void *key,
1723 const struct rte_flow_item *item)
1725 const struct rte_flow_item_meta *meta_m;
1726 const struct rte_flow_item_meta *meta_v;
1728 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
1730 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
1732 meta_m = (const void *)item->mask;
1734 meta_m = &rte_flow_item_meta_mask;
1735 meta_v = (const void *)item->spec;
1737 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
1738 rte_be_to_cpu_32(meta_m->data));
1739 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
1740 rte_be_to_cpu_32(meta_v->data & meta_m->data));
1744 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
1746 #define HEADER_IS_ZERO(match_criteria, headers) \
1747 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1748 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1751 * Calculate flow matcher enable bitmap.
1753 * @param match_criteria
1754 * Pointer to flow matcher criteria.
1757 * Bitmap of enabled fields.
1760 flow_dv_matcher_enable(uint32_t *match_criteria)
1762 uint8_t match_criteria_enable;
1764 match_criteria_enable =
1765 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1766 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
1767 match_criteria_enable |=
1768 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1769 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
1770 match_criteria_enable |=
1771 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1772 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
1773 match_criteria_enable |=
1774 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
1775 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
1777 return match_criteria_enable;
1781 * Register the flow matcher.
1783 * @param dev[in, out]
1784 * Pointer to rte_eth_dev structure.
1785 * @param[in, out] matcher
1786 * Pointer to flow matcher.
1787 * @parm[in, out] dev_flow
1788 * Pointer to the dev_flow.
1790 * pointer to error structure.
1793 * 0 on success otherwise -errno and errno is set.
1796 flow_dv_matcher_register(struct rte_eth_dev *dev,
1797 struct mlx5_flow_dv_matcher *matcher,
1798 struct mlx5_flow *dev_flow,
1799 struct rte_flow_error *error)
1801 struct priv *priv = dev->data->dev_private;
1802 struct mlx5_flow_dv_matcher *cache_matcher;
1803 struct mlx5dv_flow_matcher_attr dv_attr = {
1804 .type = IBV_FLOW_ATTR_NORMAL,
1805 .match_mask = (void *)&matcher->mask,
1808 /* Lookup from cache. */
1809 LIST_FOREACH(cache_matcher, &priv->matchers, next) {
1810 if (matcher->crc == cache_matcher->crc &&
1811 matcher->priority == cache_matcher->priority &&
1812 matcher->egress == cache_matcher->egress &&
1813 !memcmp((const void *)matcher->mask.buf,
1814 (const void *)cache_matcher->mask.buf,
1815 cache_matcher->mask.size)) {
1817 "priority %hd use %s matcher %p: refcnt %d++",
1818 cache_matcher->priority,
1819 cache_matcher->egress ? "tx" : "rx",
1820 (void *)cache_matcher,
1821 rte_atomic32_read(&cache_matcher->refcnt));
1822 rte_atomic32_inc(&cache_matcher->refcnt);
1823 dev_flow->dv.matcher = cache_matcher;
1827 /* Register new matcher. */
1828 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
1830 return rte_flow_error_set(error, ENOMEM,
1831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1832 "cannot allocate matcher memory");
1833 *cache_matcher = *matcher;
1834 dv_attr.match_criteria_enable =
1835 flow_dv_matcher_enable(cache_matcher->mask.buf);
1836 dv_attr.priority = matcher->priority;
1837 if (matcher->egress)
1838 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
1839 cache_matcher->matcher_object =
1840 mlx5_glue->dv_create_flow_matcher(priv->ctx, &dv_attr);
1841 if (!cache_matcher->matcher_object) {
1842 rte_free(cache_matcher);
1843 return rte_flow_error_set(error, ENOMEM,
1844 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1845 NULL, "cannot create matcher");
1847 rte_atomic32_inc(&cache_matcher->refcnt);
1848 LIST_INSERT_HEAD(&priv->matchers, cache_matcher, next);
1849 dev_flow->dv.matcher = cache_matcher;
1850 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
1851 cache_matcher->priority,
1852 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
1853 rte_atomic32_read(&cache_matcher->refcnt));
1858 * Fill the flow with DV spec.
1861 * Pointer to rte_eth_dev structure.
1862 * @param[in, out] dev_flow
1863 * Pointer to the sub flow.
1865 * Pointer to the flow attributes.
1867 * Pointer to the list of items.
1868 * @param[in] actions
1869 * Pointer to the list of actions.
1871 * Pointer to the error structure.
1874 * 0 on success, a negative errno value otherwise and rte_ernno is set.
1877 flow_dv_translate(struct rte_eth_dev *dev,
1878 struct mlx5_flow *dev_flow,
1879 const struct rte_flow_attr *attr,
1880 const struct rte_flow_item items[],
1881 const struct rte_flow_action actions[],
1882 struct rte_flow_error *error)
1884 struct priv *priv = dev->data->dev_private;
1885 struct rte_flow *flow = dev_flow->flow;
1886 uint64_t item_flags = 0;
1887 uint64_t last_item = 0;
1888 uint64_t action_flags = 0;
1889 uint64_t priority = attr->priority;
1890 struct mlx5_flow_dv_matcher matcher = {
1892 .size = sizeof(matcher.mask.buf),
1897 if (priority == MLX5_FLOW_PRIO_RSVD)
1898 priority = priv->config.flow_prio - 1;
1899 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
1900 const struct rte_flow_action_queue *queue;
1901 const struct rte_flow_action_rss *rss;
1902 const struct rte_flow_action *action = actions;
1903 const uint8_t *rss_key;
1905 switch (actions->type) {
1906 case RTE_FLOW_ACTION_TYPE_VOID:
1908 case RTE_FLOW_ACTION_TYPE_FLAG:
1909 dev_flow->dv.actions[actions_n].type =
1910 MLX5DV_FLOW_ACTION_TAG;
1911 dev_flow->dv.actions[actions_n].tag_value =
1912 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
1914 action_flags |= MLX5_FLOW_ACTION_FLAG;
1916 case RTE_FLOW_ACTION_TYPE_MARK:
1917 dev_flow->dv.actions[actions_n].type =
1918 MLX5DV_FLOW_ACTION_TAG;
1919 dev_flow->dv.actions[actions_n].tag_value =
1921 (((const struct rte_flow_action_mark *)
1922 (actions->conf))->id);
1924 action_flags |= MLX5_FLOW_ACTION_MARK;
1926 case RTE_FLOW_ACTION_TYPE_DROP:
1927 dev_flow->dv.actions[actions_n].type =
1928 MLX5DV_FLOW_ACTION_DROP;
1929 action_flags |= MLX5_FLOW_ACTION_DROP;
1931 case RTE_FLOW_ACTION_TYPE_QUEUE:
1932 queue = actions->conf;
1933 flow->rss.queue_num = 1;
1934 (*flow->queue)[0] = queue->index;
1935 action_flags |= MLX5_FLOW_ACTION_QUEUE;
1937 case RTE_FLOW_ACTION_TYPE_RSS:
1938 rss = actions->conf;
1940 memcpy((*flow->queue), rss->queue,
1941 rss->queue_num * sizeof(uint16_t));
1942 flow->rss.queue_num = rss->queue_num;
1943 /* NULL RSS key indicates default RSS key. */
1944 rss_key = !rss->key ? rss_hash_default_key : rss->key;
1945 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
1946 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
1947 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
1948 flow->rss.level = rss->level;
1949 action_flags |= MLX5_FLOW_ACTION_RSS;
1951 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
1952 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
1953 if (flow_dv_create_action_l2_encap(dev, actions,
1956 dev_flow->dv.actions[actions_n].type =
1957 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1958 dev_flow->dv.actions[actions_n].action =
1959 dev_flow->dv.encap_decap->verbs_action;
1961 action_flags |= actions->type ==
1962 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
1963 MLX5_FLOW_ACTION_VXLAN_ENCAP :
1964 MLX5_FLOW_ACTION_NVGRE_ENCAP;
1966 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
1967 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
1968 if (flow_dv_create_action_l2_decap(dev, dev_flow,
1971 dev_flow->dv.actions[actions_n].type =
1972 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1973 dev_flow->dv.actions[actions_n].action =
1974 dev_flow->dv.encap_decap->verbs_action;
1976 action_flags |= actions->type ==
1977 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
1978 MLX5_FLOW_ACTION_VXLAN_DECAP :
1979 MLX5_FLOW_ACTION_NVGRE_DECAP;
1981 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
1982 /* Handle encap with preceding decap. */
1983 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
1984 if (flow_dv_create_action_raw_encap
1985 (dev, actions, dev_flow, attr, error))
1987 dev_flow->dv.actions[actions_n].type =
1988 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1989 dev_flow->dv.actions[actions_n].action =
1990 dev_flow->dv.encap_decap->verbs_action;
1992 /* Handle encap without preceding decap. */
1993 if (flow_dv_create_action_l2_encap(dev, actions,
1997 dev_flow->dv.actions[actions_n].type =
1998 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1999 dev_flow->dv.actions[actions_n].action =
2000 dev_flow->dv.encap_decap->verbs_action;
2003 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
2005 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
2006 /* Check if this decap is followed by encap. */
2007 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
2008 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
2011 /* Handle decap only if it isn't followed by encap. */
2012 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2013 if (flow_dv_create_action_l2_decap(dev,
2017 dev_flow->dv.actions[actions_n].type =
2018 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
2019 dev_flow->dv.actions[actions_n].action =
2020 dev_flow->dv.encap_decap->verbs_action;
2023 /* If decap is followed by encap, handle it at encap. */
2024 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
2030 dev_flow->dv.actions_n = actions_n;
2031 flow->actions = action_flags;
2032 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2033 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2034 void *match_mask = matcher.mask.buf;
2035 void *match_value = dev_flow->dv.value.buf;
2037 switch (items->type) {
2038 case RTE_FLOW_ITEM_TYPE_ETH:
2039 flow_dv_translate_item_eth(match_mask, match_value,
2041 matcher.priority = MLX5_PRIORITY_MAP_L2;
2042 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
2043 MLX5_FLOW_LAYER_OUTER_L2;
2045 case RTE_FLOW_ITEM_TYPE_VLAN:
2046 flow_dv_translate_item_vlan(match_mask, match_value,
2048 matcher.priority = MLX5_PRIORITY_MAP_L2;
2049 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
2050 MLX5_FLOW_LAYER_INNER_VLAN) :
2051 (MLX5_FLOW_LAYER_OUTER_L2 |
2052 MLX5_FLOW_LAYER_OUTER_VLAN);
2054 case RTE_FLOW_ITEM_TYPE_IPV4:
2055 flow_dv_translate_item_ipv4(match_mask, match_value,
2057 matcher.priority = MLX5_PRIORITY_MAP_L3;
2058 dev_flow->dv.hash_fields |=
2059 mlx5_flow_hashfields_adjust
2061 MLX5_IPV4_LAYER_TYPES,
2062 MLX5_IPV4_IBV_RX_HASH);
2063 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
2064 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
2066 case RTE_FLOW_ITEM_TYPE_IPV6:
2067 flow_dv_translate_item_ipv6(match_mask, match_value,
2069 matcher.priority = MLX5_PRIORITY_MAP_L3;
2070 dev_flow->dv.hash_fields |=
2071 mlx5_flow_hashfields_adjust
2073 MLX5_IPV6_LAYER_TYPES,
2074 MLX5_IPV6_IBV_RX_HASH);
2075 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
2076 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
2078 case RTE_FLOW_ITEM_TYPE_TCP:
2079 flow_dv_translate_item_tcp(match_mask, match_value,
2081 matcher.priority = MLX5_PRIORITY_MAP_L4;
2082 dev_flow->dv.hash_fields |=
2083 mlx5_flow_hashfields_adjust
2084 (dev_flow, tunnel, ETH_RSS_TCP,
2085 IBV_RX_HASH_SRC_PORT_TCP |
2086 IBV_RX_HASH_DST_PORT_TCP);
2087 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
2088 MLX5_FLOW_LAYER_OUTER_L4_TCP;
2090 case RTE_FLOW_ITEM_TYPE_UDP:
2091 flow_dv_translate_item_udp(match_mask, match_value,
2093 matcher.priority = MLX5_PRIORITY_MAP_L4;
2094 dev_flow->dv.hash_fields |=
2095 mlx5_flow_hashfields_adjust
2096 (dev_flow, tunnel, ETH_RSS_UDP,
2097 IBV_RX_HASH_SRC_PORT_UDP |
2098 IBV_RX_HASH_DST_PORT_UDP);
2099 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
2100 MLX5_FLOW_LAYER_OUTER_L4_UDP;
2102 case RTE_FLOW_ITEM_TYPE_GRE:
2103 flow_dv_translate_item_gre(match_mask, match_value,
2105 last_item = MLX5_FLOW_LAYER_GRE;
2107 case RTE_FLOW_ITEM_TYPE_NVGRE:
2108 flow_dv_translate_item_nvgre(match_mask, match_value,
2110 last_item = MLX5_FLOW_LAYER_GRE;
2112 case RTE_FLOW_ITEM_TYPE_VXLAN:
2113 flow_dv_translate_item_vxlan(match_mask, match_value,
2115 last_item = MLX5_FLOW_LAYER_VXLAN;
2117 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2118 flow_dv_translate_item_vxlan(match_mask, match_value,
2120 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
2122 case RTE_FLOW_ITEM_TYPE_MPLS:
2123 flow_dv_translate_item_mpls(match_mask, match_value,
2124 items, last_item, tunnel);
2125 last_item = MLX5_FLOW_LAYER_MPLS;
2127 case RTE_FLOW_ITEM_TYPE_META:
2128 flow_dv_translate_item_meta(match_mask, match_value,
2130 last_item = MLX5_FLOW_ITEM_METADATA;
2135 item_flags |= last_item;
2137 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
2138 dev_flow->dv.value.buf));
2139 dev_flow->layers = item_flags;
2140 /* Register matcher. */
2141 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
2143 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
2145 matcher.egress = attr->egress;
2146 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
2152 * Apply the flow to the NIC.
2155 * Pointer to the Ethernet device structure.
2156 * @param[in, out] flow
2157 * Pointer to flow structure.
2159 * Pointer to error structure.
2162 * 0 on success, a negative errno value otherwise and rte_errno is set.
2165 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
2166 struct rte_flow_error *error)
2168 struct mlx5_flow_dv *dv;
2169 struct mlx5_flow *dev_flow;
2173 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2176 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
2177 dv->hrxq = mlx5_hrxq_drop_new(dev);
2181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2182 "cannot get drop hash queue");
2185 dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2186 dv->actions[n].qp = dv->hrxq->qp;
2188 } else if (flow->actions &
2189 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
2190 struct mlx5_hrxq *hrxq;
2192 hrxq = mlx5_hrxq_get(dev, flow->key,
2193 MLX5_RSS_HASH_KEY_LEN,
2196 flow->rss.queue_num);
2198 hrxq = mlx5_hrxq_new
2199 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
2200 dv->hash_fields, (*flow->queue),
2201 flow->rss.queue_num,
2202 !!(dev_flow->layers &
2203 MLX5_FLOW_LAYER_TUNNEL));
2207 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2208 "cannot get hash queue");
2212 dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2213 dv->actions[n].qp = hrxq->qp;
2217 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
2218 (void *)&dv->value, n,
2221 rte_flow_error_set(error, errno,
2222 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2224 "hardware refuses to create flow");
2230 err = rte_errno; /* Save rte_errno before cleanup. */
2231 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2232 struct mlx5_flow_dv *dv = &dev_flow->dv;
2234 if (flow->actions & MLX5_FLOW_ACTION_DROP)
2235 mlx5_hrxq_drop_release(dev);
2237 mlx5_hrxq_release(dev, dv->hrxq);
2241 rte_errno = err; /* Restore rte_errno. */
2246 * Release the flow matcher.
2249 * Pointer to Ethernet device.
2251 * Pointer to mlx5_flow.
2254 * 1 while a reference on it exists, 0 when freed.
2257 flow_dv_matcher_release(struct rte_eth_dev *dev,
2258 struct mlx5_flow *flow)
2260 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
2262 assert(matcher->matcher_object);
2263 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
2264 dev->data->port_id, (void *)matcher,
2265 rte_atomic32_read(&matcher->refcnt));
2266 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
2267 claim_zero(mlx5_glue->dv_destroy_flow_matcher
2268 (matcher->matcher_object));
2269 LIST_REMOVE(matcher, next);
2271 DRV_LOG(DEBUG, "port %u matcher %p: removed",
2272 dev->data->port_id, (void *)matcher);
2279 * Release an encap/decap resource.
2282 * Pointer to mlx5_flow.
2285 * 1 while a reference on it exists, 0 when freed.
2288 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
2290 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
2291 flow->dv.encap_decap;
2293 assert(cache_resource->verbs_action);
2294 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
2295 (void *)cache_resource,
2296 rte_atomic32_read(&cache_resource->refcnt));
2297 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
2298 claim_zero(mlx5_glue->destroy_flow_action
2299 (cache_resource->verbs_action));
2300 LIST_REMOVE(cache_resource, next);
2301 rte_free(cache_resource);
2302 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
2303 (void *)cache_resource);
2310 * Remove the flow from the NIC but keeps it in memory.
2313 * Pointer to Ethernet device.
2314 * @param[in, out] flow
2315 * Pointer to flow structure.
2318 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
2320 struct mlx5_flow_dv *dv;
2321 struct mlx5_flow *dev_flow;
2325 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2328 claim_zero(mlx5_glue->destroy_flow(dv->flow));
2332 if (flow->actions & MLX5_FLOW_ACTION_DROP)
2333 mlx5_hrxq_drop_release(dev);
2335 mlx5_hrxq_release(dev, dv->hrxq);
2340 flow->counter = NULL;
2344 * Remove the flow from the NIC and the memory.
2347 * Pointer to the Ethernet device structure.
2348 * @param[in, out] flow
2349 * Pointer to flow structure.
2352 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
2354 struct mlx5_flow *dev_flow;
2358 flow_dv_remove(dev, flow);
2359 while (!LIST_EMPTY(&flow->dev_flows)) {
2360 dev_flow = LIST_FIRST(&flow->dev_flows);
2361 LIST_REMOVE(dev_flow, next);
2362 if (dev_flow->dv.matcher)
2363 flow_dv_matcher_release(dev, dev_flow);
2364 if (dev_flow->dv.encap_decap)
2365 flow_dv_encap_decap_resource_release(dev_flow);
2373 * @see rte_flow_query()
2377 flow_dv_query(struct rte_eth_dev *dev __rte_unused,
2378 struct rte_flow *flow __rte_unused,
2379 const struct rte_flow_action *actions __rte_unused,
2380 void *data __rte_unused,
2381 struct rte_flow_error *error __rte_unused)
2383 return rte_flow_error_set(error, ENOTSUP,
2384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2386 "flow query with DV is not supported");
2390 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
2391 .validate = flow_dv_validate,
2392 .prepare = flow_dv_prepare,
2393 .translate = flow_dv_translate,
2394 .apply = flow_dv_apply,
2395 .remove = flow_dv_remove,
2396 .destroy = flow_dv_destroy,
2397 .query = flow_dv_query,
2400 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */