1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
215 /* Update VLAN's VID/PCP based on input rte_flow_action.
218 * Pointer to struct rte_flow_action.
220 * Pointer to struct rte_vlan_hdr.
223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
224 struct rte_vlan_hdr *vlan)
227 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
229 ((const struct rte_flow_action_of_set_vlan_pcp *)
230 action->conf)->vlan_pcp;
231 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
232 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
233 vlan->vlan_tci |= vlan_tci;
234 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
235 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
236 vlan->vlan_tci |= rte_be_to_cpu_16
237 (((const struct rte_flow_action_of_set_vlan_vid *)
238 action->conf)->vlan_vid);
243 * Fetch 1, 2, 3 or 4 byte field from the byte array
244 * and return as unsigned integer in host-endian format.
247 * Pointer to data array.
249 * Size of field to extract.
252 * converted field in host endian format.
254 static inline uint32_t
255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
264 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
267 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
268 ret = (ret << 8) | *(data + sizeof(uint16_t));
271 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
282 * Convert modify-header action to DV specification.
284 * Data length of each action is determined by provided field description
285 * and the item mask. Data bit offset and width of each action is determined
286 * by provided item mask.
289 * Pointer to item specification.
291 * Pointer to field modification information.
292 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
293 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
294 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
296 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
297 * Negative offset value sets the same offset as source offset.
298 * size field is ignored, value is taken from source field.
299 * @param[in,out] resource
300 * Pointer to the modify-header resource.
302 * Type of modification.
304 * Pointer to the error structure.
307 * 0 on success, a negative errno value otherwise and rte_errno is set.
310 flow_dv_convert_modify_action(struct rte_flow_item *item,
311 struct field_modify_info *field,
312 struct field_modify_info *dcopy,
313 struct mlx5_flow_dv_modify_hdr_resource *resource,
314 uint32_t type, struct rte_flow_error *error)
316 uint32_t i = resource->actions_num;
317 struct mlx5_modification_cmd *actions = resource->actions;
320 * The item and mask are provided in big-endian format.
321 * The fields should be presented as in big-endian format either.
322 * Mask must be always present, it defines the actual field width.
332 if (i >= MLX5_MODIFY_NUM)
333 return rte_flow_error_set(error, EINVAL,
334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
335 "too many items to modify");
336 /* Fetch variable byte size mask from the array. */
337 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
338 field->offset, field->size);
343 /* Deduce actual data width in bits from mask value. */
344 off_b = rte_bsf32(mask);
345 size_b = sizeof(uint32_t) * CHAR_BIT -
346 off_b - __builtin_clz(mask);
348 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
349 actions[i].action_type = type;
350 actions[i].field = field->id;
351 actions[i].offset = off_b;
352 actions[i].length = size_b;
353 /* Convert entire record to expected big-endian format. */
354 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
355 if (type == MLX5_MODIFICATION_TYPE_COPY) {
357 actions[i].dst_field = dcopy->id;
358 actions[i].dst_offset =
359 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
360 /* Convert entire record to big-endian format. */
361 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
364 data = flow_dv_fetch_field((const uint8_t *)item->spec +
365 field->offset, field->size);
366 /* Shift out the trailing masked bits from data. */
367 data = (data & mask) >> off_b;
368 actions[i].data1 = rte_cpu_to_be_32(data);
372 } while (field->size);
373 resource->actions_num = i;
374 if (!resource->actions_num)
375 return rte_flow_error_set(error, EINVAL,
376 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
377 "invalid modification flow item");
382 * Convert modify-header set IPv4 address action to DV specification.
384 * @param[in,out] resource
385 * Pointer to the modify-header resource.
387 * Pointer to action specification.
389 * Pointer to the error structure.
392 * 0 on success, a negative errno value otherwise and rte_errno is set.
395 flow_dv_convert_action_modify_ipv4
396 (struct mlx5_flow_dv_modify_hdr_resource *resource,
397 const struct rte_flow_action *action,
398 struct rte_flow_error *error)
400 const struct rte_flow_action_set_ipv4 *conf =
401 (const struct rte_flow_action_set_ipv4 *)(action->conf);
402 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
403 struct rte_flow_item_ipv4 ipv4;
404 struct rte_flow_item_ipv4 ipv4_mask;
406 memset(&ipv4, 0, sizeof(ipv4));
407 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
408 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
409 ipv4.hdr.src_addr = conf->ipv4_addr;
410 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
412 ipv4.hdr.dst_addr = conf->ipv4_addr;
413 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
416 item.mask = &ipv4_mask;
417 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
418 MLX5_MODIFICATION_TYPE_SET, error);
422 * Convert modify-header set IPv6 address action to DV specification.
424 * @param[in,out] resource
425 * Pointer to the modify-header resource.
427 * Pointer to action specification.
429 * Pointer to the error structure.
432 * 0 on success, a negative errno value otherwise and rte_errno is set.
435 flow_dv_convert_action_modify_ipv6
436 (struct mlx5_flow_dv_modify_hdr_resource *resource,
437 const struct rte_flow_action *action,
438 struct rte_flow_error *error)
440 const struct rte_flow_action_set_ipv6 *conf =
441 (const struct rte_flow_action_set_ipv6 *)(action->conf);
442 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
443 struct rte_flow_item_ipv6 ipv6;
444 struct rte_flow_item_ipv6 ipv6_mask;
446 memset(&ipv6, 0, sizeof(ipv6));
447 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
448 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
449 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
450 sizeof(ipv6.hdr.src_addr));
451 memcpy(&ipv6_mask.hdr.src_addr,
452 &rte_flow_item_ipv6_mask.hdr.src_addr,
453 sizeof(ipv6.hdr.src_addr));
455 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
456 sizeof(ipv6.hdr.dst_addr));
457 memcpy(&ipv6_mask.hdr.dst_addr,
458 &rte_flow_item_ipv6_mask.hdr.dst_addr,
459 sizeof(ipv6.hdr.dst_addr));
462 item.mask = &ipv6_mask;
463 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
464 MLX5_MODIFICATION_TYPE_SET, error);
468 * Convert modify-header set MAC address action to DV specification.
470 * @param[in,out] resource
471 * Pointer to the modify-header resource.
473 * Pointer to action specification.
475 * Pointer to the error structure.
478 * 0 on success, a negative errno value otherwise and rte_errno is set.
481 flow_dv_convert_action_modify_mac
482 (struct mlx5_flow_dv_modify_hdr_resource *resource,
483 const struct rte_flow_action *action,
484 struct rte_flow_error *error)
486 const struct rte_flow_action_set_mac *conf =
487 (const struct rte_flow_action_set_mac *)(action->conf);
488 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
489 struct rte_flow_item_eth eth;
490 struct rte_flow_item_eth eth_mask;
492 memset(ð, 0, sizeof(eth));
493 memset(ð_mask, 0, sizeof(eth_mask));
494 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
495 memcpy(ð.src.addr_bytes, &conf->mac_addr,
496 sizeof(eth.src.addr_bytes));
497 memcpy(ð_mask.src.addr_bytes,
498 &rte_flow_item_eth_mask.src.addr_bytes,
499 sizeof(eth_mask.src.addr_bytes));
501 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
502 sizeof(eth.dst.addr_bytes));
503 memcpy(ð_mask.dst.addr_bytes,
504 &rte_flow_item_eth_mask.dst.addr_bytes,
505 sizeof(eth_mask.dst.addr_bytes));
508 item.mask = ð_mask;
509 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
510 MLX5_MODIFICATION_TYPE_SET, error);
514 * Convert modify-header set VLAN VID action to DV specification.
516 * @param[in,out] resource
517 * Pointer to the modify-header resource.
519 * Pointer to action specification.
521 * Pointer to the error structure.
524 * 0 on success, a negative errno value otherwise and rte_errno is set.
527 flow_dv_convert_action_modify_vlan_vid
528 (struct mlx5_flow_dv_modify_hdr_resource *resource,
529 const struct rte_flow_action *action,
530 struct rte_flow_error *error)
532 const struct rte_flow_action_of_set_vlan_vid *conf =
533 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
534 int i = resource->actions_num;
535 struct mlx5_modification_cmd *actions = &resource->actions[i];
536 struct field_modify_info *field = modify_vlan_out_first_vid;
538 if (i >= MLX5_MODIFY_NUM)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "too many items to modify");
542 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
543 actions[i].field = field->id;
544 actions[i].length = field->size;
545 actions[i].offset = field->offset;
546 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
547 actions[i].data1 = conf->vlan_vid;
548 actions[i].data1 = actions[i].data1 << 16;
549 resource->actions_num = ++i;
554 * Convert modify-header set TP action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to rte_flow_item objects list.
563 * Pointer to flow attributes structure.
565 * Pointer to the error structure.
568 * 0 on success, a negative errno value otherwise and rte_errno is set.
571 flow_dv_convert_action_modify_tp
572 (struct mlx5_flow_dv_modify_hdr_resource *resource,
573 const struct rte_flow_action *action,
574 const struct rte_flow_item *items,
575 union flow_dv_attr *attr,
576 struct rte_flow_error *error)
578 const struct rte_flow_action_set_tp *conf =
579 (const struct rte_flow_action_set_tp *)(action->conf);
580 struct rte_flow_item item;
581 struct rte_flow_item_udp udp;
582 struct rte_flow_item_udp udp_mask;
583 struct rte_flow_item_tcp tcp;
584 struct rte_flow_item_tcp tcp_mask;
585 struct field_modify_info *field;
588 flow_dv_attr_init(items, attr);
590 memset(&udp, 0, sizeof(udp));
591 memset(&udp_mask, 0, sizeof(udp_mask));
592 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
593 udp.hdr.src_port = conf->port;
594 udp_mask.hdr.src_port =
595 rte_flow_item_udp_mask.hdr.src_port;
597 udp.hdr.dst_port = conf->port;
598 udp_mask.hdr.dst_port =
599 rte_flow_item_udp_mask.hdr.dst_port;
601 item.type = RTE_FLOW_ITEM_TYPE_UDP;
603 item.mask = &udp_mask;
607 memset(&tcp, 0, sizeof(tcp));
608 memset(&tcp_mask, 0, sizeof(tcp_mask));
609 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
610 tcp.hdr.src_port = conf->port;
611 tcp_mask.hdr.src_port =
612 rte_flow_item_tcp_mask.hdr.src_port;
614 tcp.hdr.dst_port = conf->port;
615 tcp_mask.hdr.dst_port =
616 rte_flow_item_tcp_mask.hdr.dst_port;
618 item.type = RTE_FLOW_ITEM_TYPE_TCP;
620 item.mask = &tcp_mask;
623 return flow_dv_convert_modify_action(&item, field, NULL, resource,
624 MLX5_MODIFICATION_TYPE_SET, error);
628 * Convert modify-header set TTL action to DV specification.
630 * @param[in,out] resource
631 * Pointer to the modify-header resource.
633 * Pointer to action specification.
635 * Pointer to rte_flow_item objects list.
637 * Pointer to flow attributes structure.
639 * Pointer to the error structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 flow_dv_convert_action_modify_ttl
646 (struct mlx5_flow_dv_modify_hdr_resource *resource,
647 const struct rte_flow_action *action,
648 const struct rte_flow_item *items,
649 union flow_dv_attr *attr,
650 struct rte_flow_error *error)
652 const struct rte_flow_action_set_ttl *conf =
653 (const struct rte_flow_action_set_ttl *)(action->conf);
654 struct rte_flow_item item;
655 struct rte_flow_item_ipv4 ipv4;
656 struct rte_flow_item_ipv4 ipv4_mask;
657 struct rte_flow_item_ipv6 ipv6;
658 struct rte_flow_item_ipv6 ipv6_mask;
659 struct field_modify_info *field;
662 flow_dv_attr_init(items, attr);
664 memset(&ipv4, 0, sizeof(ipv4));
665 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
666 ipv4.hdr.time_to_live = conf->ttl_value;
667 ipv4_mask.hdr.time_to_live = 0xFF;
668 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
670 item.mask = &ipv4_mask;
674 memset(&ipv6, 0, sizeof(ipv6));
675 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
676 ipv6.hdr.hop_limits = conf->ttl_value;
677 ipv6_mask.hdr.hop_limits = 0xFF;
678 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
680 item.mask = &ipv6_mask;
683 return flow_dv_convert_modify_action(&item, field, NULL, resource,
684 MLX5_MODIFICATION_TYPE_SET, error);
688 * Convert modify-header decrement TTL action to DV specification.
690 * @param[in,out] resource
691 * Pointer to the modify-header resource.
693 * Pointer to action specification.
695 * Pointer to rte_flow_item objects list.
697 * Pointer to flow attributes structure.
699 * Pointer to the error structure.
702 * 0 on success, a negative errno value otherwise and rte_errno is set.
705 flow_dv_convert_action_modify_dec_ttl
706 (struct mlx5_flow_dv_modify_hdr_resource *resource,
707 const struct rte_flow_item *items,
708 union flow_dv_attr *attr,
709 struct rte_flow_error *error)
711 struct rte_flow_item item;
712 struct rte_flow_item_ipv4 ipv4;
713 struct rte_flow_item_ipv4 ipv4_mask;
714 struct rte_flow_item_ipv6 ipv6;
715 struct rte_flow_item_ipv6 ipv6_mask;
716 struct field_modify_info *field;
719 flow_dv_attr_init(items, attr);
721 memset(&ipv4, 0, sizeof(ipv4));
722 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
723 ipv4.hdr.time_to_live = 0xFF;
724 ipv4_mask.hdr.time_to_live = 0xFF;
725 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
727 item.mask = &ipv4_mask;
731 memset(&ipv6, 0, sizeof(ipv6));
732 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
733 ipv6.hdr.hop_limits = 0xFF;
734 ipv6_mask.hdr.hop_limits = 0xFF;
735 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
737 item.mask = &ipv6_mask;
740 return flow_dv_convert_modify_action(&item, field, NULL, resource,
741 MLX5_MODIFICATION_TYPE_ADD, error);
745 * Convert modify-header increment/decrement TCP Sequence number
746 * to DV specification.
748 * @param[in,out] resource
749 * Pointer to the modify-header resource.
751 * Pointer to action specification.
753 * Pointer to the error structure.
756 * 0 on success, a negative errno value otherwise and rte_errno is set.
759 flow_dv_convert_action_modify_tcp_seq
760 (struct mlx5_flow_dv_modify_hdr_resource *resource,
761 const struct rte_flow_action *action,
762 struct rte_flow_error *error)
764 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
765 uint64_t value = rte_be_to_cpu_32(*conf);
766 struct rte_flow_item item;
767 struct rte_flow_item_tcp tcp;
768 struct rte_flow_item_tcp tcp_mask;
770 memset(&tcp, 0, sizeof(tcp));
771 memset(&tcp_mask, 0, sizeof(tcp_mask));
772 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
774 * The HW has no decrement operation, only increment operation.
775 * To simulate decrement X from Y using increment operation
776 * we need to add UINT32_MAX X times to Y.
777 * Each adding of UINT32_MAX decrements Y by 1.
780 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
781 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
785 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
786 MLX5_MODIFICATION_TYPE_ADD, error);
790 * Convert modify-header increment/decrement TCP Acknowledgment number
791 * to DV specification.
793 * @param[in,out] resource
794 * Pointer to the modify-header resource.
796 * Pointer to action specification.
798 * Pointer to the error structure.
801 * 0 on success, a negative errno value otherwise and rte_errno is set.
804 flow_dv_convert_action_modify_tcp_ack
805 (struct mlx5_flow_dv_modify_hdr_resource *resource,
806 const struct rte_flow_action *action,
807 struct rte_flow_error *error)
809 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
810 uint64_t value = rte_be_to_cpu_32(*conf);
811 struct rte_flow_item item;
812 struct rte_flow_item_tcp tcp;
813 struct rte_flow_item_tcp tcp_mask;
815 memset(&tcp, 0, sizeof(tcp));
816 memset(&tcp_mask, 0, sizeof(tcp_mask));
817 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
819 * The HW has no decrement operation, only increment operation.
820 * To simulate decrement X from Y using increment operation
821 * we need to add UINT32_MAX X times to Y.
822 * Each adding of UINT32_MAX decrements Y by 1.
825 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
826 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
827 item.type = RTE_FLOW_ITEM_TYPE_TCP;
829 item.mask = &tcp_mask;
830 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
831 MLX5_MODIFICATION_TYPE_ADD, error);
834 static enum mlx5_modification_field reg_to_field[] = {
835 [REG_A] = MLX5_MODI_META_DATA_REG_A,
836 [REG_B] = MLX5_MODI_META_DATA_REG_B,
837 [REG_C_0] = MLX5_MODI_META_REG_C_0,
838 [REG_C_1] = MLX5_MODI_META_REG_C_1,
839 [REG_C_2] = MLX5_MODI_META_REG_C_2,
840 [REG_C_3] = MLX5_MODI_META_REG_C_3,
841 [REG_C_4] = MLX5_MODI_META_REG_C_4,
842 [REG_C_5] = MLX5_MODI_META_REG_C_5,
843 [REG_C_6] = MLX5_MODI_META_REG_C_6,
844 [REG_C_7] = MLX5_MODI_META_REG_C_7,
848 * Convert register set to DV specification.
850 * @param[in,out] resource
851 * Pointer to the modify-header resource.
853 * Pointer to action specification.
855 * Pointer to the error structure.
858 * 0 on success, a negative errno value otherwise and rte_errno is set.
861 flow_dv_convert_action_set_reg
862 (struct mlx5_flow_dv_modify_hdr_resource *resource,
863 const struct rte_flow_action *action,
864 struct rte_flow_error *error)
866 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
867 struct mlx5_modification_cmd *actions = resource->actions;
868 uint32_t i = resource->actions_num;
870 if (i >= MLX5_MODIFY_NUM)
871 return rte_flow_error_set(error, EINVAL,
872 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
873 "too many items to modify");
874 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
875 actions[i].field = reg_to_field[conf->id];
876 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
877 actions[i].data1 = conf->data;
879 resource->actions_num = i;
880 if (!resource->actions_num)
881 return rte_flow_error_set(error, EINVAL,
882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
883 "invalid modification flow item");
888 * Convert internal COPY_REG action to DV specification.
891 * Pointer to the rte_eth_dev structure.
893 * Pointer to the modify-header resource.
895 * Pointer to action specification.
897 * Pointer to the error structure.
900 * 0 on success, a negative errno value otherwise and rte_errno is set.
903 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev __rte_unused,
904 struct mlx5_flow_dv_modify_hdr_resource *res,
905 const struct rte_flow_action *action,
906 struct rte_flow_error *error)
908 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
909 uint32_t mask = RTE_BE32(UINT32_MAX);
910 struct rte_flow_item item = {
914 struct field_modify_info reg_src[] = {
915 {4, 0, reg_to_field[conf->src]},
918 struct field_modify_info reg_dst = {
919 .offset = (uint32_t)-1, /* Same as src. */
920 .id = reg_to_field[conf->dst],
922 return flow_dv_convert_modify_action(&item,
923 reg_src, ®_dst, res,
924 MLX5_MODIFICATION_TYPE_COPY,
929 * Validate META item.
932 * Pointer to the rte_eth_dev structure.
934 * Item specification.
936 * Attributes of flow that includes this item.
938 * Pointer to error structure.
941 * 0 on success, a negative errno value otherwise and rte_errno is set.
944 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
945 const struct rte_flow_item *item,
946 const struct rte_flow_attr *attr,
947 struct rte_flow_error *error)
949 const struct rte_flow_item_meta *spec = item->spec;
950 const struct rte_flow_item_meta *mask = item->mask;
951 const struct rte_flow_item_meta nic_mask = {
957 return rte_flow_error_set(error, EINVAL,
958 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
960 "data cannot be empty");
962 return rte_flow_error_set(error, EINVAL,
963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
965 "data cannot be zero");
967 mask = &rte_flow_item_meta_mask;
968 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
969 (const uint8_t *)&nic_mask,
970 sizeof(struct rte_flow_item_meta),
975 return rte_flow_error_set(error, ENOTSUP,
976 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
978 "pattern not supported for ingress");
983 * Validate vport item.
986 * Pointer to the rte_eth_dev structure.
988 * Item specification.
990 * Attributes of flow that includes this item.
991 * @param[in] item_flags
992 * Bit-fields that holds the items detected until now.
994 * Pointer to error structure.
997 * 0 on success, a negative errno value otherwise and rte_errno is set.
1000 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1001 const struct rte_flow_item *item,
1002 const struct rte_flow_attr *attr,
1003 uint64_t item_flags,
1004 struct rte_flow_error *error)
1006 const struct rte_flow_item_port_id *spec = item->spec;
1007 const struct rte_flow_item_port_id *mask = item->mask;
1008 const struct rte_flow_item_port_id switch_mask = {
1011 struct mlx5_priv *esw_priv;
1012 struct mlx5_priv *dev_priv;
1015 if (!attr->transfer)
1016 return rte_flow_error_set(error, EINVAL,
1017 RTE_FLOW_ERROR_TYPE_ITEM,
1019 "match on port id is valid only"
1020 " when transfer flag is enabled");
1021 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1022 return rte_flow_error_set(error, ENOTSUP,
1023 RTE_FLOW_ERROR_TYPE_ITEM, item,
1024 "multiple source ports are not"
1027 mask = &switch_mask;
1028 if (mask->id != 0xffffffff)
1029 return rte_flow_error_set(error, ENOTSUP,
1030 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1032 "no support for partial mask on"
1034 ret = mlx5_flow_item_acceptable
1035 (item, (const uint8_t *)mask,
1036 (const uint8_t *)&rte_flow_item_port_id_mask,
1037 sizeof(struct rte_flow_item_port_id),
1043 esw_priv = mlx5_port_to_eswitch_info(spec->id);
1045 return rte_flow_error_set(error, rte_errno,
1046 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1047 "failed to obtain E-Switch info for"
1049 dev_priv = mlx5_dev_to_eswitch_info(dev);
1051 return rte_flow_error_set(error, rte_errno,
1052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1054 "failed to obtain E-Switch info");
1055 if (esw_priv->domain_id != dev_priv->domain_id)
1056 return rte_flow_error_set(error, EINVAL,
1057 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1058 "cannot match on a port from a"
1059 " different E-Switch");
1064 * Validate the pop VLAN action.
1067 * Pointer to the rte_eth_dev structure.
1068 * @param[in] action_flags
1069 * Holds the actions detected until now.
1071 * Pointer to the pop vlan action.
1072 * @param[in] item_flags
1073 * The items found in this flow rule.
1075 * Pointer to flow attributes.
1077 * Pointer to error structure.
1080 * 0 on success, a negative errno value otherwise and rte_errno is set.
1083 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1084 uint64_t action_flags,
1085 const struct rte_flow_action *action,
1086 uint64_t item_flags,
1087 const struct rte_flow_attr *attr,
1088 struct rte_flow_error *error)
1090 struct mlx5_priv *priv = dev->data->dev_private;
1094 if (!priv->sh->pop_vlan_action)
1095 return rte_flow_error_set(error, ENOTSUP,
1096 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1098 "pop vlan action is not supported");
1100 * Check for inconsistencies:
1101 * fail strip_vlan in a flow that matches packets without VLAN tags.
1102 * fail strip_vlan in a flow that matches packets without explicitly a
1103 * matching on VLAN tag ?
1105 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1106 return rte_flow_error_set(error, ENOTSUP,
1107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1109 "no support for multiple vlan pop "
1111 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1112 return rte_flow_error_set(error, ENOTSUP,
1113 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1115 "cannot pop vlan without a "
1116 "match on (outer) vlan in the flow");
1117 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1118 return rte_flow_error_set(error, EINVAL,
1119 RTE_FLOW_ERROR_TYPE_ACTION, action,
1120 "wrong action order, port_id should "
1121 "be after pop VLAN action");
1126 * Get VLAN default info from vlan match info.
1129 * Pointer to the rte_eth_dev structure.
1131 * the list of item specifications.
1133 * pointer VLAN info to fill to.
1135 * Pointer to error structure.
1138 * 0 on success, a negative errno value otherwise and rte_errno is set.
1141 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1142 struct rte_vlan_hdr *vlan)
1144 const struct rte_flow_item_vlan nic_mask = {
1145 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1146 MLX5DV_FLOW_VLAN_VID_MASK),
1147 .inner_type = RTE_BE16(0xffff),
1152 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1153 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1155 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1156 const struct rte_flow_item_vlan *vlan_m = items->mask;
1157 const struct rte_flow_item_vlan *vlan_v = items->spec;
1161 /* Only full match values are accepted */
1162 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1163 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1164 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1166 rte_be_to_cpu_16(vlan_v->tci &
1167 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1169 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1170 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1171 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1173 rte_be_to_cpu_16(vlan_v->tci &
1174 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1176 if (vlan_m->inner_type == nic_mask.inner_type)
1177 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1178 vlan_m->inner_type);
1183 * Validate the push VLAN action.
1185 * @param[in] action_flags
1186 * Holds the actions detected until now.
1188 * Pointer to the encap action.
1190 * Pointer to flow attributes
1192 * Pointer to error structure.
1195 * 0 on success, a negative errno value otherwise and rte_errno is set.
1198 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1199 uint64_t item_flags,
1200 const struct rte_flow_action *action,
1201 const struct rte_flow_attr *attr,
1202 struct rte_flow_error *error)
1204 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1206 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1207 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1208 return rte_flow_error_set(error, EINVAL,
1209 RTE_FLOW_ERROR_TYPE_ACTION, action,
1210 "invalid vlan ethertype");
1212 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1213 return rte_flow_error_set(error, ENOTSUP,
1214 RTE_FLOW_ERROR_TYPE_ACTION, action,
1215 "no support for multiple VLAN "
1217 if (!mlx5_flow_find_action
1218 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1219 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1220 return rte_flow_error_set(error, ENOTSUP,
1221 RTE_FLOW_ERROR_TYPE_ACTION, action,
1222 "push VLAN needs to match on VLAN in order to "
1223 "get VLAN VID information because there is "
1224 "no followed set VLAN VID action");
1225 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1226 return rte_flow_error_set(error, EINVAL,
1227 RTE_FLOW_ERROR_TYPE_ACTION, action,
1228 "wrong action order, port_id should "
1229 "be after push VLAN");
1235 * Validate the set VLAN PCP.
1237 * @param[in] action_flags
1238 * Holds the actions detected until now.
1239 * @param[in] actions
1240 * Pointer to the list of actions remaining in the flow rule.
1242 * Pointer to flow attributes
1244 * Pointer to error structure.
1247 * 0 on success, a negative errno value otherwise and rte_errno is set.
1250 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1251 const struct rte_flow_action actions[],
1252 struct rte_flow_error *error)
1254 const struct rte_flow_action *action = actions;
1255 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1257 if (conf->vlan_pcp > 7)
1258 return rte_flow_error_set(error, EINVAL,
1259 RTE_FLOW_ERROR_TYPE_ACTION, action,
1260 "VLAN PCP value is too big");
1261 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1262 return rte_flow_error_set(error, ENOTSUP,
1263 RTE_FLOW_ERROR_TYPE_ACTION, action,
1264 "set VLAN PCP action must follow "
1265 "the push VLAN action");
1266 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1267 return rte_flow_error_set(error, ENOTSUP,
1268 RTE_FLOW_ERROR_TYPE_ACTION, action,
1269 "Multiple VLAN PCP modification are "
1271 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1272 return rte_flow_error_set(error, EINVAL,
1273 RTE_FLOW_ERROR_TYPE_ACTION, action,
1274 "wrong action order, port_id should "
1275 "be after set VLAN PCP");
1280 * Validate the set VLAN VID.
1282 * @param[in] item_flags
1283 * Holds the items detected in this rule.
1284 * @param[in] actions
1285 * Pointer to the list of actions remaining in the flow rule.
1287 * Pointer to flow attributes
1289 * Pointer to error structure.
1292 * 0 on success, a negative errno value otherwise and rte_errno is set.
1295 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1296 uint64_t action_flags,
1297 const struct rte_flow_action actions[],
1298 struct rte_flow_error *error)
1300 const struct rte_flow_action *action = actions;
1301 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1303 if (conf->vlan_vid > RTE_BE16(0xFFE))
1304 return rte_flow_error_set(error, EINVAL,
1305 RTE_FLOW_ERROR_TYPE_ACTION, action,
1306 "VLAN VID value is too big");
1307 /* there is an of_push_vlan action before us */
1308 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1309 if (mlx5_flow_find_action(actions + 1,
1310 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1311 return rte_flow_error_set(error, ENOTSUP,
1312 RTE_FLOW_ERROR_TYPE_ACTION, action,
1313 "Multiple VLAN VID modifications are "
1320 * Action is on an existing VLAN header:
1321 * Need to verify this is a single modify CID action.
1322 * Rule mast include a match on outer VLAN.
1324 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1325 return rte_flow_error_set(error, ENOTSUP,
1326 RTE_FLOW_ERROR_TYPE_ACTION, action,
1327 "Multiple VLAN VID modifications are "
1329 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1330 return rte_flow_error_set(error, EINVAL,
1331 RTE_FLOW_ERROR_TYPE_ACTION, action,
1332 "match on VLAN is required in order "
1334 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1335 return rte_flow_error_set(error, EINVAL,
1336 RTE_FLOW_ERROR_TYPE_ACTION, action,
1337 "wrong action order, port_id should "
1338 "be after set VLAN VID");
1343 * Validate count action.
1348 * Pointer to error structure.
1351 * 0 on success, a negative errno value otherwise and rte_errno is set.
1354 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1355 struct rte_flow_error *error)
1357 struct mlx5_priv *priv = dev->data->dev_private;
1359 if (!priv->config.devx)
1361 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1365 return rte_flow_error_set
1367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1369 "count action not supported");
1373 * Validate the L2 encap action.
1375 * @param[in] action_flags
1376 * Holds the actions detected until now.
1378 * Pointer to the encap action.
1380 * Pointer to flow attributes
1382 * Pointer to error structure.
1385 * 0 on success, a negative errno value otherwise and rte_errno is set.
1388 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1389 const struct rte_flow_action *action,
1390 const struct rte_flow_attr *attr,
1391 struct rte_flow_error *error)
1393 if (!(action->conf))
1394 return rte_flow_error_set(error, EINVAL,
1395 RTE_FLOW_ERROR_TYPE_ACTION, action,
1396 "configuration cannot be null");
1397 if (action_flags & MLX5_FLOW_ACTION_DROP)
1398 return rte_flow_error_set(error, EINVAL,
1399 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1400 "can't drop and encap in same flow");
1401 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1402 return rte_flow_error_set(error, EINVAL,
1403 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1404 "can only have a single encap or"
1405 " decap action in a flow");
1406 if (!attr->transfer && attr->ingress)
1407 return rte_flow_error_set(error, ENOTSUP,
1408 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1410 "encap action not supported for "
1416 * Validate the L2 decap action.
1418 * @param[in] action_flags
1419 * Holds the actions detected until now.
1421 * Pointer to flow attributes
1423 * Pointer to error structure.
1426 * 0 on success, a negative errno value otherwise and rte_errno is set.
1429 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1430 const struct rte_flow_attr *attr,
1431 struct rte_flow_error *error)
1433 if (action_flags & MLX5_FLOW_ACTION_DROP)
1434 return rte_flow_error_set(error, EINVAL,
1435 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1436 "can't drop and decap in same flow");
1437 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1438 return rte_flow_error_set(error, EINVAL,
1439 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1440 "can only have a single encap or"
1441 " decap action in a flow");
1442 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1443 return rte_flow_error_set(error, EINVAL,
1444 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1445 "can't have decap action after"
1448 return rte_flow_error_set(error, ENOTSUP,
1449 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1451 "decap action not supported for "
1457 * Validate the raw encap action.
1459 * @param[in] action_flags
1460 * Holds the actions detected until now.
1462 * Pointer to the encap action.
1464 * Pointer to flow attributes
1466 * Pointer to error structure.
1469 * 0 on success, a negative errno value otherwise and rte_errno is set.
1472 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1473 const struct rte_flow_action *action,
1474 const struct rte_flow_attr *attr,
1475 struct rte_flow_error *error)
1477 const struct rte_flow_action_raw_encap *raw_encap =
1478 (const struct rte_flow_action_raw_encap *)action->conf;
1479 if (!(action->conf))
1480 return rte_flow_error_set(error, EINVAL,
1481 RTE_FLOW_ERROR_TYPE_ACTION, action,
1482 "configuration cannot be null");
1483 if (action_flags & MLX5_FLOW_ACTION_DROP)
1484 return rte_flow_error_set(error, EINVAL,
1485 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1486 "can't drop and encap in same flow");
1487 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1488 return rte_flow_error_set(error, EINVAL,
1489 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1490 "can only have a single encap"
1491 " action in a flow");
1492 /* encap without preceding decap is not supported for ingress */
1493 if (!attr->transfer && attr->ingress &&
1494 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1495 return rte_flow_error_set(error, ENOTSUP,
1496 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1498 "encap action not supported for "
1500 if (!raw_encap->size || !raw_encap->data)
1501 return rte_flow_error_set(error, EINVAL,
1502 RTE_FLOW_ERROR_TYPE_ACTION, action,
1503 "raw encap data cannot be empty");
1508 * Validate the raw decap action.
1510 * @param[in] action_flags
1511 * Holds the actions detected until now.
1513 * Pointer to the encap action.
1515 * Pointer to flow attributes
1517 * Pointer to error structure.
1520 * 0 on success, a negative errno value otherwise and rte_errno is set.
1523 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1524 const struct rte_flow_action *action,
1525 const struct rte_flow_attr *attr,
1526 struct rte_flow_error *error)
1528 if (action_flags & MLX5_FLOW_ACTION_DROP)
1529 return rte_flow_error_set(error, EINVAL,
1530 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1531 "can't drop and decap in same flow");
1532 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1533 return rte_flow_error_set(error, EINVAL,
1534 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1535 "can't have encap action before"
1537 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1540 "can only have a single decap"
1541 " action in a flow");
1542 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1543 return rte_flow_error_set(error, EINVAL,
1544 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1545 "can't have decap action after"
1547 /* decap action is valid on egress only if it is followed by encap */
1549 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1550 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1553 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1554 return rte_flow_error_set
1556 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1557 NULL, "decap action not supported"
1564 * Find existing encap/decap resource or create and register a new one.
1566 * @param dev[in, out]
1567 * Pointer to rte_eth_dev structure.
1568 * @param[in, out] resource
1569 * Pointer to encap/decap resource.
1570 * @parm[in, out] dev_flow
1571 * Pointer to the dev_flow.
1573 * pointer to error structure.
1576 * 0 on success otherwise -errno and errno is set.
1579 flow_dv_encap_decap_resource_register
1580 (struct rte_eth_dev *dev,
1581 struct mlx5_flow_dv_encap_decap_resource *resource,
1582 struct mlx5_flow *dev_flow,
1583 struct rte_flow_error *error)
1585 struct mlx5_priv *priv = dev->data->dev_private;
1586 struct mlx5_ibv_shared *sh = priv->sh;
1587 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1588 struct rte_flow *flow = dev_flow->flow;
1589 struct mlx5dv_dr_domain *domain;
1591 resource->flags = flow->group ? 0 : 1;
1592 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1593 domain = sh->fdb_domain;
1594 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1595 domain = sh->rx_domain;
1597 domain = sh->tx_domain;
1599 /* Lookup a matching resource from cache. */
1600 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1601 if (resource->reformat_type == cache_resource->reformat_type &&
1602 resource->ft_type == cache_resource->ft_type &&
1603 resource->flags == cache_resource->flags &&
1604 resource->size == cache_resource->size &&
1605 !memcmp((const void *)resource->buf,
1606 (const void *)cache_resource->buf,
1608 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1609 (void *)cache_resource,
1610 rte_atomic32_read(&cache_resource->refcnt));
1611 rte_atomic32_inc(&cache_resource->refcnt);
1612 dev_flow->dv.encap_decap = cache_resource;
1616 /* Register new encap/decap resource. */
1617 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1618 if (!cache_resource)
1619 return rte_flow_error_set(error, ENOMEM,
1620 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1621 "cannot allocate resource memory");
1622 *cache_resource = *resource;
1623 cache_resource->verbs_action =
1624 mlx5_glue->dv_create_flow_action_packet_reformat
1625 (sh->ctx, cache_resource->reformat_type,
1626 cache_resource->ft_type, domain, cache_resource->flags,
1627 cache_resource->size,
1628 (cache_resource->size ? cache_resource->buf : NULL));
1629 if (!cache_resource->verbs_action) {
1630 rte_free(cache_resource);
1631 return rte_flow_error_set(error, ENOMEM,
1632 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1633 NULL, "cannot create action");
1635 rte_atomic32_init(&cache_resource->refcnt);
1636 rte_atomic32_inc(&cache_resource->refcnt);
1637 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1638 dev_flow->dv.encap_decap = cache_resource;
1639 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1640 (void *)cache_resource,
1641 rte_atomic32_read(&cache_resource->refcnt));
1646 * Find existing table jump resource or create and register a new one.
1648 * @param dev[in, out]
1649 * Pointer to rte_eth_dev structure.
1650 * @param[in, out] resource
1651 * Pointer to jump table resource.
1652 * @parm[in, out] dev_flow
1653 * Pointer to the dev_flow.
1655 * pointer to error structure.
1658 * 0 on success otherwise -errno and errno is set.
1661 flow_dv_jump_tbl_resource_register
1662 (struct rte_eth_dev *dev,
1663 struct mlx5_flow_dv_jump_tbl_resource *resource,
1664 struct mlx5_flow *dev_flow,
1665 struct rte_flow_error *error)
1667 struct mlx5_priv *priv = dev->data->dev_private;
1668 struct mlx5_ibv_shared *sh = priv->sh;
1669 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1671 /* Lookup a matching resource from cache. */
1672 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1673 if (resource->tbl == cache_resource->tbl) {
1674 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1675 (void *)cache_resource,
1676 rte_atomic32_read(&cache_resource->refcnt));
1677 rte_atomic32_inc(&cache_resource->refcnt);
1678 dev_flow->dv.jump = cache_resource;
1682 /* Register new jump table resource. */
1683 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1684 if (!cache_resource)
1685 return rte_flow_error_set(error, ENOMEM,
1686 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1687 "cannot allocate resource memory");
1688 *cache_resource = *resource;
1689 cache_resource->action =
1690 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1691 (resource->tbl->obj);
1692 if (!cache_resource->action) {
1693 rte_free(cache_resource);
1694 return rte_flow_error_set(error, ENOMEM,
1695 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1696 NULL, "cannot create action");
1698 rte_atomic32_init(&cache_resource->refcnt);
1699 rte_atomic32_inc(&cache_resource->refcnt);
1700 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1701 dev_flow->dv.jump = cache_resource;
1702 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1703 (void *)cache_resource,
1704 rte_atomic32_read(&cache_resource->refcnt));
1709 * Find existing table port ID resource or create and register a new one.
1711 * @param dev[in, out]
1712 * Pointer to rte_eth_dev structure.
1713 * @param[in, out] resource
1714 * Pointer to port ID action resource.
1715 * @parm[in, out] dev_flow
1716 * Pointer to the dev_flow.
1718 * pointer to error structure.
1721 * 0 on success otherwise -errno and errno is set.
1724 flow_dv_port_id_action_resource_register
1725 (struct rte_eth_dev *dev,
1726 struct mlx5_flow_dv_port_id_action_resource *resource,
1727 struct mlx5_flow *dev_flow,
1728 struct rte_flow_error *error)
1730 struct mlx5_priv *priv = dev->data->dev_private;
1731 struct mlx5_ibv_shared *sh = priv->sh;
1732 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1734 /* Lookup a matching resource from cache. */
1735 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1736 if (resource->port_id == cache_resource->port_id) {
1737 DRV_LOG(DEBUG, "port id action resource resource %p: "
1739 (void *)cache_resource,
1740 rte_atomic32_read(&cache_resource->refcnt));
1741 rte_atomic32_inc(&cache_resource->refcnt);
1742 dev_flow->dv.port_id_action = cache_resource;
1746 /* Register new port id action resource. */
1747 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1748 if (!cache_resource)
1749 return rte_flow_error_set(error, ENOMEM,
1750 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1751 "cannot allocate resource memory");
1752 *cache_resource = *resource;
1753 cache_resource->action =
1754 mlx5_glue->dr_create_flow_action_dest_vport
1755 (priv->sh->fdb_domain, resource->port_id);
1756 if (!cache_resource->action) {
1757 rte_free(cache_resource);
1758 return rte_flow_error_set(error, ENOMEM,
1759 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1760 NULL, "cannot create action");
1762 rte_atomic32_init(&cache_resource->refcnt);
1763 rte_atomic32_inc(&cache_resource->refcnt);
1764 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1765 dev_flow->dv.port_id_action = cache_resource;
1766 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1767 (void *)cache_resource,
1768 rte_atomic32_read(&cache_resource->refcnt));
1773 * Find existing push vlan resource or create and register a new one.
1775 * @param dev[in, out]
1776 * Pointer to rte_eth_dev structure.
1777 * @param[in, out] resource
1778 * Pointer to port ID action resource.
1779 * @parm[in, out] dev_flow
1780 * Pointer to the dev_flow.
1782 * pointer to error structure.
1785 * 0 on success otherwise -errno and errno is set.
1788 flow_dv_push_vlan_action_resource_register
1789 (struct rte_eth_dev *dev,
1790 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1791 struct mlx5_flow *dev_flow,
1792 struct rte_flow_error *error)
1794 struct mlx5_priv *priv = dev->data->dev_private;
1795 struct mlx5_ibv_shared *sh = priv->sh;
1796 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1797 struct mlx5dv_dr_domain *domain;
1799 /* Lookup a matching resource from cache. */
1800 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1801 if (resource->vlan_tag == cache_resource->vlan_tag &&
1802 resource->ft_type == cache_resource->ft_type) {
1803 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1805 (void *)cache_resource,
1806 rte_atomic32_read(&cache_resource->refcnt));
1807 rte_atomic32_inc(&cache_resource->refcnt);
1808 dev_flow->dv.push_vlan_res = cache_resource;
1812 /* Register new push_vlan action resource. */
1813 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1814 if (!cache_resource)
1815 return rte_flow_error_set(error, ENOMEM,
1816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1817 "cannot allocate resource memory");
1818 *cache_resource = *resource;
1819 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1820 domain = sh->fdb_domain;
1821 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1822 domain = sh->rx_domain;
1824 domain = sh->tx_domain;
1825 cache_resource->action =
1826 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1827 resource->vlan_tag);
1828 if (!cache_resource->action) {
1829 rte_free(cache_resource);
1830 return rte_flow_error_set(error, ENOMEM,
1831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1832 NULL, "cannot create action");
1834 rte_atomic32_init(&cache_resource->refcnt);
1835 rte_atomic32_inc(&cache_resource->refcnt);
1836 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1837 dev_flow->dv.push_vlan_res = cache_resource;
1838 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1839 (void *)cache_resource,
1840 rte_atomic32_read(&cache_resource->refcnt));
1844 * Get the size of specific rte_flow_item_type
1846 * @param[in] item_type
1847 * Tested rte_flow_item_type.
1850 * sizeof struct item_type, 0 if void or irrelevant.
1853 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1857 switch (item_type) {
1858 case RTE_FLOW_ITEM_TYPE_ETH:
1859 retval = sizeof(struct rte_flow_item_eth);
1861 case RTE_FLOW_ITEM_TYPE_VLAN:
1862 retval = sizeof(struct rte_flow_item_vlan);
1864 case RTE_FLOW_ITEM_TYPE_IPV4:
1865 retval = sizeof(struct rte_flow_item_ipv4);
1867 case RTE_FLOW_ITEM_TYPE_IPV6:
1868 retval = sizeof(struct rte_flow_item_ipv6);
1870 case RTE_FLOW_ITEM_TYPE_UDP:
1871 retval = sizeof(struct rte_flow_item_udp);
1873 case RTE_FLOW_ITEM_TYPE_TCP:
1874 retval = sizeof(struct rte_flow_item_tcp);
1876 case RTE_FLOW_ITEM_TYPE_VXLAN:
1877 retval = sizeof(struct rte_flow_item_vxlan);
1879 case RTE_FLOW_ITEM_TYPE_GRE:
1880 retval = sizeof(struct rte_flow_item_gre);
1882 case RTE_FLOW_ITEM_TYPE_NVGRE:
1883 retval = sizeof(struct rte_flow_item_nvgre);
1885 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1886 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1888 case RTE_FLOW_ITEM_TYPE_MPLS:
1889 retval = sizeof(struct rte_flow_item_mpls);
1891 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1899 #define MLX5_ENCAP_IPV4_VERSION 0x40
1900 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1901 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1902 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1903 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1904 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1905 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1908 * Convert the encap action data from list of rte_flow_item to raw buffer
1911 * Pointer to rte_flow_item objects list.
1913 * Pointer to the output buffer.
1915 * Pointer to the output buffer size.
1917 * Pointer to the error structure.
1920 * 0 on success, a negative errno value otherwise and rte_errno is set.
1923 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1924 size_t *size, struct rte_flow_error *error)
1926 struct rte_ether_hdr *eth = NULL;
1927 struct rte_vlan_hdr *vlan = NULL;
1928 struct rte_ipv4_hdr *ipv4 = NULL;
1929 struct rte_ipv6_hdr *ipv6 = NULL;
1930 struct rte_udp_hdr *udp = NULL;
1931 struct rte_vxlan_hdr *vxlan = NULL;
1932 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1933 struct rte_gre_hdr *gre = NULL;
1935 size_t temp_size = 0;
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION,
1940 NULL, "invalid empty data");
1941 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1942 len = flow_dv_get_item_len(items->type);
1943 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1944 return rte_flow_error_set(error, EINVAL,
1945 RTE_FLOW_ERROR_TYPE_ACTION,
1946 (void *)items->type,
1947 "items total size is too big"
1948 " for encap action");
1949 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1950 switch (items->type) {
1951 case RTE_FLOW_ITEM_TYPE_ETH:
1952 eth = (struct rte_ether_hdr *)&buf[temp_size];
1954 case RTE_FLOW_ITEM_TYPE_VLAN:
1955 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION,
1959 (void *)items->type,
1960 "eth header not found");
1961 if (!eth->ether_type)
1962 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1964 case RTE_FLOW_ITEM_TYPE_IPV4:
1965 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION,
1969 (void *)items->type,
1970 "neither eth nor vlan"
1972 if (vlan && !vlan->eth_proto)
1973 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1974 else if (eth && !eth->ether_type)
1975 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1976 if (!ipv4->version_ihl)
1977 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1978 MLX5_ENCAP_IPV4_IHL_MIN;
1979 if (!ipv4->time_to_live)
1980 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1982 case RTE_FLOW_ITEM_TYPE_IPV6:
1983 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1985 return rte_flow_error_set(error, EINVAL,
1986 RTE_FLOW_ERROR_TYPE_ACTION,
1987 (void *)items->type,
1988 "neither eth nor vlan"
1990 if (vlan && !vlan->eth_proto)
1991 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1992 else if (eth && !eth->ether_type)
1993 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1994 if (!ipv6->vtc_flow)
1996 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1997 if (!ipv6->hop_limits)
1998 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2000 case RTE_FLOW_ITEM_TYPE_UDP:
2001 udp = (struct rte_udp_hdr *)&buf[temp_size];
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ACTION,
2005 (void *)items->type,
2006 "ip header not found");
2007 if (ipv4 && !ipv4->next_proto_id)
2008 ipv4->next_proto_id = IPPROTO_UDP;
2009 else if (ipv6 && !ipv6->proto)
2010 ipv6->proto = IPPROTO_UDP;
2012 case RTE_FLOW_ITEM_TYPE_VXLAN:
2013 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2015 return rte_flow_error_set(error, EINVAL,
2016 RTE_FLOW_ERROR_TYPE_ACTION,
2017 (void *)items->type,
2018 "udp header not found");
2020 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2021 if (!vxlan->vx_flags)
2023 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2025 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2026 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2028 return rte_flow_error_set(error, EINVAL,
2029 RTE_FLOW_ERROR_TYPE_ACTION,
2030 (void *)items->type,
2031 "udp header not found");
2032 if (!vxlan_gpe->proto)
2033 return rte_flow_error_set(error, EINVAL,
2034 RTE_FLOW_ERROR_TYPE_ACTION,
2035 (void *)items->type,
2036 "next protocol not found");
2039 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2040 if (!vxlan_gpe->vx_flags)
2041 vxlan_gpe->vx_flags =
2042 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2044 case RTE_FLOW_ITEM_TYPE_GRE:
2045 case RTE_FLOW_ITEM_TYPE_NVGRE:
2046 gre = (struct rte_gre_hdr *)&buf[temp_size];
2048 return rte_flow_error_set(error, EINVAL,
2049 RTE_FLOW_ERROR_TYPE_ACTION,
2050 (void *)items->type,
2051 "next protocol not found");
2053 return rte_flow_error_set(error, EINVAL,
2054 RTE_FLOW_ERROR_TYPE_ACTION,
2055 (void *)items->type,
2056 "ip header not found");
2057 if (ipv4 && !ipv4->next_proto_id)
2058 ipv4->next_proto_id = IPPROTO_GRE;
2059 else if (ipv6 && !ipv6->proto)
2060 ipv6->proto = IPPROTO_GRE;
2062 case RTE_FLOW_ITEM_TYPE_VOID:
2065 return rte_flow_error_set(error, EINVAL,
2066 RTE_FLOW_ERROR_TYPE_ACTION,
2067 (void *)items->type,
2068 "unsupported item type");
2078 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2080 struct rte_ether_hdr *eth = NULL;
2081 struct rte_vlan_hdr *vlan = NULL;
2082 struct rte_ipv6_hdr *ipv6 = NULL;
2083 struct rte_udp_hdr *udp = NULL;
2087 eth = (struct rte_ether_hdr *)data;
2088 next_hdr = (char *)(eth + 1);
2089 proto = RTE_BE16(eth->ether_type);
2092 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2093 vlan = (struct rte_vlan_hdr *)next_hdr;
2094 proto = RTE_BE16(vlan->eth_proto);
2095 next_hdr += sizeof(struct rte_vlan_hdr);
2098 /* HW calculates IPv4 csum. no need to proceed */
2099 if (proto == RTE_ETHER_TYPE_IPV4)
2102 /* non IPv4/IPv6 header. not supported */
2103 if (proto != RTE_ETHER_TYPE_IPV6) {
2104 return rte_flow_error_set(error, ENOTSUP,
2105 RTE_FLOW_ERROR_TYPE_ACTION,
2106 NULL, "Cannot offload non IPv4/IPv6");
2109 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2111 /* ignore non UDP */
2112 if (ipv6->proto != IPPROTO_UDP)
2115 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2116 udp->dgram_cksum = 0;
2122 * Convert L2 encap action to DV specification.
2125 * Pointer to rte_eth_dev structure.
2127 * Pointer to action structure.
2128 * @param[in, out] dev_flow
2129 * Pointer to the mlx5_flow.
2130 * @param[in] transfer
2131 * Mark if the flow is E-Switch flow.
2133 * Pointer to the error structure.
2136 * 0 on success, a negative errno value otherwise and rte_errno is set.
2139 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2140 const struct rte_flow_action *action,
2141 struct mlx5_flow *dev_flow,
2143 struct rte_flow_error *error)
2145 const struct rte_flow_item *encap_data;
2146 const struct rte_flow_action_raw_encap *raw_encap_data;
2147 struct mlx5_flow_dv_encap_decap_resource res = {
2149 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2150 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2151 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2154 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2156 (const struct rte_flow_action_raw_encap *)action->conf;
2157 res.size = raw_encap_data->size;
2158 memcpy(res.buf, raw_encap_data->data, res.size);
2159 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2162 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2164 ((const struct rte_flow_action_vxlan_encap *)
2165 action->conf)->definition;
2168 ((const struct rte_flow_action_nvgre_encap *)
2169 action->conf)->definition;
2170 if (flow_dv_convert_encap_data(encap_data, res.buf,
2174 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2175 return rte_flow_error_set(error, EINVAL,
2176 RTE_FLOW_ERROR_TYPE_ACTION,
2177 NULL, "can't create L2 encap action");
2182 * Convert L2 decap action to DV specification.
2185 * Pointer to rte_eth_dev structure.
2186 * @param[in, out] dev_flow
2187 * Pointer to the mlx5_flow.
2188 * @param[in] transfer
2189 * Mark if the flow is E-Switch flow.
2191 * Pointer to the error structure.
2194 * 0 on success, a negative errno value otherwise and rte_errno is set.
2197 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2198 struct mlx5_flow *dev_flow,
2200 struct rte_flow_error *error)
2202 struct mlx5_flow_dv_encap_decap_resource res = {
2205 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2206 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2207 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2210 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2211 return rte_flow_error_set(error, EINVAL,
2212 RTE_FLOW_ERROR_TYPE_ACTION,
2213 NULL, "can't create L2 decap action");
2218 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2221 * Pointer to rte_eth_dev structure.
2223 * Pointer to action structure.
2224 * @param[in, out] dev_flow
2225 * Pointer to the mlx5_flow.
2227 * Pointer to the flow attributes.
2229 * Pointer to the error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2236 const struct rte_flow_action *action,
2237 struct mlx5_flow *dev_flow,
2238 const struct rte_flow_attr *attr,
2239 struct rte_flow_error *error)
2241 const struct rte_flow_action_raw_encap *encap_data;
2242 struct mlx5_flow_dv_encap_decap_resource res;
2244 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2245 res.size = encap_data->size;
2246 memcpy(res.buf, encap_data->data, res.size);
2247 res.reformat_type = attr->egress ?
2248 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2249 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2251 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2253 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2254 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2255 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ACTION,
2258 NULL, "can't create encap action");
2263 * Create action push VLAN.
2266 * Pointer to rte_eth_dev structure.
2267 * @param[in] vlan_tag
2268 * the vlan tag to push to the Ethernet header.
2269 * @param[in, out] dev_flow
2270 * Pointer to the mlx5_flow.
2272 * Pointer to the flow attributes.
2274 * Pointer to the error structure.
2277 * 0 on success, a negative errno value otherwise and rte_errno is set.
2280 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2281 const struct rte_flow_attr *attr,
2282 const struct rte_vlan_hdr *vlan,
2283 struct mlx5_flow *dev_flow,
2284 struct rte_flow_error *error)
2286 struct mlx5_flow_dv_push_vlan_action_resource res;
2289 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2292 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2294 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2295 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2296 return flow_dv_push_vlan_action_resource_register
2297 (dev, &res, dev_flow, error);
2301 * Validate the modify-header actions.
2303 * @param[in] action_flags
2304 * Holds the actions detected until now.
2306 * Pointer to the modify action.
2308 * Pointer to error structure.
2311 * 0 on success, a negative errno value otherwise and rte_errno is set.
2314 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2315 const struct rte_flow_action *action,
2316 struct rte_flow_error *error)
2318 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2319 return rte_flow_error_set(error, EINVAL,
2320 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2321 NULL, "action configuration not set");
2322 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2323 return rte_flow_error_set(error, EINVAL,
2324 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2325 "can't have encap action before"
2331 * Validate the modify-header MAC address actions.
2333 * @param[in] action_flags
2334 * Holds the actions detected until now.
2336 * Pointer to the modify action.
2337 * @param[in] item_flags
2338 * Holds the items detected.
2340 * Pointer to error structure.
2343 * 0 on success, a negative errno value otherwise and rte_errno is set.
2346 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2347 const struct rte_flow_action *action,
2348 const uint64_t item_flags,
2349 struct rte_flow_error *error)
2353 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2355 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2356 return rte_flow_error_set(error, EINVAL,
2357 RTE_FLOW_ERROR_TYPE_ACTION,
2359 "no L2 item in pattern");
2365 * Validate the modify-header IPv4 address actions.
2367 * @param[in] action_flags
2368 * Holds the actions detected until now.
2370 * Pointer to the modify action.
2371 * @param[in] item_flags
2372 * Holds the items detected.
2374 * Pointer to error structure.
2377 * 0 on success, a negative errno value otherwise and rte_errno is set.
2380 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2381 const struct rte_flow_action *action,
2382 const uint64_t item_flags,
2383 struct rte_flow_error *error)
2387 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2389 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2390 return rte_flow_error_set(error, EINVAL,
2391 RTE_FLOW_ERROR_TYPE_ACTION,
2393 "no ipv4 item in pattern");
2399 * Validate the modify-header IPv6 address actions.
2401 * @param[in] action_flags
2402 * Holds the actions detected until now.
2404 * Pointer to the modify action.
2405 * @param[in] item_flags
2406 * Holds the items detected.
2408 * Pointer to error structure.
2411 * 0 on success, a negative errno value otherwise and rte_errno is set.
2414 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2415 const struct rte_flow_action *action,
2416 const uint64_t item_flags,
2417 struct rte_flow_error *error)
2421 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2423 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2424 return rte_flow_error_set(error, EINVAL,
2425 RTE_FLOW_ERROR_TYPE_ACTION,
2427 "no ipv6 item in pattern");
2433 * Validate the modify-header TP actions.
2435 * @param[in] action_flags
2436 * Holds the actions detected until now.
2438 * Pointer to the modify action.
2439 * @param[in] item_flags
2440 * Holds the items detected.
2442 * Pointer to error structure.
2445 * 0 on success, a negative errno value otherwise and rte_errno is set.
2448 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2449 const struct rte_flow_action *action,
2450 const uint64_t item_flags,
2451 struct rte_flow_error *error)
2455 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2457 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2458 return rte_flow_error_set(error, EINVAL,
2459 RTE_FLOW_ERROR_TYPE_ACTION,
2460 NULL, "no transport layer "
2467 * Validate the modify-header actions of increment/decrement
2468 * TCP Sequence-number.
2470 * @param[in] action_flags
2471 * Holds the actions detected until now.
2473 * Pointer to the modify action.
2474 * @param[in] item_flags
2475 * Holds the items detected.
2477 * Pointer to error structure.
2480 * 0 on success, a negative errno value otherwise and rte_errno is set.
2483 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2484 const struct rte_flow_action *action,
2485 const uint64_t item_flags,
2486 struct rte_flow_error *error)
2490 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2492 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2493 return rte_flow_error_set(error, EINVAL,
2494 RTE_FLOW_ERROR_TYPE_ACTION,
2495 NULL, "no TCP item in"
2497 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2498 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2499 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2500 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2501 return rte_flow_error_set(error, EINVAL,
2502 RTE_FLOW_ERROR_TYPE_ACTION,
2504 "cannot decrease and increase"
2505 " TCP sequence number"
2506 " at the same time");
2512 * Validate the modify-header actions of increment/decrement
2513 * TCP Acknowledgment number.
2515 * @param[in] action_flags
2516 * Holds the actions detected until now.
2518 * Pointer to the modify action.
2519 * @param[in] item_flags
2520 * Holds the items detected.
2522 * Pointer to error structure.
2525 * 0 on success, a negative errno value otherwise and rte_errno is set.
2528 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2529 const struct rte_flow_action *action,
2530 const uint64_t item_flags,
2531 struct rte_flow_error *error)
2535 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2537 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2538 return rte_flow_error_set(error, EINVAL,
2539 RTE_FLOW_ERROR_TYPE_ACTION,
2540 NULL, "no TCP item in"
2542 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2543 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2544 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2545 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2546 return rte_flow_error_set(error, EINVAL,
2547 RTE_FLOW_ERROR_TYPE_ACTION,
2549 "cannot decrease and increase"
2550 " TCP acknowledgment number"
2551 " at the same time");
2557 * Validate the modify-header TTL actions.
2559 * @param[in] action_flags
2560 * Holds the actions detected until now.
2562 * Pointer to the modify action.
2563 * @param[in] item_flags
2564 * Holds the items detected.
2566 * Pointer to error structure.
2569 * 0 on success, a negative errno value otherwise and rte_errno is set.
2572 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2573 const struct rte_flow_action *action,
2574 const uint64_t item_flags,
2575 struct rte_flow_error *error)
2579 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2581 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2582 return rte_flow_error_set(error, EINVAL,
2583 RTE_FLOW_ERROR_TYPE_ACTION,
2585 "no IP protocol in pattern");
2591 * Validate jump action.
2594 * Pointer to the jump action.
2595 * @param[in] action_flags
2596 * Holds the actions detected until now.
2597 * @param[in] attributes
2598 * Pointer to flow attributes
2599 * @param[in] external
2600 * Action belongs to flow rule created by request external to PMD.
2602 * Pointer to error structure.
2605 * 0 on success, a negative errno value otherwise and rte_errno is set.
2608 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2609 uint64_t action_flags,
2610 const struct rte_flow_attr *attributes,
2611 bool external, struct rte_flow_error *error)
2613 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2615 uint32_t target_group, table;
2618 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2619 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2620 return rte_flow_error_set(error, EINVAL,
2621 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2622 "can't have 2 fate actions in"
2625 return rte_flow_error_set(error, EINVAL,
2626 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2627 NULL, "action configuration not set");
2629 ((const struct rte_flow_action_jump *)action->conf)->group;
2630 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2634 if (table >= max_group)
2635 return rte_flow_error_set(error, EINVAL,
2636 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2637 "target group index out of range");
2638 if (attributes->group >= target_group)
2639 return rte_flow_error_set(error, EINVAL,
2640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2641 "target group must be higher than"
2642 " the current flow group");
2647 * Validate the port_id action.
2650 * Pointer to rte_eth_dev structure.
2651 * @param[in] action_flags
2652 * Bit-fields that holds the actions detected until now.
2654 * Port_id RTE action structure.
2656 * Attributes of flow that includes this action.
2658 * Pointer to error structure.
2661 * 0 on success, a negative errno value otherwise and rte_errno is set.
2664 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2665 uint64_t action_flags,
2666 const struct rte_flow_action *action,
2667 const struct rte_flow_attr *attr,
2668 struct rte_flow_error *error)
2670 const struct rte_flow_action_port_id *port_id;
2671 struct mlx5_priv *act_priv;
2672 struct mlx5_priv *dev_priv;
2675 if (!attr->transfer)
2676 return rte_flow_error_set(error, ENOTSUP,
2677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2679 "port id action is valid in transfer"
2681 if (!action || !action->conf)
2682 return rte_flow_error_set(error, ENOTSUP,
2683 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2685 "port id action parameters must be"
2687 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2688 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2691 "can have only one fate actions in"
2693 dev_priv = mlx5_dev_to_eswitch_info(dev);
2695 return rte_flow_error_set(error, rte_errno,
2696 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2698 "failed to obtain E-Switch info");
2699 port_id = action->conf;
2700 port = port_id->original ? dev->data->port_id : port_id->id;
2701 act_priv = mlx5_port_to_eswitch_info(port);
2703 return rte_flow_error_set
2705 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2706 "failed to obtain E-Switch port id for port");
2707 if (act_priv->domain_id != dev_priv->domain_id)
2708 return rte_flow_error_set
2710 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2711 "port does not belong to"
2712 " E-Switch being configured");
2717 * Find existing modify-header resource or create and register a new one.
2719 * @param dev[in, out]
2720 * Pointer to rte_eth_dev structure.
2721 * @param[in, out] resource
2722 * Pointer to modify-header resource.
2723 * @parm[in, out] dev_flow
2724 * Pointer to the dev_flow.
2726 * pointer to error structure.
2729 * 0 on success otherwise -errno and errno is set.
2732 flow_dv_modify_hdr_resource_register
2733 (struct rte_eth_dev *dev,
2734 struct mlx5_flow_dv_modify_hdr_resource *resource,
2735 struct mlx5_flow *dev_flow,
2736 struct rte_flow_error *error)
2738 struct mlx5_priv *priv = dev->data->dev_private;
2739 struct mlx5_ibv_shared *sh = priv->sh;
2740 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2741 struct mlx5dv_dr_domain *ns;
2743 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2744 ns = sh->fdb_domain;
2745 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2750 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2751 /* Lookup a matching resource from cache. */
2752 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2753 if (resource->ft_type == cache_resource->ft_type &&
2754 resource->actions_num == cache_resource->actions_num &&
2755 resource->flags == cache_resource->flags &&
2756 !memcmp((const void *)resource->actions,
2757 (const void *)cache_resource->actions,
2758 (resource->actions_num *
2759 sizeof(resource->actions[0])))) {
2760 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2761 (void *)cache_resource,
2762 rte_atomic32_read(&cache_resource->refcnt));
2763 rte_atomic32_inc(&cache_resource->refcnt);
2764 dev_flow->dv.modify_hdr = cache_resource;
2768 /* Register new modify-header resource. */
2769 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2770 if (!cache_resource)
2771 return rte_flow_error_set(error, ENOMEM,
2772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2773 "cannot allocate resource memory");
2774 *cache_resource = *resource;
2775 cache_resource->verbs_action =
2776 mlx5_glue->dv_create_flow_action_modify_header
2777 (sh->ctx, cache_resource->ft_type,
2778 ns, cache_resource->flags,
2779 cache_resource->actions_num *
2780 sizeof(cache_resource->actions[0]),
2781 (uint64_t *)cache_resource->actions);
2782 if (!cache_resource->verbs_action) {
2783 rte_free(cache_resource);
2784 return rte_flow_error_set(error, ENOMEM,
2785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2786 NULL, "cannot create action");
2788 rte_atomic32_init(&cache_resource->refcnt);
2789 rte_atomic32_inc(&cache_resource->refcnt);
2790 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2791 dev_flow->dv.modify_hdr = cache_resource;
2792 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2793 (void *)cache_resource,
2794 rte_atomic32_read(&cache_resource->refcnt));
2798 #define MLX5_CNT_CONTAINER_RESIZE 64
2801 * Get or create a flow counter.
2804 * Pointer to the Ethernet device structure.
2806 * Indicate if this counter is shared with other flows.
2808 * Counter identifier.
2811 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2813 static struct mlx5_flow_counter *
2814 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2817 struct mlx5_priv *priv = dev->data->dev_private;
2818 struct mlx5_flow_counter *cnt = NULL;
2819 struct mlx5_devx_obj *dcs = NULL;
2821 if (!priv->config.devx) {
2822 rte_errno = ENOTSUP;
2826 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2827 if (cnt->shared && cnt->id == id) {
2833 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2836 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2838 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2842 struct mlx5_flow_counter tmpl = {
2848 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2850 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2856 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2861 * Release a flow counter.
2864 * Pointer to the Ethernet device structure.
2865 * @param[in] counter
2866 * Pointer to the counter handler.
2869 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2870 struct mlx5_flow_counter *counter)
2872 struct mlx5_priv *priv = dev->data->dev_private;
2876 if (--counter->ref_cnt == 0) {
2877 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2878 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2884 * Query a devx flow counter.
2887 * Pointer to the Ethernet device structure.
2889 * Pointer to the flow counter.
2891 * The statistics value of packets.
2893 * The statistics value of bytes.
2896 * 0 on success, otherwise a negative errno value and rte_errno is set.
2899 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2900 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2903 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2908 * Get a pool by a counter.
2911 * Pointer to the counter.
2916 static struct mlx5_flow_counter_pool *
2917 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2920 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2921 return (struct mlx5_flow_counter_pool *)cnt - 1;
2927 * Get a pool by devx counter ID.
2930 * Pointer to the counter container.
2932 * The counter devx ID.
2935 * The counter pool pointer if exists, NULL otherwise,
2937 static struct mlx5_flow_counter_pool *
2938 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2940 struct mlx5_flow_counter_pool *pool;
2942 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2943 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2944 MLX5_COUNTERS_PER_POOL;
2946 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2953 * Allocate a new memory for the counter values wrapped by all the needed
2957 * Pointer to the Ethernet device structure.
2959 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2962 * The new memory management pointer on success, otherwise NULL and rte_errno
2965 static struct mlx5_counter_stats_mem_mng *
2966 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2968 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2969 (dev->data->dev_private))->sh;
2970 struct mlx5_devx_mkey_attr mkey_attr;
2971 struct mlx5_counter_stats_mem_mng *mem_mng;
2972 volatile struct flow_counter_stats *raw_data;
2973 int size = (sizeof(struct flow_counter_stats) *
2974 MLX5_COUNTERS_PER_POOL +
2975 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2976 sizeof(struct mlx5_counter_stats_mem_mng);
2977 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2984 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2985 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2986 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2987 IBV_ACCESS_LOCAL_WRITE);
2988 if (!mem_mng->umem) {
2993 mkey_attr.addr = (uintptr_t)mem;
2994 mkey_attr.size = size;
2995 mkey_attr.umem_id = mem_mng->umem->umem_id;
2996 mkey_attr.pd = sh->pdn;
2997 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2999 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3004 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3005 raw_data = (volatile struct flow_counter_stats *)mem;
3006 for (i = 0; i < raws_n; ++i) {
3007 mem_mng->raws[i].mem_mng = mem_mng;
3008 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3010 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3015 * Resize a counter container.
3018 * Pointer to the Ethernet device structure.
3020 * Whether the pool is for counter that was allocated by batch command.
3023 * The new container pointer on success, otherwise NULL and rte_errno is set.
3025 static struct mlx5_pools_container *
3026 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3028 struct mlx5_priv *priv = dev->data->dev_private;
3029 struct mlx5_pools_container *cont =
3030 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3031 struct mlx5_pools_container *new_cont =
3032 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3033 struct mlx5_counter_stats_mem_mng *mem_mng;
3034 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3035 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3038 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3039 /* The last resize still hasn't detected by the host thread. */
3043 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3044 if (!new_cont->pools) {
3049 memcpy(new_cont->pools, cont->pools, cont->n *
3050 sizeof(struct mlx5_flow_counter_pool *));
3051 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3052 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3054 rte_free(new_cont->pools);
3057 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3058 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3059 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3061 new_cont->n = resize;
3062 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3063 TAILQ_INIT(&new_cont->pool_list);
3064 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3065 new_cont->init_mem_mng = mem_mng;
3067 /* Flip the master container. */
3068 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3073 * Query a devx flow counter.
3076 * Pointer to the Ethernet device structure.
3078 * Pointer to the flow counter.
3080 * The statistics value of packets.
3082 * The statistics value of bytes.
3085 * 0 on success, otherwise a negative errno value and rte_errno is set.
3088 _flow_dv_query_count(struct rte_eth_dev *dev,
3089 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3092 struct mlx5_priv *priv = dev->data->dev_private;
3093 struct mlx5_flow_counter_pool *pool =
3094 flow_dv_counter_pool_get(cnt);
3095 int offset = cnt - &pool->counters_raw[0];
3097 if (priv->counter_fallback)
3098 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3100 rte_spinlock_lock(&pool->sl);
3102 * The single counters allocation may allocate smaller ID than the
3103 * current allocated in parallel to the host reading.
3104 * In this case the new counter values must be reported as 0.
3106 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3110 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3111 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3113 rte_spinlock_unlock(&pool->sl);
3118 * Create and initialize a new counter pool.
3121 * Pointer to the Ethernet device structure.
3123 * The devX counter handle.
3125 * Whether the pool is for counter that was allocated by batch command.
3128 * A new pool pointer on success, NULL otherwise and rte_errno is set.
3130 static struct mlx5_flow_counter_pool *
3131 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3134 struct mlx5_priv *priv = dev->data->dev_private;
3135 struct mlx5_flow_counter_pool *pool;
3136 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3138 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3141 if (cont->n == n_valid) {
3142 cont = flow_dv_container_resize(dev, batch);
3146 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3147 sizeof(struct mlx5_flow_counter);
3148 pool = rte_calloc(__func__, 1, size, 0);
3153 pool->min_dcs = dcs;
3154 pool->raw = cont->init_mem_mng->raws + n_valid %
3155 MLX5_CNT_CONTAINER_RESIZE;
3156 pool->raw_hw = NULL;
3157 rte_spinlock_init(&pool->sl);
3159 * The generation of the new allocated counters in this pool is 0, 2 in
3160 * the pool generation makes all the counters valid for allocation.
3162 rte_atomic64_set(&pool->query_gen, 0x2);
3163 TAILQ_INIT(&pool->counters);
3164 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3165 cont->pools[n_valid] = pool;
3166 /* Pool initialization must be updated before host thread access. */
3168 rte_atomic16_add(&cont->n_valid, 1);
3173 * Prepare a new counter and/or a new counter pool.
3176 * Pointer to the Ethernet device structure.
3177 * @param[out] cnt_free
3178 * Where to put the pointer of a new counter.
3180 * Whether the pool is for counter that was allocated by batch command.
3183 * The free counter pool pointer and @p cnt_free is set on success,
3184 * NULL otherwise and rte_errno is set.
3186 static struct mlx5_flow_counter_pool *
3187 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3188 struct mlx5_flow_counter **cnt_free,
3191 struct mlx5_priv *priv = dev->data->dev_private;
3192 struct mlx5_flow_counter_pool *pool;
3193 struct mlx5_devx_obj *dcs = NULL;
3194 struct mlx5_flow_counter *cnt;
3198 /* bulk_bitmap must be 0 for single counter allocation. */
3199 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3202 pool = flow_dv_find_pool_by_id
3203 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3205 pool = flow_dv_pool_create(dev, dcs, batch);
3207 mlx5_devx_cmd_destroy(dcs);
3210 } else if (dcs->id < pool->min_dcs->id) {
3211 rte_atomic64_set(&pool->a64_dcs,
3212 (int64_t)(uintptr_t)dcs);
3214 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3215 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3220 /* bulk_bitmap is in 128 counters units. */
3221 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3222 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3224 rte_errno = ENODATA;
3227 pool = flow_dv_pool_create(dev, dcs, batch);
3229 mlx5_devx_cmd_destroy(dcs);
3232 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3233 cnt = &pool->counters_raw[i];
3235 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3237 *cnt_free = &pool->counters_raw[0];
3242 * Search for existed shared counter.
3245 * Pointer to the relevant counter pool container.
3247 * The shared counter ID to search.
3250 * NULL if not existed, otherwise pointer to the shared counter.
3252 static struct mlx5_flow_counter *
3253 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3256 static struct mlx5_flow_counter *cnt;
3257 struct mlx5_flow_counter_pool *pool;
3260 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3261 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3262 cnt = &pool->counters_raw[i];
3263 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3271 * Allocate a flow counter.
3274 * Pointer to the Ethernet device structure.
3276 * Indicate if this counter is shared with other flows.
3278 * Counter identifier.
3280 * Counter flow group.
3283 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3285 static struct mlx5_flow_counter *
3286 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3289 struct mlx5_priv *priv = dev->data->dev_private;
3290 struct mlx5_flow_counter_pool *pool = NULL;
3291 struct mlx5_flow_counter *cnt_free = NULL;
3293 * Currently group 0 flow counter cannot be assigned to a flow if it is
3294 * not the first one in the batch counter allocation, so it is better
3295 * to allocate counters one by one for these flows in a separate
3297 * A counter can be shared between different groups so need to take
3298 * shared counters from the single container.
3300 uint32_t batch = (group && !shared) ? 1 : 0;
3301 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3304 if (priv->counter_fallback)
3305 return flow_dv_counter_alloc_fallback(dev, shared, id);
3306 if (!priv->config.devx) {
3307 rte_errno = ENOTSUP;
3311 cnt_free = flow_dv_counter_shared_search(cont, id);
3313 if (cnt_free->ref_cnt + 1 == 0) {
3317 cnt_free->ref_cnt++;
3321 /* Pools which has a free counters are in the start. */
3322 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3324 * The free counter reset values must be updated between the
3325 * counter release to the counter allocation, so, at least one
3326 * query must be done in this time. ensure it by saving the
3327 * query generation in the release time.
3328 * The free list is sorted according to the generation - so if
3329 * the first one is not updated, all the others are not
3332 cnt_free = TAILQ_FIRST(&pool->counters);
3333 if (cnt_free && cnt_free->query_gen + 1 <
3334 rte_atomic64_read(&pool->query_gen))
3339 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3343 cnt_free->batch = batch;
3344 /* Create a DV counter action only in the first time usage. */
3345 if (!cnt_free->action) {
3347 struct mlx5_devx_obj *dcs;
3350 offset = cnt_free - &pool->counters_raw[0];
3351 dcs = pool->min_dcs;
3354 dcs = cnt_free->dcs;
3356 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3358 if (!cnt_free->action) {
3363 /* Update the counter reset values. */
3364 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3367 cnt_free->shared = shared;
3368 cnt_free->ref_cnt = 1;
3370 if (!priv->sh->cmng.query_thread_on)
3371 /* Start the asynchronous batch query by the host thread. */
3372 mlx5_set_query_alarm(priv->sh);
3373 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3374 if (TAILQ_EMPTY(&pool->counters)) {
3375 /* Move the pool to the end of the container pool list. */
3376 TAILQ_REMOVE(&cont->pool_list, pool, next);
3377 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3383 * Release a flow counter.
3386 * Pointer to the Ethernet device structure.
3387 * @param[in] counter
3388 * Pointer to the counter handler.
3391 flow_dv_counter_release(struct rte_eth_dev *dev,
3392 struct mlx5_flow_counter *counter)
3394 struct mlx5_priv *priv = dev->data->dev_private;
3398 if (priv->counter_fallback) {
3399 flow_dv_counter_release_fallback(dev, counter);
3402 if (--counter->ref_cnt == 0) {
3403 struct mlx5_flow_counter_pool *pool =
3404 flow_dv_counter_pool_get(counter);
3406 /* Put the counter in the end - the last updated one. */
3407 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3408 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3413 * Verify the @p attributes will be correctly understood by the NIC and store
3414 * them in the @p flow if everything is correct.
3417 * Pointer to dev struct.
3418 * @param[in] attributes
3419 * Pointer to flow attributes
3420 * @param[in] external
3421 * This flow rule is created by request external to PMD.
3423 * Pointer to error structure.
3426 * 0 on success, a negative errno value otherwise and rte_errno is set.
3429 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3430 const struct rte_flow_attr *attributes,
3431 bool external __rte_unused,
3432 struct rte_flow_error *error)
3434 struct mlx5_priv *priv = dev->data->dev_private;
3435 uint32_t priority_max = priv->config.flow_prio - 1;
3437 #ifndef HAVE_MLX5DV_DR
3438 if (attributes->group)
3439 return rte_flow_error_set(error, ENOTSUP,
3440 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3442 "groups are not supported");
3444 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3449 ret = mlx5_flow_group_to_table(attributes, external,
3454 if (table >= max_group)
3455 return rte_flow_error_set(error, EINVAL,
3456 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3457 "group index out of range");
3459 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3460 attributes->priority >= priority_max)
3461 return rte_flow_error_set(error, ENOTSUP,
3462 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3464 "priority out of range");
3465 if (attributes->transfer) {
3466 if (!priv->config.dv_esw_en)
3467 return rte_flow_error_set
3469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3470 "E-Switch dr is not supported");
3471 if (!(priv->representor || priv->master))
3472 return rte_flow_error_set
3473 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3474 NULL, "E-Switch configuration can only be"
3475 " done by a master or a representor device");
3476 if (attributes->egress)
3477 return rte_flow_error_set
3479 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3480 "egress is not supported");
3482 if (!(attributes->egress ^ attributes->ingress))
3483 return rte_flow_error_set(error, ENOTSUP,
3484 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3485 "must specify exactly one of "
3486 "ingress or egress");
3491 * Internal validation function. For validating both actions and items.
3494 * Pointer to the rte_eth_dev structure.
3496 * Pointer to the flow attributes.
3498 * Pointer to the list of items.
3499 * @param[in] actions
3500 * Pointer to the list of actions.
3501 * @param[in] external
3502 * This flow rule is created by request external to PMD.
3504 * Pointer to the error structure.
3507 * 0 on success, a negative errno value otherwise and rte_errno is set.
3510 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3511 const struct rte_flow_item items[],
3512 const struct rte_flow_action actions[],
3513 bool external, struct rte_flow_error *error)
3516 uint64_t action_flags = 0;
3517 uint64_t item_flags = 0;
3518 uint64_t last_item = 0;
3519 uint8_t next_protocol = 0xff;
3520 uint16_t ether_type = 0;
3522 const struct rte_flow_item *gre_item = NULL;
3523 struct rte_flow_item_tcp nic_tcp_mask = {
3526 .src_port = RTE_BE16(UINT16_MAX),
3527 .dst_port = RTE_BE16(UINT16_MAX),
3533 ret = flow_dv_validate_attributes(dev, attr, external, error);
3536 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3537 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3538 int type = items->type;
3541 case RTE_FLOW_ITEM_TYPE_VOID:
3543 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3544 ret = flow_dv_validate_item_port_id
3545 (dev, items, attr, item_flags, error);
3548 last_item = MLX5_FLOW_ITEM_PORT_ID;
3550 case RTE_FLOW_ITEM_TYPE_ETH:
3551 ret = mlx5_flow_validate_item_eth(items, item_flags,
3555 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3556 MLX5_FLOW_LAYER_OUTER_L2;
3557 if (items->mask != NULL && items->spec != NULL) {
3559 ((const struct rte_flow_item_eth *)
3562 ((const struct rte_flow_item_eth *)
3564 ether_type = rte_be_to_cpu_16(ether_type);
3569 case RTE_FLOW_ITEM_TYPE_VLAN:
3570 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3574 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3575 MLX5_FLOW_LAYER_OUTER_VLAN;
3576 if (items->mask != NULL && items->spec != NULL) {
3578 ((const struct rte_flow_item_vlan *)
3579 items->spec)->inner_type;
3581 ((const struct rte_flow_item_vlan *)
3582 items->mask)->inner_type;
3583 ether_type = rte_be_to_cpu_16(ether_type);
3588 case RTE_FLOW_ITEM_TYPE_IPV4:
3589 mlx5_flow_tunnel_ip_check(items, next_protocol,
3590 &item_flags, &tunnel);
3591 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3597 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3598 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3599 if (items->mask != NULL &&
3600 ((const struct rte_flow_item_ipv4 *)
3601 items->mask)->hdr.next_proto_id) {
3603 ((const struct rte_flow_item_ipv4 *)
3604 (items->spec))->hdr.next_proto_id;
3606 ((const struct rte_flow_item_ipv4 *)
3607 (items->mask))->hdr.next_proto_id;
3609 /* Reset for inner layer. */
3610 next_protocol = 0xff;
3613 case RTE_FLOW_ITEM_TYPE_IPV6:
3614 mlx5_flow_tunnel_ip_check(items, next_protocol,
3615 &item_flags, &tunnel);
3616 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3622 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3623 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3624 if (items->mask != NULL &&
3625 ((const struct rte_flow_item_ipv6 *)
3626 items->mask)->hdr.proto) {
3628 ((const struct rte_flow_item_ipv6 *)
3629 items->spec)->hdr.proto;
3631 ((const struct rte_flow_item_ipv6 *)
3632 items->mask)->hdr.proto;
3634 /* Reset for inner layer. */
3635 next_protocol = 0xff;
3638 case RTE_FLOW_ITEM_TYPE_TCP:
3639 ret = mlx5_flow_validate_item_tcp
3646 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3647 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3649 case RTE_FLOW_ITEM_TYPE_UDP:
3650 ret = mlx5_flow_validate_item_udp(items, item_flags,
3655 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3656 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3658 case RTE_FLOW_ITEM_TYPE_GRE:
3659 ret = mlx5_flow_validate_item_gre(items, item_flags,
3660 next_protocol, error);
3664 last_item = MLX5_FLOW_LAYER_GRE;
3666 case RTE_FLOW_ITEM_TYPE_NVGRE:
3667 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3672 last_item = MLX5_FLOW_LAYER_NVGRE;
3674 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3675 ret = mlx5_flow_validate_item_gre_key
3676 (items, item_flags, gre_item, error);
3679 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3681 case RTE_FLOW_ITEM_TYPE_VXLAN:
3682 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3686 last_item = MLX5_FLOW_LAYER_VXLAN;
3688 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3689 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3694 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3696 case RTE_FLOW_ITEM_TYPE_GENEVE:
3697 ret = mlx5_flow_validate_item_geneve(items,
3702 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3704 case RTE_FLOW_ITEM_TYPE_MPLS:
3705 ret = mlx5_flow_validate_item_mpls(dev, items,
3710 last_item = MLX5_FLOW_LAYER_MPLS;
3712 case RTE_FLOW_ITEM_TYPE_META:
3713 ret = flow_dv_validate_item_meta(dev, items, attr,
3717 last_item = MLX5_FLOW_ITEM_METADATA;
3719 case RTE_FLOW_ITEM_TYPE_ICMP:
3720 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3725 last_item = MLX5_FLOW_LAYER_ICMP;
3727 case RTE_FLOW_ITEM_TYPE_ICMP6:
3728 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3733 last_item = MLX5_FLOW_LAYER_ICMP6;
3735 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3736 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3739 return rte_flow_error_set(error, ENOTSUP,
3740 RTE_FLOW_ERROR_TYPE_ITEM,
3741 NULL, "item not supported");
3743 item_flags |= last_item;
3745 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3746 int type = actions->type;
3747 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3748 return rte_flow_error_set(error, ENOTSUP,
3749 RTE_FLOW_ERROR_TYPE_ACTION,
3750 actions, "too many actions");
3752 case RTE_FLOW_ACTION_TYPE_VOID:
3754 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3755 ret = flow_dv_validate_action_port_id(dev,
3762 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3765 case RTE_FLOW_ACTION_TYPE_FLAG:
3766 ret = mlx5_flow_validate_action_flag(action_flags,
3770 action_flags |= MLX5_FLOW_ACTION_FLAG;
3773 case RTE_FLOW_ACTION_TYPE_MARK:
3774 ret = mlx5_flow_validate_action_mark(actions,
3779 action_flags |= MLX5_FLOW_ACTION_MARK;
3782 case RTE_FLOW_ACTION_TYPE_DROP:
3783 ret = mlx5_flow_validate_action_drop(action_flags,
3787 action_flags |= MLX5_FLOW_ACTION_DROP;
3790 case RTE_FLOW_ACTION_TYPE_QUEUE:
3791 ret = mlx5_flow_validate_action_queue(actions,
3796 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3799 case RTE_FLOW_ACTION_TYPE_RSS:
3800 ret = mlx5_flow_validate_action_rss(actions,
3806 action_flags |= MLX5_FLOW_ACTION_RSS;
3809 case RTE_FLOW_ACTION_TYPE_COUNT:
3810 ret = flow_dv_validate_action_count(dev, error);
3813 action_flags |= MLX5_FLOW_ACTION_COUNT;
3816 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3817 if (flow_dv_validate_action_pop_vlan(dev,
3823 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3826 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3827 ret = flow_dv_validate_action_push_vlan(action_flags,
3833 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3836 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3837 ret = flow_dv_validate_action_set_vlan_pcp
3838 (action_flags, actions, error);
3841 /* Count PCP with push_vlan command. */
3842 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3844 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3845 ret = flow_dv_validate_action_set_vlan_vid
3846 (item_flags, action_flags,
3850 /* Count VID with push_vlan command. */
3851 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3853 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3854 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3855 ret = flow_dv_validate_action_l2_encap(action_flags,
3860 action_flags |= actions->type ==
3861 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3862 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3863 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3866 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3867 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3868 ret = flow_dv_validate_action_l2_decap(action_flags,
3872 action_flags |= actions->type ==
3873 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3874 MLX5_FLOW_ACTION_VXLAN_DECAP :
3875 MLX5_FLOW_ACTION_NVGRE_DECAP;
3878 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3879 ret = flow_dv_validate_action_raw_encap(action_flags,
3884 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3887 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3888 ret = flow_dv_validate_action_raw_decap(action_flags,
3893 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3896 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3897 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3898 ret = flow_dv_validate_action_modify_mac(action_flags,
3904 /* Count all modify-header actions as one action. */
3905 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3907 action_flags |= actions->type ==
3908 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3909 MLX5_FLOW_ACTION_SET_MAC_SRC :
3910 MLX5_FLOW_ACTION_SET_MAC_DST;
3913 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3914 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3915 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3921 /* Count all modify-header actions as one action. */
3922 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3924 action_flags |= actions->type ==
3925 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3926 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3927 MLX5_FLOW_ACTION_SET_IPV4_DST;
3929 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3930 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3931 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3937 /* Count all modify-header actions as one action. */
3938 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3940 action_flags |= actions->type ==
3941 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3942 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3943 MLX5_FLOW_ACTION_SET_IPV6_DST;
3945 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3946 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3947 ret = flow_dv_validate_action_modify_tp(action_flags,
3953 /* Count all modify-header actions as one action. */
3954 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3956 action_flags |= actions->type ==
3957 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3958 MLX5_FLOW_ACTION_SET_TP_SRC :
3959 MLX5_FLOW_ACTION_SET_TP_DST;
3961 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3962 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3963 ret = flow_dv_validate_action_modify_ttl(action_flags,
3969 /* Count all modify-header actions as one action. */
3970 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3972 action_flags |= actions->type ==
3973 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3974 MLX5_FLOW_ACTION_SET_TTL :
3975 MLX5_FLOW_ACTION_DEC_TTL;
3977 case RTE_FLOW_ACTION_TYPE_JUMP:
3978 ret = flow_dv_validate_action_jump(actions,
3985 action_flags |= MLX5_FLOW_ACTION_JUMP;
3987 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3988 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3989 ret = flow_dv_validate_action_modify_tcp_seq
3996 /* Count all modify-header actions as one action. */
3997 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3999 action_flags |= actions->type ==
4000 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4001 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4002 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4004 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4005 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4006 ret = flow_dv_validate_action_modify_tcp_ack
4013 /* Count all modify-header actions as one action. */
4014 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4016 action_flags |= actions->type ==
4017 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4018 MLX5_FLOW_ACTION_INC_TCP_ACK :
4019 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4021 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4022 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4025 return rte_flow_error_set(error, ENOTSUP,
4026 RTE_FLOW_ERROR_TYPE_ACTION,
4028 "action not supported");
4031 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4032 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4033 return rte_flow_error_set(error, ENOTSUP,
4034 RTE_FLOW_ERROR_TYPE_ACTION,
4036 "can't have vxlan and vlan"
4037 " actions in the same rule");
4038 /* Eswitch has few restrictions on using items and actions */
4039 if (attr->transfer) {
4040 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4041 return rte_flow_error_set(error, ENOTSUP,
4042 RTE_FLOW_ERROR_TYPE_ACTION,
4044 "unsupported action FLAG");
4045 if (action_flags & MLX5_FLOW_ACTION_MARK)
4046 return rte_flow_error_set(error, ENOTSUP,
4047 RTE_FLOW_ERROR_TYPE_ACTION,
4049 "unsupported action MARK");
4050 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4051 return rte_flow_error_set(error, ENOTSUP,
4052 RTE_FLOW_ERROR_TYPE_ACTION,
4054 "unsupported action QUEUE");
4055 if (action_flags & MLX5_FLOW_ACTION_RSS)
4056 return rte_flow_error_set(error, ENOTSUP,
4057 RTE_FLOW_ERROR_TYPE_ACTION,
4059 "unsupported action RSS");
4060 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4061 return rte_flow_error_set(error, EINVAL,
4062 RTE_FLOW_ERROR_TYPE_ACTION,
4064 "no fate action is found");
4066 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4067 return rte_flow_error_set(error, EINVAL,
4068 RTE_FLOW_ERROR_TYPE_ACTION,
4070 "no fate action is found");
4076 * Internal preparation function. Allocates the DV flow size,
4077 * this size is constant.
4080 * Pointer to the flow attributes.
4082 * Pointer to the list of items.
4083 * @param[in] actions
4084 * Pointer to the list of actions.
4086 * Pointer to the error structure.
4089 * Pointer to mlx5_flow object on success,
4090 * otherwise NULL and rte_errno is set.
4092 static struct mlx5_flow *
4093 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4094 const struct rte_flow_item items[] __rte_unused,
4095 const struct rte_flow_action actions[] __rte_unused,
4096 struct rte_flow_error *error)
4098 uint32_t size = sizeof(struct mlx5_flow);
4099 struct mlx5_flow *flow;
4101 flow = rte_calloc(__func__, 1, size, 0);
4103 rte_flow_error_set(error, ENOMEM,
4104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4105 "not enough memory to create flow");
4108 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4114 * Sanity check for match mask and value. Similar to check_valid_spec() in
4115 * kernel driver. If unmasked bit is present in value, it returns failure.
4118 * pointer to match mask buffer.
4119 * @param match_value
4120 * pointer to match value buffer.
4123 * 0 if valid, -EINVAL otherwise.
4126 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4128 uint8_t *m = match_mask;
4129 uint8_t *v = match_value;
4132 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4135 "match_value differs from match_criteria"
4136 " %p[%u] != %p[%u]",
4137 match_value, i, match_mask, i);
4146 * Add Ethernet item to matcher and to the value.
4148 * @param[in, out] matcher
4150 * @param[in, out] key
4151 * Flow matcher value.
4153 * Flow pattern to translate.
4155 * Item is inner pattern.
4158 flow_dv_translate_item_eth(void *matcher, void *key,
4159 const struct rte_flow_item *item, int inner)
4161 const struct rte_flow_item_eth *eth_m = item->mask;
4162 const struct rte_flow_item_eth *eth_v = item->spec;
4163 const struct rte_flow_item_eth nic_mask = {
4164 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4165 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4166 .type = RTE_BE16(0xffff),
4178 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4180 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4182 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4184 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4186 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4187 ð_m->dst, sizeof(eth_m->dst));
4188 /* The value must be in the range of the mask. */
4189 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4190 for (i = 0; i < sizeof(eth_m->dst); ++i)
4191 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4192 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4193 ð_m->src, sizeof(eth_m->src));
4194 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4195 /* The value must be in the range of the mask. */
4196 for (i = 0; i < sizeof(eth_m->dst); ++i)
4197 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4198 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4199 rte_be_to_cpu_16(eth_m->type));
4200 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4201 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4205 * Add VLAN item to matcher and to the value.
4207 * @param[in, out] dev_flow
4209 * @param[in, out] matcher
4211 * @param[in, out] key
4212 * Flow matcher value.
4214 * Flow pattern to translate.
4216 * Item is inner pattern.
4219 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4220 void *matcher, void *key,
4221 const struct rte_flow_item *item,
4224 const struct rte_flow_item_vlan *vlan_m = item->mask;
4225 const struct rte_flow_item_vlan *vlan_v = item->spec;
4234 vlan_m = &rte_flow_item_vlan_mask;
4236 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4238 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4240 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4242 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4244 * This is workaround, masks are not supported,
4245 * and pre-validated.
4247 dev_flow->dv.vf_vlan.tag =
4248 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4250 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4251 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4252 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4254 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4255 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4256 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4257 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4258 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4259 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4260 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4261 rte_be_to_cpu_16(vlan_m->inner_type));
4262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4263 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4267 * Add IPV4 item to matcher and to the value.
4269 * @param[in, out] matcher
4271 * @param[in, out] key
4272 * Flow matcher value.
4274 * Flow pattern to translate.
4276 * Item is inner pattern.
4278 * The group to insert the rule.
4281 flow_dv_translate_item_ipv4(void *matcher, void *key,
4282 const struct rte_flow_item *item,
4283 int inner, uint32_t group)
4285 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4286 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4287 const struct rte_flow_item_ipv4 nic_mask = {
4289 .src_addr = RTE_BE32(0xffffffff),
4290 .dst_addr = RTE_BE32(0xffffffff),
4291 .type_of_service = 0xff,
4292 .next_proto_id = 0xff,
4302 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4304 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4306 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4308 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4311 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4313 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4314 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4319 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4320 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4321 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4322 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4323 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4324 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4325 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4326 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4327 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4328 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4329 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4330 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4331 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4332 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4333 ipv4_m->hdr.type_of_service);
4334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4335 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4336 ipv4_m->hdr.type_of_service >> 2);
4337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4338 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4339 ipv4_m->hdr.next_proto_id);
4340 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4341 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4345 * Add IPV6 item to matcher and to the value.
4347 * @param[in, out] matcher
4349 * @param[in, out] key
4350 * Flow matcher value.
4352 * Flow pattern to translate.
4354 * Item is inner pattern.
4356 * The group to insert the rule.
4359 flow_dv_translate_item_ipv6(void *matcher, void *key,
4360 const struct rte_flow_item *item,
4361 int inner, uint32_t group)
4363 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4364 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4365 const struct rte_flow_item_ipv6 nic_mask = {
4368 "\xff\xff\xff\xff\xff\xff\xff\xff"
4369 "\xff\xff\xff\xff\xff\xff\xff\xff",
4371 "\xff\xff\xff\xff\xff\xff\xff\xff"
4372 "\xff\xff\xff\xff\xff\xff\xff\xff",
4373 .vtc_flow = RTE_BE32(0xffffffff),
4380 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4381 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4390 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4392 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4394 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4396 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4399 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4402 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4407 size = sizeof(ipv6_m->hdr.dst_addr);
4408 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4409 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4410 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4411 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4412 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4413 for (i = 0; i < size; ++i)
4414 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4415 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4416 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4417 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4418 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4419 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4420 for (i = 0; i < size; ++i)
4421 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4423 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4424 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4425 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4426 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4428 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4431 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4433 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4436 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4438 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4442 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4445 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4449 * Add TCP item to matcher and to the value.
4451 * @param[in, out] matcher
4453 * @param[in, out] key
4454 * Flow matcher value.
4456 * Flow pattern to translate.
4458 * Item is inner pattern.
4461 flow_dv_translate_item_tcp(void *matcher, void *key,
4462 const struct rte_flow_item *item,
4465 const struct rte_flow_item_tcp *tcp_m = item->mask;
4466 const struct rte_flow_item_tcp *tcp_v = item->spec;
4471 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4473 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4475 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4477 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4479 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4480 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4484 tcp_m = &rte_flow_item_tcp_mask;
4485 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4486 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4487 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4488 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4489 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4490 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4492 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4494 tcp_m->hdr.tcp_flags);
4495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4496 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4500 * Add UDP item to matcher and to the value.
4502 * @param[in, out] matcher
4504 * @param[in, out] key
4505 * Flow matcher value.
4507 * Flow pattern to translate.
4509 * Item is inner pattern.
4512 flow_dv_translate_item_udp(void *matcher, void *key,
4513 const struct rte_flow_item *item,
4516 const struct rte_flow_item_udp *udp_m = item->mask;
4517 const struct rte_flow_item_udp *udp_v = item->spec;
4522 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4524 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4526 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4528 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4535 udp_m = &rte_flow_item_udp_mask;
4536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4537 rte_be_to_cpu_16(udp_m->hdr.src_port));
4538 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4539 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4540 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4541 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4543 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4547 * Add GRE optional Key item to matcher and to the value.
4549 * @param[in, out] matcher
4551 * @param[in, out] key
4552 * Flow matcher value.
4554 * Flow pattern to translate.
4556 * Item is inner pattern.
4559 flow_dv_translate_item_gre_key(void *matcher, void *key,
4560 const struct rte_flow_item *item)
4562 const rte_be32_t *key_m = item->mask;
4563 const rte_be32_t *key_v = item->spec;
4564 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4565 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4566 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4571 key_m = &gre_key_default_mask;
4572 /* GRE K bit must be on and should already be validated */
4573 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4574 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4575 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4576 rte_be_to_cpu_32(*key_m) >> 8);
4577 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4578 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4579 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4580 rte_be_to_cpu_32(*key_m) & 0xFF);
4581 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4582 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4586 * Add GRE item to matcher and to the value.
4588 * @param[in, out] matcher
4590 * @param[in, out] key
4591 * Flow matcher value.
4593 * Flow pattern to translate.
4595 * Item is inner pattern.
4598 flow_dv_translate_item_gre(void *matcher, void *key,
4599 const struct rte_flow_item *item,
4602 const struct rte_flow_item_gre *gre_m = item->mask;
4603 const struct rte_flow_item_gre *gre_v = item->spec;
4606 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4607 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4614 uint16_t s_present:1;
4615 uint16_t k_present:1;
4616 uint16_t rsvd_bit1:1;
4617 uint16_t c_present:1;
4621 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4624 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4626 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4628 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4630 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4632 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4633 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4637 gre_m = &rte_flow_item_gre_mask;
4638 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4639 rte_be_to_cpu_16(gre_m->protocol));
4640 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4641 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4642 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4643 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4644 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4645 gre_crks_rsvd0_ver_m.c_present);
4646 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4647 gre_crks_rsvd0_ver_v.c_present &
4648 gre_crks_rsvd0_ver_m.c_present);
4649 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4650 gre_crks_rsvd0_ver_m.k_present);
4651 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4652 gre_crks_rsvd0_ver_v.k_present &
4653 gre_crks_rsvd0_ver_m.k_present);
4654 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4655 gre_crks_rsvd0_ver_m.s_present);
4656 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4657 gre_crks_rsvd0_ver_v.s_present &
4658 gre_crks_rsvd0_ver_m.s_present);
4662 * Add NVGRE item to matcher and to the value.
4664 * @param[in, out] matcher
4666 * @param[in, out] key
4667 * Flow matcher value.
4669 * Flow pattern to translate.
4671 * Item is inner pattern.
4674 flow_dv_translate_item_nvgre(void *matcher, void *key,
4675 const struct rte_flow_item *item,
4678 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4679 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4680 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4681 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4682 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4683 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4689 /* For NVGRE, GRE header fields must be set with defined values. */
4690 const struct rte_flow_item_gre gre_spec = {
4691 .c_rsvd0_ver = RTE_BE16(0x2000),
4692 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4694 const struct rte_flow_item_gre gre_mask = {
4695 .c_rsvd0_ver = RTE_BE16(0xB000),
4696 .protocol = RTE_BE16(UINT16_MAX),
4698 const struct rte_flow_item gre_item = {
4703 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4707 nvgre_m = &rte_flow_item_nvgre_mask;
4708 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4709 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4710 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4711 memcpy(gre_key_m, tni_flow_id_m, size);
4712 for (i = 0; i < size; ++i)
4713 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4717 * Add VXLAN item to matcher and to the value.
4719 * @param[in, out] matcher
4721 * @param[in, out] key
4722 * Flow matcher value.
4724 * Flow pattern to translate.
4726 * Item is inner pattern.
4729 flow_dv_translate_item_vxlan(void *matcher, void *key,
4730 const struct rte_flow_item *item,
4733 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4734 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4737 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4738 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4746 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4748 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4750 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4752 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4754 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4755 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4756 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4757 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4758 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4763 vxlan_m = &rte_flow_item_vxlan_mask;
4764 size = sizeof(vxlan_m->vni);
4765 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4766 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4767 memcpy(vni_m, vxlan_m->vni, size);
4768 for (i = 0; i < size; ++i)
4769 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4773 * Add Geneve item to matcher and to the value.
4775 * @param[in, out] matcher
4777 * @param[in, out] key
4778 * Flow matcher value.
4780 * Flow pattern to translate.
4782 * Item is inner pattern.
4786 flow_dv_translate_item_geneve(void *matcher, void *key,
4787 const struct rte_flow_item *item, int inner)
4789 const struct rte_flow_item_geneve *geneve_m = item->mask;
4790 const struct rte_flow_item_geneve *geneve_v = item->spec;
4793 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4794 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4803 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4805 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4807 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4809 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4811 dport = MLX5_UDP_PORT_GENEVE;
4812 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4813 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4814 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4819 geneve_m = &rte_flow_item_geneve_mask;
4820 size = sizeof(geneve_m->vni);
4821 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4822 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4823 memcpy(vni_m, geneve_m->vni, size);
4824 for (i = 0; i < size; ++i)
4825 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4826 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4827 rte_be_to_cpu_16(geneve_m->protocol));
4828 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4829 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4830 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4831 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4832 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4833 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4834 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4835 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4836 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4837 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4838 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4839 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4840 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4844 * Add MPLS item to matcher and to the value.
4846 * @param[in, out] matcher
4848 * @param[in, out] key
4849 * Flow matcher value.
4851 * Flow pattern to translate.
4852 * @param[in] prev_layer
4853 * The protocol layer indicated in previous item.
4855 * Item is inner pattern.
4858 flow_dv_translate_item_mpls(void *matcher, void *key,
4859 const struct rte_flow_item *item,
4860 uint64_t prev_layer,
4863 const uint32_t *in_mpls_m = item->mask;
4864 const uint32_t *in_mpls_v = item->spec;
4865 uint32_t *out_mpls_m = 0;
4866 uint32_t *out_mpls_v = 0;
4867 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4868 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4869 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4871 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4872 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4873 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4875 switch (prev_layer) {
4876 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4877 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4878 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4879 MLX5_UDP_PORT_MPLS);
4881 case MLX5_FLOW_LAYER_GRE:
4882 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4883 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4884 RTE_ETHER_TYPE_MPLS);
4887 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4888 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4895 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4896 switch (prev_layer) {
4897 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4899 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4900 outer_first_mpls_over_udp);
4902 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4903 outer_first_mpls_over_udp);
4905 case MLX5_FLOW_LAYER_GRE:
4907 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4908 outer_first_mpls_over_gre);
4910 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4911 outer_first_mpls_over_gre);
4914 /* Inner MPLS not over GRE is not supported. */
4917 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4921 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4927 if (out_mpls_m && out_mpls_v) {
4928 *out_mpls_m = *in_mpls_m;
4929 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4934 * Add META item to matcher
4936 * @param[in, out] matcher
4938 * @param[in, out] key
4939 * Flow matcher value.
4941 * Flow pattern to translate.
4943 * Item is inner pattern.
4946 flow_dv_translate_item_meta(void *matcher, void *key,
4947 const struct rte_flow_item *item)
4949 const struct rte_flow_item_meta *meta_m;
4950 const struct rte_flow_item_meta *meta_v;
4952 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4954 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4956 meta_m = (const void *)item->mask;
4958 meta_m = &rte_flow_item_meta_mask;
4959 meta_v = (const void *)item->spec;
4961 MLX5_SET(fte_match_set_misc2, misc2_m,
4962 metadata_reg_a, meta_m->data);
4963 MLX5_SET(fte_match_set_misc2, misc2_v,
4964 metadata_reg_a, meta_v->data & meta_m->data);
4969 * Add vport metadata Reg C0 item to matcher
4971 * @param[in, out] matcher
4973 * @param[in, out] key
4974 * Flow matcher value.
4976 * Flow pattern to translate.
4979 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4980 uint32_t value, uint32_t mask)
4983 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4985 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4987 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4988 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4992 * Add tag item to matcher
4994 * @param[in, out] matcher
4996 * @param[in, out] key
4997 * Flow matcher value.
4999 * Flow pattern to translate.
5002 flow_dv_translate_item_tag(void *matcher, void *key,
5003 const struct rte_flow_item *item)
5006 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5008 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5009 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5010 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5011 enum modify_reg reg = tag_v->id;
5012 rte_be32_t value = tag_v->data;
5013 rte_be32_t mask = tag_m->data;
5017 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
5018 rte_be_to_cpu_32(mask));
5019 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
5020 rte_be_to_cpu_32(value));
5023 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
5024 rte_be_to_cpu_32(mask));
5025 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
5026 rte_be_to_cpu_32(value));
5029 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
5030 rte_be_to_cpu_32(mask));
5031 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
5032 rte_be_to_cpu_32(value));
5035 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
5036 rte_be_to_cpu_32(mask));
5037 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
5038 rte_be_to_cpu_32(value));
5041 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
5042 rte_be_to_cpu_32(mask));
5043 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
5044 rte_be_to_cpu_32(value));
5047 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
5048 rte_be_to_cpu_32(mask));
5049 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
5050 rte_be_to_cpu_32(value));
5053 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
5054 rte_be_to_cpu_32(mask));
5055 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
5056 rte_be_to_cpu_32(value));
5059 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
5060 rte_be_to_cpu_32(mask));
5061 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
5062 rte_be_to_cpu_32(value));
5065 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
5066 rte_be_to_cpu_32(mask));
5067 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
5068 rte_be_to_cpu_32(value));
5071 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
5072 rte_be_to_cpu_32(mask));
5073 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
5074 rte_be_to_cpu_32(value));
5080 * Add source vport match to the specified matcher.
5082 * @param[in, out] matcher
5084 * @param[in, out] key
5085 * Flow matcher value.
5087 * Source vport value to match
5092 flow_dv_translate_item_source_vport(void *matcher, void *key,
5093 int16_t port, uint16_t mask)
5095 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5096 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5098 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5099 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5103 * Translate port-id item to eswitch match on port-id.
5106 * The devich to configure through.
5107 * @param[in, out] matcher
5109 * @param[in, out] key
5110 * Flow matcher value.
5112 * Flow pattern to translate.
5115 * 0 on success, a negative errno value otherwise.
5118 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5119 void *key, const struct rte_flow_item *item)
5121 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5122 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5123 struct mlx5_priv *priv;
5126 mask = pid_m ? pid_m->id : 0xffff;
5127 id = pid_v ? pid_v->id : dev->data->port_id;
5128 priv = mlx5_port_to_eswitch_info(id);
5131 /* Translate to vport field or to metadata, depending on mode. */
5132 if (priv->vport_meta_mask)
5133 flow_dv_translate_item_meta_vport(matcher, key,
5134 priv->vport_meta_tag,
5135 priv->vport_meta_mask);
5137 flow_dv_translate_item_source_vport(matcher, key,
5138 priv->vport_id, mask);
5143 * Add ICMP6 item to matcher and to the value.
5145 * @param[in, out] matcher
5147 * @param[in, out] key
5148 * Flow matcher value.
5150 * Flow pattern to translate.
5152 * Item is inner pattern.
5155 flow_dv_translate_item_icmp6(void *matcher, void *key,
5156 const struct rte_flow_item *item,
5159 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5160 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5163 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5165 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5167 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5169 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5171 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5173 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5175 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5176 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5180 icmp6_m = &rte_flow_item_icmp6_mask;
5181 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5182 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5183 icmp6_v->type & icmp6_m->type);
5184 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5185 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5186 icmp6_v->code & icmp6_m->code);
5190 * Add ICMP item to matcher and to the value.
5192 * @param[in, out] matcher
5194 * @param[in, out] key
5195 * Flow matcher value.
5197 * Flow pattern to translate.
5199 * Item is inner pattern.
5202 flow_dv_translate_item_icmp(void *matcher, void *key,
5203 const struct rte_flow_item *item,
5206 const struct rte_flow_item_icmp *icmp_m = item->mask;
5207 const struct rte_flow_item_icmp *icmp_v = item->spec;
5210 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5212 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5214 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5216 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5218 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5220 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5222 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5223 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5227 icmp_m = &rte_flow_item_icmp_mask;
5228 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5229 icmp_m->hdr.icmp_type);
5230 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5231 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5232 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5233 icmp_m->hdr.icmp_code);
5234 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5235 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5238 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5240 #define HEADER_IS_ZERO(match_criteria, headers) \
5241 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5242 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5245 * Calculate flow matcher enable bitmap.
5247 * @param match_criteria
5248 * Pointer to flow matcher criteria.
5251 * Bitmap of enabled fields.
5254 flow_dv_matcher_enable(uint32_t *match_criteria)
5256 uint8_t match_criteria_enable;
5258 match_criteria_enable =
5259 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5260 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5261 match_criteria_enable |=
5262 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5263 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5264 match_criteria_enable |=
5265 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5266 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5267 match_criteria_enable |=
5268 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5269 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5270 match_criteria_enable |=
5271 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5272 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5273 return match_criteria_enable;
5280 * @param dev[in, out]
5281 * Pointer to rte_eth_dev structure.
5282 * @param[in] table_id
5285 * Direction of the table.
5286 * @param[in] transfer
5287 * E-Switch or NIC flow.
5289 * pointer to error structure.
5292 * Returns tables resource based on the index, NULL in case of failed.
5294 static struct mlx5_flow_tbl_resource *
5295 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5296 uint32_t table_id, uint8_t egress,
5298 struct rte_flow_error *error)
5300 struct mlx5_priv *priv = dev->data->dev_private;
5301 struct mlx5_ibv_shared *sh = priv->sh;
5302 struct mlx5_flow_tbl_resource *tbl;
5304 #ifdef HAVE_MLX5DV_DR
5306 tbl = &sh->fdb_tbl[table_id];
5308 tbl->obj = mlx5_glue->dr_create_flow_tbl
5309 (sh->fdb_domain, table_id);
5310 } else if (egress) {
5311 tbl = &sh->tx_tbl[table_id];
5313 tbl->obj = mlx5_glue->dr_create_flow_tbl
5314 (sh->tx_domain, table_id);
5316 tbl = &sh->rx_tbl[table_id];
5318 tbl->obj = mlx5_glue->dr_create_flow_tbl
5319 (sh->rx_domain, table_id);
5322 rte_flow_error_set(error, ENOMEM,
5323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5324 NULL, "cannot create table");
5327 rte_atomic32_inc(&tbl->refcnt);
5333 return &sh->fdb_tbl[table_id];
5335 return &sh->tx_tbl[table_id];
5337 return &sh->rx_tbl[table_id];
5342 * Release a flow table.
5345 * Table resource to be released.
5348 * Returns 0 if table was released, else return 1;
5351 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5355 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5356 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5364 * Register the flow matcher.
5366 * @param dev[in, out]
5367 * Pointer to rte_eth_dev structure.
5368 * @param[in, out] matcher
5369 * Pointer to flow matcher.
5370 * @parm[in, out] dev_flow
5371 * Pointer to the dev_flow.
5373 * pointer to error structure.
5376 * 0 on success otherwise -errno and errno is set.
5379 flow_dv_matcher_register(struct rte_eth_dev *dev,
5380 struct mlx5_flow_dv_matcher *matcher,
5381 struct mlx5_flow *dev_flow,
5382 struct rte_flow_error *error)
5384 struct mlx5_priv *priv = dev->data->dev_private;
5385 struct mlx5_ibv_shared *sh = priv->sh;
5386 struct mlx5_flow_dv_matcher *cache_matcher;
5387 struct mlx5dv_flow_matcher_attr dv_attr = {
5388 .type = IBV_FLOW_ATTR_NORMAL,
5389 .match_mask = (void *)&matcher->mask,
5391 struct mlx5_flow_tbl_resource *tbl = NULL;
5393 /* Lookup from cache. */
5394 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5395 if (matcher->crc == cache_matcher->crc &&
5396 matcher->priority == cache_matcher->priority &&
5397 matcher->egress == cache_matcher->egress &&
5398 matcher->group == cache_matcher->group &&
5399 matcher->transfer == cache_matcher->transfer &&
5400 !memcmp((const void *)matcher->mask.buf,
5401 (const void *)cache_matcher->mask.buf,
5402 cache_matcher->mask.size)) {
5404 "priority %hd use %s matcher %p: refcnt %d++",
5405 cache_matcher->priority,
5406 cache_matcher->egress ? "tx" : "rx",
5407 (void *)cache_matcher,
5408 rte_atomic32_read(&cache_matcher->refcnt));
5409 rte_atomic32_inc(&cache_matcher->refcnt);
5410 dev_flow->dv.matcher = cache_matcher;
5414 /* Register new matcher. */
5415 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5417 return rte_flow_error_set(error, ENOMEM,
5418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5419 "cannot allocate matcher memory");
5420 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5421 matcher->egress, matcher->transfer,
5424 rte_free(cache_matcher);
5425 return rte_flow_error_set(error, ENOMEM,
5426 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5427 NULL, "cannot create table");
5429 *cache_matcher = *matcher;
5430 dv_attr.match_criteria_enable =
5431 flow_dv_matcher_enable(cache_matcher->mask.buf);
5432 dv_attr.priority = matcher->priority;
5433 if (matcher->egress)
5434 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5435 cache_matcher->matcher_object =
5436 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5437 if (!cache_matcher->matcher_object) {
5438 rte_free(cache_matcher);
5439 #ifdef HAVE_MLX5DV_DR
5440 flow_dv_tbl_resource_release(tbl);
5442 return rte_flow_error_set(error, ENOMEM,
5443 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5444 NULL, "cannot create matcher");
5446 rte_atomic32_inc(&cache_matcher->refcnt);
5447 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5448 dev_flow->dv.matcher = cache_matcher;
5449 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5450 cache_matcher->priority,
5451 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5452 rte_atomic32_read(&cache_matcher->refcnt));
5453 rte_atomic32_inc(&tbl->refcnt);
5458 * Find existing tag resource or create and register a new one.
5460 * @param dev[in, out]
5461 * Pointer to rte_eth_dev structure.
5462 * @param[in, out] resource
5463 * Pointer to tag resource.
5464 * @parm[in, out] dev_flow
5465 * Pointer to the dev_flow.
5467 * pointer to error structure.
5470 * 0 on success otherwise -errno and errno is set.
5473 flow_dv_tag_resource_register
5474 (struct rte_eth_dev *dev,
5475 struct mlx5_flow_dv_tag_resource *resource,
5476 struct mlx5_flow *dev_flow,
5477 struct rte_flow_error *error)
5479 struct mlx5_priv *priv = dev->data->dev_private;
5480 struct mlx5_ibv_shared *sh = priv->sh;
5481 struct mlx5_flow_dv_tag_resource *cache_resource;
5483 /* Lookup a matching resource from cache. */
5484 LIST_FOREACH(cache_resource, &sh->tags, next) {
5485 if (resource->tag == cache_resource->tag) {
5486 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5487 (void *)cache_resource,
5488 rte_atomic32_read(&cache_resource->refcnt));
5489 rte_atomic32_inc(&cache_resource->refcnt);
5490 dev_flow->flow->tag_resource = cache_resource;
5494 /* Register new resource. */
5495 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5496 if (!cache_resource)
5497 return rte_flow_error_set(error, ENOMEM,
5498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5499 "cannot allocate resource memory");
5500 *cache_resource = *resource;
5501 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5503 if (!cache_resource->action) {
5504 rte_free(cache_resource);
5505 return rte_flow_error_set(error, ENOMEM,
5506 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5507 NULL, "cannot create action");
5509 rte_atomic32_init(&cache_resource->refcnt);
5510 rte_atomic32_inc(&cache_resource->refcnt);
5511 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5512 dev_flow->flow->tag_resource = cache_resource;
5513 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5514 (void *)cache_resource,
5515 rte_atomic32_read(&cache_resource->refcnt));
5523 * Pointer to Ethernet device.
5525 * Pointer to mlx5_flow.
5528 * 1 while a reference on it exists, 0 when freed.
5531 flow_dv_tag_release(struct rte_eth_dev *dev,
5532 struct mlx5_flow_dv_tag_resource *tag)
5535 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5536 dev->data->port_id, (void *)tag,
5537 rte_atomic32_read(&tag->refcnt));
5538 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5539 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5540 LIST_REMOVE(tag, next);
5541 DRV_LOG(DEBUG, "port %u tag %p: removed",
5542 dev->data->port_id, (void *)tag);
5550 * Translate port ID action to vport.
5553 * Pointer to rte_eth_dev structure.
5555 * Pointer to the port ID action.
5556 * @param[out] dst_port_id
5557 * The target port ID.
5559 * Pointer to the error structure.
5562 * 0 on success, a negative errno value otherwise and rte_errno is set.
5565 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5566 const struct rte_flow_action *action,
5567 uint32_t *dst_port_id,
5568 struct rte_flow_error *error)
5571 struct mlx5_priv *priv;
5572 const struct rte_flow_action_port_id *conf =
5573 (const struct rte_flow_action_port_id *)action->conf;
5575 port = conf->original ? dev->data->port_id : conf->id;
5576 priv = mlx5_port_to_eswitch_info(port);
5578 return rte_flow_error_set(error, -rte_errno,
5579 RTE_FLOW_ERROR_TYPE_ACTION,
5581 "No eswitch info was found for port");
5582 if (priv->vport_meta_mask)
5583 *dst_port_id = priv->vport_meta_tag;
5585 *dst_port_id = priv->vport_id;
5590 * Add Tx queue matcher
5593 * Pointer to the dev struct.
5594 * @param[in, out] matcher
5596 * @param[in, out] key
5597 * Flow matcher value.
5599 * Flow pattern to translate.
5601 * Item is inner pattern.
5604 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5605 void *matcher, void *key,
5606 const struct rte_flow_item *item)
5608 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5609 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5611 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5613 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5614 struct mlx5_txq_ctrl *txq;
5618 queue_m = (const void *)item->mask;
5621 queue_v = (const void *)item->spec;
5624 txq = mlx5_txq_get(dev, queue_v->queue);
5627 queue = txq->obj->sq->id;
5628 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5629 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5630 queue & queue_m->queue);
5631 mlx5_txq_release(dev, queue_v->queue);
5635 * Fill the flow with DV spec.
5638 * Pointer to rte_eth_dev structure.
5639 * @param[in, out] dev_flow
5640 * Pointer to the sub flow.
5642 * Pointer to the flow attributes.
5644 * Pointer to the list of items.
5645 * @param[in] actions
5646 * Pointer to the list of actions.
5648 * Pointer to the error structure.
5651 * 0 on success, a negative errno value otherwise and rte_errno is set.
5654 flow_dv_translate(struct rte_eth_dev *dev,
5655 struct mlx5_flow *dev_flow,
5656 const struct rte_flow_attr *attr,
5657 const struct rte_flow_item items[],
5658 const struct rte_flow_action actions[],
5659 struct rte_flow_error *error)
5661 struct mlx5_priv *priv = dev->data->dev_private;
5662 struct rte_flow *flow = dev_flow->flow;
5663 uint64_t item_flags = 0;
5664 uint64_t last_item = 0;
5665 uint64_t action_flags = 0;
5666 uint64_t priority = attr->priority;
5667 struct mlx5_flow_dv_matcher matcher = {
5669 .size = sizeof(matcher.mask.buf),
5673 bool actions_end = false;
5674 struct mlx5_flow_dv_modify_hdr_resource res = {
5675 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5676 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5678 union flow_dv_attr flow_attr = { .attr = 0 };
5679 struct mlx5_flow_dv_tag_resource tag_resource;
5680 uint32_t modify_action_position = UINT32_MAX;
5681 void *match_mask = matcher.mask.buf;
5682 void *match_value = dev_flow->dv.value.buf;
5683 uint8_t next_protocol = 0xff;
5684 struct rte_vlan_hdr vlan = { 0 };
5688 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5692 flow->group = table;
5694 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5695 if (priority == MLX5_FLOW_PRIO_RSVD)
5696 priority = priv->config.flow_prio - 1;
5697 for (; !actions_end ; actions++) {
5698 const struct rte_flow_action_queue *queue;
5699 const struct rte_flow_action_rss *rss;
5700 const struct rte_flow_action *action = actions;
5701 const struct rte_flow_action_count *count = action->conf;
5702 const uint8_t *rss_key;
5703 const struct rte_flow_action_jump *jump_data;
5704 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5705 struct mlx5_flow_tbl_resource *tbl;
5706 uint32_t port_id = 0;
5707 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5708 int action_type = actions->type;
5709 const struct rte_flow_action *found_action = NULL;
5711 switch (action_type) {
5712 case RTE_FLOW_ACTION_TYPE_VOID:
5714 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5715 if (flow_dv_translate_action_port_id(dev, action,
5718 port_id_resource.port_id = port_id;
5719 if (flow_dv_port_id_action_resource_register
5720 (dev, &port_id_resource, dev_flow, error))
5722 dev_flow->dv.actions[actions_n++] =
5723 dev_flow->dv.port_id_action->action;
5724 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5726 case RTE_FLOW_ACTION_TYPE_FLAG:
5728 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5729 if (!flow->tag_resource)
5730 if (flow_dv_tag_resource_register
5731 (dev, &tag_resource, dev_flow, error))
5733 dev_flow->dv.actions[actions_n++] =
5734 flow->tag_resource->action;
5735 action_flags |= MLX5_FLOW_ACTION_FLAG;
5737 case RTE_FLOW_ACTION_TYPE_MARK:
5738 tag_resource.tag = mlx5_flow_mark_set
5739 (((const struct rte_flow_action_mark *)
5740 (actions->conf))->id);
5741 if (!flow->tag_resource)
5742 if (flow_dv_tag_resource_register
5743 (dev, &tag_resource, dev_flow, error))
5745 dev_flow->dv.actions[actions_n++] =
5746 flow->tag_resource->action;
5747 action_flags |= MLX5_FLOW_ACTION_MARK;
5749 case RTE_FLOW_ACTION_TYPE_DROP:
5750 action_flags |= MLX5_FLOW_ACTION_DROP;
5752 case RTE_FLOW_ACTION_TYPE_QUEUE:
5753 queue = actions->conf;
5754 flow->rss.queue_num = 1;
5755 (*flow->queue)[0] = queue->index;
5756 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5758 case RTE_FLOW_ACTION_TYPE_RSS:
5759 rss = actions->conf;
5761 memcpy((*flow->queue), rss->queue,
5762 rss->queue_num * sizeof(uint16_t));
5763 flow->rss.queue_num = rss->queue_num;
5764 /* NULL RSS key indicates default RSS key. */
5765 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5766 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5767 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5768 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5769 flow->rss.level = rss->level;
5770 action_flags |= MLX5_FLOW_ACTION_RSS;
5772 case RTE_FLOW_ACTION_TYPE_COUNT:
5773 if (!priv->config.devx) {
5774 rte_errno = ENOTSUP;
5777 flow->counter = flow_dv_counter_alloc(dev,
5781 if (flow->counter == NULL)
5783 dev_flow->dv.actions[actions_n++] =
5784 flow->counter->action;
5785 action_flags |= MLX5_FLOW_ACTION_COUNT;
5788 if (rte_errno == ENOTSUP)
5789 return rte_flow_error_set
5791 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5793 "count action not supported");
5795 return rte_flow_error_set
5797 RTE_FLOW_ERROR_TYPE_ACTION,
5799 "cannot create counter"
5802 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5803 dev_flow->dv.actions[actions_n++] =
5804 priv->sh->pop_vlan_action;
5805 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5807 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5808 flow_dev_get_vlan_info_from_items(items, &vlan);
5809 vlan.eth_proto = rte_be_to_cpu_16
5810 ((((const struct rte_flow_action_of_push_vlan *)
5811 actions->conf)->ethertype));
5812 found_action = mlx5_flow_find_action
5814 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5816 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5817 found_action = mlx5_flow_find_action
5819 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5821 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5822 if (flow_dv_create_action_push_vlan
5823 (dev, attr, &vlan, dev_flow, error))
5825 dev_flow->dv.actions[actions_n++] =
5826 dev_flow->dv.push_vlan_res->action;
5827 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5829 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5830 /* of_vlan_push action handled this action */
5831 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5833 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5834 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5836 flow_dev_get_vlan_info_from_items(items, &vlan);
5837 mlx5_update_vlan_vid_pcp(actions, &vlan);
5838 /* If no VLAN push - this is a modify header action */
5839 if (flow_dv_convert_action_modify_vlan_vid
5840 (&res, actions, error))
5842 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5844 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5845 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5846 if (flow_dv_create_action_l2_encap(dev, actions,
5851 dev_flow->dv.actions[actions_n++] =
5852 dev_flow->dv.encap_decap->verbs_action;
5853 action_flags |= actions->type ==
5854 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5855 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5856 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5858 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5859 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5860 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5864 dev_flow->dv.actions[actions_n++] =
5865 dev_flow->dv.encap_decap->verbs_action;
5866 action_flags |= actions->type ==
5867 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5868 MLX5_FLOW_ACTION_VXLAN_DECAP :
5869 MLX5_FLOW_ACTION_NVGRE_DECAP;
5871 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5872 /* Handle encap with preceding decap. */
5873 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5874 if (flow_dv_create_action_raw_encap
5875 (dev, actions, dev_flow, attr, error))
5877 dev_flow->dv.actions[actions_n++] =
5878 dev_flow->dv.encap_decap->verbs_action;
5880 /* Handle encap without preceding decap. */
5881 if (flow_dv_create_action_l2_encap
5882 (dev, actions, dev_flow, attr->transfer,
5885 dev_flow->dv.actions[actions_n++] =
5886 dev_flow->dv.encap_decap->verbs_action;
5888 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5890 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5891 /* Check if this decap is followed by encap. */
5892 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5893 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5896 /* Handle decap only if it isn't followed by encap. */
5897 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5898 if (flow_dv_create_action_l2_decap
5899 (dev, dev_flow, attr->transfer, error))
5901 dev_flow->dv.actions[actions_n++] =
5902 dev_flow->dv.encap_decap->verbs_action;
5904 /* If decap is followed by encap, handle it at encap. */
5905 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5907 case RTE_FLOW_ACTION_TYPE_JUMP:
5908 jump_data = action->conf;
5909 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5910 jump_data->group, &table,
5914 tbl = flow_dv_tbl_resource_get(dev, table,
5916 attr->transfer, error);
5918 return rte_flow_error_set
5920 RTE_FLOW_ERROR_TYPE_ACTION,
5922 "cannot create jump action.");
5923 jump_tbl_resource.tbl = tbl;
5924 if (flow_dv_jump_tbl_resource_register
5925 (dev, &jump_tbl_resource, dev_flow, error)) {
5926 flow_dv_tbl_resource_release(tbl);
5927 return rte_flow_error_set
5929 RTE_FLOW_ERROR_TYPE_ACTION,
5931 "cannot create jump action.");
5933 dev_flow->dv.actions[actions_n++] =
5934 dev_flow->dv.jump->action;
5935 action_flags |= MLX5_FLOW_ACTION_JUMP;
5937 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5938 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5939 if (flow_dv_convert_action_modify_mac(&res, actions,
5942 action_flags |= actions->type ==
5943 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5944 MLX5_FLOW_ACTION_SET_MAC_SRC :
5945 MLX5_FLOW_ACTION_SET_MAC_DST;
5947 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5948 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5949 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5952 action_flags |= actions->type ==
5953 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5954 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5955 MLX5_FLOW_ACTION_SET_IPV4_DST;
5957 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5958 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5959 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5962 action_flags |= actions->type ==
5963 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5964 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5965 MLX5_FLOW_ACTION_SET_IPV6_DST;
5967 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5968 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5969 if (flow_dv_convert_action_modify_tp(&res, actions,
5973 action_flags |= actions->type ==
5974 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5975 MLX5_FLOW_ACTION_SET_TP_SRC :
5976 MLX5_FLOW_ACTION_SET_TP_DST;
5978 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5979 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5983 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5985 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5986 if (flow_dv_convert_action_modify_ttl(&res, actions,
5990 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5992 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5993 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5994 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5997 action_flags |= actions->type ==
5998 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5999 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6000 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6003 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6004 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6005 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
6008 action_flags |= actions->type ==
6009 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6010 MLX5_FLOW_ACTION_INC_TCP_ACK :
6011 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6013 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6014 if (flow_dv_convert_action_set_reg(&res, actions,
6017 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6019 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6020 if (flow_dv_convert_action_copy_mreg(dev, &res,
6023 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6025 case RTE_FLOW_ACTION_TYPE_END:
6027 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6028 /* create modify action if needed. */
6029 if (flow_dv_modify_hdr_resource_register
6034 dev_flow->dv.actions[modify_action_position] =
6035 dev_flow->dv.modify_hdr->verbs_action;
6041 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6042 modify_action_position == UINT32_MAX)
6043 modify_action_position = actions_n++;
6045 dev_flow->dv.actions_n = actions_n;
6046 dev_flow->actions = action_flags;
6047 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6048 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6049 int item_type = items->type;
6051 switch (item_type) {
6052 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6053 flow_dv_translate_item_port_id(dev, match_mask,
6054 match_value, items);
6055 last_item = MLX5_FLOW_ITEM_PORT_ID;
6057 case RTE_FLOW_ITEM_TYPE_ETH:
6058 flow_dv_translate_item_eth(match_mask, match_value,
6060 matcher.priority = MLX5_PRIORITY_MAP_L2;
6061 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6062 MLX5_FLOW_LAYER_OUTER_L2;
6064 case RTE_FLOW_ITEM_TYPE_VLAN:
6065 flow_dv_translate_item_vlan(dev_flow,
6066 match_mask, match_value,
6068 matcher.priority = MLX5_PRIORITY_MAP_L2;
6069 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6070 MLX5_FLOW_LAYER_INNER_VLAN) :
6071 (MLX5_FLOW_LAYER_OUTER_L2 |
6072 MLX5_FLOW_LAYER_OUTER_VLAN);
6074 case RTE_FLOW_ITEM_TYPE_IPV4:
6075 mlx5_flow_tunnel_ip_check(items, next_protocol,
6076 &item_flags, &tunnel);
6077 flow_dv_translate_item_ipv4(match_mask, match_value,
6078 items, tunnel, flow->group);
6079 matcher.priority = MLX5_PRIORITY_MAP_L3;
6080 dev_flow->dv.hash_fields |=
6081 mlx5_flow_hashfields_adjust
6083 MLX5_IPV4_LAYER_TYPES,
6084 MLX5_IPV4_IBV_RX_HASH);
6085 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6086 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6087 if (items->mask != NULL &&
6088 ((const struct rte_flow_item_ipv4 *)
6089 items->mask)->hdr.next_proto_id) {
6091 ((const struct rte_flow_item_ipv4 *)
6092 (items->spec))->hdr.next_proto_id;
6094 ((const struct rte_flow_item_ipv4 *)
6095 (items->mask))->hdr.next_proto_id;
6097 /* Reset for inner layer. */
6098 next_protocol = 0xff;
6101 case RTE_FLOW_ITEM_TYPE_IPV6:
6102 mlx5_flow_tunnel_ip_check(items, next_protocol,
6103 &item_flags, &tunnel);
6104 flow_dv_translate_item_ipv6(match_mask, match_value,
6105 items, tunnel, flow->group);
6106 matcher.priority = MLX5_PRIORITY_MAP_L3;
6107 dev_flow->dv.hash_fields |=
6108 mlx5_flow_hashfields_adjust
6110 MLX5_IPV6_LAYER_TYPES,
6111 MLX5_IPV6_IBV_RX_HASH);
6112 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6113 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6114 if (items->mask != NULL &&
6115 ((const struct rte_flow_item_ipv6 *)
6116 items->mask)->hdr.proto) {
6118 ((const struct rte_flow_item_ipv6 *)
6119 items->spec)->hdr.proto;
6121 ((const struct rte_flow_item_ipv6 *)
6122 items->mask)->hdr.proto;
6124 /* Reset for inner layer. */
6125 next_protocol = 0xff;
6128 case RTE_FLOW_ITEM_TYPE_TCP:
6129 flow_dv_translate_item_tcp(match_mask, match_value,
6131 matcher.priority = MLX5_PRIORITY_MAP_L4;
6132 dev_flow->dv.hash_fields |=
6133 mlx5_flow_hashfields_adjust
6134 (dev_flow, tunnel, ETH_RSS_TCP,
6135 IBV_RX_HASH_SRC_PORT_TCP |
6136 IBV_RX_HASH_DST_PORT_TCP);
6137 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6138 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6140 case RTE_FLOW_ITEM_TYPE_UDP:
6141 flow_dv_translate_item_udp(match_mask, match_value,
6143 matcher.priority = MLX5_PRIORITY_MAP_L4;
6144 dev_flow->dv.hash_fields |=
6145 mlx5_flow_hashfields_adjust
6146 (dev_flow, tunnel, ETH_RSS_UDP,
6147 IBV_RX_HASH_SRC_PORT_UDP |
6148 IBV_RX_HASH_DST_PORT_UDP);
6149 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6150 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6152 case RTE_FLOW_ITEM_TYPE_GRE:
6153 flow_dv_translate_item_gre(match_mask, match_value,
6155 last_item = MLX5_FLOW_LAYER_GRE;
6157 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6158 flow_dv_translate_item_gre_key(match_mask,
6159 match_value, items);
6160 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6162 case RTE_FLOW_ITEM_TYPE_NVGRE:
6163 flow_dv_translate_item_nvgre(match_mask, match_value,
6165 last_item = MLX5_FLOW_LAYER_GRE;
6167 case RTE_FLOW_ITEM_TYPE_VXLAN:
6168 flow_dv_translate_item_vxlan(match_mask, match_value,
6170 last_item = MLX5_FLOW_LAYER_VXLAN;
6172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6173 flow_dv_translate_item_vxlan(match_mask, match_value,
6175 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6177 case RTE_FLOW_ITEM_TYPE_GENEVE:
6178 flow_dv_translate_item_geneve(match_mask, match_value,
6180 last_item = MLX5_FLOW_LAYER_GENEVE;
6182 case RTE_FLOW_ITEM_TYPE_MPLS:
6183 flow_dv_translate_item_mpls(match_mask, match_value,
6184 items, last_item, tunnel);
6185 last_item = MLX5_FLOW_LAYER_MPLS;
6187 case RTE_FLOW_ITEM_TYPE_META:
6188 flow_dv_translate_item_meta(match_mask, match_value,
6190 last_item = MLX5_FLOW_ITEM_METADATA;
6192 case RTE_FLOW_ITEM_TYPE_ICMP:
6193 flow_dv_translate_item_icmp(match_mask, match_value,
6195 last_item = MLX5_FLOW_LAYER_ICMP;
6197 case RTE_FLOW_ITEM_TYPE_ICMP6:
6198 flow_dv_translate_item_icmp6(match_mask, match_value,
6200 last_item = MLX5_FLOW_LAYER_ICMP6;
6202 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6203 flow_dv_translate_item_tag(match_mask, match_value,
6205 last_item = MLX5_FLOW_ITEM_TAG;
6207 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6208 flow_dv_translate_item_tx_queue(dev, match_mask,
6211 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6216 item_flags |= last_item;
6219 * In case of ingress traffic when E-Switch mode is enabled,
6220 * we have two cases where we need to set the source port manually.
6221 * The first one, is in case of Nic steering rule, and the second is
6222 * E-Switch rule where no port_id item was found. In both cases
6223 * the source port is set according the current port in use.
6225 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6226 (priv->representor || priv->master)) {
6227 if (flow_dv_translate_item_port_id(dev, match_mask,
6231 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6232 dev_flow->dv.value.buf));
6233 dev_flow->layers = item_flags;
6234 /* Register matcher. */
6235 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6237 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6239 matcher.egress = attr->egress;
6240 matcher.group = flow->group;
6241 matcher.transfer = attr->transfer;
6242 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6248 * Apply the flow to the NIC.
6251 * Pointer to the Ethernet device structure.
6252 * @param[in, out] flow
6253 * Pointer to flow structure.
6255 * Pointer to error structure.
6258 * 0 on success, a negative errno value otherwise and rte_errno is set.
6261 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6262 struct rte_flow_error *error)
6264 struct mlx5_flow_dv *dv;
6265 struct mlx5_flow *dev_flow;
6266 struct mlx5_priv *priv = dev->data->dev_private;
6270 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6273 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6274 if (flow->transfer) {
6275 dv->actions[n++] = priv->sh->esw_drop_action;
6277 dv->hrxq = mlx5_hrxq_drop_new(dev);
6281 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6283 "cannot get drop hash queue");
6286 dv->actions[n++] = dv->hrxq->action;
6288 } else if (dev_flow->actions &
6289 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6290 struct mlx5_hrxq *hrxq;
6292 hrxq = mlx5_hrxq_get(dev, flow->key,
6293 MLX5_RSS_HASH_KEY_LEN,
6296 flow->rss.queue_num);
6298 hrxq = mlx5_hrxq_new
6299 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6300 dv->hash_fields, (*flow->queue),
6301 flow->rss.queue_num,
6302 !!(dev_flow->layers &
6303 MLX5_FLOW_LAYER_TUNNEL));
6308 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6309 "cannot get hash queue");
6313 dv->actions[n++] = dv->hrxq->action;
6316 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6317 (void *)&dv->value, n,
6320 rte_flow_error_set(error, errno,
6321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6323 "hardware refuses to create flow");
6326 if (priv->vmwa_context &&
6327 dev_flow->dv.vf_vlan.tag &&
6328 !dev_flow->dv.vf_vlan.created) {
6330 * The rule contains the VLAN pattern.
6331 * For VF we are going to create VLAN
6332 * interface to make hypervisor set correct
6333 * e-Switch vport context.
6335 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6340 err = rte_errno; /* Save rte_errno before cleanup. */
6341 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6342 struct mlx5_flow_dv *dv = &dev_flow->dv;
6344 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6345 mlx5_hrxq_drop_release(dev);
6347 mlx5_hrxq_release(dev, dv->hrxq);
6350 if (dev_flow->dv.vf_vlan.tag &&
6351 dev_flow->dv.vf_vlan.created)
6352 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6354 rte_errno = err; /* Restore rte_errno. */
6359 * Release the flow matcher.
6362 * Pointer to Ethernet device.
6364 * Pointer to mlx5_flow.
6367 * 1 while a reference on it exists, 0 when freed.
6370 flow_dv_matcher_release(struct rte_eth_dev *dev,
6371 struct mlx5_flow *flow)
6373 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6374 struct mlx5_priv *priv = dev->data->dev_private;
6375 struct mlx5_ibv_shared *sh = priv->sh;
6376 struct mlx5_flow_tbl_resource *tbl;
6378 assert(matcher->matcher_object);
6379 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6380 dev->data->port_id, (void *)matcher,
6381 rte_atomic32_read(&matcher->refcnt));
6382 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6383 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6384 (matcher->matcher_object));
6385 LIST_REMOVE(matcher, next);
6386 if (matcher->egress)
6387 tbl = &sh->tx_tbl[matcher->group];
6389 tbl = &sh->rx_tbl[matcher->group];
6390 flow_dv_tbl_resource_release(tbl);
6392 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6393 dev->data->port_id, (void *)matcher);
6400 * Release an encap/decap resource.
6403 * Pointer to mlx5_flow.
6406 * 1 while a reference on it exists, 0 when freed.
6409 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6411 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6412 flow->dv.encap_decap;
6414 assert(cache_resource->verbs_action);
6415 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6416 (void *)cache_resource,
6417 rte_atomic32_read(&cache_resource->refcnt));
6418 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6419 claim_zero(mlx5_glue->destroy_flow_action
6420 (cache_resource->verbs_action));
6421 LIST_REMOVE(cache_resource, next);
6422 rte_free(cache_resource);
6423 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6424 (void *)cache_resource);
6431 * Release an jump to table action resource.
6434 * Pointer to mlx5_flow.
6437 * 1 while a reference on it exists, 0 when freed.
6440 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6442 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6445 assert(cache_resource->action);
6446 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6447 (void *)cache_resource,
6448 rte_atomic32_read(&cache_resource->refcnt));
6449 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6450 claim_zero(mlx5_glue->destroy_flow_action
6451 (cache_resource->action));
6452 LIST_REMOVE(cache_resource, next);
6453 flow_dv_tbl_resource_release(cache_resource->tbl);
6454 rte_free(cache_resource);
6455 DRV_LOG(DEBUG, "jump table resource %p: removed",
6456 (void *)cache_resource);
6463 * Release a modify-header resource.
6466 * Pointer to mlx5_flow.
6469 * 1 while a reference on it exists, 0 when freed.
6472 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6474 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6475 flow->dv.modify_hdr;
6477 assert(cache_resource->verbs_action);
6478 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6479 (void *)cache_resource,
6480 rte_atomic32_read(&cache_resource->refcnt));
6481 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6482 claim_zero(mlx5_glue->destroy_flow_action
6483 (cache_resource->verbs_action));
6484 LIST_REMOVE(cache_resource, next);
6485 rte_free(cache_resource);
6486 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6487 (void *)cache_resource);
6494 * Release port ID action resource.
6497 * Pointer to mlx5_flow.
6500 * 1 while a reference on it exists, 0 when freed.
6503 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6505 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6506 flow->dv.port_id_action;
6508 assert(cache_resource->action);
6509 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6510 (void *)cache_resource,
6511 rte_atomic32_read(&cache_resource->refcnt));
6512 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6513 claim_zero(mlx5_glue->destroy_flow_action
6514 (cache_resource->action));
6515 LIST_REMOVE(cache_resource, next);
6516 rte_free(cache_resource);
6517 DRV_LOG(DEBUG, "port id action resource %p: removed",
6518 (void *)cache_resource);
6525 * Release push vlan action resource.
6528 * Pointer to mlx5_flow.
6531 * 1 while a reference on it exists, 0 when freed.
6534 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6536 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6537 flow->dv.push_vlan_res;
6539 assert(cache_resource->action);
6540 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6541 (void *)cache_resource,
6542 rte_atomic32_read(&cache_resource->refcnt));
6543 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6544 claim_zero(mlx5_glue->destroy_flow_action
6545 (cache_resource->action));
6546 LIST_REMOVE(cache_resource, next);
6547 rte_free(cache_resource);
6548 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6549 (void *)cache_resource);
6556 * Remove the flow from the NIC but keeps it in memory.
6559 * Pointer to Ethernet device.
6560 * @param[in, out] flow
6561 * Pointer to flow structure.
6564 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6566 struct mlx5_flow_dv *dv;
6567 struct mlx5_flow *dev_flow;
6571 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6574 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6578 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6579 mlx5_hrxq_drop_release(dev);
6581 mlx5_hrxq_release(dev, dv->hrxq);
6584 if (dev_flow->dv.vf_vlan.tag &&
6585 dev_flow->dv.vf_vlan.created)
6586 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6591 * Remove the flow from the NIC and the memory.
6594 * Pointer to the Ethernet device structure.
6595 * @param[in, out] flow
6596 * Pointer to flow structure.
6599 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6601 struct mlx5_flow *dev_flow;
6605 flow_dv_remove(dev, flow);
6606 if (flow->counter) {
6607 flow_dv_counter_release(dev, flow->counter);
6608 flow->counter = NULL;
6610 if (flow->tag_resource) {
6611 flow_dv_tag_release(dev, flow->tag_resource);
6612 flow->tag_resource = NULL;
6614 while (!LIST_EMPTY(&flow->dev_flows)) {
6615 dev_flow = LIST_FIRST(&flow->dev_flows);
6616 LIST_REMOVE(dev_flow, next);
6617 if (dev_flow->dv.matcher)
6618 flow_dv_matcher_release(dev, dev_flow);
6619 if (dev_flow->dv.encap_decap)
6620 flow_dv_encap_decap_resource_release(dev_flow);
6621 if (dev_flow->dv.modify_hdr)
6622 flow_dv_modify_hdr_resource_release(dev_flow);
6623 if (dev_flow->dv.jump)
6624 flow_dv_jump_tbl_resource_release(dev_flow);
6625 if (dev_flow->dv.port_id_action)
6626 flow_dv_port_id_action_resource_release(dev_flow);
6627 if (dev_flow->dv.push_vlan_res)
6628 flow_dv_push_vlan_action_resource_release(dev_flow);
6634 * Query a dv flow rule for its statistics via devx.
6637 * Pointer to Ethernet device.
6639 * Pointer to the sub flow.
6641 * data retrieved by the query.
6643 * Perform verbose error reporting if not NULL.
6646 * 0 on success, a negative errno value otherwise and rte_errno is set.
6649 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6650 void *data, struct rte_flow_error *error)
6652 struct mlx5_priv *priv = dev->data->dev_private;
6653 struct rte_flow_query_count *qc = data;
6655 if (!priv->config.devx)
6656 return rte_flow_error_set(error, ENOTSUP,
6657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6659 "counters are not supported");
6660 if (flow->counter) {
6661 uint64_t pkts, bytes;
6662 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6666 return rte_flow_error_set(error, -err,
6667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6668 NULL, "cannot read counters");
6671 qc->hits = pkts - flow->counter->hits;
6672 qc->bytes = bytes - flow->counter->bytes;
6674 flow->counter->hits = pkts;
6675 flow->counter->bytes = bytes;
6679 return rte_flow_error_set(error, EINVAL,
6680 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6682 "counters are not available");
6688 * @see rte_flow_query()
6692 flow_dv_query(struct rte_eth_dev *dev,
6693 struct rte_flow *flow __rte_unused,
6694 const struct rte_flow_action *actions __rte_unused,
6695 void *data __rte_unused,
6696 struct rte_flow_error *error __rte_unused)
6700 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6701 switch (actions->type) {
6702 case RTE_FLOW_ACTION_TYPE_VOID:
6704 case RTE_FLOW_ACTION_TYPE_COUNT:
6705 ret = flow_dv_query_count(dev, flow, data, error);
6708 return rte_flow_error_set(error, ENOTSUP,
6709 RTE_FLOW_ERROR_TYPE_ACTION,
6711 "action not supported");
6718 * Mutex-protected thunk to flow_dv_translate().
6721 flow_d_translate(struct rte_eth_dev *dev,
6722 struct mlx5_flow *dev_flow,
6723 const struct rte_flow_attr *attr,
6724 const struct rte_flow_item items[],
6725 const struct rte_flow_action actions[],
6726 struct rte_flow_error *error)
6730 flow_d_shared_lock(dev);
6731 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6732 flow_d_shared_unlock(dev);
6737 * Mutex-protected thunk to flow_dv_apply().
6740 flow_d_apply(struct rte_eth_dev *dev,
6741 struct rte_flow *flow,
6742 struct rte_flow_error *error)
6746 flow_d_shared_lock(dev);
6747 ret = flow_dv_apply(dev, flow, error);
6748 flow_d_shared_unlock(dev);
6753 * Mutex-protected thunk to flow_dv_remove().
6756 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6758 flow_d_shared_lock(dev);
6759 flow_dv_remove(dev, flow);
6760 flow_d_shared_unlock(dev);
6764 * Mutex-protected thunk to flow_dv_destroy().
6767 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6769 flow_d_shared_lock(dev);
6770 flow_dv_destroy(dev, flow);
6771 flow_d_shared_unlock(dev);
6774 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6775 .validate = flow_dv_validate,
6776 .prepare = flow_dv_prepare,
6777 .translate = flow_d_translate,
6778 .apply = flow_d_apply,
6779 .remove = flow_d_remove,
6780 .destroy = flow_d_destroy,
6781 .query = flow_dv_query,
6784 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */