1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 static inline uint16_t
97 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
99 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
100 return RTE_ETHER_TYPE_TEB;
101 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 return RTE_ETHER_TYPE_IPV4;
103 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 return RTE_ETHER_TYPE_IPV6;
105 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
106 return RTE_ETHER_TYPE_MPLS;
111 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
113 struct mlx5_priv *priv = dev->data->dev_private;
115 if (priv->pci_dev == NULL)
117 switch (priv->pci_dev->id.device_id) {
118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
119 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
120 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
121 return (int16_t)0xfffe;
128 * Initialize flow attributes structure according to flow items' types.
130 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
131 * mode. For tunnel mode, the items to be modified are the outermost ones.
134 * Pointer to item specification.
136 * Pointer to flow attributes structure.
137 * @param[in] dev_flow
138 * Pointer to the sub flow.
139 * @param[in] tunnel_decap
140 * Whether action is after tunnel decapsulation.
143 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
144 struct mlx5_flow *dev_flow, bool tunnel_decap)
146 uint64_t layers = dev_flow->handle->layers;
149 * If layers is already initialized, it means this dev_flow is the
150 * suffix flow, the layers flags is set by the prefix flow. Need to
151 * use the layer flags from prefix flow as the suffix flow may not
152 * have the user defined items as the flow is split.
155 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
157 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
159 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
161 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
166 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
167 uint8_t next_protocol = 0xff;
168 switch (item->type) {
169 case RTE_FLOW_ITEM_TYPE_GRE:
170 case RTE_FLOW_ITEM_TYPE_NVGRE:
171 case RTE_FLOW_ITEM_TYPE_VXLAN:
172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
173 case RTE_FLOW_ITEM_TYPE_GENEVE:
174 case RTE_FLOW_ITEM_TYPE_MPLS:
178 case RTE_FLOW_ITEM_TYPE_IPV4:
181 if (item->mask != NULL &&
182 ((const struct rte_flow_item_ipv4 *)
183 item->mask)->hdr.next_proto_id)
185 ((const struct rte_flow_item_ipv4 *)
186 (item->spec))->hdr.next_proto_id &
187 ((const struct rte_flow_item_ipv4 *)
188 (item->mask))->hdr.next_proto_id;
189 if ((next_protocol == IPPROTO_IPIP ||
190 next_protocol == IPPROTO_IPV6) && tunnel_decap)
193 case RTE_FLOW_ITEM_TYPE_IPV6:
196 if (item->mask != NULL &&
197 ((const struct rte_flow_item_ipv6 *)
198 item->mask)->hdr.proto)
200 ((const struct rte_flow_item_ipv6 *)
201 (item->spec))->hdr.proto &
202 ((const struct rte_flow_item_ipv6 *)
203 (item->mask))->hdr.proto;
204 if ((next_protocol == IPPROTO_IPIP ||
205 next_protocol == IPPROTO_IPV6) && tunnel_decap)
208 case RTE_FLOW_ITEM_TYPE_UDP:
212 case RTE_FLOW_ITEM_TYPE_TCP:
224 * Convert rte_mtr_color to mlx5 color.
233 rte_col_2_mlx5_col(enum rte_color rcol)
236 case RTE_COLOR_GREEN:
237 return MLX5_FLOW_COLOR_GREEN;
238 case RTE_COLOR_YELLOW:
239 return MLX5_FLOW_COLOR_YELLOW;
241 return MLX5_FLOW_COLOR_RED;
245 return MLX5_FLOW_COLOR_UNDEFINED;
248 struct field_modify_info {
249 uint32_t size; /* Size of field in protocol header, in bytes. */
250 uint32_t offset; /* Offset of field in protocol header, in bytes. */
251 enum mlx5_modification_field id;
254 struct field_modify_info modify_eth[] = {
255 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
256 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
257 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
258 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
262 struct field_modify_info modify_vlan_out_first_vid[] = {
263 /* Size in bits !!! */
264 {12, 0, MLX5_MODI_OUT_FIRST_VID},
268 struct field_modify_info modify_ipv4[] = {
269 {1, 1, MLX5_MODI_OUT_IP_DSCP},
270 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
271 {4, 12, MLX5_MODI_OUT_SIPV4},
272 {4, 16, MLX5_MODI_OUT_DIPV4},
276 struct field_modify_info modify_ipv6[] = {
277 {1, 0, MLX5_MODI_OUT_IP_DSCP},
278 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
279 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
280 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
281 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
282 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
283 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
284 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
285 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
286 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
290 struct field_modify_info modify_udp[] = {
291 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
292 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
296 struct field_modify_info modify_tcp[] = {
297 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
298 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
299 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
300 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
305 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
306 uint8_t next_protocol, uint64_t *item_flags,
309 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
310 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
311 if (next_protocol == IPPROTO_IPIP) {
312 *item_flags |= MLX5_FLOW_LAYER_IPIP;
315 if (next_protocol == IPPROTO_IPV6) {
316 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
321 static inline struct mlx5_hlist *
322 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
323 const char *name, uint32_t size, bool direct_key,
324 bool lcores_share, void *ctx,
325 mlx5_list_create_cb cb_create,
326 mlx5_list_match_cb cb_match,
327 mlx5_list_remove_cb cb_remove,
328 mlx5_list_clone_cb cb_clone,
329 mlx5_list_clone_free_cb cb_clone_free)
331 struct mlx5_hlist *hl;
332 struct mlx5_hlist *expected = NULL;
333 char s[MLX5_NAME_SIZE];
335 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
338 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
339 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
340 ctx, cb_create, cb_match, cb_remove, cb_clone,
343 DRV_LOG(ERR, "%s hash creation failed", name);
347 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
350 mlx5_hlist_destroy(hl);
351 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
356 /* Update VLAN's VID/PCP based on input rte_flow_action.
359 * Pointer to struct rte_flow_action.
361 * Pointer to struct rte_vlan_hdr.
364 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
365 struct rte_vlan_hdr *vlan)
368 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
370 ((const struct rte_flow_action_of_set_vlan_pcp *)
371 action->conf)->vlan_pcp;
372 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
373 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
374 vlan->vlan_tci |= vlan_tci;
375 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
376 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
377 vlan->vlan_tci |= rte_be_to_cpu_16
378 (((const struct rte_flow_action_of_set_vlan_vid *)
379 action->conf)->vlan_vid);
384 * Fetch 1, 2, 3 or 4 byte field from the byte array
385 * and return as unsigned integer in host-endian format.
388 * Pointer to data array.
390 * Size of field to extract.
393 * converted field in host endian format.
395 static inline uint32_t
396 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
405 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
408 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
409 ret = (ret << 8) | *(data + sizeof(uint16_t));
412 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
423 * Convert modify-header action to DV specification.
425 * Data length of each action is determined by provided field description
426 * and the item mask. Data bit offset and width of each action is determined
427 * by provided item mask.
430 * Pointer to item specification.
432 * Pointer to field modification information.
433 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
434 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
435 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
437 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
438 * Negative offset value sets the same offset as source offset.
439 * size field is ignored, value is taken from source field.
440 * @param[in,out] resource
441 * Pointer to the modify-header resource.
443 * Type of modification.
445 * Pointer to the error structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 flow_dv_convert_modify_action(struct rte_flow_item *item,
452 struct field_modify_info *field,
453 struct field_modify_info *dcopy,
454 struct mlx5_flow_dv_modify_hdr_resource *resource,
455 uint32_t type, struct rte_flow_error *error)
457 uint32_t i = resource->actions_num;
458 struct mlx5_modification_cmd *actions = resource->actions;
459 uint32_t carry_b = 0;
462 * The item and mask are provided in big-endian format.
463 * The fields should be presented as in big-endian format either.
464 * Mask must be always present, it defines the actual field width.
466 MLX5_ASSERT(item->mask);
467 MLX5_ASSERT(field->size);
473 bool next_field = true;
474 bool next_dcopy = true;
476 if (i >= MLX5_MAX_MODIFY_NUM)
477 return rte_flow_error_set(error, EINVAL,
478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
479 "too many items to modify");
480 /* Fetch variable byte size mask from the array. */
481 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
482 field->offset, field->size);
487 /* Deduce actual data width in bits from mask value. */
488 off_b = rte_bsf32(mask) + carry_b;
489 size_b = sizeof(uint32_t) * CHAR_BIT -
490 off_b - __builtin_clz(mask);
492 actions[i] = (struct mlx5_modification_cmd) {
496 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
499 if (type == MLX5_MODIFICATION_TYPE_COPY) {
501 actions[i].dst_field = dcopy->id;
502 actions[i].dst_offset =
503 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
504 /* Convert entire record to big-endian format. */
505 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
507 * Destination field overflow. Copy leftovers of
508 * a source field to the next destination field.
511 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
514 dcopy->size * CHAR_BIT - dcopy->offset;
515 carry_b = actions[i].length;
519 * Not enough bits in a source filed to fill a
520 * destination field. Switch to the next source.
522 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
523 (size_b == field->size * CHAR_BIT - off_b)) {
525 field->size * CHAR_BIT - off_b;
526 dcopy->offset += actions[i].length;
532 MLX5_ASSERT(item->spec);
533 data = flow_dv_fetch_field((const uint8_t *)item->spec +
534 field->offset, field->size);
535 /* Shift out the trailing masked bits from data. */
536 data = (data & mask) >> off_b;
537 actions[i].data1 = rte_cpu_to_be_32(data);
539 /* Convert entire record to expected big-endian format. */
540 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
544 } while (field->size);
545 if (resource->actions_num == i)
546 return rte_flow_error_set(error, EINVAL,
547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
548 "invalid modification flow item");
549 resource->actions_num = i;
554 * Convert modify-header set IPv4 address action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to the error structure.
564 * 0 on success, a negative errno value otherwise and rte_errno is set.
567 flow_dv_convert_action_modify_ipv4
568 (struct mlx5_flow_dv_modify_hdr_resource *resource,
569 const struct rte_flow_action *action,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ipv4 *conf =
573 (const struct rte_flow_action_set_ipv4 *)(action->conf);
574 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
578 memset(&ipv4, 0, sizeof(ipv4));
579 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
580 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
581 ipv4.hdr.src_addr = conf->ipv4_addr;
582 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
584 ipv4.hdr.dst_addr = conf->ipv4_addr;
585 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
588 item.mask = &ipv4_mask;
589 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
590 MLX5_MODIFICATION_TYPE_SET, error);
594 * Convert modify-header set IPv6 address action to DV specification.
596 * @param[in,out] resource
597 * Pointer to the modify-header resource.
599 * Pointer to action specification.
601 * Pointer to the error structure.
604 * 0 on success, a negative errno value otherwise and rte_errno is set.
607 flow_dv_convert_action_modify_ipv6
608 (struct mlx5_flow_dv_modify_hdr_resource *resource,
609 const struct rte_flow_action *action,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_ipv6 *conf =
613 (const struct rte_flow_action_set_ipv6 *)(action->conf);
614 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
615 struct rte_flow_item_ipv6 ipv6;
616 struct rte_flow_item_ipv6 ipv6_mask;
618 memset(&ipv6, 0, sizeof(ipv6));
619 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
620 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
621 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
622 sizeof(ipv6.hdr.src_addr));
623 memcpy(&ipv6_mask.hdr.src_addr,
624 &rte_flow_item_ipv6_mask.hdr.src_addr,
625 sizeof(ipv6.hdr.src_addr));
627 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
628 sizeof(ipv6.hdr.dst_addr));
629 memcpy(&ipv6_mask.hdr.dst_addr,
630 &rte_flow_item_ipv6_mask.hdr.dst_addr,
631 sizeof(ipv6.hdr.dst_addr));
634 item.mask = &ipv6_mask;
635 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
636 MLX5_MODIFICATION_TYPE_SET, error);
640 * Convert modify-header set MAC address action to DV specification.
642 * @param[in,out] resource
643 * Pointer to the modify-header resource.
645 * Pointer to action specification.
647 * Pointer to the error structure.
650 * 0 on success, a negative errno value otherwise and rte_errno is set.
653 flow_dv_convert_action_modify_mac
654 (struct mlx5_flow_dv_modify_hdr_resource *resource,
655 const struct rte_flow_action *action,
656 struct rte_flow_error *error)
658 const struct rte_flow_action_set_mac *conf =
659 (const struct rte_flow_action_set_mac *)(action->conf);
660 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
661 struct rte_flow_item_eth eth;
662 struct rte_flow_item_eth eth_mask;
664 memset(ð, 0, sizeof(eth));
665 memset(ð_mask, 0, sizeof(eth_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
667 memcpy(ð.src.addr_bytes, &conf->mac_addr,
668 sizeof(eth.src.addr_bytes));
669 memcpy(ð_mask.src.addr_bytes,
670 &rte_flow_item_eth_mask.src.addr_bytes,
671 sizeof(eth_mask.src.addr_bytes));
673 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
674 sizeof(eth.dst.addr_bytes));
675 memcpy(ð_mask.dst.addr_bytes,
676 &rte_flow_item_eth_mask.dst.addr_bytes,
677 sizeof(eth_mask.dst.addr_bytes));
680 item.mask = ð_mask;
681 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
682 MLX5_MODIFICATION_TYPE_SET, error);
686 * Convert modify-header set VLAN VID action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to the error structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 flow_dv_convert_action_modify_vlan_vid
700 (struct mlx5_flow_dv_modify_hdr_resource *resource,
701 const struct rte_flow_action *action,
702 struct rte_flow_error *error)
704 const struct rte_flow_action_of_set_vlan_vid *conf =
705 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
706 int i = resource->actions_num;
707 struct mlx5_modification_cmd *actions = resource->actions;
708 struct field_modify_info *field = modify_vlan_out_first_vid;
710 if (i >= MLX5_MAX_MODIFY_NUM)
711 return rte_flow_error_set(error, EINVAL,
712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
713 "too many items to modify");
714 actions[i] = (struct mlx5_modification_cmd) {
715 .action_type = MLX5_MODIFICATION_TYPE_SET,
717 .length = field->size,
718 .offset = field->offset,
720 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
721 actions[i].data1 = conf->vlan_vid;
722 actions[i].data1 = actions[i].data1 << 16;
723 resource->actions_num = ++i;
728 * Convert modify-header set TP action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_tp
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_tp *conf =
757 (const struct rte_flow_action_set_tp *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_udp udp;
760 struct rte_flow_item_udp udp_mask;
761 struct rte_flow_item_tcp tcp;
762 struct rte_flow_item_tcp tcp_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&udp, 0, sizeof(udp));
769 memset(&udp_mask, 0, sizeof(udp_mask));
770 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
771 udp.hdr.src_port = conf->port;
772 udp_mask.hdr.src_port =
773 rte_flow_item_udp_mask.hdr.src_port;
775 udp.hdr.dst_port = conf->port;
776 udp_mask.hdr.dst_port =
777 rte_flow_item_udp_mask.hdr.dst_port;
779 item.type = RTE_FLOW_ITEM_TYPE_UDP;
781 item.mask = &udp_mask;
784 MLX5_ASSERT(attr->tcp);
785 memset(&tcp, 0, sizeof(tcp));
786 memset(&tcp_mask, 0, sizeof(tcp_mask));
787 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
788 tcp.hdr.src_port = conf->port;
789 tcp_mask.hdr.src_port =
790 rte_flow_item_tcp_mask.hdr.src_port;
792 tcp.hdr.dst_port = conf->port;
793 tcp_mask.hdr.dst_port =
794 rte_flow_item_tcp_mask.hdr.dst_port;
796 item.type = RTE_FLOW_ITEM_TYPE_TCP;
798 item.mask = &tcp_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header set TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_action *action,
830 const struct rte_flow_item *items,
831 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
832 bool tunnel_decap, struct rte_flow_error *error)
834 const struct rte_flow_action_set_ttl *conf =
835 (const struct rte_flow_action_set_ttl *)(action->conf);
836 struct rte_flow_item item;
837 struct rte_flow_item_ipv4 ipv4;
838 struct rte_flow_item_ipv4 ipv4_mask;
839 struct rte_flow_item_ipv6 ipv6;
840 struct rte_flow_item_ipv6 ipv6_mask;
841 struct field_modify_info *field;
844 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
846 memset(&ipv4, 0, sizeof(ipv4));
847 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
848 ipv4.hdr.time_to_live = conf->ttl_value;
849 ipv4_mask.hdr.time_to_live = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
852 item.mask = &ipv4_mask;
855 MLX5_ASSERT(attr->ipv6);
856 memset(&ipv6, 0, sizeof(ipv6));
857 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
858 ipv6.hdr.hop_limits = conf->ttl_value;
859 ipv6_mask.hdr.hop_limits = 0xFF;
860 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
862 item.mask = &ipv6_mask;
865 return flow_dv_convert_modify_action(&item, field, NULL, resource,
866 MLX5_MODIFICATION_TYPE_SET, error);
870 * Convert modify-header decrement TTL action to DV specification.
872 * @param[in,out] resource
873 * Pointer to the modify-header resource.
875 * Pointer to action specification.
877 * Pointer to rte_flow_item objects list.
879 * Pointer to flow attributes structure.
880 * @param[in] dev_flow
881 * Pointer to the sub flow.
882 * @param[in] tunnel_decap
883 * Whether action is after tunnel decapsulation.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_dec_ttl
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_item *items,
894 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
895 bool tunnel_decap, struct rte_flow_error *error)
897 struct rte_flow_item item;
898 struct rte_flow_item_ipv4 ipv4;
899 struct rte_flow_item_ipv4 ipv4_mask;
900 struct rte_flow_item_ipv6 ipv6;
901 struct rte_flow_item_ipv6 ipv6_mask;
902 struct field_modify_info *field;
905 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
907 memset(&ipv4, 0, sizeof(ipv4));
908 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
909 ipv4.hdr.time_to_live = 0xFF;
910 ipv4_mask.hdr.time_to_live = 0xFF;
911 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
913 item.mask = &ipv4_mask;
916 MLX5_ASSERT(attr->ipv6);
917 memset(&ipv6, 0, sizeof(ipv6));
918 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
919 ipv6.hdr.hop_limits = 0xFF;
920 ipv6_mask.hdr.hop_limits = 0xFF;
921 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
923 item.mask = &ipv6_mask;
926 return flow_dv_convert_modify_action(&item, field, NULL, resource,
927 MLX5_MODIFICATION_TYPE_ADD, error);
931 * Convert modify-header increment/decrement TCP Sequence number
932 * to DV specification.
934 * @param[in,out] resource
935 * Pointer to the modify-header resource.
937 * Pointer to action specification.
939 * Pointer to the error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_convert_action_modify_tcp_seq
946 (struct mlx5_flow_dv_modify_hdr_resource *resource,
947 const struct rte_flow_action *action,
948 struct rte_flow_error *error)
950 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
951 uint64_t value = rte_be_to_cpu_32(*conf);
952 struct rte_flow_item item;
953 struct rte_flow_item_tcp tcp;
954 struct rte_flow_item_tcp tcp_mask;
956 memset(&tcp, 0, sizeof(tcp));
957 memset(&tcp_mask, 0, sizeof(tcp_mask));
958 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
960 * The HW has no decrement operation, only increment operation.
961 * To simulate decrement X from Y using increment operation
962 * we need to add UINT32_MAX X times to Y.
963 * Each adding of UINT32_MAX decrements Y by 1.
966 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
967 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
968 item.type = RTE_FLOW_ITEM_TYPE_TCP;
970 item.mask = &tcp_mask;
971 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
972 MLX5_MODIFICATION_TYPE_ADD, error);
976 * Convert modify-header increment/decrement TCP Acknowledgment number
977 * to DV specification.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_modify_tcp_ack
991 (struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action *action,
993 struct rte_flow_error *error)
995 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
996 uint64_t value = rte_be_to_cpu_32(*conf);
997 struct rte_flow_item item;
998 struct rte_flow_item_tcp tcp;
999 struct rte_flow_item_tcp tcp_mask;
1001 memset(&tcp, 0, sizeof(tcp));
1002 memset(&tcp_mask, 0, sizeof(tcp_mask));
1003 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
1005 * The HW has no decrement operation, only increment operation.
1006 * To simulate decrement X from Y using increment operation
1007 * we need to add UINT32_MAX X times to Y.
1008 * Each adding of UINT32_MAX decrements Y by 1.
1010 value *= UINT32_MAX;
1011 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1012 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1013 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1015 item.mask = &tcp_mask;
1016 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_ADD, error);
1020 static enum mlx5_modification_field reg_to_field[] = {
1021 [REG_NON] = MLX5_MODI_OUT_NONE,
1022 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1023 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1024 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1025 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1026 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1027 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1028 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1029 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1030 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1031 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1035 * Convert register set to DV specification.
1037 * @param[in,out] resource
1038 * Pointer to the modify-header resource.
1040 * Pointer to action specification.
1042 * Pointer to the error structure.
1045 * 0 on success, a negative errno value otherwise and rte_errno is set.
1048 flow_dv_convert_action_set_reg
1049 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1050 const struct rte_flow_action *action,
1051 struct rte_flow_error *error)
1053 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1054 struct mlx5_modification_cmd *actions = resource->actions;
1055 uint32_t i = resource->actions_num;
1057 if (i >= MLX5_MAX_MODIFY_NUM)
1058 return rte_flow_error_set(error, EINVAL,
1059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1060 "too many items to modify");
1061 MLX5_ASSERT(conf->id != REG_NON);
1062 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1063 actions[i] = (struct mlx5_modification_cmd) {
1064 .action_type = MLX5_MODIFICATION_TYPE_SET,
1065 .field = reg_to_field[conf->id],
1066 .offset = conf->offset,
1067 .length = conf->length,
1069 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1070 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1072 resource->actions_num = i;
1077 * Convert SET_TAG action to DV specification.
1080 * Pointer to the rte_eth_dev structure.
1081 * @param[in,out] resource
1082 * Pointer to the modify-header resource.
1084 * Pointer to action specification.
1086 * Pointer to the error structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 flow_dv_convert_action_set_tag
1093 (struct rte_eth_dev *dev,
1094 struct mlx5_flow_dv_modify_hdr_resource *resource,
1095 const struct rte_flow_action_set_tag *conf,
1096 struct rte_flow_error *error)
1098 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1099 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1100 struct rte_flow_item item = {
1104 struct field_modify_info reg_c_x[] = {
1107 enum mlx5_modification_field reg_type;
1110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1113 MLX5_ASSERT(ret != REG_NON);
1114 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1115 reg_type = reg_to_field[ret];
1116 MLX5_ASSERT(reg_type > 0);
1117 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1118 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1119 MLX5_MODIFICATION_TYPE_SET, error);
1123 * Convert internal COPY_REG action to DV specification.
1126 * Pointer to the rte_eth_dev structure.
1127 * @param[in,out] res
1128 * Pointer to the modify-header resource.
1130 * Pointer to action specification.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1139 struct mlx5_flow_dv_modify_hdr_resource *res,
1140 const struct rte_flow_action *action,
1141 struct rte_flow_error *error)
1143 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1144 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_src[] = {
1150 {4, 0, reg_to_field[conf->src]},
1153 struct field_modify_info reg_dst = {
1155 .id = reg_to_field[conf->dst],
1157 /* Adjust reg_c[0] usage according to reported mask. */
1158 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1159 struct mlx5_priv *priv = dev->data->dev_private;
1160 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1162 MLX5_ASSERT(reg_c0);
1163 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1164 if (conf->dst == REG_C_0) {
1165 /* Copy to reg_c[0], within mask only. */
1166 reg_dst.offset = rte_bsf32(reg_c0);
1167 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1170 mask = rte_cpu_to_be_32(reg_c0);
1173 return flow_dv_convert_modify_action(&item,
1174 reg_src, ®_dst, res,
1175 MLX5_MODIFICATION_TYPE_COPY,
1180 * Convert MARK action to DV specification. This routine is used
1181 * in extensive metadata only and requires metadata register to be
1182 * handled. In legacy mode hardware tag resource is engaged.
1185 * Pointer to the rte_eth_dev structure.
1187 * Pointer to MARK action specification.
1188 * @param[in,out] resource
1189 * Pointer to the modify-header resource.
1191 * Pointer to the error structure.
1194 * 0 on success, a negative errno value otherwise and rte_errno is set.
1197 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1198 const struct rte_flow_action_mark *conf,
1199 struct mlx5_flow_dv_modify_hdr_resource *resource,
1200 struct rte_flow_error *error)
1202 struct mlx5_priv *priv = dev->data->dev_private;
1203 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1204 priv->sh->dv_mark_mask);
1205 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1206 struct rte_flow_item item = {
1210 struct field_modify_info reg_c_x[] = {
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1218 NULL, "zero mark action mask");
1219 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1222 MLX5_ASSERT(reg > 0);
1223 if (reg == REG_C_0) {
1224 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1225 uint32_t shl_c0 = rte_bsf32(msk_c0);
1227 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1228 mask = rte_cpu_to_be_32(mask) & msk_c0;
1229 mask = rte_cpu_to_be_32(mask << shl_c0);
1231 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1232 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1233 MLX5_MODIFICATION_TYPE_SET, error);
1237 * Get metadata register index for specified steering domain.
1240 * Pointer to the rte_eth_dev structure.
1242 * Attributes of flow to determine steering domain.
1244 * Pointer to the error structure.
1247 * positive index on success, a negative errno value otherwise
1248 * and rte_errno is set.
1250 static enum modify_reg
1251 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1252 const struct rte_flow_attr *attr,
1253 struct rte_flow_error *error)
1256 mlx5_flow_get_reg_id(dev, attr->transfer ?
1260 MLX5_METADATA_RX, 0, error);
1262 return rte_flow_error_set(error,
1263 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1264 NULL, "unavailable "
1265 "metadata register");
1270 * Convert SET_META action to DV specification.
1273 * Pointer to the rte_eth_dev structure.
1274 * @param[in,out] resource
1275 * Pointer to the modify-header resource.
1277 * Attributes of flow that includes this item.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_set_meta
1288 (struct rte_eth_dev *dev,
1289 struct mlx5_flow_dv_modify_hdr_resource *resource,
1290 const struct rte_flow_attr *attr,
1291 const struct rte_flow_action_set_meta *conf,
1292 struct rte_flow_error *error)
1294 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1295 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1296 struct rte_flow_item item = {
1300 struct field_modify_info reg_c_x[] = {
1303 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1307 MLX5_ASSERT(reg != REG_NON);
1308 if (reg == REG_C_0) {
1309 struct mlx5_priv *priv = dev->data->dev_private;
1310 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1311 uint32_t shl_c0 = rte_bsf32(msk_c0);
1313 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1314 mask = rte_cpu_to_be_32(mask) & msk_c0;
1315 mask = rte_cpu_to_be_32(mask << shl_c0);
1317 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1318 /* The routine expects parameters in memory as big-endian ones. */
1319 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Convert modify-header set IPv4 DSCP action to DV specification.
1326 * @param[in,out] resource
1327 * Pointer to the modify-header resource.
1329 * Pointer to action specification.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_action_modify_ipv4_dscp
1338 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1339 const struct rte_flow_action *action,
1340 struct rte_flow_error *error)
1342 const struct rte_flow_action_set_dscp *conf =
1343 (const struct rte_flow_action_set_dscp *)(action->conf);
1344 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1345 struct rte_flow_item_ipv4 ipv4;
1346 struct rte_flow_item_ipv4 ipv4_mask;
1348 memset(&ipv4, 0, sizeof(ipv4));
1349 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1350 ipv4.hdr.type_of_service = conf->dscp;
1351 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1353 item.mask = &ipv4_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 * Convert modify-header set IPv6 DSCP action to DV specification.
1361 * @param[in,out] resource
1362 * Pointer to the modify-header resource.
1364 * Pointer to action specification.
1366 * Pointer to the error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_convert_action_modify_ipv6_dscp
1373 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1374 const struct rte_flow_action *action,
1375 struct rte_flow_error *error)
1377 const struct rte_flow_action_set_dscp *conf =
1378 (const struct rte_flow_action_set_dscp *)(action->conf);
1379 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1380 struct rte_flow_item_ipv6 ipv6;
1381 struct rte_flow_item_ipv6 ipv6_mask;
1383 memset(&ipv6, 0, sizeof(ipv6));
1384 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1386 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1387 * rdma-core only accept the DSCP bits byte aligned start from
1388 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1389 * bits in IPv6 case as rdma-core requires byte aligned value.
1391 ipv6.hdr.vtc_flow = conf->dscp;
1392 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1394 item.mask = &ipv6_mask;
1395 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1396 MLX5_MODIFICATION_TYPE_SET, error);
1400 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1401 enum rte_flow_field_id field, int inherit,
1402 const struct rte_flow_attr *attr,
1403 struct rte_flow_error *error)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1408 case RTE_FLOW_FIELD_START:
1410 case RTE_FLOW_FIELD_MAC_DST:
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 case RTE_FLOW_FIELD_VLAN_TYPE:
1415 case RTE_FLOW_FIELD_VLAN_ID:
1417 case RTE_FLOW_FIELD_MAC_TYPE:
1419 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 case RTE_FLOW_FIELD_IPV4_TTL:
1423 case RTE_FLOW_FIELD_IPV4_SRC:
1424 case RTE_FLOW_FIELD_IPV4_DST:
1426 case RTE_FLOW_FIELD_IPV6_DSCP:
1428 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1430 case RTE_FLOW_FIELD_IPV6_SRC:
1431 case RTE_FLOW_FIELD_IPV6_DST:
1433 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1434 case RTE_FLOW_FIELD_TCP_PORT_DST:
1436 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1437 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1439 case RTE_FLOW_FIELD_TCP_FLAGS:
1441 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1442 case RTE_FLOW_FIELD_UDP_PORT_DST:
1444 case RTE_FLOW_FIELD_VXLAN_VNI:
1445 case RTE_FLOW_FIELD_GENEVE_VNI:
1447 case RTE_FLOW_FIELD_GTP_TEID:
1448 case RTE_FLOW_FIELD_TAG:
1450 case RTE_FLOW_FIELD_MARK:
1451 return __builtin_popcount(priv->sh->dv_mark_mask);
1452 case RTE_FLOW_FIELD_META:
1453 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1454 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1455 case RTE_FLOW_FIELD_POINTER:
1456 case RTE_FLOW_FIELD_VALUE:
1457 return inherit < 0 ? 0 : inherit;
1465 mlx5_flow_field_id_to_modify_info
1466 (const struct rte_flow_action_modify_data *data,
1467 struct field_modify_info *info, uint32_t *mask,
1468 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1469 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1475 switch (data->field) {
1476 case RTE_FLOW_FIELD_START:
1477 /* not supported yet */
1480 case RTE_FLOW_FIELD_MAC_DST:
1481 off = data->offset > 16 ? data->offset - 16 : 0;
1483 if (data->offset < 16) {
1484 info[idx] = (struct field_modify_info){2, 4,
1485 MLX5_MODI_OUT_DMAC_15_0};
1487 mask[1] = rte_cpu_to_be_16(0xffff >>
1491 mask[1] = RTE_BE16(0xffff);
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DMAC_47_16};
1500 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1501 (32 - width)) << off);
1503 if (data->offset < 16)
1504 info[idx++] = (struct field_modify_info){2, 4,
1505 MLX5_MODI_OUT_DMAC_15_0};
1506 info[idx] = (struct field_modify_info){4, 0,
1507 MLX5_MODI_OUT_DMAC_47_16};
1510 case RTE_FLOW_FIELD_MAC_SRC:
1511 off = data->offset > 16 ? data->offset - 16 : 0;
1513 if (data->offset < 16) {
1514 info[idx] = (struct field_modify_info){2, 4,
1515 MLX5_MODI_OUT_SMAC_15_0};
1517 mask[1] = rte_cpu_to_be_16(0xffff >>
1521 mask[1] = RTE_BE16(0xffff);
1528 info[idx] = (struct field_modify_info){4, 0,
1529 MLX5_MODI_OUT_SMAC_47_16};
1530 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1531 (32 - width)) << off);
1533 if (data->offset < 16)
1534 info[idx++] = (struct field_modify_info){2, 4,
1535 MLX5_MODI_OUT_SMAC_15_0};
1536 info[idx] = (struct field_modify_info){4, 0,
1537 MLX5_MODI_OUT_SMAC_47_16};
1540 case RTE_FLOW_FIELD_VLAN_TYPE:
1541 /* not supported yet */
1543 case RTE_FLOW_FIELD_VLAN_ID:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_FIRST_VID};
1547 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1549 case RTE_FLOW_FIELD_MAC_TYPE:
1550 info[idx] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_ETHERTYPE};
1553 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1555 case RTE_FLOW_FIELD_IPV4_DSCP:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IP_DSCP};
1559 mask[idx] = 0x3f >> (6 - width);
1561 case RTE_FLOW_FIELD_IPV4_TTL:
1562 info[idx] = (struct field_modify_info){1, 0,
1563 MLX5_MODI_OUT_IPV4_TTL};
1565 mask[idx] = 0xff >> (8 - width);
1567 case RTE_FLOW_FIELD_IPV4_SRC:
1568 info[idx] = (struct field_modify_info){4, 0,
1569 MLX5_MODI_OUT_SIPV4};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 case RTE_FLOW_FIELD_IPV4_DST:
1575 info[idx] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_DIPV4};
1578 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1581 case RTE_FLOW_FIELD_IPV6_DSCP:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IP_DSCP};
1585 mask[idx] = 0x3f >> (6 - width);
1587 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1588 info[idx] = (struct field_modify_info){1, 0,
1589 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1591 mask[idx] = 0xff >> (8 - width);
1593 case RTE_FLOW_FIELD_IPV6_SRC:
1595 if (data->offset < 32) {
1596 info[idx] = (struct field_modify_info){4, 12,
1597 MLX5_MODI_OUT_SIPV6_31_0};
1600 rte_cpu_to_be_32(0xffffffff >>
1604 mask[3] = RTE_BE32(0xffffffff);
1611 if (data->offset < 64) {
1612 info[idx] = (struct field_modify_info){4, 8,
1613 MLX5_MODI_OUT_SIPV6_63_32};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[2] = RTE_BE32(0xffffffff);
1627 if (data->offset < 96) {
1628 info[idx] = (struct field_modify_info){4, 4,
1629 MLX5_MODI_OUT_SIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[1] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1645 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1647 if (data->offset < 32)
1648 info[idx++] = (struct field_modify_info){4, 12,
1649 MLX5_MODI_OUT_SIPV6_31_0};
1650 if (data->offset < 64)
1651 info[idx++] = (struct field_modify_info){4, 8,
1652 MLX5_MODI_OUT_SIPV6_63_32};
1653 if (data->offset < 96)
1654 info[idx++] = (struct field_modify_info){4, 4,
1655 MLX5_MODI_OUT_SIPV6_95_64};
1656 if (data->offset < 128)
1657 info[idx++] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_SIPV6_127_96};
1661 case RTE_FLOW_FIELD_IPV6_DST:
1663 if (data->offset < 32) {
1664 info[idx] = (struct field_modify_info){4, 12,
1665 MLX5_MODI_OUT_DIPV6_31_0};
1668 rte_cpu_to_be_32(0xffffffff >>
1672 mask[3] = RTE_BE32(0xffffffff);
1679 if (data->offset < 64) {
1680 info[idx] = (struct field_modify_info){4, 8,
1681 MLX5_MODI_OUT_DIPV6_63_32};
1684 rte_cpu_to_be_32(0xffffffff >>
1688 mask[2] = RTE_BE32(0xffffffff);
1695 if (data->offset < 96) {
1696 info[idx] = (struct field_modify_info){4, 4,
1697 MLX5_MODI_OUT_DIPV6_95_64};
1700 rte_cpu_to_be_32(0xffffffff >>
1704 mask[1] = RTE_BE32(0xffffffff);
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1713 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1715 if (data->offset < 32)
1716 info[idx++] = (struct field_modify_info){4, 12,
1717 MLX5_MODI_OUT_DIPV6_31_0};
1718 if (data->offset < 64)
1719 info[idx++] = (struct field_modify_info){4, 8,
1720 MLX5_MODI_OUT_DIPV6_63_32};
1721 if (data->offset < 96)
1722 info[idx++] = (struct field_modify_info){4, 4,
1723 MLX5_MODI_OUT_DIPV6_95_64};
1724 if (data->offset < 128)
1725 info[idx++] = (struct field_modify_info){4, 0,
1726 MLX5_MODI_OUT_DIPV6_127_96};
1729 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_SPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_PORT_DST:
1736 info[idx] = (struct field_modify_info){2, 0,
1737 MLX5_MODI_OUT_TCP_DPORT};
1739 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1741 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1742 info[idx] = (struct field_modify_info){4, 0,
1743 MLX5_MODI_OUT_TCP_SEQ_NUM};
1745 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1748 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1749 info[idx] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_TCP_ACK_NUM};
1752 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1755 case RTE_FLOW_FIELD_TCP_FLAGS:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_TCP_FLAGS};
1759 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_SPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_UDP_PORT_DST:
1768 info[idx] = (struct field_modify_info){2, 0,
1769 MLX5_MODI_OUT_UDP_DPORT};
1771 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1773 case RTE_FLOW_FIELD_VXLAN_VNI:
1774 /* not supported yet */
1776 case RTE_FLOW_FIELD_GENEVE_VNI:
1777 /* not supported yet*/
1779 case RTE_FLOW_FIELD_GTP_TEID:
1780 info[idx] = (struct field_modify_info){4, 0,
1781 MLX5_MODI_GTP_TEID};
1783 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1786 case RTE_FLOW_FIELD_TAG:
1788 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1789 data->level, error);
1792 MLX5_ASSERT(reg != REG_NON);
1793 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1794 info[idx] = (struct field_modify_info){4, 0,
1798 rte_cpu_to_be_32(0xffffffff >>
1802 case RTE_FLOW_FIELD_MARK:
1804 uint32_t mark_mask = priv->sh->dv_mark_mask;
1805 uint32_t mark_count = __builtin_popcount(mark_mask);
1806 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1810 MLX5_ASSERT(reg != REG_NON);
1811 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1812 info[idx] = (struct field_modify_info){4, 0,
1815 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1816 (mark_count - width)) & mark_mask);
1819 case RTE_FLOW_FIELD_META:
1821 uint32_t meta_mask = priv->sh->dv_meta_mask;
1822 uint32_t meta_count = __builtin_popcount(meta_mask);
1824 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1825 uint32_t shl_c0 = rte_bsf32(msk_c0);
1826 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1829 MLX5_ASSERT(reg != REG_NON);
1830 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1833 info[idx] = (struct field_modify_info){4, 0,
1836 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1837 (meta_count - width)) & meta_mask);
1840 case RTE_FLOW_FIELD_POINTER:
1841 case RTE_FLOW_FIELD_VALUE:
1849 * Convert modify_field action to DV specification.
1852 * Pointer to the rte_eth_dev structure.
1853 * @param[in,out] resource
1854 * Pointer to the modify-header resource.
1856 * Pointer to action specification.
1858 * Attributes of flow that includes this item.
1860 * Pointer to the error structure.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dv_convert_action_modify_field
1867 (struct rte_eth_dev *dev,
1868 struct mlx5_flow_dv_modify_hdr_resource *resource,
1869 const struct rte_flow_action *action,
1870 const struct rte_flow_attr *attr,
1871 struct rte_flow_error *error)
1873 const struct rte_flow_action_modify_field *conf =
1874 (const struct rte_flow_action_modify_field *)(action->conf);
1875 struct rte_flow_item item = {
1879 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1881 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1883 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1887 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1888 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1889 type = MLX5_MODIFICATION_TYPE_SET;
1890 /** For SET fill the destination field (field) first. */
1891 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1892 conf->width, &shift, dev,
1894 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1895 (void *)(uintptr_t)conf->src.pvalue :
1896 (void *)(uintptr_t)&conf->src.value;
1898 type = MLX5_MODIFICATION_TYPE_COPY;
1899 /** For COPY fill the destination field (dcopy) without mask. */
1900 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1901 conf->width, &shift, dev,
1903 /** Then construct the source field (field) with mask. */
1904 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1905 conf->width, &shift,
1909 return flow_dv_convert_modify_action(&item,
1910 field, dcopy, resource, type, error);
1914 * Validate MARK item.
1917 * Pointer to the rte_eth_dev structure.
1919 * Item specification.
1921 * Attributes of flow that includes this item.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1930 const struct rte_flow_item *item,
1931 const struct rte_flow_attr *attr __rte_unused,
1932 struct rte_flow_error *error)
1934 struct mlx5_priv *priv = dev->data->dev_private;
1935 struct mlx5_dev_config *config = &priv->config;
1936 const struct rte_flow_item_mark *spec = item->spec;
1937 const struct rte_flow_item_mark *mask = item->mask;
1938 const struct rte_flow_item_mark nic_mask = {
1939 .id = priv->sh->dv_mark_mask,
1943 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata feature"
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ITEM, item,
1951 "extended metadata register"
1952 " isn't supported");
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965 "data cannot be empty");
1966 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976 "mask cannot be zero");
1978 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979 (const uint8_t *)&nic_mask,
1980 sizeof(struct rte_flow_item_mark),
1981 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988 * Validate META item.
1991 * Pointer to the rte_eth_dev structure.
1993 * Item specification.
1995 * Attributes of flow that includes this item.
1997 * Pointer to error structure.
2000 * 0 on success, a negative errno value otherwise and rte_errno is set.
2003 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2004 const struct rte_flow_item *item,
2005 const struct rte_flow_attr *attr,
2006 struct rte_flow_error *error)
2008 struct mlx5_priv *priv = dev->data->dev_private;
2009 struct mlx5_dev_config *config = &priv->config;
2010 const struct rte_flow_item_meta *spec = item->spec;
2011 const struct rte_flow_item_meta *mask = item->mask;
2012 struct rte_flow_item_meta nic_mask = {
2019 return rte_flow_error_set(error, EINVAL,
2020 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022 "data cannot be empty");
2023 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2024 if (!mlx5_flow_ext_mreg_supported(dev))
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 "extended metadata register"
2028 " isn't supported");
2029 reg = flow_dv_get_metadata_reg(dev, attr, error);
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "unavalable extended metadata register");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 nic_mask.data = priv->sh->dv_meta_mask;
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "extended metadata feature "
2048 "should be enabled when "
2049 "meta item is requested "
2050 "with e-switch mode ");
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "match on metadata for ingress "
2055 "is not supported in legacy "
2059 mask = &rte_flow_item_meta_mask;
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2063 "mask cannot be zero");
2065 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2066 (const uint8_t *)&nic_mask,
2067 sizeof(struct rte_flow_item_meta),
2068 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2073 * Validate TAG item.
2076 * Pointer to the rte_eth_dev structure.
2078 * Item specification.
2080 * Attributes of flow that includes this item.
2082 * Pointer to error structure.
2085 * 0 on success, a negative errno value otherwise and rte_errno is set.
2088 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2089 const struct rte_flow_item *item,
2090 const struct rte_flow_attr *attr __rte_unused,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_item_tag *spec = item->spec;
2094 const struct rte_flow_item_tag *mask = item->mask;
2095 const struct rte_flow_item_tag nic_mask = {
2096 .data = RTE_BE32(UINT32_MAX),
2101 if (!mlx5_flow_ext_mreg_supported(dev))
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM, item,
2104 "extensive metadata register"
2105 " isn't supported");
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2110 "data cannot be empty");
2112 mask = &rte_flow_item_tag_mask;
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2116 "mask cannot be zero");
2118 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2119 (const uint8_t *)&nic_mask,
2120 sizeof(struct rte_flow_item_tag),
2121 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2124 if (mask->index != 0xff)
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2127 "partial mask for tag index"
2128 " is not supported");
2129 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2132 MLX5_ASSERT(ret != REG_NON);
2137 * Validate vport item.
2140 * Pointer to the rte_eth_dev structure.
2142 * Item specification.
2144 * Attributes of flow that includes this item.
2145 * @param[in] item_flags
2146 * Bit-fields that holds the items detected until now.
2148 * Pointer to error structure.
2151 * 0 on success, a negative errno value otherwise and rte_errno is set.
2154 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2155 const struct rte_flow_item *item,
2156 const struct rte_flow_attr *attr,
2157 uint64_t item_flags,
2158 struct rte_flow_error *error)
2160 const struct rte_flow_item_port_id *spec = item->spec;
2161 const struct rte_flow_item_port_id *mask = item->mask;
2162 const struct rte_flow_item_port_id switch_mask = {
2165 struct mlx5_priv *esw_priv;
2166 struct mlx5_priv *dev_priv;
2169 if (!attr->transfer)
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ITEM,
2173 "match on port id is valid only"
2174 " when transfer flag is enabled");
2175 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM, item,
2178 "multiple source ports are not"
2181 mask = &switch_mask;
2182 if (mask->id != 0xffffffff)
2183 return rte_flow_error_set(error, ENOTSUP,
2184 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2186 "no support for partial mask on"
2188 ret = mlx5_flow_item_acceptable
2189 (item, (const uint8_t *)mask,
2190 (const uint8_t *)&rte_flow_item_port_id_mask,
2191 sizeof(struct rte_flow_item_port_id),
2192 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2197 if (spec->id == MLX5_PORT_ESW_MGR)
2199 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2201 return rte_flow_error_set(error, rte_errno,
2202 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2203 "failed to obtain E-Switch info for"
2205 dev_priv = mlx5_dev_to_eswitch_info(dev);
2207 return rte_flow_error_set(error, rte_errno,
2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 "failed to obtain E-Switch info");
2211 if (esw_priv->domain_id != dev_priv->domain_id)
2212 return rte_flow_error_set(error, EINVAL,
2213 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2214 "cannot match on a port from a"
2215 " different E-Switch");
2220 * Validate VLAN item.
2223 * Item specification.
2224 * @param[in] item_flags
2225 * Bit-fields that holds the items detected until now.
2227 * Ethernet device flow is being created on.
2229 * Pointer to error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2236 uint64_t item_flags,
2237 struct rte_eth_dev *dev,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_item_vlan *mask = item->mask;
2241 const struct rte_flow_item_vlan nic_mask = {
2242 .tci = RTE_BE16(UINT16_MAX),
2243 .inner_type = RTE_BE16(UINT16_MAX),
2246 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2248 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2249 MLX5_FLOW_LAYER_INNER_L4) :
2250 (MLX5_FLOW_LAYER_OUTER_L3 |
2251 MLX5_FLOW_LAYER_OUTER_L4);
2252 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2253 MLX5_FLOW_LAYER_OUTER_VLAN;
2255 if (item_flags & vlanm)
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ITEM, item,
2258 "multiple VLAN layers not supported");
2259 else if ((item_flags & l34m) != 0)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ITEM, item,
2262 "VLAN cannot follow L3/L4 layer");
2264 mask = &rte_flow_item_vlan_mask;
2265 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2266 (const uint8_t *)&nic_mask,
2267 sizeof(struct rte_flow_item_vlan),
2268 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2271 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2272 struct mlx5_priv *priv = dev->data->dev_private;
2274 if (priv->vmwa_context) {
2276 * Non-NULL context means we have a virtual machine
2277 * and SR-IOV enabled, we have to create VLAN interface
2278 * to make hypervisor to setup E-Switch vport
2279 * context correctly. We avoid creating the multiple
2280 * VLAN interfaces, so we cannot support VLAN tag mask.
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ITEM,
2285 "VLAN tag mask is not"
2286 " supported in virtual"
2294 * GTP flags are contained in 1 byte of the format:
2295 * -------------------------------------------
2296 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2297 * |-----------------------------------------|
2298 * | value | Version | PT | Res | E | S | PN |
2299 * -------------------------------------------
2301 * Matching is supported only for GTP flags E, S, PN.
2303 #define MLX5_GTP_FLAGS_MASK 0x07
2306 * Validate GTP item.
2309 * Pointer to the rte_eth_dev structure.
2311 * Item specification.
2312 * @param[in] item_flags
2313 * Bit-fields that holds the items detected until now.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2322 const struct rte_flow_item *item,
2323 uint64_t item_flags,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 const struct rte_flow_item_gtp *spec = item->spec;
2328 const struct rte_flow_item_gtp *mask = item->mask;
2329 const struct rte_flow_item_gtp nic_mask = {
2330 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2332 .teid = RTE_BE32(0xffffffff),
2335 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "GTP support is not enabled");
2339 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2340 return rte_flow_error_set(error, ENOTSUP,
2341 RTE_FLOW_ERROR_TYPE_ITEM, item,
2342 "multiple tunnel layers not"
2344 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2345 return rte_flow_error_set(error, EINVAL,
2346 RTE_FLOW_ERROR_TYPE_ITEM, item,
2347 "no outer UDP layer found");
2349 mask = &rte_flow_item_gtp_mask;
2350 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ITEM, item,
2353 "Match is supported for GTP"
2355 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2356 (const uint8_t *)&nic_mask,
2357 sizeof(struct rte_flow_item_gtp),
2358 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2362 * Validate GTP PSC item.
2365 * Item specification.
2366 * @param[in] last_item
2367 * Previous validated item in the pattern items.
2368 * @param[in] gtp_item
2369 * Previous GTP item specification.
2371 * Pointer to flow attributes.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2381 const struct rte_flow_item *gtp_item,
2382 const struct rte_flow_attr *attr,
2383 struct rte_flow_error *error)
2385 const struct rte_flow_item_gtp *gtp_spec;
2386 const struct rte_flow_item_gtp *gtp_mask;
2387 const struct rte_flow_item_gtp_psc *mask;
2388 const struct rte_flow_item_gtp_psc nic_mask = {
2393 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2396 "GTP PSC item must be preceded with GTP item");
2397 gtp_spec = gtp_item->spec;
2398 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2399 /* GTP spec and E flag is requested to match zero. */
2401 (gtp_mask->v_pt_rsv_flags &
2402 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2403 return rte_flow_error_set
2404 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "GTP E flag must be 1 to match GTP PSC");
2406 /* Check the flow is not created in group zero. */
2407 if (!attr->transfer && !attr->group)
2408 return rte_flow_error_set
2409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "GTP PSC is not supported for group 0");
2411 /* GTP spec is here and E flag is requested to match zero. */
2414 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2415 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2416 (const uint8_t *)&nic_mask,
2417 sizeof(struct rte_flow_item_gtp_psc),
2418 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2422 * Validate IPV4 item.
2423 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2424 * add specific validation of fragment_offset field,
2427 * Item specification.
2428 * @param[in] item_flags
2429 * Bit-fields that holds the items detected until now.
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2438 const struct rte_flow_item *item,
2439 uint64_t item_flags, uint64_t last_item,
2440 uint16_t ether_type, struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 const struct rte_flow_item_ipv4 *spec = item->spec;
2445 const struct rte_flow_item_ipv4 *last = item->last;
2446 const struct rte_flow_item_ipv4 *mask = item->mask;
2447 rte_be16_t fragment_offset_spec = 0;
2448 rte_be16_t fragment_offset_last = 0;
2449 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2451 .src_addr = RTE_BE32(0xffffffff),
2452 .dst_addr = RTE_BE32(0xffffffff),
2453 .type_of_service = 0xff,
2454 .fragment_offset = RTE_BE16(0xffff),
2455 .next_proto_id = 0xff,
2456 .time_to_live = 0xff,
2460 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2461 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2462 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2463 priv->config.hca_attr.inner_ipv4_ihl;
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM,
2468 "IPV4 ihl offload not supported");
2469 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2471 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2472 ether_type, &nic_ipv4_mask,
2473 MLX5_ITEM_RANGE_ACCEPTED, error);
2477 fragment_offset_spec = spec->hdr.fragment_offset &
2478 mask->hdr.fragment_offset;
2479 if (!fragment_offset_spec)
2482 * spec and mask are valid, enforce using full mask to make sure the
2483 * complete value is used correctly.
2485 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2486 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2487 return rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2489 item, "must use full mask for"
2490 " fragment_offset");
2492 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2493 * indicating this is 1st fragment of fragmented packet.
2494 * This is not yet supported in MLX5, return appropriate error message.
2496 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2497 return rte_flow_error_set(error, ENOTSUP,
2498 RTE_FLOW_ERROR_TYPE_ITEM, item,
2499 "match on first fragment not "
2501 if (fragment_offset_spec && !last)
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "specified value not supported");
2505 /* spec and last are valid, validate the specified range. */
2506 fragment_offset_last = last->hdr.fragment_offset &
2507 mask->hdr.fragment_offset;
2509 * Match on fragment_offset spec 0x2001 and last 0x3fff
2510 * means MF is 1 and frag-offset is > 0.
2511 * This packet is fragment 2nd and onward, excluding last.
2512 * This is not yet supported in MLX5, return appropriate
2515 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2516 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on fragment_offset spec 0x0001 and last 0x1fff
2523 * means MF is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2535 * Match on fragment_offset spec 0x0001 and last 0x3fff
2536 * means MF and/or frag-offset is not 0.
2537 * This is a fragmented packet.
2538 * Other range values are invalid and rejected.
2540 if (!(fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2544 "specified range not supported");
2549 * Validate IPV6 fragment extension item.
2552 * Item specification.
2553 * @param[in] item_flags
2554 * Bit-fields that holds the items detected until now.
2556 * Pointer to error structure.
2559 * 0 on success, a negative errno value otherwise and rte_errno is set.
2562 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2563 uint64_t item_flags,
2564 struct rte_flow_error *error)
2566 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2567 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2568 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2569 rte_be16_t frag_data_spec = 0;
2570 rte_be16_t frag_data_last = 0;
2571 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2572 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2573 MLX5_FLOW_LAYER_OUTER_L4;
2575 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2577 .next_header = 0xff,
2578 .frag_data = RTE_BE16(0xffff),
2582 if (item_flags & l4m)
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item cannot "
2587 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2588 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM, item,
2591 "ipv6 fragment extension item must "
2592 "follow ipv6 item");
2594 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2595 if (!frag_data_spec)
2598 * spec and mask are valid, enforce using full mask to make sure the
2599 * complete value is used correctly.
2601 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2602 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2605 item, "must use full mask for"
2608 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2609 * This is 1st fragment of fragmented packet.
2611 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ITEM, item,
2614 "match on first fragment not "
2616 if (frag_data_spec && !last)
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ITEM, item,
2619 "specified value not supported");
2620 ret = mlx5_flow_item_acceptable
2621 (item, (const uint8_t *)mask,
2622 (const uint8_t *)&nic_mask,
2623 sizeof(struct rte_flow_item_ipv6_frag_ext),
2624 MLX5_ITEM_RANGE_ACCEPTED, error);
2627 /* spec and last are valid, validate the specified range. */
2628 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2630 * Match on frag_data spec 0x0009 and last 0xfff9
2631 * means M is 1 and frag-offset is > 0.
2632 * This packet is fragment 2nd and onward, excluding last.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2637 RTE_IPV6_EHDR_MF_MASK) &&
2638 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2641 last, "match on following "
2642 "fragments not supported");
2644 * Match on frag_data spec 0x0008 and last 0xfff8
2645 * means M is 0 and frag-offset is > 0.
2646 * This packet is last fragment of fragmented packet.
2647 * This is not yet supported in MLX5, return appropriate
2650 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2651 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2652 return rte_flow_error_set(error, ENOTSUP,
2653 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2654 last, "match on last "
2655 "fragment not supported");
2656 /* Other range values are invalid and rejected. */
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2659 "specified range not supported");
2663 * Validate ASO CT item.
2666 * Pointer to the rte_eth_dev structure.
2668 * Item specification.
2669 * @param[in] item_flags
2670 * Pointer to bit-fields that holds the items detected until now.
2672 * Pointer to error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2679 const struct rte_flow_item *item,
2680 uint64_t *item_flags,
2681 struct rte_flow_error *error)
2683 const struct rte_flow_item_conntrack *spec = item->spec;
2684 const struct rte_flow_item_conntrack *mask = item->mask;
2688 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2691 "Only one CT is supported");
2693 mask = &rte_flow_item_conntrack_mask;
2694 flags = spec->flags & mask->flags;
2695 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2696 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2697 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2698 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2701 "Conflict status bits");
2702 /* State change also needs to be considered. */
2703 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2708 * Validate the pop VLAN action.
2711 * Pointer to the rte_eth_dev structure.
2712 * @param[in] action_flags
2713 * Holds the actions detected until now.
2715 * Pointer to the pop vlan action.
2716 * @param[in] item_flags
2717 * The items found in this flow rule.
2719 * Pointer to flow attributes.
2721 * Pointer to error structure.
2724 * 0 on success, a negative errno value otherwise and rte_errno is set.
2727 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2728 uint64_t action_flags,
2729 const struct rte_flow_action *action,
2730 uint64_t item_flags,
2731 const struct rte_flow_attr *attr,
2732 struct rte_flow_error *error)
2734 const struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_dev_ctx_shared *sh = priv->sh;
2736 bool direction_error = false;
2738 if (!priv->sh->pop_vlan_action)
2739 return rte_flow_error_set(error, ENOTSUP,
2740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2742 "pop vlan action is not supported");
2743 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2744 if (attr->transfer) {
2745 bool fdb_tx = priv->representor_id != UINT16_MAX;
2746 bool is_cx5 = sh->steering_format_version ==
2747 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2749 if (fdb_tx && is_cx5)
2750 direction_error = true;
2751 } else if (attr->egress) {
2752 direction_error = true;
2754 if (direction_error)
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2758 "pop vlan action not supported for egress");
2759 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_ACTION, action,
2762 "no support for multiple VLAN "
2764 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2765 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2766 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2767 return rte_flow_error_set(error, ENOTSUP,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2770 "cannot pop vlan after decap without "
2771 "match on inner vlan in the flow");
2772 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2773 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2774 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2775 return rte_flow_error_set(error, ENOTSUP,
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 "cannot pop vlan without a "
2779 "match on (outer) vlan in the flow");
2780 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION, action,
2783 "wrong action order, port_id should "
2784 "be after pop VLAN action");
2785 if (!attr->transfer && priv->representor)
2786 return rte_flow_error_set(error, ENOTSUP,
2787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2788 "pop vlan action for VF representor "
2789 "not supported on NIC table");
2794 * Get VLAN default info from vlan match info.
2797 * the list of item specifications.
2799 * pointer VLAN info to fill to.
2802 * 0 on success, a negative errno value otherwise and rte_errno is set.
2805 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2806 struct rte_vlan_hdr *vlan)
2808 const struct rte_flow_item_vlan nic_mask = {
2809 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2810 MLX5DV_FLOW_VLAN_VID_MASK),
2811 .inner_type = RTE_BE16(0xffff),
2816 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2817 int type = items->type;
2819 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2820 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2823 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2824 const struct rte_flow_item_vlan *vlan_m = items->mask;
2825 const struct rte_flow_item_vlan *vlan_v = items->spec;
2827 /* If VLAN item in pattern doesn't contain data, return here. */
2832 /* Only full match values are accepted */
2833 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2834 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2835 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2837 rte_be_to_cpu_16(vlan_v->tci &
2838 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2840 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2841 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2842 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2844 rte_be_to_cpu_16(vlan_v->tci &
2845 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2847 if (vlan_m->inner_type == nic_mask.inner_type)
2848 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2849 vlan_m->inner_type);
2854 * Validate the push VLAN action.
2857 * Pointer to the rte_eth_dev structure.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] item_flags
2861 * The items found in this flow rule.
2863 * Pointer to the action structure.
2865 * Pointer to flow attributes
2867 * Pointer to error structure.
2870 * 0 on success, a negative errno value otherwise and rte_errno is set.
2873 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2874 uint64_t action_flags,
2875 const struct rte_flow_item_vlan *vlan_m,
2876 const struct rte_flow_action *action,
2877 const struct rte_flow_attr *attr,
2878 struct rte_flow_error *error)
2880 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2881 const struct mlx5_priv *priv = dev->data->dev_private;
2882 struct mlx5_dev_ctx_shared *sh = priv->sh;
2883 bool direction_error = false;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2896 if (attr->transfer) {
2897 bool fdb_tx = priv->representor_id != UINT16_MAX;
2898 bool is_cx5 = sh->steering_format_version ==
2899 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2901 if (!fdb_tx && is_cx5)
2902 direction_error = true;
2903 } else if (attr->ingress) {
2904 direction_error = true;
2906 if (direction_error)
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2910 "push vlan action not supported for ingress");
2911 if (!attr->transfer && priv->representor)
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "push vlan action for VF representor "
2915 "not supported on NIC table");
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2919 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2920 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2921 !(mlx5_flow_find_action
2922 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION, action,
2925 "not full match mask on VLAN PCP and "
2926 "there is no of_set_vlan_pcp action, "
2927 "push VLAN action cannot figure out "
2930 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2931 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2932 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2933 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2934 !(mlx5_flow_find_action
2935 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION, action,
2938 "not full match mask on VLAN VID and "
2939 "there is no of_set_vlan_vid action, "
2940 "push VLAN action cannot figure out "
2947 * Validate the set VLAN PCP.
2949 * @param[in] action_flags
2950 * Holds the actions detected until now.
2951 * @param[in] actions
2952 * Pointer to the list of actions remaining in the flow rule.
2954 * Pointer to error structure.
2957 * 0 on success, a negative errno value otherwise and rte_errno is set.
2960 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2961 const struct rte_flow_action actions[],
2962 struct rte_flow_error *error)
2964 const struct rte_flow_action *action = actions;
2965 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2967 if (conf->vlan_pcp > 7)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "VLAN PCP value is too big");
2971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, action,
2974 "set VLAN PCP action must follow "
2975 "the push VLAN action");
2976 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, action,
2979 "Multiple VLAN PCP modification are "
2981 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2982 return rte_flow_error_set(error, EINVAL,
2983 RTE_FLOW_ERROR_TYPE_ACTION, action,
2984 "wrong action order, port_id should "
2985 "be after set VLAN PCP");
2990 * Validate the set VLAN VID.
2992 * @param[in] item_flags
2993 * Holds the items detected in this rule.
2994 * @param[in] action_flags
2995 * Holds the actions detected until now.
2996 * @param[in] actions
2997 * Pointer to the list of actions remaining in the flow rule.
2999 * Pointer to error structure.
3002 * 0 on success, a negative errno value otherwise and rte_errno is set.
3005 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3006 uint64_t action_flags,
3007 const struct rte_flow_action actions[],
3008 struct rte_flow_error *error)
3010 const struct rte_flow_action *action = actions;
3011 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3013 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "VLAN VID value is too big");
3017 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3018 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3019 return rte_flow_error_set(error, ENOTSUP,
3020 RTE_FLOW_ERROR_TYPE_ACTION, action,
3021 "set VLAN VID action must follow push"
3022 " VLAN action or match on VLAN item");
3023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3024 return rte_flow_error_set(error, ENOTSUP,
3025 RTE_FLOW_ERROR_TYPE_ACTION, action,
3026 "Multiple VLAN VID modifications are "
3028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION, action,
3031 "wrong action order, port_id should "
3032 "be after set VLAN VID");
3037 * Validate the FLAG action.
3040 * Pointer to the rte_eth_dev structure.
3041 * @param[in] action_flags
3042 * Holds the actions detected until now.
3044 * Pointer to flow attributes
3046 * Pointer to error structure.
3049 * 0 on success, a negative errno value otherwise and rte_errno is set.
3052 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3053 uint64_t action_flags,
3054 const struct rte_flow_attr *attr,
3055 struct rte_flow_error *error)
3057 struct mlx5_priv *priv = dev->data->dev_private;
3058 struct mlx5_dev_config *config = &priv->config;
3061 /* Fall back if no extended metadata register support. */
3062 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3063 return mlx5_flow_validate_action_flag(action_flags, attr,
3065 /* Extensive metadata mode requires registers. */
3066 if (!mlx5_flow_ext_mreg_supported(dev))
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "no metadata registers "
3070 "to support flag action");
3071 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3072 return rte_flow_error_set(error, ENOTSUP,
3073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 "extended metadata register"
3075 " isn't available");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3079 MLX5_ASSERT(ret > 0);
3080 if (action_flags & MLX5_FLOW_ACTION_MARK)
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3083 "can't mark and flag in same flow");
3084 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3088 " actions in same flow");
3093 * Validate MARK action.
3096 * Pointer to the rte_eth_dev structure.
3098 * Pointer to action.
3099 * @param[in] action_flags
3100 * Holds the actions detected until now.
3102 * Pointer to flow attributes
3104 * Pointer to error structure.
3107 * 0 on success, a negative errno value otherwise and rte_errno is set.
3110 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3111 const struct rte_flow_action *action,
3112 uint64_t action_flags,
3113 const struct rte_flow_attr *attr,
3114 struct rte_flow_error *error)
3116 struct mlx5_priv *priv = dev->data->dev_private;
3117 struct mlx5_dev_config *config = &priv->config;
3118 const struct rte_flow_action_mark *mark = action->conf;
3121 if (is_tunnel_offload_active(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "if tunnel offload active");
3126 /* Fall back if no extended metadata register support. */
3127 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3128 return mlx5_flow_validate_action_mark(action, action_flags,
3130 /* Extensive metadata mode requires registers. */
3131 if (!mlx5_flow_ext_mreg_supported(dev))
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3134 "no metadata registers "
3135 "to support mark action");
3136 if (!priv->sh->dv_mark_mask)
3137 return rte_flow_error_set(error, ENOTSUP,
3138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3139 "extended metadata register"
3140 " isn't available");
3141 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3144 MLX5_ASSERT(ret > 0);
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, action,
3148 "configuration cannot be null");
3149 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3153 "mark id exceeds the limit");
3154 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can't flag and mark in same flow");
3158 if (action_flags & MLX5_FLOW_ACTION_MARK)
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "can't have 2 mark actions in same"
3167 * Validate SET_META action.
3170 * Pointer to the rte_eth_dev structure.
3172 * Pointer to the action structure.
3173 * @param[in] action_flags
3174 * Holds the actions detected until now.
3176 * Pointer to flow attributes
3178 * Pointer to error structure.
3181 * 0 on success, a negative errno value otherwise and rte_errno is set.
3184 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3185 const struct rte_flow_action *action,
3186 uint64_t action_flags __rte_unused,
3187 const struct rte_flow_attr *attr,
3188 struct rte_flow_error *error)
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_dev_config *config = &priv->config;
3192 const struct rte_flow_action_set_meta *conf;
3193 uint32_t nic_mask = UINT32_MAX;
3196 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3197 !mlx5_flow_ext_mreg_supported(dev))
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, action,
3200 "extended metadata register"
3201 " isn't supported");
3202 reg = flow_dv_get_metadata_reg(dev, attr, error);
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "unavalable extended metadata register");
3209 if (reg != REG_A && reg != REG_B) {
3210 struct mlx5_priv *priv = dev->data->dev_private;
3212 nic_mask = priv->sh->dv_meta_mask;
3214 if (!(action->conf))
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, action,
3217 "configuration cannot be null");
3218 conf = (const struct rte_flow_action_set_meta *)action->conf;
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, action,
3222 "zero mask doesn't have any effect");
3223 if (conf->mask & ~nic_mask)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, action,
3226 "meta data must be within reg C0");
3231 * Validate SET_TAG action.
3234 * Pointer to the rte_eth_dev structure.
3236 * Pointer to the action structure.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to flow attributes
3242 * Pointer to error structure.
3245 * 0 on success, a negative errno value otherwise and rte_errno is set.
3248 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3249 const struct rte_flow_action *action,
3250 uint64_t action_flags,
3251 const struct rte_flow_attr *attr,
3252 struct rte_flow_error *error)
3254 const struct rte_flow_action_set_tag *conf;
3255 const uint64_t terminal_action_flags =
3256 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3257 MLX5_FLOW_ACTION_RSS;
3260 if (!mlx5_flow_ext_mreg_supported(dev))
3261 return rte_flow_error_set(error, ENOTSUP,
3262 RTE_FLOW_ERROR_TYPE_ACTION, action,
3263 "extensive metadata register"
3264 " isn't supported");
3265 if (!(action->conf))
3266 return rte_flow_error_set(error, EINVAL,
3267 RTE_FLOW_ERROR_TYPE_ACTION, action,
3268 "configuration cannot be null");
3269 conf = (const struct rte_flow_action_set_tag *)action->conf;
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION, action,
3273 "zero mask doesn't have any effect");
3274 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3277 if (!attr->transfer && attr->ingress &&
3278 (action_flags & terminal_action_flags))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, action,
3281 "set_tag has no effect"
3282 " with terminal actions");
3287 * Validate count action.
3290 * Pointer to rte_eth_dev structure.
3292 * Indicator if action is shared.
3293 * @param[in] action_flags
3294 * Holds the actions detected until now.
3296 * Pointer to error structure.
3299 * 0 on success, a negative errno value otherwise and rte_errno is set.
3302 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3303 uint64_t action_flags,
3304 struct rte_flow_error *error)
3306 struct mlx5_priv *priv = dev->data->dev_private;
3308 if (!priv->sh->devx)
3310 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313 "duplicate count actions set");
3314 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3315 !priv->sh->flow_hit_aso_en)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3318 "old age and shared count combination is not supported");
3319 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3323 return rte_flow_error_set
3325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3327 "count action not supported");
3331 * Validate the L2 encap action.
3334 * Pointer to the rte_eth_dev structure.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the action structure.
3340 * Pointer to flow attributes.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3349 uint64_t action_flags,
3350 const struct rte_flow_action *action,
3351 const struct rte_flow_attr *attr,
3352 struct rte_flow_error *error)
3354 const struct mlx5_priv *priv = dev->data->dev_private;
3356 if (!(action->conf))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION, action,
3359 "configuration cannot be null");
3360 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3363 "can only have a single encap action "
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set(error, ENOTSUP,
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3374 * Validate a decap action.
3377 * Pointer to the rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Holds the actions detected until now.
3381 * Pointer to the action structure.
3382 * @param[in] item_flags
3383 * Holds the items detected.
3385 * Pointer to flow attributes
3387 * Pointer to error structure.
3390 * 0 on success, a negative errno value otherwise and rte_errno is set.
3393 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3394 uint64_t action_flags,
3395 const struct rte_flow_action *action,
3396 const uint64_t item_flags,
3397 const struct rte_flow_attr *attr,
3398 struct rte_flow_error *error)
3400 const struct mlx5_priv *priv = dev->data->dev_private;
3402 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3403 !priv->config.decap_en)
3404 return rte_flow_error_set(error, ENOTSUP,
3405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3406 "decap is not enabled");
3407 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3411 MLX5_FLOW_ACTION_DECAP ? "can only "
3412 "have a single decap action" : "decap "
3413 "after encap is not supported");
3414 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3417 "can't have decap action after"
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3423 "decap action not supported for "
3425 if (!attr->transfer && priv->representor)
3426 return rte_flow_error_set(error, ENOTSUP,
3427 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3428 "decap action for VF representor "
3429 "not supported on NIC table");
3430 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3431 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3432 return rte_flow_error_set(error, ENOTSUP,
3433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3434 "VXLAN item should be present for VXLAN decap");
3438 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3441 * Validate the raw encap and decap actions.
3444 * Pointer to the rte_eth_dev structure.
3446 * Pointer to the decap action.
3448 * Pointer to the encap action.
3450 * Pointer to flow attributes
3451 * @param[in/out] action_flags
3452 * Holds the actions detected until now.
3453 * @param[out] actions_n
3454 * pointer to the number of actions counter.
3456 * Pointer to the action structure.
3457 * @param[in] item_flags
3458 * Holds the items detected.
3460 * Pointer to error structure.
3463 * 0 on success, a negative errno value otherwise and rte_errno is set.
3466 flow_dv_validate_action_raw_encap_decap
3467 (struct rte_eth_dev *dev,
3468 const struct rte_flow_action_raw_decap *decap,
3469 const struct rte_flow_action_raw_encap *encap,
3470 const struct rte_flow_attr *attr, uint64_t *action_flags,
3471 int *actions_n, const struct rte_flow_action *action,
3472 uint64_t item_flags, struct rte_flow_error *error)
3474 const struct mlx5_priv *priv = dev->data->dev_private;
3477 if (encap && (!encap->size || !encap->data))
3478 return rte_flow_error_set(error, EINVAL,
3479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3480 "raw encap data cannot be empty");
3481 if (decap && encap) {
3482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3486 else if (encap->size <=
3487 MLX5_ENCAPSULATION_DECISION_SIZE &&
3489 MLX5_ENCAPSULATION_DECISION_SIZE)
3492 else if (encap->size >
3493 MLX5_ENCAPSULATION_DECISION_SIZE &&
3495 MLX5_ENCAPSULATION_DECISION_SIZE)
3496 /* 2 L2 actions: encap and decap. */
3499 return rte_flow_error_set(error,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "unsupported too small "
3503 "raw decap and too small raw "
3504 "encap combination");
3507 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3508 item_flags, attr, error);
3511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3516 return rte_flow_error_set(error, ENOTSUP,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3519 "small raw encap size");
3520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3521 return rte_flow_error_set(error, EINVAL,
3522 RTE_FLOW_ERROR_TYPE_ACTION,
3524 "more than one encap action");
3525 if (!attr->transfer && priv->representor)
3526 return rte_flow_error_set
3528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3529 "encap action for VF representor "
3530 "not supported on NIC table");
3531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3538 * Validate the ASO CT action.
3541 * Pointer to the rte_eth_dev structure.
3542 * @param[in] action_flags
3543 * Holds the actions detected until now.
3544 * @param[in] item_flags
3545 * The items found in this flow rule.
3547 * Pointer to flow attributes.
3549 * Pointer to error structure.
3552 * 0 on success, a negative errno value otherwise and rte_errno is set.
3555 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3556 uint64_t action_flags,
3557 uint64_t item_flags,
3558 const struct rte_flow_attr *attr,
3559 struct rte_flow_error *error)
3563 if (attr->group == 0 && !attr->transfer)
3564 return rte_flow_error_set(error, ENOTSUP,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3567 "Only support non-root table");
3568 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3571 "CT cannot follow a fate action");
3572 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3573 (action_flags & MLX5_FLOW_ACTION_AGE))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3576 "Only one ASO action is supported");
3577 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "Encap cannot exist before CT");
3581 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3584 "Not a outer TCP packet");
3589 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3590 struct mlx5_list_entry *entry, void *cb_ctx)
3592 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3593 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3594 struct mlx5_flow_dv_encap_decap_resource *resource;
3596 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3598 if (resource->reformat_type == ctx_resource->reformat_type &&
3599 resource->ft_type == ctx_resource->ft_type &&
3600 resource->flags == ctx_resource->flags &&
3601 resource->size == ctx_resource->size &&
3602 !memcmp((const void *)resource->buf,
3603 (const void *)ctx_resource->buf,
3609 struct mlx5_list_entry *
3610 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3612 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3614 struct mlx5dv_dr_domain *domain;
3615 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3616 struct mlx5_flow_dv_encap_decap_resource *resource;
3620 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 domain = sh->fdb_domain;
3622 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3623 domain = sh->rx_domain;
3625 domain = sh->tx_domain;
3626 /* Register new encap/decap resource. */
3627 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "cannot allocate resource memory");
3634 *resource = *ctx_resource;
3635 resource->idx = idx;
3636 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3640 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3641 rte_flow_error_set(ctx->error, ENOMEM,
3642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3643 NULL, "cannot create action");
3647 return &resource->entry;
3650 struct mlx5_list_entry *
3651 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3656 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3659 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3661 if (!cache_resource) {
3662 rte_flow_error_set(ctx->error, ENOMEM,
3663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3664 "cannot allocate resource memory");
3667 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3668 cache_resource->idx = idx;
3669 return &cache_resource->entry;
3673 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3675 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3676 struct mlx5_flow_dv_encap_decap_resource *res =
3677 container_of(entry, typeof(*res), entry);
3679 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3683 * Find existing encap/decap resource or create and register a new one.
3685 * @param[in, out] dev
3686 * Pointer to rte_eth_dev structure.
3687 * @param[in, out] resource
3688 * Pointer to encap/decap resource.
3689 * @parm[in, out] dev_flow
3690 * Pointer to the dev_flow.
3692 * pointer to error structure.
3695 * 0 on success otherwise -errno and errno is set.
3698 flow_dv_encap_decap_resource_register
3699 (struct rte_eth_dev *dev,
3700 struct mlx5_flow_dv_encap_decap_resource *resource,
3701 struct mlx5_flow *dev_flow,
3702 struct rte_flow_error *error)
3704 struct mlx5_priv *priv = dev->data->dev_private;
3705 struct mlx5_dev_ctx_shared *sh = priv->sh;
3706 struct mlx5_list_entry *entry;
3710 uint32_t refmt_type:8;
3712 * Header reformat actions can be shared between
3713 * non-root tables. One bit to indicate non-root
3717 uint32_t reserve:15;
3720 } encap_decap_key = {
3722 .ft_type = resource->ft_type,
3723 .refmt_type = resource->reformat_type,
3724 .is_root = !!dev_flow->dv.group,
3728 struct mlx5_flow_cb_ctx ctx = {
3732 struct mlx5_hlist *encaps_decaps;
3735 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3737 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3739 flow_dv_encap_decap_create_cb,
3740 flow_dv_encap_decap_match_cb,
3741 flow_dv_encap_decap_remove_cb,
3742 flow_dv_encap_decap_clone_cb,
3743 flow_dv_encap_decap_clone_free_cb);
3744 if (unlikely(!encaps_decaps))
3746 resource->flags = dev_flow->dv.group ? 0 : 1;
3747 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3748 sizeof(encap_decap_key.v32), 0);
3749 if (resource->reformat_type !=
3750 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3752 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3753 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3756 resource = container_of(entry, typeof(*resource), entry);
3757 dev_flow->dv.encap_decap = resource;
3758 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3763 * Find existing table jump resource or create and register a new one.
3765 * @param[in, out] dev
3766 * Pointer to rte_eth_dev structure.
3767 * @param[in, out] tbl
3768 * Pointer to flow table resource.
3769 * @parm[in, out] dev_flow
3770 * Pointer to the dev_flow.
3772 * pointer to error structure.
3775 * 0 on success otherwise -errno and errno is set.
3778 flow_dv_jump_tbl_resource_register
3779 (struct rte_eth_dev *dev __rte_unused,
3780 struct mlx5_flow_tbl_resource *tbl,
3781 struct mlx5_flow *dev_flow,
3782 struct rte_flow_error *error __rte_unused)
3784 struct mlx5_flow_tbl_data_entry *tbl_data =
3785 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3788 MLX5_ASSERT(tbl_data->jump.action);
3789 dev_flow->handle->rix_jump = tbl_data->idx;
3790 dev_flow->dv.jump = &tbl_data->jump;
3795 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3796 struct mlx5_list_entry *entry, void *cb_ctx)
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *res =
3801 container_of(entry, typeof(*res), entry);
3803 return ref->port_id != res->port_id;
3806 struct mlx5_list_entry *
3807 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3809 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3810 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3811 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3812 struct mlx5_flow_dv_port_id_action_resource *resource;
3816 /* Register new port id action resource. */
3817 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3819 rte_flow_error_set(ctx->error, ENOMEM,
3820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3821 "cannot allocate port_id action memory");
3825 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3829 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3830 rte_flow_error_set(ctx->error, ENOMEM,
3831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3832 "cannot create action");
3835 resource->idx = idx;
3836 return &resource->entry;
3839 struct mlx5_list_entry *
3840 flow_dv_port_id_clone_cb(void *tool_ctx,
3841 struct mlx5_list_entry *entry __rte_unused,
3844 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *resource;
3849 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3851 rte_flow_error_set(ctx->error, ENOMEM,
3852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853 "cannot allocate port_id action memory");
3856 memcpy(resource, entry, sizeof(*resource));
3857 resource->idx = idx;
3858 return &resource->entry;
3862 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3864 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3865 struct mlx5_flow_dv_port_id_action_resource *resource =
3866 container_of(entry, typeof(*resource), entry);
3868 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3872 * Find existing table port ID resource or create and register a new one.
3874 * @param[in, out] dev
3875 * Pointer to rte_eth_dev structure.
3876 * @param[in, out] ref
3877 * Pointer to port ID action resource reference.
3878 * @parm[in, out] dev_flow
3879 * Pointer to the dev_flow.
3881 * pointer to error structure.
3884 * 0 on success otherwise -errno and errno is set.
3887 flow_dv_port_id_action_resource_register
3888 (struct rte_eth_dev *dev,
3889 struct mlx5_flow_dv_port_id_action_resource *ref,
3890 struct mlx5_flow *dev_flow,
3891 struct rte_flow_error *error)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_list_entry *entry;
3895 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 struct mlx5_flow_cb_ctx ctx = {
3901 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3904 resource = container_of(entry, typeof(*resource), entry);
3905 dev_flow->dv.port_id_action = resource;
3906 dev_flow->handle->rix_port_id_action = resource->idx;
3911 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3912 struct mlx5_list_entry *entry, void *cb_ctx)
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *res =
3917 container_of(entry, typeof(*res), entry);
3919 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3922 struct mlx5_list_entry *
3923 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3925 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3927 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3928 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3929 struct mlx5dv_dr_domain *domain;
3933 /* Register new port id action resource. */
3934 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3936 rte_flow_error_set(ctx->error, ENOMEM,
3937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3938 "cannot allocate push_vlan action memory");
3942 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3943 domain = sh->fdb_domain;
3944 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3945 domain = sh->rx_domain;
3947 domain = sh->tx_domain;
3948 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3951 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3952 rte_flow_error_set(ctx->error, ENOMEM,
3953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3954 "cannot create push vlan action");
3957 resource->idx = idx;
3958 return &resource->entry;
3961 struct mlx5_list_entry *
3962 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3963 struct mlx5_list_entry *entry __rte_unused,
3966 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3967 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3968 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3971 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3973 rte_flow_error_set(ctx->error, ENOMEM,
3974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3975 "cannot allocate push_vlan action memory");
3978 memcpy(resource, entry, sizeof(*resource));
3979 resource->idx = idx;
3980 return &resource->entry;
3984 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3986 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3987 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3988 container_of(entry, typeof(*resource), entry);
3990 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3994 * Find existing push vlan resource or create and register a new one.
3996 * @param [in, out] dev
3997 * Pointer to rte_eth_dev structure.
3998 * @param[in, out] ref
3999 * Pointer to port ID action resource reference.
4000 * @parm[in, out] dev_flow
4001 * Pointer to the dev_flow.
4003 * pointer to error structure.
4006 * 0 on success otherwise -errno and errno is set.
4009 flow_dv_push_vlan_action_resource_register
4010 (struct rte_eth_dev *dev,
4011 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4012 struct mlx5_flow *dev_flow,
4013 struct rte_flow_error *error)
4015 struct mlx5_priv *priv = dev->data->dev_private;
4016 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4017 struct mlx5_list_entry *entry;
4018 struct mlx5_flow_cb_ctx ctx = {
4023 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4026 resource = container_of(entry, typeof(*resource), entry);
4028 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4029 dev_flow->dv.push_vlan_res = resource;
4034 * Get the size of specific rte_flow_item_type hdr size
4036 * @param[in] item_type
4037 * Tested rte_flow_item_type.
4040 * sizeof struct item_type, 0 if void or irrelevant.
4043 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4047 switch (item_type) {
4048 case RTE_FLOW_ITEM_TYPE_ETH:
4049 retval = sizeof(struct rte_ether_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VLAN:
4052 retval = sizeof(struct rte_vlan_hdr);
4054 case RTE_FLOW_ITEM_TYPE_IPV4:
4055 retval = sizeof(struct rte_ipv4_hdr);
4057 case RTE_FLOW_ITEM_TYPE_IPV6:
4058 retval = sizeof(struct rte_ipv6_hdr);
4060 case RTE_FLOW_ITEM_TYPE_UDP:
4061 retval = sizeof(struct rte_udp_hdr);
4063 case RTE_FLOW_ITEM_TYPE_TCP:
4064 retval = sizeof(struct rte_tcp_hdr);
4066 case RTE_FLOW_ITEM_TYPE_VXLAN:
4067 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4068 retval = sizeof(struct rte_vxlan_hdr);
4070 case RTE_FLOW_ITEM_TYPE_GRE:
4071 case RTE_FLOW_ITEM_TYPE_NVGRE:
4072 retval = sizeof(struct rte_gre_hdr);
4074 case RTE_FLOW_ITEM_TYPE_MPLS:
4075 retval = sizeof(struct rte_mpls_hdr);
4077 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4085 #define MLX5_ENCAP_IPV4_VERSION 0x40
4086 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4087 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4088 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4089 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4090 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4091 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4094 * Convert the encap action data from list of rte_flow_item to raw buffer
4097 * Pointer to rte_flow_item objects list.
4099 * Pointer to the output buffer.
4101 * Pointer to the output buffer size.
4103 * Pointer to the error structure.
4106 * 0 on success, a negative errno value otherwise and rte_errno is set.
4109 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4110 size_t *size, struct rte_flow_error *error)
4112 struct rte_ether_hdr *eth = NULL;
4113 struct rte_vlan_hdr *vlan = NULL;
4114 struct rte_ipv4_hdr *ipv4 = NULL;
4115 struct rte_ipv6_hdr *ipv6 = NULL;
4116 struct rte_udp_hdr *udp = NULL;
4117 struct rte_vxlan_hdr *vxlan = NULL;
4118 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4119 struct rte_gre_hdr *gre = NULL;
4121 size_t temp_size = 0;
4124 return rte_flow_error_set(error, EINVAL,
4125 RTE_FLOW_ERROR_TYPE_ACTION,
4126 NULL, "invalid empty data");
4127 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4128 len = flow_dv_get_item_hdr_len(items->type);
4129 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION,
4132 (void *)items->type,
4133 "items total size is too big"
4134 " for encap action");
4135 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4136 switch (items->type) {
4137 case RTE_FLOW_ITEM_TYPE_ETH:
4138 eth = (struct rte_ether_hdr *)&buf[temp_size];
4140 case RTE_FLOW_ITEM_TYPE_VLAN:
4141 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4143 return rte_flow_error_set(error, EINVAL,
4144 RTE_FLOW_ERROR_TYPE_ACTION,
4145 (void *)items->type,
4146 "eth header not found");
4147 if (!eth->ether_type)
4148 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4150 case RTE_FLOW_ITEM_TYPE_IPV4:
4151 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4153 return rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ACTION,
4155 (void *)items->type,
4156 "neither eth nor vlan"
4158 if (vlan && !vlan->eth_proto)
4159 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4160 else if (eth && !eth->ether_type)
4161 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4162 if (!ipv4->version_ihl)
4163 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4164 MLX5_ENCAP_IPV4_IHL_MIN;
4165 if (!ipv4->time_to_live)
4166 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4168 case RTE_FLOW_ITEM_TYPE_IPV6:
4169 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 (void *)items->type,
4174 "neither eth nor vlan"
4176 if (vlan && !vlan->eth_proto)
4177 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4178 else if (eth && !eth->ether_type)
4179 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4180 if (!ipv6->vtc_flow)
4182 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4183 if (!ipv6->hop_limits)
4184 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4186 case RTE_FLOW_ITEM_TYPE_UDP:
4187 udp = (struct rte_udp_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "ip header not found");
4193 if (ipv4 && !ipv4->next_proto_id)
4194 ipv4->next_proto_id = IPPROTO_UDP;
4195 else if (ipv6 && !ipv6->proto)
4196 ipv6->proto = IPPROTO_UDP;
4198 case RTE_FLOW_ITEM_TYPE_VXLAN:
4199 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION,
4203 (void *)items->type,
4204 "udp header not found");
4206 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4207 if (!vxlan->vx_flags)
4209 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4211 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4212 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4214 return rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 (void *)items->type,
4217 "udp header not found");
4218 if (!vxlan_gpe->proto)
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4225 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4226 if (!vxlan_gpe->vx_flags)
4227 vxlan_gpe->vx_flags =
4228 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4230 case RTE_FLOW_ITEM_TYPE_GRE:
4231 case RTE_FLOW_ITEM_TYPE_NVGRE:
4232 gre = (struct rte_gre_hdr *)&buf[temp_size];
4234 return rte_flow_error_set(error, EINVAL,
4235 RTE_FLOW_ERROR_TYPE_ACTION,
4236 (void *)items->type,
4237 "next protocol not found");
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "ip header not found");
4243 if (ipv4 && !ipv4->next_proto_id)
4244 ipv4->next_proto_id = IPPROTO_GRE;
4245 else if (ipv6 && !ipv6->proto)
4246 ipv6->proto = IPPROTO_GRE;
4248 case RTE_FLOW_ITEM_TYPE_VOID:
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "unsupported item type");
4264 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4266 struct rte_ether_hdr *eth = NULL;
4267 struct rte_vlan_hdr *vlan = NULL;
4268 struct rte_ipv6_hdr *ipv6 = NULL;
4269 struct rte_udp_hdr *udp = NULL;
4273 eth = (struct rte_ether_hdr *)data;
4274 next_hdr = (char *)(eth + 1);
4275 proto = RTE_BE16(eth->ether_type);
4278 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4279 vlan = (struct rte_vlan_hdr *)next_hdr;
4280 proto = RTE_BE16(vlan->eth_proto);
4281 next_hdr += sizeof(struct rte_vlan_hdr);
4284 /* HW calculates IPv4 csum. no need to proceed */
4285 if (proto == RTE_ETHER_TYPE_IPV4)
4288 /* non IPv4/IPv6 header. not supported */
4289 if (proto != RTE_ETHER_TYPE_IPV6) {
4290 return rte_flow_error_set(error, ENOTSUP,
4291 RTE_FLOW_ERROR_TYPE_ACTION,
4292 NULL, "Cannot offload non IPv4/IPv6");
4295 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4297 /* ignore non UDP */
4298 if (ipv6->proto != IPPROTO_UDP)
4301 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4302 udp->dgram_cksum = 0;
4308 * Convert L2 encap action to DV specification.
4311 * Pointer to rte_eth_dev structure.
4313 * Pointer to action structure.
4314 * @param[in, out] dev_flow
4315 * Pointer to the mlx5_flow.
4316 * @param[in] transfer
4317 * Mark if the flow is E-Switch flow.
4319 * Pointer to the error structure.
4322 * 0 on success, a negative errno value otherwise and rte_errno is set.
4325 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4326 const struct rte_flow_action *action,
4327 struct mlx5_flow *dev_flow,
4329 struct rte_flow_error *error)
4331 const struct rte_flow_item *encap_data;
4332 const struct rte_flow_action_raw_encap *raw_encap_data;
4333 struct mlx5_flow_dv_encap_decap_resource res = {
4335 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4336 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4337 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4340 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4342 (const struct rte_flow_action_raw_encap *)action->conf;
4343 res.size = raw_encap_data->size;
4344 memcpy(res.buf, raw_encap_data->data, res.size);
4346 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4348 ((const struct rte_flow_action_vxlan_encap *)
4349 action->conf)->definition;
4352 ((const struct rte_flow_action_nvgre_encap *)
4353 action->conf)->definition;
4354 if (flow_dv_convert_encap_data(encap_data, res.buf,
4358 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4360 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4361 return rte_flow_error_set(error, EINVAL,
4362 RTE_FLOW_ERROR_TYPE_ACTION,
4363 NULL, "can't create L2 encap action");
4368 * Convert L2 decap action to DV specification.
4371 * Pointer to rte_eth_dev structure.
4372 * @param[in, out] dev_flow
4373 * Pointer to the mlx5_flow.
4374 * @param[in] transfer
4375 * Mark if the flow is E-Switch flow.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4384 struct mlx5_flow *dev_flow,
4386 struct rte_flow_error *error)
4388 struct mlx5_flow_dv_encap_decap_resource res = {
4391 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4392 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4393 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4396 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4397 return rte_flow_error_set(error, EINVAL,
4398 RTE_FLOW_ERROR_TYPE_ACTION,
4399 NULL, "can't create L2 decap action");
4404 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4407 * Pointer to rte_eth_dev structure.
4409 * Pointer to action structure.
4410 * @param[in, out] dev_flow
4411 * Pointer to the mlx5_flow.
4413 * Pointer to the flow attributes.
4415 * Pointer to the error structure.
4418 * 0 on success, a negative errno value otherwise and rte_errno is set.
4421 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4422 const struct rte_flow_action *action,
4423 struct mlx5_flow *dev_flow,
4424 const struct rte_flow_attr *attr,
4425 struct rte_flow_error *error)
4427 const struct rte_flow_action_raw_encap *encap_data;
4428 struct mlx5_flow_dv_encap_decap_resource res;
4430 memset(&res, 0, sizeof(res));
4431 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4432 res.size = encap_data->size;
4433 memcpy(res.buf, encap_data->data, res.size);
4434 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4436 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4438 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4440 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4441 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4442 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4443 return rte_flow_error_set(error, EINVAL,
4444 RTE_FLOW_ERROR_TYPE_ACTION,
4445 NULL, "can't create encap action");
4450 * Create action push VLAN.
4453 * Pointer to rte_eth_dev structure.
4455 * Pointer to the flow attributes.
4457 * Pointer to the vlan to push to the Ethernet header.
4458 * @param[in, out] dev_flow
4459 * Pointer to the mlx5_flow.
4461 * Pointer to the error structure.
4464 * 0 on success, a negative errno value otherwise and rte_errno is set.
4467 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4468 const struct rte_flow_attr *attr,
4469 const struct rte_vlan_hdr *vlan,
4470 struct mlx5_flow *dev_flow,
4471 struct rte_flow_error *error)
4473 struct mlx5_flow_dv_push_vlan_action_resource res;
4475 memset(&res, 0, sizeof(res));
4477 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4480 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4482 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4483 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4484 return flow_dv_push_vlan_action_resource_register
4485 (dev, &res, dev_flow, error);
4489 * Validate the modify-header actions.
4491 * @param[in] action_flags
4492 * Holds the actions detected until now.
4494 * Pointer to the modify action.
4496 * Pointer to error structure.
4499 * 0 on success, a negative errno value otherwise and rte_errno is set.
4502 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4503 const struct rte_flow_action *action,
4504 struct rte_flow_error *error)
4506 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4507 return rte_flow_error_set(error, EINVAL,
4508 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4509 NULL, "action configuration not set");
4510 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4513 "can't have encap action before"
4519 * Validate the modify-header MAC address actions.
4521 * @param[in] action_flags
4522 * Holds the actions detected until now.
4524 * Pointer to the modify action.
4525 * @param[in] item_flags
4526 * Holds the items detected.
4528 * Pointer to error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4535 const struct rte_flow_action *action,
4536 const uint64_t item_flags,
4537 struct rte_flow_error *error)
4541 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4543 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4544 return rte_flow_error_set(error, EINVAL,
4545 RTE_FLOW_ERROR_TYPE_ACTION,
4547 "no L2 item in pattern");
4553 * Validate the modify-header IPv4 address actions.
4555 * @param[in] action_flags
4556 * Holds the actions detected until now.
4558 * Pointer to the modify action.
4559 * @param[in] item_flags
4560 * Holds the items detected.
4562 * Pointer to error structure.
4565 * 0 on success, a negative errno value otherwise and rte_errno is set.
4568 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4569 const struct rte_flow_action *action,
4570 const uint64_t item_flags,
4571 struct rte_flow_error *error)
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4579 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4580 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4581 if (!(item_flags & layer))
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no ipv4 item in pattern");
4591 * Validate the modify-header IPv6 address actions.
4593 * @param[in] action_flags
4594 * Holds the actions detected until now.
4596 * Pointer to the modify action.
4597 * @param[in] item_flags
4598 * Holds the items detected.
4600 * Pointer to error structure.
4603 * 0 on success, a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4607 const struct rte_flow_action *action,
4608 const uint64_t item_flags,
4609 struct rte_flow_error *error)
4614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4616 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4617 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4618 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4619 if (!(item_flags & layer))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "no ipv6 item in pattern");
4629 * Validate the modify-header TP actions.
4631 * @param[in] action_flags
4632 * Holds the actions detected until now.
4634 * Pointer to the modify action.
4635 * @param[in] item_flags
4636 * Holds the items detected.
4638 * Pointer to error structure.
4641 * 0 on success, a negative errno value otherwise and rte_errno is set.
4644 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4645 const struct rte_flow_action *action,
4646 const uint64_t item_flags,
4647 struct rte_flow_error *error)
4652 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4654 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4655 MLX5_FLOW_LAYER_INNER_L4 :
4656 MLX5_FLOW_LAYER_OUTER_L4;
4657 if (!(item_flags & layer))
4658 return rte_flow_error_set(error, EINVAL,
4659 RTE_FLOW_ERROR_TYPE_ACTION,
4660 NULL, "no transport layer "
4667 * Validate the modify-header actions of increment/decrement
4668 * TCP Sequence-number.
4670 * @param[in] action_flags
4671 * Holds the actions detected until now.
4673 * Pointer to the modify action.
4674 * @param[in] item_flags
4675 * Holds the items detected.
4677 * Pointer to error structure.
4680 * 0 on success, a negative errno value otherwise and rte_errno is set.
4683 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4684 const struct rte_flow_action *action,
4685 const uint64_t item_flags,
4686 struct rte_flow_error *error)
4691 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4693 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4694 MLX5_FLOW_LAYER_INNER_L4_TCP :
4695 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 if (!(item_flags & layer))
4697 return rte_flow_error_set(error, EINVAL,
4698 RTE_FLOW_ERROR_TYPE_ACTION,
4699 NULL, "no TCP item in"
4701 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4702 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4703 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4704 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4708 "cannot decrease and increase"
4709 " TCP sequence number"
4710 " at the same time");
4716 * Validate the modify-header actions of increment/decrement
4717 * TCP Acknowledgment number.
4719 * @param[in] action_flags
4720 * Holds the actions detected until now.
4722 * Pointer to the modify action.
4723 * @param[in] item_flags
4724 * Holds the items detected.
4726 * Pointer to error structure.
4729 * 0 on success, a negative errno value otherwise and rte_errno is set.
4732 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4733 const struct rte_flow_action *action,
4734 const uint64_t item_flags,
4735 struct rte_flow_error *error)
4740 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4742 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4743 MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4745 if (!(item_flags & layer))
4746 return rte_flow_error_set(error, EINVAL,
4747 RTE_FLOW_ERROR_TYPE_ACTION,
4748 NULL, "no TCP item in"
4750 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4751 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4752 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4753 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4754 return rte_flow_error_set(error, EINVAL,
4755 RTE_FLOW_ERROR_TYPE_ACTION,
4757 "cannot decrease and increase"
4758 " TCP acknowledgment number"
4759 " at the same time");
4765 * Validate the modify-header TTL actions.
4767 * @param[in] action_flags
4768 * Holds the actions detected until now.
4770 * Pointer to the modify action.
4771 * @param[in] item_flags
4772 * Holds the items detected.
4774 * Pointer to error structure.
4777 * 0 on success, a negative errno value otherwise and rte_errno is set.
4780 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4781 const struct rte_flow_action *action,
4782 const uint64_t item_flags,
4783 struct rte_flow_error *error)
4788 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4790 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4791 MLX5_FLOW_LAYER_INNER_L3 :
4792 MLX5_FLOW_LAYER_OUTER_L3;
4793 if (!(item_flags & layer))
4794 return rte_flow_error_set(error, EINVAL,
4795 RTE_FLOW_ERROR_TYPE_ACTION,
4797 "no IP protocol in pattern");
4803 * Validate the generic modify field actions.
4805 * Pointer to the rte_eth_dev structure.
4806 * @param[in] action_flags
4807 * Holds the actions detected until now.
4809 * Pointer to the modify action.
4811 * Pointer to the flow attributes.
4813 * Pointer to error structure.
4816 * Number of header fields to modify (0 or more) on success,
4817 * a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4821 const uint64_t action_flags,
4822 const struct rte_flow_action *action,
4823 const struct rte_flow_attr *attr,
4824 struct rte_flow_error *error)
4827 struct mlx5_priv *priv = dev->data->dev_private;
4828 struct mlx5_dev_config *config = &priv->config;
4829 const struct rte_flow_action_modify_field *action_modify_field =
4831 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4832 action_modify_field->dst.field,
4834 uint32_t src_width = mlx5_flow_item_field_width(dev,
4835 action_modify_field->src.field,
4836 dst_width, attr, error);
4838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4842 if (action_modify_field->width == 0)
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "no bits are requested to be modified");
4846 else if (action_modify_field->width > dst_width ||
4847 action_modify_field->width > src_width)
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "cannot modify more bits than"
4851 " the width of a field");
4852 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4853 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4854 if ((action_modify_field->dst.offset +
4855 action_modify_field->width > dst_width) ||
4856 (action_modify_field->dst.offset % 32))
4857 return rte_flow_error_set(error, EINVAL,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "destination offset is too big"
4860 " or not aligned to 4 bytes");
4861 if (action_modify_field->dst.level &&
4862 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4863 return rte_flow_error_set(error, ENOTSUP,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "inner header fields modification"
4866 " is not supported");
4868 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4870 if (!attr->transfer && !attr->group)
4871 return rte_flow_error_set(error, ENOTSUP,
4872 RTE_FLOW_ERROR_TYPE_ACTION, action,
4873 "modify field action is not"
4874 " supported for group 0");
4875 if ((action_modify_field->src.offset +
4876 action_modify_field->width > src_width) ||
4877 (action_modify_field->src.offset % 32))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source offset is too big"
4881 " or not aligned to 4 bytes");
4882 if (action_modify_field->src.level &&
4883 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4884 return rte_flow_error_set(error, ENOTSUP,
4885 RTE_FLOW_ERROR_TYPE_ACTION, action,
4886 "inner header fields modification"
4887 " is not supported");
4889 if ((action_modify_field->dst.field ==
4890 action_modify_field->src.field) &&
4891 (action_modify_field->dst.level ==
4892 action_modify_field->src.level))
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "source and destination fields"
4896 " cannot be the same");
4897 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4899 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4900 return rte_flow_error_set(error, EINVAL,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "mark, immediate value or a pointer to it"
4903 " cannot be used as a destination");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of an arbitrary"
4909 " place in a packet is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the 802.1Q Tag"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "modifications of the VXLAN Network"
4921 " Identifier is not supported");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "modifications of the GENEVE Network"
4927 " Identifier is not supported");
4928 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4929 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4930 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4931 !mlx5_flow_ext_mreg_supported(dev))
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify mark in legacy mode"
4935 " or without extensive registers");
4936 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4937 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4938 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4939 !mlx5_flow_ext_mreg_supported(dev))
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "cannot modify meta without"
4943 " extensive registers support");
4944 ret = flow_dv_get_metadata_reg(dev, attr, error);
4945 if (ret < 0 || ret == REG_NON)
4946 return rte_flow_error_set(error, ENOTSUP,
4947 RTE_FLOW_ERROR_TYPE_ACTION, action,
4948 "cannot modify meta without"
4949 " extensive registers available");
4951 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4952 return rte_flow_error_set(error, ENOTSUP,
4953 RTE_FLOW_ERROR_TYPE_ACTION, action,
4954 "add and sub operations"
4955 " are not supported");
4956 return (action_modify_field->width / 32) +
4957 !!(action_modify_field->width % 32);
4961 * Validate jump action.
4964 * Pointer to the jump action.
4965 * @param[in] action_flags
4966 * Holds the actions detected until now.
4967 * @param[in] attributes
4968 * Pointer to flow attributes
4969 * @param[in] external
4970 * Action belongs to flow rule created by request external to PMD.
4972 * Pointer to error structure.
4975 * 0 on success, a negative errno value otherwise and rte_errno is set.
4978 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4979 const struct mlx5_flow_tunnel *tunnel,
4980 const struct rte_flow_action *action,
4981 uint64_t action_flags,
4982 const struct rte_flow_attr *attributes,
4983 bool external, struct rte_flow_error *error)
4985 uint32_t target_group, table;
4987 struct flow_grp_info grp_info = {
4988 .external = !!external,
4989 .transfer = !!attributes->transfer,
4993 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4994 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4995 return rte_flow_error_set(error, EINVAL,
4996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4997 "can't have 2 fate actions in"
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5002 NULL, "action configuration not set");
5004 ((const struct rte_flow_action_jump *)action->conf)->group;
5005 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5009 if (attributes->group == target_group &&
5010 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5011 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "target group must be other than"
5015 " the current flow group");
5020 * Validate action PORT_ID / REPRESENTED_PORT.
5023 * Pointer to rte_eth_dev structure.
5024 * @param[in] action_flags
5025 * Bit-fields that holds the actions detected until now.
5027 * PORT_ID / REPRESENTED_PORT action structure.
5029 * Attributes of flow that includes this action.
5031 * Pointer to error structure.
5034 * 0 on success, a negative errno value otherwise and rte_errno is set.
5037 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5038 uint64_t action_flags,
5039 const struct rte_flow_action *action,
5040 const struct rte_flow_attr *attr,
5041 struct rte_flow_error *error)
5043 const struct rte_flow_action_port_id *port_id;
5044 const struct rte_flow_action_ethdev *ethdev;
5045 struct mlx5_priv *act_priv;
5046 struct mlx5_priv *dev_priv;
5049 if (!attr->transfer)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5053 "port action is valid in transfer"
5055 if (!action || !action->conf)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5059 "port action parameters must be"
5061 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5062 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5063 return rte_flow_error_set(error, EINVAL,
5064 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5065 "can have only one fate actions in"
5067 dev_priv = mlx5_dev_to_eswitch_info(dev);
5069 return rte_flow_error_set(error, rte_errno,
5070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5072 "failed to obtain E-Switch info");
5073 switch (action->type) {
5074 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5075 port_id = action->conf;
5076 port = port_id->original ? dev->data->port_id : port_id->id;
5078 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5079 ethdev = action->conf;
5080 port = ethdev->port_id;
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, action,
5087 "unknown E-Switch action");
5089 act_priv = mlx5_port_to_eswitch_info(port, false);
5091 return rte_flow_error_set
5093 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5094 "failed to obtain E-Switch port id for port");
5095 if (act_priv->domain_id != dev_priv->domain_id)
5096 return rte_flow_error_set
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "port does not belong to"
5100 " E-Switch being configured");
5105 * Get the maximum number of modify header actions.
5108 * Pointer to rte_eth_dev structure.
5110 * Whether action is on root table.
5113 * Max number of modify header actions device can support.
5115 static inline unsigned int
5116 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5120 * There's no way to directly query the max capacity from FW.
5121 * The maximal value on root table should be assumed to be supported.
5124 return MLX5_MAX_MODIFY_NUM;
5126 return MLX5_ROOT_TBL_MODIFY_NUM;
5130 * Validate the meter action.
5133 * Pointer to rte_eth_dev structure.
5134 * @param[in] action_flags
5135 * Bit-fields that holds the actions detected until now.
5137 * Pointer to the meter action.
5139 * Attributes of flow that includes this action.
5140 * @param[in] port_id_item
5141 * Pointer to item indicating port id.
5143 * Pointer to error structure.
5146 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5149 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5150 uint64_t action_flags,
5151 const struct rte_flow_action *action,
5152 const struct rte_flow_attr *attr,
5153 const struct rte_flow_item *port_id_item,
5155 struct rte_flow_error *error)
5157 struct mlx5_priv *priv = dev->data->dev_private;
5158 const struct rte_flow_action_meter *am = action->conf;
5159 struct mlx5_flow_meter_info *fm;
5160 struct mlx5_flow_meter_policy *mtr_policy;
5161 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5164 return rte_flow_error_set(error, EINVAL,
5165 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5166 "meter action conf is NULL");
5168 if (action_flags & MLX5_FLOW_ACTION_METER)
5169 return rte_flow_error_set(error, ENOTSUP,
5170 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5171 "meter chaining not support");
5172 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5173 return rte_flow_error_set(error, ENOTSUP,
5174 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5175 "meter with jump not support");
5177 return rte_flow_error_set(error, ENOTSUP,
5178 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5180 "meter action not supported");
5181 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5183 return rte_flow_error_set(error, EINVAL,
5184 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5186 /* aso meter can always be shared by different domains */
5187 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5188 !(fm->transfer == attr->transfer ||
5189 (!fm->ingress && !attr->ingress && attr->egress) ||
5190 (!fm->egress && !attr->egress && attr->ingress)))
5191 return rte_flow_error_set(error, EINVAL,
5192 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5193 "Flow attributes domain are either invalid "
5194 "or have a domain conflict with current "
5195 "meter attributes");
5196 if (fm->def_policy) {
5197 if (!((attr->transfer &&
5198 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5200 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5202 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5203 return rte_flow_error_set(error, EINVAL,
5204 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5205 "Flow attributes domain "
5206 "have a conflict with current "
5207 "meter domain attributes");
5210 mtr_policy = mlx5_flow_meter_policy_find(dev,
5211 fm->policy_id, NULL);
5213 return rte_flow_error_set(error, EINVAL,
5214 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5215 "Invalid policy id for meter ");
5216 if (!((attr->transfer && mtr_policy->transfer) ||
5217 (attr->egress && mtr_policy->egress) ||
5218 (attr->ingress && mtr_policy->ingress)))
5219 return rte_flow_error_set(error, EINVAL,
5220 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5221 "Flow attributes domain "
5222 "have a conflict with current "
5223 "meter domain attributes");
5224 if (attr->transfer && mtr_policy->dev) {
5226 * When policy has fate action of port_id,
5227 * the flow should have the same src port as policy.
5229 struct mlx5_priv *policy_port_priv =
5230 mtr_policy->dev->data->dev_private;
5231 int32_t flow_src_port = priv->representor_id;
5234 const struct rte_flow_item_port_id *spec =
5236 struct mlx5_priv *port_priv =
5237 mlx5_port_to_eswitch_info(spec->id,
5240 return rte_flow_error_set(error,
5242 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5244 "Failed to get port info.");
5245 flow_src_port = port_priv->representor_id;
5247 if (flow_src_port != policy_port_priv->representor_id)
5248 return rte_flow_error_set(error,
5250 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5252 "Flow and meter policy "
5253 "have different src port.");
5255 *def_policy = false;
5261 * Validate the age action.
5263 * @param[in] action_flags
5264 * Holds the actions detected until now.
5266 * Pointer to the age action.
5268 * Pointer to the Ethernet device structure.
5270 * Pointer to error structure.
5273 * 0 on success, a negative errno value otherwise and rte_errno is set.
5276 flow_dv_validate_action_age(uint64_t action_flags,
5277 const struct rte_flow_action *action,
5278 struct rte_eth_dev *dev,
5279 struct rte_flow_error *error)
5281 struct mlx5_priv *priv = dev->data->dev_private;
5282 const struct rte_flow_action_age *age = action->conf;
5284 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5285 !priv->sh->aso_age_mng))
5286 return rte_flow_error_set(error, ENOTSUP,
5287 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5289 "age action not supported");
5290 if (!(action->conf))
5291 return rte_flow_error_set(error, EINVAL,
5292 RTE_FLOW_ERROR_TYPE_ACTION, action,
5293 "configuration cannot be null");
5294 if (!(age->timeout))
5295 return rte_flow_error_set(error, EINVAL,
5296 RTE_FLOW_ERROR_TYPE_ACTION, action,
5297 "invalid timeout value 0");
5298 if (action_flags & MLX5_FLOW_ACTION_AGE)
5299 return rte_flow_error_set(error, EINVAL,
5300 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5301 "duplicate age actions set");
5306 * Validate the modify-header IPv4 DSCP actions.
5308 * @param[in] action_flags
5309 * Holds the actions detected until now.
5311 * Pointer to the modify action.
5312 * @param[in] item_flags
5313 * Holds the items detected.
5315 * Pointer to error structure.
5318 * 0 on success, a negative errno value otherwise and rte_errno is set.
5321 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5322 const struct rte_flow_action *action,
5323 const uint64_t item_flags,
5324 struct rte_flow_error *error)
5328 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5330 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5331 return rte_flow_error_set(error, EINVAL,
5332 RTE_FLOW_ERROR_TYPE_ACTION,
5334 "no ipv4 item in pattern");
5340 * Validate the modify-header IPv6 DSCP actions.
5342 * @param[in] action_flags
5343 * Holds the actions detected until now.
5345 * Pointer to the modify action.
5346 * @param[in] item_flags
5347 * Holds the items detected.
5349 * Pointer to error structure.
5352 * 0 on success, a negative errno value otherwise and rte_errno is set.
5355 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5356 const struct rte_flow_action *action,
5357 const uint64_t item_flags,
5358 struct rte_flow_error *error)
5362 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5364 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5365 return rte_flow_error_set(error, EINVAL,
5366 RTE_FLOW_ERROR_TYPE_ACTION,
5368 "no ipv6 item in pattern");
5374 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5375 struct mlx5_list_entry *entry, void *cb_ctx)
5377 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5378 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5379 struct mlx5_flow_dv_modify_hdr_resource *resource =
5380 container_of(entry, typeof(*resource), entry);
5381 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5383 key_len += ref->actions_num * sizeof(ref->actions[0]);
5384 return ref->actions_num != resource->actions_num ||
5385 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5388 static struct mlx5_indexed_pool *
5389 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5391 struct mlx5_indexed_pool *ipool = __atomic_load_n
5392 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5395 struct mlx5_indexed_pool *expected = NULL;
5396 struct mlx5_indexed_pool_config cfg =
5397 (struct mlx5_indexed_pool_config) {
5398 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5400 sizeof(struct mlx5_modification_cmd),
5405 .release_mem_en = !!sh->reclaim_mode,
5406 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5407 .malloc = mlx5_malloc,
5409 .type = "mlx5_modify_action_resource",
5412 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5413 ipool = mlx5_ipool_create(&cfg);
5416 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5417 &expected, ipool, false,
5419 __ATOMIC_SEQ_CST)) {
5420 mlx5_ipool_destroy(ipool);
5421 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5428 struct mlx5_list_entry *
5429 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5431 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5432 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5433 struct mlx5dv_dr_domain *ns;
5434 struct mlx5_flow_dv_modify_hdr_resource *entry;
5435 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5436 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5437 ref->actions_num - 1);
5439 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5440 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5443 if (unlikely(!ipool)) {
5444 rte_flow_error_set(ctx->error, ENOMEM,
5445 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5446 NULL, "cannot allocate modify ipool");
5449 entry = mlx5_ipool_zmalloc(ipool, &idx);
5451 rte_flow_error_set(ctx->error, ENOMEM,
5452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5453 "cannot allocate resource memory");
5456 rte_memcpy(&entry->ft_type,
5457 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5458 key_len + data_len);
5459 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5460 ns = sh->fdb_domain;
5461 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5465 ret = mlx5_flow_os_create_flow_action_modify_header
5466 (sh->cdev->ctx, ns, entry,
5467 data_len, &entry->action);
5469 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5470 rte_flow_error_set(ctx->error, ENOMEM,
5471 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5472 NULL, "cannot create modification action");
5476 return &entry->entry;
5479 struct mlx5_list_entry *
5480 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5483 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5484 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5485 struct mlx5_flow_dv_modify_hdr_resource *entry;
5486 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5487 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5490 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5493 rte_flow_error_set(ctx->error, ENOMEM,
5494 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5495 "cannot allocate resource memory");
5498 memcpy(entry, oentry, sizeof(*entry) + data_len);
5500 return &entry->entry;
5504 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5506 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5507 struct mlx5_flow_dv_modify_hdr_resource *res =
5508 container_of(entry, typeof(*res), entry);
5510 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5514 * Validate the sample action.
5516 * @param[in, out] action_flags
5517 * Holds the actions detected until now.
5519 * Pointer to the sample action.
5521 * Pointer to the Ethernet device structure.
5523 * Attributes of flow that includes this action.
5524 * @param[in] item_flags
5525 * Holds the items detected.
5527 * Pointer to the RSS action.
5528 * @param[out] sample_rss
5529 * Pointer to the RSS action in sample action list.
5531 * Pointer to the COUNT action in sample action list.
5532 * @param[out] fdb_mirror_limit
5533 * Pointer to the FDB mirror limitation flag.
5535 * Pointer to error structure.
5538 * 0 on success, a negative errno value otherwise and rte_errno is set.
5541 flow_dv_validate_action_sample(uint64_t *action_flags,
5542 const struct rte_flow_action *action,
5543 struct rte_eth_dev *dev,
5544 const struct rte_flow_attr *attr,
5545 uint64_t item_flags,
5546 const struct rte_flow_action_rss *rss,
5547 const struct rte_flow_action_rss **sample_rss,
5548 const struct rte_flow_action_count **count,
5549 int *fdb_mirror_limit,
5550 struct rte_flow_error *error)
5552 struct mlx5_priv *priv = dev->data->dev_private;
5553 struct mlx5_dev_config *dev_conf = &priv->config;
5554 const struct rte_flow_action_sample *sample = action->conf;
5555 const struct rte_flow_action *act;
5556 uint64_t sub_action_flags = 0;
5557 uint16_t queue_index = 0xFFFF;
5562 return rte_flow_error_set(error, EINVAL,
5563 RTE_FLOW_ERROR_TYPE_ACTION, action,
5564 "configuration cannot be NULL");
5565 if (sample->ratio == 0)
5566 return rte_flow_error_set(error, EINVAL,
5567 RTE_FLOW_ERROR_TYPE_ACTION, action,
5568 "ratio value starts from 1");
5569 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5570 return rte_flow_error_set(error, ENOTSUP,
5571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5573 "sample action not supported");
5574 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5575 return rte_flow_error_set(error, EINVAL,
5576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5577 "Multiple sample actions not "
5579 if (*action_flags & MLX5_FLOW_ACTION_METER)
5580 return rte_flow_error_set(error, EINVAL,
5581 RTE_FLOW_ERROR_TYPE_ACTION, action,
5582 "wrong action order, meter should "
5583 "be after sample action");
5584 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5585 return rte_flow_error_set(error, EINVAL,
5586 RTE_FLOW_ERROR_TYPE_ACTION, action,
5587 "wrong action order, jump should "
5588 "be after sample action");
5589 if (*action_flags & MLX5_FLOW_ACTION_CT)
5590 return rte_flow_error_set(error, EINVAL,
5591 RTE_FLOW_ERROR_TYPE_ACTION, action,
5592 "Sample after CT not supported");
5593 act = sample->actions;
5594 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5595 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5596 return rte_flow_error_set(error, ENOTSUP,
5597 RTE_FLOW_ERROR_TYPE_ACTION,
5598 act, "too many actions");
5599 switch (act->type) {
5600 case RTE_FLOW_ACTION_TYPE_QUEUE:
5601 ret = mlx5_flow_validate_action_queue(act,
5607 queue_index = ((const struct rte_flow_action_queue *)
5608 (act->conf))->index;
5609 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5612 case RTE_FLOW_ACTION_TYPE_RSS:
5613 *sample_rss = act->conf;
5614 ret = mlx5_flow_validate_action_rss(act,
5621 if (rss && *sample_rss &&
5622 ((*sample_rss)->level != rss->level ||
5623 (*sample_rss)->types != rss->types))
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_ACTION,
5627 "Can't use the different RSS types "
5628 "or level in the same flow");
5629 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5630 queue_index = (*sample_rss)->queue[0];
5631 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5634 case RTE_FLOW_ACTION_TYPE_MARK:
5635 ret = flow_dv_validate_action_mark(dev, act,
5640 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5641 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5642 MLX5_FLOW_ACTION_MARK_EXT;
5644 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5647 case RTE_FLOW_ACTION_TYPE_COUNT:
5648 ret = flow_dv_validate_action_count
5649 (dev, false, *action_flags | sub_action_flags,
5654 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5655 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5658 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5659 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5660 ret = flow_dv_validate_action_port_id(dev,
5667 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5670 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5671 ret = flow_dv_validate_action_raw_encap_decap
5672 (dev, NULL, act->conf, attr, &sub_action_flags,
5673 &actions_n, action, item_flags, error);
5678 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5679 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5680 ret = flow_dv_validate_action_l2_encap(dev,
5686 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5690 return rte_flow_error_set(error, ENOTSUP,
5691 RTE_FLOW_ERROR_TYPE_ACTION,
5693 "Doesn't support optional "
5697 if (attr->ingress && !attr->transfer) {
5698 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5699 MLX5_FLOW_ACTION_RSS)))
5700 return rte_flow_error_set(error, EINVAL,
5701 RTE_FLOW_ERROR_TYPE_ACTION,
5703 "Ingress must has a dest "
5704 "QUEUE for Sample");
5705 } else if (attr->egress && !attr->transfer) {
5706 return rte_flow_error_set(error, ENOTSUP,
5707 RTE_FLOW_ERROR_TYPE_ACTION,
5709 "Sample Only support Ingress "
5711 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5712 MLX5_ASSERT(attr->transfer);
5713 if (sample->ratio > 1)
5714 return rte_flow_error_set(error, ENOTSUP,
5715 RTE_FLOW_ERROR_TYPE_ACTION,
5717 "E-Switch doesn't support "
5718 "any optional action "
5720 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5721 return rte_flow_error_set(error, ENOTSUP,
5722 RTE_FLOW_ERROR_TYPE_ACTION,
5724 "unsupported action QUEUE");
5725 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5726 return rte_flow_error_set(error, ENOTSUP,
5727 RTE_FLOW_ERROR_TYPE_ACTION,
5729 "unsupported action QUEUE");
5730 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5731 return rte_flow_error_set(error, EINVAL,
5732 RTE_FLOW_ERROR_TYPE_ACTION,
5734 "E-Switch must has a dest "
5735 "port for mirroring");
5736 if (!priv->config.hca_attr.reg_c_preserve &&
5737 priv->representor_id != UINT16_MAX)
5738 *fdb_mirror_limit = 1;
5740 /* Continue validation for Xcap actions.*/
5741 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5742 (queue_index == 0xFFFF ||
5743 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5744 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5745 MLX5_FLOW_XCAP_ACTIONS)
5746 return rte_flow_error_set(error, ENOTSUP,
5747 RTE_FLOW_ERROR_TYPE_ACTION,
5748 NULL, "encap and decap "
5749 "combination aren't "
5751 if (!attr->transfer && attr->ingress && (sub_action_flags &
5752 MLX5_FLOW_ACTION_ENCAP))
5753 return rte_flow_error_set(error, ENOTSUP,
5754 RTE_FLOW_ERROR_TYPE_ACTION,
5755 NULL, "encap is not supported"
5756 " for ingress traffic");
5762 * Find existing modify-header resource or create and register a new one.
5764 * @param dev[in, out]
5765 * Pointer to rte_eth_dev structure.
5766 * @param[in, out] resource
5767 * Pointer to modify-header resource.
5768 * @parm[in, out] dev_flow
5769 * Pointer to the dev_flow.
5771 * pointer to error structure.
5774 * 0 on success otherwise -errno and errno is set.
5777 flow_dv_modify_hdr_resource_register
5778 (struct rte_eth_dev *dev,
5779 struct mlx5_flow_dv_modify_hdr_resource *resource,
5780 struct mlx5_flow *dev_flow,
5781 struct rte_flow_error *error)
5783 struct mlx5_priv *priv = dev->data->dev_private;
5784 struct mlx5_dev_ctx_shared *sh = priv->sh;
5785 uint32_t key_len = sizeof(*resource) -
5786 offsetof(typeof(*resource), ft_type) +
5787 resource->actions_num * sizeof(resource->actions[0]);
5788 struct mlx5_list_entry *entry;
5789 struct mlx5_flow_cb_ctx ctx = {
5793 struct mlx5_hlist *modify_cmds;
5796 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5798 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5800 flow_dv_modify_create_cb,
5801 flow_dv_modify_match_cb,
5802 flow_dv_modify_remove_cb,
5803 flow_dv_modify_clone_cb,
5804 flow_dv_modify_clone_free_cb);
5805 if (unlikely(!modify_cmds))
5807 resource->root = !dev_flow->dv.group;
5808 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5810 return rte_flow_error_set(error, EOVERFLOW,
5811 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5812 "too many modify header items");
5813 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5814 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5817 resource = container_of(entry, typeof(*resource), entry);
5818 dev_flow->handle->dvh.modify_hdr = resource;
5823 * Get DV flow counter by index.
5826 * Pointer to the Ethernet device structure.
5828 * mlx5 flow counter index in the container.
5830 * mlx5 flow counter pool in the container.
5833 * Pointer to the counter, NULL otherwise.
5835 static struct mlx5_flow_counter *
5836 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5838 struct mlx5_flow_counter_pool **ppool)
5840 struct mlx5_priv *priv = dev->data->dev_private;
5841 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5842 struct mlx5_flow_counter_pool *pool;
5844 /* Decrease to original index and clear shared bit. */
5845 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5846 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5847 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5851 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5855 * Check the devx counter belongs to the pool.
5858 * Pointer to the counter pool.
5860 * The counter devx ID.
5863 * True if counter belongs to the pool, false otherwise.
5866 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5868 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5869 MLX5_COUNTERS_PER_POOL;
5871 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5877 * Get a pool by devx counter ID.
5880 * Pointer to the counter management.
5882 * The counter devx ID.
5885 * The counter pool pointer if exists, NULL otherwise,
5887 static struct mlx5_flow_counter_pool *
5888 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5891 struct mlx5_flow_counter_pool *pool = NULL;
5893 rte_spinlock_lock(&cmng->pool_update_sl);
5894 /* Check last used pool. */
5895 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5896 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5897 pool = cmng->pools[cmng->last_pool_idx];
5900 /* ID out of range means no suitable pool in the container. */
5901 if (id > cmng->max_id || id < cmng->min_id)
5904 * Find the pool from the end of the container, since mostly counter
5905 * ID is sequence increasing, and the last pool should be the needed
5910 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5912 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5918 rte_spinlock_unlock(&cmng->pool_update_sl);
5923 * Resize a counter container.
5926 * Pointer to the Ethernet device structure.
5929 * 0 on success, otherwise negative errno value and rte_errno is set.
5932 flow_dv_container_resize(struct rte_eth_dev *dev)
5934 struct mlx5_priv *priv = dev->data->dev_private;
5935 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5936 void *old_pools = cmng->pools;
5937 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5938 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5939 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5946 memcpy(pools, old_pools, cmng->n *
5947 sizeof(struct mlx5_flow_counter_pool *));
5949 cmng->pools = pools;
5951 mlx5_free(old_pools);
5956 * Query a devx flow counter.
5959 * Pointer to the Ethernet device structure.
5960 * @param[in] counter
5961 * Index to the flow counter.
5963 * The statistics value of packets.
5965 * The statistics value of bytes.
5968 * 0 on success, otherwise a negative errno value and rte_errno is set.
5971 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5974 struct mlx5_priv *priv = dev->data->dev_private;
5975 struct mlx5_flow_counter_pool *pool = NULL;
5976 struct mlx5_flow_counter *cnt;
5979 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5981 if (priv->sh->cmng.counter_fallback)
5982 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5983 0, pkts, bytes, 0, NULL, NULL, 0);
5984 rte_spinlock_lock(&pool->sl);
5989 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5990 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5991 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5993 rte_spinlock_unlock(&pool->sl);
5998 * Create and initialize a new counter pool.
6001 * Pointer to the Ethernet device structure.
6003 * The devX counter handle.
6005 * Whether the pool is for counter that was allocated for aging.
6006 * @param[in/out] cont_cur
6007 * Pointer to the container pointer, it will be update in pool resize.
6010 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6012 static struct mlx5_flow_counter_pool *
6013 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6016 struct mlx5_priv *priv = dev->data->dev_private;
6017 struct mlx5_flow_counter_pool *pool;
6018 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6019 bool fallback = priv->sh->cmng.counter_fallback;
6020 uint32_t size = sizeof(*pool);
6022 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6023 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6024 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6030 pool->is_aged = !!age;
6031 pool->query_gen = 0;
6032 pool->min_dcs = dcs;
6033 rte_spinlock_init(&pool->sl);
6034 rte_spinlock_init(&pool->csl);
6035 TAILQ_INIT(&pool->counters[0]);
6036 TAILQ_INIT(&pool->counters[1]);
6037 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6038 rte_spinlock_lock(&cmng->pool_update_sl);
6039 pool->index = cmng->n_valid;
6040 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6042 rte_spinlock_unlock(&cmng->pool_update_sl);
6045 cmng->pools[pool->index] = pool;
6047 if (unlikely(fallback)) {
6048 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6050 if (base < cmng->min_id)
6051 cmng->min_id = base;
6052 if (base > cmng->max_id)
6053 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6054 cmng->last_pool_idx = pool->index;
6056 rte_spinlock_unlock(&cmng->pool_update_sl);
6061 * Prepare a new counter and/or a new counter pool.
6064 * Pointer to the Ethernet device structure.
6065 * @param[out] cnt_free
6066 * Where to put the pointer of a new counter.
6068 * Whether the pool is for counter that was allocated for aging.
6071 * The counter pool pointer and @p cnt_free is set on success,
6072 * NULL otherwise and rte_errno is set.
6074 static struct mlx5_flow_counter_pool *
6075 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6076 struct mlx5_flow_counter **cnt_free,
6079 struct mlx5_priv *priv = dev->data->dev_private;
6080 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6081 struct mlx5_flow_counter_pool *pool;
6082 struct mlx5_counters tmp_tq;
6083 struct mlx5_devx_obj *dcs = NULL;
6084 struct mlx5_flow_counter *cnt;
6085 enum mlx5_counter_type cnt_type =
6086 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6087 bool fallback = priv->sh->cmng.counter_fallback;
6091 /* bulk_bitmap must be 0 for single counter allocation. */
6092 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6095 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6097 pool = flow_dv_pool_create(dev, dcs, age);
6099 mlx5_devx_cmd_destroy(dcs);
6103 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6104 cnt = MLX5_POOL_GET_CNT(pool, i);
6106 cnt->dcs_when_free = dcs;
6110 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6112 rte_errno = ENODATA;
6115 pool = flow_dv_pool_create(dev, dcs, age);
6117 mlx5_devx_cmd_destroy(dcs);
6120 TAILQ_INIT(&tmp_tq);
6121 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6122 cnt = MLX5_POOL_GET_CNT(pool, i);
6124 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6126 rte_spinlock_lock(&cmng->csl[cnt_type]);
6127 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6128 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6129 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6130 (*cnt_free)->pool = pool;
6135 * Allocate a flow counter.
6138 * Pointer to the Ethernet device structure.
6140 * Whether the counter was allocated for aging.
6143 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6146 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6148 struct mlx5_priv *priv = dev->data->dev_private;
6149 struct mlx5_flow_counter_pool *pool = NULL;
6150 struct mlx5_flow_counter *cnt_free = NULL;
6151 bool fallback = priv->sh->cmng.counter_fallback;
6152 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6153 enum mlx5_counter_type cnt_type =
6154 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6157 if (!priv->sh->devx) {
6158 rte_errno = ENOTSUP;
6161 /* Get free counters from container. */
6162 rte_spinlock_lock(&cmng->csl[cnt_type]);
6163 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6165 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6166 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6167 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6169 pool = cnt_free->pool;
6171 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6172 /* Create a DV counter action only in the first time usage. */
6173 if (!cnt_free->action) {
6175 struct mlx5_devx_obj *dcs;
6179 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6180 dcs = pool->min_dcs;
6183 dcs = cnt_free->dcs_when_free;
6185 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6192 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6193 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6194 /* Update the counter reset values. */
6195 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6198 if (!fallback && !priv->sh->cmng.query_thread_on)
6199 /* Start the asynchronous batch query by the host thread. */
6200 mlx5_set_query_alarm(priv->sh);
6202 * When the count action isn't shared (by ID), shared_info field is
6203 * used for indirect action API's refcnt.
6204 * When the counter action is not shared neither by ID nor by indirect
6205 * action API, shared info must be 1.
6207 cnt_free->shared_info.refcnt = 1;
6211 cnt_free->pool = pool;
6213 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6214 rte_spinlock_lock(&cmng->csl[cnt_type]);
6215 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6216 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6222 * Get age param from counter index.
6225 * Pointer to the Ethernet device structure.
6226 * @param[in] counter
6227 * Index to the counter handler.
6230 * The aging parameter specified for the counter index.
6232 static struct mlx5_age_param*
6233 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6236 struct mlx5_flow_counter *cnt;
6237 struct mlx5_flow_counter_pool *pool = NULL;
6239 flow_dv_counter_get_by_idx(dev, counter, &pool);
6240 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6241 cnt = MLX5_POOL_GET_CNT(pool, counter);
6242 return MLX5_CNT_TO_AGE(cnt);
6246 * Remove a flow counter from aged counter list.
6249 * Pointer to the Ethernet device structure.
6250 * @param[in] counter
6251 * Index to the counter handler.
6253 * Pointer to the counter handler.
6256 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6257 uint32_t counter, struct mlx5_flow_counter *cnt)
6259 struct mlx5_age_info *age_info;
6260 struct mlx5_age_param *age_param;
6261 struct mlx5_priv *priv = dev->data->dev_private;
6262 uint16_t expected = AGE_CANDIDATE;
6264 age_info = GET_PORT_AGE_INFO(priv);
6265 age_param = flow_dv_counter_idx_get_age(dev, counter);
6266 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6267 AGE_FREE, false, __ATOMIC_RELAXED,
6268 __ATOMIC_RELAXED)) {
6270 * We need the lock even it is age timeout,
6271 * since counter may still in process.
6273 rte_spinlock_lock(&age_info->aged_sl);
6274 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6275 rte_spinlock_unlock(&age_info->aged_sl);
6276 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6281 * Release a flow counter.
6284 * Pointer to the Ethernet device structure.
6285 * @param[in] counter
6286 * Index to the counter handler.
6289 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6291 struct mlx5_priv *priv = dev->data->dev_private;
6292 struct mlx5_flow_counter_pool *pool = NULL;
6293 struct mlx5_flow_counter *cnt;
6294 enum mlx5_counter_type cnt_type;
6298 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6300 if (pool->is_aged) {
6301 flow_dv_counter_remove_from_age(dev, counter, cnt);
6304 * If the counter action is shared by indirect action API,
6305 * the atomic function reduces its references counter.
6306 * If after the reduction the action is still referenced, the
6307 * function returns here and does not release it.
6308 * When the counter action is not shared by
6309 * indirect action API, shared info is 1 before the reduction,
6310 * so this condition is failed and function doesn't return here.
6312 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6318 * Put the counter back to list to be updated in none fallback mode.
6319 * Currently, we are using two list alternately, while one is in query,
6320 * add the freed counter to the other list based on the pool query_gen
6321 * value. After query finishes, add counter the list to the global
6322 * container counter list. The list changes while query starts. In
6323 * this case, lock will not be needed as query callback and release
6324 * function both operate with the different list.
6326 if (!priv->sh->cmng.counter_fallback) {
6327 rte_spinlock_lock(&pool->csl);
6328 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6329 rte_spinlock_unlock(&pool->csl);
6331 cnt->dcs_when_free = cnt->dcs_when_active;
6332 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6333 MLX5_COUNTER_TYPE_ORIGIN;
6334 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6335 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6337 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6342 * Resize a meter id container.
6345 * Pointer to the Ethernet device structure.
6348 * 0 on success, otherwise negative errno value and rte_errno is set.
6351 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6353 struct mlx5_priv *priv = dev->data->dev_private;
6354 struct mlx5_aso_mtr_pools_mng *pools_mng =
6355 &priv->sh->mtrmng->pools_mng;
6356 void *old_pools = pools_mng->pools;
6357 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6358 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6359 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6366 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6371 memcpy(pools, old_pools, pools_mng->n *
6372 sizeof(struct mlx5_aso_mtr_pool *));
6373 pools_mng->n = resize;
6374 pools_mng->pools = pools;
6376 mlx5_free(old_pools);
6381 * Prepare a new meter and/or a new meter pool.
6384 * Pointer to the Ethernet device structure.
6385 * @param[out] mtr_free
6386 * Where to put the pointer of a new meter.g.
6389 * The meter pool pointer and @mtr_free is set on success,
6390 * NULL otherwise and rte_errno is set.
6392 static struct mlx5_aso_mtr_pool *
6393 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6395 struct mlx5_priv *priv = dev->data->dev_private;
6396 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6397 struct mlx5_aso_mtr_pool *pool = NULL;
6398 struct mlx5_devx_obj *dcs = NULL;
6400 uint32_t log_obj_size;
6402 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6403 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6404 priv->sh->cdev->pdn,
6407 rte_errno = ENODATA;
6410 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6413 claim_zero(mlx5_devx_cmd_destroy(dcs));
6416 pool->devx_obj = dcs;
6417 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6418 pool->index = pools_mng->n_valid;
6419 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6421 claim_zero(mlx5_devx_cmd_destroy(dcs));
6422 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6425 pools_mng->pools[pool->index] = pool;
6426 pools_mng->n_valid++;
6427 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6428 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6429 pool->mtrs[i].offset = i;
6430 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6432 pool->mtrs[0].offset = 0;
6433 *mtr_free = &pool->mtrs[0];
6438 * Release a flow meter into pool.
6441 * Pointer to the Ethernet device structure.
6442 * @param[in] mtr_idx
6443 * Index to aso flow meter.
6446 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6448 struct mlx5_priv *priv = dev->data->dev_private;
6449 struct mlx5_aso_mtr_pools_mng *pools_mng =
6450 &priv->sh->mtrmng->pools_mng;
6451 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6453 MLX5_ASSERT(aso_mtr);
6454 rte_spinlock_lock(&pools_mng->mtrsl);
6455 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6456 aso_mtr->state = ASO_METER_FREE;
6457 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6458 rte_spinlock_unlock(&pools_mng->mtrsl);
6462 * Allocate a aso flow meter.
6465 * Pointer to the Ethernet device structure.
6468 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6471 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6473 struct mlx5_priv *priv = dev->data->dev_private;
6474 struct mlx5_aso_mtr *mtr_free = NULL;
6475 struct mlx5_aso_mtr_pools_mng *pools_mng =
6476 &priv->sh->mtrmng->pools_mng;
6477 struct mlx5_aso_mtr_pool *pool;
6478 uint32_t mtr_idx = 0;
6480 if (!priv->sh->devx) {
6481 rte_errno = ENOTSUP;
6484 /* Allocate the flow meter memory. */
6485 /* Get free meters from management. */
6486 rte_spinlock_lock(&pools_mng->mtrsl);
6487 mtr_free = LIST_FIRST(&pools_mng->meters);
6489 LIST_REMOVE(mtr_free, next);
6490 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6491 rte_spinlock_unlock(&pools_mng->mtrsl);
6494 mtr_free->state = ASO_METER_WAIT;
6495 rte_spinlock_unlock(&pools_mng->mtrsl);
6496 pool = container_of(mtr_free,
6497 struct mlx5_aso_mtr_pool,
6498 mtrs[mtr_free->offset]);
6499 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6500 if (!mtr_free->fm.meter_action) {
6501 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6502 struct rte_flow_error error;
6505 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6506 mtr_free->fm.meter_action =
6507 mlx5_glue->dv_create_flow_action_aso
6508 (priv->sh->rx_domain,
6509 pool->devx_obj->obj,
6511 (1 << MLX5_FLOW_COLOR_GREEN),
6513 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6514 if (!mtr_free->fm.meter_action) {
6515 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6523 * Verify the @p attributes will be correctly understood by the NIC and store
6524 * them in the @p flow if everything is correct.
6527 * Pointer to dev struct.
6528 * @param[in] attributes
6529 * Pointer to flow attributes
6530 * @param[in] external
6531 * This flow rule is created by request external to PMD.
6533 * Pointer to error structure.
6536 * - 0 on success and non root table.
6537 * - 1 on success and root table.
6538 * - a negative errno value otherwise and rte_errno is set.
6541 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6542 const struct mlx5_flow_tunnel *tunnel,
6543 const struct rte_flow_attr *attributes,
6544 const struct flow_grp_info *grp_info,
6545 struct rte_flow_error *error)
6547 struct mlx5_priv *priv = dev->data->dev_private;
6548 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6551 #ifndef HAVE_MLX5DV_DR
6552 RTE_SET_USED(tunnel);
6553 RTE_SET_USED(grp_info);
6554 if (attributes->group)
6555 return rte_flow_error_set(error, ENOTSUP,
6556 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6558 "groups are not supported");
6562 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6567 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6569 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6570 attributes->priority > lowest_priority)
6571 return rte_flow_error_set(error, ENOTSUP,
6572 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6574 "priority out of range");
6575 if (attributes->transfer) {
6576 if (!priv->config.dv_esw_en)
6577 return rte_flow_error_set
6579 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6580 "E-Switch dr is not supported");
6581 if (!(priv->representor || priv->master))
6582 return rte_flow_error_set
6583 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6584 NULL, "E-Switch configuration can only be"
6585 " done by a master or a representor device");
6586 if (attributes->egress)
6587 return rte_flow_error_set
6589 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6590 "egress is not supported");
6592 if (!(attributes->egress ^ attributes->ingress))
6593 return rte_flow_error_set(error, ENOTSUP,
6594 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6595 "must specify exactly one of "
6596 "ingress or egress");
6601 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6602 int64_t pattern_flags, uint64_t l3_flags,
6603 uint64_t l4_flags, uint64_t ip4_flag,
6604 struct rte_flow_error *error)
6606 if (mask->l3_ok && !(pattern_flags & l3_flags))
6607 return rte_flow_error_set(error, EINVAL,
6608 RTE_FLOW_ERROR_TYPE_ITEM,
6609 NULL, "missing L3 protocol");
6611 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6612 return rte_flow_error_set(error, EINVAL,
6613 RTE_FLOW_ERROR_TYPE_ITEM,
6614 NULL, "missing IPv4 protocol");
6616 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6617 return rte_flow_error_set(error, EINVAL,
6618 RTE_FLOW_ERROR_TYPE_ITEM,
6619 NULL, "missing L4 protocol");
6625 flow_dv_validate_item_integrity_post(const struct
6626 rte_flow_item *integrity_items[2],
6627 int64_t pattern_flags,
6628 struct rte_flow_error *error)
6630 const struct rte_flow_item_integrity *mask;
6633 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6634 mask = (typeof(mask))integrity_items[0]->mask;
6635 ret = validate_integrity_bits(mask, pattern_flags,
6636 MLX5_FLOW_LAYER_OUTER_L3,
6637 MLX5_FLOW_LAYER_OUTER_L4,
6638 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6643 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6644 mask = (typeof(mask))integrity_items[1]->mask;
6645 ret = validate_integrity_bits(mask, pattern_flags,
6646 MLX5_FLOW_LAYER_INNER_L3,
6647 MLX5_FLOW_LAYER_INNER_L4,
6648 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6657 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6658 const struct rte_flow_item *integrity_item,
6659 uint64_t pattern_flags, uint64_t *last_item,
6660 const struct rte_flow_item *integrity_items[2],
6661 struct rte_flow_error *error)
6663 struct mlx5_priv *priv = dev->data->dev_private;
6664 const struct rte_flow_item_integrity *mask = (typeof(mask))
6665 integrity_item->mask;
6666 const struct rte_flow_item_integrity *spec = (typeof(spec))
6667 integrity_item->spec;
6669 if (!priv->config.hca_attr.pkt_integrity_match)
6670 return rte_flow_error_set(error, ENOTSUP,
6671 RTE_FLOW_ERROR_TYPE_ITEM,
6673 "packet integrity integrity_item not supported");
6675 return rte_flow_error_set(error, ENOTSUP,
6676 RTE_FLOW_ERROR_TYPE_ITEM,
6678 "no spec for integrity item");
6680 mask = &rte_flow_item_integrity_mask;
6681 if (!mlx5_validate_integrity_item(mask))
6682 return rte_flow_error_set(error, ENOTSUP,
6683 RTE_FLOW_ERROR_TYPE_ITEM,
6685 "unsupported integrity filter");
6686 if (spec->level > 1) {
6687 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6688 return rte_flow_error_set
6690 RTE_FLOW_ERROR_TYPE_ITEM,
6691 NULL, "multiple inner integrity items not supported");
6692 integrity_items[1] = integrity_item;
6693 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6695 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6696 return rte_flow_error_set
6698 RTE_FLOW_ERROR_TYPE_ITEM,
6699 NULL, "multiple outer integrity items not supported");
6700 integrity_items[0] = integrity_item;
6701 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6707 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6708 const struct rte_flow_item *item,
6709 uint64_t item_flags,
6710 uint64_t *last_item,
6712 struct rte_flow_error *error)
6714 const struct rte_flow_item_flex *flow_spec = item->spec;
6715 const struct rte_flow_item_flex *flow_mask = item->mask;
6716 struct mlx5_flex_item *flex;
6719 return rte_flow_error_set(error, EINVAL,
6720 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6721 "flex flow item spec cannot be NULL");
6723 return rte_flow_error_set(error, EINVAL,
6724 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6725 "flex flow item mask cannot be NULL");
6727 return rte_flow_error_set(error, ENOTSUP,
6728 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6729 "flex flow item last not supported");
6730 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6731 return rte_flow_error_set(error, EINVAL,
6732 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6733 "invalid flex flow item handle");
6734 flex = (struct mlx5_flex_item *)flow_spec->handle;
6735 switch (flex->tunnel_mode) {
6736 case FLEX_TUNNEL_MODE_SINGLE:
6738 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6739 rte_flow_error_set(error, EINVAL,
6740 RTE_FLOW_ERROR_TYPE_ITEM,
6741 NULL, "multiple flex items not supported");
6743 case FLEX_TUNNEL_MODE_OUTER:
6745 rte_flow_error_set(error, EINVAL,
6746 RTE_FLOW_ERROR_TYPE_ITEM,
6747 NULL, "inner flex item was not configured");
6748 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6749 rte_flow_error_set(error, ENOTSUP,
6750 RTE_FLOW_ERROR_TYPE_ITEM,
6751 NULL, "multiple flex items not supported");
6753 case FLEX_TUNNEL_MODE_INNER:
6755 rte_flow_error_set(error, EINVAL,
6756 RTE_FLOW_ERROR_TYPE_ITEM,
6757 NULL, "outer flex item was not configured");
6758 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6759 rte_flow_error_set(error, EINVAL,
6760 RTE_FLOW_ERROR_TYPE_ITEM,
6761 NULL, "multiple flex items not supported");
6763 case FLEX_TUNNEL_MODE_MULTI:
6764 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6765 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6766 rte_flow_error_set(error, EINVAL,
6767 RTE_FLOW_ERROR_TYPE_ITEM,
6768 NULL, "multiple flex items not supported");
6771 case FLEX_TUNNEL_MODE_TUNNEL:
6772 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6773 rte_flow_error_set(error, EINVAL,
6774 RTE_FLOW_ERROR_TYPE_ITEM,
6775 NULL, "multiple flex tunnel items not supported");
6778 rte_flow_error_set(error, EINVAL,
6779 RTE_FLOW_ERROR_TYPE_ITEM,
6780 NULL, "invalid flex item configuration");
6782 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6783 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6784 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6789 * Internal validation function. For validating both actions and items.
6792 * Pointer to the rte_eth_dev structure.
6794 * Pointer to the flow attributes.
6796 * Pointer to the list of items.
6797 * @param[in] actions
6798 * Pointer to the list of actions.
6799 * @param[in] external
6800 * This flow rule is created by request external to PMD.
6801 * @param[in] hairpin
6802 * Number of hairpin TX actions, 0 means classic flow.
6804 * Pointer to the error structure.
6807 * 0 on success, a negative errno value otherwise and rte_errno is set.
6810 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6811 const struct rte_flow_item items[],
6812 const struct rte_flow_action actions[],
6813 bool external, int hairpin, struct rte_flow_error *error)
6816 uint64_t action_flags = 0;
6817 uint64_t item_flags = 0;
6818 uint64_t last_item = 0;
6819 uint8_t next_protocol = 0xff;
6820 uint16_t ether_type = 0;
6822 uint8_t item_ipv6_proto = 0;
6823 int fdb_mirror_limit = 0;
6824 int modify_after_mirror = 0;
6825 const struct rte_flow_item *geneve_item = NULL;
6826 const struct rte_flow_item *gre_item = NULL;
6827 const struct rte_flow_item *gtp_item = NULL;
6828 const struct rte_flow_action_raw_decap *decap;
6829 const struct rte_flow_action_raw_encap *encap;
6830 const struct rte_flow_action_rss *rss = NULL;
6831 const struct rte_flow_action_rss *sample_rss = NULL;
6832 const struct rte_flow_action_count *sample_count = NULL;
6833 const struct rte_flow_item_tcp nic_tcp_mask = {
6836 .src_port = RTE_BE16(UINT16_MAX),
6837 .dst_port = RTE_BE16(UINT16_MAX),
6840 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6843 "\xff\xff\xff\xff\xff\xff\xff\xff"
6844 "\xff\xff\xff\xff\xff\xff\xff\xff",
6846 "\xff\xff\xff\xff\xff\xff\xff\xff"
6847 "\xff\xff\xff\xff\xff\xff\xff\xff",
6848 .vtc_flow = RTE_BE32(0xffffffff),
6854 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6858 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6862 .dummy[0] = 0xffffffff,
6865 struct mlx5_priv *priv = dev->data->dev_private;
6866 struct mlx5_dev_config *dev_conf = &priv->config;
6867 uint16_t queue_index = 0xFFFF;
6868 const struct rte_flow_item_vlan *vlan_m = NULL;
6869 uint32_t rw_act_num = 0;
6871 const struct mlx5_flow_tunnel *tunnel;
6872 enum mlx5_tof_rule_type tof_rule_type;
6873 struct flow_grp_info grp_info = {
6874 .external = !!external,
6875 .transfer = !!attr->transfer,
6876 .fdb_def_rule = !!priv->fdb_def_rule,
6877 .std_tbl_fix = true,
6879 const struct rte_eth_hairpin_conf *conf;
6880 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6881 const struct rte_flow_item *port_id_item = NULL;
6882 bool def_policy = false;
6883 uint16_t udp_dport = 0;
6887 tunnel = is_tunnel_offload_active(dev) ?
6888 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6890 if (!priv->config.dv_flow_en)
6891 return rte_flow_error_set
6893 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6894 NULL, "tunnel offload requires DV flow interface");
6895 if (priv->representor)
6896 return rte_flow_error_set
6898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6899 NULL, "decap not supported for VF representor");
6900 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6901 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6902 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6903 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6904 MLX5_FLOW_ACTION_DECAP;
6905 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6906 (dev, attr, tunnel, tof_rule_type);
6908 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6911 is_root = (uint64_t)ret;
6912 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6913 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6914 int type = items->type;
6916 if (!mlx5_flow_os_item_supported(type))
6917 return rte_flow_error_set(error, ENOTSUP,
6918 RTE_FLOW_ERROR_TYPE_ITEM,
6919 NULL, "item not supported");
6921 case RTE_FLOW_ITEM_TYPE_VOID:
6923 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6924 ret = flow_dv_validate_item_port_id
6925 (dev, items, attr, item_flags, error);
6928 last_item = MLX5_FLOW_ITEM_PORT_ID;
6929 port_id_item = items;
6931 case RTE_FLOW_ITEM_TYPE_ETH:
6932 ret = mlx5_flow_validate_item_eth(items, item_flags,
6936 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6937 MLX5_FLOW_LAYER_OUTER_L2;
6938 if (items->mask != NULL && items->spec != NULL) {
6940 ((const struct rte_flow_item_eth *)
6943 ((const struct rte_flow_item_eth *)
6945 ether_type = rte_be_to_cpu_16(ether_type);
6950 case RTE_FLOW_ITEM_TYPE_VLAN:
6951 ret = flow_dv_validate_item_vlan(items, item_flags,
6955 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6956 MLX5_FLOW_LAYER_OUTER_VLAN;
6957 if (items->mask != NULL && items->spec != NULL) {
6959 ((const struct rte_flow_item_vlan *)
6960 items->spec)->inner_type;
6962 ((const struct rte_flow_item_vlan *)
6963 items->mask)->inner_type;
6964 ether_type = rte_be_to_cpu_16(ether_type);
6968 /* Store outer VLAN mask for of_push_vlan action. */
6970 vlan_m = items->mask;
6972 case RTE_FLOW_ITEM_TYPE_IPV4:
6973 mlx5_flow_tunnel_ip_check(items, next_protocol,
6974 &item_flags, &tunnel);
6975 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6976 last_item, ether_type,
6980 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6981 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6982 if (items->mask != NULL &&
6983 ((const struct rte_flow_item_ipv4 *)
6984 items->mask)->hdr.next_proto_id) {
6986 ((const struct rte_flow_item_ipv4 *)
6987 (items->spec))->hdr.next_proto_id;
6989 ((const struct rte_flow_item_ipv4 *)
6990 (items->mask))->hdr.next_proto_id;
6992 /* Reset for inner layer. */
6993 next_protocol = 0xff;
6996 case RTE_FLOW_ITEM_TYPE_IPV6:
6997 mlx5_flow_tunnel_ip_check(items, next_protocol,
6998 &item_flags, &tunnel);
6999 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7006 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7007 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7008 if (items->mask != NULL &&
7009 ((const struct rte_flow_item_ipv6 *)
7010 items->mask)->hdr.proto) {
7012 ((const struct rte_flow_item_ipv6 *)
7013 items->spec)->hdr.proto;
7015 ((const struct rte_flow_item_ipv6 *)
7016 items->spec)->hdr.proto;
7018 ((const struct rte_flow_item_ipv6 *)
7019 items->mask)->hdr.proto;
7021 /* Reset for inner layer. */
7022 next_protocol = 0xff;
7025 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7026 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7031 last_item = tunnel ?
7032 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7033 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7034 if (items->mask != NULL &&
7035 ((const struct rte_flow_item_ipv6_frag_ext *)
7036 items->mask)->hdr.next_header) {
7038 ((const struct rte_flow_item_ipv6_frag_ext *)
7039 items->spec)->hdr.next_header;
7041 ((const struct rte_flow_item_ipv6_frag_ext *)
7042 items->mask)->hdr.next_header;
7044 /* Reset for inner layer. */
7045 next_protocol = 0xff;
7048 case RTE_FLOW_ITEM_TYPE_TCP:
7049 ret = mlx5_flow_validate_item_tcp
7056 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7057 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7059 case RTE_FLOW_ITEM_TYPE_UDP:
7060 ret = mlx5_flow_validate_item_udp(items, item_flags,
7063 const struct rte_flow_item_udp *spec = items->spec;
7064 const struct rte_flow_item_udp *mask = items->mask;
7066 mask = &rte_flow_item_udp_mask;
7068 udp_dport = rte_be_to_cpu_16
7069 (spec->hdr.dst_port &
7070 mask->hdr.dst_port);
7073 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7074 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7076 case RTE_FLOW_ITEM_TYPE_GRE:
7077 ret = mlx5_flow_validate_item_gre(items, item_flags,
7078 next_protocol, error);
7082 last_item = MLX5_FLOW_LAYER_GRE;
7084 case RTE_FLOW_ITEM_TYPE_NVGRE:
7085 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7090 last_item = MLX5_FLOW_LAYER_NVGRE;
7092 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7093 ret = mlx5_flow_validate_item_gre_key
7094 (items, item_flags, gre_item, error);
7097 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7099 case RTE_FLOW_ITEM_TYPE_VXLAN:
7100 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7105 last_item = MLX5_FLOW_LAYER_VXLAN;
7107 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7108 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7113 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7115 case RTE_FLOW_ITEM_TYPE_GENEVE:
7116 ret = mlx5_flow_validate_item_geneve(items,
7121 geneve_item = items;
7122 last_item = MLX5_FLOW_LAYER_GENEVE;
7124 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7125 ret = mlx5_flow_validate_item_geneve_opt(items,
7132 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7134 case RTE_FLOW_ITEM_TYPE_MPLS:
7135 ret = mlx5_flow_validate_item_mpls(dev, items,
7140 last_item = MLX5_FLOW_LAYER_MPLS;
7143 case RTE_FLOW_ITEM_TYPE_MARK:
7144 ret = flow_dv_validate_item_mark(dev, items, attr,
7148 last_item = MLX5_FLOW_ITEM_MARK;
7150 case RTE_FLOW_ITEM_TYPE_META:
7151 ret = flow_dv_validate_item_meta(dev, items, attr,
7155 last_item = MLX5_FLOW_ITEM_METADATA;
7157 case RTE_FLOW_ITEM_TYPE_ICMP:
7158 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7163 last_item = MLX5_FLOW_LAYER_ICMP;
7165 case RTE_FLOW_ITEM_TYPE_ICMP6:
7166 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7171 item_ipv6_proto = IPPROTO_ICMPV6;
7172 last_item = MLX5_FLOW_LAYER_ICMP6;
7174 case RTE_FLOW_ITEM_TYPE_TAG:
7175 ret = flow_dv_validate_item_tag(dev, items,
7179 last_item = MLX5_FLOW_ITEM_TAG;
7181 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7182 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7184 case RTE_FLOW_ITEM_TYPE_GTP:
7185 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7190 last_item = MLX5_FLOW_LAYER_GTP;
7192 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7193 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7198 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7200 case RTE_FLOW_ITEM_TYPE_ECPRI:
7201 /* Capacity will be checked in the translate stage. */
7202 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7209 last_item = MLX5_FLOW_LAYER_ECPRI;
7211 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7212 ret = flow_dv_validate_item_integrity(dev, items,
7220 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7221 ret = flow_dv_validate_item_aso_ct(dev, items,
7222 &item_flags, error);
7226 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7227 /* tunnel offload item was processed before
7228 * list it here as a supported type
7231 case RTE_FLOW_ITEM_TYPE_FLEX:
7232 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7234 tunnel != 0, error);
7239 return rte_flow_error_set(error, ENOTSUP,
7240 RTE_FLOW_ERROR_TYPE_ITEM,
7241 NULL, "item not supported");
7243 item_flags |= last_item;
7245 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7246 ret = flow_dv_validate_item_integrity_post(integrity_items,
7251 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7252 int type = actions->type;
7253 bool shared_count = false;
7255 if (!mlx5_flow_os_action_supported(type))
7256 return rte_flow_error_set(error, ENOTSUP,
7257 RTE_FLOW_ERROR_TYPE_ACTION,
7259 "action not supported");
7260 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7261 return rte_flow_error_set(error, ENOTSUP,
7262 RTE_FLOW_ERROR_TYPE_ACTION,
7263 actions, "too many actions");
7265 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7266 return rte_flow_error_set(error, ENOTSUP,
7267 RTE_FLOW_ERROR_TYPE_ACTION,
7268 NULL, "meter action with policy "
7269 "must be the last action");
7271 case RTE_FLOW_ACTION_TYPE_VOID:
7273 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7274 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7275 ret = flow_dv_validate_action_port_id(dev,
7282 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7285 case RTE_FLOW_ACTION_TYPE_FLAG:
7286 ret = flow_dv_validate_action_flag(dev, action_flags,
7290 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7291 /* Count all modify-header actions as one. */
7292 if (!(action_flags &
7293 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7295 action_flags |= MLX5_FLOW_ACTION_FLAG |
7296 MLX5_FLOW_ACTION_MARK_EXT;
7297 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7298 modify_after_mirror = 1;
7301 action_flags |= MLX5_FLOW_ACTION_FLAG;
7304 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7306 case RTE_FLOW_ACTION_TYPE_MARK:
7307 ret = flow_dv_validate_action_mark(dev, actions,
7312 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7313 /* Count all modify-header actions as one. */
7314 if (!(action_flags &
7315 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7317 action_flags |= MLX5_FLOW_ACTION_MARK |
7318 MLX5_FLOW_ACTION_MARK_EXT;
7319 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7320 modify_after_mirror = 1;
7322 action_flags |= MLX5_FLOW_ACTION_MARK;
7325 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7327 case RTE_FLOW_ACTION_TYPE_SET_META:
7328 ret = flow_dv_validate_action_set_meta(dev, actions,
7333 /* Count all modify-header actions as one action. */
7334 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7336 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7337 modify_after_mirror = 1;
7338 action_flags |= MLX5_FLOW_ACTION_SET_META;
7339 rw_act_num += MLX5_ACT_NUM_SET_META;
7341 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7342 ret = flow_dv_validate_action_set_tag(dev, actions,
7347 /* Count all modify-header actions as one action. */
7348 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7350 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7351 modify_after_mirror = 1;
7352 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7353 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7355 case RTE_FLOW_ACTION_TYPE_DROP:
7356 ret = mlx5_flow_validate_action_drop(action_flags,
7360 action_flags |= MLX5_FLOW_ACTION_DROP;
7363 case RTE_FLOW_ACTION_TYPE_QUEUE:
7364 ret = mlx5_flow_validate_action_queue(actions,
7369 queue_index = ((const struct rte_flow_action_queue *)
7370 (actions->conf))->index;
7371 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7374 case RTE_FLOW_ACTION_TYPE_RSS:
7375 rss = actions->conf;
7376 ret = mlx5_flow_validate_action_rss(actions,
7382 if (rss && sample_rss &&
7383 (sample_rss->level != rss->level ||
7384 sample_rss->types != rss->types))
7385 return rte_flow_error_set(error, ENOTSUP,
7386 RTE_FLOW_ERROR_TYPE_ACTION,
7388 "Can't use the different RSS types "
7389 "or level in the same flow");
7390 if (rss != NULL && rss->queue_num)
7391 queue_index = rss->queue[0];
7392 action_flags |= MLX5_FLOW_ACTION_RSS;
7395 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7397 mlx5_flow_validate_action_default_miss(action_flags,
7401 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7404 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7405 shared_count = true;
7407 case RTE_FLOW_ACTION_TYPE_COUNT:
7408 ret = flow_dv_validate_action_count(dev, shared_count,
7413 action_flags |= MLX5_FLOW_ACTION_COUNT;
7416 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7417 if (flow_dv_validate_action_pop_vlan(dev,
7423 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7424 modify_after_mirror = 1;
7425 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7428 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7429 ret = flow_dv_validate_action_push_vlan(dev,
7436 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7437 modify_after_mirror = 1;
7438 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7441 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7442 ret = flow_dv_validate_action_set_vlan_pcp
7443 (action_flags, actions, error);
7446 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7447 modify_after_mirror = 1;
7448 /* Count PCP with push_vlan command. */
7449 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7451 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7452 ret = flow_dv_validate_action_set_vlan_vid
7453 (item_flags, action_flags,
7457 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7458 modify_after_mirror = 1;
7459 /* Count VID with push_vlan command. */
7460 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7461 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7463 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7464 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7465 ret = flow_dv_validate_action_l2_encap(dev,
7471 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7474 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7475 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7476 ret = flow_dv_validate_action_decap(dev, action_flags,
7477 actions, item_flags,
7481 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7482 modify_after_mirror = 1;
7483 action_flags |= MLX5_FLOW_ACTION_DECAP;
7486 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7487 ret = flow_dv_validate_action_raw_encap_decap
7488 (dev, NULL, actions->conf, attr, &action_flags,
7489 &actions_n, actions, item_flags, error);
7493 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7494 decap = actions->conf;
7495 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7497 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7501 encap = actions->conf;
7503 ret = flow_dv_validate_action_raw_encap_decap
7505 decap ? decap : &empty_decap, encap,
7506 attr, &action_flags, &actions_n,
7507 actions, item_flags, error);
7510 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7511 (action_flags & MLX5_FLOW_ACTION_DECAP))
7512 modify_after_mirror = 1;
7514 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7515 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7516 ret = flow_dv_validate_action_modify_mac(action_flags,
7522 /* Count all modify-header actions as one action. */
7523 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7525 action_flags |= actions->type ==
7526 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7527 MLX5_FLOW_ACTION_SET_MAC_SRC :
7528 MLX5_FLOW_ACTION_SET_MAC_DST;
7529 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7530 modify_after_mirror = 1;
7532 * Even if the source and destination MAC addresses have
7533 * overlap in the header with 4B alignment, the convert
7534 * function will handle them separately and 4 SW actions
7535 * will be created. And 2 actions will be added each
7536 * time no matter how many bytes of address will be set.
7538 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7540 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7541 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7542 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7548 /* Count all modify-header actions as one action. */
7549 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7551 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7552 modify_after_mirror = 1;
7553 action_flags |= actions->type ==
7554 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7555 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7556 MLX5_FLOW_ACTION_SET_IPV4_DST;
7557 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7559 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7560 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7561 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7567 if (item_ipv6_proto == IPPROTO_ICMPV6)
7568 return rte_flow_error_set(error, ENOTSUP,
7569 RTE_FLOW_ERROR_TYPE_ACTION,
7571 "Can't change header "
7572 "with ICMPv6 proto");
7573 /* Count all modify-header actions as one action. */
7574 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7576 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7577 modify_after_mirror = 1;
7578 action_flags |= actions->type ==
7579 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7580 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7581 MLX5_FLOW_ACTION_SET_IPV6_DST;
7582 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7584 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7585 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7586 ret = flow_dv_validate_action_modify_tp(action_flags,
7592 /* Count all modify-header actions as one action. */
7593 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7595 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7596 modify_after_mirror = 1;
7597 action_flags |= actions->type ==
7598 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7599 MLX5_FLOW_ACTION_SET_TP_SRC :
7600 MLX5_FLOW_ACTION_SET_TP_DST;
7601 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7603 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7604 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7605 ret = flow_dv_validate_action_modify_ttl(action_flags,
7611 /* Count all modify-header actions as one action. */
7612 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7614 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7615 modify_after_mirror = 1;
7616 action_flags |= actions->type ==
7617 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7618 MLX5_FLOW_ACTION_SET_TTL :
7619 MLX5_FLOW_ACTION_DEC_TTL;
7620 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7622 case RTE_FLOW_ACTION_TYPE_JUMP:
7623 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7629 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7631 return rte_flow_error_set(error, EINVAL,
7632 RTE_FLOW_ERROR_TYPE_ACTION,
7634 "sample and jump action combination is not supported");
7636 action_flags |= MLX5_FLOW_ACTION_JUMP;
7638 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7639 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7640 ret = flow_dv_validate_action_modify_tcp_seq
7647 /* Count all modify-header actions as one action. */
7648 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7650 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7651 modify_after_mirror = 1;
7652 action_flags |= actions->type ==
7653 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7654 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7655 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7656 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7658 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7659 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7660 ret = flow_dv_validate_action_modify_tcp_ack
7667 /* Count all modify-header actions as one action. */
7668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7670 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7671 modify_after_mirror = 1;
7672 action_flags |= actions->type ==
7673 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7674 MLX5_FLOW_ACTION_INC_TCP_ACK :
7675 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7676 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7678 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7680 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7681 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7682 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7684 case RTE_FLOW_ACTION_TYPE_METER:
7685 ret = mlx5_flow_validate_action_meter(dev,
7693 action_flags |= MLX5_FLOW_ACTION_METER;
7696 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7698 /* Meter action will add one more TAG action. */
7699 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7701 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7702 if (!attr->transfer && !attr->group)
7703 return rte_flow_error_set(error, ENOTSUP,
7704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7706 "Shared ASO age action is not supported for group 0");
7707 if (action_flags & MLX5_FLOW_ACTION_AGE)
7708 return rte_flow_error_set
7710 RTE_FLOW_ERROR_TYPE_ACTION,
7712 "duplicate age actions set");
7713 action_flags |= MLX5_FLOW_ACTION_AGE;
7716 case RTE_FLOW_ACTION_TYPE_AGE:
7717 ret = flow_dv_validate_action_age(action_flags,
7723 * Validate the regular AGE action (using counter)
7724 * mutual exclusion with share counter actions.
7726 if (!priv->sh->flow_hit_aso_en) {
7728 return rte_flow_error_set
7730 RTE_FLOW_ERROR_TYPE_ACTION,
7732 "old age and shared count combination is not supported");
7734 return rte_flow_error_set
7736 RTE_FLOW_ERROR_TYPE_ACTION,
7738 "old age action and count must be in the same sub flow");
7740 action_flags |= MLX5_FLOW_ACTION_AGE;
7743 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7744 ret = flow_dv_validate_action_modify_ipv4_dscp
7751 /* Count all modify-header actions as one action. */
7752 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7754 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7755 modify_after_mirror = 1;
7756 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7757 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7759 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7760 ret = flow_dv_validate_action_modify_ipv6_dscp
7767 /* Count all modify-header actions as one action. */
7768 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7770 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7771 modify_after_mirror = 1;
7772 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7773 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7775 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7776 ret = flow_dv_validate_action_sample(&action_flags,
7785 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7788 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7789 ret = flow_dv_validate_action_modify_field(dev,
7796 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7797 modify_after_mirror = 1;
7798 /* Count all modify-header actions as one action. */
7799 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7801 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7804 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7805 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7810 action_flags |= MLX5_FLOW_ACTION_CT;
7812 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7813 /* tunnel offload action was processed before
7814 * list it here as a supported type
7818 return rte_flow_error_set(error, ENOTSUP,
7819 RTE_FLOW_ERROR_TYPE_ACTION,
7821 "action not supported");
7825 * Validate actions in flow rules
7826 * - Explicit decap action is prohibited by the tunnel offload API.
7827 * - Drop action in tunnel steer rule is prohibited by the API.
7828 * - Application cannot use MARK action because it's value can mask
7829 * tunnel default miss nitification.
7830 * - JUMP in tunnel match rule has no support in current PMD
7832 * - TAG & META are reserved for future uses.
7834 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7835 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7836 MLX5_FLOW_ACTION_MARK |
7837 MLX5_FLOW_ACTION_SET_TAG |
7838 MLX5_FLOW_ACTION_SET_META |
7839 MLX5_FLOW_ACTION_DROP;
7841 if (action_flags & bad_actions_mask)
7842 return rte_flow_error_set
7844 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7845 "Invalid RTE action in tunnel "
7847 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7848 return rte_flow_error_set
7850 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7851 "tunnel set decap rule must terminate "
7854 return rte_flow_error_set
7856 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7857 "tunnel flows for ingress traffic only");
7859 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7860 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7861 MLX5_FLOW_ACTION_MARK |
7862 MLX5_FLOW_ACTION_SET_TAG |
7863 MLX5_FLOW_ACTION_SET_META;
7865 if (action_flags & bad_actions_mask)
7866 return rte_flow_error_set
7868 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7869 "Invalid RTE action in tunnel "
7873 * Validate the drop action mutual exclusion with other actions.
7874 * Drop action is mutually-exclusive with any other action, except for
7876 * Drop action compatibility with tunnel offload was already validated.
7878 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7879 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7880 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7881 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7882 return rte_flow_error_set(error, EINVAL,
7883 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7884 "Drop action is mutually-exclusive "
7885 "with any other action, except for "
7887 /* Eswitch has few restrictions on using items and actions */
7888 if (attr->transfer) {
7889 if (!mlx5_flow_ext_mreg_supported(dev) &&
7890 action_flags & MLX5_FLOW_ACTION_FLAG)
7891 return rte_flow_error_set(error, ENOTSUP,
7892 RTE_FLOW_ERROR_TYPE_ACTION,
7894 "unsupported action FLAG");
7895 if (!mlx5_flow_ext_mreg_supported(dev) &&
7896 action_flags & MLX5_FLOW_ACTION_MARK)
7897 return rte_flow_error_set(error, ENOTSUP,
7898 RTE_FLOW_ERROR_TYPE_ACTION,
7900 "unsupported action MARK");
7901 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7902 return rte_flow_error_set(error, ENOTSUP,
7903 RTE_FLOW_ERROR_TYPE_ACTION,
7905 "unsupported action QUEUE");
7906 if (action_flags & MLX5_FLOW_ACTION_RSS)
7907 return rte_flow_error_set(error, ENOTSUP,
7908 RTE_FLOW_ERROR_TYPE_ACTION,
7910 "unsupported action RSS");
7911 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7912 return rte_flow_error_set(error, EINVAL,
7913 RTE_FLOW_ERROR_TYPE_ACTION,
7915 "no fate action is found");
7917 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7918 return rte_flow_error_set(error, EINVAL,
7919 RTE_FLOW_ERROR_TYPE_ACTION,
7921 "no fate action is found");
7924 * Continue validation for Xcap and VLAN actions.
7925 * If hairpin is working in explicit TX rule mode, there is no actions
7926 * splitting and the validation of hairpin ingress flow should be the
7927 * same as other standard flows.
7929 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7930 MLX5_FLOW_VLAN_ACTIONS)) &&
7931 (queue_index == 0xFFFF ||
7932 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7933 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7934 conf->tx_explicit != 0))) {
7935 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7936 MLX5_FLOW_XCAP_ACTIONS)
7937 return rte_flow_error_set(error, ENOTSUP,
7938 RTE_FLOW_ERROR_TYPE_ACTION,
7939 NULL, "encap and decap "
7940 "combination aren't supported");
7941 if (!attr->transfer && attr->ingress) {
7942 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7943 return rte_flow_error_set
7945 RTE_FLOW_ERROR_TYPE_ACTION,
7946 NULL, "encap is not supported"
7947 " for ingress traffic");
7948 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7949 return rte_flow_error_set
7951 RTE_FLOW_ERROR_TYPE_ACTION,
7952 NULL, "push VLAN action not "
7953 "supported for ingress");
7954 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7955 MLX5_FLOW_VLAN_ACTIONS)
7956 return rte_flow_error_set
7958 RTE_FLOW_ERROR_TYPE_ACTION,
7959 NULL, "no support for "
7960 "multiple VLAN actions");
7963 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7964 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7965 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7967 return rte_flow_error_set
7969 RTE_FLOW_ERROR_TYPE_ACTION,
7970 NULL, "fate action not supported for "
7971 "meter with policy");
7973 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7974 return rte_flow_error_set
7976 RTE_FLOW_ERROR_TYPE_ACTION,
7977 NULL, "modify header action in egress "
7978 "cannot be done before meter action");
7979 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7980 return rte_flow_error_set
7982 RTE_FLOW_ERROR_TYPE_ACTION,
7983 NULL, "encap action in egress "
7984 "cannot be done before meter action");
7985 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7986 return rte_flow_error_set
7988 RTE_FLOW_ERROR_TYPE_ACTION,
7989 NULL, "push vlan action in egress "
7990 "cannot be done before meter action");
7994 * Hairpin flow will add one more TAG action in TX implicit mode.
7995 * In TX explicit mode, there will be no hairpin flow ID.
7998 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7999 /* extra metadata enabled: one more TAG action will be add. */
8000 if (dev_conf->dv_flow_en &&
8001 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8002 mlx5_flow_ext_mreg_supported(dev))
8003 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8005 flow_dv_modify_hdr_action_max(dev, is_root)) {
8006 return rte_flow_error_set(error, ENOTSUP,
8007 RTE_FLOW_ERROR_TYPE_ACTION,
8008 NULL, "too many header modify"
8009 " actions to support");
8011 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8012 if (fdb_mirror_limit && modify_after_mirror)
8013 return rte_flow_error_set(error, EINVAL,
8014 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8015 "sample before modify action is not supported");
8020 * Internal preparation function. Allocates the DV flow size,
8021 * this size is constant.
8024 * Pointer to the rte_eth_dev structure.
8026 * Pointer to the flow attributes.
8028 * Pointer to the list of items.
8029 * @param[in] actions
8030 * Pointer to the list of actions.
8032 * Pointer to the error structure.
8035 * Pointer to mlx5_flow object on success,
8036 * otherwise NULL and rte_errno is set.
8038 static struct mlx5_flow *
8039 flow_dv_prepare(struct rte_eth_dev *dev,
8040 const struct rte_flow_attr *attr __rte_unused,
8041 const struct rte_flow_item items[] __rte_unused,
8042 const struct rte_flow_action actions[] __rte_unused,
8043 struct rte_flow_error *error)
8045 uint32_t handle_idx = 0;
8046 struct mlx5_flow *dev_flow;
8047 struct mlx5_flow_handle *dev_handle;
8048 struct mlx5_priv *priv = dev->data->dev_private;
8049 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8052 wks->skip_matcher_reg = 0;
8054 wks->final_policy = NULL;
8055 /* In case of corrupting the memory. */
8056 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8057 rte_flow_error_set(error, ENOSPC,
8058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8059 "not free temporary device flow");
8062 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8065 rte_flow_error_set(error, ENOMEM,
8066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8067 "not enough memory to create flow handle");
8070 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8071 dev_flow = &wks->flows[wks->flow_idx++];
8072 memset(dev_flow, 0, sizeof(*dev_flow));
8073 dev_flow->handle = dev_handle;
8074 dev_flow->handle_idx = handle_idx;
8075 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8076 dev_flow->ingress = attr->ingress;
8077 dev_flow->dv.transfer = attr->transfer;
8081 #ifdef RTE_LIBRTE_MLX5_DEBUG
8083 * Sanity check for match mask and value. Similar to check_valid_spec() in
8084 * kernel driver. If unmasked bit is present in value, it returns failure.
8087 * pointer to match mask buffer.
8088 * @param match_value
8089 * pointer to match value buffer.
8092 * 0 if valid, -EINVAL otherwise.
8095 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8097 uint8_t *m = match_mask;
8098 uint8_t *v = match_value;
8101 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8104 "match_value differs from match_criteria"
8105 " %p[%u] != %p[%u]",
8106 match_value, i, match_mask, i);
8115 * Add match of ip_version.
8119 * @param[in] headers_v
8120 * Values header pointer.
8121 * @param[in] headers_m
8122 * Masks header pointer.
8123 * @param[in] ip_version
8124 * The IP version to set.
8127 flow_dv_set_match_ip_version(uint32_t group,
8133 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8135 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8137 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8139 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8143 * Add Ethernet item to matcher and to the value.
8145 * @param[in, out] matcher
8147 * @param[in, out] key
8148 * Flow matcher value.
8150 * Flow pattern to translate.
8152 * Item is inner pattern.
8155 flow_dv_translate_item_eth(void *matcher, void *key,
8156 const struct rte_flow_item *item, int inner,
8159 const struct rte_flow_item_eth *eth_m = item->mask;
8160 const struct rte_flow_item_eth *eth_v = item->spec;
8161 const struct rte_flow_item_eth nic_mask = {
8162 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8163 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8164 .type = RTE_BE16(0xffff),
8177 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8179 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8181 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8183 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8185 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8186 ð_m->dst, sizeof(eth_m->dst));
8187 /* The value must be in the range of the mask. */
8188 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8189 for (i = 0; i < sizeof(eth_m->dst); ++i)
8190 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8191 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8192 ð_m->src, sizeof(eth_m->src));
8193 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8194 /* The value must be in the range of the mask. */
8195 for (i = 0; i < sizeof(eth_m->dst); ++i)
8196 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8198 * HW supports match on one Ethertype, the Ethertype following the last
8199 * VLAN tag of the packet (see PRM).
8200 * Set match on ethertype only if ETH header is not followed by VLAN.
8201 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8202 * ethertype, and use ip_version field instead.
8203 * eCPRI over Ether layer will use type value 0xAEFE.
8205 if (eth_m->type == 0xFFFF) {
8206 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8207 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8208 switch (eth_v->type) {
8209 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8210 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8212 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8213 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8214 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8216 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8217 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8219 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8220 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8226 if (eth_m->has_vlan) {
8227 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8228 if (eth_v->has_vlan) {
8230 * Here, when also has_more_vlan field in VLAN item is
8231 * not set, only single-tagged packets will be matched.
8233 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8237 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8238 rte_be_to_cpu_16(eth_m->type));
8239 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8240 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8244 * Add VLAN item to matcher and to the value.
8246 * @param[in, out] dev_flow
8248 * @param[in, out] matcher
8250 * @param[in, out] key
8251 * Flow matcher value.
8253 * Flow pattern to translate.
8255 * Item is inner pattern.
8258 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8259 void *matcher, void *key,
8260 const struct rte_flow_item *item,
8261 int inner, uint32_t group)
8263 const struct rte_flow_item_vlan *vlan_m = item->mask;
8264 const struct rte_flow_item_vlan *vlan_v = item->spec;
8271 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8273 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8275 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8277 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8279 * This is workaround, masks are not supported,
8280 * and pre-validated.
8283 dev_flow->handle->vf_vlan.tag =
8284 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8287 * When VLAN item exists in flow, mark packet as tagged,
8288 * even if TCI is not specified.
8290 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8291 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8292 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8297 vlan_m = &rte_flow_item_vlan_mask;
8298 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8299 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8300 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8301 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8302 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8303 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8304 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8305 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8307 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8308 * ethertype, and use ip_version field instead.
8310 if (vlan_m->inner_type == 0xFFFF) {
8311 switch (vlan_v->inner_type) {
8312 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8313 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8314 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8317 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8318 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8320 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8321 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8327 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8328 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8329 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8330 /* Only one vlan_tag bit can be set. */
8331 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8335 rte_be_to_cpu_16(vlan_m->inner_type));
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8337 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8341 * Add IPV4 item to matcher and to the value.
8343 * @param[in, out] matcher
8345 * @param[in, out] key
8346 * Flow matcher value.
8348 * Flow pattern to translate.
8350 * Item is inner pattern.
8352 * The group to insert the rule.
8355 flow_dv_translate_item_ipv4(void *matcher, void *key,
8356 const struct rte_flow_item *item,
8357 int inner, uint32_t group)
8359 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8360 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8361 const struct rte_flow_item_ipv4 nic_mask = {
8363 .src_addr = RTE_BE32(0xffffffff),
8364 .dst_addr = RTE_BE32(0xffffffff),
8365 .type_of_service = 0xff,
8366 .next_proto_id = 0xff,
8367 .time_to_live = 0xff,
8374 uint8_t tos, ihl_m, ihl_v;
8377 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8379 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8381 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8383 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8385 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8390 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8391 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8392 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8393 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8394 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8395 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8396 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8397 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8398 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8399 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8400 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8401 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8402 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8403 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8404 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8405 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8406 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8407 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8408 ipv4_m->hdr.type_of_service);
8409 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8410 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8411 ipv4_m->hdr.type_of_service >> 2);
8412 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8413 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8414 ipv4_m->hdr.next_proto_id);
8415 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8416 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8417 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8418 ipv4_m->hdr.time_to_live);
8419 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8420 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8421 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8422 !!(ipv4_m->hdr.fragment_offset));
8423 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8424 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8428 * Add IPV6 item to matcher and to the value.
8430 * @param[in, out] matcher
8432 * @param[in, out] key
8433 * Flow matcher value.
8435 * Flow pattern to translate.
8437 * Item is inner pattern.
8439 * The group to insert the rule.
8442 flow_dv_translate_item_ipv6(void *matcher, void *key,
8443 const struct rte_flow_item *item,
8444 int inner, uint32_t group)
8446 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8447 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8448 const struct rte_flow_item_ipv6 nic_mask = {
8451 "\xff\xff\xff\xff\xff\xff\xff\xff"
8452 "\xff\xff\xff\xff\xff\xff\xff\xff",
8454 "\xff\xff\xff\xff\xff\xff\xff\xff"
8455 "\xff\xff\xff\xff\xff\xff\xff\xff",
8456 .vtc_flow = RTE_BE32(0xffffffff),
8463 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8464 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8473 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8475 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8477 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8479 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8481 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8486 size = sizeof(ipv6_m->hdr.dst_addr);
8487 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8488 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8489 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8490 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8491 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8492 for (i = 0; i < size; ++i)
8493 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8494 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8495 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8496 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8497 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8498 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8499 for (i = 0; i < size; ++i)
8500 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8502 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8503 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8504 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8506 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8510 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8512 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8515 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8517 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8521 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8523 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8524 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8526 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8527 ipv6_m->hdr.hop_limits);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8529 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8531 !!(ipv6_m->has_frag_ext));
8532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8533 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8537 * Add IPV6 fragment extension item to matcher and to the value.
8539 * @param[in, out] matcher
8541 * @param[in, out] key
8542 * Flow matcher value.
8544 * Flow pattern to translate.
8546 * Item is inner pattern.
8549 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8550 const struct rte_flow_item *item,
8553 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8554 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8555 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8557 .next_header = 0xff,
8558 .frag_data = RTE_BE16(0xffff),
8565 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8567 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8569 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8571 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8573 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8574 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8576 if (!ipv6_frag_ext_v)
8578 if (!ipv6_frag_ext_m)
8579 ipv6_frag_ext_m = &nic_mask;
8580 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8581 ipv6_frag_ext_m->hdr.next_header);
8582 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8583 ipv6_frag_ext_v->hdr.next_header &
8584 ipv6_frag_ext_m->hdr.next_header);
8588 * Add TCP item to matcher and to the value.
8590 * @param[in, out] matcher
8592 * @param[in, out] key
8593 * Flow matcher value.
8595 * Flow pattern to translate.
8597 * Item is inner pattern.
8600 flow_dv_translate_item_tcp(void *matcher, void *key,
8601 const struct rte_flow_item *item,
8604 const struct rte_flow_item_tcp *tcp_m = item->mask;
8605 const struct rte_flow_item_tcp *tcp_v = item->spec;
8610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8612 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8614 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8616 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8618 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8619 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8623 tcp_m = &rte_flow_item_tcp_mask;
8624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8625 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8626 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8627 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8628 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8629 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8630 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8631 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8632 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8633 tcp_m->hdr.tcp_flags);
8634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8635 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8639 * Add UDP item to matcher and to the value.
8641 * @param[in, out] matcher
8643 * @param[in, out] key
8644 * Flow matcher value.
8646 * Flow pattern to translate.
8648 * Item is inner pattern.
8651 flow_dv_translate_item_udp(void *matcher, void *key,
8652 const struct rte_flow_item *item,
8655 const struct rte_flow_item_udp *udp_m = item->mask;
8656 const struct rte_flow_item_udp *udp_v = item->spec;
8661 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8663 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8667 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8674 udp_m = &rte_flow_item_udp_mask;
8675 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8676 rte_be_to_cpu_16(udp_m->hdr.src_port));
8677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8678 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8680 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8682 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8686 * Add GRE optional Key item to matcher and to the value.
8688 * @param[in, out] matcher
8690 * @param[in, out] key
8691 * Flow matcher value.
8693 * Flow pattern to translate.
8695 * Item is inner pattern.
8698 flow_dv_translate_item_gre_key(void *matcher, void *key,
8699 const struct rte_flow_item *item)
8701 const rte_be32_t *key_m = item->mask;
8702 const rte_be32_t *key_v = item->spec;
8703 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8704 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8705 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8707 /* GRE K bit must be on and should already be validated */
8708 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8709 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8713 key_m = &gre_key_default_mask;
8714 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8715 rte_be_to_cpu_32(*key_m) >> 8);
8716 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8717 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8718 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8719 rte_be_to_cpu_32(*key_m) & 0xFF);
8720 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8721 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8725 * Add GRE item to matcher and to the value.
8727 * @param[in, out] matcher
8729 * @param[in, out] key
8730 * Flow matcher value.
8732 * Flow pattern to translate.
8734 * Item is inner pattern.
8737 flow_dv_translate_item_gre(void *matcher, void *key,
8738 const struct rte_flow_item *item,
8741 const struct rte_flow_item_gre *gre_m = item->mask;
8742 const struct rte_flow_item_gre *gre_v = item->spec;
8745 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8746 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8753 uint16_t s_present:1;
8754 uint16_t k_present:1;
8755 uint16_t rsvd_bit1:1;
8756 uint16_t c_present:1;
8760 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8763 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8765 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8769 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8771 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8772 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8776 gre_m = &rte_flow_item_gre_mask;
8777 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8778 rte_be_to_cpu_16(gre_m->protocol));
8779 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8780 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8781 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8782 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8783 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8784 gre_crks_rsvd0_ver_m.c_present);
8785 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8786 gre_crks_rsvd0_ver_v.c_present &
8787 gre_crks_rsvd0_ver_m.c_present);
8788 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8789 gre_crks_rsvd0_ver_m.k_present);
8790 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8791 gre_crks_rsvd0_ver_v.k_present &
8792 gre_crks_rsvd0_ver_m.k_present);
8793 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8794 gre_crks_rsvd0_ver_m.s_present);
8795 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8796 gre_crks_rsvd0_ver_v.s_present &
8797 gre_crks_rsvd0_ver_m.s_present);
8801 * Add NVGRE item to matcher and to the value.
8803 * @param[in, out] matcher
8805 * @param[in, out] key
8806 * Flow matcher value.
8808 * Flow pattern to translate.
8810 * Item is inner pattern.
8813 flow_dv_translate_item_nvgre(void *matcher, void *key,
8814 const struct rte_flow_item *item,
8817 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8818 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8819 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8820 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8821 const char *tni_flow_id_m;
8822 const char *tni_flow_id_v;
8828 /* For NVGRE, GRE header fields must be set with defined values. */
8829 const struct rte_flow_item_gre gre_spec = {
8830 .c_rsvd0_ver = RTE_BE16(0x2000),
8831 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8833 const struct rte_flow_item_gre gre_mask = {
8834 .c_rsvd0_ver = RTE_BE16(0xB000),
8835 .protocol = RTE_BE16(UINT16_MAX),
8837 const struct rte_flow_item gre_item = {
8842 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8846 nvgre_m = &rte_flow_item_nvgre_mask;
8847 tni_flow_id_m = (const char *)nvgre_m->tni;
8848 tni_flow_id_v = (const char *)nvgre_v->tni;
8849 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8850 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8851 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8852 memcpy(gre_key_m, tni_flow_id_m, size);
8853 for (i = 0; i < size; ++i)
8854 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8858 * Add VXLAN item to matcher and to the value.
8861 * Pointer to the Ethernet device structure.
8863 * Flow rule attributes.
8864 * @param[in, out] matcher
8866 * @param[in, out] key
8867 * Flow matcher value.
8869 * Flow pattern to translate.
8871 * Item is inner pattern.
8874 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8875 const struct rte_flow_attr *attr,
8876 void *matcher, void *key,
8877 const struct rte_flow_item *item,
8880 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8881 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8886 uint32_t *tunnel_header_v;
8887 uint32_t *tunnel_header_m;
8889 struct mlx5_priv *priv = dev->data->dev_private;
8890 const struct rte_flow_item_vxlan nic_mask = {
8891 .vni = "\xff\xff\xff",
8896 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8898 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8900 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8902 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8904 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8905 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8906 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8907 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8908 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8910 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8914 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8915 (attr->group && !priv->sh->misc5_cap))
8916 vxlan_m = &rte_flow_item_vxlan_mask;
8918 vxlan_m = &nic_mask;
8920 if ((priv->sh->steering_format_version ==
8921 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8922 dport != MLX5_UDP_PORT_VXLAN) ||
8923 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8924 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8931 misc_m = MLX5_ADDR_OF(fte_match_param,
8932 matcher, misc_parameters);
8933 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8934 size = sizeof(vxlan_m->vni);
8935 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8936 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8937 memcpy(vni_m, vxlan_m->vni, size);
8938 for (i = 0; i < size; ++i)
8939 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8942 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8943 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8944 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8947 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8950 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8951 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8952 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8953 if (*tunnel_header_v)
8954 *tunnel_header_m = vxlan_m->vni[0] |
8955 vxlan_m->vni[1] << 8 |
8956 vxlan_m->vni[2] << 16;
8958 *tunnel_header_m = 0x0;
8959 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8960 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8961 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8965 * Add VXLAN-GPE item to matcher and to the value.
8967 * @param[in, out] matcher
8969 * @param[in, out] key
8970 * Flow matcher value.
8972 * Flow pattern to translate.
8974 * Item is inner pattern.
8978 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8979 const struct rte_flow_item *item,
8980 const uint64_t pattern_flags)
8982 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
8983 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8984 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8985 /* The item was validated to be on the outer side */
8986 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8987 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8989 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8991 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8993 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8995 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8996 int i, size = sizeof(vxlan_m->vni);
8997 uint8_t flags_m = 0xff;
8998 uint8_t flags_v = 0xc;
8999 uint8_t m_protocol, v_protocol;
9001 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9002 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9003 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9004 MLX5_UDP_PORT_VXLAN_GPE);
9007 vxlan_v = &dummy_vxlan_gpe_hdr;
9008 vxlan_m = &dummy_vxlan_gpe_hdr;
9011 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9013 memcpy(vni_m, vxlan_m->vni, size);
9014 for (i = 0; i < size; ++i)
9015 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9016 if (vxlan_m->flags) {
9017 flags_m = vxlan_m->flags;
9018 flags_v = vxlan_v->flags;
9020 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9021 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9022 m_protocol = vxlan_m->protocol;
9023 v_protocol = vxlan_v->protocol;
9026 /* Force next protocol to ensure next headers parsing. */
9027 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9028 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9029 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9030 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9031 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9032 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9034 MLX5_SET(fte_match_set_misc3, misc_m,
9035 outer_vxlan_gpe_next_protocol, m_protocol);
9036 MLX5_SET(fte_match_set_misc3, misc_v,
9037 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9041 * Add Geneve item to matcher and to the value.
9043 * @param[in, out] matcher
9045 * @param[in, out] key
9046 * Flow matcher value.
9048 * Flow pattern to translate.
9050 * Item is inner pattern.
9054 flow_dv_translate_item_geneve(void *matcher, void *key,
9055 const struct rte_flow_item *item,
9056 uint64_t pattern_flags)
9058 static const struct rte_flow_item_geneve empty_geneve = {0,};
9059 const struct rte_flow_item_geneve *geneve_m = item->mask;
9060 const struct rte_flow_item_geneve *geneve_v = item->spec;
9061 /* GENEVE flow item validation allows single tunnel item */
9062 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9063 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9064 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9065 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9068 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9069 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9070 size_t size = sizeof(geneve_m->vni), i;
9071 uint16_t protocol_m, protocol_v;
9073 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9074 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9075 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9076 MLX5_UDP_PORT_GENEVE);
9079 geneve_v = &empty_geneve;
9080 geneve_m = &empty_geneve;
9083 geneve_m = &rte_flow_item_geneve_mask;
9085 memcpy(vni_m, geneve_m->vni, size);
9086 for (i = 0; i < size; ++i)
9087 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9088 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9089 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9090 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9091 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9092 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9093 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9094 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9095 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9096 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9097 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9098 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9099 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9100 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9102 /* Force next protocol to prevent matchers duplication */
9103 protocol_m = 0xFFFF;
9104 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9106 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9107 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9108 protocol_m & protocol_v);
9112 * Create Geneve TLV option resource.
9114 * @param dev[in, out]
9115 * Pointer to rte_eth_dev structure.
9116 * @param[in, out] tag_be24
9117 * Tag value in big endian then R-shift 8.
9118 * @parm[in, out] dev_flow
9119 * Pointer to the dev_flow.
9121 * pointer to error structure.
9124 * 0 on success otherwise -errno and errno is set.
9128 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9129 const struct rte_flow_item *item,
9130 struct rte_flow_error *error)
9132 struct mlx5_priv *priv = dev->data->dev_private;
9133 struct mlx5_dev_ctx_shared *sh = priv->sh;
9134 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9135 sh->geneve_tlv_option_resource;
9136 struct mlx5_devx_obj *obj;
9137 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9142 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9143 if (geneve_opt_resource != NULL) {
9144 if (geneve_opt_resource->option_class ==
9145 geneve_opt_v->option_class &&
9146 geneve_opt_resource->option_type ==
9147 geneve_opt_v->option_type &&
9148 geneve_opt_resource->length ==
9149 geneve_opt_v->option_len) {
9150 /* We already have GENVE TLV option obj allocated. */
9151 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9154 ret = rte_flow_error_set(error, ENOMEM,
9155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9156 "Only one GENEVE TLV option supported");
9160 /* Create a GENEVE TLV object and resource. */
9161 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9162 geneve_opt_v->option_class,
9163 geneve_opt_v->option_type,
9164 geneve_opt_v->option_len);
9166 ret = rte_flow_error_set(error, ENODATA,
9167 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9168 "Failed to create GENEVE TLV Devx object");
9171 sh->geneve_tlv_option_resource =
9172 mlx5_malloc(MLX5_MEM_ZERO,
9173 sizeof(*geneve_opt_resource),
9175 if (!sh->geneve_tlv_option_resource) {
9176 claim_zero(mlx5_devx_cmd_destroy(obj));
9177 ret = rte_flow_error_set(error, ENOMEM,
9178 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9179 "GENEVE TLV object memory allocation failed");
9182 geneve_opt_resource = sh->geneve_tlv_option_resource;
9183 geneve_opt_resource->obj = obj;
9184 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9185 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9186 geneve_opt_resource->length = geneve_opt_v->option_len;
9187 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9191 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9196 * Add Geneve TLV option item to matcher.
9198 * @param[in, out] dev
9199 * Pointer to rte_eth_dev structure.
9200 * @param[in, out] matcher
9202 * @param[in, out] key
9203 * Flow matcher value.
9205 * Flow pattern to translate.
9207 * Pointer to error structure.
9210 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9211 void *key, const struct rte_flow_item *item,
9212 struct rte_flow_error *error)
9214 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9215 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9216 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9217 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9218 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9220 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9221 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9227 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9228 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9231 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9235 * Set the option length in GENEVE header if not requested.
9236 * The GENEVE TLV option length is expressed by the option length field
9237 * in the GENEVE header.
9238 * If the option length was not requested but the GENEVE TLV option item
9239 * is present we set the option length field implicitly.
9241 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9242 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9243 MLX5_GENEVE_OPTLEN_MASK);
9244 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9245 geneve_opt_v->option_len + 1);
9247 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9248 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9250 if (geneve_opt_v->data) {
9251 memcpy(&opt_data_key, geneve_opt_v->data,
9252 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9253 sizeof(opt_data_key)));
9254 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9255 sizeof(opt_data_key));
9256 memcpy(&opt_data_mask, geneve_opt_m->data,
9257 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9258 sizeof(opt_data_mask)));
9259 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9260 sizeof(opt_data_mask));
9261 MLX5_SET(fte_match_set_misc3, misc3_m,
9262 geneve_tlv_option_0_data,
9263 rte_be_to_cpu_32(opt_data_mask));
9264 MLX5_SET(fte_match_set_misc3, misc3_v,
9265 geneve_tlv_option_0_data,
9266 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9272 * Add MPLS item to matcher and to the value.
9274 * @param[in, out] matcher
9276 * @param[in, out] key
9277 * Flow matcher value.
9279 * Flow pattern to translate.
9280 * @param[in] prev_layer
9281 * The protocol layer indicated in previous item.
9283 * Item is inner pattern.
9286 flow_dv_translate_item_mpls(void *matcher, void *key,
9287 const struct rte_flow_item *item,
9288 uint64_t prev_layer,
9291 const uint32_t *in_mpls_m = item->mask;
9292 const uint32_t *in_mpls_v = item->spec;
9293 uint32_t *out_mpls_m = 0;
9294 uint32_t *out_mpls_v = 0;
9295 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9296 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9297 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9299 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9300 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9301 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9303 switch (prev_layer) {
9304 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9305 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9307 MLX5_UDP_PORT_MPLS);
9309 case MLX5_FLOW_LAYER_GRE:
9311 case MLX5_FLOW_LAYER_GRE_KEY:
9312 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9313 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9314 RTE_ETHER_TYPE_MPLS);
9322 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9323 switch (prev_layer) {
9324 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9326 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9327 outer_first_mpls_over_udp);
9329 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9330 outer_first_mpls_over_udp);
9332 case MLX5_FLOW_LAYER_GRE:
9334 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9335 outer_first_mpls_over_gre);
9337 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9338 outer_first_mpls_over_gre);
9341 /* Inner MPLS not over GRE is not supported. */
9344 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9348 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9354 if (out_mpls_m && out_mpls_v) {
9355 *out_mpls_m = *in_mpls_m;
9356 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9361 * Add metadata register item to matcher
9363 * @param[in, out] matcher
9365 * @param[in, out] key
9366 * Flow matcher value.
9367 * @param[in] reg_type
9368 * Type of device metadata register
9375 flow_dv_match_meta_reg(void *matcher, void *key,
9376 enum modify_reg reg_type,
9377 uint32_t data, uint32_t mask)
9380 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9382 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9388 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9389 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9392 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9393 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9397 * The metadata register C0 field might be divided into
9398 * source vport index and META item value, we should set
9399 * this field according to specified mask, not as whole one.
9401 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9403 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9404 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9407 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9410 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9411 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9414 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9415 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9418 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9419 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9422 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9423 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9426 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9427 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9430 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9431 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9434 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9435 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9444 * Add MARK item to matcher
9447 * The device to configure through.
9448 * @param[in, out] matcher
9450 * @param[in, out] key
9451 * Flow matcher value.
9453 * Flow pattern to translate.
9456 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9457 void *matcher, void *key,
9458 const struct rte_flow_item *item)
9460 struct mlx5_priv *priv = dev->data->dev_private;
9461 const struct rte_flow_item_mark *mark;
9465 mark = item->mask ? (const void *)item->mask :
9466 &rte_flow_item_mark_mask;
9467 mask = mark->id & priv->sh->dv_mark_mask;
9468 mark = (const void *)item->spec;
9470 value = mark->id & priv->sh->dv_mark_mask & mask;
9472 enum modify_reg reg;
9474 /* Get the metadata register index for the mark. */
9475 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9476 MLX5_ASSERT(reg > 0);
9477 if (reg == REG_C_0) {
9478 struct mlx5_priv *priv = dev->data->dev_private;
9479 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9480 uint32_t shl_c0 = rte_bsf32(msk_c0);
9486 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9491 * Add META item to matcher
9494 * The devich to configure through.
9495 * @param[in, out] matcher
9497 * @param[in, out] key
9498 * Flow matcher value.
9500 * Attributes of flow that includes this item.
9502 * Flow pattern to translate.
9505 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9506 void *matcher, void *key,
9507 const struct rte_flow_attr *attr,
9508 const struct rte_flow_item *item)
9510 const struct rte_flow_item_meta *meta_m;
9511 const struct rte_flow_item_meta *meta_v;
9513 meta_m = (const void *)item->mask;
9515 meta_m = &rte_flow_item_meta_mask;
9516 meta_v = (const void *)item->spec;
9519 uint32_t value = meta_v->data;
9520 uint32_t mask = meta_m->data;
9522 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9525 MLX5_ASSERT(reg != REG_NON);
9526 if (reg == REG_C_0) {
9527 struct mlx5_priv *priv = dev->data->dev_private;
9528 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9529 uint32_t shl_c0 = rte_bsf32(msk_c0);
9535 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9540 * Add vport metadata Reg C0 item to matcher
9542 * @param[in, out] matcher
9544 * @param[in, out] key
9545 * Flow matcher value.
9547 * Flow pattern to translate.
9550 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9551 uint32_t value, uint32_t mask)
9553 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9557 * Add tag item to matcher
9560 * The devich to configure through.
9561 * @param[in, out] matcher
9563 * @param[in, out] key
9564 * Flow matcher value.
9566 * Flow pattern to translate.
9569 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9570 void *matcher, void *key,
9571 const struct rte_flow_item *item)
9573 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9574 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9575 uint32_t mask, value;
9578 value = tag_v->data;
9579 mask = tag_m ? tag_m->data : UINT32_MAX;
9580 if (tag_v->id == REG_C_0) {
9581 struct mlx5_priv *priv = dev->data->dev_private;
9582 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9583 uint32_t shl_c0 = rte_bsf32(msk_c0);
9589 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9593 * Add TAG item to matcher
9596 * The devich to configure through.
9597 * @param[in, out] matcher
9599 * @param[in, out] key
9600 * Flow matcher value.
9602 * Flow pattern to translate.
9605 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9606 void *matcher, void *key,
9607 const struct rte_flow_item *item)
9609 const struct rte_flow_item_tag *tag_v = item->spec;
9610 const struct rte_flow_item_tag *tag_m = item->mask;
9611 enum modify_reg reg;
9614 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9615 /* Get the metadata register index for the tag. */
9616 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9617 MLX5_ASSERT(reg > 0);
9618 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9622 * Add source vport match to the specified matcher.
9624 * @param[in, out] matcher
9626 * @param[in, out] key
9627 * Flow matcher value.
9629 * Source vport value to match
9634 flow_dv_translate_item_source_vport(void *matcher, void *key,
9635 int16_t port, uint16_t mask)
9637 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9638 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9640 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9641 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9645 * Translate port-id item to eswitch match on port-id.
9648 * The devich to configure through.
9649 * @param[in, out] matcher
9651 * @param[in, out] key
9652 * Flow matcher value.
9654 * Flow pattern to translate.
9659 * 0 on success, a negative errno value otherwise.
9662 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9663 void *key, const struct rte_flow_item *item,
9664 const struct rte_flow_attr *attr)
9666 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9667 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9668 struct mlx5_priv *priv;
9671 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9672 flow_dv_translate_item_source_vport(matcher, key,
9673 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9676 mask = pid_m ? pid_m->id : 0xffff;
9677 id = pid_v ? pid_v->id : dev->data->port_id;
9678 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9682 * Translate to vport field or to metadata, depending on mode.
9683 * Kernel can use either misc.source_port or half of C0 metadata
9686 if (priv->vport_meta_mask) {
9688 * Provide the hint for SW steering library
9689 * to insert the flow into ingress domain and
9690 * save the extra vport match.
9692 if (mask == 0xffff && priv->vport_id == 0xffff &&
9693 priv->pf_bond < 0 && attr->transfer)
9694 flow_dv_translate_item_source_vport
9695 (matcher, key, priv->vport_id, mask);
9697 * We should always set the vport metadata register,
9698 * otherwise the SW steering library can drop
9699 * the rule if wire vport metadata value is not zero,
9700 * it depends on kernel configuration.
9702 flow_dv_translate_item_meta_vport(matcher, key,
9703 priv->vport_meta_tag,
9704 priv->vport_meta_mask);
9706 flow_dv_translate_item_source_vport(matcher, key,
9707 priv->vport_id, mask);
9713 * Add ICMP6 item to matcher and to the value.
9715 * @param[in, out] matcher
9717 * @param[in, out] key
9718 * Flow matcher value.
9720 * Flow pattern to translate.
9722 * Item is inner pattern.
9725 flow_dv_translate_item_icmp6(void *matcher, void *key,
9726 const struct rte_flow_item *item,
9729 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9730 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9733 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9735 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9737 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9739 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9741 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9743 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9745 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9750 icmp6_m = &rte_flow_item_icmp6_mask;
9751 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9752 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9753 icmp6_v->type & icmp6_m->type);
9754 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9755 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9756 icmp6_v->code & icmp6_m->code);
9760 * Add ICMP item to matcher and to the value.
9762 * @param[in, out] matcher
9764 * @param[in, out] key
9765 * Flow matcher value.
9767 * Flow pattern to translate.
9769 * Item is inner pattern.
9772 flow_dv_translate_item_icmp(void *matcher, void *key,
9773 const struct rte_flow_item *item,
9776 const struct rte_flow_item_icmp *icmp_m = item->mask;
9777 const struct rte_flow_item_icmp *icmp_v = item->spec;
9778 uint32_t icmp_header_data_m = 0;
9779 uint32_t icmp_header_data_v = 0;
9782 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9784 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9786 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9788 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9790 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9792 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9794 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9795 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9799 icmp_m = &rte_flow_item_icmp_mask;
9800 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9801 icmp_m->hdr.icmp_type);
9802 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9803 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9804 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9805 icmp_m->hdr.icmp_code);
9806 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9807 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9808 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9809 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9810 if (icmp_header_data_m) {
9811 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9812 icmp_header_data_v |=
9813 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9814 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9815 icmp_header_data_m);
9816 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9817 icmp_header_data_v & icmp_header_data_m);
9822 * Add GTP item to matcher and to the value.
9824 * @param[in, out] matcher
9826 * @param[in, out] key
9827 * Flow matcher value.
9829 * Flow pattern to translate.
9831 * Item is inner pattern.
9834 flow_dv_translate_item_gtp(void *matcher, void *key,
9835 const struct rte_flow_item *item, int inner)
9837 const struct rte_flow_item_gtp *gtp_m = item->mask;
9838 const struct rte_flow_item_gtp *gtp_v = item->spec;
9841 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9843 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9844 uint16_t dport = RTE_GTPU_UDP_PORT;
9847 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9849 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9851 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9853 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9855 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9856 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9857 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9862 gtp_m = &rte_flow_item_gtp_mask;
9863 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9864 gtp_m->v_pt_rsv_flags);
9865 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9866 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9867 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9868 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9869 gtp_v->msg_type & gtp_m->msg_type);
9870 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9871 rte_be_to_cpu_32(gtp_m->teid));
9872 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9873 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9877 * Add GTP PSC item to matcher.
9879 * @param[in, out] matcher
9881 * @param[in, out] key
9882 * Flow matcher value.
9884 * Flow pattern to translate.
9887 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9888 const struct rte_flow_item *item)
9890 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9891 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9892 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9894 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9900 uint8_t next_ext_header_type;
9905 /* Always set E-flag match on one, regardless of GTP item settings. */
9906 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9907 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9908 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9909 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9910 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9911 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9912 /*Set next extension header type. */
9915 dw_2.next_ext_header_type = 0xff;
9916 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9917 rte_cpu_to_be_32(dw_2.w32));
9920 dw_2.next_ext_header_type = 0x85;
9921 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9922 rte_cpu_to_be_32(dw_2.w32));
9934 /*Set extension header PDU type and Qos. */
9936 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9938 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9939 dw_0.qfi = gtp_psc_m->hdr.qfi;
9940 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9941 rte_cpu_to_be_32(dw_0.w32));
9943 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9944 gtp_psc_m->hdr.type);
9945 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9946 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9947 rte_cpu_to_be_32(dw_0.w32));
9953 * Add eCPRI item to matcher and to the value.
9956 * The devich to configure through.
9957 * @param[in, out] matcher
9959 * @param[in, out] key
9960 * Flow matcher value.
9962 * Flow pattern to translate.
9963 * @param[in] last_item
9967 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9968 void *key, const struct rte_flow_item *item,
9971 struct mlx5_priv *priv = dev->data->dev_private;
9972 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9973 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9974 struct rte_ecpri_common_hdr common;
9975 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9977 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9983 * In case of eCPRI over Ethernet, if EtherType is not specified,
9984 * match on eCPRI EtherType implicitly.
9986 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
9987 void *hdrs_m, *hdrs_v, *l2m, *l2v;
9989 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9990 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9991 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
9992 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
9993 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
9994 *(uint16_t *)l2m = UINT16_MAX;
9995 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10001 ecpri_m = &rte_flow_item_ecpri_mask;
10003 * Maximal four DW samples are supported in a single matching now.
10004 * Two are used now for a eCPRI matching:
10005 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10006 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10009 if (!ecpri_m->hdr.common.u32)
10011 samples = priv->sh->ecpri_parser.ids;
10012 /* Need to take the whole DW as the mask to fill the entry. */
10013 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10014 prog_sample_field_value_0);
10015 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10016 prog_sample_field_value_0);
10017 /* Already big endian (network order) in the header. */
10018 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10019 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10020 /* Sample#0, used for matching type, offset 0. */
10021 MLX5_SET(fte_match_set_misc4, misc4_m,
10022 prog_sample_field_id_0, samples[0]);
10023 /* It makes no sense to set the sample ID in the mask field. */
10024 MLX5_SET(fte_match_set_misc4, misc4_v,
10025 prog_sample_field_id_0, samples[0]);
10027 * Checking if message body part needs to be matched.
10028 * Some wildcard rules only matching type field should be supported.
10030 if (ecpri_m->hdr.dummy[0]) {
10031 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10032 switch (common.type) {
10033 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10034 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10035 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10036 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10037 prog_sample_field_value_1);
10038 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10039 prog_sample_field_value_1);
10040 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10041 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10042 ecpri_m->hdr.dummy[0];
10043 /* Sample#1, to match message body, offset 4. */
10044 MLX5_SET(fte_match_set_misc4, misc4_m,
10045 prog_sample_field_id_1, samples[1]);
10046 MLX5_SET(fte_match_set_misc4, misc4_v,
10047 prog_sample_field_id_1, samples[1]);
10050 /* Others, do not match any sample ID. */
10057 * Add connection tracking status item to matcher
10060 * The devich to configure through.
10061 * @param[in, out] matcher
10063 * @param[in, out] key
10064 * Flow matcher value.
10066 * Flow pattern to translate.
10069 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10070 void *matcher, void *key,
10071 const struct rte_flow_item *item)
10073 uint32_t reg_value = 0;
10075 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10076 uint32_t reg_mask = 0;
10077 const struct rte_flow_item_conntrack *spec = item->spec;
10078 const struct rte_flow_item_conntrack *mask = item->mask;
10080 struct rte_flow_error error;
10083 mask = &rte_flow_item_conntrack_mask;
10084 if (!spec || !mask->flags)
10086 flags = spec->flags & mask->flags;
10087 /* The conflict should be checked in the validation. */
10088 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10089 reg_value |= MLX5_CT_SYNDROME_VALID;
10090 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10091 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10092 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10093 reg_value |= MLX5_CT_SYNDROME_INVALID;
10094 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10095 reg_value |= MLX5_CT_SYNDROME_TRAP;
10096 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10097 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10098 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10099 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10100 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10102 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10103 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10104 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10105 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10106 /* The REG_C_x value could be saved during startup. */
10107 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10108 if (reg_id == REG_NON)
10110 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10111 reg_value, reg_mask);
10115 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10116 const struct rte_flow_item *item,
10117 struct mlx5_flow *dev_flow, bool is_inner)
10119 const struct rte_flow_item_flex *spec =
10120 (const struct rte_flow_item_flex *)item->spec;
10121 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10123 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10126 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10127 /* Don't count both inner and outer flex items in one rule. */
10128 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10129 MLX5_ASSERT(false);
10130 dev_flow->handle->flex_item |= RTE_BIT32(index);
10132 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10135 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10137 #define HEADER_IS_ZERO(match_criteria, headers) \
10138 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10139 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10142 * Calculate flow matcher enable bitmap.
10144 * @param match_criteria
10145 * Pointer to flow matcher criteria.
10148 * Bitmap of enabled fields.
10151 flow_dv_matcher_enable(uint32_t *match_criteria)
10153 uint8_t match_criteria_enable;
10155 match_criteria_enable =
10156 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10157 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10158 match_criteria_enable |=
10159 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10160 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10161 match_criteria_enable |=
10162 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10163 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10164 match_criteria_enable |=
10165 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10166 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10167 match_criteria_enable |=
10168 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10169 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10170 match_criteria_enable |=
10171 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10172 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10173 match_criteria_enable |=
10174 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10175 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10176 return match_criteria_enable;
10180 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10183 * Check flow matching criteria first, subtract misc5/4 length if flow
10184 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10185 * misc5/4 are not supported, and matcher creation failure is expected
10186 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10187 * misc5 is right after misc4.
10189 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10190 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10191 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10192 if (!(match_criteria & (1 <<
10193 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10194 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10199 static struct mlx5_list_entry *
10200 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10201 struct mlx5_list_entry *entry, void *cb_ctx)
10203 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10204 struct mlx5_flow_dv_matcher *ref = ctx->data;
10205 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10206 typeof(*tbl), tbl);
10207 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10212 rte_flow_error_set(ctx->error, ENOMEM,
10213 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10214 "cannot create matcher");
10217 memcpy(resource, entry, sizeof(*resource));
10218 resource->tbl = &tbl->tbl;
10219 return &resource->entry;
10223 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10224 struct mlx5_list_entry *entry)
10229 struct mlx5_list_entry *
10230 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10232 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10233 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10234 struct rte_eth_dev *dev = ctx->dev;
10235 struct mlx5_flow_tbl_data_entry *tbl_data;
10236 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10237 struct rte_flow_error *error = ctx->error;
10238 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10239 struct mlx5_flow_tbl_resource *tbl;
10244 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10246 rte_flow_error_set(error, ENOMEM,
10247 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10249 "cannot allocate flow table data entry");
10252 tbl_data->idx = idx;
10253 tbl_data->tunnel = tt_prm->tunnel;
10254 tbl_data->group_id = tt_prm->group_id;
10255 tbl_data->external = !!tt_prm->external;
10256 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10257 tbl_data->is_egress = !!key.is_egress;
10258 tbl_data->is_transfer = !!key.is_fdb;
10259 tbl_data->dummy = !!key.dummy;
10260 tbl_data->level = key.level;
10261 tbl_data->id = key.id;
10262 tbl = &tbl_data->tbl;
10264 return &tbl_data->entry;
10266 domain = sh->fdb_domain;
10267 else if (key.is_egress)
10268 domain = sh->tx_domain;
10270 domain = sh->rx_domain;
10271 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10273 rte_flow_error_set(error, ENOMEM,
10274 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10275 NULL, "cannot create flow table object");
10276 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10279 if (key.level != 0) {
10280 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10281 (tbl->obj, &tbl_data->jump.action);
10283 rte_flow_error_set(error, ENOMEM,
10284 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10286 "cannot create flow jump action");
10287 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10288 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10292 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10293 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10294 key.level, key.id);
10295 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10296 flow_dv_matcher_create_cb,
10297 flow_dv_matcher_match_cb,
10298 flow_dv_matcher_remove_cb,
10299 flow_dv_matcher_clone_cb,
10300 flow_dv_matcher_clone_free_cb);
10301 if (!tbl_data->matchers) {
10302 rte_flow_error_set(error, ENOMEM,
10303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10305 "cannot create tbl matcher list");
10306 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10307 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10308 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10311 return &tbl_data->entry;
10315 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10318 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10319 struct mlx5_flow_tbl_data_entry *tbl_data =
10320 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10321 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10323 return tbl_data->level != key.level ||
10324 tbl_data->id != key.id ||
10325 tbl_data->dummy != key.dummy ||
10326 tbl_data->is_transfer != !!key.is_fdb ||
10327 tbl_data->is_egress != !!key.is_egress;
10330 struct mlx5_list_entry *
10331 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10334 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10335 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10336 struct mlx5_flow_tbl_data_entry *tbl_data;
10337 struct rte_flow_error *error = ctx->error;
10340 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10342 rte_flow_error_set(error, ENOMEM,
10343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10345 "cannot allocate flow table data entry");
10348 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10349 tbl_data->idx = idx;
10350 return &tbl_data->entry;
10354 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10356 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10357 struct mlx5_flow_tbl_data_entry *tbl_data =
10358 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10360 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10364 * Get a flow table.
10366 * @param[in, out] dev
10367 * Pointer to rte_eth_dev structure.
10368 * @param[in] table_level
10369 * Table level to use.
10370 * @param[in] egress
10371 * Direction of the table.
10372 * @param[in] transfer
10373 * E-Switch or NIC flow.
10375 * Dummy entry for dv API.
10376 * @param[in] table_id
10378 * @param[out] error
10379 * pointer to error structure.
10382 * Returns tables resource based on the index, NULL in case of failed.
10384 struct mlx5_flow_tbl_resource *
10385 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10386 uint32_t table_level, uint8_t egress,
10389 const struct mlx5_flow_tunnel *tunnel,
10390 uint32_t group_id, uint8_t dummy,
10392 struct rte_flow_error *error)
10394 struct mlx5_priv *priv = dev->data->dev_private;
10395 union mlx5_flow_tbl_key table_key = {
10397 .level = table_level,
10401 .is_fdb = !!transfer,
10402 .is_egress = !!egress,
10405 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10407 .group_id = group_id,
10408 .external = external,
10410 struct mlx5_flow_cb_ctx ctx = {
10413 .data = &table_key.v64,
10416 struct mlx5_list_entry *entry;
10417 struct mlx5_flow_tbl_data_entry *tbl_data;
10419 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10421 rte_flow_error_set(error, ENOMEM,
10422 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10423 "cannot get table");
10426 DRV_LOG(DEBUG, "table_level %u table_id %u "
10427 "tunnel %u group %u registered.",
10428 table_level, table_id,
10429 tunnel ? tunnel->tunnel_id : 0, group_id);
10430 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10431 return &tbl_data->tbl;
10435 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10437 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10438 struct mlx5_flow_tbl_data_entry *tbl_data =
10439 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10441 MLX5_ASSERT(entry && sh);
10442 if (tbl_data->jump.action)
10443 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10444 if (tbl_data->tbl.obj)
10445 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10446 if (tbl_data->tunnel_offload && tbl_data->external) {
10447 struct mlx5_list_entry *he;
10448 struct mlx5_hlist *tunnel_grp_hash;
10449 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10450 union tunnel_tbl_key tunnel_key = {
10451 .tunnel_id = tbl_data->tunnel ?
10452 tbl_data->tunnel->tunnel_id : 0,
10453 .group = tbl_data->group_id
10455 uint32_t table_level = tbl_data->level;
10456 struct mlx5_flow_cb_ctx ctx = {
10457 .data = (void *)&tunnel_key.val,
10460 tunnel_grp_hash = tbl_data->tunnel ?
10461 tbl_data->tunnel->groups :
10463 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10465 mlx5_hlist_unregister(tunnel_grp_hash, he);
10467 "table_level %u id %u tunnel %u group %u released.",
10471 tbl_data->tunnel->tunnel_id : 0,
10472 tbl_data->group_id);
10474 mlx5_list_destroy(tbl_data->matchers);
10475 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10479 * Release a flow table.
10482 * Pointer to device shared structure.
10484 * Table resource to be released.
10487 * Returns 0 if table was released, else return 1;
10490 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10491 struct mlx5_flow_tbl_resource *tbl)
10493 struct mlx5_flow_tbl_data_entry *tbl_data =
10494 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10498 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10502 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10503 struct mlx5_list_entry *entry, void *cb_ctx)
10505 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10506 struct mlx5_flow_dv_matcher *ref = ctx->data;
10507 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10510 return cur->crc != ref->crc ||
10511 cur->priority != ref->priority ||
10512 memcmp((const void *)cur->mask.buf,
10513 (const void *)ref->mask.buf, ref->mask.size);
10516 struct mlx5_list_entry *
10517 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10519 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10520 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10521 struct mlx5_flow_dv_matcher *ref = ctx->data;
10522 struct mlx5_flow_dv_matcher *resource;
10523 struct mlx5dv_flow_matcher_attr dv_attr = {
10524 .type = IBV_FLOW_ATTR_NORMAL,
10525 .match_mask = (void *)&ref->mask,
10527 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10528 typeof(*tbl), tbl);
10531 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10534 rte_flow_error_set(ctx->error, ENOMEM,
10535 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10536 "cannot create matcher");
10540 dv_attr.match_criteria_enable =
10541 flow_dv_matcher_enable(resource->mask.buf);
10542 __flow_dv_adjust_buf_size(&ref->mask.size,
10543 dv_attr.match_criteria_enable);
10544 dv_attr.priority = ref->priority;
10545 if (tbl->is_egress)
10546 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10547 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10549 &resource->matcher_object);
10551 mlx5_free(resource);
10552 rte_flow_error_set(ctx->error, ENOMEM,
10553 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10554 "cannot create matcher");
10557 return &resource->entry;
10561 * Register the flow matcher.
10563 * @param[in, out] dev
10564 * Pointer to rte_eth_dev structure.
10565 * @param[in, out] matcher
10566 * Pointer to flow matcher.
10567 * @param[in, out] key
10568 * Pointer to flow table key.
10569 * @parm[in, out] dev_flow
10570 * Pointer to the dev_flow.
10571 * @param[out] error
10572 * pointer to error structure.
10575 * 0 on success otherwise -errno and errno is set.
10578 flow_dv_matcher_register(struct rte_eth_dev *dev,
10579 struct mlx5_flow_dv_matcher *ref,
10580 union mlx5_flow_tbl_key *key,
10581 struct mlx5_flow *dev_flow,
10582 const struct mlx5_flow_tunnel *tunnel,
10584 struct rte_flow_error *error)
10586 struct mlx5_list_entry *entry;
10587 struct mlx5_flow_dv_matcher *resource;
10588 struct mlx5_flow_tbl_resource *tbl;
10589 struct mlx5_flow_tbl_data_entry *tbl_data;
10590 struct mlx5_flow_cb_ctx ctx = {
10595 * tunnel offload API requires this registration for cases when
10596 * tunnel match rule was inserted before tunnel set rule.
10598 tbl = flow_dv_tbl_resource_get(dev, key->level,
10599 key->is_egress, key->is_fdb,
10600 dev_flow->external, tunnel,
10601 group_id, 0, key->id, error);
10603 return -rte_errno; /* No need to refill the error info */
10604 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10606 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10608 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10609 return rte_flow_error_set(error, ENOMEM,
10610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10611 "cannot allocate ref memory");
10613 resource = container_of(entry, typeof(*resource), entry);
10614 dev_flow->handle->dvh.matcher = resource;
10618 struct mlx5_list_entry *
10619 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10621 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10622 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10623 struct mlx5_flow_dv_tag_resource *entry;
10627 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10629 rte_flow_error_set(ctx->error, ENOMEM,
10630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10631 "cannot allocate resource memory");
10635 entry->tag_id = *(uint32_t *)(ctx->data);
10636 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10639 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10640 rte_flow_error_set(ctx->error, ENOMEM,
10641 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10642 NULL, "cannot create action");
10645 return &entry->entry;
10649 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10652 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10653 struct mlx5_flow_dv_tag_resource *tag =
10654 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10656 return *(uint32_t *)(ctx->data) != tag->tag_id;
10659 struct mlx5_list_entry *
10660 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10663 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10664 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10665 struct mlx5_flow_dv_tag_resource *entry;
10668 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10670 rte_flow_error_set(ctx->error, ENOMEM,
10671 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10672 "cannot allocate tag resource memory");
10675 memcpy(entry, oentry, sizeof(*entry));
10677 return &entry->entry;
10681 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10683 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10684 struct mlx5_flow_dv_tag_resource *tag =
10685 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10687 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10691 * Find existing tag resource or create and register a new one.
10693 * @param dev[in, out]
10694 * Pointer to rte_eth_dev structure.
10695 * @param[in, out] tag_be24
10696 * Tag value in big endian then R-shift 8.
10697 * @parm[in, out] dev_flow
10698 * Pointer to the dev_flow.
10699 * @param[out] error
10700 * pointer to error structure.
10703 * 0 on success otherwise -errno and errno is set.
10706 flow_dv_tag_resource_register
10707 (struct rte_eth_dev *dev,
10709 struct mlx5_flow *dev_flow,
10710 struct rte_flow_error *error)
10712 struct mlx5_priv *priv = dev->data->dev_private;
10713 struct mlx5_flow_dv_tag_resource *resource;
10714 struct mlx5_list_entry *entry;
10715 struct mlx5_flow_cb_ctx ctx = {
10719 struct mlx5_hlist *tag_table;
10721 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10723 MLX5_TAGS_HLIST_ARRAY_SIZE,
10724 false, false, priv->sh,
10725 flow_dv_tag_create_cb,
10726 flow_dv_tag_match_cb,
10727 flow_dv_tag_remove_cb,
10728 flow_dv_tag_clone_cb,
10729 flow_dv_tag_clone_free_cb);
10730 if (unlikely(!tag_table))
10732 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10734 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10736 dev_flow->handle->dvh.rix_tag = resource->idx;
10737 dev_flow->dv.tag_resource = resource;
10744 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10746 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10747 struct mlx5_flow_dv_tag_resource *tag =
10748 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10750 MLX5_ASSERT(tag && sh && tag->action);
10751 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10752 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10753 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10760 * Pointer to Ethernet device.
10765 * 1 while a reference on it exists, 0 when freed.
10768 flow_dv_tag_release(struct rte_eth_dev *dev,
10771 struct mlx5_priv *priv = dev->data->dev_private;
10772 struct mlx5_flow_dv_tag_resource *tag;
10774 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10777 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10778 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10779 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10783 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10786 * Pointer to rte_eth_dev structure.
10787 * @param[in] action
10788 * Pointer to action PORT_ID / REPRESENTED_PORT.
10789 * @param[out] dst_port_id
10790 * The target port ID.
10791 * @param[out] error
10792 * Pointer to the error structure.
10795 * 0 on success, a negative errno value otherwise and rte_errno is set.
10798 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10799 const struct rte_flow_action *action,
10800 uint32_t *dst_port_id,
10801 struct rte_flow_error *error)
10804 struct mlx5_priv *priv;
10806 switch (action->type) {
10807 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10808 const struct rte_flow_action_port_id *conf;
10810 conf = (const struct rte_flow_action_port_id *)action->conf;
10811 port = conf->original ? dev->data->port_id : conf->id;
10814 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10815 const struct rte_flow_action_ethdev *ethdev;
10817 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10818 port = ethdev->port_id;
10822 MLX5_ASSERT(false);
10823 return rte_flow_error_set(error, EINVAL,
10824 RTE_FLOW_ERROR_TYPE_ACTION, action,
10825 "unknown E-Switch action");
10828 priv = mlx5_port_to_eswitch_info(port, false);
10830 return rte_flow_error_set(error, -rte_errno,
10831 RTE_FLOW_ERROR_TYPE_ACTION,
10833 "No eswitch info was found for port");
10834 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10836 * This parameter is transferred to
10837 * mlx5dv_dr_action_create_dest_ib_port().
10839 *dst_port_id = priv->dev_port;
10842 * Legacy mode, no LAG configurations is supported.
10843 * This parameter is transferred to
10844 * mlx5dv_dr_action_create_dest_vport().
10846 *dst_port_id = priv->vport_id;
10852 * Create a counter with aging configuration.
10855 * Pointer to rte_eth_dev structure.
10856 * @param[in] dev_flow
10857 * Pointer to the mlx5_flow.
10858 * @param[out] count
10859 * Pointer to the counter action configuration.
10861 * Pointer to the aging action configuration.
10864 * Index to flow counter on success, 0 otherwise.
10867 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10868 struct mlx5_flow *dev_flow,
10869 const struct rte_flow_action_count *count
10871 const struct rte_flow_action_age *age)
10874 struct mlx5_age_param *age_param;
10876 counter = flow_dv_counter_alloc(dev, !!age);
10877 if (!counter || age == NULL)
10879 age_param = flow_dv_counter_idx_get_age(dev, counter);
10880 age_param->context = age->context ? age->context :
10881 (void *)(uintptr_t)(dev_flow->flow_idx);
10882 age_param->timeout = age->timeout;
10883 age_param->port_id = dev->data->port_id;
10884 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10885 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10890 * Add Tx queue matcher
10893 * Pointer to the dev struct.
10894 * @param[in, out] matcher
10896 * @param[in, out] key
10897 * Flow matcher value.
10899 * Flow pattern to translate.
10901 * Item is inner pattern.
10904 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10905 void *matcher, void *key,
10906 const struct rte_flow_item *item)
10908 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10909 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10911 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10913 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10914 struct mlx5_txq_ctrl *txq;
10915 uint32_t queue, mask;
10917 queue_m = (const void *)item->mask;
10918 queue_v = (const void *)item->spec;
10921 txq = mlx5_txq_get(dev, queue_v->queue);
10924 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10925 queue = txq->obj->sq->id;
10927 queue = txq->obj->sq_obj.sq->id;
10928 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10929 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10930 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10931 mlx5_txq_release(dev, queue_v->queue);
10935 * Set the hash fields according to the @p flow information.
10937 * @param[in] dev_flow
10938 * Pointer to the mlx5_flow.
10939 * @param[in] rss_desc
10940 * Pointer to the mlx5_flow_rss_desc.
10943 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10944 struct mlx5_flow_rss_desc *rss_desc)
10946 uint64_t items = dev_flow->handle->layers;
10948 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10950 dev_flow->hash_fields = 0;
10951 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10952 if (rss_desc->level >= 2)
10955 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10956 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10957 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10958 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10959 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10960 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10961 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10963 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10965 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10966 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10967 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10968 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10969 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10970 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10971 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10973 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10976 if (dev_flow->hash_fields == 0)
10978 * There is no match between the RSS types and the
10979 * L3 protocol (IPv4/IPv6) defined in the flow rule.
10982 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10983 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10984 if (rss_types & RTE_ETH_RSS_UDP) {
10985 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10986 dev_flow->hash_fields |=
10987 IBV_RX_HASH_SRC_PORT_UDP;
10988 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10989 dev_flow->hash_fields |=
10990 IBV_RX_HASH_DST_PORT_UDP;
10992 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10994 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10995 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10996 if (rss_types & RTE_ETH_RSS_TCP) {
10997 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10998 dev_flow->hash_fields |=
10999 IBV_RX_HASH_SRC_PORT_TCP;
11000 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11001 dev_flow->hash_fields |=
11002 IBV_RX_HASH_DST_PORT_TCP;
11004 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11008 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11012 * Prepare an Rx Hash queue.
11015 * Pointer to Ethernet device.
11016 * @param[in] dev_flow
11017 * Pointer to the mlx5_flow.
11018 * @param[in] rss_desc
11019 * Pointer to the mlx5_flow_rss_desc.
11020 * @param[out] hrxq_idx
11021 * Hash Rx queue index.
11024 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11026 static struct mlx5_hrxq *
11027 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11028 struct mlx5_flow *dev_flow,
11029 struct mlx5_flow_rss_desc *rss_desc,
11030 uint32_t *hrxq_idx)
11032 struct mlx5_priv *priv = dev->data->dev_private;
11033 struct mlx5_flow_handle *dh = dev_flow->handle;
11034 struct mlx5_hrxq *hrxq;
11036 MLX5_ASSERT(rss_desc->queue_num);
11037 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11038 rss_desc->hash_fields = dev_flow->hash_fields;
11039 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11040 rss_desc->shared_rss = 0;
11041 if (rss_desc->hash_fields == 0)
11042 rss_desc->queue_num = 1;
11043 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11046 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11052 * Release sample sub action resource.
11054 * @param[in, out] dev
11055 * Pointer to rte_eth_dev structure.
11056 * @param[in] act_res
11057 * Pointer to sample sub action resource.
11060 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11061 struct mlx5_flow_sub_actions_idx *act_res)
11063 if (act_res->rix_hrxq) {
11064 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11065 act_res->rix_hrxq = 0;
11067 if (act_res->rix_encap_decap) {
11068 flow_dv_encap_decap_resource_release(dev,
11069 act_res->rix_encap_decap);
11070 act_res->rix_encap_decap = 0;
11072 if (act_res->rix_port_id_action) {
11073 flow_dv_port_id_action_resource_release(dev,
11074 act_res->rix_port_id_action);
11075 act_res->rix_port_id_action = 0;
11077 if (act_res->rix_tag) {
11078 flow_dv_tag_release(dev, act_res->rix_tag);
11079 act_res->rix_tag = 0;
11081 if (act_res->rix_jump) {
11082 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11083 act_res->rix_jump = 0;
11088 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11089 struct mlx5_list_entry *entry, void *cb_ctx)
11091 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11092 struct rte_eth_dev *dev = ctx->dev;
11093 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11094 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11098 if (ctx_resource->ratio == resource->ratio &&
11099 ctx_resource->ft_type == resource->ft_type &&
11100 ctx_resource->ft_id == resource->ft_id &&
11101 ctx_resource->set_action == resource->set_action &&
11102 !memcmp((void *)&ctx_resource->sample_act,
11103 (void *)&resource->sample_act,
11104 sizeof(struct mlx5_flow_sub_actions_list))) {
11106 * Existing sample action should release the prepared
11107 * sub-actions reference counter.
11109 flow_dv_sample_sub_actions_release(dev,
11110 &ctx_resource->sample_idx);
11116 struct mlx5_list_entry *
11117 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11119 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11120 struct rte_eth_dev *dev = ctx->dev;
11121 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11122 void **sample_dv_actions = ctx_resource->sub_actions;
11123 struct mlx5_flow_dv_sample_resource *resource;
11124 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11125 struct mlx5_priv *priv = dev->data->dev_private;
11126 struct mlx5_dev_ctx_shared *sh = priv->sh;
11127 struct mlx5_flow_tbl_resource *tbl;
11129 const uint32_t next_ft_step = 1;
11130 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11131 uint8_t is_egress = 0;
11132 uint8_t is_transfer = 0;
11133 struct rte_flow_error *error = ctx->error;
11135 /* Register new sample resource. */
11136 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11138 rte_flow_error_set(error, ENOMEM,
11139 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11141 "cannot allocate resource memory");
11144 *resource = *ctx_resource;
11145 /* Create normal path table level */
11146 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11148 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11150 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11151 is_egress, is_transfer,
11152 true, NULL, 0, 0, 0, error);
11154 rte_flow_error_set(error, ENOMEM,
11155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11157 "fail to create normal path table "
11161 resource->normal_path_tbl = tbl;
11162 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11163 if (!sh->default_miss_action) {
11164 rte_flow_error_set(error, ENOMEM,
11165 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11167 "default miss action was not "
11171 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11172 sh->default_miss_action;
11174 /* Create a DR sample action */
11175 sampler_attr.sample_ratio = resource->ratio;
11176 sampler_attr.default_next_table = tbl->obj;
11177 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11178 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11179 &sample_dv_actions[0];
11180 sampler_attr.action = resource->set_action;
11181 if (mlx5_os_flow_dr_create_flow_action_sampler
11182 (&sampler_attr, &resource->verbs_action)) {
11183 rte_flow_error_set(error, ENOMEM,
11184 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11185 NULL, "cannot create sample action");
11188 resource->idx = idx;
11189 resource->dev = dev;
11190 return &resource->entry;
11192 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11193 flow_dv_sample_sub_actions_release(dev,
11194 &resource->sample_idx);
11195 if (resource->normal_path_tbl)
11196 flow_dv_tbl_resource_release(MLX5_SH(dev),
11197 resource->normal_path_tbl);
11198 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11203 struct mlx5_list_entry *
11204 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11205 struct mlx5_list_entry *entry __rte_unused,
11208 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11209 struct rte_eth_dev *dev = ctx->dev;
11210 struct mlx5_flow_dv_sample_resource *resource;
11211 struct mlx5_priv *priv = dev->data->dev_private;
11212 struct mlx5_dev_ctx_shared *sh = priv->sh;
11215 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11217 rte_flow_error_set(ctx->error, ENOMEM,
11218 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11220 "cannot allocate resource memory");
11223 memcpy(resource, entry, sizeof(*resource));
11224 resource->idx = idx;
11225 resource->dev = dev;
11226 return &resource->entry;
11230 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11231 struct mlx5_list_entry *entry)
11233 struct mlx5_flow_dv_sample_resource *resource =
11234 container_of(entry, typeof(*resource), entry);
11235 struct rte_eth_dev *dev = resource->dev;
11236 struct mlx5_priv *priv = dev->data->dev_private;
11238 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11242 * Find existing sample resource or create and register a new one.
11244 * @param[in, out] dev
11245 * Pointer to rte_eth_dev structure.
11247 * Pointer to sample resource reference.
11248 * @parm[in, out] dev_flow
11249 * Pointer to the dev_flow.
11250 * @param[out] error
11251 * pointer to error structure.
11254 * 0 on success otherwise -errno and errno is set.
11257 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11258 struct mlx5_flow_dv_sample_resource *ref,
11259 struct mlx5_flow *dev_flow,
11260 struct rte_flow_error *error)
11262 struct mlx5_flow_dv_sample_resource *resource;
11263 struct mlx5_list_entry *entry;
11264 struct mlx5_priv *priv = dev->data->dev_private;
11265 struct mlx5_flow_cb_ctx ctx = {
11271 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11274 resource = container_of(entry, typeof(*resource), entry);
11275 dev_flow->handle->dvh.rix_sample = resource->idx;
11276 dev_flow->dv.sample_res = resource;
11281 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11282 struct mlx5_list_entry *entry, void *cb_ctx)
11284 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11285 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11286 struct rte_eth_dev *dev = ctx->dev;
11287 struct mlx5_flow_dv_dest_array_resource *resource =
11288 container_of(entry, typeof(*resource), entry);
11291 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11292 ctx_resource->ft_type == resource->ft_type &&
11293 !memcmp((void *)resource->sample_act,
11294 (void *)ctx_resource->sample_act,
11295 (ctx_resource->num_of_dest *
11296 sizeof(struct mlx5_flow_sub_actions_list)))) {
11298 * Existing sample action should release the prepared
11299 * sub-actions reference counter.
11301 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11302 flow_dv_sample_sub_actions_release(dev,
11303 &ctx_resource->sample_idx[idx]);
11309 struct mlx5_list_entry *
11310 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11312 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11313 struct rte_eth_dev *dev = ctx->dev;
11314 struct mlx5_flow_dv_dest_array_resource *resource;
11315 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11316 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11317 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11318 struct mlx5_priv *priv = dev->data->dev_private;
11319 struct mlx5_dev_ctx_shared *sh = priv->sh;
11320 struct mlx5_flow_sub_actions_list *sample_act;
11321 struct mlx5dv_dr_domain *domain;
11322 uint32_t idx = 0, res_idx = 0;
11323 struct rte_flow_error *error = ctx->error;
11324 uint64_t action_flags;
11327 /* Register new destination array resource. */
11328 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11331 rte_flow_error_set(error, ENOMEM,
11332 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11334 "cannot allocate resource memory");
11337 *resource = *ctx_resource;
11338 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11339 domain = sh->fdb_domain;
11340 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11341 domain = sh->rx_domain;
11343 domain = sh->tx_domain;
11344 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11345 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11346 mlx5_malloc(MLX5_MEM_ZERO,
11347 sizeof(struct mlx5dv_dr_action_dest_attr),
11349 if (!dest_attr[idx]) {
11350 rte_flow_error_set(error, ENOMEM,
11351 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11353 "cannot allocate resource memory");
11356 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11357 sample_act = &ctx_resource->sample_act[idx];
11358 action_flags = sample_act->action_flags;
11359 switch (action_flags) {
11360 case MLX5_FLOW_ACTION_QUEUE:
11361 dest_attr[idx]->dest = sample_act->dr_queue_action;
11363 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11364 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11365 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11366 dest_attr[idx]->dest_reformat->reformat =
11367 sample_act->dr_encap_action;
11368 dest_attr[idx]->dest_reformat->dest =
11369 sample_act->dr_port_id_action;
11371 case MLX5_FLOW_ACTION_PORT_ID:
11372 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11374 case MLX5_FLOW_ACTION_JUMP:
11375 dest_attr[idx]->dest = sample_act->dr_jump_action;
11378 rte_flow_error_set(error, EINVAL,
11379 RTE_FLOW_ERROR_TYPE_ACTION,
11381 "unsupported actions type");
11385 /* create a dest array actioin */
11386 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11388 resource->num_of_dest,
11390 &resource->action);
11392 rte_flow_error_set(error, ENOMEM,
11393 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11395 "cannot create destination array action");
11398 resource->idx = res_idx;
11399 resource->dev = dev;
11400 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11401 mlx5_free(dest_attr[idx]);
11402 return &resource->entry;
11404 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11405 flow_dv_sample_sub_actions_release(dev,
11406 &resource->sample_idx[idx]);
11407 if (dest_attr[idx])
11408 mlx5_free(dest_attr[idx]);
11410 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11414 struct mlx5_list_entry *
11415 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11416 struct mlx5_list_entry *entry __rte_unused,
11419 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11420 struct rte_eth_dev *dev = ctx->dev;
11421 struct mlx5_flow_dv_dest_array_resource *resource;
11422 struct mlx5_priv *priv = dev->data->dev_private;
11423 struct mlx5_dev_ctx_shared *sh = priv->sh;
11424 uint32_t res_idx = 0;
11425 struct rte_flow_error *error = ctx->error;
11427 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11430 rte_flow_error_set(error, ENOMEM,
11431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11433 "cannot allocate dest-array memory");
11436 memcpy(resource, entry, sizeof(*resource));
11437 resource->idx = res_idx;
11438 resource->dev = dev;
11439 return &resource->entry;
11443 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11444 struct mlx5_list_entry *entry)
11446 struct mlx5_flow_dv_dest_array_resource *resource =
11447 container_of(entry, typeof(*resource), entry);
11448 struct rte_eth_dev *dev = resource->dev;
11449 struct mlx5_priv *priv = dev->data->dev_private;
11451 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11455 * Find existing destination array resource or create and register a new one.
11457 * @param[in, out] dev
11458 * Pointer to rte_eth_dev structure.
11460 * Pointer to destination array resource reference.
11461 * @parm[in, out] dev_flow
11462 * Pointer to the dev_flow.
11463 * @param[out] error
11464 * pointer to error structure.
11467 * 0 on success otherwise -errno and errno is set.
11470 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11471 struct mlx5_flow_dv_dest_array_resource *ref,
11472 struct mlx5_flow *dev_flow,
11473 struct rte_flow_error *error)
11475 struct mlx5_flow_dv_dest_array_resource *resource;
11476 struct mlx5_priv *priv = dev->data->dev_private;
11477 struct mlx5_list_entry *entry;
11478 struct mlx5_flow_cb_ctx ctx = {
11484 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11487 resource = container_of(entry, typeof(*resource), entry);
11488 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11489 dev_flow->dv.dest_array_res = resource;
11494 * Convert Sample action to DV specification.
11497 * Pointer to rte_eth_dev structure.
11498 * @param[in] action
11499 * Pointer to sample action structure.
11500 * @param[in, out] dev_flow
11501 * Pointer to the mlx5_flow.
11503 * Pointer to the flow attributes.
11504 * @param[in, out] num_of_dest
11505 * Pointer to the num of destination.
11506 * @param[in, out] sample_actions
11507 * Pointer to sample actions list.
11508 * @param[in, out] res
11509 * Pointer to sample resource.
11510 * @param[out] error
11511 * Pointer to the error structure.
11514 * 0 on success, a negative errno value otherwise and rte_errno is set.
11517 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11518 const struct rte_flow_action_sample *action,
11519 struct mlx5_flow *dev_flow,
11520 const struct rte_flow_attr *attr,
11521 uint32_t *num_of_dest,
11522 void **sample_actions,
11523 struct mlx5_flow_dv_sample_resource *res,
11524 struct rte_flow_error *error)
11526 struct mlx5_priv *priv = dev->data->dev_private;
11527 const struct rte_flow_action *sub_actions;
11528 struct mlx5_flow_sub_actions_list *sample_act;
11529 struct mlx5_flow_sub_actions_idx *sample_idx;
11530 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11531 struct rte_flow *flow = dev_flow->flow;
11532 struct mlx5_flow_rss_desc *rss_desc;
11533 uint64_t action_flags = 0;
11536 rss_desc = &wks->rss_desc;
11537 sample_act = &res->sample_act;
11538 sample_idx = &res->sample_idx;
11539 res->ratio = action->ratio;
11540 sub_actions = action->actions;
11541 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11542 int type = sub_actions->type;
11543 uint32_t pre_rix = 0;
11546 case RTE_FLOW_ACTION_TYPE_QUEUE:
11548 const struct rte_flow_action_queue *queue;
11549 struct mlx5_hrxq *hrxq;
11552 queue = sub_actions->conf;
11553 rss_desc->queue_num = 1;
11554 rss_desc->queue[0] = queue->index;
11555 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11556 rss_desc, &hrxq_idx);
11558 return rte_flow_error_set
11560 RTE_FLOW_ERROR_TYPE_ACTION,
11562 "cannot create fate queue");
11563 sample_act->dr_queue_action = hrxq->action;
11564 sample_idx->rix_hrxq = hrxq_idx;
11565 sample_actions[sample_act->actions_num++] =
11568 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11569 if (action_flags & MLX5_FLOW_ACTION_MARK)
11570 dev_flow->handle->rix_hrxq = hrxq_idx;
11571 dev_flow->handle->fate_action =
11572 MLX5_FLOW_FATE_QUEUE;
11575 case RTE_FLOW_ACTION_TYPE_RSS:
11577 struct mlx5_hrxq *hrxq;
11579 const struct rte_flow_action_rss *rss;
11580 const uint8_t *rss_key;
11582 rss = sub_actions->conf;
11583 memcpy(rss_desc->queue, rss->queue,
11584 rss->queue_num * sizeof(uint16_t));
11585 rss_desc->queue_num = rss->queue_num;
11586 /* NULL RSS key indicates default RSS key. */
11587 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11588 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11590 * rss->level and rss.types should be set in advance
11591 * when expanding items for RSS.
11593 flow_dv_hashfields_set(dev_flow, rss_desc);
11594 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11595 rss_desc, &hrxq_idx);
11597 return rte_flow_error_set
11599 RTE_FLOW_ERROR_TYPE_ACTION,
11601 "cannot create fate queue");
11602 sample_act->dr_queue_action = hrxq->action;
11603 sample_idx->rix_hrxq = hrxq_idx;
11604 sample_actions[sample_act->actions_num++] =
11607 action_flags |= MLX5_FLOW_ACTION_RSS;
11608 if (action_flags & MLX5_FLOW_ACTION_MARK)
11609 dev_flow->handle->rix_hrxq = hrxq_idx;
11610 dev_flow->handle->fate_action =
11611 MLX5_FLOW_FATE_QUEUE;
11614 case RTE_FLOW_ACTION_TYPE_MARK:
11616 uint32_t tag_be = mlx5_flow_mark_set
11617 (((const struct rte_flow_action_mark *)
11618 (sub_actions->conf))->id);
11620 dev_flow->handle->mark = 1;
11621 pre_rix = dev_flow->handle->dvh.rix_tag;
11622 /* Save the mark resource before sample */
11623 pre_r = dev_flow->dv.tag_resource;
11624 if (flow_dv_tag_resource_register(dev, tag_be,
11627 MLX5_ASSERT(dev_flow->dv.tag_resource);
11628 sample_act->dr_tag_action =
11629 dev_flow->dv.tag_resource->action;
11630 sample_idx->rix_tag =
11631 dev_flow->handle->dvh.rix_tag;
11632 sample_actions[sample_act->actions_num++] =
11633 sample_act->dr_tag_action;
11634 /* Recover the mark resource after sample */
11635 dev_flow->dv.tag_resource = pre_r;
11636 dev_flow->handle->dvh.rix_tag = pre_rix;
11637 action_flags |= MLX5_FLOW_ACTION_MARK;
11640 case RTE_FLOW_ACTION_TYPE_COUNT:
11642 if (!flow->counter) {
11644 flow_dv_translate_create_counter(dev,
11645 dev_flow, sub_actions->conf,
11647 if (!flow->counter)
11648 return rte_flow_error_set
11650 RTE_FLOW_ERROR_TYPE_ACTION,
11652 "cannot create counter"
11655 sample_act->dr_cnt_action =
11656 (flow_dv_counter_get_by_idx(dev,
11657 flow->counter, NULL))->action;
11658 sample_actions[sample_act->actions_num++] =
11659 sample_act->dr_cnt_action;
11660 action_flags |= MLX5_FLOW_ACTION_COUNT;
11663 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11664 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11666 struct mlx5_flow_dv_port_id_action_resource
11668 uint32_t port_id = 0;
11670 memset(&port_id_resource, 0, sizeof(port_id_resource));
11671 /* Save the port id resource before sample */
11672 pre_rix = dev_flow->handle->rix_port_id_action;
11673 pre_r = dev_flow->dv.port_id_action;
11674 if (flow_dv_translate_action_port_id(dev, sub_actions,
11677 port_id_resource.port_id = port_id;
11678 if (flow_dv_port_id_action_resource_register
11679 (dev, &port_id_resource, dev_flow, error))
11681 sample_act->dr_port_id_action =
11682 dev_flow->dv.port_id_action->action;
11683 sample_idx->rix_port_id_action =
11684 dev_flow->handle->rix_port_id_action;
11685 sample_actions[sample_act->actions_num++] =
11686 sample_act->dr_port_id_action;
11687 /* Recover the port id resource after sample */
11688 dev_flow->dv.port_id_action = pre_r;
11689 dev_flow->handle->rix_port_id_action = pre_rix;
11691 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11694 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11695 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11696 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11697 /* Save the encap resource before sample */
11698 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11699 pre_r = dev_flow->dv.encap_decap;
11700 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11705 sample_act->dr_encap_action =
11706 dev_flow->dv.encap_decap->action;
11707 sample_idx->rix_encap_decap =
11708 dev_flow->handle->dvh.rix_encap_decap;
11709 sample_actions[sample_act->actions_num++] =
11710 sample_act->dr_encap_action;
11711 /* Recover the encap resource after sample */
11712 dev_flow->dv.encap_decap = pre_r;
11713 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11714 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11717 return rte_flow_error_set(error, EINVAL,
11718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11720 "Not support for sampler action");
11723 sample_act->action_flags = action_flags;
11724 res->ft_id = dev_flow->dv.group;
11725 if (attr->transfer) {
11727 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11728 uint64_t set_action;
11729 } action_ctx = { .set_action = 0 };
11731 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11732 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11733 MLX5_MODIFICATION_TYPE_SET);
11734 MLX5_SET(set_action_in, action_ctx.action_in, field,
11735 MLX5_MODI_META_REG_C_0);
11736 MLX5_SET(set_action_in, action_ctx.action_in, data,
11737 priv->vport_meta_tag);
11738 res->set_action = action_ctx.set_action;
11739 } else if (attr->ingress) {
11740 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11742 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11748 * Convert Sample action to DV specification.
11751 * Pointer to rte_eth_dev structure.
11752 * @param[in, out] dev_flow
11753 * Pointer to the mlx5_flow.
11754 * @param[in] num_of_dest
11755 * The num of destination.
11756 * @param[in, out] res
11757 * Pointer to sample resource.
11758 * @param[in, out] mdest_res
11759 * Pointer to destination array resource.
11760 * @param[in] sample_actions
11761 * Pointer to sample path actions list.
11762 * @param[in] action_flags
11763 * Holds the actions detected until now.
11764 * @param[out] error
11765 * Pointer to the error structure.
11768 * 0 on success, a negative errno value otherwise and rte_errno is set.
11771 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11772 struct mlx5_flow *dev_flow,
11773 uint32_t num_of_dest,
11774 struct mlx5_flow_dv_sample_resource *res,
11775 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11776 void **sample_actions,
11777 uint64_t action_flags,
11778 struct rte_flow_error *error)
11780 /* update normal path action resource into last index of array */
11781 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11782 struct mlx5_flow_sub_actions_list *sample_act =
11783 &mdest_res->sample_act[dest_index];
11784 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11785 struct mlx5_flow_rss_desc *rss_desc;
11786 uint32_t normal_idx = 0;
11787 struct mlx5_hrxq *hrxq;
11791 rss_desc = &wks->rss_desc;
11792 if (num_of_dest > 1) {
11793 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11794 /* Handle QP action for mirroring */
11795 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11796 rss_desc, &hrxq_idx);
11798 return rte_flow_error_set
11800 RTE_FLOW_ERROR_TYPE_ACTION,
11802 "cannot create rx queue");
11804 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11805 sample_act->dr_queue_action = hrxq->action;
11806 if (action_flags & MLX5_FLOW_ACTION_MARK)
11807 dev_flow->handle->rix_hrxq = hrxq_idx;
11808 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11810 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11812 mdest_res->sample_idx[dest_index].rix_encap_decap =
11813 dev_flow->handle->dvh.rix_encap_decap;
11814 sample_act->dr_encap_action =
11815 dev_flow->dv.encap_decap->action;
11816 dev_flow->handle->dvh.rix_encap_decap = 0;
11818 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11820 mdest_res->sample_idx[dest_index].rix_port_id_action =
11821 dev_flow->handle->rix_port_id_action;
11822 sample_act->dr_port_id_action =
11823 dev_flow->dv.port_id_action->action;
11824 dev_flow->handle->rix_port_id_action = 0;
11826 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11828 mdest_res->sample_idx[dest_index].rix_jump =
11829 dev_flow->handle->rix_jump;
11830 sample_act->dr_jump_action =
11831 dev_flow->dv.jump->action;
11832 dev_flow->handle->rix_jump = 0;
11834 sample_act->actions_num = normal_idx;
11835 /* update sample action resource into first index of array */
11836 mdest_res->ft_type = res->ft_type;
11837 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11838 sizeof(struct mlx5_flow_sub_actions_idx));
11839 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11840 sizeof(struct mlx5_flow_sub_actions_list));
11841 mdest_res->num_of_dest = num_of_dest;
11842 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11844 return rte_flow_error_set(error, EINVAL,
11845 RTE_FLOW_ERROR_TYPE_ACTION,
11846 NULL, "can't create sample "
11849 res->sub_actions = sample_actions;
11850 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11851 return rte_flow_error_set(error, EINVAL,
11852 RTE_FLOW_ERROR_TYPE_ACTION,
11854 "can't create sample action");
11860 * Remove an ASO age action from age actions list.
11863 * Pointer to the Ethernet device structure.
11865 * Pointer to the aso age action handler.
11868 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11869 struct mlx5_aso_age_action *age)
11871 struct mlx5_age_info *age_info;
11872 struct mlx5_age_param *age_param = &age->age_params;
11873 struct mlx5_priv *priv = dev->data->dev_private;
11874 uint16_t expected = AGE_CANDIDATE;
11876 age_info = GET_PORT_AGE_INFO(priv);
11877 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11878 AGE_FREE, false, __ATOMIC_RELAXED,
11879 __ATOMIC_RELAXED)) {
11881 * We need the lock even it is age timeout,
11882 * since age action may still in process.
11884 rte_spinlock_lock(&age_info->aged_sl);
11885 LIST_REMOVE(age, next);
11886 rte_spinlock_unlock(&age_info->aged_sl);
11887 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11892 * Release an ASO age action.
11895 * Pointer to the Ethernet device structure.
11896 * @param[in] age_idx
11897 * Index of ASO age action to release.
11899 * True if the release operation is during flow destroy operation.
11900 * False if the release operation is during action destroy operation.
11903 * 0 when age action was removed, otherwise the number of references.
11906 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11908 struct mlx5_priv *priv = dev->data->dev_private;
11909 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11910 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11911 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11914 flow_dv_aso_age_remove_from_age(dev, age);
11915 rte_spinlock_lock(&mng->free_sl);
11916 LIST_INSERT_HEAD(&mng->free, age, next);
11917 rte_spinlock_unlock(&mng->free_sl);
11923 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11926 * Pointer to the Ethernet device structure.
11929 * 0 on success, otherwise negative errno value and rte_errno is set.
11932 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11934 struct mlx5_priv *priv = dev->data->dev_private;
11935 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11936 void *old_pools = mng->pools;
11937 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11938 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11939 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11942 rte_errno = ENOMEM;
11946 memcpy(pools, old_pools,
11947 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11948 mlx5_free(old_pools);
11950 /* First ASO flow hit allocation - starting ASO data-path. */
11951 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11959 mng->pools = pools;
11964 * Create and initialize a new ASO aging pool.
11967 * Pointer to the Ethernet device structure.
11968 * @param[out] age_free
11969 * Where to put the pointer of a new age action.
11972 * The age actions pool pointer and @p age_free is set on success,
11973 * NULL otherwise and rte_errno is set.
11975 static struct mlx5_aso_age_pool *
11976 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11977 struct mlx5_aso_age_action **age_free)
11979 struct mlx5_priv *priv = dev->data->dev_private;
11980 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11981 struct mlx5_aso_age_pool *pool = NULL;
11982 struct mlx5_devx_obj *obj = NULL;
11985 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
11986 priv->sh->cdev->pdn);
11988 rte_errno = ENODATA;
11989 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11992 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11994 claim_zero(mlx5_devx_cmd_destroy(obj));
11995 rte_errno = ENOMEM;
11998 pool->flow_hit_aso_obj = obj;
11999 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12000 rte_rwlock_write_lock(&mng->resize_rwl);
12001 pool->index = mng->next;
12002 /* Resize pools array if there is no room for the new pool in it. */
12003 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12004 claim_zero(mlx5_devx_cmd_destroy(obj));
12006 rte_rwlock_write_unlock(&mng->resize_rwl);
12009 mng->pools[pool->index] = pool;
12011 rte_rwlock_write_unlock(&mng->resize_rwl);
12012 /* Assign the first action in the new pool, the rest go to free list. */
12013 *age_free = &pool->actions[0];
12014 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12015 pool->actions[i].offset = i;
12016 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12022 * Allocate a ASO aging bit.
12025 * Pointer to the Ethernet device structure.
12026 * @param[out] error
12027 * Pointer to the error structure.
12030 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12033 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12035 struct mlx5_priv *priv = dev->data->dev_private;
12036 const struct mlx5_aso_age_pool *pool;
12037 struct mlx5_aso_age_action *age_free = NULL;
12038 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12041 /* Try to get the next free age action bit. */
12042 rte_spinlock_lock(&mng->free_sl);
12043 age_free = LIST_FIRST(&mng->free);
12045 LIST_REMOVE(age_free, next);
12046 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12047 rte_spinlock_unlock(&mng->free_sl);
12048 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12049 NULL, "failed to create ASO age pool");
12050 return 0; /* 0 is an error. */
12052 rte_spinlock_unlock(&mng->free_sl);
12053 pool = container_of
12054 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12055 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12057 if (!age_free->dr_action) {
12058 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12062 rte_flow_error_set(error, rte_errno,
12063 RTE_FLOW_ERROR_TYPE_ACTION,
12064 NULL, "failed to get reg_c "
12065 "for ASO flow hit");
12066 return 0; /* 0 is an error. */
12068 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12069 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12070 (priv->sh->rx_domain,
12071 pool->flow_hit_aso_obj->obj, age_free->offset,
12072 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12073 (reg_c - REG_C_0));
12074 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12075 if (!age_free->dr_action) {
12077 rte_spinlock_lock(&mng->free_sl);
12078 LIST_INSERT_HEAD(&mng->free, age_free, next);
12079 rte_spinlock_unlock(&mng->free_sl);
12080 rte_flow_error_set(error, rte_errno,
12081 RTE_FLOW_ERROR_TYPE_ACTION,
12082 NULL, "failed to create ASO "
12083 "flow hit action");
12084 return 0; /* 0 is an error. */
12087 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12088 return pool->index | ((age_free->offset + 1) << 16);
12092 * Initialize flow ASO age parameters.
12095 * Pointer to rte_eth_dev structure.
12096 * @param[in] age_idx
12097 * Index of ASO age action.
12098 * @param[in] context
12099 * Pointer to flow counter age context.
12100 * @param[in] timeout
12101 * Aging timeout in seconds.
12105 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12110 struct mlx5_aso_age_action *aso_age;
12112 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12113 MLX5_ASSERT(aso_age);
12114 aso_age->age_params.context = context;
12115 aso_age->age_params.timeout = timeout;
12116 aso_age->age_params.port_id = dev->data->port_id;
12117 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12119 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12124 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12125 const struct rte_flow_item_integrity *value,
12126 void *headers_m, void *headers_v)
12129 /* RTE l4_ok filter aggregates hardware l4_ok and
12130 * l4_checksum_ok filters.
12131 * Positive RTE l4_ok match requires hardware match on both L4
12132 * hardware integrity bits.
12133 * For negative match, check hardware l4_checksum_ok bit only,
12134 * because hardware sets that bit to 0 for all packets
12137 if (value->l4_ok) {
12138 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12139 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12141 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12142 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12145 if (mask->l4_csum_ok) {
12146 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12147 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12148 value->l4_csum_ok);
12153 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12154 const struct rte_flow_item_integrity *value,
12155 void *headers_m, void *headers_v, bool is_ipv4)
12158 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12159 * ipv4_csum_ok filters.
12160 * Positive RTE l3_ok match requires hardware match on both L3
12161 * hardware integrity bits.
12162 * For negative match, check hardware l3_csum_ok bit only,
12163 * because hardware sets that bit to 0 for all packets
12167 if (value->l3_ok) {
12168 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12170 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12173 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12174 ipv4_checksum_ok, 1);
12175 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12176 ipv4_checksum_ok, !!value->l3_ok);
12178 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12179 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12183 if (mask->ipv4_csum_ok) {
12184 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12185 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12186 value->ipv4_csum_ok);
12191 set_integrity_bits(void *headers_m, void *headers_v,
12192 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12194 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12195 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12197 /* Integrity bits validation cleared spec pointer */
12198 MLX5_ASSERT(spec != NULL);
12200 mask = &rte_flow_item_integrity_mask;
12201 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12203 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12207 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12209 struct rte_flow_item *integrity_items[2],
12210 uint64_t pattern_flags)
12212 void *headers_m, *headers_v;
12215 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12216 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12218 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12219 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12221 set_integrity_bits(headers_m, headers_v,
12222 integrity_items[1], is_l3_ip4);
12224 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12225 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12227 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12228 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12230 set_integrity_bits(headers_m, headers_v,
12231 integrity_items[0], is_l3_ip4);
12236 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12237 const struct rte_flow_item *integrity_items[2],
12238 uint64_t *last_item)
12240 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12242 /* integrity bits validation cleared spec pointer */
12243 MLX5_ASSERT(spec != NULL);
12244 if (spec->level > 1) {
12245 integrity_items[1] = item;
12246 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12248 integrity_items[0] = item;
12249 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12254 * Prepares DV flow counter with aging configuration.
12255 * Gets it by index when exists, creates a new one when doesn't.
12258 * Pointer to rte_eth_dev structure.
12259 * @param[in] dev_flow
12260 * Pointer to the mlx5_flow.
12261 * @param[in, out] flow
12262 * Pointer to the sub flow.
12264 * Pointer to the counter action configuration.
12266 * Pointer to the aging action configuration.
12267 * @param[out] error
12268 * Pointer to the error structure.
12271 * Pointer to the counter, NULL otherwise.
12273 static struct mlx5_flow_counter *
12274 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12275 struct mlx5_flow *dev_flow,
12276 struct rte_flow *flow,
12277 const struct rte_flow_action_count *count,
12278 const struct rte_flow_action_age *age,
12279 struct rte_flow_error *error)
12281 if (!flow->counter) {
12282 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12284 if (!flow->counter) {
12285 rte_flow_error_set(error, rte_errno,
12286 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12287 "cannot create counter object.");
12291 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12295 * Release an ASO CT action by its own device.
12298 * Pointer to the Ethernet device structure.
12300 * Index of ASO CT action to release.
12303 * 0 when CT action was removed, otherwise the number of references.
12306 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12308 struct mlx5_priv *priv = dev->data->dev_private;
12309 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12311 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12312 enum mlx5_aso_ct_state state =
12313 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12315 /* Cannot release when CT is in the ASO SQ. */
12316 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12318 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12320 if (ct->dr_action_orig) {
12321 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12322 claim_zero(mlx5_glue->destroy_flow_action
12323 (ct->dr_action_orig));
12325 ct->dr_action_orig = NULL;
12327 if (ct->dr_action_rply) {
12328 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12329 claim_zero(mlx5_glue->destroy_flow_action
12330 (ct->dr_action_rply));
12332 ct->dr_action_rply = NULL;
12334 /* Clear the state to free, no need in 1st allocation. */
12335 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12336 rte_spinlock_lock(&mng->ct_sl);
12337 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12338 rte_spinlock_unlock(&mng->ct_sl);
12344 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12345 struct rte_flow_error *error)
12347 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12348 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12349 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12352 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12353 if (dev->data->dev_started != 1)
12354 return rte_flow_error_set(error, EAGAIN,
12355 RTE_FLOW_ERROR_TYPE_ACTION,
12357 "Indirect CT action cannot be destroyed when the port is stopped");
12358 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12360 return rte_flow_error_set(error, EAGAIN,
12361 RTE_FLOW_ERROR_TYPE_ACTION,
12363 "Current state prevents indirect CT action from being destroyed");
12368 * Resize the ASO CT pools array by 64 pools.
12371 * Pointer to the Ethernet device structure.
12374 * 0 on success, otherwise negative errno value and rte_errno is set.
12377 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12379 struct mlx5_priv *priv = dev->data->dev_private;
12380 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12381 void *old_pools = mng->pools;
12382 /* Magic number now, need a macro. */
12383 uint32_t resize = mng->n + 64;
12384 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12385 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12388 rte_errno = ENOMEM;
12391 rte_rwlock_write_lock(&mng->resize_rwl);
12392 /* ASO SQ/QP was already initialized in the startup. */
12394 /* Realloc could be an alternative choice. */
12395 rte_memcpy(pools, old_pools,
12396 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12397 mlx5_free(old_pools);
12400 mng->pools = pools;
12401 rte_rwlock_write_unlock(&mng->resize_rwl);
12406 * Create and initialize a new ASO CT pool.
12409 * Pointer to the Ethernet device structure.
12410 * @param[out] ct_free
12411 * Where to put the pointer of a new CT action.
12414 * The CT actions pool pointer and @p ct_free is set on success,
12415 * NULL otherwise and rte_errno is set.
12417 static struct mlx5_aso_ct_pool *
12418 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12419 struct mlx5_aso_ct_action **ct_free)
12421 struct mlx5_priv *priv = dev->data->dev_private;
12422 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12423 struct mlx5_aso_ct_pool *pool = NULL;
12424 struct mlx5_devx_obj *obj = NULL;
12426 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12428 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12429 priv->sh->cdev->pdn,
12432 rte_errno = ENODATA;
12433 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12436 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12438 rte_errno = ENOMEM;
12439 claim_zero(mlx5_devx_cmd_destroy(obj));
12442 pool->devx_obj = obj;
12443 pool->index = mng->next;
12444 /* Resize pools array if there is no room for the new pool in it. */
12445 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12446 claim_zero(mlx5_devx_cmd_destroy(obj));
12450 mng->pools[pool->index] = pool;
12452 /* Assign the first action in the new pool, the rest go to free list. */
12453 *ct_free = &pool->actions[0];
12454 /* Lock outside, the list operation is safe here. */
12455 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12456 /* refcnt is 0 when allocating the memory. */
12457 pool->actions[i].offset = i;
12458 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12464 * Allocate a ASO CT action from free list.
12467 * Pointer to the Ethernet device structure.
12468 * @param[out] error
12469 * Pointer to the error structure.
12472 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12475 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12477 struct mlx5_priv *priv = dev->data->dev_private;
12478 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12479 struct mlx5_aso_ct_action *ct = NULL;
12480 struct mlx5_aso_ct_pool *pool;
12485 if (!priv->sh->devx) {
12486 rte_errno = ENOTSUP;
12489 /* Get a free CT action, if no, a new pool will be created. */
12490 rte_spinlock_lock(&mng->ct_sl);
12491 ct = LIST_FIRST(&mng->free_cts);
12493 LIST_REMOVE(ct, next);
12494 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12495 rte_spinlock_unlock(&mng->ct_sl);
12496 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12497 NULL, "failed to create ASO CT pool");
12500 rte_spinlock_unlock(&mng->ct_sl);
12501 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12502 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12503 /* 0: inactive, 1: created, 2+: used by flows. */
12504 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12505 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12506 if (!ct->dr_action_orig) {
12507 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12508 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12509 (priv->sh->rx_domain, pool->devx_obj->obj,
12511 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12514 RTE_SET_USED(reg_c);
12516 if (!ct->dr_action_orig) {
12517 flow_dv_aso_ct_dev_release(dev, ct_idx);
12518 rte_flow_error_set(error, rte_errno,
12519 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12520 "failed to create ASO CT action");
12524 if (!ct->dr_action_rply) {
12525 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12526 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12527 (priv->sh->rx_domain, pool->devx_obj->obj,
12529 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12532 if (!ct->dr_action_rply) {
12533 flow_dv_aso_ct_dev_release(dev, ct_idx);
12534 rte_flow_error_set(error, rte_errno,
12535 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12536 "failed to create ASO CT action");
12544 * Create a conntrack object with context and actions by using ASO mechanism.
12547 * Pointer to rte_eth_dev structure.
12549 * Pointer to conntrack information profile.
12550 * @param[out] error
12551 * Pointer to the error structure.
12554 * Index to conntrack object on success, 0 otherwise.
12557 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12558 const struct rte_flow_action_conntrack *pro,
12559 struct rte_flow_error *error)
12561 struct mlx5_priv *priv = dev->data->dev_private;
12562 struct mlx5_dev_ctx_shared *sh = priv->sh;
12563 struct mlx5_aso_ct_action *ct;
12566 if (!sh->ct_aso_en)
12567 return rte_flow_error_set(error, ENOTSUP,
12568 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12569 "Connection is not supported");
12570 idx = flow_dv_aso_ct_alloc(dev, error);
12572 return rte_flow_error_set(error, rte_errno,
12573 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12574 "Failed to allocate CT object");
12575 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12576 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12577 return rte_flow_error_set(error, EBUSY,
12578 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12579 "Failed to update CT");
12580 ct->is_original = !!pro->is_original_dir;
12581 ct->peer = pro->peer_port;
12586 * Fill the flow with DV spec, lock free
12587 * (mutex should be acquired by caller).
12590 * Pointer to rte_eth_dev structure.
12591 * @param[in, out] dev_flow
12592 * Pointer to the sub flow.
12594 * Pointer to the flow attributes.
12596 * Pointer to the list of items.
12597 * @param[in] actions
12598 * Pointer to the list of actions.
12599 * @param[out] error
12600 * Pointer to the error structure.
12603 * 0 on success, a negative errno value otherwise and rte_errno is set.
12606 flow_dv_translate(struct rte_eth_dev *dev,
12607 struct mlx5_flow *dev_flow,
12608 const struct rte_flow_attr *attr,
12609 const struct rte_flow_item items[],
12610 const struct rte_flow_action actions[],
12611 struct rte_flow_error *error)
12613 struct mlx5_priv *priv = dev->data->dev_private;
12614 struct mlx5_dev_config *dev_conf = &priv->config;
12615 struct rte_flow *flow = dev_flow->flow;
12616 struct mlx5_flow_handle *handle = dev_flow->handle;
12617 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12618 struct mlx5_flow_rss_desc *rss_desc;
12619 uint64_t item_flags = 0;
12620 uint64_t last_item = 0;
12621 uint64_t action_flags = 0;
12622 struct mlx5_flow_dv_matcher matcher = {
12624 .size = sizeof(matcher.mask.buf),
12628 bool actions_end = false;
12630 struct mlx5_flow_dv_modify_hdr_resource res;
12631 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12632 sizeof(struct mlx5_modification_cmd) *
12633 (MLX5_MAX_MODIFY_NUM + 1)];
12635 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12636 const struct rte_flow_action_count *count = NULL;
12637 const struct rte_flow_action_age *non_shared_age = NULL;
12638 union flow_dv_attr flow_attr = { .attr = 0 };
12640 union mlx5_flow_tbl_key tbl_key;
12641 uint32_t modify_action_position = UINT32_MAX;
12642 void *match_mask = matcher.mask.buf;
12643 void *match_value = dev_flow->dv.value.buf;
12644 uint8_t next_protocol = 0xff;
12645 struct rte_vlan_hdr vlan = { 0 };
12646 struct mlx5_flow_dv_dest_array_resource mdest_res;
12647 struct mlx5_flow_dv_sample_resource sample_res;
12648 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12649 const struct rte_flow_action_sample *sample = NULL;
12650 struct mlx5_flow_sub_actions_list *sample_act;
12651 uint32_t sample_act_pos = UINT32_MAX;
12652 uint32_t age_act_pos = UINT32_MAX;
12653 uint32_t num_of_dest = 0;
12654 int tmp_actions_n = 0;
12657 const struct mlx5_flow_tunnel *tunnel = NULL;
12658 struct flow_grp_info grp_info = {
12659 .external = !!dev_flow->external,
12660 .transfer = !!attr->transfer,
12661 .fdb_def_rule = !!priv->fdb_def_rule,
12662 .skip_scale = dev_flow->skip_scale &
12663 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12664 .std_tbl_fix = true,
12666 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12667 const struct rte_flow_item *tunnel_item = NULL;
12670 return rte_flow_error_set(error, ENOMEM,
12671 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12673 "failed to push flow workspace");
12674 rss_desc = &wks->rss_desc;
12675 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12676 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12677 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12678 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12679 /* update normal path action resource into last index of array */
12680 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12681 if (is_tunnel_offload_active(dev)) {
12682 if (dev_flow->tunnel) {
12683 RTE_VERIFY(dev_flow->tof_type ==
12684 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12685 tunnel = dev_flow->tunnel;
12687 tunnel = mlx5_get_tof(items, actions,
12688 &dev_flow->tof_type);
12689 dev_flow->tunnel = tunnel;
12691 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12692 (dev, attr, tunnel, dev_flow->tof_type);
12694 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12695 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12696 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12700 dev_flow->dv.group = table;
12701 if (attr->transfer)
12702 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12703 /* number of actions must be set to 0 in case of dirty stack. */
12704 mhdr_res->actions_num = 0;
12705 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12707 * do not add decap action if match rule drops packet
12708 * HW rejects rules with decap & drop
12710 * if tunnel match rule was inserted before matching tunnel set
12711 * rule flow table used in the match rule must be registered.
12712 * current implementation handles that in the
12713 * flow_dv_match_register() at the function end.
12715 bool add_decap = true;
12716 const struct rte_flow_action *ptr = actions;
12718 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12719 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12725 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12729 dev_flow->dv.actions[actions_n++] =
12730 dev_flow->dv.encap_decap->action;
12731 action_flags |= MLX5_FLOW_ACTION_DECAP;
12734 for (; !actions_end ; actions++) {
12735 const struct rte_flow_action_queue *queue;
12736 const struct rte_flow_action_rss *rss;
12737 const struct rte_flow_action *action = actions;
12738 const uint8_t *rss_key;
12739 struct mlx5_flow_tbl_resource *tbl;
12740 struct mlx5_aso_age_action *age_act;
12741 struct mlx5_flow_counter *cnt_act;
12742 uint32_t port_id = 0;
12743 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12744 int action_type = actions->type;
12745 const struct rte_flow_action *found_action = NULL;
12746 uint32_t jump_group = 0;
12747 uint32_t owner_idx;
12748 struct mlx5_aso_ct_action *ct;
12750 if (!mlx5_flow_os_action_supported(action_type))
12751 return rte_flow_error_set(error, ENOTSUP,
12752 RTE_FLOW_ERROR_TYPE_ACTION,
12754 "action not supported");
12755 switch (action_type) {
12756 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12757 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12759 case RTE_FLOW_ACTION_TYPE_VOID:
12761 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12762 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12763 if (flow_dv_translate_action_port_id(dev, action,
12766 port_id_resource.port_id = port_id;
12767 MLX5_ASSERT(!handle->rix_port_id_action);
12768 if (flow_dv_port_id_action_resource_register
12769 (dev, &port_id_resource, dev_flow, error))
12771 dev_flow->dv.actions[actions_n++] =
12772 dev_flow->dv.port_id_action->action;
12773 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12774 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12775 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12778 case RTE_FLOW_ACTION_TYPE_FLAG:
12779 action_flags |= MLX5_FLOW_ACTION_FLAG;
12780 dev_flow->handle->mark = 1;
12781 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12782 struct rte_flow_action_mark mark = {
12783 .id = MLX5_FLOW_MARK_DEFAULT,
12786 if (flow_dv_convert_action_mark(dev, &mark,
12790 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12793 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12795 * Only one FLAG or MARK is supported per device flow
12796 * right now. So the pointer to the tag resource must be
12797 * zero before the register process.
12799 MLX5_ASSERT(!handle->dvh.rix_tag);
12800 if (flow_dv_tag_resource_register(dev, tag_be,
12803 MLX5_ASSERT(dev_flow->dv.tag_resource);
12804 dev_flow->dv.actions[actions_n++] =
12805 dev_flow->dv.tag_resource->action;
12807 case RTE_FLOW_ACTION_TYPE_MARK:
12808 action_flags |= MLX5_FLOW_ACTION_MARK;
12809 dev_flow->handle->mark = 1;
12810 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12811 const struct rte_flow_action_mark *mark =
12812 (const struct rte_flow_action_mark *)
12815 if (flow_dv_convert_action_mark(dev, mark,
12819 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12823 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12824 /* Legacy (non-extensive) MARK action. */
12825 tag_be = mlx5_flow_mark_set
12826 (((const struct rte_flow_action_mark *)
12827 (actions->conf))->id);
12828 MLX5_ASSERT(!handle->dvh.rix_tag);
12829 if (flow_dv_tag_resource_register(dev, tag_be,
12832 MLX5_ASSERT(dev_flow->dv.tag_resource);
12833 dev_flow->dv.actions[actions_n++] =
12834 dev_flow->dv.tag_resource->action;
12836 case RTE_FLOW_ACTION_TYPE_SET_META:
12837 if (flow_dv_convert_action_set_meta
12838 (dev, mhdr_res, attr,
12839 (const struct rte_flow_action_set_meta *)
12840 actions->conf, error))
12842 action_flags |= MLX5_FLOW_ACTION_SET_META;
12844 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12845 if (flow_dv_convert_action_set_tag
12847 (const struct rte_flow_action_set_tag *)
12848 actions->conf, error))
12850 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12852 case RTE_FLOW_ACTION_TYPE_DROP:
12853 action_flags |= MLX5_FLOW_ACTION_DROP;
12854 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12856 case RTE_FLOW_ACTION_TYPE_QUEUE:
12857 queue = actions->conf;
12858 rss_desc->queue_num = 1;
12859 rss_desc->queue[0] = queue->index;
12860 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12861 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12862 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12865 case RTE_FLOW_ACTION_TYPE_RSS:
12866 rss = actions->conf;
12867 memcpy(rss_desc->queue, rss->queue,
12868 rss->queue_num * sizeof(uint16_t));
12869 rss_desc->queue_num = rss->queue_num;
12870 /* NULL RSS key indicates default RSS key. */
12871 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12872 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12874 * rss->level and rss.types should be set in advance
12875 * when expanding items for RSS.
12877 action_flags |= MLX5_FLOW_ACTION_RSS;
12878 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12879 MLX5_FLOW_FATE_SHARED_RSS :
12880 MLX5_FLOW_FATE_QUEUE;
12882 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12883 owner_idx = (uint32_t)(uintptr_t)action->conf;
12884 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12885 if (flow->age == 0) {
12886 flow->age = owner_idx;
12887 __atomic_fetch_add(&age_act->refcnt, 1,
12890 age_act_pos = actions_n++;
12891 action_flags |= MLX5_FLOW_ACTION_AGE;
12893 case RTE_FLOW_ACTION_TYPE_AGE:
12894 non_shared_age = action->conf;
12895 age_act_pos = actions_n++;
12896 action_flags |= MLX5_FLOW_ACTION_AGE;
12898 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12899 owner_idx = (uint32_t)(uintptr_t)action->conf;
12900 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12902 MLX5_ASSERT(cnt_act != NULL);
12904 * When creating meter drop flow in drop table, the
12905 * counter should not overwrite the rte flow counter.
12907 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12908 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12909 dev_flow->dv.actions[actions_n++] =
12912 if (flow->counter == 0) {
12913 flow->counter = owner_idx;
12915 (&cnt_act->shared_info.refcnt,
12916 1, __ATOMIC_RELAXED);
12918 /* Save information first, will apply later. */
12919 action_flags |= MLX5_FLOW_ACTION_COUNT;
12922 case RTE_FLOW_ACTION_TYPE_COUNT:
12923 if (!priv->sh->devx) {
12924 return rte_flow_error_set
12926 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12928 "count action not supported");
12930 /* Save information first, will apply later. */
12931 count = action->conf;
12932 action_flags |= MLX5_FLOW_ACTION_COUNT;
12934 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12935 dev_flow->dv.actions[actions_n++] =
12936 priv->sh->pop_vlan_action;
12937 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12939 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12940 if (!(action_flags &
12941 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12942 flow_dev_get_vlan_info_from_items(items, &vlan);
12943 vlan.eth_proto = rte_be_to_cpu_16
12944 ((((const struct rte_flow_action_of_push_vlan *)
12945 actions->conf)->ethertype));
12946 found_action = mlx5_flow_find_action
12948 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12950 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12951 found_action = mlx5_flow_find_action
12953 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12955 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12956 if (flow_dv_create_action_push_vlan
12957 (dev, attr, &vlan, dev_flow, error))
12959 dev_flow->dv.actions[actions_n++] =
12960 dev_flow->dv.push_vlan_res->action;
12961 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12963 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12964 /* of_vlan_push action handled this action */
12965 MLX5_ASSERT(action_flags &
12966 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12968 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12969 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12971 flow_dev_get_vlan_info_from_items(items, &vlan);
12972 mlx5_update_vlan_vid_pcp(actions, &vlan);
12973 /* If no VLAN push - this is a modify header action */
12974 if (flow_dv_convert_action_modify_vlan_vid
12975 (mhdr_res, actions, error))
12977 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12979 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12980 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12981 if (flow_dv_create_action_l2_encap(dev, actions,
12986 dev_flow->dv.actions[actions_n++] =
12987 dev_flow->dv.encap_decap->action;
12988 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12989 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12990 sample_act->action_flags |=
12991 MLX5_FLOW_ACTION_ENCAP;
12993 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12994 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12995 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12999 dev_flow->dv.actions[actions_n++] =
13000 dev_flow->dv.encap_decap->action;
13001 action_flags |= MLX5_FLOW_ACTION_DECAP;
13003 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13004 /* Handle encap with preceding decap. */
13005 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13006 if (flow_dv_create_action_raw_encap
13007 (dev, actions, dev_flow, attr, error))
13009 dev_flow->dv.actions[actions_n++] =
13010 dev_flow->dv.encap_decap->action;
13012 /* Handle encap without preceding decap. */
13013 if (flow_dv_create_action_l2_encap
13014 (dev, actions, dev_flow, attr->transfer,
13017 dev_flow->dv.actions[actions_n++] =
13018 dev_flow->dv.encap_decap->action;
13020 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13021 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13022 sample_act->action_flags |=
13023 MLX5_FLOW_ACTION_ENCAP;
13025 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13026 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13028 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13029 if (flow_dv_create_action_l2_decap
13030 (dev, dev_flow, attr->transfer, error))
13032 dev_flow->dv.actions[actions_n++] =
13033 dev_flow->dv.encap_decap->action;
13035 /* If decap is followed by encap, handle it at encap. */
13036 action_flags |= MLX5_FLOW_ACTION_DECAP;
13038 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13039 dev_flow->dv.actions[actions_n++] =
13040 (void *)(uintptr_t)action->conf;
13041 action_flags |= MLX5_FLOW_ACTION_JUMP;
13043 case RTE_FLOW_ACTION_TYPE_JUMP:
13044 jump_group = ((const struct rte_flow_action_jump *)
13045 action->conf)->group;
13046 grp_info.std_tbl_fix = 0;
13047 if (dev_flow->skip_scale &
13048 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13049 grp_info.skip_scale = 1;
13051 grp_info.skip_scale = 0;
13052 ret = mlx5_flow_group_to_table(dev, tunnel,
13058 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13060 !!dev_flow->external,
13061 tunnel, jump_group, 0,
13064 return rte_flow_error_set
13066 RTE_FLOW_ERROR_TYPE_ACTION,
13068 "cannot create jump action.");
13069 if (flow_dv_jump_tbl_resource_register
13070 (dev, tbl, dev_flow, error)) {
13071 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13072 return rte_flow_error_set
13074 RTE_FLOW_ERROR_TYPE_ACTION,
13076 "cannot create jump action.");
13078 dev_flow->dv.actions[actions_n++] =
13079 dev_flow->dv.jump->action;
13080 action_flags |= MLX5_FLOW_ACTION_JUMP;
13081 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13082 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13085 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13086 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13087 if (flow_dv_convert_action_modify_mac
13088 (mhdr_res, actions, error))
13090 action_flags |= actions->type ==
13091 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13092 MLX5_FLOW_ACTION_SET_MAC_SRC :
13093 MLX5_FLOW_ACTION_SET_MAC_DST;
13095 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13096 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13097 if (flow_dv_convert_action_modify_ipv4
13098 (mhdr_res, actions, error))
13100 action_flags |= actions->type ==
13101 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13102 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13103 MLX5_FLOW_ACTION_SET_IPV4_DST;
13105 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13106 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13107 if (flow_dv_convert_action_modify_ipv6
13108 (mhdr_res, actions, error))
13110 action_flags |= actions->type ==
13111 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13112 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13113 MLX5_FLOW_ACTION_SET_IPV6_DST;
13115 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13116 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13117 if (flow_dv_convert_action_modify_tp
13118 (mhdr_res, actions, items,
13119 &flow_attr, dev_flow, !!(action_flags &
13120 MLX5_FLOW_ACTION_DECAP), error))
13122 action_flags |= actions->type ==
13123 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13124 MLX5_FLOW_ACTION_SET_TP_SRC :
13125 MLX5_FLOW_ACTION_SET_TP_DST;
13127 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13128 if (flow_dv_convert_action_modify_dec_ttl
13129 (mhdr_res, items, &flow_attr, dev_flow,
13131 MLX5_FLOW_ACTION_DECAP), error))
13133 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13135 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13136 if (flow_dv_convert_action_modify_ttl
13137 (mhdr_res, actions, items, &flow_attr,
13138 dev_flow, !!(action_flags &
13139 MLX5_FLOW_ACTION_DECAP), error))
13141 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13143 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13144 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13145 if (flow_dv_convert_action_modify_tcp_seq
13146 (mhdr_res, actions, error))
13148 action_flags |= actions->type ==
13149 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13150 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13151 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13154 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13155 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13156 if (flow_dv_convert_action_modify_tcp_ack
13157 (mhdr_res, actions, error))
13159 action_flags |= actions->type ==
13160 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13161 MLX5_FLOW_ACTION_INC_TCP_ACK :
13162 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13164 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13165 if (flow_dv_convert_action_set_reg
13166 (mhdr_res, actions, error))
13168 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13170 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13171 if (flow_dv_convert_action_copy_mreg
13172 (dev, mhdr_res, actions, error))
13174 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13176 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13177 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13178 dev_flow->handle->fate_action =
13179 MLX5_FLOW_FATE_DEFAULT_MISS;
13181 case RTE_FLOW_ACTION_TYPE_METER:
13183 return rte_flow_error_set(error, rte_errno,
13184 RTE_FLOW_ERROR_TYPE_ACTION,
13185 NULL, "Failed to get meter in flow.");
13186 /* Set the meter action. */
13187 dev_flow->dv.actions[actions_n++] =
13188 wks->fm->meter_action;
13189 action_flags |= MLX5_FLOW_ACTION_METER;
13191 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13192 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13195 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13197 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13198 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13201 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13203 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13204 sample_act_pos = actions_n;
13205 sample = (const struct rte_flow_action_sample *)
13208 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13209 /* put encap action into group if work with port id */
13210 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13211 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13212 sample_act->action_flags |=
13213 MLX5_FLOW_ACTION_ENCAP;
13215 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13216 if (flow_dv_convert_action_modify_field
13217 (dev, mhdr_res, actions, attr, error))
13219 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13221 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13222 owner_idx = (uint32_t)(uintptr_t)action->conf;
13223 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13225 return rte_flow_error_set(error, EINVAL,
13226 RTE_FLOW_ERROR_TYPE_ACTION,
13228 "Failed to get CT object.");
13229 if (mlx5_aso_ct_available(priv->sh, ct))
13230 return rte_flow_error_set(error, rte_errno,
13231 RTE_FLOW_ERROR_TYPE_ACTION,
13233 "CT is unavailable.");
13234 if (ct->is_original)
13235 dev_flow->dv.actions[actions_n] =
13236 ct->dr_action_orig;
13238 dev_flow->dv.actions[actions_n] =
13239 ct->dr_action_rply;
13240 if (flow->ct == 0) {
13241 flow->indirect_type =
13242 MLX5_INDIRECT_ACTION_TYPE_CT;
13243 flow->ct = owner_idx;
13244 __atomic_fetch_add(&ct->refcnt, 1,
13248 action_flags |= MLX5_FLOW_ACTION_CT;
13250 case RTE_FLOW_ACTION_TYPE_END:
13251 actions_end = true;
13252 if (mhdr_res->actions_num) {
13253 /* create modify action if needed. */
13254 if (flow_dv_modify_hdr_resource_register
13255 (dev, mhdr_res, dev_flow, error))
13257 dev_flow->dv.actions[modify_action_position] =
13258 handle->dvh.modify_hdr->action;
13261 * Handle AGE and COUNT action by single HW counter
13262 * when they are not shared.
13264 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13265 if ((non_shared_age && count) ||
13266 !(priv->sh->flow_hit_aso_en &&
13267 (attr->group || attr->transfer))) {
13268 /* Creates age by counters. */
13269 cnt_act = flow_dv_prepare_counter
13276 dev_flow->dv.actions[age_act_pos] =
13280 if (!flow->age && non_shared_age) {
13281 flow->age = flow_dv_aso_age_alloc
13285 flow_dv_aso_age_params_init
13287 non_shared_age->context ?
13288 non_shared_age->context :
13289 (void *)(uintptr_t)
13290 (dev_flow->flow_idx),
13291 non_shared_age->timeout);
13293 age_act = flow_aso_age_get_by_idx(dev,
13295 dev_flow->dv.actions[age_act_pos] =
13296 age_act->dr_action;
13298 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13300 * Create one count action, to be used
13301 * by all sub-flows.
13303 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13308 dev_flow->dv.actions[actions_n++] =
13314 if (mhdr_res->actions_num &&
13315 modify_action_position == UINT32_MAX)
13316 modify_action_position = actions_n++;
13318 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13319 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13320 int item_type = items->type;
13322 if (!mlx5_flow_os_item_supported(item_type))
13323 return rte_flow_error_set(error, ENOTSUP,
13324 RTE_FLOW_ERROR_TYPE_ITEM,
13325 NULL, "item not supported");
13326 switch (item_type) {
13327 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13328 flow_dv_translate_item_port_id
13329 (dev, match_mask, match_value, items, attr);
13330 last_item = MLX5_FLOW_ITEM_PORT_ID;
13332 case RTE_FLOW_ITEM_TYPE_ETH:
13333 flow_dv_translate_item_eth(match_mask, match_value,
13335 dev_flow->dv.group);
13336 matcher.priority = action_flags &
13337 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13338 !dev_flow->external ?
13339 MLX5_PRIORITY_MAP_L3 :
13340 MLX5_PRIORITY_MAP_L2;
13341 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13342 MLX5_FLOW_LAYER_OUTER_L2;
13344 case RTE_FLOW_ITEM_TYPE_VLAN:
13345 flow_dv_translate_item_vlan(dev_flow,
13346 match_mask, match_value,
13348 dev_flow->dv.group);
13349 matcher.priority = MLX5_PRIORITY_MAP_L2;
13350 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13351 MLX5_FLOW_LAYER_INNER_VLAN) :
13352 (MLX5_FLOW_LAYER_OUTER_L2 |
13353 MLX5_FLOW_LAYER_OUTER_VLAN);
13355 case RTE_FLOW_ITEM_TYPE_IPV4:
13356 mlx5_flow_tunnel_ip_check(items, next_protocol,
13357 &item_flags, &tunnel);
13358 flow_dv_translate_item_ipv4(match_mask, match_value,
13360 dev_flow->dv.group);
13361 matcher.priority = MLX5_PRIORITY_MAP_L3;
13362 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13363 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13364 if (items->mask != NULL &&
13365 ((const struct rte_flow_item_ipv4 *)
13366 items->mask)->hdr.next_proto_id) {
13368 ((const struct rte_flow_item_ipv4 *)
13369 (items->spec))->hdr.next_proto_id;
13371 ((const struct rte_flow_item_ipv4 *)
13372 (items->mask))->hdr.next_proto_id;
13374 /* Reset for inner layer. */
13375 next_protocol = 0xff;
13378 case RTE_FLOW_ITEM_TYPE_IPV6:
13379 mlx5_flow_tunnel_ip_check(items, next_protocol,
13380 &item_flags, &tunnel);
13381 flow_dv_translate_item_ipv6(match_mask, match_value,
13383 dev_flow->dv.group);
13384 matcher.priority = MLX5_PRIORITY_MAP_L3;
13385 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13386 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13387 if (items->mask != NULL &&
13388 ((const struct rte_flow_item_ipv6 *)
13389 items->mask)->hdr.proto) {
13391 ((const struct rte_flow_item_ipv6 *)
13392 items->spec)->hdr.proto;
13394 ((const struct rte_flow_item_ipv6 *)
13395 items->mask)->hdr.proto;
13397 /* Reset for inner layer. */
13398 next_protocol = 0xff;
13401 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13402 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13405 last_item = tunnel ?
13406 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13407 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13408 if (items->mask != NULL &&
13409 ((const struct rte_flow_item_ipv6_frag_ext *)
13410 items->mask)->hdr.next_header) {
13412 ((const struct rte_flow_item_ipv6_frag_ext *)
13413 items->spec)->hdr.next_header;
13415 ((const struct rte_flow_item_ipv6_frag_ext *)
13416 items->mask)->hdr.next_header;
13418 /* Reset for inner layer. */
13419 next_protocol = 0xff;
13422 case RTE_FLOW_ITEM_TYPE_TCP:
13423 flow_dv_translate_item_tcp(match_mask, match_value,
13425 matcher.priority = MLX5_PRIORITY_MAP_L4;
13426 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13427 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13429 case RTE_FLOW_ITEM_TYPE_UDP:
13430 flow_dv_translate_item_udp(match_mask, match_value,
13432 matcher.priority = MLX5_PRIORITY_MAP_L4;
13433 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13434 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13436 case RTE_FLOW_ITEM_TYPE_GRE:
13437 flow_dv_translate_item_gre(match_mask, match_value,
13439 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13440 last_item = MLX5_FLOW_LAYER_GRE;
13442 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13443 flow_dv_translate_item_gre_key(match_mask,
13444 match_value, items);
13445 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13447 case RTE_FLOW_ITEM_TYPE_NVGRE:
13448 flow_dv_translate_item_nvgre(match_mask, match_value,
13450 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13451 last_item = MLX5_FLOW_LAYER_GRE;
13453 case RTE_FLOW_ITEM_TYPE_VXLAN:
13454 flow_dv_translate_item_vxlan(dev, attr,
13455 match_mask, match_value,
13457 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13458 last_item = MLX5_FLOW_LAYER_VXLAN;
13460 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13461 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13462 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13463 tunnel_item = items;
13465 case RTE_FLOW_ITEM_TYPE_GENEVE:
13466 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13467 last_item = MLX5_FLOW_LAYER_GENEVE;
13468 tunnel_item = items;
13470 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13471 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13475 return rte_flow_error_set(error, -ret,
13476 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13477 "cannot create GENEVE TLV option");
13478 flow->geneve_tlv_option = 1;
13479 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13481 case RTE_FLOW_ITEM_TYPE_MPLS:
13482 flow_dv_translate_item_mpls(match_mask, match_value,
13483 items, last_item, tunnel);
13484 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13485 last_item = MLX5_FLOW_LAYER_MPLS;
13487 case RTE_FLOW_ITEM_TYPE_MARK:
13488 flow_dv_translate_item_mark(dev, match_mask,
13489 match_value, items);
13490 last_item = MLX5_FLOW_ITEM_MARK;
13492 case RTE_FLOW_ITEM_TYPE_META:
13493 flow_dv_translate_item_meta(dev, match_mask,
13494 match_value, attr, items);
13495 last_item = MLX5_FLOW_ITEM_METADATA;
13497 case RTE_FLOW_ITEM_TYPE_ICMP:
13498 flow_dv_translate_item_icmp(match_mask, match_value,
13500 last_item = MLX5_FLOW_LAYER_ICMP;
13502 case RTE_FLOW_ITEM_TYPE_ICMP6:
13503 flow_dv_translate_item_icmp6(match_mask, match_value,
13505 last_item = MLX5_FLOW_LAYER_ICMP6;
13507 case RTE_FLOW_ITEM_TYPE_TAG:
13508 flow_dv_translate_item_tag(dev, match_mask,
13509 match_value, items);
13510 last_item = MLX5_FLOW_ITEM_TAG;
13512 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13513 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13514 match_value, items);
13515 last_item = MLX5_FLOW_ITEM_TAG;
13517 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13518 flow_dv_translate_item_tx_queue(dev, match_mask,
13521 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13523 case RTE_FLOW_ITEM_TYPE_GTP:
13524 flow_dv_translate_item_gtp(match_mask, match_value,
13526 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13527 last_item = MLX5_FLOW_LAYER_GTP;
13529 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13530 ret = flow_dv_translate_item_gtp_psc(match_mask,
13534 return rte_flow_error_set(error, -ret,
13535 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13536 "cannot create GTP PSC item");
13537 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13539 case RTE_FLOW_ITEM_TYPE_ECPRI:
13540 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13541 /* Create it only the first time to be used. */
13542 ret = mlx5_flex_parser_ecpri_alloc(dev);
13544 return rte_flow_error_set
13546 RTE_FLOW_ERROR_TYPE_ITEM,
13548 "cannot create eCPRI parser");
13550 flow_dv_translate_item_ecpri(dev, match_mask,
13551 match_value, items,
13553 /* No other protocol should follow eCPRI layer. */
13554 last_item = MLX5_FLOW_LAYER_ECPRI;
13556 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13557 flow_dv_translate_item_integrity(items, integrity_items,
13560 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13561 flow_dv_translate_item_aso_ct(dev, match_mask,
13562 match_value, items);
13564 case RTE_FLOW_ITEM_TYPE_FLEX:
13565 flow_dv_translate_item_flex(dev, match_mask,
13566 match_value, items,
13567 dev_flow, tunnel != 0);
13568 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13569 MLX5_FLOW_ITEM_OUTER_FLEX;
13574 item_flags |= last_item;
13577 * When E-Switch mode is enabled, we have two cases where we need to
13578 * set the source port manually.
13579 * The first one, is in case of Nic steering rule, and the second is
13580 * E-Switch rule where no port_id item was found. In both cases
13581 * the source port is set according the current port in use.
13583 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13584 (priv->representor || priv->master)) {
13585 if (flow_dv_translate_item_port_id(dev, match_mask,
13586 match_value, NULL, attr))
13589 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13590 flow_dv_translate_item_integrity_post(match_mask, match_value,
13594 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13595 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13596 tunnel_item, item_flags);
13597 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13598 flow_dv_translate_item_geneve(match_mask, match_value,
13599 tunnel_item, item_flags);
13600 #ifdef RTE_LIBRTE_MLX5_DEBUG
13601 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13602 dev_flow->dv.value.buf));
13605 * Layers may be already initialized from prefix flow if this dev_flow
13606 * is the suffix flow.
13608 handle->layers |= item_flags;
13609 if (action_flags & MLX5_FLOW_ACTION_RSS)
13610 flow_dv_hashfields_set(dev_flow, rss_desc);
13611 /* If has RSS action in the sample action, the Sample/Mirror resource
13612 * should be registered after the hash filed be update.
13614 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13615 ret = flow_dv_translate_action_sample(dev,
13624 ret = flow_dv_create_action_sample(dev,
13633 return rte_flow_error_set
13635 RTE_FLOW_ERROR_TYPE_ACTION,
13637 "cannot create sample action");
13638 if (num_of_dest > 1) {
13639 dev_flow->dv.actions[sample_act_pos] =
13640 dev_flow->dv.dest_array_res->action;
13642 dev_flow->dv.actions[sample_act_pos] =
13643 dev_flow->dv.sample_res->verbs_action;
13647 * For multiple destination (sample action with ratio=1), the encap
13648 * action and port id action will be combined into group action.
13649 * So need remove the original these actions in the flow and only
13650 * use the sample action instead of.
13652 if (num_of_dest > 1 &&
13653 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13655 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13657 for (i = 0; i < actions_n; i++) {
13658 if ((sample_act->dr_encap_action &&
13659 sample_act->dr_encap_action ==
13660 dev_flow->dv.actions[i]) ||
13661 (sample_act->dr_port_id_action &&
13662 sample_act->dr_port_id_action ==
13663 dev_flow->dv.actions[i]) ||
13664 (sample_act->dr_jump_action &&
13665 sample_act->dr_jump_action ==
13666 dev_flow->dv.actions[i]))
13668 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13670 memcpy((void *)dev_flow->dv.actions,
13671 (void *)temp_actions,
13672 tmp_actions_n * sizeof(void *));
13673 actions_n = tmp_actions_n;
13675 dev_flow->dv.actions_n = actions_n;
13676 dev_flow->act_flags = action_flags;
13677 if (wks->skip_matcher_reg)
13679 /* Register matcher. */
13680 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13681 matcher.mask.size);
13682 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13684 dev_flow->external);
13686 * When creating meter drop flow in drop table, using original
13687 * 5-tuple match, the matcher priority should be lower than
13690 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13691 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13692 matcher.priority <= MLX5_REG_BITS)
13693 matcher.priority += MLX5_REG_BITS;
13694 /* reserved field no needs to be set to 0 here. */
13695 tbl_key.is_fdb = attr->transfer;
13696 tbl_key.is_egress = attr->egress;
13697 tbl_key.level = dev_flow->dv.group;
13698 tbl_key.id = dev_flow->dv.table_id;
13699 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13700 tunnel, attr->group, error))
13706 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13709 * @param[in, out] action
13710 * Shred RSS action holding hash RX queue objects.
13711 * @param[in] hash_fields
13712 * Defines combination of packet fields to participate in RX hash.
13713 * @param[in] tunnel
13715 * @param[in] hrxq_idx
13716 * Hash RX queue index to set.
13719 * 0 on success, otherwise negative errno value.
13722 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13723 const uint64_t hash_fields,
13726 uint32_t *hrxqs = action->hrxq;
13728 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13729 case MLX5_RSS_HASH_IPV4:
13730 /* fall-through. */
13731 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13732 /* fall-through. */
13733 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13734 hrxqs[0] = hrxq_idx;
13736 case MLX5_RSS_HASH_IPV4_TCP:
13737 /* fall-through. */
13738 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13739 /* fall-through. */
13740 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13741 hrxqs[1] = hrxq_idx;
13743 case MLX5_RSS_HASH_IPV4_UDP:
13744 /* fall-through. */
13745 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13746 /* fall-through. */
13747 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13748 hrxqs[2] = hrxq_idx;
13750 case MLX5_RSS_HASH_IPV6:
13751 /* fall-through. */
13752 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13753 /* fall-through. */
13754 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13755 hrxqs[3] = hrxq_idx;
13757 case MLX5_RSS_HASH_IPV6_TCP:
13758 /* fall-through. */
13759 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13760 /* fall-through. */
13761 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13762 hrxqs[4] = hrxq_idx;
13764 case MLX5_RSS_HASH_IPV6_UDP:
13765 /* fall-through. */
13766 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13767 /* fall-through. */
13768 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13769 hrxqs[5] = hrxq_idx;
13771 case MLX5_RSS_HASH_NONE:
13772 hrxqs[6] = hrxq_idx;
13780 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13784 * Pointer to the Ethernet device structure.
13786 * Shared RSS action ID holding hash RX queue objects.
13787 * @param[in] hash_fields
13788 * Defines combination of packet fields to participate in RX hash.
13789 * @param[in] tunnel
13793 * Valid hash RX queue index, otherwise 0.
13796 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13797 const uint64_t hash_fields)
13799 struct mlx5_priv *priv = dev->data->dev_private;
13800 struct mlx5_shared_action_rss *shared_rss =
13801 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13802 const uint32_t *hrxqs = shared_rss->hrxq;
13804 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13805 case MLX5_RSS_HASH_IPV4:
13806 /* fall-through. */
13807 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13808 /* fall-through. */
13809 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13811 case MLX5_RSS_HASH_IPV4_TCP:
13812 /* fall-through. */
13813 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13814 /* fall-through. */
13815 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13817 case MLX5_RSS_HASH_IPV4_UDP:
13818 /* fall-through. */
13819 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13820 /* fall-through. */
13821 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13823 case MLX5_RSS_HASH_IPV6:
13824 /* fall-through. */
13825 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13826 /* fall-through. */
13827 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13829 case MLX5_RSS_HASH_IPV6_TCP:
13830 /* fall-through. */
13831 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13832 /* fall-through. */
13833 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13835 case MLX5_RSS_HASH_IPV6_UDP:
13836 /* fall-through. */
13837 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13838 /* fall-through. */
13839 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13841 case MLX5_RSS_HASH_NONE:
13850 * Apply the flow to the NIC, lock free,
13851 * (mutex should be acquired by caller).
13854 * Pointer to the Ethernet device structure.
13855 * @param[in, out] flow
13856 * Pointer to flow structure.
13857 * @param[out] error
13858 * Pointer to error structure.
13861 * 0 on success, a negative errno value otherwise and rte_errno is set.
13864 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13865 struct rte_flow_error *error)
13867 struct mlx5_flow_dv_workspace *dv;
13868 struct mlx5_flow_handle *dh;
13869 struct mlx5_flow_handle_dv *dv_h;
13870 struct mlx5_flow *dev_flow;
13871 struct mlx5_priv *priv = dev->data->dev_private;
13872 uint32_t handle_idx;
13876 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13877 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13881 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13882 dev_flow = &wks->flows[idx];
13883 dv = &dev_flow->dv;
13884 dh = dev_flow->handle;
13887 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13888 if (dv->transfer) {
13889 MLX5_ASSERT(priv->sh->dr_drop_action);
13890 dv->actions[n++] = priv->sh->dr_drop_action;
13892 #ifdef HAVE_MLX5DV_DR
13893 /* DR supports drop action placeholder. */
13894 MLX5_ASSERT(priv->sh->dr_drop_action);
13895 dv->actions[n++] = dv->group ?
13896 priv->sh->dr_drop_action :
13897 priv->root_drop_action;
13899 /* For DV we use the explicit drop queue. */
13900 MLX5_ASSERT(priv->drop_queue.hrxq);
13902 priv->drop_queue.hrxq->action;
13905 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13906 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13907 struct mlx5_hrxq *hrxq;
13910 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13915 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13916 "cannot get hash queue");
13919 dh->rix_hrxq = hrxq_idx;
13920 dv->actions[n++] = hrxq->action;
13921 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13922 struct mlx5_hrxq *hrxq = NULL;
13925 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13926 rss_desc->shared_rss,
13927 dev_flow->hash_fields);
13929 hrxq = mlx5_ipool_get
13930 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13935 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13936 "cannot get hash queue");
13939 dh->rix_srss = rss_desc->shared_rss;
13940 dv->actions[n++] = hrxq->action;
13941 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13942 if (!priv->sh->default_miss_action) {
13945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13946 "default miss action not be created.");
13949 dv->actions[n++] = priv->sh->default_miss_action;
13951 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13952 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13953 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13954 (void *)&dv->value, n,
13955 dv->actions, &dh->drv_flow);
13959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13961 (!priv->config.allow_duplicate_pattern &&
13963 "duplicating pattern is not allowed" :
13964 "hardware refuses to create flow");
13967 if (priv->vmwa_context &&
13968 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13970 * The rule contains the VLAN pattern.
13971 * For VF we are going to create VLAN
13972 * interface to make hypervisor set correct
13973 * e-Switch vport context.
13975 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13980 err = rte_errno; /* Save rte_errno before cleanup. */
13981 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13982 handle_idx, dh, next) {
13983 /* hrxq is union, don't clear it if the flag is not set. */
13984 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13985 mlx5_hrxq_release(dev, dh->rix_hrxq);
13987 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13990 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13991 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13993 rte_errno = err; /* Restore rte_errno. */
13998 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
13999 struct mlx5_list_entry *entry)
14001 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14005 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14006 mlx5_free(resource);
14010 * Release the flow matcher.
14013 * Pointer to Ethernet device.
14015 * Index to port ID action resource.
14018 * 1 while a reference on it exists, 0 when freed.
14021 flow_dv_matcher_release(struct rte_eth_dev *dev,
14022 struct mlx5_flow_handle *handle)
14024 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14025 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14026 typeof(*tbl), tbl);
14029 MLX5_ASSERT(matcher->matcher_object);
14030 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14031 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14036 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14038 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14039 struct mlx5_flow_dv_encap_decap_resource *res =
14040 container_of(entry, typeof(*res), entry);
14042 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14043 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14047 * Release an encap/decap resource.
14050 * Pointer to Ethernet device.
14051 * @param encap_decap_idx
14052 * Index of encap decap resource.
14055 * 1 while a reference on it exists, 0 when freed.
14058 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14059 uint32_t encap_decap_idx)
14061 struct mlx5_priv *priv = dev->data->dev_private;
14062 struct mlx5_flow_dv_encap_decap_resource *resource;
14064 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14068 MLX5_ASSERT(resource->action);
14069 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14073 * Release an jump to table action resource.
14076 * Pointer to Ethernet device.
14078 * Index to the jump action resource.
14081 * 1 while a reference on it exists, 0 when freed.
14084 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14087 struct mlx5_priv *priv = dev->data->dev_private;
14088 struct mlx5_flow_tbl_data_entry *tbl_data;
14090 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14094 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14098 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14100 struct mlx5_flow_dv_modify_hdr_resource *res =
14101 container_of(entry, typeof(*res), entry);
14102 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14104 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14105 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14109 * Release a modify-header resource.
14112 * Pointer to Ethernet device.
14114 * Pointer to mlx5_flow_handle.
14117 * 1 while a reference on it exists, 0 when freed.
14120 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14121 struct mlx5_flow_handle *handle)
14123 struct mlx5_priv *priv = dev->data->dev_private;
14124 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14126 MLX5_ASSERT(entry->action);
14127 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14131 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14133 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14134 struct mlx5_flow_dv_port_id_action_resource *resource =
14135 container_of(entry, typeof(*resource), entry);
14137 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14138 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14142 * Release port ID action resource.
14145 * Pointer to Ethernet device.
14147 * Pointer to mlx5_flow_handle.
14150 * 1 while a reference on it exists, 0 when freed.
14153 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14156 struct mlx5_priv *priv = dev->data->dev_private;
14157 struct mlx5_flow_dv_port_id_action_resource *resource;
14159 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14162 MLX5_ASSERT(resource->action);
14163 return mlx5_list_unregister(priv->sh->port_id_action_list,
14168 * Release shared RSS action resource.
14171 * Pointer to Ethernet device.
14173 * Shared RSS action index.
14176 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14178 struct mlx5_priv *priv = dev->data->dev_private;
14179 struct mlx5_shared_action_rss *shared_rss;
14181 shared_rss = mlx5_ipool_get
14182 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14183 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14187 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14189 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14190 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14191 container_of(entry, typeof(*resource), entry);
14193 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14194 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14198 * Release push vlan action resource.
14201 * Pointer to Ethernet device.
14203 * Pointer to mlx5_flow_handle.
14206 * 1 while a reference on it exists, 0 when freed.
14209 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14210 struct mlx5_flow_handle *handle)
14212 struct mlx5_priv *priv = dev->data->dev_private;
14213 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14214 uint32_t idx = handle->dvh.rix_push_vlan;
14216 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14219 MLX5_ASSERT(resource->action);
14220 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14225 * Release the fate resource.
14228 * Pointer to Ethernet device.
14230 * Pointer to mlx5_flow_handle.
14233 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14234 struct mlx5_flow_handle *handle)
14236 if (!handle->rix_fate)
14238 switch (handle->fate_action) {
14239 case MLX5_FLOW_FATE_QUEUE:
14240 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14241 mlx5_hrxq_release(dev, handle->rix_hrxq);
14243 case MLX5_FLOW_FATE_JUMP:
14244 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14246 case MLX5_FLOW_FATE_PORT_ID:
14247 flow_dv_port_id_action_resource_release(dev,
14248 handle->rix_port_id_action);
14251 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14254 handle->rix_fate = 0;
14258 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14259 struct mlx5_list_entry *entry)
14261 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14264 struct rte_eth_dev *dev = resource->dev;
14265 struct mlx5_priv *priv = dev->data->dev_private;
14267 if (resource->verbs_action)
14268 claim_zero(mlx5_flow_os_destroy_flow_action
14269 (resource->verbs_action));
14270 if (resource->normal_path_tbl)
14271 flow_dv_tbl_resource_release(MLX5_SH(dev),
14272 resource->normal_path_tbl);
14273 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14274 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14275 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14279 * Release an sample resource.
14282 * Pointer to Ethernet device.
14284 * Pointer to mlx5_flow_handle.
14287 * 1 while a reference on it exists, 0 when freed.
14290 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14291 struct mlx5_flow_handle *handle)
14293 struct mlx5_priv *priv = dev->data->dev_private;
14294 struct mlx5_flow_dv_sample_resource *resource;
14296 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14297 handle->dvh.rix_sample);
14300 MLX5_ASSERT(resource->verbs_action);
14301 return mlx5_list_unregister(priv->sh->sample_action_list,
14306 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14307 struct mlx5_list_entry *entry)
14309 struct mlx5_flow_dv_dest_array_resource *resource =
14310 container_of(entry, typeof(*resource), entry);
14311 struct rte_eth_dev *dev = resource->dev;
14312 struct mlx5_priv *priv = dev->data->dev_private;
14315 MLX5_ASSERT(resource->action);
14316 if (resource->action)
14317 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14318 for (; i < resource->num_of_dest; i++)
14319 flow_dv_sample_sub_actions_release(dev,
14320 &resource->sample_idx[i]);
14321 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14322 DRV_LOG(DEBUG, "destination array resource %p: removed",
14327 * Release an destination array resource.
14330 * Pointer to Ethernet device.
14332 * Pointer to mlx5_flow_handle.
14335 * 1 while a reference on it exists, 0 when freed.
14338 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14339 struct mlx5_flow_handle *handle)
14341 struct mlx5_priv *priv = dev->data->dev_private;
14342 struct mlx5_flow_dv_dest_array_resource *resource;
14344 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14345 handle->dvh.rix_dest_array);
14348 MLX5_ASSERT(resource->action);
14349 return mlx5_list_unregister(priv->sh->dest_array_list,
14354 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14356 struct mlx5_priv *priv = dev->data->dev_private;
14357 struct mlx5_dev_ctx_shared *sh = priv->sh;
14358 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14359 sh->geneve_tlv_option_resource;
14360 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14361 if (geneve_opt_resource) {
14362 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14363 __ATOMIC_RELAXED))) {
14364 claim_zero(mlx5_devx_cmd_destroy
14365 (geneve_opt_resource->obj));
14366 mlx5_free(sh->geneve_tlv_option_resource);
14367 sh->geneve_tlv_option_resource = NULL;
14370 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14374 * Remove the flow from the NIC but keeps it in memory.
14375 * Lock free, (mutex should be acquired by caller).
14378 * Pointer to Ethernet device.
14379 * @param[in, out] flow
14380 * Pointer to flow structure.
14383 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14385 struct mlx5_flow_handle *dh;
14386 uint32_t handle_idx;
14387 struct mlx5_priv *priv = dev->data->dev_private;
14391 handle_idx = flow->dev_handles;
14392 while (handle_idx) {
14393 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14397 if (dh->drv_flow) {
14398 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14399 dh->drv_flow = NULL;
14401 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14402 flow_dv_fate_resource_release(dev, dh);
14403 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14404 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14405 handle_idx = dh->next.next;
14410 * Remove the flow from the NIC and the memory.
14411 * Lock free, (mutex should be acquired by caller).
14414 * Pointer to the Ethernet device structure.
14415 * @param[in, out] flow
14416 * Pointer to flow structure.
14419 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14421 struct mlx5_flow_handle *dev_handle;
14422 struct mlx5_priv *priv = dev->data->dev_private;
14423 struct mlx5_flow_meter_info *fm = NULL;
14428 flow_dv_remove(dev, flow);
14429 if (flow->counter) {
14430 flow_dv_counter_free(dev, flow->counter);
14434 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14436 mlx5_flow_meter_detach(priv, fm);
14439 /* Keep the current age handling by default. */
14440 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14441 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14442 else if (flow->age)
14443 flow_dv_aso_age_release(dev, flow->age);
14444 if (flow->geneve_tlv_option) {
14445 flow_dv_geneve_tlv_option_resource_release(dev);
14446 flow->geneve_tlv_option = 0;
14448 while (flow->dev_handles) {
14449 uint32_t tmp_idx = flow->dev_handles;
14451 dev_handle = mlx5_ipool_get(priv->sh->ipool
14452 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14455 flow->dev_handles = dev_handle->next.next;
14456 while (dev_handle->flex_item) {
14457 int index = rte_bsf32(dev_handle->flex_item);
14459 mlx5_flex_release_index(dev, index);
14460 dev_handle->flex_item &= ~RTE_BIT32(index);
14462 if (dev_handle->dvh.matcher)
14463 flow_dv_matcher_release(dev, dev_handle);
14464 if (dev_handle->dvh.rix_sample)
14465 flow_dv_sample_resource_release(dev, dev_handle);
14466 if (dev_handle->dvh.rix_dest_array)
14467 flow_dv_dest_array_resource_release(dev, dev_handle);
14468 if (dev_handle->dvh.rix_encap_decap)
14469 flow_dv_encap_decap_resource_release(dev,
14470 dev_handle->dvh.rix_encap_decap);
14471 if (dev_handle->dvh.modify_hdr)
14472 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14473 if (dev_handle->dvh.rix_push_vlan)
14474 flow_dv_push_vlan_action_resource_release(dev,
14476 if (dev_handle->dvh.rix_tag)
14477 flow_dv_tag_release(dev,
14478 dev_handle->dvh.rix_tag);
14479 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14480 flow_dv_fate_resource_release(dev, dev_handle);
14482 srss = dev_handle->rix_srss;
14483 if (fm && dev_handle->is_meter_flow_id &&
14484 dev_handle->split_flow_id)
14485 mlx5_ipool_free(fm->flow_ipool,
14486 dev_handle->split_flow_id);
14487 else if (dev_handle->split_flow_id &&
14488 !dev_handle->is_meter_flow_id)
14489 mlx5_ipool_free(priv->sh->ipool
14490 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14491 dev_handle->split_flow_id);
14492 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14496 flow_dv_shared_rss_action_release(dev, srss);
14500 * Release array of hash RX queue objects.
14504 * Pointer to the Ethernet device structure.
14505 * @param[in, out] hrxqs
14506 * Array of hash RX queue objects.
14509 * Total number of references to hash RX queue objects in *hrxqs* array
14510 * after this operation.
14513 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14514 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14519 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14520 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14530 * Release all hash RX queue objects representing shared RSS action.
14533 * Pointer to the Ethernet device structure.
14534 * @param[in, out] action
14535 * Shared RSS action to remove hash RX queue objects from.
14538 * Total number of references to hash RX queue objects stored in *action*
14539 * after this operation.
14540 * Expected to be 0 if no external references held.
14543 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14544 struct mlx5_shared_action_rss *shared_rss)
14546 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14550 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14553 * Only one hash value is available for one L3+L4 combination:
14555 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14556 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14557 * same slot in mlx5_rss_hash_fields.
14560 * Pointer to the shared action RSS conf.
14561 * @param[in, out] hash_field
14562 * hash_field variable needed to be adjusted.
14568 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14569 uint64_t *hash_field)
14571 uint64_t rss_types = rss->origin.types;
14573 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14574 case MLX5_RSS_HASH_IPV4:
14575 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14576 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14577 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14578 *hash_field |= IBV_RX_HASH_DST_IPV4;
14579 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14580 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14582 *hash_field |= MLX5_RSS_HASH_IPV4;
14585 case MLX5_RSS_HASH_IPV6:
14586 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14587 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14588 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14589 *hash_field |= IBV_RX_HASH_DST_IPV6;
14590 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14591 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14593 *hash_field |= MLX5_RSS_HASH_IPV6;
14596 case MLX5_RSS_HASH_IPV4_UDP:
14597 /* fall-through. */
14598 case MLX5_RSS_HASH_IPV6_UDP:
14599 if (rss_types & RTE_ETH_RSS_UDP) {
14600 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14601 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14602 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14603 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14604 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14606 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14609 case MLX5_RSS_HASH_IPV4_TCP:
14610 /* fall-through. */
14611 case MLX5_RSS_HASH_IPV6_TCP:
14612 if (rss_types & RTE_ETH_RSS_TCP) {
14613 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14614 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14615 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14616 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14617 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14619 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14628 * Setup shared RSS action.
14629 * Prepare set of hash RX queue objects sufficient to handle all valid
14630 * hash_fields combinations (see enum ibv_rx_hash_fields).
14633 * Pointer to the Ethernet device structure.
14634 * @param[in] action_idx
14635 * Shared RSS action ipool index.
14636 * @param[in, out] action
14637 * Partially initialized shared RSS action.
14638 * @param[out] error
14639 * Perform verbose error reporting if not NULL. Initialized in case of
14643 * 0 on success, otherwise negative errno value.
14646 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14647 uint32_t action_idx,
14648 struct mlx5_shared_action_rss *shared_rss,
14649 struct rte_flow_error *error)
14651 struct mlx5_flow_rss_desc rss_desc = { 0 };
14655 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14656 return rte_flow_error_set(error, rte_errno,
14657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14658 "cannot setup indirection table");
14660 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14661 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14662 rss_desc.const_q = shared_rss->origin.queue;
14663 rss_desc.queue_num = shared_rss->origin.queue_num;
14664 /* Set non-zero value to indicate a shared RSS. */
14665 rss_desc.shared_rss = action_idx;
14666 rss_desc.ind_tbl = shared_rss->ind_tbl;
14667 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14669 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14672 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14673 if (shared_rss->origin.level > 1) {
14674 hash_fields |= IBV_RX_HASH_INNER;
14677 rss_desc.tunnel = tunnel;
14678 rss_desc.hash_fields = hash_fields;
14679 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14683 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14684 "cannot get hash queue");
14685 goto error_hrxq_new;
14687 err = __flow_dv_action_rss_hrxq_set
14688 (shared_rss, hash_fields, hrxq_idx);
14694 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14695 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14696 shared_rss->ind_tbl = NULL;
14702 * Create shared RSS action.
14705 * Pointer to the Ethernet device structure.
14707 * Shared action configuration.
14709 * RSS action specification used to create shared action.
14710 * @param[out] error
14711 * Perform verbose error reporting if not NULL. Initialized in case of
14715 * A valid shared action ID in case of success, 0 otherwise and
14716 * rte_errno is set.
14719 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14720 const struct rte_flow_indir_action_conf *conf,
14721 const struct rte_flow_action_rss *rss,
14722 struct rte_flow_error *error)
14724 struct mlx5_priv *priv = dev->data->dev_private;
14725 struct mlx5_shared_action_rss *shared_rss = NULL;
14726 void *queue = NULL;
14727 struct rte_flow_action_rss *origin;
14728 const uint8_t *rss_key;
14729 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14732 RTE_SET_USED(conf);
14733 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14735 shared_rss = mlx5_ipool_zmalloc
14736 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14737 if (!shared_rss || !queue) {
14738 rte_flow_error_set(error, ENOMEM,
14739 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14740 "cannot allocate resource memory");
14741 goto error_rss_init;
14743 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14744 rte_flow_error_set(error, E2BIG,
14745 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14746 "rss action number out of range");
14747 goto error_rss_init;
14749 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14750 sizeof(*shared_rss->ind_tbl),
14752 if (!shared_rss->ind_tbl) {
14753 rte_flow_error_set(error, ENOMEM,
14754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14755 "cannot allocate resource memory");
14756 goto error_rss_init;
14758 memcpy(queue, rss->queue, queue_size);
14759 shared_rss->ind_tbl->queues = queue;
14760 shared_rss->ind_tbl->queues_n = rss->queue_num;
14761 origin = &shared_rss->origin;
14762 origin->func = rss->func;
14763 origin->level = rss->level;
14764 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14765 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14766 /* NULL RSS key indicates default RSS key. */
14767 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14768 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14769 origin->key = &shared_rss->key[0];
14770 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14771 origin->queue = queue;
14772 origin->queue_num = rss->queue_num;
14773 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14774 goto error_rss_init;
14775 rte_spinlock_init(&shared_rss->action_rss_sl);
14776 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14777 rte_spinlock_lock(&priv->shared_act_sl);
14778 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14779 &priv->rss_shared_actions, idx, shared_rss, next);
14780 rte_spinlock_unlock(&priv->shared_act_sl);
14784 if (shared_rss->ind_tbl)
14785 mlx5_free(shared_rss->ind_tbl);
14786 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14795 * Destroy the shared RSS action.
14796 * Release related hash RX queue objects.
14799 * Pointer to the Ethernet device structure.
14801 * The shared RSS action object ID to be removed.
14802 * @param[out] error
14803 * Perform verbose error reporting if not NULL. Initialized in case of
14807 * 0 on success, otherwise negative errno value.
14810 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14811 struct rte_flow_error *error)
14813 struct mlx5_priv *priv = dev->data->dev_private;
14814 struct mlx5_shared_action_rss *shared_rss =
14815 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14816 uint32_t old_refcnt = 1;
14818 uint16_t *queue = NULL;
14821 return rte_flow_error_set(error, EINVAL,
14822 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14823 "invalid shared action");
14824 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14825 0, 0, __ATOMIC_ACQUIRE,
14827 return rte_flow_error_set(error, EBUSY,
14828 RTE_FLOW_ERROR_TYPE_ACTION,
14830 "shared rss has references");
14831 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14833 return rte_flow_error_set(error, EBUSY,
14834 RTE_FLOW_ERROR_TYPE_ACTION,
14836 "shared rss hrxq has references");
14837 queue = shared_rss->ind_tbl->queues;
14838 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14840 return rte_flow_error_set(error, EBUSY,
14841 RTE_FLOW_ERROR_TYPE_ACTION,
14843 "shared rss indirection table has"
14846 rte_spinlock_lock(&priv->shared_act_sl);
14847 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14848 &priv->rss_shared_actions, idx, shared_rss, next);
14849 rte_spinlock_unlock(&priv->shared_act_sl);
14850 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14856 * Create indirect action, lock free,
14857 * (mutex should be acquired by caller).
14858 * Dispatcher for action type specific call.
14861 * Pointer to the Ethernet device structure.
14863 * Shared action configuration.
14864 * @param[in] action
14865 * Action specification used to create indirect action.
14866 * @param[out] error
14867 * Perform verbose error reporting if not NULL. Initialized in case of
14871 * A valid shared action handle in case of success, NULL otherwise and
14872 * rte_errno is set.
14874 static struct rte_flow_action_handle *
14875 flow_dv_action_create(struct rte_eth_dev *dev,
14876 const struct rte_flow_indir_action_conf *conf,
14877 const struct rte_flow_action *action,
14878 struct rte_flow_error *err)
14880 struct mlx5_priv *priv = dev->data->dev_private;
14881 uint32_t age_idx = 0;
14885 switch (action->type) {
14886 case RTE_FLOW_ACTION_TYPE_RSS:
14887 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14888 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14889 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14891 case RTE_FLOW_ACTION_TYPE_AGE:
14892 age_idx = flow_dv_aso_age_alloc(dev, err);
14897 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14898 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14899 flow_dv_aso_age_params_init(dev, age_idx,
14900 ((const struct rte_flow_action_age *)
14901 action->conf)->context ?
14902 ((const struct rte_flow_action_age *)
14903 action->conf)->context :
14904 (void *)(uintptr_t)idx,
14905 ((const struct rte_flow_action_age *)
14906 action->conf)->timeout);
14909 case RTE_FLOW_ACTION_TYPE_COUNT:
14910 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14911 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14912 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14914 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14915 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14917 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14920 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14921 NULL, "action type not supported");
14924 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14928 * Destroy the indirect action.
14929 * Release action related resources on the NIC and the memory.
14930 * Lock free, (mutex should be acquired by caller).
14931 * Dispatcher for action type specific call.
14934 * Pointer to the Ethernet device structure.
14935 * @param[in] handle
14936 * The indirect action object handle to be removed.
14937 * @param[out] error
14938 * Perform verbose error reporting if not NULL. Initialized in case of
14942 * 0 on success, otherwise negative errno value.
14945 flow_dv_action_destroy(struct rte_eth_dev *dev,
14946 struct rte_flow_action_handle *handle,
14947 struct rte_flow_error *error)
14949 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14950 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14951 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14952 struct mlx5_flow_counter *cnt;
14953 uint32_t no_flow_refcnt = 1;
14957 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14958 return __flow_dv_action_rss_release(dev, idx, error);
14959 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14960 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14961 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14962 &no_flow_refcnt, 1, false,
14965 return rte_flow_error_set(error, EBUSY,
14966 RTE_FLOW_ERROR_TYPE_ACTION,
14968 "Indirect count action has references");
14969 flow_dv_counter_free(dev, idx);
14971 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14972 ret = flow_dv_aso_age_release(dev, idx);
14975 * In this case, the last flow has a reference will
14976 * actually release the age action.
14978 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14979 " released with references %d.", idx, ret);
14981 case MLX5_INDIRECT_ACTION_TYPE_CT:
14982 ret = flow_dv_aso_ct_release(dev, idx, error);
14986 DRV_LOG(DEBUG, "Connection tracking object %u still "
14987 "has references %d.", idx, ret);
14990 return rte_flow_error_set(error, ENOTSUP,
14991 RTE_FLOW_ERROR_TYPE_ACTION,
14993 "action type not supported");
14998 * Updates in place shared RSS action configuration.
15001 * Pointer to the Ethernet device structure.
15003 * The shared RSS action object ID to be updated.
15004 * @param[in] action_conf
15005 * RSS action specification used to modify *shared_rss*.
15006 * @param[out] error
15007 * Perform verbose error reporting if not NULL. Initialized in case of
15011 * 0 on success, otherwise negative errno value.
15012 * @note: currently only support update of RSS queues.
15015 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15016 const struct rte_flow_action_rss *action_conf,
15017 struct rte_flow_error *error)
15019 struct mlx5_priv *priv = dev->data->dev_private;
15020 struct mlx5_shared_action_rss *shared_rss =
15021 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15023 void *queue = NULL;
15024 uint16_t *queue_old = NULL;
15025 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15028 return rte_flow_error_set(error, EINVAL,
15029 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15030 "invalid shared action to update");
15031 if (priv->obj_ops.ind_table_modify == NULL)
15032 return rte_flow_error_set(error, ENOTSUP,
15033 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15034 "cannot modify indirection table");
15035 queue = mlx5_malloc(MLX5_MEM_ZERO,
15036 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15039 return rte_flow_error_set(error, ENOMEM,
15040 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15042 "cannot allocate resource memory");
15043 memcpy(queue, action_conf->queue, queue_size);
15044 MLX5_ASSERT(shared_rss->ind_tbl);
15045 rte_spinlock_lock(&shared_rss->action_rss_sl);
15046 queue_old = shared_rss->ind_tbl->queues;
15047 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15048 queue, action_conf->queue_num, true);
15051 ret = rte_flow_error_set(error, rte_errno,
15052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15053 "cannot update indirection table");
15055 mlx5_free(queue_old);
15056 shared_rss->origin.queue = queue;
15057 shared_rss->origin.queue_num = action_conf->queue_num;
15059 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15064 * Updates in place conntrack context or direction.
15065 * Context update should be synchronized.
15068 * Pointer to the Ethernet device structure.
15070 * The conntrack object ID to be updated.
15071 * @param[in] update
15072 * Pointer to the structure of information to update.
15073 * @param[out] error
15074 * Perform verbose error reporting if not NULL. Initialized in case of
15078 * 0 on success, otherwise negative errno value.
15081 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15082 const struct rte_flow_modify_conntrack *update,
15083 struct rte_flow_error *error)
15085 struct mlx5_priv *priv = dev->data->dev_private;
15086 struct mlx5_aso_ct_action *ct;
15087 const struct rte_flow_action_conntrack *new_prf;
15089 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15092 if (PORT_ID(priv) != owner)
15093 return rte_flow_error_set(error, EACCES,
15094 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15096 "CT object owned by another port");
15097 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15098 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15100 return rte_flow_error_set(error, ENOMEM,
15101 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15103 "CT object is inactive");
15104 new_prf = &update->new_ct;
15105 if (update->direction)
15106 ct->is_original = !!new_prf->is_original_dir;
15107 if (update->state) {
15108 /* Only validate the profile when it needs to be updated. */
15109 ret = mlx5_validate_action_ct(dev, new_prf, error);
15112 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15114 return rte_flow_error_set(error, EIO,
15115 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15117 "Failed to send CT context update WQE");
15118 /* Block until ready or a failure. */
15119 ret = mlx5_aso_ct_available(priv->sh, ct);
15121 rte_flow_error_set(error, rte_errno,
15122 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15124 "Timeout to get the CT update");
15130 * Updates in place shared action configuration, lock free,
15131 * (mutex should be acquired by caller).
15134 * Pointer to the Ethernet device structure.
15135 * @param[in] handle
15136 * The indirect action object handle to be updated.
15137 * @param[in] update
15138 * Action specification used to modify the action pointed by *handle*.
15139 * *update* could be of same type with the action pointed by the *handle*
15140 * handle argument, or some other structures like a wrapper, depending on
15141 * the indirect action type.
15142 * @param[out] error
15143 * Perform verbose error reporting if not NULL. Initialized in case of
15147 * 0 on success, otherwise negative errno value.
15150 flow_dv_action_update(struct rte_eth_dev *dev,
15151 struct rte_flow_action_handle *handle,
15152 const void *update,
15153 struct rte_flow_error *err)
15155 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15156 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15157 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15158 const void *action_conf;
15161 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15162 action_conf = ((const struct rte_flow_action *)update)->conf;
15163 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15164 case MLX5_INDIRECT_ACTION_TYPE_CT:
15165 return __flow_dv_action_ct_update(dev, idx, update, err);
15167 return rte_flow_error_set(err, ENOTSUP,
15168 RTE_FLOW_ERROR_TYPE_ACTION,
15170 "action type update not supported");
15175 * Destroy the meter sub policy table rules.
15176 * Lock free, (mutex should be acquired by caller).
15179 * Pointer to Ethernet device.
15180 * @param[in] sub_policy
15181 * Pointer to meter sub policy table.
15184 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15185 struct mlx5_flow_meter_sub_policy *sub_policy)
15187 struct mlx5_priv *priv = dev->data->dev_private;
15188 struct mlx5_flow_tbl_data_entry *tbl;
15189 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15190 struct mlx5_flow_meter_info *next_fm;
15191 struct mlx5_sub_policy_color_rule *color_rule;
15195 for (i = 0; i < RTE_COLORS; i++) {
15197 if (i == RTE_COLOR_GREEN && policy &&
15198 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15199 next_fm = mlx5_flow_meter_find(priv,
15200 policy->act_cnt[i].next_mtr_id, NULL);
15201 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15203 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15204 tbl = container_of(color_rule->matcher->tbl,
15205 typeof(*tbl), tbl);
15206 mlx5_list_unregister(tbl->matchers,
15207 &color_rule->matcher->entry);
15208 TAILQ_REMOVE(&sub_policy->color_rules[i],
15209 color_rule, next_port);
15210 mlx5_free(color_rule);
15212 mlx5_flow_meter_detach(priv, next_fm);
15215 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15216 if (sub_policy->rix_hrxq[i]) {
15217 if (policy && !policy->is_hierarchy)
15218 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15219 sub_policy->rix_hrxq[i] = 0;
15221 if (sub_policy->jump_tbl[i]) {
15222 flow_dv_tbl_resource_release(MLX5_SH(dev),
15223 sub_policy->jump_tbl[i]);
15224 sub_policy->jump_tbl[i] = NULL;
15227 if (sub_policy->tbl_rsc) {
15228 flow_dv_tbl_resource_release(MLX5_SH(dev),
15229 sub_policy->tbl_rsc);
15230 sub_policy->tbl_rsc = NULL;
15235 * Destroy policy rules, lock free,
15236 * (mutex should be acquired by caller).
15237 * Dispatcher for action type specific call.
15240 * Pointer to the Ethernet device structure.
15241 * @param[in] mtr_policy
15242 * Meter policy struct.
15245 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15246 struct mlx5_flow_meter_policy *mtr_policy)
15249 struct mlx5_flow_meter_sub_policy *sub_policy;
15250 uint16_t sub_policy_num;
15252 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15253 sub_policy_num = (mtr_policy->sub_policy_num >>
15254 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15255 MLX5_MTR_SUB_POLICY_NUM_MASK;
15256 for (j = 0; j < sub_policy_num; j++) {
15257 sub_policy = mtr_policy->sub_policys[i][j];
15259 __flow_dv_destroy_sub_policy_rules(dev,
15266 * Destroy policy action, lock free,
15267 * (mutex should be acquired by caller).
15268 * Dispatcher for action type specific call.
15271 * Pointer to the Ethernet device structure.
15272 * @param[in] mtr_policy
15273 * Meter policy struct.
15276 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15277 struct mlx5_flow_meter_policy *mtr_policy)
15279 struct rte_flow_action *rss_action;
15280 struct mlx5_flow_handle dev_handle;
15283 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15284 if (mtr_policy->act_cnt[i].rix_mark) {
15285 flow_dv_tag_release(dev,
15286 mtr_policy->act_cnt[i].rix_mark);
15287 mtr_policy->act_cnt[i].rix_mark = 0;
15289 if (mtr_policy->act_cnt[i].modify_hdr) {
15290 dev_handle.dvh.modify_hdr =
15291 mtr_policy->act_cnt[i].modify_hdr;
15292 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15294 switch (mtr_policy->act_cnt[i].fate_action) {
15295 case MLX5_FLOW_FATE_SHARED_RSS:
15296 rss_action = mtr_policy->act_cnt[i].rss;
15297 mlx5_free(rss_action);
15299 case MLX5_FLOW_FATE_PORT_ID:
15300 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15301 flow_dv_port_id_action_resource_release(dev,
15302 mtr_policy->act_cnt[i].rix_port_id_action);
15303 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15306 case MLX5_FLOW_FATE_DROP:
15307 case MLX5_FLOW_FATE_JUMP:
15308 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15309 mtr_policy->act_cnt[i].dr_jump_action[j] =
15313 /*Queue action do nothing*/
15317 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15318 mtr_policy->dr_drop_action[j] = NULL;
15322 * Create policy action per domain, lock free,
15323 * (mutex should be acquired by caller).
15324 * Dispatcher for action type specific call.
15327 * Pointer to the Ethernet device structure.
15328 * @param[in] mtr_policy
15329 * Meter policy struct.
15330 * @param[in] action
15331 * Action specification used to create meter actions.
15332 * @param[out] error
15333 * Perform verbose error reporting if not NULL. Initialized in case of
15337 * 0 on success, otherwise negative errno value.
15340 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15341 struct mlx5_flow_meter_policy *mtr_policy,
15342 const struct rte_flow_action *actions[RTE_COLORS],
15343 enum mlx5_meter_domain domain,
15344 struct rte_mtr_error *error)
15346 struct mlx5_priv *priv = dev->data->dev_private;
15347 struct rte_flow_error flow_err;
15348 const struct rte_flow_action *act;
15349 uint64_t action_flags;
15350 struct mlx5_flow_handle dh;
15351 struct mlx5_flow dev_flow;
15352 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15354 uint8_t egress, transfer;
15355 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15357 struct mlx5_flow_dv_modify_hdr_resource res;
15358 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15359 sizeof(struct mlx5_modification_cmd) *
15360 (MLX5_MAX_MODIFY_NUM + 1)];
15362 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15364 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15365 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15366 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15367 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15368 memset(&port_id_action, 0,
15369 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15370 memset(mhdr_res, 0, sizeof(*mhdr_res));
15371 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15372 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15373 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15374 dev_flow.handle = &dh;
15375 dev_flow.dv.port_id_action = &port_id_action;
15376 dev_flow.external = true;
15377 for (i = 0; i < RTE_COLORS; i++) {
15378 if (i < MLX5_MTR_RTE_COLORS)
15379 act_cnt = &mtr_policy->act_cnt[i];
15380 /* Skip the color policy actions creation. */
15381 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15382 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15385 for (act = actions[i];
15386 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15387 switch (act->type) {
15388 case RTE_FLOW_ACTION_TYPE_MARK:
15390 uint32_t tag_be = mlx5_flow_mark_set
15391 (((const struct rte_flow_action_mark *)
15394 if (i >= MLX5_MTR_RTE_COLORS)
15395 return -rte_mtr_error_set(error,
15397 RTE_MTR_ERROR_TYPE_METER_POLICY,
15399 "cannot create policy "
15400 "mark action for this color");
15401 dev_flow.handle->mark = 1;
15402 if (flow_dv_tag_resource_register(dev, tag_be,
15403 &dev_flow, &flow_err))
15404 return -rte_mtr_error_set(error,
15406 RTE_MTR_ERROR_TYPE_METER_POLICY,
15408 "cannot setup policy mark action");
15409 MLX5_ASSERT(dev_flow.dv.tag_resource);
15410 act_cnt->rix_mark =
15411 dev_flow.handle->dvh.rix_tag;
15412 action_flags |= MLX5_FLOW_ACTION_MARK;
15415 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15416 if (i >= MLX5_MTR_RTE_COLORS)
15417 return -rte_mtr_error_set(error,
15419 RTE_MTR_ERROR_TYPE_METER_POLICY,
15421 "cannot create policy "
15422 "set tag action for this color");
15423 if (flow_dv_convert_action_set_tag
15425 (const struct rte_flow_action_set_tag *)
15426 act->conf, &flow_err))
15427 return -rte_mtr_error_set(error,
15429 RTE_MTR_ERROR_TYPE_METER_POLICY,
15430 NULL, "cannot convert policy "
15432 if (!mhdr_res->actions_num)
15433 return -rte_mtr_error_set(error,
15435 RTE_MTR_ERROR_TYPE_METER_POLICY,
15436 NULL, "cannot find policy "
15438 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15440 case RTE_FLOW_ACTION_TYPE_DROP:
15442 struct mlx5_flow_mtr_mng *mtrmng =
15444 struct mlx5_flow_tbl_data_entry *tbl_data;
15447 * Create the drop table with
15448 * METER DROP level.
15450 if (!mtrmng->drop_tbl[domain]) {
15451 mtrmng->drop_tbl[domain] =
15452 flow_dv_tbl_resource_get(dev,
15453 MLX5_FLOW_TABLE_LEVEL_METER,
15454 egress, transfer, false, NULL, 0,
15455 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15456 if (!mtrmng->drop_tbl[domain])
15457 return -rte_mtr_error_set
15459 RTE_MTR_ERROR_TYPE_METER_POLICY,
15461 "Failed to create meter drop table");
15463 tbl_data = container_of
15464 (mtrmng->drop_tbl[domain],
15465 struct mlx5_flow_tbl_data_entry, tbl);
15466 if (i < MLX5_MTR_RTE_COLORS) {
15467 act_cnt->dr_jump_action[domain] =
15468 tbl_data->jump.action;
15469 act_cnt->fate_action =
15470 MLX5_FLOW_FATE_DROP;
15472 if (i == RTE_COLOR_RED)
15473 mtr_policy->dr_drop_action[domain] =
15474 tbl_data->jump.action;
15475 action_flags |= MLX5_FLOW_ACTION_DROP;
15478 case RTE_FLOW_ACTION_TYPE_QUEUE:
15480 if (i >= MLX5_MTR_RTE_COLORS)
15481 return -rte_mtr_error_set(error,
15483 RTE_MTR_ERROR_TYPE_METER_POLICY,
15484 NULL, "cannot create policy "
15485 "fate queue for this color");
15487 ((const struct rte_flow_action_queue *)
15488 (act->conf))->index;
15489 act_cnt->fate_action =
15490 MLX5_FLOW_FATE_QUEUE;
15491 dev_flow.handle->fate_action =
15492 MLX5_FLOW_FATE_QUEUE;
15493 mtr_policy->is_queue = 1;
15494 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15497 case RTE_FLOW_ACTION_TYPE_RSS:
15501 if (i >= MLX5_MTR_RTE_COLORS)
15502 return -rte_mtr_error_set(error,
15504 RTE_MTR_ERROR_TYPE_METER_POLICY,
15506 "cannot create policy "
15507 "rss action for this color");
15509 * Save RSS conf into policy struct
15510 * for translate stage.
15512 rss_size = (int)rte_flow_conv
15513 (RTE_FLOW_CONV_OP_ACTION,
15514 NULL, 0, act, &flow_err);
15516 return -rte_mtr_error_set(error,
15518 RTE_MTR_ERROR_TYPE_METER_POLICY,
15519 NULL, "Get the wrong "
15520 "rss action struct size");
15521 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15522 rss_size, 0, SOCKET_ID_ANY);
15524 return -rte_mtr_error_set(error,
15526 RTE_MTR_ERROR_TYPE_METER_POLICY,
15528 "Fail to malloc rss action memory");
15529 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15530 act_cnt->rss, rss_size,
15533 return -rte_mtr_error_set(error,
15535 RTE_MTR_ERROR_TYPE_METER_POLICY,
15536 NULL, "Fail to save "
15537 "rss action into policy struct");
15538 act_cnt->fate_action =
15539 MLX5_FLOW_FATE_SHARED_RSS;
15540 action_flags |= MLX5_FLOW_ACTION_RSS;
15543 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15544 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15546 struct mlx5_flow_dv_port_id_action_resource
15548 uint32_t port_id = 0;
15550 if (i >= MLX5_MTR_RTE_COLORS)
15551 return -rte_mtr_error_set(error,
15553 RTE_MTR_ERROR_TYPE_METER_POLICY,
15554 NULL, "cannot create policy "
15555 "port action for this color");
15556 memset(&port_id_resource, 0,
15557 sizeof(port_id_resource));
15558 if (flow_dv_translate_action_port_id(dev, act,
15559 &port_id, &flow_err))
15560 return -rte_mtr_error_set(error,
15562 RTE_MTR_ERROR_TYPE_METER_POLICY,
15563 NULL, "cannot translate "
15564 "policy port action");
15565 port_id_resource.port_id = port_id;
15566 if (flow_dv_port_id_action_resource_register
15567 (dev, &port_id_resource,
15568 &dev_flow, &flow_err))
15569 return -rte_mtr_error_set(error,
15571 RTE_MTR_ERROR_TYPE_METER_POLICY,
15572 NULL, "cannot setup "
15573 "policy port action");
15574 act_cnt->rix_port_id_action =
15575 dev_flow.handle->rix_port_id_action;
15576 act_cnt->fate_action =
15577 MLX5_FLOW_FATE_PORT_ID;
15578 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15581 case RTE_FLOW_ACTION_TYPE_JUMP:
15583 uint32_t jump_group = 0;
15584 uint32_t table = 0;
15585 struct mlx5_flow_tbl_data_entry *tbl_data;
15586 struct flow_grp_info grp_info = {
15587 .external = !!dev_flow.external,
15588 .transfer = !!transfer,
15589 .fdb_def_rule = !!priv->fdb_def_rule,
15591 .skip_scale = dev_flow.skip_scale &
15592 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15594 struct mlx5_flow_meter_sub_policy *sub_policy =
15595 mtr_policy->sub_policys[domain][0];
15597 if (i >= MLX5_MTR_RTE_COLORS)
15598 return -rte_mtr_error_set(error,
15600 RTE_MTR_ERROR_TYPE_METER_POLICY,
15602 "cannot create policy "
15603 "jump action for this color");
15605 ((const struct rte_flow_action_jump *)
15607 if (mlx5_flow_group_to_table(dev, NULL,
15610 &grp_info, &flow_err))
15611 return -rte_mtr_error_set(error,
15613 RTE_MTR_ERROR_TYPE_METER_POLICY,
15614 NULL, "cannot setup "
15615 "policy jump action");
15616 sub_policy->jump_tbl[i] =
15617 flow_dv_tbl_resource_get(dev,
15620 !!dev_flow.external,
15621 NULL, jump_group, 0,
15624 (!sub_policy->jump_tbl[i])
15625 return -rte_mtr_error_set(error,
15627 RTE_MTR_ERROR_TYPE_METER_POLICY,
15628 NULL, "cannot create jump action.");
15629 tbl_data = container_of
15630 (sub_policy->jump_tbl[i],
15631 struct mlx5_flow_tbl_data_entry, tbl);
15632 act_cnt->dr_jump_action[domain] =
15633 tbl_data->jump.action;
15634 act_cnt->fate_action =
15635 MLX5_FLOW_FATE_JUMP;
15636 action_flags |= MLX5_FLOW_ACTION_JUMP;
15640 * No need to check meter hierarchy for Y or R colors
15641 * here since it is done in the validation stage.
15643 case RTE_FLOW_ACTION_TYPE_METER:
15645 const struct rte_flow_action_meter *mtr;
15646 struct mlx5_flow_meter_info *next_fm;
15647 struct mlx5_flow_meter_policy *next_policy;
15648 struct rte_flow_action tag_action;
15649 struct mlx5_rte_flow_action_set_tag set_tag;
15650 uint32_t next_mtr_idx = 0;
15653 next_fm = mlx5_flow_meter_find(priv,
15657 return -rte_mtr_error_set(error, EINVAL,
15658 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15659 "Fail to find next meter.");
15660 if (next_fm->def_policy)
15661 return -rte_mtr_error_set(error, EINVAL,
15662 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15663 "Hierarchy only supports termination meter.");
15664 next_policy = mlx5_flow_meter_policy_find(dev,
15665 next_fm->policy_id, NULL);
15666 MLX5_ASSERT(next_policy);
15667 if (next_fm->drop_cnt) {
15670 mlx5_flow_get_reg_id(dev,
15673 (struct rte_flow_error *)error);
15674 set_tag.offset = (priv->mtr_reg_share ?
15675 MLX5_MTR_COLOR_BITS : 0);
15676 set_tag.length = (priv->mtr_reg_share ?
15677 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15679 set_tag.data = next_mtr_idx;
15681 (enum rte_flow_action_type)
15682 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15683 tag_action.conf = &set_tag;
15684 if (flow_dv_convert_action_set_reg
15685 (mhdr_res, &tag_action,
15686 (struct rte_flow_error *)error))
15689 MLX5_FLOW_ACTION_SET_TAG;
15691 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15692 act_cnt->next_mtr_id = next_fm->meter_id;
15693 act_cnt->next_sub_policy = NULL;
15694 mtr_policy->is_hierarchy = 1;
15695 mtr_policy->dev = next_policy->dev;
15697 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15701 return -rte_mtr_error_set(error, ENOTSUP,
15702 RTE_MTR_ERROR_TYPE_METER_POLICY,
15703 NULL, "action type not supported");
15705 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15706 /* create modify action if needed. */
15707 dev_flow.dv.group = 1;
15708 if (flow_dv_modify_hdr_resource_register
15709 (dev, mhdr_res, &dev_flow, &flow_err))
15710 return -rte_mtr_error_set(error,
15712 RTE_MTR_ERROR_TYPE_METER_POLICY,
15713 NULL, "cannot register policy "
15715 act_cnt->modify_hdr =
15716 dev_flow.handle->dvh.modify_hdr;
15724 * Create policy action per domain, lock free,
15725 * (mutex should be acquired by caller).
15726 * Dispatcher for action type specific call.
15729 * Pointer to the Ethernet device structure.
15730 * @param[in] mtr_policy
15731 * Meter policy struct.
15732 * @param[in] action
15733 * Action specification used to create meter actions.
15734 * @param[out] error
15735 * Perform verbose error reporting if not NULL. Initialized in case of
15739 * 0 on success, otherwise negative errno value.
15742 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15743 struct mlx5_flow_meter_policy *mtr_policy,
15744 const struct rte_flow_action *actions[RTE_COLORS],
15745 struct rte_mtr_error *error)
15748 uint16_t sub_policy_num;
15750 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15751 sub_policy_num = (mtr_policy->sub_policy_num >>
15752 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15753 MLX5_MTR_SUB_POLICY_NUM_MASK;
15754 if (sub_policy_num) {
15755 ret = __flow_dv_create_domain_policy_acts(dev,
15756 mtr_policy, actions,
15757 (enum mlx5_meter_domain)i, error);
15758 /* Cleaning resource is done in the caller level. */
15767 * Query a DV flow rule for its statistics via DevX.
15770 * Pointer to Ethernet device.
15771 * @param[in] cnt_idx
15772 * Index to the flow counter.
15774 * Data retrieved by the query.
15775 * @param[out] error
15776 * Perform verbose error reporting if not NULL.
15779 * 0 on success, a negative errno value otherwise and rte_errno is set.
15782 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15783 struct rte_flow_error *error)
15785 struct mlx5_priv *priv = dev->data->dev_private;
15786 struct rte_flow_query_count *qc = data;
15788 if (!priv->sh->devx)
15789 return rte_flow_error_set(error, ENOTSUP,
15790 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15792 "counters are not supported");
15794 uint64_t pkts, bytes;
15795 struct mlx5_flow_counter *cnt;
15796 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15799 return rte_flow_error_set(error, -err,
15800 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15801 NULL, "cannot read counters");
15802 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15805 qc->hits = pkts - cnt->hits;
15806 qc->bytes = bytes - cnt->bytes;
15809 cnt->bytes = bytes;
15813 return rte_flow_error_set(error, EINVAL,
15814 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15816 "counters are not available");
15821 * Query counter's action pointer for a DV flow rule via DevX.
15824 * Pointer to Ethernet device.
15825 * @param[in] cnt_idx
15826 * Index to the flow counter.
15827 * @param[out] action_ptr
15828 * Action pointer for counter.
15829 * @param[out] error
15830 * Perform verbose error reporting if not NULL.
15833 * 0 on success, a negative errno value otherwise and rte_errno is set.
15836 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15837 void **action_ptr, struct rte_flow_error *error)
15839 struct mlx5_priv *priv = dev->data->dev_private;
15841 if (!priv->sh->devx || !action_ptr)
15842 return rte_flow_error_set(error, ENOTSUP,
15843 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15845 "counters are not supported");
15848 struct mlx5_flow_counter *cnt = NULL;
15849 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15851 *action_ptr = cnt->action;
15855 return rte_flow_error_set(error, EINVAL,
15856 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15858 "counters are not available");
15862 flow_dv_action_query(struct rte_eth_dev *dev,
15863 const struct rte_flow_action_handle *handle, void *data,
15864 struct rte_flow_error *error)
15866 struct mlx5_age_param *age_param;
15867 struct rte_flow_query_age *resp;
15868 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15869 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15870 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15871 struct mlx5_priv *priv = dev->data->dev_private;
15872 struct mlx5_aso_ct_action *ct;
15877 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15878 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15880 resp->aged = __atomic_load_n(&age_param->state,
15881 __ATOMIC_RELAXED) == AGE_TMOUT ?
15883 resp->sec_since_last_hit_valid = !resp->aged;
15884 if (resp->sec_since_last_hit_valid)
15885 resp->sec_since_last_hit = __atomic_load_n
15886 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15888 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15889 return flow_dv_query_count(dev, idx, data, error);
15890 case MLX5_INDIRECT_ACTION_TYPE_CT:
15891 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15892 if (owner != PORT_ID(priv))
15893 return rte_flow_error_set(error, EACCES,
15894 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15896 "CT object owned by another port");
15897 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15898 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15901 return rte_flow_error_set(error, EFAULT,
15902 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15904 "CT object is inactive");
15905 ((struct rte_flow_action_conntrack *)data)->peer_port =
15907 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15909 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15910 return rte_flow_error_set(error, EIO,
15911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15913 "Failed to query CT context");
15916 return rte_flow_error_set(error, ENOTSUP,
15917 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15918 "action type query not supported");
15923 * Query a flow rule AGE action for aging information.
15926 * Pointer to Ethernet device.
15928 * Pointer to the sub flow.
15930 * data retrieved by the query.
15931 * @param[out] error
15932 * Perform verbose error reporting if not NULL.
15935 * 0 on success, a negative errno value otherwise and rte_errno is set.
15938 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15939 void *data, struct rte_flow_error *error)
15941 struct rte_flow_query_age *resp = data;
15942 struct mlx5_age_param *age_param;
15945 struct mlx5_aso_age_action *act =
15946 flow_aso_age_get_by_idx(dev, flow->age);
15948 age_param = &act->age_params;
15949 } else if (flow->counter) {
15950 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15952 if (!age_param || !age_param->timeout)
15953 return rte_flow_error_set
15955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15956 NULL, "cannot read age data");
15958 return rte_flow_error_set(error, EINVAL,
15959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15960 NULL, "age data not available");
15962 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15964 resp->sec_since_last_hit_valid = !resp->aged;
15965 if (resp->sec_since_last_hit_valid)
15966 resp->sec_since_last_hit = __atomic_load_n
15967 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15974 * @see rte_flow_query()
15975 * @see rte_flow_ops
15978 flow_dv_query(struct rte_eth_dev *dev,
15979 struct rte_flow *flow __rte_unused,
15980 const struct rte_flow_action *actions __rte_unused,
15981 void *data __rte_unused,
15982 struct rte_flow_error *error __rte_unused)
15986 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15987 switch (actions->type) {
15988 case RTE_FLOW_ACTION_TYPE_VOID:
15990 case RTE_FLOW_ACTION_TYPE_COUNT:
15991 ret = flow_dv_query_count(dev, flow->counter, data,
15994 case RTE_FLOW_ACTION_TYPE_AGE:
15995 ret = flow_dv_query_age(dev, flow, data, error);
15998 return rte_flow_error_set(error, ENOTSUP,
15999 RTE_FLOW_ERROR_TYPE_ACTION,
16001 "action not supported");
16008 * Destroy the meter table set.
16009 * Lock free, (mutex should be acquired by caller).
16012 * Pointer to Ethernet device.
16014 * Meter information table.
16017 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16018 struct mlx5_flow_meter_info *fm)
16020 struct mlx5_priv *priv = dev->data->dev_private;
16023 if (!fm || !priv->config.dv_flow_en)
16025 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16026 if (fm->drop_rule[i]) {
16027 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16028 fm->drop_rule[i] = NULL;
16034 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16036 struct mlx5_priv *priv = dev->data->dev_private;
16037 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16038 struct mlx5_flow_tbl_data_entry *tbl;
16041 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16042 if (mtrmng->def_rule[i]) {
16043 claim_zero(mlx5_flow_os_destroy_flow
16044 (mtrmng->def_rule[i]));
16045 mtrmng->def_rule[i] = NULL;
16047 if (mtrmng->def_matcher[i]) {
16048 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16049 struct mlx5_flow_tbl_data_entry, tbl);
16050 mlx5_list_unregister(tbl->matchers,
16051 &mtrmng->def_matcher[i]->entry);
16052 mtrmng->def_matcher[i] = NULL;
16054 for (j = 0; j < MLX5_REG_BITS; j++) {
16055 if (mtrmng->drop_matcher[i][j]) {
16057 container_of(mtrmng->drop_matcher[i][j]->tbl,
16058 struct mlx5_flow_tbl_data_entry,
16060 mlx5_list_unregister(tbl->matchers,
16061 &mtrmng->drop_matcher[i][j]->entry);
16062 mtrmng->drop_matcher[i][j] = NULL;
16065 if (mtrmng->drop_tbl[i]) {
16066 flow_dv_tbl_resource_release(MLX5_SH(dev),
16067 mtrmng->drop_tbl[i]);
16068 mtrmng->drop_tbl[i] = NULL;
16073 /* Number of meter flow actions, count and jump or count and drop. */
16074 #define METER_ACTIONS 2
16077 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16078 enum mlx5_meter_domain domain)
16080 struct mlx5_priv *priv = dev->data->dev_private;
16081 struct mlx5_flow_meter_def_policy *def_policy =
16082 priv->sh->mtrmng->def_policy[domain];
16084 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16085 mlx5_free(def_policy);
16086 priv->sh->mtrmng->def_policy[domain] = NULL;
16090 * Destroy the default policy table set.
16093 * Pointer to Ethernet device.
16096 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16098 struct mlx5_priv *priv = dev->data->dev_private;
16101 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16102 if (priv->sh->mtrmng->def_policy[i])
16103 __flow_dv_destroy_domain_def_policy(dev,
16104 (enum mlx5_meter_domain)i);
16105 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16109 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16110 uint32_t color_reg_c_idx,
16111 enum rte_color color, void *matcher_object,
16112 int actions_n, void *actions,
16113 bool match_src_port, const struct rte_flow_item *item,
16114 void **rule, const struct rte_flow_attr *attr)
16117 struct mlx5_flow_dv_match_params value = {
16118 .size = sizeof(value.buf),
16120 struct mlx5_flow_dv_match_params matcher = {
16121 .size = sizeof(matcher.buf),
16123 struct mlx5_priv *priv = dev->data->dev_private;
16126 if (match_src_port && (priv->representor || priv->master)) {
16127 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16128 value.buf, item, attr)) {
16129 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16130 " value with port.", color);
16134 flow_dv_match_meta_reg(matcher.buf, value.buf,
16135 (enum modify_reg)color_reg_c_idx,
16136 rte_col_2_mlx5_col(color), UINT32_MAX);
16137 misc_mask = flow_dv_matcher_enable(value.buf);
16138 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16139 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16140 actions_n, actions, rule);
16142 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16149 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16150 uint32_t color_reg_c_idx,
16152 struct mlx5_flow_meter_sub_policy *sub_policy,
16153 const struct rte_flow_attr *attr,
16154 bool match_src_port,
16155 const struct rte_flow_item *item,
16156 struct mlx5_flow_dv_matcher **policy_matcher,
16157 struct rte_flow_error *error)
16159 struct mlx5_list_entry *entry;
16160 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16161 struct mlx5_flow_dv_matcher matcher = {
16163 .size = sizeof(matcher.mask.buf),
16167 struct mlx5_flow_dv_match_params value = {
16168 .size = sizeof(value.buf),
16170 struct mlx5_flow_cb_ctx ctx = {
16174 struct mlx5_flow_tbl_data_entry *tbl_data;
16175 struct mlx5_priv *priv = dev->data->dev_private;
16176 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16178 if (match_src_port && (priv->representor || priv->master)) {
16179 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16180 value.buf, item, attr)) {
16181 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16182 " with port.", priority);
16186 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16187 if (priority < RTE_COLOR_RED)
16188 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16189 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16190 matcher.priority = priority;
16191 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16192 matcher.mask.size);
16193 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16195 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16199 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16204 * Create the policy rules per domain.
16207 * Pointer to Ethernet device.
16208 * @param[in] sub_policy
16209 * Pointer to sub policy table..
16210 * @param[in] egress
16211 * Direction of the table.
16212 * @param[in] transfer
16213 * E-Switch or NIC flow.
16215 * Pointer to policy action list per color.
16218 * 0 on success, -1 otherwise.
16221 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16222 struct mlx5_flow_meter_sub_policy *sub_policy,
16223 uint8_t egress, uint8_t transfer, bool match_src_port,
16224 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16226 struct mlx5_priv *priv = dev->data->dev_private;
16227 struct rte_flow_error flow_err;
16228 uint32_t color_reg_c_idx;
16229 struct rte_flow_attr attr = {
16230 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16233 .egress = !!egress,
16234 .transfer = !!transfer,
16238 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16239 struct mlx5_sub_policy_color_rule *color_rule;
16241 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16245 /* Create policy table with POLICY level. */
16246 if (!sub_policy->tbl_rsc)
16247 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16248 MLX5_FLOW_TABLE_LEVEL_POLICY,
16249 egress, transfer, false, NULL, 0, 0,
16250 sub_policy->idx, &flow_err);
16251 if (!sub_policy->tbl_rsc) {
16253 "Failed to create meter sub policy table.");
16256 /* Prepare matchers. */
16257 color_reg_c_idx = ret;
16258 for (i = 0; i < RTE_COLORS; i++) {
16259 TAILQ_INIT(&sub_policy->color_rules[i]);
16260 if (!acts[i].actions_n)
16262 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16263 sizeof(struct mlx5_sub_policy_color_rule),
16266 DRV_LOG(ERR, "No memory to create color rule.");
16269 tmp_rules[i] = color_rule;
16270 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16271 color_rule, next_port);
16272 color_rule->src_port = priv->representor_id;
16275 /* Create matchers for colors. */
16276 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16277 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16278 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16279 &attr, svport_match, NULL,
16280 &color_rule->matcher, &flow_err)) {
16281 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16284 /* Create flow, matching color. */
16285 if (__flow_dv_create_policy_flow(dev,
16286 color_reg_c_idx, (enum rte_color)i,
16287 color_rule->matcher->matcher_object,
16288 acts[i].actions_n, acts[i].dv_actions,
16289 svport_match, NULL, &color_rule->rule,
16291 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16297 /* All the policy rules will be cleared. */
16299 color_rule = tmp_rules[i];
16301 if (color_rule->rule)
16302 mlx5_flow_os_destroy_flow(color_rule->rule);
16303 if (color_rule->matcher) {
16304 struct mlx5_flow_tbl_data_entry *tbl =
16305 container_of(color_rule->matcher->tbl,
16306 typeof(*tbl), tbl);
16307 mlx5_list_unregister(tbl->matchers,
16308 &color_rule->matcher->entry);
16310 TAILQ_REMOVE(&sub_policy->color_rules[i],
16311 color_rule, next_port);
16312 mlx5_free(color_rule);
16319 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16320 struct mlx5_flow_meter_policy *mtr_policy,
16321 struct mlx5_flow_meter_sub_policy *sub_policy,
16324 struct mlx5_priv *priv = dev->data->dev_private;
16325 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16326 struct mlx5_flow_dv_tag_resource *tag;
16327 struct mlx5_flow_dv_port_id_action_resource *port_action;
16328 struct mlx5_hrxq *hrxq;
16329 struct mlx5_flow_meter_info *next_fm = NULL;
16330 struct mlx5_flow_meter_policy *next_policy;
16331 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16332 struct mlx5_flow_tbl_data_entry *tbl_data;
16333 struct rte_flow_error error;
16334 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16335 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16336 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16337 bool match_src_port = false;
16340 /* If RSS or Queue, no previous actions / rules is created. */
16341 for (i = 0; i < RTE_COLORS; i++) {
16342 acts[i].actions_n = 0;
16343 if (i == RTE_COLOR_RED) {
16344 /* Only support drop on red. */
16345 acts[i].dv_actions[0] =
16346 mtr_policy->dr_drop_action[domain];
16347 acts[i].actions_n = 1;
16350 if (i == RTE_COLOR_GREEN &&
16351 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16352 struct rte_flow_attr attr = {
16353 .transfer = transfer
16356 next_fm = mlx5_flow_meter_find(priv,
16357 mtr_policy->act_cnt[i].next_mtr_id,
16361 "Failed to get next hierarchy meter.");
16364 if (mlx5_flow_meter_attach(priv, next_fm,
16366 DRV_LOG(ERR, "%s", error.message);
16370 /* Meter action must be the first for TX. */
16372 acts[i].dv_actions[acts[i].actions_n] =
16373 next_fm->meter_action;
16374 acts[i].actions_n++;
16377 if (mtr_policy->act_cnt[i].rix_mark) {
16378 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16379 mtr_policy->act_cnt[i].rix_mark);
16381 DRV_LOG(ERR, "Failed to find "
16382 "mark action for policy.");
16385 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16386 acts[i].actions_n++;
16388 if (mtr_policy->act_cnt[i].modify_hdr) {
16389 acts[i].dv_actions[acts[i].actions_n] =
16390 mtr_policy->act_cnt[i].modify_hdr->action;
16391 acts[i].actions_n++;
16393 if (mtr_policy->act_cnt[i].fate_action) {
16394 switch (mtr_policy->act_cnt[i].fate_action) {
16395 case MLX5_FLOW_FATE_PORT_ID:
16396 port_action = mlx5_ipool_get
16397 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16398 mtr_policy->act_cnt[i].rix_port_id_action);
16399 if (!port_action) {
16400 DRV_LOG(ERR, "Failed to find "
16401 "port action for policy.");
16404 acts[i].dv_actions[acts[i].actions_n] =
16405 port_action->action;
16406 acts[i].actions_n++;
16407 mtr_policy->dev = dev;
16408 match_src_port = true;
16410 case MLX5_FLOW_FATE_DROP:
16411 case MLX5_FLOW_FATE_JUMP:
16412 acts[i].dv_actions[acts[i].actions_n] =
16413 mtr_policy->act_cnt[i].dr_jump_action[domain];
16414 acts[i].actions_n++;
16416 case MLX5_FLOW_FATE_SHARED_RSS:
16417 case MLX5_FLOW_FATE_QUEUE:
16418 hrxq = mlx5_ipool_get
16419 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16420 sub_policy->rix_hrxq[i]);
16422 DRV_LOG(ERR, "Failed to find "
16423 "queue action for policy.");
16426 acts[i].dv_actions[acts[i].actions_n] =
16428 acts[i].actions_n++;
16430 case MLX5_FLOW_FATE_MTR:
16433 "No next hierarchy meter.");
16437 acts[i].dv_actions[acts[i].actions_n] =
16438 next_fm->meter_action;
16439 acts[i].actions_n++;
16441 if (mtr_policy->act_cnt[i].next_sub_policy) {
16443 mtr_policy->act_cnt[i].next_sub_policy;
16446 mlx5_flow_meter_policy_find(dev,
16447 next_fm->policy_id, NULL);
16448 MLX5_ASSERT(next_policy);
16450 next_policy->sub_policys[domain][0];
16453 container_of(next_sub_policy->tbl_rsc,
16454 struct mlx5_flow_tbl_data_entry, tbl);
16455 acts[i].dv_actions[acts[i].actions_n++] =
16456 tbl_data->jump.action;
16457 if (mtr_policy->act_cnt[i].modify_hdr)
16458 match_src_port = !!transfer;
16461 /*Queue action do nothing*/
16466 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16467 egress, transfer, match_src_port, acts)) {
16469 "Failed to create policy rules per domain.");
16475 mlx5_flow_meter_detach(priv, next_fm);
16480 * Create the policy rules.
16483 * Pointer to Ethernet device.
16484 * @param[in,out] mtr_policy
16485 * Pointer to meter policy table.
16488 * 0 on success, -1 otherwise.
16491 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16492 struct mlx5_flow_meter_policy *mtr_policy)
16495 uint16_t sub_policy_num;
16497 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16498 sub_policy_num = (mtr_policy->sub_policy_num >>
16499 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16500 MLX5_MTR_SUB_POLICY_NUM_MASK;
16501 if (!sub_policy_num)
16503 /* Prepare actions list and create policy rules. */
16504 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16505 mtr_policy->sub_policys[i][0], i)) {
16506 DRV_LOG(ERR, "Failed to create policy action "
16507 "list per domain.");
16515 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16517 struct mlx5_priv *priv = dev->data->dev_private;
16518 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16519 struct mlx5_flow_meter_def_policy *def_policy;
16520 struct mlx5_flow_tbl_resource *jump_tbl;
16521 struct mlx5_flow_tbl_data_entry *tbl_data;
16522 uint8_t egress, transfer;
16523 struct rte_flow_error error;
16524 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16527 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16528 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16529 def_policy = mtrmng->def_policy[domain];
16531 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16532 sizeof(struct mlx5_flow_meter_def_policy),
16533 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16535 DRV_LOG(ERR, "Failed to alloc default policy table.");
16536 goto def_policy_error;
16538 mtrmng->def_policy[domain] = def_policy;
16539 /* Create the meter suffix table with SUFFIX level. */
16540 jump_tbl = flow_dv_tbl_resource_get(dev,
16541 MLX5_FLOW_TABLE_LEVEL_METER,
16542 egress, transfer, false, NULL, 0,
16543 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16546 "Failed to create meter suffix table.");
16547 goto def_policy_error;
16549 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16550 tbl_data = container_of(jump_tbl,
16551 struct mlx5_flow_tbl_data_entry, tbl);
16552 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16553 tbl_data->jump.action;
16554 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16555 acts[RTE_COLOR_GREEN].actions_n = 1;
16557 * YELLOW has the same default policy as GREEN does.
16558 * G & Y share the same table and action. The 2nd time of table
16559 * resource getting is just to update the reference count for
16560 * the releasing stage.
16562 jump_tbl = flow_dv_tbl_resource_get(dev,
16563 MLX5_FLOW_TABLE_LEVEL_METER,
16564 egress, transfer, false, NULL, 0,
16565 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16568 "Failed to get meter suffix table.");
16569 goto def_policy_error;
16571 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16572 tbl_data = container_of(jump_tbl,
16573 struct mlx5_flow_tbl_data_entry, tbl);
16574 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16575 tbl_data->jump.action;
16576 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16577 acts[RTE_COLOR_YELLOW].actions_n = 1;
16578 /* Create jump action to the drop table. */
16579 if (!mtrmng->drop_tbl[domain]) {
16580 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16581 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16582 egress, transfer, false, NULL, 0,
16583 0, MLX5_MTR_TABLE_ID_DROP, &error);
16584 if (!mtrmng->drop_tbl[domain]) {
16585 DRV_LOG(ERR, "Failed to create meter "
16586 "drop table for default policy.");
16587 goto def_policy_error;
16590 /* all RED: unique Drop table for jump action. */
16591 tbl_data = container_of(mtrmng->drop_tbl[domain],
16592 struct mlx5_flow_tbl_data_entry, tbl);
16593 def_policy->dr_jump_action[RTE_COLOR_RED] =
16594 tbl_data->jump.action;
16595 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16596 acts[RTE_COLOR_RED].actions_n = 1;
16597 /* Create default policy rules. */
16598 ret = __flow_dv_create_domain_policy_rules(dev,
16599 &def_policy->sub_policy,
16600 egress, transfer, false, acts);
16602 DRV_LOG(ERR, "Failed to create default policy rules.");
16603 goto def_policy_error;
16608 __flow_dv_destroy_domain_def_policy(dev,
16609 (enum mlx5_meter_domain)domain);
16614 * Create the default policy table set.
16617 * Pointer to Ethernet device.
16619 * 0 on success, -1 otherwise.
16622 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16624 struct mlx5_priv *priv = dev->data->dev_private;
16627 /* Non-termination policy table. */
16628 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16629 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16631 if (__flow_dv_create_domain_def_policy(dev, i)) {
16632 DRV_LOG(ERR, "Failed to create default policy");
16633 /* Rollback the created default policies for others. */
16634 flow_dv_destroy_def_policy(dev);
16642 * Create the needed meter tables.
16643 * Lock free, (mutex should be acquired by caller).
16646 * Pointer to Ethernet device.
16648 * Meter information table.
16649 * @param[in] mtr_idx
16651 * @param[in] domain_bitmap
16654 * 0 on success, -1 otherwise.
16657 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16658 struct mlx5_flow_meter_info *fm,
16660 uint8_t domain_bitmap)
16662 struct mlx5_priv *priv = dev->data->dev_private;
16663 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16664 struct rte_flow_error error;
16665 struct mlx5_flow_tbl_data_entry *tbl_data;
16666 uint8_t egress, transfer;
16667 void *actions[METER_ACTIONS];
16668 int domain, ret, i;
16669 struct mlx5_flow_counter *cnt;
16670 struct mlx5_flow_dv_match_params value = {
16671 .size = sizeof(value.buf),
16673 struct mlx5_flow_dv_match_params matcher_para = {
16674 .size = sizeof(matcher_para.buf),
16676 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16678 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16679 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16680 struct mlx5_list_entry *entry;
16681 struct mlx5_flow_dv_matcher matcher = {
16683 .size = sizeof(matcher.mask.buf),
16686 struct mlx5_flow_dv_matcher *drop_matcher;
16687 struct mlx5_flow_cb_ctx ctx = {
16693 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16694 rte_errno = ENOTSUP;
16697 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16698 if (!(domain_bitmap & (1 << domain)) ||
16699 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16701 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16702 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16703 /* Create the drop table with METER DROP level. */
16704 if (!mtrmng->drop_tbl[domain]) {
16705 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16706 MLX5_FLOW_TABLE_LEVEL_METER,
16707 egress, transfer, false, NULL, 0,
16708 0, MLX5_MTR_TABLE_ID_DROP, &error);
16709 if (!mtrmng->drop_tbl[domain]) {
16710 DRV_LOG(ERR, "Failed to create meter drop table.");
16714 /* Create default matcher in drop table. */
16715 matcher.tbl = mtrmng->drop_tbl[domain],
16716 tbl_data = container_of(mtrmng->drop_tbl[domain],
16717 struct mlx5_flow_tbl_data_entry, tbl);
16718 if (!mtrmng->def_matcher[domain]) {
16719 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16720 (enum modify_reg)mtr_id_reg_c,
16722 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16723 matcher.crc = rte_raw_cksum
16724 ((const void *)matcher.mask.buf,
16725 matcher.mask.size);
16726 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16728 DRV_LOG(ERR, "Failed to register meter "
16729 "drop default matcher.");
16732 mtrmng->def_matcher[domain] = container_of(entry,
16733 struct mlx5_flow_dv_matcher, entry);
16735 /* Create default rule in drop table. */
16736 if (!mtrmng->def_rule[domain]) {
16738 actions[i++] = priv->sh->dr_drop_action;
16739 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16740 (enum modify_reg)mtr_id_reg_c, 0, 0);
16741 misc_mask = flow_dv_matcher_enable(value.buf);
16742 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16743 ret = mlx5_flow_os_create_flow
16744 (mtrmng->def_matcher[domain]->matcher_object,
16745 (void *)&value, i, actions,
16746 &mtrmng->def_rule[domain]);
16748 DRV_LOG(ERR, "Failed to create meter "
16749 "default drop rule for drop table.");
16755 MLX5_ASSERT(mtrmng->max_mtr_bits);
16756 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16757 /* Create matchers for Drop. */
16758 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16759 (enum modify_reg)mtr_id_reg_c, 0,
16760 (mtr_id_mask << mtr_id_offset));
16761 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16762 matcher.crc = rte_raw_cksum
16763 ((const void *)matcher.mask.buf,
16764 matcher.mask.size);
16765 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16768 "Failed to register meter drop matcher.");
16771 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16772 container_of(entry, struct mlx5_flow_dv_matcher,
16776 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16777 /* Create drop rule, matching meter_id only. */
16778 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16779 (enum modify_reg)mtr_id_reg_c,
16780 (mtr_idx << mtr_id_offset), UINT32_MAX);
16782 cnt = flow_dv_counter_get_by_idx(dev,
16783 fm->drop_cnt, NULL);
16784 actions[i++] = cnt->action;
16785 actions[i++] = priv->sh->dr_drop_action;
16786 misc_mask = flow_dv_matcher_enable(value.buf);
16787 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16788 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16789 (void *)&value, i, actions,
16790 &fm->drop_rule[domain]);
16792 DRV_LOG(ERR, "Failed to create meter "
16793 "drop rule for drop table.");
16799 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16800 if (fm->drop_rule[i]) {
16801 claim_zero(mlx5_flow_os_destroy_flow
16802 (fm->drop_rule[i]));
16803 fm->drop_rule[i] = NULL;
16809 static struct mlx5_flow_meter_sub_policy *
16810 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16811 struct mlx5_flow_meter_policy *mtr_policy,
16812 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16813 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16816 struct mlx5_priv *priv = dev->data->dev_private;
16817 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16818 uint32_t sub_policy_idx = 0;
16819 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16821 struct mlx5_hrxq *hrxq;
16822 struct mlx5_flow_handle dh;
16823 struct mlx5_meter_policy_action_container *act_cnt;
16824 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16825 uint16_t sub_policy_num;
16827 rte_spinlock_lock(&mtr_policy->sl);
16828 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16831 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16832 if (!hrxq_idx[i]) {
16833 rte_spinlock_unlock(&mtr_policy->sl);
16837 sub_policy_num = (mtr_policy->sub_policy_num >>
16838 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16839 MLX5_MTR_SUB_POLICY_NUM_MASK;
16840 for (j = 0; j < sub_policy_num; j++) {
16841 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16844 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16847 if (i >= MLX5_MTR_RTE_COLORS) {
16849 * Found the sub policy table with
16850 * the same queue per color.
16852 rte_spinlock_unlock(&mtr_policy->sl);
16853 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16854 mlx5_hrxq_release(dev, hrxq_idx[i]);
16856 return mtr_policy->sub_policys[domain][j];
16859 /* Create sub policy. */
16860 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16861 /* Reuse the first pre-allocated sub_policy. */
16862 sub_policy = mtr_policy->sub_policys[domain][0];
16863 sub_policy_idx = sub_policy->idx;
16865 sub_policy = mlx5_ipool_zmalloc
16866 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16869 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16870 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16871 mlx5_hrxq_release(dev, hrxq_idx[i]);
16872 goto rss_sub_policy_error;
16874 sub_policy->idx = sub_policy_idx;
16875 sub_policy->main_policy = mtr_policy;
16877 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16880 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16881 if (mtr_policy->is_hierarchy) {
16882 act_cnt = &mtr_policy->act_cnt[i];
16883 act_cnt->next_sub_policy = next_sub_policy;
16884 mlx5_hrxq_release(dev, hrxq_idx[i]);
16887 * Overwrite the last action from
16888 * RSS action to Queue action.
16890 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16893 DRV_LOG(ERR, "Failed to get policy hrxq");
16894 goto rss_sub_policy_error;
16896 act_cnt = &mtr_policy->act_cnt[i];
16897 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16898 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16899 if (act_cnt->rix_mark)
16901 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16902 dh.rix_hrxq = hrxq_idx[i];
16903 flow_drv_rxq_flags_set(dev, &dh);
16907 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16908 sub_policy, domain)) {
16909 DRV_LOG(ERR, "Failed to create policy "
16910 "rules for ingress domain.");
16911 goto rss_sub_policy_error;
16913 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16914 i = (mtr_policy->sub_policy_num >>
16915 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16916 MLX5_MTR_SUB_POLICY_NUM_MASK;
16917 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16918 DRV_LOG(ERR, "No free sub-policy slot.");
16919 goto rss_sub_policy_error;
16921 mtr_policy->sub_policys[domain][i] = sub_policy;
16923 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16924 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16925 mtr_policy->sub_policy_num |=
16926 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16927 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16929 rte_spinlock_unlock(&mtr_policy->sl);
16932 rss_sub_policy_error:
16934 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16935 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16936 i = (mtr_policy->sub_policy_num >>
16937 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16938 MLX5_MTR_SUB_POLICY_NUM_MASK;
16939 mtr_policy->sub_policys[domain][i] = NULL;
16940 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16944 rte_spinlock_unlock(&mtr_policy->sl);
16949 * Find the policy table for prefix table with RSS.
16952 * Pointer to Ethernet device.
16953 * @param[in] mtr_policy
16954 * Pointer to meter policy table.
16955 * @param[in] rss_desc
16956 * Pointer to rss_desc
16958 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16960 static struct mlx5_flow_meter_sub_policy *
16961 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16962 struct mlx5_flow_meter_policy *mtr_policy,
16963 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16965 struct mlx5_priv *priv = dev->data->dev_private;
16966 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16967 struct mlx5_flow_meter_info *next_fm;
16968 struct mlx5_flow_meter_policy *next_policy;
16969 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16970 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16971 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16972 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16973 bool reuse_sub_policy;
16978 /* Iterate hierarchy to get all policies in this hierarchy. */
16979 policies[i++] = mtr_policy;
16980 if (!mtr_policy->is_hierarchy)
16982 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16983 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16986 next_fm = mlx5_flow_meter_find(priv,
16987 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16989 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16993 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16995 MLX5_ASSERT(next_policy);
16996 mtr_policy = next_policy;
17000 * From last policy to the first one in hierarchy,
17001 * create / get the sub policy for each of them.
17003 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17007 &reuse_sub_policy);
17009 DRV_LOG(ERR, "Failed to get the sub policy.");
17012 if (!reuse_sub_policy)
17013 sub_policies[j++] = sub_policy;
17014 next_sub_policy = sub_policy;
17019 uint16_t sub_policy_num;
17021 sub_policy = sub_policies[--j];
17022 mtr_policy = sub_policy->main_policy;
17023 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17024 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17025 sub_policy_num = (mtr_policy->sub_policy_num >>
17026 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17027 MLX5_MTR_SUB_POLICY_NUM_MASK;
17028 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17031 mtr_policy->sub_policy_num &=
17032 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17033 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17034 mtr_policy->sub_policy_num |=
17035 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17036 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17037 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17045 * Create the sub policy tag rule for all meters in hierarchy.
17048 * Pointer to Ethernet device.
17050 * Meter information table.
17051 * @param[in] src_port
17052 * The src port this extra rule should use.
17054 * The src port match item.
17055 * @param[out] error
17056 * Perform verbose error reporting if not NULL.
17058 * 0 on success, a negative errno value otherwise and rte_errno is set.
17061 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17062 struct mlx5_flow_meter_info *fm,
17064 const struct rte_flow_item *item,
17065 struct rte_flow_error *error)
17067 struct mlx5_priv *priv = dev->data->dev_private;
17068 struct mlx5_flow_meter_policy *mtr_policy;
17069 struct mlx5_flow_meter_sub_policy *sub_policy;
17070 struct mlx5_flow_meter_info *next_fm = NULL;
17071 struct mlx5_flow_meter_policy *next_policy;
17072 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17073 struct mlx5_flow_tbl_data_entry *tbl_data;
17074 struct mlx5_sub_policy_color_rule *color_rule;
17075 struct mlx5_meter_policy_acts acts;
17076 uint32_t color_reg_c_idx;
17077 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17078 struct rte_flow_attr attr = {
17079 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17086 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17089 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17090 MLX5_ASSERT(mtr_policy);
17091 if (!mtr_policy->is_hierarchy)
17093 next_fm = mlx5_flow_meter_find(priv,
17094 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17096 return rte_flow_error_set(error, EINVAL,
17097 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17098 "Failed to find next meter in hierarchy.");
17100 if (!next_fm->drop_cnt)
17102 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17103 sub_policy = mtr_policy->sub_policys[domain][0];
17104 for (i = 0; i < RTE_COLORS; i++) {
17105 bool rule_exist = false;
17106 struct mlx5_meter_policy_action_container *act_cnt;
17108 if (i >= RTE_COLOR_YELLOW)
17110 TAILQ_FOREACH(color_rule,
17111 &sub_policy->color_rules[i], next_port)
17112 if (color_rule->src_port == src_port) {
17118 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17119 sizeof(struct mlx5_sub_policy_color_rule),
17122 return rte_flow_error_set(error, ENOMEM,
17123 RTE_FLOW_ERROR_TYPE_ACTION,
17124 NULL, "No memory to create tag color rule.");
17125 color_rule->src_port = src_port;
17127 next_policy = mlx5_flow_meter_policy_find(dev,
17128 next_fm->policy_id, NULL);
17129 MLX5_ASSERT(next_policy);
17130 next_sub_policy = next_policy->sub_policys[domain][0];
17131 tbl_data = container_of(next_sub_policy->tbl_rsc,
17132 struct mlx5_flow_tbl_data_entry, tbl);
17133 act_cnt = &mtr_policy->act_cnt[i];
17135 acts.dv_actions[0] = next_fm->meter_action;
17136 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17138 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17139 acts.dv_actions[1] = next_fm->meter_action;
17141 acts.dv_actions[2] = tbl_data->jump.action;
17142 acts.actions_n = 3;
17143 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17147 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17148 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17150 &color_rule->matcher, error)) {
17151 rte_flow_error_set(error, errno,
17152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17153 "Failed to create hierarchy meter matcher.");
17156 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17158 color_rule->matcher->matcher_object,
17159 acts.actions_n, acts.dv_actions,
17161 &color_rule->rule, &attr)) {
17162 rte_flow_error_set(error, errno,
17163 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17164 "Failed to create hierarchy meter rule.");
17167 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17168 color_rule, next_port);
17172 * Recursive call to iterate all meters in hierarchy and
17173 * create needed rules.
17175 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17176 src_port, item, error);
17179 if (color_rule->rule)
17180 mlx5_flow_os_destroy_flow(color_rule->rule);
17181 if (color_rule->matcher) {
17182 struct mlx5_flow_tbl_data_entry *tbl =
17183 container_of(color_rule->matcher->tbl,
17184 typeof(*tbl), tbl);
17185 mlx5_list_unregister(tbl->matchers,
17186 &color_rule->matcher->entry);
17188 mlx5_free(color_rule);
17191 mlx5_flow_meter_detach(priv, next_fm);
17196 * Destroy the sub policy table with RX queue.
17199 * Pointer to Ethernet device.
17200 * @param[in] mtr_policy
17201 * Pointer to meter policy table.
17204 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17205 struct mlx5_flow_meter_policy *mtr_policy)
17207 struct mlx5_priv *priv = dev->data->dev_private;
17208 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17209 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17211 uint16_t sub_policy_num, new_policy_num;
17213 rte_spinlock_lock(&mtr_policy->sl);
17214 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17215 switch (mtr_policy->act_cnt[i].fate_action) {
17216 case MLX5_FLOW_FATE_SHARED_RSS:
17217 sub_policy_num = (mtr_policy->sub_policy_num >>
17218 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17219 MLX5_MTR_SUB_POLICY_NUM_MASK;
17220 new_policy_num = sub_policy_num;
17221 for (j = 0; j < sub_policy_num; j++) {
17223 mtr_policy->sub_policys[domain][j];
17225 __flow_dv_destroy_sub_policy_rules(dev,
17228 mtr_policy->sub_policys[domain][0]) {
17229 mtr_policy->sub_policys[domain][j] =
17232 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17238 if (new_policy_num != sub_policy_num) {
17239 mtr_policy->sub_policy_num &=
17240 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17241 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17242 mtr_policy->sub_policy_num |=
17244 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17245 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17248 case MLX5_FLOW_FATE_QUEUE:
17249 sub_policy = mtr_policy->sub_policys[domain][0];
17250 __flow_dv_destroy_sub_policy_rules(dev,
17254 /*Other actions without queue and do nothing*/
17258 rte_spinlock_unlock(&mtr_policy->sl);
17261 * Check whether the DR drop action is supported on the root table or not.
17263 * Create a simple flow with DR drop action on root table to validate
17264 * if DR drop action on root table is supported or not.
17267 * Pointer to rte_eth_dev structure.
17270 * 0 on success, a negative errno value otherwise and rte_errno is set.
17273 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17275 struct mlx5_priv *priv = dev->data->dev_private;
17276 struct mlx5_dev_ctx_shared *sh = priv->sh;
17277 struct mlx5_flow_dv_match_params mask = {
17278 .size = sizeof(mask.buf),
17280 struct mlx5_flow_dv_match_params value = {
17281 .size = sizeof(value.buf),
17283 struct mlx5dv_flow_matcher_attr dv_attr = {
17284 .type = IBV_FLOW_ATTR_NORMAL,
17286 .match_criteria_enable = 0,
17287 .match_mask = (void *)&mask,
17289 struct mlx5_flow_tbl_resource *tbl = NULL;
17290 void *matcher = NULL;
17294 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17298 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17299 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17300 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17301 tbl->obj, &matcher);
17304 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17305 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17306 &sh->dr_drop_action, &flow);
17309 * If DR drop action is not supported on root table, flow create will
17310 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17314 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17315 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17317 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17320 claim_zero(mlx5_flow_os_destroy_flow(flow));
17323 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17325 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17330 * Validate the batch counter support in root table.
17332 * Create a simple flow with invalid counter and drop action on root table to
17333 * validate if batch counter with offset on root table is supported or not.
17336 * Pointer to rte_eth_dev structure.
17339 * 0 on success, a negative errno value otherwise and rte_errno is set.
17342 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17344 struct mlx5_priv *priv = dev->data->dev_private;
17345 struct mlx5_dev_ctx_shared *sh = priv->sh;
17346 struct mlx5_flow_dv_match_params mask = {
17347 .size = sizeof(mask.buf),
17349 struct mlx5_flow_dv_match_params value = {
17350 .size = sizeof(value.buf),
17352 struct mlx5dv_flow_matcher_attr dv_attr = {
17353 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17355 .match_criteria_enable = 0,
17356 .match_mask = (void *)&mask,
17358 void *actions[2] = { 0 };
17359 struct mlx5_flow_tbl_resource *tbl = NULL;
17360 struct mlx5_devx_obj *dcs = NULL;
17361 void *matcher = NULL;
17365 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17369 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17372 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17376 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17377 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17378 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17379 tbl->obj, &matcher);
17382 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17383 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17387 * If batch counter with offset is not supported, the driver will not
17388 * validate the invalid offset value, flow create should success.
17389 * In this case, it means batch counter is not supported in root table.
17391 * Otherwise, if flow create is failed, counter offset is supported.
17394 DRV_LOG(INFO, "Batch counter is not supported in root "
17395 "table. Switch to fallback mode.");
17396 rte_errno = ENOTSUP;
17398 claim_zero(mlx5_flow_os_destroy_flow(flow));
17400 /* Check matcher to make sure validate fail at flow create. */
17401 if (!matcher || (matcher && errno != EINVAL))
17402 DRV_LOG(ERR, "Unexpected error in counter offset "
17403 "support detection");
17407 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17409 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17411 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17413 claim_zero(mlx5_devx_cmd_destroy(dcs));
17418 * Query a devx counter.
17421 * Pointer to the Ethernet device structure.
17423 * Index to the flow counter.
17425 * Set to clear the counter statistics.
17427 * The statistics value of packets.
17428 * @param[out] bytes
17429 * The statistics value of bytes.
17432 * 0 on success, otherwise return -1.
17435 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17436 uint64_t *pkts, uint64_t *bytes)
17438 struct mlx5_priv *priv = dev->data->dev_private;
17439 struct mlx5_flow_counter *cnt;
17440 uint64_t inn_pkts, inn_bytes;
17443 if (!priv->sh->devx)
17446 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17449 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17450 *pkts = inn_pkts - cnt->hits;
17451 *bytes = inn_bytes - cnt->bytes;
17453 cnt->hits = inn_pkts;
17454 cnt->bytes = inn_bytes;
17460 * Get aged-out flows.
17463 * Pointer to the Ethernet device structure.
17464 * @param[in] context
17465 * The address of an array of pointers to the aged-out flows contexts.
17466 * @param[in] nb_contexts
17467 * The length of context array pointers.
17468 * @param[out] error
17469 * Perform verbose error reporting if not NULL. Initialized in case of
17473 * how many contexts get in success, otherwise negative errno value.
17474 * if nb_contexts is 0, return the amount of all aged contexts.
17475 * if nb_contexts is not 0 , return the amount of aged flows reported
17476 * in the context array.
17477 * @note: only stub for now
17480 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17482 uint32_t nb_contexts,
17483 struct rte_flow_error *error)
17485 struct mlx5_priv *priv = dev->data->dev_private;
17486 struct mlx5_age_info *age_info;
17487 struct mlx5_age_param *age_param;
17488 struct mlx5_flow_counter *counter;
17489 struct mlx5_aso_age_action *act;
17492 if (nb_contexts && !context)
17493 return rte_flow_error_set(error, EINVAL,
17494 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17495 NULL, "empty context");
17496 age_info = GET_PORT_AGE_INFO(priv);
17497 rte_spinlock_lock(&age_info->aged_sl);
17498 LIST_FOREACH(act, &age_info->aged_aso, next) {
17501 context[nb_flows - 1] =
17502 act->age_params.context;
17503 if (!(--nb_contexts))
17507 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17510 age_param = MLX5_CNT_TO_AGE(counter);
17511 context[nb_flows - 1] = age_param->context;
17512 if (!(--nb_contexts))
17516 rte_spinlock_unlock(&age_info->aged_sl);
17517 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17522 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17525 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17527 return flow_dv_counter_alloc(dev, 0);
17531 * Validate indirect action.
17532 * Dispatcher for action type specific validation.
17535 * Pointer to the Ethernet device structure.
17537 * Indirect action configuration.
17538 * @param[in] action
17539 * The indirect action object to validate.
17540 * @param[out] error
17541 * Perform verbose error reporting if not NULL. Initialized in case of
17545 * 0 on success, otherwise negative errno value.
17548 flow_dv_action_validate(struct rte_eth_dev *dev,
17549 const struct rte_flow_indir_action_conf *conf,
17550 const struct rte_flow_action *action,
17551 struct rte_flow_error *err)
17553 struct mlx5_priv *priv = dev->data->dev_private;
17555 RTE_SET_USED(conf);
17556 switch (action->type) {
17557 case RTE_FLOW_ACTION_TYPE_RSS:
17559 * priv->obj_ops is set according to driver capabilities.
17560 * When DevX capabilities are
17561 * sufficient, it is set to devx_obj_ops.
17562 * Otherwise, it is set to ibv_obj_ops.
17563 * ibv_obj_ops doesn't support ind_table_modify operation.
17564 * In this case the indirect RSS action can't be used.
17566 if (priv->obj_ops.ind_table_modify == NULL)
17567 return rte_flow_error_set
17569 RTE_FLOW_ERROR_TYPE_ACTION,
17571 "Indirect RSS action not supported");
17572 return mlx5_validate_action_rss(dev, action, err);
17573 case RTE_FLOW_ACTION_TYPE_AGE:
17574 if (!priv->sh->aso_age_mng)
17575 return rte_flow_error_set(err, ENOTSUP,
17576 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17578 "Indirect age action not supported");
17579 return flow_dv_validate_action_age(0, action, dev, err);
17580 case RTE_FLOW_ACTION_TYPE_COUNT:
17581 return flow_dv_validate_action_count(dev, true, 0, err);
17582 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17583 if (!priv->sh->ct_aso_en)
17584 return rte_flow_error_set(err, ENOTSUP,
17585 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17586 "ASO CT is not supported");
17587 return mlx5_validate_action_ct(dev, action->conf, err);
17589 return rte_flow_error_set(err, ENOTSUP,
17590 RTE_FLOW_ERROR_TYPE_ACTION,
17592 "action type not supported");
17597 * Check if the RSS configurations for colors of a meter policy match
17598 * each other, except the queues.
17601 * Pointer to the first RSS flow action.
17603 * Pointer to the second RSS flow action.
17606 * 0 on match, 1 on conflict.
17609 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17610 const struct rte_flow_action_rss *r2)
17612 if (r1 == NULL || r2 == NULL)
17614 if (!(r1->level <= 1 && r2->level <= 1) &&
17615 !(r1->level > 1 && r2->level > 1))
17617 if (r1->types != r2->types &&
17618 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17619 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17621 if (r1->key || r2->key) {
17622 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17623 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17625 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17632 * Validate the meter hierarchy chain for meter policy.
17635 * Pointer to the Ethernet device structure.
17636 * @param[in] meter_id
17638 * @param[in] action_flags
17639 * Holds the actions detected until now.
17640 * @param[out] is_rss
17642 * @param[out] hierarchy_domain
17643 * The domain bitmap for hierarchy policy.
17644 * @param[out] error
17645 * Perform verbose error reporting if not NULL. Initialized in case of
17649 * 0 on success, otherwise negative errno value with error set.
17652 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17654 uint64_t action_flags,
17656 uint8_t *hierarchy_domain,
17657 struct rte_mtr_error *error)
17659 struct mlx5_priv *priv = dev->data->dev_private;
17660 struct mlx5_flow_meter_info *fm;
17661 struct mlx5_flow_meter_policy *policy;
17664 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17665 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17666 return -rte_mtr_error_set(error, EINVAL,
17667 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17669 "Multiple fate actions not supported.");
17670 *hierarchy_domain = 0;
17672 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17674 return -rte_mtr_error_set(error, EINVAL,
17675 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17676 "Meter not found in meter hierarchy.");
17677 if (fm->def_policy)
17678 return -rte_mtr_error_set(error, EINVAL,
17679 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17680 "Non termination meter not supported in hierarchy.");
17681 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17682 MLX5_ASSERT(policy);
17684 * Only inherit the supported domains of the first meter in
17686 * One meter supports at least one domain.
17688 if (!*hierarchy_domain) {
17689 if (policy->transfer)
17690 *hierarchy_domain |=
17691 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17692 if (policy->ingress)
17693 *hierarchy_domain |=
17694 MLX5_MTR_DOMAIN_INGRESS_BIT;
17695 if (policy->egress)
17696 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17698 if (!policy->is_hierarchy) {
17699 *is_rss = policy->is_rss;
17702 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17703 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17704 return -rte_mtr_error_set(error, EINVAL,
17705 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17706 "Exceed max hierarchy meter number.");
17712 * Validate meter policy actions.
17713 * Dispatcher for action type specific validation.
17716 * Pointer to the Ethernet device structure.
17717 * @param[in] action
17718 * The meter policy action object to validate.
17720 * Attributes of flow to determine steering domain.
17721 * @param[out] error
17722 * Perform verbose error reporting if not NULL. Initialized in case of
17726 * 0 on success, otherwise negative errno value.
17729 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17730 const struct rte_flow_action *actions[RTE_COLORS],
17731 struct rte_flow_attr *attr,
17733 uint8_t *domain_bitmap,
17734 uint8_t *policy_mode,
17735 struct rte_mtr_error *error)
17737 struct mlx5_priv *priv = dev->data->dev_private;
17738 struct mlx5_dev_config *dev_conf = &priv->config;
17739 const struct rte_flow_action *act;
17740 uint64_t action_flags[RTE_COLORS] = {0};
17743 struct rte_flow_error flow_err;
17744 uint8_t domain_color[RTE_COLORS] = {0};
17745 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17746 uint8_t hierarchy_domain = 0;
17747 const struct rte_flow_action_meter *mtr;
17748 bool def_green = false;
17749 bool def_yellow = false;
17750 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17752 if (!priv->config.dv_esw_en)
17753 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17754 *domain_bitmap = def_domain;
17755 /* Red color could only support DROP action. */
17756 if (!actions[RTE_COLOR_RED] ||
17757 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17758 return -rte_mtr_error_set(error, ENOTSUP,
17759 RTE_MTR_ERROR_TYPE_METER_POLICY,
17760 NULL, "Red color only supports drop action.");
17762 * Check default policy actions:
17763 * Green / Yellow: no action, Red: drop action
17764 * Either G or Y will trigger default policy actions to be created.
17766 if (!actions[RTE_COLOR_GREEN] ||
17767 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17769 if (!actions[RTE_COLOR_YELLOW] ||
17770 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17772 if (def_green && def_yellow) {
17773 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17775 } else if (!def_green && def_yellow) {
17776 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17777 } else if (def_green && !def_yellow) {
17778 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17780 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17782 /* Set to empty string in case of NULL pointer access by user. */
17783 flow_err.message = "";
17784 for (i = 0; i < RTE_COLORS; i++) {
17786 for (action_flags[i] = 0, actions_n = 0;
17787 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17789 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17790 return -rte_mtr_error_set(error, ENOTSUP,
17791 RTE_MTR_ERROR_TYPE_METER_POLICY,
17792 NULL, "too many actions");
17793 switch (act->type) {
17794 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17795 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17796 if (!priv->config.dv_esw_en)
17797 return -rte_mtr_error_set(error,
17799 RTE_MTR_ERROR_TYPE_METER_POLICY,
17800 NULL, "PORT action validate check"
17801 " fail for ESW disable");
17802 ret = flow_dv_validate_action_port_id(dev,
17804 act, attr, &flow_err);
17806 return -rte_mtr_error_set(error,
17808 RTE_MTR_ERROR_TYPE_METER_POLICY,
17809 NULL, flow_err.message ?
17811 "PORT action validate check fail");
17813 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17815 case RTE_FLOW_ACTION_TYPE_MARK:
17816 ret = flow_dv_validate_action_mark(dev, act,
17820 return -rte_mtr_error_set(error,
17822 RTE_MTR_ERROR_TYPE_METER_POLICY,
17823 NULL, flow_err.message ?
17825 "Mark action validate check fail");
17826 if (dev_conf->dv_xmeta_en !=
17827 MLX5_XMETA_MODE_LEGACY)
17828 return -rte_mtr_error_set(error,
17830 RTE_MTR_ERROR_TYPE_METER_POLICY,
17831 NULL, "Extend MARK action is "
17832 "not supported. Please try use "
17833 "default policy for meter.");
17834 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17837 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17838 ret = flow_dv_validate_action_set_tag(dev,
17839 act, action_flags[i],
17842 return -rte_mtr_error_set(error,
17844 RTE_MTR_ERROR_TYPE_METER_POLICY,
17845 NULL, flow_err.message ?
17847 "Set tag action validate check fail");
17848 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17851 case RTE_FLOW_ACTION_TYPE_DROP:
17852 ret = mlx5_flow_validate_action_drop
17853 (action_flags[i], attr, &flow_err);
17855 return -rte_mtr_error_set(error,
17857 RTE_MTR_ERROR_TYPE_METER_POLICY,
17858 NULL, flow_err.message ?
17860 "Drop action validate check fail");
17861 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17864 case RTE_FLOW_ACTION_TYPE_QUEUE:
17866 * Check whether extensive
17867 * metadata feature is engaged.
17869 if (dev_conf->dv_flow_en &&
17870 (dev_conf->dv_xmeta_en !=
17871 MLX5_XMETA_MODE_LEGACY) &&
17872 mlx5_flow_ext_mreg_supported(dev))
17873 return -rte_mtr_error_set(error,
17875 RTE_MTR_ERROR_TYPE_METER_POLICY,
17876 NULL, "Queue action with meta "
17877 "is not supported. Please try use "
17878 "default policy for meter.");
17879 ret = mlx5_flow_validate_action_queue(act,
17880 action_flags[i], dev,
17883 return -rte_mtr_error_set(error,
17885 RTE_MTR_ERROR_TYPE_METER_POLICY,
17886 NULL, flow_err.message ?
17888 "Queue action validate check fail");
17889 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17892 case RTE_FLOW_ACTION_TYPE_RSS:
17893 if (dev_conf->dv_flow_en &&
17894 (dev_conf->dv_xmeta_en !=
17895 MLX5_XMETA_MODE_LEGACY) &&
17896 mlx5_flow_ext_mreg_supported(dev))
17897 return -rte_mtr_error_set(error,
17899 RTE_MTR_ERROR_TYPE_METER_POLICY,
17900 NULL, "RSS action with meta "
17901 "is not supported. Please try use "
17902 "default policy for meter.");
17903 ret = mlx5_validate_action_rss(dev, act,
17906 return -rte_mtr_error_set(error,
17908 RTE_MTR_ERROR_TYPE_METER_POLICY,
17909 NULL, flow_err.message ?
17911 "RSS action validate check fail");
17912 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17914 /* Either G or Y will set the RSS. */
17915 rss_color[i] = act->conf;
17917 case RTE_FLOW_ACTION_TYPE_JUMP:
17918 ret = flow_dv_validate_action_jump(dev,
17919 NULL, act, action_flags[i],
17920 attr, true, &flow_err);
17922 return -rte_mtr_error_set(error,
17924 RTE_MTR_ERROR_TYPE_METER_POLICY,
17925 NULL, flow_err.message ?
17927 "Jump action validate check fail");
17929 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17932 * Only the last meter in the hierarchy will support
17933 * the YELLOW color steering. Then in the meter policy
17934 * actions list, there should be no other meter inside.
17936 case RTE_FLOW_ACTION_TYPE_METER:
17937 if (i != RTE_COLOR_GREEN)
17938 return -rte_mtr_error_set(error,
17940 RTE_MTR_ERROR_TYPE_METER_POLICY,
17942 "Meter hierarchy only supports GREEN color.");
17943 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17944 return -rte_mtr_error_set(error,
17946 RTE_MTR_ERROR_TYPE_METER_POLICY,
17948 "No yellow policy should be provided in meter hierarchy.");
17950 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17960 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17963 return -rte_mtr_error_set(error, ENOTSUP,
17964 RTE_MTR_ERROR_TYPE_METER_POLICY,
17966 "Doesn't support optional action");
17969 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
17970 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17971 } else if ((action_flags[i] &
17972 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17973 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
17975 * Only support MLX5_XMETA_MODE_LEGACY
17976 * so MARK action is only in ingress domain.
17978 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17980 domain_color[i] = def_domain;
17981 if (action_flags[i] &&
17982 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17984 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17986 if (action_flags[i] &
17987 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17988 domain_color[i] &= hierarchy_domain;
17990 * Non-termination actions only support NIC Tx domain.
17991 * The adjustion should be skipped when there is no
17992 * action or only END is provided. The default domains
17993 * bit-mask is set to find the MIN intersection.
17994 * The action flags checking should also be skipped.
17996 if ((def_green && i == RTE_COLOR_GREEN) ||
17997 (def_yellow && i == RTE_COLOR_YELLOW))
18000 * Validate the drop action mutual exclusion
18001 * with other actions. Drop action is mutually-exclusive
18002 * with any other action, except for Count action.
18004 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18005 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18006 return -rte_mtr_error_set(error, ENOTSUP,
18007 RTE_MTR_ERROR_TYPE_METER_POLICY,
18008 NULL, "Drop action is mutually-exclusive "
18009 "with any other action");
18011 /* Eswitch has few restrictions on using items and actions */
18012 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18013 if (!mlx5_flow_ext_mreg_supported(dev) &&
18014 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18015 return -rte_mtr_error_set(error, ENOTSUP,
18016 RTE_MTR_ERROR_TYPE_METER_POLICY,
18017 NULL, "unsupported action MARK");
18018 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18019 return -rte_mtr_error_set(error, ENOTSUP,
18020 RTE_MTR_ERROR_TYPE_METER_POLICY,
18021 NULL, "unsupported action QUEUE");
18022 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18023 return -rte_mtr_error_set(error, ENOTSUP,
18024 RTE_MTR_ERROR_TYPE_METER_POLICY,
18025 NULL, "unsupported action RSS");
18026 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18027 return -rte_mtr_error_set(error, ENOTSUP,
18028 RTE_MTR_ERROR_TYPE_METER_POLICY,
18029 NULL, "no fate action is found");
18031 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18032 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18033 if ((domain_color[i] &
18034 MLX5_MTR_DOMAIN_EGRESS_BIT))
18036 MLX5_MTR_DOMAIN_EGRESS_BIT;
18038 return -rte_mtr_error_set(error,
18040 RTE_MTR_ERROR_TYPE_METER_POLICY,
18042 "no fate action is found");
18046 /* If both colors have RSS, the attributes should be the same. */
18047 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18048 rss_color[RTE_COLOR_YELLOW]))
18049 return -rte_mtr_error_set(error, EINVAL,
18050 RTE_MTR_ERROR_TYPE_METER_POLICY,
18051 NULL, "policy RSS attr conflict");
18052 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18054 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18055 if (!def_green && !def_yellow &&
18056 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18057 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18058 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18059 return -rte_mtr_error_set(error, EINVAL,
18060 RTE_MTR_ERROR_TYPE_METER_POLICY,
18061 NULL, "policy domains conflict");
18063 * At least one color policy is listed in the actions, the domains
18064 * to be supported should be the intersection.
18066 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18067 domain_color[RTE_COLOR_YELLOW];
18072 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18074 struct mlx5_priv *priv = dev->data->dev_private;
18077 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18078 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18083 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18084 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18088 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18089 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18097 * Discover the number of available flow priorities
18098 * by trying to create a flow with the highest priority value
18099 * for each possible number.
18104 * List of possible number of available priorities.
18105 * @param[in] vprio_n
18106 * Size of @p vprio array.
18108 * On success, number of available flow priorities.
18109 * On failure, a negative errno-style code and rte_errno is set.
18112 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18113 const uint16_t *vprio, int vprio_n)
18115 struct mlx5_priv *priv = dev->data->dev_private;
18116 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18117 struct rte_flow_item_eth eth;
18118 struct rte_flow_item item = {
18119 .type = RTE_FLOW_ITEM_TYPE_ETH,
18123 struct mlx5_flow_dv_matcher matcher = {
18125 .size = sizeof(matcher.mask.buf),
18128 union mlx5_flow_tbl_key tbl_key;
18129 struct mlx5_flow flow;
18131 struct rte_flow_error error;
18133 int i, err, ret = -ENOTSUP;
18136 * Prepare a flow with a catch-all pattern and a drop action.
18137 * Use drop queue, because shared drop action may be unavailable.
18139 action = priv->drop_queue.hrxq->action;
18140 if (action == NULL) {
18141 DRV_LOG(ERR, "Priority discovery requires a drop action");
18142 rte_errno = ENOTSUP;
18145 memset(&flow, 0, sizeof(flow));
18146 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18147 if (flow.handle == NULL) {
18148 DRV_LOG(ERR, "Cannot create flow handle");
18149 rte_errno = ENOMEM;
18152 flow.ingress = true;
18153 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18154 flow.dv.actions[0] = action;
18155 flow.dv.actions_n = 1;
18156 memset(ð, 0, sizeof(eth));
18157 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18158 &item, /* inner */ false, /* group */ 0);
18159 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18160 for (i = 0; i < vprio_n; i++) {
18161 /* Configure the next proposed maximum priority. */
18162 matcher.priority = vprio[i] - 1;
18163 memset(&tbl_key, 0, sizeof(tbl_key));
18164 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18169 /* This action is pure SW and must always succeed. */
18170 DRV_LOG(ERR, "Cannot register matcher");
18174 /* Try to apply the flow to HW. */
18175 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18176 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18177 err = mlx5_flow_os_create_flow
18178 (flow.handle->dvh.matcher->matcher_object,
18179 (void *)&flow.dv.value, flow.dv.actions_n,
18180 flow.dv.actions, &flow.handle->drv_flow);
18182 claim_zero(mlx5_flow_os_destroy_flow
18183 (flow.handle->drv_flow));
18184 flow.handle->drv_flow = NULL;
18186 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18191 mlx5_ipool_free(pool, flow.handle_idx);
18192 /* Set rte_errno if no expected priority value matched. */
18198 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18199 .validate = flow_dv_validate,
18200 .prepare = flow_dv_prepare,
18201 .translate = flow_dv_translate,
18202 .apply = flow_dv_apply,
18203 .remove = flow_dv_remove,
18204 .destroy = flow_dv_destroy,
18205 .query = flow_dv_query,
18206 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18207 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18208 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18209 .create_meter = flow_dv_mtr_alloc,
18210 .free_meter = flow_dv_aso_mtr_release_to_pool,
18211 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18212 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18213 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18214 .create_policy_rules = flow_dv_create_policy_rules,
18215 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18216 .create_def_policy = flow_dv_create_def_policy,
18217 .destroy_def_policy = flow_dv_destroy_def_policy,
18218 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18219 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18220 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18221 .counter_alloc = flow_dv_counter_allocate,
18222 .counter_free = flow_dv_counter_free,
18223 .counter_query = flow_dv_counter_query,
18224 .get_aged_flows = flow_dv_get_aged_flows,
18225 .action_validate = flow_dv_action_validate,
18226 .action_create = flow_dv_action_create,
18227 .action_destroy = flow_dv_action_destroy,
18228 .action_update = flow_dv_action_update,
18229 .action_query = flow_dv_action_query,
18230 .sync_domain = flow_dv_sync_domain,
18231 .discover_priorities = flow_dv_discover_priorities,
18232 .item_create = flow_dv_item_create,
18233 .item_release = flow_dv_item_release,
18236 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */