1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
81 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
82 uint32_t encap_decap_idx);
85 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
89 * Initialize flow attributes structure according to flow items' types.
91 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
92 * mode. For tunnel mode, the items to be modified are the outermost ones.
95 * Pointer to item specification.
97 * Pointer to flow attributes structure.
99 * Pointer to the sub flow.
100 * @param[in] tunnel_decap
101 * Whether action is after tunnel decapsulation.
104 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
105 struct mlx5_flow *dev_flow, bool tunnel_decap)
107 uint64_t layers = dev_flow->handle->layers;
110 * If layers is already initialized, it means this dev_flow is the
111 * suffix flow, the layers flags is set by the prefix flow. Need to
112 * use the layer flags from prefix flow as the suffix flow may not
113 * have the user defined items as the flow is split.
116 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
118 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
120 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
122 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
127 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
128 uint8_t next_protocol = 0xff;
129 switch (item->type) {
130 case RTE_FLOW_ITEM_TYPE_GRE:
131 case RTE_FLOW_ITEM_TYPE_NVGRE:
132 case RTE_FLOW_ITEM_TYPE_VXLAN:
133 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
134 case RTE_FLOW_ITEM_TYPE_GENEVE:
135 case RTE_FLOW_ITEM_TYPE_MPLS:
139 case RTE_FLOW_ITEM_TYPE_IPV4:
142 if (item->mask != NULL &&
143 ((const struct rte_flow_item_ipv4 *)
144 item->mask)->hdr.next_proto_id)
146 ((const struct rte_flow_item_ipv4 *)
147 (item->spec))->hdr.next_proto_id &
148 ((const struct rte_flow_item_ipv4 *)
149 (item->mask))->hdr.next_proto_id;
150 if ((next_protocol == IPPROTO_IPIP ||
151 next_protocol == IPPROTO_IPV6) && tunnel_decap)
154 case RTE_FLOW_ITEM_TYPE_IPV6:
157 if (item->mask != NULL &&
158 ((const struct rte_flow_item_ipv6 *)
159 item->mask)->hdr.proto)
161 ((const struct rte_flow_item_ipv6 *)
162 (item->spec))->hdr.proto &
163 ((const struct rte_flow_item_ipv6 *)
164 (item->mask))->hdr.proto;
165 if ((next_protocol == IPPROTO_IPIP ||
166 next_protocol == IPPROTO_IPV6) && tunnel_decap)
169 case RTE_FLOW_ITEM_TYPE_UDP:
173 case RTE_FLOW_ITEM_TYPE_TCP:
185 * Convert rte_mtr_color to mlx5 color.
194 rte_col_2_mlx5_col(enum rte_color rcol)
197 case RTE_COLOR_GREEN:
198 return MLX5_FLOW_COLOR_GREEN;
199 case RTE_COLOR_YELLOW:
200 return MLX5_FLOW_COLOR_YELLOW;
202 return MLX5_FLOW_COLOR_RED;
206 return MLX5_FLOW_COLOR_UNDEFINED;
209 struct field_modify_info {
210 uint32_t size; /* Size of field in protocol header, in bytes. */
211 uint32_t offset; /* Offset of field in protocol header, in bytes. */
212 enum mlx5_modification_field id;
215 struct field_modify_info modify_eth[] = {
216 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
217 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
218 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
219 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
223 struct field_modify_info modify_vlan_out_first_vid[] = {
224 /* Size in bits !!! */
225 {12, 0, MLX5_MODI_OUT_FIRST_VID},
229 struct field_modify_info modify_ipv4[] = {
230 {1, 1, MLX5_MODI_OUT_IP_DSCP},
231 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
232 {4, 12, MLX5_MODI_OUT_SIPV4},
233 {4, 16, MLX5_MODI_OUT_DIPV4},
237 struct field_modify_info modify_ipv6[] = {
238 {1, 0, MLX5_MODI_OUT_IP_DSCP},
239 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
240 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
241 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
242 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
243 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
244 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
245 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
246 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
247 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
251 struct field_modify_info modify_udp[] = {
252 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
253 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
257 struct field_modify_info modify_tcp[] = {
258 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
259 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
260 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
261 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
266 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
267 uint8_t next_protocol, uint64_t *item_flags,
270 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
271 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
272 if (next_protocol == IPPROTO_IPIP) {
273 *item_flags |= MLX5_FLOW_LAYER_IPIP;
276 if (next_protocol == IPPROTO_IPV6) {
277 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
283 * Acquire the synchronizing object to protect multithreaded access
284 * to shared dv context. Lock occurs only if context is actually
285 * shared, i.e. we have multiport IB device and representors are
289 * Pointer to the rte_eth_dev structure.
292 flow_dv_shared_lock(struct rte_eth_dev *dev)
294 struct mlx5_priv *priv = dev->data->dev_private;
295 struct mlx5_dev_ctx_shared *sh = priv->sh;
297 if (sh->refcnt > 1) {
300 ret = pthread_mutex_lock(&sh->dv_mutex);
307 flow_dv_shared_unlock(struct rte_eth_dev *dev)
309 struct mlx5_priv *priv = dev->data->dev_private;
310 struct mlx5_dev_ctx_shared *sh = priv->sh;
312 if (sh->refcnt > 1) {
315 ret = pthread_mutex_unlock(&sh->dv_mutex);
321 /* Update VLAN's VID/PCP based on input rte_flow_action.
324 * Pointer to struct rte_flow_action.
326 * Pointer to struct rte_vlan_hdr.
329 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
330 struct rte_vlan_hdr *vlan)
333 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
335 ((const struct rte_flow_action_of_set_vlan_pcp *)
336 action->conf)->vlan_pcp;
337 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
338 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
339 vlan->vlan_tci |= vlan_tci;
340 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
341 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
342 vlan->vlan_tci |= rte_be_to_cpu_16
343 (((const struct rte_flow_action_of_set_vlan_vid *)
344 action->conf)->vlan_vid);
349 * Fetch 1, 2, 3 or 4 byte field from the byte array
350 * and return as unsigned integer in host-endian format.
353 * Pointer to data array.
355 * Size of field to extract.
358 * converted field in host endian format.
360 static inline uint32_t
361 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
370 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
373 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
374 ret = (ret << 8) | *(data + sizeof(uint16_t));
377 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
388 * Convert modify-header action to DV specification.
390 * Data length of each action is determined by provided field description
391 * and the item mask. Data bit offset and width of each action is determined
392 * by provided item mask.
395 * Pointer to item specification.
397 * Pointer to field modification information.
398 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
399 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
400 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
402 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
403 * Negative offset value sets the same offset as source offset.
404 * size field is ignored, value is taken from source field.
405 * @param[in,out] resource
406 * Pointer to the modify-header resource.
408 * Type of modification.
410 * Pointer to the error structure.
413 * 0 on success, a negative errno value otherwise and rte_errno is set.
416 flow_dv_convert_modify_action(struct rte_flow_item *item,
417 struct field_modify_info *field,
418 struct field_modify_info *dcopy,
419 struct mlx5_flow_dv_modify_hdr_resource *resource,
420 uint32_t type, struct rte_flow_error *error)
422 uint32_t i = resource->actions_num;
423 struct mlx5_modification_cmd *actions = resource->actions;
426 * The item and mask are provided in big-endian format.
427 * The fields should be presented as in big-endian format either.
428 * Mask must be always present, it defines the actual field width.
430 MLX5_ASSERT(item->mask);
431 MLX5_ASSERT(field->size);
438 if (i >= MLX5_MAX_MODIFY_NUM)
439 return rte_flow_error_set(error, EINVAL,
440 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
441 "too many items to modify");
442 /* Fetch variable byte size mask from the array. */
443 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
444 field->offset, field->size);
449 /* Deduce actual data width in bits from mask value. */
450 off_b = rte_bsf32(mask);
451 size_b = sizeof(uint32_t) * CHAR_BIT -
452 off_b - __builtin_clz(mask);
454 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
455 actions[i] = (struct mlx5_modification_cmd) {
461 /* Convert entire record to expected big-endian format. */
462 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
463 if (type == MLX5_MODIFICATION_TYPE_COPY) {
465 actions[i].dst_field = dcopy->id;
466 actions[i].dst_offset =
467 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
468 /* Convert entire record to big-endian format. */
469 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
471 MLX5_ASSERT(item->spec);
472 data = flow_dv_fetch_field((const uint8_t *)item->spec +
473 field->offset, field->size);
474 /* Shift out the trailing masked bits from data. */
475 data = (data & mask) >> off_b;
476 actions[i].data1 = rte_cpu_to_be_32(data);
480 } while (field->size);
481 if (resource->actions_num == i)
482 return rte_flow_error_set(error, EINVAL,
483 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
484 "invalid modification flow item");
485 resource->actions_num = i;
490 * Convert modify-header set IPv4 address action to DV specification.
492 * @param[in,out] resource
493 * Pointer to the modify-header resource.
495 * Pointer to action specification.
497 * Pointer to the error structure.
500 * 0 on success, a negative errno value otherwise and rte_errno is set.
503 flow_dv_convert_action_modify_ipv4
504 (struct mlx5_flow_dv_modify_hdr_resource *resource,
505 const struct rte_flow_action *action,
506 struct rte_flow_error *error)
508 const struct rte_flow_action_set_ipv4 *conf =
509 (const struct rte_flow_action_set_ipv4 *)(action->conf);
510 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
511 struct rte_flow_item_ipv4 ipv4;
512 struct rte_flow_item_ipv4 ipv4_mask;
514 memset(&ipv4, 0, sizeof(ipv4));
515 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
516 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
517 ipv4.hdr.src_addr = conf->ipv4_addr;
518 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
520 ipv4.hdr.dst_addr = conf->ipv4_addr;
521 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
524 item.mask = &ipv4_mask;
525 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
526 MLX5_MODIFICATION_TYPE_SET, error);
530 * Convert modify-header set IPv6 address action to DV specification.
532 * @param[in,out] resource
533 * Pointer to the modify-header resource.
535 * Pointer to action specification.
537 * Pointer to the error structure.
540 * 0 on success, a negative errno value otherwise and rte_errno is set.
543 flow_dv_convert_action_modify_ipv6
544 (struct mlx5_flow_dv_modify_hdr_resource *resource,
545 const struct rte_flow_action *action,
546 struct rte_flow_error *error)
548 const struct rte_flow_action_set_ipv6 *conf =
549 (const struct rte_flow_action_set_ipv6 *)(action->conf);
550 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
551 struct rte_flow_item_ipv6 ipv6;
552 struct rte_flow_item_ipv6 ipv6_mask;
554 memset(&ipv6, 0, sizeof(ipv6));
555 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
556 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
557 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
558 sizeof(ipv6.hdr.src_addr));
559 memcpy(&ipv6_mask.hdr.src_addr,
560 &rte_flow_item_ipv6_mask.hdr.src_addr,
561 sizeof(ipv6.hdr.src_addr));
563 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
564 sizeof(ipv6.hdr.dst_addr));
565 memcpy(&ipv6_mask.hdr.dst_addr,
566 &rte_flow_item_ipv6_mask.hdr.dst_addr,
567 sizeof(ipv6.hdr.dst_addr));
570 item.mask = &ipv6_mask;
571 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
572 MLX5_MODIFICATION_TYPE_SET, error);
576 * Convert modify-header set MAC address action to DV specification.
578 * @param[in,out] resource
579 * Pointer to the modify-header resource.
581 * Pointer to action specification.
583 * Pointer to the error structure.
586 * 0 on success, a negative errno value otherwise and rte_errno is set.
589 flow_dv_convert_action_modify_mac
590 (struct mlx5_flow_dv_modify_hdr_resource *resource,
591 const struct rte_flow_action *action,
592 struct rte_flow_error *error)
594 const struct rte_flow_action_set_mac *conf =
595 (const struct rte_flow_action_set_mac *)(action->conf);
596 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
597 struct rte_flow_item_eth eth;
598 struct rte_flow_item_eth eth_mask;
600 memset(ð, 0, sizeof(eth));
601 memset(ð_mask, 0, sizeof(eth_mask));
602 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
603 memcpy(ð.src.addr_bytes, &conf->mac_addr,
604 sizeof(eth.src.addr_bytes));
605 memcpy(ð_mask.src.addr_bytes,
606 &rte_flow_item_eth_mask.src.addr_bytes,
607 sizeof(eth_mask.src.addr_bytes));
609 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
610 sizeof(eth.dst.addr_bytes));
611 memcpy(ð_mask.dst.addr_bytes,
612 &rte_flow_item_eth_mask.dst.addr_bytes,
613 sizeof(eth_mask.dst.addr_bytes));
616 item.mask = ð_mask;
617 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
618 MLX5_MODIFICATION_TYPE_SET, error);
622 * Convert modify-header set VLAN VID action to DV specification.
624 * @param[in,out] resource
625 * Pointer to the modify-header resource.
627 * Pointer to action specification.
629 * Pointer to the error structure.
632 * 0 on success, a negative errno value otherwise and rte_errno is set.
635 flow_dv_convert_action_modify_vlan_vid
636 (struct mlx5_flow_dv_modify_hdr_resource *resource,
637 const struct rte_flow_action *action,
638 struct rte_flow_error *error)
640 const struct rte_flow_action_of_set_vlan_vid *conf =
641 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
642 int i = resource->actions_num;
643 struct mlx5_modification_cmd *actions = resource->actions;
644 struct field_modify_info *field = modify_vlan_out_first_vid;
646 if (i >= MLX5_MAX_MODIFY_NUM)
647 return rte_flow_error_set(error, EINVAL,
648 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
649 "too many items to modify");
650 actions[i] = (struct mlx5_modification_cmd) {
651 .action_type = MLX5_MODIFICATION_TYPE_SET,
653 .length = field->size,
654 .offset = field->offset,
656 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
657 actions[i].data1 = conf->vlan_vid;
658 actions[i].data1 = actions[i].data1 << 16;
659 resource->actions_num = ++i;
664 * Convert modify-header set TP action to DV specification.
666 * @param[in,out] resource
667 * Pointer to the modify-header resource.
669 * Pointer to action specification.
671 * Pointer to rte_flow_item objects list.
673 * Pointer to flow attributes structure.
674 * @param[in] dev_flow
675 * Pointer to the sub flow.
676 * @param[in] tunnel_decap
677 * Whether action is after tunnel decapsulation.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_tp
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 const struct rte_flow_item *items,
689 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
690 bool tunnel_decap, struct rte_flow_error *error)
692 const struct rte_flow_action_set_tp *conf =
693 (const struct rte_flow_action_set_tp *)(action->conf);
694 struct rte_flow_item item;
695 struct rte_flow_item_udp udp;
696 struct rte_flow_item_udp udp_mask;
697 struct rte_flow_item_tcp tcp;
698 struct rte_flow_item_tcp tcp_mask;
699 struct field_modify_info *field;
702 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
704 memset(&udp, 0, sizeof(udp));
705 memset(&udp_mask, 0, sizeof(udp_mask));
706 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
707 udp.hdr.src_port = conf->port;
708 udp_mask.hdr.src_port =
709 rte_flow_item_udp_mask.hdr.src_port;
711 udp.hdr.dst_port = conf->port;
712 udp_mask.hdr.dst_port =
713 rte_flow_item_udp_mask.hdr.dst_port;
715 item.type = RTE_FLOW_ITEM_TYPE_UDP;
717 item.mask = &udp_mask;
720 MLX5_ASSERT(attr->tcp);
721 memset(&tcp, 0, sizeof(tcp));
722 memset(&tcp_mask, 0, sizeof(tcp_mask));
723 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
724 tcp.hdr.src_port = conf->port;
725 tcp_mask.hdr.src_port =
726 rte_flow_item_tcp_mask.hdr.src_port;
728 tcp.hdr.dst_port = conf->port;
729 tcp_mask.hdr.dst_port =
730 rte_flow_item_tcp_mask.hdr.dst_port;
732 item.type = RTE_FLOW_ITEM_TYPE_TCP;
734 item.mask = &tcp_mask;
737 return flow_dv_convert_modify_action(&item, field, NULL, resource,
738 MLX5_MODIFICATION_TYPE_SET, error);
742 * Convert modify-header set TTL action to DV specification.
744 * @param[in,out] resource
745 * Pointer to the modify-header resource.
747 * Pointer to action specification.
749 * Pointer to rte_flow_item objects list.
751 * Pointer to flow attributes structure.
752 * @param[in] dev_flow
753 * Pointer to the sub flow.
754 * @param[in] tunnel_decap
755 * Whether action is after tunnel decapsulation.
757 * Pointer to the error structure.
760 * 0 on success, a negative errno value otherwise and rte_errno is set.
763 flow_dv_convert_action_modify_ttl
764 (struct mlx5_flow_dv_modify_hdr_resource *resource,
765 const struct rte_flow_action *action,
766 const struct rte_flow_item *items,
767 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
768 bool tunnel_decap, struct rte_flow_error *error)
770 const struct rte_flow_action_set_ttl *conf =
771 (const struct rte_flow_action_set_ttl *)(action->conf);
772 struct rte_flow_item item;
773 struct rte_flow_item_ipv4 ipv4;
774 struct rte_flow_item_ipv4 ipv4_mask;
775 struct rte_flow_item_ipv6 ipv6;
776 struct rte_flow_item_ipv6 ipv6_mask;
777 struct field_modify_info *field;
780 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
782 memset(&ipv4, 0, sizeof(ipv4));
783 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
784 ipv4.hdr.time_to_live = conf->ttl_value;
785 ipv4_mask.hdr.time_to_live = 0xFF;
786 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
788 item.mask = &ipv4_mask;
791 MLX5_ASSERT(attr->ipv6);
792 memset(&ipv6, 0, sizeof(ipv6));
793 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
794 ipv6.hdr.hop_limits = conf->ttl_value;
795 ipv6_mask.hdr.hop_limits = 0xFF;
796 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
798 item.mask = &ipv6_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header decrement TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_dec_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_item *items,
830 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
831 bool tunnel_decap, struct rte_flow_error *error)
833 struct rte_flow_item item;
834 struct rte_flow_item_ipv4 ipv4;
835 struct rte_flow_item_ipv4 ipv4_mask;
836 struct rte_flow_item_ipv6 ipv6;
837 struct rte_flow_item_ipv6 ipv6_mask;
838 struct field_modify_info *field;
841 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
843 memset(&ipv4, 0, sizeof(ipv4));
844 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
845 ipv4.hdr.time_to_live = 0xFF;
846 ipv4_mask.hdr.time_to_live = 0xFF;
847 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
849 item.mask = &ipv4_mask;
852 MLX5_ASSERT(attr->ipv6);
853 memset(&ipv6, 0, sizeof(ipv6));
854 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
855 ipv6.hdr.hop_limits = 0xFF;
856 ipv6_mask.hdr.hop_limits = 0xFF;
857 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
859 item.mask = &ipv6_mask;
862 return flow_dv_convert_modify_action(&item, field, NULL, resource,
863 MLX5_MODIFICATION_TYPE_ADD, error);
867 * Convert modify-header increment/decrement TCP Sequence number
868 * to DV specification.
870 * @param[in,out] resource
871 * Pointer to the modify-header resource.
873 * Pointer to action specification.
875 * Pointer to the error structure.
878 * 0 on success, a negative errno value otherwise and rte_errno is set.
881 flow_dv_convert_action_modify_tcp_seq
882 (struct mlx5_flow_dv_modify_hdr_resource *resource,
883 const struct rte_flow_action *action,
884 struct rte_flow_error *error)
886 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
887 uint64_t value = rte_be_to_cpu_32(*conf);
888 struct rte_flow_item item;
889 struct rte_flow_item_tcp tcp;
890 struct rte_flow_item_tcp tcp_mask;
892 memset(&tcp, 0, sizeof(tcp));
893 memset(&tcp_mask, 0, sizeof(tcp_mask));
894 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
896 * The HW has no decrement operation, only increment operation.
897 * To simulate decrement X from Y using increment operation
898 * we need to add UINT32_MAX X times to Y.
899 * Each adding of UINT32_MAX decrements Y by 1.
902 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
903 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
904 item.type = RTE_FLOW_ITEM_TYPE_TCP;
906 item.mask = &tcp_mask;
907 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
908 MLX5_MODIFICATION_TYPE_ADD, error);
912 * Convert modify-header increment/decrement TCP Acknowledgment number
913 * to DV specification.
915 * @param[in,out] resource
916 * Pointer to the modify-header resource.
918 * Pointer to action specification.
920 * Pointer to the error structure.
923 * 0 on success, a negative errno value otherwise and rte_errno is set.
926 flow_dv_convert_action_modify_tcp_ack
927 (struct mlx5_flow_dv_modify_hdr_resource *resource,
928 const struct rte_flow_action *action,
929 struct rte_flow_error *error)
931 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
932 uint64_t value = rte_be_to_cpu_32(*conf);
933 struct rte_flow_item item;
934 struct rte_flow_item_tcp tcp;
935 struct rte_flow_item_tcp tcp_mask;
937 memset(&tcp, 0, sizeof(tcp));
938 memset(&tcp_mask, 0, sizeof(tcp_mask));
939 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
941 * The HW has no decrement operation, only increment operation.
942 * To simulate decrement X from Y using increment operation
943 * we need to add UINT32_MAX X times to Y.
944 * Each adding of UINT32_MAX decrements Y by 1.
947 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
948 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
949 item.type = RTE_FLOW_ITEM_TYPE_TCP;
951 item.mask = &tcp_mask;
952 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
953 MLX5_MODIFICATION_TYPE_ADD, error);
956 static enum mlx5_modification_field reg_to_field[] = {
957 [REG_NON] = MLX5_MODI_OUT_NONE,
958 [REG_A] = MLX5_MODI_META_DATA_REG_A,
959 [REG_B] = MLX5_MODI_META_DATA_REG_B,
960 [REG_C_0] = MLX5_MODI_META_REG_C_0,
961 [REG_C_1] = MLX5_MODI_META_REG_C_1,
962 [REG_C_2] = MLX5_MODI_META_REG_C_2,
963 [REG_C_3] = MLX5_MODI_META_REG_C_3,
964 [REG_C_4] = MLX5_MODI_META_REG_C_4,
965 [REG_C_5] = MLX5_MODI_META_REG_C_5,
966 [REG_C_6] = MLX5_MODI_META_REG_C_6,
967 [REG_C_7] = MLX5_MODI_META_REG_C_7,
971 * Convert register set to DV specification.
973 * @param[in,out] resource
974 * Pointer to the modify-header resource.
976 * Pointer to action specification.
978 * Pointer to the error structure.
981 * 0 on success, a negative errno value otherwise and rte_errno is set.
984 flow_dv_convert_action_set_reg
985 (struct mlx5_flow_dv_modify_hdr_resource *resource,
986 const struct rte_flow_action *action,
987 struct rte_flow_error *error)
989 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
990 struct mlx5_modification_cmd *actions = resource->actions;
991 uint32_t i = resource->actions_num;
993 if (i >= MLX5_MAX_MODIFY_NUM)
994 return rte_flow_error_set(error, EINVAL,
995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
996 "too many items to modify");
997 MLX5_ASSERT(conf->id != REG_NON);
998 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
999 actions[i] = (struct mlx5_modification_cmd) {
1000 .action_type = MLX5_MODIFICATION_TYPE_SET,
1001 .field = reg_to_field[conf->id],
1003 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1004 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1006 resource->actions_num = i;
1011 * Convert SET_TAG action to DV specification.
1014 * Pointer to the rte_eth_dev structure.
1015 * @param[in,out] resource
1016 * Pointer to the modify-header resource.
1018 * Pointer to action specification.
1020 * Pointer to the error structure.
1023 * 0 on success, a negative errno value otherwise and rte_errno is set.
1026 flow_dv_convert_action_set_tag
1027 (struct rte_eth_dev *dev,
1028 struct mlx5_flow_dv_modify_hdr_resource *resource,
1029 const struct rte_flow_action_set_tag *conf,
1030 struct rte_flow_error *error)
1032 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1033 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1034 struct rte_flow_item item = {
1038 struct field_modify_info reg_c_x[] = {
1041 enum mlx5_modification_field reg_type;
1044 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1047 MLX5_ASSERT(ret != REG_NON);
1048 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1049 reg_type = reg_to_field[ret];
1050 MLX5_ASSERT(reg_type > 0);
1051 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1052 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1053 MLX5_MODIFICATION_TYPE_SET, error);
1057 * Convert internal COPY_REG action to DV specification.
1060 * Pointer to the rte_eth_dev structure.
1061 * @param[in,out] res
1062 * Pointer to the modify-header resource.
1064 * Pointer to action specification.
1066 * Pointer to the error structure.
1069 * 0 on success, a negative errno value otherwise and rte_errno is set.
1072 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1073 struct mlx5_flow_dv_modify_hdr_resource *res,
1074 const struct rte_flow_action *action,
1075 struct rte_flow_error *error)
1077 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1078 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1079 struct rte_flow_item item = {
1083 struct field_modify_info reg_src[] = {
1084 {4, 0, reg_to_field[conf->src]},
1087 struct field_modify_info reg_dst = {
1089 .id = reg_to_field[conf->dst],
1091 /* Adjust reg_c[0] usage according to reported mask. */
1092 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1093 struct mlx5_priv *priv = dev->data->dev_private;
1094 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1096 MLX5_ASSERT(reg_c0);
1097 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1098 if (conf->dst == REG_C_0) {
1099 /* Copy to reg_c[0], within mask only. */
1100 reg_dst.offset = rte_bsf32(reg_c0);
1102 * Mask is ignoring the enianness, because
1103 * there is no conversion in datapath.
1105 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1106 /* Copy from destination lower bits to reg_c[0]. */
1107 mask = reg_c0 >> reg_dst.offset;
1109 /* Copy from destination upper bits to reg_c[0]. */
1110 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1111 rte_fls_u32(reg_c0));
1114 mask = rte_cpu_to_be_32(reg_c0);
1115 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1116 /* Copy from reg_c[0] to destination lower bits. */
1119 /* Copy from reg_c[0] to destination upper bits. */
1120 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1121 (rte_fls_u32(reg_c0) -
1126 return flow_dv_convert_modify_action(&item,
1127 reg_src, ®_dst, res,
1128 MLX5_MODIFICATION_TYPE_COPY,
1133 * Convert MARK action to DV specification. This routine is used
1134 * in extensive metadata only and requires metadata register to be
1135 * handled. In legacy mode hardware tag resource is engaged.
1138 * Pointer to the rte_eth_dev structure.
1140 * Pointer to MARK action specification.
1141 * @param[in,out] resource
1142 * Pointer to the modify-header resource.
1144 * Pointer to the error structure.
1147 * 0 on success, a negative errno value otherwise and rte_errno is set.
1150 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1151 const struct rte_flow_action_mark *conf,
1152 struct mlx5_flow_dv_modify_hdr_resource *resource,
1153 struct rte_flow_error *error)
1155 struct mlx5_priv *priv = dev->data->dev_private;
1156 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1157 priv->sh->dv_mark_mask);
1158 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1159 struct rte_flow_item item = {
1163 struct field_modify_info reg_c_x[] = {
1169 return rte_flow_error_set(error, EINVAL,
1170 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1171 NULL, "zero mark action mask");
1172 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1175 MLX5_ASSERT(reg > 0);
1176 if (reg == REG_C_0) {
1177 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1178 uint32_t shl_c0 = rte_bsf32(msk_c0);
1180 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1181 mask = rte_cpu_to_be_32(mask) & msk_c0;
1182 mask = rte_cpu_to_be_32(mask << shl_c0);
1184 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1185 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1186 MLX5_MODIFICATION_TYPE_SET, error);
1190 * Get metadata register index for specified steering domain.
1193 * Pointer to the rte_eth_dev structure.
1195 * Attributes of flow to determine steering domain.
1197 * Pointer to the error structure.
1200 * positive index on success, a negative errno value otherwise
1201 * and rte_errno is set.
1203 static enum modify_reg
1204 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1205 const struct rte_flow_attr *attr,
1206 struct rte_flow_error *error)
1209 mlx5_flow_get_reg_id(dev, attr->transfer ?
1213 MLX5_METADATA_RX, 0, error);
1215 return rte_flow_error_set(error,
1216 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1217 NULL, "unavailable "
1218 "metadata register");
1223 * Convert SET_META action to DV specification.
1226 * Pointer to the rte_eth_dev structure.
1227 * @param[in,out] resource
1228 * Pointer to the modify-header resource.
1230 * Attributes of flow that includes this item.
1232 * Pointer to action specification.
1234 * Pointer to the error structure.
1237 * 0 on success, a negative errno value otherwise and rte_errno is set.
1240 flow_dv_convert_action_set_meta
1241 (struct rte_eth_dev *dev,
1242 struct mlx5_flow_dv_modify_hdr_resource *resource,
1243 const struct rte_flow_attr *attr,
1244 const struct rte_flow_action_set_meta *conf,
1245 struct rte_flow_error *error)
1247 uint32_t data = conf->data;
1248 uint32_t mask = conf->mask;
1249 struct rte_flow_item item = {
1253 struct field_modify_info reg_c_x[] = {
1256 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1261 * In datapath code there is no endianness
1262 * coversions for perfromance reasons, all
1263 * pattern conversions are done in rte_flow.
1265 if (reg == REG_C_0) {
1266 struct mlx5_priv *priv = dev->data->dev_private;
1267 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1270 MLX5_ASSERT(msk_c0);
1271 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1272 shl_c0 = rte_bsf32(msk_c0);
1274 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1278 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1280 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1281 /* The routine expects parameters in memory as big-endian ones. */
1282 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1283 MLX5_MODIFICATION_TYPE_SET, error);
1287 * Convert modify-header set IPv4 DSCP action to DV specification.
1289 * @param[in,out] resource
1290 * Pointer to the modify-header resource.
1292 * Pointer to action specification.
1294 * Pointer to the error structure.
1297 * 0 on success, a negative errno value otherwise and rte_errno is set.
1300 flow_dv_convert_action_modify_ipv4_dscp
1301 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1302 const struct rte_flow_action *action,
1303 struct rte_flow_error *error)
1305 const struct rte_flow_action_set_dscp *conf =
1306 (const struct rte_flow_action_set_dscp *)(action->conf);
1307 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1308 struct rte_flow_item_ipv4 ipv4;
1309 struct rte_flow_item_ipv4 ipv4_mask;
1311 memset(&ipv4, 0, sizeof(ipv4));
1312 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1313 ipv4.hdr.type_of_service = conf->dscp;
1314 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1316 item.mask = &ipv4_mask;
1317 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1318 MLX5_MODIFICATION_TYPE_SET, error);
1322 * Convert modify-header set IPv6 DSCP action to DV specification.
1324 * @param[in,out] resource
1325 * Pointer to the modify-header resource.
1327 * Pointer to action specification.
1329 * Pointer to the error structure.
1332 * 0 on success, a negative errno value otherwise and rte_errno is set.
1335 flow_dv_convert_action_modify_ipv6_dscp
1336 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1337 const struct rte_flow_action *action,
1338 struct rte_flow_error *error)
1340 const struct rte_flow_action_set_dscp *conf =
1341 (const struct rte_flow_action_set_dscp *)(action->conf);
1342 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1343 struct rte_flow_item_ipv6 ipv6;
1344 struct rte_flow_item_ipv6 ipv6_mask;
1346 memset(&ipv6, 0, sizeof(ipv6));
1347 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1349 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1350 * rdma-core only accept the DSCP bits byte aligned start from
1351 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1352 * bits in IPv6 case as rdma-core requires byte aligned value.
1354 ipv6.hdr.vtc_flow = conf->dscp;
1355 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1357 item.mask = &ipv6_mask;
1358 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1359 MLX5_MODIFICATION_TYPE_SET, error);
1363 * Validate MARK item.
1366 * Pointer to the rte_eth_dev structure.
1368 * Item specification.
1370 * Attributes of flow that includes this item.
1372 * Pointer to error structure.
1375 * 0 on success, a negative errno value otherwise and rte_errno is set.
1378 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1379 const struct rte_flow_item *item,
1380 const struct rte_flow_attr *attr __rte_unused,
1381 struct rte_flow_error *error)
1383 struct mlx5_priv *priv = dev->data->dev_private;
1384 struct mlx5_dev_config *config = &priv->config;
1385 const struct rte_flow_item_mark *spec = item->spec;
1386 const struct rte_flow_item_mark *mask = item->mask;
1387 const struct rte_flow_item_mark nic_mask = {
1388 .id = priv->sh->dv_mark_mask,
1392 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1393 return rte_flow_error_set(error, ENOTSUP,
1394 RTE_FLOW_ERROR_TYPE_ITEM, item,
1395 "extended metadata feature"
1397 if (!mlx5_flow_ext_mreg_supported(dev))
1398 return rte_flow_error_set(error, ENOTSUP,
1399 RTE_FLOW_ERROR_TYPE_ITEM, item,
1400 "extended metadata register"
1401 " isn't supported");
1403 return rte_flow_error_set(error, ENOTSUP,
1404 RTE_FLOW_ERROR_TYPE_ITEM, item,
1405 "extended metadata register"
1406 " isn't available");
1407 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1411 return rte_flow_error_set(error, EINVAL,
1412 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1414 "data cannot be empty");
1415 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1416 return rte_flow_error_set(error, EINVAL,
1417 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1419 "mark id exceeds the limit");
1423 return rte_flow_error_set(error, EINVAL,
1424 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1425 "mask cannot be zero");
1427 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1428 (const uint8_t *)&nic_mask,
1429 sizeof(struct rte_flow_item_mark),
1430 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1437 * Validate META item.
1440 * Pointer to the rte_eth_dev structure.
1442 * Item specification.
1444 * Attributes of flow that includes this item.
1446 * Pointer to error structure.
1449 * 0 on success, a negative errno value otherwise and rte_errno is set.
1452 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1453 const struct rte_flow_item *item,
1454 const struct rte_flow_attr *attr,
1455 struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1458 struct mlx5_dev_config *config = &priv->config;
1459 const struct rte_flow_item_meta *spec = item->spec;
1460 const struct rte_flow_item_meta *mask = item->mask;
1461 struct rte_flow_item_meta nic_mask = {
1468 return rte_flow_error_set(error, EINVAL,
1469 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1471 "data cannot be empty");
1472 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1473 if (!mlx5_flow_ext_mreg_supported(dev))
1474 return rte_flow_error_set(error, ENOTSUP,
1475 RTE_FLOW_ERROR_TYPE_ITEM, item,
1476 "extended metadata register"
1477 " isn't supported");
1478 reg = flow_dv_get_metadata_reg(dev, attr, error);
1482 return rte_flow_error_set(error, ENOTSUP,
1483 RTE_FLOW_ERROR_TYPE_ITEM, item,
1487 nic_mask.data = priv->sh->dv_meta_mask;
1488 } else if (attr->transfer) {
1489 return rte_flow_error_set(error, ENOTSUP,
1490 RTE_FLOW_ERROR_TYPE_ITEM, item,
1491 "extended metadata feature "
1492 "should be enabled when "
1493 "meta item is requested "
1494 "with e-switch mode ");
1497 mask = &rte_flow_item_meta_mask;
1499 return rte_flow_error_set(error, EINVAL,
1500 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1501 "mask cannot be zero");
1503 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1504 (const uint8_t *)&nic_mask,
1505 sizeof(struct rte_flow_item_meta),
1506 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1511 * Validate TAG item.
1514 * Pointer to the rte_eth_dev structure.
1516 * Item specification.
1518 * Attributes of flow that includes this item.
1520 * Pointer to error structure.
1523 * 0 on success, a negative errno value otherwise and rte_errno is set.
1526 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1527 const struct rte_flow_item *item,
1528 const struct rte_flow_attr *attr __rte_unused,
1529 struct rte_flow_error *error)
1531 const struct rte_flow_item_tag *spec = item->spec;
1532 const struct rte_flow_item_tag *mask = item->mask;
1533 const struct rte_flow_item_tag nic_mask = {
1534 .data = RTE_BE32(UINT32_MAX),
1539 if (!mlx5_flow_ext_mreg_supported(dev))
1540 return rte_flow_error_set(error, ENOTSUP,
1541 RTE_FLOW_ERROR_TYPE_ITEM, item,
1542 "extensive metadata register"
1543 " isn't supported");
1545 return rte_flow_error_set(error, EINVAL,
1546 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1548 "data cannot be empty");
1550 mask = &rte_flow_item_tag_mask;
1552 return rte_flow_error_set(error, EINVAL,
1553 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1554 "mask cannot be zero");
1556 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1557 (const uint8_t *)&nic_mask,
1558 sizeof(struct rte_flow_item_tag),
1559 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1562 if (mask->index != 0xff)
1563 return rte_flow_error_set(error, EINVAL,
1564 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1565 "partial mask for tag index"
1566 " is not supported");
1567 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1570 MLX5_ASSERT(ret != REG_NON);
1575 * Validate vport item.
1578 * Pointer to the rte_eth_dev structure.
1580 * Item specification.
1582 * Attributes of flow that includes this item.
1583 * @param[in] item_flags
1584 * Bit-fields that holds the items detected until now.
1586 * Pointer to error structure.
1589 * 0 on success, a negative errno value otherwise and rte_errno is set.
1592 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1593 const struct rte_flow_item *item,
1594 const struct rte_flow_attr *attr,
1595 uint64_t item_flags,
1596 struct rte_flow_error *error)
1598 const struct rte_flow_item_port_id *spec = item->spec;
1599 const struct rte_flow_item_port_id *mask = item->mask;
1600 const struct rte_flow_item_port_id switch_mask = {
1603 struct mlx5_priv *esw_priv;
1604 struct mlx5_priv *dev_priv;
1607 if (!attr->transfer)
1608 return rte_flow_error_set(error, EINVAL,
1609 RTE_FLOW_ERROR_TYPE_ITEM,
1611 "match on port id is valid only"
1612 " when transfer flag is enabled");
1613 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1614 return rte_flow_error_set(error, ENOTSUP,
1615 RTE_FLOW_ERROR_TYPE_ITEM, item,
1616 "multiple source ports are not"
1619 mask = &switch_mask;
1620 if (mask->id != 0xffffffff)
1621 return rte_flow_error_set(error, ENOTSUP,
1622 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1624 "no support for partial mask on"
1626 ret = mlx5_flow_item_acceptable
1627 (item, (const uint8_t *)mask,
1628 (const uint8_t *)&rte_flow_item_port_id_mask,
1629 sizeof(struct rte_flow_item_port_id),
1630 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1635 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1637 return rte_flow_error_set(error, rte_errno,
1638 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1639 "failed to obtain E-Switch info for"
1641 dev_priv = mlx5_dev_to_eswitch_info(dev);
1643 return rte_flow_error_set(error, rte_errno,
1644 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1646 "failed to obtain E-Switch info");
1647 if (esw_priv->domain_id != dev_priv->domain_id)
1648 return rte_flow_error_set(error, EINVAL,
1649 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1650 "cannot match on a port from a"
1651 " different E-Switch");
1656 * Validate VLAN item.
1659 * Item specification.
1660 * @param[in] item_flags
1661 * Bit-fields that holds the items detected until now.
1663 * Ethernet device flow is being created on.
1665 * Pointer to error structure.
1668 * 0 on success, a negative errno value otherwise and rte_errno is set.
1671 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1672 uint64_t item_flags,
1673 struct rte_eth_dev *dev,
1674 struct rte_flow_error *error)
1676 const struct rte_flow_item_vlan *mask = item->mask;
1677 const struct rte_flow_item_vlan nic_mask = {
1678 .tci = RTE_BE16(UINT16_MAX),
1679 .inner_type = RTE_BE16(UINT16_MAX),
1682 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1684 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1685 MLX5_FLOW_LAYER_INNER_L4) :
1686 (MLX5_FLOW_LAYER_OUTER_L3 |
1687 MLX5_FLOW_LAYER_OUTER_L4);
1688 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1689 MLX5_FLOW_LAYER_OUTER_VLAN;
1691 if (item_flags & vlanm)
1692 return rte_flow_error_set(error, EINVAL,
1693 RTE_FLOW_ERROR_TYPE_ITEM, item,
1694 "multiple VLAN layers not supported");
1695 else if ((item_flags & l34m) != 0)
1696 return rte_flow_error_set(error, EINVAL,
1697 RTE_FLOW_ERROR_TYPE_ITEM, item,
1698 "VLAN cannot follow L3/L4 layer");
1700 mask = &rte_flow_item_vlan_mask;
1701 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1702 (const uint8_t *)&nic_mask,
1703 sizeof(struct rte_flow_item_vlan),
1704 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1707 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1708 struct mlx5_priv *priv = dev->data->dev_private;
1710 if (priv->vmwa_context) {
1712 * Non-NULL context means we have a virtual machine
1713 * and SR-IOV enabled, we have to create VLAN interface
1714 * to make hypervisor to setup E-Switch vport
1715 * context correctly. We avoid creating the multiple
1716 * VLAN interfaces, so we cannot support VLAN tag mask.
1718 return rte_flow_error_set(error, EINVAL,
1719 RTE_FLOW_ERROR_TYPE_ITEM,
1721 "VLAN tag mask is not"
1722 " supported in virtual"
1730 * GTP flags are contained in 1 byte of the format:
1731 * -------------------------------------------
1732 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1733 * |-----------------------------------------|
1734 * | value | Version | PT | Res | E | S | PN |
1735 * -------------------------------------------
1737 * Matching is supported only for GTP flags E, S, PN.
1739 #define MLX5_GTP_FLAGS_MASK 0x07
1742 * Validate GTP item.
1745 * Pointer to the rte_eth_dev structure.
1747 * Item specification.
1748 * @param[in] item_flags
1749 * Bit-fields that holds the items detected until now.
1751 * Pointer to error structure.
1754 * 0 on success, a negative errno value otherwise and rte_errno is set.
1757 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1758 const struct rte_flow_item *item,
1759 uint64_t item_flags,
1760 struct rte_flow_error *error)
1762 struct mlx5_priv *priv = dev->data->dev_private;
1763 const struct rte_flow_item_gtp *spec = item->spec;
1764 const struct rte_flow_item_gtp *mask = item->mask;
1765 const struct rte_flow_item_gtp nic_mask = {
1766 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1768 .teid = RTE_BE32(0xffffffff),
1771 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1772 return rte_flow_error_set(error, ENOTSUP,
1773 RTE_FLOW_ERROR_TYPE_ITEM, item,
1774 "GTP support is not enabled");
1775 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1776 return rte_flow_error_set(error, ENOTSUP,
1777 RTE_FLOW_ERROR_TYPE_ITEM, item,
1778 "multiple tunnel layers not"
1780 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1781 return rte_flow_error_set(error, EINVAL,
1782 RTE_FLOW_ERROR_TYPE_ITEM, item,
1783 "no outer UDP layer found");
1785 mask = &rte_flow_item_gtp_mask;
1786 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1787 return rte_flow_error_set(error, ENOTSUP,
1788 RTE_FLOW_ERROR_TYPE_ITEM, item,
1789 "Match is supported for GTP"
1791 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1792 (const uint8_t *)&nic_mask,
1793 sizeof(struct rte_flow_item_gtp),
1794 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1798 * Validate IPV4 item.
1799 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1800 * add specific validation of fragment_offset field,
1803 * Item specification.
1804 * @param[in] item_flags
1805 * Bit-fields that holds the items detected until now.
1807 * Pointer to error structure.
1810 * 0 on success, a negative errno value otherwise and rte_errno is set.
1813 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1814 uint64_t item_flags,
1816 uint16_t ether_type,
1817 struct rte_flow_error *error)
1820 const struct rte_flow_item_ipv4 *spec = item->spec;
1821 const struct rte_flow_item_ipv4 *last = item->last;
1822 const struct rte_flow_item_ipv4 *mask = item->mask;
1823 rte_be16_t fragment_offset_spec = 0;
1824 rte_be16_t fragment_offset_last = 0;
1825 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1827 .src_addr = RTE_BE32(0xffffffff),
1828 .dst_addr = RTE_BE32(0xffffffff),
1829 .type_of_service = 0xff,
1830 .fragment_offset = RTE_BE16(0xffff),
1831 .next_proto_id = 0xff,
1832 .time_to_live = 0xff,
1836 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1837 ether_type, &nic_ipv4_mask,
1838 MLX5_ITEM_RANGE_ACCEPTED, error);
1842 fragment_offset_spec = spec->hdr.fragment_offset &
1843 mask->hdr.fragment_offset;
1844 if (!fragment_offset_spec)
1847 * spec and mask are valid, enforce using full mask to make sure the
1848 * complete value is used correctly.
1850 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1851 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1854 item, "must use full mask for"
1855 " fragment_offset");
1857 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1858 * indicating this is 1st fragment of fragmented packet.
1859 * This is not yet supported in MLX5, return appropriate error message.
1861 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1862 return rte_flow_error_set(error, ENOTSUP,
1863 RTE_FLOW_ERROR_TYPE_ITEM, item,
1864 "match on first fragment not "
1866 if (fragment_offset_spec && !last)
1867 return rte_flow_error_set(error, ENOTSUP,
1868 RTE_FLOW_ERROR_TYPE_ITEM, item,
1869 "specified value not supported");
1870 /* spec and last are valid, validate the specified range. */
1871 fragment_offset_last = last->hdr.fragment_offset &
1872 mask->hdr.fragment_offset;
1874 * Match on fragment_offset spec 0x2001 and last 0x3fff
1875 * means MF is 1 and frag-offset is > 0.
1876 * This packet is fragment 2nd and onward, excluding last.
1877 * This is not yet supported in MLX5, return appropriate
1880 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1881 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1882 return rte_flow_error_set(error, ENOTSUP,
1883 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1884 last, "match on following "
1885 "fragments not supported");
1887 * Match on fragment_offset spec 0x0001 and last 0x1fff
1888 * means MF is 0 and frag-offset is > 0.
1889 * This packet is last fragment of fragmented packet.
1890 * This is not yet supported in MLX5, return appropriate
1893 if (fragment_offset_spec == RTE_BE16(1) &&
1894 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1895 return rte_flow_error_set(error, ENOTSUP,
1896 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1897 last, "match on last "
1898 "fragment not supported");
1900 * Match on fragment_offset spec 0x0001 and last 0x3fff
1901 * means MF and/or frag-offset is not 0.
1902 * This is a fragmented packet.
1903 * Other range values are invalid and rejected.
1905 if (!(fragment_offset_spec == RTE_BE16(1) &&
1906 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1907 return rte_flow_error_set(error, ENOTSUP,
1908 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1909 "specified range not supported");
1914 * Validate IPV6 fragment extension item.
1917 * Item specification.
1918 * @param[in] item_flags
1919 * Bit-fields that holds the items detected until now.
1921 * Pointer to error structure.
1924 * 0 on success, a negative errno value otherwise and rte_errno is set.
1927 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1928 uint64_t item_flags,
1929 struct rte_flow_error *error)
1931 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1932 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1933 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1934 rte_be16_t frag_data_spec = 0;
1935 rte_be16_t frag_data_last = 0;
1936 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1937 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1938 MLX5_FLOW_LAYER_OUTER_L4;
1940 struct rte_flow_item_ipv6_frag_ext nic_mask = {
1942 .next_header = 0xff,
1943 .frag_data = RTE_BE16(0xffff),
1947 if (item_flags & l4m)
1948 return rte_flow_error_set(error, EINVAL,
1949 RTE_FLOW_ERROR_TYPE_ITEM, item,
1950 "ipv6 fragment extension item cannot "
1952 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1953 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1954 return rte_flow_error_set(error, EINVAL,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "ipv6 fragment extension item must "
1957 "follow ipv6 item");
1959 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1960 if (!frag_data_spec)
1963 * spec and mask are valid, enforce using full mask to make sure the
1964 * complete value is used correctly.
1966 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1967 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1968 return rte_flow_error_set(error, EINVAL,
1969 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1970 item, "must use full mask for"
1973 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1974 * This is 1st fragment of fragmented packet.
1976 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1977 return rte_flow_error_set(error, ENOTSUP,
1978 RTE_FLOW_ERROR_TYPE_ITEM, item,
1979 "match on first fragment not "
1981 if (frag_data_spec && !last)
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ITEM, item,
1984 "specified value not supported");
1985 ret = mlx5_flow_item_acceptable
1986 (item, (const uint8_t *)mask,
1987 (const uint8_t *)&nic_mask,
1988 sizeof(struct rte_flow_item_ipv6_frag_ext),
1989 MLX5_ITEM_RANGE_ACCEPTED, error);
1992 /* spec and last are valid, validate the specified range. */
1993 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1995 * Match on frag_data spec 0x0009 and last 0xfff9
1996 * means M is 1 and frag-offset is > 0.
1997 * This packet is fragment 2nd and onward, excluding last.
1998 * This is not yet supported in MLX5, return appropriate
2001 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2002 RTE_IPV6_EHDR_MF_MASK) &&
2003 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2004 return rte_flow_error_set(error, ENOTSUP,
2005 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2006 last, "match on following "
2007 "fragments not supported");
2009 * Match on frag_data spec 0x0008 and last 0xfff8
2010 * means M is 0 and frag-offset is > 0.
2011 * This packet is last fragment of fragmented packet.
2012 * This is not yet supported in MLX5, return appropriate
2015 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2016 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2017 return rte_flow_error_set(error, ENOTSUP,
2018 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2019 last, "match on last "
2020 "fragment not supported");
2021 /* Other range values are invalid and rejected. */
2022 return rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2024 "specified range not supported");
2028 * Validate the pop VLAN action.
2031 * Pointer to the rte_eth_dev structure.
2032 * @param[in] action_flags
2033 * Holds the actions detected until now.
2035 * Pointer to the pop vlan action.
2036 * @param[in] item_flags
2037 * The items found in this flow rule.
2039 * Pointer to flow attributes.
2041 * Pointer to error structure.
2044 * 0 on success, a negative errno value otherwise and rte_errno is set.
2047 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2048 uint64_t action_flags,
2049 const struct rte_flow_action *action,
2050 uint64_t item_flags,
2051 const struct rte_flow_attr *attr,
2052 struct rte_flow_error *error)
2054 const struct mlx5_priv *priv = dev->data->dev_private;
2058 if (!priv->sh->pop_vlan_action)
2059 return rte_flow_error_set(error, ENOTSUP,
2060 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2062 "pop vlan action is not supported");
2064 return rte_flow_error_set(error, ENOTSUP,
2065 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2067 "pop vlan action not supported for "
2069 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2070 return rte_flow_error_set(error, ENOTSUP,
2071 RTE_FLOW_ERROR_TYPE_ACTION, action,
2072 "no support for multiple VLAN "
2074 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2075 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2076 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2077 return rte_flow_error_set(error, ENOTSUP,
2078 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2080 "cannot pop vlan after decap without "
2081 "match on inner vlan in the flow");
2082 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2083 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2084 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2085 return rte_flow_error_set(error, ENOTSUP,
2086 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2088 "cannot pop vlan without a "
2089 "match on (outer) vlan in the flow");
2090 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2091 return rte_flow_error_set(error, EINVAL,
2092 RTE_FLOW_ERROR_TYPE_ACTION, action,
2093 "wrong action order, port_id should "
2094 "be after pop VLAN action");
2095 if (!attr->transfer && priv->representor)
2096 return rte_flow_error_set(error, ENOTSUP,
2097 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2098 "pop vlan action for VF representor "
2099 "not supported on NIC table");
2104 * Get VLAN default info from vlan match info.
2107 * the list of item specifications.
2109 * pointer VLAN info to fill to.
2112 * 0 on success, a negative errno value otherwise and rte_errno is set.
2115 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2116 struct rte_vlan_hdr *vlan)
2118 const struct rte_flow_item_vlan nic_mask = {
2119 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2120 MLX5DV_FLOW_VLAN_VID_MASK),
2121 .inner_type = RTE_BE16(0xffff),
2126 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2127 int type = items->type;
2129 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2130 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2133 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2134 const struct rte_flow_item_vlan *vlan_m = items->mask;
2135 const struct rte_flow_item_vlan *vlan_v = items->spec;
2137 /* If VLAN item in pattern doesn't contain data, return here. */
2142 /* Only full match values are accepted */
2143 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2144 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2145 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2147 rte_be_to_cpu_16(vlan_v->tci &
2148 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2150 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2151 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2152 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2154 rte_be_to_cpu_16(vlan_v->tci &
2155 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2157 if (vlan_m->inner_type == nic_mask.inner_type)
2158 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2159 vlan_m->inner_type);
2164 * Validate the push VLAN action.
2167 * Pointer to the rte_eth_dev structure.
2168 * @param[in] action_flags
2169 * Holds the actions detected until now.
2170 * @param[in] item_flags
2171 * The items found in this flow rule.
2173 * Pointer to the action structure.
2175 * Pointer to flow attributes
2177 * Pointer to error structure.
2180 * 0 on success, a negative errno value otherwise and rte_errno is set.
2183 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2184 uint64_t action_flags,
2185 const struct rte_flow_item_vlan *vlan_m,
2186 const struct rte_flow_action *action,
2187 const struct rte_flow_attr *attr,
2188 struct rte_flow_error *error)
2190 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2191 const struct mlx5_priv *priv = dev->data->dev_private;
2193 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2194 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "invalid vlan ethertype");
2198 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ACTION, action,
2201 "wrong action order, port_id should "
2202 "be after push VLAN");
2203 if (!attr->transfer && priv->representor)
2204 return rte_flow_error_set(error, ENOTSUP,
2205 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2206 "push vlan action for VF representor "
2207 "not supported on NIC table");
2209 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2210 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2211 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2212 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2213 !(mlx5_flow_find_action
2214 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2215 return rte_flow_error_set(error, EINVAL,
2216 RTE_FLOW_ERROR_TYPE_ACTION, action,
2217 "not full match mask on VLAN PCP and "
2218 "there is no of_set_vlan_pcp action, "
2219 "push VLAN action cannot figure out "
2222 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2223 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2224 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2225 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2226 !(mlx5_flow_find_action
2227 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2228 return rte_flow_error_set(error, EINVAL,
2229 RTE_FLOW_ERROR_TYPE_ACTION, action,
2230 "not full match mask on VLAN VID and "
2231 "there is no of_set_vlan_vid action, "
2232 "push VLAN action cannot figure out "
2239 * Validate the set VLAN PCP.
2241 * @param[in] action_flags
2242 * Holds the actions detected until now.
2243 * @param[in] actions
2244 * Pointer to the list of actions remaining in the flow rule.
2246 * Pointer to error structure.
2249 * 0 on success, a negative errno value otherwise and rte_errno is set.
2252 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2253 const struct rte_flow_action actions[],
2254 struct rte_flow_error *error)
2256 const struct rte_flow_action *action = actions;
2257 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2259 if (conf->vlan_pcp > 7)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ACTION, action,
2262 "VLAN PCP value is too big");
2263 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2264 return rte_flow_error_set(error, ENOTSUP,
2265 RTE_FLOW_ERROR_TYPE_ACTION, action,
2266 "set VLAN PCP action must follow "
2267 "the push VLAN action");
2268 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2269 return rte_flow_error_set(error, ENOTSUP,
2270 RTE_FLOW_ERROR_TYPE_ACTION, action,
2271 "Multiple VLAN PCP modification are "
2273 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2274 return rte_flow_error_set(error, EINVAL,
2275 RTE_FLOW_ERROR_TYPE_ACTION, action,
2276 "wrong action order, port_id should "
2277 "be after set VLAN PCP");
2282 * Validate the set VLAN VID.
2284 * @param[in] item_flags
2285 * Holds the items detected in this rule.
2286 * @param[in] action_flags
2287 * Holds the actions detected until now.
2288 * @param[in] actions
2289 * Pointer to the list of actions remaining in the flow rule.
2291 * Pointer to error structure.
2294 * 0 on success, a negative errno value otherwise and rte_errno is set.
2297 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2298 uint64_t action_flags,
2299 const struct rte_flow_action actions[],
2300 struct rte_flow_error *error)
2302 const struct rte_flow_action *action = actions;
2303 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2305 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2306 return rte_flow_error_set(error, EINVAL,
2307 RTE_FLOW_ERROR_TYPE_ACTION, action,
2308 "VLAN VID value is too big");
2309 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2310 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2311 return rte_flow_error_set(error, ENOTSUP,
2312 RTE_FLOW_ERROR_TYPE_ACTION, action,
2313 "set VLAN VID action must follow push"
2314 " VLAN action or match on VLAN item");
2315 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2316 return rte_flow_error_set(error, ENOTSUP,
2317 RTE_FLOW_ERROR_TYPE_ACTION, action,
2318 "Multiple VLAN VID modifications are "
2320 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2321 return rte_flow_error_set(error, EINVAL,
2322 RTE_FLOW_ERROR_TYPE_ACTION, action,
2323 "wrong action order, port_id should "
2324 "be after set VLAN VID");
2329 * Validate the FLAG action.
2332 * Pointer to the rte_eth_dev structure.
2333 * @param[in] action_flags
2334 * Holds the actions detected until now.
2336 * Pointer to flow attributes
2338 * Pointer to error structure.
2341 * 0 on success, a negative errno value otherwise and rte_errno is set.
2344 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2345 uint64_t action_flags,
2346 const struct rte_flow_attr *attr,
2347 struct rte_flow_error *error)
2349 struct mlx5_priv *priv = dev->data->dev_private;
2350 struct mlx5_dev_config *config = &priv->config;
2353 /* Fall back if no extended metadata register support. */
2354 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2355 return mlx5_flow_validate_action_flag(action_flags, attr,
2357 /* Extensive metadata mode requires registers. */
2358 if (!mlx5_flow_ext_mreg_supported(dev))
2359 return rte_flow_error_set(error, ENOTSUP,
2360 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2361 "no metadata registers "
2362 "to support flag action");
2363 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2364 return rte_flow_error_set(error, ENOTSUP,
2365 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2366 "extended metadata register"
2367 " isn't available");
2368 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2371 MLX5_ASSERT(ret > 0);
2372 if (action_flags & MLX5_FLOW_ACTION_MARK)
2373 return rte_flow_error_set(error, EINVAL,
2374 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2375 "can't mark and flag in same flow");
2376 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2377 return rte_flow_error_set(error, EINVAL,
2378 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2380 " actions in same flow");
2385 * Validate MARK action.
2388 * Pointer to the rte_eth_dev structure.
2390 * Pointer to action.
2391 * @param[in] action_flags
2392 * Holds the actions detected until now.
2394 * Pointer to flow attributes
2396 * Pointer to error structure.
2399 * 0 on success, a negative errno value otherwise and rte_errno is set.
2402 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2403 const struct rte_flow_action *action,
2404 uint64_t action_flags,
2405 const struct rte_flow_attr *attr,
2406 struct rte_flow_error *error)
2408 struct mlx5_priv *priv = dev->data->dev_private;
2409 struct mlx5_dev_config *config = &priv->config;
2410 const struct rte_flow_action_mark *mark = action->conf;
2413 /* Fall back if no extended metadata register support. */
2414 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2415 return mlx5_flow_validate_action_mark(action, action_flags,
2417 /* Extensive metadata mode requires registers. */
2418 if (!mlx5_flow_ext_mreg_supported(dev))
2419 return rte_flow_error_set(error, ENOTSUP,
2420 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2421 "no metadata registers "
2422 "to support mark action");
2423 if (!priv->sh->dv_mark_mask)
2424 return rte_flow_error_set(error, ENOTSUP,
2425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2426 "extended metadata register"
2427 " isn't available");
2428 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2431 MLX5_ASSERT(ret > 0);
2433 return rte_flow_error_set(error, EINVAL,
2434 RTE_FLOW_ERROR_TYPE_ACTION, action,
2435 "configuration cannot be null");
2436 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2437 return rte_flow_error_set(error, EINVAL,
2438 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2440 "mark id exceeds the limit");
2441 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2442 return rte_flow_error_set(error, EINVAL,
2443 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2444 "can't flag and mark in same flow");
2445 if (action_flags & MLX5_FLOW_ACTION_MARK)
2446 return rte_flow_error_set(error, EINVAL,
2447 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2448 "can't have 2 mark actions in same"
2454 * Validate SET_META action.
2457 * Pointer to the rte_eth_dev structure.
2459 * Pointer to the action structure.
2460 * @param[in] action_flags
2461 * Holds the actions detected until now.
2463 * Pointer to flow attributes
2465 * Pointer to error structure.
2468 * 0 on success, a negative errno value otherwise and rte_errno is set.
2471 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2472 const struct rte_flow_action *action,
2473 uint64_t action_flags __rte_unused,
2474 const struct rte_flow_attr *attr,
2475 struct rte_flow_error *error)
2477 const struct rte_flow_action_set_meta *conf;
2478 uint32_t nic_mask = UINT32_MAX;
2481 if (!mlx5_flow_ext_mreg_supported(dev))
2482 return rte_flow_error_set(error, ENOTSUP,
2483 RTE_FLOW_ERROR_TYPE_ACTION, action,
2484 "extended metadata register"
2485 " isn't supported");
2486 reg = flow_dv_get_metadata_reg(dev, attr, error);
2489 if (reg != REG_A && reg != REG_B) {
2490 struct mlx5_priv *priv = dev->data->dev_private;
2492 nic_mask = priv->sh->dv_meta_mask;
2494 if (!(action->conf))
2495 return rte_flow_error_set(error, EINVAL,
2496 RTE_FLOW_ERROR_TYPE_ACTION, action,
2497 "configuration cannot be null");
2498 conf = (const struct rte_flow_action_set_meta *)action->conf;
2500 return rte_flow_error_set(error, EINVAL,
2501 RTE_FLOW_ERROR_TYPE_ACTION, action,
2502 "zero mask doesn't have any effect");
2503 if (conf->mask & ~nic_mask)
2504 return rte_flow_error_set(error, EINVAL,
2505 RTE_FLOW_ERROR_TYPE_ACTION, action,
2506 "meta data must be within reg C0");
2511 * Validate SET_TAG action.
2514 * Pointer to the rte_eth_dev structure.
2516 * Pointer to the action structure.
2517 * @param[in] action_flags
2518 * Holds the actions detected until now.
2520 * Pointer to flow attributes
2522 * Pointer to error structure.
2525 * 0 on success, a negative errno value otherwise and rte_errno is set.
2528 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2529 const struct rte_flow_action *action,
2530 uint64_t action_flags,
2531 const struct rte_flow_attr *attr,
2532 struct rte_flow_error *error)
2534 const struct rte_flow_action_set_tag *conf;
2535 const uint64_t terminal_action_flags =
2536 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2537 MLX5_FLOW_ACTION_RSS;
2540 if (!mlx5_flow_ext_mreg_supported(dev))
2541 return rte_flow_error_set(error, ENOTSUP,
2542 RTE_FLOW_ERROR_TYPE_ACTION, action,
2543 "extensive metadata register"
2544 " isn't supported");
2545 if (!(action->conf))
2546 return rte_flow_error_set(error, EINVAL,
2547 RTE_FLOW_ERROR_TYPE_ACTION, action,
2548 "configuration cannot be null");
2549 conf = (const struct rte_flow_action_set_tag *)action->conf;
2551 return rte_flow_error_set(error, EINVAL,
2552 RTE_FLOW_ERROR_TYPE_ACTION, action,
2553 "zero mask doesn't have any effect");
2554 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2557 if (!attr->transfer && attr->ingress &&
2558 (action_flags & terminal_action_flags))
2559 return rte_flow_error_set(error, EINVAL,
2560 RTE_FLOW_ERROR_TYPE_ACTION, action,
2561 "set_tag has no effect"
2562 " with terminal actions");
2567 * Validate count action.
2570 * Pointer to rte_eth_dev structure.
2572 * Pointer to error structure.
2575 * 0 on success, a negative errno value otherwise and rte_errno is set.
2578 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2579 struct rte_flow_error *error)
2581 struct mlx5_priv *priv = dev->data->dev_private;
2583 if (!priv->config.devx)
2585 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2589 return rte_flow_error_set
2591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2593 "count action not supported");
2597 * Validate the L2 encap action.
2600 * Pointer to the rte_eth_dev structure.
2601 * @param[in] action_flags
2602 * Holds the actions detected until now.
2604 * Pointer to the action structure.
2606 * Pointer to flow attributes.
2608 * Pointer to error structure.
2611 * 0 on success, a negative errno value otherwise and rte_errno is set.
2614 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2615 uint64_t action_flags,
2616 const struct rte_flow_action *action,
2617 const struct rte_flow_attr *attr,
2618 struct rte_flow_error *error)
2620 const struct mlx5_priv *priv = dev->data->dev_private;
2622 if (!(action->conf))
2623 return rte_flow_error_set(error, EINVAL,
2624 RTE_FLOW_ERROR_TYPE_ACTION, action,
2625 "configuration cannot be null");
2626 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2627 return rte_flow_error_set(error, EINVAL,
2628 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2629 "can only have a single encap action "
2631 if (!attr->transfer && priv->representor)
2632 return rte_flow_error_set(error, ENOTSUP,
2633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2634 "encap action for VF representor "
2635 "not supported on NIC table");
2640 * Validate a decap action.
2643 * Pointer to the rte_eth_dev structure.
2644 * @param[in] action_flags
2645 * Holds the actions detected until now.
2647 * Pointer to flow attributes
2649 * Pointer to error structure.
2652 * 0 on success, a negative errno value otherwise and rte_errno is set.
2655 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2656 uint64_t action_flags,
2657 const struct rte_flow_attr *attr,
2658 struct rte_flow_error *error)
2660 const struct mlx5_priv *priv = dev->data->dev_private;
2662 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2663 !priv->config.decap_en)
2664 return rte_flow_error_set(error, ENOTSUP,
2665 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2666 "decap is not enabled");
2667 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2668 return rte_flow_error_set(error, ENOTSUP,
2669 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2671 MLX5_FLOW_ACTION_DECAP ? "can only "
2672 "have a single decap action" : "decap "
2673 "after encap is not supported");
2674 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2675 return rte_flow_error_set(error, EINVAL,
2676 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2677 "can't have decap action after"
2680 return rte_flow_error_set(error, ENOTSUP,
2681 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2683 "decap action not supported for "
2685 if (!attr->transfer && priv->representor)
2686 return rte_flow_error_set(error, ENOTSUP,
2687 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2688 "decap action for VF representor "
2689 "not supported on NIC table");
2693 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2696 * Validate the raw encap and decap actions.
2699 * Pointer to the rte_eth_dev structure.
2701 * Pointer to the decap action.
2703 * Pointer to the encap action.
2705 * Pointer to flow attributes
2706 * @param[in/out] action_flags
2707 * Holds the actions detected until now.
2708 * @param[out] actions_n
2709 * pointer to the number of actions counter.
2711 * Pointer to error structure.
2714 * 0 on success, a negative errno value otherwise and rte_errno is set.
2717 flow_dv_validate_action_raw_encap_decap
2718 (struct rte_eth_dev *dev,
2719 const struct rte_flow_action_raw_decap *decap,
2720 const struct rte_flow_action_raw_encap *encap,
2721 const struct rte_flow_attr *attr, uint64_t *action_flags,
2722 int *actions_n, struct rte_flow_error *error)
2724 const struct mlx5_priv *priv = dev->data->dev_private;
2727 if (encap && (!encap->size || !encap->data))
2728 return rte_flow_error_set(error, EINVAL,
2729 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2730 "raw encap data cannot be empty");
2731 if (decap && encap) {
2732 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2733 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2736 else if (encap->size <=
2737 MLX5_ENCAPSULATION_DECISION_SIZE &&
2739 MLX5_ENCAPSULATION_DECISION_SIZE)
2742 else if (encap->size >
2743 MLX5_ENCAPSULATION_DECISION_SIZE &&
2745 MLX5_ENCAPSULATION_DECISION_SIZE)
2746 /* 2 L2 actions: encap and decap. */
2749 return rte_flow_error_set(error,
2751 RTE_FLOW_ERROR_TYPE_ACTION,
2752 NULL, "unsupported too small "
2753 "raw decap and too small raw "
2754 "encap combination");
2757 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2761 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2765 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2766 return rte_flow_error_set(error, ENOTSUP,
2767 RTE_FLOW_ERROR_TYPE_ACTION,
2769 "small raw encap size");
2770 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2771 return rte_flow_error_set(error, EINVAL,
2772 RTE_FLOW_ERROR_TYPE_ACTION,
2774 "more than one encap action");
2775 if (!attr->transfer && priv->representor)
2776 return rte_flow_error_set
2778 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2779 "encap action for VF representor "
2780 "not supported on NIC table");
2781 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2788 * Match encap_decap resource.
2791 * Pointer to exist resource entry object.
2793 * Pointer to new encap_decap resource.
2796 * 0 on matching, -1 otherwise.
2799 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2801 struct mlx5_flow_dv_encap_decap_resource *resource;
2802 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2804 resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2805 cache_resource = container_of(entry,
2806 struct mlx5_flow_dv_encap_decap_resource,
2808 if (resource->entry.key == cache_resource->entry.key &&
2809 resource->reformat_type == cache_resource->reformat_type &&
2810 resource->ft_type == cache_resource->ft_type &&
2811 resource->flags == cache_resource->flags &&
2812 resource->size == cache_resource->size &&
2813 !memcmp((const void *)resource->buf,
2814 (const void *)cache_resource->buf,
2821 * Find existing encap/decap resource or create and register a new one.
2823 * @param[in, out] dev
2824 * Pointer to rte_eth_dev structure.
2825 * @param[in, out] resource
2826 * Pointer to encap/decap resource.
2827 * @parm[in, out] dev_flow
2828 * Pointer to the dev_flow.
2830 * pointer to error structure.
2833 * 0 on success otherwise -errno and errno is set.
2836 flow_dv_encap_decap_resource_register
2837 (struct rte_eth_dev *dev,
2838 struct mlx5_flow_dv_encap_decap_resource *resource,
2839 struct mlx5_flow *dev_flow,
2840 struct rte_flow_error *error)
2842 struct mlx5_priv *priv = dev->data->dev_private;
2843 struct mlx5_dev_ctx_shared *sh = priv->sh;
2844 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2845 struct mlx5dv_dr_domain *domain;
2846 struct mlx5_hlist_entry *entry;
2847 union mlx5_flow_encap_decap_key encap_decap_key = {
2849 .ft_type = resource->ft_type,
2850 .refmt_type = resource->reformat_type,
2851 .buf_size = resource->size,
2852 .table_level = !!dev_flow->dv.group,
2858 resource->flags = dev_flow->dv.group ? 0 : 1;
2859 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2860 domain = sh->fdb_domain;
2861 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2862 domain = sh->rx_domain;
2864 domain = sh->tx_domain;
2865 encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2867 resource->entry.key = encap_decap_key.v64;
2868 /* Lookup a matching resource from cache. */
2869 entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2870 flow_dv_encap_decap_resource_match,
2873 cache_resource = container_of(entry,
2874 struct mlx5_flow_dv_encap_decap_resource, entry);
2875 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2876 (void *)cache_resource,
2877 __atomic_load_n(&cache_resource->refcnt,
2879 __atomic_fetch_add(&cache_resource->refcnt, 1,
2881 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2882 dev_flow->dv.encap_decap = cache_resource;
2885 /* Register new encap/decap resource. */
2886 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2887 &dev_flow->handle->dvh.rix_encap_decap);
2888 if (!cache_resource)
2889 return rte_flow_error_set(error, ENOMEM,
2890 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2891 "cannot allocate resource memory");
2892 *cache_resource = *resource;
2893 cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2894 ret = mlx5_flow_os_create_flow_action_packet_reformat
2895 (sh->ctx, domain, cache_resource,
2896 &cache_resource->action);
2898 mlx5_free(cache_resource);
2899 return rte_flow_error_set(error, ENOMEM,
2900 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2901 NULL, "cannot create action");
2903 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
2904 if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2905 flow_dv_encap_decap_resource_match,
2906 (void *)cache_resource)) {
2907 claim_zero(mlx5_flow_os_destroy_flow_action
2908 (cache_resource->action));
2909 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2910 cache_resource->idx);
2911 return rte_flow_error_set(error, EEXIST,
2912 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2913 NULL, "action exist");
2915 dev_flow->dv.encap_decap = cache_resource;
2916 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2917 (void *)cache_resource,
2918 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
2923 * Find existing table jump resource or create and register a new one.
2925 * @param[in, out] dev
2926 * Pointer to rte_eth_dev structure.
2927 * @param[in, out] tbl
2928 * Pointer to flow table resource.
2929 * @parm[in, out] dev_flow
2930 * Pointer to the dev_flow.
2932 * pointer to error structure.
2935 * 0 on success otherwise -errno and errno is set.
2938 flow_dv_jump_tbl_resource_register
2939 (struct rte_eth_dev *dev __rte_unused,
2940 struct mlx5_flow_tbl_resource *tbl,
2941 struct mlx5_flow *dev_flow,
2942 struct rte_flow_error *error)
2944 struct mlx5_flow_tbl_data_entry *tbl_data =
2945 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2949 cnt = __atomic_load_n(&tbl_data->jump.refcnt, __ATOMIC_ACQUIRE);
2951 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2952 (tbl->obj, &tbl_data->jump.action);
2954 return rte_flow_error_set(error, ENOMEM,
2955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2956 NULL, "cannot create jump action");
2957 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2958 (void *)&tbl_data->jump, cnt);
2960 /* old jump should not make the table ref++. */
2961 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2962 MLX5_ASSERT(tbl_data->jump.action);
2963 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2964 (void *)&tbl_data->jump, cnt);
2966 __atomic_fetch_add(&tbl_data->jump.refcnt, 1, __ATOMIC_RELEASE);
2967 dev_flow->handle->rix_jump = tbl_data->idx;
2968 dev_flow->dv.jump = &tbl_data->jump;
2973 * Find existing default miss resource or create and register a new one.
2975 * @param[in, out] dev
2976 * Pointer to rte_eth_dev structure.
2978 * pointer to error structure.
2981 * 0 on success otherwise -errno and errno is set.
2984 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2985 struct rte_flow_error *error)
2987 struct mlx5_priv *priv = dev->data->dev_private;
2988 struct mlx5_dev_ctx_shared *sh = priv->sh;
2989 struct mlx5_flow_default_miss_resource *cache_resource =
2991 int cnt = __atomic_load_n(&cache_resource->refcnt, __ATOMIC_ACQUIRE);
2994 MLX5_ASSERT(cache_resource->action);
2995 cache_resource->action =
2996 mlx5_glue->dr_create_flow_action_default_miss();
2997 if (!cache_resource->action)
2998 return rte_flow_error_set(error, ENOMEM,
2999 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3000 "cannot create default miss action");
3001 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
3002 (void *)cache_resource->action, cnt);
3004 __atomic_fetch_add(&cache_resource->refcnt, 1, __ATOMIC_RELEASE);
3009 * Find existing table port ID resource or create and register a new one.
3011 * @param[in, out] dev
3012 * Pointer to rte_eth_dev structure.
3013 * @param[in, out] resource
3014 * Pointer to port ID action resource.
3015 * @parm[in, out] dev_flow
3016 * Pointer to the dev_flow.
3018 * pointer to error structure.
3021 * 0 on success otherwise -errno and errno is set.
3024 flow_dv_port_id_action_resource_register
3025 (struct rte_eth_dev *dev,
3026 struct mlx5_flow_dv_port_id_action_resource *resource,
3027 struct mlx5_flow *dev_flow,
3028 struct rte_flow_error *error)
3030 struct mlx5_priv *priv = dev->data->dev_private;
3031 struct mlx5_dev_ctx_shared *sh = priv->sh;
3032 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
3036 /* Lookup a matching resource from cache. */
3037 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
3038 idx, cache_resource, next) {
3039 if (resource->port_id == cache_resource->port_id) {
3040 DRV_LOG(DEBUG, "port id action resource resource %p: "
3042 (void *)cache_resource,
3043 __atomic_load_n(&cache_resource->refcnt,
3045 __atomic_fetch_add(&cache_resource->refcnt, 1,
3047 dev_flow->handle->rix_port_id_action = idx;
3048 dev_flow->dv.port_id_action = cache_resource;
3052 /* Register new port id action resource. */
3053 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
3054 &dev_flow->handle->rix_port_id_action);
3055 if (!cache_resource)
3056 return rte_flow_error_set(error, ENOMEM,
3057 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3058 "cannot allocate resource memory");
3059 *cache_resource = *resource;
3060 ret = mlx5_flow_os_create_flow_action_dest_port
3061 (priv->sh->fdb_domain, resource->port_id,
3062 &cache_resource->action);
3064 mlx5_free(cache_resource);
3065 return rte_flow_error_set(error, ENOMEM,
3066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3067 NULL, "cannot create action");
3069 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3070 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3071 dev_flow->handle->rix_port_id_action, cache_resource,
3073 dev_flow->dv.port_id_action = cache_resource;
3074 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3075 (void *)cache_resource,
3076 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3081 * Find existing push vlan resource or create and register a new one.
3083 * @param [in, out] dev
3084 * Pointer to rte_eth_dev structure.
3085 * @param[in, out] resource
3086 * Pointer to port ID action resource.
3087 * @parm[in, out] dev_flow
3088 * Pointer to the dev_flow.
3090 * pointer to error structure.
3093 * 0 on success otherwise -errno and errno is set.
3096 flow_dv_push_vlan_action_resource_register
3097 (struct rte_eth_dev *dev,
3098 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3099 struct mlx5_flow *dev_flow,
3100 struct rte_flow_error *error)
3102 struct mlx5_priv *priv = dev->data->dev_private;
3103 struct mlx5_dev_ctx_shared *sh = priv->sh;
3104 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3105 struct mlx5dv_dr_domain *domain;
3109 /* Lookup a matching resource from cache. */
3110 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3111 sh->push_vlan_action_list, idx, cache_resource, next) {
3112 if (resource->vlan_tag == cache_resource->vlan_tag &&
3113 resource->ft_type == cache_resource->ft_type) {
3114 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3116 (void *)cache_resource,
3117 __atomic_load_n(&cache_resource->refcnt,
3119 __atomic_fetch_add(&cache_resource->refcnt, 1,
3121 dev_flow->handle->dvh.rix_push_vlan = idx;
3122 dev_flow->dv.push_vlan_res = cache_resource;
3126 /* Register new push_vlan action resource. */
3127 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3128 &dev_flow->handle->dvh.rix_push_vlan);
3129 if (!cache_resource)
3130 return rte_flow_error_set(error, ENOMEM,
3131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3132 "cannot allocate resource memory");
3133 *cache_resource = *resource;
3134 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3135 domain = sh->fdb_domain;
3136 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3137 domain = sh->rx_domain;
3139 domain = sh->tx_domain;
3140 ret = mlx5_flow_os_create_flow_action_push_vlan
3141 (domain, resource->vlan_tag,
3142 &cache_resource->action);
3144 mlx5_free(cache_resource);
3145 return rte_flow_error_set(error, ENOMEM,
3146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3147 NULL, "cannot create action");
3149 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3150 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3151 &sh->push_vlan_action_list,
3152 dev_flow->handle->dvh.rix_push_vlan,
3153 cache_resource, next);
3154 dev_flow->dv.push_vlan_res = cache_resource;
3155 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3156 (void *)cache_resource,
3157 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3161 * Get the size of specific rte_flow_item_type hdr size
3163 * @param[in] item_type
3164 * Tested rte_flow_item_type.
3167 * sizeof struct item_type, 0 if void or irrelevant.
3170 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3174 switch (item_type) {
3175 case RTE_FLOW_ITEM_TYPE_ETH:
3176 retval = sizeof(struct rte_ether_hdr);
3178 case RTE_FLOW_ITEM_TYPE_VLAN:
3179 retval = sizeof(struct rte_vlan_hdr);
3181 case RTE_FLOW_ITEM_TYPE_IPV4:
3182 retval = sizeof(struct rte_ipv4_hdr);
3184 case RTE_FLOW_ITEM_TYPE_IPV6:
3185 retval = sizeof(struct rte_ipv6_hdr);
3187 case RTE_FLOW_ITEM_TYPE_UDP:
3188 retval = sizeof(struct rte_udp_hdr);
3190 case RTE_FLOW_ITEM_TYPE_TCP:
3191 retval = sizeof(struct rte_tcp_hdr);
3193 case RTE_FLOW_ITEM_TYPE_VXLAN:
3194 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3195 retval = sizeof(struct rte_vxlan_hdr);
3197 case RTE_FLOW_ITEM_TYPE_GRE:
3198 case RTE_FLOW_ITEM_TYPE_NVGRE:
3199 retval = sizeof(struct rte_gre_hdr);
3201 case RTE_FLOW_ITEM_TYPE_MPLS:
3202 retval = sizeof(struct rte_mpls_hdr);
3204 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3212 #define MLX5_ENCAP_IPV4_VERSION 0x40
3213 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3214 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3215 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3216 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3217 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3218 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3221 * Convert the encap action data from list of rte_flow_item to raw buffer
3224 * Pointer to rte_flow_item objects list.
3226 * Pointer to the output buffer.
3228 * Pointer to the output buffer size.
3230 * Pointer to the error structure.
3233 * 0 on success, a negative errno value otherwise and rte_errno is set.
3236 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3237 size_t *size, struct rte_flow_error *error)
3239 struct rte_ether_hdr *eth = NULL;
3240 struct rte_vlan_hdr *vlan = NULL;
3241 struct rte_ipv4_hdr *ipv4 = NULL;
3242 struct rte_ipv6_hdr *ipv6 = NULL;
3243 struct rte_udp_hdr *udp = NULL;
3244 struct rte_vxlan_hdr *vxlan = NULL;
3245 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3246 struct rte_gre_hdr *gre = NULL;
3248 size_t temp_size = 0;
3251 return rte_flow_error_set(error, EINVAL,
3252 RTE_FLOW_ERROR_TYPE_ACTION,
3253 NULL, "invalid empty data");
3254 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3255 len = flow_dv_get_item_hdr_len(items->type);
3256 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3257 return rte_flow_error_set(error, EINVAL,
3258 RTE_FLOW_ERROR_TYPE_ACTION,
3259 (void *)items->type,
3260 "items total size is too big"
3261 " for encap action");
3262 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3263 switch (items->type) {
3264 case RTE_FLOW_ITEM_TYPE_ETH:
3265 eth = (struct rte_ether_hdr *)&buf[temp_size];
3267 case RTE_FLOW_ITEM_TYPE_VLAN:
3268 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3270 return rte_flow_error_set(error, EINVAL,
3271 RTE_FLOW_ERROR_TYPE_ACTION,
3272 (void *)items->type,
3273 "eth header not found");
3274 if (!eth->ether_type)
3275 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3277 case RTE_FLOW_ITEM_TYPE_IPV4:
3278 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3280 return rte_flow_error_set(error, EINVAL,
3281 RTE_FLOW_ERROR_TYPE_ACTION,
3282 (void *)items->type,
3283 "neither eth nor vlan"
3285 if (vlan && !vlan->eth_proto)
3286 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3287 else if (eth && !eth->ether_type)
3288 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3289 if (!ipv4->version_ihl)
3290 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3291 MLX5_ENCAP_IPV4_IHL_MIN;
3292 if (!ipv4->time_to_live)
3293 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3295 case RTE_FLOW_ITEM_TYPE_IPV6:
3296 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3298 return rte_flow_error_set(error, EINVAL,
3299 RTE_FLOW_ERROR_TYPE_ACTION,
3300 (void *)items->type,
3301 "neither eth nor vlan"
3303 if (vlan && !vlan->eth_proto)
3304 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3305 else if (eth && !eth->ether_type)
3306 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3307 if (!ipv6->vtc_flow)
3309 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3310 if (!ipv6->hop_limits)
3311 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3313 case RTE_FLOW_ITEM_TYPE_UDP:
3314 udp = (struct rte_udp_hdr *)&buf[temp_size];
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION,
3318 (void *)items->type,
3319 "ip header not found");
3320 if (ipv4 && !ipv4->next_proto_id)
3321 ipv4->next_proto_id = IPPROTO_UDP;
3322 else if (ipv6 && !ipv6->proto)
3323 ipv6->proto = IPPROTO_UDP;
3325 case RTE_FLOW_ITEM_TYPE_VXLAN:
3326 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3328 return rte_flow_error_set(error, EINVAL,
3329 RTE_FLOW_ERROR_TYPE_ACTION,
3330 (void *)items->type,
3331 "udp header not found");
3333 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3334 if (!vxlan->vx_flags)
3336 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3338 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3339 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3341 return rte_flow_error_set(error, EINVAL,
3342 RTE_FLOW_ERROR_TYPE_ACTION,
3343 (void *)items->type,
3344 "udp header not found");
3345 if (!vxlan_gpe->proto)
3346 return rte_flow_error_set(error, EINVAL,
3347 RTE_FLOW_ERROR_TYPE_ACTION,
3348 (void *)items->type,
3349 "next protocol not found");
3352 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3353 if (!vxlan_gpe->vx_flags)
3354 vxlan_gpe->vx_flags =
3355 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3357 case RTE_FLOW_ITEM_TYPE_GRE:
3358 case RTE_FLOW_ITEM_TYPE_NVGRE:
3359 gre = (struct rte_gre_hdr *)&buf[temp_size];
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION,
3363 (void *)items->type,
3364 "next protocol not found");
3366 return rte_flow_error_set(error, EINVAL,
3367 RTE_FLOW_ERROR_TYPE_ACTION,
3368 (void *)items->type,
3369 "ip header not found");
3370 if (ipv4 && !ipv4->next_proto_id)
3371 ipv4->next_proto_id = IPPROTO_GRE;
3372 else if (ipv6 && !ipv6->proto)
3373 ipv6->proto = IPPROTO_GRE;
3375 case RTE_FLOW_ITEM_TYPE_VOID:
3378 return rte_flow_error_set(error, EINVAL,
3379 RTE_FLOW_ERROR_TYPE_ACTION,
3380 (void *)items->type,
3381 "unsupported item type");
3391 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3393 struct rte_ether_hdr *eth = NULL;
3394 struct rte_vlan_hdr *vlan = NULL;
3395 struct rte_ipv6_hdr *ipv6 = NULL;
3396 struct rte_udp_hdr *udp = NULL;
3400 eth = (struct rte_ether_hdr *)data;
3401 next_hdr = (char *)(eth + 1);
3402 proto = RTE_BE16(eth->ether_type);
3405 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3406 vlan = (struct rte_vlan_hdr *)next_hdr;
3407 proto = RTE_BE16(vlan->eth_proto);
3408 next_hdr += sizeof(struct rte_vlan_hdr);
3411 /* HW calculates IPv4 csum. no need to proceed */
3412 if (proto == RTE_ETHER_TYPE_IPV4)
3415 /* non IPv4/IPv6 header. not supported */
3416 if (proto != RTE_ETHER_TYPE_IPV6) {
3417 return rte_flow_error_set(error, ENOTSUP,
3418 RTE_FLOW_ERROR_TYPE_ACTION,
3419 NULL, "Cannot offload non IPv4/IPv6");
3422 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3424 /* ignore non UDP */
3425 if (ipv6->proto != IPPROTO_UDP)
3428 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3429 udp->dgram_cksum = 0;
3435 * Convert L2 encap action to DV specification.
3438 * Pointer to rte_eth_dev structure.
3440 * Pointer to action structure.
3441 * @param[in, out] dev_flow
3442 * Pointer to the mlx5_flow.
3443 * @param[in] transfer
3444 * Mark if the flow is E-Switch flow.
3446 * Pointer to the error structure.
3449 * 0 on success, a negative errno value otherwise and rte_errno is set.
3452 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3453 const struct rte_flow_action *action,
3454 struct mlx5_flow *dev_flow,
3456 struct rte_flow_error *error)
3458 const struct rte_flow_item *encap_data;
3459 const struct rte_flow_action_raw_encap *raw_encap_data;
3460 struct mlx5_flow_dv_encap_decap_resource res = {
3462 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3463 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3464 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3467 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3469 (const struct rte_flow_action_raw_encap *)action->conf;
3470 res.size = raw_encap_data->size;
3471 memcpy(res.buf, raw_encap_data->data, res.size);
3473 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3475 ((const struct rte_flow_action_vxlan_encap *)
3476 action->conf)->definition;
3479 ((const struct rte_flow_action_nvgre_encap *)
3480 action->conf)->definition;
3481 if (flow_dv_convert_encap_data(encap_data, res.buf,
3485 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3487 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3488 return rte_flow_error_set(error, EINVAL,
3489 RTE_FLOW_ERROR_TYPE_ACTION,
3490 NULL, "can't create L2 encap action");
3495 * Convert L2 decap action to DV specification.
3498 * Pointer to rte_eth_dev structure.
3499 * @param[in, out] dev_flow
3500 * Pointer to the mlx5_flow.
3501 * @param[in] transfer
3502 * Mark if the flow is E-Switch flow.
3504 * Pointer to the error structure.
3507 * 0 on success, a negative errno value otherwise and rte_errno is set.
3510 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3511 struct mlx5_flow *dev_flow,
3513 struct rte_flow_error *error)
3515 struct mlx5_flow_dv_encap_decap_resource res = {
3518 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3519 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3520 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3523 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3524 return rte_flow_error_set(error, EINVAL,
3525 RTE_FLOW_ERROR_TYPE_ACTION,
3526 NULL, "can't create L2 decap action");
3531 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3534 * Pointer to rte_eth_dev structure.
3536 * Pointer to action structure.
3537 * @param[in, out] dev_flow
3538 * Pointer to the mlx5_flow.
3540 * Pointer to the flow attributes.
3542 * Pointer to the error structure.
3545 * 0 on success, a negative errno value otherwise and rte_errno is set.
3548 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3549 const struct rte_flow_action *action,
3550 struct mlx5_flow *dev_flow,
3551 const struct rte_flow_attr *attr,
3552 struct rte_flow_error *error)
3554 const struct rte_flow_action_raw_encap *encap_data;
3555 struct mlx5_flow_dv_encap_decap_resource res;
3557 memset(&res, 0, sizeof(res));
3558 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3559 res.size = encap_data->size;
3560 memcpy(res.buf, encap_data->data, res.size);
3561 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3562 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3563 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3565 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3567 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3568 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3569 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3570 return rte_flow_error_set(error, EINVAL,
3571 RTE_FLOW_ERROR_TYPE_ACTION,
3572 NULL, "can't create encap action");
3577 * Create action push VLAN.
3580 * Pointer to rte_eth_dev structure.
3582 * Pointer to the flow attributes.
3584 * Pointer to the vlan to push to the Ethernet header.
3585 * @param[in, out] dev_flow
3586 * Pointer to the mlx5_flow.
3588 * Pointer to the error structure.
3591 * 0 on success, a negative errno value otherwise and rte_errno is set.
3594 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3595 const struct rte_flow_attr *attr,
3596 const struct rte_vlan_hdr *vlan,
3597 struct mlx5_flow *dev_flow,
3598 struct rte_flow_error *error)
3600 struct mlx5_flow_dv_push_vlan_action_resource res;
3602 memset(&res, 0, sizeof(res));
3604 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3607 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3609 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3610 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3611 return flow_dv_push_vlan_action_resource_register
3612 (dev, &res, dev_flow, error);
3615 static int fdb_mirror;
3618 * Validate the modify-header actions.
3620 * @param[in] action_flags
3621 * Holds the actions detected until now.
3623 * Pointer to the modify action.
3625 * Pointer to error structure.
3628 * 0 on success, a negative errno value otherwise and rte_errno is set.
3631 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3632 const struct rte_flow_action *action,
3633 struct rte_flow_error *error)
3635 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3636 return rte_flow_error_set(error, EINVAL,
3637 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3638 NULL, "action configuration not set");
3639 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3640 return rte_flow_error_set(error, EINVAL,
3641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3642 "can't have encap action before"
3644 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3645 return rte_flow_error_set(error, EINVAL,
3646 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3647 "can't support sample action before"
3648 " modify action for E-Switch"
3654 * Validate the modify-header MAC address actions.
3656 * @param[in] action_flags
3657 * Holds the actions detected until now.
3659 * Pointer to the modify action.
3660 * @param[in] item_flags
3661 * Holds the items detected.
3663 * Pointer to error structure.
3666 * 0 on success, a negative errno value otherwise and rte_errno is set.
3669 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3670 const struct rte_flow_action *action,
3671 const uint64_t item_flags,
3672 struct rte_flow_error *error)
3676 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3678 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3679 return rte_flow_error_set(error, EINVAL,
3680 RTE_FLOW_ERROR_TYPE_ACTION,
3682 "no L2 item in pattern");
3688 * Validate the modify-header IPv4 address actions.
3690 * @param[in] action_flags
3691 * Holds the actions detected until now.
3693 * Pointer to the modify action.
3694 * @param[in] item_flags
3695 * Holds the items detected.
3697 * Pointer to error structure.
3700 * 0 on success, a negative errno value otherwise and rte_errno is set.
3703 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3704 const struct rte_flow_action *action,
3705 const uint64_t item_flags,
3706 struct rte_flow_error *error)
3711 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3713 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3714 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3715 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3716 if (!(item_flags & layer))
3717 return rte_flow_error_set(error, EINVAL,
3718 RTE_FLOW_ERROR_TYPE_ACTION,
3720 "no ipv4 item in pattern");
3726 * Validate the modify-header IPv6 address actions.
3728 * @param[in] action_flags
3729 * Holds the actions detected until now.
3731 * Pointer to the modify action.
3732 * @param[in] item_flags
3733 * Holds the items detected.
3735 * Pointer to error structure.
3738 * 0 on success, a negative errno value otherwise and rte_errno is set.
3741 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3742 const struct rte_flow_action *action,
3743 const uint64_t item_flags,
3744 struct rte_flow_error *error)
3749 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3751 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3752 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3753 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3754 if (!(item_flags & layer))
3755 return rte_flow_error_set(error, EINVAL,
3756 RTE_FLOW_ERROR_TYPE_ACTION,
3758 "no ipv6 item in pattern");
3764 * Validate the modify-header TP actions.
3766 * @param[in] action_flags
3767 * Holds the actions detected until now.
3769 * Pointer to the modify action.
3770 * @param[in] item_flags
3771 * Holds the items detected.
3773 * Pointer to error structure.
3776 * 0 on success, a negative errno value otherwise and rte_errno is set.
3779 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3780 const struct rte_flow_action *action,
3781 const uint64_t item_flags,
3782 struct rte_flow_error *error)
3787 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3789 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3790 MLX5_FLOW_LAYER_INNER_L4 :
3791 MLX5_FLOW_LAYER_OUTER_L4;
3792 if (!(item_flags & layer))
3793 return rte_flow_error_set(error, EINVAL,
3794 RTE_FLOW_ERROR_TYPE_ACTION,
3795 NULL, "no transport layer "
3802 * Validate the modify-header actions of increment/decrement
3803 * TCP Sequence-number.
3805 * @param[in] action_flags
3806 * Holds the actions detected until now.
3808 * Pointer to the modify action.
3809 * @param[in] item_flags
3810 * Holds the items detected.
3812 * Pointer to error structure.
3815 * 0 on success, a negative errno value otherwise and rte_errno is set.
3818 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3819 const struct rte_flow_action *action,
3820 const uint64_t item_flags,
3821 struct rte_flow_error *error)
3826 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3828 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3829 MLX5_FLOW_LAYER_INNER_L4_TCP :
3830 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3831 if (!(item_flags & layer))
3832 return rte_flow_error_set(error, EINVAL,
3833 RTE_FLOW_ERROR_TYPE_ACTION,
3834 NULL, "no TCP item in"
3836 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3837 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3838 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3839 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3840 return rte_flow_error_set(error, EINVAL,
3841 RTE_FLOW_ERROR_TYPE_ACTION,
3843 "cannot decrease and increase"
3844 " TCP sequence number"
3845 " at the same time");
3851 * Validate the modify-header actions of increment/decrement
3852 * TCP Acknowledgment number.
3854 * @param[in] action_flags
3855 * Holds the actions detected until now.
3857 * Pointer to the modify action.
3858 * @param[in] item_flags
3859 * Holds the items detected.
3861 * Pointer to error structure.
3864 * 0 on success, a negative errno value otherwise and rte_errno is set.
3867 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3868 const struct rte_flow_action *action,
3869 const uint64_t item_flags,
3870 struct rte_flow_error *error)
3875 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3877 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3878 MLX5_FLOW_LAYER_INNER_L4_TCP :
3879 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3880 if (!(item_flags & layer))
3881 return rte_flow_error_set(error, EINVAL,
3882 RTE_FLOW_ERROR_TYPE_ACTION,
3883 NULL, "no TCP item in"
3885 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3886 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3887 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3888 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3889 return rte_flow_error_set(error, EINVAL,
3890 RTE_FLOW_ERROR_TYPE_ACTION,
3892 "cannot decrease and increase"
3893 " TCP acknowledgment number"
3894 " at the same time");
3900 * Validate the modify-header TTL actions.
3902 * @param[in] action_flags
3903 * Holds the actions detected until now.
3905 * Pointer to the modify action.
3906 * @param[in] item_flags
3907 * Holds the items detected.
3909 * Pointer to error structure.
3912 * 0 on success, a negative errno value otherwise and rte_errno is set.
3915 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3916 const struct rte_flow_action *action,
3917 const uint64_t item_flags,
3918 struct rte_flow_error *error)
3923 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3925 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3926 MLX5_FLOW_LAYER_INNER_L3 :
3927 MLX5_FLOW_LAYER_OUTER_L3;
3928 if (!(item_flags & layer))
3929 return rte_flow_error_set(error, EINVAL,
3930 RTE_FLOW_ERROR_TYPE_ACTION,
3932 "no IP protocol in pattern");
3938 * Validate jump action.
3941 * Pointer to the jump action.
3942 * @param[in] action_flags
3943 * Holds the actions detected until now.
3944 * @param[in] attributes
3945 * Pointer to flow attributes
3946 * @param[in] external
3947 * Action belongs to flow rule created by request external to PMD.
3949 * Pointer to error structure.
3952 * 0 on success, a negative errno value otherwise and rte_errno is set.
3955 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3956 const struct mlx5_flow_tunnel *tunnel,
3957 const struct rte_flow_action *action,
3958 uint64_t action_flags,
3959 const struct rte_flow_attr *attributes,
3960 bool external, struct rte_flow_error *error)
3962 uint32_t target_group, table;
3964 struct flow_grp_info grp_info = {
3965 .external = !!external,
3966 .transfer = !!attributes->transfer,
3970 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3971 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3972 return rte_flow_error_set(error, EINVAL,
3973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3974 "can't have 2 fate actions in"
3976 if (action_flags & MLX5_FLOW_ACTION_METER)
3977 return rte_flow_error_set(error, ENOTSUP,
3978 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3979 "jump with meter not support");
3980 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3981 return rte_flow_error_set(error, EINVAL,
3982 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3983 "E-Switch mirroring can't support"
3984 " Sample action and jump action in"
3987 return rte_flow_error_set(error, EINVAL,
3988 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3989 NULL, "action configuration not set");
3991 ((const struct rte_flow_action_jump *)action->conf)->group;
3992 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3996 if (attributes->group == target_group &&
3997 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3998 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3999 return rte_flow_error_set(error, EINVAL,
4000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4001 "target group must be other than"
4002 " the current flow group");
4007 * Validate the port_id action.
4010 * Pointer to rte_eth_dev structure.
4011 * @param[in] action_flags
4012 * Bit-fields that holds the actions detected until now.
4014 * Port_id RTE action structure.
4016 * Attributes of flow that includes this action.
4018 * Pointer to error structure.
4021 * 0 on success, a negative errno value otherwise and rte_errno is set.
4024 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4025 uint64_t action_flags,
4026 const struct rte_flow_action *action,
4027 const struct rte_flow_attr *attr,
4028 struct rte_flow_error *error)
4030 const struct rte_flow_action_port_id *port_id;
4031 struct mlx5_priv *act_priv;
4032 struct mlx5_priv *dev_priv;
4035 if (!attr->transfer)
4036 return rte_flow_error_set(error, ENOTSUP,
4037 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4039 "port id action is valid in transfer"
4041 if (!action || !action->conf)
4042 return rte_flow_error_set(error, ENOTSUP,
4043 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4045 "port id action parameters must be"
4047 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4048 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4049 return rte_flow_error_set(error, EINVAL,
4050 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4051 "can have only one fate actions in"
4053 dev_priv = mlx5_dev_to_eswitch_info(dev);
4055 return rte_flow_error_set(error, rte_errno,
4056 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4058 "failed to obtain E-Switch info");
4059 port_id = action->conf;
4060 port = port_id->original ? dev->data->port_id : port_id->id;
4061 act_priv = mlx5_port_to_eswitch_info(port, false);
4063 return rte_flow_error_set
4065 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4066 "failed to obtain E-Switch port id for port");
4067 if (act_priv->domain_id != dev_priv->domain_id)
4068 return rte_flow_error_set
4070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4071 "port does not belong to"
4072 " E-Switch being configured");
4077 * Get the maximum number of modify header actions.
4080 * Pointer to rte_eth_dev structure.
4082 * Flags bits to check if root level.
4085 * Max number of modify header actions device can support.
4087 static inline unsigned int
4088 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4092 * There's no way to directly query the max capacity from FW.
4093 * The maximal value on root table should be assumed to be supported.
4095 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4096 return MLX5_MAX_MODIFY_NUM;
4098 return MLX5_ROOT_TBL_MODIFY_NUM;
4102 * Validate the meter action.
4105 * Pointer to rte_eth_dev structure.
4106 * @param[in] action_flags
4107 * Bit-fields that holds the actions detected until now.
4109 * Pointer to the meter action.
4111 * Attributes of flow that includes this action.
4113 * Pointer to error structure.
4116 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4119 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4120 uint64_t action_flags,
4121 const struct rte_flow_action *action,
4122 const struct rte_flow_attr *attr,
4123 struct rte_flow_error *error)
4125 struct mlx5_priv *priv = dev->data->dev_private;
4126 const struct rte_flow_action_meter *am = action->conf;
4127 struct mlx5_flow_meter *fm;
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4132 "meter action conf is NULL");
4134 if (action_flags & MLX5_FLOW_ACTION_METER)
4135 return rte_flow_error_set(error, ENOTSUP,
4136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4137 "meter chaining not support");
4138 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4139 return rte_flow_error_set(error, ENOTSUP,
4140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4141 "meter with jump not support");
4143 return rte_flow_error_set(error, ENOTSUP,
4144 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4146 "meter action not supported");
4147 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4149 return rte_flow_error_set(error, EINVAL,
4150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4152 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4153 (!fm->ingress && !attr->ingress && attr->egress) ||
4154 (!fm->egress && !attr->egress && attr->ingress))))
4155 return rte_flow_error_set(error, EINVAL,
4156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4157 "Flow attributes are either invalid "
4158 "or have a conflict with current "
4159 "meter attributes");
4164 * Validate the age action.
4166 * @param[in] action_flags
4167 * Holds the actions detected until now.
4169 * Pointer to the age action.
4171 * Pointer to the Ethernet device structure.
4173 * Pointer to error structure.
4176 * 0 on success, a negative errno value otherwise and rte_errno is set.
4179 flow_dv_validate_action_age(uint64_t action_flags,
4180 const struct rte_flow_action *action,
4181 struct rte_eth_dev *dev,
4182 struct rte_flow_error *error)
4184 struct mlx5_priv *priv = dev->data->dev_private;
4185 const struct rte_flow_action_age *age = action->conf;
4187 if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4188 return rte_flow_error_set(error, ENOTSUP,
4189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4191 "age action not supported");
4192 if (!(action->conf))
4193 return rte_flow_error_set(error, EINVAL,
4194 RTE_FLOW_ERROR_TYPE_ACTION, action,
4195 "configuration cannot be null");
4196 if (!(age->timeout))
4197 return rte_flow_error_set(error, EINVAL,
4198 RTE_FLOW_ERROR_TYPE_ACTION, action,
4199 "invalid timeout value 0");
4200 if (action_flags & MLX5_FLOW_ACTION_AGE)
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4203 "duplicate age actions set");
4208 * Validate the modify-header IPv4 DSCP actions.
4210 * @param[in] action_flags
4211 * Holds the actions detected until now.
4213 * Pointer to the modify action.
4214 * @param[in] item_flags
4215 * Holds the items detected.
4217 * Pointer to error structure.
4220 * 0 on success, a negative errno value otherwise and rte_errno is set.
4223 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4224 const struct rte_flow_action *action,
4225 const uint64_t item_flags,
4226 struct rte_flow_error *error)
4230 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4232 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4233 return rte_flow_error_set(error, EINVAL,
4234 RTE_FLOW_ERROR_TYPE_ACTION,
4236 "no ipv4 item in pattern");
4242 * Validate the modify-header IPv6 DSCP actions.
4244 * @param[in] action_flags
4245 * Holds the actions detected until now.
4247 * Pointer to the modify action.
4248 * @param[in] item_flags
4249 * Holds the items detected.
4251 * Pointer to error structure.
4254 * 0 on success, a negative errno value otherwise and rte_errno is set.
4257 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4258 const struct rte_flow_action *action,
4259 const uint64_t item_flags,
4260 struct rte_flow_error *error)
4264 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4266 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4267 return rte_flow_error_set(error, EINVAL,
4268 RTE_FLOW_ERROR_TYPE_ACTION,
4270 "no ipv6 item in pattern");
4276 * Match modify-header resource.
4279 * Pointer to exist resource entry object.
4281 * Pointer to new modify-header resource.
4284 * 0 on matching, -1 otherwise.
4287 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4289 struct mlx5_flow_dv_modify_hdr_resource *resource;
4290 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4291 uint32_t actions_len;
4293 resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4294 cache_resource = container_of(entry,
4295 struct mlx5_flow_dv_modify_hdr_resource,
4297 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4298 if (resource->entry.key == cache_resource->entry.key &&
4299 resource->ft_type == cache_resource->ft_type &&
4300 resource->actions_num == cache_resource->actions_num &&
4301 resource->flags == cache_resource->flags &&
4302 !memcmp((const void *)resource->actions,
4303 (const void *)cache_resource->actions,
4310 * Validate the sample action.
4312 * @param[in] action_flags
4313 * Holds the actions detected until now.
4315 * Pointer to the sample action.
4317 * Pointer to the Ethernet device structure.
4319 * Attributes of flow that includes this action.
4321 * Pointer to error structure.
4324 * 0 on success, a negative errno value otherwise and rte_errno is set.
4327 flow_dv_validate_action_sample(uint64_t action_flags,
4328 const struct rte_flow_action *action,
4329 struct rte_eth_dev *dev,
4330 const struct rte_flow_attr *attr,
4331 struct rte_flow_error *error)
4333 struct mlx5_priv *priv = dev->data->dev_private;
4334 struct mlx5_dev_config *dev_conf = &priv->config;
4335 const struct rte_flow_action_sample *sample = action->conf;
4336 const struct rte_flow_action *act;
4337 uint64_t sub_action_flags = 0;
4338 uint16_t queue_index = 0xFFFF;
4344 return rte_flow_error_set(error, EINVAL,
4345 RTE_FLOW_ERROR_TYPE_ACTION, action,
4346 "configuration cannot be NULL");
4347 if (sample->ratio == 0)
4348 return rte_flow_error_set(error, EINVAL,
4349 RTE_FLOW_ERROR_TYPE_ACTION, action,
4350 "ratio value starts from 1");
4351 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4352 return rte_flow_error_set(error, ENOTSUP,
4353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4355 "sample action not supported");
4356 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4357 return rte_flow_error_set(error, EINVAL,
4358 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4359 "Multiple sample actions not "
4361 if (action_flags & MLX5_FLOW_ACTION_METER)
4362 return rte_flow_error_set(error, EINVAL,
4363 RTE_FLOW_ERROR_TYPE_ACTION, action,
4364 "wrong action order, meter should "
4365 "be after sample action");
4366 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4367 return rte_flow_error_set(error, EINVAL,
4368 RTE_FLOW_ERROR_TYPE_ACTION, action,
4369 "wrong action order, jump should "
4370 "be after sample action");
4371 act = sample->actions;
4372 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4373 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4374 return rte_flow_error_set(error, ENOTSUP,
4375 RTE_FLOW_ERROR_TYPE_ACTION,
4376 act, "too many actions");
4377 switch (act->type) {
4378 case RTE_FLOW_ACTION_TYPE_QUEUE:
4379 ret = mlx5_flow_validate_action_queue(act,
4385 queue_index = ((const struct rte_flow_action_queue *)
4386 (act->conf))->index;
4387 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4390 case RTE_FLOW_ACTION_TYPE_MARK:
4391 ret = flow_dv_validate_action_mark(dev, act,
4396 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4397 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4398 MLX5_FLOW_ACTION_MARK_EXT;
4400 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4403 case RTE_FLOW_ACTION_TYPE_COUNT:
4404 ret = flow_dv_validate_action_count(dev, error);
4407 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4410 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4411 ret = flow_dv_validate_action_port_id(dev,
4418 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4421 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4422 ret = flow_dv_validate_action_raw_encap_decap
4423 (dev, NULL, act->conf, attr, &sub_action_flags,
4430 return rte_flow_error_set(error, ENOTSUP,
4431 RTE_FLOW_ERROR_TYPE_ACTION,
4433 "Doesn't support optional "
4437 if (attr->ingress && !attr->transfer) {
4438 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4439 return rte_flow_error_set(error, EINVAL,
4440 RTE_FLOW_ERROR_TYPE_ACTION,
4442 "Ingress must has a dest "
4443 "QUEUE for Sample");
4444 } else if (attr->egress && !attr->transfer) {
4445 return rte_flow_error_set(error, ENOTSUP,
4446 RTE_FLOW_ERROR_TYPE_ACTION,
4448 "Sample Only support Ingress "
4450 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4451 MLX5_ASSERT(attr->transfer);
4452 if (sample->ratio > 1)
4453 return rte_flow_error_set(error, ENOTSUP,
4454 RTE_FLOW_ERROR_TYPE_ACTION,
4456 "E-Switch doesn't support "
4457 "any optional action "
4460 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4461 return rte_flow_error_set(error, ENOTSUP,
4462 RTE_FLOW_ERROR_TYPE_ACTION,
4464 "unsupported action QUEUE");
4465 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4466 return rte_flow_error_set(error, EINVAL,
4467 RTE_FLOW_ERROR_TYPE_ACTION,
4469 "E-Switch must has a dest "
4470 "port for mirroring");
4472 /* Continue validation for Xcap actions.*/
4473 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4474 (queue_index == 0xFFFF ||
4475 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4476 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4477 MLX5_FLOW_XCAP_ACTIONS)
4478 return rte_flow_error_set(error, ENOTSUP,
4479 RTE_FLOW_ERROR_TYPE_ACTION,
4480 NULL, "encap and decap "
4481 "combination aren't "
4483 if (!attr->transfer && attr->ingress && (sub_action_flags &
4484 MLX5_FLOW_ACTION_ENCAP))
4485 return rte_flow_error_set(error, ENOTSUP,
4486 RTE_FLOW_ERROR_TYPE_ACTION,
4487 NULL, "encap is not supported"
4488 " for ingress traffic");
4494 * Find existing modify-header resource or create and register a new one.
4496 * @param dev[in, out]
4497 * Pointer to rte_eth_dev structure.
4498 * @param[in, out] resource
4499 * Pointer to modify-header resource.
4500 * @parm[in, out] dev_flow
4501 * Pointer to the dev_flow.
4503 * pointer to error structure.
4506 * 0 on success otherwise -errno and errno is set.
4509 flow_dv_modify_hdr_resource_register
4510 (struct rte_eth_dev *dev,
4511 struct mlx5_flow_dv_modify_hdr_resource *resource,
4512 struct mlx5_flow *dev_flow,
4513 struct rte_flow_error *error)
4515 struct mlx5_priv *priv = dev->data->dev_private;
4516 struct mlx5_dev_ctx_shared *sh = priv->sh;
4517 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4518 struct mlx5dv_dr_domain *ns;
4519 uint32_t actions_len;
4520 struct mlx5_hlist_entry *entry;
4521 union mlx5_flow_modify_hdr_key hdr_mod_key = {
4523 .ft_type = resource->ft_type,
4524 .actions_num = resource->actions_num,
4525 .group = dev_flow->dv.group,
4531 resource->flags = dev_flow->dv.group ? 0 :
4532 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4533 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4535 return rte_flow_error_set(error, EOVERFLOW,
4536 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4537 "too many modify header items");
4538 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4539 ns = sh->fdb_domain;
4540 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4544 /* Lookup a matching resource from cache. */
4545 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4546 hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4547 resource->entry.key = hdr_mod_key.v64;
4548 entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4549 flow_dv_modify_hdr_resource_match,
4552 cache_resource = container_of(entry,
4553 struct mlx5_flow_dv_modify_hdr_resource,
4555 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4556 (void *)cache_resource,
4557 __atomic_load_n(&cache_resource->refcnt,
4559 __atomic_fetch_add(&cache_resource->refcnt, 1,
4561 dev_flow->handle->dvh.modify_hdr = cache_resource;
4565 /* Register new modify-header resource. */
4566 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4567 sizeof(*cache_resource) + actions_len, 0,
4569 if (!cache_resource)
4570 return rte_flow_error_set(error, ENOMEM,
4571 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4572 "cannot allocate resource memory");
4573 *cache_resource = *resource;
4574 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4575 ret = mlx5_flow_os_create_flow_action_modify_header
4576 (sh->ctx, ns, cache_resource,
4577 actions_len, &cache_resource->action);
4579 mlx5_free(cache_resource);
4580 return rte_flow_error_set(error, ENOMEM,
4581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4582 NULL, "cannot create action");
4584 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
4585 if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4586 flow_dv_modify_hdr_resource_match,
4587 (void *)cache_resource)) {
4588 claim_zero(mlx5_flow_os_destroy_flow_action
4589 (cache_resource->action));
4590 mlx5_free(cache_resource);
4591 return rte_flow_error_set(error, EEXIST,
4592 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4593 NULL, "action exist");
4595 dev_flow->handle->dvh.modify_hdr = cache_resource;
4596 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4597 (void *)cache_resource,
4598 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
4603 * Get DV flow counter by index.
4606 * Pointer to the Ethernet device structure.
4608 * mlx5 flow counter index in the container.
4610 * mlx5 flow counter pool in the container,
4613 * Pointer to the counter, NULL otherwise.
4615 static struct mlx5_flow_counter *
4616 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4618 struct mlx5_flow_counter_pool **ppool)
4620 struct mlx5_priv *priv = dev->data->dev_private;
4621 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4622 struct mlx5_flow_counter_pool *pool;
4624 /* Decrease to original index and clear shared bit. */
4625 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4626 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4627 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4631 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4635 * Check the devx counter belongs to the pool.
4638 * Pointer to the counter pool.
4640 * The counter devx ID.
4643 * True if counter belongs to the pool, false otherwise.
4646 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4648 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4649 MLX5_COUNTERS_PER_POOL;
4651 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4657 * Get a pool by devx counter ID.
4660 * Pointer to the counter management.
4662 * The counter devx ID.
4665 * The counter pool pointer if exists, NULL otherwise,
4667 static struct mlx5_flow_counter_pool *
4668 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4671 struct mlx5_flow_counter_pool *pool = NULL;
4673 rte_spinlock_lock(&cmng->pool_update_sl);
4674 /* Check last used pool. */
4675 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4676 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4677 pool = cmng->pools[cmng->last_pool_idx];
4680 /* ID out of range means no suitable pool in the container. */
4681 if (id > cmng->max_id || id < cmng->min_id)
4684 * Find the pool from the end of the container, since mostly counter
4685 * ID is sequence increasing, and the last pool should be the needed
4690 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4692 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4698 rte_spinlock_unlock(&cmng->pool_update_sl);
4703 * Resize a counter container.
4706 * Pointer to the Ethernet device structure.
4709 * 0 on success, otherwise negative errno value and rte_errno is set.
4712 flow_dv_container_resize(struct rte_eth_dev *dev)
4714 struct mlx5_priv *priv = dev->data->dev_private;
4715 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4716 void *old_pools = cmng->pools;
4717 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4718 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4719 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4726 memcpy(pools, old_pools, cmng->n *
4727 sizeof(struct mlx5_flow_counter_pool *));
4729 cmng->pools = pools;
4731 mlx5_free(old_pools);
4736 * Query a devx flow counter.
4739 * Pointer to the Ethernet device structure.
4741 * Index to the flow counter.
4743 * The statistics value of packets.
4745 * The statistics value of bytes.
4748 * 0 on success, otherwise a negative errno value and rte_errno is set.
4751 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4754 struct mlx5_priv *priv = dev->data->dev_private;
4755 struct mlx5_flow_counter_pool *pool = NULL;
4756 struct mlx5_flow_counter *cnt;
4759 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4761 if (priv->sh->cmng.counter_fallback)
4762 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4763 0, pkts, bytes, 0, NULL, NULL, 0);
4764 rte_spinlock_lock(&pool->sl);
4769 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4770 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4771 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4773 rte_spinlock_unlock(&pool->sl);
4778 * Create and initialize a new counter pool.
4781 * Pointer to the Ethernet device structure.
4783 * The devX counter handle.
4785 * Whether the pool is for counter that was allocated for aging.
4786 * @param[in/out] cont_cur
4787 * Pointer to the container pointer, it will be update in pool resize.
4790 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4792 static struct mlx5_flow_counter_pool *
4793 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4796 struct mlx5_priv *priv = dev->data->dev_private;
4797 struct mlx5_flow_counter_pool *pool;
4798 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4799 bool fallback = priv->sh->cmng.counter_fallback;
4800 uint32_t size = sizeof(*pool);
4802 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4803 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4804 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4810 pool->is_aged = !!age;
4811 pool->query_gen = 0;
4812 pool->min_dcs = dcs;
4813 rte_spinlock_init(&pool->sl);
4814 rte_spinlock_init(&pool->csl);
4815 TAILQ_INIT(&pool->counters[0]);
4816 TAILQ_INIT(&pool->counters[1]);
4817 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4818 rte_spinlock_lock(&cmng->pool_update_sl);
4819 pool->index = cmng->n_valid;
4820 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4822 rte_spinlock_unlock(&cmng->pool_update_sl);
4825 cmng->pools[pool->index] = pool;
4827 if (unlikely(fallback)) {
4828 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4830 if (base < cmng->min_id)
4831 cmng->min_id = base;
4832 if (base > cmng->max_id)
4833 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4834 cmng->last_pool_idx = pool->index;
4836 rte_spinlock_unlock(&cmng->pool_update_sl);
4841 * Prepare a new counter and/or a new counter pool.
4844 * Pointer to the Ethernet device structure.
4845 * @param[out] cnt_free
4846 * Where to put the pointer of a new counter.
4848 * Whether the pool is for counter that was allocated for aging.
4851 * The counter pool pointer and @p cnt_free is set on success,
4852 * NULL otherwise and rte_errno is set.
4854 static struct mlx5_flow_counter_pool *
4855 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4856 struct mlx5_flow_counter **cnt_free,
4859 struct mlx5_priv *priv = dev->data->dev_private;
4860 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4861 struct mlx5_flow_counter_pool *pool;
4862 struct mlx5_counters tmp_tq;
4863 struct mlx5_devx_obj *dcs = NULL;
4864 struct mlx5_flow_counter *cnt;
4865 enum mlx5_counter_type cnt_type =
4866 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4867 bool fallback = priv->sh->cmng.counter_fallback;
4871 /* bulk_bitmap must be 0 for single counter allocation. */
4872 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4875 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4877 pool = flow_dv_pool_create(dev, dcs, age);
4879 mlx5_devx_cmd_destroy(dcs);
4883 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4884 cnt = MLX5_POOL_GET_CNT(pool, i);
4886 cnt->dcs_when_free = dcs;
4890 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4892 rte_errno = ENODATA;
4895 pool = flow_dv_pool_create(dev, dcs, age);
4897 mlx5_devx_cmd_destroy(dcs);
4900 TAILQ_INIT(&tmp_tq);
4901 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4902 cnt = MLX5_POOL_GET_CNT(pool, i);
4904 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4906 rte_spinlock_lock(&cmng->csl[cnt_type]);
4907 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4908 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4909 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4910 (*cnt_free)->pool = pool;
4915 * Allocate a flow counter.
4918 * Pointer to the Ethernet device structure.
4920 * Whether the counter was allocated for aging.
4923 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4926 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4928 struct mlx5_priv *priv = dev->data->dev_private;
4929 struct mlx5_flow_counter_pool *pool = NULL;
4930 struct mlx5_flow_counter *cnt_free = NULL;
4931 bool fallback = priv->sh->cmng.counter_fallback;
4932 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4933 enum mlx5_counter_type cnt_type =
4934 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4937 if (!priv->config.devx) {
4938 rte_errno = ENOTSUP;
4941 /* Get free counters from container. */
4942 rte_spinlock_lock(&cmng->csl[cnt_type]);
4943 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4945 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4946 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4947 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4949 pool = cnt_free->pool;
4951 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4952 /* Create a DV counter action only in the first time usage. */
4953 if (!cnt_free->action) {
4955 struct mlx5_devx_obj *dcs;
4959 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4960 dcs = pool->min_dcs;
4963 dcs = cnt_free->dcs_when_free;
4965 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4972 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4973 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4974 /* Update the counter reset values. */
4975 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4978 if (!fallback && !priv->sh->cmng.query_thread_on)
4979 /* Start the asynchronous batch query by the host thread. */
4980 mlx5_set_query_alarm(priv->sh);
4984 cnt_free->pool = pool;
4986 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4987 rte_spinlock_lock(&cmng->csl[cnt_type]);
4988 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4989 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4995 * Allocate a shared flow counter.
4998 * Pointer to the shared counter configuration.
5000 * Pointer to save the allocated counter index.
5003 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5007 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5009 struct mlx5_shared_counter_conf *conf = ctx;
5010 struct rte_eth_dev *dev = conf->dev;
5011 struct mlx5_flow_counter *cnt;
5013 data->dword = flow_dv_counter_alloc(dev, 0);
5014 data->dword |= MLX5_CNT_SHARED_OFFSET;
5015 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5016 cnt->shared_info.id = conf->id;
5021 * Get a shared flow counter.
5024 * Pointer to the Ethernet device structure.
5026 * Counter identifier.
5029 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5032 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5034 struct mlx5_priv *priv = dev->data->dev_private;
5035 struct mlx5_shared_counter_conf conf = {
5039 union mlx5_l3t_data data = {
5043 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5044 flow_dv_counter_alloc_shared_cb, &conf);
5049 * Get age param from counter index.
5052 * Pointer to the Ethernet device structure.
5053 * @param[in] counter
5054 * Index to the counter handler.
5057 * The aging parameter specified for the counter index.
5059 static struct mlx5_age_param*
5060 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5063 struct mlx5_flow_counter *cnt;
5064 struct mlx5_flow_counter_pool *pool = NULL;
5066 flow_dv_counter_get_by_idx(dev, counter, &pool);
5067 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5068 cnt = MLX5_POOL_GET_CNT(pool, counter);
5069 return MLX5_CNT_TO_AGE(cnt);
5073 * Remove a flow counter from aged counter list.
5076 * Pointer to the Ethernet device structure.
5077 * @param[in] counter
5078 * Index to the counter handler.
5080 * Pointer to the counter handler.
5083 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5084 uint32_t counter, struct mlx5_flow_counter *cnt)
5086 struct mlx5_age_info *age_info;
5087 struct mlx5_age_param *age_param;
5088 struct mlx5_priv *priv = dev->data->dev_private;
5089 uint16_t expected = AGE_CANDIDATE;
5091 age_info = GET_PORT_AGE_INFO(priv);
5092 age_param = flow_dv_counter_idx_get_age(dev, counter);
5093 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5094 AGE_FREE, false, __ATOMIC_RELAXED,
5095 __ATOMIC_RELAXED)) {
5097 * We need the lock even it is age timeout,
5098 * since counter may still in process.
5100 rte_spinlock_lock(&age_info->aged_sl);
5101 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5102 rte_spinlock_unlock(&age_info->aged_sl);
5103 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5108 * Release a flow counter.
5111 * Pointer to the Ethernet device structure.
5112 * @param[in] counter
5113 * Index to the counter handler.
5116 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5118 struct mlx5_priv *priv = dev->data->dev_private;
5119 struct mlx5_flow_counter_pool *pool = NULL;
5120 struct mlx5_flow_counter *cnt;
5121 enum mlx5_counter_type cnt_type;
5125 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5127 if (IS_SHARED_CNT(counter) &&
5128 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5131 flow_dv_counter_remove_from_age(dev, counter, cnt);
5134 * Put the counter back to list to be updated in none fallback mode.
5135 * Currently, we are using two list alternately, while one is in query,
5136 * add the freed counter to the other list based on the pool query_gen
5137 * value. After query finishes, add counter the list to the global
5138 * container counter list. The list changes while query starts. In
5139 * this case, lock will not be needed as query callback and release
5140 * function both operate with the different list.
5143 if (!priv->sh->cmng.counter_fallback) {
5144 rte_spinlock_lock(&pool->csl);
5145 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5146 rte_spinlock_unlock(&pool->csl);
5148 cnt->dcs_when_free = cnt->dcs_when_active;
5149 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5150 MLX5_COUNTER_TYPE_ORIGIN;
5151 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5152 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5154 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5159 * Verify the @p attributes will be correctly understood by the NIC and store
5160 * them in the @p flow if everything is correct.
5163 * Pointer to dev struct.
5164 * @param[in] attributes
5165 * Pointer to flow attributes
5166 * @param[in] external
5167 * This flow rule is created by request external to PMD.
5169 * Pointer to error structure.
5172 * - 0 on success and non root table.
5173 * - 1 on success and root table.
5174 * - a negative errno value otherwise and rte_errno is set.
5177 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5178 const struct mlx5_flow_tunnel *tunnel,
5179 const struct rte_flow_attr *attributes,
5180 struct flow_grp_info grp_info,
5181 struct rte_flow_error *error)
5183 struct mlx5_priv *priv = dev->data->dev_private;
5184 uint32_t priority_max = priv->config.flow_prio - 1;
5187 #ifndef HAVE_MLX5DV_DR
5188 RTE_SET_USED(tunnel);
5189 RTE_SET_USED(grp_info);
5190 if (attributes->group)
5191 return rte_flow_error_set(error, ENOTSUP,
5192 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5194 "groups are not supported");
5198 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5203 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5205 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5206 attributes->priority >= priority_max)
5207 return rte_flow_error_set(error, ENOTSUP,
5208 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5210 "priority out of range");
5211 if (attributes->transfer) {
5212 if (!priv->config.dv_esw_en)
5213 return rte_flow_error_set
5215 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5216 "E-Switch dr is not supported");
5217 if (!(priv->representor || priv->master))
5218 return rte_flow_error_set
5219 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5220 NULL, "E-Switch configuration can only be"
5221 " done by a master or a representor device");
5222 if (attributes->egress)
5223 return rte_flow_error_set
5225 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5226 "egress is not supported");
5228 if (!(attributes->egress ^ attributes->ingress))
5229 return rte_flow_error_set(error, ENOTSUP,
5230 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5231 "must specify exactly one of "
5232 "ingress or egress");
5237 * Internal validation function. For validating both actions and items.
5240 * Pointer to the rte_eth_dev structure.
5242 * Pointer to the flow attributes.
5244 * Pointer to the list of items.
5245 * @param[in] actions
5246 * Pointer to the list of actions.
5247 * @param[in] external
5248 * This flow rule is created by request external to PMD.
5249 * @param[in] hairpin
5250 * Number of hairpin TX actions, 0 means classic flow.
5252 * Pointer to the error structure.
5255 * 0 on success, a negative errno value otherwise and rte_errno is set.
5258 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5259 const struct rte_flow_item items[],
5260 const struct rte_flow_action actions[],
5261 bool external, int hairpin, struct rte_flow_error *error)
5264 uint64_t action_flags = 0;
5265 uint64_t item_flags = 0;
5266 uint64_t last_item = 0;
5267 uint8_t next_protocol = 0xff;
5268 uint16_t ether_type = 0;
5270 uint8_t item_ipv6_proto = 0;
5271 const struct rte_flow_item *gre_item = NULL;
5272 const struct rte_flow_action_raw_decap *decap;
5273 const struct rte_flow_action_raw_encap *encap;
5274 const struct rte_flow_action_rss *rss;
5275 const struct rte_flow_item_tcp nic_tcp_mask = {
5278 .src_port = RTE_BE16(UINT16_MAX),
5279 .dst_port = RTE_BE16(UINT16_MAX),
5282 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5285 "\xff\xff\xff\xff\xff\xff\xff\xff"
5286 "\xff\xff\xff\xff\xff\xff\xff\xff",
5288 "\xff\xff\xff\xff\xff\xff\xff\xff"
5289 "\xff\xff\xff\xff\xff\xff\xff\xff",
5290 .vtc_flow = RTE_BE32(0xffffffff),
5296 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5300 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5304 .dummy[0] = 0xffffffff,
5307 struct mlx5_priv *priv = dev->data->dev_private;
5308 struct mlx5_dev_config *dev_conf = &priv->config;
5309 uint16_t queue_index = 0xFFFF;
5310 const struct rte_flow_item_vlan *vlan_m = NULL;
5311 int16_t rw_act_num = 0;
5313 const struct mlx5_flow_tunnel *tunnel;
5314 struct flow_grp_info grp_info = {
5315 .external = !!external,
5316 .transfer = !!attr->transfer,
5317 .fdb_def_rule = !!priv->fdb_def_rule,
5319 const struct rte_eth_hairpin_conf *conf;
5323 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5324 tunnel = flow_items_to_tunnel(items);
5325 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5326 MLX5_FLOW_ACTION_DECAP;
5327 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5328 tunnel = flow_actions_to_tunnel(actions);
5329 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5333 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5334 (dev, tunnel, attr, items, actions);
5335 ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5338 is_root = (uint64_t)ret;
5339 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5340 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5341 int type = items->type;
5343 if (!mlx5_flow_os_item_supported(type))
5344 return rte_flow_error_set(error, ENOTSUP,
5345 RTE_FLOW_ERROR_TYPE_ITEM,
5346 NULL, "item not supported");
5348 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5349 if (items[0].type != (typeof(items[0].type))
5350 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5351 return rte_flow_error_set
5353 RTE_FLOW_ERROR_TYPE_ITEM,
5354 NULL, "MLX5 private items "
5355 "must be the first");
5357 case RTE_FLOW_ITEM_TYPE_VOID:
5359 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5360 ret = flow_dv_validate_item_port_id
5361 (dev, items, attr, item_flags, error);
5364 last_item = MLX5_FLOW_ITEM_PORT_ID;
5366 case RTE_FLOW_ITEM_TYPE_ETH:
5367 ret = mlx5_flow_validate_item_eth(items, item_flags,
5371 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5372 MLX5_FLOW_LAYER_OUTER_L2;
5373 if (items->mask != NULL && items->spec != NULL) {
5375 ((const struct rte_flow_item_eth *)
5378 ((const struct rte_flow_item_eth *)
5380 ether_type = rte_be_to_cpu_16(ether_type);
5385 case RTE_FLOW_ITEM_TYPE_VLAN:
5386 ret = flow_dv_validate_item_vlan(items, item_flags,
5390 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5391 MLX5_FLOW_LAYER_OUTER_VLAN;
5392 if (items->mask != NULL && items->spec != NULL) {
5394 ((const struct rte_flow_item_vlan *)
5395 items->spec)->inner_type;
5397 ((const struct rte_flow_item_vlan *)
5398 items->mask)->inner_type;
5399 ether_type = rte_be_to_cpu_16(ether_type);
5403 /* Store outer VLAN mask for of_push_vlan action. */
5405 vlan_m = items->mask;
5407 case RTE_FLOW_ITEM_TYPE_IPV4:
5408 mlx5_flow_tunnel_ip_check(items, next_protocol,
5409 &item_flags, &tunnel);
5410 ret = flow_dv_validate_item_ipv4(items, item_flags,
5411 last_item, ether_type,
5415 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5416 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5417 if (items->mask != NULL &&
5418 ((const struct rte_flow_item_ipv4 *)
5419 items->mask)->hdr.next_proto_id) {
5421 ((const struct rte_flow_item_ipv4 *)
5422 (items->spec))->hdr.next_proto_id;
5424 ((const struct rte_flow_item_ipv4 *)
5425 (items->mask))->hdr.next_proto_id;
5427 /* Reset for inner layer. */
5428 next_protocol = 0xff;
5431 case RTE_FLOW_ITEM_TYPE_IPV6:
5432 mlx5_flow_tunnel_ip_check(items, next_protocol,
5433 &item_flags, &tunnel);
5434 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5441 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5442 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5443 if (items->mask != NULL &&
5444 ((const struct rte_flow_item_ipv6 *)
5445 items->mask)->hdr.proto) {
5447 ((const struct rte_flow_item_ipv6 *)
5448 items->spec)->hdr.proto;
5450 ((const struct rte_flow_item_ipv6 *)
5451 items->spec)->hdr.proto;
5453 ((const struct rte_flow_item_ipv6 *)
5454 items->mask)->hdr.proto;
5456 /* Reset for inner layer. */
5457 next_protocol = 0xff;
5460 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5461 ret = flow_dv_validate_item_ipv6_frag_ext(items,
5466 last_item = tunnel ?
5467 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5468 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5469 if (items->mask != NULL &&
5470 ((const struct rte_flow_item_ipv6_frag_ext *)
5471 items->mask)->hdr.next_header) {
5473 ((const struct rte_flow_item_ipv6_frag_ext *)
5474 items->spec)->hdr.next_header;
5476 ((const struct rte_flow_item_ipv6_frag_ext *)
5477 items->mask)->hdr.next_header;
5479 /* Reset for inner layer. */
5480 next_protocol = 0xff;
5483 case RTE_FLOW_ITEM_TYPE_TCP:
5484 ret = mlx5_flow_validate_item_tcp
5491 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5492 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5494 case RTE_FLOW_ITEM_TYPE_UDP:
5495 ret = mlx5_flow_validate_item_udp(items, item_flags,
5500 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5501 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5503 case RTE_FLOW_ITEM_TYPE_GRE:
5504 ret = mlx5_flow_validate_item_gre(items, item_flags,
5505 next_protocol, error);
5509 last_item = MLX5_FLOW_LAYER_GRE;
5511 case RTE_FLOW_ITEM_TYPE_NVGRE:
5512 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5517 last_item = MLX5_FLOW_LAYER_NVGRE;
5519 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5520 ret = mlx5_flow_validate_item_gre_key
5521 (items, item_flags, gre_item, error);
5524 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5526 case RTE_FLOW_ITEM_TYPE_VXLAN:
5527 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5531 last_item = MLX5_FLOW_LAYER_VXLAN;
5533 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5534 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5539 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5541 case RTE_FLOW_ITEM_TYPE_GENEVE:
5542 ret = mlx5_flow_validate_item_geneve(items,
5547 last_item = MLX5_FLOW_LAYER_GENEVE;
5549 case RTE_FLOW_ITEM_TYPE_MPLS:
5550 ret = mlx5_flow_validate_item_mpls(dev, items,
5555 last_item = MLX5_FLOW_LAYER_MPLS;
5558 case RTE_FLOW_ITEM_TYPE_MARK:
5559 ret = flow_dv_validate_item_mark(dev, items, attr,
5563 last_item = MLX5_FLOW_ITEM_MARK;
5565 case RTE_FLOW_ITEM_TYPE_META:
5566 ret = flow_dv_validate_item_meta(dev, items, attr,
5570 last_item = MLX5_FLOW_ITEM_METADATA;
5572 case RTE_FLOW_ITEM_TYPE_ICMP:
5573 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5578 last_item = MLX5_FLOW_LAYER_ICMP;
5580 case RTE_FLOW_ITEM_TYPE_ICMP6:
5581 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5586 item_ipv6_proto = IPPROTO_ICMPV6;
5587 last_item = MLX5_FLOW_LAYER_ICMP6;
5589 case RTE_FLOW_ITEM_TYPE_TAG:
5590 ret = flow_dv_validate_item_tag(dev, items,
5594 last_item = MLX5_FLOW_ITEM_TAG;
5596 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5597 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5599 case RTE_FLOW_ITEM_TYPE_GTP:
5600 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5604 last_item = MLX5_FLOW_LAYER_GTP;
5606 case RTE_FLOW_ITEM_TYPE_ECPRI:
5607 /* Capacity will be checked in the translate stage. */
5608 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5615 last_item = MLX5_FLOW_LAYER_ECPRI;
5618 return rte_flow_error_set(error, ENOTSUP,
5619 RTE_FLOW_ERROR_TYPE_ITEM,
5620 NULL, "item not supported");
5622 item_flags |= last_item;
5624 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5625 int type = actions->type;
5627 if (!mlx5_flow_os_action_supported(type))
5628 return rte_flow_error_set(error, ENOTSUP,
5629 RTE_FLOW_ERROR_TYPE_ACTION,
5631 "action not supported");
5632 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5633 return rte_flow_error_set(error, ENOTSUP,
5634 RTE_FLOW_ERROR_TYPE_ACTION,
5635 actions, "too many actions");
5637 case RTE_FLOW_ACTION_TYPE_VOID:
5639 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5640 ret = flow_dv_validate_action_port_id(dev,
5647 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5650 case RTE_FLOW_ACTION_TYPE_FLAG:
5651 ret = flow_dv_validate_action_flag(dev, action_flags,
5655 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5656 /* Count all modify-header actions as one. */
5657 if (!(action_flags &
5658 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5660 action_flags |= MLX5_FLOW_ACTION_FLAG |
5661 MLX5_FLOW_ACTION_MARK_EXT;
5663 action_flags |= MLX5_FLOW_ACTION_FLAG;
5666 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5668 case RTE_FLOW_ACTION_TYPE_MARK:
5669 ret = flow_dv_validate_action_mark(dev, actions,
5674 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5675 /* Count all modify-header actions as one. */
5676 if (!(action_flags &
5677 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5679 action_flags |= MLX5_FLOW_ACTION_MARK |
5680 MLX5_FLOW_ACTION_MARK_EXT;
5682 action_flags |= MLX5_FLOW_ACTION_MARK;
5685 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5687 case RTE_FLOW_ACTION_TYPE_SET_META:
5688 ret = flow_dv_validate_action_set_meta(dev, actions,
5693 /* Count all modify-header actions as one action. */
5694 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5696 action_flags |= MLX5_FLOW_ACTION_SET_META;
5697 rw_act_num += MLX5_ACT_NUM_SET_META;
5699 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5700 ret = flow_dv_validate_action_set_tag(dev, actions,
5705 /* Count all modify-header actions as one action. */
5706 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5708 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5709 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5711 case RTE_FLOW_ACTION_TYPE_DROP:
5712 ret = mlx5_flow_validate_action_drop(action_flags,
5716 action_flags |= MLX5_FLOW_ACTION_DROP;
5719 case RTE_FLOW_ACTION_TYPE_QUEUE:
5720 ret = mlx5_flow_validate_action_queue(actions,
5725 queue_index = ((const struct rte_flow_action_queue *)
5726 (actions->conf))->index;
5727 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5730 case RTE_FLOW_ACTION_TYPE_RSS:
5731 rss = actions->conf;
5732 ret = mlx5_flow_validate_action_rss(actions,
5738 if (rss != NULL && rss->queue_num)
5739 queue_index = rss->queue[0];
5740 action_flags |= MLX5_FLOW_ACTION_RSS;
5743 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5745 mlx5_flow_validate_action_default_miss(action_flags,
5749 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5752 case RTE_FLOW_ACTION_TYPE_COUNT:
5753 ret = flow_dv_validate_action_count(dev, error);
5756 action_flags |= MLX5_FLOW_ACTION_COUNT;
5759 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5760 if (flow_dv_validate_action_pop_vlan(dev,
5766 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5769 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5770 ret = flow_dv_validate_action_push_vlan(dev,
5777 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5780 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5781 ret = flow_dv_validate_action_set_vlan_pcp
5782 (action_flags, actions, error);
5785 /* Count PCP with push_vlan command. */
5786 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5788 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5789 ret = flow_dv_validate_action_set_vlan_vid
5790 (item_flags, action_flags,
5794 /* Count VID with push_vlan command. */
5795 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5796 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5798 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5799 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5800 ret = flow_dv_validate_action_l2_encap(dev,
5806 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5809 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5810 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5811 ret = flow_dv_validate_action_decap(dev, action_flags,
5815 action_flags |= MLX5_FLOW_ACTION_DECAP;
5818 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5819 ret = flow_dv_validate_action_raw_encap_decap
5820 (dev, NULL, actions->conf, attr, &action_flags,
5825 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5826 decap = actions->conf;
5827 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5829 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5833 encap = actions->conf;
5835 ret = flow_dv_validate_action_raw_encap_decap
5837 decap ? decap : &empty_decap, encap,
5838 attr, &action_flags, &actions_n,
5843 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5844 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5845 ret = flow_dv_validate_action_modify_mac(action_flags,
5851 /* Count all modify-header actions as one action. */
5852 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5854 action_flags |= actions->type ==
5855 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5856 MLX5_FLOW_ACTION_SET_MAC_SRC :
5857 MLX5_FLOW_ACTION_SET_MAC_DST;
5859 * Even if the source and destination MAC addresses have
5860 * overlap in the header with 4B alignment, the convert
5861 * function will handle them separately and 4 SW actions
5862 * will be created. And 2 actions will be added each
5863 * time no matter how many bytes of address will be set.
5865 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5867 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5868 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5869 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5875 /* Count all modify-header actions as one action. */
5876 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5878 action_flags |= actions->type ==
5879 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5880 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5881 MLX5_FLOW_ACTION_SET_IPV4_DST;
5882 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5884 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5885 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5886 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5892 if (item_ipv6_proto == IPPROTO_ICMPV6)
5893 return rte_flow_error_set(error, ENOTSUP,
5894 RTE_FLOW_ERROR_TYPE_ACTION,
5896 "Can't change header "
5897 "with ICMPv6 proto");
5898 /* Count all modify-header actions as one action. */
5899 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5901 action_flags |= actions->type ==
5902 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5903 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5904 MLX5_FLOW_ACTION_SET_IPV6_DST;
5905 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5907 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5908 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5909 ret = flow_dv_validate_action_modify_tp(action_flags,
5915 /* Count all modify-header actions as one action. */
5916 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5918 action_flags |= actions->type ==
5919 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5920 MLX5_FLOW_ACTION_SET_TP_SRC :
5921 MLX5_FLOW_ACTION_SET_TP_DST;
5922 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5924 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5925 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5926 ret = flow_dv_validate_action_modify_ttl(action_flags,
5932 /* Count all modify-header actions as one action. */
5933 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5935 action_flags |= actions->type ==
5936 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5937 MLX5_FLOW_ACTION_SET_TTL :
5938 MLX5_FLOW_ACTION_DEC_TTL;
5939 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5941 case RTE_FLOW_ACTION_TYPE_JUMP:
5942 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5949 action_flags |= MLX5_FLOW_ACTION_JUMP;
5951 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5952 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5953 ret = flow_dv_validate_action_modify_tcp_seq
5960 /* Count all modify-header actions as one action. */
5961 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5963 action_flags |= actions->type ==
5964 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5965 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5966 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5967 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5969 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5970 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5971 ret = flow_dv_validate_action_modify_tcp_ack
5978 /* Count all modify-header actions as one action. */
5979 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5981 action_flags |= actions->type ==
5982 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5983 MLX5_FLOW_ACTION_INC_TCP_ACK :
5984 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5985 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5987 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5989 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5990 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5991 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5993 case RTE_FLOW_ACTION_TYPE_METER:
5994 ret = mlx5_flow_validate_action_meter(dev,
6000 action_flags |= MLX5_FLOW_ACTION_METER;
6002 /* Meter action will add one more TAG action. */
6003 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6005 case RTE_FLOW_ACTION_TYPE_AGE:
6006 ret = flow_dv_validate_action_age(action_flags,
6011 action_flags |= MLX5_FLOW_ACTION_AGE;
6014 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6015 ret = flow_dv_validate_action_modify_ipv4_dscp
6022 /* Count all modify-header actions as one action. */
6023 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6025 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6026 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6028 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6029 ret = flow_dv_validate_action_modify_ipv6_dscp
6036 /* Count all modify-header actions as one action. */
6037 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6039 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6040 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6042 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6043 ret = flow_dv_validate_action_sample(action_flags,
6048 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6051 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6052 if (actions[0].type != (typeof(actions[0].type))
6053 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6054 return rte_flow_error_set
6056 RTE_FLOW_ERROR_TYPE_ACTION,
6057 NULL, "MLX5 private action "
6058 "must be the first");
6060 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6063 return rte_flow_error_set(error, ENOTSUP,
6064 RTE_FLOW_ERROR_TYPE_ACTION,
6066 "action not supported");
6070 * Validate actions in flow rules
6071 * - Explicit decap action is prohibited by the tunnel offload API.
6072 * - Drop action in tunnel steer rule is prohibited by the API.
6073 * - Application cannot use MARK action because it's value can mask
6074 * tunnel default miss nitification.
6075 * - JUMP in tunnel match rule has no support in current PMD
6077 * - TAG & META are reserved for future uses.
6079 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6080 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6081 MLX5_FLOW_ACTION_MARK |
6082 MLX5_FLOW_ACTION_SET_TAG |
6083 MLX5_FLOW_ACTION_SET_META |
6084 MLX5_FLOW_ACTION_DROP;
6086 if (action_flags & bad_actions_mask)
6087 return rte_flow_error_set
6089 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6090 "Invalid RTE action in tunnel "
6092 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6093 return rte_flow_error_set
6095 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6096 "tunnel set decap rule must terminate "
6099 return rte_flow_error_set
6101 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6102 "tunnel flows for ingress traffic only");
6104 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6105 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6106 MLX5_FLOW_ACTION_MARK |
6107 MLX5_FLOW_ACTION_SET_TAG |
6108 MLX5_FLOW_ACTION_SET_META;
6110 if (action_flags & bad_actions_mask)
6111 return rte_flow_error_set
6113 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6114 "Invalid RTE action in tunnel "
6118 * Validate the drop action mutual exclusion with other actions.
6119 * Drop action is mutually-exclusive with any other action, except for
6122 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6123 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6124 return rte_flow_error_set(error, EINVAL,
6125 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6126 "Drop action is mutually-exclusive "
6127 "with any other action, except for "
6129 /* Eswitch has few restrictions on using items and actions */
6130 if (attr->transfer) {
6131 if (!mlx5_flow_ext_mreg_supported(dev) &&
6132 action_flags & MLX5_FLOW_ACTION_FLAG)
6133 return rte_flow_error_set(error, ENOTSUP,
6134 RTE_FLOW_ERROR_TYPE_ACTION,
6136 "unsupported action FLAG");
6137 if (!mlx5_flow_ext_mreg_supported(dev) &&
6138 action_flags & MLX5_FLOW_ACTION_MARK)
6139 return rte_flow_error_set(error, ENOTSUP,
6140 RTE_FLOW_ERROR_TYPE_ACTION,
6142 "unsupported action MARK");
6143 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6144 return rte_flow_error_set(error, ENOTSUP,
6145 RTE_FLOW_ERROR_TYPE_ACTION,
6147 "unsupported action QUEUE");
6148 if (action_flags & MLX5_FLOW_ACTION_RSS)
6149 return rte_flow_error_set(error, ENOTSUP,
6150 RTE_FLOW_ERROR_TYPE_ACTION,
6152 "unsupported action RSS");
6153 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6154 return rte_flow_error_set(error, EINVAL,
6155 RTE_FLOW_ERROR_TYPE_ACTION,
6157 "no fate action is found");
6159 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6160 return rte_flow_error_set(error, EINVAL,
6161 RTE_FLOW_ERROR_TYPE_ACTION,
6163 "no fate action is found");
6166 * Continue validation for Xcap and VLAN actions.
6167 * If hairpin is working in explicit TX rule mode, there is no actions
6168 * splitting and the validation of hairpin ingress flow should be the
6169 * same as other standard flows.
6171 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6172 MLX5_FLOW_VLAN_ACTIONS)) &&
6173 (queue_index == 0xFFFF ||
6174 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6175 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6176 conf->tx_explicit != 0))) {
6177 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6178 MLX5_FLOW_XCAP_ACTIONS)
6179 return rte_flow_error_set(error, ENOTSUP,
6180 RTE_FLOW_ERROR_TYPE_ACTION,
6181 NULL, "encap and decap "
6182 "combination aren't supported");
6183 if (!attr->transfer && attr->ingress) {
6184 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6185 return rte_flow_error_set
6187 RTE_FLOW_ERROR_TYPE_ACTION,
6188 NULL, "encap is not supported"
6189 " for ingress traffic");
6190 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6191 return rte_flow_error_set
6193 RTE_FLOW_ERROR_TYPE_ACTION,
6194 NULL, "push VLAN action not "
6195 "supported for ingress");
6196 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6197 MLX5_FLOW_VLAN_ACTIONS)
6198 return rte_flow_error_set
6200 RTE_FLOW_ERROR_TYPE_ACTION,
6201 NULL, "no support for "
6202 "multiple VLAN actions");
6206 * Hairpin flow will add one more TAG action in TX implicit mode.
6207 * In TX explicit mode, there will be no hairpin flow ID.
6210 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6211 /* extra metadata enabled: one more TAG action will be add. */
6212 if (dev_conf->dv_flow_en &&
6213 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6214 mlx5_flow_ext_mreg_supported(dev))
6215 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6216 if ((uint32_t)rw_act_num >
6217 flow_dv_modify_hdr_action_max(dev, is_root)) {
6218 return rte_flow_error_set(error, ENOTSUP,
6219 RTE_FLOW_ERROR_TYPE_ACTION,
6220 NULL, "too many header modify"
6221 " actions to support");
6227 * Internal preparation function. Allocates the DV flow size,
6228 * this size is constant.
6231 * Pointer to the rte_eth_dev structure.
6233 * Pointer to the flow attributes.
6235 * Pointer to the list of items.
6236 * @param[in] actions
6237 * Pointer to the list of actions.
6239 * Pointer to the error structure.
6242 * Pointer to mlx5_flow object on success,
6243 * otherwise NULL and rte_errno is set.
6245 static struct mlx5_flow *
6246 flow_dv_prepare(struct rte_eth_dev *dev,
6247 const struct rte_flow_attr *attr __rte_unused,
6248 const struct rte_flow_item items[] __rte_unused,
6249 const struct rte_flow_action actions[] __rte_unused,
6250 struct rte_flow_error *error)
6252 uint32_t handle_idx = 0;
6253 struct mlx5_flow *dev_flow;
6254 struct mlx5_flow_handle *dev_handle;
6255 struct mlx5_priv *priv = dev->data->dev_private;
6256 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6259 /* In case of corrupting the memory. */
6260 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6261 rte_flow_error_set(error, ENOSPC,
6262 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6263 "not free temporary device flow");
6266 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6269 rte_flow_error_set(error, ENOMEM,
6270 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6271 "not enough memory to create flow handle");
6274 MLX5_ASSERT(wks->flow_idx + 1 < RTE_DIM(wks->flows));
6275 dev_flow = &wks->flows[wks->flow_idx++];
6276 dev_flow->handle = dev_handle;
6277 dev_flow->handle_idx = handle_idx;
6279 * In some old rdma-core releases, before continuing, a check of the
6280 * length of matching parameter will be done at first. It needs to use
6281 * the length without misc4 param. If the flow has misc4 support, then
6282 * the length needs to be adjusted accordingly. Each param member is
6283 * aligned with a 64B boundary naturally.
6285 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6286 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6288 * The matching value needs to be cleared to 0 before using. In the
6289 * past, it will be automatically cleared when using rte_*alloc
6290 * API. The time consumption will be almost the same as before.
6292 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6293 dev_flow->ingress = attr->ingress;
6294 dev_flow->dv.transfer = attr->transfer;
6298 #ifdef RTE_LIBRTE_MLX5_DEBUG
6300 * Sanity check for match mask and value. Similar to check_valid_spec() in
6301 * kernel driver. If unmasked bit is present in value, it returns failure.
6304 * pointer to match mask buffer.
6305 * @param match_value
6306 * pointer to match value buffer.
6309 * 0 if valid, -EINVAL otherwise.
6312 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6314 uint8_t *m = match_mask;
6315 uint8_t *v = match_value;
6318 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6321 "match_value differs from match_criteria"
6322 " %p[%u] != %p[%u]",
6323 match_value, i, match_mask, i);
6332 * Add match of ip_version.
6336 * @param[in] headers_v
6337 * Values header pointer.
6338 * @param[in] headers_m
6339 * Masks header pointer.
6340 * @param[in] ip_version
6341 * The IP version to set.
6344 flow_dv_set_match_ip_version(uint32_t group,
6350 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6352 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6354 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6356 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6360 * Add Ethernet item to matcher and to the value.
6362 * @param[in, out] matcher
6364 * @param[in, out] key
6365 * Flow matcher value.
6367 * Flow pattern to translate.
6369 * Item is inner pattern.
6372 flow_dv_translate_item_eth(void *matcher, void *key,
6373 const struct rte_flow_item *item, int inner,
6376 const struct rte_flow_item_eth *eth_m = item->mask;
6377 const struct rte_flow_item_eth *eth_v = item->spec;
6378 const struct rte_flow_item_eth nic_mask = {
6379 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6380 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6381 .type = RTE_BE16(0xffff),
6394 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6396 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6398 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6400 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6402 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6403 ð_m->dst, sizeof(eth_m->dst));
6404 /* The value must be in the range of the mask. */
6405 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6406 for (i = 0; i < sizeof(eth_m->dst); ++i)
6407 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6408 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6409 ð_m->src, sizeof(eth_m->src));
6410 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6411 /* The value must be in the range of the mask. */
6412 for (i = 0; i < sizeof(eth_m->dst); ++i)
6413 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6415 * HW supports match on one Ethertype, the Ethertype following the last
6416 * VLAN tag of the packet (see PRM).
6417 * Set match on ethertype only if ETH header is not followed by VLAN.
6418 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6419 * ethertype, and use ip_version field instead.
6420 * eCPRI over Ether layer will use type value 0xAEFE.
6422 if (eth_m->type == 0xFFFF) {
6423 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6424 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6425 switch (eth_v->type) {
6426 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6427 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6429 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6430 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6431 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6433 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6434 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6436 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6437 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6443 if (eth_m->has_vlan) {
6444 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6445 if (eth_v->has_vlan) {
6447 * Here, when also has_more_vlan field in VLAN item is
6448 * not set, only single-tagged packets will be matched.
6450 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6454 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6455 rte_be_to_cpu_16(eth_m->type));
6456 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6457 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6461 * Add VLAN item to matcher and to the value.
6463 * @param[in, out] dev_flow
6465 * @param[in, out] matcher
6467 * @param[in, out] key
6468 * Flow matcher value.
6470 * Flow pattern to translate.
6472 * Item is inner pattern.
6475 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6476 void *matcher, void *key,
6477 const struct rte_flow_item *item,
6478 int inner, uint32_t group)
6480 const struct rte_flow_item_vlan *vlan_m = item->mask;
6481 const struct rte_flow_item_vlan *vlan_v = item->spec;
6488 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6490 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6492 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6494 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6496 * This is workaround, masks are not supported,
6497 * and pre-validated.
6500 dev_flow->handle->vf_vlan.tag =
6501 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6504 * When VLAN item exists in flow, mark packet as tagged,
6505 * even if TCI is not specified.
6507 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6508 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6509 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6514 vlan_m = &rte_flow_item_vlan_mask;
6515 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6516 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6517 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6518 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6519 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6520 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6521 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6522 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6524 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6525 * ethertype, and use ip_version field instead.
6527 if (vlan_m->inner_type == 0xFFFF) {
6528 switch (vlan_v->inner_type) {
6529 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6530 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6531 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6532 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6534 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6535 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6537 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6538 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6544 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6545 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6546 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6547 /* Only one vlan_tag bit can be set. */
6548 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6551 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6552 rte_be_to_cpu_16(vlan_m->inner_type));
6553 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6554 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6558 * Add IPV4 item to matcher and to the value.
6560 * @param[in, out] matcher
6562 * @param[in, out] key
6563 * Flow matcher value.
6565 * Flow pattern to translate.
6567 * Item is inner pattern.
6569 * The group to insert the rule.
6572 flow_dv_translate_item_ipv4(void *matcher, void *key,
6573 const struct rte_flow_item *item,
6574 int inner, uint32_t group)
6576 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6577 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6578 const struct rte_flow_item_ipv4 nic_mask = {
6580 .src_addr = RTE_BE32(0xffffffff),
6581 .dst_addr = RTE_BE32(0xffffffff),
6582 .type_of_service = 0xff,
6583 .next_proto_id = 0xff,
6584 .time_to_live = 0xff,
6594 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6596 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6598 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6600 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6602 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6607 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6608 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6609 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6610 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6611 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6612 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6613 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6614 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6615 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6616 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6617 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6618 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6619 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6621 ipv4_m->hdr.type_of_service);
6622 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6623 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6624 ipv4_m->hdr.type_of_service >> 2);
6625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6626 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6627 ipv4_m->hdr.next_proto_id);
6628 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6629 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6630 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6631 ipv4_m->hdr.time_to_live);
6632 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6633 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6634 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6635 !!(ipv4_m->hdr.fragment_offset));
6636 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6637 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6641 * Add IPV6 item to matcher and to the value.
6643 * @param[in, out] matcher
6645 * @param[in, out] key
6646 * Flow matcher value.
6648 * Flow pattern to translate.
6650 * Item is inner pattern.
6652 * The group to insert the rule.
6655 flow_dv_translate_item_ipv6(void *matcher, void *key,
6656 const struct rte_flow_item *item,
6657 int inner, uint32_t group)
6659 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6660 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6661 const struct rte_flow_item_ipv6 nic_mask = {
6664 "\xff\xff\xff\xff\xff\xff\xff\xff"
6665 "\xff\xff\xff\xff\xff\xff\xff\xff",
6667 "\xff\xff\xff\xff\xff\xff\xff\xff"
6668 "\xff\xff\xff\xff\xff\xff\xff\xff",
6669 .vtc_flow = RTE_BE32(0xffffffff),
6676 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6677 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6686 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6688 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6690 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6692 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6694 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6699 size = sizeof(ipv6_m->hdr.dst_addr);
6700 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6701 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6702 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6703 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6704 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6705 for (i = 0; i < size; ++i)
6706 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6707 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6708 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6709 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6710 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6711 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6712 for (i = 0; i < size; ++i)
6713 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6715 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6716 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6717 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6718 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6719 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6720 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6723 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6725 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6728 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6730 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6734 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6737 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6739 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6740 ipv6_m->hdr.hop_limits);
6741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6742 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6743 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6744 !!(ipv6_m->has_frag_ext));
6745 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6746 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6750 * Add IPV6 fragment extension item to matcher and to the value.
6752 * @param[in, out] matcher
6754 * @param[in, out] key
6755 * Flow matcher value.
6757 * Flow pattern to translate.
6759 * Item is inner pattern.
6762 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6763 const struct rte_flow_item *item,
6766 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6767 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6768 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6770 .next_header = 0xff,
6771 .frag_data = RTE_BE16(0xffff),
6778 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6780 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6782 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6784 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6786 /* IPv6 fragment extension item exists, so packet is IP fragment. */
6787 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6788 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6789 if (!ipv6_frag_ext_v)
6791 if (!ipv6_frag_ext_m)
6792 ipv6_frag_ext_m = &nic_mask;
6793 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6794 ipv6_frag_ext_m->hdr.next_header);
6795 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6796 ipv6_frag_ext_v->hdr.next_header &
6797 ipv6_frag_ext_m->hdr.next_header);
6801 * Add TCP item to matcher and to the value.
6803 * @param[in, out] matcher
6805 * @param[in, out] key
6806 * Flow matcher value.
6808 * Flow pattern to translate.
6810 * Item is inner pattern.
6813 flow_dv_translate_item_tcp(void *matcher, void *key,
6814 const struct rte_flow_item *item,
6817 const struct rte_flow_item_tcp *tcp_m = item->mask;
6818 const struct rte_flow_item_tcp *tcp_v = item->spec;
6823 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6825 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6829 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6831 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6832 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6836 tcp_m = &rte_flow_item_tcp_mask;
6837 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6838 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6839 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6840 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6841 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6842 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6843 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6844 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6845 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6846 tcp_m->hdr.tcp_flags);
6847 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6848 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6852 * Add UDP item to matcher and to the value.
6854 * @param[in, out] matcher
6856 * @param[in, out] key
6857 * Flow matcher value.
6859 * Flow pattern to translate.
6861 * Item is inner pattern.
6864 flow_dv_translate_item_udp(void *matcher, void *key,
6865 const struct rte_flow_item *item,
6868 const struct rte_flow_item_udp *udp_m = item->mask;
6869 const struct rte_flow_item_udp *udp_v = item->spec;
6874 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6876 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6878 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6880 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6882 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6883 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6887 udp_m = &rte_flow_item_udp_mask;
6888 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6889 rte_be_to_cpu_16(udp_m->hdr.src_port));
6890 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6891 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6892 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6893 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6894 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6895 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6899 * Add GRE optional Key item to matcher and to the value.
6901 * @param[in, out] matcher
6903 * @param[in, out] key
6904 * Flow matcher value.
6906 * Flow pattern to translate.
6908 * Item is inner pattern.
6911 flow_dv_translate_item_gre_key(void *matcher, void *key,
6912 const struct rte_flow_item *item)
6914 const rte_be32_t *key_m = item->mask;
6915 const rte_be32_t *key_v = item->spec;
6916 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6917 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6918 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6920 /* GRE K bit must be on and should already be validated */
6921 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6922 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6926 key_m = &gre_key_default_mask;
6927 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6928 rte_be_to_cpu_32(*key_m) >> 8);
6929 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6930 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6931 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6932 rte_be_to_cpu_32(*key_m) & 0xFF);
6933 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6934 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6938 * Add GRE item to matcher and to the value.
6940 * @param[in, out] matcher
6942 * @param[in, out] key
6943 * Flow matcher value.
6945 * Flow pattern to translate.
6947 * Item is inner pattern.
6950 flow_dv_translate_item_gre(void *matcher, void *key,
6951 const struct rte_flow_item *item,
6954 const struct rte_flow_item_gre *gre_m = item->mask;
6955 const struct rte_flow_item_gre *gre_v = item->spec;
6958 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6959 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6966 uint16_t s_present:1;
6967 uint16_t k_present:1;
6968 uint16_t rsvd_bit1:1;
6969 uint16_t c_present:1;
6973 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6976 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6978 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6980 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6982 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6984 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6985 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6989 gre_m = &rte_flow_item_gre_mask;
6990 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6991 rte_be_to_cpu_16(gre_m->protocol));
6992 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6993 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6994 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6995 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6996 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6997 gre_crks_rsvd0_ver_m.c_present);
6998 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6999 gre_crks_rsvd0_ver_v.c_present &
7000 gre_crks_rsvd0_ver_m.c_present);
7001 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7002 gre_crks_rsvd0_ver_m.k_present);
7003 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7004 gre_crks_rsvd0_ver_v.k_present &
7005 gre_crks_rsvd0_ver_m.k_present);
7006 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7007 gre_crks_rsvd0_ver_m.s_present);
7008 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7009 gre_crks_rsvd0_ver_v.s_present &
7010 gre_crks_rsvd0_ver_m.s_present);
7014 * Add NVGRE item to matcher and to the value.
7016 * @param[in, out] matcher
7018 * @param[in, out] key
7019 * Flow matcher value.
7021 * Flow pattern to translate.
7023 * Item is inner pattern.
7026 flow_dv_translate_item_nvgre(void *matcher, void *key,
7027 const struct rte_flow_item *item,
7030 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7031 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7032 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7033 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7034 const char *tni_flow_id_m;
7035 const char *tni_flow_id_v;
7041 /* For NVGRE, GRE header fields must be set with defined values. */
7042 const struct rte_flow_item_gre gre_spec = {
7043 .c_rsvd0_ver = RTE_BE16(0x2000),
7044 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7046 const struct rte_flow_item_gre gre_mask = {
7047 .c_rsvd0_ver = RTE_BE16(0xB000),
7048 .protocol = RTE_BE16(UINT16_MAX),
7050 const struct rte_flow_item gre_item = {
7055 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7059 nvgre_m = &rte_flow_item_nvgre_mask;
7060 tni_flow_id_m = (const char *)nvgre_m->tni;
7061 tni_flow_id_v = (const char *)nvgre_v->tni;
7062 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7063 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7064 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7065 memcpy(gre_key_m, tni_flow_id_m, size);
7066 for (i = 0; i < size; ++i)
7067 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7071 * Add VXLAN item to matcher and to the value.
7073 * @param[in, out] matcher
7075 * @param[in, out] key
7076 * Flow matcher value.
7078 * Flow pattern to translate.
7080 * Item is inner pattern.
7083 flow_dv_translate_item_vxlan(void *matcher, void *key,
7084 const struct rte_flow_item *item,
7087 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7088 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7091 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7092 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7100 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7102 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7104 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7106 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7108 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7109 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7110 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7111 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7112 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7117 vxlan_m = &rte_flow_item_vxlan_mask;
7118 size = sizeof(vxlan_m->vni);
7119 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7120 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7121 memcpy(vni_m, vxlan_m->vni, size);
7122 for (i = 0; i < size; ++i)
7123 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7127 * Add VXLAN-GPE item to matcher and to the value.
7129 * @param[in, out] matcher
7131 * @param[in, out] key
7132 * Flow matcher value.
7134 * Flow pattern to translate.
7136 * Item is inner pattern.
7140 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7141 const struct rte_flow_item *item, int inner)
7143 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7144 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7148 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7150 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7156 uint8_t flags_m = 0xff;
7157 uint8_t flags_v = 0xc;
7160 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7162 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7164 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7166 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7168 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7169 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7170 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7177 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7178 size = sizeof(vxlan_m->vni);
7179 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7180 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7181 memcpy(vni_m, vxlan_m->vni, size);
7182 for (i = 0; i < size; ++i)
7183 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7184 if (vxlan_m->flags) {
7185 flags_m = vxlan_m->flags;
7186 flags_v = vxlan_v->flags;
7188 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7189 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7190 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7192 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7197 * Add Geneve item to matcher and to the value.
7199 * @param[in, out] matcher
7201 * @param[in, out] key
7202 * Flow matcher value.
7204 * Flow pattern to translate.
7206 * Item is inner pattern.
7210 flow_dv_translate_item_geneve(void *matcher, void *key,
7211 const struct rte_flow_item *item, int inner)
7213 const struct rte_flow_item_geneve *geneve_m = item->mask;
7214 const struct rte_flow_item_geneve *geneve_v = item->spec;
7217 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7218 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7227 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7229 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7231 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7233 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7235 dport = MLX5_UDP_PORT_GENEVE;
7236 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7237 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7238 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7243 geneve_m = &rte_flow_item_geneve_mask;
7244 size = sizeof(geneve_m->vni);
7245 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7246 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7247 memcpy(vni_m, geneve_m->vni, size);
7248 for (i = 0; i < size; ++i)
7249 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7250 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7251 rte_be_to_cpu_16(geneve_m->protocol));
7252 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7253 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7254 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7255 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7256 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7257 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7258 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7259 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7260 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7261 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7262 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7263 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7264 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7268 * Add MPLS item to matcher and to the value.
7270 * @param[in, out] matcher
7272 * @param[in, out] key
7273 * Flow matcher value.
7275 * Flow pattern to translate.
7276 * @param[in] prev_layer
7277 * The protocol layer indicated in previous item.
7279 * Item is inner pattern.
7282 flow_dv_translate_item_mpls(void *matcher, void *key,
7283 const struct rte_flow_item *item,
7284 uint64_t prev_layer,
7287 const uint32_t *in_mpls_m = item->mask;
7288 const uint32_t *in_mpls_v = item->spec;
7289 uint32_t *out_mpls_m = 0;
7290 uint32_t *out_mpls_v = 0;
7291 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7292 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7293 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7295 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7296 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7297 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7299 switch (prev_layer) {
7300 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7301 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7302 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7303 MLX5_UDP_PORT_MPLS);
7305 case MLX5_FLOW_LAYER_GRE:
7306 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7307 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7308 RTE_ETHER_TYPE_MPLS);
7311 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7312 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7319 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7320 switch (prev_layer) {
7321 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7323 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7324 outer_first_mpls_over_udp);
7326 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7327 outer_first_mpls_over_udp);
7329 case MLX5_FLOW_LAYER_GRE:
7331 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7332 outer_first_mpls_over_gre);
7334 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7335 outer_first_mpls_over_gre);
7338 /* Inner MPLS not over GRE is not supported. */
7341 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7345 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7351 if (out_mpls_m && out_mpls_v) {
7352 *out_mpls_m = *in_mpls_m;
7353 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7358 * Add metadata register item to matcher
7360 * @param[in, out] matcher
7362 * @param[in, out] key
7363 * Flow matcher value.
7364 * @param[in] reg_type
7365 * Type of device metadata register
7372 flow_dv_match_meta_reg(void *matcher, void *key,
7373 enum modify_reg reg_type,
7374 uint32_t data, uint32_t mask)
7377 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7379 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7385 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7386 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7389 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7390 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7394 * The metadata register C0 field might be divided into
7395 * source vport index and META item value, we should set
7396 * this field according to specified mask, not as whole one.
7398 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7400 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7401 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7404 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7407 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7408 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7411 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7412 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7415 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7416 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7419 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7420 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7423 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7424 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7427 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7428 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7431 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7432 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7441 * Add MARK item to matcher
7444 * The device to configure through.
7445 * @param[in, out] matcher
7447 * @param[in, out] key
7448 * Flow matcher value.
7450 * Flow pattern to translate.
7453 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7454 void *matcher, void *key,
7455 const struct rte_flow_item *item)
7457 struct mlx5_priv *priv = dev->data->dev_private;
7458 const struct rte_flow_item_mark *mark;
7462 mark = item->mask ? (const void *)item->mask :
7463 &rte_flow_item_mark_mask;
7464 mask = mark->id & priv->sh->dv_mark_mask;
7465 mark = (const void *)item->spec;
7467 value = mark->id & priv->sh->dv_mark_mask & mask;
7469 enum modify_reg reg;
7471 /* Get the metadata register index for the mark. */
7472 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7473 MLX5_ASSERT(reg > 0);
7474 if (reg == REG_C_0) {
7475 struct mlx5_priv *priv = dev->data->dev_private;
7476 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7477 uint32_t shl_c0 = rte_bsf32(msk_c0);
7483 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7488 * Add META item to matcher
7491 * The devich to configure through.
7492 * @param[in, out] matcher
7494 * @param[in, out] key
7495 * Flow matcher value.
7497 * Attributes of flow that includes this item.
7499 * Flow pattern to translate.
7502 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7503 void *matcher, void *key,
7504 const struct rte_flow_attr *attr,
7505 const struct rte_flow_item *item)
7507 const struct rte_flow_item_meta *meta_m;
7508 const struct rte_flow_item_meta *meta_v;
7510 meta_m = (const void *)item->mask;
7512 meta_m = &rte_flow_item_meta_mask;
7513 meta_v = (const void *)item->spec;
7516 uint32_t value = meta_v->data;
7517 uint32_t mask = meta_m->data;
7519 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7523 * In datapath code there is no endianness
7524 * coversions for perfromance reasons, all
7525 * pattern conversions are done in rte_flow.
7527 value = rte_cpu_to_be_32(value);
7528 mask = rte_cpu_to_be_32(mask);
7529 if (reg == REG_C_0) {
7530 struct mlx5_priv *priv = dev->data->dev_private;
7531 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7532 uint32_t shl_c0 = rte_bsf32(msk_c0);
7533 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7534 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7541 MLX5_ASSERT(msk_c0);
7542 MLX5_ASSERT(!(~msk_c0 & mask));
7544 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7549 * Add vport metadata Reg C0 item to matcher
7551 * @param[in, out] matcher
7553 * @param[in, out] key
7554 * Flow matcher value.
7556 * Flow pattern to translate.
7559 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7560 uint32_t value, uint32_t mask)
7562 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7566 * Add tag item to matcher
7569 * The devich to configure through.
7570 * @param[in, out] matcher
7572 * @param[in, out] key
7573 * Flow matcher value.
7575 * Flow pattern to translate.
7578 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7579 void *matcher, void *key,
7580 const struct rte_flow_item *item)
7582 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7583 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7584 uint32_t mask, value;
7587 value = tag_v->data;
7588 mask = tag_m ? tag_m->data : UINT32_MAX;
7589 if (tag_v->id == REG_C_0) {
7590 struct mlx5_priv *priv = dev->data->dev_private;
7591 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7592 uint32_t shl_c0 = rte_bsf32(msk_c0);
7598 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7602 * Add TAG item to matcher
7605 * The devich to configure through.
7606 * @param[in, out] matcher
7608 * @param[in, out] key
7609 * Flow matcher value.
7611 * Flow pattern to translate.
7614 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7615 void *matcher, void *key,
7616 const struct rte_flow_item *item)
7618 const struct rte_flow_item_tag *tag_v = item->spec;
7619 const struct rte_flow_item_tag *tag_m = item->mask;
7620 enum modify_reg reg;
7623 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7624 /* Get the metadata register index for the tag. */
7625 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7626 MLX5_ASSERT(reg > 0);
7627 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7631 * Add source vport match to the specified matcher.
7633 * @param[in, out] matcher
7635 * @param[in, out] key
7636 * Flow matcher value.
7638 * Source vport value to match
7643 flow_dv_translate_item_source_vport(void *matcher, void *key,
7644 int16_t port, uint16_t mask)
7646 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7647 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7649 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7650 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7654 * Translate port-id item to eswitch match on port-id.
7657 * The devich to configure through.
7658 * @param[in, out] matcher
7660 * @param[in, out] key
7661 * Flow matcher value.
7663 * Flow pattern to translate.
7666 * 0 on success, a negative errno value otherwise.
7669 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7670 void *key, const struct rte_flow_item *item)
7672 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7673 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7674 struct mlx5_priv *priv;
7677 mask = pid_m ? pid_m->id : 0xffff;
7678 id = pid_v ? pid_v->id : dev->data->port_id;
7679 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7682 /* Translate to vport field or to metadata, depending on mode. */
7683 if (priv->vport_meta_mask)
7684 flow_dv_translate_item_meta_vport(matcher, key,
7685 priv->vport_meta_tag,
7686 priv->vport_meta_mask);
7688 flow_dv_translate_item_source_vport(matcher, key,
7689 priv->vport_id, mask);
7694 * Add ICMP6 item to matcher and to the value.
7696 * @param[in, out] matcher
7698 * @param[in, out] key
7699 * Flow matcher value.
7701 * Flow pattern to translate.
7703 * Item is inner pattern.
7706 flow_dv_translate_item_icmp6(void *matcher, void *key,
7707 const struct rte_flow_item *item,
7710 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7711 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7714 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7716 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7718 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7720 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7722 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7724 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7731 icmp6_m = &rte_flow_item_icmp6_mask;
7732 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7733 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7734 icmp6_v->type & icmp6_m->type);
7735 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7736 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7737 icmp6_v->code & icmp6_m->code);
7741 * Add ICMP item to matcher and to the value.
7743 * @param[in, out] matcher
7745 * @param[in, out] key
7746 * Flow matcher value.
7748 * Flow pattern to translate.
7750 * Item is inner pattern.
7753 flow_dv_translate_item_icmp(void *matcher, void *key,
7754 const struct rte_flow_item *item,
7757 const struct rte_flow_item_icmp *icmp_m = item->mask;
7758 const struct rte_flow_item_icmp *icmp_v = item->spec;
7759 uint32_t icmp_header_data_m = 0;
7760 uint32_t icmp_header_data_v = 0;
7763 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7765 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7767 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7769 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7771 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7773 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7775 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7776 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7780 icmp_m = &rte_flow_item_icmp_mask;
7781 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7782 icmp_m->hdr.icmp_type);
7783 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7784 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7785 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7786 icmp_m->hdr.icmp_code);
7787 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7788 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7789 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7790 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7791 if (icmp_header_data_m) {
7792 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7793 icmp_header_data_v |=
7794 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7795 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7796 icmp_header_data_m);
7797 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7798 icmp_header_data_v & icmp_header_data_m);
7803 * Add GTP item to matcher and to the value.
7805 * @param[in, out] matcher
7807 * @param[in, out] key
7808 * Flow matcher value.
7810 * Flow pattern to translate.
7812 * Item is inner pattern.
7815 flow_dv_translate_item_gtp(void *matcher, void *key,
7816 const struct rte_flow_item *item, int inner)
7818 const struct rte_flow_item_gtp *gtp_m = item->mask;
7819 const struct rte_flow_item_gtp *gtp_v = item->spec;
7822 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7824 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7825 uint16_t dport = RTE_GTPU_UDP_PORT;
7828 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7830 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7832 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7834 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7836 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7837 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7838 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7843 gtp_m = &rte_flow_item_gtp_mask;
7844 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7845 gtp_m->v_pt_rsv_flags);
7846 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7847 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7848 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7849 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7850 gtp_v->msg_type & gtp_m->msg_type);
7851 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7852 rte_be_to_cpu_32(gtp_m->teid));
7853 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7854 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7858 * Add eCPRI item to matcher and to the value.
7861 * The devich to configure through.
7862 * @param[in, out] matcher
7864 * @param[in, out] key
7865 * Flow matcher value.
7867 * Flow pattern to translate.
7868 * @param[in] samples
7869 * Sample IDs to be used in the matching.
7872 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7873 void *key, const struct rte_flow_item *item)
7875 struct mlx5_priv *priv = dev->data->dev_private;
7876 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7877 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7878 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7880 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7888 ecpri_m = &rte_flow_item_ecpri_mask;
7890 * Maximal four DW samples are supported in a single matching now.
7891 * Two are used now for a eCPRI matching:
7892 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7893 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7896 if (!ecpri_m->hdr.common.u32)
7898 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7899 /* Need to take the whole DW as the mask to fill the entry. */
7900 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7901 prog_sample_field_value_0);
7902 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7903 prog_sample_field_value_0);
7904 /* Already big endian (network order) in the header. */
7905 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7906 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7907 /* Sample#0, used for matching type, offset 0. */
7908 MLX5_SET(fte_match_set_misc4, misc4_m,
7909 prog_sample_field_id_0, samples[0]);
7910 /* It makes no sense to set the sample ID in the mask field. */
7911 MLX5_SET(fte_match_set_misc4, misc4_v,
7912 prog_sample_field_id_0, samples[0]);
7914 * Checking if message body part needs to be matched.
7915 * Some wildcard rules only matching type field should be supported.
7917 if (ecpri_m->hdr.dummy[0]) {
7918 switch (ecpri_v->hdr.common.type) {
7919 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7920 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7921 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7922 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7923 prog_sample_field_value_1);
7924 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7925 prog_sample_field_value_1);
7926 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7927 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7928 /* Sample#1, to match message body, offset 4. */
7929 MLX5_SET(fte_match_set_misc4, misc4_m,
7930 prog_sample_field_id_1, samples[1]);
7931 MLX5_SET(fte_match_set_misc4, misc4_v,
7932 prog_sample_field_id_1, samples[1]);
7935 /* Others, do not match any sample ID. */
7941 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7943 #define HEADER_IS_ZERO(match_criteria, headers) \
7944 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7945 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7948 * Calculate flow matcher enable bitmap.
7950 * @param match_criteria
7951 * Pointer to flow matcher criteria.
7954 * Bitmap of enabled fields.
7957 flow_dv_matcher_enable(uint32_t *match_criteria)
7959 uint8_t match_criteria_enable;
7961 match_criteria_enable =
7962 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7963 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7964 match_criteria_enable |=
7965 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7966 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7967 match_criteria_enable |=
7968 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7969 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7970 match_criteria_enable |=
7971 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7972 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7973 match_criteria_enable |=
7974 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7975 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7976 match_criteria_enable |=
7977 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7978 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7979 return match_criteria_enable;
7986 * @param[in, out] dev
7987 * Pointer to rte_eth_dev structure.
7988 * @param[in] table_id
7991 * Direction of the table.
7992 * @param[in] transfer
7993 * E-Switch or NIC flow.
7995 * pointer to error structure.
7998 * Returns tables resource based on the index, NULL in case of failed.
8000 static struct mlx5_flow_tbl_resource *
8001 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8002 uint32_t table_id, uint8_t egress,
8005 const struct mlx5_flow_tunnel *tunnel,
8007 struct rte_flow_error *error)
8009 struct mlx5_priv *priv = dev->data->dev_private;
8010 struct mlx5_dev_ctx_shared *sh = priv->sh;
8011 struct mlx5_flow_tbl_resource *tbl;
8012 union mlx5_flow_tbl_key table_key = {
8014 .table_id = table_id,
8016 .domain = !!transfer,
8017 .direction = !!egress,
8020 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
8022 struct mlx5_flow_tbl_data_entry *tbl_data;
8028 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
8030 tbl = &tbl_data->tbl;
8031 __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
8034 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8036 rte_flow_error_set(error, ENOMEM,
8037 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8039 "cannot allocate flow table data entry");
8042 tbl_data->idx = idx;
8043 tbl_data->tunnel = tunnel;
8044 tbl_data->group_id = group_id;
8045 tbl_data->external = external;
8046 tbl = &tbl_data->tbl;
8047 pos = &tbl_data->entry;
8049 domain = sh->fdb_domain;
8051 domain = sh->tx_domain;
8053 domain = sh->rx_domain;
8054 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
8056 rte_flow_error_set(error, ENOMEM,
8057 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8058 NULL, "cannot create flow table object");
8059 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8063 * No multi-threads now, but still better to initialize the reference
8064 * count before insert it into the hash list.
8066 __atomic_store_n(&tbl->refcnt, 0, __ATOMIC_RELAXED);
8067 /* Jump action reference count is initialized here. */
8068 __atomic_store_n(&tbl_data->jump.refcnt, 0, __ATOMIC_RELAXED);
8069 pos->key = table_key.v64;
8070 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
8072 rte_flow_error_set(error, -ret,
8073 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8074 "cannot insert flow table data entry");
8075 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8076 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8078 __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
8083 * Release a flow table.
8086 * Pointer to rte_eth_dev structure.
8088 * Table resource to be released.
8091 * Returns 0 if table was released, else return 1;
8094 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8095 struct mlx5_flow_tbl_resource *tbl)
8097 struct mlx5_priv *priv = dev->data->dev_private;
8098 struct mlx5_dev_ctx_shared *sh = priv->sh;
8099 struct mlx5_flow_tbl_data_entry *tbl_data =
8100 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8104 if (__atomic_sub_fetch(&tbl->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8105 struct mlx5_hlist_entry *pos = &tbl_data->entry;
8107 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8109 if (is_tunnel_offload_active(dev) && tbl_data->external) {
8110 struct mlx5_hlist_entry *he;
8111 struct mlx5_hlist *tunnel_grp_hash;
8112 struct mlx5_flow_tunnel_hub *thub =
8113 mlx5_tunnel_hub(dev);
8114 union tunnel_tbl_key tunnel_key = {
8115 .tunnel_id = tbl_data->tunnel ?
8116 tbl_data->tunnel->tunnel_id : 0,
8117 .group = tbl_data->group_id
8119 union mlx5_flow_tbl_key table_key = {
8122 uint32_t table_id = table_key.table_id;
8124 tunnel_grp_hash = tbl_data->tunnel ?
8125 tbl_data->tunnel->groups :
8127 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val);
8129 struct tunnel_tbl_entry *tte;
8130 tte = container_of(he, typeof(*tte), hash);
8131 MLX5_ASSERT(tte->flow_table == table_id);
8132 mlx5_hlist_remove(tunnel_grp_hash, he);
8135 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TNL_TBL_ID],
8136 tunnel_flow_tbl_to_id(table_id));
8138 "port %u release table_id %#x tunnel %u group %u",
8139 dev->data->port_id, table_id,
8141 tbl_data->tunnel->tunnel_id : 0,
8142 tbl_data->group_id);
8144 /* remove the entry from the hash list and free memory. */
8145 mlx5_hlist_remove(sh->flow_tbls, pos);
8146 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
8154 * Register the flow matcher.
8156 * @param[in, out] dev
8157 * Pointer to rte_eth_dev structure.
8158 * @param[in, out] matcher
8159 * Pointer to flow matcher.
8160 * @param[in, out] key
8161 * Pointer to flow table key.
8162 * @parm[in, out] dev_flow
8163 * Pointer to the dev_flow.
8165 * pointer to error structure.
8168 * 0 on success otherwise -errno and errno is set.
8171 flow_dv_matcher_register(struct rte_eth_dev *dev,
8172 struct mlx5_flow_dv_matcher *matcher,
8173 union mlx5_flow_tbl_key *key,
8174 struct mlx5_flow *dev_flow,
8175 struct rte_flow_error *error)
8177 struct mlx5_priv *priv = dev->data->dev_private;
8178 struct mlx5_dev_ctx_shared *sh = priv->sh;
8179 struct mlx5_flow_dv_matcher *cache_matcher;
8180 struct mlx5dv_flow_matcher_attr dv_attr = {
8181 .type = IBV_FLOW_ATTR_NORMAL,
8182 .match_mask = (void *)&matcher->mask,
8184 struct mlx5_flow_tbl_resource *tbl;
8185 struct mlx5_flow_tbl_data_entry *tbl_data;
8188 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8189 key->domain, false, NULL, 0, error);
8191 return -rte_errno; /* No need to refill the error info */
8192 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8193 /* Lookup from cache. */
8194 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8195 if (matcher->crc == cache_matcher->crc &&
8196 matcher->priority == cache_matcher->priority &&
8197 !memcmp((const void *)matcher->mask.buf,
8198 (const void *)cache_matcher->mask.buf,
8199 cache_matcher->mask.size)) {
8201 "%s group %u priority %hd use %s "
8202 "matcher %p: refcnt %d++",
8203 key->domain ? "FDB" : "NIC", key->table_id,
8204 cache_matcher->priority,
8205 key->direction ? "tx" : "rx",
8206 (void *)cache_matcher,
8207 __atomic_load_n(&cache_matcher->refcnt,
8209 __atomic_fetch_add(&cache_matcher->refcnt, 1,
8211 dev_flow->handle->dvh.matcher = cache_matcher;
8212 /* old matcher should not make the table ref++. */
8213 flow_dv_tbl_resource_release(dev, tbl);
8217 /* Register new matcher. */
8218 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8220 if (!cache_matcher) {
8221 flow_dv_tbl_resource_release(dev, tbl);
8222 return rte_flow_error_set(error, ENOMEM,
8223 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8224 "cannot allocate matcher memory");
8226 *cache_matcher = *matcher;
8227 dv_attr.match_criteria_enable =
8228 flow_dv_matcher_enable(cache_matcher->mask.buf);
8229 dv_attr.priority = matcher->priority;
8231 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8232 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8233 &cache_matcher->matcher_object);
8235 mlx5_free(cache_matcher);
8236 #ifdef HAVE_MLX5DV_DR
8237 flow_dv_tbl_resource_release(dev, tbl);
8239 return rte_flow_error_set(error, ENOMEM,
8240 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8241 NULL, "cannot create matcher");
8243 /* Save the table information */
8244 cache_matcher->tbl = tbl;
8245 /* only matcher ref++, table ref++ already done above in get API. */
8246 __atomic_store_n(&cache_matcher->refcnt, 1, __ATOMIC_RELAXED);
8247 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8248 dev_flow->handle->dvh.matcher = cache_matcher;
8249 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8250 key->domain ? "FDB" : "NIC", key->table_id,
8251 cache_matcher->priority,
8252 key->direction ? "tx" : "rx", (void *)cache_matcher,
8253 __atomic_load_n(&cache_matcher->refcnt, __ATOMIC_RELAXED));
8258 * Find existing tag resource or create and register a new one.
8260 * @param dev[in, out]
8261 * Pointer to rte_eth_dev structure.
8262 * @param[in, out] tag_be24
8263 * Tag value in big endian then R-shift 8.
8264 * @parm[in, out] dev_flow
8265 * Pointer to the dev_flow.
8267 * pointer to error structure.
8270 * 0 on success otherwise -errno and errno is set.
8273 flow_dv_tag_resource_register
8274 (struct rte_eth_dev *dev,
8276 struct mlx5_flow *dev_flow,
8277 struct rte_flow_error *error)
8279 struct mlx5_priv *priv = dev->data->dev_private;
8280 struct mlx5_dev_ctx_shared *sh = priv->sh;
8281 struct mlx5_flow_dv_tag_resource *cache_resource;
8282 struct mlx5_hlist_entry *entry;
8285 /* Lookup a matching resource from cache. */
8286 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8288 cache_resource = container_of
8289 (entry, struct mlx5_flow_dv_tag_resource, entry);
8290 __atomic_fetch_add(&cache_resource->refcnt, 1,
8292 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8293 dev_flow->dv.tag_resource = cache_resource;
8294 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8295 (void *)cache_resource,
8296 __atomic_load_n(&cache_resource->refcnt,
8300 /* Register new resource. */
8301 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8302 &dev_flow->handle->dvh.rix_tag);
8303 if (!cache_resource)
8304 return rte_flow_error_set(error, ENOMEM,
8305 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8306 "cannot allocate resource memory");
8307 cache_resource->entry.key = (uint64_t)tag_be24;
8308 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8309 &cache_resource->action);
8311 mlx5_free(cache_resource);
8312 return rte_flow_error_set(error, ENOMEM,
8313 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8314 NULL, "cannot create action");
8316 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8317 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8318 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8319 mlx5_free(cache_resource);
8320 return rte_flow_error_set(error, EEXIST,
8321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8322 NULL, "cannot insert tag");
8324 dev_flow->dv.tag_resource = cache_resource;
8325 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8326 (void *)cache_resource,
8327 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8335 * Pointer to Ethernet device.
8340 * 1 while a reference on it exists, 0 when freed.
8343 flow_dv_tag_release(struct rte_eth_dev *dev,
8346 struct mlx5_priv *priv = dev->data->dev_private;
8347 struct mlx5_dev_ctx_shared *sh = priv->sh;
8348 struct mlx5_flow_dv_tag_resource *tag;
8350 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8353 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8354 dev->data->port_id, (void *)tag,
8355 __atomic_load_n(&tag->refcnt, __ATOMIC_RELAXED));
8356 if (__atomic_sub_fetch(&tag->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8357 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8358 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8359 DRV_LOG(DEBUG, "port %u tag %p: removed",
8360 dev->data->port_id, (void *)tag);
8361 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8368 * Translate port ID action to vport.
8371 * Pointer to rte_eth_dev structure.
8373 * Pointer to the port ID action.
8374 * @param[out] dst_port_id
8375 * The target port ID.
8377 * Pointer to the error structure.
8380 * 0 on success, a negative errno value otherwise and rte_errno is set.
8383 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8384 const struct rte_flow_action *action,
8385 uint32_t *dst_port_id,
8386 struct rte_flow_error *error)
8389 struct mlx5_priv *priv;
8390 const struct rte_flow_action_port_id *conf =
8391 (const struct rte_flow_action_port_id *)action->conf;
8393 port = conf->original ? dev->data->port_id : conf->id;
8394 priv = mlx5_port_to_eswitch_info(port, false);
8396 return rte_flow_error_set(error, -rte_errno,
8397 RTE_FLOW_ERROR_TYPE_ACTION,
8399 "No eswitch info was found for port");
8400 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8402 * This parameter is transferred to
8403 * mlx5dv_dr_action_create_dest_ib_port().
8405 *dst_port_id = priv->dev_port;
8408 * Legacy mode, no LAG configurations is supported.
8409 * This parameter is transferred to
8410 * mlx5dv_dr_action_create_dest_vport().
8412 *dst_port_id = priv->vport_id;
8418 * Create a counter with aging configuration.
8421 * Pointer to rte_eth_dev structure.
8423 * Pointer to the counter action configuration.
8425 * Pointer to the aging action configuration.
8428 * Index to flow counter on success, 0 otherwise.
8431 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8432 struct mlx5_flow *dev_flow,
8433 const struct rte_flow_action_count *count,
8434 const struct rte_flow_action_age *age)
8437 struct mlx5_age_param *age_param;
8439 if (count && count->shared)
8440 counter = flow_dv_counter_get_shared(dev, count->id);
8442 counter = flow_dv_counter_alloc(dev, !!age);
8443 if (!counter || age == NULL)
8445 age_param = flow_dv_counter_idx_get_age(dev, counter);
8446 age_param->context = age->context ? age->context :
8447 (void *)(uintptr_t)(dev_flow->flow_idx);
8448 age_param->timeout = age->timeout;
8449 age_param->port_id = dev->data->port_id;
8450 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8451 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8455 * Add Tx queue matcher
8458 * Pointer to the dev struct.
8459 * @param[in, out] matcher
8461 * @param[in, out] key
8462 * Flow matcher value.
8464 * Flow pattern to translate.
8466 * Item is inner pattern.
8469 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8470 void *matcher, void *key,
8471 const struct rte_flow_item *item)
8473 const struct mlx5_rte_flow_item_tx_queue *queue_m;
8474 const struct mlx5_rte_flow_item_tx_queue *queue_v;
8476 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8478 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8479 struct mlx5_txq_ctrl *txq;
8483 queue_m = (const void *)item->mask;
8486 queue_v = (const void *)item->spec;
8489 txq = mlx5_txq_get(dev, queue_v->queue);
8492 queue = txq->obj->sq->id;
8493 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8494 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8495 queue & queue_m->queue);
8496 mlx5_txq_release(dev, queue_v->queue);
8500 * Set the hash fields according to the @p flow information.
8502 * @param[in] dev_flow
8503 * Pointer to the mlx5_flow.
8504 * @param[in] rss_desc
8505 * Pointer to the mlx5_flow_rss_desc.
8508 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8509 struct mlx5_flow_rss_desc *rss_desc)
8511 uint64_t items = dev_flow->handle->layers;
8513 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8515 dev_flow->hash_fields = 0;
8516 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8517 if (rss_desc->level >= 2) {
8518 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8522 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8523 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8524 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8525 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8526 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8527 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8528 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8530 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8532 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8533 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8534 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8535 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8536 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8537 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8538 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8540 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8543 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8544 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8545 if (rss_types & ETH_RSS_UDP) {
8546 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8547 dev_flow->hash_fields |=
8548 IBV_RX_HASH_SRC_PORT_UDP;
8549 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8550 dev_flow->hash_fields |=
8551 IBV_RX_HASH_DST_PORT_UDP;
8553 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8555 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8556 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8557 if (rss_types & ETH_RSS_TCP) {
8558 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8559 dev_flow->hash_fields |=
8560 IBV_RX_HASH_SRC_PORT_TCP;
8561 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8562 dev_flow->hash_fields |=
8563 IBV_RX_HASH_DST_PORT_TCP;
8565 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8571 * Create an Rx Hash queue.
8574 * Pointer to Ethernet device.
8575 * @param[in] dev_flow
8576 * Pointer to the mlx5_flow.
8577 * @param[in] rss_desc
8578 * Pointer to the mlx5_flow_rss_desc.
8579 * @param[out] hrxq_idx
8580 * Hash Rx queue index.
8583 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8585 static struct mlx5_hrxq *
8586 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8587 struct mlx5_flow *dev_flow,
8588 struct mlx5_flow_rss_desc *rss_desc,
8591 struct mlx5_priv *priv = dev->data->dev_private;
8592 struct mlx5_flow_handle *dh = dev_flow->handle;
8593 struct mlx5_hrxq *hrxq;
8595 MLX5_ASSERT(rss_desc->queue_num);
8596 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8597 dev_flow->hash_fields,
8598 rss_desc->queue, rss_desc->queue_num);
8600 *hrxq_idx = mlx5_hrxq_new
8601 (dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8602 dev_flow->hash_fields,
8603 rss_desc->queue, rss_desc->queue_num,
8604 !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL),
8609 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8615 * Find existing sample resource or create and register a new one.
8617 * @param[in, out] dev
8618 * Pointer to rte_eth_dev structure.
8620 * Attributes of flow that includes this item.
8621 * @param[in] resource
8622 * Pointer to sample resource.
8623 * @parm[in, out] dev_flow
8624 * Pointer to the dev_flow.
8625 * @param[in, out] sample_dv_actions
8626 * Pointer to sample actions list.
8628 * pointer to error structure.
8631 * 0 on success otherwise -errno and errno is set.
8634 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8635 const struct rte_flow_attr *attr,
8636 struct mlx5_flow_dv_sample_resource *resource,
8637 struct mlx5_flow *dev_flow,
8638 void **sample_dv_actions,
8639 struct rte_flow_error *error)
8641 struct mlx5_flow_dv_sample_resource *cache_resource;
8642 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8643 struct mlx5_priv *priv = dev->data->dev_private;
8644 struct mlx5_dev_ctx_shared *sh = priv->sh;
8645 struct mlx5_flow_tbl_resource *tbl;
8647 const uint32_t next_ft_step = 1;
8648 uint32_t next_ft_id = resource->ft_id + next_ft_step;
8650 /* Lookup a matching resource from cache. */
8651 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8652 idx, cache_resource, next) {
8653 if (resource->ratio == cache_resource->ratio &&
8654 resource->ft_type == cache_resource->ft_type &&
8655 resource->ft_id == cache_resource->ft_id &&
8656 resource->set_action == cache_resource->set_action &&
8657 !memcmp((void *)&resource->sample_act,
8658 (void *)&cache_resource->sample_act,
8659 sizeof(struct mlx5_flow_sub_actions_list))) {
8660 DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8661 (void *)cache_resource,
8662 __atomic_load_n(&cache_resource->refcnt,
8664 __atomic_fetch_add(&cache_resource->refcnt, 1,
8666 dev_flow->handle->dvh.rix_sample = idx;
8667 dev_flow->dv.sample_res = cache_resource;
8671 /* Register new sample resource. */
8672 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8673 &dev_flow->handle->dvh.rix_sample);
8674 if (!cache_resource)
8675 return rte_flow_error_set(error, ENOMEM,
8676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8678 "cannot allocate resource memory");
8679 *cache_resource = *resource;
8680 /* Create normal path table level */
8681 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8682 attr->egress, attr->transfer,
8683 dev_flow->external, NULL, 0, error);
8685 rte_flow_error_set(error, ENOMEM,
8686 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8688 "fail to create normal path table "
8692 cache_resource->normal_path_tbl = tbl;
8693 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8694 cache_resource->default_miss =
8695 mlx5_glue->dr_create_flow_action_default_miss();
8696 if (!cache_resource->default_miss) {
8697 rte_flow_error_set(error, ENOMEM,
8698 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8700 "cannot create default miss "
8704 sample_dv_actions[resource->sample_act.actions_num++] =
8705 cache_resource->default_miss;
8707 /* Create a DR sample action */
8708 sampler_attr.sample_ratio = cache_resource->ratio;
8709 sampler_attr.default_next_table = tbl->obj;
8710 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8711 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8712 &sample_dv_actions[0];
8713 sampler_attr.action = cache_resource->set_action;
8714 cache_resource->verbs_action =
8715 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8716 if (!cache_resource->verbs_action) {
8717 rte_flow_error_set(error, ENOMEM,
8718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8719 NULL, "cannot create sample action");
8722 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8723 ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8724 dev_flow->handle->dvh.rix_sample, cache_resource,
8726 dev_flow->dv.sample_res = cache_resource;
8727 DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8728 (void *)cache_resource,
8729 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8732 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8733 if (cache_resource->default_miss)
8734 claim_zero(mlx5_glue->destroy_flow_action
8735 (cache_resource->default_miss));
8737 if (cache_resource->sample_idx.rix_hrxq &&
8738 !mlx5_hrxq_release(dev,
8739 cache_resource->sample_idx.rix_hrxq))
8740 cache_resource->sample_idx.rix_hrxq = 0;
8741 if (cache_resource->sample_idx.rix_tag &&
8742 !flow_dv_tag_release(dev,
8743 cache_resource->sample_idx.rix_tag))
8744 cache_resource->sample_idx.rix_tag = 0;
8745 if (cache_resource->sample_idx.cnt) {
8746 flow_dv_counter_release(dev,
8747 cache_resource->sample_idx.cnt);
8748 cache_resource->sample_idx.cnt = 0;
8751 if (cache_resource->normal_path_tbl)
8752 flow_dv_tbl_resource_release(dev,
8753 cache_resource->normal_path_tbl);
8754 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8755 dev_flow->handle->dvh.rix_sample);
8756 dev_flow->handle->dvh.rix_sample = 0;
8761 * Find existing destination array resource or create and register a new one.
8763 * @param[in, out] dev
8764 * Pointer to rte_eth_dev structure.
8766 * Attributes of flow that includes this item.
8767 * @param[in] resource
8768 * Pointer to destination array resource.
8769 * @parm[in, out] dev_flow
8770 * Pointer to the dev_flow.
8772 * pointer to error structure.
8775 * 0 on success otherwise -errno and errno is set.
8778 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8779 const struct rte_flow_attr *attr,
8780 struct mlx5_flow_dv_dest_array_resource *resource,
8781 struct mlx5_flow *dev_flow,
8782 struct rte_flow_error *error)
8784 struct mlx5_flow_dv_dest_array_resource *cache_resource;
8785 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8786 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8787 struct mlx5_priv *priv = dev->data->dev_private;
8788 struct mlx5_dev_ctx_shared *sh = priv->sh;
8789 struct mlx5_flow_sub_actions_list *sample_act;
8790 struct mlx5dv_dr_domain *domain;
8793 /* Lookup a matching resource from cache. */
8794 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8795 sh->dest_array_list,
8796 idx, cache_resource, next) {
8797 if (resource->num_of_dest == cache_resource->num_of_dest &&
8798 resource->ft_type == cache_resource->ft_type &&
8799 !memcmp((void *)cache_resource->sample_act,
8800 (void *)resource->sample_act,
8801 (resource->num_of_dest *
8802 sizeof(struct mlx5_flow_sub_actions_list)))) {
8803 DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8804 (void *)cache_resource,
8805 __atomic_load_n(&cache_resource->refcnt,
8807 __atomic_fetch_add(&cache_resource->refcnt, 1,
8809 dev_flow->handle->dvh.rix_dest_array = idx;
8810 dev_flow->dv.dest_array_res = cache_resource;
8814 /* Register new destination array resource. */
8815 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8816 &dev_flow->handle->dvh.rix_dest_array);
8817 if (!cache_resource)
8818 return rte_flow_error_set(error, ENOMEM,
8819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8821 "cannot allocate resource memory");
8822 *cache_resource = *resource;
8824 domain = sh->fdb_domain;
8825 else if (attr->ingress)
8826 domain = sh->rx_domain;
8828 domain = sh->tx_domain;
8829 for (idx = 0; idx < resource->num_of_dest; idx++) {
8830 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8831 mlx5_malloc(MLX5_MEM_ZERO,
8832 sizeof(struct mlx5dv_dr_action_dest_attr),
8834 if (!dest_attr[idx]) {
8835 rte_flow_error_set(error, ENOMEM,
8836 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8838 "cannot allocate resource memory");
8841 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8842 sample_act = &resource->sample_act[idx];
8843 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8844 dest_attr[idx]->dest = sample_act->dr_queue_action;
8845 } else if (sample_act->action_flags ==
8846 (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8847 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8848 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8849 dest_attr[idx]->dest_reformat->reformat =
8850 sample_act->dr_encap_action;
8851 dest_attr[idx]->dest_reformat->dest =
8852 sample_act->dr_port_id_action;
8853 } else if (sample_act->action_flags ==
8854 MLX5_FLOW_ACTION_PORT_ID) {
8855 dest_attr[idx]->dest = sample_act->dr_port_id_action;
8858 /* create a dest array actioin */
8859 cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8861 cache_resource->num_of_dest,
8863 if (!cache_resource->action) {
8864 rte_flow_error_set(error, ENOMEM,
8865 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8867 "cannot create destination array action");
8870 __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8871 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8872 &sh->dest_array_list,
8873 dev_flow->handle->dvh.rix_dest_array, cache_resource,
8875 dev_flow->dv.dest_array_res = cache_resource;
8876 DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8877 (void *)cache_resource,
8878 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8879 for (idx = 0; idx < resource->num_of_dest; idx++)
8880 mlx5_free(dest_attr[idx]);
8883 for (idx = 0; idx < resource->num_of_dest; idx++) {
8884 struct mlx5_flow_sub_actions_idx *act_res =
8885 &cache_resource->sample_idx[idx];
8886 if (act_res->rix_hrxq &&
8887 !mlx5_hrxq_release(dev,
8889 act_res->rix_hrxq = 0;
8890 if (act_res->rix_encap_decap &&
8891 !flow_dv_encap_decap_resource_release(dev,
8892 act_res->rix_encap_decap))
8893 act_res->rix_encap_decap = 0;
8894 if (act_res->rix_port_id_action &&
8895 !flow_dv_port_id_action_resource_release(dev,
8896 act_res->rix_port_id_action))
8897 act_res->rix_port_id_action = 0;
8899 mlx5_free(dest_attr[idx]);
8902 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8903 dev_flow->handle->dvh.rix_dest_array);
8904 dev_flow->handle->dvh.rix_dest_array = 0;
8909 * Convert Sample action to DV specification.
8912 * Pointer to rte_eth_dev structure.
8914 * Pointer to action structure.
8915 * @param[in, out] dev_flow
8916 * Pointer to the mlx5_flow.
8918 * Pointer to the flow attributes.
8919 * @param[in, out] num_of_dest
8920 * Pointer to the num of destination.
8921 * @param[in, out] sample_actions
8922 * Pointer to sample actions list.
8923 * @param[in, out] res
8924 * Pointer to sample resource.
8926 * Pointer to the error structure.
8929 * 0 on success, a negative errno value otherwise and rte_errno is set.
8932 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8933 const struct rte_flow_action *action,
8934 struct mlx5_flow *dev_flow,
8935 const struct rte_flow_attr *attr,
8936 uint32_t *num_of_dest,
8937 void **sample_actions,
8938 struct mlx5_flow_dv_sample_resource *res,
8939 struct rte_flow_error *error)
8941 struct mlx5_priv *priv = dev->data->dev_private;
8942 const struct rte_flow_action_sample *sample_action;
8943 const struct rte_flow_action *sub_actions;
8944 const struct rte_flow_action_queue *queue;
8945 struct mlx5_flow_sub_actions_list *sample_act;
8946 struct mlx5_flow_sub_actions_idx *sample_idx;
8947 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8948 struct mlx5_flow_rss_desc *rss_desc;
8949 uint64_t action_flags = 0;
8952 rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
8953 sample_act = &res->sample_act;
8954 sample_idx = &res->sample_idx;
8955 sample_action = (const struct rte_flow_action_sample *)action->conf;
8956 res->ratio = sample_action->ratio;
8957 sub_actions = sample_action->actions;
8958 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8959 int type = sub_actions->type;
8960 uint32_t pre_rix = 0;
8963 case RTE_FLOW_ACTION_TYPE_QUEUE:
8965 struct mlx5_hrxq *hrxq;
8968 queue = sub_actions->conf;
8969 rss_desc->queue_num = 1;
8970 rss_desc->queue[0] = queue->index;
8971 hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8972 rss_desc, &hrxq_idx);
8974 return rte_flow_error_set
8976 RTE_FLOW_ERROR_TYPE_ACTION,
8978 "cannot create fate queue");
8979 sample_act->dr_queue_action = hrxq->action;
8980 sample_idx->rix_hrxq = hrxq_idx;
8981 sample_actions[sample_act->actions_num++] =
8984 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8985 if (action_flags & MLX5_FLOW_ACTION_MARK)
8986 dev_flow->handle->rix_hrxq = hrxq_idx;
8987 dev_flow->handle->fate_action =
8988 MLX5_FLOW_FATE_QUEUE;
8991 case RTE_FLOW_ACTION_TYPE_MARK:
8993 uint32_t tag_be = mlx5_flow_mark_set
8994 (((const struct rte_flow_action_mark *)
8995 (sub_actions->conf))->id);
8997 dev_flow->handle->mark = 1;
8998 pre_rix = dev_flow->handle->dvh.rix_tag;
8999 /* Save the mark resource before sample */
9000 pre_r = dev_flow->dv.tag_resource;
9001 if (flow_dv_tag_resource_register(dev, tag_be,
9004 MLX5_ASSERT(dev_flow->dv.tag_resource);
9005 sample_act->dr_tag_action =
9006 dev_flow->dv.tag_resource->action;
9007 sample_idx->rix_tag =
9008 dev_flow->handle->dvh.rix_tag;
9009 sample_actions[sample_act->actions_num++] =
9010 sample_act->dr_tag_action;
9011 /* Recover the mark resource after sample */
9012 dev_flow->dv.tag_resource = pre_r;
9013 dev_flow->handle->dvh.rix_tag = pre_rix;
9014 action_flags |= MLX5_FLOW_ACTION_MARK;
9017 case RTE_FLOW_ACTION_TYPE_COUNT:
9021 counter = flow_dv_translate_create_counter(dev,
9022 dev_flow, sub_actions->conf, 0);
9024 return rte_flow_error_set
9026 RTE_FLOW_ERROR_TYPE_ACTION,
9028 "cannot create counter"
9030 sample_idx->cnt = counter;
9031 sample_act->dr_cnt_action =
9032 (flow_dv_counter_get_by_idx(dev,
9033 counter, NULL))->action;
9034 sample_actions[sample_act->actions_num++] =
9035 sample_act->dr_cnt_action;
9036 action_flags |= MLX5_FLOW_ACTION_COUNT;
9039 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9041 struct mlx5_flow_dv_port_id_action_resource
9043 uint32_t port_id = 0;
9045 memset(&port_id_resource, 0, sizeof(port_id_resource));
9046 /* Save the port id resource before sample */
9047 pre_rix = dev_flow->handle->rix_port_id_action;
9048 pre_r = dev_flow->dv.port_id_action;
9049 if (flow_dv_translate_action_port_id(dev, sub_actions,
9052 port_id_resource.port_id = port_id;
9053 if (flow_dv_port_id_action_resource_register
9054 (dev, &port_id_resource, dev_flow, error))
9056 sample_act->dr_port_id_action =
9057 dev_flow->dv.port_id_action->action;
9058 sample_idx->rix_port_id_action =
9059 dev_flow->handle->rix_port_id_action;
9060 sample_actions[sample_act->actions_num++] =
9061 sample_act->dr_port_id_action;
9062 /* Recover the port id resource after sample */
9063 dev_flow->dv.port_id_action = pre_r;
9064 dev_flow->handle->rix_port_id_action = pre_rix;
9066 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9069 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9070 /* Save the encap resource before sample */
9071 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9072 pre_r = dev_flow->dv.encap_decap;
9073 if (flow_dv_create_action_l2_encap(dev, sub_actions,
9078 sample_act->dr_encap_action =
9079 dev_flow->dv.encap_decap->action;
9080 sample_idx->rix_encap_decap =
9081 dev_flow->handle->dvh.rix_encap_decap;
9082 sample_actions[sample_act->actions_num++] =
9083 sample_act->dr_encap_action;
9084 /* Recover the encap resource after sample */
9085 dev_flow->dv.encap_decap = pre_r;
9086 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9087 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9090 return rte_flow_error_set(error, EINVAL,
9091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9093 "Not support for sampler action");
9096 sample_act->action_flags = action_flags;
9097 res->ft_id = dev_flow->dv.group;
9098 if (attr->transfer) {
9100 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9101 uint64_t set_action;
9102 } action_ctx = { .set_action = 0 };
9104 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9105 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9106 MLX5_MODIFICATION_TYPE_SET);
9107 MLX5_SET(set_action_in, action_ctx.action_in, field,
9108 MLX5_MODI_META_REG_C_0);
9109 MLX5_SET(set_action_in, action_ctx.action_in, data,
9110 priv->vport_meta_tag);
9111 res->set_action = action_ctx.set_action;
9112 } else if (attr->ingress) {
9113 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9119 * Convert Sample action to DV specification.
9122 * Pointer to rte_eth_dev structure.
9123 * @param[in, out] dev_flow
9124 * Pointer to the mlx5_flow.
9126 * Pointer to the flow attributes.
9127 * @param[in] num_of_dest
9128 * The num of destination.
9129 * @param[in, out] res
9130 * Pointer to sample resource.
9131 * @param[in, out] mdest_res
9132 * Pointer to destination array resource.
9133 * @param[in] sample_actions
9134 * Pointer to sample path actions list.
9135 * @param[in] action_flags
9136 * Holds the actions detected until now.
9138 * Pointer to the error structure.
9141 * 0 on success, a negative errno value otherwise and rte_errno is set.
9144 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9145 struct mlx5_flow *dev_flow,
9146 const struct rte_flow_attr *attr,
9147 uint32_t num_of_dest,
9148 struct mlx5_flow_dv_sample_resource *res,
9149 struct mlx5_flow_dv_dest_array_resource *mdest_res,
9150 void **sample_actions,
9151 uint64_t action_flags,
9152 struct rte_flow_error *error)
9154 /* update normal path action resource into last index of array */
9155 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9156 struct mlx5_flow_sub_actions_list *sample_act =
9157 &mdest_res->sample_act[dest_index];
9158 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9159 struct mlx5_flow_rss_desc *rss_desc;
9160 uint32_t normal_idx = 0;
9161 struct mlx5_hrxq *hrxq;
9165 rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9166 if (num_of_dest > 1) {
9167 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9168 /* Handle QP action for mirroring */
9169 hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
9170 rss_desc, &hrxq_idx);
9172 return rte_flow_error_set
9174 RTE_FLOW_ERROR_TYPE_ACTION,
9176 "cannot create rx queue");
9178 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9179 sample_act->dr_queue_action = hrxq->action;
9180 if (action_flags & MLX5_FLOW_ACTION_MARK)
9181 dev_flow->handle->rix_hrxq = hrxq_idx;
9182 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9184 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9186 mdest_res->sample_idx[dest_index].rix_encap_decap =
9187 dev_flow->handle->dvh.rix_encap_decap;
9188 sample_act->dr_encap_action =
9189 dev_flow->dv.encap_decap->action;
9191 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9193 mdest_res->sample_idx[dest_index].rix_port_id_action =
9194 dev_flow->handle->rix_port_id_action;
9195 sample_act->dr_port_id_action =
9196 dev_flow->dv.port_id_action->action;
9198 sample_act->actions_num = normal_idx;
9199 /* update sample action resource into first index of array */
9200 mdest_res->ft_type = res->ft_type;
9201 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9202 sizeof(struct mlx5_flow_sub_actions_idx));
9203 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9204 sizeof(struct mlx5_flow_sub_actions_list));
9205 mdest_res->num_of_dest = num_of_dest;
9206 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9208 return rte_flow_error_set(error, EINVAL,
9209 RTE_FLOW_ERROR_TYPE_ACTION,
9210 NULL, "can't create sample "
9213 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9214 sample_actions, error))
9215 return rte_flow_error_set(error, EINVAL,
9216 RTE_FLOW_ERROR_TYPE_ACTION,
9218 "can't create sample action");
9224 * Fill the flow with DV spec, lock free
9225 * (mutex should be acquired by caller).
9228 * Pointer to rte_eth_dev structure.
9229 * @param[in, out] dev_flow
9230 * Pointer to the sub flow.
9232 * Pointer to the flow attributes.
9234 * Pointer to the list of items.
9235 * @param[in] actions
9236 * Pointer to the list of actions.
9238 * Pointer to the error structure.
9241 * 0 on success, a negative errno value otherwise and rte_errno is set.
9244 __flow_dv_translate(struct rte_eth_dev *dev,
9245 struct mlx5_flow *dev_flow,
9246 const struct rte_flow_attr *attr,
9247 const struct rte_flow_item items[],
9248 const struct rte_flow_action actions[],
9249 struct rte_flow_error *error)
9251 struct mlx5_priv *priv = dev->data->dev_private;
9252 struct mlx5_dev_config *dev_conf = &priv->config;
9253 struct rte_flow *flow = dev_flow->flow;
9254 struct mlx5_flow_handle *handle = dev_flow->handle;
9255 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9256 struct mlx5_flow_rss_desc *rss_desc;
9257 uint64_t item_flags = 0;
9258 uint64_t last_item = 0;
9259 uint64_t action_flags = 0;
9260 uint64_t priority = attr->priority;
9261 struct mlx5_flow_dv_matcher matcher = {
9263 .size = sizeof(matcher.mask.buf) -
9264 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9268 bool actions_end = false;
9270 struct mlx5_flow_dv_modify_hdr_resource res;
9271 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9272 sizeof(struct mlx5_modification_cmd) *
9273 (MLX5_MAX_MODIFY_NUM + 1)];
9275 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9276 const struct rte_flow_action_count *count = NULL;
9277 const struct rte_flow_action_age *age = NULL;
9278 union flow_dv_attr flow_attr = { .attr = 0 };
9280 union mlx5_flow_tbl_key tbl_key;
9281 uint32_t modify_action_position = UINT32_MAX;
9282 void *match_mask = matcher.mask.buf;
9283 void *match_value = dev_flow->dv.value.buf;
9284 uint8_t next_protocol = 0xff;
9285 struct rte_vlan_hdr vlan = { 0 };
9286 struct mlx5_flow_dv_dest_array_resource mdest_res;
9287 struct mlx5_flow_dv_sample_resource sample_res;
9288 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9289 struct mlx5_flow_sub_actions_list *sample_act;
9290 uint32_t sample_act_pos = UINT32_MAX;
9291 uint32_t num_of_dest = 0;
9292 int tmp_actions_n = 0;
9295 const struct mlx5_flow_tunnel *tunnel;
9296 struct flow_grp_info grp_info = {
9297 .external = !!dev_flow->external,
9298 .transfer = !!attr->transfer,
9299 .fdb_def_rule = !!priv->fdb_def_rule,
9303 rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9304 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9305 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9306 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9307 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9308 /* update normal path action resource into last index of array */
9309 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9310 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9311 flow_items_to_tunnel(items) :
9312 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9313 flow_actions_to_tunnel(actions) :
9314 dev_flow->tunnel ? dev_flow->tunnel : NULL;
9315 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9316 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9317 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9318 (dev, tunnel, attr, items, actions);
9319 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9323 dev_flow->dv.group = table;
9325 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9326 if (priority == MLX5_FLOW_PRIO_RSVD)
9327 priority = dev_conf->flow_prio - 1;
9328 /* number of actions must be set to 0 in case of dirty stack. */
9329 mhdr_res->actions_num = 0;
9330 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9332 * do not add decap action if match rule drops packet
9333 * HW rejects rules with decap & drop
9335 bool add_decap = true;
9336 const struct rte_flow_action *ptr = actions;
9337 struct mlx5_flow_tbl_resource *tbl;
9339 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9340 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9346 if (flow_dv_create_action_l2_decap(dev, dev_flow,
9350 dev_flow->dv.actions[actions_n++] =
9351 dev_flow->dv.encap_decap->action;
9352 action_flags |= MLX5_FLOW_ACTION_DECAP;
9355 * bind table_id with <group, table> for tunnel match rule.
9356 * Tunnel set rule establishes that bind in JUMP action handler.
9357 * Required for scenario when application creates tunnel match
9358 * rule before tunnel set rule.
9360 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9362 !!dev_flow->external, tunnel,
9363 attr->group, error);
9365 return rte_flow_error_set
9366 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9367 actions, "cannot register tunnel group");
9369 for (; !actions_end ; actions++) {
9370 const struct rte_flow_action_queue *queue;
9371 const struct rte_flow_action_rss *rss;
9372 const struct rte_flow_action *action = actions;
9373 const uint8_t *rss_key;
9374 const struct rte_flow_action_meter *mtr;
9375 struct mlx5_flow_tbl_resource *tbl;
9376 uint32_t port_id = 0;
9377 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9378 int action_type = actions->type;
9379 const struct rte_flow_action *found_action = NULL;
9380 struct mlx5_flow_meter *fm = NULL;
9381 uint32_t jump_group = 0;
9383 if (!mlx5_flow_os_action_supported(action_type))
9384 return rte_flow_error_set(error, ENOTSUP,
9385 RTE_FLOW_ERROR_TYPE_ACTION,
9387 "action not supported");
9388 switch (action_type) {
9389 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9390 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9392 case RTE_FLOW_ACTION_TYPE_VOID:
9394 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9395 if (flow_dv_translate_action_port_id(dev, action,
9398 port_id_resource.port_id = port_id;
9399 MLX5_ASSERT(!handle->rix_port_id_action);
9400 if (flow_dv_port_id_action_resource_register
9401 (dev, &port_id_resource, dev_flow, error))
9403 dev_flow->dv.actions[actions_n++] =
9404 dev_flow->dv.port_id_action->action;
9405 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9406 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9407 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9410 case RTE_FLOW_ACTION_TYPE_FLAG:
9411 action_flags |= MLX5_FLOW_ACTION_FLAG;
9412 dev_flow->handle->mark = 1;
9413 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9414 struct rte_flow_action_mark mark = {
9415 .id = MLX5_FLOW_MARK_DEFAULT,
9418 if (flow_dv_convert_action_mark(dev, &mark,
9422 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9425 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9427 * Only one FLAG or MARK is supported per device flow
9428 * right now. So the pointer to the tag resource must be
9429 * zero before the register process.
9431 MLX5_ASSERT(!handle->dvh.rix_tag);
9432 if (flow_dv_tag_resource_register(dev, tag_be,
9435 MLX5_ASSERT(dev_flow->dv.tag_resource);
9436 dev_flow->dv.actions[actions_n++] =
9437 dev_flow->dv.tag_resource->action;
9439 case RTE_FLOW_ACTION_TYPE_MARK:
9440 action_flags |= MLX5_FLOW_ACTION_MARK;
9441 dev_flow->handle->mark = 1;
9442 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9443 const struct rte_flow_action_mark *mark =
9444 (const struct rte_flow_action_mark *)
9447 if (flow_dv_convert_action_mark(dev, mark,
9451 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9455 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9456 /* Legacy (non-extensive) MARK action. */
9457 tag_be = mlx5_flow_mark_set
9458 (((const struct rte_flow_action_mark *)
9459 (actions->conf))->id);
9460 MLX5_ASSERT(!handle->dvh.rix_tag);
9461 if (flow_dv_tag_resource_register(dev, tag_be,
9464 MLX5_ASSERT(dev_flow->dv.tag_resource);
9465 dev_flow->dv.actions[actions_n++] =
9466 dev_flow->dv.tag_resource->action;
9468 case RTE_FLOW_ACTION_TYPE_SET_META:
9469 if (flow_dv_convert_action_set_meta
9470 (dev, mhdr_res, attr,
9471 (const struct rte_flow_action_set_meta *)
9472 actions->conf, error))
9474 action_flags |= MLX5_FLOW_ACTION_SET_META;
9476 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9477 if (flow_dv_convert_action_set_tag
9479 (const struct rte_flow_action_set_tag *)
9480 actions->conf, error))
9482 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9484 case RTE_FLOW_ACTION_TYPE_DROP:
9485 action_flags |= MLX5_FLOW_ACTION_DROP;
9486 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9488 case RTE_FLOW_ACTION_TYPE_QUEUE:
9489 queue = actions->conf;
9490 rss_desc->queue_num = 1;
9491 rss_desc->queue[0] = queue->index;
9492 action_flags |= MLX5_FLOW_ACTION_QUEUE;
9493 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9494 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9497 case RTE_FLOW_ACTION_TYPE_RSS:
9498 rss = actions->conf;
9499 memcpy(rss_desc->queue, rss->queue,
9500 rss->queue_num * sizeof(uint16_t));
9501 rss_desc->queue_num = rss->queue_num;
9502 /* NULL RSS key indicates default RSS key. */
9503 rss_key = !rss->key ? rss_hash_default_key : rss->key;
9504 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9506 * rss->level and rss.types should be set in advance
9507 * when expanding items for RSS.
9509 action_flags |= MLX5_FLOW_ACTION_RSS;
9510 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9512 case RTE_FLOW_ACTION_TYPE_AGE:
9513 case RTE_FLOW_ACTION_TYPE_COUNT:
9514 if (!dev_conf->devx) {
9515 return rte_flow_error_set
9517 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9519 "count action not supported");
9521 /* Save information first, will apply later. */
9522 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9523 count = action->conf;
9526 action_flags |= MLX5_FLOW_ACTION_COUNT;
9528 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9529 dev_flow->dv.actions[actions_n++] =
9530 priv->sh->pop_vlan_action;
9531 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9533 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9534 if (!(action_flags &
9535 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9536 flow_dev_get_vlan_info_from_items(items, &vlan);
9537 vlan.eth_proto = rte_be_to_cpu_16
9538 ((((const struct rte_flow_action_of_push_vlan *)
9539 actions->conf)->ethertype));
9540 found_action = mlx5_flow_find_action
9542 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9544 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9545 found_action = mlx5_flow_find_action
9547 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9549 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9550 if (flow_dv_create_action_push_vlan
9551 (dev, attr, &vlan, dev_flow, error))
9553 dev_flow->dv.actions[actions_n++] =
9554 dev_flow->dv.push_vlan_res->action;
9555 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9557 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9558 /* of_vlan_push action handled this action */
9559 MLX5_ASSERT(action_flags &
9560 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9562 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9563 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9565 flow_dev_get_vlan_info_from_items(items, &vlan);
9566 mlx5_update_vlan_vid_pcp(actions, &vlan);
9567 /* If no VLAN push - this is a modify header action */
9568 if (flow_dv_convert_action_modify_vlan_vid
9569 (mhdr_res, actions, error))
9571 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9573 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9574 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9575 if (flow_dv_create_action_l2_encap(dev, actions,
9580 dev_flow->dv.actions[actions_n++] =
9581 dev_flow->dv.encap_decap->action;
9582 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9583 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9584 sample_act->action_flags |=
9585 MLX5_FLOW_ACTION_ENCAP;
9587 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9588 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9589 if (flow_dv_create_action_l2_decap(dev, dev_flow,
9593 dev_flow->dv.actions[actions_n++] =
9594 dev_flow->dv.encap_decap->action;
9595 action_flags |= MLX5_FLOW_ACTION_DECAP;
9597 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9598 /* Handle encap with preceding decap. */
9599 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9600 if (flow_dv_create_action_raw_encap
9601 (dev, actions, dev_flow, attr, error))
9603 dev_flow->dv.actions[actions_n++] =
9604 dev_flow->dv.encap_decap->action;
9606 /* Handle encap without preceding decap. */
9607 if (flow_dv_create_action_l2_encap
9608 (dev, actions, dev_flow, attr->transfer,
9611 dev_flow->dv.actions[actions_n++] =
9612 dev_flow->dv.encap_decap->action;
9614 action_flags |= MLX5_FLOW_ACTION_ENCAP;
9615 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9616 sample_act->action_flags |=
9617 MLX5_FLOW_ACTION_ENCAP;
9619 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9620 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9622 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9623 if (flow_dv_create_action_l2_decap
9624 (dev, dev_flow, attr->transfer, error))
9626 dev_flow->dv.actions[actions_n++] =
9627 dev_flow->dv.encap_decap->action;
9629 /* If decap is followed by encap, handle it at encap. */
9630 action_flags |= MLX5_FLOW_ACTION_DECAP;
9632 case RTE_FLOW_ACTION_TYPE_JUMP:
9633 jump_group = ((const struct rte_flow_action_jump *)
9634 action->conf)->group;
9635 grp_info.std_tbl_fix = 0;
9636 ret = mlx5_flow_group_to_table(dev, tunnel,
9642 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9644 !!dev_flow->external,
9648 return rte_flow_error_set
9650 RTE_FLOW_ERROR_TYPE_ACTION,
9652 "cannot create jump action.");
9653 if (flow_dv_jump_tbl_resource_register
9654 (dev, tbl, dev_flow, error)) {
9655 flow_dv_tbl_resource_release(dev, tbl);
9656 return rte_flow_error_set
9658 RTE_FLOW_ERROR_TYPE_ACTION,
9660 "cannot create jump action.");
9662 dev_flow->dv.actions[actions_n++] =
9663 dev_flow->dv.jump->action;
9664 action_flags |= MLX5_FLOW_ACTION_JUMP;
9665 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9667 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9668 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9669 if (flow_dv_convert_action_modify_mac
9670 (mhdr_res, actions, error))
9672 action_flags |= actions->type ==
9673 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9674 MLX5_FLOW_ACTION_SET_MAC_SRC :
9675 MLX5_FLOW_ACTION_SET_MAC_DST;
9677 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9678 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9679 if (flow_dv_convert_action_modify_ipv4
9680 (mhdr_res, actions, error))
9682 action_flags |= actions->type ==
9683 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9684 MLX5_FLOW_ACTION_SET_IPV4_SRC :
9685 MLX5_FLOW_ACTION_SET_IPV4_DST;
9687 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9688 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9689 if (flow_dv_convert_action_modify_ipv6
9690 (mhdr_res, actions, error))
9692 action_flags |= actions->type ==
9693 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9694 MLX5_FLOW_ACTION_SET_IPV6_SRC :
9695 MLX5_FLOW_ACTION_SET_IPV6_DST;
9697 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9698 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9699 if (flow_dv_convert_action_modify_tp
9700 (mhdr_res, actions, items,
9701 &flow_attr, dev_flow, !!(action_flags &
9702 MLX5_FLOW_ACTION_DECAP), error))
9704 action_flags |= actions->type ==
9705 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9706 MLX5_FLOW_ACTION_SET_TP_SRC :
9707 MLX5_FLOW_ACTION_SET_TP_DST;
9709 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9710 if (flow_dv_convert_action_modify_dec_ttl
9711 (mhdr_res, items, &flow_attr, dev_flow,
9713 MLX5_FLOW_ACTION_DECAP), error))
9715 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9717 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9718 if (flow_dv_convert_action_modify_ttl
9719 (mhdr_res, actions, items, &flow_attr,
9720 dev_flow, !!(action_flags &
9721 MLX5_FLOW_ACTION_DECAP), error))
9723 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9725 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9726 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9727 if (flow_dv_convert_action_modify_tcp_seq
9728 (mhdr_res, actions, error))
9730 action_flags |= actions->type ==
9731 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9732 MLX5_FLOW_ACTION_INC_TCP_SEQ :
9733 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9736 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9737 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9738 if (flow_dv_convert_action_modify_tcp_ack
9739 (mhdr_res, actions, error))
9741 action_flags |= actions->type ==
9742 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9743 MLX5_FLOW_ACTION_INC_TCP_ACK :
9744 MLX5_FLOW_ACTION_DEC_TCP_ACK;
9746 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9747 if (flow_dv_convert_action_set_reg
9748 (mhdr_res, actions, error))
9750 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9752 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9753 if (flow_dv_convert_action_copy_mreg
9754 (dev, mhdr_res, actions, error))
9756 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9758 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9759 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9760 dev_flow->handle->fate_action =
9761 MLX5_FLOW_FATE_DEFAULT_MISS;
9763 case RTE_FLOW_ACTION_TYPE_METER:
9764 mtr = actions->conf;
9766 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9769 return rte_flow_error_set(error,
9771 RTE_FLOW_ERROR_TYPE_ACTION,
9774 "or invalid parameters");
9775 flow->meter = fm->idx;
9777 /* Set the meter action. */
9779 fm = mlx5_ipool_get(priv->sh->ipool
9780 [MLX5_IPOOL_MTR], flow->meter);
9782 return rte_flow_error_set(error,
9784 RTE_FLOW_ERROR_TYPE_ACTION,
9787 "or invalid parameters");
9789 dev_flow->dv.actions[actions_n++] =
9790 fm->mfts->meter_action;
9791 action_flags |= MLX5_FLOW_ACTION_METER;
9793 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9794 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9797 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9799 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9800 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9803 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9805 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9806 sample_act_pos = actions_n;
9807 ret = flow_dv_translate_action_sample(dev,
9817 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9818 /* put encap action into group if work with port id */
9819 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9820 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9821 sample_act->action_flags |=
9822 MLX5_FLOW_ACTION_ENCAP;
9824 case RTE_FLOW_ACTION_TYPE_END:
9826 if (mhdr_res->actions_num) {
9827 /* create modify action if needed. */
9828 if (flow_dv_modify_hdr_resource_register
9829 (dev, mhdr_res, dev_flow, error))
9831 dev_flow->dv.actions[modify_action_position] =
9832 handle->dvh.modify_hdr->action;
9834 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9836 flow_dv_translate_create_counter(dev,
9837 dev_flow, count, age);
9840 return rte_flow_error_set
9842 RTE_FLOW_ERROR_TYPE_ACTION,
9844 "cannot create counter"
9846 dev_flow->dv.actions[actions_n] =
9847 (flow_dv_counter_get_by_idx(dev,
9848 flow->counter, NULL))->action;
9851 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9852 ret = flow_dv_create_action_sample(dev,
9861 return rte_flow_error_set
9863 RTE_FLOW_ERROR_TYPE_ACTION,
9865 "cannot create sample action");
9866 if (num_of_dest > 1) {
9867 dev_flow->dv.actions[sample_act_pos] =
9868 dev_flow->dv.dest_array_res->action;
9870 dev_flow->dv.actions[sample_act_pos] =
9871 dev_flow->dv.sample_res->verbs_action;
9878 if (mhdr_res->actions_num &&
9879 modify_action_position == UINT32_MAX)
9880 modify_action_position = actions_n++;
9883 * For multiple destination (sample action with ratio=1), the encap
9884 * action and port id action will be combined into group action.
9885 * So need remove the original these actions in the flow and only
9886 * use the sample action instead of.
9888 if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9890 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9892 for (i = 0; i < actions_n; i++) {
9893 if ((sample_act->dr_encap_action &&
9894 sample_act->dr_encap_action ==
9895 dev_flow->dv.actions[i]) ||
9896 (sample_act->dr_port_id_action &&
9897 sample_act->dr_port_id_action ==
9898 dev_flow->dv.actions[i]))
9900 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9902 memcpy((void *)dev_flow->dv.actions,
9903 (void *)temp_actions,
9904 tmp_actions_n * sizeof(void *));
9905 actions_n = tmp_actions_n;
9907 dev_flow->dv.actions_n = actions_n;
9908 dev_flow->act_flags = action_flags;
9909 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9910 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9911 int item_type = items->type;
9913 if (!mlx5_flow_os_item_supported(item_type))
9914 return rte_flow_error_set(error, ENOTSUP,
9915 RTE_FLOW_ERROR_TYPE_ITEM,
9916 NULL, "item not supported");
9917 switch (item_type) {
9918 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9919 flow_dv_translate_item_port_id(dev, match_mask,
9920 match_value, items);
9921 last_item = MLX5_FLOW_ITEM_PORT_ID;
9923 case RTE_FLOW_ITEM_TYPE_ETH:
9924 flow_dv_translate_item_eth(match_mask, match_value,
9926 dev_flow->dv.group);
9927 matcher.priority = action_flags &
9928 MLX5_FLOW_ACTION_DEFAULT_MISS &&
9929 !dev_flow->external ?
9930 MLX5_PRIORITY_MAP_L3 :
9931 MLX5_PRIORITY_MAP_L2;
9932 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9933 MLX5_FLOW_LAYER_OUTER_L2;
9935 case RTE_FLOW_ITEM_TYPE_VLAN:
9936 flow_dv_translate_item_vlan(dev_flow,
9937 match_mask, match_value,
9939 dev_flow->dv.group);
9940 matcher.priority = MLX5_PRIORITY_MAP_L2;
9941 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9942 MLX5_FLOW_LAYER_INNER_VLAN) :
9943 (MLX5_FLOW_LAYER_OUTER_L2 |
9944 MLX5_FLOW_LAYER_OUTER_VLAN);
9946 case RTE_FLOW_ITEM_TYPE_IPV4:
9947 mlx5_flow_tunnel_ip_check(items, next_protocol,
9948 &item_flags, &tunnel);
9949 flow_dv_translate_item_ipv4(match_mask, match_value,
9951 dev_flow->dv.group);
9952 matcher.priority = MLX5_PRIORITY_MAP_L3;
9953 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9954 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9955 if (items->mask != NULL &&
9956 ((const struct rte_flow_item_ipv4 *)
9957 items->mask)->hdr.next_proto_id) {
9959 ((const struct rte_flow_item_ipv4 *)
9960 (items->spec))->hdr.next_proto_id;
9962 ((const struct rte_flow_item_ipv4 *)
9963 (items->mask))->hdr.next_proto_id;
9965 /* Reset for inner layer. */
9966 next_protocol = 0xff;
9969 case RTE_FLOW_ITEM_TYPE_IPV6:
9970 mlx5_flow_tunnel_ip_check(items, next_protocol,
9971 &item_flags, &tunnel);
9972 flow_dv_translate_item_ipv6(match_mask, match_value,
9974 dev_flow->dv.group);
9975 matcher.priority = MLX5_PRIORITY_MAP_L3;
9976 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9977 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9978 if (items->mask != NULL &&
9979 ((const struct rte_flow_item_ipv6 *)
9980 items->mask)->hdr.proto) {
9982 ((const struct rte_flow_item_ipv6 *)
9983 items->spec)->hdr.proto;
9985 ((const struct rte_flow_item_ipv6 *)
9986 items->mask)->hdr.proto;
9988 /* Reset for inner layer. */
9989 next_protocol = 0xff;
9992 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9993 flow_dv_translate_item_ipv6_frag_ext(match_mask,
9996 last_item = tunnel ?
9997 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9998 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9999 if (items->mask != NULL &&
10000 ((const struct rte_flow_item_ipv6_frag_ext *)
10001 items->mask)->hdr.next_header) {
10003 ((const struct rte_flow_item_ipv6_frag_ext *)
10004 items->spec)->hdr.next_header;
10006 ((const struct rte_flow_item_ipv6_frag_ext *)
10007 items->mask)->hdr.next_header;
10009 /* Reset for inner layer. */
10010 next_protocol = 0xff;
10013 case RTE_FLOW_ITEM_TYPE_TCP:
10014 flow_dv_translate_item_tcp(match_mask, match_value,
10016 matcher.priority = MLX5_PRIORITY_MAP_L4;
10017 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10018 MLX5_FLOW_LAYER_OUTER_L4_TCP;
10020 case RTE_FLOW_ITEM_TYPE_UDP:
10021 flow_dv_translate_item_udp(match_mask, match_value,
10023 matcher.priority = MLX5_PRIORITY_MAP_L4;
10024 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10025 MLX5_FLOW_LAYER_OUTER_L4_UDP;
10027 case RTE_FLOW_ITEM_TYPE_GRE:
10028 flow_dv_translate_item_gre(match_mask, match_value,
10030 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10031 last_item = MLX5_FLOW_LAYER_GRE;
10033 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10034 flow_dv_translate_item_gre_key(match_mask,
10035 match_value, items);
10036 last_item = MLX5_FLOW_LAYER_GRE_KEY;
10038 case RTE_FLOW_ITEM_TYPE_NVGRE:
10039 flow_dv_translate_item_nvgre(match_mask, match_value,
10041 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10042 last_item = MLX5_FLOW_LAYER_GRE;
10044 case RTE_FLOW_ITEM_TYPE_VXLAN:
10045 flow_dv_translate_item_vxlan(match_mask, match_value,
10047 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10048 last_item = MLX5_FLOW_LAYER_VXLAN;
10050 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10051 flow_dv_translate_item_vxlan_gpe(match_mask,
10052 match_value, items,
10054 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10055 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10057 case RTE_FLOW_ITEM_TYPE_GENEVE:
10058 flow_dv_translate_item_geneve(match_mask, match_value,
10060 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10061 last_item = MLX5_FLOW_LAYER_GENEVE;
10063 case RTE_FLOW_ITEM_TYPE_MPLS:
10064 flow_dv_translate_item_mpls(match_mask, match_value,
10065 items, last_item, tunnel);
10066 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10067 last_item = MLX5_FLOW_LAYER_MPLS;
10069 case RTE_FLOW_ITEM_TYPE_MARK:
10070 flow_dv_translate_item_mark(dev, match_mask,
10071 match_value, items);
10072 last_item = MLX5_FLOW_ITEM_MARK;
10074 case RTE_FLOW_ITEM_TYPE_META:
10075 flow_dv_translate_item_meta(dev, match_mask,
10076 match_value, attr, items);
10077 last_item = MLX5_FLOW_ITEM_METADATA;
10079 case RTE_FLOW_ITEM_TYPE_ICMP:
10080 flow_dv_translate_item_icmp(match_mask, match_value,
10082 last_item = MLX5_FLOW_LAYER_ICMP;
10084 case RTE_FLOW_ITEM_TYPE_ICMP6:
10085 flow_dv_translate_item_icmp6(match_mask, match_value,
10087 last_item = MLX5_FLOW_LAYER_ICMP6;
10089 case RTE_FLOW_ITEM_TYPE_TAG:
10090 flow_dv_translate_item_tag(dev, match_mask,
10091 match_value, items);
10092 last_item = MLX5_FLOW_ITEM_TAG;
10094 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10095 flow_dv_translate_mlx5_item_tag(dev, match_mask,
10096 match_value, items);
10097 last_item = MLX5_FLOW_ITEM_TAG;
10099 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10100 flow_dv_translate_item_tx_queue(dev, match_mask,
10103 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10105 case RTE_FLOW_ITEM_TYPE_GTP:
10106 flow_dv_translate_item_gtp(match_mask, match_value,
10108 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10109 last_item = MLX5_FLOW_LAYER_GTP;
10111 case RTE_FLOW_ITEM_TYPE_ECPRI:
10112 if (!mlx5_flex_parser_ecpri_exist(dev)) {
10113 /* Create it only the first time to be used. */
10114 ret = mlx5_flex_parser_ecpri_alloc(dev);
10116 return rte_flow_error_set
10118 RTE_FLOW_ERROR_TYPE_ITEM,
10120 "cannot create eCPRI parser");
10122 /* Adjust the length matcher and device flow value. */
10123 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10124 dev_flow->dv.value.size =
10125 MLX5_ST_SZ_BYTES(fte_match_param);
10126 flow_dv_translate_item_ecpri(dev, match_mask,
10127 match_value, items);
10128 /* No other protocol should follow eCPRI layer. */
10129 last_item = MLX5_FLOW_LAYER_ECPRI;
10134 item_flags |= last_item;
10137 * When E-Switch mode is enabled, we have two cases where we need to
10138 * set the source port manually.
10139 * The first one, is in case of Nic steering rule, and the second is
10140 * E-Switch rule where no port_id item was found. In both cases
10141 * the source port is set according the current port in use.
10143 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10144 (priv->representor || priv->master)) {
10145 if (flow_dv_translate_item_port_id(dev, match_mask,
10146 match_value, NULL))
10149 #ifdef RTE_LIBRTE_MLX5_DEBUG
10150 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10151 dev_flow->dv.value.buf));
10154 * Layers may be already initialized from prefix flow if this dev_flow
10155 * is the suffix flow.
10157 handle->layers |= item_flags;
10158 if (action_flags & MLX5_FLOW_ACTION_RSS)
10159 flow_dv_hashfields_set(dev_flow, rss_desc);
10160 /* Register matcher. */
10161 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10162 matcher.mask.size);
10163 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10165 /* reserved field no needs to be set to 0 here. */
10166 tbl_key.domain = attr->transfer;
10167 tbl_key.direction = attr->egress;
10168 tbl_key.table_id = dev_flow->dv.group;
10169 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10175 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10178 * @param[in, out] action
10179 * Shred RSS action holding hash RX queue objects.
10180 * @param[in] hash_fields
10181 * Defines combination of packet fields to participate in RX hash.
10182 * @param[in] tunnel
10184 * @param[in] hrxq_idx
10185 * Hash RX queue index to set.
10188 * 0 on success, otherwise negative errno value.
10191 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10192 const uint64_t hash_fields,
10196 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10198 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10199 case MLX5_RSS_HASH_IPV4:
10200 hrxqs[0] = hrxq_idx;
10202 case MLX5_RSS_HASH_IPV4_TCP:
10203 hrxqs[1] = hrxq_idx;
10205 case MLX5_RSS_HASH_IPV4_UDP:
10206 hrxqs[2] = hrxq_idx;
10208 case MLX5_RSS_HASH_IPV6:
10209 hrxqs[3] = hrxq_idx;
10211 case MLX5_RSS_HASH_IPV6_TCP:
10212 hrxqs[4] = hrxq_idx;
10214 case MLX5_RSS_HASH_IPV6_UDP:
10215 hrxqs[5] = hrxq_idx;
10217 case MLX5_RSS_HASH_NONE:
10218 hrxqs[6] = hrxq_idx;
10226 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10229 * @param[in] action
10230 * Shred RSS action holding hash RX queue objects.
10231 * @param[in] hash_fields
10232 * Defines combination of packet fields to participate in RX hash.
10233 * @param[in] tunnel
10237 * Valid hash RX queue index, otherwise 0.
10240 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10241 const uint64_t hash_fields,
10244 const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10246 switch (hash_fields & ~IBV_RX_HASH_INNER) {
10247 case MLX5_RSS_HASH_IPV4:
10249 case MLX5_RSS_HASH_IPV4_TCP:
10251 case MLX5_RSS_HASH_IPV4_UDP:
10253 case MLX5_RSS_HASH_IPV6:
10255 case MLX5_RSS_HASH_IPV6_TCP:
10257 case MLX5_RSS_HASH_IPV6_UDP:
10259 case MLX5_RSS_HASH_NONE:
10267 * Retrieves hash RX queue suitable for the *flow*.
10268 * If shared action configured for *flow* suitable hash RX queue will be
10269 * retrieved from attached shared action.
10272 * Shred RSS action holding hash RX queue objects.
10273 * @param[in] dev_flow
10274 * Pointer to the sub flow.
10276 * Pointer to retrieved hash RX queue object.
10279 * Valid hash RX queue index, otherwise 0 and rte_errno is set.
10282 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10283 struct mlx5_flow *dev_flow,
10284 struct mlx5_hrxq **hrxq)
10286 struct mlx5_priv *priv = dev->data->dev_private;
10287 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10290 if (flow->shared_rss) {
10291 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10292 (flow->shared_rss, dev_flow->hash_fields,
10293 !!(dev_flow->handle->layers &
10294 MLX5_FLOW_LAYER_TUNNEL));
10296 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10298 __atomic_fetch_add(&(*hrxq)->refcnt, 1,
10302 struct mlx5_flow_rss_desc *rss_desc =
10303 &wks->rss_desc[!!wks->flow_nested_idx];
10305 MLX5_ASSERT(rss_desc->queue_num);
10306 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
10307 MLX5_RSS_HASH_KEY_LEN,
10308 dev_flow->hash_fields,
10309 rss_desc->queue, rss_desc->queue_num);
10311 hrxq_idx = mlx5_hrxq_new(dev,
10313 MLX5_RSS_HASH_KEY_LEN,
10314 dev_flow->hash_fields,
10316 rss_desc->queue_num,
10317 !!(dev_flow->handle->layers &
10318 MLX5_FLOW_LAYER_TUNNEL),
10321 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10328 * Apply the flow to the NIC, lock free,
10329 * (mutex should be acquired by caller).
10332 * Pointer to the Ethernet device structure.
10333 * @param[in, out] flow
10334 * Pointer to flow structure.
10335 * @param[out] error
10336 * Pointer to error structure.
10339 * 0 on success, a negative errno value otherwise and rte_errno is set.
10342 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10343 struct rte_flow_error *error)
10345 struct mlx5_flow_dv_workspace *dv;
10346 struct mlx5_flow_handle *dh;
10347 struct mlx5_flow_handle_dv *dv_h;
10348 struct mlx5_flow *dev_flow;
10349 struct mlx5_priv *priv = dev->data->dev_private;
10350 uint32_t handle_idx;
10354 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10357 for (idx = wks->flow_idx - 1; idx >= wks->flow_nested_idx; idx--) {
10358 dev_flow = &wks->flows[idx];
10359 dv = &dev_flow->dv;
10360 dh = dev_flow->handle;
10363 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10364 if (dv->transfer) {
10365 dv->actions[n++] = priv->sh->esw_drop_action;
10367 struct mlx5_hrxq *drop_hrxq;
10368 drop_hrxq = mlx5_drop_action_create(dev);
10372 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10374 "cannot get drop hash queue");
10378 * Drop queues will be released by the specify
10379 * mlx5_drop_action_destroy() function. Assign
10380 * the special index to hrxq to mark the queue
10381 * has been allocated.
10383 dh->rix_hrxq = UINT32_MAX;
10384 dv->actions[n++] = drop_hrxq->action;
10386 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10387 !dv_h->rix_sample && !dv_h->rix_dest_array) {
10388 struct mlx5_hrxq *hrxq = NULL;
10389 uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10390 (dev, flow, dev_flow, &hrxq);
10395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10396 "cannot get hash queue");
10399 dh->rix_hrxq = hrxq_idx;
10400 dv->actions[n++] = hrxq->action;
10401 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10402 if (flow_dv_default_miss_resource_register
10406 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10407 "cannot create default miss resource");
10408 goto error_default_miss;
10410 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
10411 dv->actions[n++] = priv->sh->default_miss.action;
10413 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10414 (void *)&dv->value, n,
10415 dv->actions, &dh->drv_flow);
10417 rte_flow_error_set(error, errno,
10418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10420 "hardware refuses to create flow");
10423 if (priv->vmwa_context &&
10424 dh->vf_vlan.tag && !dh->vf_vlan.created) {
10426 * The rule contains the VLAN pattern.
10427 * For VF we are going to create VLAN
10428 * interface to make hypervisor set correct
10429 * e-Switch vport context.
10431 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10436 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10437 flow_dv_default_miss_resource_release(dev);
10438 error_default_miss:
10439 err = rte_errno; /* Save rte_errno before cleanup. */
10440 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10441 handle_idx, dh, next) {
10442 /* hrxq is union, don't clear it if the flag is not set. */
10443 if (dh->rix_hrxq) {
10444 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10445 mlx5_drop_action_destroy(dev);
10447 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
10448 mlx5_hrxq_release(dev, dh->rix_hrxq);
10452 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10453 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10455 rte_errno = err; /* Restore rte_errno. */
10460 * Release the flow matcher.
10463 * Pointer to Ethernet device.
10465 * Pointer to mlx5_flow_handle.
10468 * 1 while a reference on it exists, 0 when freed.
10471 flow_dv_matcher_release(struct rte_eth_dev *dev,
10472 struct mlx5_flow_handle *handle)
10474 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10476 MLX5_ASSERT(matcher->matcher_object);
10477 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10478 dev->data->port_id, (void *)matcher,
10479 __atomic_load_n(&matcher->refcnt, __ATOMIC_RELAXED));
10480 if (__atomic_sub_fetch(&matcher->refcnt, 1, __ATOMIC_RELAXED) == 0) {
10481 claim_zero(mlx5_flow_os_destroy_flow_matcher
10482 (matcher->matcher_object));
10483 LIST_REMOVE(matcher, next);
10484 /* table ref-- in release interface. */
10485 flow_dv_tbl_resource_release(dev, matcher->tbl);
10486 mlx5_free(matcher);
10487 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10488 dev->data->port_id, (void *)matcher);
10495 * Release an encap/decap resource.
10498 * Pointer to Ethernet device.
10499 * @param encap_decap_idx
10500 * Index of encap decap resource.
10503 * 1 while a reference on it exists, 0 when freed.
10506 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10507 uint32_t encap_decap_idx)
10509 struct mlx5_priv *priv = dev->data->dev_private;
10510 uint32_t idx = encap_decap_idx;
10511 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10513 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10515 if (!cache_resource)
10517 MLX5_ASSERT(cache_resource->action);
10518 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
10519 (void *)cache_resource,
10520 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10521 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10522 __ATOMIC_RELAXED) == 0) {
10523 claim_zero(mlx5_flow_os_destroy_flow_action
10524 (cache_resource->action));
10525 mlx5_hlist_remove(priv->sh->encaps_decaps,
10526 &cache_resource->entry);
10527 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
10528 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
10529 (void *)cache_resource);
10536 * Release an jump to table action resource.
10539 * Pointer to Ethernet device.
10541 * Pointer to mlx5_flow_handle.
10544 * 1 while a reference on it exists, 0 when freed.
10547 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10548 struct mlx5_flow_handle *handle)
10550 struct mlx5_priv *priv = dev->data->dev_private;
10551 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
10552 struct mlx5_flow_tbl_data_entry *tbl_data;
10554 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10558 cache_resource = &tbl_data->jump;
10559 MLX5_ASSERT(cache_resource->action);
10560 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
10561 (void *)cache_resource,
10562 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10563 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10564 __ATOMIC_RELAXED) == 0) {
10565 claim_zero(mlx5_flow_os_destroy_flow_action
10566 (cache_resource->action));
10567 /* jump action memory free is inside the table release. */
10568 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10569 DRV_LOG(DEBUG, "jump table resource %p: removed",
10570 (void *)cache_resource);
10577 * Release a default miss resource.
10580 * Pointer to Ethernet device.
10582 * 1 while a reference on it exists, 0 when freed.
10585 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
10587 struct mlx5_priv *priv = dev->data->dev_private;
10588 struct mlx5_dev_ctx_shared *sh = priv->sh;
10589 struct mlx5_flow_default_miss_resource *cache_resource =
10592 MLX5_ASSERT(cache_resource->action);
10593 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
10594 (void *)cache_resource->action,
10595 __atomic_load_n(&cache_resource->refcnt,
10596 __ATOMIC_RELAXED));
10597 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10598 __ATOMIC_RELAXED) == 0) {
10599 claim_zero(mlx5_glue->destroy_flow_action
10600 (cache_resource->action));
10601 DRV_LOG(DEBUG, "default miss resource %p: removed",
10602 (void *)cache_resource->action);
10609 * Release a modify-header resource.
10612 * Pointer to Ethernet device.
10614 * Pointer to mlx5_flow_handle.
10617 * 1 while a reference on it exists, 0 when freed.
10620 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10621 struct mlx5_flow_handle *handle)
10623 struct mlx5_priv *priv = dev->data->dev_private;
10624 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
10625 handle->dvh.modify_hdr;
10627 MLX5_ASSERT(cache_resource->action);
10628 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
10629 (void *)cache_resource,
10630 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10631 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10632 __ATOMIC_RELAXED) == 0) {
10633 claim_zero(mlx5_flow_os_destroy_flow_action
10634 (cache_resource->action));
10635 mlx5_hlist_remove(priv->sh->modify_cmds,
10636 &cache_resource->entry);
10637 mlx5_free(cache_resource);
10638 DRV_LOG(DEBUG, "modify-header resource %p: removed",
10639 (void *)cache_resource);
10646 * Release port ID action resource.
10649 * Pointer to Ethernet device.
10651 * Pointer to mlx5_flow_handle.
10654 * 1 while a reference on it exists, 0 when freed.
10657 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10660 struct mlx5_priv *priv = dev->data->dev_private;
10661 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10662 uint32_t idx = port_id;
10664 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10666 if (!cache_resource)
10668 MLX5_ASSERT(cache_resource->action);
10669 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10670 (void *)cache_resource,
10671 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10672 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10673 __ATOMIC_RELAXED) == 0) {
10674 claim_zero(mlx5_flow_os_destroy_flow_action
10675 (cache_resource->action));
10676 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10677 &priv->sh->port_id_action_list, idx,
10678 cache_resource, next);
10679 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10680 DRV_LOG(DEBUG, "port id action resource %p: removed",
10681 (void *)cache_resource);
10688 * Release push vlan action resource.
10691 * Pointer to Ethernet device.
10693 * Pointer to mlx5_flow_handle.
10696 * 1 while a reference on it exists, 0 when freed.
10699 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10700 struct mlx5_flow_handle *handle)
10702 struct mlx5_priv *priv = dev->data->dev_private;
10703 uint32_t idx = handle->dvh.rix_push_vlan;
10704 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10706 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10708 if (!cache_resource)
10710 MLX5_ASSERT(cache_resource->action);
10711 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10712 (void *)cache_resource,
10713 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10714 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10715 __ATOMIC_RELAXED) == 0) {
10716 claim_zero(mlx5_flow_os_destroy_flow_action
10717 (cache_resource->action));
10718 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10719 &priv->sh->push_vlan_action_list, idx,
10720 cache_resource, next);
10721 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10722 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10723 (void *)cache_resource);
10730 * Release the fate resource.
10733 * Pointer to Ethernet device.
10735 * Pointer to mlx5_flow_handle.
10738 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10739 struct mlx5_flow_handle *handle)
10741 if (!handle->rix_fate)
10743 switch (handle->fate_action) {
10744 case MLX5_FLOW_FATE_DROP:
10745 mlx5_drop_action_destroy(dev);
10747 case MLX5_FLOW_FATE_QUEUE:
10748 mlx5_hrxq_release(dev, handle->rix_hrxq);
10750 case MLX5_FLOW_FATE_JUMP:
10751 flow_dv_jump_tbl_resource_release(dev, handle);
10753 case MLX5_FLOW_FATE_PORT_ID:
10754 flow_dv_port_id_action_resource_release(dev,
10755 handle->rix_port_id_action);
10757 case MLX5_FLOW_FATE_DEFAULT_MISS:
10758 flow_dv_default_miss_resource_release(dev);
10761 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10764 handle->rix_fate = 0;
10768 * Release an sample resource.
10771 * Pointer to Ethernet device.
10773 * Pointer to mlx5_flow_handle.
10776 * 1 while a reference on it exists, 0 when freed.
10779 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10780 struct mlx5_flow_handle *handle)
10782 struct mlx5_priv *priv = dev->data->dev_private;
10783 uint32_t idx = handle->dvh.rix_sample;
10784 struct mlx5_flow_dv_sample_resource *cache_resource;
10786 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10788 if (!cache_resource)
10790 MLX5_ASSERT(cache_resource->verbs_action);
10791 DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10792 (void *)cache_resource,
10793 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10794 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10795 __ATOMIC_RELAXED) == 0) {
10796 if (cache_resource->verbs_action)
10797 claim_zero(mlx5_glue->destroy_flow_action
10798 (cache_resource->verbs_action));
10799 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10800 if (cache_resource->default_miss)
10801 claim_zero(mlx5_glue->destroy_flow_action
10802 (cache_resource->default_miss));
10804 if (cache_resource->normal_path_tbl)
10805 flow_dv_tbl_resource_release(dev,
10806 cache_resource->normal_path_tbl);
10808 if (cache_resource->sample_idx.rix_hrxq &&
10809 !mlx5_hrxq_release(dev,
10810 cache_resource->sample_idx.rix_hrxq))
10811 cache_resource->sample_idx.rix_hrxq = 0;
10812 if (cache_resource->sample_idx.rix_tag &&
10813 !flow_dv_tag_release(dev,
10814 cache_resource->sample_idx.rix_tag))
10815 cache_resource->sample_idx.rix_tag = 0;
10816 if (cache_resource->sample_idx.cnt) {
10817 flow_dv_counter_release(dev,
10818 cache_resource->sample_idx.cnt);
10819 cache_resource->sample_idx.cnt = 0;
10821 if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10822 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10823 &priv->sh->sample_action_list, idx,
10824 cache_resource, next);
10825 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10826 DRV_LOG(DEBUG, "sample resource %p: removed",
10827 (void *)cache_resource);
10834 * Release an destination array resource.
10837 * Pointer to Ethernet device.
10839 * Pointer to mlx5_flow_handle.
10842 * 1 while a reference on it exists, 0 when freed.
10845 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10846 struct mlx5_flow_handle *handle)
10848 struct mlx5_priv *priv = dev->data->dev_private;
10849 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10850 struct mlx5_flow_sub_actions_idx *mdest_act_res;
10851 uint32_t idx = handle->dvh.rix_dest_array;
10854 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10856 if (!cache_resource)
10858 MLX5_ASSERT(cache_resource->action);
10859 DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10860 (void *)cache_resource,
10861 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10862 if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10863 __ATOMIC_RELAXED) == 0) {
10864 if (cache_resource->action)
10865 claim_zero(mlx5_glue->destroy_flow_action
10866 (cache_resource->action));
10867 for (; i < cache_resource->num_of_dest; i++) {
10868 mdest_act_res = &cache_resource->sample_idx[i];
10869 if (mdest_act_res->rix_hrxq) {
10870 mlx5_hrxq_release(dev,
10871 mdest_act_res->rix_hrxq);
10872 mdest_act_res->rix_hrxq = 0;
10874 if (mdest_act_res->rix_encap_decap) {
10875 flow_dv_encap_decap_resource_release(dev,
10876 mdest_act_res->rix_encap_decap);
10877 mdest_act_res->rix_encap_decap = 0;
10879 if (mdest_act_res->rix_port_id_action) {
10880 flow_dv_port_id_action_resource_release(dev,
10881 mdest_act_res->rix_port_id_action);
10882 mdest_act_res->rix_port_id_action = 0;
10884 if (mdest_act_res->rix_tag) {
10885 flow_dv_tag_release(dev,
10886 mdest_act_res->rix_tag);
10887 mdest_act_res->rix_tag = 0;
10890 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10891 &priv->sh->dest_array_list, idx,
10892 cache_resource, next);
10893 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10894 DRV_LOG(DEBUG, "destination array resource %p: removed",
10895 (void *)cache_resource);
10902 * Remove the flow from the NIC but keeps it in memory.
10903 * Lock free, (mutex should be acquired by caller).
10906 * Pointer to Ethernet device.
10907 * @param[in, out] flow
10908 * Pointer to flow structure.
10911 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10913 struct mlx5_flow_handle *dh;
10914 uint32_t handle_idx;
10915 struct mlx5_priv *priv = dev->data->dev_private;
10919 handle_idx = flow->dev_handles;
10920 while (handle_idx) {
10921 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10925 if (dh->drv_flow) {
10926 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10927 dh->drv_flow = NULL;
10929 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
10930 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
10931 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10932 flow_dv_fate_resource_release(dev, dh);
10933 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10934 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10935 handle_idx = dh->next.next;
10940 * Remove the flow from the NIC and the memory.
10941 * Lock free, (mutex should be acquired by caller).
10944 * Pointer to the Ethernet device structure.
10945 * @param[in, out] flow
10946 * Pointer to flow structure.
10949 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10951 struct rte_flow_shared_action *shared;
10952 struct mlx5_flow_handle *dev_handle;
10953 struct mlx5_priv *priv = dev->data->dev_private;
10957 __flow_dv_remove(dev, flow);
10958 shared = mlx5_flow_get_shared_rss(flow);
10960 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10961 if (flow->counter) {
10962 flow_dv_counter_release(dev, flow->counter);
10966 struct mlx5_flow_meter *fm;
10968 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10971 mlx5_flow_meter_detach(fm);
10974 while (flow->dev_handles) {
10975 uint32_t tmp_idx = flow->dev_handles;
10977 dev_handle = mlx5_ipool_get(priv->sh->ipool
10978 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10981 flow->dev_handles = dev_handle->next.next;
10982 if (dev_handle->dvh.matcher)
10983 flow_dv_matcher_release(dev, dev_handle);
10984 if (dev_handle->dvh.rix_sample)
10985 flow_dv_sample_resource_release(dev, dev_handle);
10986 if (dev_handle->dvh.rix_dest_array)
10987 flow_dv_dest_array_resource_release(dev, dev_handle);
10988 if (dev_handle->dvh.rix_encap_decap)
10989 flow_dv_encap_decap_resource_release(dev,
10990 dev_handle->dvh.rix_encap_decap);
10991 if (dev_handle->dvh.modify_hdr)
10992 flow_dv_modify_hdr_resource_release(dev, dev_handle);
10993 if (dev_handle->dvh.rix_push_vlan)
10994 flow_dv_push_vlan_action_resource_release(dev,
10996 if (dev_handle->dvh.rix_tag)
10997 flow_dv_tag_release(dev,
10998 dev_handle->dvh.rix_tag);
10999 flow_dv_fate_resource_release(dev, dev_handle);
11000 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11006 * Release array of hash RX queue objects.
11010 * Pointer to the Ethernet device structure.
11011 * @param[in, out] hrxqs
11012 * Array of hash RX queue objects.
11015 * Total number of references to hash RX queue objects in *hrxqs* array
11016 * after this operation.
11019 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11020 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11025 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11026 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11036 * Release all hash RX queue objects representing shared RSS action.
11039 * Pointer to the Ethernet device structure.
11040 * @param[in, out] action
11041 * Shared RSS action to remove hash RX queue objects from.
11044 * Total number of references to hash RX queue objects stored in *action*
11045 * after this operation.
11046 * Expected to be 0 if no external references held.
11049 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11050 struct mlx5_shared_action_rss *action)
11052 return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11053 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11057 * Setup shared RSS action.
11058 * Prepare set of hash RX queue objects sufficient to handle all valid
11059 * hash_fields combinations (see enum ibv_rx_hash_fields).
11062 * Pointer to the Ethernet device structure.
11063 * @param[in, out] action
11064 * Partially initialized shared RSS action.
11065 * @param[out] error
11066 * Perform verbose error reporting if not NULL. Initialized in case of
11070 * 0 on success, otherwise negative errno value.
11073 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11074 struct mlx5_shared_action_rss *action,
11075 struct rte_flow_error *error)
11080 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11082 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11085 for (tunnel = 0; tunnel < 2; tunnel++) {
11086 hrxq_idx = mlx5_hrxq_new(dev, action->origin.key,
11087 MLX5_RSS_HASH_KEY_LEN,
11089 action->origin.queue,
11090 action->origin.queue_num,
11095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11096 "cannot get hash queue");
11097 goto error_hrxq_new;
11099 err = __flow_dv_action_rss_hrxq_set
11100 (action, hash_fields, tunnel, hrxq_idx);
11107 __flow_dv_action_rss_hrxqs_release(dev, action);
11113 * Create shared RSS action.
11116 * Pointer to the Ethernet device structure.
11118 * Shared action configuration.
11120 * RSS action specification used to create shared action.
11121 * @param[out] error
11122 * Perform verbose error reporting if not NULL. Initialized in case of
11126 * A valid shared action handle in case of success, NULL otherwise and
11127 * rte_errno is set.
11129 static struct rte_flow_shared_action *
11130 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11131 const struct rte_flow_shared_action_conf *conf,
11132 const struct rte_flow_action_rss *rss,
11133 struct rte_flow_error *error)
11135 struct rte_flow_shared_action *shared_action = NULL;
11136 void *queue = NULL;
11137 struct mlx5_shared_action_rss *shared_rss;
11138 struct rte_flow_action_rss *origin;
11139 const uint8_t *rss_key;
11140 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11142 RTE_SET_USED(conf);
11143 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11145 shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11147 if (!shared_action || !queue) {
11148 rte_flow_error_set(error, ENOMEM,
11149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11150 "cannot allocate resource memory");
11151 goto error_rss_init;
11153 shared_rss = &shared_action->rss;
11154 shared_rss->queue = queue;
11155 origin = &shared_rss->origin;
11156 origin->func = rss->func;
11157 origin->level = rss->level;
11158 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11159 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11160 /* NULL RSS key indicates default RSS key. */
11161 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11162 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11163 origin->key = &shared_rss->key[0];
11164 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11165 memcpy(shared_rss->queue, rss->queue, queue_size);
11166 origin->queue = shared_rss->queue;
11167 origin->queue_num = rss->queue_num;
11168 if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11169 goto error_rss_init;
11170 shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11171 return shared_action;
11173 mlx5_free(shared_action);
11179 * Destroy the shared RSS action.
11180 * Release related hash RX queue objects.
11183 * Pointer to the Ethernet device structure.
11184 * @param[in] shared_rss
11185 * The shared RSS action object to be removed.
11186 * @param[out] error
11187 * Perform verbose error reporting if not NULL. Initialized in case of
11191 * 0 on success, otherwise negative errno value.
11194 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11195 struct mlx5_shared_action_rss *shared_rss,
11196 struct rte_flow_error *error)
11198 struct rte_flow_shared_action *shared_action = NULL;
11199 uint32_t old_refcnt = 1;
11200 int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11203 return rte_flow_error_set(error, ETOOMANYREFS,
11204 RTE_FLOW_ERROR_TYPE_ACTION,
11206 "shared rss hrxq has references");
11208 shared_action = container_of(shared_rss,
11209 struct rte_flow_shared_action, rss);
11210 if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11212 __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11213 return rte_flow_error_set(error, ETOOMANYREFS,
11214 RTE_FLOW_ERROR_TYPE_ACTION,
11216 "shared rss has references");
11218 rte_free(shared_rss->queue);
11223 * Create shared action, lock free,
11224 * (mutex should be acquired by caller).
11225 * Dispatcher for action type specific call.
11228 * Pointer to the Ethernet device structure.
11230 * Shared action configuration.
11231 * @param[in] action
11232 * Action specification used to create shared action.
11233 * @param[out] error
11234 * Perform verbose error reporting if not NULL. Initialized in case of
11238 * A valid shared action handle in case of success, NULL otherwise and
11239 * rte_errno is set.
11241 static struct rte_flow_shared_action *
11242 __flow_dv_action_create(struct rte_eth_dev *dev,
11243 const struct rte_flow_shared_action_conf *conf,
11244 const struct rte_flow_action *action,
11245 struct rte_flow_error *error)
11247 struct rte_flow_shared_action *shared_action = NULL;
11248 struct mlx5_priv *priv = dev->data->dev_private;
11250 switch (action->type) {
11251 case RTE_FLOW_ACTION_TYPE_RSS:
11252 shared_action = __flow_dv_action_rss_create(dev, conf,
11257 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11258 NULL, "action type not supported");
11261 if (shared_action) {
11262 __atomic_add_fetch(&shared_action->refcnt, 1,
11264 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11266 return shared_action;
11270 * Destroy the shared action.
11271 * Release action related resources on the NIC and the memory.
11272 * Lock free, (mutex should be acquired by caller).
11273 * Dispatcher for action type specific call.
11276 * Pointer to the Ethernet device structure.
11277 * @param[in] action
11278 * The shared action object to be removed.
11279 * @param[out] error
11280 * Perform verbose error reporting if not NULL. Initialized in case of
11284 * 0 on success, otherwise negative errno value.
11287 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11288 struct rte_flow_shared_action *action,
11289 struct rte_flow_error *error)
11293 switch (action->type) {
11294 case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11295 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11298 return rte_flow_error_set(error, ENOTSUP,
11299 RTE_FLOW_ERROR_TYPE_ACTION,
11301 "action type not supported");
11305 LIST_REMOVE(action, next);
11311 * Updates in place shared RSS action configuration.
11314 * Pointer to the Ethernet device structure.
11315 * @param[in] shared_rss
11316 * The shared RSS action object to be updated.
11317 * @param[in] action_conf
11318 * RSS action specification used to modify *shared_rss*.
11319 * @param[out] error
11320 * Perform verbose error reporting if not NULL. Initialized in case of
11324 * 0 on success, otherwise negative errno value.
11325 * @note: currently only support update of RSS queues.
11328 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11329 struct mlx5_shared_action_rss *shared_rss,
11330 const struct rte_flow_action_rss *action_conf,
11331 struct rte_flow_error *error)
11335 void *queue = NULL;
11336 const uint8_t *rss_key;
11337 uint32_t rss_key_len;
11338 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11340 queue = mlx5_malloc(MLX5_MEM_ZERO,
11341 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11344 return rte_flow_error_set(error, ENOMEM,
11345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11347 "cannot allocate resource memory");
11348 if (action_conf->key) {
11349 rss_key = action_conf->key;
11350 rss_key_len = action_conf->key_len;
11352 rss_key = rss_hash_default_key;
11353 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11355 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11357 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11360 for (tunnel = 0; tunnel < 2; tunnel++) {
11361 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11362 (shared_rss, hash_fields, tunnel);
11363 MLX5_ASSERT(hrxq_idx);
11364 ret = mlx5_hrxq_modify
11366 rss_key, rss_key_len,
11368 action_conf->queue, action_conf->queue_num);
11371 return rte_flow_error_set
11373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11374 "cannot update hash queue");
11378 mlx5_free(shared_rss->queue);
11379 shared_rss->queue = queue;
11380 memcpy(shared_rss->queue, action_conf->queue, queue_size);
11381 shared_rss->origin.queue = shared_rss->queue;
11382 shared_rss->origin.queue_num = action_conf->queue_num;
11387 * Updates in place shared action configuration, lock free,
11388 * (mutex should be acquired by caller).
11391 * Pointer to the Ethernet device structure.
11392 * @param[in] action
11393 * The shared action object to be updated.
11394 * @param[in] action_conf
11395 * Action specification used to modify *action*.
11396 * *action_conf* should be of type correlating with type of the *action*,
11397 * otherwise considered as invalid.
11398 * @param[out] error
11399 * Perform verbose error reporting if not NULL. Initialized in case of
11403 * 0 on success, otherwise negative errno value.
11406 __flow_dv_action_update(struct rte_eth_dev *dev,
11407 struct rte_flow_shared_action *action,
11408 const void *action_conf,
11409 struct rte_flow_error *error)
11411 switch (action->type) {
11412 case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11413 return __flow_dv_action_rss_update(dev, &action->rss,
11414 action_conf, error);
11416 return rte_flow_error_set(error, ENOTSUP,
11417 RTE_FLOW_ERROR_TYPE_ACTION,
11419 "action type not supported");
11423 * Query a dv flow rule for its statistics via devx.
11426 * Pointer to Ethernet device.
11428 * Pointer to the sub flow.
11430 * data retrieved by the query.
11431 * @param[out] error
11432 * Perform verbose error reporting if not NULL.
11435 * 0 on success, a negative errno value otherwise and rte_errno is set.
11438 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11439 void *data, struct rte_flow_error *error)
11441 struct mlx5_priv *priv = dev->data->dev_private;
11442 struct rte_flow_query_count *qc = data;
11444 if (!priv->config.devx)
11445 return rte_flow_error_set(error, ENOTSUP,
11446 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11448 "counters are not supported");
11449 if (flow->counter) {
11450 uint64_t pkts, bytes;
11451 struct mlx5_flow_counter *cnt;
11453 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11455 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11459 return rte_flow_error_set(error, -err,
11460 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11461 NULL, "cannot read counters");
11464 qc->hits = pkts - cnt->hits;
11465 qc->bytes = bytes - cnt->bytes;
11468 cnt->bytes = bytes;
11472 return rte_flow_error_set(error, EINVAL,
11473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11475 "counters are not available");
11479 * Query a flow rule AGE action for aging information.
11482 * Pointer to Ethernet device.
11484 * Pointer to the sub flow.
11486 * data retrieved by the query.
11487 * @param[out] error
11488 * Perform verbose error reporting if not NULL.
11491 * 0 on success, a negative errno value otherwise and rte_errno is set.
11494 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11495 void *data, struct rte_flow_error *error)
11497 struct rte_flow_query_age *resp = data;
11499 if (flow->counter) {
11500 struct mlx5_age_param *age_param =
11501 flow_dv_counter_idx_get_age(dev, flow->counter);
11503 if (!age_param || !age_param->timeout)
11504 return rte_flow_error_set
11506 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11507 NULL, "cannot read age data");
11508 resp->aged = __atomic_load_n(&age_param->state,
11509 __ATOMIC_RELAXED) ==
11511 resp->sec_since_last_hit_valid = !resp->aged;
11512 if (resp->sec_since_last_hit_valid)
11513 resp->sec_since_last_hit =
11514 __atomic_load_n(&age_param->sec_since_last_hit,
11518 return rte_flow_error_set(error, EINVAL,
11519 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11521 "age data not available");
11527 * @see rte_flow_query()
11528 * @see rte_flow_ops
11531 flow_dv_query(struct rte_eth_dev *dev,
11532 struct rte_flow *flow __rte_unused,
11533 const struct rte_flow_action *actions __rte_unused,
11534 void *data __rte_unused,
11535 struct rte_flow_error *error __rte_unused)
11539 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11540 switch (actions->type) {
11541 case RTE_FLOW_ACTION_TYPE_VOID:
11543 case RTE_FLOW_ACTION_TYPE_COUNT:
11544 ret = flow_dv_query_count(dev, flow, data, error);
11546 case RTE_FLOW_ACTION_TYPE_AGE:
11547 ret = flow_dv_query_age(dev, flow, data, error);
11550 return rte_flow_error_set(error, ENOTSUP,
11551 RTE_FLOW_ERROR_TYPE_ACTION,
11553 "action not supported");
11560 * Destroy the meter table set.
11561 * Lock free, (mutex should be acquired by caller).
11564 * Pointer to Ethernet device.
11566 * Pointer to the meter table set.
11572 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11573 struct mlx5_meter_domains_infos *tbl)
11575 struct mlx5_priv *priv = dev->data->dev_private;
11576 struct mlx5_meter_domains_infos *mtd =
11577 (struct mlx5_meter_domains_infos *)tbl;
11579 if (!mtd || !priv->config.dv_flow_en)
11581 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11582 claim_zero(mlx5_flow_os_destroy_flow
11583 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11584 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11585 claim_zero(mlx5_flow_os_destroy_flow
11586 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11587 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11588 claim_zero(mlx5_flow_os_destroy_flow
11589 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11590 if (mtd->egress.color_matcher)
11591 claim_zero(mlx5_flow_os_destroy_flow_matcher
11592 (mtd->egress.color_matcher));
11593 if (mtd->egress.any_matcher)
11594 claim_zero(mlx5_flow_os_destroy_flow_matcher
11595 (mtd->egress.any_matcher));
11596 if (mtd->egress.tbl)
11597 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11598 if (mtd->egress.sfx_tbl)
11599 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11600 if (mtd->ingress.color_matcher)
11601 claim_zero(mlx5_flow_os_destroy_flow_matcher
11602 (mtd->ingress.color_matcher));
11603 if (mtd->ingress.any_matcher)
11604 claim_zero(mlx5_flow_os_destroy_flow_matcher
11605 (mtd->ingress.any_matcher));
11606 if (mtd->ingress.tbl)
11607 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11608 if (mtd->ingress.sfx_tbl)
11609 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11610 if (mtd->transfer.color_matcher)
11611 claim_zero(mlx5_flow_os_destroy_flow_matcher
11612 (mtd->transfer.color_matcher));
11613 if (mtd->transfer.any_matcher)
11614 claim_zero(mlx5_flow_os_destroy_flow_matcher
11615 (mtd->transfer.any_matcher));
11616 if (mtd->transfer.tbl)
11617 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11618 if (mtd->transfer.sfx_tbl)
11619 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11620 if (mtd->drop_actn)
11621 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11626 /* Number of meter flow actions, count and jump or count and drop. */
11627 #define METER_ACTIONS 2
11630 * Create specify domain meter table and suffix table.
11633 * Pointer to Ethernet device.
11634 * @param[in,out] mtb
11635 * Pointer to DV meter table set.
11636 * @param[in] egress
11638 * @param[in] transfer
11640 * @param[in] color_reg_c_idx
11641 * Reg C index for color match.
11644 * 0 on success, -1 otherwise and rte_errno is set.
11647 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11648 struct mlx5_meter_domains_infos *mtb,
11649 uint8_t egress, uint8_t transfer,
11650 uint32_t color_reg_c_idx)
11652 struct mlx5_priv *priv = dev->data->dev_private;
11653 struct mlx5_dev_ctx_shared *sh = priv->sh;
11654 struct mlx5_flow_dv_match_params mask = {
11655 .size = sizeof(mask.buf),
11657 struct mlx5_flow_dv_match_params value = {
11658 .size = sizeof(value.buf),
11660 struct mlx5dv_flow_matcher_attr dv_attr = {
11661 .type = IBV_FLOW_ATTR_NORMAL,
11663 .match_criteria_enable = 0,
11664 .match_mask = (void *)&mask,
11666 void *actions[METER_ACTIONS];
11667 struct mlx5_meter_domain_info *dtb;
11668 struct rte_flow_error error;
11673 dtb = &mtb->transfer;
11675 dtb = &mtb->egress;
11677 dtb = &mtb->ingress;
11678 /* Create the meter table with METER level. */
11679 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11680 egress, transfer, false, NULL, 0,
11683 DRV_LOG(ERR, "Failed to create meter policer table.");
11686 /* Create the meter suffix table with SUFFIX level. */
11687 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11688 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11689 egress, transfer, false, NULL, 0,
11691 if (!dtb->sfx_tbl) {
11692 DRV_LOG(ERR, "Failed to create meter suffix table.");
11695 /* Create matchers, Any and Color. */
11696 dv_attr.priority = 3;
11697 dv_attr.match_criteria_enable = 0;
11698 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11699 &dtb->any_matcher);
11701 DRV_LOG(ERR, "Failed to create meter"
11702 " policer default matcher.");
11705 dv_attr.priority = 0;
11706 dv_attr.match_criteria_enable =
11707 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11708 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11709 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11710 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11711 &dtb->color_matcher);
11713 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11716 if (mtb->count_actns[RTE_MTR_DROPPED])
11717 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11718 actions[i++] = mtb->drop_actn;
11719 /* Default rule: lowest priority, match any, actions: drop. */
11720 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11722 &dtb->policer_rules[RTE_MTR_DROPPED]);
11724 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11733 * Create the needed meter and suffix tables.
11734 * Lock free, (mutex should be acquired by caller).
11737 * Pointer to Ethernet device.
11739 * Pointer to the flow meter.
11742 * Pointer to table set on success, NULL otherwise and rte_errno is set.
11744 static struct mlx5_meter_domains_infos *
11745 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11746 const struct mlx5_flow_meter *fm)
11748 struct mlx5_priv *priv = dev->data->dev_private;
11749 struct mlx5_meter_domains_infos *mtb;
11753 if (!priv->mtr_en) {
11754 rte_errno = ENOTSUP;
11757 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11759 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11762 /* Create meter count actions */
11763 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11764 struct mlx5_flow_counter *cnt;
11765 if (!fm->policer_stats.cnt[i])
11767 cnt = flow_dv_counter_get_by_idx(dev,
11768 fm->policer_stats.cnt[i], NULL);
11769 mtb->count_actns[i] = cnt->action;
11771 /* Create drop action. */
11772 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11774 DRV_LOG(ERR, "Failed to create drop action.");
11777 /* Egress meter table. */
11778 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11780 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11783 /* Ingress meter table. */
11784 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11786 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11789 /* FDB meter table. */
11790 if (priv->config.dv_esw_en) {
11791 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11792 priv->mtr_color_reg);
11794 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11800 flow_dv_destroy_mtr_tbl(dev, mtb);
11805 * Destroy domain policer rule.
11808 * Pointer to domain table.
11811 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11815 for (i = 0; i < RTE_MTR_DROPPED; i++) {
11816 if (dt->policer_rules[i]) {
11817 claim_zero(mlx5_flow_os_destroy_flow
11818 (dt->policer_rules[i]));
11819 dt->policer_rules[i] = NULL;
11822 if (dt->jump_actn) {
11823 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11824 dt->jump_actn = NULL;
11829 * Destroy policer rules.
11832 * Pointer to Ethernet device.
11834 * Pointer to flow meter structure.
11836 * Pointer to flow attributes.
11842 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11843 const struct mlx5_flow_meter *fm,
11844 const struct rte_flow_attr *attr)
11846 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11851 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11853 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11854 if (attr->transfer)
11855 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11860 * Create specify domain meter policer rule.
11863 * Pointer to flow meter structure.
11865 * Pointer to DV meter table set.
11866 * @param[in] mtr_reg_c
11867 * Color match REG_C.
11870 * 0 on success, -1 otherwise.
11873 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11874 struct mlx5_meter_domain_info *dtb,
11877 struct mlx5_flow_dv_match_params matcher = {
11878 .size = sizeof(matcher.buf),
11880 struct mlx5_flow_dv_match_params value = {
11881 .size = sizeof(value.buf),
11883 struct mlx5_meter_domains_infos *mtb = fm->mfts;
11884 void *actions[METER_ACTIONS];
11888 /* Create jump action. */
11889 if (!dtb->jump_actn)
11890 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11891 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11893 DRV_LOG(ERR, "Failed to create policer jump action.");
11896 for (i = 0; i < RTE_MTR_DROPPED; i++) {
11899 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11900 rte_col_2_mlx5_col(i), UINT8_MAX);
11901 if (mtb->count_actns[i])
11902 actions[j++] = mtb->count_actns[i];
11903 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11904 actions[j++] = mtb->drop_actn;
11906 actions[j++] = dtb->jump_actn;
11907 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11908 (void *)&value, j, actions,
11909 &dtb->policer_rules[i]);
11911 DRV_LOG(ERR, "Failed to create policer rule.");
11922 * Create policer rules.
11925 * Pointer to Ethernet device.
11927 * Pointer to flow meter structure.
11929 * Pointer to flow attributes.
11932 * 0 on success, -1 otherwise.
11935 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11936 struct mlx5_flow_meter *fm,
11937 const struct rte_flow_attr *attr)
11939 struct mlx5_priv *priv = dev->data->dev_private;
11940 struct mlx5_meter_domains_infos *mtb = fm->mfts;
11943 if (attr->egress) {
11944 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11945 priv->mtr_color_reg);
11947 DRV_LOG(ERR, "Failed to create egress policer.");
11951 if (attr->ingress) {
11952 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11953 priv->mtr_color_reg);
11955 DRV_LOG(ERR, "Failed to create ingress policer.");
11959 if (attr->transfer) {
11960 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11961 priv->mtr_color_reg);
11963 DRV_LOG(ERR, "Failed to create transfer policer.");
11969 flow_dv_destroy_policer_rules(dev, fm, attr);
11974 * Validate the batch counter support in root table.
11976 * Create a simple flow with invalid counter and drop action on root table to
11977 * validate if batch counter with offset on root table is supported or not.
11980 * Pointer to rte_eth_dev structure.
11983 * 0 on success, a negative errno value otherwise and rte_errno is set.
11986 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11988 struct mlx5_priv *priv = dev->data->dev_private;
11989 struct mlx5_dev_ctx_shared *sh = priv->sh;
11990 struct mlx5_flow_dv_match_params mask = {
11991 .size = sizeof(mask.buf),
11993 struct mlx5_flow_dv_match_params value = {
11994 .size = sizeof(value.buf),
11996 struct mlx5dv_flow_matcher_attr dv_attr = {
11997 .type = IBV_FLOW_ATTR_NORMAL,
11999 .match_criteria_enable = 0,
12000 .match_mask = (void *)&mask,
12002 void *actions[2] = { 0 };
12003 struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
12004 struct mlx5_devx_obj *dcs = NULL;
12005 void *matcher = NULL;
12009 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, NULL);
12012 dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false, NULL, 0, NULL);
12015 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12018 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12022 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12023 (dest_tbl->obj, &actions[1]);
12026 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12027 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12031 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12035 * If batch counter with offset is not supported, the driver will not
12036 * validate the invalid offset value, flow create should success.
12037 * In this case, it means batch counter is not supported in root table.
12039 * Otherwise, if flow create is failed, counter offset is supported.
12042 DRV_LOG(INFO, "Batch counter is not supported in root "
12043 "table. Switch to fallback mode.");
12044 rte_errno = ENOTSUP;
12046 claim_zero(mlx5_flow_os_destroy_flow(flow));
12048 /* Check matcher to make sure validate fail at flow create. */
12049 if (!matcher || (matcher && errno != EINVAL))
12050 DRV_LOG(ERR, "Unexpected error in counter offset "
12051 "support detection");
12054 for (i = 0; i < 2; i++) {
12056 claim_zero(mlx5_flow_os_destroy_flow_action
12060 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12062 flow_dv_tbl_resource_release(dev, tbl);
12064 flow_dv_tbl_resource_release(dev, dest_tbl);
12066 claim_zero(mlx5_devx_cmd_destroy(dcs));
12071 * Query a devx counter.
12074 * Pointer to the Ethernet device structure.
12076 * Index to the flow counter.
12078 * Set to clear the counter statistics.
12080 * The statistics value of packets.
12081 * @param[out] bytes
12082 * The statistics value of bytes.
12085 * 0 on success, otherwise return -1.
12088 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12089 uint64_t *pkts, uint64_t *bytes)
12091 struct mlx5_priv *priv = dev->data->dev_private;
12092 struct mlx5_flow_counter *cnt;
12093 uint64_t inn_pkts, inn_bytes;
12096 if (!priv->config.devx)
12099 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12102 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12103 *pkts = inn_pkts - cnt->hits;
12104 *bytes = inn_bytes - cnt->bytes;
12106 cnt->hits = inn_pkts;
12107 cnt->bytes = inn_bytes;
12113 * Get aged-out flows.
12116 * Pointer to the Ethernet device structure.
12117 * @param[in] context
12118 * The address of an array of pointers to the aged-out flows contexts.
12119 * @param[in] nb_contexts
12120 * The length of context array pointers.
12121 * @param[out] error
12122 * Perform verbose error reporting if not NULL. Initialized in case of
12126 * how many contexts get in success, otherwise negative errno value.
12127 * if nb_contexts is 0, return the amount of all aged contexts.
12128 * if nb_contexts is not 0 , return the amount of aged flows reported
12129 * in the context array.
12130 * @note: only stub for now
12133 flow_get_aged_flows(struct rte_eth_dev *dev,
12135 uint32_t nb_contexts,
12136 struct rte_flow_error *error)
12138 struct mlx5_priv *priv = dev->data->dev_private;
12139 struct mlx5_age_info *age_info;
12140 struct mlx5_age_param *age_param;
12141 struct mlx5_flow_counter *counter;
12144 if (nb_contexts && !context)
12145 return rte_flow_error_set(error, EINVAL,
12146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12148 "Should assign at least one flow or"
12149 " context to get if nb_contexts != 0");
12150 age_info = GET_PORT_AGE_INFO(priv);
12151 rte_spinlock_lock(&age_info->aged_sl);
12152 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12155 age_param = MLX5_CNT_TO_AGE(counter);
12156 context[nb_flows - 1] = age_param->context;
12157 if (!(--nb_contexts))
12161 rte_spinlock_unlock(&age_info->aged_sl);
12162 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12167 * Mutex-protected thunk to lock-free __flow_dv_translate().
12170 flow_dv_translate(struct rte_eth_dev *dev,
12171 struct mlx5_flow *dev_flow,
12172 const struct rte_flow_attr *attr,
12173 const struct rte_flow_item items[],
12174 const struct rte_flow_action actions[],
12175 struct rte_flow_error *error)
12179 flow_dv_shared_lock(dev);
12180 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12181 flow_dv_shared_unlock(dev);
12186 * Mutex-protected thunk to lock-free __flow_dv_apply().
12189 flow_dv_apply(struct rte_eth_dev *dev,
12190 struct rte_flow *flow,
12191 struct rte_flow_error *error)
12195 flow_dv_shared_lock(dev);
12196 ret = __flow_dv_apply(dev, flow, error);
12197 flow_dv_shared_unlock(dev);
12202 * Mutex-protected thunk to lock-free __flow_dv_remove().
12205 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12207 flow_dv_shared_lock(dev);
12208 __flow_dv_remove(dev, flow);
12209 flow_dv_shared_unlock(dev);
12213 * Mutex-protected thunk to lock-free __flow_dv_destroy().
12216 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12218 flow_dv_shared_lock(dev);
12219 __flow_dv_destroy(dev, flow);
12220 flow_dv_shared_unlock(dev);
12224 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12227 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12231 flow_dv_shared_lock(dev);
12232 cnt = flow_dv_counter_alloc(dev, 0);
12233 flow_dv_shared_unlock(dev);
12238 * Mutex-protected thunk to lock-free flow_dv_counter_release().
12241 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12243 flow_dv_shared_lock(dev);
12244 flow_dv_counter_release(dev, cnt);
12245 flow_dv_shared_unlock(dev);
12249 * Validate shared action.
12250 * Dispatcher for action type specific validation.
12253 * Pointer to the Ethernet device structure.
12255 * Shared action configuration.
12256 * @param[in] action
12257 * The shared action object to validate.
12258 * @param[out] error
12259 * Perform verbose error reporting if not NULL. Initialized in case of
12263 * 0 on success, otherwise negative errno value.
12266 flow_dv_action_validate(struct rte_eth_dev *dev,
12267 const struct rte_flow_shared_action_conf *conf,
12268 const struct rte_flow_action *action,
12269 struct rte_flow_error *error)
12271 RTE_SET_USED(conf);
12272 switch (action->type) {
12273 case RTE_FLOW_ACTION_TYPE_RSS:
12274 return mlx5_validate_action_rss(dev, action, error);
12276 return rte_flow_error_set(error, ENOTSUP,
12277 RTE_FLOW_ERROR_TYPE_ACTION,
12279 "action type not supported");
12284 * Mutex-protected thunk to lock-free __flow_dv_action_create().
12286 static struct rte_flow_shared_action *
12287 flow_dv_action_create(struct rte_eth_dev *dev,
12288 const struct rte_flow_shared_action_conf *conf,
12289 const struct rte_flow_action *action,
12290 struct rte_flow_error *error)
12292 struct rte_flow_shared_action *shared_action = NULL;
12294 flow_dv_shared_lock(dev);
12295 shared_action = __flow_dv_action_create(dev, conf, action, error);
12296 flow_dv_shared_unlock(dev);
12297 return shared_action;
12301 * Mutex-protected thunk to lock-free __flow_dv_action_destroy().
12304 flow_dv_action_destroy(struct rte_eth_dev *dev,
12305 struct rte_flow_shared_action *action,
12306 struct rte_flow_error *error)
12310 flow_dv_shared_lock(dev);
12311 ret = __flow_dv_action_destroy(dev, action, error);
12312 flow_dv_shared_unlock(dev);
12317 * Mutex-protected thunk to lock-free __flow_dv_action_update().
12320 flow_dv_action_update(struct rte_eth_dev *dev,
12321 struct rte_flow_shared_action *action,
12322 const void *action_conf,
12323 struct rte_flow_error *error)
12327 flow_dv_shared_lock(dev);
12328 ret = __flow_dv_action_update(dev, action, action_conf,
12330 flow_dv_shared_unlock(dev);
12335 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12337 struct mlx5_priv *priv = dev->data->dev_private;
12340 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12341 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12346 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12347 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12351 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12352 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12359 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12360 .validate = flow_dv_validate,
12361 .prepare = flow_dv_prepare,
12362 .translate = flow_dv_translate,
12363 .apply = flow_dv_apply,
12364 .remove = flow_dv_remove,
12365 .destroy = flow_dv_destroy,
12366 .query = flow_dv_query,
12367 .create_mtr_tbls = flow_dv_create_mtr_tbl,
12368 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12369 .create_policer_rules = flow_dv_create_policer_rules,
12370 .destroy_policer_rules = flow_dv_destroy_policer_rules,
12371 .counter_alloc = flow_dv_counter_allocate,
12372 .counter_free = flow_dv_counter_free,
12373 .counter_query = flow_dv_counter_query,
12374 .get_aged_flows = flow_get_aged_flows,
12375 .action_validate = flow_dv_action_validate,
12376 .action_create = flow_dv_action_create,
12377 .action_destroy = flow_dv_action_destroy,
12378 .action_update = flow_dv_action_update,
12379 .sync_domain = flow_dv_sync_domain,
12382 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */