1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_cycles.h>
30 #include <rte_vxlan.h>
33 #include <mlx5_glue.h>
34 #include <mlx5_devx_cmds.h>
37 #include "mlx5_defs.h"
39 #include "mlx5_flow.h"
40 #include "mlx5_rxtx.h"
42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
48 #ifndef HAVE_MLX5DV_DR_ESWITCH
49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
54 #ifndef HAVE_MLX5DV_DR
55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
58 /* VLAN header definitions */
59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
79 struct mlx5_flow_tbl_resource *tbl);
82 * Initialize flow attributes structure according to flow items' types.
84 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
85 * mode. For tunnel mode, the items to be modified are the outermost ones.
88 * Pointer to item specification.
90 * Pointer to flow attributes structure.
92 * Pointer to the sub flow.
93 * @param[in] tunnel_decap
94 * Whether action is after tunnel decapsulation.
97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
98 struct mlx5_flow *dev_flow, bool tunnel_decap)
100 uint64_t layers = dev_flow->handle->layers;
103 * If layers is already initialized, it means this dev_flow is the
104 * suffix flow, the layers flags is set by the prefix flow. Need to
105 * use the layer flags from prefix flow as the suffix flow may not
106 * have the user defined items as the flow is split.
109 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
111 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
113 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
115 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
120 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
121 uint8_t next_protocol = 0xff;
122 switch (item->type) {
123 case RTE_FLOW_ITEM_TYPE_GRE:
124 case RTE_FLOW_ITEM_TYPE_NVGRE:
125 case RTE_FLOW_ITEM_TYPE_VXLAN:
126 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
127 case RTE_FLOW_ITEM_TYPE_GENEVE:
128 case RTE_FLOW_ITEM_TYPE_MPLS:
132 case RTE_FLOW_ITEM_TYPE_IPV4:
135 if (item->mask != NULL &&
136 ((const struct rte_flow_item_ipv4 *)
137 item->mask)->hdr.next_proto_id)
139 ((const struct rte_flow_item_ipv4 *)
140 (item->spec))->hdr.next_proto_id &
141 ((const struct rte_flow_item_ipv4 *)
142 (item->mask))->hdr.next_proto_id;
143 if ((next_protocol == IPPROTO_IPIP ||
144 next_protocol == IPPROTO_IPV6) && tunnel_decap)
147 case RTE_FLOW_ITEM_TYPE_IPV6:
150 if (item->mask != NULL &&
151 ((const struct rte_flow_item_ipv6 *)
152 item->mask)->hdr.proto)
154 ((const struct rte_flow_item_ipv6 *)
155 (item->spec))->hdr.proto &
156 ((const struct rte_flow_item_ipv6 *)
157 (item->mask))->hdr.proto;
158 if ((next_protocol == IPPROTO_IPIP ||
159 next_protocol == IPPROTO_IPV6) && tunnel_decap)
162 case RTE_FLOW_ITEM_TYPE_UDP:
166 case RTE_FLOW_ITEM_TYPE_TCP:
178 * Convert rte_mtr_color to mlx5 color.
187 rte_col_2_mlx5_col(enum rte_color rcol)
190 case RTE_COLOR_GREEN:
191 return MLX5_FLOW_COLOR_GREEN;
192 case RTE_COLOR_YELLOW:
193 return MLX5_FLOW_COLOR_YELLOW;
195 return MLX5_FLOW_COLOR_RED;
199 return MLX5_FLOW_COLOR_UNDEFINED;
202 struct field_modify_info {
203 uint32_t size; /* Size of field in protocol header, in bytes. */
204 uint32_t offset; /* Offset of field in protocol header, in bytes. */
205 enum mlx5_modification_field id;
208 struct field_modify_info modify_eth[] = {
209 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
210 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
211 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
212 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
216 struct field_modify_info modify_vlan_out_first_vid[] = {
217 /* Size in bits !!! */
218 {12, 0, MLX5_MODI_OUT_FIRST_VID},
222 struct field_modify_info modify_ipv4[] = {
223 {1, 1, MLX5_MODI_OUT_IP_DSCP},
224 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
225 {4, 12, MLX5_MODI_OUT_SIPV4},
226 {4, 16, MLX5_MODI_OUT_DIPV4},
230 struct field_modify_info modify_ipv6[] = {
231 {1, 0, MLX5_MODI_OUT_IP_DSCP},
232 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
233 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
234 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
235 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
236 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
237 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
238 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
239 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
240 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
244 struct field_modify_info modify_udp[] = {
245 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
246 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
250 struct field_modify_info modify_tcp[] = {
251 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
252 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
253 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
254 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
260 uint8_t next_protocol, uint64_t *item_flags,
263 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
264 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
265 if (next_protocol == IPPROTO_IPIP) {
266 *item_flags |= MLX5_FLOW_LAYER_IPIP;
269 if (next_protocol == IPPROTO_IPV6) {
270 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
276 * Acquire the synchronizing object to protect multithreaded access
277 * to shared dv context. Lock occurs only if context is actually
278 * shared, i.e. we have multiport IB device and representors are
282 * Pointer to the rte_eth_dev structure.
285 flow_dv_shared_lock(struct rte_eth_dev *dev)
287 struct mlx5_priv *priv = dev->data->dev_private;
288 struct mlx5_ibv_shared *sh = priv->sh;
290 if (sh->dv_refcnt > 1) {
293 ret = pthread_mutex_lock(&sh->dv_mutex);
300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
302 struct mlx5_priv *priv = dev->data->dev_private;
303 struct mlx5_ibv_shared *sh = priv->sh;
305 if (sh->dv_refcnt > 1) {
308 ret = pthread_mutex_unlock(&sh->dv_mutex);
314 /* Update VLAN's VID/PCP based on input rte_flow_action.
317 * Pointer to struct rte_flow_action.
319 * Pointer to struct rte_vlan_hdr.
322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
323 struct rte_vlan_hdr *vlan)
326 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
328 ((const struct rte_flow_action_of_set_vlan_pcp *)
329 action->conf)->vlan_pcp;
330 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
331 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
332 vlan->vlan_tci |= vlan_tci;
333 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
334 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
335 vlan->vlan_tci |= rte_be_to_cpu_16
336 (((const struct rte_flow_action_of_set_vlan_vid *)
337 action->conf)->vlan_vid);
342 * Fetch 1, 2, 3 or 4 byte field from the byte array
343 * and return as unsigned integer in host-endian format.
346 * Pointer to data array.
348 * Size of field to extract.
351 * converted field in host endian format.
353 static inline uint32_t
354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
363 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
367 ret = (ret << 8) | *(data + sizeof(uint16_t));
370 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
381 * Convert modify-header action to DV specification.
383 * Data length of each action is determined by provided field description
384 * and the item mask. Data bit offset and width of each action is determined
385 * by provided item mask.
388 * Pointer to item specification.
390 * Pointer to field modification information.
391 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
393 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
395 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
396 * Negative offset value sets the same offset as source offset.
397 * size field is ignored, value is taken from source field.
398 * @param[in,out] resource
399 * Pointer to the modify-header resource.
401 * Type of modification.
403 * Pointer to the error structure.
406 * 0 on success, a negative errno value otherwise and rte_errno is set.
409 flow_dv_convert_modify_action(struct rte_flow_item *item,
410 struct field_modify_info *field,
411 struct field_modify_info *dcopy,
412 struct mlx5_flow_dv_modify_hdr_resource *resource,
413 uint32_t type, struct rte_flow_error *error)
415 uint32_t i = resource->actions_num;
416 struct mlx5_modification_cmd *actions = resource->actions;
419 * The item and mask are provided in big-endian format.
420 * The fields should be presented as in big-endian format either.
421 * Mask must be always present, it defines the actual field width.
423 MLX5_ASSERT(item->mask);
424 MLX5_ASSERT(field->size);
431 if (i >= MLX5_MAX_MODIFY_NUM)
432 return rte_flow_error_set(error, EINVAL,
433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434 "too many items to modify");
435 /* Fetch variable byte size mask from the array. */
436 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
437 field->offset, field->size);
442 /* Deduce actual data width in bits from mask value. */
443 off_b = rte_bsf32(mask);
444 size_b = sizeof(uint32_t) * CHAR_BIT -
445 off_b - __builtin_clz(mask);
447 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
448 actions[i] = (struct mlx5_modification_cmd) {
454 /* Convert entire record to expected big-endian format. */
455 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
456 if (type == MLX5_MODIFICATION_TYPE_COPY) {
458 actions[i].dst_field = dcopy->id;
459 actions[i].dst_offset =
460 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
461 /* Convert entire record to big-endian format. */
462 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
464 MLX5_ASSERT(item->spec);
465 data = flow_dv_fetch_field((const uint8_t *)item->spec +
466 field->offset, field->size);
467 /* Shift out the trailing masked bits from data. */
468 data = (data & mask) >> off_b;
469 actions[i].data1 = rte_cpu_to_be_32(data);
473 } while (field->size);
474 if (resource->actions_num == i)
475 return rte_flow_error_set(error, EINVAL,
476 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
477 "invalid modification flow item");
478 resource->actions_num = i;
483 * Convert modify-header set IPv4 address action to DV specification.
485 * @param[in,out] resource
486 * Pointer to the modify-header resource.
488 * Pointer to action specification.
490 * Pointer to the error structure.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 flow_dv_convert_action_modify_ipv4
497 (struct mlx5_flow_dv_modify_hdr_resource *resource,
498 const struct rte_flow_action *action,
499 struct rte_flow_error *error)
501 const struct rte_flow_action_set_ipv4 *conf =
502 (const struct rte_flow_action_set_ipv4 *)(action->conf);
503 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
504 struct rte_flow_item_ipv4 ipv4;
505 struct rte_flow_item_ipv4 ipv4_mask;
507 memset(&ipv4, 0, sizeof(ipv4));
508 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
509 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
510 ipv4.hdr.src_addr = conf->ipv4_addr;
511 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
513 ipv4.hdr.dst_addr = conf->ipv4_addr;
514 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
517 item.mask = &ipv4_mask;
518 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
519 MLX5_MODIFICATION_TYPE_SET, error);
523 * Convert modify-header set IPv6 address action to DV specification.
525 * @param[in,out] resource
526 * Pointer to the modify-header resource.
528 * Pointer to action specification.
530 * Pointer to the error structure.
533 * 0 on success, a negative errno value otherwise and rte_errno is set.
536 flow_dv_convert_action_modify_ipv6
537 (struct mlx5_flow_dv_modify_hdr_resource *resource,
538 const struct rte_flow_action *action,
539 struct rte_flow_error *error)
541 const struct rte_flow_action_set_ipv6 *conf =
542 (const struct rte_flow_action_set_ipv6 *)(action->conf);
543 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
544 struct rte_flow_item_ipv6 ipv6;
545 struct rte_flow_item_ipv6 ipv6_mask;
547 memset(&ipv6, 0, sizeof(ipv6));
548 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
549 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
550 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
551 sizeof(ipv6.hdr.src_addr));
552 memcpy(&ipv6_mask.hdr.src_addr,
553 &rte_flow_item_ipv6_mask.hdr.src_addr,
554 sizeof(ipv6.hdr.src_addr));
556 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
557 sizeof(ipv6.hdr.dst_addr));
558 memcpy(&ipv6_mask.hdr.dst_addr,
559 &rte_flow_item_ipv6_mask.hdr.dst_addr,
560 sizeof(ipv6.hdr.dst_addr));
563 item.mask = &ipv6_mask;
564 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
565 MLX5_MODIFICATION_TYPE_SET, error);
569 * Convert modify-header set MAC address action to DV specification.
571 * @param[in,out] resource
572 * Pointer to the modify-header resource.
574 * Pointer to action specification.
576 * Pointer to the error structure.
579 * 0 on success, a negative errno value otherwise and rte_errno is set.
582 flow_dv_convert_action_modify_mac
583 (struct mlx5_flow_dv_modify_hdr_resource *resource,
584 const struct rte_flow_action *action,
585 struct rte_flow_error *error)
587 const struct rte_flow_action_set_mac *conf =
588 (const struct rte_flow_action_set_mac *)(action->conf);
589 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
590 struct rte_flow_item_eth eth;
591 struct rte_flow_item_eth eth_mask;
593 memset(ð, 0, sizeof(eth));
594 memset(ð_mask, 0, sizeof(eth_mask));
595 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
596 memcpy(ð.src.addr_bytes, &conf->mac_addr,
597 sizeof(eth.src.addr_bytes));
598 memcpy(ð_mask.src.addr_bytes,
599 &rte_flow_item_eth_mask.src.addr_bytes,
600 sizeof(eth_mask.src.addr_bytes));
602 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
603 sizeof(eth.dst.addr_bytes));
604 memcpy(ð_mask.dst.addr_bytes,
605 &rte_flow_item_eth_mask.dst.addr_bytes,
606 sizeof(eth_mask.dst.addr_bytes));
609 item.mask = ð_mask;
610 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
611 MLX5_MODIFICATION_TYPE_SET, error);
615 * Convert modify-header set VLAN VID action to DV specification.
617 * @param[in,out] resource
618 * Pointer to the modify-header resource.
620 * Pointer to action specification.
622 * Pointer to the error structure.
625 * 0 on success, a negative errno value otherwise and rte_errno is set.
628 flow_dv_convert_action_modify_vlan_vid
629 (struct mlx5_flow_dv_modify_hdr_resource *resource,
630 const struct rte_flow_action *action,
631 struct rte_flow_error *error)
633 const struct rte_flow_action_of_set_vlan_vid *conf =
634 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
635 int i = resource->actions_num;
636 struct mlx5_modification_cmd *actions = resource->actions;
637 struct field_modify_info *field = modify_vlan_out_first_vid;
639 if (i >= MLX5_MAX_MODIFY_NUM)
640 return rte_flow_error_set(error, EINVAL,
641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
642 "too many items to modify");
643 actions[i] = (struct mlx5_modification_cmd) {
644 .action_type = MLX5_MODIFICATION_TYPE_SET,
646 .length = field->size,
647 .offset = field->offset,
649 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
650 actions[i].data1 = conf->vlan_vid;
651 actions[i].data1 = actions[i].data1 << 16;
652 resource->actions_num = ++i;
657 * Convert modify-header set TP action to DV specification.
659 * @param[in,out] resource
660 * Pointer to the modify-header resource.
662 * Pointer to action specification.
664 * Pointer to rte_flow_item objects list.
666 * Pointer to flow attributes structure.
667 * @param[in] dev_flow
668 * Pointer to the sub flow.
669 * @param[in] tunnel_decap
670 * Whether action is after tunnel decapsulation.
672 * Pointer to the error structure.
675 * 0 on success, a negative errno value otherwise and rte_errno is set.
678 flow_dv_convert_action_modify_tp
679 (struct mlx5_flow_dv_modify_hdr_resource *resource,
680 const struct rte_flow_action *action,
681 const struct rte_flow_item *items,
682 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
683 bool tunnel_decap, struct rte_flow_error *error)
685 const struct rte_flow_action_set_tp *conf =
686 (const struct rte_flow_action_set_tp *)(action->conf);
687 struct rte_flow_item item;
688 struct rte_flow_item_udp udp;
689 struct rte_flow_item_udp udp_mask;
690 struct rte_flow_item_tcp tcp;
691 struct rte_flow_item_tcp tcp_mask;
692 struct field_modify_info *field;
695 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
697 memset(&udp, 0, sizeof(udp));
698 memset(&udp_mask, 0, sizeof(udp_mask));
699 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
700 udp.hdr.src_port = conf->port;
701 udp_mask.hdr.src_port =
702 rte_flow_item_udp_mask.hdr.src_port;
704 udp.hdr.dst_port = conf->port;
705 udp_mask.hdr.dst_port =
706 rte_flow_item_udp_mask.hdr.dst_port;
708 item.type = RTE_FLOW_ITEM_TYPE_UDP;
710 item.mask = &udp_mask;
713 MLX5_ASSERT(attr->tcp);
714 memset(&tcp, 0, sizeof(tcp));
715 memset(&tcp_mask, 0, sizeof(tcp_mask));
716 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
717 tcp.hdr.src_port = conf->port;
718 tcp_mask.hdr.src_port =
719 rte_flow_item_tcp_mask.hdr.src_port;
721 tcp.hdr.dst_port = conf->port;
722 tcp_mask.hdr.dst_port =
723 rte_flow_item_tcp_mask.hdr.dst_port;
725 item.type = RTE_FLOW_ITEM_TYPE_TCP;
727 item.mask = &tcp_mask;
730 return flow_dv_convert_modify_action(&item, field, NULL, resource,
731 MLX5_MODIFICATION_TYPE_SET, error);
735 * Convert modify-header set TTL action to DV specification.
737 * @param[in,out] resource
738 * Pointer to the modify-header resource.
740 * Pointer to action specification.
742 * Pointer to rte_flow_item objects list.
744 * Pointer to flow attributes structure.
745 * @param[in] dev_flow
746 * Pointer to the sub flow.
747 * @param[in] tunnel_decap
748 * Whether action is after tunnel decapsulation.
750 * Pointer to the error structure.
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
756 flow_dv_convert_action_modify_ttl
757 (struct mlx5_flow_dv_modify_hdr_resource *resource,
758 const struct rte_flow_action *action,
759 const struct rte_flow_item *items,
760 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
761 bool tunnel_decap, struct rte_flow_error *error)
763 const struct rte_flow_action_set_ttl *conf =
764 (const struct rte_flow_action_set_ttl *)(action->conf);
765 struct rte_flow_item item;
766 struct rte_flow_item_ipv4 ipv4;
767 struct rte_flow_item_ipv4 ipv4_mask;
768 struct rte_flow_item_ipv6 ipv6;
769 struct rte_flow_item_ipv6 ipv6_mask;
770 struct field_modify_info *field;
773 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
775 memset(&ipv4, 0, sizeof(ipv4));
776 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
777 ipv4.hdr.time_to_live = conf->ttl_value;
778 ipv4_mask.hdr.time_to_live = 0xFF;
779 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
781 item.mask = &ipv4_mask;
784 MLX5_ASSERT(attr->ipv6);
785 memset(&ipv6, 0, sizeof(ipv6));
786 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
787 ipv6.hdr.hop_limits = conf->ttl_value;
788 ipv6_mask.hdr.hop_limits = 0xFF;
789 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
791 item.mask = &ipv6_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header decrement TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_dec_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_item *items,
823 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
824 bool tunnel_decap, struct rte_flow_error *error)
826 struct rte_flow_item item;
827 struct rte_flow_item_ipv4 ipv4;
828 struct rte_flow_item_ipv4 ipv4_mask;
829 struct rte_flow_item_ipv6 ipv6;
830 struct rte_flow_item_ipv6 ipv6_mask;
831 struct field_modify_info *field;
834 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
836 memset(&ipv4, 0, sizeof(ipv4));
837 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
838 ipv4.hdr.time_to_live = 0xFF;
839 ipv4_mask.hdr.time_to_live = 0xFF;
840 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
842 item.mask = &ipv4_mask;
845 MLX5_ASSERT(attr->ipv6);
846 memset(&ipv6, 0, sizeof(ipv6));
847 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
848 ipv6.hdr.hop_limits = 0xFF;
849 ipv6_mask.hdr.hop_limits = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
852 item.mask = &ipv6_mask;
855 return flow_dv_convert_modify_action(&item, field, NULL, resource,
856 MLX5_MODIFICATION_TYPE_ADD, error);
860 * Convert modify-header increment/decrement TCP Sequence number
861 * to DV specification.
863 * @param[in,out] resource
864 * Pointer to the modify-header resource.
866 * Pointer to action specification.
868 * Pointer to the error structure.
871 * 0 on success, a negative errno value otherwise and rte_errno is set.
874 flow_dv_convert_action_modify_tcp_seq
875 (struct mlx5_flow_dv_modify_hdr_resource *resource,
876 const struct rte_flow_action *action,
877 struct rte_flow_error *error)
879 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
880 uint64_t value = rte_be_to_cpu_32(*conf);
881 struct rte_flow_item item;
882 struct rte_flow_item_tcp tcp;
883 struct rte_flow_item_tcp tcp_mask;
885 memset(&tcp, 0, sizeof(tcp));
886 memset(&tcp_mask, 0, sizeof(tcp_mask));
887 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
889 * The HW has no decrement operation, only increment operation.
890 * To simulate decrement X from Y using increment operation
891 * we need to add UINT32_MAX X times to Y.
892 * Each adding of UINT32_MAX decrements Y by 1.
895 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
896 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
897 item.type = RTE_FLOW_ITEM_TYPE_TCP;
899 item.mask = &tcp_mask;
900 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
901 MLX5_MODIFICATION_TYPE_ADD, error);
905 * Convert modify-header increment/decrement TCP Acknowledgment number
906 * to DV specification.
908 * @param[in,out] resource
909 * Pointer to the modify-header resource.
911 * Pointer to action specification.
913 * Pointer to the error structure.
916 * 0 on success, a negative errno value otherwise and rte_errno is set.
919 flow_dv_convert_action_modify_tcp_ack
920 (struct mlx5_flow_dv_modify_hdr_resource *resource,
921 const struct rte_flow_action *action,
922 struct rte_flow_error *error)
924 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
925 uint64_t value = rte_be_to_cpu_32(*conf);
926 struct rte_flow_item item;
927 struct rte_flow_item_tcp tcp;
928 struct rte_flow_item_tcp tcp_mask;
930 memset(&tcp, 0, sizeof(tcp));
931 memset(&tcp_mask, 0, sizeof(tcp_mask));
932 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
934 * The HW has no decrement operation, only increment operation.
935 * To simulate decrement X from Y using increment operation
936 * we need to add UINT32_MAX X times to Y.
937 * Each adding of UINT32_MAX decrements Y by 1.
940 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
941 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
942 item.type = RTE_FLOW_ITEM_TYPE_TCP;
944 item.mask = &tcp_mask;
945 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
946 MLX5_MODIFICATION_TYPE_ADD, error);
949 static enum mlx5_modification_field reg_to_field[] = {
950 [REG_NONE] = MLX5_MODI_OUT_NONE,
951 [REG_A] = MLX5_MODI_META_DATA_REG_A,
952 [REG_B] = MLX5_MODI_META_DATA_REG_B,
953 [REG_C_0] = MLX5_MODI_META_REG_C_0,
954 [REG_C_1] = MLX5_MODI_META_REG_C_1,
955 [REG_C_2] = MLX5_MODI_META_REG_C_2,
956 [REG_C_3] = MLX5_MODI_META_REG_C_3,
957 [REG_C_4] = MLX5_MODI_META_REG_C_4,
958 [REG_C_5] = MLX5_MODI_META_REG_C_5,
959 [REG_C_6] = MLX5_MODI_META_REG_C_6,
960 [REG_C_7] = MLX5_MODI_META_REG_C_7,
964 * Convert register set to DV specification.
966 * @param[in,out] resource
967 * Pointer to the modify-header resource.
969 * Pointer to action specification.
971 * Pointer to the error structure.
974 * 0 on success, a negative errno value otherwise and rte_errno is set.
977 flow_dv_convert_action_set_reg
978 (struct mlx5_flow_dv_modify_hdr_resource *resource,
979 const struct rte_flow_action *action,
980 struct rte_flow_error *error)
982 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
983 struct mlx5_modification_cmd *actions = resource->actions;
984 uint32_t i = resource->actions_num;
986 if (i >= MLX5_MAX_MODIFY_NUM)
987 return rte_flow_error_set(error, EINVAL,
988 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
989 "too many items to modify");
990 MLX5_ASSERT(conf->id != REG_NONE);
991 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
992 actions[i] = (struct mlx5_modification_cmd) {
993 .action_type = MLX5_MODIFICATION_TYPE_SET,
994 .field = reg_to_field[conf->id],
996 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
997 actions[i].data1 = rte_cpu_to_be_32(conf->data);
999 resource->actions_num = i;
1004 * Convert SET_TAG action to DV specification.
1007 * Pointer to the rte_eth_dev structure.
1008 * @param[in,out] resource
1009 * Pointer to the modify-header resource.
1011 * Pointer to action specification.
1013 * Pointer to the error structure.
1016 * 0 on success, a negative errno value otherwise and rte_errno is set.
1019 flow_dv_convert_action_set_tag
1020 (struct rte_eth_dev *dev,
1021 struct mlx5_flow_dv_modify_hdr_resource *resource,
1022 const struct rte_flow_action_set_tag *conf,
1023 struct rte_flow_error *error)
1025 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027 struct rte_flow_item item = {
1031 struct field_modify_info reg_c_x[] = {
1034 enum mlx5_modification_field reg_type;
1037 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040 MLX5_ASSERT(ret != REG_NONE);
1041 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042 reg_type = reg_to_field[ret];
1043 MLX5_ASSERT(reg_type > 0);
1044 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046 MLX5_MODIFICATION_TYPE_SET, error);
1050 * Convert internal COPY_REG action to DV specification.
1053 * Pointer to the rte_eth_dev structure.
1054 * @param[in,out] res
1055 * Pointer to the modify-header resource.
1057 * Pointer to action specification.
1059 * Pointer to the error structure.
1062 * 0 on success, a negative errno value otherwise and rte_errno is set.
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066 struct mlx5_flow_dv_modify_hdr_resource *res,
1067 const struct rte_flow_action *action,
1068 struct rte_flow_error *error)
1070 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_src[] = {
1077 {4, 0, reg_to_field[conf->src]},
1080 struct field_modify_info reg_dst = {
1082 .id = reg_to_field[conf->dst],
1084 /* Adjust reg_c[0] usage according to reported mask. */
1085 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086 struct mlx5_priv *priv = dev->data->dev_private;
1087 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1089 MLX5_ASSERT(reg_c0);
1090 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091 if (conf->dst == REG_C_0) {
1092 /* Copy to reg_c[0], within mask only. */
1093 reg_dst.offset = rte_bsf32(reg_c0);
1095 * Mask is ignoring the enianness, because
1096 * there is no conversion in datapath.
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099 /* Copy from destination lower bits to reg_c[0]. */
1100 mask = reg_c0 >> reg_dst.offset;
1102 /* Copy from destination upper bits to reg_c[0]. */
1103 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104 rte_fls_u32(reg_c0));
1107 mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109 /* Copy from reg_c[0] to destination lower bits. */
1112 /* Copy from reg_c[0] to destination upper bits. */
1113 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114 (rte_fls_u32(reg_c0) -
1119 return flow_dv_convert_modify_action(&item,
1120 reg_src, ®_dst, res,
1121 MLX5_MODIFICATION_TYPE_COPY,
1126 * Convert MARK action to DV specification. This routine is used
1127 * in extensive metadata only and requires metadata register to be
1128 * handled. In legacy mode hardware tag resource is engaged.
1131 * Pointer to the rte_eth_dev structure.
1133 * Pointer to MARK action specification.
1134 * @param[in,out] resource
1135 * Pointer to the modify-header resource.
1137 * Pointer to the error structure.
1140 * 0 on success, a negative errno value otherwise and rte_errno is set.
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144 const struct rte_flow_action_mark *conf,
1145 struct mlx5_flow_dv_modify_hdr_resource *resource,
1146 struct rte_flow_error *error)
1148 struct mlx5_priv *priv = dev->data->dev_private;
1149 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150 priv->sh->dv_mark_mask);
1151 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152 struct rte_flow_item item = {
1156 struct field_modify_info reg_c_x[] = {
1157 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1163 return rte_flow_error_set(error, EINVAL,
1164 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165 NULL, "zero mark action mask");
1166 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1169 MLX5_ASSERT(reg > 0);
1170 if (reg == REG_C_0) {
1171 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172 uint32_t shl_c0 = rte_bsf32(msk_c0);
1174 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176 mask = rte_cpu_to_be_32(mask << shl_c0);
1178 reg_c_x[0].id = reg_to_field[reg];
1179 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180 MLX5_MODIFICATION_TYPE_SET, error);
1184 * Get metadata register index for specified steering domain.
1187 * Pointer to the rte_eth_dev structure.
1189 * Attributes of flow to determine steering domain.
1191 * Pointer to the error structure.
1194 * positive index on success, a negative errno value otherwise
1195 * and rte_errno is set.
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199 const struct rte_flow_attr *attr,
1200 struct rte_flow_error *error)
1203 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207 MLX5_METADATA_RX, 0, error);
1209 return rte_flow_error_set(error,
1210 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211 NULL, "unavailable "
1212 "metadata register");
1217 * Convert SET_META action to DV specification.
1220 * Pointer to the rte_eth_dev structure.
1221 * @param[in,out] resource
1222 * Pointer to the modify-header resource.
1224 * Attributes of flow that includes this item.
1226 * Pointer to action specification.
1228 * Pointer to the error structure.
1231 * 0 on success, a negative errno value otherwise and rte_errno is set.
1234 flow_dv_convert_action_set_meta
1235 (struct rte_eth_dev *dev,
1236 struct mlx5_flow_dv_modify_hdr_resource *resource,
1237 const struct rte_flow_attr *attr,
1238 const struct rte_flow_action_set_meta *conf,
1239 struct rte_flow_error *error)
1241 uint32_t data = conf->data;
1242 uint32_t mask = conf->mask;
1243 struct rte_flow_item item = {
1247 struct field_modify_info reg_c_x[] = {
1250 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1255 * In datapath code there is no endianness
1256 * coversions for perfromance reasons, all
1257 * pattern conversions are done in rte_flow.
1259 if (reg == REG_C_0) {
1260 struct mlx5_priv *priv = dev->data->dev_private;
1261 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1264 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266 shl_c0 = rte_bsf32(msk_c0);
1268 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1274 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275 /* The routine expects parameters in memory as big-endian ones. */
1276 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277 MLX5_MODIFICATION_TYPE_SET, error);
1281 * Convert modify-header set IPv4 DSCP action to DV specification.
1283 * @param[in,out] resource
1284 * Pointer to the modify-header resource.
1286 * Pointer to action specification.
1288 * Pointer to the error structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 flow_dv_convert_action_modify_ipv4_dscp
1295 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296 const struct rte_flow_action *action,
1297 struct rte_flow_error *error)
1299 const struct rte_flow_action_set_dscp *conf =
1300 (const struct rte_flow_action_set_dscp *)(action->conf);
1301 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302 struct rte_flow_item_ipv4 ipv4;
1303 struct rte_flow_item_ipv4 ipv4_mask;
1305 memset(&ipv4, 0, sizeof(ipv4));
1306 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307 ipv4.hdr.type_of_service = conf->dscp;
1308 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1310 item.mask = &ipv4_mask;
1311 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312 MLX5_MODIFICATION_TYPE_SET, error);
1316 * Convert modify-header set IPv6 DSCP action to DV specification.
1318 * @param[in,out] resource
1319 * Pointer to the modify-header resource.
1321 * Pointer to action specification.
1323 * Pointer to the error structure.
1326 * 0 on success, a negative errno value otherwise and rte_errno is set.
1329 flow_dv_convert_action_modify_ipv6_dscp
1330 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331 const struct rte_flow_action *action,
1332 struct rte_flow_error *error)
1334 const struct rte_flow_action_set_dscp *conf =
1335 (const struct rte_flow_action_set_dscp *)(action->conf);
1336 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337 struct rte_flow_item_ipv6 ipv6;
1338 struct rte_flow_item_ipv6 ipv6_mask;
1340 memset(&ipv6, 0, sizeof(ipv6));
1341 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1343 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344 * rdma-core only accept the DSCP bits byte aligned start from
1345 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346 * bits in IPv6 case as rdma-core requires byte aligned value.
1348 ipv6.hdr.vtc_flow = conf->dscp;
1349 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1351 item.mask = &ipv6_mask;
1352 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353 MLX5_MODIFICATION_TYPE_SET, error);
1357 * Validate MARK item.
1360 * Pointer to the rte_eth_dev structure.
1362 * Item specification.
1364 * Attributes of flow that includes this item.
1366 * Pointer to error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373 const struct rte_flow_item *item,
1374 const struct rte_flow_attr *attr __rte_unused,
1375 struct rte_flow_error *error)
1377 struct mlx5_priv *priv = dev->data->dev_private;
1378 struct mlx5_dev_config *config = &priv->config;
1379 const struct rte_flow_item_mark *spec = item->spec;
1380 const struct rte_flow_item_mark *mask = item->mask;
1381 const struct rte_flow_item_mark nic_mask = {
1382 .id = priv->sh->dv_mark_mask,
1386 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata feature"
1391 if (!mlx5_flow_ext_mreg_supported(dev))
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't supported");
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1399 "extended metadata register"
1400 " isn't available");
1401 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1408 "data cannot be empty");
1409 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1413 "mark id exceeds the limit");
1417 return rte_flow_error_set(error, EINVAL,
1418 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419 "mask cannot be zero");
1421 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422 (const uint8_t *)&nic_mask,
1423 sizeof(struct rte_flow_item_mark),
1431 * Validate META item.
1434 * Pointer to the rte_eth_dev structure.
1436 * Item specification.
1438 * Attributes of flow that includes this item.
1440 * Pointer to error structure.
1443 * 0 on success, a negative errno value otherwise and rte_errno is set.
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447 const struct rte_flow_item *item,
1448 const struct rte_flow_attr *attr,
1449 struct rte_flow_error *error)
1451 struct mlx5_priv *priv = dev->data->dev_private;
1452 struct mlx5_dev_config *config = &priv->config;
1453 const struct rte_flow_item_meta *spec = item->spec;
1454 const struct rte_flow_item_meta *mask = item->mask;
1455 struct rte_flow_item_meta nic_mask = {
1462 return rte_flow_error_set(error, EINVAL,
1463 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1465 "data cannot be empty");
1466 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467 if (!mlx5_flow_ext_mreg_supported(dev))
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ITEM, item,
1470 "extended metadata register"
1471 " isn't supported");
1472 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476 return rte_flow_error_set(error, ENOTSUP,
1477 RTE_FLOW_ERROR_TYPE_ITEM, item,
1481 nic_mask.data = priv->sh->dv_meta_mask;
1484 mask = &rte_flow_item_meta_mask;
1486 return rte_flow_error_set(error, EINVAL,
1487 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488 "mask cannot be zero");
1490 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491 (const uint8_t *)&nic_mask,
1492 sizeof(struct rte_flow_item_meta),
1498 * Validate TAG item.
1501 * Pointer to the rte_eth_dev structure.
1503 * Item specification.
1505 * Attributes of flow that includes this item.
1507 * Pointer to error structure.
1510 * 0 on success, a negative errno value otherwise and rte_errno is set.
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514 const struct rte_flow_item *item,
1515 const struct rte_flow_attr *attr __rte_unused,
1516 struct rte_flow_error *error)
1518 const struct rte_flow_item_tag *spec = item->spec;
1519 const struct rte_flow_item_tag *mask = item->mask;
1520 const struct rte_flow_item_tag nic_mask = {
1521 .data = RTE_BE32(UINT32_MAX),
1526 if (!mlx5_flow_ext_mreg_supported(dev))
1527 return rte_flow_error_set(error, ENOTSUP,
1528 RTE_FLOW_ERROR_TYPE_ITEM, item,
1529 "extensive metadata register"
1530 " isn't supported");
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1535 "data cannot be empty");
1537 mask = &rte_flow_item_tag_mask;
1539 return rte_flow_error_set(error, EINVAL,
1540 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541 "mask cannot be zero");
1543 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544 (const uint8_t *)&nic_mask,
1545 sizeof(struct rte_flow_item_tag),
1549 if (mask->index != 0xff)
1550 return rte_flow_error_set(error, EINVAL,
1551 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552 "partial mask for tag index"
1553 " is not supported");
1554 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1557 MLX5_ASSERT(ret != REG_NONE);
1562 * Validate vport item.
1565 * Pointer to the rte_eth_dev structure.
1567 * Item specification.
1569 * Attributes of flow that includes this item.
1570 * @param[in] item_flags
1571 * Bit-fields that holds the items detected until now.
1573 * Pointer to error structure.
1576 * 0 on success, a negative errno value otherwise and rte_errno is set.
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580 const struct rte_flow_item *item,
1581 const struct rte_flow_attr *attr,
1582 uint64_t item_flags,
1583 struct rte_flow_error *error)
1585 const struct rte_flow_item_port_id *spec = item->spec;
1586 const struct rte_flow_item_port_id *mask = item->mask;
1587 const struct rte_flow_item_port_id switch_mask = {
1590 struct mlx5_priv *esw_priv;
1591 struct mlx5_priv *dev_priv;
1594 if (!attr->transfer)
1595 return rte_flow_error_set(error, EINVAL,
1596 RTE_FLOW_ERROR_TYPE_ITEM,
1598 "match on port id is valid only"
1599 " when transfer flag is enabled");
1600 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601 return rte_flow_error_set(error, ENOTSUP,
1602 RTE_FLOW_ERROR_TYPE_ITEM, item,
1603 "multiple source ports are not"
1606 mask = &switch_mask;
1607 if (mask->id != 0xffffffff)
1608 return rte_flow_error_set(error, ENOTSUP,
1609 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1611 "no support for partial mask on"
1613 ret = mlx5_flow_item_acceptable
1614 (item, (const uint8_t *)mask,
1615 (const uint8_t *)&rte_flow_item_port_id_mask,
1616 sizeof(struct rte_flow_item_port_id),
1622 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1624 return rte_flow_error_set(error, rte_errno,
1625 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626 "failed to obtain E-Switch info for"
1628 dev_priv = mlx5_dev_to_eswitch_info(dev);
1630 return rte_flow_error_set(error, rte_errno,
1631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1633 "failed to obtain E-Switch info");
1634 if (esw_priv->domain_id != dev_priv->domain_id)
1635 return rte_flow_error_set(error, EINVAL,
1636 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637 "cannot match on a port from a"
1638 " different E-Switch");
1643 * GTP flags are contained in 1 byte of the format:
1644 * -------------------------------------------
1645 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1646 * |-----------------------------------------|
1647 * | value | Version | PT | Res | E | S | PN |
1648 * -------------------------------------------
1650 * Matching is supported only for GTP flags E, S, PN.
1652 #define MLX5_GTP_FLAGS_MASK 0x07
1655 * Validate VLAN item.
1658 * Item specification.
1659 * @param[in] item_flags
1660 * Bit-fields that holds the items detected until now.
1662 * Ethernet device flow is being created on.
1664 * Pointer to error structure.
1667 * 0 on success, a negative errno value otherwise and rte_errno is set.
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671 uint64_t item_flags,
1672 struct rte_eth_dev *dev,
1673 struct rte_flow_error *error)
1675 const struct rte_flow_item_vlan *mask = item->mask;
1676 const struct rte_flow_item_vlan nic_mask = {
1677 .tci = RTE_BE16(UINT16_MAX),
1678 .inner_type = RTE_BE16(UINT16_MAX),
1680 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1682 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683 MLX5_FLOW_LAYER_INNER_L4) :
1684 (MLX5_FLOW_LAYER_OUTER_L3 |
1685 MLX5_FLOW_LAYER_OUTER_L4);
1686 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687 MLX5_FLOW_LAYER_OUTER_VLAN;
1689 if (item_flags & vlanm)
1690 return rte_flow_error_set(error, EINVAL,
1691 RTE_FLOW_ERROR_TYPE_ITEM, item,
1692 "multiple VLAN layers not supported");
1693 else if ((item_flags & l34m) != 0)
1694 return rte_flow_error_set(error, EINVAL,
1695 RTE_FLOW_ERROR_TYPE_ITEM, item,
1696 "VLAN cannot follow L3/L4 layer");
1698 mask = &rte_flow_item_vlan_mask;
1699 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700 (const uint8_t *)&nic_mask,
1701 sizeof(struct rte_flow_item_vlan),
1705 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706 struct mlx5_priv *priv = dev->data->dev_private;
1708 if (priv->vmwa_context) {
1710 * Non-NULL context means we have a virtual machine
1711 * and SR-IOV enabled, we have to create VLAN interface
1712 * to make hypervisor to setup E-Switch vport
1713 * context correctly. We avoid creating the multiple
1714 * VLAN interfaces, so we cannot support VLAN tag mask.
1716 return rte_flow_error_set(error, EINVAL,
1717 RTE_FLOW_ERROR_TYPE_ITEM,
1719 "VLAN tag mask is not"
1720 " supported in virtual"
1728 * Validate GTP item.
1731 * Pointer to the rte_eth_dev structure.
1733 * Item specification.
1734 * @param[in] item_flags
1735 * Bit-fields that holds the items detected until now.
1737 * Pointer to error structure.
1740 * 0 on success, a negative errno value otherwise and rte_errno is set.
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744 const struct rte_flow_item *item,
1745 uint64_t item_flags,
1746 struct rte_flow_error *error)
1748 struct mlx5_priv *priv = dev->data->dev_private;
1749 const struct rte_flow_item_gtp *spec = item->spec;
1750 const struct rte_flow_item_gtp *mask = item->mask;
1751 const struct rte_flow_item_gtp nic_mask = {
1752 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1754 .teid = RTE_BE32(0xffffffff),
1757 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758 return rte_flow_error_set(error, ENOTSUP,
1759 RTE_FLOW_ERROR_TYPE_ITEM, item,
1760 "GTP support is not enabled");
1761 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762 return rte_flow_error_set(error, ENOTSUP,
1763 RTE_FLOW_ERROR_TYPE_ITEM, item,
1764 "multiple tunnel layers not"
1766 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767 return rte_flow_error_set(error, EINVAL,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "no outer UDP layer found");
1771 mask = &rte_flow_item_gtp_mask;
1772 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773 return rte_flow_error_set(error, ENOTSUP,
1774 RTE_FLOW_ERROR_TYPE_ITEM, item,
1775 "Match is supported for GTP"
1777 return mlx5_flow_item_acceptable
1778 (item, (const uint8_t *)mask,
1779 (const uint8_t *)&nic_mask,
1780 sizeof(struct rte_flow_item_gtp),
1785 * Validate the pop VLAN action.
1788 * Pointer to the rte_eth_dev structure.
1789 * @param[in] action_flags
1790 * Holds the actions detected until now.
1792 * Pointer to the pop vlan action.
1793 * @param[in] item_flags
1794 * The items found in this flow rule.
1796 * Pointer to flow attributes.
1798 * Pointer to error structure.
1801 * 0 on success, a negative errno value otherwise and rte_errno is set.
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805 uint64_t action_flags,
1806 const struct rte_flow_action *action,
1807 uint64_t item_flags,
1808 const struct rte_flow_attr *attr,
1809 struct rte_flow_error *error)
1811 const struct mlx5_priv *priv = dev->data->dev_private;
1815 if (!priv->sh->pop_vlan_action)
1816 return rte_flow_error_set(error, ENOTSUP,
1817 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1819 "pop vlan action is not supported");
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1824 "pop vlan action not supported for "
1826 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827 return rte_flow_error_set(error, ENOTSUP,
1828 RTE_FLOW_ERROR_TYPE_ACTION, action,
1829 "no support for multiple VLAN "
1831 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1835 "cannot pop vlan without a "
1836 "match on (outer) vlan in the flow");
1837 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838 return rte_flow_error_set(error, EINVAL,
1839 RTE_FLOW_ERROR_TYPE_ACTION, action,
1840 "wrong action order, port_id should "
1841 "be after pop VLAN action");
1842 if (!attr->transfer && priv->representor)
1843 return rte_flow_error_set(error, ENOTSUP,
1844 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845 "pop vlan action for VF representor "
1846 "not supported on NIC table");
1851 * Get VLAN default info from vlan match info.
1854 * the list of item specifications.
1856 * pointer VLAN info to fill to.
1859 * 0 on success, a negative errno value otherwise and rte_errno is set.
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863 struct rte_vlan_hdr *vlan)
1865 const struct rte_flow_item_vlan nic_mask = {
1866 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867 MLX5DV_FLOW_VLAN_VID_MASK),
1868 .inner_type = RTE_BE16(0xffff),
1873 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874 int type = items->type;
1876 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1880 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882 const struct rte_flow_item_vlan *vlan_v = items->spec;
1886 /* Only full match values are accepted */
1887 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1888 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1889 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1891 rte_be_to_cpu_16(vlan_v->tci &
1892 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1894 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1895 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1896 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1898 rte_be_to_cpu_16(vlan_v->tci &
1899 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1901 if (vlan_m->inner_type == nic_mask.inner_type)
1902 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1903 vlan_m->inner_type);
1908 * Validate the push VLAN action.
1911 * Pointer to the rte_eth_dev structure.
1912 * @param[in] action_flags
1913 * Holds the actions detected until now.
1914 * @param[in] item_flags
1915 * The items found in this flow rule.
1917 * Pointer to the action structure.
1919 * Pointer to flow attributes
1921 * Pointer to error structure.
1924 * 0 on success, a negative errno value otherwise and rte_errno is set.
1927 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1928 uint64_t action_flags,
1929 const struct rte_flow_item_vlan *vlan_m,
1930 const struct rte_flow_action *action,
1931 const struct rte_flow_attr *attr,
1932 struct rte_flow_error *error)
1934 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1935 const struct mlx5_priv *priv = dev->data->dev_private;
1937 if (!attr->transfer && attr->ingress)
1938 return rte_flow_error_set(error, ENOTSUP,
1939 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1941 "push VLAN action not supported for "
1943 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1944 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1945 return rte_flow_error_set(error, EINVAL,
1946 RTE_FLOW_ERROR_TYPE_ACTION, action,
1947 "invalid vlan ethertype");
1948 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ACTION, action,
1951 "no support for multiple VLAN "
1953 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1954 return rte_flow_error_set(error, EINVAL,
1955 RTE_FLOW_ERROR_TYPE_ACTION, action,
1956 "wrong action order, port_id should "
1957 "be after push VLAN");
1958 if (!attr->transfer && priv->representor)
1959 return rte_flow_error_set(error, ENOTSUP,
1960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1961 "push vlan action for VF representor "
1962 "not supported on NIC table");
1964 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1965 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1966 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1967 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1968 !(mlx5_flow_find_action
1969 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1970 return rte_flow_error_set(error, EINVAL,
1971 RTE_FLOW_ERROR_TYPE_ACTION, action,
1972 "not full match mask on VLAN PCP and "
1973 "there is no of_set_vlan_pcp action, "
1974 "push VLAN action cannot figure out "
1977 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1978 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1979 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1980 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1981 !(mlx5_flow_find_action
1982 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ACTION, action,
1985 "not full match mask on VLAN VID and "
1986 "there is no of_set_vlan_vid action, "
1987 "push VLAN action cannot figure out "
1994 * Validate the set VLAN PCP.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1998 * @param[in] actions
1999 * Pointer to the list of actions remaining in the flow rule.
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2008 const struct rte_flow_action actions[],
2009 struct rte_flow_error *error)
2011 const struct rte_flow_action *action = actions;
2012 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2014 if (conf->vlan_pcp > 7)
2015 return rte_flow_error_set(error, EINVAL,
2016 RTE_FLOW_ERROR_TYPE_ACTION, action,
2017 "VLAN PCP value is too big");
2018 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2019 return rte_flow_error_set(error, ENOTSUP,
2020 RTE_FLOW_ERROR_TYPE_ACTION, action,
2021 "set VLAN PCP action must follow "
2022 "the push VLAN action");
2023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2024 return rte_flow_error_set(error, ENOTSUP,
2025 RTE_FLOW_ERROR_TYPE_ACTION, action,
2026 "Multiple VLAN PCP modification are "
2028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2029 return rte_flow_error_set(error, EINVAL,
2030 RTE_FLOW_ERROR_TYPE_ACTION, action,
2031 "wrong action order, port_id should "
2032 "be after set VLAN PCP");
2037 * Validate the set VLAN VID.
2039 * @param[in] item_flags
2040 * Holds the items detected in this rule.
2041 * @param[in] action_flags
2042 * Holds the actions detected until now.
2043 * @param[in] actions
2044 * Pointer to the list of actions remaining in the flow rule.
2046 * Pointer to error structure.
2049 * 0 on success, a negative errno value otherwise and rte_errno is set.
2052 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2053 uint64_t action_flags,
2054 const struct rte_flow_action actions[],
2055 struct rte_flow_error *error)
2057 const struct rte_flow_action *action = actions;
2058 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2060 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ACTION, action,
2063 "VLAN VID value is too big");
2064 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2065 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2066 return rte_flow_error_set(error, ENOTSUP,
2067 RTE_FLOW_ERROR_TYPE_ACTION, action,
2068 "set VLAN VID action must follow push"
2069 " VLAN action or match on VLAN item");
2070 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2071 return rte_flow_error_set(error, ENOTSUP,
2072 RTE_FLOW_ERROR_TYPE_ACTION, action,
2073 "Multiple VLAN VID modifications are "
2075 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2076 return rte_flow_error_set(error, EINVAL,
2077 RTE_FLOW_ERROR_TYPE_ACTION, action,
2078 "wrong action order, port_id should "
2079 "be after set VLAN VID");
2084 * Validate the FLAG action.
2087 * Pointer to the rte_eth_dev structure.
2088 * @param[in] action_flags
2089 * Holds the actions detected until now.
2091 * Pointer to flow attributes
2093 * Pointer to error structure.
2096 * 0 on success, a negative errno value otherwise and rte_errno is set.
2099 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2100 uint64_t action_flags,
2101 const struct rte_flow_attr *attr,
2102 struct rte_flow_error *error)
2104 struct mlx5_priv *priv = dev->data->dev_private;
2105 struct mlx5_dev_config *config = &priv->config;
2108 /* Fall back if no extended metadata register support. */
2109 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2110 return mlx5_flow_validate_action_flag(action_flags, attr,
2112 /* Extensive metadata mode requires registers. */
2113 if (!mlx5_flow_ext_mreg_supported(dev))
2114 return rte_flow_error_set(error, ENOTSUP,
2115 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2116 "no metadata registers "
2117 "to support flag action");
2118 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2119 return rte_flow_error_set(error, ENOTSUP,
2120 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2121 "extended metadata register"
2122 " isn't available");
2123 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2126 MLX5_ASSERT(ret > 0);
2127 if (action_flags & MLX5_FLOW_ACTION_MARK)
2128 return rte_flow_error_set(error, EINVAL,
2129 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2130 "can't mark and flag in same flow");
2131 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2135 " actions in same flow");
2140 * Validate MARK action.
2143 * Pointer to the rte_eth_dev structure.
2145 * Pointer to action.
2146 * @param[in] action_flags
2147 * Holds the actions detected until now.
2149 * Pointer to flow attributes
2151 * Pointer to error structure.
2154 * 0 on success, a negative errno value otherwise and rte_errno is set.
2157 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2158 const struct rte_flow_action *action,
2159 uint64_t action_flags,
2160 const struct rte_flow_attr *attr,
2161 struct rte_flow_error *error)
2163 struct mlx5_priv *priv = dev->data->dev_private;
2164 struct mlx5_dev_config *config = &priv->config;
2165 const struct rte_flow_action_mark *mark = action->conf;
2168 /* Fall back if no extended metadata register support. */
2169 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2170 return mlx5_flow_validate_action_mark(action, action_flags,
2172 /* Extensive metadata mode requires registers. */
2173 if (!mlx5_flow_ext_mreg_supported(dev))
2174 return rte_flow_error_set(error, ENOTSUP,
2175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2176 "no metadata registers "
2177 "to support mark action");
2178 if (!priv->sh->dv_mark_mask)
2179 return rte_flow_error_set(error, ENOTSUP,
2180 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2181 "extended metadata register"
2182 " isn't available");
2183 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2186 MLX5_ASSERT(ret > 0);
2188 return rte_flow_error_set(error, EINVAL,
2189 RTE_FLOW_ERROR_TYPE_ACTION, action,
2190 "configuration cannot be null");
2191 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2192 return rte_flow_error_set(error, EINVAL,
2193 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2195 "mark id exceeds the limit");
2196 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2199 "can't flag and mark in same flow");
2200 if (action_flags & MLX5_FLOW_ACTION_MARK)
2201 return rte_flow_error_set(error, EINVAL,
2202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2203 "can't have 2 mark actions in same"
2209 * Validate SET_META action.
2212 * Pointer to the rte_eth_dev structure.
2214 * Pointer to the action structure.
2215 * @param[in] action_flags
2216 * Holds the actions detected until now.
2218 * Pointer to flow attributes
2220 * Pointer to error structure.
2223 * 0 on success, a negative errno value otherwise and rte_errno is set.
2226 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2227 const struct rte_flow_action *action,
2228 uint64_t action_flags __rte_unused,
2229 const struct rte_flow_attr *attr,
2230 struct rte_flow_error *error)
2232 const struct rte_flow_action_set_meta *conf;
2233 uint32_t nic_mask = UINT32_MAX;
2236 if (!mlx5_flow_ext_mreg_supported(dev))
2237 return rte_flow_error_set(error, ENOTSUP,
2238 RTE_FLOW_ERROR_TYPE_ACTION, action,
2239 "extended metadata register"
2240 " isn't supported");
2241 reg = flow_dv_get_metadata_reg(dev, attr, error);
2244 if (reg != REG_A && reg != REG_B) {
2245 struct mlx5_priv *priv = dev->data->dev_private;
2247 nic_mask = priv->sh->dv_meta_mask;
2249 if (!(action->conf))
2250 return rte_flow_error_set(error, EINVAL,
2251 RTE_FLOW_ERROR_TYPE_ACTION, action,
2252 "configuration cannot be null");
2253 conf = (const struct rte_flow_action_set_meta *)action->conf;
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "zero mask doesn't have any effect");
2258 if (conf->mask & ~nic_mask)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, action,
2261 "meta data must be within reg C0");
2266 * Validate SET_TAG action.
2269 * Pointer to the rte_eth_dev structure.
2271 * Pointer to the action structure.
2272 * @param[in] action_flags
2273 * Holds the actions detected until now.
2275 * Pointer to flow attributes
2277 * Pointer to error structure.
2280 * 0 on success, a negative errno value otherwise and rte_errno is set.
2283 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2284 const struct rte_flow_action *action,
2285 uint64_t action_flags,
2286 const struct rte_flow_attr *attr,
2287 struct rte_flow_error *error)
2289 const struct rte_flow_action_set_tag *conf;
2290 const uint64_t terminal_action_flags =
2291 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2292 MLX5_FLOW_ACTION_RSS;
2295 if (!mlx5_flow_ext_mreg_supported(dev))
2296 return rte_flow_error_set(error, ENOTSUP,
2297 RTE_FLOW_ERROR_TYPE_ACTION, action,
2298 "extensive metadata register"
2299 " isn't supported");
2300 if (!(action->conf))
2301 return rte_flow_error_set(error, EINVAL,
2302 RTE_FLOW_ERROR_TYPE_ACTION, action,
2303 "configuration cannot be null");
2304 conf = (const struct rte_flow_action_set_tag *)action->conf;
2306 return rte_flow_error_set(error, EINVAL,
2307 RTE_FLOW_ERROR_TYPE_ACTION, action,
2308 "zero mask doesn't have any effect");
2309 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2312 if (!attr->transfer && attr->ingress &&
2313 (action_flags & terminal_action_flags))
2314 return rte_flow_error_set(error, EINVAL,
2315 RTE_FLOW_ERROR_TYPE_ACTION, action,
2316 "set_tag has no effect"
2317 " with terminal actions");
2322 * Validate count action.
2325 * Pointer to rte_eth_dev structure.
2327 * Pointer to error structure.
2330 * 0 on success, a negative errno value otherwise and rte_errno is set.
2333 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2334 struct rte_flow_error *error)
2336 struct mlx5_priv *priv = dev->data->dev_private;
2338 if (!priv->config.devx)
2340 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344 return rte_flow_error_set
2346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2348 "count action not supported");
2352 * Validate the L2 encap action.
2355 * Pointer to the rte_eth_dev structure.
2356 * @param[in] action_flags
2357 * Holds the actions detected until now.
2359 * Pointer to the action structure.
2361 * Pointer to flow attributes.
2363 * Pointer to error structure.
2366 * 0 on success, a negative errno value otherwise and rte_errno is set.
2369 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2370 uint64_t action_flags,
2371 const struct rte_flow_action *action,
2372 const struct rte_flow_attr *attr,
2373 struct rte_flow_error *error)
2375 const struct mlx5_priv *priv = dev->data->dev_private;
2377 if (!(action->conf))
2378 return rte_flow_error_set(error, EINVAL,
2379 RTE_FLOW_ERROR_TYPE_ACTION, action,
2380 "configuration cannot be null");
2381 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2382 return rte_flow_error_set(error, EINVAL,
2383 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2384 "can only have a single encap action "
2386 if (!attr->transfer && priv->representor)
2387 return rte_flow_error_set(error, ENOTSUP,
2388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2389 "encap action for VF representor "
2390 "not supported on NIC table");
2395 * Validate a decap action.
2398 * Pointer to the rte_eth_dev structure.
2399 * @param[in] action_flags
2400 * Holds the actions detected until now.
2402 * Pointer to flow attributes
2404 * Pointer to error structure.
2407 * 0 on success, a negative errno value otherwise and rte_errno is set.
2410 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2411 uint64_t action_flags,
2412 const struct rte_flow_attr *attr,
2413 struct rte_flow_error *error)
2415 const struct mlx5_priv *priv = dev->data->dev_private;
2417 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2418 return rte_flow_error_set(error, ENOTSUP,
2419 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2421 MLX5_FLOW_ACTION_DECAP ? "can only "
2422 "have a single decap action" : "decap "
2423 "after encap is not supported");
2424 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2425 return rte_flow_error_set(error, EINVAL,
2426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2427 "can't have decap action after"
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2433 "decap action not supported for "
2435 if (!attr->transfer && priv->representor)
2436 return rte_flow_error_set(error, ENOTSUP,
2437 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2438 "decap action for VF representor "
2439 "not supported on NIC table");
2443 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2446 * Validate the raw encap and decap actions.
2449 * Pointer to the rte_eth_dev structure.
2451 * Pointer to the decap action.
2453 * Pointer to the encap action.
2455 * Pointer to flow attributes
2456 * @param[in/out] action_flags
2457 * Holds the actions detected until now.
2458 * @param[out] actions_n
2459 * pointer to the number of actions counter.
2461 * Pointer to error structure.
2464 * 0 on success, a negative errno value otherwise and rte_errno is set.
2467 flow_dv_validate_action_raw_encap_decap
2468 (struct rte_eth_dev *dev,
2469 const struct rte_flow_action_raw_decap *decap,
2470 const struct rte_flow_action_raw_encap *encap,
2471 const struct rte_flow_attr *attr, uint64_t *action_flags,
2472 int *actions_n, struct rte_flow_error *error)
2474 const struct mlx5_priv *priv = dev->data->dev_private;
2477 if (encap && (!encap->size || !encap->data))
2478 return rte_flow_error_set(error, EINVAL,
2479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2480 "raw encap data cannot be empty");
2481 if (decap && encap) {
2482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2486 else if (encap->size <=
2487 MLX5_ENCAPSULATION_DECISION_SIZE &&
2489 MLX5_ENCAPSULATION_DECISION_SIZE)
2492 else if (encap->size >
2493 MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 MLX5_ENCAPSULATION_DECISION_SIZE)
2496 /* 2 L2 actions: encap and decap. */
2499 return rte_flow_error_set(error,
2501 RTE_FLOW_ERROR_TYPE_ACTION,
2502 NULL, "unsupported too small "
2503 "raw decap and too small raw "
2504 "encap combination");
2507 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2516 return rte_flow_error_set(error, ENOTSUP,
2517 RTE_FLOW_ERROR_TYPE_ACTION,
2519 "small raw encap size");
2520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2521 return rte_flow_error_set(error, EINVAL,
2522 RTE_FLOW_ERROR_TYPE_ACTION,
2524 "more than one encap action");
2525 if (!attr->transfer && priv->representor)
2526 return rte_flow_error_set
2528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2529 "encap action for VF representor "
2530 "not supported on NIC table");
2531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2538 * Find existing encap/decap resource or create and register a new one.
2540 * @param[in, out] dev
2541 * Pointer to rte_eth_dev structure.
2542 * @param[in, out] resource
2543 * Pointer to encap/decap resource.
2544 * @parm[in, out] dev_flow
2545 * Pointer to the dev_flow.
2547 * pointer to error structure.
2550 * 0 on success otherwise -errno and errno is set.
2553 flow_dv_encap_decap_resource_register
2554 (struct rte_eth_dev *dev,
2555 struct mlx5_flow_dv_encap_decap_resource *resource,
2556 struct mlx5_flow *dev_flow,
2557 struct rte_flow_error *error)
2559 struct mlx5_priv *priv = dev->data->dev_private;
2560 struct mlx5_ibv_shared *sh = priv->sh;
2561 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2562 struct mlx5dv_dr_domain *domain;
2565 resource->flags = dev_flow->dv.group ? 0 : 1;
2566 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2567 domain = sh->fdb_domain;
2568 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2569 domain = sh->rx_domain;
2571 domain = sh->tx_domain;
2572 /* Lookup a matching resource from cache. */
2573 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2574 cache_resource, next) {
2575 if (resource->reformat_type == cache_resource->reformat_type &&
2576 resource->ft_type == cache_resource->ft_type &&
2577 resource->flags == cache_resource->flags &&
2578 resource->size == cache_resource->size &&
2579 !memcmp((const void *)resource->buf,
2580 (const void *)cache_resource->buf,
2582 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2583 (void *)cache_resource,
2584 rte_atomic32_read(&cache_resource->refcnt));
2585 rte_atomic32_inc(&cache_resource->refcnt);
2586 dev_flow->handle->dvh.rix_encap_decap = idx;
2587 dev_flow->dv.encap_decap = cache_resource;
2591 /* Register new encap/decap resource. */
2592 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2593 &dev_flow->handle->dvh.rix_encap_decap);
2594 if (!cache_resource)
2595 return rte_flow_error_set(error, ENOMEM,
2596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597 "cannot allocate resource memory");
2598 *cache_resource = *resource;
2599 cache_resource->verbs_action =
2600 mlx5_glue->dv_create_flow_action_packet_reformat
2601 (sh->ctx, cache_resource->reformat_type,
2602 cache_resource->ft_type, domain, cache_resource->flags,
2603 cache_resource->size,
2604 (cache_resource->size ? cache_resource->buf : NULL));
2605 if (!cache_resource->verbs_action) {
2606 rte_free(cache_resource);
2607 return rte_flow_error_set(error, ENOMEM,
2608 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2609 NULL, "cannot create action");
2611 rte_atomic32_init(&cache_resource->refcnt);
2612 rte_atomic32_inc(&cache_resource->refcnt);
2613 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2614 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2616 dev_flow->dv.encap_decap = cache_resource;
2617 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2618 (void *)cache_resource,
2619 rte_atomic32_read(&cache_resource->refcnt));
2624 * Find existing table jump resource or create and register a new one.
2626 * @param[in, out] dev
2627 * Pointer to rte_eth_dev structure.
2628 * @param[in, out] tbl
2629 * Pointer to flow table resource.
2630 * @parm[in, out] dev_flow
2631 * Pointer to the dev_flow.
2633 * pointer to error structure.
2636 * 0 on success otherwise -errno and errno is set.
2639 flow_dv_jump_tbl_resource_register
2640 (struct rte_eth_dev *dev __rte_unused,
2641 struct mlx5_flow_tbl_resource *tbl,
2642 struct mlx5_flow *dev_flow,
2643 struct rte_flow_error *error)
2645 struct mlx5_flow_tbl_data_entry *tbl_data =
2646 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2652 tbl_data->jump.action =
2653 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2655 if (!tbl_data->jump.action)
2656 return rte_flow_error_set(error, ENOMEM,
2657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2658 NULL, "cannot create jump action");
2659 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2660 (void *)&tbl_data->jump, cnt);
2662 /* old jump should not make the table ref++. */
2663 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2664 MLX5_ASSERT(tbl_data->jump.action);
2665 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2666 (void *)&tbl_data->jump, cnt);
2668 rte_atomic32_inc(&tbl_data->jump.refcnt);
2669 dev_flow->handle->rix_jump = tbl_data->idx;
2670 dev_flow->dv.jump = &tbl_data->jump;
2675 * Find existing table port ID resource or create and register a new one.
2677 * @param[in, out] dev
2678 * Pointer to rte_eth_dev structure.
2679 * @param[in, out] resource
2680 * Pointer to port ID action resource.
2681 * @parm[in, out] dev_flow
2682 * Pointer to the dev_flow.
2684 * pointer to error structure.
2687 * 0 on success otherwise -errno and errno is set.
2690 flow_dv_port_id_action_resource_register
2691 (struct rte_eth_dev *dev,
2692 struct mlx5_flow_dv_port_id_action_resource *resource,
2693 struct mlx5_flow *dev_flow,
2694 struct rte_flow_error *error)
2696 struct mlx5_priv *priv = dev->data->dev_private;
2697 struct mlx5_ibv_shared *sh = priv->sh;
2698 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2701 /* Lookup a matching resource from cache. */
2702 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2703 idx, cache_resource, next) {
2704 if (resource->port_id == cache_resource->port_id) {
2705 DRV_LOG(DEBUG, "port id action resource resource %p: "
2707 (void *)cache_resource,
2708 rte_atomic32_read(&cache_resource->refcnt));
2709 rte_atomic32_inc(&cache_resource->refcnt);
2710 dev_flow->handle->rix_port_id_action = idx;
2711 dev_flow->dv.port_id_action = cache_resource;
2715 /* Register new port id action resource. */
2716 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2717 &dev_flow->handle->rix_port_id_action);
2718 if (!cache_resource)
2719 return rte_flow_error_set(error, ENOMEM,
2720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2721 "cannot allocate resource memory");
2722 *cache_resource = *resource;
2724 * Depending on rdma_core version the glue routine calls
2725 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2726 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2728 cache_resource->action =
2729 mlx5_glue->dr_create_flow_action_dest_port
2730 (priv->sh->fdb_domain, resource->port_id);
2731 if (!cache_resource->action) {
2732 rte_free(cache_resource);
2733 return rte_flow_error_set(error, ENOMEM,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2735 NULL, "cannot create action");
2737 rte_atomic32_init(&cache_resource->refcnt);
2738 rte_atomic32_inc(&cache_resource->refcnt);
2739 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2740 dev_flow->handle->rix_port_id_action, cache_resource,
2742 dev_flow->dv.port_id_action = cache_resource;
2743 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2744 (void *)cache_resource,
2745 rte_atomic32_read(&cache_resource->refcnt));
2750 * Find existing push vlan resource or create and register a new one.
2752 * @param [in, out] dev
2753 * Pointer to rte_eth_dev structure.
2754 * @param[in, out] resource
2755 * Pointer to port ID action resource.
2756 * @parm[in, out] dev_flow
2757 * Pointer to the dev_flow.
2759 * pointer to error structure.
2762 * 0 on success otherwise -errno and errno is set.
2765 flow_dv_push_vlan_action_resource_register
2766 (struct rte_eth_dev *dev,
2767 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2768 struct mlx5_flow *dev_flow,
2769 struct rte_flow_error *error)
2771 struct mlx5_priv *priv = dev->data->dev_private;
2772 struct mlx5_ibv_shared *sh = priv->sh;
2773 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2774 struct mlx5dv_dr_domain *domain;
2777 /* Lookup a matching resource from cache. */
2778 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2779 sh->push_vlan_action_list, idx, cache_resource, next) {
2780 if (resource->vlan_tag == cache_resource->vlan_tag &&
2781 resource->ft_type == cache_resource->ft_type) {
2782 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2784 (void *)cache_resource,
2785 rte_atomic32_read(&cache_resource->refcnt));
2786 rte_atomic32_inc(&cache_resource->refcnt);
2787 dev_flow->handle->dvh.rix_push_vlan = idx;
2788 dev_flow->dv.push_vlan_res = cache_resource;
2792 /* Register new push_vlan action resource. */
2793 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2794 &dev_flow->handle->dvh.rix_push_vlan);
2795 if (!cache_resource)
2796 return rte_flow_error_set(error, ENOMEM,
2797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2798 "cannot allocate resource memory");
2799 *cache_resource = *resource;
2800 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2801 domain = sh->fdb_domain;
2802 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2803 domain = sh->rx_domain;
2805 domain = sh->tx_domain;
2806 cache_resource->action =
2807 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2808 resource->vlan_tag);
2809 if (!cache_resource->action) {
2810 rte_free(cache_resource);
2811 return rte_flow_error_set(error, ENOMEM,
2812 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2813 NULL, "cannot create action");
2815 rte_atomic32_init(&cache_resource->refcnt);
2816 rte_atomic32_inc(&cache_resource->refcnt);
2817 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2818 &sh->push_vlan_action_list,
2819 dev_flow->handle->dvh.rix_push_vlan,
2820 cache_resource, next);
2821 dev_flow->dv.push_vlan_res = cache_resource;
2822 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2823 (void *)cache_resource,
2824 rte_atomic32_read(&cache_resource->refcnt));
2828 * Get the size of specific rte_flow_item_type
2830 * @param[in] item_type
2831 * Tested rte_flow_item_type.
2834 * sizeof struct item_type, 0 if void or irrelevant.
2837 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 switch (item_type) {
2842 case RTE_FLOW_ITEM_TYPE_ETH:
2843 retval = sizeof(struct rte_flow_item_eth);
2845 case RTE_FLOW_ITEM_TYPE_VLAN:
2846 retval = sizeof(struct rte_flow_item_vlan);
2848 case RTE_FLOW_ITEM_TYPE_IPV4:
2849 retval = sizeof(struct rte_flow_item_ipv4);
2851 case RTE_FLOW_ITEM_TYPE_IPV6:
2852 retval = sizeof(struct rte_flow_item_ipv6);
2854 case RTE_FLOW_ITEM_TYPE_UDP:
2855 retval = sizeof(struct rte_flow_item_udp);
2857 case RTE_FLOW_ITEM_TYPE_TCP:
2858 retval = sizeof(struct rte_flow_item_tcp);
2860 case RTE_FLOW_ITEM_TYPE_VXLAN:
2861 retval = sizeof(struct rte_flow_item_vxlan);
2863 case RTE_FLOW_ITEM_TYPE_GRE:
2864 retval = sizeof(struct rte_flow_item_gre);
2866 case RTE_FLOW_ITEM_TYPE_NVGRE:
2867 retval = sizeof(struct rte_flow_item_nvgre);
2869 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2870 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2872 case RTE_FLOW_ITEM_TYPE_MPLS:
2873 retval = sizeof(struct rte_flow_item_mpls);
2875 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2883 #define MLX5_ENCAP_IPV4_VERSION 0x40
2884 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2885 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2886 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2887 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2888 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2889 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2892 * Convert the encap action data from list of rte_flow_item to raw buffer
2895 * Pointer to rte_flow_item objects list.
2897 * Pointer to the output buffer.
2899 * Pointer to the output buffer size.
2901 * Pointer to the error structure.
2904 * 0 on success, a negative errno value otherwise and rte_errno is set.
2907 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2908 size_t *size, struct rte_flow_error *error)
2910 struct rte_ether_hdr *eth = NULL;
2911 struct rte_vlan_hdr *vlan = NULL;
2912 struct rte_ipv4_hdr *ipv4 = NULL;
2913 struct rte_ipv6_hdr *ipv6 = NULL;
2914 struct rte_udp_hdr *udp = NULL;
2915 struct rte_vxlan_hdr *vxlan = NULL;
2916 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2917 struct rte_gre_hdr *gre = NULL;
2919 size_t temp_size = 0;
2922 return rte_flow_error_set(error, EINVAL,
2923 RTE_FLOW_ERROR_TYPE_ACTION,
2924 NULL, "invalid empty data");
2925 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2926 len = flow_dv_get_item_len(items->type);
2927 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2928 return rte_flow_error_set(error, EINVAL,
2929 RTE_FLOW_ERROR_TYPE_ACTION,
2930 (void *)items->type,
2931 "items total size is too big"
2932 " for encap action");
2933 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2934 switch (items->type) {
2935 case RTE_FLOW_ITEM_TYPE_ETH:
2936 eth = (struct rte_ether_hdr *)&buf[temp_size];
2938 case RTE_FLOW_ITEM_TYPE_VLAN:
2939 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2941 return rte_flow_error_set(error, EINVAL,
2942 RTE_FLOW_ERROR_TYPE_ACTION,
2943 (void *)items->type,
2944 "eth header not found");
2945 if (!eth->ether_type)
2946 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2948 case RTE_FLOW_ITEM_TYPE_IPV4:
2949 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2951 return rte_flow_error_set(error, EINVAL,
2952 RTE_FLOW_ERROR_TYPE_ACTION,
2953 (void *)items->type,
2954 "neither eth nor vlan"
2956 if (vlan && !vlan->eth_proto)
2957 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2958 else if (eth && !eth->ether_type)
2959 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2960 if (!ipv4->version_ihl)
2961 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2962 MLX5_ENCAP_IPV4_IHL_MIN;
2963 if (!ipv4->time_to_live)
2964 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2966 case RTE_FLOW_ITEM_TYPE_IPV6:
2967 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2969 return rte_flow_error_set(error, EINVAL,
2970 RTE_FLOW_ERROR_TYPE_ACTION,
2971 (void *)items->type,
2972 "neither eth nor vlan"
2974 if (vlan && !vlan->eth_proto)
2975 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2976 else if (eth && !eth->ether_type)
2977 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2978 if (!ipv6->vtc_flow)
2980 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2981 if (!ipv6->hop_limits)
2982 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2984 case RTE_FLOW_ITEM_TYPE_UDP:
2985 udp = (struct rte_udp_hdr *)&buf[temp_size];
2987 return rte_flow_error_set(error, EINVAL,
2988 RTE_FLOW_ERROR_TYPE_ACTION,
2989 (void *)items->type,
2990 "ip header not found");
2991 if (ipv4 && !ipv4->next_proto_id)
2992 ipv4->next_proto_id = IPPROTO_UDP;
2993 else if (ipv6 && !ipv6->proto)
2994 ipv6->proto = IPPROTO_UDP;
2996 case RTE_FLOW_ITEM_TYPE_VXLAN:
2997 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2999 return rte_flow_error_set(error, EINVAL,
3000 RTE_FLOW_ERROR_TYPE_ACTION,
3001 (void *)items->type,
3002 "udp header not found");
3004 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3005 if (!vxlan->vx_flags)
3007 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3009 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3010 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3012 return rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ACTION,
3014 (void *)items->type,
3015 "udp header not found");
3016 if (!vxlan_gpe->proto)
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION,
3019 (void *)items->type,
3020 "next protocol not found");
3023 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3024 if (!vxlan_gpe->vx_flags)
3025 vxlan_gpe->vx_flags =
3026 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3028 case RTE_FLOW_ITEM_TYPE_GRE:
3029 case RTE_FLOW_ITEM_TYPE_NVGRE:
3030 gre = (struct rte_gre_hdr *)&buf[temp_size];
3032 return rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION,
3034 (void *)items->type,
3035 "next protocol not found");
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION,
3039 (void *)items->type,
3040 "ip header not found");
3041 if (ipv4 && !ipv4->next_proto_id)
3042 ipv4->next_proto_id = IPPROTO_GRE;
3043 else if (ipv6 && !ipv6->proto)
3044 ipv6->proto = IPPROTO_GRE;
3046 case RTE_FLOW_ITEM_TYPE_VOID:
3049 return rte_flow_error_set(error, EINVAL,
3050 RTE_FLOW_ERROR_TYPE_ACTION,
3051 (void *)items->type,
3052 "unsupported item type");
3062 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3064 struct rte_ether_hdr *eth = NULL;
3065 struct rte_vlan_hdr *vlan = NULL;
3066 struct rte_ipv6_hdr *ipv6 = NULL;
3067 struct rte_udp_hdr *udp = NULL;
3071 eth = (struct rte_ether_hdr *)data;
3072 next_hdr = (char *)(eth + 1);
3073 proto = RTE_BE16(eth->ether_type);
3076 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3077 vlan = (struct rte_vlan_hdr *)next_hdr;
3078 proto = RTE_BE16(vlan->eth_proto);
3079 next_hdr += sizeof(struct rte_vlan_hdr);
3082 /* HW calculates IPv4 csum. no need to proceed */
3083 if (proto == RTE_ETHER_TYPE_IPV4)
3086 /* non IPv4/IPv6 header. not supported */
3087 if (proto != RTE_ETHER_TYPE_IPV6) {
3088 return rte_flow_error_set(error, ENOTSUP,
3089 RTE_FLOW_ERROR_TYPE_ACTION,
3090 NULL, "Cannot offload non IPv4/IPv6");
3093 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3095 /* ignore non UDP */
3096 if (ipv6->proto != IPPROTO_UDP)
3099 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3100 udp->dgram_cksum = 0;
3106 * Convert L2 encap action to DV specification.
3109 * Pointer to rte_eth_dev structure.
3111 * Pointer to action structure.
3112 * @param[in, out] dev_flow
3113 * Pointer to the mlx5_flow.
3114 * @param[in] transfer
3115 * Mark if the flow is E-Switch flow.
3117 * Pointer to the error structure.
3120 * 0 on success, a negative errno value otherwise and rte_errno is set.
3123 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3124 const struct rte_flow_action *action,
3125 struct mlx5_flow *dev_flow,
3127 struct rte_flow_error *error)
3129 const struct rte_flow_item *encap_data;
3130 const struct rte_flow_action_raw_encap *raw_encap_data;
3131 struct mlx5_flow_dv_encap_decap_resource res = {
3133 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3134 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3135 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3138 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3140 (const struct rte_flow_action_raw_encap *)action->conf;
3141 res.size = raw_encap_data->size;
3142 memcpy(res.buf, raw_encap_data->data, res.size);
3144 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3146 ((const struct rte_flow_action_vxlan_encap *)
3147 action->conf)->definition;
3150 ((const struct rte_flow_action_nvgre_encap *)
3151 action->conf)->definition;
3152 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3158 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION,
3161 NULL, "can't create L2 encap action");
3166 * Convert L2 decap action to DV specification.
3169 * Pointer to rte_eth_dev structure.
3170 * @param[in, out] dev_flow
3171 * Pointer to the mlx5_flow.
3172 * @param[in] transfer
3173 * Mark if the flow is E-Switch flow.
3175 * Pointer to the error structure.
3178 * 0 on success, a negative errno value otherwise and rte_errno is set.
3181 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3182 struct mlx5_flow *dev_flow,
3184 struct rte_flow_error *error)
3186 struct mlx5_flow_dv_encap_decap_resource res = {
3189 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3190 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3191 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3194 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3195 return rte_flow_error_set(error, EINVAL,
3196 RTE_FLOW_ERROR_TYPE_ACTION,
3197 NULL, "can't create L2 decap action");
3202 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3205 * Pointer to rte_eth_dev structure.
3207 * Pointer to action structure.
3208 * @param[in, out] dev_flow
3209 * Pointer to the mlx5_flow.
3211 * Pointer to the flow attributes.
3213 * Pointer to the error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3220 const struct rte_flow_action *action,
3221 struct mlx5_flow *dev_flow,
3222 const struct rte_flow_attr *attr,
3223 struct rte_flow_error *error)
3225 const struct rte_flow_action_raw_encap *encap_data;
3226 struct mlx5_flow_dv_encap_decap_resource res;
3228 memset(&res, 0, sizeof(res));
3229 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3230 res.size = encap_data->size;
3231 memcpy(res.buf, encap_data->data, res.size);
3232 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3233 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3234 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3236 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3238 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3239 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3240 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3241 return rte_flow_error_set(error, EINVAL,
3242 RTE_FLOW_ERROR_TYPE_ACTION,
3243 NULL, "can't create encap action");
3248 * Create action push VLAN.
3251 * Pointer to rte_eth_dev structure.
3253 * Pointer to the flow attributes.
3255 * Pointer to the vlan to push to the Ethernet header.
3256 * @param[in, out] dev_flow
3257 * Pointer to the mlx5_flow.
3259 * Pointer to the error structure.
3262 * 0 on success, a negative errno value otherwise and rte_errno is set.
3265 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3266 const struct rte_flow_attr *attr,
3267 const struct rte_vlan_hdr *vlan,
3268 struct mlx5_flow *dev_flow,
3269 struct rte_flow_error *error)
3271 struct mlx5_flow_dv_push_vlan_action_resource res;
3273 memset(&res, 0, sizeof(res));
3275 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3278 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3280 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3281 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3282 return flow_dv_push_vlan_action_resource_register
3283 (dev, &res, dev_flow, error);
3287 * Validate the modify-header actions.
3289 * @param[in] action_flags
3290 * Holds the actions detected until now.
3292 * Pointer to the modify action.
3294 * Pointer to error structure.
3297 * 0 on success, a negative errno value otherwise and rte_errno is set.
3300 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3301 const struct rte_flow_action *action,
3302 struct rte_flow_error *error)
3304 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3305 return rte_flow_error_set(error, EINVAL,
3306 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3307 NULL, "action configuration not set");
3308 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311 "can't have encap action before"
3317 * Validate the modify-header MAC address actions.
3319 * @param[in] action_flags
3320 * Holds the actions detected until now.
3322 * Pointer to the modify action.
3323 * @param[in] item_flags
3324 * Holds the items detected.
3326 * Pointer to error structure.
3329 * 0 on success, a negative errno value otherwise and rte_errno is set.
3332 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3333 const struct rte_flow_action *action,
3334 const uint64_t item_flags,
3335 struct rte_flow_error *error)
3339 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3341 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION,
3345 "no L2 item in pattern");
3351 * Validate the modify-header IPv4 address actions.
3353 * @param[in] action_flags
3354 * Holds the actions detected until now.
3356 * Pointer to the modify action.
3357 * @param[in] item_flags
3358 * Holds the items detected.
3360 * Pointer to error structure.
3363 * 0 on success, a negative errno value otherwise and rte_errno is set.
3366 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3367 const struct rte_flow_action *action,
3368 const uint64_t item_flags,
3369 struct rte_flow_error *error)
3374 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3376 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3377 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3378 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3379 if (!(item_flags & layer))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "no ipv4 item in pattern");
3389 * Validate the modify-header IPv6 address actions.
3391 * @param[in] action_flags
3392 * Holds the actions detected until now.
3394 * Pointer to the modify action.
3395 * @param[in] item_flags
3396 * Holds the items detected.
3398 * Pointer to error structure.
3401 * 0 on success, a negative errno value otherwise and rte_errno is set.
3404 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3405 const struct rte_flow_action *action,
3406 const uint64_t item_flags,
3407 struct rte_flow_error *error)
3412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3416 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3417 if (!(item_flags & layer))
3418 return rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ACTION,
3421 "no ipv6 item in pattern");
3427 * Validate the modify-header TP actions.
3429 * @param[in] action_flags
3430 * Holds the actions detected until now.
3432 * Pointer to the modify action.
3433 * @param[in] item_flags
3434 * Holds the items detected.
3436 * Pointer to error structure.
3439 * 0 on success, a negative errno value otherwise and rte_errno is set.
3442 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const uint64_t item_flags,
3445 struct rte_flow_error *error)
3450 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3452 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453 MLX5_FLOW_LAYER_INNER_L4 :
3454 MLX5_FLOW_LAYER_OUTER_L4;
3455 if (!(item_flags & layer))
3456 return rte_flow_error_set(error, EINVAL,
3457 RTE_FLOW_ERROR_TYPE_ACTION,
3458 NULL, "no transport layer "
3465 * Validate the modify-header actions of increment/decrement
3466 * TCP Sequence-number.
3468 * @param[in] action_flags
3469 * Holds the actions detected until now.
3471 * Pointer to the modify action.
3472 * @param[in] item_flags
3473 * Holds the items detected.
3475 * Pointer to error structure.
3478 * 0 on success, a negative errno value otherwise and rte_errno is set.
3481 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3482 const struct rte_flow_action *action,
3483 const uint64_t item_flags,
3484 struct rte_flow_error *error)
3489 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3491 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3492 MLX5_FLOW_LAYER_INNER_L4_TCP :
3493 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3494 if (!(item_flags & layer))
3495 return rte_flow_error_set(error, EINVAL,
3496 RTE_FLOW_ERROR_TYPE_ACTION,
3497 NULL, "no TCP item in"
3499 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3500 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3501 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3502 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3503 return rte_flow_error_set(error, EINVAL,
3504 RTE_FLOW_ERROR_TYPE_ACTION,
3506 "cannot decrease and increase"
3507 " TCP sequence number"
3508 " at the same time");
3514 * Validate the modify-header actions of increment/decrement
3515 * TCP Acknowledgment number.
3517 * @param[in] action_flags
3518 * Holds the actions detected until now.
3520 * Pointer to the modify action.
3521 * @param[in] item_flags
3522 * Holds the items detected.
3524 * Pointer to error structure.
3527 * 0 on success, a negative errno value otherwise and rte_errno is set.
3530 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3531 const struct rte_flow_action *action,
3532 const uint64_t item_flags,
3533 struct rte_flow_error *error)
3538 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3540 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3541 MLX5_FLOW_LAYER_INNER_L4_TCP :
3542 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3543 if (!(item_flags & layer))
3544 return rte_flow_error_set(error, EINVAL,
3545 RTE_FLOW_ERROR_TYPE_ACTION,
3546 NULL, "no TCP item in"
3548 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3549 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3550 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3551 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3552 return rte_flow_error_set(error, EINVAL,
3553 RTE_FLOW_ERROR_TYPE_ACTION,
3555 "cannot decrease and increase"
3556 " TCP acknowledgment number"
3557 " at the same time");
3563 * Validate the modify-header TTL actions.
3565 * @param[in] action_flags
3566 * Holds the actions detected until now.
3568 * Pointer to the modify action.
3569 * @param[in] item_flags
3570 * Holds the items detected.
3572 * Pointer to error structure.
3575 * 0 on success, a negative errno value otherwise and rte_errno is set.
3578 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3579 const struct rte_flow_action *action,
3580 const uint64_t item_flags,
3581 struct rte_flow_error *error)
3586 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3588 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3589 MLX5_FLOW_LAYER_INNER_L3 :
3590 MLX5_FLOW_LAYER_OUTER_L3;
3591 if (!(item_flags & layer))
3592 return rte_flow_error_set(error, EINVAL,
3593 RTE_FLOW_ERROR_TYPE_ACTION,
3595 "no IP protocol in pattern");
3601 * Validate jump action.
3604 * Pointer to the jump action.
3605 * @param[in] action_flags
3606 * Holds the actions detected until now.
3607 * @param[in] attributes
3608 * Pointer to flow attributes
3609 * @param[in] external
3610 * Action belongs to flow rule created by request external to PMD.
3612 * Pointer to error structure.
3615 * 0 on success, a negative errno value otherwise and rte_errno is set.
3618 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3619 uint64_t action_flags,
3620 const struct rte_flow_attr *attributes,
3621 bool external, struct rte_flow_error *error)
3623 uint32_t target_group, table;
3626 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3627 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3628 return rte_flow_error_set(error, EINVAL,
3629 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3630 "can't have 2 fate actions in"
3632 if (action_flags & MLX5_FLOW_ACTION_METER)
3633 return rte_flow_error_set(error, ENOTSUP,
3634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3635 "jump with meter not support");
3637 return rte_flow_error_set(error, EINVAL,
3638 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3639 NULL, "action configuration not set");
3641 ((const struct rte_flow_action_jump *)action->conf)->group;
3642 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3643 true, &table, error);
3646 if (attributes->group == target_group)
3647 return rte_flow_error_set(error, EINVAL,
3648 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3649 "target group must be other than"
3650 " the current flow group");
3655 * Validate the port_id action.
3658 * Pointer to rte_eth_dev structure.
3659 * @param[in] action_flags
3660 * Bit-fields that holds the actions detected until now.
3662 * Port_id RTE action structure.
3664 * Attributes of flow that includes this action.
3666 * Pointer to error structure.
3669 * 0 on success, a negative errno value otherwise and rte_errno is set.
3672 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3673 uint64_t action_flags,
3674 const struct rte_flow_action *action,
3675 const struct rte_flow_attr *attr,
3676 struct rte_flow_error *error)
3678 const struct rte_flow_action_port_id *port_id;
3679 struct mlx5_priv *act_priv;
3680 struct mlx5_priv *dev_priv;
3683 if (!attr->transfer)
3684 return rte_flow_error_set(error, ENOTSUP,
3685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3687 "port id action is valid in transfer"
3689 if (!action || !action->conf)
3690 return rte_flow_error_set(error, ENOTSUP,
3691 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3693 "port id action parameters must be"
3695 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3696 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3697 return rte_flow_error_set(error, EINVAL,
3698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699 "can have only one fate actions in"
3701 dev_priv = mlx5_dev_to_eswitch_info(dev);
3703 return rte_flow_error_set(error, rte_errno,
3704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3706 "failed to obtain E-Switch info");
3707 port_id = action->conf;
3708 port = port_id->original ? dev->data->port_id : port_id->id;
3709 act_priv = mlx5_port_to_eswitch_info(port, false);
3711 return rte_flow_error_set
3713 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3714 "failed to obtain E-Switch port id for port");
3715 if (act_priv->domain_id != dev_priv->domain_id)
3716 return rte_flow_error_set
3718 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3719 "port does not belong to"
3720 " E-Switch being configured");
3725 * Get the maximum number of modify header actions.
3728 * Pointer to rte_eth_dev structure.
3730 * Flags bits to check if root level.
3733 * Max number of modify header actions device can support.
3735 static inline unsigned int
3736 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740 * There's no way to directly query the max capacity from FW.
3741 * The maximal value on root table should be assumed to be supported.
3743 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3744 return MLX5_MAX_MODIFY_NUM;
3746 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 * Validate the meter action.
3753 * Pointer to rte_eth_dev structure.
3754 * @param[in] action_flags
3755 * Bit-fields that holds the actions detected until now.
3757 * Pointer to the meter action.
3759 * Attributes of flow that includes this action.
3761 * Pointer to error structure.
3764 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3767 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3768 uint64_t action_flags,
3769 const struct rte_flow_action *action,
3770 const struct rte_flow_attr *attr,
3771 struct rte_flow_error *error)
3773 struct mlx5_priv *priv = dev->data->dev_private;
3774 const struct rte_flow_action_meter *am = action->conf;
3775 struct mlx5_flow_meter *fm;
3778 return rte_flow_error_set(error, EINVAL,
3779 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3780 "meter action conf is NULL");
3782 if (action_flags & MLX5_FLOW_ACTION_METER)
3783 return rte_flow_error_set(error, ENOTSUP,
3784 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3785 "meter chaining not support");
3786 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3787 return rte_flow_error_set(error, ENOTSUP,
3788 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3789 "meter with jump not support");
3791 return rte_flow_error_set(error, ENOTSUP,
3792 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3794 "meter action not supported");
3795 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3797 return rte_flow_error_set(error, EINVAL,
3798 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3800 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3801 (!fm->ingress && !attr->ingress && attr->egress) ||
3802 (!fm->egress && !attr->egress && attr->ingress))))
3803 return rte_flow_error_set(error, EINVAL,
3804 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3805 "Flow attributes are either invalid "
3806 "or have a conflict with current "
3807 "meter attributes");
3812 * Validate the age action.
3814 * @param[in] action_flags
3815 * Holds the actions detected until now.
3817 * Pointer to the age action.
3819 * Pointer to the Ethernet device structure.
3821 * Pointer to error structure.
3824 * 0 on success, a negative errno value otherwise and rte_errno is set.
3827 flow_dv_validate_action_age(uint64_t action_flags,
3828 const struct rte_flow_action *action,
3829 struct rte_eth_dev *dev,
3830 struct rte_flow_error *error)
3832 struct mlx5_priv *priv = dev->data->dev_private;
3833 const struct rte_flow_action_age *age = action->conf;
3835 if (!priv->config.devx || priv->counter_fallback)
3836 return rte_flow_error_set(error, ENOTSUP,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3839 "age action not supported");
3840 if (!(action->conf))
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, action,
3843 "configuration cannot be null");
3844 if (age->timeout >= UINT16_MAX / 2 / 10)
3845 return rte_flow_error_set(error, ENOTSUP,
3846 RTE_FLOW_ERROR_TYPE_ACTION, action,
3847 "Max age time: 3275 seconds");
3848 if (action_flags & MLX5_FLOW_ACTION_AGE)
3849 return rte_flow_error_set(error, EINVAL,
3850 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3851 "Duplicate age ctions set");
3856 * Validate the modify-header IPv4 DSCP actions.
3858 * @param[in] action_flags
3859 * Holds the actions detected until now.
3861 * Pointer to the modify action.
3862 * @param[in] item_flags
3863 * Holds the items detected.
3865 * Pointer to error structure.
3868 * 0 on success, a negative errno value otherwise and rte_errno is set.
3871 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3872 const struct rte_flow_action *action,
3873 const uint64_t item_flags,
3874 struct rte_flow_error *error)
3878 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3880 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3881 return rte_flow_error_set(error, EINVAL,
3882 RTE_FLOW_ERROR_TYPE_ACTION,
3884 "no ipv4 item in pattern");
3890 * Validate the modify-header IPv6 DSCP actions.
3892 * @param[in] action_flags
3893 * Holds the actions detected until now.
3895 * Pointer to the modify action.
3896 * @param[in] item_flags
3897 * Holds the items detected.
3899 * Pointer to error structure.
3902 * 0 on success, a negative errno value otherwise and rte_errno is set.
3905 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3906 const struct rte_flow_action *action,
3907 const uint64_t item_flags,
3908 struct rte_flow_error *error)
3912 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3914 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3915 return rte_flow_error_set(error, EINVAL,
3916 RTE_FLOW_ERROR_TYPE_ACTION,
3918 "no ipv6 item in pattern");
3924 * Find existing modify-header resource or create and register a new one.
3926 * @param dev[in, out]
3927 * Pointer to rte_eth_dev structure.
3928 * @param[in, out] resource
3929 * Pointer to modify-header resource.
3930 * @parm[in, out] dev_flow
3931 * Pointer to the dev_flow.
3933 * pointer to error structure.
3936 * 0 on success otherwise -errno and errno is set.
3939 flow_dv_modify_hdr_resource_register
3940 (struct rte_eth_dev *dev,
3941 struct mlx5_flow_dv_modify_hdr_resource *resource,
3942 struct mlx5_flow *dev_flow,
3943 struct rte_flow_error *error)
3945 struct mlx5_priv *priv = dev->data->dev_private;
3946 struct mlx5_ibv_shared *sh = priv->sh;
3947 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3948 struct mlx5dv_dr_domain *ns;
3949 uint32_t actions_len;
3951 resource->flags = dev_flow->dv.group ? 0 :
3952 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3953 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3955 return rte_flow_error_set(error, EOVERFLOW,
3956 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3957 "too many modify header items");
3958 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3959 ns = sh->fdb_domain;
3960 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964 /* Lookup a matching resource from cache. */
3965 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3966 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3967 if (resource->ft_type == cache_resource->ft_type &&
3968 resource->actions_num == cache_resource->actions_num &&
3969 resource->flags == cache_resource->flags &&
3970 !memcmp((const void *)resource->actions,
3971 (const void *)cache_resource->actions,
3973 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3974 (void *)cache_resource,
3975 rte_atomic32_read(&cache_resource->refcnt));
3976 rte_atomic32_inc(&cache_resource->refcnt);
3977 dev_flow->handle->dvh.modify_hdr = cache_resource;
3981 /* Register new modify-header resource. */
3982 cache_resource = rte_calloc(__func__, 1,
3983 sizeof(*cache_resource) + actions_len, 0);
3984 if (!cache_resource)
3985 return rte_flow_error_set(error, ENOMEM,
3986 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3987 "cannot allocate resource memory");
3988 *cache_resource = *resource;
3989 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3990 cache_resource->verbs_action =
3991 mlx5_glue->dv_create_flow_action_modify_header
3992 (sh->ctx, cache_resource->ft_type, ns,
3993 cache_resource->flags, actions_len,
3994 (uint64_t *)cache_resource->actions);
3995 if (!cache_resource->verbs_action) {
3996 rte_free(cache_resource);
3997 return rte_flow_error_set(error, ENOMEM,
3998 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3999 NULL, "cannot create action");
4001 rte_atomic32_init(&cache_resource->refcnt);
4002 rte_atomic32_inc(&cache_resource->refcnt);
4003 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4004 dev_flow->handle->dvh.modify_hdr = cache_resource;
4005 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4006 (void *)cache_resource,
4007 rte_atomic32_read(&cache_resource->refcnt));
4012 * Get DV flow counter by index.
4015 * Pointer to the Ethernet device structure.
4017 * mlx5 flow counter index in the container.
4019 * mlx5 flow counter pool in the container,
4022 * Pointer to the counter, NULL otherwise.
4024 static struct mlx5_flow_counter *
4025 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4027 struct mlx5_flow_counter_pool **ppool)
4029 struct mlx5_priv *priv = dev->data->dev_private;
4030 struct mlx5_pools_container *cont;
4031 struct mlx5_flow_counter_pool *pool;
4032 uint32_t batch = 0, age = 0;
4035 age = MLX_CNT_IS_AGE(idx);
4036 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4037 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4038 idx -= MLX5_CNT_BATCH_OFFSET;
4041 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4042 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4043 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 * Get a pool by devx counter ID.
4054 * Pointer to the counter container.
4056 * The counter devx ID.
4059 * The counter pool pointer if exists, NULL otherwise,
4061 static struct mlx5_flow_counter_pool *
4062 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4065 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4067 for (i = 0; i < n_valid; i++) {
4068 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4069 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4070 MLX5_COUNTERS_PER_POOL;
4072 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4074 * Move the pool to the head, as counter allocate
4075 * always gets the first pool in the container.
4077 if (pool != TAILQ_FIRST(&cont->pool_list)) {
4078 TAILQ_REMOVE(&cont->pool_list, pool, next);
4079 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4088 * Allocate a new memory for the counter values wrapped by all the needed
4092 * Pointer to the Ethernet device structure.
4094 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4097 * The new memory management pointer on success, otherwise NULL and rte_errno
4100 static struct mlx5_counter_stats_mem_mng *
4101 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4103 struct mlx5_priv *priv = dev->data->dev_private;
4104 struct mlx5_ibv_shared *sh = priv->sh;
4105 struct mlx5_devx_mkey_attr mkey_attr;
4106 struct mlx5_counter_stats_mem_mng *mem_mng;
4107 volatile struct flow_counter_stats *raw_data;
4108 int size = (sizeof(struct flow_counter_stats) *
4109 MLX5_COUNTERS_PER_POOL +
4110 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4111 sizeof(struct mlx5_counter_stats_mem_mng);
4112 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4119 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4120 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4121 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4122 IBV_ACCESS_LOCAL_WRITE);
4123 if (!mem_mng->umem) {
4128 mkey_attr.addr = (uintptr_t)mem;
4129 mkey_attr.size = size;
4130 mkey_attr.umem_id = mem_mng->umem->umem_id;
4131 mkey_attr.pd = sh->pdn;
4132 mkey_attr.log_entity_size = 0;
4133 mkey_attr.pg_access = 0;
4134 mkey_attr.klm_array = NULL;
4135 mkey_attr.klm_num = 0;
4136 if (priv->config.hca_attr.relaxed_ordering_write &&
4137 priv->config.hca_attr.relaxed_ordering_read)
4138 mkey_attr.relaxed_ordering = 1;
4139 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4141 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4146 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4147 raw_data = (volatile struct flow_counter_stats *)mem;
4148 for (i = 0; i < raws_n; ++i) {
4149 mem_mng->raws[i].mem_mng = mem_mng;
4150 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4152 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4157 * Resize a counter container.
4160 * Pointer to the Ethernet device structure.
4162 * Whether the pool is for counter that was allocated by batch command.
4164 * Whether the pool is for Aging counter.
4167 * The new container pointer on success, otherwise NULL and rte_errno is set.
4169 static struct mlx5_pools_container *
4170 flow_dv_container_resize(struct rte_eth_dev *dev,
4171 uint32_t batch, uint32_t age)
4173 struct mlx5_priv *priv = dev->data->dev_private;
4174 struct mlx5_pools_container *cont =
4175 MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4176 struct mlx5_pools_container *new_cont =
4177 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4178 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4179 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4180 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4183 /* Fallback mode has no background thread. Skip the check. */
4184 if (!priv->counter_fallback &&
4185 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4186 /* The last resize still hasn't detected by the host thread. */
4190 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4191 if (!new_cont->pools) {
4196 memcpy(new_cont->pools, cont->pools, cont->n *
4197 sizeof(struct mlx5_flow_counter_pool *));
4199 * Fallback mode query the counter directly, no background query
4200 * resources are needed.
4202 if (!priv->counter_fallback) {
4203 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4204 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4206 rte_free(new_cont->pools);
4209 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4210 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4212 MLX5_CNT_CONTAINER_RESIZE +
4216 * Release the old container pools directly as no background
4217 * thread helps that.
4219 rte_free(cont->pools);
4221 new_cont->n = resize;
4222 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4223 TAILQ_INIT(&new_cont->pool_list);
4224 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4225 new_cont->init_mem_mng = mem_mng;
4227 /* Flip the master container. */
4228 priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4233 * Query a devx flow counter.
4236 * Pointer to the Ethernet device structure.
4238 * Index to the flow counter.
4240 * The statistics value of packets.
4242 * The statistics value of bytes.
4245 * 0 on success, otherwise a negative errno value and rte_errno is set.
4248 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4251 struct mlx5_priv *priv = dev->data->dev_private;
4252 struct mlx5_flow_counter_pool *pool = NULL;
4253 struct mlx5_flow_counter *cnt;
4254 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4257 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4259 if (counter < MLX5_CNT_BATCH_OFFSET) {
4260 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4261 if (priv->counter_fallback)
4262 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4263 0, pkts, bytes, 0, NULL, NULL, 0);
4266 rte_spinlock_lock(&pool->sl);
4268 * The single counters allocation may allocate smaller ID than the
4269 * current allocated in parallel to the host reading.
4270 * In this case the new counter values must be reported as 0.
4272 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4276 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4277 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4278 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4280 rte_spinlock_unlock(&pool->sl);
4285 * Create and initialize a new counter pool.
4288 * Pointer to the Ethernet device structure.
4290 * The devX counter handle.
4292 * Whether the pool is for counter that was allocated by batch command.
4294 * Whether the pool is for counter that was allocated for aging.
4295 * @param[in/out] cont_cur
4296 * Pointer to the container pointer, it will be update in pool resize.
4299 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4301 static struct mlx5_pools_container *
4302 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4303 uint32_t batch, uint32_t age)
4305 struct mlx5_priv *priv = dev->data->dev_private;
4306 struct mlx5_flow_counter_pool *pool;
4307 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4309 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4310 uint32_t size = sizeof(*pool);
4312 if (cont->n == n_valid) {
4313 cont = flow_dv_container_resize(dev, batch, age);
4317 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4318 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4319 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4320 pool = rte_calloc(__func__, 1, size, 0);
4325 pool->min_dcs = dcs;
4326 if (!priv->counter_fallback)
4327 pool->raw = cont->init_mem_mng->raws + n_valid %
4328 MLX5_CNT_CONTAINER_RESIZE;
4329 pool->raw_hw = NULL;
4331 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4332 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4333 rte_spinlock_init(&pool->sl);
4335 * The generation of the new allocated counters in this pool is 0, 2 in
4336 * the pool generation makes all the counters valid for allocation.
4337 * The start and end query generation protect the counters be released
4338 * between the query and update gap period will not be reallocated
4339 * without the last query finished and stats updated to the memory.
4341 rte_atomic64_set(&pool->start_query_gen, 0x2);
4343 * There's no background query thread for fallback mode, set the
4344 * end_query_gen to the maximum value since no need to wait for
4345 * statistics update.
4347 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4349 TAILQ_INIT(&pool->counters);
4350 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4351 pool->index = n_valid;
4352 cont->pools[n_valid] = pool;
4353 /* Pool initialization must be updated before host thread access. */
4355 rte_atomic16_add(&cont->n_valid, 1);
4360 * Update the minimum dcs-id for aged or no-aged counter pool.
4363 * Pointer to the Ethernet device structure.
4365 * Current counter pool.
4367 * Whether the pool is for counter that was allocated by batch command.
4369 * Whether the counter is for aging.
4372 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4373 struct mlx5_flow_counter_pool *pool,
4374 uint32_t batch, uint32_t age)
4376 struct mlx5_priv *priv = dev->data->dev_private;
4377 struct mlx5_flow_counter_pool *other;
4378 struct mlx5_pools_container *cont;
4380 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4381 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4384 if (pool->min_dcs->id < other->min_dcs->id) {
4385 rte_atomic64_set(&other->a64_dcs,
4386 rte_atomic64_read(&pool->a64_dcs));
4388 rte_atomic64_set(&pool->a64_dcs,
4389 rte_atomic64_read(&other->a64_dcs));
4393 * Prepare a new counter and/or a new counter pool.
4396 * Pointer to the Ethernet device structure.
4397 * @param[out] cnt_free
4398 * Where to put the pointer of a new counter.
4400 * Whether the pool is for counter that was allocated by batch command.
4402 * Whether the pool is for counter that was allocated for aging.
4405 * The counter container pointer and @p cnt_free is set on success,
4406 * NULL otherwise and rte_errno is set.
4408 static struct mlx5_pools_container *
4409 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4410 struct mlx5_flow_counter **cnt_free,
4411 uint32_t batch, uint32_t age)
4413 struct mlx5_priv *priv = dev->data->dev_private;
4414 struct mlx5_pools_container *cont;
4415 struct mlx5_flow_counter_pool *pool;
4416 struct mlx5_devx_obj *dcs = NULL;
4417 struct mlx5_flow_counter *cnt;
4420 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4422 /* bulk_bitmap must be 0 for single counter allocation. */
4423 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4426 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4428 cont = flow_dv_pool_create(dev, dcs, batch, age);
4430 mlx5_devx_cmd_destroy(dcs);
4433 pool = TAILQ_FIRST(&cont->pool_list);
4434 } else if (dcs->id < pool->min_dcs->id) {
4435 rte_atomic64_set(&pool->a64_dcs,
4436 (int64_t)(uintptr_t)dcs);
4438 flow_dv_counter_update_min_dcs(dev,
4440 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4441 cnt = MLX5_POOL_GET_CNT(pool, i);
4442 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4443 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4447 /* bulk_bitmap is in 128 counters units. */
4448 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4449 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4451 rte_errno = ENODATA;
4454 cont = flow_dv_pool_create(dev, dcs, batch, age);
4456 mlx5_devx_cmd_destroy(dcs);
4459 pool = TAILQ_FIRST(&cont->pool_list);
4460 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4461 cnt = MLX5_POOL_GET_CNT(pool, i);
4462 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4464 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4469 * Search for existed shared counter.
4472 * Pointer to the relevant counter pool container.
4474 * The shared counter ID to search.
4476 * mlx5 flow counter pool in the container,
4479 * NULL if not existed, otherwise pointer to the shared extend counter.
4481 static struct mlx5_flow_counter_ext *
4482 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4483 struct mlx5_flow_counter_pool **ppool)
4485 static struct mlx5_flow_counter_ext *cnt;
4486 struct mlx5_flow_counter_pool *pool;
4488 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4490 for (i = 0; i < n_valid; i++) {
4491 pool = cont->pools[i];
4492 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4493 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4494 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4496 *ppool = cont->pools[i];
4505 * Allocate a flow counter.
4508 * Pointer to the Ethernet device structure.
4510 * Indicate if this counter is shared with other flows.
4512 * Counter identifier.
4514 * Counter flow group.
4516 * Whether the counter was allocated for aging.
4519 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4522 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4523 uint16_t group, uint32_t age)
4525 struct mlx5_priv *priv = dev->data->dev_private;
4526 struct mlx5_flow_counter_pool *pool = NULL;
4527 struct mlx5_flow_counter *cnt_free = NULL;
4528 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4530 * Currently group 0 flow counter cannot be assigned to a flow if it is
4531 * not the first one in the batch counter allocation, so it is better
4532 * to allocate counters one by one for these flows in a separate
4534 * A counter can be shared between different groups so need to take
4535 * shared counters from the single container.
4537 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4538 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4542 if (!priv->config.devx) {
4543 rte_errno = ENOTSUP;
4547 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4549 if (cnt_ext->ref_cnt + 1 == 0) {
4554 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4555 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4560 /* Pools which has a free counters are in the start. */
4561 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4563 * The free counter reset values must be updated between the
4564 * counter release to the counter allocation, so, at least one
4565 * query must be done in this time. ensure it by saving the
4566 * query generation in the release time.
4567 * The free list is sorted according to the generation - so if
4568 * the first one is not updated, all the others are not
4571 cnt_free = TAILQ_FIRST(&pool->counters);
4572 if (cnt_free && cnt_free->query_gen <
4573 rte_atomic64_read(&pool->end_query_gen))
4578 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4581 pool = TAILQ_FIRST(&cont->pool_list);
4584 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4585 /* Create a DV counter action only in the first time usage. */
4586 if (!cnt_free->action) {
4588 struct mlx5_devx_obj *dcs;
4591 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4592 dcs = pool->min_dcs;
4597 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4599 if (!cnt_free->action) {
4604 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4605 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4606 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4607 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4608 /* Update the counter reset values. */
4609 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4613 cnt_ext->shared = shared;
4614 cnt_ext->ref_cnt = 1;
4617 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4618 /* Start the asynchronous batch query by the host thread. */
4619 mlx5_set_query_alarm(priv->sh);
4620 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4621 if (TAILQ_EMPTY(&pool->counters)) {
4622 /* Move the pool to the end of the container pool list. */
4623 TAILQ_REMOVE(&cont->pool_list, pool, next);
4624 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4630 * Get age param from counter index.
4633 * Pointer to the Ethernet device structure.
4634 * @param[in] counter
4635 * Index to the counter handler.
4638 * The aging parameter specified for the counter index.
4640 static struct mlx5_age_param*
4641 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4644 struct mlx5_flow_counter *cnt;
4645 struct mlx5_flow_counter_pool *pool = NULL;
4647 flow_dv_counter_get_by_idx(dev, counter, &pool);
4648 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4649 cnt = MLX5_POOL_GET_CNT(pool, counter);
4650 return MLX5_CNT_TO_AGE(cnt);
4654 * Remove a flow counter from aged counter list.
4657 * Pointer to the Ethernet device structure.
4658 * @param[in] counter
4659 * Index to the counter handler.
4661 * Pointer to the counter handler.
4664 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4665 uint32_t counter, struct mlx5_flow_counter *cnt)
4667 struct mlx5_age_info *age_info;
4668 struct mlx5_age_param *age_param;
4669 struct mlx5_priv *priv = dev->data->dev_private;
4671 age_info = GET_PORT_AGE_INFO(priv);
4672 age_param = flow_dv_counter_idx_get_age(dev, counter);
4673 if (rte_atomic16_cmpset((volatile uint16_t *)
4675 AGE_CANDIDATE, AGE_FREE)
4678 * We need the lock even it is age timeout,
4679 * since counter may still in process.
4681 rte_spinlock_lock(&age_info->aged_sl);
4682 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4683 rte_spinlock_unlock(&age_info->aged_sl);
4685 rte_atomic16_set(&age_param->state, AGE_FREE);
4688 * Release a flow counter.
4691 * Pointer to the Ethernet device structure.
4692 * @param[in] counter
4693 * Index to the counter handler.
4696 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4698 struct mlx5_flow_counter_pool *pool = NULL;
4699 struct mlx5_flow_counter *cnt;
4700 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4704 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4706 if (counter < MLX5_CNT_BATCH_OFFSET) {
4707 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4708 if (cnt_ext && --cnt_ext->ref_cnt)
4711 if (IS_AGE_POOL(pool))
4712 flow_dv_counter_remove_from_age(dev, counter, cnt);
4713 /* Put the counter in the end - the last updated one. */
4714 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4716 * Counters released between query trigger and handler need
4717 * to wait the next round of query. Since the packets arrive
4718 * in the gap period will not be taken into account to the
4721 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4725 * Verify the @p attributes will be correctly understood by the NIC and store
4726 * them in the @p flow if everything is correct.
4729 * Pointer to dev struct.
4730 * @param[in] attributes
4731 * Pointer to flow attributes
4732 * @param[in] external
4733 * This flow rule is created by request external to PMD.
4735 * Pointer to error structure.
4738 * - 0 on success and non root table.
4739 * - 1 on success and root table.
4740 * - a negative errno value otherwise and rte_errno is set.
4743 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4744 const struct rte_flow_attr *attributes,
4745 bool external __rte_unused,
4746 struct rte_flow_error *error)
4748 struct mlx5_priv *priv = dev->data->dev_private;
4749 uint32_t priority_max = priv->config.flow_prio - 1;
4752 #ifndef HAVE_MLX5DV_DR
4753 if (attributes->group)
4754 return rte_flow_error_set(error, ENOTSUP,
4755 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4757 "groups are not supported");
4761 ret = mlx5_flow_group_to_table(attributes, external,
4762 attributes->group, !!priv->fdb_def_rule,
4767 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4769 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4770 attributes->priority >= priority_max)
4771 return rte_flow_error_set(error, ENOTSUP,
4772 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4774 "priority out of range");
4775 if (attributes->transfer) {
4776 if (!priv->config.dv_esw_en)
4777 return rte_flow_error_set
4779 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4780 "E-Switch dr is not supported");
4781 if (!(priv->representor || priv->master))
4782 return rte_flow_error_set
4783 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4784 NULL, "E-Switch configuration can only be"
4785 " done by a master or a representor device");
4786 if (attributes->egress)
4787 return rte_flow_error_set
4789 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4790 "egress is not supported");
4792 if (!(attributes->egress ^ attributes->ingress))
4793 return rte_flow_error_set(error, ENOTSUP,
4794 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4795 "must specify exactly one of "
4796 "ingress or egress");
4801 * Internal validation function. For validating both actions and items.
4804 * Pointer to the rte_eth_dev structure.
4806 * Pointer to the flow attributes.
4808 * Pointer to the list of items.
4809 * @param[in] actions
4810 * Pointer to the list of actions.
4811 * @param[in] external
4812 * This flow rule is created by request external to PMD.
4813 * @param[in] hairpin
4814 * Number of hairpin TX actions, 0 means classic flow.
4816 * Pointer to the error structure.
4819 * 0 on success, a negative errno value otherwise and rte_errno is set.
4822 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4823 const struct rte_flow_item items[],
4824 const struct rte_flow_action actions[],
4825 bool external, int hairpin, struct rte_flow_error *error)
4828 uint64_t action_flags = 0;
4829 uint64_t item_flags = 0;
4830 uint64_t last_item = 0;
4831 uint8_t next_protocol = 0xff;
4832 uint16_t ether_type = 0;
4834 uint8_t item_ipv6_proto = 0;
4835 const struct rte_flow_item *gre_item = NULL;
4836 const struct rte_flow_action_raw_decap *decap;
4837 const struct rte_flow_action_raw_encap *encap;
4838 const struct rte_flow_action_rss *rss;
4839 const struct rte_flow_item_tcp nic_tcp_mask = {
4842 .src_port = RTE_BE16(UINT16_MAX),
4843 .dst_port = RTE_BE16(UINT16_MAX),
4846 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4848 .src_addr = RTE_BE32(0xffffffff),
4849 .dst_addr = RTE_BE32(0xffffffff),
4850 .type_of_service = 0xff,
4851 .next_proto_id = 0xff,
4852 .time_to_live = 0xff,
4855 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4858 "\xff\xff\xff\xff\xff\xff\xff\xff"
4859 "\xff\xff\xff\xff\xff\xff\xff\xff",
4861 "\xff\xff\xff\xff\xff\xff\xff\xff"
4862 "\xff\xff\xff\xff\xff\xff\xff\xff",
4863 .vtc_flow = RTE_BE32(0xffffffff),
4868 struct mlx5_priv *priv = dev->data->dev_private;
4869 struct mlx5_dev_config *dev_conf = &priv->config;
4870 uint16_t queue_index = 0xFFFF;
4871 const struct rte_flow_item_vlan *vlan_m = NULL;
4872 int16_t rw_act_num = 0;
4877 ret = flow_dv_validate_attributes(dev, attr, external, error);
4880 is_root = (uint64_t)ret;
4881 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4882 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4883 int type = items->type;
4886 case RTE_FLOW_ITEM_TYPE_VOID:
4888 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4889 ret = flow_dv_validate_item_port_id
4890 (dev, items, attr, item_flags, error);
4893 last_item = MLX5_FLOW_ITEM_PORT_ID;
4895 case RTE_FLOW_ITEM_TYPE_ETH:
4896 ret = mlx5_flow_validate_item_eth(items, item_flags,
4900 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4901 MLX5_FLOW_LAYER_OUTER_L2;
4902 if (items->mask != NULL && items->spec != NULL) {
4904 ((const struct rte_flow_item_eth *)
4907 ((const struct rte_flow_item_eth *)
4909 ether_type = rte_be_to_cpu_16(ether_type);
4914 case RTE_FLOW_ITEM_TYPE_VLAN:
4915 ret = flow_dv_validate_item_vlan(items, item_flags,
4919 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4920 MLX5_FLOW_LAYER_OUTER_VLAN;
4921 if (items->mask != NULL && items->spec != NULL) {
4923 ((const struct rte_flow_item_vlan *)
4924 items->spec)->inner_type;
4926 ((const struct rte_flow_item_vlan *)
4927 items->mask)->inner_type;
4928 ether_type = rte_be_to_cpu_16(ether_type);
4932 /* Store outer VLAN mask for of_push_vlan action. */
4934 vlan_m = items->mask;
4936 case RTE_FLOW_ITEM_TYPE_IPV4:
4937 mlx5_flow_tunnel_ip_check(items, next_protocol,
4938 &item_flags, &tunnel);
4939 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4946 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4947 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4948 if (items->mask != NULL &&
4949 ((const struct rte_flow_item_ipv4 *)
4950 items->mask)->hdr.next_proto_id) {
4952 ((const struct rte_flow_item_ipv4 *)
4953 (items->spec))->hdr.next_proto_id;
4955 ((const struct rte_flow_item_ipv4 *)
4956 (items->mask))->hdr.next_proto_id;
4958 /* Reset for inner layer. */
4959 next_protocol = 0xff;
4962 case RTE_FLOW_ITEM_TYPE_IPV6:
4963 mlx5_flow_tunnel_ip_check(items, next_protocol,
4964 &item_flags, &tunnel);
4965 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4972 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4973 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4974 if (items->mask != NULL &&
4975 ((const struct rte_flow_item_ipv6 *)
4976 items->mask)->hdr.proto) {
4978 ((const struct rte_flow_item_ipv6 *)
4979 items->spec)->hdr.proto;
4981 ((const struct rte_flow_item_ipv6 *)
4982 items->spec)->hdr.proto;
4984 ((const struct rte_flow_item_ipv6 *)
4985 items->mask)->hdr.proto;
4987 /* Reset for inner layer. */
4988 next_protocol = 0xff;
4991 case RTE_FLOW_ITEM_TYPE_TCP:
4992 ret = mlx5_flow_validate_item_tcp
4999 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5000 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5002 case RTE_FLOW_ITEM_TYPE_UDP:
5003 ret = mlx5_flow_validate_item_udp(items, item_flags,
5008 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5009 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5011 case RTE_FLOW_ITEM_TYPE_GRE:
5012 ret = mlx5_flow_validate_item_gre(items, item_flags,
5013 next_protocol, error);
5017 last_item = MLX5_FLOW_LAYER_GRE;
5019 case RTE_FLOW_ITEM_TYPE_NVGRE:
5020 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5025 last_item = MLX5_FLOW_LAYER_NVGRE;
5027 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5028 ret = mlx5_flow_validate_item_gre_key
5029 (items, item_flags, gre_item, error);
5032 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5034 case RTE_FLOW_ITEM_TYPE_VXLAN:
5035 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5039 last_item = MLX5_FLOW_LAYER_VXLAN;
5041 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5042 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5047 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5049 case RTE_FLOW_ITEM_TYPE_GENEVE:
5050 ret = mlx5_flow_validate_item_geneve(items,
5055 last_item = MLX5_FLOW_LAYER_GENEVE;
5057 case RTE_FLOW_ITEM_TYPE_MPLS:
5058 ret = mlx5_flow_validate_item_mpls(dev, items,
5063 last_item = MLX5_FLOW_LAYER_MPLS;
5066 case RTE_FLOW_ITEM_TYPE_MARK:
5067 ret = flow_dv_validate_item_mark(dev, items, attr,
5071 last_item = MLX5_FLOW_ITEM_MARK;
5073 case RTE_FLOW_ITEM_TYPE_META:
5074 ret = flow_dv_validate_item_meta(dev, items, attr,
5078 last_item = MLX5_FLOW_ITEM_METADATA;
5080 case RTE_FLOW_ITEM_TYPE_ICMP:
5081 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5086 last_item = MLX5_FLOW_LAYER_ICMP;
5088 case RTE_FLOW_ITEM_TYPE_ICMP6:
5089 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5094 item_ipv6_proto = IPPROTO_ICMPV6;
5095 last_item = MLX5_FLOW_LAYER_ICMP6;
5097 case RTE_FLOW_ITEM_TYPE_TAG:
5098 ret = flow_dv_validate_item_tag(dev, items,
5102 last_item = MLX5_FLOW_ITEM_TAG;
5104 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5105 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5107 case RTE_FLOW_ITEM_TYPE_GTP:
5108 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5112 last_item = MLX5_FLOW_LAYER_GTP;
5115 return rte_flow_error_set(error, ENOTSUP,
5116 RTE_FLOW_ERROR_TYPE_ITEM,
5117 NULL, "item not supported");
5119 item_flags |= last_item;
5121 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5122 int type = actions->type;
5123 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5124 return rte_flow_error_set(error, ENOTSUP,
5125 RTE_FLOW_ERROR_TYPE_ACTION,
5126 actions, "too many actions");
5128 case RTE_FLOW_ACTION_TYPE_VOID:
5130 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5131 ret = flow_dv_validate_action_port_id(dev,
5138 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5141 case RTE_FLOW_ACTION_TYPE_FLAG:
5142 ret = flow_dv_validate_action_flag(dev, action_flags,
5146 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5147 /* Count all modify-header actions as one. */
5148 if (!(action_flags &
5149 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5151 action_flags |= MLX5_FLOW_ACTION_FLAG |
5152 MLX5_FLOW_ACTION_MARK_EXT;
5154 action_flags |= MLX5_FLOW_ACTION_FLAG;
5157 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5159 case RTE_FLOW_ACTION_TYPE_MARK:
5160 ret = flow_dv_validate_action_mark(dev, actions,
5165 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5166 /* Count all modify-header actions as one. */
5167 if (!(action_flags &
5168 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5170 action_flags |= MLX5_FLOW_ACTION_MARK |
5171 MLX5_FLOW_ACTION_MARK_EXT;
5173 action_flags |= MLX5_FLOW_ACTION_MARK;
5176 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5178 case RTE_FLOW_ACTION_TYPE_SET_META:
5179 ret = flow_dv_validate_action_set_meta(dev, actions,
5184 /* Count all modify-header actions as one action. */
5185 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5187 action_flags |= MLX5_FLOW_ACTION_SET_META;
5188 rw_act_num += MLX5_ACT_NUM_SET_META;
5190 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5191 ret = flow_dv_validate_action_set_tag(dev, actions,
5196 /* Count all modify-header actions as one action. */
5197 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5199 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5200 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5202 case RTE_FLOW_ACTION_TYPE_DROP:
5203 ret = mlx5_flow_validate_action_drop(action_flags,
5207 action_flags |= MLX5_FLOW_ACTION_DROP;
5210 case RTE_FLOW_ACTION_TYPE_QUEUE:
5211 ret = mlx5_flow_validate_action_queue(actions,
5216 queue_index = ((const struct rte_flow_action_queue *)
5217 (actions->conf))->index;
5218 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5221 case RTE_FLOW_ACTION_TYPE_RSS:
5222 rss = actions->conf;
5223 ret = mlx5_flow_validate_action_rss(actions,
5229 if (rss != NULL && rss->queue_num)
5230 queue_index = rss->queue[0];
5231 action_flags |= MLX5_FLOW_ACTION_RSS;
5234 case RTE_FLOW_ACTION_TYPE_COUNT:
5235 ret = flow_dv_validate_action_count(dev, error);
5238 action_flags |= MLX5_FLOW_ACTION_COUNT;
5241 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5242 if (flow_dv_validate_action_pop_vlan(dev,
5248 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5251 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5252 ret = flow_dv_validate_action_push_vlan(dev,
5259 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5262 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5263 ret = flow_dv_validate_action_set_vlan_pcp
5264 (action_flags, actions, error);
5267 /* Count PCP with push_vlan command. */
5268 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5270 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5271 ret = flow_dv_validate_action_set_vlan_vid
5272 (item_flags, action_flags,
5276 /* Count VID with push_vlan command. */
5277 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5278 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5280 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5281 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5282 ret = flow_dv_validate_action_l2_encap(dev,
5288 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5291 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5292 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5293 ret = flow_dv_validate_action_decap(dev, action_flags,
5297 action_flags |= MLX5_FLOW_ACTION_DECAP;
5300 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5301 ret = flow_dv_validate_action_raw_encap_decap
5302 (dev, NULL, actions->conf, attr, &action_flags,
5307 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5308 decap = actions->conf;
5309 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5311 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5315 encap = actions->conf;
5317 ret = flow_dv_validate_action_raw_encap_decap
5319 decap ? decap : &empty_decap, encap,
5320 attr, &action_flags, &actions_n,
5325 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5326 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5327 ret = flow_dv_validate_action_modify_mac(action_flags,
5333 /* Count all modify-header actions as one action. */
5334 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5336 action_flags |= actions->type ==
5337 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5338 MLX5_FLOW_ACTION_SET_MAC_SRC :
5339 MLX5_FLOW_ACTION_SET_MAC_DST;
5341 * Even if the source and destination MAC addresses have
5342 * overlap in the header with 4B alignment, the convert
5343 * function will handle them separately and 4 SW actions
5344 * will be created. And 2 actions will be added each
5345 * time no matter how many bytes of address will be set.
5347 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5349 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5350 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5351 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5357 /* Count all modify-header actions as one action. */
5358 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5360 action_flags |= actions->type ==
5361 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5362 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5363 MLX5_FLOW_ACTION_SET_IPV4_DST;
5364 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5366 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5367 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5368 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5374 if (item_ipv6_proto == IPPROTO_ICMPV6)
5375 return rte_flow_error_set(error, ENOTSUP,
5376 RTE_FLOW_ERROR_TYPE_ACTION,
5378 "Can't change header "
5379 "with ICMPv6 proto");
5380 /* Count all modify-header actions as one action. */
5381 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5383 action_flags |= actions->type ==
5384 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5385 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5386 MLX5_FLOW_ACTION_SET_IPV6_DST;
5387 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5389 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5390 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5391 ret = flow_dv_validate_action_modify_tp(action_flags,
5397 /* Count all modify-header actions as one action. */
5398 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5400 action_flags |= actions->type ==
5401 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5402 MLX5_FLOW_ACTION_SET_TP_SRC :
5403 MLX5_FLOW_ACTION_SET_TP_DST;
5404 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5406 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5407 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5408 ret = flow_dv_validate_action_modify_ttl(action_flags,
5414 /* Count all modify-header actions as one action. */
5415 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5417 action_flags |= actions->type ==
5418 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5419 MLX5_FLOW_ACTION_SET_TTL :
5420 MLX5_FLOW_ACTION_DEC_TTL;
5421 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5423 case RTE_FLOW_ACTION_TYPE_JUMP:
5424 ret = flow_dv_validate_action_jump(actions,
5431 action_flags |= MLX5_FLOW_ACTION_JUMP;
5433 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5434 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5435 ret = flow_dv_validate_action_modify_tcp_seq
5442 /* Count all modify-header actions as one action. */
5443 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5445 action_flags |= actions->type ==
5446 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5447 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5448 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5449 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5451 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5452 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5453 ret = flow_dv_validate_action_modify_tcp_ack
5460 /* Count all modify-header actions as one action. */
5461 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5463 action_flags |= actions->type ==
5464 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5465 MLX5_FLOW_ACTION_INC_TCP_ACK :
5466 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5467 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5469 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5471 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5472 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5473 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5475 case RTE_FLOW_ACTION_TYPE_METER:
5476 ret = mlx5_flow_validate_action_meter(dev,
5482 action_flags |= MLX5_FLOW_ACTION_METER;
5484 /* Meter action will add one more TAG action. */
5485 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5487 case RTE_FLOW_ACTION_TYPE_AGE:
5488 ret = flow_dv_validate_action_age(action_flags,
5493 action_flags |= MLX5_FLOW_ACTION_AGE;
5496 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5497 ret = flow_dv_validate_action_modify_ipv4_dscp
5504 /* Count all modify-header actions as one action. */
5505 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5507 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5508 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5510 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5511 ret = flow_dv_validate_action_modify_ipv6_dscp
5518 /* Count all modify-header actions as one action. */
5519 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5521 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5522 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5525 return rte_flow_error_set(error, ENOTSUP,
5526 RTE_FLOW_ERROR_TYPE_ACTION,
5528 "action not supported");
5532 * Validate the drop action mutual exclusion with other actions.
5533 * Drop action is mutually-exclusive with any other action, except for
5536 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5537 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5538 return rte_flow_error_set(error, EINVAL,
5539 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5540 "Drop action is mutually-exclusive "
5541 "with any other action, except for "
5543 /* Eswitch has few restrictions on using items and actions */
5544 if (attr->transfer) {
5545 if (!mlx5_flow_ext_mreg_supported(dev) &&
5546 action_flags & MLX5_FLOW_ACTION_FLAG)
5547 return rte_flow_error_set(error, ENOTSUP,
5548 RTE_FLOW_ERROR_TYPE_ACTION,
5550 "unsupported action FLAG");
5551 if (!mlx5_flow_ext_mreg_supported(dev) &&
5552 action_flags & MLX5_FLOW_ACTION_MARK)
5553 return rte_flow_error_set(error, ENOTSUP,
5554 RTE_FLOW_ERROR_TYPE_ACTION,
5556 "unsupported action MARK");
5557 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5558 return rte_flow_error_set(error, ENOTSUP,
5559 RTE_FLOW_ERROR_TYPE_ACTION,
5561 "unsupported action QUEUE");
5562 if (action_flags & MLX5_FLOW_ACTION_RSS)
5563 return rte_flow_error_set(error, ENOTSUP,
5564 RTE_FLOW_ERROR_TYPE_ACTION,
5566 "unsupported action RSS");
5567 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5568 return rte_flow_error_set(error, EINVAL,
5569 RTE_FLOW_ERROR_TYPE_ACTION,
5571 "no fate action is found");
5573 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5574 return rte_flow_error_set(error, EINVAL,
5575 RTE_FLOW_ERROR_TYPE_ACTION,
5577 "no fate action is found");
5579 /* Continue validation for Xcap actions.*/
5580 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5581 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5582 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5583 MLX5_FLOW_XCAP_ACTIONS)
5584 return rte_flow_error_set(error, ENOTSUP,
5585 RTE_FLOW_ERROR_TYPE_ACTION,
5586 NULL, "encap and decap "
5587 "combination aren't supported");
5588 if (!attr->transfer && attr->ingress && (action_flags &
5589 MLX5_FLOW_ACTION_ENCAP))
5590 return rte_flow_error_set(error, ENOTSUP,
5591 RTE_FLOW_ERROR_TYPE_ACTION,
5592 NULL, "encap is not supported"
5593 " for ingress traffic");
5595 /* Hairpin flow will add one more TAG action. */
5597 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5598 /* extra metadata enabled: one more TAG action will be add. */
5599 if (dev_conf->dv_flow_en &&
5600 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5601 mlx5_flow_ext_mreg_supported(dev))
5602 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5603 if ((uint32_t)rw_act_num >
5604 flow_dv_modify_hdr_action_max(dev, is_root)) {
5605 return rte_flow_error_set(error, ENOTSUP,
5606 RTE_FLOW_ERROR_TYPE_ACTION,
5607 NULL, "too many header modify"
5608 " actions to support");
5614 * Internal preparation function. Allocates the DV flow size,
5615 * this size is constant.
5618 * Pointer to the rte_eth_dev structure.
5620 * Pointer to the flow attributes.
5622 * Pointer to the list of items.
5623 * @param[in] actions
5624 * Pointer to the list of actions.
5626 * Pointer to the error structure.
5629 * Pointer to mlx5_flow object on success,
5630 * otherwise NULL and rte_errno is set.
5632 static struct mlx5_flow *
5633 flow_dv_prepare(struct rte_eth_dev *dev,
5634 const struct rte_flow_attr *attr __rte_unused,
5635 const struct rte_flow_item items[] __rte_unused,
5636 const struct rte_flow_action actions[] __rte_unused,
5637 struct rte_flow_error *error)
5639 uint32_t handle_idx = 0;
5640 struct mlx5_flow *dev_flow;
5641 struct mlx5_flow_handle *dev_handle;
5642 struct mlx5_priv *priv = dev->data->dev_private;
5644 /* In case of corrupting the memory. */
5645 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5646 rte_flow_error_set(error, ENOSPC,
5647 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5648 "not free temporary device flow");
5651 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5654 rte_flow_error_set(error, ENOMEM,
5655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5656 "not enough memory to create flow handle");
5659 /* No multi-thread supporting. */
5660 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5661 dev_flow->handle = dev_handle;
5662 dev_flow->handle_idx = handle_idx;
5663 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5665 * The matching value needs to be cleared to 0 before using. In the
5666 * past, it will be automatically cleared when using rte_*alloc
5667 * API. The time consumption will be almost the same as before.
5669 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5670 dev_flow->ingress = attr->ingress;
5671 dev_flow->dv.transfer = attr->transfer;
5675 #ifdef RTE_LIBRTE_MLX5_DEBUG
5677 * Sanity check for match mask and value. Similar to check_valid_spec() in
5678 * kernel driver. If unmasked bit is present in value, it returns failure.
5681 * pointer to match mask buffer.
5682 * @param match_value
5683 * pointer to match value buffer.
5686 * 0 if valid, -EINVAL otherwise.
5689 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5691 uint8_t *m = match_mask;
5692 uint8_t *v = match_value;
5695 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5698 "match_value differs from match_criteria"
5699 " %p[%u] != %p[%u]",
5700 match_value, i, match_mask, i);
5709 * Add match of ip_version.
5713 * @param[in] headers_v
5714 * Values header pointer.
5715 * @param[in] headers_m
5716 * Masks header pointer.
5717 * @param[in] ip_version
5718 * The IP version to set.
5721 flow_dv_set_match_ip_version(uint32_t group,
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5729 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5737 * Add Ethernet item to matcher and to the value.
5739 * @param[in, out] matcher
5741 * @param[in, out] key
5742 * Flow matcher value.
5744 * Flow pattern to translate.
5746 * Item is inner pattern.
5749 flow_dv_translate_item_eth(void *matcher, void *key,
5750 const struct rte_flow_item *item, int inner,
5753 const struct rte_flow_item_eth *eth_m = item->mask;
5754 const struct rte_flow_item_eth *eth_v = item->spec;
5755 const struct rte_flow_item_eth nic_mask = {
5756 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5757 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5758 .type = RTE_BE16(0xffff),
5770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5772 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5774 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5776 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5778 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5779 ð_m->dst, sizeof(eth_m->dst));
5780 /* The value must be in the range of the mask. */
5781 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5782 for (i = 0; i < sizeof(eth_m->dst); ++i)
5783 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5784 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5785 ð_m->src, sizeof(eth_m->src));
5786 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5787 /* The value must be in the range of the mask. */
5788 for (i = 0; i < sizeof(eth_m->dst); ++i)
5789 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5791 /* When ethertype is present set mask for tagged VLAN. */
5792 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5793 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5794 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5795 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5796 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5798 /* Return here to avoid setting match on ethertype. */
5803 * HW supports match on one Ethertype, the Ethertype following the last
5804 * VLAN tag of the packet (see PRM).
5805 * Set match on ethertype only if ETH header is not followed by VLAN.
5806 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5807 * ethertype, and use ip_version field instead.
5809 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5810 eth_m->type == 0xFFFF) {
5811 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5812 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5813 eth_m->type == 0xFFFF) {
5814 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5816 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5817 rte_be_to_cpu_16(eth_m->type));
5818 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5820 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5825 * Add VLAN item to matcher and to the value.
5827 * @param[in, out] dev_flow
5829 * @param[in, out] matcher
5831 * @param[in, out] key
5832 * Flow matcher value.
5834 * Flow pattern to translate.
5836 * Item is inner pattern.
5839 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5840 void *matcher, void *key,
5841 const struct rte_flow_item *item,
5842 int inner, uint32_t group)
5844 const struct rte_flow_item_vlan *vlan_m = item->mask;
5845 const struct rte_flow_item_vlan *vlan_v = item->spec;
5852 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5854 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5856 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5858 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5860 * This is workaround, masks are not supported,
5861 * and pre-validated.
5864 dev_flow->handle->vf_vlan.tag =
5865 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5868 * When VLAN item exists in flow, mark packet as tagged,
5869 * even if TCI is not specified.
5871 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5872 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5876 vlan_m = &rte_flow_item_vlan_mask;
5877 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5878 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5879 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5881 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5883 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5884 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5886 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5887 * ethertype, and use ip_version field instead.
5889 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5890 vlan_m->inner_type == 0xFFFF) {
5891 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5892 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5893 vlan_m->inner_type == 0xFFFF) {
5894 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5896 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5897 rte_be_to_cpu_16(vlan_m->inner_type));
5898 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5899 rte_be_to_cpu_16(vlan_m->inner_type &
5900 vlan_v->inner_type));
5905 * Add IPV4 item to matcher and to the value.
5907 * @param[in, out] matcher
5909 * @param[in, out] key
5910 * Flow matcher value.
5912 * Flow pattern to translate.
5913 * @param[in] item_flags
5914 * Bit-fields that holds the items detected until now.
5916 * Item is inner pattern.
5918 * The group to insert the rule.
5921 flow_dv_translate_item_ipv4(void *matcher, void *key,
5922 const struct rte_flow_item *item,
5923 const uint64_t item_flags,
5924 int inner, uint32_t group)
5926 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5927 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5928 const struct rte_flow_item_ipv4 nic_mask = {
5930 .src_addr = RTE_BE32(0xffffffff),
5931 .dst_addr = RTE_BE32(0xffffffff),
5932 .type_of_service = 0xff,
5933 .next_proto_id = 0xff,
5934 .time_to_live = 0xff,
5944 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5946 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5948 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5950 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5952 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5954 * On outer header (which must contains L2), or inner header with L2,
5955 * set cvlan_tag mask bit to mark this packet as untagged.
5956 * This should be done even if item->spec is empty.
5958 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5959 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5964 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5965 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5966 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5967 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5968 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5969 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5970 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5971 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5972 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5973 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5974 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5975 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5976 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5977 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5978 ipv4_m->hdr.type_of_service);
5979 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5980 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5981 ipv4_m->hdr.type_of_service >> 2);
5982 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5983 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5984 ipv4_m->hdr.next_proto_id);
5985 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5986 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5987 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5988 ipv4_m->hdr.time_to_live);
5989 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5990 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5994 * Add IPV6 item to matcher and to the value.
5996 * @param[in, out] matcher
5998 * @param[in, out] key
5999 * Flow matcher value.
6001 * Flow pattern to translate.
6002 * @param[in] item_flags
6003 * Bit-fields that holds the items detected until now.
6005 * Item is inner pattern.
6007 * The group to insert the rule.
6010 flow_dv_translate_item_ipv6(void *matcher, void *key,
6011 const struct rte_flow_item *item,
6012 const uint64_t item_flags,
6013 int inner, uint32_t group)
6015 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6016 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6017 const struct rte_flow_item_ipv6 nic_mask = {
6020 "\xff\xff\xff\xff\xff\xff\xff\xff"
6021 "\xff\xff\xff\xff\xff\xff\xff\xff",
6023 "\xff\xff\xff\xff\xff\xff\xff\xff"
6024 "\xff\xff\xff\xff\xff\xff\xff\xff",
6025 .vtc_flow = RTE_BE32(0xffffffff),
6032 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6033 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6042 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6044 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6046 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6048 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6050 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6052 * On outer header (which must contains L2), or inner header with L2,
6053 * set cvlan_tag mask bit to mark this packet as untagged.
6054 * This should be done even if item->spec is empty.
6056 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6057 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6062 size = sizeof(ipv6_m->hdr.dst_addr);
6063 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6064 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6065 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6066 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6067 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6068 for (i = 0; i < size; ++i)
6069 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6070 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6071 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6072 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6073 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6074 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6075 for (i = 0; i < size; ++i)
6076 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6078 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6079 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6080 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6081 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6082 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6083 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6086 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6088 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6091 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6093 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6097 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6099 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6100 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6102 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6103 ipv6_m->hdr.hop_limits);
6104 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6105 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6109 * Add TCP item to matcher and to the value.
6111 * @param[in, out] matcher
6113 * @param[in, out] key
6114 * Flow matcher value.
6116 * Flow pattern to translate.
6118 * Item is inner pattern.
6121 flow_dv_translate_item_tcp(void *matcher, void *key,
6122 const struct rte_flow_item *item,
6125 const struct rte_flow_item_tcp *tcp_m = item->mask;
6126 const struct rte_flow_item_tcp *tcp_v = item->spec;
6131 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6133 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6135 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6137 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6139 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6140 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6144 tcp_m = &rte_flow_item_tcp_mask;
6145 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6146 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6147 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6148 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6149 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6150 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6151 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6152 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6153 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6154 tcp_m->hdr.tcp_flags);
6155 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6156 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6160 * Add UDP item to matcher and to the value.
6162 * @param[in, out] matcher
6164 * @param[in, out] key
6165 * Flow matcher value.
6167 * Flow pattern to translate.
6169 * Item is inner pattern.
6172 flow_dv_translate_item_udp(void *matcher, void *key,
6173 const struct rte_flow_item *item,
6176 const struct rte_flow_item_udp *udp_m = item->mask;
6177 const struct rte_flow_item_udp *udp_v = item->spec;
6182 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6184 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6186 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6188 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6190 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6191 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6195 udp_m = &rte_flow_item_udp_mask;
6196 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6197 rte_be_to_cpu_16(udp_m->hdr.src_port));
6198 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6199 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6200 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6201 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6202 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6203 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6207 * Add GRE optional Key item to matcher and to the value.
6209 * @param[in, out] matcher
6211 * @param[in, out] key
6212 * Flow matcher value.
6214 * Flow pattern to translate.
6216 * Item is inner pattern.
6219 flow_dv_translate_item_gre_key(void *matcher, void *key,
6220 const struct rte_flow_item *item)
6222 const rte_be32_t *key_m = item->mask;
6223 const rte_be32_t *key_v = item->spec;
6224 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6225 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6226 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6228 /* GRE K bit must be on and should already be validated */
6229 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6230 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6234 key_m = &gre_key_default_mask;
6235 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6236 rte_be_to_cpu_32(*key_m) >> 8);
6237 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6238 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6239 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6240 rte_be_to_cpu_32(*key_m) & 0xFF);
6241 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6242 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6246 * Add GRE item to matcher and to the value.
6248 * @param[in, out] matcher
6250 * @param[in, out] key
6251 * Flow matcher value.
6253 * Flow pattern to translate.
6255 * Item is inner pattern.
6258 flow_dv_translate_item_gre(void *matcher, void *key,
6259 const struct rte_flow_item *item,
6262 const struct rte_flow_item_gre *gre_m = item->mask;
6263 const struct rte_flow_item_gre *gre_v = item->spec;
6266 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6267 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6274 uint16_t s_present:1;
6275 uint16_t k_present:1;
6276 uint16_t rsvd_bit1:1;
6277 uint16_t c_present:1;
6281 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6284 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6286 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6288 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6290 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6292 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6293 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6297 gre_m = &rte_flow_item_gre_mask;
6298 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6299 rte_be_to_cpu_16(gre_m->protocol));
6300 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6301 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6302 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6303 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6304 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6305 gre_crks_rsvd0_ver_m.c_present);
6306 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6307 gre_crks_rsvd0_ver_v.c_present &
6308 gre_crks_rsvd0_ver_m.c_present);
6309 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6310 gre_crks_rsvd0_ver_m.k_present);
6311 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6312 gre_crks_rsvd0_ver_v.k_present &
6313 gre_crks_rsvd0_ver_m.k_present);
6314 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6315 gre_crks_rsvd0_ver_m.s_present);
6316 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6317 gre_crks_rsvd0_ver_v.s_present &
6318 gre_crks_rsvd0_ver_m.s_present);
6322 * Add NVGRE item to matcher and to the value.
6324 * @param[in, out] matcher
6326 * @param[in, out] key
6327 * Flow matcher value.
6329 * Flow pattern to translate.
6331 * Item is inner pattern.
6334 flow_dv_translate_item_nvgre(void *matcher, void *key,
6335 const struct rte_flow_item *item,
6338 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6339 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6340 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6341 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6342 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6343 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6349 /* For NVGRE, GRE header fields must be set with defined values. */
6350 const struct rte_flow_item_gre gre_spec = {
6351 .c_rsvd0_ver = RTE_BE16(0x2000),
6352 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6354 const struct rte_flow_item_gre gre_mask = {
6355 .c_rsvd0_ver = RTE_BE16(0xB000),
6356 .protocol = RTE_BE16(UINT16_MAX),
6358 const struct rte_flow_item gre_item = {
6363 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6367 nvgre_m = &rte_flow_item_nvgre_mask;
6368 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6369 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6370 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6371 memcpy(gre_key_m, tni_flow_id_m, size);
6372 for (i = 0; i < size; ++i)
6373 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6377 * Add VXLAN item to matcher and to the value.
6379 * @param[in, out] matcher
6381 * @param[in, out] key
6382 * Flow matcher value.
6384 * Flow pattern to translate.
6386 * Item is inner pattern.
6389 flow_dv_translate_item_vxlan(void *matcher, void *key,
6390 const struct rte_flow_item *item,
6393 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6394 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6397 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6398 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6406 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6408 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6410 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6412 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6414 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6415 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6416 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6417 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6418 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6423 vxlan_m = &rte_flow_item_vxlan_mask;
6424 size = sizeof(vxlan_m->vni);
6425 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6426 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6427 memcpy(vni_m, vxlan_m->vni, size);
6428 for (i = 0; i < size; ++i)
6429 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6433 * Add VXLAN-GPE item to matcher and to the value.
6435 * @param[in, out] matcher
6437 * @param[in, out] key
6438 * Flow matcher value.
6440 * Flow pattern to translate.
6442 * Item is inner pattern.
6446 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6447 const struct rte_flow_item *item, int inner)
6449 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6450 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6454 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6456 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6462 uint8_t flags_m = 0xff;
6463 uint8_t flags_v = 0xc;
6466 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6468 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6470 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6472 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6474 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6475 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6476 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6477 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6478 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6483 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6484 size = sizeof(vxlan_m->vni);
6485 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6486 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6487 memcpy(vni_m, vxlan_m->vni, size);
6488 for (i = 0; i < size; ++i)
6489 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6490 if (vxlan_m->flags) {
6491 flags_m = vxlan_m->flags;
6492 flags_v = vxlan_v->flags;
6494 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6495 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6496 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6498 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6503 * Add Geneve item to matcher and to the value.
6505 * @param[in, out] matcher
6507 * @param[in, out] key
6508 * Flow matcher value.
6510 * Flow pattern to translate.
6512 * Item is inner pattern.
6516 flow_dv_translate_item_geneve(void *matcher, void *key,
6517 const struct rte_flow_item *item, int inner)
6519 const struct rte_flow_item_geneve *geneve_m = item->mask;
6520 const struct rte_flow_item_geneve *geneve_v = item->spec;
6523 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6524 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6533 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6535 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6537 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6539 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6541 dport = MLX5_UDP_PORT_GENEVE;
6542 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6543 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6549 geneve_m = &rte_flow_item_geneve_mask;
6550 size = sizeof(geneve_m->vni);
6551 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6552 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6553 memcpy(vni_m, geneve_m->vni, size);
6554 for (i = 0; i < size; ++i)
6555 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6556 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6557 rte_be_to_cpu_16(geneve_m->protocol));
6558 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6559 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6560 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6561 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6562 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6563 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6564 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6565 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6566 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6567 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6568 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6569 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6570 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6574 * Add MPLS item to matcher and to the value.
6576 * @param[in, out] matcher
6578 * @param[in, out] key
6579 * Flow matcher value.
6581 * Flow pattern to translate.
6582 * @param[in] prev_layer
6583 * The protocol layer indicated in previous item.
6585 * Item is inner pattern.
6588 flow_dv_translate_item_mpls(void *matcher, void *key,
6589 const struct rte_flow_item *item,
6590 uint64_t prev_layer,
6593 const uint32_t *in_mpls_m = item->mask;
6594 const uint32_t *in_mpls_v = item->spec;
6595 uint32_t *out_mpls_m = 0;
6596 uint32_t *out_mpls_v = 0;
6597 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6598 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6599 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6601 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6602 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6603 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6605 switch (prev_layer) {
6606 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6607 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6608 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6609 MLX5_UDP_PORT_MPLS);
6611 case MLX5_FLOW_LAYER_GRE:
6612 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6613 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6614 RTE_ETHER_TYPE_MPLS);
6617 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6618 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6625 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6626 switch (prev_layer) {
6627 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6629 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6630 outer_first_mpls_over_udp);
6632 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6633 outer_first_mpls_over_udp);
6635 case MLX5_FLOW_LAYER_GRE:
6637 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6638 outer_first_mpls_over_gre);
6640 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6641 outer_first_mpls_over_gre);
6644 /* Inner MPLS not over GRE is not supported. */
6647 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6651 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6657 if (out_mpls_m && out_mpls_v) {
6658 *out_mpls_m = *in_mpls_m;
6659 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6664 * Add metadata register item to matcher
6666 * @param[in, out] matcher
6668 * @param[in, out] key
6669 * Flow matcher value.
6670 * @param[in] reg_type
6671 * Type of device metadata register
6678 flow_dv_match_meta_reg(void *matcher, void *key,
6679 enum modify_reg reg_type,
6680 uint32_t data, uint32_t mask)
6683 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6685 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6691 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6692 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6695 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6696 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6700 * The metadata register C0 field might be divided into
6701 * source vport index and META item value, we should set
6702 * this field according to specified mask, not as whole one.
6704 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6706 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6707 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6710 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6713 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6714 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6717 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6718 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6721 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6722 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6725 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6726 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6729 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6730 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6733 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6734 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6737 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6738 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6747 * Add MARK item to matcher
6750 * The device to configure through.
6751 * @param[in, out] matcher
6753 * @param[in, out] key
6754 * Flow matcher value.
6756 * Flow pattern to translate.
6759 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6760 void *matcher, void *key,
6761 const struct rte_flow_item *item)
6763 struct mlx5_priv *priv = dev->data->dev_private;
6764 const struct rte_flow_item_mark *mark;
6768 mark = item->mask ? (const void *)item->mask :
6769 &rte_flow_item_mark_mask;
6770 mask = mark->id & priv->sh->dv_mark_mask;
6771 mark = (const void *)item->spec;
6773 value = mark->id & priv->sh->dv_mark_mask & mask;
6775 enum modify_reg reg;
6777 /* Get the metadata register index for the mark. */
6778 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6779 MLX5_ASSERT(reg > 0);
6780 if (reg == REG_C_0) {
6781 struct mlx5_priv *priv = dev->data->dev_private;
6782 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6783 uint32_t shl_c0 = rte_bsf32(msk_c0);
6789 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6794 * Add META item to matcher
6797 * The devich to configure through.
6798 * @param[in, out] matcher
6800 * @param[in, out] key
6801 * Flow matcher value.
6803 * Attributes of flow that includes this item.
6805 * Flow pattern to translate.
6808 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6809 void *matcher, void *key,
6810 const struct rte_flow_attr *attr,
6811 const struct rte_flow_item *item)
6813 const struct rte_flow_item_meta *meta_m;
6814 const struct rte_flow_item_meta *meta_v;
6816 meta_m = (const void *)item->mask;
6818 meta_m = &rte_flow_item_meta_mask;
6819 meta_v = (const void *)item->spec;
6822 uint32_t value = meta_v->data;
6823 uint32_t mask = meta_m->data;
6825 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6829 * In datapath code there is no endianness
6830 * coversions for perfromance reasons, all
6831 * pattern conversions are done in rte_flow.
6833 value = rte_cpu_to_be_32(value);
6834 mask = rte_cpu_to_be_32(mask);
6835 if (reg == REG_C_0) {
6836 struct mlx5_priv *priv = dev->data->dev_private;
6837 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6838 uint32_t shl_c0 = rte_bsf32(msk_c0);
6839 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6840 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6847 MLX5_ASSERT(msk_c0);
6848 MLX5_ASSERT(!(~msk_c0 & mask));
6850 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6855 * Add vport metadata Reg C0 item to matcher
6857 * @param[in, out] matcher
6859 * @param[in, out] key
6860 * Flow matcher value.
6862 * Flow pattern to translate.
6865 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6866 uint32_t value, uint32_t mask)
6868 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6872 * Add tag item to matcher
6875 * The devich to configure through.
6876 * @param[in, out] matcher
6878 * @param[in, out] key
6879 * Flow matcher value.
6881 * Flow pattern to translate.
6884 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6885 void *matcher, void *key,
6886 const struct rte_flow_item *item)
6888 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6889 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6890 uint32_t mask, value;
6893 value = tag_v->data;
6894 mask = tag_m ? tag_m->data : UINT32_MAX;
6895 if (tag_v->id == REG_C_0) {
6896 struct mlx5_priv *priv = dev->data->dev_private;
6897 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6898 uint32_t shl_c0 = rte_bsf32(msk_c0);
6904 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6908 * Add TAG item to matcher
6911 * The devich to configure through.
6912 * @param[in, out] matcher
6914 * @param[in, out] key
6915 * Flow matcher value.
6917 * Flow pattern to translate.
6920 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6921 void *matcher, void *key,
6922 const struct rte_flow_item *item)
6924 const struct rte_flow_item_tag *tag_v = item->spec;
6925 const struct rte_flow_item_tag *tag_m = item->mask;
6926 enum modify_reg reg;
6929 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6930 /* Get the metadata register index for the tag. */
6931 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6932 MLX5_ASSERT(reg > 0);
6933 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6937 * Add source vport match to the specified matcher.
6939 * @param[in, out] matcher
6941 * @param[in, out] key
6942 * Flow matcher value.
6944 * Source vport value to match
6949 flow_dv_translate_item_source_vport(void *matcher, void *key,
6950 int16_t port, uint16_t mask)
6952 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6953 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6955 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6956 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6960 * Translate port-id item to eswitch match on port-id.
6963 * The devich to configure through.
6964 * @param[in, out] matcher
6966 * @param[in, out] key
6967 * Flow matcher value.
6969 * Flow pattern to translate.
6972 * 0 on success, a negative errno value otherwise.
6975 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6976 void *key, const struct rte_flow_item *item)
6978 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6979 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6980 struct mlx5_priv *priv;
6983 mask = pid_m ? pid_m->id : 0xffff;
6984 id = pid_v ? pid_v->id : dev->data->port_id;
6985 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6988 /* Translate to vport field or to metadata, depending on mode. */
6989 if (priv->vport_meta_mask)
6990 flow_dv_translate_item_meta_vport(matcher, key,
6991 priv->vport_meta_tag,
6992 priv->vport_meta_mask);
6994 flow_dv_translate_item_source_vport(matcher, key,
6995 priv->vport_id, mask);
7000 * Add ICMP6 item to matcher and to the value.
7002 * @param[in, out] matcher
7004 * @param[in, out] key
7005 * Flow matcher value.
7007 * Flow pattern to translate.
7009 * Item is inner pattern.
7012 flow_dv_translate_item_icmp6(void *matcher, void *key,
7013 const struct rte_flow_item *item,
7016 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7017 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7020 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7022 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7024 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7026 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7028 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7030 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7032 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7033 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7037 icmp6_m = &rte_flow_item_icmp6_mask;
7039 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7040 * If only the protocol is specified, no need to match the frag.
7042 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7043 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7044 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7045 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7046 icmp6_v->type & icmp6_m->type);
7047 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7048 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7049 icmp6_v->code & icmp6_m->code);
7053 * Add ICMP item to matcher and to the value.
7055 * @param[in, out] matcher
7057 * @param[in, out] key
7058 * Flow matcher value.
7060 * Flow pattern to translate.
7062 * Item is inner pattern.
7065 flow_dv_translate_item_icmp(void *matcher, void *key,
7066 const struct rte_flow_item *item,
7069 const struct rte_flow_item_icmp *icmp_m = item->mask;
7070 const struct rte_flow_item_icmp *icmp_v = item->spec;
7073 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7075 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7077 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7079 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7081 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7083 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7085 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7086 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7090 icmp_m = &rte_flow_item_icmp_mask;
7092 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7093 * If only the protocol is specified, no need to match the frag.
7095 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7096 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7097 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7098 icmp_m->hdr.icmp_type);
7099 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7100 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7101 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7102 icmp_m->hdr.icmp_code);
7103 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7104 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7108 * Add GTP item to matcher and to the value.
7110 * @param[in, out] matcher
7112 * @param[in, out] key
7113 * Flow matcher value.
7115 * Flow pattern to translate.
7117 * Item is inner pattern.
7120 flow_dv_translate_item_gtp(void *matcher, void *key,
7121 const struct rte_flow_item *item, int inner)
7123 const struct rte_flow_item_gtp *gtp_m = item->mask;
7124 const struct rte_flow_item_gtp *gtp_v = item->spec;
7127 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7129 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7130 uint16_t dport = RTE_GTPU_UDP_PORT;
7133 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7135 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7137 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7139 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7141 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7142 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7143 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7148 gtp_m = &rte_flow_item_gtp_mask;
7149 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7150 gtp_m->v_pt_rsv_flags);
7151 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7152 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7153 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7154 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7155 gtp_v->msg_type & gtp_m->msg_type);
7156 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7157 rte_be_to_cpu_32(gtp_m->teid));
7158 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7159 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7162 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7164 #define HEADER_IS_ZERO(match_criteria, headers) \
7165 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7166 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7169 * Calculate flow matcher enable bitmap.
7171 * @param match_criteria
7172 * Pointer to flow matcher criteria.
7175 * Bitmap of enabled fields.
7178 flow_dv_matcher_enable(uint32_t *match_criteria)
7180 uint8_t match_criteria_enable;
7182 match_criteria_enable =
7183 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7184 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7185 match_criteria_enable |=
7186 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7187 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7188 match_criteria_enable |=
7189 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7190 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7191 match_criteria_enable |=
7192 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7193 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7194 match_criteria_enable |=
7195 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7196 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7197 return match_criteria_enable;
7204 * @param[in, out] dev
7205 * Pointer to rte_eth_dev structure.
7206 * @param[in] table_id
7209 * Direction of the table.
7210 * @param[in] transfer
7211 * E-Switch or NIC flow.
7213 * pointer to error structure.
7216 * Returns tables resource based on the index, NULL in case of failed.
7218 static struct mlx5_flow_tbl_resource *
7219 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7220 uint32_t table_id, uint8_t egress,
7222 struct rte_flow_error *error)
7224 struct mlx5_priv *priv = dev->data->dev_private;
7225 struct mlx5_ibv_shared *sh = priv->sh;
7226 struct mlx5_flow_tbl_resource *tbl;
7227 union mlx5_flow_tbl_key table_key = {
7229 .table_id = table_id,
7231 .domain = !!transfer,
7232 .direction = !!egress,
7235 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7237 struct mlx5_flow_tbl_data_entry *tbl_data;
7243 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7245 tbl = &tbl_data->tbl;
7246 rte_atomic32_inc(&tbl->refcnt);
7249 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7251 rte_flow_error_set(error, ENOMEM,
7252 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7254 "cannot allocate flow table data entry");
7257 tbl_data->idx = idx;
7258 tbl = &tbl_data->tbl;
7259 pos = &tbl_data->entry;
7261 domain = sh->fdb_domain;
7263 domain = sh->tx_domain;
7265 domain = sh->rx_domain;
7266 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7268 rte_flow_error_set(error, ENOMEM,
7269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7270 NULL, "cannot create flow table object");
7271 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7275 * No multi-threads now, but still better to initialize the reference
7276 * count before insert it into the hash list.
7278 rte_atomic32_init(&tbl->refcnt);
7279 /* Jump action reference count is initialized here. */
7280 rte_atomic32_init(&tbl_data->jump.refcnt);
7281 pos->key = table_key.v64;
7282 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7284 rte_flow_error_set(error, -ret,
7285 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7286 "cannot insert flow table data entry");
7287 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7288 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7290 rte_atomic32_inc(&tbl->refcnt);
7295 * Release a flow table.
7298 * Pointer to rte_eth_dev structure.
7300 * Table resource to be released.
7303 * Returns 0 if table was released, else return 1;
7306 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7307 struct mlx5_flow_tbl_resource *tbl)
7309 struct mlx5_priv *priv = dev->data->dev_private;
7310 struct mlx5_ibv_shared *sh = priv->sh;
7311 struct mlx5_flow_tbl_data_entry *tbl_data =
7312 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7316 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7317 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7319 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7321 /* remove the entry from the hash list and free memory. */
7322 mlx5_hlist_remove(sh->flow_tbls, pos);
7323 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7331 * Register the flow matcher.
7333 * @param[in, out] dev
7334 * Pointer to rte_eth_dev structure.
7335 * @param[in, out] matcher
7336 * Pointer to flow matcher.
7337 * @param[in, out] key
7338 * Pointer to flow table key.
7339 * @parm[in, out] dev_flow
7340 * Pointer to the dev_flow.
7342 * pointer to error structure.
7345 * 0 on success otherwise -errno and errno is set.
7348 flow_dv_matcher_register(struct rte_eth_dev *dev,
7349 struct mlx5_flow_dv_matcher *matcher,
7350 union mlx5_flow_tbl_key *key,
7351 struct mlx5_flow *dev_flow,
7352 struct rte_flow_error *error)
7354 struct mlx5_priv *priv = dev->data->dev_private;
7355 struct mlx5_ibv_shared *sh = priv->sh;
7356 struct mlx5_flow_dv_matcher *cache_matcher;
7357 struct mlx5dv_flow_matcher_attr dv_attr = {
7358 .type = IBV_FLOW_ATTR_NORMAL,
7359 .match_mask = (void *)&matcher->mask,
7361 struct mlx5_flow_tbl_resource *tbl;
7362 struct mlx5_flow_tbl_data_entry *tbl_data;
7364 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7365 key->domain, error);
7367 return -rte_errno; /* No need to refill the error info */
7368 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7369 /* Lookup from cache. */
7370 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7371 if (matcher->crc == cache_matcher->crc &&
7372 matcher->priority == cache_matcher->priority &&
7373 !memcmp((const void *)matcher->mask.buf,
7374 (const void *)cache_matcher->mask.buf,
7375 cache_matcher->mask.size)) {
7377 "%s group %u priority %hd use %s "
7378 "matcher %p: refcnt %d++",
7379 key->domain ? "FDB" : "NIC", key->table_id,
7380 cache_matcher->priority,
7381 key->direction ? "tx" : "rx",
7382 (void *)cache_matcher,
7383 rte_atomic32_read(&cache_matcher->refcnt));
7384 rte_atomic32_inc(&cache_matcher->refcnt);
7385 dev_flow->handle->dvh.matcher = cache_matcher;
7386 /* old matcher should not make the table ref++. */
7387 flow_dv_tbl_resource_release(dev, tbl);
7391 /* Register new matcher. */
7392 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7393 if (!cache_matcher) {
7394 flow_dv_tbl_resource_release(dev, tbl);
7395 return rte_flow_error_set(error, ENOMEM,
7396 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7397 "cannot allocate matcher memory");
7399 *cache_matcher = *matcher;
7400 dv_attr.match_criteria_enable =
7401 flow_dv_matcher_enable(cache_matcher->mask.buf);
7402 dv_attr.priority = matcher->priority;
7404 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7405 cache_matcher->matcher_object =
7406 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7407 if (!cache_matcher->matcher_object) {
7408 rte_free(cache_matcher);
7409 #ifdef HAVE_MLX5DV_DR
7410 flow_dv_tbl_resource_release(dev, tbl);
7412 return rte_flow_error_set(error, ENOMEM,
7413 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7414 NULL, "cannot create matcher");
7416 /* Save the table information */
7417 cache_matcher->tbl = tbl;
7418 rte_atomic32_init(&cache_matcher->refcnt);
7419 /* only matcher ref++, table ref++ already done above in get API. */
7420 rte_atomic32_inc(&cache_matcher->refcnt);
7421 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7422 dev_flow->handle->dvh.matcher = cache_matcher;
7423 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7424 key->domain ? "FDB" : "NIC", key->table_id,
7425 cache_matcher->priority,
7426 key->direction ? "tx" : "rx", (void *)cache_matcher,
7427 rte_atomic32_read(&cache_matcher->refcnt));
7432 * Find existing tag resource or create and register a new one.
7434 * @param dev[in, out]
7435 * Pointer to rte_eth_dev structure.
7436 * @param[in, out] tag_be24
7437 * Tag value in big endian then R-shift 8.
7438 * @parm[in, out] dev_flow
7439 * Pointer to the dev_flow.
7441 * pointer to error structure.
7444 * 0 on success otherwise -errno and errno is set.
7447 flow_dv_tag_resource_register
7448 (struct rte_eth_dev *dev,
7450 struct mlx5_flow *dev_flow,
7451 struct rte_flow_error *error)
7453 struct mlx5_priv *priv = dev->data->dev_private;
7454 struct mlx5_ibv_shared *sh = priv->sh;
7455 struct mlx5_flow_dv_tag_resource *cache_resource;
7456 struct mlx5_hlist_entry *entry;
7458 /* Lookup a matching resource from cache. */
7459 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7461 cache_resource = container_of
7462 (entry, struct mlx5_flow_dv_tag_resource, entry);
7463 rte_atomic32_inc(&cache_resource->refcnt);
7464 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7465 dev_flow->dv.tag_resource = cache_resource;
7466 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7467 (void *)cache_resource,
7468 rte_atomic32_read(&cache_resource->refcnt));
7471 /* Register new resource. */
7472 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7473 &dev_flow->handle->dvh.rix_tag);
7474 if (!cache_resource)
7475 return rte_flow_error_set(error, ENOMEM,
7476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7477 "cannot allocate resource memory");
7478 cache_resource->entry.key = (uint64_t)tag_be24;
7479 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7480 if (!cache_resource->action) {
7481 rte_free(cache_resource);
7482 return rte_flow_error_set(error, ENOMEM,
7483 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7484 NULL, "cannot create action");
7486 rte_atomic32_init(&cache_resource->refcnt);
7487 rte_atomic32_inc(&cache_resource->refcnt);
7488 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7489 mlx5_glue->destroy_flow_action(cache_resource->action);
7490 rte_free(cache_resource);
7491 return rte_flow_error_set(error, EEXIST,
7492 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7493 NULL, "cannot insert tag");
7495 dev_flow->dv.tag_resource = cache_resource;
7496 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7497 (void *)cache_resource,
7498 rte_atomic32_read(&cache_resource->refcnt));
7506 * Pointer to Ethernet device.
7511 * 1 while a reference on it exists, 0 when freed.
7514 flow_dv_tag_release(struct rte_eth_dev *dev,
7517 struct mlx5_priv *priv = dev->data->dev_private;
7518 struct mlx5_ibv_shared *sh = priv->sh;
7519 struct mlx5_flow_dv_tag_resource *tag;
7521 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7524 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7525 dev->data->port_id, (void *)tag,
7526 rte_atomic32_read(&tag->refcnt));
7527 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7528 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7529 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7530 DRV_LOG(DEBUG, "port %u tag %p: removed",
7531 dev->data->port_id, (void *)tag);
7532 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7539 * Translate port ID action to vport.
7542 * Pointer to rte_eth_dev structure.
7544 * Pointer to the port ID action.
7545 * @param[out] dst_port_id
7546 * The target port ID.
7548 * Pointer to the error structure.
7551 * 0 on success, a negative errno value otherwise and rte_errno is set.
7554 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7555 const struct rte_flow_action *action,
7556 uint32_t *dst_port_id,
7557 struct rte_flow_error *error)
7560 struct mlx5_priv *priv;
7561 const struct rte_flow_action_port_id *conf =
7562 (const struct rte_flow_action_port_id *)action->conf;
7564 port = conf->original ? dev->data->port_id : conf->id;
7565 priv = mlx5_port_to_eswitch_info(port, false);
7567 return rte_flow_error_set(error, -rte_errno,
7568 RTE_FLOW_ERROR_TYPE_ACTION,
7570 "No eswitch info was found for port");
7571 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7573 * This parameter is transferred to
7574 * mlx5dv_dr_action_create_dest_ib_port().
7576 *dst_port_id = priv->ibv_port;
7579 * Legacy mode, no LAG configurations is supported.
7580 * This parameter is transferred to
7581 * mlx5dv_dr_action_create_dest_vport().
7583 *dst_port_id = priv->vport_id;
7589 * Create a counter with aging configuration.
7592 * Pointer to rte_eth_dev structure.
7594 * Pointer to the counter action configuration.
7596 * Pointer to the aging action configuration.
7599 * Index to flow counter on success, 0 otherwise.
7602 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7603 struct mlx5_flow *dev_flow,
7604 const struct rte_flow_action_count *count,
7605 const struct rte_flow_action_age *age)
7608 struct mlx5_age_param *age_param;
7610 counter = flow_dv_counter_alloc(dev,
7611 count ? count->shared : 0,
7612 count ? count->id : 0,
7613 dev_flow->dv.group, !!age);
7614 if (!counter || age == NULL)
7616 age_param = flow_dv_counter_idx_get_age(dev, counter);
7618 * The counter age accuracy may have a bit delay. Have 3/4
7619 * second bias on the timeount in order to let it age in time.
7621 age_param->context = age->context ? age->context :
7622 (void *)(uintptr_t)(dev_flow->flow_idx);
7624 * The counter age accuracy may have a bit delay. Have 3/4
7625 * second bias on the timeount in order to let it age in time.
7627 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7628 /* Set expire time in unit of 0.1 sec. */
7629 age_param->port_id = dev->data->port_id;
7630 age_param->expire = age_param->timeout +
7631 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7632 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7636 * Add Tx queue matcher
7639 * Pointer to the dev struct.
7640 * @param[in, out] matcher
7642 * @param[in, out] key
7643 * Flow matcher value.
7645 * Flow pattern to translate.
7647 * Item is inner pattern.
7650 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7651 void *matcher, void *key,
7652 const struct rte_flow_item *item)
7654 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7655 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7657 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7659 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7660 struct mlx5_txq_ctrl *txq;
7664 queue_m = (const void *)item->mask;
7667 queue_v = (const void *)item->spec;
7670 txq = mlx5_txq_get(dev, queue_v->queue);
7673 queue = txq->obj->sq->id;
7674 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7675 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7676 queue & queue_m->queue);
7677 mlx5_txq_release(dev, queue_v->queue);
7681 * Set the hash fields according to the @p flow information.
7683 * @param[in] dev_flow
7684 * Pointer to the mlx5_flow.
7685 * @param[in] rss_desc
7686 * Pointer to the mlx5_flow_rss_desc.
7689 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7690 struct mlx5_flow_rss_desc *rss_desc)
7692 uint64_t items = dev_flow->handle->layers;
7694 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7696 dev_flow->hash_fields = 0;
7697 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7698 if (rss_desc->level >= 2) {
7699 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7703 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7704 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7705 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7706 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7707 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7708 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7709 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7711 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7713 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7714 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7715 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7716 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7717 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7718 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7719 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7721 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7724 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7725 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7726 if (rss_types & ETH_RSS_UDP) {
7727 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7728 dev_flow->hash_fields |=
7729 IBV_RX_HASH_SRC_PORT_UDP;
7730 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7731 dev_flow->hash_fields |=
7732 IBV_RX_HASH_DST_PORT_UDP;
7734 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7736 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7737 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7738 if (rss_types & ETH_RSS_TCP) {
7739 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7740 dev_flow->hash_fields |=
7741 IBV_RX_HASH_SRC_PORT_TCP;
7742 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7743 dev_flow->hash_fields |=
7744 IBV_RX_HASH_DST_PORT_TCP;
7746 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7752 * Fill the flow with DV spec, lock free
7753 * (mutex should be acquired by caller).
7756 * Pointer to rte_eth_dev structure.
7757 * @param[in, out] dev_flow
7758 * Pointer to the sub flow.
7760 * Pointer to the flow attributes.
7762 * Pointer to the list of items.
7763 * @param[in] actions
7764 * Pointer to the list of actions.
7766 * Pointer to the error structure.
7769 * 0 on success, a negative errno value otherwise and rte_errno is set.
7772 __flow_dv_translate(struct rte_eth_dev *dev,
7773 struct mlx5_flow *dev_flow,
7774 const struct rte_flow_attr *attr,
7775 const struct rte_flow_item items[],
7776 const struct rte_flow_action actions[],
7777 struct rte_flow_error *error)
7779 struct mlx5_priv *priv = dev->data->dev_private;
7780 struct mlx5_dev_config *dev_conf = &priv->config;
7781 struct rte_flow *flow = dev_flow->flow;
7782 struct mlx5_flow_handle *handle = dev_flow->handle;
7783 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7785 [!!priv->flow_nested_idx];
7786 uint64_t item_flags = 0;
7787 uint64_t last_item = 0;
7788 uint64_t action_flags = 0;
7789 uint64_t priority = attr->priority;
7790 struct mlx5_flow_dv_matcher matcher = {
7792 .size = sizeof(matcher.mask.buf),
7796 bool actions_end = false;
7798 struct mlx5_flow_dv_modify_hdr_resource res;
7799 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7800 sizeof(struct mlx5_modification_cmd) *
7801 (MLX5_MAX_MODIFY_NUM + 1)];
7803 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7804 const struct rte_flow_action_count *count = NULL;
7805 const struct rte_flow_action_age *age = NULL;
7806 union flow_dv_attr flow_attr = { .attr = 0 };
7808 union mlx5_flow_tbl_key tbl_key;
7809 uint32_t modify_action_position = UINT32_MAX;
7810 void *match_mask = matcher.mask.buf;
7811 void *match_value = dev_flow->dv.value.buf;
7812 uint8_t next_protocol = 0xff;
7813 struct rte_vlan_hdr vlan = { 0 };
7817 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7818 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7819 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7820 !!priv->fdb_def_rule, &table, error);
7823 dev_flow->dv.group = table;
7825 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7826 if (priority == MLX5_FLOW_PRIO_RSVD)
7827 priority = dev_conf->flow_prio - 1;
7828 /* number of actions must be set to 0 in case of dirty stack. */
7829 mhdr_res->actions_num = 0;
7830 for (; !actions_end ; actions++) {
7831 const struct rte_flow_action_queue *queue;
7832 const struct rte_flow_action_rss *rss;
7833 const struct rte_flow_action *action = actions;
7834 const uint8_t *rss_key;
7835 const struct rte_flow_action_jump *jump_data;
7836 const struct rte_flow_action_meter *mtr;
7837 struct mlx5_flow_tbl_resource *tbl;
7838 uint32_t port_id = 0;
7839 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7840 int action_type = actions->type;
7841 const struct rte_flow_action *found_action = NULL;
7842 struct mlx5_flow_meter *fm = NULL;
7844 switch (action_type) {
7845 case RTE_FLOW_ACTION_TYPE_VOID:
7847 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7848 if (flow_dv_translate_action_port_id(dev, action,
7851 memset(&port_id_resource, 0, sizeof(port_id_resource));
7852 port_id_resource.port_id = port_id;
7853 if (flow_dv_port_id_action_resource_register
7854 (dev, &port_id_resource, dev_flow, error))
7856 MLX5_ASSERT(!handle->rix_port_id_action);
7857 dev_flow->dv.actions[actions_n++] =
7858 dev_flow->dv.port_id_action->action;
7859 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7860 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7862 case RTE_FLOW_ACTION_TYPE_FLAG:
7863 action_flags |= MLX5_FLOW_ACTION_FLAG;
7864 dev_flow->handle->mark = 1;
7865 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7866 struct rte_flow_action_mark mark = {
7867 .id = MLX5_FLOW_MARK_DEFAULT,
7870 if (flow_dv_convert_action_mark(dev, &mark,
7874 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7877 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7879 * Only one FLAG or MARK is supported per device flow
7880 * right now. So the pointer to the tag resource must be
7881 * zero before the register process.
7883 MLX5_ASSERT(!handle->dvh.rix_tag);
7884 if (flow_dv_tag_resource_register(dev, tag_be,
7887 MLX5_ASSERT(dev_flow->dv.tag_resource);
7888 dev_flow->dv.actions[actions_n++] =
7889 dev_flow->dv.tag_resource->action;
7891 case RTE_FLOW_ACTION_TYPE_MARK:
7892 action_flags |= MLX5_FLOW_ACTION_MARK;
7893 dev_flow->handle->mark = 1;
7894 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7895 const struct rte_flow_action_mark *mark =
7896 (const struct rte_flow_action_mark *)
7899 if (flow_dv_convert_action_mark(dev, mark,
7903 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7907 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7908 /* Legacy (non-extensive) MARK action. */
7909 tag_be = mlx5_flow_mark_set
7910 (((const struct rte_flow_action_mark *)
7911 (actions->conf))->id);
7912 MLX5_ASSERT(!handle->dvh.rix_tag);
7913 if (flow_dv_tag_resource_register(dev, tag_be,
7916 MLX5_ASSERT(dev_flow->dv.tag_resource);
7917 dev_flow->dv.actions[actions_n++] =
7918 dev_flow->dv.tag_resource->action;
7920 case RTE_FLOW_ACTION_TYPE_SET_META:
7921 if (flow_dv_convert_action_set_meta
7922 (dev, mhdr_res, attr,
7923 (const struct rte_flow_action_set_meta *)
7924 actions->conf, error))
7926 action_flags |= MLX5_FLOW_ACTION_SET_META;
7928 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7929 if (flow_dv_convert_action_set_tag
7931 (const struct rte_flow_action_set_tag *)
7932 actions->conf, error))
7934 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7936 case RTE_FLOW_ACTION_TYPE_DROP:
7937 action_flags |= MLX5_FLOW_ACTION_DROP;
7938 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7940 case RTE_FLOW_ACTION_TYPE_QUEUE:
7941 queue = actions->conf;
7942 rss_desc->queue_num = 1;
7943 rss_desc->queue[0] = queue->index;
7944 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7945 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7947 case RTE_FLOW_ACTION_TYPE_RSS:
7948 rss = actions->conf;
7949 memcpy(rss_desc->queue, rss->queue,
7950 rss->queue_num * sizeof(uint16_t));
7951 rss_desc->queue_num = rss->queue_num;
7952 /* NULL RSS key indicates default RSS key. */
7953 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7954 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7956 * rss->level and rss.types should be set in advance
7957 * when expanding items for RSS.
7959 action_flags |= MLX5_FLOW_ACTION_RSS;
7960 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7962 case RTE_FLOW_ACTION_TYPE_AGE:
7963 case RTE_FLOW_ACTION_TYPE_COUNT:
7964 if (!dev_conf->devx) {
7965 return rte_flow_error_set
7967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7969 "count action not supported");
7971 /* Save information first, will apply later. */
7972 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7973 count = action->conf;
7976 action_flags |= MLX5_FLOW_ACTION_COUNT;
7978 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7979 dev_flow->dv.actions[actions_n++] =
7980 priv->sh->pop_vlan_action;
7981 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7983 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7984 if (!(action_flags &
7985 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7986 flow_dev_get_vlan_info_from_items(items, &vlan);
7987 vlan.eth_proto = rte_be_to_cpu_16
7988 ((((const struct rte_flow_action_of_push_vlan *)
7989 actions->conf)->ethertype));
7990 found_action = mlx5_flow_find_action
7992 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7994 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7995 found_action = mlx5_flow_find_action
7997 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7999 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8000 if (flow_dv_create_action_push_vlan
8001 (dev, attr, &vlan, dev_flow, error))
8003 dev_flow->dv.actions[actions_n++] =
8004 dev_flow->dv.push_vlan_res->action;
8005 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8007 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8008 /* of_vlan_push action handled this action */
8009 MLX5_ASSERT(action_flags &
8010 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8012 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8013 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8015 flow_dev_get_vlan_info_from_items(items, &vlan);
8016 mlx5_update_vlan_vid_pcp(actions, &vlan);
8017 /* If no VLAN push - this is a modify header action */
8018 if (flow_dv_convert_action_modify_vlan_vid
8019 (mhdr_res, actions, error))
8021 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8023 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8024 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8025 if (flow_dv_create_action_l2_encap(dev, actions,
8030 dev_flow->dv.actions[actions_n++] =
8031 dev_flow->dv.encap_decap->verbs_action;
8032 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8034 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8035 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8036 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8040 dev_flow->dv.actions[actions_n++] =
8041 dev_flow->dv.encap_decap->verbs_action;
8042 action_flags |= MLX5_FLOW_ACTION_DECAP;
8044 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8045 /* Handle encap with preceding decap. */
8046 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8047 if (flow_dv_create_action_raw_encap
8048 (dev, actions, dev_flow, attr, error))
8050 dev_flow->dv.actions[actions_n++] =
8051 dev_flow->dv.encap_decap->verbs_action;
8053 /* Handle encap without preceding decap. */
8054 if (flow_dv_create_action_l2_encap
8055 (dev, actions, dev_flow, attr->transfer,
8058 dev_flow->dv.actions[actions_n++] =
8059 dev_flow->dv.encap_decap->verbs_action;
8061 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8063 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8064 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8066 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8067 if (flow_dv_create_action_l2_decap
8068 (dev, dev_flow, attr->transfer, error))
8070 dev_flow->dv.actions[actions_n++] =
8071 dev_flow->dv.encap_decap->verbs_action;
8073 /* If decap is followed by encap, handle it at encap. */
8074 action_flags |= MLX5_FLOW_ACTION_DECAP;
8076 case RTE_FLOW_ACTION_TYPE_JUMP:
8077 jump_data = action->conf;
8078 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8080 !!priv->fdb_def_rule,
8084 tbl = flow_dv_tbl_resource_get(dev, table,
8086 attr->transfer, error);
8088 return rte_flow_error_set
8090 RTE_FLOW_ERROR_TYPE_ACTION,
8092 "cannot create jump action.");
8093 if (flow_dv_jump_tbl_resource_register
8094 (dev, tbl, dev_flow, error)) {
8095 flow_dv_tbl_resource_release(dev, tbl);
8096 return rte_flow_error_set
8098 RTE_FLOW_ERROR_TYPE_ACTION,
8100 "cannot create jump action.");
8102 dev_flow->dv.actions[actions_n++] =
8103 dev_flow->dv.jump->action;
8104 action_flags |= MLX5_FLOW_ACTION_JUMP;
8105 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8107 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8108 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8109 if (flow_dv_convert_action_modify_mac
8110 (mhdr_res, actions, error))
8112 action_flags |= actions->type ==
8113 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8114 MLX5_FLOW_ACTION_SET_MAC_SRC :
8115 MLX5_FLOW_ACTION_SET_MAC_DST;
8117 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8118 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8119 if (flow_dv_convert_action_modify_ipv4
8120 (mhdr_res, actions, error))
8122 action_flags |= actions->type ==
8123 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8124 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8125 MLX5_FLOW_ACTION_SET_IPV4_DST;
8127 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8128 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8129 if (flow_dv_convert_action_modify_ipv6
8130 (mhdr_res, actions, error))
8132 action_flags |= actions->type ==
8133 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8134 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8135 MLX5_FLOW_ACTION_SET_IPV6_DST;
8137 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8138 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8139 if (flow_dv_convert_action_modify_tp
8140 (mhdr_res, actions, items,
8141 &flow_attr, dev_flow, !!(action_flags &
8142 MLX5_FLOW_ACTION_DECAP), error))
8144 action_flags |= actions->type ==
8145 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8146 MLX5_FLOW_ACTION_SET_TP_SRC :
8147 MLX5_FLOW_ACTION_SET_TP_DST;
8149 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8150 if (flow_dv_convert_action_modify_dec_ttl
8151 (mhdr_res, items, &flow_attr, dev_flow,
8153 MLX5_FLOW_ACTION_DECAP), error))
8155 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8157 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8158 if (flow_dv_convert_action_modify_ttl
8159 (mhdr_res, actions, items, &flow_attr,
8160 dev_flow, !!(action_flags &
8161 MLX5_FLOW_ACTION_DECAP), error))
8163 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8165 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8166 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8167 if (flow_dv_convert_action_modify_tcp_seq
8168 (mhdr_res, actions, error))
8170 action_flags |= actions->type ==
8171 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8172 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8173 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8176 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8177 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8178 if (flow_dv_convert_action_modify_tcp_ack
8179 (mhdr_res, actions, error))
8181 action_flags |= actions->type ==
8182 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8183 MLX5_FLOW_ACTION_INC_TCP_ACK :
8184 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8186 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8187 if (flow_dv_convert_action_set_reg
8188 (mhdr_res, actions, error))
8190 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8192 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8193 if (flow_dv_convert_action_copy_mreg
8194 (dev, mhdr_res, actions, error))
8196 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8198 case RTE_FLOW_ACTION_TYPE_METER:
8199 mtr = actions->conf;
8201 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8204 return rte_flow_error_set(error,
8206 RTE_FLOW_ERROR_TYPE_ACTION,
8209 "or invalid parameters");
8210 flow->meter = fm->idx;
8212 /* Set the meter action. */
8214 fm = mlx5_ipool_get(priv->sh->ipool
8215 [MLX5_IPOOL_MTR], flow->meter);
8217 return rte_flow_error_set(error,
8219 RTE_FLOW_ERROR_TYPE_ACTION,
8222 "or invalid parameters");
8224 dev_flow->dv.actions[actions_n++] =
8225 fm->mfts->meter_action;
8226 action_flags |= MLX5_FLOW_ACTION_METER;
8228 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8229 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8232 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8234 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8235 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8238 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8240 case RTE_FLOW_ACTION_TYPE_END:
8242 if (mhdr_res->actions_num) {
8243 /* create modify action if needed. */
8244 if (flow_dv_modify_hdr_resource_register
8245 (dev, mhdr_res, dev_flow, error))
8247 dev_flow->dv.actions[modify_action_position] =
8248 handle->dvh.modify_hdr->verbs_action;
8250 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8252 flow_dv_translate_create_counter(dev,
8253 dev_flow, count, age);
8256 return rte_flow_error_set
8258 RTE_FLOW_ERROR_TYPE_ACTION,
8260 "cannot create counter"
8262 dev_flow->dv.actions[actions_n++] =
8263 (flow_dv_counter_get_by_idx(dev,
8264 flow->counter, NULL))->action;
8270 if (mhdr_res->actions_num &&
8271 modify_action_position == UINT32_MAX)
8272 modify_action_position = actions_n++;
8274 dev_flow->dv.actions_n = actions_n;
8275 dev_flow->act_flags = action_flags;
8276 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8277 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8278 int item_type = items->type;
8280 switch (item_type) {
8281 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8282 flow_dv_translate_item_port_id(dev, match_mask,
8283 match_value, items);
8284 last_item = MLX5_FLOW_ITEM_PORT_ID;
8286 case RTE_FLOW_ITEM_TYPE_ETH:
8287 flow_dv_translate_item_eth(match_mask, match_value,
8289 dev_flow->dv.group);
8290 matcher.priority = MLX5_PRIORITY_MAP_L2;
8291 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8292 MLX5_FLOW_LAYER_OUTER_L2;
8294 case RTE_FLOW_ITEM_TYPE_VLAN:
8295 flow_dv_translate_item_vlan(dev_flow,
8296 match_mask, match_value,
8298 dev_flow->dv.group);
8299 matcher.priority = MLX5_PRIORITY_MAP_L2;
8300 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8301 MLX5_FLOW_LAYER_INNER_VLAN) :
8302 (MLX5_FLOW_LAYER_OUTER_L2 |
8303 MLX5_FLOW_LAYER_OUTER_VLAN);
8305 case RTE_FLOW_ITEM_TYPE_IPV4:
8306 mlx5_flow_tunnel_ip_check(items, next_protocol,
8307 &item_flags, &tunnel);
8308 flow_dv_translate_item_ipv4(match_mask, match_value,
8309 items, item_flags, tunnel,
8310 dev_flow->dv.group);
8311 matcher.priority = MLX5_PRIORITY_MAP_L3;
8312 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8313 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8314 if (items->mask != NULL &&
8315 ((const struct rte_flow_item_ipv4 *)
8316 items->mask)->hdr.next_proto_id) {
8318 ((const struct rte_flow_item_ipv4 *)
8319 (items->spec))->hdr.next_proto_id;
8321 ((const struct rte_flow_item_ipv4 *)
8322 (items->mask))->hdr.next_proto_id;
8324 /* Reset for inner layer. */
8325 next_protocol = 0xff;
8328 case RTE_FLOW_ITEM_TYPE_IPV6:
8329 mlx5_flow_tunnel_ip_check(items, next_protocol,
8330 &item_flags, &tunnel);
8331 flow_dv_translate_item_ipv6(match_mask, match_value,
8332 items, item_flags, tunnel,
8333 dev_flow->dv.group);
8334 matcher.priority = MLX5_PRIORITY_MAP_L3;
8335 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8336 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8337 if (items->mask != NULL &&
8338 ((const struct rte_flow_item_ipv6 *)
8339 items->mask)->hdr.proto) {
8341 ((const struct rte_flow_item_ipv6 *)
8342 items->spec)->hdr.proto;
8344 ((const struct rte_flow_item_ipv6 *)
8345 items->mask)->hdr.proto;
8347 /* Reset for inner layer. */
8348 next_protocol = 0xff;
8351 case RTE_FLOW_ITEM_TYPE_TCP:
8352 flow_dv_translate_item_tcp(match_mask, match_value,
8354 matcher.priority = MLX5_PRIORITY_MAP_L4;
8355 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8356 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8358 case RTE_FLOW_ITEM_TYPE_UDP:
8359 flow_dv_translate_item_udp(match_mask, match_value,
8361 matcher.priority = MLX5_PRIORITY_MAP_L4;
8362 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8363 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8365 case RTE_FLOW_ITEM_TYPE_GRE:
8366 flow_dv_translate_item_gre(match_mask, match_value,
8368 matcher.priority = rss_desc->level >= 2 ?
8369 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8370 last_item = MLX5_FLOW_LAYER_GRE;
8372 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8373 flow_dv_translate_item_gre_key(match_mask,
8374 match_value, items);
8375 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8377 case RTE_FLOW_ITEM_TYPE_NVGRE:
8378 flow_dv_translate_item_nvgre(match_mask, match_value,
8380 matcher.priority = rss_desc->level >= 2 ?
8381 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8382 last_item = MLX5_FLOW_LAYER_GRE;
8384 case RTE_FLOW_ITEM_TYPE_VXLAN:
8385 flow_dv_translate_item_vxlan(match_mask, match_value,
8387 matcher.priority = rss_desc->level >= 2 ?
8388 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8389 last_item = MLX5_FLOW_LAYER_VXLAN;
8391 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8392 flow_dv_translate_item_vxlan_gpe(match_mask,
8395 matcher.priority = rss_desc->level >= 2 ?
8396 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8397 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8399 case RTE_FLOW_ITEM_TYPE_GENEVE:
8400 flow_dv_translate_item_geneve(match_mask, match_value,
8402 matcher.priority = rss_desc->level >= 2 ?
8403 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8404 last_item = MLX5_FLOW_LAYER_GENEVE;
8406 case RTE_FLOW_ITEM_TYPE_MPLS:
8407 flow_dv_translate_item_mpls(match_mask, match_value,
8408 items, last_item, tunnel);
8409 matcher.priority = rss_desc->level >= 2 ?
8410 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8411 last_item = MLX5_FLOW_LAYER_MPLS;
8413 case RTE_FLOW_ITEM_TYPE_MARK:
8414 flow_dv_translate_item_mark(dev, match_mask,
8415 match_value, items);
8416 last_item = MLX5_FLOW_ITEM_MARK;
8418 case RTE_FLOW_ITEM_TYPE_META:
8419 flow_dv_translate_item_meta(dev, match_mask,
8420 match_value, attr, items);
8421 last_item = MLX5_FLOW_ITEM_METADATA;
8423 case RTE_FLOW_ITEM_TYPE_ICMP:
8424 flow_dv_translate_item_icmp(match_mask, match_value,
8426 last_item = MLX5_FLOW_LAYER_ICMP;
8428 case RTE_FLOW_ITEM_TYPE_ICMP6:
8429 flow_dv_translate_item_icmp6(match_mask, match_value,
8431 last_item = MLX5_FLOW_LAYER_ICMP6;
8433 case RTE_FLOW_ITEM_TYPE_TAG:
8434 flow_dv_translate_item_tag(dev, match_mask,
8435 match_value, items);
8436 last_item = MLX5_FLOW_ITEM_TAG;
8438 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8439 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8440 match_value, items);
8441 last_item = MLX5_FLOW_ITEM_TAG;
8443 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8444 flow_dv_translate_item_tx_queue(dev, match_mask,
8447 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8449 case RTE_FLOW_ITEM_TYPE_GTP:
8450 flow_dv_translate_item_gtp(match_mask, match_value,
8452 matcher.priority = rss_desc->level >= 2 ?
8453 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8454 last_item = MLX5_FLOW_LAYER_GTP;
8459 item_flags |= last_item;
8462 * When E-Switch mode is enabled, we have two cases where we need to
8463 * set the source port manually.
8464 * The first one, is in case of Nic steering rule, and the second is
8465 * E-Switch rule where no port_id item was found. In both cases
8466 * the source port is set according the current port in use.
8468 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8469 (priv->representor || priv->master)) {
8470 if (flow_dv_translate_item_port_id(dev, match_mask,
8474 #ifdef RTE_LIBRTE_MLX5_DEBUG
8475 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8476 dev_flow->dv.value.buf));
8479 * Layers may be already initialized from prefix flow if this dev_flow
8480 * is the suffix flow.
8482 handle->layers |= item_flags;
8483 if (action_flags & MLX5_FLOW_ACTION_RSS)
8484 flow_dv_hashfields_set(dev_flow, rss_desc);
8485 /* Register matcher. */
8486 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8488 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8490 /* reserved field no needs to be set to 0 here. */
8491 tbl_key.domain = attr->transfer;
8492 tbl_key.direction = attr->egress;
8493 tbl_key.table_id = dev_flow->dv.group;
8494 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8500 * Apply the flow to the NIC, lock free,
8501 * (mutex should be acquired by caller).
8504 * Pointer to the Ethernet device structure.
8505 * @param[in, out] flow
8506 * Pointer to flow structure.
8508 * Pointer to error structure.
8511 * 0 on success, a negative errno value otherwise and rte_errno is set.
8514 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8515 struct rte_flow_error *error)
8517 struct mlx5_flow_dv_workspace *dv;
8518 struct mlx5_flow_handle *dh;
8519 struct mlx5_flow_handle_dv *dv_h;
8520 struct mlx5_flow *dev_flow;
8521 struct mlx5_priv *priv = dev->data->dev_private;
8522 uint32_t handle_idx;
8527 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8528 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8530 dh = dev_flow->handle;
8533 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8535 dv->actions[n++] = priv->sh->esw_drop_action;
8537 struct mlx5_hrxq *drop_hrxq;
8538 drop_hrxq = mlx5_hrxq_drop_new(dev);
8542 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8544 "cannot get drop hash queue");
8548 * Drop queues will be released by the specify
8549 * mlx5_hrxq_drop_release() function. Assign
8550 * the special index to hrxq to mark the queue
8551 * has been allocated.
8553 dh->rix_hrxq = UINT32_MAX;
8554 dv->actions[n++] = drop_hrxq->action;
8556 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8557 struct mlx5_hrxq *hrxq;
8559 struct mlx5_flow_rss_desc *rss_desc =
8560 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8561 [!!priv->flow_nested_idx];
8563 MLX5_ASSERT(rss_desc->queue_num);
8564 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8565 MLX5_RSS_HASH_KEY_LEN,
8566 dev_flow->hash_fields,
8568 rss_desc->queue_num);
8570 hrxq_idx = mlx5_hrxq_new
8571 (dev, rss_desc->key,
8572 MLX5_RSS_HASH_KEY_LEN,
8573 dev_flow->hash_fields,
8575 rss_desc->queue_num,
8577 MLX5_FLOW_LAYER_TUNNEL));
8579 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8585 "cannot get hash queue");
8588 dh->rix_hrxq = hrxq_idx;
8589 dv->actions[n++] = hrxq->action;
8592 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8593 (void *)&dv->value, n,
8596 rte_flow_error_set(error, errno,
8597 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8599 "hardware refuses to create flow");
8602 if (priv->vmwa_context &&
8603 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8605 * The rule contains the VLAN pattern.
8606 * For VF we are going to create VLAN
8607 * interface to make hypervisor set correct
8608 * e-Switch vport context.
8610 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8615 err = rte_errno; /* Save rte_errno before cleanup. */
8616 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8617 handle_idx, dh, next) {
8618 /* hrxq is union, don't clear it if the flag is not set. */
8620 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8621 mlx5_hrxq_drop_release(dev);
8623 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8624 mlx5_hrxq_release(dev, dh->rix_hrxq);
8628 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8629 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8631 rte_errno = err; /* Restore rte_errno. */
8636 * Release the flow matcher.
8639 * Pointer to Ethernet device.
8641 * Pointer to mlx5_flow_handle.
8644 * 1 while a reference on it exists, 0 when freed.
8647 flow_dv_matcher_release(struct rte_eth_dev *dev,
8648 struct mlx5_flow_handle *handle)
8650 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8652 MLX5_ASSERT(matcher->matcher_object);
8653 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8654 dev->data->port_id, (void *)matcher,
8655 rte_atomic32_read(&matcher->refcnt));
8656 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8657 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8658 (matcher->matcher_object));
8659 LIST_REMOVE(matcher, next);
8660 /* table ref-- in release interface. */
8661 flow_dv_tbl_resource_release(dev, matcher->tbl);
8663 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8664 dev->data->port_id, (void *)matcher);
8671 * Release an encap/decap resource.
8674 * Pointer to Ethernet device.
8676 * Pointer to mlx5_flow_handle.
8679 * 1 while a reference on it exists, 0 when freed.
8682 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8683 struct mlx5_flow_handle *handle)
8685 struct mlx5_priv *priv = dev->data->dev_private;
8686 uint32_t idx = handle->dvh.rix_encap_decap;
8687 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8689 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8691 if (!cache_resource)
8693 MLX5_ASSERT(cache_resource->verbs_action);
8694 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8695 (void *)cache_resource,
8696 rte_atomic32_read(&cache_resource->refcnt));
8697 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8698 claim_zero(mlx5_glue->destroy_flow_action
8699 (cache_resource->verbs_action));
8700 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8701 &priv->sh->encaps_decaps, idx,
8702 cache_resource, next);
8703 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8704 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8705 (void *)cache_resource);
8712 * Release an jump to table action resource.
8715 * Pointer to Ethernet device.
8717 * Pointer to mlx5_flow_handle.
8720 * 1 while a reference on it exists, 0 when freed.
8723 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8724 struct mlx5_flow_handle *handle)
8726 struct mlx5_priv *priv = dev->data->dev_private;
8727 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8728 struct mlx5_flow_tbl_data_entry *tbl_data;
8730 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8734 cache_resource = &tbl_data->jump;
8735 MLX5_ASSERT(cache_resource->action);
8736 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8737 (void *)cache_resource,
8738 rte_atomic32_read(&cache_resource->refcnt));
8739 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8740 claim_zero(mlx5_glue->destroy_flow_action
8741 (cache_resource->action));
8742 /* jump action memory free is inside the table release. */
8743 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8744 DRV_LOG(DEBUG, "jump table resource %p: removed",
8745 (void *)cache_resource);
8752 * Release a modify-header resource.
8755 * Pointer to mlx5_flow_handle.
8758 * 1 while a reference on it exists, 0 when freed.
8761 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8763 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8764 handle->dvh.modify_hdr;
8766 MLX5_ASSERT(cache_resource->verbs_action);
8767 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8768 (void *)cache_resource,
8769 rte_atomic32_read(&cache_resource->refcnt));
8770 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8771 claim_zero(mlx5_glue->destroy_flow_action
8772 (cache_resource->verbs_action));
8773 LIST_REMOVE(cache_resource, next);
8774 rte_free(cache_resource);
8775 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8776 (void *)cache_resource);
8783 * Release port ID action resource.
8786 * Pointer to Ethernet device.
8788 * Pointer to mlx5_flow_handle.
8791 * 1 while a reference on it exists, 0 when freed.
8794 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8795 struct mlx5_flow_handle *handle)
8797 struct mlx5_priv *priv = dev->data->dev_private;
8798 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8799 uint32_t idx = handle->rix_port_id_action;
8801 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8803 if (!cache_resource)
8805 MLX5_ASSERT(cache_resource->action);
8806 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8807 (void *)cache_resource,
8808 rte_atomic32_read(&cache_resource->refcnt));
8809 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8810 claim_zero(mlx5_glue->destroy_flow_action
8811 (cache_resource->action));
8812 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8813 &priv->sh->port_id_action_list, idx,
8814 cache_resource, next);
8815 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8816 DRV_LOG(DEBUG, "port id action resource %p: removed",
8817 (void *)cache_resource);
8824 * Release push vlan action resource.
8827 * Pointer to Ethernet device.
8829 * Pointer to mlx5_flow_handle.
8832 * 1 while a reference on it exists, 0 when freed.
8835 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8836 struct mlx5_flow_handle *handle)
8838 struct mlx5_priv *priv = dev->data->dev_private;
8839 uint32_t idx = handle->dvh.rix_push_vlan;
8840 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8842 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8844 if (!cache_resource)
8846 MLX5_ASSERT(cache_resource->action);
8847 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8848 (void *)cache_resource,
8849 rte_atomic32_read(&cache_resource->refcnt));
8850 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8851 claim_zero(mlx5_glue->destroy_flow_action
8852 (cache_resource->action));
8853 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8854 &priv->sh->push_vlan_action_list, idx,
8855 cache_resource, next);
8856 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8857 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8858 (void *)cache_resource);
8865 * Release the fate resource.
8868 * Pointer to Ethernet device.
8870 * Pointer to mlx5_flow_handle.
8873 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8874 struct mlx5_flow_handle *handle)
8876 if (!handle->rix_fate)
8878 if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8879 mlx5_hrxq_drop_release(dev);
8880 else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8881 mlx5_hrxq_release(dev, handle->rix_hrxq);
8882 else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8883 flow_dv_jump_tbl_resource_release(dev, handle);
8884 else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8885 flow_dv_port_id_action_resource_release(dev, handle);
8887 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8888 handle->rix_fate = 0;
8892 * Remove the flow from the NIC but keeps it in memory.
8893 * Lock free, (mutex should be acquired by caller).
8896 * Pointer to Ethernet device.
8897 * @param[in, out] flow
8898 * Pointer to flow structure.
8901 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8903 struct mlx5_flow_handle *dh;
8904 uint32_t handle_idx;
8905 struct mlx5_priv *priv = dev->data->dev_private;
8909 handle_idx = flow->dev_handles;
8910 while (handle_idx) {
8911 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8916 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8919 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8920 dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8921 flow_dv_fate_resource_release(dev, dh);
8922 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8923 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8924 handle_idx = dh->next.next;
8929 * Remove the flow from the NIC and the memory.
8930 * Lock free, (mutex should be acquired by caller).
8933 * Pointer to the Ethernet device structure.
8934 * @param[in, out] flow
8935 * Pointer to flow structure.
8938 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8940 struct mlx5_flow_handle *dev_handle;
8941 struct mlx5_priv *priv = dev->data->dev_private;
8945 __flow_dv_remove(dev, flow);
8946 if (flow->counter) {
8947 flow_dv_counter_release(dev, flow->counter);
8951 struct mlx5_flow_meter *fm;
8953 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8956 mlx5_flow_meter_detach(fm);
8959 while (flow->dev_handles) {
8960 uint32_t tmp_idx = flow->dev_handles;
8962 dev_handle = mlx5_ipool_get(priv->sh->ipool
8963 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8966 flow->dev_handles = dev_handle->next.next;
8967 if (dev_handle->dvh.matcher)
8968 flow_dv_matcher_release(dev, dev_handle);
8969 if (dev_handle->dvh.rix_encap_decap)
8970 flow_dv_encap_decap_resource_release(dev, dev_handle);
8971 if (dev_handle->dvh.modify_hdr)
8972 flow_dv_modify_hdr_resource_release(dev_handle);
8973 if (dev_handle->dvh.rix_push_vlan)
8974 flow_dv_push_vlan_action_resource_release(dev,
8976 if (dev_handle->dvh.rix_tag)
8977 flow_dv_tag_release(dev,
8978 dev_handle->dvh.rix_tag);
8979 flow_dv_fate_resource_release(dev, dev_handle);
8980 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8986 * Query a dv flow rule for its statistics via devx.
8989 * Pointer to Ethernet device.
8991 * Pointer to the sub flow.
8993 * data retrieved by the query.
8995 * Perform verbose error reporting if not NULL.
8998 * 0 on success, a negative errno value otherwise and rte_errno is set.
9001 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9002 void *data, struct rte_flow_error *error)
9004 struct mlx5_priv *priv = dev->data->dev_private;
9005 struct rte_flow_query_count *qc = data;
9007 if (!priv->config.devx)
9008 return rte_flow_error_set(error, ENOTSUP,
9009 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9011 "counters are not supported");
9012 if (flow->counter) {
9013 uint64_t pkts, bytes;
9014 struct mlx5_flow_counter *cnt;
9016 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9018 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9022 return rte_flow_error_set(error, -err,
9023 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9024 NULL, "cannot read counters");
9027 qc->hits = pkts - cnt->hits;
9028 qc->bytes = bytes - cnt->bytes;
9035 return rte_flow_error_set(error, EINVAL,
9036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9038 "counters are not available");
9044 * @see rte_flow_query()
9048 flow_dv_query(struct rte_eth_dev *dev,
9049 struct rte_flow *flow __rte_unused,
9050 const struct rte_flow_action *actions __rte_unused,
9051 void *data __rte_unused,
9052 struct rte_flow_error *error __rte_unused)
9056 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9057 switch (actions->type) {
9058 case RTE_FLOW_ACTION_TYPE_VOID:
9060 case RTE_FLOW_ACTION_TYPE_COUNT:
9061 ret = flow_dv_query_count(dev, flow, data, error);
9064 return rte_flow_error_set(error, ENOTSUP,
9065 RTE_FLOW_ERROR_TYPE_ACTION,
9067 "action not supported");
9074 * Destroy the meter table set.
9075 * Lock free, (mutex should be acquired by caller).
9078 * Pointer to Ethernet device.
9080 * Pointer to the meter table set.
9086 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9087 struct mlx5_meter_domains_infos *tbl)
9089 struct mlx5_priv *priv = dev->data->dev_private;
9090 struct mlx5_meter_domains_infos *mtd =
9091 (struct mlx5_meter_domains_infos *)tbl;
9093 if (!mtd || !priv->config.dv_flow_en)
9095 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9096 claim_zero(mlx5_glue->dv_destroy_flow
9097 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9098 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9099 claim_zero(mlx5_glue->dv_destroy_flow
9100 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9101 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9102 claim_zero(mlx5_glue->dv_destroy_flow
9103 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9104 if (mtd->egress.color_matcher)
9105 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9106 (mtd->egress.color_matcher));
9107 if (mtd->egress.any_matcher)
9108 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9109 (mtd->egress.any_matcher));
9110 if (mtd->egress.tbl)
9111 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9112 if (mtd->egress.sfx_tbl)
9113 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9114 if (mtd->ingress.color_matcher)
9115 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9116 (mtd->ingress.color_matcher));
9117 if (mtd->ingress.any_matcher)
9118 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9119 (mtd->ingress.any_matcher));
9120 if (mtd->ingress.tbl)
9121 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9122 if (mtd->ingress.sfx_tbl)
9123 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9124 if (mtd->transfer.color_matcher)
9125 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9126 (mtd->transfer.color_matcher));
9127 if (mtd->transfer.any_matcher)
9128 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9129 (mtd->transfer.any_matcher));
9130 if (mtd->transfer.tbl)
9131 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9132 if (mtd->transfer.sfx_tbl)
9133 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9135 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9140 /* Number of meter flow actions, count and jump or count and drop. */
9141 #define METER_ACTIONS 2
9144 * Create specify domain meter table and suffix table.
9147 * Pointer to Ethernet device.
9148 * @param[in,out] mtb
9149 * Pointer to DV meter table set.
9152 * @param[in] transfer
9154 * @param[in] color_reg_c_idx
9155 * Reg C index for color match.
9158 * 0 on success, -1 otherwise and rte_errno is set.
9161 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9162 struct mlx5_meter_domains_infos *mtb,
9163 uint8_t egress, uint8_t transfer,
9164 uint32_t color_reg_c_idx)
9166 struct mlx5_priv *priv = dev->data->dev_private;
9167 struct mlx5_ibv_shared *sh = priv->sh;
9168 struct mlx5_flow_dv_match_params mask = {
9169 .size = sizeof(mask.buf),
9171 struct mlx5_flow_dv_match_params value = {
9172 .size = sizeof(value.buf),
9174 struct mlx5dv_flow_matcher_attr dv_attr = {
9175 .type = IBV_FLOW_ATTR_NORMAL,
9177 .match_criteria_enable = 0,
9178 .match_mask = (void *)&mask,
9180 void *actions[METER_ACTIONS];
9181 struct mlx5_meter_domain_info *dtb;
9182 struct rte_flow_error error;
9186 dtb = &mtb->transfer;
9190 dtb = &mtb->ingress;
9191 /* Create the meter table with METER level. */
9192 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9193 egress, transfer, &error);
9195 DRV_LOG(ERR, "Failed to create meter policer table.");
9198 /* Create the meter suffix table with SUFFIX level. */
9199 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9200 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9201 egress, transfer, &error);
9202 if (!dtb->sfx_tbl) {
9203 DRV_LOG(ERR, "Failed to create meter suffix table.");
9206 /* Create matchers, Any and Color. */
9207 dv_attr.priority = 3;
9208 dv_attr.match_criteria_enable = 0;
9209 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9212 if (!dtb->any_matcher) {
9213 DRV_LOG(ERR, "Failed to create meter"
9214 " policer default matcher.");
9217 dv_attr.priority = 0;
9218 dv_attr.match_criteria_enable =
9219 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9220 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9221 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9222 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9225 if (!dtb->color_matcher) {
9226 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9229 if (mtb->count_actns[RTE_MTR_DROPPED])
9230 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9231 actions[i++] = mtb->drop_actn;
9232 /* Default rule: lowest priority, match any, actions: drop. */
9233 dtb->policer_rules[RTE_MTR_DROPPED] =
9234 mlx5_glue->dv_create_flow(dtb->any_matcher,
9235 (void *)&value, i, actions);
9236 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9237 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9246 * Create the needed meter and suffix tables.
9247 * Lock free, (mutex should be acquired by caller).
9250 * Pointer to Ethernet device.
9252 * Pointer to the flow meter.
9255 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9257 static struct mlx5_meter_domains_infos *
9258 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9259 const struct mlx5_flow_meter *fm)
9261 struct mlx5_priv *priv = dev->data->dev_private;
9262 struct mlx5_meter_domains_infos *mtb;
9266 if (!priv->mtr_en) {
9267 rte_errno = ENOTSUP;
9270 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9272 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9275 /* Create meter count actions */
9276 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9277 struct mlx5_flow_counter *cnt;
9278 if (!fm->policer_stats.cnt[i])
9280 cnt = flow_dv_counter_get_by_idx(dev,
9281 fm->policer_stats.cnt[i], NULL);
9282 mtb->count_actns[i] = cnt->action;
9284 /* Create drop action. */
9285 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9286 if (!mtb->drop_actn) {
9287 DRV_LOG(ERR, "Failed to create drop action.");
9290 /* Egress meter table. */
9291 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9293 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9296 /* Ingress meter table. */
9297 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9299 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9302 /* FDB meter table. */
9303 if (priv->config.dv_esw_en) {
9304 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9305 priv->mtr_color_reg);
9307 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9313 flow_dv_destroy_mtr_tbl(dev, mtb);
9318 * Destroy domain policer rule.
9321 * Pointer to domain table.
9324 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9328 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9329 if (dt->policer_rules[i]) {
9330 claim_zero(mlx5_glue->dv_destroy_flow
9331 (dt->policer_rules[i]));
9332 dt->policer_rules[i] = NULL;
9335 if (dt->jump_actn) {
9336 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9337 dt->jump_actn = NULL;
9342 * Destroy policer rules.
9345 * Pointer to Ethernet device.
9347 * Pointer to flow meter structure.
9349 * Pointer to flow attributes.
9355 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9356 const struct mlx5_flow_meter *fm,
9357 const struct rte_flow_attr *attr)
9359 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9364 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9366 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9368 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9373 * Create specify domain meter policer rule.
9376 * Pointer to flow meter structure.
9378 * Pointer to DV meter table set.
9379 * @param[in] mtr_reg_c
9380 * Color match REG_C.
9383 * 0 on success, -1 otherwise.
9386 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9387 struct mlx5_meter_domain_info *dtb,
9390 struct mlx5_flow_dv_match_params matcher = {
9391 .size = sizeof(matcher.buf),
9393 struct mlx5_flow_dv_match_params value = {
9394 .size = sizeof(value.buf),
9396 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9397 void *actions[METER_ACTIONS];
9400 /* Create jump action. */
9401 if (!dtb->jump_actn)
9403 mlx5_glue->dr_create_flow_action_dest_flow_tbl
9404 (dtb->sfx_tbl->obj);
9405 if (!dtb->jump_actn) {
9406 DRV_LOG(ERR, "Failed to create policer jump action.");
9409 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9412 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9413 rte_col_2_mlx5_col(i), UINT8_MAX);
9414 if (mtb->count_actns[i])
9415 actions[j++] = mtb->count_actns[i];
9416 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9417 actions[j++] = mtb->drop_actn;
9419 actions[j++] = dtb->jump_actn;
9420 dtb->policer_rules[i] =
9421 mlx5_glue->dv_create_flow(dtb->color_matcher,
9424 if (!dtb->policer_rules[i]) {
9425 DRV_LOG(ERR, "Failed to create policer rule.");
9436 * Create policer rules.
9439 * Pointer to Ethernet device.
9441 * Pointer to flow meter structure.
9443 * Pointer to flow attributes.
9446 * 0 on success, -1 otherwise.
9449 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9450 struct mlx5_flow_meter *fm,
9451 const struct rte_flow_attr *attr)
9453 struct mlx5_priv *priv = dev->data->dev_private;
9454 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9458 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9459 priv->mtr_color_reg);
9461 DRV_LOG(ERR, "Failed to create egress policer.");
9465 if (attr->ingress) {
9466 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9467 priv->mtr_color_reg);
9469 DRV_LOG(ERR, "Failed to create ingress policer.");
9473 if (attr->transfer) {
9474 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9475 priv->mtr_color_reg);
9477 DRV_LOG(ERR, "Failed to create transfer policer.");
9483 flow_dv_destroy_policer_rules(dev, fm, attr);
9488 * Query a devx counter.
9491 * Pointer to the Ethernet device structure.
9493 * Index to the flow counter.
9495 * Set to clear the counter statistics.
9497 * The statistics value of packets.
9499 * The statistics value of bytes.
9502 * 0 on success, otherwise return -1.
9505 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9506 uint64_t *pkts, uint64_t *bytes)
9508 struct mlx5_priv *priv = dev->data->dev_private;
9509 struct mlx5_flow_counter *cnt;
9510 uint64_t inn_pkts, inn_bytes;
9513 if (!priv->config.devx)
9516 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9519 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9520 *pkts = inn_pkts - cnt->hits;
9521 *bytes = inn_bytes - cnt->bytes;
9523 cnt->hits = inn_pkts;
9524 cnt->bytes = inn_bytes;
9530 * Get aged-out flows.
9533 * Pointer to the Ethernet device structure.
9534 * @param[in] context
9535 * The address of an array of pointers to the aged-out flows contexts.
9536 * @param[in] nb_contexts
9537 * The length of context array pointers.
9539 * Perform verbose error reporting if not NULL. Initialized in case of
9543 * how many contexts get in success, otherwise negative errno value.
9544 * if nb_contexts is 0, return the amount of all aged contexts.
9545 * if nb_contexts is not 0 , return the amount of aged flows reported
9546 * in the context array.
9547 * @note: only stub for now
9550 flow_get_aged_flows(struct rte_eth_dev *dev,
9552 uint32_t nb_contexts,
9553 struct rte_flow_error *error)
9555 struct mlx5_priv *priv = dev->data->dev_private;
9556 struct mlx5_age_info *age_info;
9557 struct mlx5_age_param *age_param;
9558 struct mlx5_flow_counter *counter;
9561 if (nb_contexts && !context)
9562 return rte_flow_error_set(error, EINVAL,
9563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9565 "Should assign at least one flow or"
9566 " context to get if nb_contexts != 0");
9567 age_info = GET_PORT_AGE_INFO(priv);
9568 rte_spinlock_lock(&age_info->aged_sl);
9569 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9572 age_param = MLX5_CNT_TO_AGE(counter);
9573 context[nb_flows - 1] = age_param->context;
9574 if (!(--nb_contexts))
9578 rte_spinlock_unlock(&age_info->aged_sl);
9579 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9584 * Mutex-protected thunk to lock-free __flow_dv_translate().
9587 flow_dv_translate(struct rte_eth_dev *dev,
9588 struct mlx5_flow *dev_flow,
9589 const struct rte_flow_attr *attr,
9590 const struct rte_flow_item items[],
9591 const struct rte_flow_action actions[],
9592 struct rte_flow_error *error)
9596 flow_dv_shared_lock(dev);
9597 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9598 flow_dv_shared_unlock(dev);
9603 * Mutex-protected thunk to lock-free __flow_dv_apply().
9606 flow_dv_apply(struct rte_eth_dev *dev,
9607 struct rte_flow *flow,
9608 struct rte_flow_error *error)
9612 flow_dv_shared_lock(dev);
9613 ret = __flow_dv_apply(dev, flow, error);
9614 flow_dv_shared_unlock(dev);
9619 * Mutex-protected thunk to lock-free __flow_dv_remove().
9622 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9624 flow_dv_shared_lock(dev);
9625 __flow_dv_remove(dev, flow);
9626 flow_dv_shared_unlock(dev);
9630 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9633 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9635 flow_dv_shared_lock(dev);
9636 __flow_dv_destroy(dev, flow);
9637 flow_dv_shared_unlock(dev);
9641 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9644 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9648 flow_dv_shared_lock(dev);
9649 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9650 flow_dv_shared_unlock(dev);
9655 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9658 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9660 flow_dv_shared_lock(dev);
9661 flow_dv_counter_release(dev, cnt);
9662 flow_dv_shared_unlock(dev);
9665 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9666 .validate = flow_dv_validate,
9667 .prepare = flow_dv_prepare,
9668 .translate = flow_dv_translate,
9669 .apply = flow_dv_apply,
9670 .remove = flow_dv_remove,
9671 .destroy = flow_dv_destroy,
9672 .query = flow_dv_query,
9673 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9674 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9675 .create_policer_rules = flow_dv_create_policer_rules,
9676 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9677 .counter_alloc = flow_dv_counter_allocate,
9678 .counter_free = flow_dv_counter_free,
9679 .counter_query = flow_dv_counter_query,
9680 .get_aged_flows = flow_get_aged_flows,
9683 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */