1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <rte_mtr_driver.h>
26 #include <rte_tailq.h>
28 #include <mlx5_glue.h>
29 #include <mlx5_devx_cmds.h>
31 #include <mlx5_malloc.h>
33 #include "mlx5_defs.h"
35 #include "mlx5_common_os.h"
36 #include "mlx5_flow.h"
37 #include "mlx5_flow_os.h"
40 #include "rte_pmd_mlx5.h"
42 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
48 #ifndef HAVE_MLX5DV_DR_ESWITCH
49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
54 #ifndef HAVE_MLX5DV_DR
55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
58 /* VLAN header definitions */
59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
78 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
79 struct mlx5_flow_tbl_resource *tbl);
82 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
83 uint32_t encap_decap_idx);
86 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
89 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
92 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 * Initialize flow attributes structure according to flow items' types.
98 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
99 * mode. For tunnel mode, the items to be modified are the outermost ones.
102 * Pointer to item specification.
104 * Pointer to flow attributes structure.
105 * @param[in] dev_flow
106 * Pointer to the sub flow.
107 * @param[in] tunnel_decap
108 * Whether action is after tunnel decapsulation.
111 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
112 struct mlx5_flow *dev_flow, bool tunnel_decap)
114 uint64_t layers = dev_flow->handle->layers;
117 * If layers is already initialized, it means this dev_flow is the
118 * suffix flow, the layers flags is set by the prefix flow. Need to
119 * use the layer flags from prefix flow as the suffix flow may not
120 * have the user defined items as the flow is split.
123 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
127 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
129 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
134 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
135 uint8_t next_protocol = 0xff;
136 switch (item->type) {
137 case RTE_FLOW_ITEM_TYPE_GRE:
138 case RTE_FLOW_ITEM_TYPE_NVGRE:
139 case RTE_FLOW_ITEM_TYPE_VXLAN:
140 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
141 case RTE_FLOW_ITEM_TYPE_GENEVE:
142 case RTE_FLOW_ITEM_TYPE_MPLS:
146 case RTE_FLOW_ITEM_TYPE_IPV4:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv4 *)
151 item->mask)->hdr.next_proto_id)
153 ((const struct rte_flow_item_ipv4 *)
154 (item->spec))->hdr.next_proto_id &
155 ((const struct rte_flow_item_ipv4 *)
156 (item->mask))->hdr.next_proto_id;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_IPV6:
164 if (item->mask != NULL &&
165 ((const struct rte_flow_item_ipv6 *)
166 item->mask)->hdr.proto)
168 ((const struct rte_flow_item_ipv6 *)
169 (item->spec))->hdr.proto &
170 ((const struct rte_flow_item_ipv6 *)
171 (item->mask))->hdr.proto;
172 if ((next_protocol == IPPROTO_IPIP ||
173 next_protocol == IPPROTO_IPV6) && tunnel_decap)
176 case RTE_FLOW_ITEM_TYPE_UDP:
180 case RTE_FLOW_ITEM_TYPE_TCP:
192 * Convert rte_mtr_color to mlx5 color.
201 rte_col_2_mlx5_col(enum rte_color rcol)
204 case RTE_COLOR_GREEN:
205 return MLX5_FLOW_COLOR_GREEN;
206 case RTE_COLOR_YELLOW:
207 return MLX5_FLOW_COLOR_YELLOW;
209 return MLX5_FLOW_COLOR_RED;
213 return MLX5_FLOW_COLOR_UNDEFINED;
216 struct field_modify_info {
217 uint32_t size; /* Size of field in protocol header, in bytes. */
218 uint32_t offset; /* Offset of field in protocol header, in bytes. */
219 enum mlx5_modification_field id;
222 struct field_modify_info modify_eth[] = {
223 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
224 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
225 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
226 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
230 struct field_modify_info modify_vlan_out_first_vid[] = {
231 /* Size in bits !!! */
232 {12, 0, MLX5_MODI_OUT_FIRST_VID},
236 struct field_modify_info modify_ipv4[] = {
237 {1, 1, MLX5_MODI_OUT_IP_DSCP},
238 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
239 {4, 12, MLX5_MODI_OUT_SIPV4},
240 {4, 16, MLX5_MODI_OUT_DIPV4},
244 struct field_modify_info modify_ipv6[] = {
245 {1, 0, MLX5_MODI_OUT_IP_DSCP},
246 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
247 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
248 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
249 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
250 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
251 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
252 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
253 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
254 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
258 struct field_modify_info modify_udp[] = {
259 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
260 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
264 struct field_modify_info modify_tcp[] = {
265 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
266 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
267 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
268 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
272 static const struct rte_flow_item *
273 mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)
275 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
276 switch (item->type) {
279 case RTE_FLOW_ITEM_TYPE_VXLAN:
280 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
281 case RTE_FLOW_ITEM_TYPE_GRE:
282 case RTE_FLOW_ITEM_TYPE_MPLS:
283 case RTE_FLOW_ITEM_TYPE_NVGRE:
284 case RTE_FLOW_ITEM_TYPE_GENEVE:
286 case RTE_FLOW_ITEM_TYPE_IPV4:
287 case RTE_FLOW_ITEM_TYPE_IPV6:
288 if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||
289 item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)
298 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
299 uint8_t next_protocol, uint64_t *item_flags,
302 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
303 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
304 if (next_protocol == IPPROTO_IPIP) {
305 *item_flags |= MLX5_FLOW_LAYER_IPIP;
308 if (next_protocol == IPPROTO_IPV6) {
309 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
314 /* Update VLAN's VID/PCP based on input rte_flow_action.
317 * Pointer to struct rte_flow_action.
319 * Pointer to struct rte_vlan_hdr.
322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
323 struct rte_vlan_hdr *vlan)
326 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
328 ((const struct rte_flow_action_of_set_vlan_pcp *)
329 action->conf)->vlan_pcp;
330 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
331 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
332 vlan->vlan_tci |= vlan_tci;
333 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
334 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
335 vlan->vlan_tci |= rte_be_to_cpu_16
336 (((const struct rte_flow_action_of_set_vlan_vid *)
337 action->conf)->vlan_vid);
342 * Fetch 1, 2, 3 or 4 byte field from the byte array
343 * and return as unsigned integer in host-endian format.
346 * Pointer to data array.
348 * Size of field to extract.
351 * converted field in host endian format.
353 static inline uint32_t
354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
363 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
367 ret = (ret << 8) | *(data + sizeof(uint16_t));
370 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
381 * Convert modify-header action to DV specification.
383 * Data length of each action is determined by provided field description
384 * and the item mask. Data bit offset and width of each action is determined
385 * by provided item mask.
388 * Pointer to item specification.
390 * Pointer to field modification information.
391 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
393 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
395 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
396 * Negative offset value sets the same offset as source offset.
397 * size field is ignored, value is taken from source field.
398 * @param[in,out] resource
399 * Pointer to the modify-header resource.
401 * Type of modification.
403 * Pointer to the error structure.
406 * 0 on success, a negative errno value otherwise and rte_errno is set.
409 flow_dv_convert_modify_action(struct rte_flow_item *item,
410 struct field_modify_info *field,
411 struct field_modify_info *dcopy,
412 struct mlx5_flow_dv_modify_hdr_resource *resource,
413 uint32_t type, struct rte_flow_error *error)
415 uint32_t i = resource->actions_num;
416 struct mlx5_modification_cmd *actions = resource->actions;
417 uint32_t carry_b = 0;
420 * The item and mask are provided in big-endian format.
421 * The fields should be presented as in big-endian format either.
422 * Mask must be always present, it defines the actual field width.
424 MLX5_ASSERT(item->mask);
425 MLX5_ASSERT(field->size);
431 bool next_field = true;
432 bool next_dcopy = true;
434 if (i >= MLX5_MAX_MODIFY_NUM)
435 return rte_flow_error_set(error, EINVAL,
436 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
437 "too many items to modify");
438 /* Fetch variable byte size mask from the array. */
439 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
440 field->offset, field->size);
445 /* Deduce actual data width in bits from mask value. */
446 off_b = rte_bsf32(mask) + carry_b;
447 size_b = sizeof(uint32_t) * CHAR_BIT -
448 off_b - __builtin_clz(mask);
450 actions[i] = (struct mlx5_modification_cmd) {
454 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
457 if (type == MLX5_MODIFICATION_TYPE_COPY) {
459 actions[i].dst_field = dcopy->id;
460 actions[i].dst_offset =
461 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
462 /* Convert entire record to big-endian format. */
463 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
465 * Destination field overflow. Copy leftovers of
466 * a source field to the next destination field.
469 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
472 dcopy->size * CHAR_BIT - dcopy->offset;
473 carry_b = actions[i].length;
477 * Not enough bits in a source filed to fill a
478 * destination field. Switch to the next source.
480 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
481 (size_b == field->size * CHAR_BIT - off_b)) {
483 field->size * CHAR_BIT - off_b;
484 dcopy->offset += actions[i].length;
490 MLX5_ASSERT(item->spec);
491 data = flow_dv_fetch_field((const uint8_t *)item->spec +
492 field->offset, field->size);
493 /* Shift out the trailing masked bits from data. */
494 data = (data & mask) >> off_b;
495 actions[i].data1 = rte_cpu_to_be_32(data);
497 /* Convert entire record to expected big-endian format. */
498 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
502 } while (field->size);
503 if (resource->actions_num == i)
504 return rte_flow_error_set(error, EINVAL,
505 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
506 "invalid modification flow item");
507 resource->actions_num = i;
512 * Convert modify-header set IPv4 address action to DV specification.
514 * @param[in,out] resource
515 * Pointer to the modify-header resource.
517 * Pointer to action specification.
519 * Pointer to the error structure.
522 * 0 on success, a negative errno value otherwise and rte_errno is set.
525 flow_dv_convert_action_modify_ipv4
526 (struct mlx5_flow_dv_modify_hdr_resource *resource,
527 const struct rte_flow_action *action,
528 struct rte_flow_error *error)
530 const struct rte_flow_action_set_ipv4 *conf =
531 (const struct rte_flow_action_set_ipv4 *)(action->conf);
532 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
533 struct rte_flow_item_ipv4 ipv4;
534 struct rte_flow_item_ipv4 ipv4_mask;
536 memset(&ipv4, 0, sizeof(ipv4));
537 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
538 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
539 ipv4.hdr.src_addr = conf->ipv4_addr;
540 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
542 ipv4.hdr.dst_addr = conf->ipv4_addr;
543 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
546 item.mask = &ipv4_mask;
547 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
548 MLX5_MODIFICATION_TYPE_SET, error);
552 * Convert modify-header set IPv6 address action to DV specification.
554 * @param[in,out] resource
555 * Pointer to the modify-header resource.
557 * Pointer to action specification.
559 * Pointer to the error structure.
562 * 0 on success, a negative errno value otherwise and rte_errno is set.
565 flow_dv_convert_action_modify_ipv6
566 (struct mlx5_flow_dv_modify_hdr_resource *resource,
567 const struct rte_flow_action *action,
568 struct rte_flow_error *error)
570 const struct rte_flow_action_set_ipv6 *conf =
571 (const struct rte_flow_action_set_ipv6 *)(action->conf);
572 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
573 struct rte_flow_item_ipv6 ipv6;
574 struct rte_flow_item_ipv6 ipv6_mask;
576 memset(&ipv6, 0, sizeof(ipv6));
577 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
578 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
579 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
580 sizeof(ipv6.hdr.src_addr));
581 memcpy(&ipv6_mask.hdr.src_addr,
582 &rte_flow_item_ipv6_mask.hdr.src_addr,
583 sizeof(ipv6.hdr.src_addr));
585 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
586 sizeof(ipv6.hdr.dst_addr));
587 memcpy(&ipv6_mask.hdr.dst_addr,
588 &rte_flow_item_ipv6_mask.hdr.dst_addr,
589 sizeof(ipv6.hdr.dst_addr));
592 item.mask = &ipv6_mask;
593 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
594 MLX5_MODIFICATION_TYPE_SET, error);
598 * Convert modify-header set MAC address action to DV specification.
600 * @param[in,out] resource
601 * Pointer to the modify-header resource.
603 * Pointer to action specification.
605 * Pointer to the error structure.
608 * 0 on success, a negative errno value otherwise and rte_errno is set.
611 flow_dv_convert_action_modify_mac
612 (struct mlx5_flow_dv_modify_hdr_resource *resource,
613 const struct rte_flow_action *action,
614 struct rte_flow_error *error)
616 const struct rte_flow_action_set_mac *conf =
617 (const struct rte_flow_action_set_mac *)(action->conf);
618 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
619 struct rte_flow_item_eth eth;
620 struct rte_flow_item_eth eth_mask;
622 memset(ð, 0, sizeof(eth));
623 memset(ð_mask, 0, sizeof(eth_mask));
624 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
625 memcpy(ð.src.addr_bytes, &conf->mac_addr,
626 sizeof(eth.src.addr_bytes));
627 memcpy(ð_mask.src.addr_bytes,
628 &rte_flow_item_eth_mask.src.addr_bytes,
629 sizeof(eth_mask.src.addr_bytes));
631 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
632 sizeof(eth.dst.addr_bytes));
633 memcpy(ð_mask.dst.addr_bytes,
634 &rte_flow_item_eth_mask.dst.addr_bytes,
635 sizeof(eth_mask.dst.addr_bytes));
638 item.mask = ð_mask;
639 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
640 MLX5_MODIFICATION_TYPE_SET, error);
644 * Convert modify-header set VLAN VID action to DV specification.
646 * @param[in,out] resource
647 * Pointer to the modify-header resource.
649 * Pointer to action specification.
651 * Pointer to the error structure.
654 * 0 on success, a negative errno value otherwise and rte_errno is set.
657 flow_dv_convert_action_modify_vlan_vid
658 (struct mlx5_flow_dv_modify_hdr_resource *resource,
659 const struct rte_flow_action *action,
660 struct rte_flow_error *error)
662 const struct rte_flow_action_of_set_vlan_vid *conf =
663 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
664 int i = resource->actions_num;
665 struct mlx5_modification_cmd *actions = resource->actions;
666 struct field_modify_info *field = modify_vlan_out_first_vid;
668 if (i >= MLX5_MAX_MODIFY_NUM)
669 return rte_flow_error_set(error, EINVAL,
670 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
671 "too many items to modify");
672 actions[i] = (struct mlx5_modification_cmd) {
673 .action_type = MLX5_MODIFICATION_TYPE_SET,
675 .length = field->size,
676 .offset = field->offset,
678 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
679 actions[i].data1 = conf->vlan_vid;
680 actions[i].data1 = actions[i].data1 << 16;
681 resource->actions_num = ++i;
686 * Convert modify-header set TP action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to rte_flow_item objects list.
695 * Pointer to flow attributes structure.
696 * @param[in] dev_flow
697 * Pointer to the sub flow.
698 * @param[in] tunnel_decap
699 * Whether action is after tunnel decapsulation.
701 * Pointer to the error structure.
704 * 0 on success, a negative errno value otherwise and rte_errno is set.
707 flow_dv_convert_action_modify_tp
708 (struct mlx5_flow_dv_modify_hdr_resource *resource,
709 const struct rte_flow_action *action,
710 const struct rte_flow_item *items,
711 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
712 bool tunnel_decap, struct rte_flow_error *error)
714 const struct rte_flow_action_set_tp *conf =
715 (const struct rte_flow_action_set_tp *)(action->conf);
716 struct rte_flow_item item;
717 struct rte_flow_item_udp udp;
718 struct rte_flow_item_udp udp_mask;
719 struct rte_flow_item_tcp tcp;
720 struct rte_flow_item_tcp tcp_mask;
721 struct field_modify_info *field;
724 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
726 memset(&udp, 0, sizeof(udp));
727 memset(&udp_mask, 0, sizeof(udp_mask));
728 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
729 udp.hdr.src_port = conf->port;
730 udp_mask.hdr.src_port =
731 rte_flow_item_udp_mask.hdr.src_port;
733 udp.hdr.dst_port = conf->port;
734 udp_mask.hdr.dst_port =
735 rte_flow_item_udp_mask.hdr.dst_port;
737 item.type = RTE_FLOW_ITEM_TYPE_UDP;
739 item.mask = &udp_mask;
742 MLX5_ASSERT(attr->tcp);
743 memset(&tcp, 0, sizeof(tcp));
744 memset(&tcp_mask, 0, sizeof(tcp_mask));
745 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
746 tcp.hdr.src_port = conf->port;
747 tcp_mask.hdr.src_port =
748 rte_flow_item_tcp_mask.hdr.src_port;
750 tcp.hdr.dst_port = conf->port;
751 tcp_mask.hdr.dst_port =
752 rte_flow_item_tcp_mask.hdr.dst_port;
754 item.type = RTE_FLOW_ITEM_TYPE_TCP;
756 item.mask = &tcp_mask;
759 return flow_dv_convert_modify_action(&item, field, NULL, resource,
760 MLX5_MODIFICATION_TYPE_SET, error);
764 * Convert modify-header set TTL action to DV specification.
766 * @param[in,out] resource
767 * Pointer to the modify-header resource.
769 * Pointer to action specification.
771 * Pointer to rte_flow_item objects list.
773 * Pointer to flow attributes structure.
774 * @param[in] dev_flow
775 * Pointer to the sub flow.
776 * @param[in] tunnel_decap
777 * Whether action is after tunnel decapsulation.
779 * Pointer to the error structure.
782 * 0 on success, a negative errno value otherwise and rte_errno is set.
785 flow_dv_convert_action_modify_ttl
786 (struct mlx5_flow_dv_modify_hdr_resource *resource,
787 const struct rte_flow_action *action,
788 const struct rte_flow_item *items,
789 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
790 bool tunnel_decap, struct rte_flow_error *error)
792 const struct rte_flow_action_set_ttl *conf =
793 (const struct rte_flow_action_set_ttl *)(action->conf);
794 struct rte_flow_item item;
795 struct rte_flow_item_ipv4 ipv4;
796 struct rte_flow_item_ipv4 ipv4_mask;
797 struct rte_flow_item_ipv6 ipv6;
798 struct rte_flow_item_ipv6 ipv6_mask;
799 struct field_modify_info *field;
802 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
804 memset(&ipv4, 0, sizeof(ipv4));
805 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
806 ipv4.hdr.time_to_live = conf->ttl_value;
807 ipv4_mask.hdr.time_to_live = 0xFF;
808 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
810 item.mask = &ipv4_mask;
813 MLX5_ASSERT(attr->ipv6);
814 memset(&ipv6, 0, sizeof(ipv6));
815 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
816 ipv6.hdr.hop_limits = conf->ttl_value;
817 ipv6_mask.hdr.hop_limits = 0xFF;
818 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
820 item.mask = &ipv6_mask;
823 return flow_dv_convert_modify_action(&item, field, NULL, resource,
824 MLX5_MODIFICATION_TYPE_SET, error);
828 * Convert modify-header decrement TTL action to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to rte_flow_item objects list.
837 * Pointer to flow attributes structure.
838 * @param[in] dev_flow
839 * Pointer to the sub flow.
840 * @param[in] tunnel_decap
841 * Whether action is after tunnel decapsulation.
843 * Pointer to the error structure.
846 * 0 on success, a negative errno value otherwise and rte_errno is set.
849 flow_dv_convert_action_modify_dec_ttl
850 (struct mlx5_flow_dv_modify_hdr_resource *resource,
851 const struct rte_flow_item *items,
852 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
853 bool tunnel_decap, struct rte_flow_error *error)
855 struct rte_flow_item item;
856 struct rte_flow_item_ipv4 ipv4;
857 struct rte_flow_item_ipv4 ipv4_mask;
858 struct rte_flow_item_ipv6 ipv6;
859 struct rte_flow_item_ipv6 ipv6_mask;
860 struct field_modify_info *field;
863 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
865 memset(&ipv4, 0, sizeof(ipv4));
866 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
867 ipv4.hdr.time_to_live = 0xFF;
868 ipv4_mask.hdr.time_to_live = 0xFF;
869 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
871 item.mask = &ipv4_mask;
874 MLX5_ASSERT(attr->ipv6);
875 memset(&ipv6, 0, sizeof(ipv6));
876 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
877 ipv6.hdr.hop_limits = 0xFF;
878 ipv6_mask.hdr.hop_limits = 0xFF;
879 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
881 item.mask = &ipv6_mask;
884 return flow_dv_convert_modify_action(&item, field, NULL, resource,
885 MLX5_MODIFICATION_TYPE_ADD, error);
889 * Convert modify-header increment/decrement TCP Sequence number
890 * to DV specification.
892 * @param[in,out] resource
893 * Pointer to the modify-header resource.
895 * Pointer to action specification.
897 * Pointer to the error structure.
900 * 0 on success, a negative errno value otherwise and rte_errno is set.
903 flow_dv_convert_action_modify_tcp_seq
904 (struct mlx5_flow_dv_modify_hdr_resource *resource,
905 const struct rte_flow_action *action,
906 struct rte_flow_error *error)
908 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
909 uint64_t value = rte_be_to_cpu_32(*conf);
910 struct rte_flow_item item;
911 struct rte_flow_item_tcp tcp;
912 struct rte_flow_item_tcp tcp_mask;
914 memset(&tcp, 0, sizeof(tcp));
915 memset(&tcp_mask, 0, sizeof(tcp_mask));
916 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
918 * The HW has no decrement operation, only increment operation.
919 * To simulate decrement X from Y using increment operation
920 * we need to add UINT32_MAX X times to Y.
921 * Each adding of UINT32_MAX decrements Y by 1.
924 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
925 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
926 item.type = RTE_FLOW_ITEM_TYPE_TCP;
928 item.mask = &tcp_mask;
929 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
930 MLX5_MODIFICATION_TYPE_ADD, error);
934 * Convert modify-header increment/decrement TCP Acknowledgment number
935 * to DV specification.
937 * @param[in,out] resource
938 * Pointer to the modify-header resource.
940 * Pointer to action specification.
942 * Pointer to the error structure.
945 * 0 on success, a negative errno value otherwise and rte_errno is set.
948 flow_dv_convert_action_modify_tcp_ack
949 (struct mlx5_flow_dv_modify_hdr_resource *resource,
950 const struct rte_flow_action *action,
951 struct rte_flow_error *error)
953 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
954 uint64_t value = rte_be_to_cpu_32(*conf);
955 struct rte_flow_item item;
956 struct rte_flow_item_tcp tcp;
957 struct rte_flow_item_tcp tcp_mask;
959 memset(&tcp, 0, sizeof(tcp));
960 memset(&tcp_mask, 0, sizeof(tcp_mask));
961 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
963 * The HW has no decrement operation, only increment operation.
964 * To simulate decrement X from Y using increment operation
965 * we need to add UINT32_MAX X times to Y.
966 * Each adding of UINT32_MAX decrements Y by 1.
969 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
970 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
971 item.type = RTE_FLOW_ITEM_TYPE_TCP;
973 item.mask = &tcp_mask;
974 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
975 MLX5_MODIFICATION_TYPE_ADD, error);
978 static enum mlx5_modification_field reg_to_field[] = {
979 [REG_NON] = MLX5_MODI_OUT_NONE,
980 [REG_A] = MLX5_MODI_META_DATA_REG_A,
981 [REG_B] = MLX5_MODI_META_DATA_REG_B,
982 [REG_C_0] = MLX5_MODI_META_REG_C_0,
983 [REG_C_1] = MLX5_MODI_META_REG_C_1,
984 [REG_C_2] = MLX5_MODI_META_REG_C_2,
985 [REG_C_3] = MLX5_MODI_META_REG_C_3,
986 [REG_C_4] = MLX5_MODI_META_REG_C_4,
987 [REG_C_5] = MLX5_MODI_META_REG_C_5,
988 [REG_C_6] = MLX5_MODI_META_REG_C_6,
989 [REG_C_7] = MLX5_MODI_META_REG_C_7,
993 * Convert register set to DV specification.
995 * @param[in,out] resource
996 * Pointer to the modify-header resource.
998 * Pointer to action specification.
1000 * Pointer to the error structure.
1003 * 0 on success, a negative errno value otherwise and rte_errno is set.
1006 flow_dv_convert_action_set_reg
1007 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1008 const struct rte_flow_action *action,
1009 struct rte_flow_error *error)
1011 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1012 struct mlx5_modification_cmd *actions = resource->actions;
1013 uint32_t i = resource->actions_num;
1015 if (i >= MLX5_MAX_MODIFY_NUM)
1016 return rte_flow_error_set(error, EINVAL,
1017 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1018 "too many items to modify");
1019 MLX5_ASSERT(conf->id != REG_NON);
1020 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1021 actions[i] = (struct mlx5_modification_cmd) {
1022 .action_type = MLX5_MODIFICATION_TYPE_SET,
1023 .field = reg_to_field[conf->id],
1024 .offset = conf->offset,
1025 .length = conf->length,
1027 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1028 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1030 resource->actions_num = i;
1035 * Convert SET_TAG action to DV specification.
1038 * Pointer to the rte_eth_dev structure.
1039 * @param[in,out] resource
1040 * Pointer to the modify-header resource.
1042 * Pointer to action specification.
1044 * Pointer to the error structure.
1047 * 0 on success, a negative errno value otherwise and rte_errno is set.
1050 flow_dv_convert_action_set_tag
1051 (struct rte_eth_dev *dev,
1052 struct mlx5_flow_dv_modify_hdr_resource *resource,
1053 const struct rte_flow_action_set_tag *conf,
1054 struct rte_flow_error *error)
1056 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1057 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1058 struct rte_flow_item item = {
1062 struct field_modify_info reg_c_x[] = {
1065 enum mlx5_modification_field reg_type;
1068 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1071 MLX5_ASSERT(ret != REG_NON);
1072 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1073 reg_type = reg_to_field[ret];
1074 MLX5_ASSERT(reg_type > 0);
1075 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1076 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1077 MLX5_MODIFICATION_TYPE_SET, error);
1081 * Convert internal COPY_REG action to DV specification.
1084 * Pointer to the rte_eth_dev structure.
1085 * @param[in,out] res
1086 * Pointer to the modify-header resource.
1088 * Pointer to action specification.
1090 * Pointer to the error structure.
1093 * 0 on success, a negative errno value otherwise and rte_errno is set.
1096 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1097 struct mlx5_flow_dv_modify_hdr_resource *res,
1098 const struct rte_flow_action *action,
1099 struct rte_flow_error *error)
1101 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1102 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1103 struct rte_flow_item item = {
1107 struct field_modify_info reg_src[] = {
1108 {4, 0, reg_to_field[conf->src]},
1111 struct field_modify_info reg_dst = {
1113 .id = reg_to_field[conf->dst],
1115 /* Adjust reg_c[0] usage according to reported mask. */
1116 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1117 struct mlx5_priv *priv = dev->data->dev_private;
1118 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1120 MLX5_ASSERT(reg_c0);
1121 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1122 if (conf->dst == REG_C_0) {
1123 /* Copy to reg_c[0], within mask only. */
1124 reg_dst.offset = rte_bsf32(reg_c0);
1126 * Mask is ignoring the enianness, because
1127 * there is no conversion in datapath.
1129 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1130 /* Copy from destination lower bits to reg_c[0]. */
1131 mask = reg_c0 >> reg_dst.offset;
1133 /* Copy from destination upper bits to reg_c[0]. */
1134 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1135 rte_fls_u32(reg_c0));
1138 mask = rte_cpu_to_be_32(reg_c0);
1139 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1140 /* Copy from reg_c[0] to destination lower bits. */
1143 /* Copy from reg_c[0] to destination upper bits. */
1144 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1145 (rte_fls_u32(reg_c0) -
1150 return flow_dv_convert_modify_action(&item,
1151 reg_src, ®_dst, res,
1152 MLX5_MODIFICATION_TYPE_COPY,
1157 * Convert MARK action to DV specification. This routine is used
1158 * in extensive metadata only and requires metadata register to be
1159 * handled. In legacy mode hardware tag resource is engaged.
1162 * Pointer to the rte_eth_dev structure.
1164 * Pointer to MARK action specification.
1165 * @param[in,out] resource
1166 * Pointer to the modify-header resource.
1168 * Pointer to the error structure.
1171 * 0 on success, a negative errno value otherwise and rte_errno is set.
1174 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1175 const struct rte_flow_action_mark *conf,
1176 struct mlx5_flow_dv_modify_hdr_resource *resource,
1177 struct rte_flow_error *error)
1179 struct mlx5_priv *priv = dev->data->dev_private;
1180 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1181 priv->sh->dv_mark_mask);
1182 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1183 struct rte_flow_item item = {
1187 struct field_modify_info reg_c_x[] = {
1193 return rte_flow_error_set(error, EINVAL,
1194 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1195 NULL, "zero mark action mask");
1196 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1199 MLX5_ASSERT(reg > 0);
1200 if (reg == REG_C_0) {
1201 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1202 uint32_t shl_c0 = rte_bsf32(msk_c0);
1204 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1205 mask = rte_cpu_to_be_32(mask) & msk_c0;
1206 mask = rte_cpu_to_be_32(mask << shl_c0);
1208 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1209 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1210 MLX5_MODIFICATION_TYPE_SET, error);
1214 * Get metadata register index for specified steering domain.
1217 * Pointer to the rte_eth_dev structure.
1219 * Attributes of flow to determine steering domain.
1221 * Pointer to the error structure.
1224 * positive index on success, a negative errno value otherwise
1225 * and rte_errno is set.
1227 static enum modify_reg
1228 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1229 const struct rte_flow_attr *attr,
1230 struct rte_flow_error *error)
1233 mlx5_flow_get_reg_id(dev, attr->transfer ?
1237 MLX5_METADATA_RX, 0, error);
1239 return rte_flow_error_set(error,
1240 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1241 NULL, "unavailable "
1242 "metadata register");
1247 * Convert SET_META action to DV specification.
1250 * Pointer to the rte_eth_dev structure.
1251 * @param[in,out] resource
1252 * Pointer to the modify-header resource.
1254 * Attributes of flow that includes this item.
1256 * Pointer to action specification.
1258 * Pointer to the error structure.
1261 * 0 on success, a negative errno value otherwise and rte_errno is set.
1264 flow_dv_convert_action_set_meta
1265 (struct rte_eth_dev *dev,
1266 struct mlx5_flow_dv_modify_hdr_resource *resource,
1267 const struct rte_flow_attr *attr,
1268 const struct rte_flow_action_set_meta *conf,
1269 struct rte_flow_error *error)
1271 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1272 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1273 struct rte_flow_item item = {
1277 struct field_modify_info reg_c_x[] = {
1280 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1284 MLX5_ASSERT(reg != REG_NON);
1285 if (reg == REG_C_0) {
1286 struct mlx5_priv *priv = dev->data->dev_private;
1287 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1288 uint32_t shl_c0 = rte_bsf32(msk_c0);
1290 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1291 mask = rte_cpu_to_be_32(mask) & msk_c0;
1292 mask = rte_cpu_to_be_32(mask << shl_c0);
1294 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1295 /* The routine expects parameters in memory as big-endian ones. */
1296 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1297 MLX5_MODIFICATION_TYPE_SET, error);
1301 * Convert modify-header set IPv4 DSCP action to DV specification.
1303 * @param[in,out] resource
1304 * Pointer to the modify-header resource.
1306 * Pointer to action specification.
1308 * Pointer to the error structure.
1311 * 0 on success, a negative errno value otherwise and rte_errno is set.
1314 flow_dv_convert_action_modify_ipv4_dscp
1315 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1316 const struct rte_flow_action *action,
1317 struct rte_flow_error *error)
1319 const struct rte_flow_action_set_dscp *conf =
1320 (const struct rte_flow_action_set_dscp *)(action->conf);
1321 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1322 struct rte_flow_item_ipv4 ipv4;
1323 struct rte_flow_item_ipv4 ipv4_mask;
1325 memset(&ipv4, 0, sizeof(ipv4));
1326 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1327 ipv4.hdr.type_of_service = conf->dscp;
1328 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1330 item.mask = &ipv4_mask;
1331 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1332 MLX5_MODIFICATION_TYPE_SET, error);
1336 * Convert modify-header set IPv6 DSCP action to DV specification.
1338 * @param[in,out] resource
1339 * Pointer to the modify-header resource.
1341 * Pointer to action specification.
1343 * Pointer to the error structure.
1346 * 0 on success, a negative errno value otherwise and rte_errno is set.
1349 flow_dv_convert_action_modify_ipv6_dscp
1350 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1351 const struct rte_flow_action *action,
1352 struct rte_flow_error *error)
1354 const struct rte_flow_action_set_dscp *conf =
1355 (const struct rte_flow_action_set_dscp *)(action->conf);
1356 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1357 struct rte_flow_item_ipv6 ipv6;
1358 struct rte_flow_item_ipv6 ipv6_mask;
1360 memset(&ipv6, 0, sizeof(ipv6));
1361 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1363 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1364 * rdma-core only accept the DSCP bits byte aligned start from
1365 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1366 * bits in IPv6 case as rdma-core requires byte aligned value.
1368 ipv6.hdr.vtc_flow = conf->dscp;
1369 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1371 item.mask = &ipv6_mask;
1372 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1373 MLX5_MODIFICATION_TYPE_SET, error);
1377 mlx5_flow_item_field_width(struct mlx5_dev_config *config,
1378 enum rte_flow_field_id field)
1381 case RTE_FLOW_FIELD_START:
1383 case RTE_FLOW_FIELD_MAC_DST:
1384 case RTE_FLOW_FIELD_MAC_SRC:
1386 case RTE_FLOW_FIELD_VLAN_TYPE:
1388 case RTE_FLOW_FIELD_VLAN_ID:
1390 case RTE_FLOW_FIELD_MAC_TYPE:
1392 case RTE_FLOW_FIELD_IPV4_DSCP:
1394 case RTE_FLOW_FIELD_IPV4_TTL:
1396 case RTE_FLOW_FIELD_IPV4_SRC:
1397 case RTE_FLOW_FIELD_IPV4_DST:
1399 case RTE_FLOW_FIELD_IPV6_DSCP:
1401 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1403 case RTE_FLOW_FIELD_IPV6_SRC:
1404 case RTE_FLOW_FIELD_IPV6_DST:
1406 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1407 case RTE_FLOW_FIELD_TCP_PORT_DST:
1409 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1410 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1412 case RTE_FLOW_FIELD_TCP_FLAGS:
1414 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1415 case RTE_FLOW_FIELD_UDP_PORT_DST:
1417 case RTE_FLOW_FIELD_VXLAN_VNI:
1418 case RTE_FLOW_FIELD_GENEVE_VNI:
1420 case RTE_FLOW_FIELD_GTP_TEID:
1421 case RTE_FLOW_FIELD_TAG:
1423 case RTE_FLOW_FIELD_MARK:
1425 case RTE_FLOW_FIELD_META:
1426 if (config->dv_xmeta_en == MLX5_XMETA_MODE_META16)
1428 else if (config->dv_xmeta_en == MLX5_XMETA_MODE_META32)
1432 case RTE_FLOW_FIELD_POINTER:
1433 case RTE_FLOW_FIELD_VALUE:
1442 mlx5_flow_field_id_to_modify_info
1443 (const struct rte_flow_action_modify_data *data,
1444 struct field_modify_info *info,
1445 uint32_t *mask, uint32_t *value,
1446 uint32_t width, uint32_t dst_width,
1447 struct rte_eth_dev *dev,
1448 const struct rte_flow_attr *attr,
1449 struct rte_flow_error *error)
1451 struct mlx5_priv *priv = dev->data->dev_private;
1452 struct mlx5_dev_config *config = &priv->config;
1456 switch (data->field) {
1457 case RTE_FLOW_FIELD_START:
1458 /* not supported yet */
1461 case RTE_FLOW_FIELD_MAC_DST:
1462 off = data->offset > 16 ? data->offset - 16 : 0;
1464 if (data->offset < 16) {
1465 info[idx] = (struct field_modify_info){2, 0,
1466 MLX5_MODI_OUT_DMAC_15_0};
1468 mask[idx] = rte_cpu_to_be_16(0xffff >>
1472 mask[idx] = RTE_BE16(0xffff);
1479 info[idx] = (struct field_modify_info){4, 4 * idx,
1480 MLX5_MODI_OUT_DMAC_47_16};
1481 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1482 (32 - width)) << off);
1484 if (data->offset < 16)
1485 info[idx++] = (struct field_modify_info){2, 0,
1486 MLX5_MODI_OUT_DMAC_15_0};
1487 info[idx] = (struct field_modify_info){4, off,
1488 MLX5_MODI_OUT_DMAC_47_16};
1491 case RTE_FLOW_FIELD_MAC_SRC:
1492 off = data->offset > 16 ? data->offset - 16 : 0;
1494 if (data->offset < 16) {
1495 info[idx] = (struct field_modify_info){2, 0,
1496 MLX5_MODI_OUT_SMAC_15_0};
1498 mask[idx] = rte_cpu_to_be_16(0xffff >>
1502 mask[idx] = RTE_BE16(0xffff);
1509 info[idx] = (struct field_modify_info){4, 4 * idx,
1510 MLX5_MODI_OUT_SMAC_47_16};
1511 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1512 (32 - width)) << off);
1514 if (data->offset < 16)
1515 info[idx++] = (struct field_modify_info){2, 0,
1516 MLX5_MODI_OUT_SMAC_15_0};
1517 info[idx] = (struct field_modify_info){4, off,
1518 MLX5_MODI_OUT_SMAC_47_16};
1521 case RTE_FLOW_FIELD_VLAN_TYPE:
1522 /* not supported yet */
1524 case RTE_FLOW_FIELD_VLAN_ID:
1525 info[idx] = (struct field_modify_info){2, 0,
1526 MLX5_MODI_OUT_FIRST_VID};
1528 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1530 case RTE_FLOW_FIELD_MAC_TYPE:
1531 info[idx] = (struct field_modify_info){2, 0,
1532 MLX5_MODI_OUT_ETHERTYPE};
1534 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1536 case RTE_FLOW_FIELD_IPV4_DSCP:
1537 info[idx] = (struct field_modify_info){1, 0,
1538 MLX5_MODI_OUT_IP_DSCP};
1540 mask[idx] = 0x3f >> (6 - width);
1542 case RTE_FLOW_FIELD_IPV4_TTL:
1543 info[idx] = (struct field_modify_info){1, 0,
1544 MLX5_MODI_OUT_IPV4_TTL};
1546 mask[idx] = 0xff >> (8 - width);
1548 case RTE_FLOW_FIELD_IPV4_SRC:
1549 info[idx] = (struct field_modify_info){4, 0,
1550 MLX5_MODI_OUT_SIPV4};
1552 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1555 case RTE_FLOW_FIELD_IPV4_DST:
1556 info[idx] = (struct field_modify_info){4, 0,
1557 MLX5_MODI_OUT_DIPV4};
1559 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1562 case RTE_FLOW_FIELD_IPV6_DSCP:
1563 info[idx] = (struct field_modify_info){1, 0,
1564 MLX5_MODI_OUT_IP_DSCP};
1566 mask[idx] = 0x3f >> (6 - width);
1568 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1569 info[idx] = (struct field_modify_info){1, 0,
1570 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1572 mask[idx] = 0xff >> (8 - width);
1574 case RTE_FLOW_FIELD_IPV6_SRC:
1576 if (data->offset < 32) {
1577 info[idx] = (struct field_modify_info){4,
1579 MLX5_MODI_OUT_SIPV6_31_0};
1582 rte_cpu_to_be_32(0xffffffff >>
1586 mask[idx] = RTE_BE32(0xffffffff);
1593 if (data->offset < 64) {
1594 info[idx] = (struct field_modify_info){4,
1596 MLX5_MODI_OUT_SIPV6_63_32};
1599 rte_cpu_to_be_32(0xffffffff >>
1603 mask[idx] = RTE_BE32(0xffffffff);
1610 if (data->offset < 96) {
1611 info[idx] = (struct field_modify_info){4,
1613 MLX5_MODI_OUT_SIPV6_95_64};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[idx] = RTE_BE32(0xffffffff);
1627 info[idx] = (struct field_modify_info){4, 4 * idx,
1628 MLX5_MODI_OUT_SIPV6_127_96};
1629 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1632 if (data->offset < 32)
1633 info[idx++] = (struct field_modify_info){4, 0,
1634 MLX5_MODI_OUT_SIPV6_31_0};
1635 if (data->offset < 64)
1636 info[idx++] = (struct field_modify_info){4, 0,
1637 MLX5_MODI_OUT_SIPV6_63_32};
1638 if (data->offset < 96)
1639 info[idx++] = (struct field_modify_info){4, 0,
1640 MLX5_MODI_OUT_SIPV6_95_64};
1641 if (data->offset < 128)
1642 info[idx++] = (struct field_modify_info){4, 0,
1643 MLX5_MODI_OUT_SIPV6_127_96};
1646 case RTE_FLOW_FIELD_IPV6_DST:
1648 if (data->offset < 32) {
1649 info[idx] = (struct field_modify_info){4,
1651 MLX5_MODI_OUT_DIPV6_31_0};
1654 rte_cpu_to_be_32(0xffffffff >>
1658 mask[idx] = RTE_BE32(0xffffffff);
1665 if (data->offset < 64) {
1666 info[idx] = (struct field_modify_info){4,
1668 MLX5_MODI_OUT_DIPV6_63_32};
1671 rte_cpu_to_be_32(0xffffffff >>
1675 mask[idx] = RTE_BE32(0xffffffff);
1682 if (data->offset < 96) {
1683 info[idx] = (struct field_modify_info){4,
1685 MLX5_MODI_OUT_DIPV6_95_64};
1688 rte_cpu_to_be_32(0xffffffff >>
1692 mask[idx] = RTE_BE32(0xffffffff);
1699 info[idx] = (struct field_modify_info){4, 4 * idx,
1700 MLX5_MODI_OUT_DIPV6_127_96};
1701 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1704 if (data->offset < 32)
1705 info[idx++] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_31_0};
1707 if (data->offset < 64)
1708 info[idx++] = (struct field_modify_info){4, 0,
1709 MLX5_MODI_OUT_DIPV6_63_32};
1710 if (data->offset < 96)
1711 info[idx++] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_95_64};
1713 if (data->offset < 128)
1714 info[idx++] = (struct field_modify_info){4, 0,
1715 MLX5_MODI_OUT_DIPV6_127_96};
1718 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1719 info[idx] = (struct field_modify_info){2, 0,
1720 MLX5_MODI_OUT_TCP_SPORT};
1722 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1724 case RTE_FLOW_FIELD_TCP_PORT_DST:
1725 info[idx] = (struct field_modify_info){2, 0,
1726 MLX5_MODI_OUT_TCP_DPORT};
1728 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1730 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1731 info[idx] = (struct field_modify_info){4, 0,
1732 MLX5_MODI_OUT_TCP_SEQ_NUM};
1734 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1737 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1738 info[idx] = (struct field_modify_info){4, 0,
1739 MLX5_MODI_OUT_TCP_ACK_NUM};
1741 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1744 case RTE_FLOW_FIELD_TCP_FLAGS:
1745 info[idx] = (struct field_modify_info){2, 0,
1746 MLX5_MODI_OUT_TCP_FLAGS};
1748 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1750 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1751 info[idx] = (struct field_modify_info){2, 0,
1752 MLX5_MODI_OUT_UDP_SPORT};
1754 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1756 case RTE_FLOW_FIELD_UDP_PORT_DST:
1757 info[idx] = (struct field_modify_info){2, 0,
1758 MLX5_MODI_OUT_UDP_DPORT};
1760 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1762 case RTE_FLOW_FIELD_VXLAN_VNI:
1763 /* not supported yet */
1765 case RTE_FLOW_FIELD_GENEVE_VNI:
1766 /* not supported yet*/
1768 case RTE_FLOW_FIELD_GTP_TEID:
1769 info[idx] = (struct field_modify_info){4, 0,
1770 MLX5_MODI_GTP_TEID};
1772 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1775 case RTE_FLOW_FIELD_TAG:
1777 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1778 data->level, error);
1781 MLX5_ASSERT(reg != REG_NON);
1782 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1783 info[idx] = (struct field_modify_info){4, 0,
1787 rte_cpu_to_be_32(0xffffffff >>
1791 case RTE_FLOW_FIELD_MARK:
1793 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1797 MLX5_ASSERT(reg != REG_NON);
1798 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1799 info[idx] = (struct field_modify_info){4, 0,
1803 rte_cpu_to_be_32(0xffffffff >>
1807 case RTE_FLOW_FIELD_META:
1809 unsigned int xmeta = config->dv_xmeta_en;
1810 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1813 MLX5_ASSERT(reg != REG_NON);
1814 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1815 if (xmeta == MLX5_XMETA_MODE_META16) {
1816 info[idx] = (struct field_modify_info){2, 0,
1819 mask[idx] = rte_cpu_to_be_16(0xffff >>
1821 } else if (xmeta == MLX5_XMETA_MODE_META32) {
1822 info[idx] = (struct field_modify_info){4, 0,
1826 rte_cpu_to_be_32(0xffffffff >>
1833 case RTE_FLOW_FIELD_POINTER:
1834 case RTE_FLOW_FIELD_VALUE:
1835 if (data->field == RTE_FLOW_FIELD_POINTER)
1836 memcpy(&val, (void *)(uintptr_t)data->value,
1840 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1842 if (dst_width == 48) {
1843 /*special case for MAC addresses */
1844 value[idx] = rte_cpu_to_be_16(val);
1847 } else if (dst_width > 16) {
1848 value[idx] = rte_cpu_to_be_32(val);
1850 } else if (dst_width > 8) {
1851 value[idx] = rte_cpu_to_be_16(val);
1854 value[idx] = (uint8_t)val;
1869 * Convert modify_field action to DV specification.
1872 * Pointer to the rte_eth_dev structure.
1873 * @param[in,out] resource
1874 * Pointer to the modify-header resource.
1876 * Pointer to action specification.
1878 * Attributes of flow that includes this item.
1880 * Pointer to the error structure.
1883 * 0 on success, a negative errno value otherwise and rte_errno is set.
1886 flow_dv_convert_action_modify_field
1887 (struct rte_eth_dev *dev,
1888 struct mlx5_flow_dv_modify_hdr_resource *resource,
1889 const struct rte_flow_action *action,
1890 const struct rte_flow_attr *attr,
1891 struct rte_flow_error *error)
1893 struct mlx5_priv *priv = dev->data->dev_private;
1894 struct mlx5_dev_config *config = &priv->config;
1895 const struct rte_flow_action_modify_field *conf =
1896 (const struct rte_flow_action_modify_field *)(action->conf);
1897 struct rte_flow_item item;
1898 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1900 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1902 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1903 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1905 uint32_t dst_width = mlx5_flow_item_field_width(config,
1908 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1909 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1910 type = MLX5_MODIFICATION_TYPE_SET;
1911 /** For SET fill the destination field (field) first. */
1912 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1913 value, conf->width, dst_width, dev, attr, error);
1914 /** Then copy immediate value from source as per mask. */
1915 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1916 value, conf->width, dst_width, dev, attr, error);
1919 type = MLX5_MODIFICATION_TYPE_COPY;
1920 /** For COPY fill the destination field (dcopy) without mask. */
1921 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1922 value, conf->width, dst_width, dev, attr, error);
1923 /** Then construct the source field (field) with mask. */
1924 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1925 value, conf->width, dst_width, dev, attr, error);
1928 return flow_dv_convert_modify_action(&item,
1929 field, dcopy, resource, type, error);
1933 * Validate MARK item.
1936 * Pointer to the rte_eth_dev structure.
1938 * Item specification.
1940 * Attributes of flow that includes this item.
1942 * Pointer to error structure.
1945 * 0 on success, a negative errno value otherwise and rte_errno is set.
1948 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1949 const struct rte_flow_item *item,
1950 const struct rte_flow_attr *attr __rte_unused,
1951 struct rte_flow_error *error)
1953 struct mlx5_priv *priv = dev->data->dev_private;
1954 struct mlx5_dev_config *config = &priv->config;
1955 const struct rte_flow_item_mark *spec = item->spec;
1956 const struct rte_flow_item_mark *mask = item->mask;
1957 const struct rte_flow_item_mark nic_mask = {
1958 .id = priv->sh->dv_mark_mask,
1962 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1963 return rte_flow_error_set(error, ENOTSUP,
1964 RTE_FLOW_ERROR_TYPE_ITEM, item,
1965 "extended metadata feature"
1967 if (!mlx5_flow_ext_mreg_supported(dev))
1968 return rte_flow_error_set(error, ENOTSUP,
1969 RTE_FLOW_ERROR_TYPE_ITEM, item,
1970 "extended metadata register"
1971 " isn't supported");
1973 return rte_flow_error_set(error, ENOTSUP,
1974 RTE_FLOW_ERROR_TYPE_ITEM, item,
1975 "extended metadata register"
1976 " isn't available");
1977 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1981 return rte_flow_error_set(error, EINVAL,
1982 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1984 "data cannot be empty");
1985 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1986 return rte_flow_error_set(error, EINVAL,
1987 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1989 "mark id exceeds the limit");
1993 return rte_flow_error_set(error, EINVAL,
1994 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1995 "mask cannot be zero");
1997 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1998 (const uint8_t *)&nic_mask,
1999 sizeof(struct rte_flow_item_mark),
2000 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2007 * Validate META item.
2010 * Pointer to the rte_eth_dev structure.
2012 * Item specification.
2014 * Attributes of flow that includes this item.
2016 * Pointer to error structure.
2019 * 0 on success, a negative errno value otherwise and rte_errno is set.
2022 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2023 const struct rte_flow_item *item,
2024 const struct rte_flow_attr *attr,
2025 struct rte_flow_error *error)
2027 struct mlx5_priv *priv = dev->data->dev_private;
2028 struct mlx5_dev_config *config = &priv->config;
2029 const struct rte_flow_item_meta *spec = item->spec;
2030 const struct rte_flow_item_meta *mask = item->mask;
2031 struct rte_flow_item_meta nic_mask = {
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2041 "data cannot be empty");
2042 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2043 if (!mlx5_flow_ext_mreg_supported(dev))
2044 return rte_flow_error_set(error, ENOTSUP,
2045 RTE_FLOW_ERROR_TYPE_ITEM, item,
2046 "extended metadata register"
2047 " isn't supported");
2048 reg = flow_dv_get_metadata_reg(dev, attr, error);
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "unavalable extended metadata register");
2056 return rte_flow_error_set(error, ENOTSUP,
2057 RTE_FLOW_ERROR_TYPE_ITEM, item,
2061 nic_mask.data = priv->sh->dv_meta_mask;
2064 return rte_flow_error_set(error, ENOTSUP,
2065 RTE_FLOW_ERROR_TYPE_ITEM, item,
2066 "extended metadata feature "
2067 "should be enabled when "
2068 "meta item is requested "
2069 "with e-switch mode ");
2071 return rte_flow_error_set(error, ENOTSUP,
2072 RTE_FLOW_ERROR_TYPE_ITEM, item,
2073 "match on metadata for ingress "
2074 "is not supported in legacy "
2078 mask = &rte_flow_item_meta_mask;
2080 return rte_flow_error_set(error, EINVAL,
2081 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2082 "mask cannot be zero");
2084 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2085 (const uint8_t *)&nic_mask,
2086 sizeof(struct rte_flow_item_meta),
2087 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2092 * Validate TAG item.
2095 * Pointer to the rte_eth_dev structure.
2097 * Item specification.
2099 * Attributes of flow that includes this item.
2101 * Pointer to error structure.
2104 * 0 on success, a negative errno value otherwise and rte_errno is set.
2107 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2108 const struct rte_flow_item *item,
2109 const struct rte_flow_attr *attr __rte_unused,
2110 struct rte_flow_error *error)
2112 const struct rte_flow_item_tag *spec = item->spec;
2113 const struct rte_flow_item_tag *mask = item->mask;
2114 const struct rte_flow_item_tag nic_mask = {
2115 .data = RTE_BE32(UINT32_MAX),
2120 if (!mlx5_flow_ext_mreg_supported(dev))
2121 return rte_flow_error_set(error, ENOTSUP,
2122 RTE_FLOW_ERROR_TYPE_ITEM, item,
2123 "extensive metadata register"
2124 " isn't supported");
2126 return rte_flow_error_set(error, EINVAL,
2127 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2129 "data cannot be empty");
2131 mask = &rte_flow_item_tag_mask;
2133 return rte_flow_error_set(error, EINVAL,
2134 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2135 "mask cannot be zero");
2137 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2138 (const uint8_t *)&nic_mask,
2139 sizeof(struct rte_flow_item_tag),
2140 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2143 if (mask->index != 0xff)
2144 return rte_flow_error_set(error, EINVAL,
2145 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2146 "partial mask for tag index"
2147 " is not supported");
2148 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2151 MLX5_ASSERT(ret != REG_NON);
2156 * Validate vport item.
2159 * Pointer to the rte_eth_dev structure.
2161 * Item specification.
2163 * Attributes of flow that includes this item.
2164 * @param[in] item_flags
2165 * Bit-fields that holds the items detected until now.
2167 * Pointer to error structure.
2170 * 0 on success, a negative errno value otherwise and rte_errno is set.
2173 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2174 const struct rte_flow_item *item,
2175 const struct rte_flow_attr *attr,
2176 uint64_t item_flags,
2177 struct rte_flow_error *error)
2179 const struct rte_flow_item_port_id *spec = item->spec;
2180 const struct rte_flow_item_port_id *mask = item->mask;
2181 const struct rte_flow_item_port_id switch_mask = {
2184 struct mlx5_priv *esw_priv;
2185 struct mlx5_priv *dev_priv;
2188 if (!attr->transfer)
2189 return rte_flow_error_set(error, EINVAL,
2190 RTE_FLOW_ERROR_TYPE_ITEM,
2192 "match on port id is valid only"
2193 " when transfer flag is enabled");
2194 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2195 return rte_flow_error_set(error, ENOTSUP,
2196 RTE_FLOW_ERROR_TYPE_ITEM, item,
2197 "multiple source ports are not"
2200 mask = &switch_mask;
2201 if (mask->id != 0xffffffff)
2202 return rte_flow_error_set(error, ENOTSUP,
2203 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2205 "no support for partial mask on"
2207 ret = mlx5_flow_item_acceptable
2208 (item, (const uint8_t *)mask,
2209 (const uint8_t *)&rte_flow_item_port_id_mask,
2210 sizeof(struct rte_flow_item_port_id),
2211 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2216 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2218 return rte_flow_error_set(error, rte_errno,
2219 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2220 "failed to obtain E-Switch info for"
2222 dev_priv = mlx5_dev_to_eswitch_info(dev);
2224 return rte_flow_error_set(error, rte_errno,
2225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2227 "failed to obtain E-Switch info");
2228 if (esw_priv->domain_id != dev_priv->domain_id)
2229 return rte_flow_error_set(error, EINVAL,
2230 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2231 "cannot match on a port from a"
2232 " different E-Switch");
2237 * Validate VLAN item.
2240 * Item specification.
2241 * @param[in] item_flags
2242 * Bit-fields that holds the items detected until now.
2244 * Ethernet device flow is being created on.
2246 * Pointer to error structure.
2249 * 0 on success, a negative errno value otherwise and rte_errno is set.
2252 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2253 uint64_t item_flags,
2254 struct rte_eth_dev *dev,
2255 struct rte_flow_error *error)
2257 const struct rte_flow_item_vlan *mask = item->mask;
2258 const struct rte_flow_item_vlan nic_mask = {
2259 .tci = RTE_BE16(UINT16_MAX),
2260 .inner_type = RTE_BE16(UINT16_MAX),
2263 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2265 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2266 MLX5_FLOW_LAYER_INNER_L4) :
2267 (MLX5_FLOW_LAYER_OUTER_L3 |
2268 MLX5_FLOW_LAYER_OUTER_L4);
2269 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2270 MLX5_FLOW_LAYER_OUTER_VLAN;
2272 if (item_flags & vlanm)
2273 return rte_flow_error_set(error, EINVAL,
2274 RTE_FLOW_ERROR_TYPE_ITEM, item,
2275 "multiple VLAN layers not supported");
2276 else if ((item_flags & l34m) != 0)
2277 return rte_flow_error_set(error, EINVAL,
2278 RTE_FLOW_ERROR_TYPE_ITEM, item,
2279 "VLAN cannot follow L3/L4 layer");
2281 mask = &rte_flow_item_vlan_mask;
2282 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2283 (const uint8_t *)&nic_mask,
2284 sizeof(struct rte_flow_item_vlan),
2285 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2288 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2289 struct mlx5_priv *priv = dev->data->dev_private;
2291 if (priv->vmwa_context) {
2293 * Non-NULL context means we have a virtual machine
2294 * and SR-IOV enabled, we have to create VLAN interface
2295 * to make hypervisor to setup E-Switch vport
2296 * context correctly. We avoid creating the multiple
2297 * VLAN interfaces, so we cannot support VLAN tag mask.
2299 return rte_flow_error_set(error, EINVAL,
2300 RTE_FLOW_ERROR_TYPE_ITEM,
2302 "VLAN tag mask is not"
2303 " supported in virtual"
2311 * GTP flags are contained in 1 byte of the format:
2312 * -------------------------------------------
2313 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2314 * |-----------------------------------------|
2315 * | value | Version | PT | Res | E | S | PN |
2316 * -------------------------------------------
2318 * Matching is supported only for GTP flags E, S, PN.
2320 #define MLX5_GTP_FLAGS_MASK 0x07
2323 * Validate GTP item.
2326 * Pointer to the rte_eth_dev structure.
2328 * Item specification.
2329 * @param[in] item_flags
2330 * Bit-fields that holds the items detected until now.
2332 * Pointer to error structure.
2335 * 0 on success, a negative errno value otherwise and rte_errno is set.
2338 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2339 const struct rte_flow_item *item,
2340 uint64_t item_flags,
2341 struct rte_flow_error *error)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2344 const struct rte_flow_item_gtp *spec = item->spec;
2345 const struct rte_flow_item_gtp *mask = item->mask;
2346 const struct rte_flow_item_gtp nic_mask = {
2347 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2349 .teid = RTE_BE32(0xffffffff),
2352 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2353 return rte_flow_error_set(error, ENOTSUP,
2354 RTE_FLOW_ERROR_TYPE_ITEM, item,
2355 "GTP support is not enabled");
2356 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2357 return rte_flow_error_set(error, ENOTSUP,
2358 RTE_FLOW_ERROR_TYPE_ITEM, item,
2359 "multiple tunnel layers not"
2361 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2362 return rte_flow_error_set(error, EINVAL,
2363 RTE_FLOW_ERROR_TYPE_ITEM, item,
2364 "no outer UDP layer found");
2366 mask = &rte_flow_item_gtp_mask;
2367 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2368 return rte_flow_error_set(error, ENOTSUP,
2369 RTE_FLOW_ERROR_TYPE_ITEM, item,
2370 "Match is supported for GTP"
2372 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2373 (const uint8_t *)&nic_mask,
2374 sizeof(struct rte_flow_item_gtp),
2375 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2379 * Validate GTP PSC item.
2382 * Item specification.
2383 * @param[in] last_item
2384 * Previous validated item in the pattern items.
2385 * @param[in] gtp_item
2386 * Previous GTP item specification.
2388 * Pointer to flow attributes.
2390 * Pointer to error structure.
2393 * 0 on success, a negative errno value otherwise and rte_errno is set.
2396 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2398 const struct rte_flow_item *gtp_item,
2399 const struct rte_flow_attr *attr,
2400 struct rte_flow_error *error)
2402 const struct rte_flow_item_gtp *gtp_spec;
2403 const struct rte_flow_item_gtp *gtp_mask;
2404 const struct rte_flow_item_gtp_psc *spec;
2405 const struct rte_flow_item_gtp_psc *mask;
2406 const struct rte_flow_item_gtp_psc nic_mask = {
2411 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2412 return rte_flow_error_set
2413 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2414 "GTP PSC item must be preceded with GTP item");
2415 gtp_spec = gtp_item->spec;
2416 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2417 /* GTP spec and E flag is requested to match zero. */
2419 (gtp_mask->v_pt_rsv_flags &
2420 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2421 return rte_flow_error_set
2422 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2423 "GTP E flag must be 1 to match GTP PSC");
2424 /* Check the flow is not created in group zero. */
2425 if (!attr->transfer && !attr->group)
2426 return rte_flow_error_set
2427 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2428 "GTP PSC is not supported for group 0");
2429 /* GTP spec is here and E flag is requested to match zero. */
2433 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2434 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2435 return rte_flow_error_set
2436 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2437 "PDU type should be smaller than 16");
2438 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2439 (const uint8_t *)&nic_mask,
2440 sizeof(struct rte_flow_item_gtp_psc),
2441 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2445 * Validate IPV4 item.
2446 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2447 * add specific validation of fragment_offset field,
2450 * Item specification.
2451 * @param[in] item_flags
2452 * Bit-fields that holds the items detected until now.
2454 * Pointer to error structure.
2457 * 0 on success, a negative errno value otherwise and rte_errno is set.
2460 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2461 uint64_t item_flags,
2463 uint16_t ether_type,
2464 struct rte_flow_error *error)
2467 const struct rte_flow_item_ipv4 *spec = item->spec;
2468 const struct rte_flow_item_ipv4 *last = item->last;
2469 const struct rte_flow_item_ipv4 *mask = item->mask;
2470 rte_be16_t fragment_offset_spec = 0;
2471 rte_be16_t fragment_offset_last = 0;
2472 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2474 .src_addr = RTE_BE32(0xffffffff),
2475 .dst_addr = RTE_BE32(0xffffffff),
2476 .type_of_service = 0xff,
2477 .fragment_offset = RTE_BE16(0xffff),
2478 .next_proto_id = 0xff,
2479 .time_to_live = 0xff,
2483 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2484 ether_type, &nic_ipv4_mask,
2485 MLX5_ITEM_RANGE_ACCEPTED, error);
2489 fragment_offset_spec = spec->hdr.fragment_offset &
2490 mask->hdr.fragment_offset;
2491 if (!fragment_offset_spec)
2494 * spec and mask are valid, enforce using full mask to make sure the
2495 * complete value is used correctly.
2497 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2498 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2499 return rte_flow_error_set(error, EINVAL,
2500 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2501 item, "must use full mask for"
2502 " fragment_offset");
2504 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2505 * indicating this is 1st fragment of fragmented packet.
2506 * This is not yet supported in MLX5, return appropriate error message.
2508 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2509 return rte_flow_error_set(error, ENOTSUP,
2510 RTE_FLOW_ERROR_TYPE_ITEM, item,
2511 "match on first fragment not "
2513 if (fragment_offset_spec && !last)
2514 return rte_flow_error_set(error, ENOTSUP,
2515 RTE_FLOW_ERROR_TYPE_ITEM, item,
2516 "specified value not supported");
2517 /* spec and last are valid, validate the specified range. */
2518 fragment_offset_last = last->hdr.fragment_offset &
2519 mask->hdr.fragment_offset;
2521 * Match on fragment_offset spec 0x2001 and last 0x3fff
2522 * means MF is 1 and frag-offset is > 0.
2523 * This packet is fragment 2nd and onward, excluding last.
2524 * This is not yet supported in MLX5, return appropriate
2527 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2528 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2529 return rte_flow_error_set(error, ENOTSUP,
2530 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2531 last, "match on following "
2532 "fragments not supported");
2534 * Match on fragment_offset spec 0x0001 and last 0x1fff
2535 * means MF is 0 and frag-offset is > 0.
2536 * This packet is last fragment of fragmented packet.
2537 * This is not yet supported in MLX5, return appropriate
2540 if (fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2544 last, "match on last "
2545 "fragment not supported");
2547 * Match on fragment_offset spec 0x0001 and last 0x3fff
2548 * means MF and/or frag-offset is not 0.
2549 * This is a fragmented packet.
2550 * Other range values are invalid and rejected.
2552 if (!(fragment_offset_spec == RTE_BE16(1) &&
2553 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2554 return rte_flow_error_set(error, ENOTSUP,
2555 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2556 "specified range not supported");
2561 * Validate IPV6 fragment extension item.
2564 * Item specification.
2565 * @param[in] item_flags
2566 * Bit-fields that holds the items detected until now.
2568 * Pointer to error structure.
2571 * 0 on success, a negative errno value otherwise and rte_errno is set.
2574 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2575 uint64_t item_flags,
2576 struct rte_flow_error *error)
2578 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2579 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2580 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2581 rte_be16_t frag_data_spec = 0;
2582 rte_be16_t frag_data_last = 0;
2583 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2584 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2585 MLX5_FLOW_LAYER_OUTER_L4;
2587 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2589 .next_header = 0xff,
2590 .frag_data = RTE_BE16(0xffff),
2594 if (item_flags & l4m)
2595 return rte_flow_error_set(error, EINVAL,
2596 RTE_FLOW_ERROR_TYPE_ITEM, item,
2597 "ipv6 fragment extension item cannot "
2599 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2600 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2601 return rte_flow_error_set(error, EINVAL,
2602 RTE_FLOW_ERROR_TYPE_ITEM, item,
2603 "ipv6 fragment extension item must "
2604 "follow ipv6 item");
2606 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2607 if (!frag_data_spec)
2610 * spec and mask are valid, enforce using full mask to make sure the
2611 * complete value is used correctly.
2613 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2614 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2615 return rte_flow_error_set(error, EINVAL,
2616 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2617 item, "must use full mask for"
2620 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2621 * This is 1st fragment of fragmented packet.
2623 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2624 return rte_flow_error_set(error, ENOTSUP,
2625 RTE_FLOW_ERROR_TYPE_ITEM, item,
2626 "match on first fragment not "
2628 if (frag_data_spec && !last)
2629 return rte_flow_error_set(error, EINVAL,
2630 RTE_FLOW_ERROR_TYPE_ITEM, item,
2631 "specified value not supported");
2632 ret = mlx5_flow_item_acceptable
2633 (item, (const uint8_t *)mask,
2634 (const uint8_t *)&nic_mask,
2635 sizeof(struct rte_flow_item_ipv6_frag_ext),
2636 MLX5_ITEM_RANGE_ACCEPTED, error);
2639 /* spec and last are valid, validate the specified range. */
2640 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2642 * Match on frag_data spec 0x0009 and last 0xfff9
2643 * means M is 1 and frag-offset is > 0.
2644 * This packet is fragment 2nd and onward, excluding last.
2645 * This is not yet supported in MLX5, return appropriate
2648 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2649 RTE_IPV6_EHDR_MF_MASK) &&
2650 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2651 return rte_flow_error_set(error, ENOTSUP,
2652 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2653 last, "match on following "
2654 "fragments not supported");
2656 * Match on frag_data spec 0x0008 and last 0xfff8
2657 * means M is 0 and frag-offset is > 0.
2658 * This packet is last fragment of fragmented packet.
2659 * This is not yet supported in MLX5, return appropriate
2662 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2663 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2664 return rte_flow_error_set(error, ENOTSUP,
2665 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2666 last, "match on last "
2667 "fragment not supported");
2668 /* Other range values are invalid and rejected. */
2669 return rte_flow_error_set(error, EINVAL,
2670 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2671 "specified range not supported");
2675 * Validate ASO CT item.
2678 * Pointer to the rte_eth_dev structure.
2680 * Item specification.
2681 * @param[in] item_flags
2682 * Pointer to bit-fields that holds the items detected until now.
2684 * Pointer to error structure.
2687 * 0 on success, a negative errno value otherwise and rte_errno is set.
2690 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2691 const struct rte_flow_item *item,
2692 uint64_t *item_flags,
2693 struct rte_flow_error *error)
2695 const struct rte_flow_item_conntrack *spec = item->spec;
2696 const struct rte_flow_item_conntrack *mask = item->mask;
2700 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2701 return rte_flow_error_set(error, EINVAL,
2702 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2703 "Only one CT is supported");
2705 mask = &rte_flow_item_conntrack_mask;
2706 flags = spec->flags & mask->flags;
2707 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2708 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2709 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2710 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2711 return rte_flow_error_set(error, EINVAL,
2712 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2713 "Conflict status bits");
2714 /* State change also needs to be considered. */
2715 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2720 * Validate the pop VLAN action.
2723 * Pointer to the rte_eth_dev structure.
2724 * @param[in] action_flags
2725 * Holds the actions detected until now.
2727 * Pointer to the pop vlan action.
2728 * @param[in] item_flags
2729 * The items found in this flow rule.
2731 * Pointer to flow attributes.
2733 * Pointer to error structure.
2736 * 0 on success, a negative errno value otherwise and rte_errno is set.
2739 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2740 uint64_t action_flags,
2741 const struct rte_flow_action *action,
2742 uint64_t item_flags,
2743 const struct rte_flow_attr *attr,
2744 struct rte_flow_error *error)
2746 const struct mlx5_priv *priv = dev->data->dev_private;
2750 if (!priv->sh->pop_vlan_action)
2751 return rte_flow_error_set(error, ENOTSUP,
2752 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2754 "pop vlan action is not supported");
2756 return rte_flow_error_set(error, ENOTSUP,
2757 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2759 "pop vlan action not supported for "
2761 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2762 return rte_flow_error_set(error, ENOTSUP,
2763 RTE_FLOW_ERROR_TYPE_ACTION, action,
2764 "no support for multiple VLAN "
2766 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2767 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2768 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2769 return rte_flow_error_set(error, ENOTSUP,
2770 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2772 "cannot pop vlan after decap without "
2773 "match on inner vlan in the flow");
2774 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2775 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2776 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2777 return rte_flow_error_set(error, ENOTSUP,
2778 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2780 "cannot pop vlan without a "
2781 "match on (outer) vlan in the flow");
2782 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION, action,
2785 "wrong action order, port_id should "
2786 "be after pop VLAN action");
2787 if (!attr->transfer && priv->representor)
2788 return rte_flow_error_set(error, ENOTSUP,
2789 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2790 "pop vlan action for VF representor "
2791 "not supported on NIC table");
2796 * Get VLAN default info from vlan match info.
2799 * the list of item specifications.
2801 * pointer VLAN info to fill to.
2804 * 0 on success, a negative errno value otherwise and rte_errno is set.
2807 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2808 struct rte_vlan_hdr *vlan)
2810 const struct rte_flow_item_vlan nic_mask = {
2811 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2812 MLX5DV_FLOW_VLAN_VID_MASK),
2813 .inner_type = RTE_BE16(0xffff),
2818 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2819 int type = items->type;
2821 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2822 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2825 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2826 const struct rte_flow_item_vlan *vlan_m = items->mask;
2827 const struct rte_flow_item_vlan *vlan_v = items->spec;
2829 /* If VLAN item in pattern doesn't contain data, return here. */
2834 /* Only full match values are accepted */
2835 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2836 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2837 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2839 rte_be_to_cpu_16(vlan_v->tci &
2840 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2842 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2843 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2844 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2846 rte_be_to_cpu_16(vlan_v->tci &
2847 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2849 if (vlan_m->inner_type == nic_mask.inner_type)
2850 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2851 vlan_m->inner_type);
2856 * Validate the push VLAN action.
2859 * Pointer to the rte_eth_dev structure.
2860 * @param[in] action_flags
2861 * Holds the actions detected until now.
2862 * @param[in] item_flags
2863 * The items found in this flow rule.
2865 * Pointer to the action structure.
2867 * Pointer to flow attributes
2869 * Pointer to error structure.
2872 * 0 on success, a negative errno value otherwise and rte_errno is set.
2875 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2876 uint64_t action_flags,
2877 const struct rte_flow_item_vlan *vlan_m,
2878 const struct rte_flow_action *action,
2879 const struct rte_flow_attr *attr,
2880 struct rte_flow_error *error)
2882 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2883 const struct mlx5_priv *priv = dev->data->dev_private;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 if (!attr->transfer && priv->representor)
2896 return rte_flow_error_set(error, ENOTSUP,
2897 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2898 "push vlan action for VF representor "
2899 "not supported on NIC table");
2901 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2902 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2903 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2904 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2905 !(mlx5_flow_find_action
2906 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2907 return rte_flow_error_set(error, EINVAL,
2908 RTE_FLOW_ERROR_TYPE_ACTION, action,
2909 "not full match mask on VLAN PCP and "
2910 "there is no of_set_vlan_pcp action, "
2911 "push VLAN action cannot figure out "
2914 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2915 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2916 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2917 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2918 !(mlx5_flow_find_action
2919 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2920 return rte_flow_error_set(error, EINVAL,
2921 RTE_FLOW_ERROR_TYPE_ACTION, action,
2922 "not full match mask on VLAN VID and "
2923 "there is no of_set_vlan_vid action, "
2924 "push VLAN action cannot figure out "
2931 * Validate the set VLAN PCP.
2933 * @param[in] action_flags
2934 * Holds the actions detected until now.
2935 * @param[in] actions
2936 * Pointer to the list of actions remaining in the flow rule.
2938 * Pointer to error structure.
2941 * 0 on success, a negative errno value otherwise and rte_errno is set.
2944 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2945 const struct rte_flow_action actions[],
2946 struct rte_flow_error *error)
2948 const struct rte_flow_action *action = actions;
2949 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2951 if (conf->vlan_pcp > 7)
2952 return rte_flow_error_set(error, EINVAL,
2953 RTE_FLOW_ERROR_TYPE_ACTION, action,
2954 "VLAN PCP value is too big");
2955 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2956 return rte_flow_error_set(error, ENOTSUP,
2957 RTE_FLOW_ERROR_TYPE_ACTION, action,
2958 "set VLAN PCP action must follow "
2959 "the push VLAN action");
2960 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2961 return rte_flow_error_set(error, ENOTSUP,
2962 RTE_FLOW_ERROR_TYPE_ACTION, action,
2963 "Multiple VLAN PCP modification are "
2965 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION, action,
2968 "wrong action order, port_id should "
2969 "be after set VLAN PCP");
2974 * Validate the set VLAN VID.
2976 * @param[in] item_flags
2977 * Holds the items detected in this rule.
2978 * @param[in] action_flags
2979 * Holds the actions detected until now.
2980 * @param[in] actions
2981 * Pointer to the list of actions remaining in the flow rule.
2983 * Pointer to error structure.
2986 * 0 on success, a negative errno value otherwise and rte_errno is set.
2989 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2990 uint64_t action_flags,
2991 const struct rte_flow_action actions[],
2992 struct rte_flow_error *error)
2994 const struct rte_flow_action *action = actions;
2995 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2997 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2998 return rte_flow_error_set(error, EINVAL,
2999 RTE_FLOW_ERROR_TYPE_ACTION, action,
3000 "VLAN VID value is too big");
3001 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3002 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3003 return rte_flow_error_set(error, ENOTSUP,
3004 RTE_FLOW_ERROR_TYPE_ACTION, action,
3005 "set VLAN VID action must follow push"
3006 " VLAN action or match on VLAN item");
3007 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3008 return rte_flow_error_set(error, ENOTSUP,
3009 RTE_FLOW_ERROR_TYPE_ACTION, action,
3010 "Multiple VLAN VID modifications are "
3012 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3013 return rte_flow_error_set(error, EINVAL,
3014 RTE_FLOW_ERROR_TYPE_ACTION, action,
3015 "wrong action order, port_id should "
3016 "be after set VLAN VID");
3021 * Validate the FLAG action.
3024 * Pointer to the rte_eth_dev structure.
3025 * @param[in] action_flags
3026 * Holds the actions detected until now.
3028 * Pointer to flow attributes
3030 * Pointer to error structure.
3033 * 0 on success, a negative errno value otherwise and rte_errno is set.
3036 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3037 uint64_t action_flags,
3038 const struct rte_flow_attr *attr,
3039 struct rte_flow_error *error)
3041 struct mlx5_priv *priv = dev->data->dev_private;
3042 struct mlx5_dev_config *config = &priv->config;
3045 /* Fall back if no extended metadata register support. */
3046 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3047 return mlx5_flow_validate_action_flag(action_flags, attr,
3049 /* Extensive metadata mode requires registers. */
3050 if (!mlx5_flow_ext_mreg_supported(dev))
3051 return rte_flow_error_set(error, ENOTSUP,
3052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3053 "no metadata registers "
3054 "to support flag action");
3055 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3056 return rte_flow_error_set(error, ENOTSUP,
3057 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3058 "extended metadata register"
3059 " isn't available");
3060 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3063 MLX5_ASSERT(ret > 0);
3064 if (action_flags & MLX5_FLOW_ACTION_MARK)
3065 return rte_flow_error_set(error, EINVAL,
3066 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3067 "can't mark and flag in same flow");
3068 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3069 return rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3072 " actions in same flow");
3077 * Validate MARK action.
3080 * Pointer to the rte_eth_dev structure.
3082 * Pointer to action.
3083 * @param[in] action_flags
3084 * Holds the actions detected until now.
3086 * Pointer to flow attributes
3088 * Pointer to error structure.
3091 * 0 on success, a negative errno value otherwise and rte_errno is set.
3094 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3095 const struct rte_flow_action *action,
3096 uint64_t action_flags,
3097 const struct rte_flow_attr *attr,
3098 struct rte_flow_error *error)
3100 struct mlx5_priv *priv = dev->data->dev_private;
3101 struct mlx5_dev_config *config = &priv->config;
3102 const struct rte_flow_action_mark *mark = action->conf;
3105 if (is_tunnel_offload_active(dev))
3106 return rte_flow_error_set(error, ENOTSUP,
3107 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3109 "if tunnel offload active");
3110 /* Fall back if no extended metadata register support. */
3111 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3112 return mlx5_flow_validate_action_mark(action, action_flags,
3114 /* Extensive metadata mode requires registers. */
3115 if (!mlx5_flow_ext_mreg_supported(dev))
3116 return rte_flow_error_set(error, ENOTSUP,
3117 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3118 "no metadata registers "
3119 "to support mark action");
3120 if (!priv->sh->dv_mark_mask)
3121 return rte_flow_error_set(error, ENOTSUP,
3122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123 "extended metadata register"
3124 " isn't available");
3125 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3128 MLX5_ASSERT(ret > 0);
3130 return rte_flow_error_set(error, EINVAL,
3131 RTE_FLOW_ERROR_TYPE_ACTION, action,
3132 "configuration cannot be null");
3133 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3134 return rte_flow_error_set(error, EINVAL,
3135 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3137 "mark id exceeds the limit");
3138 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3139 return rte_flow_error_set(error, EINVAL,
3140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3141 "can't flag and mark in same flow");
3142 if (action_flags & MLX5_FLOW_ACTION_MARK)
3143 return rte_flow_error_set(error, EINVAL,
3144 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3145 "can't have 2 mark actions in same"
3151 * Validate SET_META action.
3154 * Pointer to the rte_eth_dev structure.
3156 * Pointer to the action structure.
3157 * @param[in] action_flags
3158 * Holds the actions detected until now.
3160 * Pointer to flow attributes
3162 * Pointer to error structure.
3165 * 0 on success, a negative errno value otherwise and rte_errno is set.
3168 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3169 const struct rte_flow_action *action,
3170 uint64_t action_flags __rte_unused,
3171 const struct rte_flow_attr *attr,
3172 struct rte_flow_error *error)
3174 const struct rte_flow_action_set_meta *conf;
3175 uint32_t nic_mask = UINT32_MAX;
3178 if (!mlx5_flow_ext_mreg_supported(dev))
3179 return rte_flow_error_set(error, ENOTSUP,
3180 RTE_FLOW_ERROR_TYPE_ACTION, action,
3181 "extended metadata register"
3182 " isn't supported");
3183 reg = flow_dv_get_metadata_reg(dev, attr, error);
3187 return rte_flow_error_set(error, ENOTSUP,
3188 RTE_FLOW_ERROR_TYPE_ACTION, action,
3189 "unavalable extended metadata register");
3190 if (reg != REG_A && reg != REG_B) {
3191 struct mlx5_priv *priv = dev->data->dev_private;
3193 nic_mask = priv->sh->dv_meta_mask;
3195 if (!(action->conf))
3196 return rte_flow_error_set(error, EINVAL,
3197 RTE_FLOW_ERROR_TYPE_ACTION, action,
3198 "configuration cannot be null");
3199 conf = (const struct rte_flow_action_set_meta *)action->conf;
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION, action,
3203 "zero mask doesn't have any effect");
3204 if (conf->mask & ~nic_mask)
3205 return rte_flow_error_set(error, EINVAL,
3206 RTE_FLOW_ERROR_TYPE_ACTION, action,
3207 "meta data must be within reg C0");
3212 * Validate SET_TAG action.
3215 * Pointer to the rte_eth_dev structure.
3217 * Pointer to the action structure.
3218 * @param[in] action_flags
3219 * Holds the actions detected until now.
3221 * Pointer to flow attributes
3223 * Pointer to error structure.
3226 * 0 on success, a negative errno value otherwise and rte_errno is set.
3229 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3230 const struct rte_flow_action *action,
3231 uint64_t action_flags,
3232 const struct rte_flow_attr *attr,
3233 struct rte_flow_error *error)
3235 const struct rte_flow_action_set_tag *conf;
3236 const uint64_t terminal_action_flags =
3237 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3238 MLX5_FLOW_ACTION_RSS;
3241 if (!mlx5_flow_ext_mreg_supported(dev))
3242 return rte_flow_error_set(error, ENOTSUP,
3243 RTE_FLOW_ERROR_TYPE_ACTION, action,
3244 "extensive metadata register"
3245 " isn't supported");
3246 if (!(action->conf))
3247 return rte_flow_error_set(error, EINVAL,
3248 RTE_FLOW_ERROR_TYPE_ACTION, action,
3249 "configuration cannot be null");
3250 conf = (const struct rte_flow_action_set_tag *)action->conf;
3252 return rte_flow_error_set(error, EINVAL,
3253 RTE_FLOW_ERROR_TYPE_ACTION, action,
3254 "zero mask doesn't have any effect");
3255 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3258 if (!attr->transfer && attr->ingress &&
3259 (action_flags & terminal_action_flags))
3260 return rte_flow_error_set(error, EINVAL,
3261 RTE_FLOW_ERROR_TYPE_ACTION, action,
3262 "set_tag has no effect"
3263 " with terminal actions");
3268 * Check if action counter is shared by either old or new mechanism.
3271 * Pointer to the action structure.
3274 * True when counter is shared, false otherwise.
3277 is_shared_action_count(const struct rte_flow_action *action)
3279 const struct rte_flow_action_count *count =
3280 (const struct rte_flow_action_count *)action->conf;
3282 if ((int)action->type == MLX5_RTE_FLOW_ACTION_TYPE_COUNT)
3284 return !!(count && count->shared);
3288 * Validate count action.
3291 * Pointer to rte_eth_dev structure.
3293 * Indicator if action is shared.
3294 * @param[in] action_flags
3295 * Holds the actions detected until now.
3297 * Pointer to error structure.
3300 * 0 on success, a negative errno value otherwise and rte_errno is set.
3303 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3304 uint64_t action_flags,
3305 struct rte_flow_error *error)
3307 struct mlx5_priv *priv = dev->data->dev_private;
3309 if (!priv->config.devx)
3311 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3312 return rte_flow_error_set(error, EINVAL,
3313 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314 "duplicate count actions set");
3315 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3316 !priv->sh->flow_hit_aso_en)
3317 return rte_flow_error_set(error, EINVAL,
3318 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3319 "old age and shared count combination is not supported");
3320 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3324 return rte_flow_error_set
3326 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3328 "count action not supported");
3332 * Validate the L2 encap action.
3335 * Pointer to the rte_eth_dev structure.
3336 * @param[in] action_flags
3337 * Holds the actions detected until now.
3339 * Pointer to the action structure.
3341 * Pointer to flow attributes.
3343 * Pointer to error structure.
3346 * 0 on success, a negative errno value otherwise and rte_errno is set.
3349 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3350 uint64_t action_flags,
3351 const struct rte_flow_action *action,
3352 const struct rte_flow_attr *attr,
3353 struct rte_flow_error *error)
3355 const struct mlx5_priv *priv = dev->data->dev_private;
3357 if (!(action->conf))
3358 return rte_flow_error_set(error, EINVAL,
3359 RTE_FLOW_ERROR_TYPE_ACTION, action,
3360 "configuration cannot be null");
3361 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3362 return rte_flow_error_set(error, EINVAL,
3363 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3364 "can only have a single encap action "
3366 if (!attr->transfer && priv->representor)
3367 return rte_flow_error_set(error, ENOTSUP,
3368 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3369 "encap action for VF representor "
3370 "not supported on NIC table");
3375 * Validate a decap action.
3378 * Pointer to the rte_eth_dev structure.
3379 * @param[in] action_flags
3380 * Holds the actions detected until now.
3382 * Pointer to the action structure.
3383 * @param[in] item_flags
3384 * Holds the items detected.
3386 * Pointer to flow attributes
3388 * Pointer to error structure.
3391 * 0 on success, a negative errno value otherwise and rte_errno is set.
3394 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3395 uint64_t action_flags,
3396 const struct rte_flow_action *action,
3397 const uint64_t item_flags,
3398 const struct rte_flow_attr *attr,
3399 struct rte_flow_error *error)
3401 const struct mlx5_priv *priv = dev->data->dev_private;
3403 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3404 !priv->config.decap_en)
3405 return rte_flow_error_set(error, ENOTSUP,
3406 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3407 "decap is not enabled");
3408 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3409 return rte_flow_error_set(error, ENOTSUP,
3410 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3412 MLX5_FLOW_ACTION_DECAP ? "can only "
3413 "have a single decap action" : "decap "
3414 "after encap is not supported");
3415 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3416 return rte_flow_error_set(error, EINVAL,
3417 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3418 "can't have decap action after"
3421 return rte_flow_error_set(error, ENOTSUP,
3422 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3424 "decap action not supported for "
3426 if (!attr->transfer && priv->representor)
3427 return rte_flow_error_set(error, ENOTSUP,
3428 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3429 "decap action for VF representor "
3430 "not supported on NIC table");
3431 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3432 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3433 return rte_flow_error_set(error, ENOTSUP,
3434 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3435 "VXLAN item should be present for VXLAN decap");
3439 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3442 * Validate the raw encap and decap actions.
3445 * Pointer to the rte_eth_dev structure.
3447 * Pointer to the decap action.
3449 * Pointer to the encap action.
3451 * Pointer to flow attributes
3452 * @param[in/out] action_flags
3453 * Holds the actions detected until now.
3454 * @param[out] actions_n
3455 * pointer to the number of actions counter.
3457 * Pointer to the action structure.
3458 * @param[in] item_flags
3459 * Holds the items detected.
3461 * Pointer to error structure.
3464 * 0 on success, a negative errno value otherwise and rte_errno is set.
3467 flow_dv_validate_action_raw_encap_decap
3468 (struct rte_eth_dev *dev,
3469 const struct rte_flow_action_raw_decap *decap,
3470 const struct rte_flow_action_raw_encap *encap,
3471 const struct rte_flow_attr *attr, uint64_t *action_flags,
3472 int *actions_n, const struct rte_flow_action *action,
3473 uint64_t item_flags, struct rte_flow_error *error)
3475 const struct mlx5_priv *priv = dev->data->dev_private;
3478 if (encap && (!encap->size || !encap->data))
3479 return rte_flow_error_set(error, EINVAL,
3480 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3481 "raw encap data cannot be empty");
3482 if (decap && encap) {
3483 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3484 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3487 else if (encap->size <=
3488 MLX5_ENCAPSULATION_DECISION_SIZE &&
3490 MLX5_ENCAPSULATION_DECISION_SIZE)
3493 else if (encap->size >
3494 MLX5_ENCAPSULATION_DECISION_SIZE &&
3496 MLX5_ENCAPSULATION_DECISION_SIZE)
3497 /* 2 L2 actions: encap and decap. */
3500 return rte_flow_error_set(error,
3502 RTE_FLOW_ERROR_TYPE_ACTION,
3503 NULL, "unsupported too small "
3504 "raw decap and too small raw "
3505 "encap combination");
3508 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3509 item_flags, attr, error);
3512 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3516 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3517 return rte_flow_error_set(error, ENOTSUP,
3518 RTE_FLOW_ERROR_TYPE_ACTION,
3520 "small raw encap size");
3521 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3522 return rte_flow_error_set(error, EINVAL,
3523 RTE_FLOW_ERROR_TYPE_ACTION,
3525 "more than one encap action");
3526 if (!attr->transfer && priv->representor)
3527 return rte_flow_error_set
3529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3530 "encap action for VF representor "
3531 "not supported on NIC table");
3532 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3539 * Validate the ASO CT action.
3542 * Pointer to the rte_eth_dev structure.
3543 * @param[in] action_flags
3544 * Holds the actions detected until now.
3545 * @param[in] item_flags
3546 * The items found in this flow rule.
3548 * Pointer to flow attributes.
3550 * Pointer to error structure.
3553 * 0 on success, a negative errno value otherwise and rte_errno is set.
3556 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3557 uint64_t action_flags,
3558 uint64_t item_flags,
3559 const struct rte_flow_attr *attr,
3560 struct rte_flow_error *error)
3564 if (attr->group == 0 && !attr->transfer)
3565 return rte_flow_error_set(error, ENOTSUP,
3566 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3568 "Only support non-root table");
3569 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3570 return rte_flow_error_set(error, ENOTSUP,
3571 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3572 "CT cannot follow a fate action");
3573 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3574 (action_flags & MLX5_FLOW_ACTION_AGE))
3575 return rte_flow_error_set(error, EINVAL,
3576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3577 "Only one ASO action is supported");
3578 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3579 return rte_flow_error_set(error, EINVAL,
3580 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3581 "Encap cannot exist before CT");
3582 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3583 return rte_flow_error_set(error, EINVAL,
3584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3585 "Not a outer TCP packet");
3590 * Match encap_decap resource.
3593 * Pointer to the hash list.
3595 * Pointer to exist resource entry object.
3597 * Key of the new entry.
3599 * Pointer to new encap_decap resource.
3602 * 0 on matching, none-zero otherwise.
3605 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3606 struct mlx5_hlist_entry *entry,
3607 uint64_t key __rte_unused, void *cb_ctx)
3609 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3610 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3611 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3613 cache_resource = container_of(entry,
3614 struct mlx5_flow_dv_encap_decap_resource,
3616 if (resource->reformat_type == cache_resource->reformat_type &&
3617 resource->ft_type == cache_resource->ft_type &&
3618 resource->flags == cache_resource->flags &&
3619 resource->size == cache_resource->size &&
3620 !memcmp((const void *)resource->buf,
3621 (const void *)cache_resource->buf,
3628 * Allocate encap_decap resource.
3631 * Pointer to the hash list.
3633 * Pointer to exist resource entry object.
3635 * Pointer to new encap_decap resource.
3638 * 0 on matching, none-zero otherwise.
3640 struct mlx5_hlist_entry *
3641 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3642 uint64_t key __rte_unused,
3645 struct mlx5_dev_ctx_shared *sh = list->ctx;
3646 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3647 struct mlx5dv_dr_domain *domain;
3648 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3649 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3653 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3654 domain = sh->fdb_domain;
3655 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3656 domain = sh->rx_domain;
3658 domain = sh->tx_domain;
3659 /* Register new encap/decap resource. */
3660 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3662 if (!cache_resource) {
3663 rte_flow_error_set(ctx->error, ENOMEM,
3664 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3665 "cannot allocate resource memory");
3668 *cache_resource = *resource;
3669 cache_resource->idx = idx;
3670 ret = mlx5_flow_os_create_flow_action_packet_reformat
3671 (sh->ctx, domain, cache_resource,
3672 &cache_resource->action);
3674 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3675 rte_flow_error_set(ctx->error, ENOMEM,
3676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3677 NULL, "cannot create action");
3681 return &cache_resource->entry;
3685 * Find existing encap/decap resource or create and register a new one.
3687 * @param[in, out] dev
3688 * Pointer to rte_eth_dev structure.
3689 * @param[in, out] resource
3690 * Pointer to encap/decap resource.
3691 * @parm[in, out] dev_flow
3692 * Pointer to the dev_flow.
3694 * pointer to error structure.
3697 * 0 on success otherwise -errno and errno is set.
3700 flow_dv_encap_decap_resource_register
3701 (struct rte_eth_dev *dev,
3702 struct mlx5_flow_dv_encap_decap_resource *resource,
3703 struct mlx5_flow *dev_flow,
3704 struct rte_flow_error *error)
3706 struct mlx5_priv *priv = dev->data->dev_private;
3707 struct mlx5_dev_ctx_shared *sh = priv->sh;
3708 struct mlx5_hlist_entry *entry;
3712 uint32_t refmt_type:8;
3714 * Header reformat actions can be shared between
3715 * non-root tables. One bit to indicate non-root
3719 uint32_t reserve:15;
3722 } encap_decap_key = {
3724 .ft_type = resource->ft_type,
3725 .refmt_type = resource->reformat_type,
3726 .is_root = !!dev_flow->dv.group,
3730 struct mlx5_flow_cb_ctx ctx = {
3736 resource->flags = dev_flow->dv.group ? 0 : 1;
3737 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3738 sizeof(encap_decap_key.v32), 0);
3739 if (resource->reformat_type !=
3740 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3742 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3743 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3746 resource = container_of(entry, typeof(*resource), entry);
3747 dev_flow->dv.encap_decap = resource;
3748 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3753 * Find existing table jump resource or create and register a new one.
3755 * @param[in, out] dev
3756 * Pointer to rte_eth_dev structure.
3757 * @param[in, out] tbl
3758 * Pointer to flow table resource.
3759 * @parm[in, out] dev_flow
3760 * Pointer to the dev_flow.
3762 * pointer to error structure.
3765 * 0 on success otherwise -errno and errno is set.
3768 flow_dv_jump_tbl_resource_register
3769 (struct rte_eth_dev *dev __rte_unused,
3770 struct mlx5_flow_tbl_resource *tbl,
3771 struct mlx5_flow *dev_flow,
3772 struct rte_flow_error *error __rte_unused)
3774 struct mlx5_flow_tbl_data_entry *tbl_data =
3775 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3778 MLX5_ASSERT(tbl_data->jump.action);
3779 dev_flow->handle->rix_jump = tbl_data->idx;
3780 dev_flow->dv.jump = &tbl_data->jump;
3785 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3786 struct mlx5_cache_entry *entry, void *cb_ctx)
3788 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3789 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3790 struct mlx5_flow_dv_port_id_action_resource *res =
3791 container_of(entry, typeof(*res), entry);
3793 return ref->port_id != res->port_id;
3796 struct mlx5_cache_entry *
3797 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3798 struct mlx5_cache_entry *entry __rte_unused,
3801 struct mlx5_dev_ctx_shared *sh = list->ctx;
3802 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3803 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3804 struct mlx5_flow_dv_port_id_action_resource *cache;
3808 /* Register new port id action resource. */
3809 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3811 rte_flow_error_set(ctx->error, ENOMEM,
3812 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3813 "cannot allocate port_id action cache memory");
3817 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3821 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3822 rte_flow_error_set(ctx->error, ENOMEM,
3823 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3824 "cannot create action");
3828 return &cache->entry;
3832 * Find existing table port ID resource or create and register a new one.
3834 * @param[in, out] dev
3835 * Pointer to rte_eth_dev structure.
3836 * @param[in, out] resource
3837 * Pointer to port ID action resource.
3838 * @parm[in, out] dev_flow
3839 * Pointer to the dev_flow.
3841 * pointer to error structure.
3844 * 0 on success otherwise -errno and errno is set.
3847 flow_dv_port_id_action_resource_register
3848 (struct rte_eth_dev *dev,
3849 struct mlx5_flow_dv_port_id_action_resource *resource,
3850 struct mlx5_flow *dev_flow,
3851 struct rte_flow_error *error)
3853 struct mlx5_priv *priv = dev->data->dev_private;
3854 struct mlx5_cache_entry *entry;
3855 struct mlx5_flow_dv_port_id_action_resource *cache;
3856 struct mlx5_flow_cb_ctx ctx = {
3861 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3864 cache = container_of(entry, typeof(*cache), entry);
3865 dev_flow->dv.port_id_action = cache;
3866 dev_flow->handle->rix_port_id_action = cache->idx;
3871 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3872 struct mlx5_cache_entry *entry, void *cb_ctx)
3874 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3875 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3876 struct mlx5_flow_dv_push_vlan_action_resource *res =
3877 container_of(entry, typeof(*res), entry);
3879 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3882 struct mlx5_cache_entry *
3883 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3884 struct mlx5_cache_entry *entry __rte_unused,
3887 struct mlx5_dev_ctx_shared *sh = list->ctx;
3888 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3889 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3890 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3891 struct mlx5dv_dr_domain *domain;
3895 /* Register new port id action resource. */
3896 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3898 rte_flow_error_set(ctx->error, ENOMEM,
3899 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3900 "cannot allocate push_vlan action cache memory");
3904 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3905 domain = sh->fdb_domain;
3906 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3907 domain = sh->rx_domain;
3909 domain = sh->tx_domain;
3910 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3913 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3914 rte_flow_error_set(ctx->error, ENOMEM,
3915 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3916 "cannot create push vlan action");
3920 return &cache->entry;
3924 * Find existing push vlan resource or create and register a new one.
3926 * @param [in, out] dev
3927 * Pointer to rte_eth_dev structure.
3928 * @param[in, out] resource
3929 * Pointer to port ID action resource.
3930 * @parm[in, out] dev_flow
3931 * Pointer to the dev_flow.
3933 * pointer to error structure.
3936 * 0 on success otherwise -errno and errno is set.
3939 flow_dv_push_vlan_action_resource_register
3940 (struct rte_eth_dev *dev,
3941 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3942 struct mlx5_flow *dev_flow,
3943 struct rte_flow_error *error)
3945 struct mlx5_priv *priv = dev->data->dev_private;
3946 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3947 struct mlx5_cache_entry *entry;
3948 struct mlx5_flow_cb_ctx ctx = {
3953 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3956 cache = container_of(entry, typeof(*cache), entry);
3958 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3959 dev_flow->dv.push_vlan_res = cache;
3964 * Get the size of specific rte_flow_item_type hdr size
3966 * @param[in] item_type
3967 * Tested rte_flow_item_type.
3970 * sizeof struct item_type, 0 if void or irrelevant.
3973 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3977 switch (item_type) {
3978 case RTE_FLOW_ITEM_TYPE_ETH:
3979 retval = sizeof(struct rte_ether_hdr);
3981 case RTE_FLOW_ITEM_TYPE_VLAN:
3982 retval = sizeof(struct rte_vlan_hdr);
3984 case RTE_FLOW_ITEM_TYPE_IPV4:
3985 retval = sizeof(struct rte_ipv4_hdr);
3987 case RTE_FLOW_ITEM_TYPE_IPV6:
3988 retval = sizeof(struct rte_ipv6_hdr);
3990 case RTE_FLOW_ITEM_TYPE_UDP:
3991 retval = sizeof(struct rte_udp_hdr);
3993 case RTE_FLOW_ITEM_TYPE_TCP:
3994 retval = sizeof(struct rte_tcp_hdr);
3996 case RTE_FLOW_ITEM_TYPE_VXLAN:
3997 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3998 retval = sizeof(struct rte_vxlan_hdr);
4000 case RTE_FLOW_ITEM_TYPE_GRE:
4001 case RTE_FLOW_ITEM_TYPE_NVGRE:
4002 retval = sizeof(struct rte_gre_hdr);
4004 case RTE_FLOW_ITEM_TYPE_MPLS:
4005 retval = sizeof(struct rte_mpls_hdr);
4007 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4015 #define MLX5_ENCAP_IPV4_VERSION 0x40
4016 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4017 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4018 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4019 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4020 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4021 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4024 * Convert the encap action data from list of rte_flow_item to raw buffer
4027 * Pointer to rte_flow_item objects list.
4029 * Pointer to the output buffer.
4031 * Pointer to the output buffer size.
4033 * Pointer to the error structure.
4036 * 0 on success, a negative errno value otherwise and rte_errno is set.
4039 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4040 size_t *size, struct rte_flow_error *error)
4042 struct rte_ether_hdr *eth = NULL;
4043 struct rte_vlan_hdr *vlan = NULL;
4044 struct rte_ipv4_hdr *ipv4 = NULL;
4045 struct rte_ipv6_hdr *ipv6 = NULL;
4046 struct rte_udp_hdr *udp = NULL;
4047 struct rte_vxlan_hdr *vxlan = NULL;
4048 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4049 struct rte_gre_hdr *gre = NULL;
4051 size_t temp_size = 0;
4054 return rte_flow_error_set(error, EINVAL,
4055 RTE_FLOW_ERROR_TYPE_ACTION,
4056 NULL, "invalid empty data");
4057 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4058 len = flow_dv_get_item_hdr_len(items->type);
4059 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4060 return rte_flow_error_set(error, EINVAL,
4061 RTE_FLOW_ERROR_TYPE_ACTION,
4062 (void *)items->type,
4063 "items total size is too big"
4064 " for encap action");
4065 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4066 switch (items->type) {
4067 case RTE_FLOW_ITEM_TYPE_ETH:
4068 eth = (struct rte_ether_hdr *)&buf[temp_size];
4070 case RTE_FLOW_ITEM_TYPE_VLAN:
4071 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4073 return rte_flow_error_set(error, EINVAL,
4074 RTE_FLOW_ERROR_TYPE_ACTION,
4075 (void *)items->type,
4076 "eth header not found");
4077 if (!eth->ether_type)
4078 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4080 case RTE_FLOW_ITEM_TYPE_IPV4:
4081 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4083 return rte_flow_error_set(error, EINVAL,
4084 RTE_FLOW_ERROR_TYPE_ACTION,
4085 (void *)items->type,
4086 "neither eth nor vlan"
4088 if (vlan && !vlan->eth_proto)
4089 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4090 else if (eth && !eth->ether_type)
4091 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4092 if (!ipv4->version_ihl)
4093 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4094 MLX5_ENCAP_IPV4_IHL_MIN;
4095 if (!ipv4->time_to_live)
4096 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4098 case RTE_FLOW_ITEM_TYPE_IPV6:
4099 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4101 return rte_flow_error_set(error, EINVAL,
4102 RTE_FLOW_ERROR_TYPE_ACTION,
4103 (void *)items->type,
4104 "neither eth nor vlan"
4106 if (vlan && !vlan->eth_proto)
4107 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4108 else if (eth && !eth->ether_type)
4109 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4110 if (!ipv6->vtc_flow)
4112 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4113 if (!ipv6->hop_limits)
4114 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4116 case RTE_FLOW_ITEM_TYPE_UDP:
4117 udp = (struct rte_udp_hdr *)&buf[temp_size];
4119 return rte_flow_error_set(error, EINVAL,
4120 RTE_FLOW_ERROR_TYPE_ACTION,
4121 (void *)items->type,
4122 "ip header not found");
4123 if (ipv4 && !ipv4->next_proto_id)
4124 ipv4->next_proto_id = IPPROTO_UDP;
4125 else if (ipv6 && !ipv6->proto)
4126 ipv6->proto = IPPROTO_UDP;
4128 case RTE_FLOW_ITEM_TYPE_VXLAN:
4129 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4131 return rte_flow_error_set(error, EINVAL,
4132 RTE_FLOW_ERROR_TYPE_ACTION,
4133 (void *)items->type,
4134 "udp header not found");
4136 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4137 if (!vxlan->vx_flags)
4139 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4141 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4142 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4144 return rte_flow_error_set(error, EINVAL,
4145 RTE_FLOW_ERROR_TYPE_ACTION,
4146 (void *)items->type,
4147 "udp header not found");
4148 if (!vxlan_gpe->proto)
4149 return rte_flow_error_set(error, EINVAL,
4150 RTE_FLOW_ERROR_TYPE_ACTION,
4151 (void *)items->type,
4152 "next protocol not found");
4155 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4156 if (!vxlan_gpe->vx_flags)
4157 vxlan_gpe->vx_flags =
4158 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4160 case RTE_FLOW_ITEM_TYPE_GRE:
4161 case RTE_FLOW_ITEM_TYPE_NVGRE:
4162 gre = (struct rte_gre_hdr *)&buf[temp_size];
4164 return rte_flow_error_set(error, EINVAL,
4165 RTE_FLOW_ERROR_TYPE_ACTION,
4166 (void *)items->type,
4167 "next protocol not found");
4169 return rte_flow_error_set(error, EINVAL,
4170 RTE_FLOW_ERROR_TYPE_ACTION,
4171 (void *)items->type,
4172 "ip header not found");
4173 if (ipv4 && !ipv4->next_proto_id)
4174 ipv4->next_proto_id = IPPROTO_GRE;
4175 else if (ipv6 && !ipv6->proto)
4176 ipv6->proto = IPPROTO_GRE;
4178 case RTE_FLOW_ITEM_TYPE_VOID:
4181 return rte_flow_error_set(error, EINVAL,
4182 RTE_FLOW_ERROR_TYPE_ACTION,
4183 (void *)items->type,
4184 "unsupported item type");
4194 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4196 struct rte_ether_hdr *eth = NULL;
4197 struct rte_vlan_hdr *vlan = NULL;
4198 struct rte_ipv6_hdr *ipv6 = NULL;
4199 struct rte_udp_hdr *udp = NULL;
4203 eth = (struct rte_ether_hdr *)data;
4204 next_hdr = (char *)(eth + 1);
4205 proto = RTE_BE16(eth->ether_type);
4208 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4209 vlan = (struct rte_vlan_hdr *)next_hdr;
4210 proto = RTE_BE16(vlan->eth_proto);
4211 next_hdr += sizeof(struct rte_vlan_hdr);
4214 /* HW calculates IPv4 csum. no need to proceed */
4215 if (proto == RTE_ETHER_TYPE_IPV4)
4218 /* non IPv4/IPv6 header. not supported */
4219 if (proto != RTE_ETHER_TYPE_IPV6) {
4220 return rte_flow_error_set(error, ENOTSUP,
4221 RTE_FLOW_ERROR_TYPE_ACTION,
4222 NULL, "Cannot offload non IPv4/IPv6");
4225 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4227 /* ignore non UDP */
4228 if (ipv6->proto != IPPROTO_UDP)
4231 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4232 udp->dgram_cksum = 0;
4238 * Convert L2 encap action to DV specification.
4241 * Pointer to rte_eth_dev structure.
4243 * Pointer to action structure.
4244 * @param[in, out] dev_flow
4245 * Pointer to the mlx5_flow.
4246 * @param[in] transfer
4247 * Mark if the flow is E-Switch flow.
4249 * Pointer to the error structure.
4252 * 0 on success, a negative errno value otherwise and rte_errno is set.
4255 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4256 const struct rte_flow_action *action,
4257 struct mlx5_flow *dev_flow,
4259 struct rte_flow_error *error)
4261 const struct rte_flow_item *encap_data;
4262 const struct rte_flow_action_raw_encap *raw_encap_data;
4263 struct mlx5_flow_dv_encap_decap_resource res = {
4265 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4266 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4267 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4270 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4272 (const struct rte_flow_action_raw_encap *)action->conf;
4273 res.size = raw_encap_data->size;
4274 memcpy(res.buf, raw_encap_data->data, res.size);
4276 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4278 ((const struct rte_flow_action_vxlan_encap *)
4279 action->conf)->definition;
4282 ((const struct rte_flow_action_nvgre_encap *)
4283 action->conf)->definition;
4284 if (flow_dv_convert_encap_data(encap_data, res.buf,
4288 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4290 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4291 return rte_flow_error_set(error, EINVAL,
4292 RTE_FLOW_ERROR_TYPE_ACTION,
4293 NULL, "can't create L2 encap action");
4298 * Convert L2 decap action to DV specification.
4301 * Pointer to rte_eth_dev structure.
4302 * @param[in, out] dev_flow
4303 * Pointer to the mlx5_flow.
4304 * @param[in] transfer
4305 * Mark if the flow is E-Switch flow.
4307 * Pointer to the error structure.
4310 * 0 on success, a negative errno value otherwise and rte_errno is set.
4313 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4314 struct mlx5_flow *dev_flow,
4316 struct rte_flow_error *error)
4318 struct mlx5_flow_dv_encap_decap_resource res = {
4321 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4322 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4323 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4326 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4327 return rte_flow_error_set(error, EINVAL,
4328 RTE_FLOW_ERROR_TYPE_ACTION,
4329 NULL, "can't create L2 decap action");
4334 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4337 * Pointer to rte_eth_dev structure.
4339 * Pointer to action structure.
4340 * @param[in, out] dev_flow
4341 * Pointer to the mlx5_flow.
4343 * Pointer to the flow attributes.
4345 * Pointer to the error structure.
4348 * 0 on success, a negative errno value otherwise and rte_errno is set.
4351 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4352 const struct rte_flow_action *action,
4353 struct mlx5_flow *dev_flow,
4354 const struct rte_flow_attr *attr,
4355 struct rte_flow_error *error)
4357 const struct rte_flow_action_raw_encap *encap_data;
4358 struct mlx5_flow_dv_encap_decap_resource res;
4360 memset(&res, 0, sizeof(res));
4361 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4362 res.size = encap_data->size;
4363 memcpy(res.buf, encap_data->data, res.size);
4364 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4365 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4366 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4368 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4370 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4371 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4372 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4373 return rte_flow_error_set(error, EINVAL,
4374 RTE_FLOW_ERROR_TYPE_ACTION,
4375 NULL, "can't create encap action");
4380 * Create action push VLAN.
4383 * Pointer to rte_eth_dev structure.
4385 * Pointer to the flow attributes.
4387 * Pointer to the vlan to push to the Ethernet header.
4388 * @param[in, out] dev_flow
4389 * Pointer to the mlx5_flow.
4391 * Pointer to the error structure.
4394 * 0 on success, a negative errno value otherwise and rte_errno is set.
4397 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4398 const struct rte_flow_attr *attr,
4399 const struct rte_vlan_hdr *vlan,
4400 struct mlx5_flow *dev_flow,
4401 struct rte_flow_error *error)
4403 struct mlx5_flow_dv_push_vlan_action_resource res;
4405 memset(&res, 0, sizeof(res));
4407 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4410 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4412 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4413 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4414 return flow_dv_push_vlan_action_resource_register
4415 (dev, &res, dev_flow, error);
4419 * Validate the modify-header actions.
4421 * @param[in] action_flags
4422 * Holds the actions detected until now.
4424 * Pointer to the modify action.
4426 * Pointer to error structure.
4429 * 0 on success, a negative errno value otherwise and rte_errno is set.
4432 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4433 const struct rte_flow_action *action,
4434 struct rte_flow_error *error)
4436 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4437 return rte_flow_error_set(error, EINVAL,
4438 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4439 NULL, "action configuration not set");
4440 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4441 return rte_flow_error_set(error, EINVAL,
4442 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4443 "can't have encap action before"
4449 * Validate the modify-header MAC address actions.
4451 * @param[in] action_flags
4452 * Holds the actions detected until now.
4454 * Pointer to the modify action.
4455 * @param[in] item_flags
4456 * Holds the items detected.
4458 * Pointer to error structure.
4461 * 0 on success, a negative errno value otherwise and rte_errno is set.
4464 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4465 const struct rte_flow_action *action,
4466 const uint64_t item_flags,
4467 struct rte_flow_error *error)
4471 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4473 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4474 return rte_flow_error_set(error, EINVAL,
4475 RTE_FLOW_ERROR_TYPE_ACTION,
4477 "no L2 item in pattern");
4483 * Validate the modify-header IPv4 address actions.
4485 * @param[in] action_flags
4486 * Holds the actions detected until now.
4488 * Pointer to the modify action.
4489 * @param[in] item_flags
4490 * Holds the items detected.
4492 * Pointer to error structure.
4495 * 0 on success, a negative errno value otherwise and rte_errno is set.
4498 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4499 const struct rte_flow_action *action,
4500 const uint64_t item_flags,
4501 struct rte_flow_error *error)
4506 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4508 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4509 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4510 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4511 if (!(item_flags & layer))
4512 return rte_flow_error_set(error, EINVAL,
4513 RTE_FLOW_ERROR_TYPE_ACTION,
4515 "no ipv4 item in pattern");
4521 * Validate the modify-header IPv6 address actions.
4523 * @param[in] action_flags
4524 * Holds the actions detected until now.
4526 * Pointer to the modify action.
4527 * @param[in] item_flags
4528 * Holds the items detected.
4530 * Pointer to error structure.
4533 * 0 on success, a negative errno value otherwise and rte_errno is set.
4536 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4537 const struct rte_flow_action *action,
4538 const uint64_t item_flags,
4539 struct rte_flow_error *error)
4544 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4546 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4547 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4548 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4549 if (!(item_flags & layer))
4550 return rte_flow_error_set(error, EINVAL,
4551 RTE_FLOW_ERROR_TYPE_ACTION,
4553 "no ipv6 item in pattern");
4559 * Validate the modify-header TP actions.
4561 * @param[in] action_flags
4562 * Holds the actions detected until now.
4564 * Pointer to the modify action.
4565 * @param[in] item_flags
4566 * Holds the items detected.
4568 * Pointer to error structure.
4571 * 0 on success, a negative errno value otherwise and rte_errno is set.
4574 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4575 const struct rte_flow_action *action,
4576 const uint64_t item_flags,
4577 struct rte_flow_error *error)
4582 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4584 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4585 MLX5_FLOW_LAYER_INNER_L4 :
4586 MLX5_FLOW_LAYER_OUTER_L4;
4587 if (!(item_flags & layer))
4588 return rte_flow_error_set(error, EINVAL,
4589 RTE_FLOW_ERROR_TYPE_ACTION,
4590 NULL, "no transport layer "
4597 * Validate the modify-header actions of increment/decrement
4598 * TCP Sequence-number.
4600 * @param[in] action_flags
4601 * Holds the actions detected until now.
4603 * Pointer to the modify action.
4604 * @param[in] item_flags
4605 * Holds the items detected.
4607 * Pointer to error structure.
4610 * 0 on success, a negative errno value otherwise and rte_errno is set.
4613 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4614 const struct rte_flow_action *action,
4615 const uint64_t item_flags,
4616 struct rte_flow_error *error)
4621 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4623 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4624 MLX5_FLOW_LAYER_INNER_L4_TCP :
4625 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4626 if (!(item_flags & layer))
4627 return rte_flow_error_set(error, EINVAL,
4628 RTE_FLOW_ERROR_TYPE_ACTION,
4629 NULL, "no TCP item in"
4631 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4632 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4633 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4634 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4635 return rte_flow_error_set(error, EINVAL,
4636 RTE_FLOW_ERROR_TYPE_ACTION,
4638 "cannot decrease and increase"
4639 " TCP sequence number"
4640 " at the same time");
4646 * Validate the modify-header actions of increment/decrement
4647 * TCP Acknowledgment number.
4649 * @param[in] action_flags
4650 * Holds the actions detected until now.
4652 * Pointer to the modify action.
4653 * @param[in] item_flags
4654 * Holds the items detected.
4656 * Pointer to error structure.
4659 * 0 on success, a negative errno value otherwise and rte_errno is set.
4662 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4663 const struct rte_flow_action *action,
4664 const uint64_t item_flags,
4665 struct rte_flow_error *error)
4670 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4672 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4673 MLX5_FLOW_LAYER_INNER_L4_TCP :
4674 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4675 if (!(item_flags & layer))
4676 return rte_flow_error_set(error, EINVAL,
4677 RTE_FLOW_ERROR_TYPE_ACTION,
4678 NULL, "no TCP item in"
4680 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4681 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4682 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4683 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4684 return rte_flow_error_set(error, EINVAL,
4685 RTE_FLOW_ERROR_TYPE_ACTION,
4687 "cannot decrease and increase"
4688 " TCP acknowledgment number"
4689 " at the same time");
4695 * Validate the modify-header TTL actions.
4697 * @param[in] action_flags
4698 * Holds the actions detected until now.
4700 * Pointer to the modify action.
4701 * @param[in] item_flags
4702 * Holds the items detected.
4704 * Pointer to error structure.
4707 * 0 on success, a negative errno value otherwise and rte_errno is set.
4710 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4711 const struct rte_flow_action *action,
4712 const uint64_t item_flags,
4713 struct rte_flow_error *error)
4718 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4720 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4721 MLX5_FLOW_LAYER_INNER_L3 :
4722 MLX5_FLOW_LAYER_OUTER_L3;
4723 if (!(item_flags & layer))
4724 return rte_flow_error_set(error, EINVAL,
4725 RTE_FLOW_ERROR_TYPE_ACTION,
4727 "no IP protocol in pattern");
4733 * Validate the generic modify field actions.
4735 * Pointer to the rte_eth_dev structure.
4736 * @param[in] action_flags
4737 * Holds the actions detected until now.
4739 * Pointer to the modify action.
4741 * Pointer to the flow attributes.
4743 * Pointer to error structure.
4746 * Number of header fields to modify (0 or more) on success,
4747 * a negative errno value otherwise and rte_errno is set.
4750 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4751 const uint64_t action_flags,
4752 const struct rte_flow_action *action,
4753 const struct rte_flow_attr *attr,
4754 struct rte_flow_error *error)
4757 struct mlx5_priv *priv = dev->data->dev_private;
4758 struct mlx5_dev_config *config = &priv->config;
4759 const struct rte_flow_action_modify_field *action_modify_field =
4761 uint32_t dst_width = mlx5_flow_item_field_width(config,
4762 action_modify_field->dst.field);
4763 uint32_t src_width = mlx5_flow_item_field_width(config,
4764 action_modify_field->src.field);
4766 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4770 if (action_modify_field->width == 0)
4771 return rte_flow_error_set(error, EINVAL,
4772 RTE_FLOW_ERROR_TYPE_ACTION, action,
4773 "no bits are requested to be modified");
4774 else if (action_modify_field->width > dst_width ||
4775 action_modify_field->width > src_width)
4776 return rte_flow_error_set(error, EINVAL,
4777 RTE_FLOW_ERROR_TYPE_ACTION, action,
4778 "cannot modify more bits than"
4779 " the width of a field");
4780 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4781 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4782 if ((action_modify_field->dst.offset +
4783 action_modify_field->width > dst_width) ||
4784 (action_modify_field->dst.offset % 32))
4785 return rte_flow_error_set(error, EINVAL,
4786 RTE_FLOW_ERROR_TYPE_ACTION, action,
4787 "destination offset is too big"
4788 " or not aligned to 4 bytes");
4789 if (action_modify_field->dst.level &&
4790 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4791 return rte_flow_error_set(error, ENOTSUP,
4792 RTE_FLOW_ERROR_TYPE_ACTION, action,
4793 "inner header fields modification"
4794 " is not supported");
4796 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4797 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4798 if (!attr->transfer && !attr->group)
4799 return rte_flow_error_set(error, ENOTSUP,
4800 RTE_FLOW_ERROR_TYPE_ACTION, action,
4801 "modify field action is not"
4802 " supported for group 0");
4803 if ((action_modify_field->src.offset +
4804 action_modify_field->width > src_width) ||
4805 (action_modify_field->src.offset % 32))
4806 return rte_flow_error_set(error, EINVAL,
4807 RTE_FLOW_ERROR_TYPE_ACTION, action,
4808 "source offset is too big"
4809 " or not aligned to 4 bytes");
4810 if (action_modify_field->src.level &&
4811 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4812 return rte_flow_error_set(error, ENOTSUP,
4813 RTE_FLOW_ERROR_TYPE_ACTION, action,
4814 "inner header fields modification"
4815 " is not supported");
4817 if ((action_modify_field->dst.field ==
4818 action_modify_field->src.field) &&
4819 (action_modify_field->dst.level ==
4820 action_modify_field->src.level))
4821 return rte_flow_error_set(error, EINVAL,
4822 RTE_FLOW_ERROR_TYPE_ACTION, action,
4823 "source and destination fields"
4824 " cannot be the same");
4825 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4826 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4827 return rte_flow_error_set(error, EINVAL,
4828 RTE_FLOW_ERROR_TYPE_ACTION, action,
4829 "immediate value or a pointer to it"
4830 " cannot be used as a destination");
4831 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4832 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4833 return rte_flow_error_set(error, ENOTSUP,
4834 RTE_FLOW_ERROR_TYPE_ACTION, action,
4835 "modifications of an arbitrary"
4836 " place in a packet is not supported");
4837 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4838 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4839 return rte_flow_error_set(error, ENOTSUP,
4840 RTE_FLOW_ERROR_TYPE_ACTION, action,
4841 "modifications of the 802.1Q Tag"
4842 " Identifier is not supported");
4843 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4844 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4845 return rte_flow_error_set(error, ENOTSUP,
4846 RTE_FLOW_ERROR_TYPE_ACTION, action,
4847 "modifications of the VXLAN Network"
4848 " Identifier is not supported");
4849 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4850 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4851 return rte_flow_error_set(error, ENOTSUP,
4852 RTE_FLOW_ERROR_TYPE_ACTION, action,
4853 "modifications of the GENEVE Network"
4854 " Identifier is not supported");
4855 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4856 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4857 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4858 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4859 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4860 !mlx5_flow_ext_mreg_supported(dev))
4861 return rte_flow_error_set(error, ENOTSUP,
4862 RTE_FLOW_ERROR_TYPE_ACTION, action,
4863 "cannot modify mark or metadata without"
4864 " extended metadata register support");
4866 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4867 return rte_flow_error_set(error, ENOTSUP,
4868 RTE_FLOW_ERROR_TYPE_ACTION, action,
4869 "add and sub operations"
4870 " are not supported");
4871 return (action_modify_field->width / 32) +
4872 !!(action_modify_field->width % 32);
4876 * Validate jump action.
4879 * Pointer to the jump action.
4880 * @param[in] action_flags
4881 * Holds the actions detected until now.
4882 * @param[in] attributes
4883 * Pointer to flow attributes
4884 * @param[in] external
4885 * Action belongs to flow rule created by request external to PMD.
4887 * Pointer to error structure.
4890 * 0 on success, a negative errno value otherwise and rte_errno is set.
4893 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4894 const struct mlx5_flow_tunnel *tunnel,
4895 const struct rte_flow_action *action,
4896 uint64_t action_flags,
4897 const struct rte_flow_attr *attributes,
4898 bool external, struct rte_flow_error *error)
4900 uint32_t target_group, table;
4902 struct flow_grp_info grp_info = {
4903 .external = !!external,
4904 .transfer = !!attributes->transfer,
4908 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4909 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4910 return rte_flow_error_set(error, EINVAL,
4911 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4912 "can't have 2 fate actions in"
4915 return rte_flow_error_set(error, EINVAL,
4916 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4917 NULL, "action configuration not set");
4919 ((const struct rte_flow_action_jump *)action->conf)->group;
4920 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4924 if (attributes->group == target_group &&
4925 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4926 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4927 return rte_flow_error_set(error, EINVAL,
4928 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4929 "target group must be other than"
4930 " the current flow group");
4935 * Validate the port_id action.
4938 * Pointer to rte_eth_dev structure.
4939 * @param[in] action_flags
4940 * Bit-fields that holds the actions detected until now.
4942 * Port_id RTE action structure.
4944 * Attributes of flow that includes this action.
4946 * Pointer to error structure.
4949 * 0 on success, a negative errno value otherwise and rte_errno is set.
4952 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4953 uint64_t action_flags,
4954 const struct rte_flow_action *action,
4955 const struct rte_flow_attr *attr,
4956 struct rte_flow_error *error)
4958 const struct rte_flow_action_port_id *port_id;
4959 struct mlx5_priv *act_priv;
4960 struct mlx5_priv *dev_priv;
4963 if (!attr->transfer)
4964 return rte_flow_error_set(error, ENOTSUP,
4965 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4967 "port id action is valid in transfer"
4969 if (!action || !action->conf)
4970 return rte_flow_error_set(error, ENOTSUP,
4971 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4973 "port id action parameters must be"
4975 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4976 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4977 return rte_flow_error_set(error, EINVAL,
4978 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4979 "can have only one fate actions in"
4981 dev_priv = mlx5_dev_to_eswitch_info(dev);
4983 return rte_flow_error_set(error, rte_errno,
4984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4986 "failed to obtain E-Switch info");
4987 port_id = action->conf;
4988 port = port_id->original ? dev->data->port_id : port_id->id;
4989 act_priv = mlx5_port_to_eswitch_info(port, false);
4991 return rte_flow_error_set
4993 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4994 "failed to obtain E-Switch port id for port");
4995 if (act_priv->domain_id != dev_priv->domain_id)
4996 return rte_flow_error_set
4998 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4999 "port does not belong to"
5000 " E-Switch being configured");
5005 * Get the maximum number of modify header actions.
5008 * Pointer to rte_eth_dev structure.
5010 * Flags bits to check if root level.
5013 * Max number of modify header actions device can support.
5015 static inline unsigned int
5016 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5020 * There's no way to directly query the max capacity from FW.
5021 * The maximal value on root table should be assumed to be supported.
5023 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
5024 return MLX5_MAX_MODIFY_NUM;
5026 return MLX5_ROOT_TBL_MODIFY_NUM;
5030 * Validate the meter action.
5033 * Pointer to rte_eth_dev structure.
5034 * @param[in] action_flags
5035 * Bit-fields that holds the actions detected until now.
5037 * Pointer to the meter action.
5039 * Attributes of flow that includes this action.
5040 * @param[in] port_id_item
5041 * Pointer to item indicating port id.
5043 * Pointer to error structure.
5046 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5049 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5050 uint64_t action_flags,
5051 const struct rte_flow_action *action,
5052 const struct rte_flow_attr *attr,
5053 const struct rte_flow_item *port_id_item,
5055 struct rte_flow_error *error)
5057 struct mlx5_priv *priv = dev->data->dev_private;
5058 const struct rte_flow_action_meter *am = action->conf;
5059 struct mlx5_flow_meter_info *fm;
5060 struct mlx5_flow_meter_policy *mtr_policy;
5061 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5064 return rte_flow_error_set(error, EINVAL,
5065 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5066 "meter action conf is NULL");
5068 if (action_flags & MLX5_FLOW_ACTION_METER)
5069 return rte_flow_error_set(error, ENOTSUP,
5070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5071 "meter chaining not support");
5072 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5073 return rte_flow_error_set(error, ENOTSUP,
5074 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5075 "meter with jump not support");
5077 return rte_flow_error_set(error, ENOTSUP,
5078 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5080 "meter action not supported");
5081 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5083 return rte_flow_error_set(error, EINVAL,
5084 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5086 /* aso meter can always be shared by different domains */
5087 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5088 !(fm->transfer == attr->transfer ||
5089 (!fm->ingress && !attr->ingress && attr->egress) ||
5090 (!fm->egress && !attr->egress && attr->ingress)))
5091 return rte_flow_error_set(error, EINVAL,
5092 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5093 "Flow attributes domain are either invalid "
5094 "or have a domain conflict with current "
5095 "meter attributes");
5096 if (fm->def_policy) {
5097 if (!((attr->transfer &&
5098 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5100 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5102 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5103 return rte_flow_error_set(error, EINVAL,
5104 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5105 "Flow attributes domain "
5106 "have a conflict with current "
5107 "meter domain attributes");
5110 mtr_policy = mlx5_flow_meter_policy_find(dev,
5111 fm->policy_id, NULL);
5113 return rte_flow_error_set(error, EINVAL,
5114 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5115 "Invalid policy id for meter ");
5116 if (!((attr->transfer && mtr_policy->transfer) ||
5117 (attr->egress && mtr_policy->egress) ||
5118 (attr->ingress && mtr_policy->ingress)))
5119 return rte_flow_error_set(error, EINVAL,
5120 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5121 "Flow attributes domain "
5122 "have a conflict with current "
5123 "meter domain attributes");
5124 if (attr->transfer && mtr_policy->dev) {
5126 * When policy has fate action of port_id,
5127 * the flow should have the same src port as policy.
5129 struct mlx5_priv *policy_port_priv =
5130 mtr_policy->dev->data->dev_private;
5131 int32_t flow_src_port = priv->representor_id;
5134 const struct rte_flow_item_port_id *spec =
5136 struct mlx5_priv *port_priv =
5137 mlx5_port_to_eswitch_info(spec->id,
5140 return rte_flow_error_set(error,
5142 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5144 "Failed to get port info.");
5145 flow_src_port = port_priv->representor_id;
5147 if (flow_src_port != policy_port_priv->representor_id)
5148 return rte_flow_error_set(error,
5150 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5152 "Flow and meter policy "
5153 "have different src port.");
5155 *def_policy = false;
5161 * Validate the age action.
5163 * @param[in] action_flags
5164 * Holds the actions detected until now.
5166 * Pointer to the age action.
5168 * Pointer to the Ethernet device structure.
5170 * Pointer to error structure.
5173 * 0 on success, a negative errno value otherwise and rte_errno is set.
5176 flow_dv_validate_action_age(uint64_t action_flags,
5177 const struct rte_flow_action *action,
5178 struct rte_eth_dev *dev,
5179 struct rte_flow_error *error)
5181 struct mlx5_priv *priv = dev->data->dev_private;
5182 const struct rte_flow_action_age *age = action->conf;
5184 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
5185 !priv->sh->aso_age_mng))
5186 return rte_flow_error_set(error, ENOTSUP,
5187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5189 "age action not supported");
5190 if (!(action->conf))
5191 return rte_flow_error_set(error, EINVAL,
5192 RTE_FLOW_ERROR_TYPE_ACTION, action,
5193 "configuration cannot be null");
5194 if (!(age->timeout))
5195 return rte_flow_error_set(error, EINVAL,
5196 RTE_FLOW_ERROR_TYPE_ACTION, action,
5197 "invalid timeout value 0");
5198 if (action_flags & MLX5_FLOW_ACTION_AGE)
5199 return rte_flow_error_set(error, EINVAL,
5200 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5201 "duplicate age actions set");
5206 * Validate the modify-header IPv4 DSCP actions.
5208 * @param[in] action_flags
5209 * Holds the actions detected until now.
5211 * Pointer to the modify action.
5212 * @param[in] item_flags
5213 * Holds the items detected.
5215 * Pointer to error structure.
5218 * 0 on success, a negative errno value otherwise and rte_errno is set.
5221 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5222 const struct rte_flow_action *action,
5223 const uint64_t item_flags,
5224 struct rte_flow_error *error)
5228 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5230 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5231 return rte_flow_error_set(error, EINVAL,
5232 RTE_FLOW_ERROR_TYPE_ACTION,
5234 "no ipv4 item in pattern");
5240 * Validate the modify-header IPv6 DSCP actions.
5242 * @param[in] action_flags
5243 * Holds the actions detected until now.
5245 * Pointer to the modify action.
5246 * @param[in] item_flags
5247 * Holds the items detected.
5249 * Pointer to error structure.
5252 * 0 on success, a negative errno value otherwise and rte_errno is set.
5255 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5256 const struct rte_flow_action *action,
5257 const uint64_t item_flags,
5258 struct rte_flow_error *error)
5262 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5264 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5265 return rte_flow_error_set(error, EINVAL,
5266 RTE_FLOW_ERROR_TYPE_ACTION,
5268 "no ipv6 item in pattern");
5274 * Match modify-header resource.
5277 * Pointer to the hash list.
5279 * Pointer to exist resource entry object.
5281 * Key of the new entry.
5283 * Pointer to new modify-header resource.
5286 * 0 on matching, non-zero otherwise.
5289 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5290 struct mlx5_hlist_entry *entry,
5291 uint64_t key __rte_unused, void *cb_ctx)
5293 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5294 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5295 struct mlx5_flow_dv_modify_hdr_resource *resource =
5296 container_of(entry, typeof(*resource), entry);
5297 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5299 key_len += ref->actions_num * sizeof(ref->actions[0]);
5300 return ref->actions_num != resource->actions_num ||
5301 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5304 struct mlx5_hlist_entry *
5305 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5308 struct mlx5_dev_ctx_shared *sh = list->ctx;
5309 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5310 struct mlx5dv_dr_domain *ns;
5311 struct mlx5_flow_dv_modify_hdr_resource *entry;
5312 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5314 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5315 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5317 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5320 rte_flow_error_set(ctx->error, ENOMEM,
5321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5322 "cannot allocate resource memory");
5325 rte_memcpy(&entry->ft_type,
5326 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5327 key_len + data_len);
5328 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5329 ns = sh->fdb_domain;
5330 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5334 ret = mlx5_flow_os_create_flow_action_modify_header
5335 (sh->ctx, ns, entry,
5336 data_len, &entry->action);
5339 rte_flow_error_set(ctx->error, ENOMEM,
5340 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5341 NULL, "cannot create modification action");
5344 return &entry->entry;
5348 * Validate the sample action.
5350 * @param[in, out] action_flags
5351 * Holds the actions detected until now.
5353 * Pointer to the sample action.
5355 * Pointer to the Ethernet device structure.
5357 * Attributes of flow that includes this action.
5358 * @param[in] item_flags
5359 * Holds the items detected.
5361 * Pointer to the RSS action.
5362 * @param[out] sample_rss
5363 * Pointer to the RSS action in sample action list.
5365 * Pointer to the COUNT action in sample action list.
5366 * @param[out] fdb_mirror_limit
5367 * Pointer to the FDB mirror limitation flag.
5369 * Pointer to error structure.
5372 * 0 on success, a negative errno value otherwise and rte_errno is set.
5375 flow_dv_validate_action_sample(uint64_t *action_flags,
5376 const struct rte_flow_action *action,
5377 struct rte_eth_dev *dev,
5378 const struct rte_flow_attr *attr,
5379 uint64_t item_flags,
5380 const struct rte_flow_action_rss *rss,
5381 const struct rte_flow_action_rss **sample_rss,
5382 const struct rte_flow_action_count **count,
5383 int *fdb_mirror_limit,
5384 struct rte_flow_error *error)
5386 struct mlx5_priv *priv = dev->data->dev_private;
5387 struct mlx5_dev_config *dev_conf = &priv->config;
5388 const struct rte_flow_action_sample *sample = action->conf;
5389 const struct rte_flow_action *act;
5390 uint64_t sub_action_flags = 0;
5391 uint16_t queue_index = 0xFFFF;
5396 return rte_flow_error_set(error, EINVAL,
5397 RTE_FLOW_ERROR_TYPE_ACTION, action,
5398 "configuration cannot be NULL");
5399 if (sample->ratio == 0)
5400 return rte_flow_error_set(error, EINVAL,
5401 RTE_FLOW_ERROR_TYPE_ACTION, action,
5402 "ratio value starts from 1");
5403 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5404 return rte_flow_error_set(error, ENOTSUP,
5405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5407 "sample action not supported");
5408 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5409 return rte_flow_error_set(error, EINVAL,
5410 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5411 "Multiple sample actions not "
5413 if (*action_flags & MLX5_FLOW_ACTION_METER)
5414 return rte_flow_error_set(error, EINVAL,
5415 RTE_FLOW_ERROR_TYPE_ACTION, action,
5416 "wrong action order, meter should "
5417 "be after sample action");
5418 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5419 return rte_flow_error_set(error, EINVAL,
5420 RTE_FLOW_ERROR_TYPE_ACTION, action,
5421 "wrong action order, jump should "
5422 "be after sample action");
5423 act = sample->actions;
5424 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5425 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5426 return rte_flow_error_set(error, ENOTSUP,
5427 RTE_FLOW_ERROR_TYPE_ACTION,
5428 act, "too many actions");
5429 switch (act->type) {
5430 case RTE_FLOW_ACTION_TYPE_QUEUE:
5431 ret = mlx5_flow_validate_action_queue(act,
5437 queue_index = ((const struct rte_flow_action_queue *)
5438 (act->conf))->index;
5439 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5442 case RTE_FLOW_ACTION_TYPE_RSS:
5443 *sample_rss = act->conf;
5444 ret = mlx5_flow_validate_action_rss(act,
5451 if (rss && *sample_rss &&
5452 ((*sample_rss)->level != rss->level ||
5453 (*sample_rss)->types != rss->types))
5454 return rte_flow_error_set(error, ENOTSUP,
5455 RTE_FLOW_ERROR_TYPE_ACTION,
5457 "Can't use the different RSS types "
5458 "or level in the same flow");
5459 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5460 queue_index = (*sample_rss)->queue[0];
5461 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5464 case RTE_FLOW_ACTION_TYPE_MARK:
5465 ret = flow_dv_validate_action_mark(dev, act,
5470 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5471 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5472 MLX5_FLOW_ACTION_MARK_EXT;
5474 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5477 case RTE_FLOW_ACTION_TYPE_COUNT:
5478 ret = flow_dv_validate_action_count
5479 (dev, is_shared_action_count(act),
5480 *action_flags | sub_action_flags,
5485 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5486 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5489 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5490 ret = flow_dv_validate_action_port_id(dev,
5497 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5500 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5501 ret = flow_dv_validate_action_raw_encap_decap
5502 (dev, NULL, act->conf, attr, &sub_action_flags,
5503 &actions_n, action, item_flags, error);
5508 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5509 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5510 ret = flow_dv_validate_action_l2_encap(dev,
5516 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5520 return rte_flow_error_set(error, ENOTSUP,
5521 RTE_FLOW_ERROR_TYPE_ACTION,
5523 "Doesn't support optional "
5527 if (attr->ingress && !attr->transfer) {
5528 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5529 MLX5_FLOW_ACTION_RSS)))
5530 return rte_flow_error_set(error, EINVAL,
5531 RTE_FLOW_ERROR_TYPE_ACTION,
5533 "Ingress must has a dest "
5534 "QUEUE for Sample");
5535 } else if (attr->egress && !attr->transfer) {
5536 return rte_flow_error_set(error, ENOTSUP,
5537 RTE_FLOW_ERROR_TYPE_ACTION,
5539 "Sample Only support Ingress "
5541 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5542 MLX5_ASSERT(attr->transfer);
5543 if (sample->ratio > 1)
5544 return rte_flow_error_set(error, ENOTSUP,
5545 RTE_FLOW_ERROR_TYPE_ACTION,
5547 "E-Switch doesn't support "
5548 "any optional action "
5550 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5551 return rte_flow_error_set(error, ENOTSUP,
5552 RTE_FLOW_ERROR_TYPE_ACTION,
5554 "unsupported action QUEUE");
5555 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5556 return rte_flow_error_set(error, ENOTSUP,
5557 RTE_FLOW_ERROR_TYPE_ACTION,
5559 "unsupported action QUEUE");
5560 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5561 return rte_flow_error_set(error, EINVAL,
5562 RTE_FLOW_ERROR_TYPE_ACTION,
5564 "E-Switch must has a dest "
5565 "port for mirroring");
5566 if (!priv->config.hca_attr.reg_c_preserve &&
5567 priv->representor_id != UINT16_MAX)
5568 *fdb_mirror_limit = 1;
5570 /* Continue validation for Xcap actions.*/
5571 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5572 (queue_index == 0xFFFF ||
5573 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5574 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5575 MLX5_FLOW_XCAP_ACTIONS)
5576 return rte_flow_error_set(error, ENOTSUP,
5577 RTE_FLOW_ERROR_TYPE_ACTION,
5578 NULL, "encap and decap "
5579 "combination aren't "
5581 if (!attr->transfer && attr->ingress && (sub_action_flags &
5582 MLX5_FLOW_ACTION_ENCAP))
5583 return rte_flow_error_set(error, ENOTSUP,
5584 RTE_FLOW_ERROR_TYPE_ACTION,
5585 NULL, "encap is not supported"
5586 " for ingress traffic");
5592 * Find existing modify-header resource or create and register a new one.
5594 * @param dev[in, out]
5595 * Pointer to rte_eth_dev structure.
5596 * @param[in, out] resource
5597 * Pointer to modify-header resource.
5598 * @parm[in, out] dev_flow
5599 * Pointer to the dev_flow.
5601 * pointer to error structure.
5604 * 0 on success otherwise -errno and errno is set.
5607 flow_dv_modify_hdr_resource_register
5608 (struct rte_eth_dev *dev,
5609 struct mlx5_flow_dv_modify_hdr_resource *resource,
5610 struct mlx5_flow *dev_flow,
5611 struct rte_flow_error *error)
5613 struct mlx5_priv *priv = dev->data->dev_private;
5614 struct mlx5_dev_ctx_shared *sh = priv->sh;
5615 uint32_t key_len = sizeof(*resource) -
5616 offsetof(typeof(*resource), ft_type) +
5617 resource->actions_num * sizeof(resource->actions[0]);
5618 struct mlx5_hlist_entry *entry;
5619 struct mlx5_flow_cb_ctx ctx = {
5625 resource->flags = dev_flow->dv.group ? 0 :
5626 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5627 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5629 return rte_flow_error_set(error, EOVERFLOW,
5630 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5631 "too many modify header items");
5632 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5633 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5636 resource = container_of(entry, typeof(*resource), entry);
5637 dev_flow->handle->dvh.modify_hdr = resource;
5642 * Get DV flow counter by index.
5645 * Pointer to the Ethernet device structure.
5647 * mlx5 flow counter index in the container.
5649 * mlx5 flow counter pool in the container.
5652 * Pointer to the counter, NULL otherwise.
5654 static struct mlx5_flow_counter *
5655 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5657 struct mlx5_flow_counter_pool **ppool)
5659 struct mlx5_priv *priv = dev->data->dev_private;
5660 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5661 struct mlx5_flow_counter_pool *pool;
5663 /* Decrease to original index and clear shared bit. */
5664 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5665 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5666 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5670 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5674 * Check the devx counter belongs to the pool.
5677 * Pointer to the counter pool.
5679 * The counter devx ID.
5682 * True if counter belongs to the pool, false otherwise.
5685 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5687 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5688 MLX5_COUNTERS_PER_POOL;
5690 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5696 * Get a pool by devx counter ID.
5699 * Pointer to the counter management.
5701 * The counter devx ID.
5704 * The counter pool pointer if exists, NULL otherwise,
5706 static struct mlx5_flow_counter_pool *
5707 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5710 struct mlx5_flow_counter_pool *pool = NULL;
5712 rte_spinlock_lock(&cmng->pool_update_sl);
5713 /* Check last used pool. */
5714 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5715 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5716 pool = cmng->pools[cmng->last_pool_idx];
5719 /* ID out of range means no suitable pool in the container. */
5720 if (id > cmng->max_id || id < cmng->min_id)
5723 * Find the pool from the end of the container, since mostly counter
5724 * ID is sequence increasing, and the last pool should be the needed
5729 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5731 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5737 rte_spinlock_unlock(&cmng->pool_update_sl);
5742 * Resize a counter container.
5745 * Pointer to the Ethernet device structure.
5748 * 0 on success, otherwise negative errno value and rte_errno is set.
5751 flow_dv_container_resize(struct rte_eth_dev *dev)
5753 struct mlx5_priv *priv = dev->data->dev_private;
5754 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5755 void *old_pools = cmng->pools;
5756 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5757 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5758 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5765 memcpy(pools, old_pools, cmng->n *
5766 sizeof(struct mlx5_flow_counter_pool *));
5768 cmng->pools = pools;
5770 mlx5_free(old_pools);
5775 * Query a devx flow counter.
5778 * Pointer to the Ethernet device structure.
5779 * @param[in] counter
5780 * Index to the flow counter.
5782 * The statistics value of packets.
5784 * The statistics value of bytes.
5787 * 0 on success, otherwise a negative errno value and rte_errno is set.
5790 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5793 struct mlx5_priv *priv = dev->data->dev_private;
5794 struct mlx5_flow_counter_pool *pool = NULL;
5795 struct mlx5_flow_counter *cnt;
5798 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5800 if (priv->sh->cmng.counter_fallback)
5801 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5802 0, pkts, bytes, 0, NULL, NULL, 0);
5803 rte_spinlock_lock(&pool->sl);
5808 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5809 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5810 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5812 rte_spinlock_unlock(&pool->sl);
5817 * Create and initialize a new counter pool.
5820 * Pointer to the Ethernet device structure.
5822 * The devX counter handle.
5824 * Whether the pool is for counter that was allocated for aging.
5825 * @param[in/out] cont_cur
5826 * Pointer to the container pointer, it will be update in pool resize.
5829 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5831 static struct mlx5_flow_counter_pool *
5832 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5835 struct mlx5_priv *priv = dev->data->dev_private;
5836 struct mlx5_flow_counter_pool *pool;
5837 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5838 bool fallback = priv->sh->cmng.counter_fallback;
5839 uint32_t size = sizeof(*pool);
5841 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5842 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5843 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5849 pool->is_aged = !!age;
5850 pool->query_gen = 0;
5851 pool->min_dcs = dcs;
5852 rte_spinlock_init(&pool->sl);
5853 rte_spinlock_init(&pool->csl);
5854 TAILQ_INIT(&pool->counters[0]);
5855 TAILQ_INIT(&pool->counters[1]);
5856 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5857 rte_spinlock_lock(&cmng->pool_update_sl);
5858 pool->index = cmng->n_valid;
5859 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5861 rte_spinlock_unlock(&cmng->pool_update_sl);
5864 cmng->pools[pool->index] = pool;
5866 if (unlikely(fallback)) {
5867 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5869 if (base < cmng->min_id)
5870 cmng->min_id = base;
5871 if (base > cmng->max_id)
5872 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5873 cmng->last_pool_idx = pool->index;
5875 rte_spinlock_unlock(&cmng->pool_update_sl);
5880 * Prepare a new counter and/or a new counter pool.
5883 * Pointer to the Ethernet device structure.
5884 * @param[out] cnt_free
5885 * Where to put the pointer of a new counter.
5887 * Whether the pool is for counter that was allocated for aging.
5890 * The counter pool pointer and @p cnt_free is set on success,
5891 * NULL otherwise and rte_errno is set.
5893 static struct mlx5_flow_counter_pool *
5894 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5895 struct mlx5_flow_counter **cnt_free,
5898 struct mlx5_priv *priv = dev->data->dev_private;
5899 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5900 struct mlx5_flow_counter_pool *pool;
5901 struct mlx5_counters tmp_tq;
5902 struct mlx5_devx_obj *dcs = NULL;
5903 struct mlx5_flow_counter *cnt;
5904 enum mlx5_counter_type cnt_type =
5905 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5906 bool fallback = priv->sh->cmng.counter_fallback;
5910 /* bulk_bitmap must be 0 for single counter allocation. */
5911 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5914 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5916 pool = flow_dv_pool_create(dev, dcs, age);
5918 mlx5_devx_cmd_destroy(dcs);
5922 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5923 cnt = MLX5_POOL_GET_CNT(pool, i);
5925 cnt->dcs_when_free = dcs;
5929 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5931 rte_errno = ENODATA;
5934 pool = flow_dv_pool_create(dev, dcs, age);
5936 mlx5_devx_cmd_destroy(dcs);
5939 TAILQ_INIT(&tmp_tq);
5940 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5941 cnt = MLX5_POOL_GET_CNT(pool, i);
5943 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5945 rte_spinlock_lock(&cmng->csl[cnt_type]);
5946 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5947 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5948 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5949 (*cnt_free)->pool = pool;
5954 * Allocate a flow counter.
5957 * Pointer to the Ethernet device structure.
5959 * Whether the counter was allocated for aging.
5962 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5965 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5967 struct mlx5_priv *priv = dev->data->dev_private;
5968 struct mlx5_flow_counter_pool *pool = NULL;
5969 struct mlx5_flow_counter *cnt_free = NULL;
5970 bool fallback = priv->sh->cmng.counter_fallback;
5971 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5972 enum mlx5_counter_type cnt_type =
5973 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5976 if (!priv->config.devx) {
5977 rte_errno = ENOTSUP;
5980 /* Get free counters from container. */
5981 rte_spinlock_lock(&cmng->csl[cnt_type]);
5982 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5984 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5985 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5986 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5988 pool = cnt_free->pool;
5990 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5991 /* Create a DV counter action only in the first time usage. */
5992 if (!cnt_free->action) {
5994 struct mlx5_devx_obj *dcs;
5998 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5999 dcs = pool->min_dcs;
6002 dcs = cnt_free->dcs_when_free;
6004 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6011 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6012 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6013 /* Update the counter reset values. */
6014 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6017 if (!fallback && !priv->sh->cmng.query_thread_on)
6018 /* Start the asynchronous batch query by the host thread. */
6019 mlx5_set_query_alarm(priv->sh);
6021 * When the count action isn't shared (by ID), shared_info field is
6022 * used for indirect action API's refcnt.
6023 * When the counter action is not shared neither by ID nor by indirect
6024 * action API, shared info must be 1.
6026 cnt_free->shared_info.refcnt = 1;
6030 cnt_free->pool = pool;
6032 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6033 rte_spinlock_lock(&cmng->csl[cnt_type]);
6034 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6035 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6041 * Allocate a shared flow counter.
6044 * Pointer to the shared counter configuration.
6046 * Pointer to save the allocated counter index.
6049 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6053 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
6055 struct mlx5_shared_counter_conf *conf = ctx;
6056 struct rte_eth_dev *dev = conf->dev;
6057 struct mlx5_flow_counter *cnt;
6059 data->dword = flow_dv_counter_alloc(dev, 0);
6060 data->dword |= MLX5_CNT_SHARED_OFFSET;
6061 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
6062 cnt->shared_info.id = conf->id;
6067 * Get a shared flow counter.
6070 * Pointer to the Ethernet device structure.
6072 * Counter identifier.
6075 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6078 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
6080 struct mlx5_priv *priv = dev->data->dev_private;
6081 struct mlx5_shared_counter_conf conf = {
6085 union mlx5_l3t_data data = {
6089 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
6090 flow_dv_counter_alloc_shared_cb, &conf);
6095 * Get age param from counter index.
6098 * Pointer to the Ethernet device structure.
6099 * @param[in] counter
6100 * Index to the counter handler.
6103 * The aging parameter specified for the counter index.
6105 static struct mlx5_age_param*
6106 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6109 struct mlx5_flow_counter *cnt;
6110 struct mlx5_flow_counter_pool *pool = NULL;
6112 flow_dv_counter_get_by_idx(dev, counter, &pool);
6113 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6114 cnt = MLX5_POOL_GET_CNT(pool, counter);
6115 return MLX5_CNT_TO_AGE(cnt);
6119 * Remove a flow counter from aged counter list.
6122 * Pointer to the Ethernet device structure.
6123 * @param[in] counter
6124 * Index to the counter handler.
6126 * Pointer to the counter handler.
6129 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6130 uint32_t counter, struct mlx5_flow_counter *cnt)
6132 struct mlx5_age_info *age_info;
6133 struct mlx5_age_param *age_param;
6134 struct mlx5_priv *priv = dev->data->dev_private;
6135 uint16_t expected = AGE_CANDIDATE;
6137 age_info = GET_PORT_AGE_INFO(priv);
6138 age_param = flow_dv_counter_idx_get_age(dev, counter);
6139 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6140 AGE_FREE, false, __ATOMIC_RELAXED,
6141 __ATOMIC_RELAXED)) {
6143 * We need the lock even it is age timeout,
6144 * since counter may still in process.
6146 rte_spinlock_lock(&age_info->aged_sl);
6147 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6148 rte_spinlock_unlock(&age_info->aged_sl);
6149 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6154 * Release a flow counter.
6157 * Pointer to the Ethernet device structure.
6158 * @param[in] counter
6159 * Index to the counter handler.
6162 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6164 struct mlx5_priv *priv = dev->data->dev_private;
6165 struct mlx5_flow_counter_pool *pool = NULL;
6166 struct mlx5_flow_counter *cnt;
6167 enum mlx5_counter_type cnt_type;
6171 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6173 if (pool->is_aged) {
6174 flow_dv_counter_remove_from_age(dev, counter, cnt);
6177 * If the counter action is shared by ID, the l3t_clear_entry
6178 * function reduces its references counter. If after the
6179 * reduction the action is still referenced, the function
6180 * returns here and does not release it.
6182 if (IS_LEGACY_SHARED_CNT(counter) &&
6183 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
6184 cnt->shared_info.id))
6187 * If the counter action is shared by indirect action API,
6188 * the atomic function reduces its references counter.
6189 * If after the reduction the action is still referenced, the
6190 * function returns here and does not release it.
6191 * When the counter action is not shared neither by ID nor by
6192 * indirect action API, shared info is 1 before the reduction,
6193 * so this condition is failed and function doesn't return here.
6195 if (!IS_LEGACY_SHARED_CNT(counter) &&
6196 __atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6202 * Put the counter back to list to be updated in none fallback mode.
6203 * Currently, we are using two list alternately, while one is in query,
6204 * add the freed counter to the other list based on the pool query_gen
6205 * value. After query finishes, add counter the list to the global
6206 * container counter list. The list changes while query starts. In
6207 * this case, lock will not be needed as query callback and release
6208 * function both operate with the different list.
6210 if (!priv->sh->cmng.counter_fallback) {
6211 rte_spinlock_lock(&pool->csl);
6212 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6213 rte_spinlock_unlock(&pool->csl);
6215 cnt->dcs_when_free = cnt->dcs_when_active;
6216 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6217 MLX5_COUNTER_TYPE_ORIGIN;
6218 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6219 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6221 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6226 * Resize a meter id container.
6229 * Pointer to the Ethernet device structure.
6232 * 0 on success, otherwise negative errno value and rte_errno is set.
6235 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6237 struct mlx5_priv *priv = dev->data->dev_private;
6238 struct mlx5_aso_mtr_pools_mng *pools_mng =
6239 &priv->sh->mtrmng->pools_mng;
6240 void *old_pools = pools_mng->pools;
6241 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6242 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6243 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6250 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6255 memcpy(pools, old_pools, pools_mng->n *
6256 sizeof(struct mlx5_aso_mtr_pool *));
6257 pools_mng->n = resize;
6258 pools_mng->pools = pools;
6260 mlx5_free(old_pools);
6265 * Prepare a new meter and/or a new meter pool.
6268 * Pointer to the Ethernet device structure.
6269 * @param[out] mtr_free
6270 * Where to put the pointer of a new meter.g.
6273 * The meter pool pointer and @mtr_free is set on success,
6274 * NULL otherwise and rte_errno is set.
6276 static struct mlx5_aso_mtr_pool *
6277 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
6278 struct mlx5_aso_mtr **mtr_free)
6280 struct mlx5_priv *priv = dev->data->dev_private;
6281 struct mlx5_aso_mtr_pools_mng *pools_mng =
6282 &priv->sh->mtrmng->pools_mng;
6283 struct mlx5_aso_mtr_pool *pool = NULL;
6284 struct mlx5_devx_obj *dcs = NULL;
6286 uint32_t log_obj_size;
6288 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6289 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6290 priv->sh->pdn, log_obj_size);
6292 rte_errno = ENODATA;
6295 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6298 claim_zero(mlx5_devx_cmd_destroy(dcs));
6301 pool->devx_obj = dcs;
6302 pool->index = pools_mng->n_valid;
6303 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6305 claim_zero(mlx5_devx_cmd_destroy(dcs));
6308 pools_mng->pools[pool->index] = pool;
6309 pools_mng->n_valid++;
6310 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6311 pool->mtrs[i].offset = i;
6312 LIST_INSERT_HEAD(&pools_mng->meters,
6313 &pool->mtrs[i], next);
6315 pool->mtrs[0].offset = 0;
6316 *mtr_free = &pool->mtrs[0];
6321 * Release a flow meter into pool.
6324 * Pointer to the Ethernet device structure.
6325 * @param[in] mtr_idx
6326 * Index to aso flow meter.
6329 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6331 struct mlx5_priv *priv = dev->data->dev_private;
6332 struct mlx5_aso_mtr_pools_mng *pools_mng =
6333 &priv->sh->mtrmng->pools_mng;
6334 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6336 MLX5_ASSERT(aso_mtr);
6337 rte_spinlock_lock(&pools_mng->mtrsl);
6338 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6339 aso_mtr->state = ASO_METER_FREE;
6340 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6341 rte_spinlock_unlock(&pools_mng->mtrsl);
6345 * Allocate a aso flow meter.
6348 * Pointer to the Ethernet device structure.
6351 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6354 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6356 struct mlx5_priv *priv = dev->data->dev_private;
6357 struct mlx5_aso_mtr *mtr_free = NULL;
6358 struct mlx5_aso_mtr_pools_mng *pools_mng =
6359 &priv->sh->mtrmng->pools_mng;
6360 struct mlx5_aso_mtr_pool *pool;
6361 uint32_t mtr_idx = 0;
6363 if (!priv->config.devx) {
6364 rte_errno = ENOTSUP;
6367 /* Allocate the flow meter memory. */
6368 /* Get free meters from management. */
6369 rte_spinlock_lock(&pools_mng->mtrsl);
6370 mtr_free = LIST_FIRST(&pools_mng->meters);
6372 LIST_REMOVE(mtr_free, next);
6373 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6374 rte_spinlock_unlock(&pools_mng->mtrsl);
6377 mtr_free->state = ASO_METER_WAIT;
6378 rte_spinlock_unlock(&pools_mng->mtrsl);
6379 pool = container_of(mtr_free,
6380 struct mlx5_aso_mtr_pool,
6381 mtrs[mtr_free->offset]);
6382 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6383 if (!mtr_free->fm.meter_action) {
6384 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6385 struct rte_flow_error error;
6388 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6389 mtr_free->fm.meter_action =
6390 mlx5_glue->dv_create_flow_action_aso
6391 (priv->sh->rx_domain,
6392 pool->devx_obj->obj,
6394 (1 << MLX5_FLOW_COLOR_GREEN),
6396 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6397 if (!mtr_free->fm.meter_action) {
6398 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6406 * Verify the @p attributes will be correctly understood by the NIC and store
6407 * them in the @p flow if everything is correct.
6410 * Pointer to dev struct.
6411 * @param[in] attributes
6412 * Pointer to flow attributes
6413 * @param[in] external
6414 * This flow rule is created by request external to PMD.
6416 * Pointer to error structure.
6419 * - 0 on success and non root table.
6420 * - 1 on success and root table.
6421 * - a negative errno value otherwise and rte_errno is set.
6424 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6425 const struct mlx5_flow_tunnel *tunnel,
6426 const struct rte_flow_attr *attributes,
6427 const struct flow_grp_info *grp_info,
6428 struct rte_flow_error *error)
6430 struct mlx5_priv *priv = dev->data->dev_private;
6431 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6434 #ifndef HAVE_MLX5DV_DR
6435 RTE_SET_USED(tunnel);
6436 RTE_SET_USED(grp_info);
6437 if (attributes->group)
6438 return rte_flow_error_set(error, ENOTSUP,
6439 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6441 "groups are not supported");
6445 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6450 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6452 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6453 attributes->priority > lowest_priority)
6454 return rte_flow_error_set(error, ENOTSUP,
6455 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6457 "priority out of range");
6458 if (attributes->transfer) {
6459 if (!priv->config.dv_esw_en)
6460 return rte_flow_error_set
6462 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6463 "E-Switch dr is not supported");
6464 if (!(priv->representor || priv->master))
6465 return rte_flow_error_set
6466 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6467 NULL, "E-Switch configuration can only be"
6468 " done by a master or a representor device");
6469 if (attributes->egress)
6470 return rte_flow_error_set
6472 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6473 "egress is not supported");
6475 if (!(attributes->egress ^ attributes->ingress))
6476 return rte_flow_error_set(error, ENOTSUP,
6477 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6478 "must specify exactly one of "
6479 "ingress or egress");
6484 mlx5_flow_locate_proto_l3(const struct rte_flow_item **head,
6485 const struct rte_flow_item *end)
6487 const struct rte_flow_item *item = *head;
6488 uint16_t l3_protocol;
6490 for (; item != end; item++) {
6491 switch (item->type) {
6494 case RTE_FLOW_ITEM_TYPE_IPV4:
6495 l3_protocol = RTE_ETHER_TYPE_IPV4;
6497 case RTE_FLOW_ITEM_TYPE_IPV6:
6498 l3_protocol = RTE_ETHER_TYPE_IPV6;
6500 case RTE_FLOW_ITEM_TYPE_ETH:
6501 if (item->mask && item->spec) {
6502 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_eth,
6505 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6506 l3_protocol == RTE_ETHER_TYPE_IPV6)
6510 case RTE_FLOW_ITEM_TYPE_VLAN:
6511 if (item->mask && item->spec) {
6512 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_vlan,
6515 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6516 l3_protocol == RTE_ETHER_TYPE_IPV6)
6529 mlx5_flow_locate_proto_l4(const struct rte_flow_item **head,
6530 const struct rte_flow_item *end)
6532 const struct rte_flow_item *item = *head;
6533 uint8_t l4_protocol;
6535 for (; item != end; item++) {
6536 switch (item->type) {
6539 case RTE_FLOW_ITEM_TYPE_TCP:
6540 l4_protocol = IPPROTO_TCP;
6542 case RTE_FLOW_ITEM_TYPE_UDP:
6543 l4_protocol = IPPROTO_UDP;
6545 case RTE_FLOW_ITEM_TYPE_IPV4:
6546 if (item->mask && item->spec) {
6547 const struct rte_flow_item_ipv4 *mask, *spec;
6549 mask = (typeof(mask))item->mask;
6550 spec = (typeof(spec))item->spec;
6551 l4_protocol = mask->hdr.next_proto_id &
6552 spec->hdr.next_proto_id;
6553 if (l4_protocol == IPPROTO_TCP ||
6554 l4_protocol == IPPROTO_UDP)
6558 case RTE_FLOW_ITEM_TYPE_IPV6:
6559 if (item->mask && item->spec) {
6560 const struct rte_flow_item_ipv6 *mask, *spec;
6561 mask = (typeof(mask))item->mask;
6562 spec = (typeof(spec))item->spec;
6563 l4_protocol = mask->hdr.proto & spec->hdr.proto;
6564 if (l4_protocol == IPPROTO_TCP ||
6565 l4_protocol == IPPROTO_UDP)
6578 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6579 const struct rte_flow_item *rule_items,
6580 const struct rte_flow_item *integrity_item,
6581 struct rte_flow_error *error)
6583 struct mlx5_priv *priv = dev->data->dev_private;
6584 const struct rte_flow_item *tunnel_item, *end_item, *item = rule_items;
6585 const struct rte_flow_item_integrity *mask = (typeof(mask))
6586 integrity_item->mask;
6587 const struct rte_flow_item_integrity *spec = (typeof(spec))
6588 integrity_item->spec;
6591 if (!priv->config.hca_attr.pkt_integrity_match)
6592 return rte_flow_error_set(error, ENOTSUP,
6593 RTE_FLOW_ERROR_TYPE_ITEM,
6595 "packet integrity integrity_item not supported");
6597 mask = &rte_flow_item_integrity_mask;
6598 if (!mlx5_validate_integrity_item(mask))
6599 return rte_flow_error_set(error, ENOTSUP,
6600 RTE_FLOW_ERROR_TYPE_ITEM,
6602 "unsupported integrity filter");
6603 tunnel_item = mlx5_flow_find_tunnel_item(rule_items);
6604 if (spec->level > 1) {
6606 return rte_flow_error_set(error, ENOTSUP,
6607 RTE_FLOW_ERROR_TYPE_ITEM,
6609 "missing tunnel item");
6611 end_item = mlx5_find_end_item(tunnel_item);
6613 end_item = tunnel_item ? tunnel_item :
6614 mlx5_find_end_item(integrity_item);
6616 if (mask->l3_ok || mask->ipv4_csum_ok) {
6617 protocol = mlx5_flow_locate_proto_l3(&item, end_item);
6619 return rte_flow_error_set(error, EINVAL,
6620 RTE_FLOW_ERROR_TYPE_ITEM,
6622 "missing L3 protocol");
6624 if (mask->l4_ok || mask->l4_csum_ok) {
6625 protocol = mlx5_flow_locate_proto_l4(&item, end_item);
6627 return rte_flow_error_set(error, EINVAL,
6628 RTE_FLOW_ERROR_TYPE_ITEM,
6630 "missing L4 protocol");
6636 * Internal validation function. For validating both actions and items.
6639 * Pointer to the rte_eth_dev structure.
6641 * Pointer to the flow attributes.
6643 * Pointer to the list of items.
6644 * @param[in] actions
6645 * Pointer to the list of actions.
6646 * @param[in] external
6647 * This flow rule is created by request external to PMD.
6648 * @param[in] hairpin
6649 * Number of hairpin TX actions, 0 means classic flow.
6651 * Pointer to the error structure.
6654 * 0 on success, a negative errno value otherwise and rte_errno is set.
6657 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6658 const struct rte_flow_item items[],
6659 const struct rte_flow_action actions[],
6660 bool external, int hairpin, struct rte_flow_error *error)
6663 uint64_t action_flags = 0;
6664 uint64_t item_flags = 0;
6665 uint64_t last_item = 0;
6666 uint8_t next_protocol = 0xff;
6667 uint16_t ether_type = 0;
6669 uint8_t item_ipv6_proto = 0;
6670 int fdb_mirror_limit = 0;
6671 int modify_after_mirror = 0;
6672 const struct rte_flow_item *geneve_item = NULL;
6673 const struct rte_flow_item *gre_item = NULL;
6674 const struct rte_flow_item *gtp_item = NULL;
6675 const struct rte_flow_action_raw_decap *decap;
6676 const struct rte_flow_action_raw_encap *encap;
6677 const struct rte_flow_action_rss *rss = NULL;
6678 const struct rte_flow_action_rss *sample_rss = NULL;
6679 const struct rte_flow_action_count *sample_count = NULL;
6680 const struct rte_flow_item_tcp nic_tcp_mask = {
6683 .src_port = RTE_BE16(UINT16_MAX),
6684 .dst_port = RTE_BE16(UINT16_MAX),
6687 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6690 "\xff\xff\xff\xff\xff\xff\xff\xff"
6691 "\xff\xff\xff\xff\xff\xff\xff\xff",
6693 "\xff\xff\xff\xff\xff\xff\xff\xff"
6694 "\xff\xff\xff\xff\xff\xff\xff\xff",
6695 .vtc_flow = RTE_BE32(0xffffffff),
6701 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6705 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6709 .dummy[0] = 0xffffffff,
6712 struct mlx5_priv *priv = dev->data->dev_private;
6713 struct mlx5_dev_config *dev_conf = &priv->config;
6714 uint16_t queue_index = 0xFFFF;
6715 const struct rte_flow_item_vlan *vlan_m = NULL;
6716 uint32_t rw_act_num = 0;
6718 const struct mlx5_flow_tunnel *tunnel;
6719 enum mlx5_tof_rule_type tof_rule_type;
6720 struct flow_grp_info grp_info = {
6721 .external = !!external,
6722 .transfer = !!attr->transfer,
6723 .fdb_def_rule = !!priv->fdb_def_rule,
6724 .std_tbl_fix = true,
6726 const struct rte_eth_hairpin_conf *conf;
6727 const struct rte_flow_item *rule_items = items;
6728 const struct rte_flow_item *port_id_item = NULL;
6729 bool def_policy = false;
6733 tunnel = is_tunnel_offload_active(dev) ?
6734 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6736 if (priv->representor)
6737 return rte_flow_error_set
6739 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6740 NULL, "decap not supported for VF representor");
6741 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6742 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6743 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6744 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6745 MLX5_FLOW_ACTION_DECAP;
6746 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6747 (dev, attr, tunnel, tof_rule_type);
6749 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6752 is_root = (uint64_t)ret;
6753 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6754 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6755 int type = items->type;
6757 if (!mlx5_flow_os_item_supported(type))
6758 return rte_flow_error_set(error, ENOTSUP,
6759 RTE_FLOW_ERROR_TYPE_ITEM,
6760 NULL, "item not supported");
6762 case RTE_FLOW_ITEM_TYPE_VOID:
6764 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6765 ret = flow_dv_validate_item_port_id
6766 (dev, items, attr, item_flags, error);
6769 last_item = MLX5_FLOW_ITEM_PORT_ID;
6770 port_id_item = items;
6772 case RTE_FLOW_ITEM_TYPE_ETH:
6773 ret = mlx5_flow_validate_item_eth(items, item_flags,
6777 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6778 MLX5_FLOW_LAYER_OUTER_L2;
6779 if (items->mask != NULL && items->spec != NULL) {
6781 ((const struct rte_flow_item_eth *)
6784 ((const struct rte_flow_item_eth *)
6786 ether_type = rte_be_to_cpu_16(ether_type);
6791 case RTE_FLOW_ITEM_TYPE_VLAN:
6792 ret = flow_dv_validate_item_vlan(items, item_flags,
6796 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6797 MLX5_FLOW_LAYER_OUTER_VLAN;
6798 if (items->mask != NULL && items->spec != NULL) {
6800 ((const struct rte_flow_item_vlan *)
6801 items->spec)->inner_type;
6803 ((const struct rte_flow_item_vlan *)
6804 items->mask)->inner_type;
6805 ether_type = rte_be_to_cpu_16(ether_type);
6809 /* Store outer VLAN mask for of_push_vlan action. */
6811 vlan_m = items->mask;
6813 case RTE_FLOW_ITEM_TYPE_IPV4:
6814 mlx5_flow_tunnel_ip_check(items, next_protocol,
6815 &item_flags, &tunnel);
6816 ret = flow_dv_validate_item_ipv4(items, item_flags,
6817 last_item, ether_type,
6821 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6822 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6823 if (items->mask != NULL &&
6824 ((const struct rte_flow_item_ipv4 *)
6825 items->mask)->hdr.next_proto_id) {
6827 ((const struct rte_flow_item_ipv4 *)
6828 (items->spec))->hdr.next_proto_id;
6830 ((const struct rte_flow_item_ipv4 *)
6831 (items->mask))->hdr.next_proto_id;
6833 /* Reset for inner layer. */
6834 next_protocol = 0xff;
6837 case RTE_FLOW_ITEM_TYPE_IPV6:
6838 mlx5_flow_tunnel_ip_check(items, next_protocol,
6839 &item_flags, &tunnel);
6840 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6847 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6848 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6849 if (items->mask != NULL &&
6850 ((const struct rte_flow_item_ipv6 *)
6851 items->mask)->hdr.proto) {
6853 ((const struct rte_flow_item_ipv6 *)
6854 items->spec)->hdr.proto;
6856 ((const struct rte_flow_item_ipv6 *)
6857 items->spec)->hdr.proto;
6859 ((const struct rte_flow_item_ipv6 *)
6860 items->mask)->hdr.proto;
6862 /* Reset for inner layer. */
6863 next_protocol = 0xff;
6866 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6867 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6872 last_item = tunnel ?
6873 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6874 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6875 if (items->mask != NULL &&
6876 ((const struct rte_flow_item_ipv6_frag_ext *)
6877 items->mask)->hdr.next_header) {
6879 ((const struct rte_flow_item_ipv6_frag_ext *)
6880 items->spec)->hdr.next_header;
6882 ((const struct rte_flow_item_ipv6_frag_ext *)
6883 items->mask)->hdr.next_header;
6885 /* Reset for inner layer. */
6886 next_protocol = 0xff;
6889 case RTE_FLOW_ITEM_TYPE_TCP:
6890 ret = mlx5_flow_validate_item_tcp
6897 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6898 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6900 case RTE_FLOW_ITEM_TYPE_UDP:
6901 ret = mlx5_flow_validate_item_udp(items, item_flags,
6906 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6907 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6909 case RTE_FLOW_ITEM_TYPE_GRE:
6910 ret = mlx5_flow_validate_item_gre(items, item_flags,
6911 next_protocol, error);
6915 last_item = MLX5_FLOW_LAYER_GRE;
6917 case RTE_FLOW_ITEM_TYPE_NVGRE:
6918 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6923 last_item = MLX5_FLOW_LAYER_NVGRE;
6925 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6926 ret = mlx5_flow_validate_item_gre_key
6927 (items, item_flags, gre_item, error);
6930 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6932 case RTE_FLOW_ITEM_TYPE_VXLAN:
6933 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6937 last_item = MLX5_FLOW_LAYER_VXLAN;
6939 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6940 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6945 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6947 case RTE_FLOW_ITEM_TYPE_GENEVE:
6948 ret = mlx5_flow_validate_item_geneve(items,
6953 geneve_item = items;
6954 last_item = MLX5_FLOW_LAYER_GENEVE;
6956 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6957 ret = mlx5_flow_validate_item_geneve_opt(items,
6964 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6966 case RTE_FLOW_ITEM_TYPE_MPLS:
6967 ret = mlx5_flow_validate_item_mpls(dev, items,
6972 last_item = MLX5_FLOW_LAYER_MPLS;
6975 case RTE_FLOW_ITEM_TYPE_MARK:
6976 ret = flow_dv_validate_item_mark(dev, items, attr,
6980 last_item = MLX5_FLOW_ITEM_MARK;
6982 case RTE_FLOW_ITEM_TYPE_META:
6983 ret = flow_dv_validate_item_meta(dev, items, attr,
6987 last_item = MLX5_FLOW_ITEM_METADATA;
6989 case RTE_FLOW_ITEM_TYPE_ICMP:
6990 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6995 last_item = MLX5_FLOW_LAYER_ICMP;
6997 case RTE_FLOW_ITEM_TYPE_ICMP6:
6998 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7003 item_ipv6_proto = IPPROTO_ICMPV6;
7004 last_item = MLX5_FLOW_LAYER_ICMP6;
7006 case RTE_FLOW_ITEM_TYPE_TAG:
7007 ret = flow_dv_validate_item_tag(dev, items,
7011 last_item = MLX5_FLOW_ITEM_TAG;
7013 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7014 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7016 case RTE_FLOW_ITEM_TYPE_GTP:
7017 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7022 last_item = MLX5_FLOW_LAYER_GTP;
7024 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7025 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7030 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7032 case RTE_FLOW_ITEM_TYPE_ECPRI:
7033 /* Capacity will be checked in the translate stage. */
7034 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7041 last_item = MLX5_FLOW_LAYER_ECPRI;
7043 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7044 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY)
7045 return rte_flow_error_set
7047 RTE_FLOW_ERROR_TYPE_ITEM,
7048 NULL, "multiple integrity items not supported");
7049 ret = flow_dv_validate_item_integrity(dev, rule_items,
7053 last_item = MLX5_FLOW_ITEM_INTEGRITY;
7055 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7056 ret = flow_dv_validate_item_aso_ct(dev, items,
7057 &item_flags, error);
7061 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7062 /* tunnel offload item was processed before
7063 * list it here as a supported type
7067 return rte_flow_error_set(error, ENOTSUP,
7068 RTE_FLOW_ERROR_TYPE_ITEM,
7069 NULL, "item not supported");
7071 item_flags |= last_item;
7073 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7074 int type = actions->type;
7075 bool shared_count = false;
7077 if (!mlx5_flow_os_action_supported(type))
7078 return rte_flow_error_set(error, ENOTSUP,
7079 RTE_FLOW_ERROR_TYPE_ACTION,
7081 "action not supported");
7082 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7083 return rte_flow_error_set(error, ENOTSUP,
7084 RTE_FLOW_ERROR_TYPE_ACTION,
7085 actions, "too many actions");
7087 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7088 return rte_flow_error_set(error, ENOTSUP,
7089 RTE_FLOW_ERROR_TYPE_ACTION,
7090 NULL, "meter action with policy "
7091 "must be the last action");
7093 case RTE_FLOW_ACTION_TYPE_VOID:
7095 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7096 ret = flow_dv_validate_action_port_id(dev,
7103 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7106 case RTE_FLOW_ACTION_TYPE_FLAG:
7107 ret = flow_dv_validate_action_flag(dev, action_flags,
7111 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7112 /* Count all modify-header actions as one. */
7113 if (!(action_flags &
7114 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7116 action_flags |= MLX5_FLOW_ACTION_FLAG |
7117 MLX5_FLOW_ACTION_MARK_EXT;
7118 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7119 modify_after_mirror = 1;
7122 action_flags |= MLX5_FLOW_ACTION_FLAG;
7125 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7127 case RTE_FLOW_ACTION_TYPE_MARK:
7128 ret = flow_dv_validate_action_mark(dev, actions,
7133 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7134 /* Count all modify-header actions as one. */
7135 if (!(action_flags &
7136 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7138 action_flags |= MLX5_FLOW_ACTION_MARK |
7139 MLX5_FLOW_ACTION_MARK_EXT;
7140 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7141 modify_after_mirror = 1;
7143 action_flags |= MLX5_FLOW_ACTION_MARK;
7146 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7148 case RTE_FLOW_ACTION_TYPE_SET_META:
7149 ret = flow_dv_validate_action_set_meta(dev, actions,
7154 /* Count all modify-header actions as one action. */
7155 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7157 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7158 modify_after_mirror = 1;
7159 action_flags |= MLX5_FLOW_ACTION_SET_META;
7160 rw_act_num += MLX5_ACT_NUM_SET_META;
7162 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7163 ret = flow_dv_validate_action_set_tag(dev, actions,
7168 /* Count all modify-header actions as one action. */
7169 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7171 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7172 modify_after_mirror = 1;
7173 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7174 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7176 case RTE_FLOW_ACTION_TYPE_DROP:
7177 ret = mlx5_flow_validate_action_drop(action_flags,
7181 action_flags |= MLX5_FLOW_ACTION_DROP;
7184 case RTE_FLOW_ACTION_TYPE_QUEUE:
7185 ret = mlx5_flow_validate_action_queue(actions,
7190 queue_index = ((const struct rte_flow_action_queue *)
7191 (actions->conf))->index;
7192 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7195 case RTE_FLOW_ACTION_TYPE_RSS:
7196 rss = actions->conf;
7197 ret = mlx5_flow_validate_action_rss(actions,
7203 if (rss && sample_rss &&
7204 (sample_rss->level != rss->level ||
7205 sample_rss->types != rss->types))
7206 return rte_flow_error_set(error, ENOTSUP,
7207 RTE_FLOW_ERROR_TYPE_ACTION,
7209 "Can't use the different RSS types "
7210 "or level in the same flow");
7211 if (rss != NULL && rss->queue_num)
7212 queue_index = rss->queue[0];
7213 action_flags |= MLX5_FLOW_ACTION_RSS;
7216 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7218 mlx5_flow_validate_action_default_miss(action_flags,
7222 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7225 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7226 case RTE_FLOW_ACTION_TYPE_COUNT:
7227 shared_count = is_shared_action_count(actions);
7228 ret = flow_dv_validate_action_count(dev, shared_count,
7233 action_flags |= MLX5_FLOW_ACTION_COUNT;
7236 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7237 if (flow_dv_validate_action_pop_vlan(dev,
7243 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7244 modify_after_mirror = 1;
7245 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7248 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7249 ret = flow_dv_validate_action_push_vlan(dev,
7256 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7257 modify_after_mirror = 1;
7258 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7261 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7262 ret = flow_dv_validate_action_set_vlan_pcp
7263 (action_flags, actions, error);
7266 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7267 modify_after_mirror = 1;
7268 /* Count PCP with push_vlan command. */
7269 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7271 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7272 ret = flow_dv_validate_action_set_vlan_vid
7273 (item_flags, action_flags,
7277 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7278 modify_after_mirror = 1;
7279 /* Count VID with push_vlan command. */
7280 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7281 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7283 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7284 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7285 ret = flow_dv_validate_action_l2_encap(dev,
7291 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7294 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7295 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7296 ret = flow_dv_validate_action_decap(dev, action_flags,
7297 actions, item_flags,
7301 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7302 modify_after_mirror = 1;
7303 action_flags |= MLX5_FLOW_ACTION_DECAP;
7306 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7307 ret = flow_dv_validate_action_raw_encap_decap
7308 (dev, NULL, actions->conf, attr, &action_flags,
7309 &actions_n, actions, item_flags, error);
7313 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7314 decap = actions->conf;
7315 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7317 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7321 encap = actions->conf;
7323 ret = flow_dv_validate_action_raw_encap_decap
7325 decap ? decap : &empty_decap, encap,
7326 attr, &action_flags, &actions_n,
7327 actions, item_flags, error);
7330 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7331 (action_flags & MLX5_FLOW_ACTION_DECAP))
7332 modify_after_mirror = 1;
7334 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7335 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7336 ret = flow_dv_validate_action_modify_mac(action_flags,
7342 /* Count all modify-header actions as one action. */
7343 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7345 action_flags |= actions->type ==
7346 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7347 MLX5_FLOW_ACTION_SET_MAC_SRC :
7348 MLX5_FLOW_ACTION_SET_MAC_DST;
7349 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7350 modify_after_mirror = 1;
7352 * Even if the source and destination MAC addresses have
7353 * overlap in the header with 4B alignment, the convert
7354 * function will handle them separately and 4 SW actions
7355 * will be created. And 2 actions will be added each
7356 * time no matter how many bytes of address will be set.
7358 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7360 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7361 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7362 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7368 /* Count all modify-header actions as one action. */
7369 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7371 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7372 modify_after_mirror = 1;
7373 action_flags |= actions->type ==
7374 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7375 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7376 MLX5_FLOW_ACTION_SET_IPV4_DST;
7377 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7379 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7380 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7381 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7387 if (item_ipv6_proto == IPPROTO_ICMPV6)
7388 return rte_flow_error_set(error, ENOTSUP,
7389 RTE_FLOW_ERROR_TYPE_ACTION,
7391 "Can't change header "
7392 "with ICMPv6 proto");
7393 /* Count all modify-header actions as one action. */
7394 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7396 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7397 modify_after_mirror = 1;
7398 action_flags |= actions->type ==
7399 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7400 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7401 MLX5_FLOW_ACTION_SET_IPV6_DST;
7402 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7404 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7405 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7406 ret = flow_dv_validate_action_modify_tp(action_flags,
7412 /* Count all modify-header actions as one action. */
7413 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7415 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7416 modify_after_mirror = 1;
7417 action_flags |= actions->type ==
7418 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7419 MLX5_FLOW_ACTION_SET_TP_SRC :
7420 MLX5_FLOW_ACTION_SET_TP_DST;
7421 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7423 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7424 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7425 ret = flow_dv_validate_action_modify_ttl(action_flags,
7431 /* Count all modify-header actions as one action. */
7432 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7434 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7435 modify_after_mirror = 1;
7436 action_flags |= actions->type ==
7437 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7438 MLX5_FLOW_ACTION_SET_TTL :
7439 MLX5_FLOW_ACTION_DEC_TTL;
7440 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7442 case RTE_FLOW_ACTION_TYPE_JUMP:
7443 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7449 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7451 return rte_flow_error_set(error, EINVAL,
7452 RTE_FLOW_ERROR_TYPE_ACTION,
7454 "sample and jump action combination is not supported");
7456 action_flags |= MLX5_FLOW_ACTION_JUMP;
7458 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7459 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7460 ret = flow_dv_validate_action_modify_tcp_seq
7467 /* Count all modify-header actions as one action. */
7468 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7470 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7471 modify_after_mirror = 1;
7472 action_flags |= actions->type ==
7473 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7474 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7475 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7476 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7478 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7479 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7480 ret = flow_dv_validate_action_modify_tcp_ack
7487 /* Count all modify-header actions as one action. */
7488 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7490 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7491 modify_after_mirror = 1;
7492 action_flags |= actions->type ==
7493 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7494 MLX5_FLOW_ACTION_INC_TCP_ACK :
7495 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7496 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7498 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7500 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7501 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7502 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7504 case RTE_FLOW_ACTION_TYPE_METER:
7505 ret = mlx5_flow_validate_action_meter(dev,
7513 action_flags |= MLX5_FLOW_ACTION_METER;
7516 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7518 /* Meter action will add one more TAG action. */
7519 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7521 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7522 if (!attr->transfer && !attr->group)
7523 return rte_flow_error_set(error, ENOTSUP,
7524 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7526 "Shared ASO age action is not supported for group 0");
7527 if (action_flags & MLX5_FLOW_ACTION_AGE)
7528 return rte_flow_error_set
7530 RTE_FLOW_ERROR_TYPE_ACTION,
7532 "duplicate age actions set");
7533 action_flags |= MLX5_FLOW_ACTION_AGE;
7536 case RTE_FLOW_ACTION_TYPE_AGE:
7537 ret = flow_dv_validate_action_age(action_flags,
7543 * Validate the regular AGE action (using counter)
7544 * mutual exclusion with share counter actions.
7546 if (!priv->sh->flow_hit_aso_en) {
7548 return rte_flow_error_set
7550 RTE_FLOW_ERROR_TYPE_ACTION,
7552 "old age and shared count combination is not supported");
7554 return rte_flow_error_set
7556 RTE_FLOW_ERROR_TYPE_ACTION,
7558 "old age action and count must be in the same sub flow");
7560 action_flags |= MLX5_FLOW_ACTION_AGE;
7563 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7564 ret = flow_dv_validate_action_modify_ipv4_dscp
7571 /* Count all modify-header actions as one action. */
7572 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7574 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7575 modify_after_mirror = 1;
7576 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7577 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7579 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7580 ret = flow_dv_validate_action_modify_ipv6_dscp
7587 /* Count all modify-header actions as one action. */
7588 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7590 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7591 modify_after_mirror = 1;
7592 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7593 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7595 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7596 ret = flow_dv_validate_action_sample(&action_flags,
7605 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7608 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7609 ret = flow_dv_validate_action_modify_field(dev,
7616 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7617 modify_after_mirror = 1;
7618 /* Count all modify-header actions as one action. */
7619 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7621 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7624 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7625 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7630 action_flags |= MLX5_FLOW_ACTION_CT;
7632 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7633 /* tunnel offload action was processed before
7634 * list it here as a supported type
7638 return rte_flow_error_set(error, ENOTSUP,
7639 RTE_FLOW_ERROR_TYPE_ACTION,
7641 "action not supported");
7645 * Validate actions in flow rules
7646 * - Explicit decap action is prohibited by the tunnel offload API.
7647 * - Drop action in tunnel steer rule is prohibited by the API.
7648 * - Application cannot use MARK action because it's value can mask
7649 * tunnel default miss nitification.
7650 * - JUMP in tunnel match rule has no support in current PMD
7652 * - TAG & META are reserved for future uses.
7654 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7655 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7656 MLX5_FLOW_ACTION_MARK |
7657 MLX5_FLOW_ACTION_SET_TAG |
7658 MLX5_FLOW_ACTION_SET_META |
7659 MLX5_FLOW_ACTION_DROP;
7661 if (action_flags & bad_actions_mask)
7662 return rte_flow_error_set
7664 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7665 "Invalid RTE action in tunnel "
7667 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7668 return rte_flow_error_set
7670 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7671 "tunnel set decap rule must terminate "
7674 return rte_flow_error_set
7676 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7677 "tunnel flows for ingress traffic only");
7679 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7680 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7681 MLX5_FLOW_ACTION_MARK |
7682 MLX5_FLOW_ACTION_SET_TAG |
7683 MLX5_FLOW_ACTION_SET_META;
7685 if (action_flags & bad_actions_mask)
7686 return rte_flow_error_set
7688 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7689 "Invalid RTE action in tunnel "
7693 * Validate the drop action mutual exclusion with other actions.
7694 * Drop action is mutually-exclusive with any other action, except for
7696 * Drop action compatibility with tunnel offload was already validated.
7698 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7699 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7700 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7701 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7702 return rte_flow_error_set(error, EINVAL,
7703 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7704 "Drop action is mutually-exclusive "
7705 "with any other action, except for "
7707 /* Eswitch has few restrictions on using items and actions */
7708 if (attr->transfer) {
7709 if (!mlx5_flow_ext_mreg_supported(dev) &&
7710 action_flags & MLX5_FLOW_ACTION_FLAG)
7711 return rte_flow_error_set(error, ENOTSUP,
7712 RTE_FLOW_ERROR_TYPE_ACTION,
7714 "unsupported action FLAG");
7715 if (!mlx5_flow_ext_mreg_supported(dev) &&
7716 action_flags & MLX5_FLOW_ACTION_MARK)
7717 return rte_flow_error_set(error, ENOTSUP,
7718 RTE_FLOW_ERROR_TYPE_ACTION,
7720 "unsupported action MARK");
7721 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7722 return rte_flow_error_set(error, ENOTSUP,
7723 RTE_FLOW_ERROR_TYPE_ACTION,
7725 "unsupported action QUEUE");
7726 if (action_flags & MLX5_FLOW_ACTION_RSS)
7727 return rte_flow_error_set(error, ENOTSUP,
7728 RTE_FLOW_ERROR_TYPE_ACTION,
7730 "unsupported action RSS");
7731 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7732 return rte_flow_error_set(error, EINVAL,
7733 RTE_FLOW_ERROR_TYPE_ACTION,
7735 "no fate action is found");
7737 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7738 return rte_flow_error_set(error, EINVAL,
7739 RTE_FLOW_ERROR_TYPE_ACTION,
7741 "no fate action is found");
7744 * Continue validation for Xcap and VLAN actions.
7745 * If hairpin is working in explicit TX rule mode, there is no actions
7746 * splitting and the validation of hairpin ingress flow should be the
7747 * same as other standard flows.
7749 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7750 MLX5_FLOW_VLAN_ACTIONS)) &&
7751 (queue_index == 0xFFFF ||
7752 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7753 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7754 conf->tx_explicit != 0))) {
7755 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7756 MLX5_FLOW_XCAP_ACTIONS)
7757 return rte_flow_error_set(error, ENOTSUP,
7758 RTE_FLOW_ERROR_TYPE_ACTION,
7759 NULL, "encap and decap "
7760 "combination aren't supported");
7761 if (!attr->transfer && attr->ingress) {
7762 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7763 return rte_flow_error_set
7765 RTE_FLOW_ERROR_TYPE_ACTION,
7766 NULL, "encap is not supported"
7767 " for ingress traffic");
7768 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7769 return rte_flow_error_set
7771 RTE_FLOW_ERROR_TYPE_ACTION,
7772 NULL, "push VLAN action not "
7773 "supported for ingress");
7774 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7775 MLX5_FLOW_VLAN_ACTIONS)
7776 return rte_flow_error_set
7778 RTE_FLOW_ERROR_TYPE_ACTION,
7779 NULL, "no support for "
7780 "multiple VLAN actions");
7783 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7784 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7785 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7787 return rte_flow_error_set
7789 RTE_FLOW_ERROR_TYPE_ACTION,
7790 NULL, "fate action not supported for "
7791 "meter with policy");
7793 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7794 return rte_flow_error_set
7796 RTE_FLOW_ERROR_TYPE_ACTION,
7797 NULL, "modify header action in egress "
7798 "cannot be done before meter action");
7799 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7800 return rte_flow_error_set
7802 RTE_FLOW_ERROR_TYPE_ACTION,
7803 NULL, "encap action in egress "
7804 "cannot be done before meter action");
7805 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7806 return rte_flow_error_set
7808 RTE_FLOW_ERROR_TYPE_ACTION,
7809 NULL, "push vlan action in egress "
7810 "cannot be done before meter action");
7814 * Hairpin flow will add one more TAG action in TX implicit mode.
7815 * In TX explicit mode, there will be no hairpin flow ID.
7818 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7819 /* extra metadata enabled: one more TAG action will be add. */
7820 if (dev_conf->dv_flow_en &&
7821 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7822 mlx5_flow_ext_mreg_supported(dev))
7823 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7825 flow_dv_modify_hdr_action_max(dev, is_root)) {
7826 return rte_flow_error_set(error, ENOTSUP,
7827 RTE_FLOW_ERROR_TYPE_ACTION,
7828 NULL, "too many header modify"
7829 " actions to support");
7831 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7832 if (fdb_mirror_limit && modify_after_mirror)
7833 return rte_flow_error_set(error, EINVAL,
7834 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7835 "sample before modify action is not supported");
7840 * Internal preparation function. Allocates the DV flow size,
7841 * this size is constant.
7844 * Pointer to the rte_eth_dev structure.
7846 * Pointer to the flow attributes.
7848 * Pointer to the list of items.
7849 * @param[in] actions
7850 * Pointer to the list of actions.
7852 * Pointer to the error structure.
7855 * Pointer to mlx5_flow object on success,
7856 * otherwise NULL and rte_errno is set.
7858 static struct mlx5_flow *
7859 flow_dv_prepare(struct rte_eth_dev *dev,
7860 const struct rte_flow_attr *attr __rte_unused,
7861 const struct rte_flow_item items[] __rte_unused,
7862 const struct rte_flow_action actions[] __rte_unused,
7863 struct rte_flow_error *error)
7865 uint32_t handle_idx = 0;
7866 struct mlx5_flow *dev_flow;
7867 struct mlx5_flow_handle *dev_handle;
7868 struct mlx5_priv *priv = dev->data->dev_private;
7869 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7872 wks->skip_matcher_reg = 0;
7874 wks->final_policy = NULL;
7875 /* In case of corrupting the memory. */
7876 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7877 rte_flow_error_set(error, ENOSPC,
7878 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7879 "not free temporary device flow");
7882 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7885 rte_flow_error_set(error, ENOMEM,
7886 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7887 "not enough memory to create flow handle");
7890 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7891 dev_flow = &wks->flows[wks->flow_idx++];
7892 memset(dev_flow, 0, sizeof(*dev_flow));
7893 dev_flow->handle = dev_handle;
7894 dev_flow->handle_idx = handle_idx;
7896 * In some old rdma-core releases, before continuing, a check of the
7897 * length of matching parameter will be done at first. It needs to use
7898 * the length without misc4 param. If the flow has misc4 support, then
7899 * the length needs to be adjusted accordingly. Each param member is
7900 * aligned with a 64B boundary naturally.
7902 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7903 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7904 dev_flow->ingress = attr->ingress;
7905 dev_flow->dv.transfer = attr->transfer;
7909 #ifdef RTE_LIBRTE_MLX5_DEBUG
7911 * Sanity check for match mask and value. Similar to check_valid_spec() in
7912 * kernel driver. If unmasked bit is present in value, it returns failure.
7915 * pointer to match mask buffer.
7916 * @param match_value
7917 * pointer to match value buffer.
7920 * 0 if valid, -EINVAL otherwise.
7923 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7925 uint8_t *m = match_mask;
7926 uint8_t *v = match_value;
7929 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7932 "match_value differs from match_criteria"
7933 " %p[%u] != %p[%u]",
7934 match_value, i, match_mask, i);
7943 * Add match of ip_version.
7947 * @param[in] headers_v
7948 * Values header pointer.
7949 * @param[in] headers_m
7950 * Masks header pointer.
7951 * @param[in] ip_version
7952 * The IP version to set.
7955 flow_dv_set_match_ip_version(uint32_t group,
7961 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7963 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7965 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7966 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7967 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7971 * Add Ethernet item to matcher and to the value.
7973 * @param[in, out] matcher
7975 * @param[in, out] key
7976 * Flow matcher value.
7978 * Flow pattern to translate.
7980 * Item is inner pattern.
7983 flow_dv_translate_item_eth(void *matcher, void *key,
7984 const struct rte_flow_item *item, int inner,
7987 const struct rte_flow_item_eth *eth_m = item->mask;
7988 const struct rte_flow_item_eth *eth_v = item->spec;
7989 const struct rte_flow_item_eth nic_mask = {
7990 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7991 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7992 .type = RTE_BE16(0xffff),
8005 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8007 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8009 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8011 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8013 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8014 ð_m->dst, sizeof(eth_m->dst));
8015 /* The value must be in the range of the mask. */
8016 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8017 for (i = 0; i < sizeof(eth_m->dst); ++i)
8018 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8019 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8020 ð_m->src, sizeof(eth_m->src));
8021 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8022 /* The value must be in the range of the mask. */
8023 for (i = 0; i < sizeof(eth_m->dst); ++i)
8024 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8026 * HW supports match on one Ethertype, the Ethertype following the last
8027 * VLAN tag of the packet (see PRM).
8028 * Set match on ethertype only if ETH header is not followed by VLAN.
8029 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8030 * ethertype, and use ip_version field instead.
8031 * eCPRI over Ether layer will use type value 0xAEFE.
8033 if (eth_m->type == 0xFFFF) {
8034 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8035 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8036 switch (eth_v->type) {
8037 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8038 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8040 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8041 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8042 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8044 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8045 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8047 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8048 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8054 if (eth_m->has_vlan) {
8055 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8056 if (eth_v->has_vlan) {
8058 * Here, when also has_more_vlan field in VLAN item is
8059 * not set, only single-tagged packets will be matched.
8061 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8065 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8066 rte_be_to_cpu_16(eth_m->type));
8067 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8068 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8072 * Add VLAN item to matcher and to the value.
8074 * @param[in, out] dev_flow
8076 * @param[in, out] matcher
8078 * @param[in, out] key
8079 * Flow matcher value.
8081 * Flow pattern to translate.
8083 * Item is inner pattern.
8086 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8087 void *matcher, void *key,
8088 const struct rte_flow_item *item,
8089 int inner, uint32_t group)
8091 const struct rte_flow_item_vlan *vlan_m = item->mask;
8092 const struct rte_flow_item_vlan *vlan_v = item->spec;
8099 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8101 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8103 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8105 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8107 * This is workaround, masks are not supported,
8108 * and pre-validated.
8111 dev_flow->handle->vf_vlan.tag =
8112 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8115 * When VLAN item exists in flow, mark packet as tagged,
8116 * even if TCI is not specified.
8118 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8119 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8120 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8125 vlan_m = &rte_flow_item_vlan_mask;
8126 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8127 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8128 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8129 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8130 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8131 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8132 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8133 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8135 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8136 * ethertype, and use ip_version field instead.
8138 if (vlan_m->inner_type == 0xFFFF) {
8139 switch (vlan_v->inner_type) {
8140 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8141 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8142 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8143 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8145 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8146 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8148 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8149 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8155 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8156 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8157 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8158 /* Only one vlan_tag bit can be set. */
8159 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8162 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8163 rte_be_to_cpu_16(vlan_m->inner_type));
8164 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8165 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8169 * Add IPV4 item to matcher and to the value.
8171 * @param[in, out] matcher
8173 * @param[in, out] key
8174 * Flow matcher value.
8176 * Flow pattern to translate.
8178 * Item is inner pattern.
8180 * The group to insert the rule.
8183 flow_dv_translate_item_ipv4(void *matcher, void *key,
8184 const struct rte_flow_item *item,
8185 int inner, uint32_t group)
8187 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8188 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8189 const struct rte_flow_item_ipv4 nic_mask = {
8191 .src_addr = RTE_BE32(0xffffffff),
8192 .dst_addr = RTE_BE32(0xffffffff),
8193 .type_of_service = 0xff,
8194 .next_proto_id = 0xff,
8195 .time_to_live = 0xff,
8205 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8207 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8209 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8211 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8213 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8218 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8219 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8220 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8221 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8222 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8223 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8224 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8225 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8226 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8227 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8228 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8229 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8230 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8231 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8232 ipv4_m->hdr.type_of_service);
8233 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8235 ipv4_m->hdr.type_of_service >> 2);
8236 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8237 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8238 ipv4_m->hdr.next_proto_id);
8239 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8240 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8241 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8242 ipv4_m->hdr.time_to_live);
8243 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8244 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8245 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8246 !!(ipv4_m->hdr.fragment_offset));
8247 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8248 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8252 * Add IPV6 item to matcher and to the value.
8254 * @param[in, out] matcher
8256 * @param[in, out] key
8257 * Flow matcher value.
8259 * Flow pattern to translate.
8261 * Item is inner pattern.
8263 * The group to insert the rule.
8266 flow_dv_translate_item_ipv6(void *matcher, void *key,
8267 const struct rte_flow_item *item,
8268 int inner, uint32_t group)
8270 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8271 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8272 const struct rte_flow_item_ipv6 nic_mask = {
8275 "\xff\xff\xff\xff\xff\xff\xff\xff"
8276 "\xff\xff\xff\xff\xff\xff\xff\xff",
8278 "\xff\xff\xff\xff\xff\xff\xff\xff"
8279 "\xff\xff\xff\xff\xff\xff\xff\xff",
8280 .vtc_flow = RTE_BE32(0xffffffff),
8287 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8288 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8297 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8299 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8301 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8303 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8305 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8310 size = sizeof(ipv6_m->hdr.dst_addr);
8311 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8312 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8313 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8314 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8315 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8316 for (i = 0; i < size; ++i)
8317 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8318 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8319 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8320 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8321 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8322 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8323 for (i = 0; i < size; ++i)
8324 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8326 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8327 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8328 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8329 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8330 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8331 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8334 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8336 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8339 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8341 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8345 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8347 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8348 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8350 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8351 ipv6_m->hdr.hop_limits);
8352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8353 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8354 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8355 !!(ipv6_m->has_frag_ext));
8356 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8357 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8361 * Add IPV6 fragment extension item to matcher and to the value.
8363 * @param[in, out] matcher
8365 * @param[in, out] key
8366 * Flow matcher value.
8368 * Flow pattern to translate.
8370 * Item is inner pattern.
8373 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8374 const struct rte_flow_item *item,
8377 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8378 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8379 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8381 .next_header = 0xff,
8382 .frag_data = RTE_BE16(0xffff),
8389 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8391 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8393 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8395 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8397 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8398 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8400 if (!ipv6_frag_ext_v)
8402 if (!ipv6_frag_ext_m)
8403 ipv6_frag_ext_m = &nic_mask;
8404 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8405 ipv6_frag_ext_m->hdr.next_header);
8406 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8407 ipv6_frag_ext_v->hdr.next_header &
8408 ipv6_frag_ext_m->hdr.next_header);
8412 * Add TCP item to matcher and to the value.
8414 * @param[in, out] matcher
8416 * @param[in, out] key
8417 * Flow matcher value.
8419 * Flow pattern to translate.
8421 * Item is inner pattern.
8424 flow_dv_translate_item_tcp(void *matcher, void *key,
8425 const struct rte_flow_item *item,
8428 const struct rte_flow_item_tcp *tcp_m = item->mask;
8429 const struct rte_flow_item_tcp *tcp_v = item->spec;
8434 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8436 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8438 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8440 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8442 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8443 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8447 tcp_m = &rte_flow_item_tcp_mask;
8448 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8449 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8450 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8451 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8452 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8453 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8455 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8456 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8457 tcp_m->hdr.tcp_flags);
8458 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8459 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8463 * Add UDP item to matcher and to the value.
8465 * @param[in, out] matcher
8467 * @param[in, out] key
8468 * Flow matcher value.
8470 * Flow pattern to translate.
8472 * Item is inner pattern.
8475 flow_dv_translate_item_udp(void *matcher, void *key,
8476 const struct rte_flow_item *item,
8479 const struct rte_flow_item_udp *udp_m = item->mask;
8480 const struct rte_flow_item_udp *udp_v = item->spec;
8485 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8487 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8489 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8491 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8498 udp_m = &rte_flow_item_udp_mask;
8499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8500 rte_be_to_cpu_16(udp_m->hdr.src_port));
8501 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8502 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8503 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8504 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8505 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8506 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8510 * Add GRE optional Key item to matcher and to the value.
8512 * @param[in, out] matcher
8514 * @param[in, out] key
8515 * Flow matcher value.
8517 * Flow pattern to translate.
8519 * Item is inner pattern.
8522 flow_dv_translate_item_gre_key(void *matcher, void *key,
8523 const struct rte_flow_item *item)
8525 const rte_be32_t *key_m = item->mask;
8526 const rte_be32_t *key_v = item->spec;
8527 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8528 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8529 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8531 /* GRE K bit must be on and should already be validated */
8532 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8533 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8537 key_m = &gre_key_default_mask;
8538 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8539 rte_be_to_cpu_32(*key_m) >> 8);
8540 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8541 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8542 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8543 rte_be_to_cpu_32(*key_m) & 0xFF);
8544 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8545 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8549 * Add GRE item to matcher and to the value.
8551 * @param[in, out] matcher
8553 * @param[in, out] key
8554 * Flow matcher value.
8556 * Flow pattern to translate.
8558 * Item is inner pattern.
8561 flow_dv_translate_item_gre(void *matcher, void *key,
8562 const struct rte_flow_item *item,
8565 const struct rte_flow_item_gre *gre_m = item->mask;
8566 const struct rte_flow_item_gre *gre_v = item->spec;
8569 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8570 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8577 uint16_t s_present:1;
8578 uint16_t k_present:1;
8579 uint16_t rsvd_bit1:1;
8580 uint16_t c_present:1;
8584 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8587 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8589 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8591 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8593 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8595 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8596 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8600 gre_m = &rte_flow_item_gre_mask;
8601 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8602 rte_be_to_cpu_16(gre_m->protocol));
8603 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8604 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8605 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8606 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8607 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8608 gre_crks_rsvd0_ver_m.c_present);
8609 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8610 gre_crks_rsvd0_ver_v.c_present &
8611 gre_crks_rsvd0_ver_m.c_present);
8612 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8613 gre_crks_rsvd0_ver_m.k_present);
8614 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8615 gre_crks_rsvd0_ver_v.k_present &
8616 gre_crks_rsvd0_ver_m.k_present);
8617 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8618 gre_crks_rsvd0_ver_m.s_present);
8619 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8620 gre_crks_rsvd0_ver_v.s_present &
8621 gre_crks_rsvd0_ver_m.s_present);
8625 * Add NVGRE item to matcher and to the value.
8627 * @param[in, out] matcher
8629 * @param[in, out] key
8630 * Flow matcher value.
8632 * Flow pattern to translate.
8634 * Item is inner pattern.
8637 flow_dv_translate_item_nvgre(void *matcher, void *key,
8638 const struct rte_flow_item *item,
8641 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8642 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8643 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8644 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8645 const char *tni_flow_id_m;
8646 const char *tni_flow_id_v;
8652 /* For NVGRE, GRE header fields must be set with defined values. */
8653 const struct rte_flow_item_gre gre_spec = {
8654 .c_rsvd0_ver = RTE_BE16(0x2000),
8655 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8657 const struct rte_flow_item_gre gre_mask = {
8658 .c_rsvd0_ver = RTE_BE16(0xB000),
8659 .protocol = RTE_BE16(UINT16_MAX),
8661 const struct rte_flow_item gre_item = {
8666 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8670 nvgre_m = &rte_flow_item_nvgre_mask;
8671 tni_flow_id_m = (const char *)nvgre_m->tni;
8672 tni_flow_id_v = (const char *)nvgre_v->tni;
8673 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8674 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8675 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8676 memcpy(gre_key_m, tni_flow_id_m, size);
8677 for (i = 0; i < size; ++i)
8678 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8682 * Add VXLAN item to matcher and to the value.
8684 * @param[in, out] matcher
8686 * @param[in, out] key
8687 * Flow matcher value.
8689 * Flow pattern to translate.
8691 * Item is inner pattern.
8694 flow_dv_translate_item_vxlan(void *matcher, void *key,
8695 const struct rte_flow_item *item,
8698 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8699 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8702 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8703 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8711 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8713 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8715 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8717 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8719 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8720 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8721 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8723 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8728 vxlan_m = &rte_flow_item_vxlan_mask;
8729 size = sizeof(vxlan_m->vni);
8730 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8731 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8732 memcpy(vni_m, vxlan_m->vni, size);
8733 for (i = 0; i < size; ++i)
8734 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8738 * Add VXLAN-GPE item to matcher and to the value.
8740 * @param[in, out] matcher
8742 * @param[in, out] key
8743 * Flow matcher value.
8745 * Flow pattern to translate.
8747 * Item is inner pattern.
8751 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8752 const struct rte_flow_item *item, int inner)
8754 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8755 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8759 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8761 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8767 uint8_t flags_m = 0xff;
8768 uint8_t flags_v = 0xc;
8771 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8773 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8775 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8777 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8779 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8780 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8781 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8782 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8783 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8788 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8789 size = sizeof(vxlan_m->vni);
8790 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8791 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8792 memcpy(vni_m, vxlan_m->vni, size);
8793 for (i = 0; i < size; ++i)
8794 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8795 if (vxlan_m->flags) {
8796 flags_m = vxlan_m->flags;
8797 flags_v = vxlan_v->flags;
8799 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8800 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8801 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8803 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8808 * Add Geneve item to matcher and to the value.
8810 * @param[in, out] matcher
8812 * @param[in, out] key
8813 * Flow matcher value.
8815 * Flow pattern to translate.
8817 * Item is inner pattern.
8821 flow_dv_translate_item_geneve(void *matcher, void *key,
8822 const struct rte_flow_item *item, int inner)
8824 const struct rte_flow_item_geneve *geneve_m = item->mask;
8825 const struct rte_flow_item_geneve *geneve_v = item->spec;
8828 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8829 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8838 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8840 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8842 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8844 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8846 dport = MLX5_UDP_PORT_GENEVE;
8847 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8848 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8849 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8854 geneve_m = &rte_flow_item_geneve_mask;
8855 size = sizeof(geneve_m->vni);
8856 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8857 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8858 memcpy(vni_m, geneve_m->vni, size);
8859 for (i = 0; i < size; ++i)
8860 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8861 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8862 rte_be_to_cpu_16(geneve_m->protocol));
8863 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8864 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8865 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8866 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8867 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8868 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8869 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8870 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8871 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8872 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8873 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8874 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8875 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8879 * Create Geneve TLV option resource.
8881 * @param dev[in, out]
8882 * Pointer to rte_eth_dev structure.
8883 * @param[in, out] tag_be24
8884 * Tag value in big endian then R-shift 8.
8885 * @parm[in, out] dev_flow
8886 * Pointer to the dev_flow.
8888 * pointer to error structure.
8891 * 0 on success otherwise -errno and errno is set.
8895 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8896 const struct rte_flow_item *item,
8897 struct rte_flow_error *error)
8899 struct mlx5_priv *priv = dev->data->dev_private;
8900 struct mlx5_dev_ctx_shared *sh = priv->sh;
8901 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8902 sh->geneve_tlv_option_resource;
8903 struct mlx5_devx_obj *obj;
8904 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8909 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8910 if (geneve_opt_resource != NULL) {
8911 if (geneve_opt_resource->option_class ==
8912 geneve_opt_v->option_class &&
8913 geneve_opt_resource->option_type ==
8914 geneve_opt_v->option_type &&
8915 geneve_opt_resource->length ==
8916 geneve_opt_v->option_len) {
8917 /* We already have GENVE TLV option obj allocated. */
8918 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8921 ret = rte_flow_error_set(error, ENOMEM,
8922 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8923 "Only one GENEVE TLV option supported");
8927 /* Create a GENEVE TLV object and resource. */
8928 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8929 geneve_opt_v->option_class,
8930 geneve_opt_v->option_type,
8931 geneve_opt_v->option_len);
8933 ret = rte_flow_error_set(error, ENODATA,
8934 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8935 "Failed to create GENEVE TLV Devx object");
8938 sh->geneve_tlv_option_resource =
8939 mlx5_malloc(MLX5_MEM_ZERO,
8940 sizeof(*geneve_opt_resource),
8942 if (!sh->geneve_tlv_option_resource) {
8943 claim_zero(mlx5_devx_cmd_destroy(obj));
8944 ret = rte_flow_error_set(error, ENOMEM,
8945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8946 "GENEVE TLV object memory allocation failed");
8949 geneve_opt_resource = sh->geneve_tlv_option_resource;
8950 geneve_opt_resource->obj = obj;
8951 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8952 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8953 geneve_opt_resource->length = geneve_opt_v->option_len;
8954 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8958 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8963 * Add Geneve TLV option item to matcher.
8965 * @param[in, out] dev
8966 * Pointer to rte_eth_dev structure.
8967 * @param[in, out] matcher
8969 * @param[in, out] key
8970 * Flow matcher value.
8972 * Flow pattern to translate.
8974 * Pointer to error structure.
8977 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8978 void *key, const struct rte_flow_item *item,
8979 struct rte_flow_error *error)
8981 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8982 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8983 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8984 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8985 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8987 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8988 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8994 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8995 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8998 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9002 * Set the option length in GENEVE header if not requested.
9003 * The GENEVE TLV option length is expressed by the option length field
9004 * in the GENEVE header.
9005 * If the option length was not requested but the GENEVE TLV option item
9006 * is present we set the option length field implicitly.
9008 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9009 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9010 MLX5_GENEVE_OPTLEN_MASK);
9011 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9012 geneve_opt_v->option_len + 1);
9015 if (geneve_opt_v->data) {
9016 memcpy(&opt_data_key, geneve_opt_v->data,
9017 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9018 sizeof(opt_data_key)));
9019 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9020 sizeof(opt_data_key));
9021 memcpy(&opt_data_mask, geneve_opt_m->data,
9022 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9023 sizeof(opt_data_mask)));
9024 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9025 sizeof(opt_data_mask));
9026 MLX5_SET(fte_match_set_misc3, misc3_m,
9027 geneve_tlv_option_0_data,
9028 rte_be_to_cpu_32(opt_data_mask));
9029 MLX5_SET(fte_match_set_misc3, misc3_v,
9030 geneve_tlv_option_0_data,
9031 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9037 * Add MPLS item to matcher and to the value.
9039 * @param[in, out] matcher
9041 * @param[in, out] key
9042 * Flow matcher value.
9044 * Flow pattern to translate.
9045 * @param[in] prev_layer
9046 * The protocol layer indicated in previous item.
9048 * Item is inner pattern.
9051 flow_dv_translate_item_mpls(void *matcher, void *key,
9052 const struct rte_flow_item *item,
9053 uint64_t prev_layer,
9056 const uint32_t *in_mpls_m = item->mask;
9057 const uint32_t *in_mpls_v = item->spec;
9058 uint32_t *out_mpls_m = 0;
9059 uint32_t *out_mpls_v = 0;
9060 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9061 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9062 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9064 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9065 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9066 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9068 switch (prev_layer) {
9069 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9070 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9071 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9072 MLX5_UDP_PORT_MPLS);
9074 case MLX5_FLOW_LAYER_GRE:
9076 case MLX5_FLOW_LAYER_GRE_KEY:
9077 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9078 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9079 RTE_ETHER_TYPE_MPLS);
9087 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9088 switch (prev_layer) {
9089 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9091 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9092 outer_first_mpls_over_udp);
9094 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9095 outer_first_mpls_over_udp);
9097 case MLX5_FLOW_LAYER_GRE:
9099 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9100 outer_first_mpls_over_gre);
9102 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9103 outer_first_mpls_over_gre);
9106 /* Inner MPLS not over GRE is not supported. */
9109 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9113 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9119 if (out_mpls_m && out_mpls_v) {
9120 *out_mpls_m = *in_mpls_m;
9121 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9126 * Add metadata register item to matcher
9128 * @param[in, out] matcher
9130 * @param[in, out] key
9131 * Flow matcher value.
9132 * @param[in] reg_type
9133 * Type of device metadata register
9140 flow_dv_match_meta_reg(void *matcher, void *key,
9141 enum modify_reg reg_type,
9142 uint32_t data, uint32_t mask)
9145 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9147 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9153 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9154 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9157 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9158 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9162 * The metadata register C0 field might be divided into
9163 * source vport index and META item value, we should set
9164 * this field according to specified mask, not as whole one.
9166 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9168 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9169 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9172 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9175 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9176 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9179 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9180 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9183 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9184 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9187 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9188 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9191 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9192 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9195 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9196 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9199 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9200 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9209 * Add MARK item to matcher
9212 * The device to configure through.
9213 * @param[in, out] matcher
9215 * @param[in, out] key
9216 * Flow matcher value.
9218 * Flow pattern to translate.
9221 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9222 void *matcher, void *key,
9223 const struct rte_flow_item *item)
9225 struct mlx5_priv *priv = dev->data->dev_private;
9226 const struct rte_flow_item_mark *mark;
9230 mark = item->mask ? (const void *)item->mask :
9231 &rte_flow_item_mark_mask;
9232 mask = mark->id & priv->sh->dv_mark_mask;
9233 mark = (const void *)item->spec;
9235 value = mark->id & priv->sh->dv_mark_mask & mask;
9237 enum modify_reg reg;
9239 /* Get the metadata register index for the mark. */
9240 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9241 MLX5_ASSERT(reg > 0);
9242 if (reg == REG_C_0) {
9243 struct mlx5_priv *priv = dev->data->dev_private;
9244 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9245 uint32_t shl_c0 = rte_bsf32(msk_c0);
9251 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9256 * Add META item to matcher
9259 * The devich to configure through.
9260 * @param[in, out] matcher
9262 * @param[in, out] key
9263 * Flow matcher value.
9265 * Attributes of flow that includes this item.
9267 * Flow pattern to translate.
9270 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9271 void *matcher, void *key,
9272 const struct rte_flow_attr *attr,
9273 const struct rte_flow_item *item)
9275 const struct rte_flow_item_meta *meta_m;
9276 const struct rte_flow_item_meta *meta_v;
9278 meta_m = (const void *)item->mask;
9280 meta_m = &rte_flow_item_meta_mask;
9281 meta_v = (const void *)item->spec;
9284 uint32_t value = meta_v->data;
9285 uint32_t mask = meta_m->data;
9287 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9290 MLX5_ASSERT(reg != REG_NON);
9291 if (reg == REG_C_0) {
9292 struct mlx5_priv *priv = dev->data->dev_private;
9293 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9294 uint32_t shl_c0 = rte_bsf32(msk_c0);
9300 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9305 * Add vport metadata Reg C0 item to matcher
9307 * @param[in, out] matcher
9309 * @param[in, out] key
9310 * Flow matcher value.
9312 * Flow pattern to translate.
9315 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9316 uint32_t value, uint32_t mask)
9318 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9322 * Add tag item to matcher
9325 * The devich to configure through.
9326 * @param[in, out] matcher
9328 * @param[in, out] key
9329 * Flow matcher value.
9331 * Flow pattern to translate.
9334 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9335 void *matcher, void *key,
9336 const struct rte_flow_item *item)
9338 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9339 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9340 uint32_t mask, value;
9343 value = tag_v->data;
9344 mask = tag_m ? tag_m->data : UINT32_MAX;
9345 if (tag_v->id == REG_C_0) {
9346 struct mlx5_priv *priv = dev->data->dev_private;
9347 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9348 uint32_t shl_c0 = rte_bsf32(msk_c0);
9354 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9358 * Add TAG item to matcher
9361 * The devich to configure through.
9362 * @param[in, out] matcher
9364 * @param[in, out] key
9365 * Flow matcher value.
9367 * Flow pattern to translate.
9370 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9371 void *matcher, void *key,
9372 const struct rte_flow_item *item)
9374 const struct rte_flow_item_tag *tag_v = item->spec;
9375 const struct rte_flow_item_tag *tag_m = item->mask;
9376 enum modify_reg reg;
9379 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9380 /* Get the metadata register index for the tag. */
9381 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9382 MLX5_ASSERT(reg > 0);
9383 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9387 * Add source vport match to the specified matcher.
9389 * @param[in, out] matcher
9391 * @param[in, out] key
9392 * Flow matcher value.
9394 * Source vport value to match
9399 flow_dv_translate_item_source_vport(void *matcher, void *key,
9400 int16_t port, uint16_t mask)
9402 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9403 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9405 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9406 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9410 * Translate port-id item to eswitch match on port-id.
9413 * The devich to configure through.
9414 * @param[in, out] matcher
9416 * @param[in, out] key
9417 * Flow matcher value.
9419 * Flow pattern to translate.
9424 * 0 on success, a negative errno value otherwise.
9427 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9428 void *key, const struct rte_flow_item *item,
9429 const struct rte_flow_attr *attr)
9431 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9432 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9433 struct mlx5_priv *priv;
9436 mask = pid_m ? pid_m->id : 0xffff;
9437 id = pid_v ? pid_v->id : dev->data->port_id;
9438 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9442 * Translate to vport field or to metadata, depending on mode.
9443 * Kernel can use either misc.source_port or half of C0 metadata
9446 if (priv->vport_meta_mask) {
9448 * Provide the hint for SW steering library
9449 * to insert the flow into ingress domain and
9450 * save the extra vport match.
9452 if (mask == 0xffff && priv->vport_id == 0xffff &&
9453 priv->pf_bond < 0 && attr->transfer)
9454 flow_dv_translate_item_source_vport
9455 (matcher, key, priv->vport_id, mask);
9457 * We should always set the vport metadata register,
9458 * otherwise the SW steering library can drop
9459 * the rule if wire vport metadata value is not zero,
9460 * it depends on kernel configuration.
9462 flow_dv_translate_item_meta_vport(matcher, key,
9463 priv->vport_meta_tag,
9464 priv->vport_meta_mask);
9466 flow_dv_translate_item_source_vport(matcher, key,
9467 priv->vport_id, mask);
9473 * Add ICMP6 item to matcher and to the value.
9475 * @param[in, out] matcher
9477 * @param[in, out] key
9478 * Flow matcher value.
9480 * Flow pattern to translate.
9482 * Item is inner pattern.
9485 flow_dv_translate_item_icmp6(void *matcher, void *key,
9486 const struct rte_flow_item *item,
9489 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9490 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9493 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9495 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9497 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9499 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9501 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9503 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9505 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9510 icmp6_m = &rte_flow_item_icmp6_mask;
9511 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9512 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9513 icmp6_v->type & icmp6_m->type);
9514 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9515 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9516 icmp6_v->code & icmp6_m->code);
9520 * Add ICMP item to matcher and to the value.
9522 * @param[in, out] matcher
9524 * @param[in, out] key
9525 * Flow matcher value.
9527 * Flow pattern to translate.
9529 * Item is inner pattern.
9532 flow_dv_translate_item_icmp(void *matcher, void *key,
9533 const struct rte_flow_item *item,
9536 const struct rte_flow_item_icmp *icmp_m = item->mask;
9537 const struct rte_flow_item_icmp *icmp_v = item->spec;
9538 uint32_t icmp_header_data_m = 0;
9539 uint32_t icmp_header_data_v = 0;
9542 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9544 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9546 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9548 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9550 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9552 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9555 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9559 icmp_m = &rte_flow_item_icmp_mask;
9560 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9561 icmp_m->hdr.icmp_type);
9562 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9563 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9564 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9565 icmp_m->hdr.icmp_code);
9566 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9567 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9568 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9569 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9570 if (icmp_header_data_m) {
9571 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9572 icmp_header_data_v |=
9573 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9574 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9575 icmp_header_data_m);
9576 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9577 icmp_header_data_v & icmp_header_data_m);
9582 * Add GTP item to matcher and to the value.
9584 * @param[in, out] matcher
9586 * @param[in, out] key
9587 * Flow matcher value.
9589 * Flow pattern to translate.
9591 * Item is inner pattern.
9594 flow_dv_translate_item_gtp(void *matcher, void *key,
9595 const struct rte_flow_item *item, int inner)
9597 const struct rte_flow_item_gtp *gtp_m = item->mask;
9598 const struct rte_flow_item_gtp *gtp_v = item->spec;
9601 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9603 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9604 uint16_t dport = RTE_GTPU_UDP_PORT;
9607 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9609 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9611 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9613 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9615 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9616 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9617 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9622 gtp_m = &rte_flow_item_gtp_mask;
9623 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9624 gtp_m->v_pt_rsv_flags);
9625 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9626 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9627 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9628 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9629 gtp_v->msg_type & gtp_m->msg_type);
9630 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9631 rte_be_to_cpu_32(gtp_m->teid));
9632 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9633 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9637 * Add GTP PSC item to matcher.
9639 * @param[in, out] matcher
9641 * @param[in, out] key
9642 * Flow matcher value.
9644 * Flow pattern to translate.
9647 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9648 const struct rte_flow_item *item)
9650 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9651 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9652 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9654 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9660 uint8_t next_ext_header_type;
9665 /* Always set E-flag match on one, regardless of GTP item settings. */
9666 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9667 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9668 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9669 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9670 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9671 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9672 /*Set next extension header type. */
9675 dw_2.next_ext_header_type = 0xff;
9676 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9677 rte_cpu_to_be_32(dw_2.w32));
9680 dw_2.next_ext_header_type = 0x85;
9681 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9682 rte_cpu_to_be_32(dw_2.w32));
9694 /*Set extension header PDU type and Qos. */
9696 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9698 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9699 dw_0.qfi = gtp_psc_m->qfi;
9700 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9701 rte_cpu_to_be_32(dw_0.w32));
9703 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9704 gtp_psc_m->pdu_type);
9705 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9706 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9707 rte_cpu_to_be_32(dw_0.w32));
9713 * Add eCPRI item to matcher and to the value.
9716 * The devich to configure through.
9717 * @param[in, out] matcher
9719 * @param[in, out] key
9720 * Flow matcher value.
9722 * Flow pattern to translate.
9723 * @param[in] samples
9724 * Sample IDs to be used in the matching.
9727 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9728 void *key, const struct rte_flow_item *item)
9730 struct mlx5_priv *priv = dev->data->dev_private;
9731 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9732 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9733 struct rte_ecpri_common_hdr common;
9734 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9736 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9744 ecpri_m = &rte_flow_item_ecpri_mask;
9746 * Maximal four DW samples are supported in a single matching now.
9747 * Two are used now for a eCPRI matching:
9748 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9749 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9752 if (!ecpri_m->hdr.common.u32)
9754 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9755 /* Need to take the whole DW as the mask to fill the entry. */
9756 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9757 prog_sample_field_value_0);
9758 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9759 prog_sample_field_value_0);
9760 /* Already big endian (network order) in the header. */
9761 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9762 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9763 /* Sample#0, used for matching type, offset 0. */
9764 MLX5_SET(fte_match_set_misc4, misc4_m,
9765 prog_sample_field_id_0, samples[0]);
9766 /* It makes no sense to set the sample ID in the mask field. */
9767 MLX5_SET(fte_match_set_misc4, misc4_v,
9768 prog_sample_field_id_0, samples[0]);
9770 * Checking if message body part needs to be matched.
9771 * Some wildcard rules only matching type field should be supported.
9773 if (ecpri_m->hdr.dummy[0]) {
9774 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9775 switch (common.type) {
9776 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9777 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9778 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9779 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9780 prog_sample_field_value_1);
9781 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9782 prog_sample_field_value_1);
9783 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9784 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9785 ecpri_m->hdr.dummy[0];
9786 /* Sample#1, to match message body, offset 4. */
9787 MLX5_SET(fte_match_set_misc4, misc4_m,
9788 prog_sample_field_id_1, samples[1]);
9789 MLX5_SET(fte_match_set_misc4, misc4_v,
9790 prog_sample_field_id_1, samples[1]);
9793 /* Others, do not match any sample ID. */
9800 * Add connection tracking status item to matcher
9803 * The devich to configure through.
9804 * @param[in, out] matcher
9806 * @param[in, out] key
9807 * Flow matcher value.
9809 * Flow pattern to translate.
9812 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
9813 void *matcher, void *key,
9814 const struct rte_flow_item *item)
9816 uint32_t reg_value = 0;
9818 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
9819 uint32_t reg_mask = 0;
9820 const struct rte_flow_item_conntrack *spec = item->spec;
9821 const struct rte_flow_item_conntrack *mask = item->mask;
9823 struct rte_flow_error error;
9826 mask = &rte_flow_item_conntrack_mask;
9827 if (!spec || !mask->flags)
9829 flags = spec->flags & mask->flags;
9830 /* The conflict should be checked in the validation. */
9831 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
9832 reg_value |= MLX5_CT_SYNDROME_VALID;
9833 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
9834 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
9835 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
9836 reg_value |= MLX5_CT_SYNDROME_INVALID;
9837 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
9838 reg_value |= MLX5_CT_SYNDROME_TRAP;
9839 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
9840 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
9841 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
9842 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
9843 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
9845 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
9846 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
9847 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
9848 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
9849 /* The REG_C_x value could be saved during startup. */
9850 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
9851 if (reg_id == REG_NON)
9853 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
9854 reg_value, reg_mask);
9857 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9859 #define HEADER_IS_ZERO(match_criteria, headers) \
9860 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9861 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9864 * Calculate flow matcher enable bitmap.
9866 * @param match_criteria
9867 * Pointer to flow matcher criteria.
9870 * Bitmap of enabled fields.
9873 flow_dv_matcher_enable(uint32_t *match_criteria)
9875 uint8_t match_criteria_enable;
9877 match_criteria_enable =
9878 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9879 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9880 match_criteria_enable |=
9881 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9882 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9883 match_criteria_enable |=
9884 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9885 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9886 match_criteria_enable |=
9887 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9888 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9889 match_criteria_enable |=
9890 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9891 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9892 match_criteria_enable |=
9893 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9894 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9895 return match_criteria_enable;
9898 struct mlx5_hlist_entry *
9899 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9901 struct mlx5_dev_ctx_shared *sh = list->ctx;
9902 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9903 struct rte_eth_dev *dev = ctx->dev;
9904 struct mlx5_flow_tbl_data_entry *tbl_data;
9905 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9906 struct rte_flow_error *error = ctx->error;
9907 union mlx5_flow_tbl_key key = { .v64 = key64 };
9908 struct mlx5_flow_tbl_resource *tbl;
9913 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9915 rte_flow_error_set(error, ENOMEM,
9916 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9918 "cannot allocate flow table data entry");
9921 tbl_data->idx = idx;
9922 tbl_data->tunnel = tt_prm->tunnel;
9923 tbl_data->group_id = tt_prm->group_id;
9924 tbl_data->external = !!tt_prm->external;
9925 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9926 tbl_data->is_egress = !!key.is_egress;
9927 tbl_data->is_transfer = !!key.is_fdb;
9928 tbl_data->dummy = !!key.dummy;
9929 tbl_data->level = key.level;
9930 tbl_data->id = key.id;
9931 tbl = &tbl_data->tbl;
9933 return &tbl_data->entry;
9935 domain = sh->fdb_domain;
9936 else if (key.is_egress)
9937 domain = sh->tx_domain;
9939 domain = sh->rx_domain;
9940 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
9942 rte_flow_error_set(error, ENOMEM,
9943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9944 NULL, "cannot create flow table object");
9945 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9948 if (key.level != 0) {
9949 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9950 (tbl->obj, &tbl_data->jump.action);
9952 rte_flow_error_set(error, ENOMEM,
9953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9955 "cannot create flow jump action");
9956 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9957 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9961 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_cache",
9962 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
9964 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9965 flow_dv_matcher_create_cb,
9966 flow_dv_matcher_match_cb,
9967 flow_dv_matcher_remove_cb);
9968 return &tbl_data->entry;
9972 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9973 struct mlx5_hlist_entry *entry, uint64_t key64,
9974 void *cb_ctx __rte_unused)
9976 struct mlx5_flow_tbl_data_entry *tbl_data =
9977 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9978 union mlx5_flow_tbl_key key = { .v64 = key64 };
9980 return tbl_data->level != key.level ||
9981 tbl_data->id != key.id ||
9982 tbl_data->dummy != key.dummy ||
9983 tbl_data->is_transfer != !!key.is_fdb ||
9984 tbl_data->is_egress != !!key.is_egress;
9990 * @param[in, out] dev
9991 * Pointer to rte_eth_dev structure.
9992 * @param[in] table_level
9993 * Table level to use.
9995 * Direction of the table.
9996 * @param[in] transfer
9997 * E-Switch or NIC flow.
9999 * Dummy entry for dv API.
10000 * @param[in] table_id
10002 * @param[out] error
10003 * pointer to error structure.
10006 * Returns tables resource based on the index, NULL in case of failed.
10008 struct mlx5_flow_tbl_resource *
10009 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10010 uint32_t table_level, uint8_t egress,
10013 const struct mlx5_flow_tunnel *tunnel,
10014 uint32_t group_id, uint8_t dummy,
10016 struct rte_flow_error *error)
10018 struct mlx5_priv *priv = dev->data->dev_private;
10019 union mlx5_flow_tbl_key table_key = {
10021 .level = table_level,
10025 .is_fdb = !!transfer,
10026 .is_egress = !!egress,
10029 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10031 .group_id = group_id,
10032 .external = external,
10034 struct mlx5_flow_cb_ctx ctx = {
10039 struct mlx5_hlist_entry *entry;
10040 struct mlx5_flow_tbl_data_entry *tbl_data;
10042 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10044 rte_flow_error_set(error, ENOMEM,
10045 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10046 "cannot get table");
10049 DRV_LOG(DEBUG, "table_level %u table_id %u "
10050 "tunnel %u group %u registered.",
10051 table_level, table_id,
10052 tunnel ? tunnel->tunnel_id : 0, group_id);
10053 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10054 return &tbl_data->tbl;
10058 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
10059 struct mlx5_hlist_entry *entry)
10061 struct mlx5_dev_ctx_shared *sh = list->ctx;
10062 struct mlx5_flow_tbl_data_entry *tbl_data =
10063 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10065 MLX5_ASSERT(entry && sh);
10066 if (tbl_data->jump.action)
10067 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10068 if (tbl_data->tbl.obj)
10069 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10070 if (tbl_data->tunnel_offload && tbl_data->external) {
10071 struct mlx5_hlist_entry *he;
10072 struct mlx5_hlist *tunnel_grp_hash;
10073 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10074 union tunnel_tbl_key tunnel_key = {
10075 .tunnel_id = tbl_data->tunnel ?
10076 tbl_data->tunnel->tunnel_id : 0,
10077 .group = tbl_data->group_id
10079 uint32_t table_level = tbl_data->level;
10081 tunnel_grp_hash = tbl_data->tunnel ?
10082 tbl_data->tunnel->groups :
10084 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
10086 mlx5_hlist_unregister(tunnel_grp_hash, he);
10088 "table_level %u id %u tunnel %u group %u released.",
10092 tbl_data->tunnel->tunnel_id : 0,
10093 tbl_data->group_id);
10095 mlx5_cache_list_destroy(&tbl_data->matchers);
10096 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10100 * Release a flow table.
10103 * Pointer to device shared structure.
10105 * Table resource to be released.
10108 * Returns 0 if table was released, else return 1;
10111 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10112 struct mlx5_flow_tbl_resource *tbl)
10114 struct mlx5_flow_tbl_data_entry *tbl_data =
10115 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10119 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10123 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
10124 struct mlx5_cache_entry *entry, void *cb_ctx)
10126 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10127 struct mlx5_flow_dv_matcher *ref = ctx->data;
10128 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10131 return cur->crc != ref->crc ||
10132 cur->priority != ref->priority ||
10133 memcmp((const void *)cur->mask.buf,
10134 (const void *)ref->mask.buf, ref->mask.size);
10137 struct mlx5_cache_entry *
10138 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
10139 struct mlx5_cache_entry *entry __rte_unused,
10142 struct mlx5_dev_ctx_shared *sh = list->ctx;
10143 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10144 struct mlx5_flow_dv_matcher *ref = ctx->data;
10145 struct mlx5_flow_dv_matcher *cache;
10146 struct mlx5dv_flow_matcher_attr dv_attr = {
10147 .type = IBV_FLOW_ATTR_NORMAL,
10148 .match_mask = (void *)&ref->mask,
10150 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10151 typeof(*tbl), tbl);
10154 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
10156 rte_flow_error_set(ctx->error, ENOMEM,
10157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10158 "cannot create matcher");
10162 dv_attr.match_criteria_enable =
10163 flow_dv_matcher_enable(cache->mask.buf);
10164 dv_attr.priority = ref->priority;
10165 if (tbl->is_egress)
10166 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10167 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
10168 &cache->matcher_object);
10171 rte_flow_error_set(ctx->error, ENOMEM,
10172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10173 "cannot create matcher");
10176 return &cache->entry;
10180 * Register the flow matcher.
10182 * @param[in, out] dev
10183 * Pointer to rte_eth_dev structure.
10184 * @param[in, out] matcher
10185 * Pointer to flow matcher.
10186 * @param[in, out] key
10187 * Pointer to flow table key.
10188 * @parm[in, out] dev_flow
10189 * Pointer to the dev_flow.
10190 * @param[out] error
10191 * pointer to error structure.
10194 * 0 on success otherwise -errno and errno is set.
10197 flow_dv_matcher_register(struct rte_eth_dev *dev,
10198 struct mlx5_flow_dv_matcher *ref,
10199 union mlx5_flow_tbl_key *key,
10200 struct mlx5_flow *dev_flow,
10201 const struct mlx5_flow_tunnel *tunnel,
10203 struct rte_flow_error *error)
10205 struct mlx5_cache_entry *entry;
10206 struct mlx5_flow_dv_matcher *cache;
10207 struct mlx5_flow_tbl_resource *tbl;
10208 struct mlx5_flow_tbl_data_entry *tbl_data;
10209 struct mlx5_flow_cb_ctx ctx = {
10215 * tunnel offload API requires this registration for cases when
10216 * tunnel match rule was inserted before tunnel set rule.
10218 tbl = flow_dv_tbl_resource_get(dev, key->level,
10219 key->is_egress, key->is_fdb,
10220 dev_flow->external, tunnel,
10221 group_id, 0, key->id, error);
10223 return -rte_errno; /* No need to refill the error info */
10224 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10226 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
10228 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10229 return rte_flow_error_set(error, ENOMEM,
10230 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10231 "cannot allocate ref memory");
10233 cache = container_of(entry, typeof(*cache), entry);
10234 dev_flow->handle->dvh.matcher = cache;
10238 struct mlx5_hlist_entry *
10239 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
10241 struct mlx5_dev_ctx_shared *sh = list->ctx;
10242 struct rte_flow_error *error = ctx;
10243 struct mlx5_flow_dv_tag_resource *entry;
10247 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10249 rte_flow_error_set(error, ENOMEM,
10250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10251 "cannot allocate resource memory");
10255 entry->tag_id = key;
10256 ret = mlx5_flow_os_create_flow_action_tag(key,
10259 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10260 rte_flow_error_set(error, ENOMEM,
10261 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10262 NULL, "cannot create action");
10265 return &entry->entry;
10269 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
10270 struct mlx5_hlist_entry *entry, uint64_t key,
10271 void *cb_ctx __rte_unused)
10273 struct mlx5_flow_dv_tag_resource *tag =
10274 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10276 return key != tag->tag_id;
10280 * Find existing tag resource or create and register a new one.
10282 * @param dev[in, out]
10283 * Pointer to rte_eth_dev structure.
10284 * @param[in, out] tag_be24
10285 * Tag value in big endian then R-shift 8.
10286 * @parm[in, out] dev_flow
10287 * Pointer to the dev_flow.
10288 * @param[out] error
10289 * pointer to error structure.
10292 * 0 on success otherwise -errno and errno is set.
10295 flow_dv_tag_resource_register
10296 (struct rte_eth_dev *dev,
10298 struct mlx5_flow *dev_flow,
10299 struct rte_flow_error *error)
10301 struct mlx5_priv *priv = dev->data->dev_private;
10302 struct mlx5_flow_dv_tag_resource *cache_resource;
10303 struct mlx5_hlist_entry *entry;
10305 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
10307 cache_resource = container_of
10308 (entry, struct mlx5_flow_dv_tag_resource, entry);
10309 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
10310 dev_flow->dv.tag_resource = cache_resource;
10317 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
10318 struct mlx5_hlist_entry *entry)
10320 struct mlx5_dev_ctx_shared *sh = list->ctx;
10321 struct mlx5_flow_dv_tag_resource *tag =
10322 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10324 MLX5_ASSERT(tag && sh && tag->action);
10325 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10326 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10327 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10334 * Pointer to Ethernet device.
10339 * 1 while a reference on it exists, 0 when freed.
10342 flow_dv_tag_release(struct rte_eth_dev *dev,
10345 struct mlx5_priv *priv = dev->data->dev_private;
10346 struct mlx5_flow_dv_tag_resource *tag;
10348 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10351 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10352 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10353 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10357 * Translate port ID action to vport.
10360 * Pointer to rte_eth_dev structure.
10361 * @param[in] action
10362 * Pointer to the port ID action.
10363 * @param[out] dst_port_id
10364 * The target port ID.
10365 * @param[out] error
10366 * Pointer to the error structure.
10369 * 0 on success, a negative errno value otherwise and rte_errno is set.
10372 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10373 const struct rte_flow_action *action,
10374 uint32_t *dst_port_id,
10375 struct rte_flow_error *error)
10378 struct mlx5_priv *priv;
10379 const struct rte_flow_action_port_id *conf =
10380 (const struct rte_flow_action_port_id *)action->conf;
10382 port = conf->original ? dev->data->port_id : conf->id;
10383 priv = mlx5_port_to_eswitch_info(port, false);
10385 return rte_flow_error_set(error, -rte_errno,
10386 RTE_FLOW_ERROR_TYPE_ACTION,
10388 "No eswitch info was found for port");
10389 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
10391 * This parameter is transferred to
10392 * mlx5dv_dr_action_create_dest_ib_port().
10394 *dst_port_id = priv->dev_port;
10397 * Legacy mode, no LAG configurations is supported.
10398 * This parameter is transferred to
10399 * mlx5dv_dr_action_create_dest_vport().
10401 *dst_port_id = priv->vport_id;
10407 * Create a counter with aging configuration.
10410 * Pointer to rte_eth_dev structure.
10411 * @param[in] dev_flow
10412 * Pointer to the mlx5_flow.
10413 * @param[out] count
10414 * Pointer to the counter action configuration.
10416 * Pointer to the aging action configuration.
10419 * Index to flow counter on success, 0 otherwise.
10422 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10423 struct mlx5_flow *dev_flow,
10424 const struct rte_flow_action_count *count,
10425 const struct rte_flow_action_age *age)
10428 struct mlx5_age_param *age_param;
10430 if (count && count->shared)
10431 counter = flow_dv_counter_get_shared(dev, count->id);
10433 counter = flow_dv_counter_alloc(dev, !!age);
10434 if (!counter || age == NULL)
10436 age_param = flow_dv_counter_idx_get_age(dev, counter);
10437 age_param->context = age->context ? age->context :
10438 (void *)(uintptr_t)(dev_flow->flow_idx);
10439 age_param->timeout = age->timeout;
10440 age_param->port_id = dev->data->port_id;
10441 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10442 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10447 * Add Tx queue matcher
10450 * Pointer to the dev struct.
10451 * @param[in, out] matcher
10453 * @param[in, out] key
10454 * Flow matcher value.
10456 * Flow pattern to translate.
10458 * Item is inner pattern.
10461 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10462 void *matcher, void *key,
10463 const struct rte_flow_item *item)
10465 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10466 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10468 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10470 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10471 struct mlx5_txq_ctrl *txq;
10475 queue_m = (const void *)item->mask;
10478 queue_v = (const void *)item->spec;
10481 txq = mlx5_txq_get(dev, queue_v->queue);
10484 queue = txq->obj->sq->id;
10485 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
10486 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
10487 queue & queue_m->queue);
10488 mlx5_txq_release(dev, queue_v->queue);
10492 * Set the hash fields according to the @p flow information.
10494 * @param[in] dev_flow
10495 * Pointer to the mlx5_flow.
10496 * @param[in] rss_desc
10497 * Pointer to the mlx5_flow_rss_desc.
10500 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10501 struct mlx5_flow_rss_desc *rss_desc)
10503 uint64_t items = dev_flow->handle->layers;
10505 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10507 dev_flow->hash_fields = 0;
10508 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10509 if (rss_desc->level >= 2) {
10510 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10514 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10515 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10516 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10517 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10518 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10519 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10520 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10522 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10524 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10525 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10526 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10527 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10528 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10529 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10530 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10532 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10535 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10536 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10537 if (rss_types & ETH_RSS_UDP) {
10538 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10539 dev_flow->hash_fields |=
10540 IBV_RX_HASH_SRC_PORT_UDP;
10541 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10542 dev_flow->hash_fields |=
10543 IBV_RX_HASH_DST_PORT_UDP;
10545 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10547 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10548 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10549 if (rss_types & ETH_RSS_TCP) {
10550 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10551 dev_flow->hash_fields |=
10552 IBV_RX_HASH_SRC_PORT_TCP;
10553 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10554 dev_flow->hash_fields |=
10555 IBV_RX_HASH_DST_PORT_TCP;
10557 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10563 * Prepare an Rx Hash queue.
10566 * Pointer to Ethernet device.
10567 * @param[in] dev_flow
10568 * Pointer to the mlx5_flow.
10569 * @param[in] rss_desc
10570 * Pointer to the mlx5_flow_rss_desc.
10571 * @param[out] hrxq_idx
10572 * Hash Rx queue index.
10575 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10577 static struct mlx5_hrxq *
10578 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10579 struct mlx5_flow *dev_flow,
10580 struct mlx5_flow_rss_desc *rss_desc,
10581 uint32_t *hrxq_idx)
10583 struct mlx5_priv *priv = dev->data->dev_private;
10584 struct mlx5_flow_handle *dh = dev_flow->handle;
10585 struct mlx5_hrxq *hrxq;
10587 MLX5_ASSERT(rss_desc->queue_num);
10588 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10589 rss_desc->hash_fields = dev_flow->hash_fields;
10590 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10591 rss_desc->shared_rss = 0;
10592 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10595 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10601 * Release sample sub action resource.
10603 * @param[in, out] dev
10604 * Pointer to rte_eth_dev structure.
10605 * @param[in] act_res
10606 * Pointer to sample sub action resource.
10609 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10610 struct mlx5_flow_sub_actions_idx *act_res)
10612 if (act_res->rix_hrxq) {
10613 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10614 act_res->rix_hrxq = 0;
10616 if (act_res->rix_encap_decap) {
10617 flow_dv_encap_decap_resource_release(dev,
10618 act_res->rix_encap_decap);
10619 act_res->rix_encap_decap = 0;
10621 if (act_res->rix_port_id_action) {
10622 flow_dv_port_id_action_resource_release(dev,
10623 act_res->rix_port_id_action);
10624 act_res->rix_port_id_action = 0;
10626 if (act_res->rix_tag) {
10627 flow_dv_tag_release(dev, act_res->rix_tag);
10628 act_res->rix_tag = 0;
10630 if (act_res->rix_jump) {
10631 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10632 act_res->rix_jump = 0;
10637 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10638 struct mlx5_cache_entry *entry, void *cb_ctx)
10640 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10641 struct rte_eth_dev *dev = ctx->dev;
10642 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10643 struct mlx5_flow_dv_sample_resource *cache_resource =
10644 container_of(entry, typeof(*cache_resource), entry);
10646 if (resource->ratio == cache_resource->ratio &&
10647 resource->ft_type == cache_resource->ft_type &&
10648 resource->ft_id == cache_resource->ft_id &&
10649 resource->set_action == cache_resource->set_action &&
10650 !memcmp((void *)&resource->sample_act,
10651 (void *)&cache_resource->sample_act,
10652 sizeof(struct mlx5_flow_sub_actions_list))) {
10654 * Existing sample action should release the prepared
10655 * sub-actions reference counter.
10657 flow_dv_sample_sub_actions_release(dev,
10658 &resource->sample_idx);
10664 struct mlx5_cache_entry *
10665 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10666 struct mlx5_cache_entry *entry __rte_unused,
10669 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10670 struct rte_eth_dev *dev = ctx->dev;
10671 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10672 void **sample_dv_actions = resource->sub_actions;
10673 struct mlx5_flow_dv_sample_resource *cache_resource;
10674 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10675 struct mlx5_priv *priv = dev->data->dev_private;
10676 struct mlx5_dev_ctx_shared *sh = priv->sh;
10677 struct mlx5_flow_tbl_resource *tbl;
10679 const uint32_t next_ft_step = 1;
10680 uint32_t next_ft_id = resource->ft_id + next_ft_step;
10681 uint8_t is_egress = 0;
10682 uint8_t is_transfer = 0;
10683 struct rte_flow_error *error = ctx->error;
10685 /* Register new sample resource. */
10686 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10687 if (!cache_resource) {
10688 rte_flow_error_set(error, ENOMEM,
10689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10691 "cannot allocate resource memory");
10694 *cache_resource = *resource;
10695 /* Create normal path table level */
10696 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10698 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10700 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10701 is_egress, is_transfer,
10702 true, NULL, 0, 0, 0, error);
10704 rte_flow_error_set(error, ENOMEM,
10705 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10707 "fail to create normal path table "
10711 cache_resource->normal_path_tbl = tbl;
10712 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10713 if (!sh->default_miss_action) {
10714 rte_flow_error_set(error, ENOMEM,
10715 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10717 "default miss action was not "
10721 sample_dv_actions[resource->sample_act.actions_num++] =
10722 sh->default_miss_action;
10724 /* Create a DR sample action */
10725 sampler_attr.sample_ratio = cache_resource->ratio;
10726 sampler_attr.default_next_table = tbl->obj;
10727 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10728 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10729 &sample_dv_actions[0];
10730 sampler_attr.action = cache_resource->set_action;
10731 if (mlx5_os_flow_dr_create_flow_action_sampler
10732 (&sampler_attr, &cache_resource->verbs_action)) {
10733 rte_flow_error_set(error, ENOMEM,
10734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10735 NULL, "cannot create sample action");
10738 cache_resource->idx = idx;
10739 cache_resource->dev = dev;
10740 return &cache_resource->entry;
10742 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10743 flow_dv_sample_sub_actions_release(dev,
10744 &cache_resource->sample_idx);
10745 if (cache_resource->normal_path_tbl)
10746 flow_dv_tbl_resource_release(MLX5_SH(dev),
10747 cache_resource->normal_path_tbl);
10748 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10754 * Find existing sample resource or create and register a new one.
10756 * @param[in, out] dev
10757 * Pointer to rte_eth_dev structure.
10758 * @param[in] resource
10759 * Pointer to sample resource.
10760 * @parm[in, out] dev_flow
10761 * Pointer to the dev_flow.
10762 * @param[out] error
10763 * pointer to error structure.
10766 * 0 on success otherwise -errno and errno is set.
10769 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10770 struct mlx5_flow_dv_sample_resource *resource,
10771 struct mlx5_flow *dev_flow,
10772 struct rte_flow_error *error)
10774 struct mlx5_flow_dv_sample_resource *cache_resource;
10775 struct mlx5_cache_entry *entry;
10776 struct mlx5_priv *priv = dev->data->dev_private;
10777 struct mlx5_flow_cb_ctx ctx = {
10783 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10786 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10787 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10788 dev_flow->dv.sample_res = cache_resource;
10793 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10794 struct mlx5_cache_entry *entry, void *cb_ctx)
10796 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10797 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10798 struct rte_eth_dev *dev = ctx->dev;
10799 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10800 container_of(entry, typeof(*cache_resource), entry);
10803 if (resource->num_of_dest == cache_resource->num_of_dest &&
10804 resource->ft_type == cache_resource->ft_type &&
10805 !memcmp((void *)cache_resource->sample_act,
10806 (void *)resource->sample_act,
10807 (resource->num_of_dest *
10808 sizeof(struct mlx5_flow_sub_actions_list)))) {
10810 * Existing sample action should release the prepared
10811 * sub-actions reference counter.
10813 for (idx = 0; idx < resource->num_of_dest; idx++)
10814 flow_dv_sample_sub_actions_release(dev,
10815 &resource->sample_idx[idx]);
10821 struct mlx5_cache_entry *
10822 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10823 struct mlx5_cache_entry *entry __rte_unused,
10826 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10827 struct rte_eth_dev *dev = ctx->dev;
10828 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10829 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10830 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10831 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10832 struct mlx5_priv *priv = dev->data->dev_private;
10833 struct mlx5_dev_ctx_shared *sh = priv->sh;
10834 struct mlx5_flow_sub_actions_list *sample_act;
10835 struct mlx5dv_dr_domain *domain;
10836 uint32_t idx = 0, res_idx = 0;
10837 struct rte_flow_error *error = ctx->error;
10838 uint64_t action_flags;
10841 /* Register new destination array resource. */
10842 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10844 if (!cache_resource) {
10845 rte_flow_error_set(error, ENOMEM,
10846 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10848 "cannot allocate resource memory");
10851 *cache_resource = *resource;
10852 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10853 domain = sh->fdb_domain;
10854 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10855 domain = sh->rx_domain;
10857 domain = sh->tx_domain;
10858 for (idx = 0; idx < resource->num_of_dest; idx++) {
10859 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10860 mlx5_malloc(MLX5_MEM_ZERO,
10861 sizeof(struct mlx5dv_dr_action_dest_attr),
10863 if (!dest_attr[idx]) {
10864 rte_flow_error_set(error, ENOMEM,
10865 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10867 "cannot allocate resource memory");
10870 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10871 sample_act = &resource->sample_act[idx];
10872 action_flags = sample_act->action_flags;
10873 switch (action_flags) {
10874 case MLX5_FLOW_ACTION_QUEUE:
10875 dest_attr[idx]->dest = sample_act->dr_queue_action;
10877 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10878 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10879 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10880 dest_attr[idx]->dest_reformat->reformat =
10881 sample_act->dr_encap_action;
10882 dest_attr[idx]->dest_reformat->dest =
10883 sample_act->dr_port_id_action;
10885 case MLX5_FLOW_ACTION_PORT_ID:
10886 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10888 case MLX5_FLOW_ACTION_JUMP:
10889 dest_attr[idx]->dest = sample_act->dr_jump_action;
10892 rte_flow_error_set(error, EINVAL,
10893 RTE_FLOW_ERROR_TYPE_ACTION,
10895 "unsupported actions type");
10899 /* create a dest array actioin */
10900 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10902 cache_resource->num_of_dest,
10904 &cache_resource->action);
10906 rte_flow_error_set(error, ENOMEM,
10907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10909 "cannot create destination array action");
10912 cache_resource->idx = res_idx;
10913 cache_resource->dev = dev;
10914 for (idx = 0; idx < resource->num_of_dest; idx++)
10915 mlx5_free(dest_attr[idx]);
10916 return &cache_resource->entry;
10918 for (idx = 0; idx < resource->num_of_dest; idx++) {
10919 flow_dv_sample_sub_actions_release(dev,
10920 &cache_resource->sample_idx[idx]);
10921 if (dest_attr[idx])
10922 mlx5_free(dest_attr[idx]);
10925 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10930 * Find existing destination array resource or create and register a new one.
10932 * @param[in, out] dev
10933 * Pointer to rte_eth_dev structure.
10934 * @param[in] resource
10935 * Pointer to destination array resource.
10936 * @parm[in, out] dev_flow
10937 * Pointer to the dev_flow.
10938 * @param[out] error
10939 * pointer to error structure.
10942 * 0 on success otherwise -errno and errno is set.
10945 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10946 struct mlx5_flow_dv_dest_array_resource *resource,
10947 struct mlx5_flow *dev_flow,
10948 struct rte_flow_error *error)
10950 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10951 struct mlx5_priv *priv = dev->data->dev_private;
10952 struct mlx5_cache_entry *entry;
10953 struct mlx5_flow_cb_ctx ctx = {
10959 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10962 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10963 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10964 dev_flow->dv.dest_array_res = cache_resource;
10969 * Convert Sample action to DV specification.
10972 * Pointer to rte_eth_dev structure.
10973 * @param[in] action
10974 * Pointer to sample action structure.
10975 * @param[in, out] dev_flow
10976 * Pointer to the mlx5_flow.
10978 * Pointer to the flow attributes.
10979 * @param[in, out] num_of_dest
10980 * Pointer to the num of destination.
10981 * @param[in, out] sample_actions
10982 * Pointer to sample actions list.
10983 * @param[in, out] res
10984 * Pointer to sample resource.
10985 * @param[out] error
10986 * Pointer to the error structure.
10989 * 0 on success, a negative errno value otherwise and rte_errno is set.
10992 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10993 const struct rte_flow_action_sample *action,
10994 struct mlx5_flow *dev_flow,
10995 const struct rte_flow_attr *attr,
10996 uint32_t *num_of_dest,
10997 void **sample_actions,
10998 struct mlx5_flow_dv_sample_resource *res,
10999 struct rte_flow_error *error)
11001 struct mlx5_priv *priv = dev->data->dev_private;
11002 const struct rte_flow_action *sub_actions;
11003 struct mlx5_flow_sub_actions_list *sample_act;
11004 struct mlx5_flow_sub_actions_idx *sample_idx;
11005 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11006 struct rte_flow *flow = dev_flow->flow;
11007 struct mlx5_flow_rss_desc *rss_desc;
11008 uint64_t action_flags = 0;
11011 rss_desc = &wks->rss_desc;
11012 sample_act = &res->sample_act;
11013 sample_idx = &res->sample_idx;
11014 res->ratio = action->ratio;
11015 sub_actions = action->actions;
11016 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11017 int type = sub_actions->type;
11018 uint32_t pre_rix = 0;
11021 case RTE_FLOW_ACTION_TYPE_QUEUE:
11023 const struct rte_flow_action_queue *queue;
11024 struct mlx5_hrxq *hrxq;
11027 queue = sub_actions->conf;
11028 rss_desc->queue_num = 1;
11029 rss_desc->queue[0] = queue->index;
11030 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11031 rss_desc, &hrxq_idx);
11033 return rte_flow_error_set
11035 RTE_FLOW_ERROR_TYPE_ACTION,
11037 "cannot create fate queue");
11038 sample_act->dr_queue_action = hrxq->action;
11039 sample_idx->rix_hrxq = hrxq_idx;
11040 sample_actions[sample_act->actions_num++] =
11043 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11044 if (action_flags & MLX5_FLOW_ACTION_MARK)
11045 dev_flow->handle->rix_hrxq = hrxq_idx;
11046 dev_flow->handle->fate_action =
11047 MLX5_FLOW_FATE_QUEUE;
11050 case RTE_FLOW_ACTION_TYPE_RSS:
11052 struct mlx5_hrxq *hrxq;
11054 const struct rte_flow_action_rss *rss;
11055 const uint8_t *rss_key;
11057 rss = sub_actions->conf;
11058 memcpy(rss_desc->queue, rss->queue,
11059 rss->queue_num * sizeof(uint16_t));
11060 rss_desc->queue_num = rss->queue_num;
11061 /* NULL RSS key indicates default RSS key. */
11062 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11063 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11065 * rss->level and rss.types should be set in advance
11066 * when expanding items for RSS.
11068 flow_dv_hashfields_set(dev_flow, rss_desc);
11069 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11070 rss_desc, &hrxq_idx);
11072 return rte_flow_error_set
11074 RTE_FLOW_ERROR_TYPE_ACTION,
11076 "cannot create fate queue");
11077 sample_act->dr_queue_action = hrxq->action;
11078 sample_idx->rix_hrxq = hrxq_idx;
11079 sample_actions[sample_act->actions_num++] =
11082 action_flags |= MLX5_FLOW_ACTION_RSS;
11083 if (action_flags & MLX5_FLOW_ACTION_MARK)
11084 dev_flow->handle->rix_hrxq = hrxq_idx;
11085 dev_flow->handle->fate_action =
11086 MLX5_FLOW_FATE_QUEUE;
11089 case RTE_FLOW_ACTION_TYPE_MARK:
11091 uint32_t tag_be = mlx5_flow_mark_set
11092 (((const struct rte_flow_action_mark *)
11093 (sub_actions->conf))->id);
11095 dev_flow->handle->mark = 1;
11096 pre_rix = dev_flow->handle->dvh.rix_tag;
11097 /* Save the mark resource before sample */
11098 pre_r = dev_flow->dv.tag_resource;
11099 if (flow_dv_tag_resource_register(dev, tag_be,
11102 MLX5_ASSERT(dev_flow->dv.tag_resource);
11103 sample_act->dr_tag_action =
11104 dev_flow->dv.tag_resource->action;
11105 sample_idx->rix_tag =
11106 dev_flow->handle->dvh.rix_tag;
11107 sample_actions[sample_act->actions_num++] =
11108 sample_act->dr_tag_action;
11109 /* Recover the mark resource after sample */
11110 dev_flow->dv.tag_resource = pre_r;
11111 dev_flow->handle->dvh.rix_tag = pre_rix;
11112 action_flags |= MLX5_FLOW_ACTION_MARK;
11115 case RTE_FLOW_ACTION_TYPE_COUNT:
11117 if (!flow->counter) {
11119 flow_dv_translate_create_counter(dev,
11120 dev_flow, sub_actions->conf,
11122 if (!flow->counter)
11123 return rte_flow_error_set
11125 RTE_FLOW_ERROR_TYPE_ACTION,
11127 "cannot create counter"
11130 sample_act->dr_cnt_action =
11131 (flow_dv_counter_get_by_idx(dev,
11132 flow->counter, NULL))->action;
11133 sample_actions[sample_act->actions_num++] =
11134 sample_act->dr_cnt_action;
11135 action_flags |= MLX5_FLOW_ACTION_COUNT;
11138 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11140 struct mlx5_flow_dv_port_id_action_resource
11142 uint32_t port_id = 0;
11144 memset(&port_id_resource, 0, sizeof(port_id_resource));
11145 /* Save the port id resource before sample */
11146 pre_rix = dev_flow->handle->rix_port_id_action;
11147 pre_r = dev_flow->dv.port_id_action;
11148 if (flow_dv_translate_action_port_id(dev, sub_actions,
11151 port_id_resource.port_id = port_id;
11152 if (flow_dv_port_id_action_resource_register
11153 (dev, &port_id_resource, dev_flow, error))
11155 sample_act->dr_port_id_action =
11156 dev_flow->dv.port_id_action->action;
11157 sample_idx->rix_port_id_action =
11158 dev_flow->handle->rix_port_id_action;
11159 sample_actions[sample_act->actions_num++] =
11160 sample_act->dr_port_id_action;
11161 /* Recover the port id resource after sample */
11162 dev_flow->dv.port_id_action = pre_r;
11163 dev_flow->handle->rix_port_id_action = pre_rix;
11165 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11168 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11169 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11170 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11171 /* Save the encap resource before sample */
11172 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11173 pre_r = dev_flow->dv.encap_decap;
11174 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11179 sample_act->dr_encap_action =
11180 dev_flow->dv.encap_decap->action;
11181 sample_idx->rix_encap_decap =
11182 dev_flow->handle->dvh.rix_encap_decap;
11183 sample_actions[sample_act->actions_num++] =
11184 sample_act->dr_encap_action;
11185 /* Recover the encap resource after sample */
11186 dev_flow->dv.encap_decap = pre_r;
11187 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11188 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11191 return rte_flow_error_set(error, EINVAL,
11192 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11194 "Not support for sampler action");
11197 sample_act->action_flags = action_flags;
11198 res->ft_id = dev_flow->dv.group;
11199 if (attr->transfer) {
11201 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11202 uint64_t set_action;
11203 } action_ctx = { .set_action = 0 };
11205 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11206 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11207 MLX5_MODIFICATION_TYPE_SET);
11208 MLX5_SET(set_action_in, action_ctx.action_in, field,
11209 MLX5_MODI_META_REG_C_0);
11210 MLX5_SET(set_action_in, action_ctx.action_in, data,
11211 priv->vport_meta_tag);
11212 res->set_action = action_ctx.set_action;
11213 } else if (attr->ingress) {
11214 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11216 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11222 * Convert Sample action to DV specification.
11225 * Pointer to rte_eth_dev structure.
11226 * @param[in, out] dev_flow
11227 * Pointer to the mlx5_flow.
11228 * @param[in] num_of_dest
11229 * The num of destination.
11230 * @param[in, out] res
11231 * Pointer to sample resource.
11232 * @param[in, out] mdest_res
11233 * Pointer to destination array resource.
11234 * @param[in] sample_actions
11235 * Pointer to sample path actions list.
11236 * @param[in] action_flags
11237 * Holds the actions detected until now.
11238 * @param[out] error
11239 * Pointer to the error structure.
11242 * 0 on success, a negative errno value otherwise and rte_errno is set.
11245 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11246 struct mlx5_flow *dev_flow,
11247 uint32_t num_of_dest,
11248 struct mlx5_flow_dv_sample_resource *res,
11249 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11250 void **sample_actions,
11251 uint64_t action_flags,
11252 struct rte_flow_error *error)
11254 /* update normal path action resource into last index of array */
11255 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11256 struct mlx5_flow_sub_actions_list *sample_act =
11257 &mdest_res->sample_act[dest_index];
11258 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11259 struct mlx5_flow_rss_desc *rss_desc;
11260 uint32_t normal_idx = 0;
11261 struct mlx5_hrxq *hrxq;
11265 rss_desc = &wks->rss_desc;
11266 if (num_of_dest > 1) {
11267 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11268 /* Handle QP action for mirroring */
11269 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11270 rss_desc, &hrxq_idx);
11272 return rte_flow_error_set
11274 RTE_FLOW_ERROR_TYPE_ACTION,
11276 "cannot create rx queue");
11278 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11279 sample_act->dr_queue_action = hrxq->action;
11280 if (action_flags & MLX5_FLOW_ACTION_MARK)
11281 dev_flow->handle->rix_hrxq = hrxq_idx;
11282 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11284 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11286 mdest_res->sample_idx[dest_index].rix_encap_decap =
11287 dev_flow->handle->dvh.rix_encap_decap;
11288 sample_act->dr_encap_action =
11289 dev_flow->dv.encap_decap->action;
11290 dev_flow->handle->dvh.rix_encap_decap = 0;
11292 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11294 mdest_res->sample_idx[dest_index].rix_port_id_action =
11295 dev_flow->handle->rix_port_id_action;
11296 sample_act->dr_port_id_action =
11297 dev_flow->dv.port_id_action->action;
11298 dev_flow->handle->rix_port_id_action = 0;
11300 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11302 mdest_res->sample_idx[dest_index].rix_jump =
11303 dev_flow->handle->rix_jump;
11304 sample_act->dr_jump_action =
11305 dev_flow->dv.jump->action;
11306 dev_flow->handle->rix_jump = 0;
11308 sample_act->actions_num = normal_idx;
11309 /* update sample action resource into first index of array */
11310 mdest_res->ft_type = res->ft_type;
11311 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11312 sizeof(struct mlx5_flow_sub_actions_idx));
11313 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11314 sizeof(struct mlx5_flow_sub_actions_list));
11315 mdest_res->num_of_dest = num_of_dest;
11316 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11318 return rte_flow_error_set(error, EINVAL,
11319 RTE_FLOW_ERROR_TYPE_ACTION,
11320 NULL, "can't create sample "
11323 res->sub_actions = sample_actions;
11324 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11325 return rte_flow_error_set(error, EINVAL,
11326 RTE_FLOW_ERROR_TYPE_ACTION,
11328 "can't create sample action");
11334 * Remove an ASO age action from age actions list.
11337 * Pointer to the Ethernet device structure.
11339 * Pointer to the aso age action handler.
11342 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11343 struct mlx5_aso_age_action *age)
11345 struct mlx5_age_info *age_info;
11346 struct mlx5_age_param *age_param = &age->age_params;
11347 struct mlx5_priv *priv = dev->data->dev_private;
11348 uint16_t expected = AGE_CANDIDATE;
11350 age_info = GET_PORT_AGE_INFO(priv);
11351 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11352 AGE_FREE, false, __ATOMIC_RELAXED,
11353 __ATOMIC_RELAXED)) {
11355 * We need the lock even it is age timeout,
11356 * since age action may still in process.
11358 rte_spinlock_lock(&age_info->aged_sl);
11359 LIST_REMOVE(age, next);
11360 rte_spinlock_unlock(&age_info->aged_sl);
11361 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11366 * Release an ASO age action.
11369 * Pointer to the Ethernet device structure.
11370 * @param[in] age_idx
11371 * Index of ASO age action to release.
11373 * True if the release operation is during flow destroy operation.
11374 * False if the release operation is during action destroy operation.
11377 * 0 when age action was removed, otherwise the number of references.
11380 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11382 struct mlx5_priv *priv = dev->data->dev_private;
11383 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11384 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11385 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11388 flow_dv_aso_age_remove_from_age(dev, age);
11389 rte_spinlock_lock(&mng->free_sl);
11390 LIST_INSERT_HEAD(&mng->free, age, next);
11391 rte_spinlock_unlock(&mng->free_sl);
11397 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11400 * Pointer to the Ethernet device structure.
11403 * 0 on success, otherwise negative errno value and rte_errno is set.
11406 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11408 struct mlx5_priv *priv = dev->data->dev_private;
11409 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11410 void *old_pools = mng->pools;
11411 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11412 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11413 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11416 rte_errno = ENOMEM;
11420 memcpy(pools, old_pools,
11421 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11422 mlx5_free(old_pools);
11424 /* First ASO flow hit allocation - starting ASO data-path. */
11425 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11433 mng->pools = pools;
11438 * Create and initialize a new ASO aging pool.
11441 * Pointer to the Ethernet device structure.
11442 * @param[out] age_free
11443 * Where to put the pointer of a new age action.
11446 * The age actions pool pointer and @p age_free is set on success,
11447 * NULL otherwise and rte_errno is set.
11449 static struct mlx5_aso_age_pool *
11450 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11451 struct mlx5_aso_age_action **age_free)
11453 struct mlx5_priv *priv = dev->data->dev_private;
11454 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11455 struct mlx5_aso_age_pool *pool = NULL;
11456 struct mlx5_devx_obj *obj = NULL;
11459 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
11462 rte_errno = ENODATA;
11463 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11466 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11468 claim_zero(mlx5_devx_cmd_destroy(obj));
11469 rte_errno = ENOMEM;
11472 pool->flow_hit_aso_obj = obj;
11473 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11474 rte_spinlock_lock(&mng->resize_sl);
11475 pool->index = mng->next;
11476 /* Resize pools array if there is no room for the new pool in it. */
11477 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11478 claim_zero(mlx5_devx_cmd_destroy(obj));
11480 rte_spinlock_unlock(&mng->resize_sl);
11483 mng->pools[pool->index] = pool;
11485 rte_spinlock_unlock(&mng->resize_sl);
11486 /* Assign the first action in the new pool, the rest go to free list. */
11487 *age_free = &pool->actions[0];
11488 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11489 pool->actions[i].offset = i;
11490 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
11496 * Allocate a ASO aging bit.
11499 * Pointer to the Ethernet device structure.
11500 * @param[out] error
11501 * Pointer to the error structure.
11504 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
11507 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
11509 struct mlx5_priv *priv = dev->data->dev_private;
11510 const struct mlx5_aso_age_pool *pool;
11511 struct mlx5_aso_age_action *age_free = NULL;
11512 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11515 /* Try to get the next free age action bit. */
11516 rte_spinlock_lock(&mng->free_sl);
11517 age_free = LIST_FIRST(&mng->free);
11519 LIST_REMOVE(age_free, next);
11520 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
11521 rte_spinlock_unlock(&mng->free_sl);
11522 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
11523 NULL, "failed to create ASO age pool");
11524 return 0; /* 0 is an error. */
11526 rte_spinlock_unlock(&mng->free_sl);
11527 pool = container_of
11528 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
11529 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
11531 if (!age_free->dr_action) {
11532 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
11536 rte_flow_error_set(error, rte_errno,
11537 RTE_FLOW_ERROR_TYPE_ACTION,
11538 NULL, "failed to get reg_c "
11539 "for ASO flow hit");
11540 return 0; /* 0 is an error. */
11542 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
11543 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
11544 (priv->sh->rx_domain,
11545 pool->flow_hit_aso_obj->obj, age_free->offset,
11546 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
11547 (reg_c - REG_C_0));
11548 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
11549 if (!age_free->dr_action) {
11551 rte_spinlock_lock(&mng->free_sl);
11552 LIST_INSERT_HEAD(&mng->free, age_free, next);
11553 rte_spinlock_unlock(&mng->free_sl);
11554 rte_flow_error_set(error, rte_errno,
11555 RTE_FLOW_ERROR_TYPE_ACTION,
11556 NULL, "failed to create ASO "
11557 "flow hit action");
11558 return 0; /* 0 is an error. */
11561 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
11562 return pool->index | ((age_free->offset + 1) << 16);
11566 * Initialize flow ASO age parameters.
11569 * Pointer to rte_eth_dev structure.
11570 * @param[in] age_idx
11571 * Index of ASO age action.
11572 * @param[in] context
11573 * Pointer to flow counter age context.
11574 * @param[in] timeout
11575 * Aging timeout in seconds.
11579 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
11584 struct mlx5_aso_age_action *aso_age;
11586 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11587 MLX5_ASSERT(aso_age);
11588 aso_age->age_params.context = context;
11589 aso_age->age_params.timeout = timeout;
11590 aso_age->age_params.port_id = dev->data->port_id;
11591 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11593 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11598 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
11599 const struct rte_flow_item_integrity *value,
11600 void *headers_m, void *headers_v)
11603 /* application l4_ok filter aggregates all hardware l4 filters
11604 * therefore hw l4_checksum_ok must be implicitly added here.
11606 struct rte_flow_item_integrity local_item;
11608 local_item.l4_csum_ok = 1;
11609 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
11610 local_item.l4_csum_ok);
11611 if (value->l4_ok) {
11612 /* application l4_ok = 1 matches sets both hw flags
11613 * l4_ok and l4_checksum_ok flags to 1.
11615 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11616 l4_checksum_ok, local_item.l4_csum_ok);
11617 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok,
11619 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok,
11622 /* application l4_ok = 0 matches on hw flag
11623 * l4_checksum_ok = 0 only.
11625 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11626 l4_checksum_ok, 0);
11628 } else if (mask->l4_csum_ok) {
11629 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
11631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
11632 value->l4_csum_ok);
11637 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
11638 const struct rte_flow_item_integrity *value,
11639 void *headers_m, void *headers_v,
11643 /* application l3_ok filter aggregates all hardware l3 filters
11644 * therefore hw ipv4_checksum_ok must be implicitly added here.
11646 struct rte_flow_item_integrity local_item;
11648 local_item.ipv4_csum_ok = !!is_ipv4;
11649 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
11650 local_item.ipv4_csum_ok);
11651 if (value->l3_ok) {
11652 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11653 ipv4_checksum_ok, local_item.ipv4_csum_ok);
11654 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok,
11656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
11659 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11660 ipv4_checksum_ok, 0);
11662 } else if (mask->ipv4_csum_ok) {
11663 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
11664 mask->ipv4_csum_ok);
11665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
11666 value->ipv4_csum_ok);
11671 flow_dv_translate_item_integrity(void *matcher, void *key,
11672 const struct rte_flow_item *head_item,
11673 const struct rte_flow_item *integrity_item)
11675 const struct rte_flow_item_integrity *mask = integrity_item->mask;
11676 const struct rte_flow_item_integrity *value = integrity_item->spec;
11677 const struct rte_flow_item *tunnel_item, *end_item, *item;
11680 uint32_t l3_protocol;
11685 mask = &rte_flow_item_integrity_mask;
11686 if (value->level > 1) {
11687 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
11689 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
11691 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
11693 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
11695 tunnel_item = mlx5_flow_find_tunnel_item(head_item);
11696 if (value->level > 1) {
11697 /* tunnel item was verified during the item validation */
11698 item = tunnel_item;
11699 end_item = mlx5_find_end_item(tunnel_item);
11702 end_item = tunnel_item ? tunnel_item :
11703 mlx5_find_end_item(integrity_item);
11705 l3_protocol = mask->l3_ok ?
11706 mlx5_flow_locate_proto_l3(&item, end_item) : 0;
11707 flow_dv_translate_integrity_l3(mask, value, headers_m, headers_v,
11708 l3_protocol == RTE_ETHER_TYPE_IPV4);
11709 flow_dv_translate_integrity_l4(mask, value, headers_m, headers_v);
11713 * Prepares DV flow counter with aging configuration.
11714 * Gets it by index when exists, creates a new one when doesn't.
11717 * Pointer to rte_eth_dev structure.
11718 * @param[in] dev_flow
11719 * Pointer to the mlx5_flow.
11720 * @param[in, out] flow
11721 * Pointer to the sub flow.
11723 * Pointer to the counter action configuration.
11725 * Pointer to the aging action configuration.
11726 * @param[out] error
11727 * Pointer to the error structure.
11730 * Pointer to the counter, NULL otherwise.
11732 static struct mlx5_flow_counter *
11733 flow_dv_prepare_counter(struct rte_eth_dev *dev,
11734 struct mlx5_flow *dev_flow,
11735 struct rte_flow *flow,
11736 const struct rte_flow_action_count *count,
11737 const struct rte_flow_action_age *age,
11738 struct rte_flow_error *error)
11740 if (!flow->counter) {
11741 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
11743 if (!flow->counter) {
11744 rte_flow_error_set(error, rte_errno,
11745 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11746 "cannot create counter object.");
11750 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
11754 * Release an ASO CT action by its own device.
11757 * Pointer to the Ethernet device structure.
11759 * Index of ASO CT action to release.
11762 * 0 when CT action was removed, otherwise the number of references.
11765 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
11767 struct mlx5_priv *priv = dev->data->dev_private;
11768 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
11770 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
11771 enum mlx5_aso_ct_state state =
11772 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
11774 /* Cannot release when CT is in the ASO SQ. */
11775 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
11777 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
11779 if (ct->dr_action_orig) {
11780 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
11781 claim_zero(mlx5_glue->destroy_flow_action
11782 (ct->dr_action_orig));
11784 ct->dr_action_orig = NULL;
11786 if (ct->dr_action_rply) {
11787 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
11788 claim_zero(mlx5_glue->destroy_flow_action
11789 (ct->dr_action_rply));
11791 ct->dr_action_rply = NULL;
11793 /* Clear the state to free, no need in 1st allocation. */
11794 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
11795 rte_spinlock_lock(&mng->ct_sl);
11796 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
11797 rte_spinlock_unlock(&mng->ct_sl);
11803 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx)
11805 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
11806 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
11807 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
11810 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
11811 if (dev->data->dev_started != 1)
11813 return flow_dv_aso_ct_dev_release(owndev, idx);
11817 * Resize the ASO CT pools array by 64 pools.
11820 * Pointer to the Ethernet device structure.
11823 * 0 on success, otherwise negative errno value and rte_errno is set.
11826 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
11828 struct mlx5_priv *priv = dev->data->dev_private;
11829 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
11830 void *old_pools = mng->pools;
11831 /* Magic number now, need a macro. */
11832 uint32_t resize = mng->n + 64;
11833 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
11834 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11837 rte_errno = ENOMEM;
11840 rte_rwlock_write_lock(&mng->resize_rwl);
11841 /* ASO SQ/QP was already initialized in the startup. */
11843 /* Realloc could be an alternative choice. */
11844 rte_memcpy(pools, old_pools,
11845 mng->n * sizeof(struct mlx5_aso_ct_pool *));
11846 mlx5_free(old_pools);
11849 mng->pools = pools;
11850 rte_rwlock_write_unlock(&mng->resize_rwl);
11855 * Create and initialize a new ASO CT pool.
11858 * Pointer to the Ethernet device structure.
11859 * @param[out] ct_free
11860 * Where to put the pointer of a new CT action.
11863 * The CT actions pool pointer and @p ct_free is set on success,
11864 * NULL otherwise and rte_errno is set.
11866 static struct mlx5_aso_ct_pool *
11867 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
11868 struct mlx5_aso_ct_action **ct_free)
11870 struct mlx5_priv *priv = dev->data->dev_private;
11871 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
11872 struct mlx5_aso_ct_pool *pool = NULL;
11873 struct mlx5_devx_obj *obj = NULL;
11875 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
11877 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->ctx,
11878 priv->sh->pdn, log_obj_size);
11880 rte_errno = ENODATA;
11881 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
11884 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11886 rte_errno = ENOMEM;
11887 claim_zero(mlx5_devx_cmd_destroy(obj));
11890 pool->devx_obj = obj;
11891 pool->index = mng->next;
11892 /* Resize pools array if there is no room for the new pool in it. */
11893 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
11894 claim_zero(mlx5_devx_cmd_destroy(obj));
11898 mng->pools[pool->index] = pool;
11900 /* Assign the first action in the new pool, the rest go to free list. */
11901 *ct_free = &pool->actions[0];
11902 /* Lock outside, the list operation is safe here. */
11903 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
11904 /* refcnt is 0 when allocating the memory. */
11905 pool->actions[i].offset = i;
11906 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
11912 * Allocate a ASO CT action from free list.
11915 * Pointer to the Ethernet device structure.
11916 * @param[out] error
11917 * Pointer to the error structure.
11920 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
11923 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
11925 struct mlx5_priv *priv = dev->data->dev_private;
11926 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
11927 struct mlx5_aso_ct_action *ct = NULL;
11928 struct mlx5_aso_ct_pool *pool;
11933 if (!priv->config.devx) {
11934 rte_errno = ENOTSUP;
11937 /* Get a free CT action, if no, a new pool will be created. */
11938 rte_spinlock_lock(&mng->ct_sl);
11939 ct = LIST_FIRST(&mng->free_cts);
11941 LIST_REMOVE(ct, next);
11942 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
11943 rte_spinlock_unlock(&mng->ct_sl);
11944 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
11945 NULL, "failed to create ASO CT pool");
11948 rte_spinlock_unlock(&mng->ct_sl);
11949 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
11950 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
11951 /* 0: inactive, 1: created, 2+: used by flows. */
11952 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
11953 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
11954 if (!ct->dr_action_orig) {
11955 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
11956 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
11957 (priv->sh->rx_domain, pool->devx_obj->obj,
11959 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
11962 RTE_SET_USED(reg_c);
11964 if (!ct->dr_action_orig) {
11965 flow_dv_aso_ct_dev_release(dev, ct_idx);
11966 rte_flow_error_set(error, rte_errno,
11967 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11968 "failed to create ASO CT action");
11972 if (!ct->dr_action_rply) {
11973 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
11974 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
11975 (priv->sh->rx_domain, pool->devx_obj->obj,
11977 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
11980 if (!ct->dr_action_rply) {
11981 flow_dv_aso_ct_dev_release(dev, ct_idx);
11982 rte_flow_error_set(error, rte_errno,
11983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11984 "failed to create ASO CT action");
11992 * Create a conntrack object with context and actions by using ASO mechanism.
11995 * Pointer to rte_eth_dev structure.
11997 * Pointer to conntrack information profile.
11998 * @param[out] error
11999 * Pointer to the error structure.
12002 * Index to conntrack object on success, 0 otherwise.
12005 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12006 const struct rte_flow_action_conntrack *pro,
12007 struct rte_flow_error *error)
12009 struct mlx5_priv *priv = dev->data->dev_private;
12010 struct mlx5_dev_ctx_shared *sh = priv->sh;
12011 struct mlx5_aso_ct_action *ct;
12014 if (!sh->ct_aso_en)
12015 return rte_flow_error_set(error, ENOTSUP,
12016 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12017 "Connection is not supported");
12018 idx = flow_dv_aso_ct_alloc(dev, error);
12020 return rte_flow_error_set(error, rte_errno,
12021 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12022 "Failed to allocate CT object");
12023 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12024 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12025 return rte_flow_error_set(error, EBUSY,
12026 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12027 "Failed to update CT");
12028 ct->is_original = !!pro->is_original_dir;
12029 ct->peer = pro->peer_port;
12034 * Fill the flow with DV spec, lock free
12035 * (mutex should be acquired by caller).
12038 * Pointer to rte_eth_dev structure.
12039 * @param[in, out] dev_flow
12040 * Pointer to the sub flow.
12042 * Pointer to the flow attributes.
12044 * Pointer to the list of items.
12045 * @param[in] actions
12046 * Pointer to the list of actions.
12047 * @param[out] error
12048 * Pointer to the error structure.
12051 * 0 on success, a negative errno value otherwise and rte_errno is set.
12054 flow_dv_translate(struct rte_eth_dev *dev,
12055 struct mlx5_flow *dev_flow,
12056 const struct rte_flow_attr *attr,
12057 const struct rte_flow_item items[],
12058 const struct rte_flow_action actions[],
12059 struct rte_flow_error *error)
12061 struct mlx5_priv *priv = dev->data->dev_private;
12062 struct mlx5_dev_config *dev_conf = &priv->config;
12063 struct rte_flow *flow = dev_flow->flow;
12064 struct mlx5_flow_handle *handle = dev_flow->handle;
12065 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12066 struct mlx5_flow_rss_desc *rss_desc;
12067 uint64_t item_flags = 0;
12068 uint64_t last_item = 0;
12069 uint64_t action_flags = 0;
12070 struct mlx5_flow_dv_matcher matcher = {
12072 .size = sizeof(matcher.mask.buf) -
12073 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
12077 bool actions_end = false;
12079 struct mlx5_flow_dv_modify_hdr_resource res;
12080 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12081 sizeof(struct mlx5_modification_cmd) *
12082 (MLX5_MAX_MODIFY_NUM + 1)];
12084 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12085 const struct rte_flow_action_count *count = NULL;
12086 const struct rte_flow_action_age *non_shared_age = NULL;
12087 union flow_dv_attr flow_attr = { .attr = 0 };
12089 union mlx5_flow_tbl_key tbl_key;
12090 uint32_t modify_action_position = UINT32_MAX;
12091 void *match_mask = matcher.mask.buf;
12092 void *match_value = dev_flow->dv.value.buf;
12093 uint8_t next_protocol = 0xff;
12094 struct rte_vlan_hdr vlan = { 0 };
12095 struct mlx5_flow_dv_dest_array_resource mdest_res;
12096 struct mlx5_flow_dv_sample_resource sample_res;
12097 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12098 const struct rte_flow_action_sample *sample = NULL;
12099 struct mlx5_flow_sub_actions_list *sample_act;
12100 uint32_t sample_act_pos = UINT32_MAX;
12101 uint32_t age_act_pos = UINT32_MAX;
12102 uint32_t num_of_dest = 0;
12103 int tmp_actions_n = 0;
12106 const struct mlx5_flow_tunnel *tunnel = NULL;
12107 struct flow_grp_info grp_info = {
12108 .external = !!dev_flow->external,
12109 .transfer = !!attr->transfer,
12110 .fdb_def_rule = !!priv->fdb_def_rule,
12111 .skip_scale = dev_flow->skip_scale &
12112 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12113 .std_tbl_fix = true,
12115 const struct rte_flow_item *head_item = items;
12118 return rte_flow_error_set(error, ENOMEM,
12119 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12121 "failed to push flow workspace");
12122 rss_desc = &wks->rss_desc;
12123 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12124 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12125 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12126 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12127 /* update normal path action resource into last index of array */
12128 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12129 if (is_tunnel_offload_active(dev)) {
12130 if (dev_flow->tunnel) {
12131 RTE_VERIFY(dev_flow->tof_type ==
12132 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12133 tunnel = dev_flow->tunnel;
12135 tunnel = mlx5_get_tof(items, actions,
12136 &dev_flow->tof_type);
12137 dev_flow->tunnel = tunnel;
12139 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12140 (dev, attr, tunnel, dev_flow->tof_type);
12142 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12143 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12144 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12148 dev_flow->dv.group = table;
12149 if (attr->transfer)
12150 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12151 /* number of actions must be set to 0 in case of dirty stack. */
12152 mhdr_res->actions_num = 0;
12153 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12155 * do not add decap action if match rule drops packet
12156 * HW rejects rules with decap & drop
12158 * if tunnel match rule was inserted before matching tunnel set
12159 * rule flow table used in the match rule must be registered.
12160 * current implementation handles that in the
12161 * flow_dv_match_register() at the function end.
12163 bool add_decap = true;
12164 const struct rte_flow_action *ptr = actions;
12166 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12167 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12173 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12177 dev_flow->dv.actions[actions_n++] =
12178 dev_flow->dv.encap_decap->action;
12179 action_flags |= MLX5_FLOW_ACTION_DECAP;
12182 for (; !actions_end ; actions++) {
12183 const struct rte_flow_action_queue *queue;
12184 const struct rte_flow_action_rss *rss;
12185 const struct rte_flow_action *action = actions;
12186 const uint8_t *rss_key;
12187 struct mlx5_flow_tbl_resource *tbl;
12188 struct mlx5_aso_age_action *age_act;
12189 struct mlx5_flow_counter *cnt_act;
12190 uint32_t port_id = 0;
12191 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12192 int action_type = actions->type;
12193 const struct rte_flow_action *found_action = NULL;
12194 uint32_t jump_group = 0;
12195 uint32_t owner_idx;
12196 struct mlx5_aso_ct_action *ct;
12198 if (!mlx5_flow_os_action_supported(action_type))
12199 return rte_flow_error_set(error, ENOTSUP,
12200 RTE_FLOW_ERROR_TYPE_ACTION,
12202 "action not supported");
12203 switch (action_type) {
12204 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12205 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12207 case RTE_FLOW_ACTION_TYPE_VOID:
12209 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12210 if (flow_dv_translate_action_port_id(dev, action,
12213 port_id_resource.port_id = port_id;
12214 MLX5_ASSERT(!handle->rix_port_id_action);
12215 if (flow_dv_port_id_action_resource_register
12216 (dev, &port_id_resource, dev_flow, error))
12218 dev_flow->dv.actions[actions_n++] =
12219 dev_flow->dv.port_id_action->action;
12220 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12221 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12222 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12225 case RTE_FLOW_ACTION_TYPE_FLAG:
12226 action_flags |= MLX5_FLOW_ACTION_FLAG;
12227 dev_flow->handle->mark = 1;
12228 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12229 struct rte_flow_action_mark mark = {
12230 .id = MLX5_FLOW_MARK_DEFAULT,
12233 if (flow_dv_convert_action_mark(dev, &mark,
12237 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12240 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12242 * Only one FLAG or MARK is supported per device flow
12243 * right now. So the pointer to the tag resource must be
12244 * zero before the register process.
12246 MLX5_ASSERT(!handle->dvh.rix_tag);
12247 if (flow_dv_tag_resource_register(dev, tag_be,
12250 MLX5_ASSERT(dev_flow->dv.tag_resource);
12251 dev_flow->dv.actions[actions_n++] =
12252 dev_flow->dv.tag_resource->action;
12254 case RTE_FLOW_ACTION_TYPE_MARK:
12255 action_flags |= MLX5_FLOW_ACTION_MARK;
12256 dev_flow->handle->mark = 1;
12257 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12258 const struct rte_flow_action_mark *mark =
12259 (const struct rte_flow_action_mark *)
12262 if (flow_dv_convert_action_mark(dev, mark,
12266 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12270 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12271 /* Legacy (non-extensive) MARK action. */
12272 tag_be = mlx5_flow_mark_set
12273 (((const struct rte_flow_action_mark *)
12274 (actions->conf))->id);
12275 MLX5_ASSERT(!handle->dvh.rix_tag);
12276 if (flow_dv_tag_resource_register(dev, tag_be,
12279 MLX5_ASSERT(dev_flow->dv.tag_resource);
12280 dev_flow->dv.actions[actions_n++] =
12281 dev_flow->dv.tag_resource->action;
12283 case RTE_FLOW_ACTION_TYPE_SET_META:
12284 if (flow_dv_convert_action_set_meta
12285 (dev, mhdr_res, attr,
12286 (const struct rte_flow_action_set_meta *)
12287 actions->conf, error))
12289 action_flags |= MLX5_FLOW_ACTION_SET_META;
12291 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12292 if (flow_dv_convert_action_set_tag
12294 (const struct rte_flow_action_set_tag *)
12295 actions->conf, error))
12297 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12299 case RTE_FLOW_ACTION_TYPE_DROP:
12300 action_flags |= MLX5_FLOW_ACTION_DROP;
12301 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12303 case RTE_FLOW_ACTION_TYPE_QUEUE:
12304 queue = actions->conf;
12305 rss_desc->queue_num = 1;
12306 rss_desc->queue[0] = queue->index;
12307 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12308 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12309 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12312 case RTE_FLOW_ACTION_TYPE_RSS:
12313 rss = actions->conf;
12314 memcpy(rss_desc->queue, rss->queue,
12315 rss->queue_num * sizeof(uint16_t));
12316 rss_desc->queue_num = rss->queue_num;
12317 /* NULL RSS key indicates default RSS key. */
12318 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12319 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12321 * rss->level and rss.types should be set in advance
12322 * when expanding items for RSS.
12324 action_flags |= MLX5_FLOW_ACTION_RSS;
12325 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12326 MLX5_FLOW_FATE_SHARED_RSS :
12327 MLX5_FLOW_FATE_QUEUE;
12329 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12330 flow->age = (uint32_t)(uintptr_t)(action->conf);
12331 age_act = flow_aso_age_get_by_idx(dev, flow->age);
12332 __atomic_fetch_add(&age_act->refcnt, 1,
12334 age_act_pos = actions_n++;
12335 action_flags |= MLX5_FLOW_ACTION_AGE;
12337 case RTE_FLOW_ACTION_TYPE_AGE:
12338 non_shared_age = action->conf;
12339 age_act_pos = actions_n++;
12340 action_flags |= MLX5_FLOW_ACTION_AGE;
12342 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12343 flow->counter = (uint32_t)(uintptr_t)(action->conf);
12344 cnt_act = flow_dv_counter_get_by_idx(dev, flow->counter,
12346 __atomic_fetch_add(&cnt_act->shared_info.refcnt, 1,
12348 /* Save information first, will apply later. */
12349 action_flags |= MLX5_FLOW_ACTION_COUNT;
12351 case RTE_FLOW_ACTION_TYPE_COUNT:
12352 if (!dev_conf->devx) {
12353 return rte_flow_error_set
12355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12357 "count action not supported");
12359 /* Save information first, will apply later. */
12360 count = action->conf;
12361 action_flags |= MLX5_FLOW_ACTION_COUNT;
12363 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12364 dev_flow->dv.actions[actions_n++] =
12365 priv->sh->pop_vlan_action;
12366 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12368 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12369 if (!(action_flags &
12370 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12371 flow_dev_get_vlan_info_from_items(items, &vlan);
12372 vlan.eth_proto = rte_be_to_cpu_16
12373 ((((const struct rte_flow_action_of_push_vlan *)
12374 actions->conf)->ethertype));
12375 found_action = mlx5_flow_find_action
12377 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12379 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12380 found_action = mlx5_flow_find_action
12382 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12384 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12385 if (flow_dv_create_action_push_vlan
12386 (dev, attr, &vlan, dev_flow, error))
12388 dev_flow->dv.actions[actions_n++] =
12389 dev_flow->dv.push_vlan_res->action;
12390 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12392 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12393 /* of_vlan_push action handled this action */
12394 MLX5_ASSERT(action_flags &
12395 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12397 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12398 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12400 flow_dev_get_vlan_info_from_items(items, &vlan);
12401 mlx5_update_vlan_vid_pcp(actions, &vlan);
12402 /* If no VLAN push - this is a modify header action */
12403 if (flow_dv_convert_action_modify_vlan_vid
12404 (mhdr_res, actions, error))
12406 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12408 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12409 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12410 if (flow_dv_create_action_l2_encap(dev, actions,
12415 dev_flow->dv.actions[actions_n++] =
12416 dev_flow->dv.encap_decap->action;
12417 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12418 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12419 sample_act->action_flags |=
12420 MLX5_FLOW_ACTION_ENCAP;
12422 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12423 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12424 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12428 dev_flow->dv.actions[actions_n++] =
12429 dev_flow->dv.encap_decap->action;
12430 action_flags |= MLX5_FLOW_ACTION_DECAP;
12432 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
12433 /* Handle encap with preceding decap. */
12434 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
12435 if (flow_dv_create_action_raw_encap
12436 (dev, actions, dev_flow, attr, error))
12438 dev_flow->dv.actions[actions_n++] =
12439 dev_flow->dv.encap_decap->action;
12441 /* Handle encap without preceding decap. */
12442 if (flow_dv_create_action_l2_encap
12443 (dev, actions, dev_flow, attr->transfer,
12446 dev_flow->dv.actions[actions_n++] =
12447 dev_flow->dv.encap_decap->action;
12449 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12450 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12451 sample_act->action_flags |=
12452 MLX5_FLOW_ACTION_ENCAP;
12454 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
12455 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
12457 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
12458 if (flow_dv_create_action_l2_decap
12459 (dev, dev_flow, attr->transfer, error))
12461 dev_flow->dv.actions[actions_n++] =
12462 dev_flow->dv.encap_decap->action;
12464 /* If decap is followed by encap, handle it at encap. */
12465 action_flags |= MLX5_FLOW_ACTION_DECAP;
12467 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
12468 dev_flow->dv.actions[actions_n++] =
12469 (void *)(uintptr_t)action->conf;
12470 action_flags |= MLX5_FLOW_ACTION_JUMP;
12472 case RTE_FLOW_ACTION_TYPE_JUMP:
12473 jump_group = ((const struct rte_flow_action_jump *)
12474 action->conf)->group;
12475 grp_info.std_tbl_fix = 0;
12476 if (dev_flow->skip_scale &
12477 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
12478 grp_info.skip_scale = 1;
12480 grp_info.skip_scale = 0;
12481 ret = mlx5_flow_group_to_table(dev, tunnel,
12487 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
12489 !!dev_flow->external,
12490 tunnel, jump_group, 0,
12493 return rte_flow_error_set
12495 RTE_FLOW_ERROR_TYPE_ACTION,
12497 "cannot create jump action.");
12498 if (flow_dv_jump_tbl_resource_register
12499 (dev, tbl, dev_flow, error)) {
12500 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12501 return rte_flow_error_set
12503 RTE_FLOW_ERROR_TYPE_ACTION,
12505 "cannot create jump action.");
12507 dev_flow->dv.actions[actions_n++] =
12508 dev_flow->dv.jump->action;
12509 action_flags |= MLX5_FLOW_ACTION_JUMP;
12510 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
12511 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
12514 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
12515 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
12516 if (flow_dv_convert_action_modify_mac
12517 (mhdr_res, actions, error))
12519 action_flags |= actions->type ==
12520 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
12521 MLX5_FLOW_ACTION_SET_MAC_SRC :
12522 MLX5_FLOW_ACTION_SET_MAC_DST;
12524 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
12525 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
12526 if (flow_dv_convert_action_modify_ipv4
12527 (mhdr_res, actions, error))
12529 action_flags |= actions->type ==
12530 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
12531 MLX5_FLOW_ACTION_SET_IPV4_SRC :
12532 MLX5_FLOW_ACTION_SET_IPV4_DST;
12534 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
12535 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
12536 if (flow_dv_convert_action_modify_ipv6
12537 (mhdr_res, actions, error))
12539 action_flags |= actions->type ==
12540 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
12541 MLX5_FLOW_ACTION_SET_IPV6_SRC :
12542 MLX5_FLOW_ACTION_SET_IPV6_DST;
12544 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
12545 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
12546 if (flow_dv_convert_action_modify_tp
12547 (mhdr_res, actions, items,
12548 &flow_attr, dev_flow, !!(action_flags &
12549 MLX5_FLOW_ACTION_DECAP), error))
12551 action_flags |= actions->type ==
12552 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
12553 MLX5_FLOW_ACTION_SET_TP_SRC :
12554 MLX5_FLOW_ACTION_SET_TP_DST;
12556 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
12557 if (flow_dv_convert_action_modify_dec_ttl
12558 (mhdr_res, items, &flow_attr, dev_flow,
12560 MLX5_FLOW_ACTION_DECAP), error))
12562 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
12564 case RTE_FLOW_ACTION_TYPE_SET_TTL:
12565 if (flow_dv_convert_action_modify_ttl
12566 (mhdr_res, actions, items, &flow_attr,
12567 dev_flow, !!(action_flags &
12568 MLX5_FLOW_ACTION_DECAP), error))
12570 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
12572 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
12573 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
12574 if (flow_dv_convert_action_modify_tcp_seq
12575 (mhdr_res, actions, error))
12577 action_flags |= actions->type ==
12578 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
12579 MLX5_FLOW_ACTION_INC_TCP_SEQ :
12580 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
12583 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
12584 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
12585 if (flow_dv_convert_action_modify_tcp_ack
12586 (mhdr_res, actions, error))
12588 action_flags |= actions->type ==
12589 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
12590 MLX5_FLOW_ACTION_INC_TCP_ACK :
12591 MLX5_FLOW_ACTION_DEC_TCP_ACK;
12593 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
12594 if (flow_dv_convert_action_set_reg
12595 (mhdr_res, actions, error))
12597 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12599 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
12600 if (flow_dv_convert_action_copy_mreg
12601 (dev, mhdr_res, actions, error))
12603 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12605 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
12606 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
12607 dev_flow->handle->fate_action =
12608 MLX5_FLOW_FATE_DEFAULT_MISS;
12610 case RTE_FLOW_ACTION_TYPE_METER:
12612 return rte_flow_error_set(error, rte_errno,
12613 RTE_FLOW_ERROR_TYPE_ACTION,
12614 NULL, "Failed to get meter in flow.");
12615 /* Set the meter action. */
12616 dev_flow->dv.actions[actions_n++] =
12617 wks->fm->meter_action;
12618 action_flags |= MLX5_FLOW_ACTION_METER;
12620 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
12621 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
12624 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
12626 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
12627 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
12630 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
12632 case RTE_FLOW_ACTION_TYPE_SAMPLE:
12633 sample_act_pos = actions_n;
12634 sample = (const struct rte_flow_action_sample *)
12637 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
12638 /* put encap action into group if work with port id */
12639 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
12640 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
12641 sample_act->action_flags |=
12642 MLX5_FLOW_ACTION_ENCAP;
12644 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
12645 if (flow_dv_convert_action_modify_field
12646 (dev, mhdr_res, actions, attr, error))
12648 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
12650 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
12651 owner_idx = (uint32_t)(uintptr_t)action->conf;
12652 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
12654 return rte_flow_error_set(error, EINVAL,
12655 RTE_FLOW_ERROR_TYPE_ACTION,
12657 "Failed to get CT object.");
12658 if (mlx5_aso_ct_available(priv->sh, ct))
12659 return rte_flow_error_set(error, rte_errno,
12660 RTE_FLOW_ERROR_TYPE_ACTION,
12662 "CT is unavailable.");
12663 if (ct->is_original)
12664 dev_flow->dv.actions[actions_n] =
12665 ct->dr_action_orig;
12667 dev_flow->dv.actions[actions_n] =
12668 ct->dr_action_rply;
12669 flow->indirect_type = MLX5_INDIRECT_ACTION_TYPE_CT;
12670 flow->ct = owner_idx;
12671 __atomic_fetch_add(&ct->refcnt, 1, __ATOMIC_RELAXED);
12673 action_flags |= MLX5_FLOW_ACTION_CT;
12675 case RTE_FLOW_ACTION_TYPE_END:
12676 actions_end = true;
12677 if (mhdr_res->actions_num) {
12678 /* create modify action if needed. */
12679 if (flow_dv_modify_hdr_resource_register
12680 (dev, mhdr_res, dev_flow, error))
12682 dev_flow->dv.actions[modify_action_position] =
12683 handle->dvh.modify_hdr->action;
12686 * Handle AGE and COUNT action by single HW counter
12687 * when they are not shared.
12689 if (action_flags & MLX5_FLOW_ACTION_AGE) {
12690 if ((non_shared_age &&
12691 count && !count->shared) ||
12692 !(priv->sh->flow_hit_aso_en &&
12693 (attr->group || attr->transfer))) {
12694 /* Creates age by counters. */
12695 cnt_act = flow_dv_prepare_counter
12702 dev_flow->dv.actions[age_act_pos] =
12706 if (!flow->age && non_shared_age) {
12707 flow->age = flow_dv_aso_age_alloc
12711 flow_dv_aso_age_params_init
12713 non_shared_age->context ?
12714 non_shared_age->context :
12715 (void *)(uintptr_t)
12716 (dev_flow->flow_idx),
12717 non_shared_age->timeout);
12719 age_act = flow_aso_age_get_by_idx(dev,
12721 dev_flow->dv.actions[age_act_pos] =
12722 age_act->dr_action;
12724 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
12726 * Create one count action, to be used
12727 * by all sub-flows.
12729 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
12734 dev_flow->dv.actions[actions_n++] =
12740 if (mhdr_res->actions_num &&
12741 modify_action_position == UINT32_MAX)
12742 modify_action_position = actions_n++;
12744 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
12745 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
12746 int item_type = items->type;
12748 if (!mlx5_flow_os_item_supported(item_type))
12749 return rte_flow_error_set(error, ENOTSUP,
12750 RTE_FLOW_ERROR_TYPE_ITEM,
12751 NULL, "item not supported");
12752 switch (item_type) {
12753 case RTE_FLOW_ITEM_TYPE_PORT_ID:
12754 flow_dv_translate_item_port_id
12755 (dev, match_mask, match_value, items, attr);
12756 last_item = MLX5_FLOW_ITEM_PORT_ID;
12758 case RTE_FLOW_ITEM_TYPE_ETH:
12759 flow_dv_translate_item_eth(match_mask, match_value,
12761 dev_flow->dv.group);
12762 matcher.priority = action_flags &
12763 MLX5_FLOW_ACTION_DEFAULT_MISS &&
12764 !dev_flow->external ?
12765 MLX5_PRIORITY_MAP_L3 :
12766 MLX5_PRIORITY_MAP_L2;
12767 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
12768 MLX5_FLOW_LAYER_OUTER_L2;
12770 case RTE_FLOW_ITEM_TYPE_VLAN:
12771 flow_dv_translate_item_vlan(dev_flow,
12772 match_mask, match_value,
12774 dev_flow->dv.group);
12775 matcher.priority = MLX5_PRIORITY_MAP_L2;
12776 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
12777 MLX5_FLOW_LAYER_INNER_VLAN) :
12778 (MLX5_FLOW_LAYER_OUTER_L2 |
12779 MLX5_FLOW_LAYER_OUTER_VLAN);
12781 case RTE_FLOW_ITEM_TYPE_IPV4:
12782 mlx5_flow_tunnel_ip_check(items, next_protocol,
12783 &item_flags, &tunnel);
12784 flow_dv_translate_item_ipv4(match_mask, match_value,
12786 dev_flow->dv.group);
12787 matcher.priority = MLX5_PRIORITY_MAP_L3;
12788 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
12789 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
12790 if (items->mask != NULL &&
12791 ((const struct rte_flow_item_ipv4 *)
12792 items->mask)->hdr.next_proto_id) {
12794 ((const struct rte_flow_item_ipv4 *)
12795 (items->spec))->hdr.next_proto_id;
12797 ((const struct rte_flow_item_ipv4 *)
12798 (items->mask))->hdr.next_proto_id;
12800 /* Reset for inner layer. */
12801 next_protocol = 0xff;
12804 case RTE_FLOW_ITEM_TYPE_IPV6:
12805 mlx5_flow_tunnel_ip_check(items, next_protocol,
12806 &item_flags, &tunnel);
12807 flow_dv_translate_item_ipv6(match_mask, match_value,
12809 dev_flow->dv.group);
12810 matcher.priority = MLX5_PRIORITY_MAP_L3;
12811 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
12812 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
12813 if (items->mask != NULL &&
12814 ((const struct rte_flow_item_ipv6 *)
12815 items->mask)->hdr.proto) {
12817 ((const struct rte_flow_item_ipv6 *)
12818 items->spec)->hdr.proto;
12820 ((const struct rte_flow_item_ipv6 *)
12821 items->mask)->hdr.proto;
12823 /* Reset for inner layer. */
12824 next_protocol = 0xff;
12827 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
12828 flow_dv_translate_item_ipv6_frag_ext(match_mask,
12831 last_item = tunnel ?
12832 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
12833 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
12834 if (items->mask != NULL &&
12835 ((const struct rte_flow_item_ipv6_frag_ext *)
12836 items->mask)->hdr.next_header) {
12838 ((const struct rte_flow_item_ipv6_frag_ext *)
12839 items->spec)->hdr.next_header;
12841 ((const struct rte_flow_item_ipv6_frag_ext *)
12842 items->mask)->hdr.next_header;
12844 /* Reset for inner layer. */
12845 next_protocol = 0xff;
12848 case RTE_FLOW_ITEM_TYPE_TCP:
12849 flow_dv_translate_item_tcp(match_mask, match_value,
12851 matcher.priority = MLX5_PRIORITY_MAP_L4;
12852 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
12853 MLX5_FLOW_LAYER_OUTER_L4_TCP;
12855 case RTE_FLOW_ITEM_TYPE_UDP:
12856 flow_dv_translate_item_udp(match_mask, match_value,
12858 matcher.priority = MLX5_PRIORITY_MAP_L4;
12859 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
12860 MLX5_FLOW_LAYER_OUTER_L4_UDP;
12862 case RTE_FLOW_ITEM_TYPE_GRE:
12863 flow_dv_translate_item_gre(match_mask, match_value,
12865 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12866 last_item = MLX5_FLOW_LAYER_GRE;
12868 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
12869 flow_dv_translate_item_gre_key(match_mask,
12870 match_value, items);
12871 last_item = MLX5_FLOW_LAYER_GRE_KEY;
12873 case RTE_FLOW_ITEM_TYPE_NVGRE:
12874 flow_dv_translate_item_nvgre(match_mask, match_value,
12876 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12877 last_item = MLX5_FLOW_LAYER_GRE;
12879 case RTE_FLOW_ITEM_TYPE_VXLAN:
12880 flow_dv_translate_item_vxlan(match_mask, match_value,
12882 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12883 last_item = MLX5_FLOW_LAYER_VXLAN;
12885 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
12886 flow_dv_translate_item_vxlan_gpe(match_mask,
12887 match_value, items,
12889 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12890 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
12892 case RTE_FLOW_ITEM_TYPE_GENEVE:
12893 flow_dv_translate_item_geneve(match_mask, match_value,
12895 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12896 last_item = MLX5_FLOW_LAYER_GENEVE;
12898 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
12899 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
12903 return rte_flow_error_set(error, -ret,
12904 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
12905 "cannot create GENEVE TLV option");
12906 flow->geneve_tlv_option = 1;
12907 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
12909 case RTE_FLOW_ITEM_TYPE_MPLS:
12910 flow_dv_translate_item_mpls(match_mask, match_value,
12911 items, last_item, tunnel);
12912 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12913 last_item = MLX5_FLOW_LAYER_MPLS;
12915 case RTE_FLOW_ITEM_TYPE_MARK:
12916 flow_dv_translate_item_mark(dev, match_mask,
12917 match_value, items);
12918 last_item = MLX5_FLOW_ITEM_MARK;
12920 case RTE_FLOW_ITEM_TYPE_META:
12921 flow_dv_translate_item_meta(dev, match_mask,
12922 match_value, attr, items);
12923 last_item = MLX5_FLOW_ITEM_METADATA;
12925 case RTE_FLOW_ITEM_TYPE_ICMP:
12926 flow_dv_translate_item_icmp(match_mask, match_value,
12928 last_item = MLX5_FLOW_LAYER_ICMP;
12930 case RTE_FLOW_ITEM_TYPE_ICMP6:
12931 flow_dv_translate_item_icmp6(match_mask, match_value,
12933 last_item = MLX5_FLOW_LAYER_ICMP6;
12935 case RTE_FLOW_ITEM_TYPE_TAG:
12936 flow_dv_translate_item_tag(dev, match_mask,
12937 match_value, items);
12938 last_item = MLX5_FLOW_ITEM_TAG;
12940 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
12941 flow_dv_translate_mlx5_item_tag(dev, match_mask,
12942 match_value, items);
12943 last_item = MLX5_FLOW_ITEM_TAG;
12945 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
12946 flow_dv_translate_item_tx_queue(dev, match_mask,
12949 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
12951 case RTE_FLOW_ITEM_TYPE_GTP:
12952 flow_dv_translate_item_gtp(match_mask, match_value,
12954 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12955 last_item = MLX5_FLOW_LAYER_GTP;
12957 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
12958 ret = flow_dv_translate_item_gtp_psc(match_mask,
12962 return rte_flow_error_set(error, -ret,
12963 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
12964 "cannot create GTP PSC item");
12965 last_item = MLX5_FLOW_LAYER_GTP_PSC;
12967 case RTE_FLOW_ITEM_TYPE_ECPRI:
12968 if (!mlx5_flex_parser_ecpri_exist(dev)) {
12969 /* Create it only the first time to be used. */
12970 ret = mlx5_flex_parser_ecpri_alloc(dev);
12972 return rte_flow_error_set
12974 RTE_FLOW_ERROR_TYPE_ITEM,
12976 "cannot create eCPRI parser");
12978 /* Adjust the length matcher and device flow value. */
12979 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
12980 dev_flow->dv.value.size =
12981 MLX5_ST_SZ_BYTES(fte_match_param);
12982 flow_dv_translate_item_ecpri(dev, match_mask,
12983 match_value, items);
12984 /* No other protocol should follow eCPRI layer. */
12985 last_item = MLX5_FLOW_LAYER_ECPRI;
12987 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
12988 flow_dv_translate_item_integrity(match_mask,
12992 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
12993 flow_dv_translate_item_aso_ct(dev, match_mask,
12994 match_value, items);
12999 item_flags |= last_item;
13002 * When E-Switch mode is enabled, we have two cases where we need to
13003 * set the source port manually.
13004 * The first one, is in case of Nic steering rule, and the second is
13005 * E-Switch rule where no port_id item was found. In both cases
13006 * the source port is set according the current port in use.
13008 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13009 (priv->representor || priv->master)) {
13010 if (flow_dv_translate_item_port_id(dev, match_mask,
13011 match_value, NULL, attr))
13014 #ifdef RTE_LIBRTE_MLX5_DEBUG
13015 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13016 dev_flow->dv.value.buf));
13019 * Layers may be already initialized from prefix flow if this dev_flow
13020 * is the suffix flow.
13022 handle->layers |= item_flags;
13023 if (action_flags & MLX5_FLOW_ACTION_RSS)
13024 flow_dv_hashfields_set(dev_flow, rss_desc);
13025 /* If has RSS action in the sample action, the Sample/Mirror resource
13026 * should be registered after the hash filed be update.
13028 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13029 ret = flow_dv_translate_action_sample(dev,
13038 ret = flow_dv_create_action_sample(dev,
13047 return rte_flow_error_set
13049 RTE_FLOW_ERROR_TYPE_ACTION,
13051 "cannot create sample action");
13052 if (num_of_dest > 1) {
13053 dev_flow->dv.actions[sample_act_pos] =
13054 dev_flow->dv.dest_array_res->action;
13056 dev_flow->dv.actions[sample_act_pos] =
13057 dev_flow->dv.sample_res->verbs_action;
13061 * For multiple destination (sample action with ratio=1), the encap
13062 * action and port id action will be combined into group action.
13063 * So need remove the original these actions in the flow and only
13064 * use the sample action instead of.
13066 if (num_of_dest > 1 &&
13067 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13069 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13071 for (i = 0; i < actions_n; i++) {
13072 if ((sample_act->dr_encap_action &&
13073 sample_act->dr_encap_action ==
13074 dev_flow->dv.actions[i]) ||
13075 (sample_act->dr_port_id_action &&
13076 sample_act->dr_port_id_action ==
13077 dev_flow->dv.actions[i]) ||
13078 (sample_act->dr_jump_action &&
13079 sample_act->dr_jump_action ==
13080 dev_flow->dv.actions[i]))
13082 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13084 memcpy((void *)dev_flow->dv.actions,
13085 (void *)temp_actions,
13086 tmp_actions_n * sizeof(void *));
13087 actions_n = tmp_actions_n;
13089 dev_flow->dv.actions_n = actions_n;
13090 dev_flow->act_flags = action_flags;
13091 if (wks->skip_matcher_reg)
13093 /* Register matcher. */
13094 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13095 matcher.mask.size);
13096 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13099 * When creating meter drop flow in drop table, using original
13100 * 5-tuple match, the matcher priority should be lower than
13103 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13104 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13105 matcher.priority <= MLX5_REG_BITS)
13106 matcher.priority += MLX5_REG_BITS;
13107 /* reserved field no needs to be set to 0 here. */
13108 tbl_key.is_fdb = attr->transfer;
13109 tbl_key.is_egress = attr->egress;
13110 tbl_key.level = dev_flow->dv.group;
13111 tbl_key.id = dev_flow->dv.table_id;
13112 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13113 tunnel, attr->group, error))
13119 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13122 * @param[in, out] action
13123 * Shred RSS action holding hash RX queue objects.
13124 * @param[in] hash_fields
13125 * Defines combination of packet fields to participate in RX hash.
13126 * @param[in] tunnel
13128 * @param[in] hrxq_idx
13129 * Hash RX queue index to set.
13132 * 0 on success, otherwise negative errno value.
13135 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13136 const uint64_t hash_fields,
13139 uint32_t *hrxqs = action->hrxq;
13141 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13142 case MLX5_RSS_HASH_IPV4:
13143 /* fall-through. */
13144 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13145 /* fall-through. */
13146 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13147 hrxqs[0] = hrxq_idx;
13149 case MLX5_RSS_HASH_IPV4_TCP:
13150 /* fall-through. */
13151 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13152 /* fall-through. */
13153 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13154 hrxqs[1] = hrxq_idx;
13156 case MLX5_RSS_HASH_IPV4_UDP:
13157 /* fall-through. */
13158 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13159 /* fall-through. */
13160 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13161 hrxqs[2] = hrxq_idx;
13163 case MLX5_RSS_HASH_IPV6:
13164 /* fall-through. */
13165 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13166 /* fall-through. */
13167 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13168 hrxqs[3] = hrxq_idx;
13170 case MLX5_RSS_HASH_IPV6_TCP:
13171 /* fall-through. */
13172 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13173 /* fall-through. */
13174 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13175 hrxqs[4] = hrxq_idx;
13177 case MLX5_RSS_HASH_IPV6_UDP:
13178 /* fall-through. */
13179 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13180 /* fall-through. */
13181 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13182 hrxqs[5] = hrxq_idx;
13184 case MLX5_RSS_HASH_NONE:
13185 hrxqs[6] = hrxq_idx;
13193 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13197 * Pointer to the Ethernet device structure.
13199 * Shared RSS action ID holding hash RX queue objects.
13200 * @param[in] hash_fields
13201 * Defines combination of packet fields to participate in RX hash.
13202 * @param[in] tunnel
13206 * Valid hash RX queue index, otherwise 0.
13209 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13210 const uint64_t hash_fields)
13212 struct mlx5_priv *priv = dev->data->dev_private;
13213 struct mlx5_shared_action_rss *shared_rss =
13214 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13215 const uint32_t *hrxqs = shared_rss->hrxq;
13217 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13218 case MLX5_RSS_HASH_IPV4:
13219 /* fall-through. */
13220 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13221 /* fall-through. */
13222 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13224 case MLX5_RSS_HASH_IPV4_TCP:
13225 /* fall-through. */
13226 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13227 /* fall-through. */
13228 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13230 case MLX5_RSS_HASH_IPV4_UDP:
13231 /* fall-through. */
13232 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13233 /* fall-through. */
13234 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13236 case MLX5_RSS_HASH_IPV6:
13237 /* fall-through. */
13238 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13239 /* fall-through. */
13240 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13242 case MLX5_RSS_HASH_IPV6_TCP:
13243 /* fall-through. */
13244 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13245 /* fall-through. */
13246 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13248 case MLX5_RSS_HASH_IPV6_UDP:
13249 /* fall-through. */
13250 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13251 /* fall-through. */
13252 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13254 case MLX5_RSS_HASH_NONE:
13263 * Apply the flow to the NIC, lock free,
13264 * (mutex should be acquired by caller).
13267 * Pointer to the Ethernet device structure.
13268 * @param[in, out] flow
13269 * Pointer to flow structure.
13270 * @param[out] error
13271 * Pointer to error structure.
13274 * 0 on success, a negative errno value otherwise and rte_errno is set.
13277 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13278 struct rte_flow_error *error)
13280 struct mlx5_flow_dv_workspace *dv;
13281 struct mlx5_flow_handle *dh;
13282 struct mlx5_flow_handle_dv *dv_h;
13283 struct mlx5_flow *dev_flow;
13284 struct mlx5_priv *priv = dev->data->dev_private;
13285 uint32_t handle_idx;
13289 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13290 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13293 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13294 dev_flow = &wks->flows[idx];
13295 dv = &dev_flow->dv;
13296 dh = dev_flow->handle;
13299 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13300 if (dv->transfer) {
13301 MLX5_ASSERT(priv->sh->dr_drop_action);
13302 dv->actions[n++] = priv->sh->dr_drop_action;
13304 #ifdef HAVE_MLX5DV_DR
13305 /* DR supports drop action placeholder. */
13306 MLX5_ASSERT(priv->sh->dr_drop_action);
13307 dv->actions[n++] = priv->sh->dr_drop_action;
13309 /* For DV we use the explicit drop queue. */
13310 MLX5_ASSERT(priv->drop_queue.hrxq);
13312 priv->drop_queue.hrxq->action;
13315 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13316 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13317 struct mlx5_hrxq *hrxq;
13320 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13326 "cannot get hash queue");
13329 dh->rix_hrxq = hrxq_idx;
13330 dv->actions[n++] = hrxq->action;
13331 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13332 struct mlx5_hrxq *hrxq = NULL;
13335 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13336 rss_desc->shared_rss,
13337 dev_flow->hash_fields);
13339 hrxq = mlx5_ipool_get
13340 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13345 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13346 "cannot get hash queue");
13349 dh->rix_srss = rss_desc->shared_rss;
13350 dv->actions[n++] = hrxq->action;
13351 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13352 if (!priv->sh->default_miss_action) {
13355 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13356 "default miss action not be created.");
13359 dv->actions[n++] = priv->sh->default_miss_action;
13361 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13362 (void *)&dv->value, n,
13363 dv->actions, &dh->drv_flow);
13365 rte_flow_error_set(error, errno,
13366 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13368 "hardware refuses to create flow");
13371 if (priv->vmwa_context &&
13372 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13374 * The rule contains the VLAN pattern.
13375 * For VF we are going to create VLAN
13376 * interface to make hypervisor set correct
13377 * e-Switch vport context.
13379 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13384 err = rte_errno; /* Save rte_errno before cleanup. */
13385 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13386 handle_idx, dh, next) {
13387 /* hrxq is union, don't clear it if the flag is not set. */
13388 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13389 mlx5_hrxq_release(dev, dh->rix_hrxq);
13391 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13394 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13395 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13397 rte_errno = err; /* Restore rte_errno. */
13402 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
13403 struct mlx5_cache_entry *entry)
13405 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
13408 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
13413 * Release the flow matcher.
13416 * Pointer to Ethernet device.
13418 * Index to port ID action resource.
13421 * 1 while a reference on it exists, 0 when freed.
13424 flow_dv_matcher_release(struct rte_eth_dev *dev,
13425 struct mlx5_flow_handle *handle)
13427 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
13428 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
13429 typeof(*tbl), tbl);
13432 MLX5_ASSERT(matcher->matcher_object);
13433 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
13434 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
13439 * Release encap_decap resource.
13442 * Pointer to the hash list.
13444 * Pointer to exist resource entry object.
13447 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
13448 struct mlx5_hlist_entry *entry)
13450 struct mlx5_dev_ctx_shared *sh = list->ctx;
13451 struct mlx5_flow_dv_encap_decap_resource *res =
13452 container_of(entry, typeof(*res), entry);
13454 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13455 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
13459 * Release an encap/decap resource.
13462 * Pointer to Ethernet device.
13463 * @param encap_decap_idx
13464 * Index of encap decap resource.
13467 * 1 while a reference on it exists, 0 when freed.
13470 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
13471 uint32_t encap_decap_idx)
13473 struct mlx5_priv *priv = dev->data->dev_private;
13474 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
13476 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
13478 if (!cache_resource)
13480 MLX5_ASSERT(cache_resource->action);
13481 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
13482 &cache_resource->entry);
13486 * Release an jump to table action resource.
13489 * Pointer to Ethernet device.
13491 * Index to the jump action resource.
13494 * 1 while a reference on it exists, 0 when freed.
13497 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
13500 struct mlx5_priv *priv = dev->data->dev_private;
13501 struct mlx5_flow_tbl_data_entry *tbl_data;
13503 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
13507 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
13511 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
13512 struct mlx5_hlist_entry *entry)
13514 struct mlx5_flow_dv_modify_hdr_resource *res =
13515 container_of(entry, typeof(*res), entry);
13517 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13522 * Release a modify-header resource.
13525 * Pointer to Ethernet device.
13527 * Pointer to mlx5_flow_handle.
13530 * 1 while a reference on it exists, 0 when freed.
13533 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
13534 struct mlx5_flow_handle *handle)
13536 struct mlx5_priv *priv = dev->data->dev_private;
13537 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
13539 MLX5_ASSERT(entry->action);
13540 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
13544 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
13545 struct mlx5_cache_entry *entry)
13547 struct mlx5_dev_ctx_shared *sh = list->ctx;
13548 struct mlx5_flow_dv_port_id_action_resource *cache =
13549 container_of(entry, typeof(*cache), entry);
13551 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
13552 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
13556 * Release port ID action resource.
13559 * Pointer to Ethernet device.
13561 * Pointer to mlx5_flow_handle.
13564 * 1 while a reference on it exists, 0 when freed.
13567 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
13570 struct mlx5_priv *priv = dev->data->dev_private;
13571 struct mlx5_flow_dv_port_id_action_resource *cache;
13573 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
13576 MLX5_ASSERT(cache->action);
13577 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
13582 * Release shared RSS action resource.
13585 * Pointer to Ethernet device.
13587 * Shared RSS action index.
13590 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
13592 struct mlx5_priv *priv = dev->data->dev_private;
13593 struct mlx5_shared_action_rss *shared_rss;
13595 shared_rss = mlx5_ipool_get
13596 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
13597 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13601 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
13602 struct mlx5_cache_entry *entry)
13604 struct mlx5_dev_ctx_shared *sh = list->ctx;
13605 struct mlx5_flow_dv_push_vlan_action_resource *cache =
13606 container_of(entry, typeof(*cache), entry);
13608 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
13609 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
13613 * Release push vlan action resource.
13616 * Pointer to Ethernet device.
13618 * Pointer to mlx5_flow_handle.
13621 * 1 while a reference on it exists, 0 when freed.
13624 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
13625 struct mlx5_flow_handle *handle)
13627 struct mlx5_priv *priv = dev->data->dev_private;
13628 struct mlx5_flow_dv_push_vlan_action_resource *cache;
13629 uint32_t idx = handle->dvh.rix_push_vlan;
13631 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
13634 MLX5_ASSERT(cache->action);
13635 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
13640 * Release the fate resource.
13643 * Pointer to Ethernet device.
13645 * Pointer to mlx5_flow_handle.
13648 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
13649 struct mlx5_flow_handle *handle)
13651 if (!handle->rix_fate)
13653 switch (handle->fate_action) {
13654 case MLX5_FLOW_FATE_QUEUE:
13655 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
13656 mlx5_hrxq_release(dev, handle->rix_hrxq);
13658 case MLX5_FLOW_FATE_JUMP:
13659 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
13661 case MLX5_FLOW_FATE_PORT_ID:
13662 flow_dv_port_id_action_resource_release(dev,
13663 handle->rix_port_id_action);
13666 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
13669 handle->rix_fate = 0;
13673 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
13674 struct mlx5_cache_entry *entry)
13676 struct mlx5_flow_dv_sample_resource *cache_resource =
13677 container_of(entry, typeof(*cache_resource), entry);
13678 struct rte_eth_dev *dev = cache_resource->dev;
13679 struct mlx5_priv *priv = dev->data->dev_private;
13681 if (cache_resource->verbs_action)
13682 claim_zero(mlx5_flow_os_destroy_flow_action
13683 (cache_resource->verbs_action));
13684 if (cache_resource->normal_path_tbl)
13685 flow_dv_tbl_resource_release(MLX5_SH(dev),
13686 cache_resource->normal_path_tbl);
13687 flow_dv_sample_sub_actions_release(dev,
13688 &cache_resource->sample_idx);
13689 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
13690 cache_resource->idx);
13691 DRV_LOG(DEBUG, "sample resource %p: removed",
13692 (void *)cache_resource);
13696 * Release an sample resource.
13699 * Pointer to Ethernet device.
13701 * Pointer to mlx5_flow_handle.
13704 * 1 while a reference on it exists, 0 when freed.
13707 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
13708 struct mlx5_flow_handle *handle)
13710 struct mlx5_priv *priv = dev->data->dev_private;
13711 struct mlx5_flow_dv_sample_resource *cache_resource;
13713 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
13714 handle->dvh.rix_sample);
13715 if (!cache_resource)
13717 MLX5_ASSERT(cache_resource->verbs_action);
13718 return mlx5_cache_unregister(&priv->sh->sample_action_list,
13719 &cache_resource->entry);
13723 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
13724 struct mlx5_cache_entry *entry)
13726 struct mlx5_flow_dv_dest_array_resource *cache_resource =
13727 container_of(entry, typeof(*cache_resource), entry);
13728 struct rte_eth_dev *dev = cache_resource->dev;
13729 struct mlx5_priv *priv = dev->data->dev_private;
13732 MLX5_ASSERT(cache_resource->action);
13733 if (cache_resource->action)
13734 claim_zero(mlx5_flow_os_destroy_flow_action
13735 (cache_resource->action));
13736 for (; i < cache_resource->num_of_dest; i++)
13737 flow_dv_sample_sub_actions_release(dev,
13738 &cache_resource->sample_idx[i]);
13739 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
13740 cache_resource->idx);
13741 DRV_LOG(DEBUG, "destination array resource %p: removed",
13742 (void *)cache_resource);
13746 * Release an destination array resource.
13749 * Pointer to Ethernet device.
13751 * Pointer to mlx5_flow_handle.
13754 * 1 while a reference on it exists, 0 when freed.
13757 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
13758 struct mlx5_flow_handle *handle)
13760 struct mlx5_priv *priv = dev->data->dev_private;
13761 struct mlx5_flow_dv_dest_array_resource *cache;
13763 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
13764 handle->dvh.rix_dest_array);
13767 MLX5_ASSERT(cache->action);
13768 return mlx5_cache_unregister(&priv->sh->dest_array_list,
13773 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
13775 struct mlx5_priv *priv = dev->data->dev_private;
13776 struct mlx5_dev_ctx_shared *sh = priv->sh;
13777 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
13778 sh->geneve_tlv_option_resource;
13779 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
13780 if (geneve_opt_resource) {
13781 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
13782 __ATOMIC_RELAXED))) {
13783 claim_zero(mlx5_devx_cmd_destroy
13784 (geneve_opt_resource->obj));
13785 mlx5_free(sh->geneve_tlv_option_resource);
13786 sh->geneve_tlv_option_resource = NULL;
13789 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
13793 * Remove the flow from the NIC but keeps it in memory.
13794 * Lock free, (mutex should be acquired by caller).
13797 * Pointer to Ethernet device.
13798 * @param[in, out] flow
13799 * Pointer to flow structure.
13802 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
13804 struct mlx5_flow_handle *dh;
13805 uint32_t handle_idx;
13806 struct mlx5_priv *priv = dev->data->dev_private;
13810 handle_idx = flow->dev_handles;
13811 while (handle_idx) {
13812 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
13816 if (dh->drv_flow) {
13817 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
13818 dh->drv_flow = NULL;
13820 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
13821 flow_dv_fate_resource_release(dev, dh);
13822 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13823 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13824 handle_idx = dh->next.next;
13829 * Remove the flow from the NIC and the memory.
13830 * Lock free, (mutex should be acquired by caller).
13833 * Pointer to the Ethernet device structure.
13834 * @param[in, out] flow
13835 * Pointer to flow structure.
13838 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
13840 struct mlx5_flow_handle *dev_handle;
13841 struct mlx5_priv *priv = dev->data->dev_private;
13842 struct mlx5_flow_meter_info *fm = NULL;
13847 flow_dv_remove(dev, flow);
13848 if (flow->counter) {
13849 flow_dv_counter_free(dev, flow->counter);
13853 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
13855 mlx5_flow_meter_detach(priv, fm);
13858 /* Keep the current age handling by default. */
13859 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
13860 flow_dv_aso_ct_release(dev, flow->ct);
13861 else if (flow->age)
13862 flow_dv_aso_age_release(dev, flow->age);
13863 if (flow->geneve_tlv_option) {
13864 flow_dv_geneve_tlv_option_resource_release(dev);
13865 flow->geneve_tlv_option = 0;
13867 while (flow->dev_handles) {
13868 uint32_t tmp_idx = flow->dev_handles;
13870 dev_handle = mlx5_ipool_get(priv->sh->ipool
13871 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
13874 flow->dev_handles = dev_handle->next.next;
13875 if (dev_handle->dvh.matcher)
13876 flow_dv_matcher_release(dev, dev_handle);
13877 if (dev_handle->dvh.rix_sample)
13878 flow_dv_sample_resource_release(dev, dev_handle);
13879 if (dev_handle->dvh.rix_dest_array)
13880 flow_dv_dest_array_resource_release(dev, dev_handle);
13881 if (dev_handle->dvh.rix_encap_decap)
13882 flow_dv_encap_decap_resource_release(dev,
13883 dev_handle->dvh.rix_encap_decap);
13884 if (dev_handle->dvh.modify_hdr)
13885 flow_dv_modify_hdr_resource_release(dev, dev_handle);
13886 if (dev_handle->dvh.rix_push_vlan)
13887 flow_dv_push_vlan_action_resource_release(dev,
13889 if (dev_handle->dvh.rix_tag)
13890 flow_dv_tag_release(dev,
13891 dev_handle->dvh.rix_tag);
13892 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
13893 flow_dv_fate_resource_release(dev, dev_handle);
13895 srss = dev_handle->rix_srss;
13896 if (fm && dev_handle->is_meter_flow_id &&
13897 dev_handle->split_flow_id)
13898 mlx5_ipool_free(fm->flow_ipool,
13899 dev_handle->split_flow_id);
13900 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
13904 flow_dv_shared_rss_action_release(dev, srss);
13908 * Release array of hash RX queue objects.
13912 * Pointer to the Ethernet device structure.
13913 * @param[in, out] hrxqs
13914 * Array of hash RX queue objects.
13917 * Total number of references to hash RX queue objects in *hrxqs* array
13918 * after this operation.
13921 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
13922 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
13927 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
13928 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
13938 * Release all hash RX queue objects representing shared RSS action.
13941 * Pointer to the Ethernet device structure.
13942 * @param[in, out] action
13943 * Shared RSS action to remove hash RX queue objects from.
13946 * Total number of references to hash RX queue objects stored in *action*
13947 * after this operation.
13948 * Expected to be 0 if no external references held.
13951 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
13952 struct mlx5_shared_action_rss *shared_rss)
13954 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
13958 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
13961 * Only one hash value is available for one L3+L4 combination:
13963 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
13964 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
13965 * same slot in mlx5_rss_hash_fields.
13968 * Pointer to the shared action RSS conf.
13969 * @param[in, out] hash_field
13970 * hash_field variable needed to be adjusted.
13976 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
13977 uint64_t *hash_field)
13979 uint64_t rss_types = rss->origin.types;
13981 switch (*hash_field & ~IBV_RX_HASH_INNER) {
13982 case MLX5_RSS_HASH_IPV4:
13983 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
13984 *hash_field &= ~MLX5_RSS_HASH_IPV4;
13985 if (rss_types & ETH_RSS_L3_DST_ONLY)
13986 *hash_field |= IBV_RX_HASH_DST_IPV4;
13987 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
13988 *hash_field |= IBV_RX_HASH_SRC_IPV4;
13990 *hash_field |= MLX5_RSS_HASH_IPV4;
13993 case MLX5_RSS_HASH_IPV6:
13994 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
13995 *hash_field &= ~MLX5_RSS_HASH_IPV6;
13996 if (rss_types & ETH_RSS_L3_DST_ONLY)
13997 *hash_field |= IBV_RX_HASH_DST_IPV6;
13998 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
13999 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14001 *hash_field |= MLX5_RSS_HASH_IPV6;
14004 case MLX5_RSS_HASH_IPV4_UDP:
14005 /* fall-through. */
14006 case MLX5_RSS_HASH_IPV6_UDP:
14007 if (rss_types & ETH_RSS_UDP) {
14008 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14009 if (rss_types & ETH_RSS_L4_DST_ONLY)
14010 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14011 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
14012 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14014 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14017 case MLX5_RSS_HASH_IPV4_TCP:
14018 /* fall-through. */
14019 case MLX5_RSS_HASH_IPV6_TCP:
14020 if (rss_types & ETH_RSS_TCP) {
14021 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14022 if (rss_types & ETH_RSS_L4_DST_ONLY)
14023 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14024 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
14025 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14027 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14036 * Setup shared RSS action.
14037 * Prepare set of hash RX queue objects sufficient to handle all valid
14038 * hash_fields combinations (see enum ibv_rx_hash_fields).
14041 * Pointer to the Ethernet device structure.
14042 * @param[in] action_idx
14043 * Shared RSS action ipool index.
14044 * @param[in, out] action
14045 * Partially initialized shared RSS action.
14046 * @param[out] error
14047 * Perform verbose error reporting if not NULL. Initialized in case of
14051 * 0 on success, otherwise negative errno value.
14054 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14055 uint32_t action_idx,
14056 struct mlx5_shared_action_rss *shared_rss,
14057 struct rte_flow_error *error)
14059 struct mlx5_flow_rss_desc rss_desc = { 0 };
14063 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14064 return rte_flow_error_set(error, rte_errno,
14065 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14066 "cannot setup indirection table");
14068 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14069 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14070 rss_desc.const_q = shared_rss->origin.queue;
14071 rss_desc.queue_num = shared_rss->origin.queue_num;
14072 /* Set non-zero value to indicate a shared RSS. */
14073 rss_desc.shared_rss = action_idx;
14074 rss_desc.ind_tbl = shared_rss->ind_tbl;
14075 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14077 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14080 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14081 if (shared_rss->origin.level > 1) {
14082 hash_fields |= IBV_RX_HASH_INNER;
14085 rss_desc.tunnel = tunnel;
14086 rss_desc.hash_fields = hash_fields;
14087 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14092 "cannot get hash queue");
14093 goto error_hrxq_new;
14095 err = __flow_dv_action_rss_hrxq_set
14096 (shared_rss, hash_fields, hrxq_idx);
14102 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14103 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14104 shared_rss->ind_tbl = NULL;
14110 * Create shared RSS action.
14113 * Pointer to the Ethernet device structure.
14115 * Shared action configuration.
14117 * RSS action specification used to create shared action.
14118 * @param[out] error
14119 * Perform verbose error reporting if not NULL. Initialized in case of
14123 * A valid shared action ID in case of success, 0 otherwise and
14124 * rte_errno is set.
14127 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14128 const struct rte_flow_indir_action_conf *conf,
14129 const struct rte_flow_action_rss *rss,
14130 struct rte_flow_error *error)
14132 struct mlx5_priv *priv = dev->data->dev_private;
14133 struct mlx5_shared_action_rss *shared_rss = NULL;
14134 void *queue = NULL;
14135 struct rte_flow_action_rss *origin;
14136 const uint8_t *rss_key;
14137 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14140 RTE_SET_USED(conf);
14141 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14143 shared_rss = mlx5_ipool_zmalloc
14144 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14145 if (!shared_rss || !queue) {
14146 rte_flow_error_set(error, ENOMEM,
14147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14148 "cannot allocate resource memory");
14149 goto error_rss_init;
14151 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14152 rte_flow_error_set(error, E2BIG,
14153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14154 "rss action number out of range");
14155 goto error_rss_init;
14157 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14158 sizeof(*shared_rss->ind_tbl),
14160 if (!shared_rss->ind_tbl) {
14161 rte_flow_error_set(error, ENOMEM,
14162 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14163 "cannot allocate resource memory");
14164 goto error_rss_init;
14166 memcpy(queue, rss->queue, queue_size);
14167 shared_rss->ind_tbl->queues = queue;
14168 shared_rss->ind_tbl->queues_n = rss->queue_num;
14169 origin = &shared_rss->origin;
14170 origin->func = rss->func;
14171 origin->level = rss->level;
14172 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
14173 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
14174 /* NULL RSS key indicates default RSS key. */
14175 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14176 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14177 origin->key = &shared_rss->key[0];
14178 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14179 origin->queue = queue;
14180 origin->queue_num = rss->queue_num;
14181 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14182 goto error_rss_init;
14183 rte_spinlock_init(&shared_rss->action_rss_sl);
14184 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14185 rte_spinlock_lock(&priv->shared_act_sl);
14186 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14187 &priv->rss_shared_actions, idx, shared_rss, next);
14188 rte_spinlock_unlock(&priv->shared_act_sl);
14192 if (shared_rss->ind_tbl)
14193 mlx5_free(shared_rss->ind_tbl);
14194 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14203 * Destroy the shared RSS action.
14204 * Release related hash RX queue objects.
14207 * Pointer to the Ethernet device structure.
14209 * The shared RSS action object ID to be removed.
14210 * @param[out] error
14211 * Perform verbose error reporting if not NULL. Initialized in case of
14215 * 0 on success, otherwise negative errno value.
14218 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14219 struct rte_flow_error *error)
14221 struct mlx5_priv *priv = dev->data->dev_private;
14222 struct mlx5_shared_action_rss *shared_rss =
14223 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14224 uint32_t old_refcnt = 1;
14226 uint16_t *queue = NULL;
14229 return rte_flow_error_set(error, EINVAL,
14230 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14231 "invalid shared action");
14232 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14234 return rte_flow_error_set(error, EBUSY,
14235 RTE_FLOW_ERROR_TYPE_ACTION,
14237 "shared rss hrxq has references");
14238 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14239 0, 0, __ATOMIC_ACQUIRE,
14241 return rte_flow_error_set(error, EBUSY,
14242 RTE_FLOW_ERROR_TYPE_ACTION,
14244 "shared rss has references");
14245 queue = shared_rss->ind_tbl->queues;
14246 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14248 return rte_flow_error_set(error, EBUSY,
14249 RTE_FLOW_ERROR_TYPE_ACTION,
14251 "shared rss indirection table has"
14254 rte_spinlock_lock(&priv->shared_act_sl);
14255 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14256 &priv->rss_shared_actions, idx, shared_rss, next);
14257 rte_spinlock_unlock(&priv->shared_act_sl);
14258 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14264 * Create indirect action, lock free,
14265 * (mutex should be acquired by caller).
14266 * Dispatcher for action type specific call.
14269 * Pointer to the Ethernet device structure.
14271 * Shared action configuration.
14272 * @param[in] action
14273 * Action specification used to create indirect action.
14274 * @param[out] error
14275 * Perform verbose error reporting if not NULL. Initialized in case of
14279 * A valid shared action handle in case of success, NULL otherwise and
14280 * rte_errno is set.
14282 static struct rte_flow_action_handle *
14283 flow_dv_action_create(struct rte_eth_dev *dev,
14284 const struct rte_flow_indir_action_conf *conf,
14285 const struct rte_flow_action *action,
14286 struct rte_flow_error *err)
14288 struct mlx5_priv *priv = dev->data->dev_private;
14289 uint32_t age_idx = 0;
14293 switch (action->type) {
14294 case RTE_FLOW_ACTION_TYPE_RSS:
14295 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14296 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14297 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14299 case RTE_FLOW_ACTION_TYPE_AGE:
14300 age_idx = flow_dv_aso_age_alloc(dev, err);
14305 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14306 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14307 flow_dv_aso_age_params_init(dev, age_idx,
14308 ((const struct rte_flow_action_age *)
14309 action->conf)->context ?
14310 ((const struct rte_flow_action_age *)
14311 action->conf)->context :
14312 (void *)(uintptr_t)idx,
14313 ((const struct rte_flow_action_age *)
14314 action->conf)->timeout);
14317 case RTE_FLOW_ACTION_TYPE_COUNT:
14318 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14319 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14320 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14322 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14323 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14325 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14328 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14329 NULL, "action type not supported");
14332 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14336 * Destroy the indirect action.
14337 * Release action related resources on the NIC and the memory.
14338 * Lock free, (mutex should be acquired by caller).
14339 * Dispatcher for action type specific call.
14342 * Pointer to the Ethernet device structure.
14343 * @param[in] handle
14344 * The indirect action object handle to be removed.
14345 * @param[out] error
14346 * Perform verbose error reporting if not NULL. Initialized in case of
14350 * 0 on success, otherwise negative errno value.
14353 flow_dv_action_destroy(struct rte_eth_dev *dev,
14354 struct rte_flow_action_handle *handle,
14355 struct rte_flow_error *error)
14357 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14358 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14359 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14360 struct mlx5_flow_counter *cnt;
14361 uint32_t no_flow_refcnt = 1;
14365 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14366 return __flow_dv_action_rss_release(dev, idx, error);
14367 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14368 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14369 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14370 &no_flow_refcnt, 1, false,
14373 return rte_flow_error_set(error, EBUSY,
14374 RTE_FLOW_ERROR_TYPE_ACTION,
14376 "Indirect count action has references");
14377 flow_dv_counter_free(dev, idx);
14379 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14380 ret = flow_dv_aso_age_release(dev, idx);
14383 * In this case, the last flow has a reference will
14384 * actually release the age action.
14386 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14387 " released with references %d.", idx, ret);
14389 case MLX5_INDIRECT_ACTION_TYPE_CT:
14390 ret = flow_dv_aso_ct_release(dev, idx);
14394 DRV_LOG(DEBUG, "Connection tracking object %u still "
14395 "has references %d.", idx, ret);
14398 return rte_flow_error_set(error, ENOTSUP,
14399 RTE_FLOW_ERROR_TYPE_ACTION,
14401 "action type not supported");
14406 * Updates in place shared RSS action configuration.
14409 * Pointer to the Ethernet device structure.
14411 * The shared RSS action object ID to be updated.
14412 * @param[in] action_conf
14413 * RSS action specification used to modify *shared_rss*.
14414 * @param[out] error
14415 * Perform verbose error reporting if not NULL. Initialized in case of
14419 * 0 on success, otherwise negative errno value.
14420 * @note: currently only support update of RSS queues.
14423 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
14424 const struct rte_flow_action_rss *action_conf,
14425 struct rte_flow_error *error)
14427 struct mlx5_priv *priv = dev->data->dev_private;
14428 struct mlx5_shared_action_rss *shared_rss =
14429 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14431 void *queue = NULL;
14432 uint16_t *queue_old = NULL;
14433 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
14436 return rte_flow_error_set(error, EINVAL,
14437 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14438 "invalid shared action to update");
14439 if (priv->obj_ops.ind_table_modify == NULL)
14440 return rte_flow_error_set(error, ENOTSUP,
14441 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14442 "cannot modify indirection table");
14443 queue = mlx5_malloc(MLX5_MEM_ZERO,
14444 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14447 return rte_flow_error_set(error, ENOMEM,
14448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14450 "cannot allocate resource memory");
14451 memcpy(queue, action_conf->queue, queue_size);
14452 MLX5_ASSERT(shared_rss->ind_tbl);
14453 rte_spinlock_lock(&shared_rss->action_rss_sl);
14454 queue_old = shared_rss->ind_tbl->queues;
14455 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
14456 queue, action_conf->queue_num, true);
14459 ret = rte_flow_error_set(error, rte_errno,
14460 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14461 "cannot update indirection table");
14463 mlx5_free(queue_old);
14464 shared_rss->origin.queue = queue;
14465 shared_rss->origin.queue_num = action_conf->queue_num;
14467 rte_spinlock_unlock(&shared_rss->action_rss_sl);
14472 * Updates in place conntrack context or direction.
14473 * Context update should be synchronized.
14476 * Pointer to the Ethernet device structure.
14478 * The conntrack object ID to be updated.
14479 * @param[in] update
14480 * Pointer to the structure of information to update.
14481 * @param[out] error
14482 * Perform verbose error reporting if not NULL. Initialized in case of
14486 * 0 on success, otherwise negative errno value.
14489 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
14490 const struct rte_flow_modify_conntrack *update,
14491 struct rte_flow_error *error)
14493 struct mlx5_priv *priv = dev->data->dev_private;
14494 struct mlx5_aso_ct_action *ct;
14495 const struct rte_flow_action_conntrack *new_prf;
14497 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
14500 if (PORT_ID(priv) != owner)
14501 return rte_flow_error_set(error, EACCES,
14502 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14504 "CT object owned by another port");
14505 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
14506 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
14508 return rte_flow_error_set(error, ENOMEM,
14509 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14511 "CT object is inactive");
14512 new_prf = &update->new_ct;
14513 if (update->direction)
14514 ct->is_original = !!new_prf->is_original_dir;
14515 if (update->state) {
14516 /* Only validate the profile when it needs to be updated. */
14517 ret = mlx5_validate_action_ct(dev, new_prf, error);
14520 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
14522 return rte_flow_error_set(error, EIO,
14523 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14525 "Failed to send CT context update WQE");
14526 /* Block until ready or a failure. */
14527 ret = mlx5_aso_ct_available(priv->sh, ct);
14529 rte_flow_error_set(error, rte_errno,
14530 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14532 "Timeout to get the CT update");
14538 * Updates in place shared action configuration, lock free,
14539 * (mutex should be acquired by caller).
14542 * Pointer to the Ethernet device structure.
14543 * @param[in] handle
14544 * The indirect action object handle to be updated.
14545 * @param[in] update
14546 * Action specification used to modify the action pointed by *handle*.
14547 * *update* could be of same type with the action pointed by the *handle*
14548 * handle argument, or some other structures like a wrapper, depending on
14549 * the indirect action type.
14550 * @param[out] error
14551 * Perform verbose error reporting if not NULL. Initialized in case of
14555 * 0 on success, otherwise negative errno value.
14558 flow_dv_action_update(struct rte_eth_dev *dev,
14559 struct rte_flow_action_handle *handle,
14560 const void *update,
14561 struct rte_flow_error *err)
14563 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14564 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14565 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14566 const void *action_conf;
14569 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14570 action_conf = ((const struct rte_flow_action *)update)->conf;
14571 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
14572 case MLX5_INDIRECT_ACTION_TYPE_CT:
14573 return __flow_dv_action_ct_update(dev, idx, update, err);
14575 return rte_flow_error_set(err, ENOTSUP,
14576 RTE_FLOW_ERROR_TYPE_ACTION,
14578 "action type update not supported");
14583 * Destroy the meter sub policy table rules.
14584 * Lock free, (mutex should be acquired by caller).
14587 * Pointer to Ethernet device.
14588 * @param[in] sub_policy
14589 * Pointer to meter sub policy table.
14592 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
14593 struct mlx5_flow_meter_sub_policy *sub_policy)
14595 struct mlx5_priv *priv = dev->data->dev_private;
14596 struct mlx5_flow_tbl_data_entry *tbl;
14597 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
14598 struct mlx5_flow_meter_info *next_fm;
14599 struct mlx5_sub_policy_color_rule *color_rule;
14603 for (i = 0; i < RTE_COLORS; i++) {
14605 if (i == RTE_COLOR_GREEN && policy &&
14606 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
14607 next_fm = mlx5_flow_meter_find(priv,
14608 policy->act_cnt[i].next_mtr_id, NULL);
14609 TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
14611 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
14612 tbl = container_of(color_rule->matcher->tbl,
14613 typeof(*tbl), tbl);
14614 mlx5_cache_unregister(&tbl->matchers,
14615 &color_rule->matcher->entry);
14616 TAILQ_REMOVE(&sub_policy->color_rules[i],
14617 color_rule, next_port);
14618 mlx5_free(color_rule);
14620 mlx5_flow_meter_detach(priv, next_fm);
14623 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
14624 if (sub_policy->rix_hrxq[i]) {
14625 if (policy && !policy->is_hierarchy)
14626 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
14627 sub_policy->rix_hrxq[i] = 0;
14629 if (sub_policy->jump_tbl[i]) {
14630 flow_dv_tbl_resource_release(MLX5_SH(dev),
14631 sub_policy->jump_tbl[i]);
14632 sub_policy->jump_tbl[i] = NULL;
14635 if (sub_policy->tbl_rsc) {
14636 flow_dv_tbl_resource_release(MLX5_SH(dev),
14637 sub_policy->tbl_rsc);
14638 sub_policy->tbl_rsc = NULL;
14643 * Destroy policy rules, lock free,
14644 * (mutex should be acquired by caller).
14645 * Dispatcher for action type specific call.
14648 * Pointer to the Ethernet device structure.
14649 * @param[in] mtr_policy
14650 * Meter policy struct.
14653 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
14654 struct mlx5_flow_meter_policy *mtr_policy)
14657 struct mlx5_flow_meter_sub_policy *sub_policy;
14658 uint16_t sub_policy_num;
14660 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
14661 sub_policy_num = (mtr_policy->sub_policy_num >>
14662 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
14663 MLX5_MTR_SUB_POLICY_NUM_MASK;
14664 for (j = 0; j < sub_policy_num; j++) {
14665 sub_policy = mtr_policy->sub_policys[i][j];
14667 __flow_dv_destroy_sub_policy_rules
14674 * Destroy policy action, lock free,
14675 * (mutex should be acquired by caller).
14676 * Dispatcher for action type specific call.
14679 * Pointer to the Ethernet device structure.
14680 * @param[in] mtr_policy
14681 * Meter policy struct.
14684 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
14685 struct mlx5_flow_meter_policy *mtr_policy)
14687 struct rte_flow_action *rss_action;
14688 struct mlx5_flow_handle dev_handle;
14691 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
14692 if (mtr_policy->act_cnt[i].rix_mark) {
14693 flow_dv_tag_release(dev,
14694 mtr_policy->act_cnt[i].rix_mark);
14695 mtr_policy->act_cnt[i].rix_mark = 0;
14697 if (mtr_policy->act_cnt[i].modify_hdr) {
14698 dev_handle.dvh.modify_hdr =
14699 mtr_policy->act_cnt[i].modify_hdr;
14700 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
14702 switch (mtr_policy->act_cnt[i].fate_action) {
14703 case MLX5_FLOW_FATE_SHARED_RSS:
14704 rss_action = mtr_policy->act_cnt[i].rss;
14705 mlx5_free(rss_action);
14707 case MLX5_FLOW_FATE_PORT_ID:
14708 if (mtr_policy->act_cnt[i].rix_port_id_action) {
14709 flow_dv_port_id_action_resource_release(dev,
14710 mtr_policy->act_cnt[i].rix_port_id_action);
14711 mtr_policy->act_cnt[i].rix_port_id_action = 0;
14714 case MLX5_FLOW_FATE_DROP:
14715 case MLX5_FLOW_FATE_JUMP:
14716 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
14717 mtr_policy->act_cnt[i].dr_jump_action[j] =
14721 /*Queue action do nothing*/
14725 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
14726 mtr_policy->dr_drop_action[j] = NULL;
14730 * Create policy action per domain, lock free,
14731 * (mutex should be acquired by caller).
14732 * Dispatcher for action type specific call.
14735 * Pointer to the Ethernet device structure.
14736 * @param[in] mtr_policy
14737 * Meter policy struct.
14738 * @param[in] action
14739 * Action specification used to create meter actions.
14740 * @param[out] error
14741 * Perform verbose error reporting if not NULL. Initialized in case of
14745 * 0 on success, otherwise negative errno value.
14748 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
14749 struct mlx5_flow_meter_policy *mtr_policy,
14750 const struct rte_flow_action *actions[RTE_COLORS],
14751 enum mlx5_meter_domain domain,
14752 struct rte_mtr_error *error)
14754 struct mlx5_priv *priv = dev->data->dev_private;
14755 struct rte_flow_error flow_err;
14756 const struct rte_flow_action *act;
14757 uint64_t action_flags = 0;
14758 struct mlx5_flow_handle dh;
14759 struct mlx5_flow dev_flow;
14760 struct mlx5_flow_dv_port_id_action_resource port_id_action;
14762 uint8_t egress, transfer;
14763 struct mlx5_meter_policy_action_container *act_cnt = NULL;
14765 struct mlx5_flow_dv_modify_hdr_resource res;
14766 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
14767 sizeof(struct mlx5_modification_cmd) *
14768 (MLX5_MAX_MODIFY_NUM + 1)];
14770 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
14772 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
14773 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
14774 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
14775 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
14776 memset(&port_id_action, 0,
14777 sizeof(struct mlx5_flow_dv_port_id_action_resource));
14778 memset(mhdr_res, 0, sizeof(*mhdr_res));
14779 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
14781 MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
14782 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
14783 dev_flow.handle = &dh;
14784 dev_flow.dv.port_id_action = &port_id_action;
14785 dev_flow.external = true;
14786 for (i = 0; i < RTE_COLORS; i++) {
14787 if (i < MLX5_MTR_RTE_COLORS)
14788 act_cnt = &mtr_policy->act_cnt[i];
14789 for (act = actions[i];
14790 act && act->type != RTE_FLOW_ACTION_TYPE_END;
14792 switch (act->type) {
14793 case RTE_FLOW_ACTION_TYPE_MARK:
14795 uint32_t tag_be = mlx5_flow_mark_set
14796 (((const struct rte_flow_action_mark *)
14799 if (i >= MLX5_MTR_RTE_COLORS)
14800 return -rte_mtr_error_set(error,
14802 RTE_MTR_ERROR_TYPE_METER_POLICY,
14804 "cannot create policy "
14805 "mark action for this color");
14806 dev_flow.handle->mark = 1;
14807 if (flow_dv_tag_resource_register(dev, tag_be,
14808 &dev_flow, &flow_err))
14809 return -rte_mtr_error_set(error,
14811 RTE_MTR_ERROR_TYPE_METER_POLICY,
14813 "cannot setup policy mark action");
14814 MLX5_ASSERT(dev_flow.dv.tag_resource);
14815 act_cnt->rix_mark =
14816 dev_flow.handle->dvh.rix_tag;
14817 action_flags |= MLX5_FLOW_ACTION_MARK;
14820 case RTE_FLOW_ACTION_TYPE_SET_TAG:
14821 if (i >= MLX5_MTR_RTE_COLORS)
14822 return -rte_mtr_error_set(error,
14824 RTE_MTR_ERROR_TYPE_METER_POLICY,
14826 "cannot create policy "
14827 "set tag action for this color");
14828 if (flow_dv_convert_action_set_tag
14830 (const struct rte_flow_action_set_tag *)
14831 act->conf, &flow_err))
14832 return -rte_mtr_error_set(error,
14834 RTE_MTR_ERROR_TYPE_METER_POLICY,
14835 NULL, "cannot convert policy "
14837 if (!mhdr_res->actions_num)
14838 return -rte_mtr_error_set(error,
14840 RTE_MTR_ERROR_TYPE_METER_POLICY,
14841 NULL, "cannot find policy "
14843 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
14845 case RTE_FLOW_ACTION_TYPE_DROP:
14847 struct mlx5_flow_mtr_mng *mtrmng =
14849 struct mlx5_flow_tbl_data_entry *tbl_data;
14852 * Create the drop table with
14853 * METER DROP level.
14855 if (!mtrmng->drop_tbl[domain]) {
14856 mtrmng->drop_tbl[domain] =
14857 flow_dv_tbl_resource_get(dev,
14858 MLX5_FLOW_TABLE_LEVEL_METER,
14859 egress, transfer, false, NULL, 0,
14860 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
14861 if (!mtrmng->drop_tbl[domain])
14862 return -rte_mtr_error_set
14864 RTE_MTR_ERROR_TYPE_METER_POLICY,
14866 "Failed to create meter drop table");
14868 tbl_data = container_of
14869 (mtrmng->drop_tbl[domain],
14870 struct mlx5_flow_tbl_data_entry, tbl);
14871 if (i < MLX5_MTR_RTE_COLORS) {
14872 act_cnt->dr_jump_action[domain] =
14873 tbl_data->jump.action;
14874 act_cnt->fate_action =
14875 MLX5_FLOW_FATE_DROP;
14877 if (i == RTE_COLOR_RED)
14878 mtr_policy->dr_drop_action[domain] =
14879 tbl_data->jump.action;
14880 action_flags |= MLX5_FLOW_ACTION_DROP;
14883 case RTE_FLOW_ACTION_TYPE_QUEUE:
14885 if (i >= MLX5_MTR_RTE_COLORS)
14886 return -rte_mtr_error_set(error,
14888 RTE_MTR_ERROR_TYPE_METER_POLICY,
14889 NULL, "cannot create policy "
14890 "fate queue for this color");
14892 ((const struct rte_flow_action_queue *)
14893 (act->conf))->index;
14894 act_cnt->fate_action =
14895 MLX5_FLOW_FATE_QUEUE;
14896 dev_flow.handle->fate_action =
14897 MLX5_FLOW_FATE_QUEUE;
14898 mtr_policy->is_queue = 1;
14899 action_flags |= MLX5_FLOW_ACTION_QUEUE;
14902 case RTE_FLOW_ACTION_TYPE_RSS:
14906 if (i >= MLX5_MTR_RTE_COLORS)
14907 return -rte_mtr_error_set(error,
14909 RTE_MTR_ERROR_TYPE_METER_POLICY,
14911 "cannot create policy "
14912 "rss action for this color");
14914 * Save RSS conf into policy struct
14915 * for translate stage.
14917 rss_size = (int)rte_flow_conv
14918 (RTE_FLOW_CONV_OP_ACTION,
14919 NULL, 0, act, &flow_err);
14921 return -rte_mtr_error_set(error,
14923 RTE_MTR_ERROR_TYPE_METER_POLICY,
14924 NULL, "Get the wrong "
14925 "rss action struct size");
14926 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
14927 rss_size, 0, SOCKET_ID_ANY);
14929 return -rte_mtr_error_set(error,
14931 RTE_MTR_ERROR_TYPE_METER_POLICY,
14933 "Fail to malloc rss action memory");
14934 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
14935 act_cnt->rss, rss_size,
14938 return -rte_mtr_error_set(error,
14940 RTE_MTR_ERROR_TYPE_METER_POLICY,
14941 NULL, "Fail to save "
14942 "rss action into policy struct");
14943 act_cnt->fate_action =
14944 MLX5_FLOW_FATE_SHARED_RSS;
14945 action_flags |= MLX5_FLOW_ACTION_RSS;
14948 case RTE_FLOW_ACTION_TYPE_PORT_ID:
14950 struct mlx5_flow_dv_port_id_action_resource
14952 uint32_t port_id = 0;
14954 if (i >= MLX5_MTR_RTE_COLORS)
14955 return -rte_mtr_error_set(error,
14957 RTE_MTR_ERROR_TYPE_METER_POLICY,
14958 NULL, "cannot create policy "
14959 "port action for this color");
14960 memset(&port_id_resource, 0,
14961 sizeof(port_id_resource));
14962 if (flow_dv_translate_action_port_id(dev, act,
14963 &port_id, &flow_err))
14964 return -rte_mtr_error_set(error,
14966 RTE_MTR_ERROR_TYPE_METER_POLICY,
14967 NULL, "cannot translate "
14968 "policy port action");
14969 port_id_resource.port_id = port_id;
14970 if (flow_dv_port_id_action_resource_register
14971 (dev, &port_id_resource,
14972 &dev_flow, &flow_err))
14973 return -rte_mtr_error_set(error,
14975 RTE_MTR_ERROR_TYPE_METER_POLICY,
14976 NULL, "cannot setup "
14977 "policy port action");
14978 act_cnt->rix_port_id_action =
14979 dev_flow.handle->rix_port_id_action;
14980 act_cnt->fate_action =
14981 MLX5_FLOW_FATE_PORT_ID;
14982 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
14985 case RTE_FLOW_ACTION_TYPE_JUMP:
14987 uint32_t jump_group = 0;
14988 uint32_t table = 0;
14989 struct mlx5_flow_tbl_data_entry *tbl_data;
14990 struct flow_grp_info grp_info = {
14991 .external = !!dev_flow.external,
14992 .transfer = !!transfer,
14993 .fdb_def_rule = !!priv->fdb_def_rule,
14995 .skip_scale = dev_flow.skip_scale &
14996 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
14998 struct mlx5_flow_meter_sub_policy *sub_policy =
14999 mtr_policy->sub_policys[domain][0];
15001 if (i >= MLX5_MTR_RTE_COLORS)
15002 return -rte_mtr_error_set(error,
15004 RTE_MTR_ERROR_TYPE_METER_POLICY,
15006 "cannot create policy "
15007 "jump action for this color");
15009 ((const struct rte_flow_action_jump *)
15011 if (mlx5_flow_group_to_table(dev, NULL,
15014 &grp_info, &flow_err))
15015 return -rte_mtr_error_set(error,
15017 RTE_MTR_ERROR_TYPE_METER_POLICY,
15018 NULL, "cannot setup "
15019 "policy jump action");
15020 sub_policy->jump_tbl[i] =
15021 flow_dv_tbl_resource_get(dev,
15024 !!dev_flow.external,
15025 NULL, jump_group, 0,
15028 (!sub_policy->jump_tbl[i])
15029 return -rte_mtr_error_set(error,
15031 RTE_MTR_ERROR_TYPE_METER_POLICY,
15032 NULL, "cannot create jump action.");
15033 tbl_data = container_of
15034 (sub_policy->jump_tbl[i],
15035 struct mlx5_flow_tbl_data_entry, tbl);
15036 act_cnt->dr_jump_action[domain] =
15037 tbl_data->jump.action;
15038 act_cnt->fate_action =
15039 MLX5_FLOW_FATE_JUMP;
15040 action_flags |= MLX5_FLOW_ACTION_JUMP;
15043 case RTE_FLOW_ACTION_TYPE_METER:
15045 const struct rte_flow_action_meter *mtr;
15046 struct mlx5_flow_meter_info *next_fm;
15047 struct mlx5_flow_meter_policy *next_policy;
15048 struct rte_flow_action tag_action;
15049 struct mlx5_rte_flow_action_set_tag set_tag;
15050 uint32_t next_mtr_idx = 0;
15053 next_fm = mlx5_flow_meter_find(priv,
15057 return -rte_mtr_error_set(error, EINVAL,
15058 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15059 "Fail to find next meter.");
15060 if (next_fm->def_policy)
15061 return -rte_mtr_error_set(error, EINVAL,
15062 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15063 "Hierarchy only supports termination meter.");
15064 next_policy = mlx5_flow_meter_policy_find(dev,
15065 next_fm->policy_id, NULL);
15066 MLX5_ASSERT(next_policy);
15067 if (next_fm->drop_cnt) {
15070 mlx5_flow_get_reg_id(dev,
15073 (struct rte_flow_error *)error);
15074 set_tag.offset = (priv->mtr_reg_share ?
15075 MLX5_MTR_COLOR_BITS : 0);
15076 set_tag.length = (priv->mtr_reg_share ?
15077 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15079 set_tag.data = next_mtr_idx;
15081 (enum rte_flow_action_type)
15082 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15083 tag_action.conf = &set_tag;
15084 if (flow_dv_convert_action_set_reg
15085 (mhdr_res, &tag_action,
15086 (struct rte_flow_error *)error))
15089 MLX5_FLOW_ACTION_SET_TAG;
15091 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15092 act_cnt->next_mtr_id = next_fm->meter_id;
15093 act_cnt->next_sub_policy = NULL;
15094 mtr_policy->is_hierarchy = 1;
15095 mtr_policy->dev = next_policy->dev;
15097 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15101 return -rte_mtr_error_set(error, ENOTSUP,
15102 RTE_MTR_ERROR_TYPE_METER_POLICY,
15103 NULL, "action type not supported");
15105 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15106 /* create modify action if needed. */
15107 dev_flow.dv.group = 1;
15108 if (flow_dv_modify_hdr_resource_register
15109 (dev, mhdr_res, &dev_flow, &flow_err))
15110 return -rte_mtr_error_set(error,
15112 RTE_MTR_ERROR_TYPE_METER_POLICY,
15113 NULL, "cannot register policy "
15115 act_cnt->modify_hdr =
15116 dev_flow.handle->dvh.modify_hdr;
15124 * Create policy action per domain, lock free,
15125 * (mutex should be acquired by caller).
15126 * Dispatcher for action type specific call.
15129 * Pointer to the Ethernet device structure.
15130 * @param[in] mtr_policy
15131 * Meter policy struct.
15132 * @param[in] action
15133 * Action specification used to create meter actions.
15134 * @param[out] error
15135 * Perform verbose error reporting if not NULL. Initialized in case of
15139 * 0 on success, otherwise negative errno value.
15142 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15143 struct mlx5_flow_meter_policy *mtr_policy,
15144 const struct rte_flow_action *actions[RTE_COLORS],
15145 struct rte_mtr_error *error)
15148 uint16_t sub_policy_num;
15150 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15151 sub_policy_num = (mtr_policy->sub_policy_num >>
15152 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15153 MLX5_MTR_SUB_POLICY_NUM_MASK;
15154 if (sub_policy_num) {
15155 ret = __flow_dv_create_domain_policy_acts(dev,
15156 mtr_policy, actions,
15157 (enum mlx5_meter_domain)i, error);
15166 * Query a DV flow rule for its statistics via DevX.
15169 * Pointer to Ethernet device.
15170 * @param[in] cnt_idx
15171 * Index to the flow counter.
15173 * Data retrieved by the query.
15174 * @param[out] error
15175 * Perform verbose error reporting if not NULL.
15178 * 0 on success, a negative errno value otherwise and rte_errno is set.
15181 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15182 struct rte_flow_error *error)
15184 struct mlx5_priv *priv = dev->data->dev_private;
15185 struct rte_flow_query_count *qc = data;
15187 if (!priv->config.devx)
15188 return rte_flow_error_set(error, ENOTSUP,
15189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15191 "counters are not supported");
15193 uint64_t pkts, bytes;
15194 struct mlx5_flow_counter *cnt;
15195 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15198 return rte_flow_error_set(error, -err,
15199 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15200 NULL, "cannot read counters");
15201 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15204 qc->hits = pkts - cnt->hits;
15205 qc->bytes = bytes - cnt->bytes;
15208 cnt->bytes = bytes;
15212 return rte_flow_error_set(error, EINVAL,
15213 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15215 "counters are not available");
15219 flow_dv_action_query(struct rte_eth_dev *dev,
15220 const struct rte_flow_action_handle *handle, void *data,
15221 struct rte_flow_error *error)
15223 struct mlx5_age_param *age_param;
15224 struct rte_flow_query_age *resp;
15225 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15226 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15227 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15228 struct mlx5_priv *priv = dev->data->dev_private;
15229 struct mlx5_aso_ct_action *ct;
15234 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15235 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15237 resp->aged = __atomic_load_n(&age_param->state,
15238 __ATOMIC_RELAXED) == AGE_TMOUT ?
15240 resp->sec_since_last_hit_valid = !resp->aged;
15241 if (resp->sec_since_last_hit_valid)
15242 resp->sec_since_last_hit = __atomic_load_n
15243 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15245 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15246 return flow_dv_query_count(dev, idx, data, error);
15247 case MLX5_INDIRECT_ACTION_TYPE_CT:
15248 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15249 if (owner != PORT_ID(priv))
15250 return rte_flow_error_set(error, EACCES,
15251 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15253 "CT object owned by another port");
15254 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15255 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15258 return rte_flow_error_set(error, EFAULT,
15259 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15261 "CT object is inactive");
15262 ((struct rte_flow_action_conntrack *)data)->peer_port =
15264 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15266 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15267 return rte_flow_error_set(error, EIO,
15268 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15270 "Failed to query CT context");
15273 return rte_flow_error_set(error, ENOTSUP,
15274 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15275 "action type query not supported");
15280 * Query a flow rule AGE action for aging information.
15283 * Pointer to Ethernet device.
15285 * Pointer to the sub flow.
15287 * data retrieved by the query.
15288 * @param[out] error
15289 * Perform verbose error reporting if not NULL.
15292 * 0 on success, a negative errno value otherwise and rte_errno is set.
15295 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15296 void *data, struct rte_flow_error *error)
15298 struct rte_flow_query_age *resp = data;
15299 struct mlx5_age_param *age_param;
15302 struct mlx5_aso_age_action *act =
15303 flow_aso_age_get_by_idx(dev, flow->age);
15305 age_param = &act->age_params;
15306 } else if (flow->counter) {
15307 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15309 if (!age_param || !age_param->timeout)
15310 return rte_flow_error_set
15312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15313 NULL, "cannot read age data");
15315 return rte_flow_error_set(error, EINVAL,
15316 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15317 NULL, "age data not available");
15319 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15321 resp->sec_since_last_hit_valid = !resp->aged;
15322 if (resp->sec_since_last_hit_valid)
15323 resp->sec_since_last_hit = __atomic_load_n
15324 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15331 * @see rte_flow_query()
15332 * @see rte_flow_ops
15335 flow_dv_query(struct rte_eth_dev *dev,
15336 struct rte_flow *flow __rte_unused,
15337 const struct rte_flow_action *actions __rte_unused,
15338 void *data __rte_unused,
15339 struct rte_flow_error *error __rte_unused)
15343 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15344 switch (actions->type) {
15345 case RTE_FLOW_ACTION_TYPE_VOID:
15347 case RTE_FLOW_ACTION_TYPE_COUNT:
15348 ret = flow_dv_query_count(dev, flow->counter, data,
15351 case RTE_FLOW_ACTION_TYPE_AGE:
15352 ret = flow_dv_query_age(dev, flow, data, error);
15355 return rte_flow_error_set(error, ENOTSUP,
15356 RTE_FLOW_ERROR_TYPE_ACTION,
15358 "action not supported");
15365 * Destroy the meter table set.
15366 * Lock free, (mutex should be acquired by caller).
15369 * Pointer to Ethernet device.
15371 * Meter information table.
15374 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
15375 struct mlx5_flow_meter_info *fm)
15377 struct mlx5_priv *priv = dev->data->dev_private;
15380 if (!fm || !priv->config.dv_flow_en)
15382 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15383 if (fm->drop_rule[i]) {
15384 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
15385 fm->drop_rule[i] = NULL;
15391 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
15393 struct mlx5_priv *priv = dev->data->dev_private;
15394 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15395 struct mlx5_flow_tbl_data_entry *tbl;
15398 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15399 if (mtrmng->def_rule[i]) {
15400 claim_zero(mlx5_flow_os_destroy_flow
15401 (mtrmng->def_rule[i]));
15402 mtrmng->def_rule[i] = NULL;
15404 if (mtrmng->def_matcher[i]) {
15405 tbl = container_of(mtrmng->def_matcher[i]->tbl,
15406 struct mlx5_flow_tbl_data_entry, tbl);
15407 mlx5_cache_unregister(&tbl->matchers,
15408 &mtrmng->def_matcher[i]->entry);
15409 mtrmng->def_matcher[i] = NULL;
15411 for (j = 0; j < MLX5_REG_BITS; j++) {
15412 if (mtrmng->drop_matcher[i][j]) {
15414 container_of(mtrmng->drop_matcher[i][j]->tbl,
15415 struct mlx5_flow_tbl_data_entry,
15417 mlx5_cache_unregister(&tbl->matchers,
15418 &mtrmng->drop_matcher[i][j]->entry);
15419 mtrmng->drop_matcher[i][j] = NULL;
15422 if (mtrmng->drop_tbl[i]) {
15423 flow_dv_tbl_resource_release(MLX5_SH(dev),
15424 mtrmng->drop_tbl[i]);
15425 mtrmng->drop_tbl[i] = NULL;
15430 /* Number of meter flow actions, count and jump or count and drop. */
15431 #define METER_ACTIONS 2
15434 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
15435 enum mlx5_meter_domain domain)
15437 struct mlx5_priv *priv = dev->data->dev_private;
15438 struct mlx5_flow_meter_def_policy *def_policy =
15439 priv->sh->mtrmng->def_policy[domain];
15441 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
15442 mlx5_free(def_policy);
15443 priv->sh->mtrmng->def_policy[domain] = NULL;
15447 * Destroy the default policy table set.
15450 * Pointer to Ethernet device.
15453 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
15455 struct mlx5_priv *priv = dev->data->dev_private;
15458 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
15459 if (priv->sh->mtrmng->def_policy[i])
15460 __flow_dv_destroy_domain_def_policy(dev,
15461 (enum mlx5_meter_domain)i);
15462 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
15466 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
15467 uint32_t color_reg_c_idx,
15468 enum rte_color color, void *matcher_object,
15469 int actions_n, void *actions,
15470 bool match_src_port, const struct rte_flow_item *item,
15471 void **rule, const struct rte_flow_attr *attr)
15474 struct mlx5_flow_dv_match_params value = {
15475 .size = sizeof(value.buf) -
15476 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15478 struct mlx5_flow_dv_match_params matcher = {
15479 .size = sizeof(matcher.buf) -
15480 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15482 struct mlx5_priv *priv = dev->data->dev_private;
15484 if (match_src_port && (priv->representor || priv->master)) {
15485 if (flow_dv_translate_item_port_id(dev, matcher.buf,
15486 value.buf, item, attr)) {
15488 "Failed to create meter policy flow with port.");
15492 flow_dv_match_meta_reg(matcher.buf, value.buf,
15493 (enum modify_reg)color_reg_c_idx,
15494 rte_col_2_mlx5_col(color),
15496 ret = mlx5_flow_os_create_flow(matcher_object,
15497 (void *)&value, actions_n, actions, rule);
15499 DRV_LOG(ERR, "Failed to create meter policy flow.");
15506 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
15507 uint32_t color_reg_c_idx,
15509 struct mlx5_flow_meter_sub_policy *sub_policy,
15510 const struct rte_flow_attr *attr,
15511 bool match_src_port,
15512 const struct rte_flow_item *item,
15513 struct mlx5_flow_dv_matcher **policy_matcher,
15514 struct rte_flow_error *error)
15516 struct mlx5_cache_entry *entry;
15517 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
15518 struct mlx5_flow_dv_matcher matcher = {
15520 .size = sizeof(matcher.mask.buf) -
15521 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15525 struct mlx5_flow_dv_match_params value = {
15526 .size = sizeof(value.buf) -
15527 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15529 struct mlx5_flow_cb_ctx ctx = {
15533 struct mlx5_flow_tbl_data_entry *tbl_data;
15534 struct mlx5_priv *priv = dev->data->dev_private;
15535 uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
15537 if (match_src_port && (priv->representor || priv->master)) {
15538 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
15539 value.buf, item, attr)) {
15541 "Failed to register meter drop matcher with port.");
15545 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
15546 if (priority < RTE_COLOR_RED)
15547 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
15548 (enum modify_reg)color_reg_c_idx, 0, color_mask);
15549 matcher.priority = priority;
15550 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
15551 matcher.mask.size);
15552 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
15554 DRV_LOG(ERR, "Failed to register meter drop matcher.");
15558 container_of(entry, struct mlx5_flow_dv_matcher, entry);
15563 * Create the policy rules per domain.
15566 * Pointer to Ethernet device.
15567 * @param[in] sub_policy
15568 * Pointer to sub policy table..
15569 * @param[in] egress
15570 * Direction of the table.
15571 * @param[in] transfer
15572 * E-Switch or NIC flow.
15574 * Pointer to policy action list per color.
15577 * 0 on success, -1 otherwise.
15580 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
15581 struct mlx5_flow_meter_sub_policy *sub_policy,
15582 uint8_t egress, uint8_t transfer, bool match_src_port,
15583 struct mlx5_meter_policy_acts acts[RTE_COLORS])
15585 struct mlx5_priv *priv = dev->data->dev_private;
15586 struct rte_flow_error flow_err;
15587 uint32_t color_reg_c_idx;
15588 struct rte_flow_attr attr = {
15589 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
15592 .egress = !!egress,
15593 .transfer = !!transfer,
15597 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
15598 struct mlx5_sub_policy_color_rule *color_rule;
15602 /* Create policy table with POLICY level. */
15603 if (!sub_policy->tbl_rsc)
15604 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
15605 MLX5_FLOW_TABLE_LEVEL_POLICY,
15606 egress, transfer, false, NULL, 0, 0,
15607 sub_policy->idx, &flow_err);
15608 if (!sub_policy->tbl_rsc) {
15610 "Failed to create meter sub policy table.");
15613 /* Prepare matchers. */
15614 color_reg_c_idx = ret;
15615 for (i = 0; i < RTE_COLORS; i++) {
15616 TAILQ_INIT(&sub_policy->color_rules[i]);
15617 if (i == RTE_COLOR_YELLOW || !acts[i].actions_n)
15619 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
15620 sizeof(struct mlx5_sub_policy_color_rule),
15623 DRV_LOG(ERR, "No memory to create color rule.");
15626 color_rule->src_port = priv->representor_id;
15628 /* Create matchers for Color. */
15629 if (__flow_dv_create_policy_matcher(dev,
15630 color_reg_c_idx, i, sub_policy, &attr,
15631 (i != RTE_COLOR_RED ? match_src_port : false),
15632 NULL, &color_rule->matcher, &flow_err)) {
15633 DRV_LOG(ERR, "Failed to create color matcher.");
15636 /* Create flow, matching color. */
15637 if (__flow_dv_create_policy_flow(dev,
15638 color_reg_c_idx, (enum rte_color)i,
15639 color_rule->matcher->matcher_object,
15641 acts[i].dv_actions,
15642 (i != RTE_COLOR_RED ? match_src_port : false),
15643 NULL, &color_rule->rule,
15645 DRV_LOG(ERR, "Failed to create color rule.");
15648 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
15649 color_rule, next_port);
15654 if (color_rule->rule)
15655 mlx5_flow_os_destroy_flow(color_rule->rule);
15656 if (color_rule->matcher) {
15657 struct mlx5_flow_tbl_data_entry *tbl =
15658 container_of(color_rule->matcher->tbl,
15659 typeof(*tbl), tbl);
15660 mlx5_cache_unregister(&tbl->matchers,
15661 &color_rule->matcher->entry);
15663 mlx5_free(color_rule);
15669 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
15670 struct mlx5_flow_meter_policy *mtr_policy,
15671 struct mlx5_flow_meter_sub_policy *sub_policy,
15674 struct mlx5_priv *priv = dev->data->dev_private;
15675 struct mlx5_meter_policy_acts acts[RTE_COLORS];
15676 struct mlx5_flow_dv_tag_resource *tag;
15677 struct mlx5_flow_dv_port_id_action_resource *port_action;
15678 struct mlx5_hrxq *hrxq;
15679 struct mlx5_flow_meter_info *next_fm = NULL;
15680 struct mlx5_flow_meter_policy *next_policy;
15681 struct mlx5_flow_meter_sub_policy *next_sub_policy;
15682 struct mlx5_flow_tbl_data_entry *tbl_data;
15683 struct rte_flow_error error;
15684 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15685 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15686 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
15687 bool match_src_port = false;
15690 for (i = 0; i < RTE_COLORS; i++) {
15691 acts[i].actions_n = 0;
15692 if (i == RTE_COLOR_YELLOW)
15694 if (i == RTE_COLOR_RED) {
15695 /* Only support drop on red. */
15696 acts[i].dv_actions[0] =
15697 mtr_policy->dr_drop_action[domain];
15698 acts[i].actions_n = 1;
15701 if (mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
15702 struct rte_flow_attr attr = {
15703 .transfer = transfer
15706 next_fm = mlx5_flow_meter_find(priv,
15707 mtr_policy->act_cnt[i].next_mtr_id,
15711 "Failed to get next hierarchy meter.");
15714 if (mlx5_flow_meter_attach(priv, next_fm,
15716 DRV_LOG(ERR, "%s", error.message);
15720 /* Meter action must be the first for TX. */
15722 acts[i].dv_actions[acts[i].actions_n] =
15723 next_fm->meter_action;
15724 acts[i].actions_n++;
15727 if (mtr_policy->act_cnt[i].rix_mark) {
15728 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
15729 mtr_policy->act_cnt[i].rix_mark);
15731 DRV_LOG(ERR, "Failed to find "
15732 "mark action for policy.");
15735 acts[i].dv_actions[acts[i].actions_n] =
15737 acts[i].actions_n++;
15739 if (mtr_policy->act_cnt[i].modify_hdr) {
15740 acts[i].dv_actions[acts[i].actions_n] =
15741 mtr_policy->act_cnt[i].modify_hdr->action;
15742 acts[i].actions_n++;
15744 if (mtr_policy->act_cnt[i].fate_action) {
15745 switch (mtr_policy->act_cnt[i].fate_action) {
15746 case MLX5_FLOW_FATE_PORT_ID:
15747 port_action = mlx5_ipool_get
15748 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
15749 mtr_policy->act_cnt[i].rix_port_id_action);
15750 if (!port_action) {
15751 DRV_LOG(ERR, "Failed to find "
15752 "port action for policy.");
15755 acts[i].dv_actions[acts[i].actions_n] =
15756 port_action->action;
15757 acts[i].actions_n++;
15758 mtr_policy->dev = dev;
15759 match_src_port = true;
15761 case MLX5_FLOW_FATE_DROP:
15762 case MLX5_FLOW_FATE_JUMP:
15763 acts[i].dv_actions[acts[i].actions_n] =
15764 mtr_policy->act_cnt[i].dr_jump_action[domain];
15765 acts[i].actions_n++;
15767 case MLX5_FLOW_FATE_SHARED_RSS:
15768 case MLX5_FLOW_FATE_QUEUE:
15769 hrxq = mlx5_ipool_get
15770 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
15771 sub_policy->rix_hrxq[i]);
15773 DRV_LOG(ERR, "Failed to find "
15774 "queue action for policy.");
15777 acts[i].dv_actions[acts[i].actions_n] =
15779 acts[i].actions_n++;
15781 case MLX5_FLOW_FATE_MTR:
15784 "No next hierarchy meter.");
15788 acts[i].dv_actions[acts[i].actions_n] =
15789 next_fm->meter_action;
15790 acts[i].actions_n++;
15792 if (mtr_policy->act_cnt[i].next_sub_policy) {
15794 mtr_policy->act_cnt[i].next_sub_policy;
15797 mlx5_flow_meter_policy_find(dev,
15798 next_fm->policy_id, NULL);
15799 MLX5_ASSERT(next_policy);
15801 next_policy->sub_policys[domain][0];
15804 container_of(next_sub_policy->tbl_rsc,
15805 struct mlx5_flow_tbl_data_entry, tbl);
15806 acts[i].dv_actions[acts[i].actions_n++] =
15807 tbl_data->jump.action;
15808 if (mtr_policy->act_cnt[i].modify_hdr)
15809 match_src_port = !!transfer;
15812 /*Queue action do nothing*/
15817 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
15818 egress, transfer, match_src_port, acts)) {
15820 "Failed to create policy rules per domain.");
15826 mlx5_flow_meter_detach(priv, next_fm);
15831 * Create the policy rules.
15834 * Pointer to Ethernet device.
15835 * @param[in,out] mtr_policy
15836 * Pointer to meter policy table.
15839 * 0 on success, -1 otherwise.
15842 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
15843 struct mlx5_flow_meter_policy *mtr_policy)
15846 uint16_t sub_policy_num;
15848 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15849 sub_policy_num = (mtr_policy->sub_policy_num >>
15850 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15851 MLX5_MTR_SUB_POLICY_NUM_MASK;
15852 if (!sub_policy_num)
15854 /* Prepare actions list and create policy rules. */
15855 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
15856 mtr_policy->sub_policys[i][0], i)) {
15858 "Failed to create policy action list per domain.");
15866 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
15868 struct mlx5_priv *priv = dev->data->dev_private;
15869 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15870 struct mlx5_flow_meter_def_policy *def_policy;
15871 struct mlx5_flow_tbl_resource *jump_tbl;
15872 struct mlx5_flow_tbl_data_entry *tbl_data;
15873 uint8_t egress, transfer;
15874 struct rte_flow_error error;
15875 struct mlx5_meter_policy_acts acts[RTE_COLORS];
15878 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15879 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15880 def_policy = mtrmng->def_policy[domain];
15882 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
15883 sizeof(struct mlx5_flow_meter_def_policy),
15884 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
15886 DRV_LOG(ERR, "Failed to alloc "
15887 "default policy table.");
15888 goto def_policy_error;
15890 mtrmng->def_policy[domain] = def_policy;
15891 /* Create the meter suffix table with SUFFIX level. */
15892 jump_tbl = flow_dv_tbl_resource_get(dev,
15893 MLX5_FLOW_TABLE_LEVEL_METER,
15894 egress, transfer, false, NULL, 0,
15895 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
15898 "Failed to create meter suffix table.");
15899 goto def_policy_error;
15901 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
15902 tbl_data = container_of(jump_tbl,
15903 struct mlx5_flow_tbl_data_entry, tbl);
15904 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
15905 tbl_data->jump.action;
15906 acts[RTE_COLOR_GREEN].dv_actions[0] =
15907 tbl_data->jump.action;
15908 acts[RTE_COLOR_GREEN].actions_n = 1;
15909 /* Create jump action to the drop table. */
15910 if (!mtrmng->drop_tbl[domain]) {
15911 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
15912 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
15913 egress, transfer, false, NULL, 0,
15914 0, MLX5_MTR_TABLE_ID_DROP, &error);
15915 if (!mtrmng->drop_tbl[domain]) {
15916 DRV_LOG(ERR, "Failed to create "
15917 "meter drop table for default policy.");
15918 goto def_policy_error;
15921 tbl_data = container_of(mtrmng->drop_tbl[domain],
15922 struct mlx5_flow_tbl_data_entry, tbl);
15923 def_policy->dr_jump_action[RTE_COLOR_RED] =
15924 tbl_data->jump.action;
15925 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
15926 acts[RTE_COLOR_RED].actions_n = 1;
15927 /* Create default policy rules. */
15928 ret = __flow_dv_create_domain_policy_rules(dev,
15929 &def_policy->sub_policy,
15930 egress, transfer, false, acts);
15932 DRV_LOG(ERR, "Failed to create "
15933 "default policy rules.");
15934 goto def_policy_error;
15939 __flow_dv_destroy_domain_def_policy(dev,
15940 (enum mlx5_meter_domain)domain);
15945 * Create the default policy table set.
15948 * Pointer to Ethernet device.
15950 * 0 on success, -1 otherwise.
15953 flow_dv_create_def_policy(struct rte_eth_dev *dev)
15955 struct mlx5_priv *priv = dev->data->dev_private;
15958 /* Non-termination policy table. */
15959 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15960 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
15962 if (__flow_dv_create_domain_def_policy(dev, i)) {
15964 "Failed to create default policy");
15972 * Create the needed meter tables.
15973 * Lock free, (mutex should be acquired by caller).
15976 * Pointer to Ethernet device.
15978 * Meter information table.
15979 * @param[in] mtr_idx
15981 * @param[in] domain_bitmap
15984 * 0 on success, -1 otherwise.
15987 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
15988 struct mlx5_flow_meter_info *fm,
15990 uint8_t domain_bitmap)
15992 struct mlx5_priv *priv = dev->data->dev_private;
15993 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15994 struct rte_flow_error error;
15995 struct mlx5_flow_tbl_data_entry *tbl_data;
15996 uint8_t egress, transfer;
15997 void *actions[METER_ACTIONS];
15998 int domain, ret, i;
15999 struct mlx5_flow_counter *cnt;
16000 struct mlx5_flow_dv_match_params value = {
16001 .size = sizeof(value.buf) -
16002 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
16004 struct mlx5_flow_dv_match_params matcher_para = {
16005 .size = sizeof(matcher_para.buf) -
16006 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
16008 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16010 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16011 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16012 struct mlx5_cache_entry *entry;
16013 struct mlx5_flow_dv_matcher matcher = {
16015 .size = sizeof(matcher.mask.buf) -
16016 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
16019 struct mlx5_flow_dv_matcher *drop_matcher;
16020 struct mlx5_flow_cb_ctx ctx = {
16025 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16026 rte_errno = ENOTSUP;
16029 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16030 if (!(domain_bitmap & (1 << domain)) ||
16031 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16033 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16034 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16035 /* Create the drop table with METER DROP level. */
16036 if (!mtrmng->drop_tbl[domain]) {
16037 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16038 MLX5_FLOW_TABLE_LEVEL_METER,
16039 egress, transfer, false, NULL, 0,
16040 0, MLX5_MTR_TABLE_ID_DROP, &error);
16041 if (!mtrmng->drop_tbl[domain]) {
16042 DRV_LOG(ERR, "Failed to create meter drop table.");
16046 /* Create default matcher in drop table. */
16047 matcher.tbl = mtrmng->drop_tbl[domain],
16048 tbl_data = container_of(mtrmng->drop_tbl[domain],
16049 struct mlx5_flow_tbl_data_entry, tbl);
16050 if (!mtrmng->def_matcher[domain]) {
16051 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16052 (enum modify_reg)mtr_id_reg_c,
16054 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16055 matcher.crc = rte_raw_cksum
16056 ((const void *)matcher.mask.buf,
16057 matcher.mask.size);
16058 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
16060 DRV_LOG(ERR, "Failed to register meter "
16061 "drop default matcher.");
16064 mtrmng->def_matcher[domain] = container_of(entry,
16065 struct mlx5_flow_dv_matcher, entry);
16067 /* Create default rule in drop table. */
16068 if (!mtrmng->def_rule[domain]) {
16070 actions[i++] = priv->sh->dr_drop_action;
16071 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16072 (enum modify_reg)mtr_id_reg_c, 0, 0);
16073 ret = mlx5_flow_os_create_flow
16074 (mtrmng->def_matcher[domain]->matcher_object,
16075 (void *)&value, i, actions,
16076 &mtrmng->def_rule[domain]);
16078 DRV_LOG(ERR, "Failed to create meter "
16079 "default drop rule for drop table.");
16085 MLX5_ASSERT(mtrmng->max_mtr_bits);
16086 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16087 /* Create matchers for Drop. */
16088 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16089 (enum modify_reg)mtr_id_reg_c, 0,
16090 (mtr_id_mask << mtr_id_offset));
16091 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16092 matcher.crc = rte_raw_cksum
16093 ((const void *)matcher.mask.buf,
16094 matcher.mask.size);
16095 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
16098 "Failed to register meter drop matcher.");
16101 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16102 container_of(entry, struct mlx5_flow_dv_matcher,
16106 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16107 /* Create drop rule, matching meter_id only. */
16108 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16109 (enum modify_reg)mtr_id_reg_c,
16110 (mtr_idx << mtr_id_offset), UINT32_MAX);
16112 cnt = flow_dv_counter_get_by_idx(dev,
16113 fm->drop_cnt, NULL);
16114 actions[i++] = cnt->action;
16115 actions[i++] = priv->sh->dr_drop_action;
16116 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16117 (void *)&value, i, actions,
16118 &fm->drop_rule[domain]);
16120 DRV_LOG(ERR, "Failed to create meter "
16121 "drop rule for drop table.");
16127 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16128 if (fm->drop_rule[i]) {
16129 claim_zero(mlx5_flow_os_destroy_flow
16130 (fm->drop_rule[i]));
16131 fm->drop_rule[i] = NULL;
16137 static struct mlx5_flow_meter_sub_policy *
16138 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16139 struct mlx5_flow_meter_policy *mtr_policy,
16140 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16141 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16144 struct mlx5_priv *priv = dev->data->dev_private;
16145 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16146 uint32_t sub_policy_idx = 0;
16147 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16149 struct mlx5_hrxq *hrxq;
16150 struct mlx5_flow_handle dh;
16151 struct mlx5_meter_policy_action_container *act_cnt;
16152 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16153 uint16_t sub_policy_num;
16155 rte_spinlock_lock(&mtr_policy->sl);
16156 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16159 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16160 if (!hrxq_idx[i]) {
16161 rte_spinlock_unlock(&mtr_policy->sl);
16165 sub_policy_num = (mtr_policy->sub_policy_num >>
16166 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16167 MLX5_MTR_SUB_POLICY_NUM_MASK;
16168 for (i = 0; i < sub_policy_num;
16170 for (j = 0; j < MLX5_MTR_RTE_COLORS; j++) {
16173 mtr_policy->sub_policys[domain][i]->rix_hrxq[j])
16176 if (j >= MLX5_MTR_RTE_COLORS) {
16178 * Found the sub policy table with
16179 * the same queue per color
16181 rte_spinlock_unlock(&mtr_policy->sl);
16182 for (j = 0; j < MLX5_MTR_RTE_COLORS; j++)
16183 mlx5_hrxq_release(dev, hrxq_idx[j]);
16185 return mtr_policy->sub_policys[domain][i];
16188 /* Create sub policy. */
16189 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16190 /* Reuse the first dummy sub_policy*/
16191 sub_policy = mtr_policy->sub_policys[domain][0];
16192 sub_policy_idx = sub_policy->idx;
16194 sub_policy = mlx5_ipool_zmalloc
16195 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16198 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16199 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16200 mlx5_hrxq_release(dev, hrxq_idx[i]);
16201 goto rss_sub_policy_error;
16203 sub_policy->idx = sub_policy_idx;
16204 sub_policy->main_policy = mtr_policy;
16206 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16209 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16210 if (mtr_policy->is_hierarchy) {
16211 act_cnt = &mtr_policy->act_cnt[i];
16212 act_cnt->next_sub_policy = next_sub_policy;
16213 mlx5_hrxq_release(dev, hrxq_idx[i]);
16216 * Overwrite the last action from
16217 * RSS action to Queue action.
16219 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16222 DRV_LOG(ERR, "Failed to create policy hrxq");
16223 goto rss_sub_policy_error;
16225 act_cnt = &mtr_policy->act_cnt[i];
16226 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16227 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16228 if (act_cnt->rix_mark)
16230 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16231 dh.rix_hrxq = hrxq_idx[i];
16232 flow_drv_rxq_flags_set(dev, &dh);
16236 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16237 sub_policy, domain)) {
16238 DRV_LOG(ERR, "Failed to create policy "
16239 "rules per domain.");
16240 goto rss_sub_policy_error;
16242 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16243 i = (mtr_policy->sub_policy_num >>
16244 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16245 MLX5_MTR_SUB_POLICY_NUM_MASK;
16246 mtr_policy->sub_policys[domain][i] = sub_policy;
16248 if (i > MLX5_MTR_RSS_MAX_SUB_POLICY)
16249 goto rss_sub_policy_error;
16250 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16251 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16252 mtr_policy->sub_policy_num |=
16253 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16254 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16256 rte_spinlock_unlock(&mtr_policy->sl);
16259 rss_sub_policy_error:
16261 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16262 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16263 i = (mtr_policy->sub_policy_num >>
16264 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16265 MLX5_MTR_SUB_POLICY_NUM_MASK;
16266 mtr_policy->sub_policys[domain][i] = NULL;
16268 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16272 rte_spinlock_unlock(&mtr_policy->sl);
16277 * Find the policy table for prefix table with RSS.
16280 * Pointer to Ethernet device.
16281 * @param[in] mtr_policy
16282 * Pointer to meter policy table.
16283 * @param[in] rss_desc
16284 * Pointer to rss_desc
16286 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16288 static struct mlx5_flow_meter_sub_policy *
16289 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16290 struct mlx5_flow_meter_policy *mtr_policy,
16291 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16293 struct mlx5_priv *priv = dev->data->dev_private;
16294 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16295 struct mlx5_flow_meter_info *next_fm;
16296 struct mlx5_flow_meter_policy *next_policy;
16297 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16298 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16299 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16300 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16301 bool reuse_sub_policy;
16306 /* Iterate hierarchy to get all policies in this hierarchy. */
16307 policies[i++] = mtr_policy;
16308 if (!mtr_policy->is_hierarchy)
16310 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16311 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16314 next_fm = mlx5_flow_meter_find(priv,
16315 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16317 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16321 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16323 MLX5_ASSERT(next_policy);
16324 mtr_policy = next_policy;
16328 * From last policy to the first one in hierarchy,
16329 * create/get the sub policy for each of them.
16331 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
16335 &reuse_sub_policy);
16337 DRV_LOG(ERR, "Failed to get the sub policy.");
16340 if (!reuse_sub_policy)
16341 sub_policies[j++] = sub_policy;
16342 next_sub_policy = sub_policy;
16347 uint16_t sub_policy_num;
16349 sub_policy = sub_policies[--j];
16350 mtr_policy = sub_policy->main_policy;
16351 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16352 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16353 sub_policy_num = (mtr_policy->sub_policy_num >>
16354 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16355 MLX5_MTR_SUB_POLICY_NUM_MASK;
16356 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
16359 mtr_policy->sub_policy_num &=
16360 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16361 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
16362 mtr_policy->sub_policy_num |=
16363 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16364 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
16365 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16373 * Create the sub policy tag rule for all meters in hierarchy.
16376 * Pointer to Ethernet device.
16378 * Meter information table.
16379 * @param[in] src_port
16380 * The src port this extra rule should use.
16382 * The src port match item.
16383 * @param[out] error
16384 * Perform verbose error reporting if not NULL.
16386 * 0 on success, a negative errno value otherwise and rte_errno is set.
16389 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
16390 struct mlx5_flow_meter_info *fm,
16392 const struct rte_flow_item *item,
16393 struct rte_flow_error *error)
16395 struct mlx5_priv *priv = dev->data->dev_private;
16396 struct mlx5_flow_meter_policy *mtr_policy;
16397 struct mlx5_flow_meter_sub_policy *sub_policy;
16398 struct mlx5_flow_meter_info *next_fm = NULL;
16399 struct mlx5_flow_meter_policy *next_policy;
16400 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16401 struct mlx5_flow_tbl_data_entry *tbl_data;
16402 struct mlx5_sub_policy_color_rule *color_rule;
16403 struct mlx5_meter_policy_acts acts;
16404 uint32_t color_reg_c_idx;
16405 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
16406 struct rte_flow_attr attr = {
16407 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16414 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
16417 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
16418 MLX5_ASSERT(mtr_policy);
16419 if (!mtr_policy->is_hierarchy)
16421 next_fm = mlx5_flow_meter_find(priv,
16422 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16424 return rte_flow_error_set(error, EINVAL,
16425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16426 "Failed to find next meter in hierarchy.");
16428 if (!next_fm->drop_cnt)
16430 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
16431 sub_policy = mtr_policy->sub_policys[domain][0];
16432 for (i = 0; i < RTE_COLORS; i++) {
16433 bool rule_exist = false;
16434 struct mlx5_meter_policy_action_container *act_cnt;
16436 if (i >= RTE_COLOR_YELLOW)
16438 TAILQ_FOREACH(color_rule,
16439 &sub_policy->color_rules[i], next_port)
16440 if (color_rule->src_port == src_port) {
16446 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16447 sizeof(struct mlx5_sub_policy_color_rule),
16450 return rte_flow_error_set(error, ENOMEM,
16451 RTE_FLOW_ERROR_TYPE_ACTION,
16452 NULL, "No memory to create tag color rule.");
16453 color_rule->src_port = src_port;
16455 next_policy = mlx5_flow_meter_policy_find(dev,
16456 next_fm->policy_id, NULL);
16457 MLX5_ASSERT(next_policy);
16458 next_sub_policy = next_policy->sub_policys[domain][0];
16459 tbl_data = container_of(next_sub_policy->tbl_rsc,
16460 struct mlx5_flow_tbl_data_entry, tbl);
16461 act_cnt = &mtr_policy->act_cnt[i];
16463 acts.dv_actions[0] = next_fm->meter_action;
16464 acts.dv_actions[1] = act_cnt->modify_hdr->action;
16466 acts.dv_actions[0] = act_cnt->modify_hdr->action;
16467 acts.dv_actions[1] = next_fm->meter_action;
16469 acts.dv_actions[2] = tbl_data->jump.action;
16470 acts.actions_n = 3;
16471 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
16475 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16476 i, sub_policy, &attr, true, item,
16477 &color_rule->matcher, error)) {
16478 rte_flow_error_set(error, errno,
16479 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16480 "Failed to create hierarchy meter matcher.");
16483 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
16485 color_rule->matcher->matcher_object,
16486 acts.actions_n, acts.dv_actions,
16488 &color_rule->rule, &attr)) {
16489 rte_flow_error_set(error, errno,
16490 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16491 "Failed to create hierarchy meter rule.");
16494 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16495 color_rule, next_port);
16499 * Recursive call to iterate all meters in hierarchy and
16500 * create needed rules.
16502 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
16503 src_port, item, error);
16506 if (color_rule->rule)
16507 mlx5_flow_os_destroy_flow(color_rule->rule);
16508 if (color_rule->matcher) {
16509 struct mlx5_flow_tbl_data_entry *tbl =
16510 container_of(color_rule->matcher->tbl,
16511 typeof(*tbl), tbl);
16512 mlx5_cache_unregister(&tbl->matchers,
16513 &color_rule->matcher->entry);
16515 mlx5_free(color_rule);
16518 mlx5_flow_meter_detach(priv, next_fm);
16523 * Destroy the sub policy table with RX queue.
16526 * Pointer to Ethernet device.
16527 * @param[in] mtr_policy
16528 * Pointer to meter policy table.
16531 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
16532 struct mlx5_flow_meter_policy *mtr_policy)
16534 struct mlx5_priv *priv = dev->data->dev_private;
16535 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16536 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16538 uint16_t sub_policy_num, new_policy_num;
16540 rte_spinlock_lock(&mtr_policy->sl);
16541 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16542 switch (mtr_policy->act_cnt[i].fate_action) {
16543 case MLX5_FLOW_FATE_SHARED_RSS:
16544 sub_policy_num = (mtr_policy->sub_policy_num >>
16545 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16546 MLX5_MTR_SUB_POLICY_NUM_MASK;
16547 new_policy_num = sub_policy_num;
16548 for (j = 0; j < sub_policy_num; j++) {
16550 mtr_policy->sub_policys[domain][j];
16552 __flow_dv_destroy_sub_policy_rules(dev,
16555 mtr_policy->sub_policys[domain][0]) {
16556 mtr_policy->sub_policys[domain][j] =
16559 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16565 if (new_policy_num != sub_policy_num) {
16566 mtr_policy->sub_policy_num &=
16567 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16568 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16569 mtr_policy->sub_policy_num |=
16571 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16572 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16575 case MLX5_FLOW_FATE_QUEUE:
16576 sub_policy = mtr_policy->sub_policys[domain][0];
16577 __flow_dv_destroy_sub_policy_rules(dev,
16581 /*Other actions without queue and do nothing*/
16585 rte_spinlock_unlock(&mtr_policy->sl);
16589 * Validate the batch counter support in root table.
16591 * Create a simple flow with invalid counter and drop action on root table to
16592 * validate if batch counter with offset on root table is supported or not.
16595 * Pointer to rte_eth_dev structure.
16598 * 0 on success, a negative errno value otherwise and rte_errno is set.
16601 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
16603 struct mlx5_priv *priv = dev->data->dev_private;
16604 struct mlx5_dev_ctx_shared *sh = priv->sh;
16605 struct mlx5_flow_dv_match_params mask = {
16606 .size = sizeof(mask.buf),
16608 struct mlx5_flow_dv_match_params value = {
16609 .size = sizeof(value.buf),
16611 struct mlx5dv_flow_matcher_attr dv_attr = {
16612 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
16614 .match_criteria_enable = 0,
16615 .match_mask = (void *)&mask,
16617 void *actions[2] = { 0 };
16618 struct mlx5_flow_tbl_resource *tbl = NULL;
16619 struct mlx5_devx_obj *dcs = NULL;
16620 void *matcher = NULL;
16624 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
16628 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
16631 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
16635 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
16636 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
16640 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
16644 * If batch counter with offset is not supported, the driver will not
16645 * validate the invalid offset value, flow create should success.
16646 * In this case, it means batch counter is not supported in root table.
16648 * Otherwise, if flow create is failed, counter offset is supported.
16651 DRV_LOG(INFO, "Batch counter is not supported in root "
16652 "table. Switch to fallback mode.");
16653 rte_errno = ENOTSUP;
16655 claim_zero(mlx5_flow_os_destroy_flow(flow));
16657 /* Check matcher to make sure validate fail at flow create. */
16658 if (!matcher || (matcher && errno != EINVAL))
16659 DRV_LOG(ERR, "Unexpected error in counter offset "
16660 "support detection");
16664 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
16666 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
16668 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
16670 claim_zero(mlx5_devx_cmd_destroy(dcs));
16675 * Query a devx counter.
16678 * Pointer to the Ethernet device structure.
16680 * Index to the flow counter.
16682 * Set to clear the counter statistics.
16684 * The statistics value of packets.
16685 * @param[out] bytes
16686 * The statistics value of bytes.
16689 * 0 on success, otherwise return -1.
16692 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
16693 uint64_t *pkts, uint64_t *bytes)
16695 struct mlx5_priv *priv = dev->data->dev_private;
16696 struct mlx5_flow_counter *cnt;
16697 uint64_t inn_pkts, inn_bytes;
16700 if (!priv->config.devx)
16703 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
16706 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
16707 *pkts = inn_pkts - cnt->hits;
16708 *bytes = inn_bytes - cnt->bytes;
16710 cnt->hits = inn_pkts;
16711 cnt->bytes = inn_bytes;
16717 * Get aged-out flows.
16720 * Pointer to the Ethernet device structure.
16721 * @param[in] context
16722 * The address of an array of pointers to the aged-out flows contexts.
16723 * @param[in] nb_contexts
16724 * The length of context array pointers.
16725 * @param[out] error
16726 * Perform verbose error reporting if not NULL. Initialized in case of
16730 * how many contexts get in success, otherwise negative errno value.
16731 * if nb_contexts is 0, return the amount of all aged contexts.
16732 * if nb_contexts is not 0 , return the amount of aged flows reported
16733 * in the context array.
16734 * @note: only stub for now
16737 flow_get_aged_flows(struct rte_eth_dev *dev,
16739 uint32_t nb_contexts,
16740 struct rte_flow_error *error)
16742 struct mlx5_priv *priv = dev->data->dev_private;
16743 struct mlx5_age_info *age_info;
16744 struct mlx5_age_param *age_param;
16745 struct mlx5_flow_counter *counter;
16746 struct mlx5_aso_age_action *act;
16749 if (nb_contexts && !context)
16750 return rte_flow_error_set(error, EINVAL,
16751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16752 NULL, "empty context");
16753 age_info = GET_PORT_AGE_INFO(priv);
16754 rte_spinlock_lock(&age_info->aged_sl);
16755 LIST_FOREACH(act, &age_info->aged_aso, next) {
16758 context[nb_flows - 1] =
16759 act->age_params.context;
16760 if (!(--nb_contexts))
16764 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
16767 age_param = MLX5_CNT_TO_AGE(counter);
16768 context[nb_flows - 1] = age_param->context;
16769 if (!(--nb_contexts))
16773 rte_spinlock_unlock(&age_info->aged_sl);
16774 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
16779 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
16782 flow_dv_counter_allocate(struct rte_eth_dev *dev)
16784 return flow_dv_counter_alloc(dev, 0);
16788 * Validate indirect action.
16789 * Dispatcher for action type specific validation.
16792 * Pointer to the Ethernet device structure.
16794 * Indirect action configuration.
16795 * @param[in] action
16796 * The indirect action object to validate.
16797 * @param[out] error
16798 * Perform verbose error reporting if not NULL. Initialized in case of
16802 * 0 on success, otherwise negative errno value.
16805 flow_dv_action_validate(struct rte_eth_dev *dev,
16806 const struct rte_flow_indir_action_conf *conf,
16807 const struct rte_flow_action *action,
16808 struct rte_flow_error *err)
16810 struct mlx5_priv *priv = dev->data->dev_private;
16812 RTE_SET_USED(conf);
16813 switch (action->type) {
16814 case RTE_FLOW_ACTION_TYPE_RSS:
16816 * priv->obj_ops is set according to driver capabilities.
16817 * When DevX capabilities are
16818 * sufficient, it is set to devx_obj_ops.
16819 * Otherwise, it is set to ibv_obj_ops.
16820 * ibv_obj_ops doesn't support ind_table_modify operation.
16821 * In this case the indirect RSS action can't be used.
16823 if (priv->obj_ops.ind_table_modify == NULL)
16824 return rte_flow_error_set
16826 RTE_FLOW_ERROR_TYPE_ACTION,
16828 "Indirect RSS action not supported");
16829 return mlx5_validate_action_rss(dev, action, err);
16830 case RTE_FLOW_ACTION_TYPE_AGE:
16831 if (!priv->sh->aso_age_mng)
16832 return rte_flow_error_set(err, ENOTSUP,
16833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16835 "Indirect age action not supported");
16836 return flow_dv_validate_action_age(0, action, dev, err);
16837 case RTE_FLOW_ACTION_TYPE_COUNT:
16839 * There are two mechanisms to share the action count.
16840 * The old mechanism uses the shared field to share, while the
16841 * new mechanism uses the indirect action API.
16842 * This validation comes to make sure that the two mechanisms
16843 * are not combined.
16845 if (is_shared_action_count(action))
16846 return rte_flow_error_set(err, ENOTSUP,
16847 RTE_FLOW_ERROR_TYPE_ACTION,
16849 "Mix shared and indirect counter is not supported");
16850 return flow_dv_validate_action_count(dev, true, 0, err);
16851 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
16852 if (!priv->sh->ct_aso_en)
16853 return rte_flow_error_set(err, ENOTSUP,
16854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16855 "ASO CT is not supported");
16856 return mlx5_validate_action_ct(dev, action->conf, err);
16858 return rte_flow_error_set(err, ENOTSUP,
16859 RTE_FLOW_ERROR_TYPE_ACTION,
16861 "action type not supported");
16866 * Validate meter policy actions.
16867 * Dispatcher for action type specific validation.
16870 * Pointer to the Ethernet device structure.
16871 * @param[in] action
16872 * The meter policy action object to validate.
16874 * Attributes of flow to determine steering domain.
16875 * @param[out] error
16876 * Perform verbose error reporting if not NULL. Initialized in case of
16880 * 0 on success, otherwise negative errno value.
16883 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
16884 const struct rte_flow_action *actions[RTE_COLORS],
16885 struct rte_flow_attr *attr,
16887 uint8_t *domain_bitmap,
16888 bool *is_def_policy,
16889 struct rte_mtr_error *error)
16891 struct mlx5_priv *priv = dev->data->dev_private;
16892 struct mlx5_dev_config *dev_conf = &priv->config;
16893 const struct rte_flow_action *act;
16894 uint64_t action_flags = 0;
16897 struct rte_flow_error flow_err;
16898 uint8_t domain_color[RTE_COLORS] = {0};
16899 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
16901 if (!priv->config.dv_esw_en)
16902 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
16903 *domain_bitmap = def_domain;
16904 if (actions[RTE_COLOR_YELLOW] &&
16905 actions[RTE_COLOR_YELLOW]->type != RTE_FLOW_ACTION_TYPE_END)
16906 return -rte_mtr_error_set(error, ENOTSUP,
16907 RTE_MTR_ERROR_TYPE_METER_POLICY,
16909 "Yellow color does not support any action.");
16910 if (actions[RTE_COLOR_YELLOW] &&
16911 actions[RTE_COLOR_YELLOW]->type != RTE_FLOW_ACTION_TYPE_DROP)
16912 return -rte_mtr_error_set(error, ENOTSUP,
16913 RTE_MTR_ERROR_TYPE_METER_POLICY,
16914 NULL, "Red color only supports drop action.");
16916 * Check default policy actions:
16917 * Green/Yellow: no action, Red: drop action
16919 if ((!actions[RTE_COLOR_GREEN] ||
16920 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)) {
16921 *is_def_policy = true;
16924 flow_err.message = NULL;
16925 for (i = 0; i < RTE_COLORS; i++) {
16927 for (action_flags = 0, actions_n = 0;
16928 act && act->type != RTE_FLOW_ACTION_TYPE_END;
16930 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
16931 return -rte_mtr_error_set(error, ENOTSUP,
16932 RTE_MTR_ERROR_TYPE_METER_POLICY,
16933 NULL, "too many actions");
16934 switch (act->type) {
16935 case RTE_FLOW_ACTION_TYPE_PORT_ID:
16936 if (!priv->config.dv_esw_en)
16937 return -rte_mtr_error_set(error,
16939 RTE_MTR_ERROR_TYPE_METER_POLICY,
16940 NULL, "PORT action validate check"
16941 " fail for ESW disable");
16942 ret = flow_dv_validate_action_port_id(dev,
16944 act, attr, &flow_err);
16946 return -rte_mtr_error_set(error,
16948 RTE_MTR_ERROR_TYPE_METER_POLICY,
16949 NULL, flow_err.message ?
16951 "PORT action validate check fail");
16953 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
16955 case RTE_FLOW_ACTION_TYPE_MARK:
16956 ret = flow_dv_validate_action_mark(dev, act,
16960 return -rte_mtr_error_set(error,
16962 RTE_MTR_ERROR_TYPE_METER_POLICY,
16963 NULL, flow_err.message ?
16965 "Mark action validate check fail");
16966 if (dev_conf->dv_xmeta_en !=
16967 MLX5_XMETA_MODE_LEGACY)
16968 return -rte_mtr_error_set(error,
16970 RTE_MTR_ERROR_TYPE_METER_POLICY,
16971 NULL, "Extend MARK action is "
16972 "not supported. Please try use "
16973 "default policy for meter.");
16974 action_flags |= MLX5_FLOW_ACTION_MARK;
16977 case RTE_FLOW_ACTION_TYPE_SET_TAG:
16978 ret = flow_dv_validate_action_set_tag(dev,
16982 return -rte_mtr_error_set(error,
16984 RTE_MTR_ERROR_TYPE_METER_POLICY,
16985 NULL, flow_err.message ?
16987 "Set tag action validate check fail");
16989 * Count all modify-header actions
16992 if (!(action_flags &
16993 MLX5_FLOW_MODIFY_HDR_ACTIONS))
16995 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
16997 case RTE_FLOW_ACTION_TYPE_DROP:
16998 ret = mlx5_flow_validate_action_drop
17002 return -rte_mtr_error_set(error,
17004 RTE_MTR_ERROR_TYPE_METER_POLICY,
17005 NULL, flow_err.message ?
17007 "Drop action validate check fail");
17008 action_flags |= MLX5_FLOW_ACTION_DROP;
17011 case RTE_FLOW_ACTION_TYPE_QUEUE:
17013 * Check whether extensive
17014 * metadata feature is engaged.
17016 if (dev_conf->dv_flow_en &&
17017 (dev_conf->dv_xmeta_en !=
17018 MLX5_XMETA_MODE_LEGACY) &&
17019 mlx5_flow_ext_mreg_supported(dev))
17020 return -rte_mtr_error_set(error,
17022 RTE_MTR_ERROR_TYPE_METER_POLICY,
17023 NULL, "Queue action with meta "
17024 "is not supported. Please try use "
17025 "default policy for meter.");
17026 ret = mlx5_flow_validate_action_queue(act,
17030 return -rte_mtr_error_set(error,
17032 RTE_MTR_ERROR_TYPE_METER_POLICY,
17033 NULL, flow_err.message ?
17035 "Queue action validate check fail");
17036 action_flags |= MLX5_FLOW_ACTION_QUEUE;
17039 case RTE_FLOW_ACTION_TYPE_RSS:
17040 if (dev_conf->dv_flow_en &&
17041 (dev_conf->dv_xmeta_en !=
17042 MLX5_XMETA_MODE_LEGACY) &&
17043 mlx5_flow_ext_mreg_supported(dev))
17044 return -rte_mtr_error_set(error,
17046 RTE_MTR_ERROR_TYPE_METER_POLICY,
17047 NULL, "RSS action with meta "
17048 "is not supported. Please try use "
17049 "default policy for meter.");
17050 ret = mlx5_validate_action_rss(dev, act,
17053 return -rte_mtr_error_set(error,
17055 RTE_MTR_ERROR_TYPE_METER_POLICY,
17056 NULL, flow_err.message ?
17058 "RSS action validate check fail");
17059 action_flags |= MLX5_FLOW_ACTION_RSS;
17063 case RTE_FLOW_ACTION_TYPE_JUMP:
17064 ret = flow_dv_validate_action_jump(dev,
17065 NULL, act, action_flags,
17066 attr, true, &flow_err);
17068 return -rte_mtr_error_set(error,
17070 RTE_MTR_ERROR_TYPE_METER_POLICY,
17071 NULL, flow_err.message ?
17073 "Jump action validate check fail");
17075 action_flags |= MLX5_FLOW_ACTION_JUMP;
17078 return -rte_mtr_error_set(error, ENOTSUP,
17079 RTE_MTR_ERROR_TYPE_METER_POLICY,
17081 "Doesn't support optional action");
17084 /* Yellow is not supported, just skip. */
17085 if (i == RTE_COLOR_YELLOW)
17087 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
17088 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17089 else if ((action_flags &
17090 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17091 (action_flags & MLX5_FLOW_ACTION_MARK))
17093 * Only support MLX5_XMETA_MODE_LEGACY
17094 * so MARK action only in ingress domain.
17096 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17098 domain_color[i] = def_domain;
17100 * Validate the drop action mutual exclusion
17101 * with other actions. Drop action is mutually-exclusive
17102 * with any other action, except for Count action.
17104 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
17105 (action_flags & ~MLX5_FLOW_ACTION_DROP)) {
17106 return -rte_mtr_error_set(error, ENOTSUP,
17107 RTE_MTR_ERROR_TYPE_METER_POLICY,
17108 NULL, "Drop action is mutually-exclusive "
17109 "with any other action");
17111 /* Eswitch has few restrictions on using items and actions */
17112 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
17113 if (!mlx5_flow_ext_mreg_supported(dev) &&
17114 action_flags & MLX5_FLOW_ACTION_MARK)
17115 return -rte_mtr_error_set(error, ENOTSUP,
17116 RTE_MTR_ERROR_TYPE_METER_POLICY,
17117 NULL, "unsupported action MARK");
17118 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
17119 return -rte_mtr_error_set(error, ENOTSUP,
17120 RTE_MTR_ERROR_TYPE_METER_POLICY,
17121 NULL, "unsupported action QUEUE");
17122 if (action_flags & MLX5_FLOW_ACTION_RSS)
17123 return -rte_mtr_error_set(error, ENOTSUP,
17124 RTE_MTR_ERROR_TYPE_METER_POLICY,
17125 NULL, "unsupported action RSS");
17126 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17127 return -rte_mtr_error_set(error, ENOTSUP,
17128 RTE_MTR_ERROR_TYPE_METER_POLICY,
17129 NULL, "no fate action is found");
17131 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) &&
17133 MLX5_MTR_DOMAIN_INGRESS_BIT)) {
17134 if ((domain_color[i] &
17135 MLX5_MTR_DOMAIN_EGRESS_BIT))
17137 MLX5_MTR_DOMAIN_EGRESS_BIT;
17139 return -rte_mtr_error_set(error,
17141 RTE_MTR_ERROR_TYPE_METER_POLICY,
17142 NULL, "no fate action is found");
17145 if (domain_color[i] != def_domain)
17146 *domain_bitmap = domain_color[i];
17152 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
17154 struct mlx5_priv *priv = dev->data->dev_private;
17157 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
17158 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
17163 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
17164 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
17168 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
17169 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
17176 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
17177 .validate = flow_dv_validate,
17178 .prepare = flow_dv_prepare,
17179 .translate = flow_dv_translate,
17180 .apply = flow_dv_apply,
17181 .remove = flow_dv_remove,
17182 .destroy = flow_dv_destroy,
17183 .query = flow_dv_query,
17184 .create_mtr_tbls = flow_dv_create_mtr_tbls,
17185 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
17186 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
17187 .create_meter = flow_dv_mtr_alloc,
17188 .free_meter = flow_dv_aso_mtr_release_to_pool,
17189 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
17190 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
17191 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
17192 .create_policy_rules = flow_dv_create_policy_rules,
17193 .destroy_policy_rules = flow_dv_destroy_policy_rules,
17194 .create_def_policy = flow_dv_create_def_policy,
17195 .destroy_def_policy = flow_dv_destroy_def_policy,
17196 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
17197 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
17198 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
17199 .counter_alloc = flow_dv_counter_allocate,
17200 .counter_free = flow_dv_counter_free,
17201 .counter_query = flow_dv_counter_query,
17202 .get_aged_flows = flow_get_aged_flows,
17203 .action_validate = flow_dv_action_validate,
17204 .action_create = flow_dv_action_create,
17205 .action_destroy = flow_dv_action_destroy,
17206 .action_update = flow_dv_action_update,
17207 .action_query = flow_dv_action_query,
17208 .sync_domain = flow_dv_sync_domain,
17211 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */