1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
101 if (priv->pci_dev == NULL)
103 switch (priv->pci_dev->id.device_id) {
104 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
105 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
106 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
107 return (int16_t)0xfffe;
114 * Initialize flow attributes structure according to flow items' types.
116 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
117 * mode. For tunnel mode, the items to be modified are the outermost ones.
120 * Pointer to item specification.
122 * Pointer to flow attributes structure.
123 * @param[in] dev_flow
124 * Pointer to the sub flow.
125 * @param[in] tunnel_decap
126 * Whether action is after tunnel decapsulation.
129 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
130 struct mlx5_flow *dev_flow, bool tunnel_decap)
132 uint64_t layers = dev_flow->handle->layers;
135 * If layers is already initialized, it means this dev_flow is the
136 * suffix flow, the layers flags is set by the prefix flow. Need to
137 * use the layer flags from prefix flow as the suffix flow may not
138 * have the user defined items as the flow is split.
141 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
143 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
145 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
153 uint8_t next_protocol = 0xff;
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_GRE:
156 case RTE_FLOW_ITEM_TYPE_NVGRE:
157 case RTE_FLOW_ITEM_TYPE_VXLAN:
158 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
159 case RTE_FLOW_ITEM_TYPE_GENEVE:
160 case RTE_FLOW_ITEM_TYPE_MPLS:
164 case RTE_FLOW_ITEM_TYPE_IPV4:
167 if (item->mask != NULL &&
168 ((const struct rte_flow_item_ipv4 *)
169 item->mask)->hdr.next_proto_id)
171 ((const struct rte_flow_item_ipv4 *)
172 (item->spec))->hdr.next_proto_id &
173 ((const struct rte_flow_item_ipv4 *)
174 (item->mask))->hdr.next_proto_id;
175 if ((next_protocol == IPPROTO_IPIP ||
176 next_protocol == IPPROTO_IPV6) && tunnel_decap)
179 case RTE_FLOW_ITEM_TYPE_IPV6:
182 if (item->mask != NULL &&
183 ((const struct rte_flow_item_ipv6 *)
184 item->mask)->hdr.proto)
186 ((const struct rte_flow_item_ipv6 *)
187 (item->spec))->hdr.proto &
188 ((const struct rte_flow_item_ipv6 *)
189 (item->mask))->hdr.proto;
190 if ((next_protocol == IPPROTO_IPIP ||
191 next_protocol == IPPROTO_IPV6) && tunnel_decap)
194 case RTE_FLOW_ITEM_TYPE_UDP:
198 case RTE_FLOW_ITEM_TYPE_TCP:
210 * Convert rte_mtr_color to mlx5 color.
219 rte_col_2_mlx5_col(enum rte_color rcol)
222 case RTE_COLOR_GREEN:
223 return MLX5_FLOW_COLOR_GREEN;
224 case RTE_COLOR_YELLOW:
225 return MLX5_FLOW_COLOR_YELLOW;
227 return MLX5_FLOW_COLOR_RED;
231 return MLX5_FLOW_COLOR_UNDEFINED;
234 struct field_modify_info {
235 uint32_t size; /* Size of field in protocol header, in bytes. */
236 uint32_t offset; /* Offset of field in protocol header, in bytes. */
237 enum mlx5_modification_field id;
240 struct field_modify_info modify_eth[] = {
241 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
242 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
243 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
244 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
248 struct field_modify_info modify_vlan_out_first_vid[] = {
249 /* Size in bits !!! */
250 {12, 0, MLX5_MODI_OUT_FIRST_VID},
254 struct field_modify_info modify_ipv4[] = {
255 {1, 1, MLX5_MODI_OUT_IP_DSCP},
256 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
257 {4, 12, MLX5_MODI_OUT_SIPV4},
258 {4, 16, MLX5_MODI_OUT_DIPV4},
262 struct field_modify_info modify_ipv6[] = {
263 {1, 0, MLX5_MODI_OUT_IP_DSCP},
264 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
265 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
266 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
267 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
268 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
269 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
270 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
271 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
272 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
276 struct field_modify_info modify_udp[] = {
277 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
278 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
282 struct field_modify_info modify_tcp[] = {
283 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
284 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
285 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
286 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
291 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
292 uint8_t next_protocol, uint64_t *item_flags,
295 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
296 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
297 if (next_protocol == IPPROTO_IPIP) {
298 *item_flags |= MLX5_FLOW_LAYER_IPIP;
301 if (next_protocol == IPPROTO_IPV6) {
302 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
307 static inline struct mlx5_hlist *
308 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
309 const char *name, uint32_t size, bool direct_key,
310 bool lcores_share, void *ctx,
311 mlx5_list_create_cb cb_create,
312 mlx5_list_match_cb cb_match,
313 mlx5_list_remove_cb cb_remove,
314 mlx5_list_clone_cb cb_clone,
315 mlx5_list_clone_free_cb cb_clone_free)
317 struct mlx5_hlist *hl;
318 struct mlx5_hlist *expected = NULL;
319 char s[MLX5_NAME_SIZE];
321 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
324 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
325 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
326 ctx, cb_create, cb_match, cb_remove, cb_clone,
329 DRV_LOG(ERR, "%s hash creation failed", name);
333 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
336 mlx5_hlist_destroy(hl);
337 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
342 /* Update VLAN's VID/PCP based on input rte_flow_action.
345 * Pointer to struct rte_flow_action.
347 * Pointer to struct rte_vlan_hdr.
350 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
351 struct rte_vlan_hdr *vlan)
354 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
356 ((const struct rte_flow_action_of_set_vlan_pcp *)
357 action->conf)->vlan_pcp;
358 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
359 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
360 vlan->vlan_tci |= vlan_tci;
361 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
362 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
363 vlan->vlan_tci |= rte_be_to_cpu_16
364 (((const struct rte_flow_action_of_set_vlan_vid *)
365 action->conf)->vlan_vid);
370 * Fetch 1, 2, 3 or 4 byte field from the byte array
371 * and return as unsigned integer in host-endian format.
374 * Pointer to data array.
376 * Size of field to extract.
379 * converted field in host endian format.
381 static inline uint32_t
382 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
391 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
394 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
395 ret = (ret << 8) | *(data + sizeof(uint16_t));
398 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
409 * Convert modify-header action to DV specification.
411 * Data length of each action is determined by provided field description
412 * and the item mask. Data bit offset and width of each action is determined
413 * by provided item mask.
416 * Pointer to item specification.
418 * Pointer to field modification information.
419 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
420 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
421 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
423 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
424 * Negative offset value sets the same offset as source offset.
425 * size field is ignored, value is taken from source field.
426 * @param[in,out] resource
427 * Pointer to the modify-header resource.
429 * Type of modification.
431 * Pointer to the error structure.
434 * 0 on success, a negative errno value otherwise and rte_errno is set.
437 flow_dv_convert_modify_action(struct rte_flow_item *item,
438 struct field_modify_info *field,
439 struct field_modify_info *dcopy,
440 struct mlx5_flow_dv_modify_hdr_resource *resource,
441 uint32_t type, struct rte_flow_error *error)
443 uint32_t i = resource->actions_num;
444 struct mlx5_modification_cmd *actions = resource->actions;
445 uint32_t carry_b = 0;
448 * The item and mask are provided in big-endian format.
449 * The fields should be presented as in big-endian format either.
450 * Mask must be always present, it defines the actual field width.
452 MLX5_ASSERT(item->mask);
453 MLX5_ASSERT(field->size);
459 bool next_field = true;
460 bool next_dcopy = true;
462 if (i >= MLX5_MAX_MODIFY_NUM)
463 return rte_flow_error_set(error, EINVAL,
464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
465 "too many items to modify");
466 /* Fetch variable byte size mask from the array. */
467 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
468 field->offset, field->size);
473 /* Deduce actual data width in bits from mask value. */
474 off_b = rte_bsf32(mask) + carry_b;
475 size_b = sizeof(uint32_t) * CHAR_BIT -
476 off_b - __builtin_clz(mask);
478 actions[i] = (struct mlx5_modification_cmd) {
482 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
485 if (type == MLX5_MODIFICATION_TYPE_COPY) {
487 actions[i].dst_field = dcopy->id;
488 actions[i].dst_offset =
489 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
490 /* Convert entire record to big-endian format. */
491 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
493 * Destination field overflow. Copy leftovers of
494 * a source field to the next destination field.
497 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
500 dcopy->size * CHAR_BIT - dcopy->offset;
501 carry_b = actions[i].length;
505 * Not enough bits in a source filed to fill a
506 * destination field. Switch to the next source.
508 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
509 (size_b == field->size * CHAR_BIT - off_b)) {
511 field->size * CHAR_BIT - off_b;
512 dcopy->offset += actions[i].length;
518 MLX5_ASSERT(item->spec);
519 data = flow_dv_fetch_field((const uint8_t *)item->spec +
520 field->offset, field->size);
521 /* Shift out the trailing masked bits from data. */
522 data = (data & mask) >> off_b;
523 actions[i].data1 = rte_cpu_to_be_32(data);
525 /* Convert entire record to expected big-endian format. */
526 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
530 } while (field->size);
531 if (resource->actions_num == i)
532 return rte_flow_error_set(error, EINVAL,
533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
534 "invalid modification flow item");
535 resource->actions_num = i;
540 * Convert modify-header set IPv4 address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_ipv4
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_ipv4 *conf =
559 (const struct rte_flow_action_set_ipv4 *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
561 struct rte_flow_item_ipv4 ipv4;
562 struct rte_flow_item_ipv4 ipv4_mask;
564 memset(&ipv4, 0, sizeof(ipv4));
565 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
567 ipv4.hdr.src_addr = conf->ipv4_addr;
568 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
570 ipv4.hdr.dst_addr = conf->ipv4_addr;
571 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
574 item.mask = &ipv4_mask;
575 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
576 MLX5_MODIFICATION_TYPE_SET, error);
580 * Convert modify-header set IPv6 address action to DV specification.
582 * @param[in,out] resource
583 * Pointer to the modify-header resource.
585 * Pointer to action specification.
587 * Pointer to the error structure.
590 * 0 on success, a negative errno value otherwise and rte_errno is set.
593 flow_dv_convert_action_modify_ipv6
594 (struct mlx5_flow_dv_modify_hdr_resource *resource,
595 const struct rte_flow_action *action,
596 struct rte_flow_error *error)
598 const struct rte_flow_action_set_ipv6 *conf =
599 (const struct rte_flow_action_set_ipv6 *)(action->conf);
600 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
601 struct rte_flow_item_ipv6 ipv6;
602 struct rte_flow_item_ipv6 ipv6_mask;
604 memset(&ipv6, 0, sizeof(ipv6));
605 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
606 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
607 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
608 sizeof(ipv6.hdr.src_addr));
609 memcpy(&ipv6_mask.hdr.src_addr,
610 &rte_flow_item_ipv6_mask.hdr.src_addr,
611 sizeof(ipv6.hdr.src_addr));
613 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
614 sizeof(ipv6.hdr.dst_addr));
615 memcpy(&ipv6_mask.hdr.dst_addr,
616 &rte_flow_item_ipv6_mask.hdr.dst_addr,
617 sizeof(ipv6.hdr.dst_addr));
620 item.mask = &ipv6_mask;
621 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
622 MLX5_MODIFICATION_TYPE_SET, error);
626 * Convert modify-header set MAC address action to DV specification.
628 * @param[in,out] resource
629 * Pointer to the modify-header resource.
631 * Pointer to action specification.
633 * Pointer to the error structure.
636 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 flow_dv_convert_action_modify_mac
640 (struct mlx5_flow_dv_modify_hdr_resource *resource,
641 const struct rte_flow_action *action,
642 struct rte_flow_error *error)
644 const struct rte_flow_action_set_mac *conf =
645 (const struct rte_flow_action_set_mac *)(action->conf);
646 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
647 struct rte_flow_item_eth eth;
648 struct rte_flow_item_eth eth_mask;
650 memset(ð, 0, sizeof(eth));
651 memset(ð_mask, 0, sizeof(eth_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
653 memcpy(ð.src.addr_bytes, &conf->mac_addr,
654 sizeof(eth.src.addr_bytes));
655 memcpy(ð_mask.src.addr_bytes,
656 &rte_flow_item_eth_mask.src.addr_bytes,
657 sizeof(eth_mask.src.addr_bytes));
659 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
660 sizeof(eth.dst.addr_bytes));
661 memcpy(ð_mask.dst.addr_bytes,
662 &rte_flow_item_eth_mask.dst.addr_bytes,
663 sizeof(eth_mask.dst.addr_bytes));
666 item.mask = ð_mask;
667 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
668 MLX5_MODIFICATION_TYPE_SET, error);
672 * Convert modify-header set VLAN VID action to DV specification.
674 * @param[in,out] resource
675 * Pointer to the modify-header resource.
677 * Pointer to action specification.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_vlan_vid
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 struct rte_flow_error *error)
690 const struct rte_flow_action_of_set_vlan_vid *conf =
691 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
692 int i = resource->actions_num;
693 struct mlx5_modification_cmd *actions = resource->actions;
694 struct field_modify_info *field = modify_vlan_out_first_vid;
696 if (i >= MLX5_MAX_MODIFY_NUM)
697 return rte_flow_error_set(error, EINVAL,
698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
699 "too many items to modify");
700 actions[i] = (struct mlx5_modification_cmd) {
701 .action_type = MLX5_MODIFICATION_TYPE_SET,
703 .length = field->size,
704 .offset = field->offset,
706 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
707 actions[i].data1 = conf->vlan_vid;
708 actions[i].data1 = actions[i].data1 << 16;
709 resource->actions_num = ++i;
714 * Convert modify-header set TP action to DV specification.
716 * @param[in,out] resource
717 * Pointer to the modify-header resource.
719 * Pointer to action specification.
721 * Pointer to rte_flow_item objects list.
723 * Pointer to flow attributes structure.
724 * @param[in] dev_flow
725 * Pointer to the sub flow.
726 * @param[in] tunnel_decap
727 * Whether action is after tunnel decapsulation.
729 * Pointer to the error structure.
732 * 0 on success, a negative errno value otherwise and rte_errno is set.
735 flow_dv_convert_action_modify_tp
736 (struct mlx5_flow_dv_modify_hdr_resource *resource,
737 const struct rte_flow_action *action,
738 const struct rte_flow_item *items,
739 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
740 bool tunnel_decap, struct rte_flow_error *error)
742 const struct rte_flow_action_set_tp *conf =
743 (const struct rte_flow_action_set_tp *)(action->conf);
744 struct rte_flow_item item;
745 struct rte_flow_item_udp udp;
746 struct rte_flow_item_udp udp_mask;
747 struct rte_flow_item_tcp tcp;
748 struct rte_flow_item_tcp tcp_mask;
749 struct field_modify_info *field;
752 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
754 memset(&udp, 0, sizeof(udp));
755 memset(&udp_mask, 0, sizeof(udp_mask));
756 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
757 udp.hdr.src_port = conf->port;
758 udp_mask.hdr.src_port =
759 rte_flow_item_udp_mask.hdr.src_port;
761 udp.hdr.dst_port = conf->port;
762 udp_mask.hdr.dst_port =
763 rte_flow_item_udp_mask.hdr.dst_port;
765 item.type = RTE_FLOW_ITEM_TYPE_UDP;
767 item.mask = &udp_mask;
770 MLX5_ASSERT(attr->tcp);
771 memset(&tcp, 0, sizeof(tcp));
772 memset(&tcp_mask, 0, sizeof(tcp_mask));
773 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
774 tcp.hdr.src_port = conf->port;
775 tcp_mask.hdr.src_port =
776 rte_flow_item_tcp_mask.hdr.src_port;
778 tcp.hdr.dst_port = conf->port;
779 tcp_mask.hdr.dst_port =
780 rte_flow_item_tcp_mask.hdr.dst_port;
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header set TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_action *action,
816 const struct rte_flow_item *items,
817 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
818 bool tunnel_decap, struct rte_flow_error *error)
820 const struct rte_flow_action_set_ttl *conf =
821 (const struct rte_flow_action_set_ttl *)(action->conf);
822 struct rte_flow_item item;
823 struct rte_flow_item_ipv4 ipv4;
824 struct rte_flow_item_ipv4 ipv4_mask;
825 struct rte_flow_item_ipv6 ipv6;
826 struct rte_flow_item_ipv6 ipv6_mask;
827 struct field_modify_info *field;
830 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
832 memset(&ipv4, 0, sizeof(ipv4));
833 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
834 ipv4.hdr.time_to_live = conf->ttl_value;
835 ipv4_mask.hdr.time_to_live = 0xFF;
836 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
838 item.mask = &ipv4_mask;
841 MLX5_ASSERT(attr->ipv6);
842 memset(&ipv6, 0, sizeof(ipv6));
843 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
844 ipv6.hdr.hop_limits = conf->ttl_value;
845 ipv6_mask.hdr.hop_limits = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
848 item.mask = &ipv6_mask;
851 return flow_dv_convert_modify_action(&item, field, NULL, resource,
852 MLX5_MODIFICATION_TYPE_SET, error);
856 * Convert modify-header decrement TTL action to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to rte_flow_item objects list.
865 * Pointer to flow attributes structure.
866 * @param[in] dev_flow
867 * Pointer to the sub flow.
868 * @param[in] tunnel_decap
869 * Whether action is after tunnel decapsulation.
871 * Pointer to the error structure.
874 * 0 on success, a negative errno value otherwise and rte_errno is set.
877 flow_dv_convert_action_modify_dec_ttl
878 (struct mlx5_flow_dv_modify_hdr_resource *resource,
879 const struct rte_flow_item *items,
880 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
881 bool tunnel_decap, struct rte_flow_error *error)
883 struct rte_flow_item item;
884 struct rte_flow_item_ipv4 ipv4;
885 struct rte_flow_item_ipv4 ipv4_mask;
886 struct rte_flow_item_ipv6 ipv6;
887 struct rte_flow_item_ipv6 ipv6_mask;
888 struct field_modify_info *field;
891 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
893 memset(&ipv4, 0, sizeof(ipv4));
894 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
895 ipv4.hdr.time_to_live = 0xFF;
896 ipv4_mask.hdr.time_to_live = 0xFF;
897 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
899 item.mask = &ipv4_mask;
902 MLX5_ASSERT(attr->ipv6);
903 memset(&ipv6, 0, sizeof(ipv6));
904 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
905 ipv6.hdr.hop_limits = 0xFF;
906 ipv6_mask.hdr.hop_limits = 0xFF;
907 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
909 item.mask = &ipv6_mask;
912 return flow_dv_convert_modify_action(&item, field, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
917 * Convert modify-header increment/decrement TCP Sequence number
918 * to DV specification.
920 * @param[in,out] resource
921 * Pointer to the modify-header resource.
923 * Pointer to action specification.
925 * Pointer to the error structure.
928 * 0 on success, a negative errno value otherwise and rte_errno is set.
931 flow_dv_convert_action_modify_tcp_seq
932 (struct mlx5_flow_dv_modify_hdr_resource *resource,
933 const struct rte_flow_action *action,
934 struct rte_flow_error *error)
936 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
937 uint64_t value = rte_be_to_cpu_32(*conf);
938 struct rte_flow_item item;
939 struct rte_flow_item_tcp tcp;
940 struct rte_flow_item_tcp tcp_mask;
942 memset(&tcp, 0, sizeof(tcp));
943 memset(&tcp_mask, 0, sizeof(tcp_mask));
944 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
946 * The HW has no decrement operation, only increment operation.
947 * To simulate decrement X from Y using increment operation
948 * we need to add UINT32_MAX X times to Y.
949 * Each adding of UINT32_MAX decrements Y by 1.
952 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
953 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
954 item.type = RTE_FLOW_ITEM_TYPE_TCP;
956 item.mask = &tcp_mask;
957 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
958 MLX5_MODIFICATION_TYPE_ADD, error);
962 * Convert modify-header increment/decrement TCP Acknowledgment number
963 * to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_modify_tcp_ack
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
982 uint64_t value = rte_be_to_cpu_32(*conf);
983 struct rte_flow_item item;
984 struct rte_flow_item_tcp tcp;
985 struct rte_flow_item_tcp tcp_mask;
987 memset(&tcp, 0, sizeof(tcp));
988 memset(&tcp_mask, 0, sizeof(tcp_mask));
989 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
991 * The HW has no decrement operation, only increment operation.
992 * To simulate decrement X from Y using increment operation
993 * we need to add UINT32_MAX X times to Y.
994 * Each adding of UINT32_MAX decrements Y by 1.
997 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
998 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
999 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1001 item.mask = &tcp_mask;
1002 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1003 MLX5_MODIFICATION_TYPE_ADD, error);
1006 static enum mlx5_modification_field reg_to_field[] = {
1007 [REG_NON] = MLX5_MODI_OUT_NONE,
1008 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1009 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1010 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1011 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1012 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1013 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1014 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1015 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1016 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1017 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1021 * Convert register set to DV specification.
1023 * @param[in,out] resource
1024 * Pointer to the modify-header resource.
1026 * Pointer to action specification.
1028 * Pointer to the error structure.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 flow_dv_convert_action_set_reg
1035 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1036 const struct rte_flow_action *action,
1037 struct rte_flow_error *error)
1039 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1040 struct mlx5_modification_cmd *actions = resource->actions;
1041 uint32_t i = resource->actions_num;
1043 if (i >= MLX5_MAX_MODIFY_NUM)
1044 return rte_flow_error_set(error, EINVAL,
1045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1046 "too many items to modify");
1047 MLX5_ASSERT(conf->id != REG_NON);
1048 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1049 actions[i] = (struct mlx5_modification_cmd) {
1050 .action_type = MLX5_MODIFICATION_TYPE_SET,
1051 .field = reg_to_field[conf->id],
1052 .offset = conf->offset,
1053 .length = conf->length,
1055 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1056 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1058 resource->actions_num = i;
1063 * Convert SET_TAG action to DV specification.
1066 * Pointer to the rte_eth_dev structure.
1067 * @param[in,out] resource
1068 * Pointer to the modify-header resource.
1070 * Pointer to action specification.
1072 * Pointer to the error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_convert_action_set_tag
1079 (struct rte_eth_dev *dev,
1080 struct mlx5_flow_dv_modify_hdr_resource *resource,
1081 const struct rte_flow_action_set_tag *conf,
1082 struct rte_flow_error *error)
1084 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1085 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1086 struct rte_flow_item item = {
1090 struct field_modify_info reg_c_x[] = {
1093 enum mlx5_modification_field reg_type;
1096 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1099 MLX5_ASSERT(ret != REG_NON);
1100 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1101 reg_type = reg_to_field[ret];
1102 MLX5_ASSERT(reg_type > 0);
1103 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1104 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1105 MLX5_MODIFICATION_TYPE_SET, error);
1109 * Convert internal COPY_REG action to DV specification.
1112 * Pointer to the rte_eth_dev structure.
1113 * @param[in,out] res
1114 * Pointer to the modify-header resource.
1116 * Pointer to action specification.
1118 * Pointer to the error structure.
1121 * 0 on success, a negative errno value otherwise and rte_errno is set.
1124 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1125 struct mlx5_flow_dv_modify_hdr_resource *res,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error)
1129 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1130 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1131 struct rte_flow_item item = {
1135 struct field_modify_info reg_src[] = {
1136 {4, 0, reg_to_field[conf->src]},
1139 struct field_modify_info reg_dst = {
1141 .id = reg_to_field[conf->dst],
1143 /* Adjust reg_c[0] usage according to reported mask. */
1144 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1148 MLX5_ASSERT(reg_c0);
1149 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1150 if (conf->dst == REG_C_0) {
1151 /* Copy to reg_c[0], within mask only. */
1152 reg_dst.offset = rte_bsf32(reg_c0);
1153 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1156 mask = rte_cpu_to_be_32(reg_c0);
1159 return flow_dv_convert_modify_action(&item,
1160 reg_src, ®_dst, res,
1161 MLX5_MODIFICATION_TYPE_COPY,
1166 * Convert MARK action to DV specification. This routine is used
1167 * in extensive metadata only and requires metadata register to be
1168 * handled. In legacy mode hardware tag resource is engaged.
1171 * Pointer to the rte_eth_dev structure.
1173 * Pointer to MARK action specification.
1174 * @param[in,out] resource
1175 * Pointer to the modify-header resource.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1184 const struct rte_flow_action_mark *conf,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 struct rte_flow_error *error)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1190 priv->sh->dv_mark_mask);
1191 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1202 return rte_flow_error_set(error, EINVAL,
1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1204 NULL, "zero mark action mask");
1205 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1208 MLX5_ASSERT(reg > 0);
1209 if (reg == REG_C_0) {
1210 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1211 uint32_t shl_c0 = rte_bsf32(msk_c0);
1213 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1214 mask = rte_cpu_to_be_32(mask) & msk_c0;
1215 mask = rte_cpu_to_be_32(mask << shl_c0);
1217 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1218 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1219 MLX5_MODIFICATION_TYPE_SET, error);
1223 * Get metadata register index for specified steering domain.
1226 * Pointer to the rte_eth_dev structure.
1228 * Attributes of flow to determine steering domain.
1230 * Pointer to the error structure.
1233 * positive index on success, a negative errno value otherwise
1234 * and rte_errno is set.
1236 static enum modify_reg
1237 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1238 const struct rte_flow_attr *attr,
1239 struct rte_flow_error *error)
1242 mlx5_flow_get_reg_id(dev, attr->transfer ?
1246 MLX5_METADATA_RX, 0, error);
1248 return rte_flow_error_set(error,
1249 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1250 NULL, "unavailable "
1251 "metadata register");
1256 * Convert SET_META action to DV specification.
1259 * Pointer to the rte_eth_dev structure.
1260 * @param[in,out] resource
1261 * Pointer to the modify-header resource.
1263 * Attributes of flow that includes this item.
1265 * Pointer to action specification.
1267 * Pointer to the error structure.
1270 * 0 on success, a negative errno value otherwise and rte_errno is set.
1273 flow_dv_convert_action_set_meta
1274 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_dv_modify_hdr_resource *resource,
1276 const struct rte_flow_attr *attr,
1277 const struct rte_flow_action_set_meta *conf,
1278 struct rte_flow_error *error)
1280 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1281 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1282 struct rte_flow_item item = {
1286 struct field_modify_info reg_c_x[] = {
1289 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1293 MLX5_ASSERT(reg != REG_NON);
1294 if (reg == REG_C_0) {
1295 struct mlx5_priv *priv = dev->data->dev_private;
1296 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1297 uint32_t shl_c0 = rte_bsf32(msk_c0);
1299 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1300 mask = rte_cpu_to_be_32(mask) & msk_c0;
1301 mask = rte_cpu_to_be_32(mask << shl_c0);
1303 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1304 /* The routine expects parameters in memory as big-endian ones. */
1305 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1306 MLX5_MODIFICATION_TYPE_SET, error);
1310 * Convert modify-header set IPv4 DSCP action to DV specification.
1312 * @param[in,out] resource
1313 * Pointer to the modify-header resource.
1315 * Pointer to action specification.
1317 * Pointer to the error structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 flow_dv_convert_action_modify_ipv4_dscp
1324 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error)
1328 const struct rte_flow_action_set_dscp *conf =
1329 (const struct rte_flow_action_set_dscp *)(action->conf);
1330 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1331 struct rte_flow_item_ipv4 ipv4;
1332 struct rte_flow_item_ipv4 ipv4_mask;
1334 memset(&ipv4, 0, sizeof(ipv4));
1335 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1336 ipv4.hdr.type_of_service = conf->dscp;
1337 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1339 item.mask = &ipv4_mask;
1340 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1341 MLX5_MODIFICATION_TYPE_SET, error);
1345 * Convert modify-header set IPv6 DSCP action to DV specification.
1347 * @param[in,out] resource
1348 * Pointer to the modify-header resource.
1350 * Pointer to action specification.
1352 * Pointer to the error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_convert_action_modify_ipv6_dscp
1359 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1360 const struct rte_flow_action *action,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_set_dscp *conf =
1364 (const struct rte_flow_action_set_dscp *)(action->conf);
1365 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1366 struct rte_flow_item_ipv6 ipv6;
1367 struct rte_flow_item_ipv6 ipv6_mask;
1369 memset(&ipv6, 0, sizeof(ipv6));
1370 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1372 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1373 * rdma-core only accept the DSCP bits byte aligned start from
1374 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1375 * bits in IPv6 case as rdma-core requires byte aligned value.
1377 ipv6.hdr.vtc_flow = conf->dscp;
1378 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1380 item.mask = &ipv6_mask;
1381 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1382 MLX5_MODIFICATION_TYPE_SET, error);
1386 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1387 enum rte_flow_field_id field, int inherit,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1394 case RTE_FLOW_FIELD_START:
1396 case RTE_FLOW_FIELD_MAC_DST:
1397 case RTE_FLOW_FIELD_MAC_SRC:
1399 case RTE_FLOW_FIELD_VLAN_TYPE:
1401 case RTE_FLOW_FIELD_VLAN_ID:
1403 case RTE_FLOW_FIELD_MAC_TYPE:
1405 case RTE_FLOW_FIELD_IPV4_DSCP:
1407 case RTE_FLOW_FIELD_IPV4_TTL:
1409 case RTE_FLOW_FIELD_IPV4_SRC:
1410 case RTE_FLOW_FIELD_IPV4_DST:
1412 case RTE_FLOW_FIELD_IPV6_DSCP:
1414 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1416 case RTE_FLOW_FIELD_IPV6_SRC:
1417 case RTE_FLOW_FIELD_IPV6_DST:
1419 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1420 case RTE_FLOW_FIELD_TCP_PORT_DST:
1422 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1423 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1425 case RTE_FLOW_FIELD_TCP_FLAGS:
1427 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1428 case RTE_FLOW_FIELD_UDP_PORT_DST:
1430 case RTE_FLOW_FIELD_VXLAN_VNI:
1431 case RTE_FLOW_FIELD_GENEVE_VNI:
1433 case RTE_FLOW_FIELD_GTP_TEID:
1434 case RTE_FLOW_FIELD_TAG:
1436 case RTE_FLOW_FIELD_MARK:
1437 return __builtin_popcount(priv->sh->dv_mark_mask);
1438 case RTE_FLOW_FIELD_META:
1439 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1440 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1441 case RTE_FLOW_FIELD_POINTER:
1442 case RTE_FLOW_FIELD_VALUE:
1443 return inherit < 0 ? 0 : inherit;
1451 mlx5_flow_field_id_to_modify_info
1452 (const struct rte_flow_action_modify_data *data,
1453 struct field_modify_info *info, uint32_t *mask,
1454 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1455 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1461 switch (data->field) {
1462 case RTE_FLOW_FIELD_START:
1463 /* not supported yet */
1466 case RTE_FLOW_FIELD_MAC_DST:
1467 off = data->offset > 16 ? data->offset - 16 : 0;
1469 if (data->offset < 16) {
1470 info[idx] = (struct field_modify_info){2, 4,
1471 MLX5_MODI_OUT_DMAC_15_0};
1473 mask[idx] = rte_cpu_to_be_16(0xffff >>
1477 mask[idx] = RTE_BE16(0xffff);
1484 info[idx] = (struct field_modify_info){4, 0,
1485 MLX5_MODI_OUT_DMAC_47_16};
1486 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1487 (32 - width)) << off);
1489 if (data->offset < 16)
1490 info[idx++] = (struct field_modify_info){2, 4,
1491 MLX5_MODI_OUT_DMAC_15_0};
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1496 case RTE_FLOW_FIELD_MAC_SRC:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 4,
1501 MLX5_MODI_OUT_SMAC_15_0};
1503 mask[idx] = rte_cpu_to_be_16(0xffff >>
1507 mask[idx] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 0,
1515 MLX5_MODI_OUT_SMAC_47_16};
1516 mask[idx] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 4,
1521 MLX5_MODI_OUT_SMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1526 case RTE_FLOW_FIELD_VLAN_TYPE:
1527 /* not supported yet */
1529 case RTE_FLOW_FIELD_VLAN_ID:
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_FIRST_VID};
1533 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1535 case RTE_FLOW_FIELD_MAC_TYPE:
1536 info[idx] = (struct field_modify_info){2, 0,
1537 MLX5_MODI_OUT_ETHERTYPE};
1539 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1541 case RTE_FLOW_FIELD_IPV4_DSCP:
1542 info[idx] = (struct field_modify_info){1, 0,
1543 MLX5_MODI_OUT_IP_DSCP};
1545 mask[idx] = 0x3f >> (6 - width);
1547 case RTE_FLOW_FIELD_IPV4_TTL:
1548 info[idx] = (struct field_modify_info){1, 0,
1549 MLX5_MODI_OUT_IPV4_TTL};
1551 mask[idx] = 0xff >> (8 - width);
1553 case RTE_FLOW_FIELD_IPV4_SRC:
1554 info[idx] = (struct field_modify_info){4, 0,
1555 MLX5_MODI_OUT_SIPV4};
1557 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1560 case RTE_FLOW_FIELD_IPV4_DST:
1561 info[idx] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_DIPV4};
1564 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1567 case RTE_FLOW_FIELD_IPV6_DSCP:
1568 info[idx] = (struct field_modify_info){1, 0,
1569 MLX5_MODI_OUT_IP_DSCP};
1571 mask[idx] = 0x3f >> (6 - width);
1573 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1574 info[idx] = (struct field_modify_info){1, 0,
1575 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1577 mask[idx] = 0xff >> (8 - width);
1579 case RTE_FLOW_FIELD_IPV6_SRC:
1581 if (data->offset < 32) {
1582 info[idx] = (struct field_modify_info){4, 12,
1583 MLX5_MODI_OUT_SIPV6_31_0};
1586 rte_cpu_to_be_32(0xffffffff >>
1590 mask[idx] = RTE_BE32(0xffffffff);
1597 if (data->offset < 64) {
1598 info[idx] = (struct field_modify_info){4, 8,
1599 MLX5_MODI_OUT_SIPV6_63_32};
1602 rte_cpu_to_be_32(0xffffffff >>
1606 mask[idx] = RTE_BE32(0xffffffff);
1613 if (data->offset < 96) {
1614 info[idx] = (struct field_modify_info){4, 4,
1615 MLX5_MODI_OUT_SIPV6_95_64};
1618 rte_cpu_to_be_32(0xffffffff >>
1622 mask[idx] = RTE_BE32(0xffffffff);
1629 info[idx] = (struct field_modify_info){4, 0,
1630 MLX5_MODI_OUT_SIPV6_127_96};
1631 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1634 if (data->offset < 32)
1635 info[idx++] = (struct field_modify_info){4, 12,
1636 MLX5_MODI_OUT_SIPV6_31_0};
1637 if (data->offset < 64)
1638 info[idx++] = (struct field_modify_info){4, 8,
1639 MLX5_MODI_OUT_SIPV6_63_32};
1640 if (data->offset < 96)
1641 info[idx++] = (struct field_modify_info){4, 4,
1642 MLX5_MODI_OUT_SIPV6_95_64};
1643 if (data->offset < 128)
1644 info[idx++] = (struct field_modify_info){4, 0,
1645 MLX5_MODI_OUT_SIPV6_127_96};
1648 case RTE_FLOW_FIELD_IPV6_DST:
1650 if (data->offset < 32) {
1651 info[idx] = (struct field_modify_info){4, 12,
1652 MLX5_MODI_OUT_DIPV6_31_0};
1655 rte_cpu_to_be_32(0xffffffff >>
1659 mask[idx] = RTE_BE32(0xffffffff);
1666 if (data->offset < 64) {
1667 info[idx] = (struct field_modify_info){4, 8,
1668 MLX5_MODI_OUT_DIPV6_63_32};
1671 rte_cpu_to_be_32(0xffffffff >>
1675 mask[idx] = RTE_BE32(0xffffffff);
1682 if (data->offset < 96) {
1683 info[idx] = (struct field_modify_info){4, 4,
1684 MLX5_MODI_OUT_DIPV6_95_64};
1687 rte_cpu_to_be_32(0xffffffff >>
1691 mask[idx] = RTE_BE32(0xffffffff);
1698 info[idx] = (struct field_modify_info){4, 0,
1699 MLX5_MODI_OUT_DIPV6_127_96};
1700 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1703 if (data->offset < 32)
1704 info[idx++] = (struct field_modify_info){4, 12,
1705 MLX5_MODI_OUT_DIPV6_31_0};
1706 if (data->offset < 64)
1707 info[idx++] = (struct field_modify_info){4, 8,
1708 MLX5_MODI_OUT_DIPV6_63_32};
1709 if (data->offset < 96)
1710 info[idx++] = (struct field_modify_info){4, 4,
1711 MLX5_MODI_OUT_DIPV6_95_64};
1712 if (data->offset < 128)
1713 info[idx++] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_OUT_DIPV6_127_96};
1717 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1718 info[idx] = (struct field_modify_info){2, 0,
1719 MLX5_MODI_OUT_TCP_SPORT};
1721 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1723 case RTE_FLOW_FIELD_TCP_PORT_DST:
1724 info[idx] = (struct field_modify_info){2, 0,
1725 MLX5_MODI_OUT_TCP_DPORT};
1727 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1729 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1730 info[idx] = (struct field_modify_info){4, 0,
1731 MLX5_MODI_OUT_TCP_SEQ_NUM};
1733 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1736 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1737 info[idx] = (struct field_modify_info){4, 0,
1738 MLX5_MODI_OUT_TCP_ACK_NUM};
1740 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1743 case RTE_FLOW_FIELD_TCP_FLAGS:
1744 info[idx] = (struct field_modify_info){2, 0,
1745 MLX5_MODI_OUT_TCP_FLAGS};
1747 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1749 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1750 info[idx] = (struct field_modify_info){2, 0,
1751 MLX5_MODI_OUT_UDP_SPORT};
1753 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1755 case RTE_FLOW_FIELD_UDP_PORT_DST:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_UDP_DPORT};
1759 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1761 case RTE_FLOW_FIELD_VXLAN_VNI:
1762 /* not supported yet */
1764 case RTE_FLOW_FIELD_GENEVE_VNI:
1765 /* not supported yet*/
1767 case RTE_FLOW_FIELD_GTP_TEID:
1768 info[idx] = (struct field_modify_info){4, 0,
1769 MLX5_MODI_GTP_TEID};
1771 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1774 case RTE_FLOW_FIELD_TAG:
1776 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1777 data->level, error);
1780 MLX5_ASSERT(reg != REG_NON);
1781 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1782 info[idx] = (struct field_modify_info){4, 0,
1786 rte_cpu_to_be_32(0xffffffff >>
1790 case RTE_FLOW_FIELD_MARK:
1792 uint32_t mark_mask = priv->sh->dv_mark_mask;
1793 uint32_t mark_count = __builtin_popcount(mark_mask);
1794 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1798 MLX5_ASSERT(reg != REG_NON);
1799 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1800 info[idx] = (struct field_modify_info){4, 0,
1803 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1804 (mark_count - width)) & mark_mask);
1807 case RTE_FLOW_FIELD_META:
1809 uint32_t meta_mask = priv->sh->dv_meta_mask;
1810 uint32_t meta_count = __builtin_popcount(meta_mask);
1812 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1813 uint32_t shl_c0 = rte_bsf32(msk_c0);
1814 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1817 MLX5_ASSERT(reg != REG_NON);
1818 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1821 info[idx] = (struct field_modify_info){4, 0,
1824 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1825 (meta_count - width)) & meta_mask);
1828 case RTE_FLOW_FIELD_POINTER:
1829 case RTE_FLOW_FIELD_VALUE:
1837 * Convert modify_field action to DV specification.
1840 * Pointer to the rte_eth_dev structure.
1841 * @param[in,out] resource
1842 * Pointer to the modify-header resource.
1844 * Pointer to action specification.
1846 * Attributes of flow that includes this item.
1848 * Pointer to the error structure.
1851 * 0 on success, a negative errno value otherwise and rte_errno is set.
1854 flow_dv_convert_action_modify_field
1855 (struct rte_eth_dev *dev,
1856 struct mlx5_flow_dv_modify_hdr_resource *resource,
1857 const struct rte_flow_action *action,
1858 const struct rte_flow_attr *attr,
1859 struct rte_flow_error *error)
1861 const struct rte_flow_action_modify_field *conf =
1862 (const struct rte_flow_action_modify_field *)(action->conf);
1863 struct rte_flow_item item = {
1867 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1869 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1871 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1875 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1876 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1877 type = MLX5_MODIFICATION_TYPE_SET;
1878 /** For SET fill the destination field (field) first. */
1879 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1880 conf->width, &shift, dev,
1882 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1883 (void *)(uintptr_t)conf->src.pvalue :
1884 (void *)(uintptr_t)&conf->src.value;
1886 type = MLX5_MODIFICATION_TYPE_COPY;
1887 /** For COPY fill the destination field (dcopy) without mask. */
1888 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1889 conf->width, &shift, dev,
1891 /** Then construct the source field (field) with mask. */
1892 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1893 conf->width, &shift,
1897 return flow_dv_convert_modify_action(&item,
1898 field, dcopy, resource, type, error);
1902 * Validate MARK item.
1905 * Pointer to the rte_eth_dev structure.
1907 * Item specification.
1909 * Attributes of flow that includes this item.
1911 * Pointer to error structure.
1914 * 0 on success, a negative errno value otherwise and rte_errno is set.
1917 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1918 const struct rte_flow_item *item,
1919 const struct rte_flow_attr *attr __rte_unused,
1920 struct rte_flow_error *error)
1922 struct mlx5_priv *priv = dev->data->dev_private;
1923 struct mlx5_dev_config *config = &priv->config;
1924 const struct rte_flow_item_mark *spec = item->spec;
1925 const struct rte_flow_item_mark *mask = item->mask;
1926 const struct rte_flow_item_mark nic_mask = {
1927 .id = priv->sh->dv_mark_mask,
1931 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1932 return rte_flow_error_set(error, ENOTSUP,
1933 RTE_FLOW_ERROR_TYPE_ITEM, item,
1934 "extended metadata feature"
1936 if (!mlx5_flow_ext_mreg_supported(dev))
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "extended metadata register"
1940 " isn't supported");
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "extended metadata register"
1945 " isn't available");
1946 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1950 return rte_flow_error_set(error, EINVAL,
1951 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1953 "data cannot be empty");
1954 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1958 "mark id exceeds the limit");
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1964 "mask cannot be zero");
1966 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1967 (const uint8_t *)&nic_mask,
1968 sizeof(struct rte_flow_item_mark),
1969 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1976 * Validate META item.
1979 * Pointer to the rte_eth_dev structure.
1981 * Item specification.
1983 * Attributes of flow that includes this item.
1985 * Pointer to error structure.
1988 * 0 on success, a negative errno value otherwise and rte_errno is set.
1991 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1992 const struct rte_flow_item *item,
1993 const struct rte_flow_attr *attr,
1994 struct rte_flow_error *error)
1996 struct mlx5_priv *priv = dev->data->dev_private;
1997 struct mlx5_dev_config *config = &priv->config;
1998 const struct rte_flow_item_meta *spec = item->spec;
1999 const struct rte_flow_item_meta *mask = item->mask;
2000 struct rte_flow_item_meta nic_mask = {
2007 return rte_flow_error_set(error, EINVAL,
2008 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2010 "data cannot be empty");
2011 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2012 if (!mlx5_flow_ext_mreg_supported(dev))
2013 return rte_flow_error_set(error, ENOTSUP,
2014 RTE_FLOW_ERROR_TYPE_ITEM, item,
2015 "extended metadata register"
2016 " isn't supported");
2017 reg = flow_dv_get_metadata_reg(dev, attr, error);
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ITEM, item,
2023 "unavalable extended metadata register");
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2030 nic_mask.data = priv->sh->dv_meta_mask;
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "extended metadata feature "
2036 "should be enabled when "
2037 "meta item is requested "
2038 "with e-switch mode ");
2040 return rte_flow_error_set(error, ENOTSUP,
2041 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 "match on metadata for ingress "
2043 "is not supported in legacy "
2047 mask = &rte_flow_item_meta_mask;
2049 return rte_flow_error_set(error, EINVAL,
2050 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2051 "mask cannot be zero");
2053 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2054 (const uint8_t *)&nic_mask,
2055 sizeof(struct rte_flow_item_meta),
2056 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2061 * Validate TAG item.
2064 * Pointer to the rte_eth_dev structure.
2066 * Item specification.
2068 * Attributes of flow that includes this item.
2070 * Pointer to error structure.
2073 * 0 on success, a negative errno value otherwise and rte_errno is set.
2076 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2077 const struct rte_flow_item *item,
2078 const struct rte_flow_attr *attr __rte_unused,
2079 struct rte_flow_error *error)
2081 const struct rte_flow_item_tag *spec = item->spec;
2082 const struct rte_flow_item_tag *mask = item->mask;
2083 const struct rte_flow_item_tag nic_mask = {
2084 .data = RTE_BE32(UINT32_MAX),
2089 if (!mlx5_flow_ext_mreg_supported(dev))
2090 return rte_flow_error_set(error, ENOTSUP,
2091 RTE_FLOW_ERROR_TYPE_ITEM, item,
2092 "extensive metadata register"
2093 " isn't supported");
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2098 "data cannot be empty");
2100 mask = &rte_flow_item_tag_mask;
2102 return rte_flow_error_set(error, EINVAL,
2103 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2104 "mask cannot be zero");
2106 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2107 (const uint8_t *)&nic_mask,
2108 sizeof(struct rte_flow_item_tag),
2109 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2112 if (mask->index != 0xff)
2113 return rte_flow_error_set(error, EINVAL,
2114 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2115 "partial mask for tag index"
2116 " is not supported");
2117 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2120 MLX5_ASSERT(ret != REG_NON);
2125 * Validate vport item.
2128 * Pointer to the rte_eth_dev structure.
2130 * Item specification.
2132 * Attributes of flow that includes this item.
2133 * @param[in] item_flags
2134 * Bit-fields that holds the items detected until now.
2136 * Pointer to error structure.
2139 * 0 on success, a negative errno value otherwise and rte_errno is set.
2142 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2143 const struct rte_flow_item *item,
2144 const struct rte_flow_attr *attr,
2145 uint64_t item_flags,
2146 struct rte_flow_error *error)
2148 const struct rte_flow_item_port_id *spec = item->spec;
2149 const struct rte_flow_item_port_id *mask = item->mask;
2150 const struct rte_flow_item_port_id switch_mask = {
2153 struct mlx5_priv *esw_priv;
2154 struct mlx5_priv *dev_priv;
2157 if (!attr->transfer)
2158 return rte_flow_error_set(error, EINVAL,
2159 RTE_FLOW_ERROR_TYPE_ITEM,
2161 "match on port id is valid only"
2162 " when transfer flag is enabled");
2163 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2164 return rte_flow_error_set(error, ENOTSUP,
2165 RTE_FLOW_ERROR_TYPE_ITEM, item,
2166 "multiple source ports are not"
2169 mask = &switch_mask;
2170 if (mask->id != 0xffffffff)
2171 return rte_flow_error_set(error, ENOTSUP,
2172 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2174 "no support for partial mask on"
2176 ret = mlx5_flow_item_acceptable
2177 (item, (const uint8_t *)mask,
2178 (const uint8_t *)&rte_flow_item_port_id_mask,
2179 sizeof(struct rte_flow_item_port_id),
2180 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2185 if (spec->id == MLX5_PORT_ESW_MGR)
2187 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2189 return rte_flow_error_set(error, rte_errno,
2190 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2191 "failed to obtain E-Switch info for"
2193 dev_priv = mlx5_dev_to_eswitch_info(dev);
2195 return rte_flow_error_set(error, rte_errno,
2196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2198 "failed to obtain E-Switch info");
2199 if (esw_priv->domain_id != dev_priv->domain_id)
2200 return rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2202 "cannot match on a port from a"
2203 " different E-Switch");
2208 * Validate VLAN item.
2211 * Item specification.
2212 * @param[in] item_flags
2213 * Bit-fields that holds the items detected until now.
2215 * Ethernet device flow is being created on.
2217 * Pointer to error structure.
2220 * 0 on success, a negative errno value otherwise and rte_errno is set.
2223 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2224 uint64_t item_flags,
2225 struct rte_eth_dev *dev,
2226 struct rte_flow_error *error)
2228 const struct rte_flow_item_vlan *mask = item->mask;
2229 const struct rte_flow_item_vlan nic_mask = {
2230 .tci = RTE_BE16(UINT16_MAX),
2231 .inner_type = RTE_BE16(UINT16_MAX),
2234 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2236 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2237 MLX5_FLOW_LAYER_INNER_L4) :
2238 (MLX5_FLOW_LAYER_OUTER_L3 |
2239 MLX5_FLOW_LAYER_OUTER_L4);
2240 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2241 MLX5_FLOW_LAYER_OUTER_VLAN;
2243 if (item_flags & vlanm)
2244 return rte_flow_error_set(error, EINVAL,
2245 RTE_FLOW_ERROR_TYPE_ITEM, item,
2246 "multiple VLAN layers not supported");
2247 else if ((item_flags & l34m) != 0)
2248 return rte_flow_error_set(error, EINVAL,
2249 RTE_FLOW_ERROR_TYPE_ITEM, item,
2250 "VLAN cannot follow L3/L4 layer");
2252 mask = &rte_flow_item_vlan_mask;
2253 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2254 (const uint8_t *)&nic_mask,
2255 sizeof(struct rte_flow_item_vlan),
2256 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2259 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2260 struct mlx5_priv *priv = dev->data->dev_private;
2262 if (priv->vmwa_context) {
2264 * Non-NULL context means we have a virtual machine
2265 * and SR-IOV enabled, we have to create VLAN interface
2266 * to make hypervisor to setup E-Switch vport
2267 * context correctly. We avoid creating the multiple
2268 * VLAN interfaces, so we cannot support VLAN tag mask.
2270 return rte_flow_error_set(error, EINVAL,
2271 RTE_FLOW_ERROR_TYPE_ITEM,
2273 "VLAN tag mask is not"
2274 " supported in virtual"
2282 * GTP flags are contained in 1 byte of the format:
2283 * -------------------------------------------
2284 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2285 * |-----------------------------------------|
2286 * | value | Version | PT | Res | E | S | PN |
2287 * -------------------------------------------
2289 * Matching is supported only for GTP flags E, S, PN.
2291 #define MLX5_GTP_FLAGS_MASK 0x07
2294 * Validate GTP item.
2297 * Pointer to the rte_eth_dev structure.
2299 * Item specification.
2300 * @param[in] item_flags
2301 * Bit-fields that holds the items detected until now.
2303 * Pointer to error structure.
2306 * 0 on success, a negative errno value otherwise and rte_errno is set.
2309 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2310 const struct rte_flow_item *item,
2311 uint64_t item_flags,
2312 struct rte_flow_error *error)
2314 struct mlx5_priv *priv = dev->data->dev_private;
2315 const struct rte_flow_item_gtp *spec = item->spec;
2316 const struct rte_flow_item_gtp *mask = item->mask;
2317 const struct rte_flow_item_gtp nic_mask = {
2318 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2320 .teid = RTE_BE32(0xffffffff),
2323 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2324 return rte_flow_error_set(error, ENOTSUP,
2325 RTE_FLOW_ERROR_TYPE_ITEM, item,
2326 "GTP support is not enabled");
2327 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2328 return rte_flow_error_set(error, ENOTSUP,
2329 RTE_FLOW_ERROR_TYPE_ITEM, item,
2330 "multiple tunnel layers not"
2332 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2333 return rte_flow_error_set(error, EINVAL,
2334 RTE_FLOW_ERROR_TYPE_ITEM, item,
2335 "no outer UDP layer found");
2337 mask = &rte_flow_item_gtp_mask;
2338 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2339 return rte_flow_error_set(error, ENOTSUP,
2340 RTE_FLOW_ERROR_TYPE_ITEM, item,
2341 "Match is supported for GTP"
2343 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2344 (const uint8_t *)&nic_mask,
2345 sizeof(struct rte_flow_item_gtp),
2346 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2350 * Validate GTP PSC item.
2353 * Item specification.
2354 * @param[in] last_item
2355 * Previous validated item in the pattern items.
2356 * @param[in] gtp_item
2357 * Previous GTP item specification.
2359 * Pointer to flow attributes.
2361 * Pointer to error structure.
2364 * 0 on success, a negative errno value otherwise and rte_errno is set.
2367 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2369 const struct rte_flow_item *gtp_item,
2370 const struct rte_flow_attr *attr,
2371 struct rte_flow_error *error)
2373 const struct rte_flow_item_gtp *gtp_spec;
2374 const struct rte_flow_item_gtp *gtp_mask;
2375 const struct rte_flow_item_gtp_psc *mask;
2376 const struct rte_flow_item_gtp_psc nic_mask = {
2381 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2382 return rte_flow_error_set
2383 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2384 "GTP PSC item must be preceded with GTP item");
2385 gtp_spec = gtp_item->spec;
2386 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2387 /* GTP spec and E flag is requested to match zero. */
2389 (gtp_mask->v_pt_rsv_flags &
2390 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2391 return rte_flow_error_set
2392 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2393 "GTP E flag must be 1 to match GTP PSC");
2394 /* Check the flow is not created in group zero. */
2395 if (!attr->transfer && !attr->group)
2396 return rte_flow_error_set
2397 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2398 "GTP PSC is not supported for group 0");
2399 /* GTP spec is here and E flag is requested to match zero. */
2402 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2403 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2404 (const uint8_t *)&nic_mask,
2405 sizeof(struct rte_flow_item_gtp_psc),
2406 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2410 * Validate IPV4 item.
2411 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2412 * add specific validation of fragment_offset field,
2415 * Item specification.
2416 * @param[in] item_flags
2417 * Bit-fields that holds the items detected until now.
2419 * Pointer to error structure.
2422 * 0 on success, a negative errno value otherwise and rte_errno is set.
2425 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2426 const struct rte_flow_item *item,
2427 uint64_t item_flags, uint64_t last_item,
2428 uint16_t ether_type, struct rte_flow_error *error)
2431 struct mlx5_priv *priv = dev->data->dev_private;
2432 const struct rte_flow_item_ipv4 *spec = item->spec;
2433 const struct rte_flow_item_ipv4 *last = item->last;
2434 const struct rte_flow_item_ipv4 *mask = item->mask;
2435 rte_be16_t fragment_offset_spec = 0;
2436 rte_be16_t fragment_offset_last = 0;
2437 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2439 .src_addr = RTE_BE32(0xffffffff),
2440 .dst_addr = RTE_BE32(0xffffffff),
2441 .type_of_service = 0xff,
2442 .fragment_offset = RTE_BE16(0xffff),
2443 .next_proto_id = 0xff,
2444 .time_to_live = 0xff,
2448 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2449 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2451 priv->config.hca_attr.inner_ipv4_ihl;
2453 return rte_flow_error_set(error, ENOTSUP,
2454 RTE_FLOW_ERROR_TYPE_ITEM,
2456 "IPV4 ihl offload not supported");
2457 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2459 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2460 ether_type, &nic_ipv4_mask,
2461 MLX5_ITEM_RANGE_ACCEPTED, error);
2465 fragment_offset_spec = spec->hdr.fragment_offset &
2466 mask->hdr.fragment_offset;
2467 if (!fragment_offset_spec)
2470 * spec and mask are valid, enforce using full mask to make sure the
2471 * complete value is used correctly.
2473 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2474 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2475 return rte_flow_error_set(error, EINVAL,
2476 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2477 item, "must use full mask for"
2478 " fragment_offset");
2480 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2481 * indicating this is 1st fragment of fragmented packet.
2482 * This is not yet supported in MLX5, return appropriate error message.
2484 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2485 return rte_flow_error_set(error, ENOTSUP,
2486 RTE_FLOW_ERROR_TYPE_ITEM, item,
2487 "match on first fragment not "
2489 if (fragment_offset_spec && !last)
2490 return rte_flow_error_set(error, ENOTSUP,
2491 RTE_FLOW_ERROR_TYPE_ITEM, item,
2492 "specified value not supported");
2493 /* spec and last are valid, validate the specified range. */
2494 fragment_offset_last = last->hdr.fragment_offset &
2495 mask->hdr.fragment_offset;
2497 * Match on fragment_offset spec 0x2001 and last 0x3fff
2498 * means MF is 1 and frag-offset is > 0.
2499 * This packet is fragment 2nd and onward, excluding last.
2500 * This is not yet supported in MLX5, return appropriate
2503 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2504 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2505 return rte_flow_error_set(error, ENOTSUP,
2506 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2507 last, "match on following "
2508 "fragments not supported");
2510 * Match on fragment_offset spec 0x0001 and last 0x1fff
2511 * means MF is 0 and frag-offset is > 0.
2512 * This packet is last fragment of fragmented packet.
2513 * This is not yet supported in MLX5, return appropriate
2516 if (fragment_offset_spec == RTE_BE16(1) &&
2517 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2518 return rte_flow_error_set(error, ENOTSUP,
2519 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2520 last, "match on last "
2521 "fragment not supported");
2523 * Match on fragment_offset spec 0x0001 and last 0x3fff
2524 * means MF and/or frag-offset is not 0.
2525 * This is a fragmented packet.
2526 * Other range values are invalid and rejected.
2528 if (!(fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2532 "specified range not supported");
2537 * Validate IPV6 fragment extension item.
2540 * Item specification.
2541 * @param[in] item_flags
2542 * Bit-fields that holds the items detected until now.
2544 * Pointer to error structure.
2547 * 0 on success, a negative errno value otherwise and rte_errno is set.
2550 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2551 uint64_t item_flags,
2552 struct rte_flow_error *error)
2554 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2555 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2556 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2557 rte_be16_t frag_data_spec = 0;
2558 rte_be16_t frag_data_last = 0;
2559 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2560 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2561 MLX5_FLOW_LAYER_OUTER_L4;
2563 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2565 .next_header = 0xff,
2566 .frag_data = RTE_BE16(0xffff),
2570 if (item_flags & l4m)
2571 return rte_flow_error_set(error, EINVAL,
2572 RTE_FLOW_ERROR_TYPE_ITEM, item,
2573 "ipv6 fragment extension item cannot "
2575 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2576 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2577 return rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM, item,
2579 "ipv6 fragment extension item must "
2580 "follow ipv6 item");
2582 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2583 if (!frag_data_spec)
2586 * spec and mask are valid, enforce using full mask to make sure the
2587 * complete value is used correctly.
2589 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2590 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2591 return rte_flow_error_set(error, EINVAL,
2592 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2593 item, "must use full mask for"
2596 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2597 * This is 1st fragment of fragmented packet.
2599 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2600 return rte_flow_error_set(error, ENOTSUP,
2601 RTE_FLOW_ERROR_TYPE_ITEM, item,
2602 "match on first fragment not "
2604 if (frag_data_spec && !last)
2605 return rte_flow_error_set(error, EINVAL,
2606 RTE_FLOW_ERROR_TYPE_ITEM, item,
2607 "specified value not supported");
2608 ret = mlx5_flow_item_acceptable
2609 (item, (const uint8_t *)mask,
2610 (const uint8_t *)&nic_mask,
2611 sizeof(struct rte_flow_item_ipv6_frag_ext),
2612 MLX5_ITEM_RANGE_ACCEPTED, error);
2615 /* spec and last are valid, validate the specified range. */
2616 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2618 * Match on frag_data spec 0x0009 and last 0xfff9
2619 * means M is 1 and frag-offset is > 0.
2620 * This packet is fragment 2nd and onward, excluding last.
2621 * This is not yet supported in MLX5, return appropriate
2624 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2625 RTE_IPV6_EHDR_MF_MASK) &&
2626 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2627 return rte_flow_error_set(error, ENOTSUP,
2628 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2629 last, "match on following "
2630 "fragments not supported");
2632 * Match on frag_data spec 0x0008 and last 0xfff8
2633 * means M is 0 and frag-offset is > 0.
2634 * This packet is last fragment of fragmented packet.
2635 * This is not yet supported in MLX5, return appropriate
2638 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2639 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2640 return rte_flow_error_set(error, ENOTSUP,
2641 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2642 last, "match on last "
2643 "fragment not supported");
2644 /* Other range values are invalid and rejected. */
2645 return rte_flow_error_set(error, EINVAL,
2646 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2647 "specified range not supported");
2651 * Validate ASO CT item.
2654 * Pointer to the rte_eth_dev structure.
2656 * Item specification.
2657 * @param[in] item_flags
2658 * Pointer to bit-fields that holds the items detected until now.
2660 * Pointer to error structure.
2663 * 0 on success, a negative errno value otherwise and rte_errno is set.
2666 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2667 const struct rte_flow_item *item,
2668 uint64_t *item_flags,
2669 struct rte_flow_error *error)
2671 const struct rte_flow_item_conntrack *spec = item->spec;
2672 const struct rte_flow_item_conntrack *mask = item->mask;
2676 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2677 return rte_flow_error_set(error, EINVAL,
2678 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2679 "Only one CT is supported");
2681 mask = &rte_flow_item_conntrack_mask;
2682 flags = spec->flags & mask->flags;
2683 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2684 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2685 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2686 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2687 return rte_flow_error_set(error, EINVAL,
2688 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2689 "Conflict status bits");
2690 /* State change also needs to be considered. */
2691 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2696 * Validate the pop VLAN action.
2699 * Pointer to the rte_eth_dev structure.
2700 * @param[in] action_flags
2701 * Holds the actions detected until now.
2703 * Pointer to the pop vlan action.
2704 * @param[in] item_flags
2705 * The items found in this flow rule.
2707 * Pointer to flow attributes.
2709 * Pointer to error structure.
2712 * 0 on success, a negative errno value otherwise and rte_errno is set.
2715 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2716 uint64_t action_flags,
2717 const struct rte_flow_action *action,
2718 uint64_t item_flags,
2719 const struct rte_flow_attr *attr,
2720 struct rte_flow_error *error)
2722 const struct mlx5_priv *priv = dev->data->dev_private;
2723 struct mlx5_dev_ctx_shared *sh = priv->sh;
2724 bool direction_error = false;
2726 if (!priv->sh->pop_vlan_action)
2727 return rte_flow_error_set(error, ENOTSUP,
2728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2730 "pop vlan action is not supported");
2731 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2732 if (attr->transfer) {
2733 bool fdb_tx = priv->representor_id != UINT16_MAX;
2734 bool is_cx5 = sh->steering_format_version ==
2735 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2737 if (fdb_tx && is_cx5)
2738 direction_error = true;
2739 } else if (attr->egress) {
2740 direction_error = true;
2742 if (direction_error)
2743 return rte_flow_error_set(error, ENOTSUP,
2744 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2746 "pop vlan action not supported for egress");
2747 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2748 return rte_flow_error_set(error, ENOTSUP,
2749 RTE_FLOW_ERROR_TYPE_ACTION, action,
2750 "no support for multiple VLAN "
2752 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2753 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2754 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2758 "cannot pop vlan after decap without "
2759 "match on inner vlan in the flow");
2760 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2761 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2762 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2763 return rte_flow_error_set(error, ENOTSUP,
2764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2766 "cannot pop vlan without a "
2767 "match on (outer) vlan in the flow");
2768 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION, action,
2771 "wrong action order, port_id should "
2772 "be after pop VLAN action");
2773 if (!attr->transfer && priv->representor)
2774 return rte_flow_error_set(error, ENOTSUP,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776 "pop vlan action for VF representor "
2777 "not supported on NIC table");
2782 * Get VLAN default info from vlan match info.
2785 * the list of item specifications.
2787 * pointer VLAN info to fill to.
2790 * 0 on success, a negative errno value otherwise and rte_errno is set.
2793 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2794 struct rte_vlan_hdr *vlan)
2796 const struct rte_flow_item_vlan nic_mask = {
2797 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2798 MLX5DV_FLOW_VLAN_VID_MASK),
2799 .inner_type = RTE_BE16(0xffff),
2804 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2805 int type = items->type;
2807 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2808 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2811 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2812 const struct rte_flow_item_vlan *vlan_m = items->mask;
2813 const struct rte_flow_item_vlan *vlan_v = items->spec;
2815 /* If VLAN item in pattern doesn't contain data, return here. */
2820 /* Only full match values are accepted */
2821 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2822 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2823 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2825 rte_be_to_cpu_16(vlan_v->tci &
2826 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2828 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2829 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2830 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2832 rte_be_to_cpu_16(vlan_v->tci &
2833 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2835 if (vlan_m->inner_type == nic_mask.inner_type)
2836 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2837 vlan_m->inner_type);
2842 * Validate the push VLAN action.
2845 * Pointer to the rte_eth_dev structure.
2846 * @param[in] action_flags
2847 * Holds the actions detected until now.
2848 * @param[in] item_flags
2849 * The items found in this flow rule.
2851 * Pointer to the action structure.
2853 * Pointer to flow attributes
2855 * Pointer to error structure.
2858 * 0 on success, a negative errno value otherwise and rte_errno is set.
2861 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2862 uint64_t action_flags,
2863 const struct rte_flow_item_vlan *vlan_m,
2864 const struct rte_flow_action *action,
2865 const struct rte_flow_attr *attr,
2866 struct rte_flow_error *error)
2868 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2869 const struct mlx5_priv *priv = dev->data->dev_private;
2870 struct mlx5_dev_ctx_shared *sh = priv->sh;
2871 bool direction_error = false;
2873 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2874 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2875 return rte_flow_error_set(error, EINVAL,
2876 RTE_FLOW_ERROR_TYPE_ACTION, action,
2877 "invalid vlan ethertype");
2878 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2879 return rte_flow_error_set(error, EINVAL,
2880 RTE_FLOW_ERROR_TYPE_ACTION, action,
2881 "wrong action order, port_id should "
2882 "be after push VLAN");
2883 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2884 if (attr->transfer) {
2885 bool fdb_tx = priv->representor_id != UINT16_MAX;
2886 bool is_cx5 = sh->steering_format_version ==
2887 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2889 if (!fdb_tx && is_cx5)
2890 direction_error = true;
2891 } else if (attr->ingress) {
2892 direction_error = true;
2894 if (direction_error)
2895 return rte_flow_error_set(error, ENOTSUP,
2896 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2898 "push vlan action not supported for ingress");
2899 if (!attr->transfer && priv->representor)
2900 return rte_flow_error_set(error, ENOTSUP,
2901 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2902 "push vlan action for VF representor "
2903 "not supported on NIC table");
2905 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2906 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2907 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2908 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2909 !(mlx5_flow_find_action
2910 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2911 return rte_flow_error_set(error, EINVAL,
2912 RTE_FLOW_ERROR_TYPE_ACTION, action,
2913 "not full match mask on VLAN PCP and "
2914 "there is no of_set_vlan_pcp action, "
2915 "push VLAN action cannot figure out "
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2919 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2920 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2921 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2922 !(mlx5_flow_find_action
2923 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2924 return rte_flow_error_set(error, EINVAL,
2925 RTE_FLOW_ERROR_TYPE_ACTION, action,
2926 "not full match mask on VLAN VID and "
2927 "there is no of_set_vlan_vid action, "
2928 "push VLAN action cannot figure out "
2935 * Validate the set VLAN PCP.
2937 * @param[in] action_flags
2938 * Holds the actions detected until now.
2939 * @param[in] actions
2940 * Pointer to the list of actions remaining in the flow rule.
2942 * Pointer to error structure.
2945 * 0 on success, a negative errno value otherwise and rte_errno is set.
2948 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2949 const struct rte_flow_action actions[],
2950 struct rte_flow_error *error)
2952 const struct rte_flow_action *action = actions;
2953 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2955 if (conf->vlan_pcp > 7)
2956 return rte_flow_error_set(error, EINVAL,
2957 RTE_FLOW_ERROR_TYPE_ACTION, action,
2958 "VLAN PCP value is too big");
2959 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2960 return rte_flow_error_set(error, ENOTSUP,
2961 RTE_FLOW_ERROR_TYPE_ACTION, action,
2962 "set VLAN PCP action must follow "
2963 "the push VLAN action");
2964 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2965 return rte_flow_error_set(error, ENOTSUP,
2966 RTE_FLOW_ERROR_TYPE_ACTION, action,
2967 "Multiple VLAN PCP modification are "
2969 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2970 return rte_flow_error_set(error, EINVAL,
2971 RTE_FLOW_ERROR_TYPE_ACTION, action,
2972 "wrong action order, port_id should "
2973 "be after set VLAN PCP");
2978 * Validate the set VLAN VID.
2980 * @param[in] item_flags
2981 * Holds the items detected in this rule.
2982 * @param[in] action_flags
2983 * Holds the actions detected until now.
2984 * @param[in] actions
2985 * Pointer to the list of actions remaining in the flow rule.
2987 * Pointer to error structure.
2990 * 0 on success, a negative errno value otherwise and rte_errno is set.
2993 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2994 uint64_t action_flags,
2995 const struct rte_flow_action actions[],
2996 struct rte_flow_error *error)
2998 const struct rte_flow_action *action = actions;
2999 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3001 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3002 return rte_flow_error_set(error, EINVAL,
3003 RTE_FLOW_ERROR_TYPE_ACTION, action,
3004 "VLAN VID value is too big");
3005 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3006 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3007 return rte_flow_error_set(error, ENOTSUP,
3008 RTE_FLOW_ERROR_TYPE_ACTION, action,
3009 "set VLAN VID action must follow push"
3010 " VLAN action or match on VLAN item");
3011 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3012 return rte_flow_error_set(error, ENOTSUP,
3013 RTE_FLOW_ERROR_TYPE_ACTION, action,
3014 "Multiple VLAN VID modifications are "
3016 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION, action,
3019 "wrong action order, port_id should "
3020 "be after set VLAN VID");
3025 * Validate the FLAG action.
3028 * Pointer to the rte_eth_dev structure.
3029 * @param[in] action_flags
3030 * Holds the actions detected until now.
3032 * Pointer to flow attributes
3034 * Pointer to error structure.
3037 * 0 on success, a negative errno value otherwise and rte_errno is set.
3040 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3041 uint64_t action_flags,
3042 const struct rte_flow_attr *attr,
3043 struct rte_flow_error *error)
3045 struct mlx5_priv *priv = dev->data->dev_private;
3046 struct mlx5_dev_config *config = &priv->config;
3049 /* Fall back if no extended metadata register support. */
3050 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3051 return mlx5_flow_validate_action_flag(action_flags, attr,
3053 /* Extensive metadata mode requires registers. */
3054 if (!mlx5_flow_ext_mreg_supported(dev))
3055 return rte_flow_error_set(error, ENOTSUP,
3056 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3057 "no metadata registers "
3058 "to support flag action");
3059 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3060 return rte_flow_error_set(error, ENOTSUP,
3061 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3062 "extended metadata register"
3063 " isn't available");
3064 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3067 MLX5_ASSERT(ret > 0);
3068 if (action_flags & MLX5_FLOW_ACTION_MARK)
3069 return rte_flow_error_set(error, EINVAL,
3070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3071 "can't mark and flag in same flow");
3072 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3073 return rte_flow_error_set(error, EINVAL,
3074 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3076 " actions in same flow");
3081 * Validate MARK action.
3084 * Pointer to the rte_eth_dev structure.
3086 * Pointer to action.
3087 * @param[in] action_flags
3088 * Holds the actions detected until now.
3090 * Pointer to flow attributes
3092 * Pointer to error structure.
3095 * 0 on success, a negative errno value otherwise and rte_errno is set.
3098 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3099 const struct rte_flow_action *action,
3100 uint64_t action_flags,
3101 const struct rte_flow_attr *attr,
3102 struct rte_flow_error *error)
3104 struct mlx5_priv *priv = dev->data->dev_private;
3105 struct mlx5_dev_config *config = &priv->config;
3106 const struct rte_flow_action_mark *mark = action->conf;
3109 if (is_tunnel_offload_active(dev))
3110 return rte_flow_error_set(error, ENOTSUP,
3111 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3113 "if tunnel offload active");
3114 /* Fall back if no extended metadata register support. */
3115 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3116 return mlx5_flow_validate_action_mark(action, action_flags,
3118 /* Extensive metadata mode requires registers. */
3119 if (!mlx5_flow_ext_mreg_supported(dev))
3120 return rte_flow_error_set(error, ENOTSUP,
3121 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3122 "no metadata registers "
3123 "to support mark action");
3124 if (!priv->sh->dv_mark_mask)
3125 return rte_flow_error_set(error, ENOTSUP,
3126 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3127 "extended metadata register"
3128 " isn't available");
3129 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3132 MLX5_ASSERT(ret > 0);
3134 return rte_flow_error_set(error, EINVAL,
3135 RTE_FLOW_ERROR_TYPE_ACTION, action,
3136 "configuration cannot be null");
3137 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3138 return rte_flow_error_set(error, EINVAL,
3139 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3141 "mark id exceeds the limit");
3142 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3143 return rte_flow_error_set(error, EINVAL,
3144 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3145 "can't flag and mark in same flow");
3146 if (action_flags & MLX5_FLOW_ACTION_MARK)
3147 return rte_flow_error_set(error, EINVAL,
3148 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3149 "can't have 2 mark actions in same"
3155 * Validate SET_META action.
3158 * Pointer to the rte_eth_dev structure.
3160 * Pointer to the action structure.
3161 * @param[in] action_flags
3162 * Holds the actions detected until now.
3164 * Pointer to flow attributes
3166 * Pointer to error structure.
3169 * 0 on success, a negative errno value otherwise and rte_errno is set.
3172 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3173 const struct rte_flow_action *action,
3174 uint64_t action_flags __rte_unused,
3175 const struct rte_flow_attr *attr,
3176 struct rte_flow_error *error)
3178 const struct rte_flow_action_set_meta *conf;
3179 uint32_t nic_mask = UINT32_MAX;
3182 if (!mlx5_flow_ext_mreg_supported(dev))
3183 return rte_flow_error_set(error, ENOTSUP,
3184 RTE_FLOW_ERROR_TYPE_ACTION, action,
3185 "extended metadata register"
3186 " isn't supported");
3187 reg = flow_dv_get_metadata_reg(dev, attr, error);
3191 return rte_flow_error_set(error, ENOTSUP,
3192 RTE_FLOW_ERROR_TYPE_ACTION, action,
3193 "unavalable extended metadata register");
3194 if (reg != REG_A && reg != REG_B) {
3195 struct mlx5_priv *priv = dev->data->dev_private;
3197 nic_mask = priv->sh->dv_meta_mask;
3199 if (!(action->conf))
3200 return rte_flow_error_set(error, EINVAL,
3201 RTE_FLOW_ERROR_TYPE_ACTION, action,
3202 "configuration cannot be null");
3203 conf = (const struct rte_flow_action_set_meta *)action->conf;
3205 return rte_flow_error_set(error, EINVAL,
3206 RTE_FLOW_ERROR_TYPE_ACTION, action,
3207 "zero mask doesn't have any effect");
3208 if (conf->mask & ~nic_mask)
3209 return rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, action,
3211 "meta data must be within reg C0");
3216 * Validate SET_TAG action.
3219 * Pointer to the rte_eth_dev structure.
3221 * Pointer to the action structure.
3222 * @param[in] action_flags
3223 * Holds the actions detected until now.
3225 * Pointer to flow attributes
3227 * Pointer to error structure.
3230 * 0 on success, a negative errno value otherwise and rte_errno is set.
3233 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3234 const struct rte_flow_action *action,
3235 uint64_t action_flags,
3236 const struct rte_flow_attr *attr,
3237 struct rte_flow_error *error)
3239 const struct rte_flow_action_set_tag *conf;
3240 const uint64_t terminal_action_flags =
3241 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3242 MLX5_FLOW_ACTION_RSS;
3245 if (!mlx5_flow_ext_mreg_supported(dev))
3246 return rte_flow_error_set(error, ENOTSUP,
3247 RTE_FLOW_ERROR_TYPE_ACTION, action,
3248 "extensive metadata register"
3249 " isn't supported");
3250 if (!(action->conf))
3251 return rte_flow_error_set(error, EINVAL,
3252 RTE_FLOW_ERROR_TYPE_ACTION, action,
3253 "configuration cannot be null");
3254 conf = (const struct rte_flow_action_set_tag *)action->conf;
3256 return rte_flow_error_set(error, EINVAL,
3257 RTE_FLOW_ERROR_TYPE_ACTION, action,
3258 "zero mask doesn't have any effect");
3259 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3262 if (!attr->transfer && attr->ingress &&
3263 (action_flags & terminal_action_flags))
3264 return rte_flow_error_set(error, EINVAL,
3265 RTE_FLOW_ERROR_TYPE_ACTION, action,
3266 "set_tag has no effect"
3267 " with terminal actions");
3272 * Validate count action.
3275 * Pointer to rte_eth_dev structure.
3277 * Indicator if action is shared.
3278 * @param[in] action_flags
3279 * Holds the actions detected until now.
3281 * Pointer to error structure.
3284 * 0 on success, a negative errno value otherwise and rte_errno is set.
3287 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3288 uint64_t action_flags,
3289 struct rte_flow_error *error)
3291 struct mlx5_priv *priv = dev->data->dev_private;
3293 if (!priv->sh->devx)
3295 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3296 return rte_flow_error_set(error, EINVAL,
3297 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3298 "duplicate count actions set");
3299 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3300 !priv->sh->flow_hit_aso_en)
3301 return rte_flow_error_set(error, EINVAL,
3302 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3303 "old age and shared count combination is not supported");
3304 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3308 return rte_flow_error_set
3310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3312 "count action not supported");
3316 * Validate the L2 encap action.
3319 * Pointer to the rte_eth_dev structure.
3320 * @param[in] action_flags
3321 * Holds the actions detected until now.
3323 * Pointer to the action structure.
3325 * Pointer to flow attributes.
3327 * Pointer to error structure.
3330 * 0 on success, a negative errno value otherwise and rte_errno is set.
3333 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3334 uint64_t action_flags,
3335 const struct rte_flow_action *action,
3336 const struct rte_flow_attr *attr,
3337 struct rte_flow_error *error)
3339 const struct mlx5_priv *priv = dev->data->dev_private;
3341 if (!(action->conf))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION, action,
3344 "configuration cannot be null");
3345 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3346 return rte_flow_error_set(error, EINVAL,
3347 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3348 "can only have a single encap action "
3350 if (!attr->transfer && priv->representor)
3351 return rte_flow_error_set(error, ENOTSUP,
3352 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3353 "encap action for VF representor "
3354 "not supported on NIC table");
3359 * Validate a decap action.
3362 * Pointer to the rte_eth_dev structure.
3363 * @param[in] action_flags
3364 * Holds the actions detected until now.
3366 * Pointer to the action structure.
3367 * @param[in] item_flags
3368 * Holds the items detected.
3370 * Pointer to flow attributes
3372 * Pointer to error structure.
3375 * 0 on success, a negative errno value otherwise and rte_errno is set.
3378 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3379 uint64_t action_flags,
3380 const struct rte_flow_action *action,
3381 const uint64_t item_flags,
3382 const struct rte_flow_attr *attr,
3383 struct rte_flow_error *error)
3385 const struct mlx5_priv *priv = dev->data->dev_private;
3387 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3388 !priv->config.decap_en)
3389 return rte_flow_error_set(error, ENOTSUP,
3390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3391 "decap is not enabled");
3392 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3393 return rte_flow_error_set(error, ENOTSUP,
3394 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3396 MLX5_FLOW_ACTION_DECAP ? "can only "
3397 "have a single decap action" : "decap "
3398 "after encap is not supported");
3399 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3402 "can't have decap action after"
3405 return rte_flow_error_set(error, ENOTSUP,
3406 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3408 "decap action not supported for "
3410 if (!attr->transfer && priv->representor)
3411 return rte_flow_error_set(error, ENOTSUP,
3412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3413 "decap action for VF representor "
3414 "not supported on NIC table");
3415 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3416 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3417 return rte_flow_error_set(error, ENOTSUP,
3418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3419 "VXLAN item should be present for VXLAN decap");
3423 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3426 * Validate the raw encap and decap actions.
3429 * Pointer to the rte_eth_dev structure.
3431 * Pointer to the decap action.
3433 * Pointer to the encap action.
3435 * Pointer to flow attributes
3436 * @param[in/out] action_flags
3437 * Holds the actions detected until now.
3438 * @param[out] actions_n
3439 * pointer to the number of actions counter.
3441 * Pointer to the action structure.
3442 * @param[in] item_flags
3443 * Holds the items detected.
3445 * Pointer to error structure.
3448 * 0 on success, a negative errno value otherwise and rte_errno is set.
3451 flow_dv_validate_action_raw_encap_decap
3452 (struct rte_eth_dev *dev,
3453 const struct rte_flow_action_raw_decap *decap,
3454 const struct rte_flow_action_raw_encap *encap,
3455 const struct rte_flow_attr *attr, uint64_t *action_flags,
3456 int *actions_n, const struct rte_flow_action *action,
3457 uint64_t item_flags, struct rte_flow_error *error)
3459 const struct mlx5_priv *priv = dev->data->dev_private;
3462 if (encap && (!encap->size || !encap->data))
3463 return rte_flow_error_set(error, EINVAL,
3464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3465 "raw encap data cannot be empty");
3466 if (decap && encap) {
3467 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3468 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3471 else if (encap->size <=
3472 MLX5_ENCAPSULATION_DECISION_SIZE &&
3474 MLX5_ENCAPSULATION_DECISION_SIZE)
3477 else if (encap->size >
3478 MLX5_ENCAPSULATION_DECISION_SIZE &&
3480 MLX5_ENCAPSULATION_DECISION_SIZE)
3481 /* 2 L2 actions: encap and decap. */
3484 return rte_flow_error_set(error,
3486 RTE_FLOW_ERROR_TYPE_ACTION,
3487 NULL, "unsupported too small "
3488 "raw decap and too small raw "
3489 "encap combination");
3492 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3493 item_flags, attr, error);
3496 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3500 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3501 return rte_flow_error_set(error, ENOTSUP,
3502 RTE_FLOW_ERROR_TYPE_ACTION,
3504 "small raw encap size");
3505 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3506 return rte_flow_error_set(error, EINVAL,
3507 RTE_FLOW_ERROR_TYPE_ACTION,
3509 "more than one encap action");
3510 if (!attr->transfer && priv->representor)
3511 return rte_flow_error_set
3513 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3514 "encap action for VF representor "
3515 "not supported on NIC table");
3516 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3523 * Validate the ASO CT action.
3526 * Pointer to the rte_eth_dev structure.
3527 * @param[in] action_flags
3528 * Holds the actions detected until now.
3529 * @param[in] item_flags
3530 * The items found in this flow rule.
3532 * Pointer to flow attributes.
3534 * Pointer to error structure.
3537 * 0 on success, a negative errno value otherwise and rte_errno is set.
3540 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3541 uint64_t action_flags,
3542 uint64_t item_flags,
3543 const struct rte_flow_attr *attr,
3544 struct rte_flow_error *error)
3548 if (attr->group == 0 && !attr->transfer)
3549 return rte_flow_error_set(error, ENOTSUP,
3550 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3552 "Only support non-root table");
3553 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3554 return rte_flow_error_set(error, ENOTSUP,
3555 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3556 "CT cannot follow a fate action");
3557 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3558 (action_flags & MLX5_FLOW_ACTION_AGE))
3559 return rte_flow_error_set(error, EINVAL,
3560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3561 "Only one ASO action is supported");
3562 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3563 return rte_flow_error_set(error, EINVAL,
3564 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3565 "Encap cannot exist before CT");
3566 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3567 return rte_flow_error_set(error, EINVAL,
3568 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3569 "Not a outer TCP packet");
3574 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3575 struct mlx5_list_entry *entry, void *cb_ctx)
3577 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3578 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3579 struct mlx5_flow_dv_encap_decap_resource *resource;
3581 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3583 if (resource->reformat_type == ctx_resource->reformat_type &&
3584 resource->ft_type == ctx_resource->ft_type &&
3585 resource->flags == ctx_resource->flags &&
3586 resource->size == ctx_resource->size &&
3587 !memcmp((const void *)resource->buf,
3588 (const void *)ctx_resource->buf,
3594 struct mlx5_list_entry *
3595 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3597 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3598 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3599 struct mlx5dv_dr_domain *domain;
3600 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3601 struct mlx5_flow_dv_encap_decap_resource *resource;
3605 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3606 domain = sh->fdb_domain;
3607 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3608 domain = sh->rx_domain;
3610 domain = sh->tx_domain;
3611 /* Register new encap/decap resource. */
3612 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3614 rte_flow_error_set(ctx->error, ENOMEM,
3615 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3616 "cannot allocate resource memory");
3619 *resource = *ctx_resource;
3620 resource->idx = idx;
3621 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3625 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3626 rte_flow_error_set(ctx->error, ENOMEM,
3627 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3628 NULL, "cannot create action");
3632 return &resource->entry;
3635 struct mlx5_list_entry *
3636 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3639 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3640 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3641 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3644 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3646 if (!cache_resource) {
3647 rte_flow_error_set(ctx->error, ENOMEM,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3649 "cannot allocate resource memory");
3652 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3653 cache_resource->idx = idx;
3654 return &cache_resource->entry;
3658 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3660 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3661 struct mlx5_flow_dv_encap_decap_resource *res =
3662 container_of(entry, typeof(*res), entry);
3664 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3668 * Find existing encap/decap resource or create and register a new one.
3670 * @param[in, out] dev
3671 * Pointer to rte_eth_dev structure.
3672 * @param[in, out] resource
3673 * Pointer to encap/decap resource.
3674 * @parm[in, out] dev_flow
3675 * Pointer to the dev_flow.
3677 * pointer to error structure.
3680 * 0 on success otherwise -errno and errno is set.
3683 flow_dv_encap_decap_resource_register
3684 (struct rte_eth_dev *dev,
3685 struct mlx5_flow_dv_encap_decap_resource *resource,
3686 struct mlx5_flow *dev_flow,
3687 struct rte_flow_error *error)
3689 struct mlx5_priv *priv = dev->data->dev_private;
3690 struct mlx5_dev_ctx_shared *sh = priv->sh;
3691 struct mlx5_list_entry *entry;
3695 uint32_t refmt_type:8;
3697 * Header reformat actions can be shared between
3698 * non-root tables. One bit to indicate non-root
3702 uint32_t reserve:15;
3705 } encap_decap_key = {
3707 .ft_type = resource->ft_type,
3708 .refmt_type = resource->reformat_type,
3709 .is_root = !!dev_flow->dv.group,
3713 struct mlx5_flow_cb_ctx ctx = {
3717 struct mlx5_hlist *encaps_decaps;
3720 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3722 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3724 flow_dv_encap_decap_create_cb,
3725 flow_dv_encap_decap_match_cb,
3726 flow_dv_encap_decap_remove_cb,
3727 flow_dv_encap_decap_clone_cb,
3728 flow_dv_encap_decap_clone_free_cb);
3729 if (unlikely(!encaps_decaps))
3731 resource->flags = dev_flow->dv.group ? 0 : 1;
3732 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3733 sizeof(encap_decap_key.v32), 0);
3734 if (resource->reformat_type !=
3735 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3737 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3738 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3741 resource = container_of(entry, typeof(*resource), entry);
3742 dev_flow->dv.encap_decap = resource;
3743 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3748 * Find existing table jump resource or create and register a new one.
3750 * @param[in, out] dev
3751 * Pointer to rte_eth_dev structure.
3752 * @param[in, out] tbl
3753 * Pointer to flow table resource.
3754 * @parm[in, out] dev_flow
3755 * Pointer to the dev_flow.
3757 * pointer to error structure.
3760 * 0 on success otherwise -errno and errno is set.
3763 flow_dv_jump_tbl_resource_register
3764 (struct rte_eth_dev *dev __rte_unused,
3765 struct mlx5_flow_tbl_resource *tbl,
3766 struct mlx5_flow *dev_flow,
3767 struct rte_flow_error *error __rte_unused)
3769 struct mlx5_flow_tbl_data_entry *tbl_data =
3770 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3773 MLX5_ASSERT(tbl_data->jump.action);
3774 dev_flow->handle->rix_jump = tbl_data->idx;
3775 dev_flow->dv.jump = &tbl_data->jump;
3780 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3781 struct mlx5_list_entry *entry, void *cb_ctx)
3783 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3784 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3785 struct mlx5_flow_dv_port_id_action_resource *res =
3786 container_of(entry, typeof(*res), entry);
3788 return ref->port_id != res->port_id;
3791 struct mlx5_list_entry *
3792 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3794 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3795 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3796 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3797 struct mlx5_flow_dv_port_id_action_resource *resource;
3801 /* Register new port id action resource. */
3802 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3804 rte_flow_error_set(ctx->error, ENOMEM,
3805 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3806 "cannot allocate port_id action memory");
3810 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3814 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3815 rte_flow_error_set(ctx->error, ENOMEM,
3816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3817 "cannot create action");
3820 resource->idx = idx;
3821 return &resource->entry;
3824 struct mlx5_list_entry *
3825 flow_dv_port_id_clone_cb(void *tool_ctx,
3826 struct mlx5_list_entry *entry __rte_unused,
3829 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3830 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3831 struct mlx5_flow_dv_port_id_action_resource *resource;
3834 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3836 rte_flow_error_set(ctx->error, ENOMEM,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3838 "cannot allocate port_id action memory");
3841 memcpy(resource, entry, sizeof(*resource));
3842 resource->idx = idx;
3843 return &resource->entry;
3847 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3849 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3850 struct mlx5_flow_dv_port_id_action_resource *resource =
3851 container_of(entry, typeof(*resource), entry);
3853 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3857 * Find existing table port ID resource or create and register a new one.
3859 * @param[in, out] dev
3860 * Pointer to rte_eth_dev structure.
3861 * @param[in, out] ref
3862 * Pointer to port ID action resource reference.
3863 * @parm[in, out] dev_flow
3864 * Pointer to the dev_flow.
3866 * pointer to error structure.
3869 * 0 on success otherwise -errno and errno is set.
3872 flow_dv_port_id_action_resource_register
3873 (struct rte_eth_dev *dev,
3874 struct mlx5_flow_dv_port_id_action_resource *ref,
3875 struct mlx5_flow *dev_flow,
3876 struct rte_flow_error *error)
3878 struct mlx5_priv *priv = dev->data->dev_private;
3879 struct mlx5_list_entry *entry;
3880 struct mlx5_flow_dv_port_id_action_resource *resource;
3881 struct mlx5_flow_cb_ctx ctx = {
3886 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3889 resource = container_of(entry, typeof(*resource), entry);
3890 dev_flow->dv.port_id_action = resource;
3891 dev_flow->handle->rix_port_id_action = resource->idx;
3896 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3897 struct mlx5_list_entry *entry, void *cb_ctx)
3899 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3900 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3901 struct mlx5_flow_dv_push_vlan_action_resource *res =
3902 container_of(entry, typeof(*res), entry);
3904 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3907 struct mlx5_list_entry *
3908 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3910 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3911 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3912 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3913 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3914 struct mlx5dv_dr_domain *domain;
3918 /* Register new port id action resource. */
3919 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3921 rte_flow_error_set(ctx->error, ENOMEM,
3922 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3923 "cannot allocate push_vlan action memory");
3927 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3928 domain = sh->fdb_domain;
3929 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3930 domain = sh->rx_domain;
3932 domain = sh->tx_domain;
3933 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3936 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3937 rte_flow_error_set(ctx->error, ENOMEM,
3938 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3939 "cannot create push vlan action");
3942 resource->idx = idx;
3943 return &resource->entry;
3946 struct mlx5_list_entry *
3947 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3948 struct mlx5_list_entry *entry __rte_unused,
3951 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3952 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3953 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3956 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3958 rte_flow_error_set(ctx->error, ENOMEM,
3959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3960 "cannot allocate push_vlan action memory");
3963 memcpy(resource, entry, sizeof(*resource));
3964 resource->idx = idx;
3965 return &resource->entry;
3969 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3971 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3972 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3973 container_of(entry, typeof(*resource), entry);
3975 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3979 * Find existing push vlan resource or create and register a new one.
3981 * @param [in, out] dev
3982 * Pointer to rte_eth_dev structure.
3983 * @param[in, out] ref
3984 * Pointer to port ID action resource reference.
3985 * @parm[in, out] dev_flow
3986 * Pointer to the dev_flow.
3988 * pointer to error structure.
3991 * 0 on success otherwise -errno and errno is set.
3994 flow_dv_push_vlan_action_resource_register
3995 (struct rte_eth_dev *dev,
3996 struct mlx5_flow_dv_push_vlan_action_resource *ref,
3997 struct mlx5_flow *dev_flow,
3998 struct rte_flow_error *error)
4000 struct mlx5_priv *priv = dev->data->dev_private;
4001 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4002 struct mlx5_list_entry *entry;
4003 struct mlx5_flow_cb_ctx ctx = {
4008 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4011 resource = container_of(entry, typeof(*resource), entry);
4013 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4014 dev_flow->dv.push_vlan_res = resource;
4019 * Get the size of specific rte_flow_item_type hdr size
4021 * @param[in] item_type
4022 * Tested rte_flow_item_type.
4025 * sizeof struct item_type, 0 if void or irrelevant.
4028 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4032 switch (item_type) {
4033 case RTE_FLOW_ITEM_TYPE_ETH:
4034 retval = sizeof(struct rte_ether_hdr);
4036 case RTE_FLOW_ITEM_TYPE_VLAN:
4037 retval = sizeof(struct rte_vlan_hdr);
4039 case RTE_FLOW_ITEM_TYPE_IPV4:
4040 retval = sizeof(struct rte_ipv4_hdr);
4042 case RTE_FLOW_ITEM_TYPE_IPV6:
4043 retval = sizeof(struct rte_ipv6_hdr);
4045 case RTE_FLOW_ITEM_TYPE_UDP:
4046 retval = sizeof(struct rte_udp_hdr);
4048 case RTE_FLOW_ITEM_TYPE_TCP:
4049 retval = sizeof(struct rte_tcp_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VXLAN:
4052 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4053 retval = sizeof(struct rte_vxlan_hdr);
4055 case RTE_FLOW_ITEM_TYPE_GRE:
4056 case RTE_FLOW_ITEM_TYPE_NVGRE:
4057 retval = sizeof(struct rte_gre_hdr);
4059 case RTE_FLOW_ITEM_TYPE_MPLS:
4060 retval = sizeof(struct rte_mpls_hdr);
4062 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4070 #define MLX5_ENCAP_IPV4_VERSION 0x40
4071 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4072 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4073 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4074 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4075 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4076 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4079 * Convert the encap action data from list of rte_flow_item to raw buffer
4082 * Pointer to rte_flow_item objects list.
4084 * Pointer to the output buffer.
4086 * Pointer to the output buffer size.
4088 * Pointer to the error structure.
4091 * 0 on success, a negative errno value otherwise and rte_errno is set.
4094 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4095 size_t *size, struct rte_flow_error *error)
4097 struct rte_ether_hdr *eth = NULL;
4098 struct rte_vlan_hdr *vlan = NULL;
4099 struct rte_ipv4_hdr *ipv4 = NULL;
4100 struct rte_ipv6_hdr *ipv6 = NULL;
4101 struct rte_udp_hdr *udp = NULL;
4102 struct rte_vxlan_hdr *vxlan = NULL;
4103 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4104 struct rte_gre_hdr *gre = NULL;
4106 size_t temp_size = 0;
4109 return rte_flow_error_set(error, EINVAL,
4110 RTE_FLOW_ERROR_TYPE_ACTION,
4111 NULL, "invalid empty data");
4112 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4113 len = flow_dv_get_item_hdr_len(items->type);
4114 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4115 return rte_flow_error_set(error, EINVAL,
4116 RTE_FLOW_ERROR_TYPE_ACTION,
4117 (void *)items->type,
4118 "items total size is too big"
4119 " for encap action");
4120 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4121 switch (items->type) {
4122 case RTE_FLOW_ITEM_TYPE_ETH:
4123 eth = (struct rte_ether_hdr *)&buf[temp_size];
4125 case RTE_FLOW_ITEM_TYPE_VLAN:
4126 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4128 return rte_flow_error_set(error, EINVAL,
4129 RTE_FLOW_ERROR_TYPE_ACTION,
4130 (void *)items->type,
4131 "eth header not found");
4132 if (!eth->ether_type)
4133 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4135 case RTE_FLOW_ITEM_TYPE_IPV4:
4136 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4138 return rte_flow_error_set(error, EINVAL,
4139 RTE_FLOW_ERROR_TYPE_ACTION,
4140 (void *)items->type,
4141 "neither eth nor vlan"
4143 if (vlan && !vlan->eth_proto)
4144 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4145 else if (eth && !eth->ether_type)
4146 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4147 if (!ipv4->version_ihl)
4148 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4149 MLX5_ENCAP_IPV4_IHL_MIN;
4150 if (!ipv4->time_to_live)
4151 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4153 case RTE_FLOW_ITEM_TYPE_IPV6:
4154 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4156 return rte_flow_error_set(error, EINVAL,
4157 RTE_FLOW_ERROR_TYPE_ACTION,
4158 (void *)items->type,
4159 "neither eth nor vlan"
4161 if (vlan && !vlan->eth_proto)
4162 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4163 else if (eth && !eth->ether_type)
4164 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4165 if (!ipv6->vtc_flow)
4167 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4168 if (!ipv6->hop_limits)
4169 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4171 case RTE_FLOW_ITEM_TYPE_UDP:
4172 udp = (struct rte_udp_hdr *)&buf[temp_size];
4174 return rte_flow_error_set(error, EINVAL,
4175 RTE_FLOW_ERROR_TYPE_ACTION,
4176 (void *)items->type,
4177 "ip header not found");
4178 if (ipv4 && !ipv4->next_proto_id)
4179 ipv4->next_proto_id = IPPROTO_UDP;
4180 else if (ipv6 && !ipv6->proto)
4181 ipv6->proto = IPPROTO_UDP;
4183 case RTE_FLOW_ITEM_TYPE_VXLAN:
4184 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4186 return rte_flow_error_set(error, EINVAL,
4187 RTE_FLOW_ERROR_TYPE_ACTION,
4188 (void *)items->type,
4189 "udp header not found");
4191 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4192 if (!vxlan->vx_flags)
4194 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4196 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4197 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4199 return rte_flow_error_set(error, EINVAL,
4200 RTE_FLOW_ERROR_TYPE_ACTION,
4201 (void *)items->type,
4202 "udp header not found");
4203 if (!vxlan_gpe->proto)
4204 return rte_flow_error_set(error, EINVAL,
4205 RTE_FLOW_ERROR_TYPE_ACTION,
4206 (void *)items->type,
4207 "next protocol not found");
4210 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4211 if (!vxlan_gpe->vx_flags)
4212 vxlan_gpe->vx_flags =
4213 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4215 case RTE_FLOW_ITEM_TYPE_GRE:
4216 case RTE_FLOW_ITEM_TYPE_NVGRE:
4217 gre = (struct rte_gre_hdr *)&buf[temp_size];
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4224 return rte_flow_error_set(error, EINVAL,
4225 RTE_FLOW_ERROR_TYPE_ACTION,
4226 (void *)items->type,
4227 "ip header not found");
4228 if (ipv4 && !ipv4->next_proto_id)
4229 ipv4->next_proto_id = IPPROTO_GRE;
4230 else if (ipv6 && !ipv6->proto)
4231 ipv6->proto = IPPROTO_GRE;
4233 case RTE_FLOW_ITEM_TYPE_VOID:
4236 return rte_flow_error_set(error, EINVAL,
4237 RTE_FLOW_ERROR_TYPE_ACTION,
4238 (void *)items->type,
4239 "unsupported item type");
4249 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4251 struct rte_ether_hdr *eth = NULL;
4252 struct rte_vlan_hdr *vlan = NULL;
4253 struct rte_ipv6_hdr *ipv6 = NULL;
4254 struct rte_udp_hdr *udp = NULL;
4258 eth = (struct rte_ether_hdr *)data;
4259 next_hdr = (char *)(eth + 1);
4260 proto = RTE_BE16(eth->ether_type);
4263 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4264 vlan = (struct rte_vlan_hdr *)next_hdr;
4265 proto = RTE_BE16(vlan->eth_proto);
4266 next_hdr += sizeof(struct rte_vlan_hdr);
4269 /* HW calculates IPv4 csum. no need to proceed */
4270 if (proto == RTE_ETHER_TYPE_IPV4)
4273 /* non IPv4/IPv6 header. not supported */
4274 if (proto != RTE_ETHER_TYPE_IPV6) {
4275 return rte_flow_error_set(error, ENOTSUP,
4276 RTE_FLOW_ERROR_TYPE_ACTION,
4277 NULL, "Cannot offload non IPv4/IPv6");
4280 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4282 /* ignore non UDP */
4283 if (ipv6->proto != IPPROTO_UDP)
4286 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4287 udp->dgram_cksum = 0;
4293 * Convert L2 encap action to DV specification.
4296 * Pointer to rte_eth_dev structure.
4298 * Pointer to action structure.
4299 * @param[in, out] dev_flow
4300 * Pointer to the mlx5_flow.
4301 * @param[in] transfer
4302 * Mark if the flow is E-Switch flow.
4304 * Pointer to the error structure.
4307 * 0 on success, a negative errno value otherwise and rte_errno is set.
4310 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4311 const struct rte_flow_action *action,
4312 struct mlx5_flow *dev_flow,
4314 struct rte_flow_error *error)
4316 const struct rte_flow_item *encap_data;
4317 const struct rte_flow_action_raw_encap *raw_encap_data;
4318 struct mlx5_flow_dv_encap_decap_resource res = {
4320 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4321 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4322 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4325 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4327 (const struct rte_flow_action_raw_encap *)action->conf;
4328 res.size = raw_encap_data->size;
4329 memcpy(res.buf, raw_encap_data->data, res.size);
4331 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4333 ((const struct rte_flow_action_vxlan_encap *)
4334 action->conf)->definition;
4337 ((const struct rte_flow_action_nvgre_encap *)
4338 action->conf)->definition;
4339 if (flow_dv_convert_encap_data(encap_data, res.buf,
4343 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4345 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4346 return rte_flow_error_set(error, EINVAL,
4347 RTE_FLOW_ERROR_TYPE_ACTION,
4348 NULL, "can't create L2 encap action");
4353 * Convert L2 decap action to DV specification.
4356 * Pointer to rte_eth_dev structure.
4357 * @param[in, out] dev_flow
4358 * Pointer to the mlx5_flow.
4359 * @param[in] transfer
4360 * Mark if the flow is E-Switch flow.
4362 * Pointer to the error structure.
4365 * 0 on success, a negative errno value otherwise and rte_errno is set.
4368 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4369 struct mlx5_flow *dev_flow,
4371 struct rte_flow_error *error)
4373 struct mlx5_flow_dv_encap_decap_resource res = {
4376 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4377 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4378 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4381 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4382 return rte_flow_error_set(error, EINVAL,
4383 RTE_FLOW_ERROR_TYPE_ACTION,
4384 NULL, "can't create L2 decap action");
4389 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4392 * Pointer to rte_eth_dev structure.
4394 * Pointer to action structure.
4395 * @param[in, out] dev_flow
4396 * Pointer to the mlx5_flow.
4398 * Pointer to the flow attributes.
4400 * Pointer to the error structure.
4403 * 0 on success, a negative errno value otherwise and rte_errno is set.
4406 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4407 const struct rte_flow_action *action,
4408 struct mlx5_flow *dev_flow,
4409 const struct rte_flow_attr *attr,
4410 struct rte_flow_error *error)
4412 const struct rte_flow_action_raw_encap *encap_data;
4413 struct mlx5_flow_dv_encap_decap_resource res;
4415 memset(&res, 0, sizeof(res));
4416 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4417 res.size = encap_data->size;
4418 memcpy(res.buf, encap_data->data, res.size);
4419 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4420 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4421 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4423 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4425 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4426 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4427 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4428 return rte_flow_error_set(error, EINVAL,
4429 RTE_FLOW_ERROR_TYPE_ACTION,
4430 NULL, "can't create encap action");
4435 * Create action push VLAN.
4438 * Pointer to rte_eth_dev structure.
4440 * Pointer to the flow attributes.
4442 * Pointer to the vlan to push to the Ethernet header.
4443 * @param[in, out] dev_flow
4444 * Pointer to the mlx5_flow.
4446 * Pointer to the error structure.
4449 * 0 on success, a negative errno value otherwise and rte_errno is set.
4452 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4453 const struct rte_flow_attr *attr,
4454 const struct rte_vlan_hdr *vlan,
4455 struct mlx5_flow *dev_flow,
4456 struct rte_flow_error *error)
4458 struct mlx5_flow_dv_push_vlan_action_resource res;
4460 memset(&res, 0, sizeof(res));
4462 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4465 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4467 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4468 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4469 return flow_dv_push_vlan_action_resource_register
4470 (dev, &res, dev_flow, error);
4474 * Validate the modify-header actions.
4476 * @param[in] action_flags
4477 * Holds the actions detected until now.
4479 * Pointer to the modify action.
4481 * Pointer to error structure.
4484 * 0 on success, a negative errno value otherwise and rte_errno is set.
4487 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4488 const struct rte_flow_action *action,
4489 struct rte_flow_error *error)
4491 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4492 return rte_flow_error_set(error, EINVAL,
4493 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4494 NULL, "action configuration not set");
4495 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4496 return rte_flow_error_set(error, EINVAL,
4497 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4498 "can't have encap action before"
4504 * Validate the modify-header MAC address actions.
4506 * @param[in] action_flags
4507 * Holds the actions detected until now.
4509 * Pointer to the modify action.
4510 * @param[in] item_flags
4511 * Holds the items detected.
4513 * Pointer to error structure.
4516 * 0 on success, a negative errno value otherwise and rte_errno is set.
4519 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4520 const struct rte_flow_action *action,
4521 const uint64_t item_flags,
4522 struct rte_flow_error *error)
4526 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4528 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4529 return rte_flow_error_set(error, EINVAL,
4530 RTE_FLOW_ERROR_TYPE_ACTION,
4532 "no L2 item in pattern");
4538 * Validate the modify-header IPv4 address actions.
4540 * @param[in] action_flags
4541 * Holds the actions detected until now.
4543 * Pointer to the modify action.
4544 * @param[in] item_flags
4545 * Holds the items detected.
4547 * Pointer to error structure.
4550 * 0 on success, a negative errno value otherwise and rte_errno is set.
4553 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4554 const struct rte_flow_action *action,
4555 const uint64_t item_flags,
4556 struct rte_flow_error *error)
4561 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4563 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4564 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4565 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4566 if (!(item_flags & layer))
4567 return rte_flow_error_set(error, EINVAL,
4568 RTE_FLOW_ERROR_TYPE_ACTION,
4570 "no ipv4 item in pattern");
4576 * Validate the modify-header IPv6 address actions.
4578 * @param[in] action_flags
4579 * Holds the actions detected until now.
4581 * Pointer to the modify action.
4582 * @param[in] item_flags
4583 * Holds the items detected.
4585 * Pointer to error structure.
4588 * 0 on success, a negative errno value otherwise and rte_errno is set.
4591 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4592 const struct rte_flow_action *action,
4593 const uint64_t item_flags,
4594 struct rte_flow_error *error)
4599 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4601 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4602 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4603 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4604 if (!(item_flags & layer))
4605 return rte_flow_error_set(error, EINVAL,
4606 RTE_FLOW_ERROR_TYPE_ACTION,
4608 "no ipv6 item in pattern");
4614 * Validate the modify-header TP actions.
4616 * @param[in] action_flags
4617 * Holds the actions detected until now.
4619 * Pointer to the modify action.
4620 * @param[in] item_flags
4621 * Holds the items detected.
4623 * Pointer to error structure.
4626 * 0 on success, a negative errno value otherwise and rte_errno is set.
4629 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4630 const struct rte_flow_action *action,
4631 const uint64_t item_flags,
4632 struct rte_flow_error *error)
4637 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4639 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4640 MLX5_FLOW_LAYER_INNER_L4 :
4641 MLX5_FLOW_LAYER_OUTER_L4;
4642 if (!(item_flags & layer))
4643 return rte_flow_error_set(error, EINVAL,
4644 RTE_FLOW_ERROR_TYPE_ACTION,
4645 NULL, "no transport layer "
4652 * Validate the modify-header actions of increment/decrement
4653 * TCP Sequence-number.
4655 * @param[in] action_flags
4656 * Holds the actions detected until now.
4658 * Pointer to the modify action.
4659 * @param[in] item_flags
4660 * Holds the items detected.
4662 * Pointer to error structure.
4665 * 0 on success, a negative errno value otherwise and rte_errno is set.
4668 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4669 const struct rte_flow_action *action,
4670 const uint64_t item_flags,
4671 struct rte_flow_error *error)
4676 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4678 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4679 MLX5_FLOW_LAYER_INNER_L4_TCP :
4680 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4681 if (!(item_flags & layer))
4682 return rte_flow_error_set(error, EINVAL,
4683 RTE_FLOW_ERROR_TYPE_ACTION,
4684 NULL, "no TCP item in"
4686 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4687 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4688 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4689 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4690 return rte_flow_error_set(error, EINVAL,
4691 RTE_FLOW_ERROR_TYPE_ACTION,
4693 "cannot decrease and increase"
4694 " TCP sequence number"
4695 " at the same time");
4701 * Validate the modify-header actions of increment/decrement
4702 * TCP Acknowledgment number.
4704 * @param[in] action_flags
4705 * Holds the actions detected until now.
4707 * Pointer to the modify action.
4708 * @param[in] item_flags
4709 * Holds the items detected.
4711 * Pointer to error structure.
4714 * 0 on success, a negative errno value otherwise and rte_errno is set.
4717 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4718 const struct rte_flow_action *action,
4719 const uint64_t item_flags,
4720 struct rte_flow_error *error)
4725 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4727 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4728 MLX5_FLOW_LAYER_INNER_L4_TCP :
4729 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4730 if (!(item_flags & layer))
4731 return rte_flow_error_set(error, EINVAL,
4732 RTE_FLOW_ERROR_TYPE_ACTION,
4733 NULL, "no TCP item in"
4735 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4736 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4737 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4738 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4739 return rte_flow_error_set(error, EINVAL,
4740 RTE_FLOW_ERROR_TYPE_ACTION,
4742 "cannot decrease and increase"
4743 " TCP acknowledgment number"
4744 " at the same time");
4750 * Validate the modify-header TTL actions.
4752 * @param[in] action_flags
4753 * Holds the actions detected until now.
4755 * Pointer to the modify action.
4756 * @param[in] item_flags
4757 * Holds the items detected.
4759 * Pointer to error structure.
4762 * 0 on success, a negative errno value otherwise and rte_errno is set.
4765 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4766 const struct rte_flow_action *action,
4767 const uint64_t item_flags,
4768 struct rte_flow_error *error)
4773 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4775 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4776 MLX5_FLOW_LAYER_INNER_L3 :
4777 MLX5_FLOW_LAYER_OUTER_L3;
4778 if (!(item_flags & layer))
4779 return rte_flow_error_set(error, EINVAL,
4780 RTE_FLOW_ERROR_TYPE_ACTION,
4782 "no IP protocol in pattern");
4788 * Validate the generic modify field actions.
4790 * Pointer to the rte_eth_dev structure.
4791 * @param[in] action_flags
4792 * Holds the actions detected until now.
4794 * Pointer to the modify action.
4796 * Pointer to the flow attributes.
4798 * Pointer to error structure.
4801 * Number of header fields to modify (0 or more) on success,
4802 * a negative errno value otherwise and rte_errno is set.
4805 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4806 const uint64_t action_flags,
4807 const struct rte_flow_action *action,
4808 const struct rte_flow_attr *attr,
4809 struct rte_flow_error *error)
4812 struct mlx5_priv *priv = dev->data->dev_private;
4813 struct mlx5_dev_config *config = &priv->config;
4814 const struct rte_flow_action_modify_field *action_modify_field =
4816 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4817 action_modify_field->dst.field,
4819 uint32_t src_width = mlx5_flow_item_field_width(dev,
4820 action_modify_field->src.field,
4821 dst_width, attr, error);
4823 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4827 if (action_modify_field->width == 0)
4828 return rte_flow_error_set(error, EINVAL,
4829 RTE_FLOW_ERROR_TYPE_ACTION, action,
4830 "no bits are requested to be modified");
4831 else if (action_modify_field->width > dst_width ||
4832 action_modify_field->width > src_width)
4833 return rte_flow_error_set(error, EINVAL,
4834 RTE_FLOW_ERROR_TYPE_ACTION, action,
4835 "cannot modify more bits than"
4836 " the width of a field");
4837 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4838 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4839 if ((action_modify_field->dst.offset +
4840 action_modify_field->width > dst_width) ||
4841 (action_modify_field->dst.offset % 32))
4842 return rte_flow_error_set(error, EINVAL,
4843 RTE_FLOW_ERROR_TYPE_ACTION, action,
4844 "destination offset is too big"
4845 " or not aligned to 4 bytes");
4846 if (action_modify_field->dst.level &&
4847 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4848 return rte_flow_error_set(error, ENOTSUP,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "inner header fields modification"
4851 " is not supported");
4853 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4854 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4855 if (!attr->transfer && !attr->group)
4856 return rte_flow_error_set(error, ENOTSUP,
4857 RTE_FLOW_ERROR_TYPE_ACTION, action,
4858 "modify field action is not"
4859 " supported for group 0");
4860 if ((action_modify_field->src.offset +
4861 action_modify_field->width > src_width) ||
4862 (action_modify_field->src.offset % 32))
4863 return rte_flow_error_set(error, EINVAL,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "source offset is too big"
4866 " or not aligned to 4 bytes");
4867 if (action_modify_field->src.level &&
4868 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4869 return rte_flow_error_set(error, ENOTSUP,
4870 RTE_FLOW_ERROR_TYPE_ACTION, action,
4871 "inner header fields modification"
4872 " is not supported");
4874 if ((action_modify_field->dst.field ==
4875 action_modify_field->src.field) &&
4876 (action_modify_field->dst.level ==
4877 action_modify_field->src.level))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source and destination fields"
4881 " cannot be the same");
4882 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4883 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4884 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4885 return rte_flow_error_set(error, EINVAL,
4886 RTE_FLOW_ERROR_TYPE_ACTION, action,
4887 "mark, immediate value or a pointer to it"
4888 " cannot be used as a destination");
4889 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4890 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4891 return rte_flow_error_set(error, ENOTSUP,
4892 RTE_FLOW_ERROR_TYPE_ACTION, action,
4893 "modifications of an arbitrary"
4894 " place in a packet is not supported");
4895 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4896 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4897 return rte_flow_error_set(error, ENOTSUP,
4898 RTE_FLOW_ERROR_TYPE_ACTION, action,
4899 "modifications of the 802.1Q Tag"
4900 " Identifier is not supported");
4901 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4902 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4903 return rte_flow_error_set(error, ENOTSUP,
4904 RTE_FLOW_ERROR_TYPE_ACTION, action,
4905 "modifications of the VXLAN Network"
4906 " Identifier is not supported");
4907 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4908 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4909 return rte_flow_error_set(error, ENOTSUP,
4910 RTE_FLOW_ERROR_TYPE_ACTION, action,
4911 "modifications of the GENEVE Network"
4912 " Identifier is not supported");
4913 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4914 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4915 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4916 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4917 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4918 !mlx5_flow_ext_mreg_supported(dev))
4919 return rte_flow_error_set(error, ENOTSUP,
4920 RTE_FLOW_ERROR_TYPE_ACTION, action,
4921 "cannot modify mark or metadata without"
4922 " extended metadata register support");
4924 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4925 return rte_flow_error_set(error, ENOTSUP,
4926 RTE_FLOW_ERROR_TYPE_ACTION, action,
4927 "add and sub operations"
4928 " are not supported");
4929 return (action_modify_field->width / 32) +
4930 !!(action_modify_field->width % 32);
4934 * Validate jump action.
4937 * Pointer to the jump action.
4938 * @param[in] action_flags
4939 * Holds the actions detected until now.
4940 * @param[in] attributes
4941 * Pointer to flow attributes
4942 * @param[in] external
4943 * Action belongs to flow rule created by request external to PMD.
4945 * Pointer to error structure.
4948 * 0 on success, a negative errno value otherwise and rte_errno is set.
4951 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4952 const struct mlx5_flow_tunnel *tunnel,
4953 const struct rte_flow_action *action,
4954 uint64_t action_flags,
4955 const struct rte_flow_attr *attributes,
4956 bool external, struct rte_flow_error *error)
4958 uint32_t target_group, table;
4960 struct flow_grp_info grp_info = {
4961 .external = !!external,
4962 .transfer = !!attributes->transfer,
4966 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4967 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4968 return rte_flow_error_set(error, EINVAL,
4969 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4970 "can't have 2 fate actions in"
4973 return rte_flow_error_set(error, EINVAL,
4974 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4975 NULL, "action configuration not set");
4977 ((const struct rte_flow_action_jump *)action->conf)->group;
4978 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4982 if (attributes->group == target_group &&
4983 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4984 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4985 return rte_flow_error_set(error, EINVAL,
4986 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4987 "target group must be other than"
4988 " the current flow group");
4993 * Validate action PORT_ID / REPRESENTED_PORT.
4996 * Pointer to rte_eth_dev structure.
4997 * @param[in] action_flags
4998 * Bit-fields that holds the actions detected until now.
5000 * PORT_ID / REPRESENTED_PORT action structure.
5002 * Attributes of flow that includes this action.
5004 * Pointer to error structure.
5007 * 0 on success, a negative errno value otherwise and rte_errno is set.
5010 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5011 uint64_t action_flags,
5012 const struct rte_flow_action *action,
5013 const struct rte_flow_attr *attr,
5014 struct rte_flow_error *error)
5016 const struct rte_flow_action_port_id *port_id;
5017 const struct rte_flow_action_ethdev *ethdev;
5018 struct mlx5_priv *act_priv;
5019 struct mlx5_priv *dev_priv;
5022 if (!attr->transfer)
5023 return rte_flow_error_set(error, ENOTSUP,
5024 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5026 "port action is valid in transfer"
5028 if (!action || !action->conf)
5029 return rte_flow_error_set(error, ENOTSUP,
5030 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5032 "port action parameters must be"
5034 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5035 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5036 return rte_flow_error_set(error, EINVAL,
5037 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5038 "can have only one fate actions in"
5040 dev_priv = mlx5_dev_to_eswitch_info(dev);
5042 return rte_flow_error_set(error, rte_errno,
5043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5045 "failed to obtain E-Switch info");
5046 switch (action->type) {
5047 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5048 port_id = action->conf;
5049 port = port_id->original ? dev->data->port_id : port_id->id;
5051 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5052 ethdev = action->conf;
5053 port = ethdev->port_id;
5057 return rte_flow_error_set
5059 RTE_FLOW_ERROR_TYPE_ACTION, action,
5060 "unknown E-Switch action");
5062 act_priv = mlx5_port_to_eswitch_info(port, false);
5064 return rte_flow_error_set
5066 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5067 "failed to obtain E-Switch port id for port");
5068 if (act_priv->domain_id != dev_priv->domain_id)
5069 return rte_flow_error_set
5071 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5072 "port does not belong to"
5073 " E-Switch being configured");
5078 * Get the maximum number of modify header actions.
5081 * Pointer to rte_eth_dev structure.
5083 * Whether action is on root table.
5086 * Max number of modify header actions device can support.
5088 static inline unsigned int
5089 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5093 * There's no way to directly query the max capacity from FW.
5094 * The maximal value on root table should be assumed to be supported.
5097 return MLX5_MAX_MODIFY_NUM;
5099 return MLX5_ROOT_TBL_MODIFY_NUM;
5103 * Validate the meter action.
5106 * Pointer to rte_eth_dev structure.
5107 * @param[in] action_flags
5108 * Bit-fields that holds the actions detected until now.
5110 * Pointer to the meter action.
5112 * Attributes of flow that includes this action.
5113 * @param[in] port_id_item
5114 * Pointer to item indicating port id.
5116 * Pointer to error structure.
5119 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5122 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5123 uint64_t action_flags,
5124 const struct rte_flow_action *action,
5125 const struct rte_flow_attr *attr,
5126 const struct rte_flow_item *port_id_item,
5128 struct rte_flow_error *error)
5130 struct mlx5_priv *priv = dev->data->dev_private;
5131 const struct rte_flow_action_meter *am = action->conf;
5132 struct mlx5_flow_meter_info *fm;
5133 struct mlx5_flow_meter_policy *mtr_policy;
5134 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5137 return rte_flow_error_set(error, EINVAL,
5138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5139 "meter action conf is NULL");
5141 if (action_flags & MLX5_FLOW_ACTION_METER)
5142 return rte_flow_error_set(error, ENOTSUP,
5143 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5144 "meter chaining not support");
5145 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5146 return rte_flow_error_set(error, ENOTSUP,
5147 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5148 "meter with jump not support");
5150 return rte_flow_error_set(error, ENOTSUP,
5151 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5153 "meter action not supported");
5154 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5156 return rte_flow_error_set(error, EINVAL,
5157 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5159 /* aso meter can always be shared by different domains */
5160 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5161 !(fm->transfer == attr->transfer ||
5162 (!fm->ingress && !attr->ingress && attr->egress) ||
5163 (!fm->egress && !attr->egress && attr->ingress)))
5164 return rte_flow_error_set(error, EINVAL,
5165 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5166 "Flow attributes domain are either invalid "
5167 "or have a domain conflict with current "
5168 "meter attributes");
5169 if (fm->def_policy) {
5170 if (!((attr->transfer &&
5171 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5173 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5175 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5176 return rte_flow_error_set(error, EINVAL,
5177 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5178 "Flow attributes domain "
5179 "have a conflict with current "
5180 "meter domain attributes");
5183 mtr_policy = mlx5_flow_meter_policy_find(dev,
5184 fm->policy_id, NULL);
5186 return rte_flow_error_set(error, EINVAL,
5187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5188 "Invalid policy id for meter ");
5189 if (!((attr->transfer && mtr_policy->transfer) ||
5190 (attr->egress && mtr_policy->egress) ||
5191 (attr->ingress && mtr_policy->ingress)))
5192 return rte_flow_error_set(error, EINVAL,
5193 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5194 "Flow attributes domain "
5195 "have a conflict with current "
5196 "meter domain attributes");
5197 if (attr->transfer && mtr_policy->dev) {
5199 * When policy has fate action of port_id,
5200 * the flow should have the same src port as policy.
5202 struct mlx5_priv *policy_port_priv =
5203 mtr_policy->dev->data->dev_private;
5204 int32_t flow_src_port = priv->representor_id;
5207 const struct rte_flow_item_port_id *spec =
5209 struct mlx5_priv *port_priv =
5210 mlx5_port_to_eswitch_info(spec->id,
5213 return rte_flow_error_set(error,
5215 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5217 "Failed to get port info.");
5218 flow_src_port = port_priv->representor_id;
5220 if (flow_src_port != policy_port_priv->representor_id)
5221 return rte_flow_error_set(error,
5223 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5225 "Flow and meter policy "
5226 "have different src port.");
5228 *def_policy = false;
5234 * Validate the age action.
5236 * @param[in] action_flags
5237 * Holds the actions detected until now.
5239 * Pointer to the age action.
5241 * Pointer to the Ethernet device structure.
5243 * Pointer to error structure.
5246 * 0 on success, a negative errno value otherwise and rte_errno is set.
5249 flow_dv_validate_action_age(uint64_t action_flags,
5250 const struct rte_flow_action *action,
5251 struct rte_eth_dev *dev,
5252 struct rte_flow_error *error)
5254 struct mlx5_priv *priv = dev->data->dev_private;
5255 const struct rte_flow_action_age *age = action->conf;
5257 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5258 !priv->sh->aso_age_mng))
5259 return rte_flow_error_set(error, ENOTSUP,
5260 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5262 "age action not supported");
5263 if (!(action->conf))
5264 return rte_flow_error_set(error, EINVAL,
5265 RTE_FLOW_ERROR_TYPE_ACTION, action,
5266 "configuration cannot be null");
5267 if (!(age->timeout))
5268 return rte_flow_error_set(error, EINVAL,
5269 RTE_FLOW_ERROR_TYPE_ACTION, action,
5270 "invalid timeout value 0");
5271 if (action_flags & MLX5_FLOW_ACTION_AGE)
5272 return rte_flow_error_set(error, EINVAL,
5273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5274 "duplicate age actions set");
5279 * Validate the modify-header IPv4 DSCP actions.
5281 * @param[in] action_flags
5282 * Holds the actions detected until now.
5284 * Pointer to the modify action.
5285 * @param[in] item_flags
5286 * Holds the items detected.
5288 * Pointer to error structure.
5291 * 0 on success, a negative errno value otherwise and rte_errno is set.
5294 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5295 const struct rte_flow_action *action,
5296 const uint64_t item_flags,
5297 struct rte_flow_error *error)
5301 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5303 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5304 return rte_flow_error_set(error, EINVAL,
5305 RTE_FLOW_ERROR_TYPE_ACTION,
5307 "no ipv4 item in pattern");
5313 * Validate the modify-header IPv6 DSCP actions.
5315 * @param[in] action_flags
5316 * Holds the actions detected until now.
5318 * Pointer to the modify action.
5319 * @param[in] item_flags
5320 * Holds the items detected.
5322 * Pointer to error structure.
5325 * 0 on success, a negative errno value otherwise and rte_errno is set.
5328 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5329 const struct rte_flow_action *action,
5330 const uint64_t item_flags,
5331 struct rte_flow_error *error)
5335 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5337 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5338 return rte_flow_error_set(error, EINVAL,
5339 RTE_FLOW_ERROR_TYPE_ACTION,
5341 "no ipv6 item in pattern");
5347 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5348 struct mlx5_list_entry *entry, void *cb_ctx)
5350 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5351 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5352 struct mlx5_flow_dv_modify_hdr_resource *resource =
5353 container_of(entry, typeof(*resource), entry);
5354 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5356 key_len += ref->actions_num * sizeof(ref->actions[0]);
5357 return ref->actions_num != resource->actions_num ||
5358 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5361 static struct mlx5_indexed_pool *
5362 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5364 struct mlx5_indexed_pool *ipool = __atomic_load_n
5365 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5368 struct mlx5_indexed_pool *expected = NULL;
5369 struct mlx5_indexed_pool_config cfg =
5370 (struct mlx5_indexed_pool_config) {
5371 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5373 sizeof(struct mlx5_modification_cmd),
5378 .release_mem_en = !!sh->reclaim_mode,
5379 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5380 .malloc = mlx5_malloc,
5382 .type = "mlx5_modify_action_resource",
5385 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5386 ipool = mlx5_ipool_create(&cfg);
5389 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5390 &expected, ipool, false,
5392 __ATOMIC_SEQ_CST)) {
5393 mlx5_ipool_destroy(ipool);
5394 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5401 struct mlx5_list_entry *
5402 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5404 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5405 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5406 struct mlx5dv_dr_domain *ns;
5407 struct mlx5_flow_dv_modify_hdr_resource *entry;
5408 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5409 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5410 ref->actions_num - 1);
5412 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5413 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5416 if (unlikely(!ipool)) {
5417 rte_flow_error_set(ctx->error, ENOMEM,
5418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5419 NULL, "cannot allocate modify ipool");
5422 entry = mlx5_ipool_zmalloc(ipool, &idx);
5424 rte_flow_error_set(ctx->error, ENOMEM,
5425 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5426 "cannot allocate resource memory");
5429 rte_memcpy(&entry->ft_type,
5430 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5431 key_len + data_len);
5432 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5433 ns = sh->fdb_domain;
5434 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5438 ret = mlx5_flow_os_create_flow_action_modify_header
5439 (sh->cdev->ctx, ns, entry,
5440 data_len, &entry->action);
5442 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5443 rte_flow_error_set(ctx->error, ENOMEM,
5444 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5445 NULL, "cannot create modification action");
5449 return &entry->entry;
5452 struct mlx5_list_entry *
5453 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5456 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5457 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5458 struct mlx5_flow_dv_modify_hdr_resource *entry;
5459 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5460 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5463 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5466 rte_flow_error_set(ctx->error, ENOMEM,
5467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5468 "cannot allocate resource memory");
5471 memcpy(entry, oentry, sizeof(*entry) + data_len);
5473 return &entry->entry;
5477 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5479 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5480 struct mlx5_flow_dv_modify_hdr_resource *res =
5481 container_of(entry, typeof(*res), entry);
5483 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5487 * Validate the sample action.
5489 * @param[in, out] action_flags
5490 * Holds the actions detected until now.
5492 * Pointer to the sample action.
5494 * Pointer to the Ethernet device structure.
5496 * Attributes of flow that includes this action.
5497 * @param[in] item_flags
5498 * Holds the items detected.
5500 * Pointer to the RSS action.
5501 * @param[out] sample_rss
5502 * Pointer to the RSS action in sample action list.
5504 * Pointer to the COUNT action in sample action list.
5505 * @param[out] fdb_mirror_limit
5506 * Pointer to the FDB mirror limitation flag.
5508 * Pointer to error structure.
5511 * 0 on success, a negative errno value otherwise and rte_errno is set.
5514 flow_dv_validate_action_sample(uint64_t *action_flags,
5515 const struct rte_flow_action *action,
5516 struct rte_eth_dev *dev,
5517 const struct rte_flow_attr *attr,
5518 uint64_t item_flags,
5519 const struct rte_flow_action_rss *rss,
5520 const struct rte_flow_action_rss **sample_rss,
5521 const struct rte_flow_action_count **count,
5522 int *fdb_mirror_limit,
5523 struct rte_flow_error *error)
5525 struct mlx5_priv *priv = dev->data->dev_private;
5526 struct mlx5_dev_config *dev_conf = &priv->config;
5527 const struct rte_flow_action_sample *sample = action->conf;
5528 const struct rte_flow_action *act;
5529 uint64_t sub_action_flags = 0;
5530 uint16_t queue_index = 0xFFFF;
5535 return rte_flow_error_set(error, EINVAL,
5536 RTE_FLOW_ERROR_TYPE_ACTION, action,
5537 "configuration cannot be NULL");
5538 if (sample->ratio == 0)
5539 return rte_flow_error_set(error, EINVAL,
5540 RTE_FLOW_ERROR_TYPE_ACTION, action,
5541 "ratio value starts from 1");
5542 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5543 return rte_flow_error_set(error, ENOTSUP,
5544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5546 "sample action not supported");
5547 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5548 return rte_flow_error_set(error, EINVAL,
5549 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5550 "Multiple sample actions not "
5552 if (*action_flags & MLX5_FLOW_ACTION_METER)
5553 return rte_flow_error_set(error, EINVAL,
5554 RTE_FLOW_ERROR_TYPE_ACTION, action,
5555 "wrong action order, meter should "
5556 "be after sample action");
5557 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5558 return rte_flow_error_set(error, EINVAL,
5559 RTE_FLOW_ERROR_TYPE_ACTION, action,
5560 "wrong action order, jump should "
5561 "be after sample action");
5562 act = sample->actions;
5563 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5564 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5565 return rte_flow_error_set(error, ENOTSUP,
5566 RTE_FLOW_ERROR_TYPE_ACTION,
5567 act, "too many actions");
5568 switch (act->type) {
5569 case RTE_FLOW_ACTION_TYPE_QUEUE:
5570 ret = mlx5_flow_validate_action_queue(act,
5576 queue_index = ((const struct rte_flow_action_queue *)
5577 (act->conf))->index;
5578 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5581 case RTE_FLOW_ACTION_TYPE_RSS:
5582 *sample_rss = act->conf;
5583 ret = mlx5_flow_validate_action_rss(act,
5590 if (rss && *sample_rss &&
5591 ((*sample_rss)->level != rss->level ||
5592 (*sample_rss)->types != rss->types))
5593 return rte_flow_error_set(error, ENOTSUP,
5594 RTE_FLOW_ERROR_TYPE_ACTION,
5596 "Can't use the different RSS types "
5597 "or level in the same flow");
5598 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5599 queue_index = (*sample_rss)->queue[0];
5600 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5603 case RTE_FLOW_ACTION_TYPE_MARK:
5604 ret = flow_dv_validate_action_mark(dev, act,
5609 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5610 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5611 MLX5_FLOW_ACTION_MARK_EXT;
5613 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5616 case RTE_FLOW_ACTION_TYPE_COUNT:
5617 ret = flow_dv_validate_action_count
5618 (dev, false, *action_flags | sub_action_flags,
5623 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5624 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5627 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5628 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5629 ret = flow_dv_validate_action_port_id(dev,
5636 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5639 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5640 ret = flow_dv_validate_action_raw_encap_decap
5641 (dev, NULL, act->conf, attr, &sub_action_flags,
5642 &actions_n, action, item_flags, error);
5647 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5648 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5649 ret = flow_dv_validate_action_l2_encap(dev,
5655 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5659 return rte_flow_error_set(error, ENOTSUP,
5660 RTE_FLOW_ERROR_TYPE_ACTION,
5662 "Doesn't support optional "
5666 if (attr->ingress && !attr->transfer) {
5667 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5668 MLX5_FLOW_ACTION_RSS)))
5669 return rte_flow_error_set(error, EINVAL,
5670 RTE_FLOW_ERROR_TYPE_ACTION,
5672 "Ingress must has a dest "
5673 "QUEUE for Sample");
5674 } else if (attr->egress && !attr->transfer) {
5675 return rte_flow_error_set(error, ENOTSUP,
5676 RTE_FLOW_ERROR_TYPE_ACTION,
5678 "Sample Only support Ingress "
5680 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5681 MLX5_ASSERT(attr->transfer);
5682 if (sample->ratio > 1)
5683 return rte_flow_error_set(error, ENOTSUP,
5684 RTE_FLOW_ERROR_TYPE_ACTION,
5686 "E-Switch doesn't support "
5687 "any optional action "
5689 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5690 return rte_flow_error_set(error, ENOTSUP,
5691 RTE_FLOW_ERROR_TYPE_ACTION,
5693 "unsupported action QUEUE");
5694 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5695 return rte_flow_error_set(error, ENOTSUP,
5696 RTE_FLOW_ERROR_TYPE_ACTION,
5698 "unsupported action QUEUE");
5699 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5700 return rte_flow_error_set(error, EINVAL,
5701 RTE_FLOW_ERROR_TYPE_ACTION,
5703 "E-Switch must has a dest "
5704 "port for mirroring");
5705 if (!priv->config.hca_attr.reg_c_preserve &&
5706 priv->representor_id != UINT16_MAX)
5707 *fdb_mirror_limit = 1;
5709 /* Continue validation for Xcap actions.*/
5710 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5711 (queue_index == 0xFFFF ||
5712 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5713 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5714 MLX5_FLOW_XCAP_ACTIONS)
5715 return rte_flow_error_set(error, ENOTSUP,
5716 RTE_FLOW_ERROR_TYPE_ACTION,
5717 NULL, "encap and decap "
5718 "combination aren't "
5720 if (!attr->transfer && attr->ingress && (sub_action_flags &
5721 MLX5_FLOW_ACTION_ENCAP))
5722 return rte_flow_error_set(error, ENOTSUP,
5723 RTE_FLOW_ERROR_TYPE_ACTION,
5724 NULL, "encap is not supported"
5725 " for ingress traffic");
5731 * Find existing modify-header resource or create and register a new one.
5733 * @param dev[in, out]
5734 * Pointer to rte_eth_dev structure.
5735 * @param[in, out] resource
5736 * Pointer to modify-header resource.
5737 * @parm[in, out] dev_flow
5738 * Pointer to the dev_flow.
5740 * pointer to error structure.
5743 * 0 on success otherwise -errno and errno is set.
5746 flow_dv_modify_hdr_resource_register
5747 (struct rte_eth_dev *dev,
5748 struct mlx5_flow_dv_modify_hdr_resource *resource,
5749 struct mlx5_flow *dev_flow,
5750 struct rte_flow_error *error)
5752 struct mlx5_priv *priv = dev->data->dev_private;
5753 struct mlx5_dev_ctx_shared *sh = priv->sh;
5754 uint32_t key_len = sizeof(*resource) -
5755 offsetof(typeof(*resource), ft_type) +
5756 resource->actions_num * sizeof(resource->actions[0]);
5757 struct mlx5_list_entry *entry;
5758 struct mlx5_flow_cb_ctx ctx = {
5762 struct mlx5_hlist *modify_cmds;
5765 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5767 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5769 flow_dv_modify_create_cb,
5770 flow_dv_modify_match_cb,
5771 flow_dv_modify_remove_cb,
5772 flow_dv_modify_clone_cb,
5773 flow_dv_modify_clone_free_cb);
5774 if (unlikely(!modify_cmds))
5776 resource->root = !dev_flow->dv.group;
5777 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5779 return rte_flow_error_set(error, EOVERFLOW,
5780 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5781 "too many modify header items");
5782 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5783 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5786 resource = container_of(entry, typeof(*resource), entry);
5787 dev_flow->handle->dvh.modify_hdr = resource;
5792 * Get DV flow counter by index.
5795 * Pointer to the Ethernet device structure.
5797 * mlx5 flow counter index in the container.
5799 * mlx5 flow counter pool in the container.
5802 * Pointer to the counter, NULL otherwise.
5804 static struct mlx5_flow_counter *
5805 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5807 struct mlx5_flow_counter_pool **ppool)
5809 struct mlx5_priv *priv = dev->data->dev_private;
5810 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5811 struct mlx5_flow_counter_pool *pool;
5813 /* Decrease to original index and clear shared bit. */
5814 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5815 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5816 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5820 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5824 * Check the devx counter belongs to the pool.
5827 * Pointer to the counter pool.
5829 * The counter devx ID.
5832 * True if counter belongs to the pool, false otherwise.
5835 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5837 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5838 MLX5_COUNTERS_PER_POOL;
5840 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5846 * Get a pool by devx counter ID.
5849 * Pointer to the counter management.
5851 * The counter devx ID.
5854 * The counter pool pointer if exists, NULL otherwise,
5856 static struct mlx5_flow_counter_pool *
5857 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5860 struct mlx5_flow_counter_pool *pool = NULL;
5862 rte_spinlock_lock(&cmng->pool_update_sl);
5863 /* Check last used pool. */
5864 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5865 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5866 pool = cmng->pools[cmng->last_pool_idx];
5869 /* ID out of range means no suitable pool in the container. */
5870 if (id > cmng->max_id || id < cmng->min_id)
5873 * Find the pool from the end of the container, since mostly counter
5874 * ID is sequence increasing, and the last pool should be the needed
5879 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5881 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5887 rte_spinlock_unlock(&cmng->pool_update_sl);
5892 * Resize a counter container.
5895 * Pointer to the Ethernet device structure.
5898 * 0 on success, otherwise negative errno value and rte_errno is set.
5901 flow_dv_container_resize(struct rte_eth_dev *dev)
5903 struct mlx5_priv *priv = dev->data->dev_private;
5904 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5905 void *old_pools = cmng->pools;
5906 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5907 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5908 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5915 memcpy(pools, old_pools, cmng->n *
5916 sizeof(struct mlx5_flow_counter_pool *));
5918 cmng->pools = pools;
5920 mlx5_free(old_pools);
5925 * Query a devx flow counter.
5928 * Pointer to the Ethernet device structure.
5929 * @param[in] counter
5930 * Index to the flow counter.
5932 * The statistics value of packets.
5934 * The statistics value of bytes.
5937 * 0 on success, otherwise a negative errno value and rte_errno is set.
5940 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5943 struct mlx5_priv *priv = dev->data->dev_private;
5944 struct mlx5_flow_counter_pool *pool = NULL;
5945 struct mlx5_flow_counter *cnt;
5948 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5950 if (priv->sh->cmng.counter_fallback)
5951 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5952 0, pkts, bytes, 0, NULL, NULL, 0);
5953 rte_spinlock_lock(&pool->sl);
5958 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5959 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5960 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5962 rte_spinlock_unlock(&pool->sl);
5967 * Create and initialize a new counter pool.
5970 * Pointer to the Ethernet device structure.
5972 * The devX counter handle.
5974 * Whether the pool is for counter that was allocated for aging.
5975 * @param[in/out] cont_cur
5976 * Pointer to the container pointer, it will be update in pool resize.
5979 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5981 static struct mlx5_flow_counter_pool *
5982 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5985 struct mlx5_priv *priv = dev->data->dev_private;
5986 struct mlx5_flow_counter_pool *pool;
5987 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5988 bool fallback = priv->sh->cmng.counter_fallback;
5989 uint32_t size = sizeof(*pool);
5991 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5992 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5993 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5999 pool->is_aged = !!age;
6000 pool->query_gen = 0;
6001 pool->min_dcs = dcs;
6002 rte_spinlock_init(&pool->sl);
6003 rte_spinlock_init(&pool->csl);
6004 TAILQ_INIT(&pool->counters[0]);
6005 TAILQ_INIT(&pool->counters[1]);
6006 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6007 rte_spinlock_lock(&cmng->pool_update_sl);
6008 pool->index = cmng->n_valid;
6009 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6011 rte_spinlock_unlock(&cmng->pool_update_sl);
6014 cmng->pools[pool->index] = pool;
6016 if (unlikely(fallback)) {
6017 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6019 if (base < cmng->min_id)
6020 cmng->min_id = base;
6021 if (base > cmng->max_id)
6022 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6023 cmng->last_pool_idx = pool->index;
6025 rte_spinlock_unlock(&cmng->pool_update_sl);
6030 * Prepare a new counter and/or a new counter pool.
6033 * Pointer to the Ethernet device structure.
6034 * @param[out] cnt_free
6035 * Where to put the pointer of a new counter.
6037 * Whether the pool is for counter that was allocated for aging.
6040 * The counter pool pointer and @p cnt_free is set on success,
6041 * NULL otherwise and rte_errno is set.
6043 static struct mlx5_flow_counter_pool *
6044 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6045 struct mlx5_flow_counter **cnt_free,
6048 struct mlx5_priv *priv = dev->data->dev_private;
6049 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6050 struct mlx5_flow_counter_pool *pool;
6051 struct mlx5_counters tmp_tq;
6052 struct mlx5_devx_obj *dcs = NULL;
6053 struct mlx5_flow_counter *cnt;
6054 enum mlx5_counter_type cnt_type =
6055 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6056 bool fallback = priv->sh->cmng.counter_fallback;
6060 /* bulk_bitmap must be 0 for single counter allocation. */
6061 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6064 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6066 pool = flow_dv_pool_create(dev, dcs, age);
6068 mlx5_devx_cmd_destroy(dcs);
6072 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6073 cnt = MLX5_POOL_GET_CNT(pool, i);
6075 cnt->dcs_when_free = dcs;
6079 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6081 rte_errno = ENODATA;
6084 pool = flow_dv_pool_create(dev, dcs, age);
6086 mlx5_devx_cmd_destroy(dcs);
6089 TAILQ_INIT(&tmp_tq);
6090 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6091 cnt = MLX5_POOL_GET_CNT(pool, i);
6093 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6095 rte_spinlock_lock(&cmng->csl[cnt_type]);
6096 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6097 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6098 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6099 (*cnt_free)->pool = pool;
6104 * Allocate a flow counter.
6107 * Pointer to the Ethernet device structure.
6109 * Whether the counter was allocated for aging.
6112 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6115 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6117 struct mlx5_priv *priv = dev->data->dev_private;
6118 struct mlx5_flow_counter_pool *pool = NULL;
6119 struct mlx5_flow_counter *cnt_free = NULL;
6120 bool fallback = priv->sh->cmng.counter_fallback;
6121 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6122 enum mlx5_counter_type cnt_type =
6123 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6126 if (!priv->sh->devx) {
6127 rte_errno = ENOTSUP;
6130 /* Get free counters from container. */
6131 rte_spinlock_lock(&cmng->csl[cnt_type]);
6132 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6134 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6135 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6136 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6138 pool = cnt_free->pool;
6140 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6141 /* Create a DV counter action only in the first time usage. */
6142 if (!cnt_free->action) {
6144 struct mlx5_devx_obj *dcs;
6148 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6149 dcs = pool->min_dcs;
6152 dcs = cnt_free->dcs_when_free;
6154 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6161 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6162 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6163 /* Update the counter reset values. */
6164 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6167 if (!fallback && !priv->sh->cmng.query_thread_on)
6168 /* Start the asynchronous batch query by the host thread. */
6169 mlx5_set_query_alarm(priv->sh);
6171 * When the count action isn't shared (by ID), shared_info field is
6172 * used for indirect action API's refcnt.
6173 * When the counter action is not shared neither by ID nor by indirect
6174 * action API, shared info must be 1.
6176 cnt_free->shared_info.refcnt = 1;
6180 cnt_free->pool = pool;
6182 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6183 rte_spinlock_lock(&cmng->csl[cnt_type]);
6184 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6185 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6191 * Get age param from counter index.
6194 * Pointer to the Ethernet device structure.
6195 * @param[in] counter
6196 * Index to the counter handler.
6199 * The aging parameter specified for the counter index.
6201 static struct mlx5_age_param*
6202 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6205 struct mlx5_flow_counter *cnt;
6206 struct mlx5_flow_counter_pool *pool = NULL;
6208 flow_dv_counter_get_by_idx(dev, counter, &pool);
6209 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6210 cnt = MLX5_POOL_GET_CNT(pool, counter);
6211 return MLX5_CNT_TO_AGE(cnt);
6215 * Remove a flow counter from aged counter list.
6218 * Pointer to the Ethernet device structure.
6219 * @param[in] counter
6220 * Index to the counter handler.
6222 * Pointer to the counter handler.
6225 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6226 uint32_t counter, struct mlx5_flow_counter *cnt)
6228 struct mlx5_age_info *age_info;
6229 struct mlx5_age_param *age_param;
6230 struct mlx5_priv *priv = dev->data->dev_private;
6231 uint16_t expected = AGE_CANDIDATE;
6233 age_info = GET_PORT_AGE_INFO(priv);
6234 age_param = flow_dv_counter_idx_get_age(dev, counter);
6235 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6236 AGE_FREE, false, __ATOMIC_RELAXED,
6237 __ATOMIC_RELAXED)) {
6239 * We need the lock even it is age timeout,
6240 * since counter may still in process.
6242 rte_spinlock_lock(&age_info->aged_sl);
6243 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6244 rte_spinlock_unlock(&age_info->aged_sl);
6245 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6250 * Release a flow counter.
6253 * Pointer to the Ethernet device structure.
6254 * @param[in] counter
6255 * Index to the counter handler.
6258 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6260 struct mlx5_priv *priv = dev->data->dev_private;
6261 struct mlx5_flow_counter_pool *pool = NULL;
6262 struct mlx5_flow_counter *cnt;
6263 enum mlx5_counter_type cnt_type;
6267 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6269 if (pool->is_aged) {
6270 flow_dv_counter_remove_from_age(dev, counter, cnt);
6273 * If the counter action is shared by indirect action API,
6274 * the atomic function reduces its references counter.
6275 * If after the reduction the action is still referenced, the
6276 * function returns here and does not release it.
6277 * When the counter action is not shared by
6278 * indirect action API, shared info is 1 before the reduction,
6279 * so this condition is failed and function doesn't return here.
6281 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6287 * Put the counter back to list to be updated in none fallback mode.
6288 * Currently, we are using two list alternately, while one is in query,
6289 * add the freed counter to the other list based on the pool query_gen
6290 * value. After query finishes, add counter the list to the global
6291 * container counter list. The list changes while query starts. In
6292 * this case, lock will not be needed as query callback and release
6293 * function both operate with the different list.
6295 if (!priv->sh->cmng.counter_fallback) {
6296 rte_spinlock_lock(&pool->csl);
6297 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6298 rte_spinlock_unlock(&pool->csl);
6300 cnt->dcs_when_free = cnt->dcs_when_active;
6301 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6302 MLX5_COUNTER_TYPE_ORIGIN;
6303 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6304 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6306 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6311 * Resize a meter id container.
6314 * Pointer to the Ethernet device structure.
6317 * 0 on success, otherwise negative errno value and rte_errno is set.
6320 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6322 struct mlx5_priv *priv = dev->data->dev_private;
6323 struct mlx5_aso_mtr_pools_mng *pools_mng =
6324 &priv->sh->mtrmng->pools_mng;
6325 void *old_pools = pools_mng->pools;
6326 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6327 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6328 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6335 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6340 memcpy(pools, old_pools, pools_mng->n *
6341 sizeof(struct mlx5_aso_mtr_pool *));
6342 pools_mng->n = resize;
6343 pools_mng->pools = pools;
6345 mlx5_free(old_pools);
6350 * Prepare a new meter and/or a new meter pool.
6353 * Pointer to the Ethernet device structure.
6354 * @param[out] mtr_free
6355 * Where to put the pointer of a new meter.g.
6358 * The meter pool pointer and @mtr_free is set on success,
6359 * NULL otherwise and rte_errno is set.
6361 static struct mlx5_aso_mtr_pool *
6362 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6364 struct mlx5_priv *priv = dev->data->dev_private;
6365 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6366 struct mlx5_aso_mtr_pool *pool = NULL;
6367 struct mlx5_devx_obj *dcs = NULL;
6369 uint32_t log_obj_size;
6371 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6372 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6373 priv->sh->cdev->pdn,
6376 rte_errno = ENODATA;
6379 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6382 claim_zero(mlx5_devx_cmd_destroy(dcs));
6385 pool->devx_obj = dcs;
6386 pool->index = pools_mng->n_valid;
6387 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6389 claim_zero(mlx5_devx_cmd_destroy(dcs));
6392 pools_mng->pools[pool->index] = pool;
6393 pools_mng->n_valid++;
6394 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6395 pool->mtrs[i].offset = i;
6396 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6398 pool->mtrs[0].offset = 0;
6399 *mtr_free = &pool->mtrs[0];
6404 * Release a flow meter into pool.
6407 * Pointer to the Ethernet device structure.
6408 * @param[in] mtr_idx
6409 * Index to aso flow meter.
6412 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6414 struct mlx5_priv *priv = dev->data->dev_private;
6415 struct mlx5_aso_mtr_pools_mng *pools_mng =
6416 &priv->sh->mtrmng->pools_mng;
6417 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6419 MLX5_ASSERT(aso_mtr);
6420 rte_spinlock_lock(&pools_mng->mtrsl);
6421 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6422 aso_mtr->state = ASO_METER_FREE;
6423 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6424 rte_spinlock_unlock(&pools_mng->mtrsl);
6428 * Allocate a aso flow meter.
6431 * Pointer to the Ethernet device structure.
6434 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6437 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6439 struct mlx5_priv *priv = dev->data->dev_private;
6440 struct mlx5_aso_mtr *mtr_free = NULL;
6441 struct mlx5_aso_mtr_pools_mng *pools_mng =
6442 &priv->sh->mtrmng->pools_mng;
6443 struct mlx5_aso_mtr_pool *pool;
6444 uint32_t mtr_idx = 0;
6446 if (!priv->sh->devx) {
6447 rte_errno = ENOTSUP;
6450 /* Allocate the flow meter memory. */
6451 /* Get free meters from management. */
6452 rte_spinlock_lock(&pools_mng->mtrsl);
6453 mtr_free = LIST_FIRST(&pools_mng->meters);
6455 LIST_REMOVE(mtr_free, next);
6456 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6457 rte_spinlock_unlock(&pools_mng->mtrsl);
6460 mtr_free->state = ASO_METER_WAIT;
6461 rte_spinlock_unlock(&pools_mng->mtrsl);
6462 pool = container_of(mtr_free,
6463 struct mlx5_aso_mtr_pool,
6464 mtrs[mtr_free->offset]);
6465 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6466 if (!mtr_free->fm.meter_action) {
6467 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6468 struct rte_flow_error error;
6471 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6472 mtr_free->fm.meter_action =
6473 mlx5_glue->dv_create_flow_action_aso
6474 (priv->sh->rx_domain,
6475 pool->devx_obj->obj,
6477 (1 << MLX5_FLOW_COLOR_GREEN),
6479 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6480 if (!mtr_free->fm.meter_action) {
6481 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6489 * Verify the @p attributes will be correctly understood by the NIC and store
6490 * them in the @p flow if everything is correct.
6493 * Pointer to dev struct.
6494 * @param[in] attributes
6495 * Pointer to flow attributes
6496 * @param[in] external
6497 * This flow rule is created by request external to PMD.
6499 * Pointer to error structure.
6502 * - 0 on success and non root table.
6503 * - 1 on success and root table.
6504 * - a negative errno value otherwise and rte_errno is set.
6507 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6508 const struct mlx5_flow_tunnel *tunnel,
6509 const struct rte_flow_attr *attributes,
6510 const struct flow_grp_info *grp_info,
6511 struct rte_flow_error *error)
6513 struct mlx5_priv *priv = dev->data->dev_private;
6514 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6517 #ifndef HAVE_MLX5DV_DR
6518 RTE_SET_USED(tunnel);
6519 RTE_SET_USED(grp_info);
6520 if (attributes->group)
6521 return rte_flow_error_set(error, ENOTSUP,
6522 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6524 "groups are not supported");
6528 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6533 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6535 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6536 attributes->priority > lowest_priority)
6537 return rte_flow_error_set(error, ENOTSUP,
6538 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6540 "priority out of range");
6541 if (attributes->transfer) {
6542 if (!priv->config.dv_esw_en)
6543 return rte_flow_error_set
6545 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6546 "E-Switch dr is not supported");
6547 if (!(priv->representor || priv->master))
6548 return rte_flow_error_set
6549 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6550 NULL, "E-Switch configuration can only be"
6551 " done by a master or a representor device");
6552 if (attributes->egress)
6553 return rte_flow_error_set
6555 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6556 "egress is not supported");
6558 if (!(attributes->egress ^ attributes->ingress))
6559 return rte_flow_error_set(error, ENOTSUP,
6560 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6561 "must specify exactly one of "
6562 "ingress or egress");
6567 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6568 int64_t pattern_flags, uint64_t l3_flags,
6569 uint64_t l4_flags, uint64_t ip4_flag,
6570 struct rte_flow_error *error)
6572 if (mask->l3_ok && !(pattern_flags & l3_flags))
6573 return rte_flow_error_set(error, EINVAL,
6574 RTE_FLOW_ERROR_TYPE_ITEM,
6575 NULL, "missing L3 protocol");
6577 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6578 return rte_flow_error_set(error, EINVAL,
6579 RTE_FLOW_ERROR_TYPE_ITEM,
6580 NULL, "missing IPv4 protocol");
6582 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6583 return rte_flow_error_set(error, EINVAL,
6584 RTE_FLOW_ERROR_TYPE_ITEM,
6585 NULL, "missing L4 protocol");
6591 flow_dv_validate_item_integrity_post(const struct
6592 rte_flow_item *integrity_items[2],
6593 int64_t pattern_flags,
6594 struct rte_flow_error *error)
6596 const struct rte_flow_item_integrity *mask;
6599 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6600 mask = (typeof(mask))integrity_items[0]->mask;
6601 ret = validate_integrity_bits(mask, pattern_flags,
6602 MLX5_FLOW_LAYER_OUTER_L3,
6603 MLX5_FLOW_LAYER_OUTER_L4,
6604 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6609 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6610 mask = (typeof(mask))integrity_items[1]->mask;
6611 ret = validate_integrity_bits(mask, pattern_flags,
6612 MLX5_FLOW_LAYER_INNER_L3,
6613 MLX5_FLOW_LAYER_INNER_L4,
6614 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6623 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6624 const struct rte_flow_item *integrity_item,
6625 uint64_t pattern_flags, uint64_t *last_item,
6626 const struct rte_flow_item *integrity_items[2],
6627 struct rte_flow_error *error)
6629 struct mlx5_priv *priv = dev->data->dev_private;
6630 const struct rte_flow_item_integrity *mask = (typeof(mask))
6631 integrity_item->mask;
6632 const struct rte_flow_item_integrity *spec = (typeof(spec))
6633 integrity_item->spec;
6635 if (!priv->config.hca_attr.pkt_integrity_match)
6636 return rte_flow_error_set(error, ENOTSUP,
6637 RTE_FLOW_ERROR_TYPE_ITEM,
6639 "packet integrity integrity_item not supported");
6641 return rte_flow_error_set(error, ENOTSUP,
6642 RTE_FLOW_ERROR_TYPE_ITEM,
6644 "no spec for integrity item");
6646 mask = &rte_flow_item_integrity_mask;
6647 if (!mlx5_validate_integrity_item(mask))
6648 return rte_flow_error_set(error, ENOTSUP,
6649 RTE_FLOW_ERROR_TYPE_ITEM,
6651 "unsupported integrity filter");
6652 if (spec->level > 1) {
6653 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6654 return rte_flow_error_set
6656 RTE_FLOW_ERROR_TYPE_ITEM,
6657 NULL, "multiple inner integrity items not supported");
6658 integrity_items[1] = integrity_item;
6659 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6661 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6662 return rte_flow_error_set
6664 RTE_FLOW_ERROR_TYPE_ITEM,
6665 NULL, "multiple outer integrity items not supported");
6666 integrity_items[0] = integrity_item;
6667 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6673 * Internal validation function. For validating both actions and items.
6676 * Pointer to the rte_eth_dev structure.
6678 * Pointer to the flow attributes.
6680 * Pointer to the list of items.
6681 * @param[in] actions
6682 * Pointer to the list of actions.
6683 * @param[in] external
6684 * This flow rule is created by request external to PMD.
6685 * @param[in] hairpin
6686 * Number of hairpin TX actions, 0 means classic flow.
6688 * Pointer to the error structure.
6691 * 0 on success, a negative errno value otherwise and rte_errno is set.
6694 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6695 const struct rte_flow_item items[],
6696 const struct rte_flow_action actions[],
6697 bool external, int hairpin, struct rte_flow_error *error)
6700 uint64_t action_flags = 0;
6701 uint64_t item_flags = 0;
6702 uint64_t last_item = 0;
6703 uint8_t next_protocol = 0xff;
6704 uint16_t ether_type = 0;
6706 uint8_t item_ipv6_proto = 0;
6707 int fdb_mirror_limit = 0;
6708 int modify_after_mirror = 0;
6709 const struct rte_flow_item *geneve_item = NULL;
6710 const struct rte_flow_item *gre_item = NULL;
6711 const struct rte_flow_item *gtp_item = NULL;
6712 const struct rte_flow_action_raw_decap *decap;
6713 const struct rte_flow_action_raw_encap *encap;
6714 const struct rte_flow_action_rss *rss = NULL;
6715 const struct rte_flow_action_rss *sample_rss = NULL;
6716 const struct rte_flow_action_count *sample_count = NULL;
6717 const struct rte_flow_item_tcp nic_tcp_mask = {
6720 .src_port = RTE_BE16(UINT16_MAX),
6721 .dst_port = RTE_BE16(UINT16_MAX),
6724 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6727 "\xff\xff\xff\xff\xff\xff\xff\xff"
6728 "\xff\xff\xff\xff\xff\xff\xff\xff",
6730 "\xff\xff\xff\xff\xff\xff\xff\xff"
6731 "\xff\xff\xff\xff\xff\xff\xff\xff",
6732 .vtc_flow = RTE_BE32(0xffffffff),
6738 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6742 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6746 .dummy[0] = 0xffffffff,
6749 struct mlx5_priv *priv = dev->data->dev_private;
6750 struct mlx5_dev_config *dev_conf = &priv->config;
6751 uint16_t queue_index = 0xFFFF;
6752 const struct rte_flow_item_vlan *vlan_m = NULL;
6753 uint32_t rw_act_num = 0;
6755 const struct mlx5_flow_tunnel *tunnel;
6756 enum mlx5_tof_rule_type tof_rule_type;
6757 struct flow_grp_info grp_info = {
6758 .external = !!external,
6759 .transfer = !!attr->transfer,
6760 .fdb_def_rule = !!priv->fdb_def_rule,
6761 .std_tbl_fix = true,
6763 const struct rte_eth_hairpin_conf *conf;
6764 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6765 const struct rte_flow_item *port_id_item = NULL;
6766 bool def_policy = false;
6767 uint16_t udp_dport = 0;
6771 tunnel = is_tunnel_offload_active(dev) ?
6772 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6774 if (priv->representor)
6775 return rte_flow_error_set
6777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6778 NULL, "decap not supported for VF representor");
6779 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6780 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6781 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6782 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6783 MLX5_FLOW_ACTION_DECAP;
6784 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6785 (dev, attr, tunnel, tof_rule_type);
6787 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6790 is_root = (uint64_t)ret;
6791 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6792 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6793 int type = items->type;
6795 if (!mlx5_flow_os_item_supported(type))
6796 return rte_flow_error_set(error, ENOTSUP,
6797 RTE_FLOW_ERROR_TYPE_ITEM,
6798 NULL, "item not supported");
6800 case RTE_FLOW_ITEM_TYPE_VOID:
6802 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6803 ret = flow_dv_validate_item_port_id
6804 (dev, items, attr, item_flags, error);
6807 last_item = MLX5_FLOW_ITEM_PORT_ID;
6808 port_id_item = items;
6810 case RTE_FLOW_ITEM_TYPE_ETH:
6811 ret = mlx5_flow_validate_item_eth(items, item_flags,
6815 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6816 MLX5_FLOW_LAYER_OUTER_L2;
6817 if (items->mask != NULL && items->spec != NULL) {
6819 ((const struct rte_flow_item_eth *)
6822 ((const struct rte_flow_item_eth *)
6824 ether_type = rte_be_to_cpu_16(ether_type);
6829 case RTE_FLOW_ITEM_TYPE_VLAN:
6830 ret = flow_dv_validate_item_vlan(items, item_flags,
6834 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6835 MLX5_FLOW_LAYER_OUTER_VLAN;
6836 if (items->mask != NULL && items->spec != NULL) {
6838 ((const struct rte_flow_item_vlan *)
6839 items->spec)->inner_type;
6841 ((const struct rte_flow_item_vlan *)
6842 items->mask)->inner_type;
6843 ether_type = rte_be_to_cpu_16(ether_type);
6847 /* Store outer VLAN mask for of_push_vlan action. */
6849 vlan_m = items->mask;
6851 case RTE_FLOW_ITEM_TYPE_IPV4:
6852 mlx5_flow_tunnel_ip_check(items, next_protocol,
6853 &item_flags, &tunnel);
6854 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6855 last_item, ether_type,
6859 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6860 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6861 if (items->mask != NULL &&
6862 ((const struct rte_flow_item_ipv4 *)
6863 items->mask)->hdr.next_proto_id) {
6865 ((const struct rte_flow_item_ipv4 *)
6866 (items->spec))->hdr.next_proto_id;
6868 ((const struct rte_flow_item_ipv4 *)
6869 (items->mask))->hdr.next_proto_id;
6871 /* Reset for inner layer. */
6872 next_protocol = 0xff;
6875 case RTE_FLOW_ITEM_TYPE_IPV6:
6876 mlx5_flow_tunnel_ip_check(items, next_protocol,
6877 &item_flags, &tunnel);
6878 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6885 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6886 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6887 if (items->mask != NULL &&
6888 ((const struct rte_flow_item_ipv6 *)
6889 items->mask)->hdr.proto) {
6891 ((const struct rte_flow_item_ipv6 *)
6892 items->spec)->hdr.proto;
6894 ((const struct rte_flow_item_ipv6 *)
6895 items->spec)->hdr.proto;
6897 ((const struct rte_flow_item_ipv6 *)
6898 items->mask)->hdr.proto;
6900 /* Reset for inner layer. */
6901 next_protocol = 0xff;
6904 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6905 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6910 last_item = tunnel ?
6911 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6912 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6913 if (items->mask != NULL &&
6914 ((const struct rte_flow_item_ipv6_frag_ext *)
6915 items->mask)->hdr.next_header) {
6917 ((const struct rte_flow_item_ipv6_frag_ext *)
6918 items->spec)->hdr.next_header;
6920 ((const struct rte_flow_item_ipv6_frag_ext *)
6921 items->mask)->hdr.next_header;
6923 /* Reset for inner layer. */
6924 next_protocol = 0xff;
6927 case RTE_FLOW_ITEM_TYPE_TCP:
6928 ret = mlx5_flow_validate_item_tcp
6935 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6936 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6938 case RTE_FLOW_ITEM_TYPE_UDP:
6939 ret = mlx5_flow_validate_item_udp(items, item_flags,
6942 const struct rte_flow_item_udp *spec = items->spec;
6943 const struct rte_flow_item_udp *mask = items->mask;
6945 mask = &rte_flow_item_udp_mask;
6947 udp_dport = rte_be_to_cpu_16
6948 (spec->hdr.dst_port &
6949 mask->hdr.dst_port);
6952 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6953 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6955 case RTE_FLOW_ITEM_TYPE_GRE:
6956 ret = mlx5_flow_validate_item_gre(items, item_flags,
6957 next_protocol, error);
6961 last_item = MLX5_FLOW_LAYER_GRE;
6963 case RTE_FLOW_ITEM_TYPE_NVGRE:
6964 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6969 last_item = MLX5_FLOW_LAYER_NVGRE;
6971 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6972 ret = mlx5_flow_validate_item_gre_key
6973 (items, item_flags, gre_item, error);
6976 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6978 case RTE_FLOW_ITEM_TYPE_VXLAN:
6979 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
6984 last_item = MLX5_FLOW_LAYER_VXLAN;
6986 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6987 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6992 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6994 case RTE_FLOW_ITEM_TYPE_GENEVE:
6995 ret = mlx5_flow_validate_item_geneve(items,
7000 geneve_item = items;
7001 last_item = MLX5_FLOW_LAYER_GENEVE;
7003 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7004 ret = mlx5_flow_validate_item_geneve_opt(items,
7011 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7013 case RTE_FLOW_ITEM_TYPE_MPLS:
7014 ret = mlx5_flow_validate_item_mpls(dev, items,
7019 last_item = MLX5_FLOW_LAYER_MPLS;
7022 case RTE_FLOW_ITEM_TYPE_MARK:
7023 ret = flow_dv_validate_item_mark(dev, items, attr,
7027 last_item = MLX5_FLOW_ITEM_MARK;
7029 case RTE_FLOW_ITEM_TYPE_META:
7030 ret = flow_dv_validate_item_meta(dev, items, attr,
7034 last_item = MLX5_FLOW_ITEM_METADATA;
7036 case RTE_FLOW_ITEM_TYPE_ICMP:
7037 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7042 last_item = MLX5_FLOW_LAYER_ICMP;
7044 case RTE_FLOW_ITEM_TYPE_ICMP6:
7045 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7050 item_ipv6_proto = IPPROTO_ICMPV6;
7051 last_item = MLX5_FLOW_LAYER_ICMP6;
7053 case RTE_FLOW_ITEM_TYPE_TAG:
7054 ret = flow_dv_validate_item_tag(dev, items,
7058 last_item = MLX5_FLOW_ITEM_TAG;
7060 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7061 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7063 case RTE_FLOW_ITEM_TYPE_GTP:
7064 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7069 last_item = MLX5_FLOW_LAYER_GTP;
7071 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7072 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7077 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7079 case RTE_FLOW_ITEM_TYPE_ECPRI:
7080 /* Capacity will be checked in the translate stage. */
7081 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7088 last_item = MLX5_FLOW_LAYER_ECPRI;
7090 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7091 ret = flow_dv_validate_item_integrity(dev, items,
7099 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7100 ret = flow_dv_validate_item_aso_ct(dev, items,
7101 &item_flags, error);
7105 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7106 /* tunnel offload item was processed before
7107 * list it here as a supported type
7111 return rte_flow_error_set(error, ENOTSUP,
7112 RTE_FLOW_ERROR_TYPE_ITEM,
7113 NULL, "item not supported");
7115 item_flags |= last_item;
7117 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7118 ret = flow_dv_validate_item_integrity_post(integrity_items,
7123 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7124 int type = actions->type;
7125 bool shared_count = false;
7127 if (!mlx5_flow_os_action_supported(type))
7128 return rte_flow_error_set(error, ENOTSUP,
7129 RTE_FLOW_ERROR_TYPE_ACTION,
7131 "action not supported");
7132 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7133 return rte_flow_error_set(error, ENOTSUP,
7134 RTE_FLOW_ERROR_TYPE_ACTION,
7135 actions, "too many actions");
7137 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7138 return rte_flow_error_set(error, ENOTSUP,
7139 RTE_FLOW_ERROR_TYPE_ACTION,
7140 NULL, "meter action with policy "
7141 "must be the last action");
7143 case RTE_FLOW_ACTION_TYPE_VOID:
7145 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7146 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7147 ret = flow_dv_validate_action_port_id(dev,
7154 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7157 case RTE_FLOW_ACTION_TYPE_FLAG:
7158 ret = flow_dv_validate_action_flag(dev, action_flags,
7162 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7163 /* Count all modify-header actions as one. */
7164 if (!(action_flags &
7165 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7167 action_flags |= MLX5_FLOW_ACTION_FLAG |
7168 MLX5_FLOW_ACTION_MARK_EXT;
7169 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7170 modify_after_mirror = 1;
7173 action_flags |= MLX5_FLOW_ACTION_FLAG;
7176 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7178 case RTE_FLOW_ACTION_TYPE_MARK:
7179 ret = flow_dv_validate_action_mark(dev, actions,
7184 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7185 /* Count all modify-header actions as one. */
7186 if (!(action_flags &
7187 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7189 action_flags |= MLX5_FLOW_ACTION_MARK |
7190 MLX5_FLOW_ACTION_MARK_EXT;
7191 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7192 modify_after_mirror = 1;
7194 action_flags |= MLX5_FLOW_ACTION_MARK;
7197 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7199 case RTE_FLOW_ACTION_TYPE_SET_META:
7200 ret = flow_dv_validate_action_set_meta(dev, actions,
7205 /* Count all modify-header actions as one action. */
7206 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7208 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7209 modify_after_mirror = 1;
7210 action_flags |= MLX5_FLOW_ACTION_SET_META;
7211 rw_act_num += MLX5_ACT_NUM_SET_META;
7213 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7214 ret = flow_dv_validate_action_set_tag(dev, actions,
7219 /* Count all modify-header actions as one action. */
7220 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7222 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7223 modify_after_mirror = 1;
7224 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7225 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7227 case RTE_FLOW_ACTION_TYPE_DROP:
7228 ret = mlx5_flow_validate_action_drop(action_flags,
7232 action_flags |= MLX5_FLOW_ACTION_DROP;
7235 case RTE_FLOW_ACTION_TYPE_QUEUE:
7236 ret = mlx5_flow_validate_action_queue(actions,
7241 queue_index = ((const struct rte_flow_action_queue *)
7242 (actions->conf))->index;
7243 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7246 case RTE_FLOW_ACTION_TYPE_RSS:
7247 rss = actions->conf;
7248 ret = mlx5_flow_validate_action_rss(actions,
7254 if (rss && sample_rss &&
7255 (sample_rss->level != rss->level ||
7256 sample_rss->types != rss->types))
7257 return rte_flow_error_set(error, ENOTSUP,
7258 RTE_FLOW_ERROR_TYPE_ACTION,
7260 "Can't use the different RSS types "
7261 "or level in the same flow");
7262 if (rss != NULL && rss->queue_num)
7263 queue_index = rss->queue[0];
7264 action_flags |= MLX5_FLOW_ACTION_RSS;
7267 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7269 mlx5_flow_validate_action_default_miss(action_flags,
7273 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7276 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7277 shared_count = true;
7279 case RTE_FLOW_ACTION_TYPE_COUNT:
7280 ret = flow_dv_validate_action_count(dev, shared_count,
7285 action_flags |= MLX5_FLOW_ACTION_COUNT;
7288 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7289 if (flow_dv_validate_action_pop_vlan(dev,
7295 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7296 modify_after_mirror = 1;
7297 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7300 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7301 ret = flow_dv_validate_action_push_vlan(dev,
7308 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7309 modify_after_mirror = 1;
7310 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7313 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7314 ret = flow_dv_validate_action_set_vlan_pcp
7315 (action_flags, actions, error);
7318 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7319 modify_after_mirror = 1;
7320 /* Count PCP with push_vlan command. */
7321 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7323 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7324 ret = flow_dv_validate_action_set_vlan_vid
7325 (item_flags, action_flags,
7329 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7330 modify_after_mirror = 1;
7331 /* Count VID with push_vlan command. */
7332 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7333 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7335 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7336 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7337 ret = flow_dv_validate_action_l2_encap(dev,
7343 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7346 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7347 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7348 ret = flow_dv_validate_action_decap(dev, action_flags,
7349 actions, item_flags,
7353 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7354 modify_after_mirror = 1;
7355 action_flags |= MLX5_FLOW_ACTION_DECAP;
7358 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7359 ret = flow_dv_validate_action_raw_encap_decap
7360 (dev, NULL, actions->conf, attr, &action_flags,
7361 &actions_n, actions, item_flags, error);
7365 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7366 decap = actions->conf;
7367 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7369 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7373 encap = actions->conf;
7375 ret = flow_dv_validate_action_raw_encap_decap
7377 decap ? decap : &empty_decap, encap,
7378 attr, &action_flags, &actions_n,
7379 actions, item_flags, error);
7382 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7383 (action_flags & MLX5_FLOW_ACTION_DECAP))
7384 modify_after_mirror = 1;
7386 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7387 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7388 ret = flow_dv_validate_action_modify_mac(action_flags,
7394 /* Count all modify-header actions as one action. */
7395 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7397 action_flags |= actions->type ==
7398 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7399 MLX5_FLOW_ACTION_SET_MAC_SRC :
7400 MLX5_FLOW_ACTION_SET_MAC_DST;
7401 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7402 modify_after_mirror = 1;
7404 * Even if the source and destination MAC addresses have
7405 * overlap in the header with 4B alignment, the convert
7406 * function will handle them separately and 4 SW actions
7407 * will be created. And 2 actions will be added each
7408 * time no matter how many bytes of address will be set.
7410 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7412 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7413 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7414 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7420 /* Count all modify-header actions as one action. */
7421 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7423 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7424 modify_after_mirror = 1;
7425 action_flags |= actions->type ==
7426 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7427 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7428 MLX5_FLOW_ACTION_SET_IPV4_DST;
7429 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7431 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7432 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7433 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7439 if (item_ipv6_proto == IPPROTO_ICMPV6)
7440 return rte_flow_error_set(error, ENOTSUP,
7441 RTE_FLOW_ERROR_TYPE_ACTION,
7443 "Can't change header "
7444 "with ICMPv6 proto");
7445 /* Count all modify-header actions as one action. */
7446 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7448 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7449 modify_after_mirror = 1;
7450 action_flags |= actions->type ==
7451 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7452 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7453 MLX5_FLOW_ACTION_SET_IPV6_DST;
7454 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7456 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7457 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7458 ret = flow_dv_validate_action_modify_tp(action_flags,
7464 /* Count all modify-header actions as one action. */
7465 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7467 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7468 modify_after_mirror = 1;
7469 action_flags |= actions->type ==
7470 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7471 MLX5_FLOW_ACTION_SET_TP_SRC :
7472 MLX5_FLOW_ACTION_SET_TP_DST;
7473 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7475 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7476 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7477 ret = flow_dv_validate_action_modify_ttl(action_flags,
7483 /* Count all modify-header actions as one action. */
7484 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7486 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7487 modify_after_mirror = 1;
7488 action_flags |= actions->type ==
7489 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7490 MLX5_FLOW_ACTION_SET_TTL :
7491 MLX5_FLOW_ACTION_DEC_TTL;
7492 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7494 case RTE_FLOW_ACTION_TYPE_JUMP:
7495 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7501 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7503 return rte_flow_error_set(error, EINVAL,
7504 RTE_FLOW_ERROR_TYPE_ACTION,
7506 "sample and jump action combination is not supported");
7508 action_flags |= MLX5_FLOW_ACTION_JUMP;
7510 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7511 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7512 ret = flow_dv_validate_action_modify_tcp_seq
7519 /* Count all modify-header actions as one action. */
7520 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7522 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7523 modify_after_mirror = 1;
7524 action_flags |= actions->type ==
7525 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7526 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7527 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7528 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7530 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7531 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7532 ret = flow_dv_validate_action_modify_tcp_ack
7539 /* Count all modify-header actions as one action. */
7540 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7542 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7543 modify_after_mirror = 1;
7544 action_flags |= actions->type ==
7545 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7546 MLX5_FLOW_ACTION_INC_TCP_ACK :
7547 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7548 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7550 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7552 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7553 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7554 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7556 case RTE_FLOW_ACTION_TYPE_METER:
7557 ret = mlx5_flow_validate_action_meter(dev,
7565 action_flags |= MLX5_FLOW_ACTION_METER;
7568 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7570 /* Meter action will add one more TAG action. */
7571 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7573 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7574 if (!attr->transfer && !attr->group)
7575 return rte_flow_error_set(error, ENOTSUP,
7576 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7578 "Shared ASO age action is not supported for group 0");
7579 if (action_flags & MLX5_FLOW_ACTION_AGE)
7580 return rte_flow_error_set
7582 RTE_FLOW_ERROR_TYPE_ACTION,
7584 "duplicate age actions set");
7585 action_flags |= MLX5_FLOW_ACTION_AGE;
7588 case RTE_FLOW_ACTION_TYPE_AGE:
7589 ret = flow_dv_validate_action_age(action_flags,
7595 * Validate the regular AGE action (using counter)
7596 * mutual exclusion with share counter actions.
7598 if (!priv->sh->flow_hit_aso_en) {
7600 return rte_flow_error_set
7602 RTE_FLOW_ERROR_TYPE_ACTION,
7604 "old age and shared count combination is not supported");
7606 return rte_flow_error_set
7608 RTE_FLOW_ERROR_TYPE_ACTION,
7610 "old age action and count must be in the same sub flow");
7612 action_flags |= MLX5_FLOW_ACTION_AGE;
7615 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7616 ret = flow_dv_validate_action_modify_ipv4_dscp
7623 /* Count all modify-header actions as one action. */
7624 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7626 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7627 modify_after_mirror = 1;
7628 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7629 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7631 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7632 ret = flow_dv_validate_action_modify_ipv6_dscp
7639 /* Count all modify-header actions as one action. */
7640 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7642 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7643 modify_after_mirror = 1;
7644 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7645 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7647 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7648 ret = flow_dv_validate_action_sample(&action_flags,
7657 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7660 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7661 ret = flow_dv_validate_action_modify_field(dev,
7668 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7669 modify_after_mirror = 1;
7670 /* Count all modify-header actions as one action. */
7671 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7673 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7676 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7677 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7682 action_flags |= MLX5_FLOW_ACTION_CT;
7684 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7685 /* tunnel offload action was processed before
7686 * list it here as a supported type
7690 return rte_flow_error_set(error, ENOTSUP,
7691 RTE_FLOW_ERROR_TYPE_ACTION,
7693 "action not supported");
7697 * Validate actions in flow rules
7698 * - Explicit decap action is prohibited by the tunnel offload API.
7699 * - Drop action in tunnel steer rule is prohibited by the API.
7700 * - Application cannot use MARK action because it's value can mask
7701 * tunnel default miss nitification.
7702 * - JUMP in tunnel match rule has no support in current PMD
7704 * - TAG & META are reserved for future uses.
7706 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7707 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7708 MLX5_FLOW_ACTION_MARK |
7709 MLX5_FLOW_ACTION_SET_TAG |
7710 MLX5_FLOW_ACTION_SET_META |
7711 MLX5_FLOW_ACTION_DROP;
7713 if (action_flags & bad_actions_mask)
7714 return rte_flow_error_set
7716 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7717 "Invalid RTE action in tunnel "
7719 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7720 return rte_flow_error_set
7722 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7723 "tunnel set decap rule must terminate "
7726 return rte_flow_error_set
7728 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7729 "tunnel flows for ingress traffic only");
7731 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7732 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7733 MLX5_FLOW_ACTION_MARK |
7734 MLX5_FLOW_ACTION_SET_TAG |
7735 MLX5_FLOW_ACTION_SET_META;
7737 if (action_flags & bad_actions_mask)
7738 return rte_flow_error_set
7740 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7741 "Invalid RTE action in tunnel "
7745 * Validate the drop action mutual exclusion with other actions.
7746 * Drop action is mutually-exclusive with any other action, except for
7748 * Drop action compatibility with tunnel offload was already validated.
7750 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7751 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7752 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7753 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7754 return rte_flow_error_set(error, EINVAL,
7755 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7756 "Drop action is mutually-exclusive "
7757 "with any other action, except for "
7759 /* Eswitch has few restrictions on using items and actions */
7760 if (attr->transfer) {
7761 if (!mlx5_flow_ext_mreg_supported(dev) &&
7762 action_flags & MLX5_FLOW_ACTION_FLAG)
7763 return rte_flow_error_set(error, ENOTSUP,
7764 RTE_FLOW_ERROR_TYPE_ACTION,
7766 "unsupported action FLAG");
7767 if (!mlx5_flow_ext_mreg_supported(dev) &&
7768 action_flags & MLX5_FLOW_ACTION_MARK)
7769 return rte_flow_error_set(error, ENOTSUP,
7770 RTE_FLOW_ERROR_TYPE_ACTION,
7772 "unsupported action MARK");
7773 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7774 return rte_flow_error_set(error, ENOTSUP,
7775 RTE_FLOW_ERROR_TYPE_ACTION,
7777 "unsupported action QUEUE");
7778 if (action_flags & MLX5_FLOW_ACTION_RSS)
7779 return rte_flow_error_set(error, ENOTSUP,
7780 RTE_FLOW_ERROR_TYPE_ACTION,
7782 "unsupported action RSS");
7783 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7784 return rte_flow_error_set(error, EINVAL,
7785 RTE_FLOW_ERROR_TYPE_ACTION,
7787 "no fate action is found");
7789 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7790 return rte_flow_error_set(error, EINVAL,
7791 RTE_FLOW_ERROR_TYPE_ACTION,
7793 "no fate action is found");
7796 * Continue validation for Xcap and VLAN actions.
7797 * If hairpin is working in explicit TX rule mode, there is no actions
7798 * splitting and the validation of hairpin ingress flow should be the
7799 * same as other standard flows.
7801 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7802 MLX5_FLOW_VLAN_ACTIONS)) &&
7803 (queue_index == 0xFFFF ||
7804 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7805 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7806 conf->tx_explicit != 0))) {
7807 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7808 MLX5_FLOW_XCAP_ACTIONS)
7809 return rte_flow_error_set(error, ENOTSUP,
7810 RTE_FLOW_ERROR_TYPE_ACTION,
7811 NULL, "encap and decap "
7812 "combination aren't supported");
7813 if (!attr->transfer && attr->ingress) {
7814 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7815 return rte_flow_error_set
7817 RTE_FLOW_ERROR_TYPE_ACTION,
7818 NULL, "encap is not supported"
7819 " for ingress traffic");
7820 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7821 return rte_flow_error_set
7823 RTE_FLOW_ERROR_TYPE_ACTION,
7824 NULL, "push VLAN action not "
7825 "supported for ingress");
7826 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7827 MLX5_FLOW_VLAN_ACTIONS)
7828 return rte_flow_error_set
7830 RTE_FLOW_ERROR_TYPE_ACTION,
7831 NULL, "no support for "
7832 "multiple VLAN actions");
7835 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7836 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7837 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7839 return rte_flow_error_set
7841 RTE_FLOW_ERROR_TYPE_ACTION,
7842 NULL, "fate action not supported for "
7843 "meter with policy");
7845 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7846 return rte_flow_error_set
7848 RTE_FLOW_ERROR_TYPE_ACTION,
7849 NULL, "modify header action in egress "
7850 "cannot be done before meter action");
7851 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7852 return rte_flow_error_set
7854 RTE_FLOW_ERROR_TYPE_ACTION,
7855 NULL, "encap action in egress "
7856 "cannot be done before meter action");
7857 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7858 return rte_flow_error_set
7860 RTE_FLOW_ERROR_TYPE_ACTION,
7861 NULL, "push vlan action in egress "
7862 "cannot be done before meter action");
7866 * Hairpin flow will add one more TAG action in TX implicit mode.
7867 * In TX explicit mode, there will be no hairpin flow ID.
7870 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7871 /* extra metadata enabled: one more TAG action will be add. */
7872 if (dev_conf->dv_flow_en &&
7873 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7874 mlx5_flow_ext_mreg_supported(dev))
7875 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7877 flow_dv_modify_hdr_action_max(dev, is_root)) {
7878 return rte_flow_error_set(error, ENOTSUP,
7879 RTE_FLOW_ERROR_TYPE_ACTION,
7880 NULL, "too many header modify"
7881 " actions to support");
7883 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7884 if (fdb_mirror_limit && modify_after_mirror)
7885 return rte_flow_error_set(error, EINVAL,
7886 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7887 "sample before modify action is not supported");
7892 * Internal preparation function. Allocates the DV flow size,
7893 * this size is constant.
7896 * Pointer to the rte_eth_dev structure.
7898 * Pointer to the flow attributes.
7900 * Pointer to the list of items.
7901 * @param[in] actions
7902 * Pointer to the list of actions.
7904 * Pointer to the error structure.
7907 * Pointer to mlx5_flow object on success,
7908 * otherwise NULL and rte_errno is set.
7910 static struct mlx5_flow *
7911 flow_dv_prepare(struct rte_eth_dev *dev,
7912 const struct rte_flow_attr *attr __rte_unused,
7913 const struct rte_flow_item items[] __rte_unused,
7914 const struct rte_flow_action actions[] __rte_unused,
7915 struct rte_flow_error *error)
7917 uint32_t handle_idx = 0;
7918 struct mlx5_flow *dev_flow;
7919 struct mlx5_flow_handle *dev_handle;
7920 struct mlx5_priv *priv = dev->data->dev_private;
7921 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7924 wks->skip_matcher_reg = 0;
7926 wks->final_policy = NULL;
7927 /* In case of corrupting the memory. */
7928 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7929 rte_flow_error_set(error, ENOSPC,
7930 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7931 "not free temporary device flow");
7934 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7937 rte_flow_error_set(error, ENOMEM,
7938 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7939 "not enough memory to create flow handle");
7942 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7943 dev_flow = &wks->flows[wks->flow_idx++];
7944 memset(dev_flow, 0, sizeof(*dev_flow));
7945 dev_flow->handle = dev_handle;
7946 dev_flow->handle_idx = handle_idx;
7947 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
7948 dev_flow->ingress = attr->ingress;
7949 dev_flow->dv.transfer = attr->transfer;
7953 #ifdef RTE_LIBRTE_MLX5_DEBUG
7955 * Sanity check for match mask and value. Similar to check_valid_spec() in
7956 * kernel driver. If unmasked bit is present in value, it returns failure.
7959 * pointer to match mask buffer.
7960 * @param match_value
7961 * pointer to match value buffer.
7964 * 0 if valid, -EINVAL otherwise.
7967 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7969 uint8_t *m = match_mask;
7970 uint8_t *v = match_value;
7973 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7976 "match_value differs from match_criteria"
7977 " %p[%u] != %p[%u]",
7978 match_value, i, match_mask, i);
7987 * Add match of ip_version.
7991 * @param[in] headers_v
7992 * Values header pointer.
7993 * @param[in] headers_m
7994 * Masks header pointer.
7995 * @param[in] ip_version
7996 * The IP version to set.
7999 flow_dv_set_match_ip_version(uint32_t group,
8005 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8007 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8009 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8010 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8011 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8015 * Add Ethernet item to matcher and to the value.
8017 * @param[in, out] matcher
8019 * @param[in, out] key
8020 * Flow matcher value.
8022 * Flow pattern to translate.
8024 * Item is inner pattern.
8027 flow_dv_translate_item_eth(void *matcher, void *key,
8028 const struct rte_flow_item *item, int inner,
8031 const struct rte_flow_item_eth *eth_m = item->mask;
8032 const struct rte_flow_item_eth *eth_v = item->spec;
8033 const struct rte_flow_item_eth nic_mask = {
8034 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8035 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8036 .type = RTE_BE16(0xffff),
8049 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8051 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8053 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8055 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8057 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8058 ð_m->dst, sizeof(eth_m->dst));
8059 /* The value must be in the range of the mask. */
8060 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8061 for (i = 0; i < sizeof(eth_m->dst); ++i)
8062 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8063 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8064 ð_m->src, sizeof(eth_m->src));
8065 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8066 /* The value must be in the range of the mask. */
8067 for (i = 0; i < sizeof(eth_m->dst); ++i)
8068 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8070 * HW supports match on one Ethertype, the Ethertype following the last
8071 * VLAN tag of the packet (see PRM).
8072 * Set match on ethertype only if ETH header is not followed by VLAN.
8073 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8074 * ethertype, and use ip_version field instead.
8075 * eCPRI over Ether layer will use type value 0xAEFE.
8077 if (eth_m->type == 0xFFFF) {
8078 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8079 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8080 switch (eth_v->type) {
8081 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8082 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8084 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8085 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8086 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8088 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8089 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8091 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8092 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8098 if (eth_m->has_vlan) {
8099 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8100 if (eth_v->has_vlan) {
8102 * Here, when also has_more_vlan field in VLAN item is
8103 * not set, only single-tagged packets will be matched.
8105 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8109 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8110 rte_be_to_cpu_16(eth_m->type));
8111 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8112 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8116 * Add VLAN item to matcher and to the value.
8118 * @param[in, out] dev_flow
8120 * @param[in, out] matcher
8122 * @param[in, out] key
8123 * Flow matcher value.
8125 * Flow pattern to translate.
8127 * Item is inner pattern.
8130 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8131 void *matcher, void *key,
8132 const struct rte_flow_item *item,
8133 int inner, uint32_t group)
8135 const struct rte_flow_item_vlan *vlan_m = item->mask;
8136 const struct rte_flow_item_vlan *vlan_v = item->spec;
8143 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8145 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8147 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8149 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8151 * This is workaround, masks are not supported,
8152 * and pre-validated.
8155 dev_flow->handle->vf_vlan.tag =
8156 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8159 * When VLAN item exists in flow, mark packet as tagged,
8160 * even if TCI is not specified.
8162 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8163 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8164 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8169 vlan_m = &rte_flow_item_vlan_mask;
8170 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8171 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8172 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8173 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8174 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8175 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8176 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8177 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8179 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8180 * ethertype, and use ip_version field instead.
8182 if (vlan_m->inner_type == 0xFFFF) {
8183 switch (vlan_v->inner_type) {
8184 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8185 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8186 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8187 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8189 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8190 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8192 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8193 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8199 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8200 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8201 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8202 /* Only one vlan_tag bit can be set. */
8203 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8206 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8207 rte_be_to_cpu_16(vlan_m->inner_type));
8208 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8209 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8213 * Add IPV4 item to matcher and to the value.
8215 * @param[in, out] matcher
8217 * @param[in, out] key
8218 * Flow matcher value.
8220 * Flow pattern to translate.
8222 * Item is inner pattern.
8224 * The group to insert the rule.
8227 flow_dv_translate_item_ipv4(void *matcher, void *key,
8228 const struct rte_flow_item *item,
8229 int inner, uint32_t group)
8231 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8232 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8233 const struct rte_flow_item_ipv4 nic_mask = {
8235 .src_addr = RTE_BE32(0xffffffff),
8236 .dst_addr = RTE_BE32(0xffffffff),
8237 .type_of_service = 0xff,
8238 .next_proto_id = 0xff,
8239 .time_to_live = 0xff,
8246 uint8_t tos, ihl_m, ihl_v;
8249 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8251 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8253 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8255 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8257 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8262 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8263 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8264 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8265 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8266 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8267 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8268 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8269 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8270 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8271 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8272 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8273 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8274 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8275 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8276 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8277 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8278 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8279 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8280 ipv4_m->hdr.type_of_service);
8281 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8282 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8283 ipv4_m->hdr.type_of_service >> 2);
8284 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8286 ipv4_m->hdr.next_proto_id);
8287 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8288 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8289 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8290 ipv4_m->hdr.time_to_live);
8291 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8292 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8293 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8294 !!(ipv4_m->hdr.fragment_offset));
8295 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8296 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8300 * Add IPV6 item to matcher and to the value.
8302 * @param[in, out] matcher
8304 * @param[in, out] key
8305 * Flow matcher value.
8307 * Flow pattern to translate.
8309 * Item is inner pattern.
8311 * The group to insert the rule.
8314 flow_dv_translate_item_ipv6(void *matcher, void *key,
8315 const struct rte_flow_item *item,
8316 int inner, uint32_t group)
8318 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8319 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8320 const struct rte_flow_item_ipv6 nic_mask = {
8323 "\xff\xff\xff\xff\xff\xff\xff\xff"
8324 "\xff\xff\xff\xff\xff\xff\xff\xff",
8326 "\xff\xff\xff\xff\xff\xff\xff\xff"
8327 "\xff\xff\xff\xff\xff\xff\xff\xff",
8328 .vtc_flow = RTE_BE32(0xffffffff),
8335 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8336 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8345 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8347 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8349 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8351 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8353 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8358 size = sizeof(ipv6_m->hdr.dst_addr);
8359 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8360 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8361 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8362 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8363 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8364 for (i = 0; i < size; ++i)
8365 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8366 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8367 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8368 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8369 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8370 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8371 for (i = 0; i < size; ++i)
8372 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8374 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8375 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8376 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8377 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8378 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8379 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8382 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8384 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8387 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8389 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8395 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8396 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8398 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8399 ipv6_m->hdr.hop_limits);
8400 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8401 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8402 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8403 !!(ipv6_m->has_frag_ext));
8404 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8405 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8409 * Add IPV6 fragment extension item to matcher and to the value.
8411 * @param[in, out] matcher
8413 * @param[in, out] key
8414 * Flow matcher value.
8416 * Flow pattern to translate.
8418 * Item is inner pattern.
8421 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8422 const struct rte_flow_item *item,
8425 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8426 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8427 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8429 .next_header = 0xff,
8430 .frag_data = RTE_BE16(0xffff),
8437 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8439 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8441 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8443 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8445 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8446 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8448 if (!ipv6_frag_ext_v)
8450 if (!ipv6_frag_ext_m)
8451 ipv6_frag_ext_m = &nic_mask;
8452 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8453 ipv6_frag_ext_m->hdr.next_header);
8454 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8455 ipv6_frag_ext_v->hdr.next_header &
8456 ipv6_frag_ext_m->hdr.next_header);
8460 * Add TCP item to matcher and to the value.
8462 * @param[in, out] matcher
8464 * @param[in, out] key
8465 * Flow matcher value.
8467 * Flow pattern to translate.
8469 * Item is inner pattern.
8472 flow_dv_translate_item_tcp(void *matcher, void *key,
8473 const struct rte_flow_item *item,
8476 const struct rte_flow_item_tcp *tcp_m = item->mask;
8477 const struct rte_flow_item_tcp *tcp_v = item->spec;
8482 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8484 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8486 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8488 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8490 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8495 tcp_m = &rte_flow_item_tcp_mask;
8496 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8497 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8499 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8500 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8501 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8502 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8503 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8504 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8505 tcp_m->hdr.tcp_flags);
8506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8507 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8511 * Add UDP item to matcher and to the value.
8513 * @param[in, out] matcher
8515 * @param[in, out] key
8516 * Flow matcher value.
8518 * Flow pattern to translate.
8520 * Item is inner pattern.
8523 flow_dv_translate_item_udp(void *matcher, void *key,
8524 const struct rte_flow_item *item,
8527 const struct rte_flow_item_udp *udp_m = item->mask;
8528 const struct rte_flow_item_udp *udp_v = item->spec;
8533 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8535 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8537 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8539 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8546 udp_m = &rte_flow_item_udp_mask;
8547 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8548 rte_be_to_cpu_16(udp_m->hdr.src_port));
8549 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8550 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8551 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8552 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8553 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8554 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8558 * Add GRE optional Key item to matcher and to the value.
8560 * @param[in, out] matcher
8562 * @param[in, out] key
8563 * Flow matcher value.
8565 * Flow pattern to translate.
8567 * Item is inner pattern.
8570 flow_dv_translate_item_gre_key(void *matcher, void *key,
8571 const struct rte_flow_item *item)
8573 const rte_be32_t *key_m = item->mask;
8574 const rte_be32_t *key_v = item->spec;
8575 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8576 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8577 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8579 /* GRE K bit must be on and should already be validated */
8580 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8581 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8585 key_m = &gre_key_default_mask;
8586 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8587 rte_be_to_cpu_32(*key_m) >> 8);
8588 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8589 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8590 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8591 rte_be_to_cpu_32(*key_m) & 0xFF);
8592 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8593 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8597 * Add GRE item to matcher and to the value.
8599 * @param[in, out] matcher
8601 * @param[in, out] key
8602 * Flow matcher value.
8604 * Flow pattern to translate.
8606 * Item is inner pattern.
8609 flow_dv_translate_item_gre(void *matcher, void *key,
8610 const struct rte_flow_item *item,
8613 const struct rte_flow_item_gre *gre_m = item->mask;
8614 const struct rte_flow_item_gre *gre_v = item->spec;
8617 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8618 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8625 uint16_t s_present:1;
8626 uint16_t k_present:1;
8627 uint16_t rsvd_bit1:1;
8628 uint16_t c_present:1;
8632 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8635 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8637 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8639 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8641 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8643 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8644 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8648 gre_m = &rte_flow_item_gre_mask;
8649 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8650 rte_be_to_cpu_16(gre_m->protocol));
8651 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8652 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8653 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8654 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8655 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8656 gre_crks_rsvd0_ver_m.c_present);
8657 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8658 gre_crks_rsvd0_ver_v.c_present &
8659 gre_crks_rsvd0_ver_m.c_present);
8660 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8661 gre_crks_rsvd0_ver_m.k_present);
8662 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8663 gre_crks_rsvd0_ver_v.k_present &
8664 gre_crks_rsvd0_ver_m.k_present);
8665 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8666 gre_crks_rsvd0_ver_m.s_present);
8667 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8668 gre_crks_rsvd0_ver_v.s_present &
8669 gre_crks_rsvd0_ver_m.s_present);
8673 * Add NVGRE item to matcher and to the value.
8675 * @param[in, out] matcher
8677 * @param[in, out] key
8678 * Flow matcher value.
8680 * Flow pattern to translate.
8682 * Item is inner pattern.
8685 flow_dv_translate_item_nvgre(void *matcher, void *key,
8686 const struct rte_flow_item *item,
8689 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8690 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8691 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8692 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8693 const char *tni_flow_id_m;
8694 const char *tni_flow_id_v;
8700 /* For NVGRE, GRE header fields must be set with defined values. */
8701 const struct rte_flow_item_gre gre_spec = {
8702 .c_rsvd0_ver = RTE_BE16(0x2000),
8703 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8705 const struct rte_flow_item_gre gre_mask = {
8706 .c_rsvd0_ver = RTE_BE16(0xB000),
8707 .protocol = RTE_BE16(UINT16_MAX),
8709 const struct rte_flow_item gre_item = {
8714 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8718 nvgre_m = &rte_flow_item_nvgre_mask;
8719 tni_flow_id_m = (const char *)nvgre_m->tni;
8720 tni_flow_id_v = (const char *)nvgre_v->tni;
8721 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8722 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8723 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8724 memcpy(gre_key_m, tni_flow_id_m, size);
8725 for (i = 0; i < size; ++i)
8726 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8730 * Add VXLAN item to matcher and to the value.
8733 * Pointer to the Ethernet device structure.
8735 * Flow rule attributes.
8736 * @param[in, out] matcher
8738 * @param[in, out] key
8739 * Flow matcher value.
8741 * Flow pattern to translate.
8743 * Item is inner pattern.
8746 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8747 const struct rte_flow_attr *attr,
8748 void *matcher, void *key,
8749 const struct rte_flow_item *item,
8752 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8753 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8758 uint32_t *tunnel_header_v;
8759 uint32_t *tunnel_header_m;
8761 struct mlx5_priv *priv = dev->data->dev_private;
8762 const struct rte_flow_item_vxlan nic_mask = {
8763 .vni = "\xff\xff\xff",
8768 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8770 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8772 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8774 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8776 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8777 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8778 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8779 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8780 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8782 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8786 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8787 (attr->group && !priv->sh->misc5_cap))
8788 vxlan_m = &rte_flow_item_vxlan_mask;
8790 vxlan_m = &nic_mask;
8792 if ((priv->sh->steering_format_version ==
8793 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8794 dport != MLX5_UDP_PORT_VXLAN) ||
8795 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8796 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8803 misc_m = MLX5_ADDR_OF(fte_match_param,
8804 matcher, misc_parameters);
8805 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8806 size = sizeof(vxlan_m->vni);
8807 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8808 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8809 memcpy(vni_m, vxlan_m->vni, size);
8810 for (i = 0; i < size; ++i)
8811 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8814 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8815 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8816 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8819 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8822 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8823 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8824 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8825 if (*tunnel_header_v)
8826 *tunnel_header_m = vxlan_m->vni[0] |
8827 vxlan_m->vni[1] << 8 |
8828 vxlan_m->vni[2] << 16;
8830 *tunnel_header_m = 0x0;
8831 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8832 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8833 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8837 * Add VXLAN-GPE item to matcher and to the value.
8839 * @param[in, out] matcher
8841 * @param[in, out] key
8842 * Flow matcher value.
8844 * Flow pattern to translate.
8846 * Item is inner pattern.
8850 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8851 const struct rte_flow_item *item, int inner)
8853 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8854 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8858 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8860 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8866 uint8_t flags_m = 0xff;
8867 uint8_t flags_v = 0xc;
8870 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8872 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8874 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8876 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8878 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8879 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8880 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8881 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8887 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8888 size = sizeof(vxlan_m->vni);
8889 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8890 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8891 memcpy(vni_m, vxlan_m->vni, size);
8892 for (i = 0; i < size; ++i)
8893 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8894 if (vxlan_m->flags) {
8895 flags_m = vxlan_m->flags;
8896 flags_v = vxlan_v->flags;
8898 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8899 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8900 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8902 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8907 * Add Geneve item to matcher and to the value.
8909 * @param[in, out] matcher
8911 * @param[in, out] key
8912 * Flow matcher value.
8914 * Flow pattern to translate.
8916 * Item is inner pattern.
8920 flow_dv_translate_item_geneve(void *matcher, void *key,
8921 const struct rte_flow_item *item, int inner)
8923 const struct rte_flow_item_geneve *geneve_m = item->mask;
8924 const struct rte_flow_item_geneve *geneve_v = item->spec;
8927 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8928 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8937 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8939 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8941 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8943 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8945 dport = MLX5_UDP_PORT_GENEVE;
8946 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8947 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8948 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8953 geneve_m = &rte_flow_item_geneve_mask;
8954 size = sizeof(geneve_m->vni);
8955 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8956 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8957 memcpy(vni_m, geneve_m->vni, size);
8958 for (i = 0; i < size; ++i)
8959 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8960 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8961 rte_be_to_cpu_16(geneve_m->protocol));
8962 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8963 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8964 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8965 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8966 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8967 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8968 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8969 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8970 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8971 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8972 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8973 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8974 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8978 * Create Geneve TLV option resource.
8980 * @param dev[in, out]
8981 * Pointer to rte_eth_dev structure.
8982 * @param[in, out] tag_be24
8983 * Tag value in big endian then R-shift 8.
8984 * @parm[in, out] dev_flow
8985 * Pointer to the dev_flow.
8987 * pointer to error structure.
8990 * 0 on success otherwise -errno and errno is set.
8994 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8995 const struct rte_flow_item *item,
8996 struct rte_flow_error *error)
8998 struct mlx5_priv *priv = dev->data->dev_private;
8999 struct mlx5_dev_ctx_shared *sh = priv->sh;
9000 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9001 sh->geneve_tlv_option_resource;
9002 struct mlx5_devx_obj *obj;
9003 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9008 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9009 if (geneve_opt_resource != NULL) {
9010 if (geneve_opt_resource->option_class ==
9011 geneve_opt_v->option_class &&
9012 geneve_opt_resource->option_type ==
9013 geneve_opt_v->option_type &&
9014 geneve_opt_resource->length ==
9015 geneve_opt_v->option_len) {
9016 /* We already have GENVE TLV option obj allocated. */
9017 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9020 ret = rte_flow_error_set(error, ENOMEM,
9021 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9022 "Only one GENEVE TLV option supported");
9026 /* Create a GENEVE TLV object and resource. */
9027 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9028 geneve_opt_v->option_class,
9029 geneve_opt_v->option_type,
9030 geneve_opt_v->option_len);
9032 ret = rte_flow_error_set(error, ENODATA,
9033 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9034 "Failed to create GENEVE TLV Devx object");
9037 sh->geneve_tlv_option_resource =
9038 mlx5_malloc(MLX5_MEM_ZERO,
9039 sizeof(*geneve_opt_resource),
9041 if (!sh->geneve_tlv_option_resource) {
9042 claim_zero(mlx5_devx_cmd_destroy(obj));
9043 ret = rte_flow_error_set(error, ENOMEM,
9044 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9045 "GENEVE TLV object memory allocation failed");
9048 geneve_opt_resource = sh->geneve_tlv_option_resource;
9049 geneve_opt_resource->obj = obj;
9050 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9051 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9052 geneve_opt_resource->length = geneve_opt_v->option_len;
9053 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9057 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9062 * Add Geneve TLV option item to matcher.
9064 * @param[in, out] dev
9065 * Pointer to rte_eth_dev structure.
9066 * @param[in, out] matcher
9068 * @param[in, out] key
9069 * Flow matcher value.
9071 * Flow pattern to translate.
9073 * Pointer to error structure.
9076 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9077 void *key, const struct rte_flow_item *item,
9078 struct rte_flow_error *error)
9080 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9081 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9082 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9083 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9084 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9086 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9087 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9093 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9094 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9097 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9101 * Set the option length in GENEVE header if not requested.
9102 * The GENEVE TLV option length is expressed by the option length field
9103 * in the GENEVE header.
9104 * If the option length was not requested but the GENEVE TLV option item
9105 * is present we set the option length field implicitly.
9107 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9108 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9109 MLX5_GENEVE_OPTLEN_MASK);
9110 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9111 geneve_opt_v->option_len + 1);
9113 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9114 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9116 if (geneve_opt_v->data) {
9117 memcpy(&opt_data_key, geneve_opt_v->data,
9118 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9119 sizeof(opt_data_key)));
9120 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9121 sizeof(opt_data_key));
9122 memcpy(&opt_data_mask, geneve_opt_m->data,
9123 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9124 sizeof(opt_data_mask)));
9125 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9126 sizeof(opt_data_mask));
9127 MLX5_SET(fte_match_set_misc3, misc3_m,
9128 geneve_tlv_option_0_data,
9129 rte_be_to_cpu_32(opt_data_mask));
9130 MLX5_SET(fte_match_set_misc3, misc3_v,
9131 geneve_tlv_option_0_data,
9132 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9138 * Add MPLS item to matcher and to the value.
9140 * @param[in, out] matcher
9142 * @param[in, out] key
9143 * Flow matcher value.
9145 * Flow pattern to translate.
9146 * @param[in] prev_layer
9147 * The protocol layer indicated in previous item.
9149 * Item is inner pattern.
9152 flow_dv_translate_item_mpls(void *matcher, void *key,
9153 const struct rte_flow_item *item,
9154 uint64_t prev_layer,
9157 const uint32_t *in_mpls_m = item->mask;
9158 const uint32_t *in_mpls_v = item->spec;
9159 uint32_t *out_mpls_m = 0;
9160 uint32_t *out_mpls_v = 0;
9161 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9162 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9163 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9165 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9166 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9167 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9169 switch (prev_layer) {
9170 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
9172 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9173 MLX5_UDP_PORT_MPLS);
9175 case MLX5_FLOW_LAYER_GRE:
9177 case MLX5_FLOW_LAYER_GRE_KEY:
9178 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
9179 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9180 RTE_ETHER_TYPE_MPLS);
9188 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9189 switch (prev_layer) {
9190 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9192 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9193 outer_first_mpls_over_udp);
9195 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9196 outer_first_mpls_over_udp);
9198 case MLX5_FLOW_LAYER_GRE:
9200 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9201 outer_first_mpls_over_gre);
9203 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9204 outer_first_mpls_over_gre);
9207 /* Inner MPLS not over GRE is not supported. */
9210 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9214 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9220 if (out_mpls_m && out_mpls_v) {
9221 *out_mpls_m = *in_mpls_m;
9222 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9227 * Add metadata register item to matcher
9229 * @param[in, out] matcher
9231 * @param[in, out] key
9232 * Flow matcher value.
9233 * @param[in] reg_type
9234 * Type of device metadata register
9241 flow_dv_match_meta_reg(void *matcher, void *key,
9242 enum modify_reg reg_type,
9243 uint32_t data, uint32_t mask)
9246 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9248 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9254 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9255 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9258 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9259 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9263 * The metadata register C0 field might be divided into
9264 * source vport index and META item value, we should set
9265 * this field according to specified mask, not as whole one.
9267 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9269 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9270 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9273 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9276 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9277 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9280 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9281 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9284 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9285 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9288 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9289 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9292 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9293 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9296 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9297 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9300 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9301 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9310 * Add MARK item to matcher
9313 * The device to configure through.
9314 * @param[in, out] matcher
9316 * @param[in, out] key
9317 * Flow matcher value.
9319 * Flow pattern to translate.
9322 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9323 void *matcher, void *key,
9324 const struct rte_flow_item *item)
9326 struct mlx5_priv *priv = dev->data->dev_private;
9327 const struct rte_flow_item_mark *mark;
9331 mark = item->mask ? (const void *)item->mask :
9332 &rte_flow_item_mark_mask;
9333 mask = mark->id & priv->sh->dv_mark_mask;
9334 mark = (const void *)item->spec;
9336 value = mark->id & priv->sh->dv_mark_mask & mask;
9338 enum modify_reg reg;
9340 /* Get the metadata register index for the mark. */
9341 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9342 MLX5_ASSERT(reg > 0);
9343 if (reg == REG_C_0) {
9344 struct mlx5_priv *priv = dev->data->dev_private;
9345 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9346 uint32_t shl_c0 = rte_bsf32(msk_c0);
9352 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9357 * Add META item to matcher
9360 * The devich to configure through.
9361 * @param[in, out] matcher
9363 * @param[in, out] key
9364 * Flow matcher value.
9366 * Attributes of flow that includes this item.
9368 * Flow pattern to translate.
9371 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9372 void *matcher, void *key,
9373 const struct rte_flow_attr *attr,
9374 const struct rte_flow_item *item)
9376 const struct rte_flow_item_meta *meta_m;
9377 const struct rte_flow_item_meta *meta_v;
9379 meta_m = (const void *)item->mask;
9381 meta_m = &rte_flow_item_meta_mask;
9382 meta_v = (const void *)item->spec;
9385 uint32_t value = meta_v->data;
9386 uint32_t mask = meta_m->data;
9388 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9391 MLX5_ASSERT(reg != REG_NON);
9392 if (reg == REG_C_0) {
9393 struct mlx5_priv *priv = dev->data->dev_private;
9394 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9395 uint32_t shl_c0 = rte_bsf32(msk_c0);
9401 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9406 * Add vport metadata Reg C0 item to matcher
9408 * @param[in, out] matcher
9410 * @param[in, out] key
9411 * Flow matcher value.
9413 * Flow pattern to translate.
9416 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9417 uint32_t value, uint32_t mask)
9419 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9423 * Add tag item to matcher
9426 * The devich to configure through.
9427 * @param[in, out] matcher
9429 * @param[in, out] key
9430 * Flow matcher value.
9432 * Flow pattern to translate.
9435 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9436 void *matcher, void *key,
9437 const struct rte_flow_item *item)
9439 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9440 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9441 uint32_t mask, value;
9444 value = tag_v->data;
9445 mask = tag_m ? tag_m->data : UINT32_MAX;
9446 if (tag_v->id == REG_C_0) {
9447 struct mlx5_priv *priv = dev->data->dev_private;
9448 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9449 uint32_t shl_c0 = rte_bsf32(msk_c0);
9455 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9459 * Add TAG item to matcher
9462 * The devich to configure through.
9463 * @param[in, out] matcher
9465 * @param[in, out] key
9466 * Flow matcher value.
9468 * Flow pattern to translate.
9471 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9472 void *matcher, void *key,
9473 const struct rte_flow_item *item)
9475 const struct rte_flow_item_tag *tag_v = item->spec;
9476 const struct rte_flow_item_tag *tag_m = item->mask;
9477 enum modify_reg reg;
9480 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9481 /* Get the metadata register index for the tag. */
9482 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9483 MLX5_ASSERT(reg > 0);
9484 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9488 * Add source vport match to the specified matcher.
9490 * @param[in, out] matcher
9492 * @param[in, out] key
9493 * Flow matcher value.
9495 * Source vport value to match
9500 flow_dv_translate_item_source_vport(void *matcher, void *key,
9501 int16_t port, uint16_t mask)
9503 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9504 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9506 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9507 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9511 * Translate port-id item to eswitch match on port-id.
9514 * The devich to configure through.
9515 * @param[in, out] matcher
9517 * @param[in, out] key
9518 * Flow matcher value.
9520 * Flow pattern to translate.
9525 * 0 on success, a negative errno value otherwise.
9528 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9529 void *key, const struct rte_flow_item *item,
9530 const struct rte_flow_attr *attr)
9532 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9533 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9534 struct mlx5_priv *priv;
9537 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9538 flow_dv_translate_item_source_vport(matcher, key,
9539 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9542 mask = pid_m ? pid_m->id : 0xffff;
9543 id = pid_v ? pid_v->id : dev->data->port_id;
9544 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9548 * Translate to vport field or to metadata, depending on mode.
9549 * Kernel can use either misc.source_port or half of C0 metadata
9552 if (priv->vport_meta_mask) {
9554 * Provide the hint for SW steering library
9555 * to insert the flow into ingress domain and
9556 * save the extra vport match.
9558 if (mask == 0xffff && priv->vport_id == 0xffff &&
9559 priv->pf_bond < 0 && attr->transfer)
9560 flow_dv_translate_item_source_vport
9561 (matcher, key, priv->vport_id, mask);
9563 * We should always set the vport metadata register,
9564 * otherwise the SW steering library can drop
9565 * the rule if wire vport metadata value is not zero,
9566 * it depends on kernel configuration.
9568 flow_dv_translate_item_meta_vport(matcher, key,
9569 priv->vport_meta_tag,
9570 priv->vport_meta_mask);
9572 flow_dv_translate_item_source_vport(matcher, key,
9573 priv->vport_id, mask);
9579 * Add ICMP6 item to matcher and to the value.
9581 * @param[in, out] matcher
9583 * @param[in, out] key
9584 * Flow matcher value.
9586 * Flow pattern to translate.
9588 * Item is inner pattern.
9591 flow_dv_translate_item_icmp6(void *matcher, void *key,
9592 const struct rte_flow_item *item,
9595 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9596 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9599 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9601 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9603 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9605 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9607 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9609 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9611 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9612 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9616 icmp6_m = &rte_flow_item_icmp6_mask;
9617 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9618 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9619 icmp6_v->type & icmp6_m->type);
9620 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9621 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9622 icmp6_v->code & icmp6_m->code);
9626 * Add ICMP item to matcher and to the value.
9628 * @param[in, out] matcher
9630 * @param[in, out] key
9631 * Flow matcher value.
9633 * Flow pattern to translate.
9635 * Item is inner pattern.
9638 flow_dv_translate_item_icmp(void *matcher, void *key,
9639 const struct rte_flow_item *item,
9642 const struct rte_flow_item_icmp *icmp_m = item->mask;
9643 const struct rte_flow_item_icmp *icmp_v = item->spec;
9644 uint32_t icmp_header_data_m = 0;
9645 uint32_t icmp_header_data_v = 0;
9648 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9650 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9652 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9654 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9656 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9658 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9660 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9665 icmp_m = &rte_flow_item_icmp_mask;
9666 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9667 icmp_m->hdr.icmp_type);
9668 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9669 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9670 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9671 icmp_m->hdr.icmp_code);
9672 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9673 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9674 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9675 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9676 if (icmp_header_data_m) {
9677 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9678 icmp_header_data_v |=
9679 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9680 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9681 icmp_header_data_m);
9682 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9683 icmp_header_data_v & icmp_header_data_m);
9688 * Add GTP item to matcher and to the value.
9690 * @param[in, out] matcher
9692 * @param[in, out] key
9693 * Flow matcher value.
9695 * Flow pattern to translate.
9697 * Item is inner pattern.
9700 flow_dv_translate_item_gtp(void *matcher, void *key,
9701 const struct rte_flow_item *item, int inner)
9703 const struct rte_flow_item_gtp *gtp_m = item->mask;
9704 const struct rte_flow_item_gtp *gtp_v = item->spec;
9707 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9709 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9710 uint16_t dport = RTE_GTPU_UDP_PORT;
9713 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9715 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9717 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9719 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9721 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9723 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9728 gtp_m = &rte_flow_item_gtp_mask;
9729 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9730 gtp_m->v_pt_rsv_flags);
9731 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9732 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9733 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9734 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9735 gtp_v->msg_type & gtp_m->msg_type);
9736 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9737 rte_be_to_cpu_32(gtp_m->teid));
9738 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9739 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9743 * Add GTP PSC item to matcher.
9745 * @param[in, out] matcher
9747 * @param[in, out] key
9748 * Flow matcher value.
9750 * Flow pattern to translate.
9753 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9754 const struct rte_flow_item *item)
9756 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9757 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9758 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9760 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9766 uint8_t next_ext_header_type;
9771 /* Always set E-flag match on one, regardless of GTP item settings. */
9772 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9773 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9774 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9775 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9776 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9777 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9778 /*Set next extension header type. */
9781 dw_2.next_ext_header_type = 0xff;
9782 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9783 rte_cpu_to_be_32(dw_2.w32));
9786 dw_2.next_ext_header_type = 0x85;
9787 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9788 rte_cpu_to_be_32(dw_2.w32));
9800 /*Set extension header PDU type and Qos. */
9802 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9804 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9805 dw_0.qfi = gtp_psc_m->hdr.qfi;
9806 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9807 rte_cpu_to_be_32(dw_0.w32));
9809 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9810 gtp_psc_m->hdr.type);
9811 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9812 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9813 rte_cpu_to_be_32(dw_0.w32));
9819 * Add eCPRI item to matcher and to the value.
9822 * The devich to configure through.
9823 * @param[in, out] matcher
9825 * @param[in, out] key
9826 * Flow matcher value.
9828 * Flow pattern to translate.
9829 * @param[in] last_item
9833 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9834 void *key, const struct rte_flow_item *item,
9837 struct mlx5_priv *priv = dev->data->dev_private;
9838 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9839 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9840 struct rte_ecpri_common_hdr common;
9841 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9843 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9849 * In case of eCPRI over Ethernet, if EtherType is not specified,
9850 * match on eCPRI EtherType implicitly.
9852 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
9853 void *hdrs_m, *hdrs_v, *l2m, *l2v;
9855 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9856 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9857 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
9858 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
9859 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
9860 *(uint16_t *)l2m = UINT16_MAX;
9861 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
9867 ecpri_m = &rte_flow_item_ecpri_mask;
9869 * Maximal four DW samples are supported in a single matching now.
9870 * Two are used now for a eCPRI matching:
9871 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9872 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9875 if (!ecpri_m->hdr.common.u32)
9877 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9878 /* Need to take the whole DW as the mask to fill the entry. */
9879 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9880 prog_sample_field_value_0);
9881 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9882 prog_sample_field_value_0);
9883 /* Already big endian (network order) in the header. */
9884 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9885 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9886 /* Sample#0, used for matching type, offset 0. */
9887 MLX5_SET(fte_match_set_misc4, misc4_m,
9888 prog_sample_field_id_0, samples[0]);
9889 /* It makes no sense to set the sample ID in the mask field. */
9890 MLX5_SET(fte_match_set_misc4, misc4_v,
9891 prog_sample_field_id_0, samples[0]);
9893 * Checking if message body part needs to be matched.
9894 * Some wildcard rules only matching type field should be supported.
9896 if (ecpri_m->hdr.dummy[0]) {
9897 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9898 switch (common.type) {
9899 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9900 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9901 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9902 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9903 prog_sample_field_value_1);
9904 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9905 prog_sample_field_value_1);
9906 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9907 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9908 ecpri_m->hdr.dummy[0];
9909 /* Sample#1, to match message body, offset 4. */
9910 MLX5_SET(fte_match_set_misc4, misc4_m,
9911 prog_sample_field_id_1, samples[1]);
9912 MLX5_SET(fte_match_set_misc4, misc4_v,
9913 prog_sample_field_id_1, samples[1]);
9916 /* Others, do not match any sample ID. */
9923 * Add connection tracking status item to matcher
9926 * The devich to configure through.
9927 * @param[in, out] matcher
9929 * @param[in, out] key
9930 * Flow matcher value.
9932 * Flow pattern to translate.
9935 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
9936 void *matcher, void *key,
9937 const struct rte_flow_item *item)
9939 uint32_t reg_value = 0;
9941 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
9942 uint32_t reg_mask = 0;
9943 const struct rte_flow_item_conntrack *spec = item->spec;
9944 const struct rte_flow_item_conntrack *mask = item->mask;
9946 struct rte_flow_error error;
9949 mask = &rte_flow_item_conntrack_mask;
9950 if (!spec || !mask->flags)
9952 flags = spec->flags & mask->flags;
9953 /* The conflict should be checked in the validation. */
9954 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
9955 reg_value |= MLX5_CT_SYNDROME_VALID;
9956 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
9957 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
9958 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
9959 reg_value |= MLX5_CT_SYNDROME_INVALID;
9960 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
9961 reg_value |= MLX5_CT_SYNDROME_TRAP;
9962 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
9963 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
9964 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
9965 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
9966 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
9968 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
9969 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
9970 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
9971 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
9972 /* The REG_C_x value could be saved during startup. */
9973 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
9974 if (reg_id == REG_NON)
9976 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
9977 reg_value, reg_mask);
9980 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9982 #define HEADER_IS_ZERO(match_criteria, headers) \
9983 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9984 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9987 * Calculate flow matcher enable bitmap.
9989 * @param match_criteria
9990 * Pointer to flow matcher criteria.
9993 * Bitmap of enabled fields.
9996 flow_dv_matcher_enable(uint32_t *match_criteria)
9998 uint8_t match_criteria_enable;
10000 match_criteria_enable =
10001 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10002 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10003 match_criteria_enable |=
10004 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10005 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10006 match_criteria_enable |=
10007 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10008 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10009 match_criteria_enable |=
10010 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10011 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10012 match_criteria_enable |=
10013 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10014 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10015 match_criteria_enable |=
10016 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10017 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10018 match_criteria_enable |=
10019 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10020 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10021 return match_criteria_enable;
10025 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10028 * Check flow matching criteria first, subtract misc5/4 length if flow
10029 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10030 * misc5/4 are not supported, and matcher creation failure is expected
10031 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10032 * misc5 is right after misc4.
10034 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10035 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10036 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10037 if (!(match_criteria & (1 <<
10038 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10039 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10044 static struct mlx5_list_entry *
10045 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10046 struct mlx5_list_entry *entry, void *cb_ctx)
10048 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10049 struct mlx5_flow_dv_matcher *ref = ctx->data;
10050 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10051 typeof(*tbl), tbl);
10052 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10057 rte_flow_error_set(ctx->error, ENOMEM,
10058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10059 "cannot create matcher");
10062 memcpy(resource, entry, sizeof(*resource));
10063 resource->tbl = &tbl->tbl;
10064 return &resource->entry;
10068 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10069 struct mlx5_list_entry *entry)
10074 struct mlx5_list_entry *
10075 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10077 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10078 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10079 struct rte_eth_dev *dev = ctx->dev;
10080 struct mlx5_flow_tbl_data_entry *tbl_data;
10081 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10082 struct rte_flow_error *error = ctx->error;
10083 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10084 struct mlx5_flow_tbl_resource *tbl;
10089 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10091 rte_flow_error_set(error, ENOMEM,
10092 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10094 "cannot allocate flow table data entry");
10097 tbl_data->idx = idx;
10098 tbl_data->tunnel = tt_prm->tunnel;
10099 tbl_data->group_id = tt_prm->group_id;
10100 tbl_data->external = !!tt_prm->external;
10101 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10102 tbl_data->is_egress = !!key.is_egress;
10103 tbl_data->is_transfer = !!key.is_fdb;
10104 tbl_data->dummy = !!key.dummy;
10105 tbl_data->level = key.level;
10106 tbl_data->id = key.id;
10107 tbl = &tbl_data->tbl;
10109 return &tbl_data->entry;
10111 domain = sh->fdb_domain;
10112 else if (key.is_egress)
10113 domain = sh->tx_domain;
10115 domain = sh->rx_domain;
10116 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10118 rte_flow_error_set(error, ENOMEM,
10119 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10120 NULL, "cannot create flow table object");
10121 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10124 if (key.level != 0) {
10125 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10126 (tbl->obj, &tbl_data->jump.action);
10128 rte_flow_error_set(error, ENOMEM,
10129 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10131 "cannot create flow jump action");
10132 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10133 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10137 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10138 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10139 key.level, key.id);
10140 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10141 flow_dv_matcher_create_cb,
10142 flow_dv_matcher_match_cb,
10143 flow_dv_matcher_remove_cb,
10144 flow_dv_matcher_clone_cb,
10145 flow_dv_matcher_clone_free_cb);
10146 if (!tbl_data->matchers) {
10147 rte_flow_error_set(error, ENOMEM,
10148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10150 "cannot create tbl matcher list");
10151 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10152 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10153 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10156 return &tbl_data->entry;
10160 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10163 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10164 struct mlx5_flow_tbl_data_entry *tbl_data =
10165 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10166 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10168 return tbl_data->level != key.level ||
10169 tbl_data->id != key.id ||
10170 tbl_data->dummy != key.dummy ||
10171 tbl_data->is_transfer != !!key.is_fdb ||
10172 tbl_data->is_egress != !!key.is_egress;
10175 struct mlx5_list_entry *
10176 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10179 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10180 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10181 struct mlx5_flow_tbl_data_entry *tbl_data;
10182 struct rte_flow_error *error = ctx->error;
10185 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10187 rte_flow_error_set(error, ENOMEM,
10188 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10190 "cannot allocate flow table data entry");
10193 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10194 tbl_data->idx = idx;
10195 return &tbl_data->entry;
10199 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10201 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10202 struct mlx5_flow_tbl_data_entry *tbl_data =
10203 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10205 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10209 * Get a flow table.
10211 * @param[in, out] dev
10212 * Pointer to rte_eth_dev structure.
10213 * @param[in] table_level
10214 * Table level to use.
10215 * @param[in] egress
10216 * Direction of the table.
10217 * @param[in] transfer
10218 * E-Switch or NIC flow.
10220 * Dummy entry for dv API.
10221 * @param[in] table_id
10223 * @param[out] error
10224 * pointer to error structure.
10227 * Returns tables resource based on the index, NULL in case of failed.
10229 struct mlx5_flow_tbl_resource *
10230 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10231 uint32_t table_level, uint8_t egress,
10234 const struct mlx5_flow_tunnel *tunnel,
10235 uint32_t group_id, uint8_t dummy,
10237 struct rte_flow_error *error)
10239 struct mlx5_priv *priv = dev->data->dev_private;
10240 union mlx5_flow_tbl_key table_key = {
10242 .level = table_level,
10246 .is_fdb = !!transfer,
10247 .is_egress = !!egress,
10250 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10252 .group_id = group_id,
10253 .external = external,
10255 struct mlx5_flow_cb_ctx ctx = {
10258 .data = &table_key.v64,
10261 struct mlx5_list_entry *entry;
10262 struct mlx5_flow_tbl_data_entry *tbl_data;
10264 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10266 rte_flow_error_set(error, ENOMEM,
10267 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10268 "cannot get table");
10271 DRV_LOG(DEBUG, "table_level %u table_id %u "
10272 "tunnel %u group %u registered.",
10273 table_level, table_id,
10274 tunnel ? tunnel->tunnel_id : 0, group_id);
10275 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10276 return &tbl_data->tbl;
10280 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10282 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10283 struct mlx5_flow_tbl_data_entry *tbl_data =
10284 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10286 MLX5_ASSERT(entry && sh);
10287 if (tbl_data->jump.action)
10288 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10289 if (tbl_data->tbl.obj)
10290 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10291 if (tbl_data->tunnel_offload && tbl_data->external) {
10292 struct mlx5_list_entry *he;
10293 struct mlx5_hlist *tunnel_grp_hash;
10294 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10295 union tunnel_tbl_key tunnel_key = {
10296 .tunnel_id = tbl_data->tunnel ?
10297 tbl_data->tunnel->tunnel_id : 0,
10298 .group = tbl_data->group_id
10300 uint32_t table_level = tbl_data->level;
10301 struct mlx5_flow_cb_ctx ctx = {
10302 .data = (void *)&tunnel_key.val,
10305 tunnel_grp_hash = tbl_data->tunnel ?
10306 tbl_data->tunnel->groups :
10308 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10310 mlx5_hlist_unregister(tunnel_grp_hash, he);
10312 "table_level %u id %u tunnel %u group %u released.",
10316 tbl_data->tunnel->tunnel_id : 0,
10317 tbl_data->group_id);
10319 mlx5_list_destroy(tbl_data->matchers);
10320 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10324 * Release a flow table.
10327 * Pointer to device shared structure.
10329 * Table resource to be released.
10332 * Returns 0 if table was released, else return 1;
10335 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10336 struct mlx5_flow_tbl_resource *tbl)
10338 struct mlx5_flow_tbl_data_entry *tbl_data =
10339 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10343 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10347 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10348 struct mlx5_list_entry *entry, void *cb_ctx)
10350 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10351 struct mlx5_flow_dv_matcher *ref = ctx->data;
10352 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10355 return cur->crc != ref->crc ||
10356 cur->priority != ref->priority ||
10357 memcmp((const void *)cur->mask.buf,
10358 (const void *)ref->mask.buf, ref->mask.size);
10361 struct mlx5_list_entry *
10362 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10364 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10365 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10366 struct mlx5_flow_dv_matcher *ref = ctx->data;
10367 struct mlx5_flow_dv_matcher *resource;
10368 struct mlx5dv_flow_matcher_attr dv_attr = {
10369 .type = IBV_FLOW_ATTR_NORMAL,
10370 .match_mask = (void *)&ref->mask,
10372 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10373 typeof(*tbl), tbl);
10376 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10379 rte_flow_error_set(ctx->error, ENOMEM,
10380 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10381 "cannot create matcher");
10385 dv_attr.match_criteria_enable =
10386 flow_dv_matcher_enable(resource->mask.buf);
10387 __flow_dv_adjust_buf_size(&ref->mask.size,
10388 dv_attr.match_criteria_enable);
10389 dv_attr.priority = ref->priority;
10390 if (tbl->is_egress)
10391 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10392 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10394 &resource->matcher_object);
10396 mlx5_free(resource);
10397 rte_flow_error_set(ctx->error, ENOMEM,
10398 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10399 "cannot create matcher");
10402 return &resource->entry;
10406 * Register the flow matcher.
10408 * @param[in, out] dev
10409 * Pointer to rte_eth_dev structure.
10410 * @param[in, out] matcher
10411 * Pointer to flow matcher.
10412 * @param[in, out] key
10413 * Pointer to flow table key.
10414 * @parm[in, out] dev_flow
10415 * Pointer to the dev_flow.
10416 * @param[out] error
10417 * pointer to error structure.
10420 * 0 on success otherwise -errno and errno is set.
10423 flow_dv_matcher_register(struct rte_eth_dev *dev,
10424 struct mlx5_flow_dv_matcher *ref,
10425 union mlx5_flow_tbl_key *key,
10426 struct mlx5_flow *dev_flow,
10427 const struct mlx5_flow_tunnel *tunnel,
10429 struct rte_flow_error *error)
10431 struct mlx5_list_entry *entry;
10432 struct mlx5_flow_dv_matcher *resource;
10433 struct mlx5_flow_tbl_resource *tbl;
10434 struct mlx5_flow_tbl_data_entry *tbl_data;
10435 struct mlx5_flow_cb_ctx ctx = {
10440 * tunnel offload API requires this registration for cases when
10441 * tunnel match rule was inserted before tunnel set rule.
10443 tbl = flow_dv_tbl_resource_get(dev, key->level,
10444 key->is_egress, key->is_fdb,
10445 dev_flow->external, tunnel,
10446 group_id, 0, key->id, error);
10448 return -rte_errno; /* No need to refill the error info */
10449 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10451 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10453 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10454 return rte_flow_error_set(error, ENOMEM,
10455 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10456 "cannot allocate ref memory");
10458 resource = container_of(entry, typeof(*resource), entry);
10459 dev_flow->handle->dvh.matcher = resource;
10463 struct mlx5_list_entry *
10464 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10466 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10467 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10468 struct mlx5_flow_dv_tag_resource *entry;
10472 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10474 rte_flow_error_set(ctx->error, ENOMEM,
10475 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10476 "cannot allocate resource memory");
10480 entry->tag_id = *(uint32_t *)(ctx->data);
10481 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10484 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10485 rte_flow_error_set(ctx->error, ENOMEM,
10486 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10487 NULL, "cannot create action");
10490 return &entry->entry;
10494 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10497 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10498 struct mlx5_flow_dv_tag_resource *tag =
10499 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10501 return *(uint32_t *)(ctx->data) != tag->tag_id;
10504 struct mlx5_list_entry *
10505 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10508 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10509 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10510 struct mlx5_flow_dv_tag_resource *entry;
10513 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10515 rte_flow_error_set(ctx->error, ENOMEM,
10516 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10517 "cannot allocate tag resource memory");
10520 memcpy(entry, oentry, sizeof(*entry));
10522 return &entry->entry;
10526 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10528 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10529 struct mlx5_flow_dv_tag_resource *tag =
10530 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10532 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10536 * Find existing tag resource or create and register a new one.
10538 * @param dev[in, out]
10539 * Pointer to rte_eth_dev structure.
10540 * @param[in, out] tag_be24
10541 * Tag value in big endian then R-shift 8.
10542 * @parm[in, out] dev_flow
10543 * Pointer to the dev_flow.
10544 * @param[out] error
10545 * pointer to error structure.
10548 * 0 on success otherwise -errno and errno is set.
10551 flow_dv_tag_resource_register
10552 (struct rte_eth_dev *dev,
10554 struct mlx5_flow *dev_flow,
10555 struct rte_flow_error *error)
10557 struct mlx5_priv *priv = dev->data->dev_private;
10558 struct mlx5_flow_dv_tag_resource *resource;
10559 struct mlx5_list_entry *entry;
10560 struct mlx5_flow_cb_ctx ctx = {
10564 struct mlx5_hlist *tag_table;
10566 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10568 MLX5_TAGS_HLIST_ARRAY_SIZE,
10569 false, false, priv->sh,
10570 flow_dv_tag_create_cb,
10571 flow_dv_tag_match_cb,
10572 flow_dv_tag_remove_cb,
10573 flow_dv_tag_clone_cb,
10574 flow_dv_tag_clone_free_cb);
10575 if (unlikely(!tag_table))
10577 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10579 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10581 dev_flow->handle->dvh.rix_tag = resource->idx;
10582 dev_flow->dv.tag_resource = resource;
10589 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10591 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10592 struct mlx5_flow_dv_tag_resource *tag =
10593 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10595 MLX5_ASSERT(tag && sh && tag->action);
10596 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10597 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10598 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10605 * Pointer to Ethernet device.
10610 * 1 while a reference on it exists, 0 when freed.
10613 flow_dv_tag_release(struct rte_eth_dev *dev,
10616 struct mlx5_priv *priv = dev->data->dev_private;
10617 struct mlx5_flow_dv_tag_resource *tag;
10619 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10622 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10623 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10624 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10628 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10631 * Pointer to rte_eth_dev structure.
10632 * @param[in] action
10633 * Pointer to action PORT_ID / REPRESENTED_PORT.
10634 * @param[out] dst_port_id
10635 * The target port ID.
10636 * @param[out] error
10637 * Pointer to the error structure.
10640 * 0 on success, a negative errno value otherwise and rte_errno is set.
10643 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10644 const struct rte_flow_action *action,
10645 uint32_t *dst_port_id,
10646 struct rte_flow_error *error)
10649 struct mlx5_priv *priv;
10651 switch (action->type) {
10652 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10653 const struct rte_flow_action_port_id *conf;
10655 conf = (const struct rte_flow_action_port_id *)action->conf;
10656 port = conf->original ? dev->data->port_id : conf->id;
10659 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10660 const struct rte_flow_action_ethdev *ethdev;
10662 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10663 port = ethdev->port_id;
10667 MLX5_ASSERT(false);
10668 return rte_flow_error_set(error, EINVAL,
10669 RTE_FLOW_ERROR_TYPE_ACTION, action,
10670 "unknown E-Switch action");
10673 priv = mlx5_port_to_eswitch_info(port, false);
10675 return rte_flow_error_set(error, -rte_errno,
10676 RTE_FLOW_ERROR_TYPE_ACTION,
10678 "No eswitch info was found for port");
10679 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10681 * This parameter is transferred to
10682 * mlx5dv_dr_action_create_dest_ib_port().
10684 *dst_port_id = priv->dev_port;
10687 * Legacy mode, no LAG configurations is supported.
10688 * This parameter is transferred to
10689 * mlx5dv_dr_action_create_dest_vport().
10691 *dst_port_id = priv->vport_id;
10697 * Create a counter with aging configuration.
10700 * Pointer to rte_eth_dev structure.
10701 * @param[in] dev_flow
10702 * Pointer to the mlx5_flow.
10703 * @param[out] count
10704 * Pointer to the counter action configuration.
10706 * Pointer to the aging action configuration.
10709 * Index to flow counter on success, 0 otherwise.
10712 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10713 struct mlx5_flow *dev_flow,
10714 const struct rte_flow_action_count *count
10716 const struct rte_flow_action_age *age)
10719 struct mlx5_age_param *age_param;
10721 counter = flow_dv_counter_alloc(dev, !!age);
10722 if (!counter || age == NULL)
10724 age_param = flow_dv_counter_idx_get_age(dev, counter);
10725 age_param->context = age->context ? age->context :
10726 (void *)(uintptr_t)(dev_flow->flow_idx);
10727 age_param->timeout = age->timeout;
10728 age_param->port_id = dev->data->port_id;
10729 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10730 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10735 * Add Tx queue matcher
10738 * Pointer to the dev struct.
10739 * @param[in, out] matcher
10741 * @param[in, out] key
10742 * Flow matcher value.
10744 * Flow pattern to translate.
10746 * Item is inner pattern.
10749 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10750 void *matcher, void *key,
10751 const struct rte_flow_item *item)
10753 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10754 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10756 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10758 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10759 struct mlx5_txq_ctrl *txq;
10760 uint32_t queue, mask;
10762 queue_m = (const void *)item->mask;
10763 queue_v = (const void *)item->spec;
10766 txq = mlx5_txq_get(dev, queue_v->queue);
10769 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10770 queue = txq->obj->sq->id;
10772 queue = txq->obj->sq_obj.sq->id;
10773 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10774 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10775 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10776 mlx5_txq_release(dev, queue_v->queue);
10780 * Set the hash fields according to the @p flow information.
10782 * @param[in] dev_flow
10783 * Pointer to the mlx5_flow.
10784 * @param[in] rss_desc
10785 * Pointer to the mlx5_flow_rss_desc.
10788 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10789 struct mlx5_flow_rss_desc *rss_desc)
10791 uint64_t items = dev_flow->handle->layers;
10793 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10795 dev_flow->hash_fields = 0;
10796 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10797 if (rss_desc->level >= 2)
10800 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10801 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10802 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10803 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10804 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10805 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10806 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10808 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10810 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10811 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10812 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10813 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10814 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10815 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10816 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10818 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10821 if (dev_flow->hash_fields == 0)
10823 * There is no match between the RSS types and the
10824 * L3 protocol (IPv4/IPv6) defined in the flow rule.
10827 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10828 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10829 if (rss_types & RTE_ETH_RSS_UDP) {
10830 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10831 dev_flow->hash_fields |=
10832 IBV_RX_HASH_SRC_PORT_UDP;
10833 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10834 dev_flow->hash_fields |=
10835 IBV_RX_HASH_DST_PORT_UDP;
10837 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10839 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10840 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10841 if (rss_types & RTE_ETH_RSS_TCP) {
10842 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
10843 dev_flow->hash_fields |=
10844 IBV_RX_HASH_SRC_PORT_TCP;
10845 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
10846 dev_flow->hash_fields |=
10847 IBV_RX_HASH_DST_PORT_TCP;
10849 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10853 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10857 * Prepare an Rx Hash queue.
10860 * Pointer to Ethernet device.
10861 * @param[in] dev_flow
10862 * Pointer to the mlx5_flow.
10863 * @param[in] rss_desc
10864 * Pointer to the mlx5_flow_rss_desc.
10865 * @param[out] hrxq_idx
10866 * Hash Rx queue index.
10869 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10871 static struct mlx5_hrxq *
10872 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10873 struct mlx5_flow *dev_flow,
10874 struct mlx5_flow_rss_desc *rss_desc,
10875 uint32_t *hrxq_idx)
10877 struct mlx5_priv *priv = dev->data->dev_private;
10878 struct mlx5_flow_handle *dh = dev_flow->handle;
10879 struct mlx5_hrxq *hrxq;
10881 MLX5_ASSERT(rss_desc->queue_num);
10882 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10883 rss_desc->hash_fields = dev_flow->hash_fields;
10884 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10885 rss_desc->shared_rss = 0;
10886 if (rss_desc->hash_fields == 0)
10887 rss_desc->queue_num = 1;
10888 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10891 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10897 * Release sample sub action resource.
10899 * @param[in, out] dev
10900 * Pointer to rte_eth_dev structure.
10901 * @param[in] act_res
10902 * Pointer to sample sub action resource.
10905 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10906 struct mlx5_flow_sub_actions_idx *act_res)
10908 if (act_res->rix_hrxq) {
10909 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10910 act_res->rix_hrxq = 0;
10912 if (act_res->rix_encap_decap) {
10913 flow_dv_encap_decap_resource_release(dev,
10914 act_res->rix_encap_decap);
10915 act_res->rix_encap_decap = 0;
10917 if (act_res->rix_port_id_action) {
10918 flow_dv_port_id_action_resource_release(dev,
10919 act_res->rix_port_id_action);
10920 act_res->rix_port_id_action = 0;
10922 if (act_res->rix_tag) {
10923 flow_dv_tag_release(dev, act_res->rix_tag);
10924 act_res->rix_tag = 0;
10926 if (act_res->rix_jump) {
10927 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10928 act_res->rix_jump = 0;
10933 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
10934 struct mlx5_list_entry *entry, void *cb_ctx)
10936 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10937 struct rte_eth_dev *dev = ctx->dev;
10938 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
10939 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
10943 if (ctx_resource->ratio == resource->ratio &&
10944 ctx_resource->ft_type == resource->ft_type &&
10945 ctx_resource->ft_id == resource->ft_id &&
10946 ctx_resource->set_action == resource->set_action &&
10947 !memcmp((void *)&ctx_resource->sample_act,
10948 (void *)&resource->sample_act,
10949 sizeof(struct mlx5_flow_sub_actions_list))) {
10951 * Existing sample action should release the prepared
10952 * sub-actions reference counter.
10954 flow_dv_sample_sub_actions_release(dev,
10955 &ctx_resource->sample_idx);
10961 struct mlx5_list_entry *
10962 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
10964 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10965 struct rte_eth_dev *dev = ctx->dev;
10966 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
10967 void **sample_dv_actions = ctx_resource->sub_actions;
10968 struct mlx5_flow_dv_sample_resource *resource;
10969 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10970 struct mlx5_priv *priv = dev->data->dev_private;
10971 struct mlx5_dev_ctx_shared *sh = priv->sh;
10972 struct mlx5_flow_tbl_resource *tbl;
10974 const uint32_t next_ft_step = 1;
10975 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
10976 uint8_t is_egress = 0;
10977 uint8_t is_transfer = 0;
10978 struct rte_flow_error *error = ctx->error;
10980 /* Register new sample resource. */
10981 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10983 rte_flow_error_set(error, ENOMEM,
10984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10986 "cannot allocate resource memory");
10989 *resource = *ctx_resource;
10990 /* Create normal path table level */
10991 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10993 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10995 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10996 is_egress, is_transfer,
10997 true, NULL, 0, 0, 0, error);
10999 rte_flow_error_set(error, ENOMEM,
11000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11002 "fail to create normal path table "
11006 resource->normal_path_tbl = tbl;
11007 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11008 if (!sh->default_miss_action) {
11009 rte_flow_error_set(error, ENOMEM,
11010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11012 "default miss action was not "
11016 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11017 sh->default_miss_action;
11019 /* Create a DR sample action */
11020 sampler_attr.sample_ratio = resource->ratio;
11021 sampler_attr.default_next_table = tbl->obj;
11022 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11023 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11024 &sample_dv_actions[0];
11025 sampler_attr.action = resource->set_action;
11026 if (mlx5_os_flow_dr_create_flow_action_sampler
11027 (&sampler_attr, &resource->verbs_action)) {
11028 rte_flow_error_set(error, ENOMEM,
11029 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11030 NULL, "cannot create sample action");
11033 resource->idx = idx;
11034 resource->dev = dev;
11035 return &resource->entry;
11037 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11038 flow_dv_sample_sub_actions_release(dev,
11039 &resource->sample_idx);
11040 if (resource->normal_path_tbl)
11041 flow_dv_tbl_resource_release(MLX5_SH(dev),
11042 resource->normal_path_tbl);
11043 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11048 struct mlx5_list_entry *
11049 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11050 struct mlx5_list_entry *entry __rte_unused,
11053 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11054 struct rte_eth_dev *dev = ctx->dev;
11055 struct mlx5_flow_dv_sample_resource *resource;
11056 struct mlx5_priv *priv = dev->data->dev_private;
11057 struct mlx5_dev_ctx_shared *sh = priv->sh;
11060 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11062 rte_flow_error_set(ctx->error, ENOMEM,
11063 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11065 "cannot allocate resource memory");
11068 memcpy(resource, entry, sizeof(*resource));
11069 resource->idx = idx;
11070 resource->dev = dev;
11071 return &resource->entry;
11075 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11076 struct mlx5_list_entry *entry)
11078 struct mlx5_flow_dv_sample_resource *resource =
11079 container_of(entry, typeof(*resource), entry);
11080 struct rte_eth_dev *dev = resource->dev;
11081 struct mlx5_priv *priv = dev->data->dev_private;
11083 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11087 * Find existing sample resource or create and register a new one.
11089 * @param[in, out] dev
11090 * Pointer to rte_eth_dev structure.
11092 * Pointer to sample resource reference.
11093 * @parm[in, out] dev_flow
11094 * Pointer to the dev_flow.
11095 * @param[out] error
11096 * pointer to error structure.
11099 * 0 on success otherwise -errno and errno is set.
11102 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11103 struct mlx5_flow_dv_sample_resource *ref,
11104 struct mlx5_flow *dev_flow,
11105 struct rte_flow_error *error)
11107 struct mlx5_flow_dv_sample_resource *resource;
11108 struct mlx5_list_entry *entry;
11109 struct mlx5_priv *priv = dev->data->dev_private;
11110 struct mlx5_flow_cb_ctx ctx = {
11116 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11119 resource = container_of(entry, typeof(*resource), entry);
11120 dev_flow->handle->dvh.rix_sample = resource->idx;
11121 dev_flow->dv.sample_res = resource;
11126 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11127 struct mlx5_list_entry *entry, void *cb_ctx)
11129 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11130 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11131 struct rte_eth_dev *dev = ctx->dev;
11132 struct mlx5_flow_dv_dest_array_resource *resource =
11133 container_of(entry, typeof(*resource), entry);
11136 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11137 ctx_resource->ft_type == resource->ft_type &&
11138 !memcmp((void *)resource->sample_act,
11139 (void *)ctx_resource->sample_act,
11140 (ctx_resource->num_of_dest *
11141 sizeof(struct mlx5_flow_sub_actions_list)))) {
11143 * Existing sample action should release the prepared
11144 * sub-actions reference counter.
11146 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11147 flow_dv_sample_sub_actions_release(dev,
11148 &ctx_resource->sample_idx[idx]);
11154 struct mlx5_list_entry *
11155 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11157 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11158 struct rte_eth_dev *dev = ctx->dev;
11159 struct mlx5_flow_dv_dest_array_resource *resource;
11160 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11161 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11162 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11163 struct mlx5_priv *priv = dev->data->dev_private;
11164 struct mlx5_dev_ctx_shared *sh = priv->sh;
11165 struct mlx5_flow_sub_actions_list *sample_act;
11166 struct mlx5dv_dr_domain *domain;
11167 uint32_t idx = 0, res_idx = 0;
11168 struct rte_flow_error *error = ctx->error;
11169 uint64_t action_flags;
11172 /* Register new destination array resource. */
11173 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11176 rte_flow_error_set(error, ENOMEM,
11177 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11179 "cannot allocate resource memory");
11182 *resource = *ctx_resource;
11183 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11184 domain = sh->fdb_domain;
11185 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11186 domain = sh->rx_domain;
11188 domain = sh->tx_domain;
11189 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11190 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11191 mlx5_malloc(MLX5_MEM_ZERO,
11192 sizeof(struct mlx5dv_dr_action_dest_attr),
11194 if (!dest_attr[idx]) {
11195 rte_flow_error_set(error, ENOMEM,
11196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11198 "cannot allocate resource memory");
11201 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11202 sample_act = &ctx_resource->sample_act[idx];
11203 action_flags = sample_act->action_flags;
11204 switch (action_flags) {
11205 case MLX5_FLOW_ACTION_QUEUE:
11206 dest_attr[idx]->dest = sample_act->dr_queue_action;
11208 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11209 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11210 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11211 dest_attr[idx]->dest_reformat->reformat =
11212 sample_act->dr_encap_action;
11213 dest_attr[idx]->dest_reformat->dest =
11214 sample_act->dr_port_id_action;
11216 case MLX5_FLOW_ACTION_PORT_ID:
11217 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11219 case MLX5_FLOW_ACTION_JUMP:
11220 dest_attr[idx]->dest = sample_act->dr_jump_action;
11223 rte_flow_error_set(error, EINVAL,
11224 RTE_FLOW_ERROR_TYPE_ACTION,
11226 "unsupported actions type");
11230 /* create a dest array actioin */
11231 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11233 resource->num_of_dest,
11235 &resource->action);
11237 rte_flow_error_set(error, ENOMEM,
11238 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11240 "cannot create destination array action");
11243 resource->idx = res_idx;
11244 resource->dev = dev;
11245 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11246 mlx5_free(dest_attr[idx]);
11247 return &resource->entry;
11249 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11250 flow_dv_sample_sub_actions_release(dev,
11251 &resource->sample_idx[idx]);
11252 if (dest_attr[idx])
11253 mlx5_free(dest_attr[idx]);
11255 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11259 struct mlx5_list_entry *
11260 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11261 struct mlx5_list_entry *entry __rte_unused,
11264 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11265 struct rte_eth_dev *dev = ctx->dev;
11266 struct mlx5_flow_dv_dest_array_resource *resource;
11267 struct mlx5_priv *priv = dev->data->dev_private;
11268 struct mlx5_dev_ctx_shared *sh = priv->sh;
11269 uint32_t res_idx = 0;
11270 struct rte_flow_error *error = ctx->error;
11272 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11275 rte_flow_error_set(error, ENOMEM,
11276 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11278 "cannot allocate dest-array memory");
11281 memcpy(resource, entry, sizeof(*resource));
11282 resource->idx = res_idx;
11283 resource->dev = dev;
11284 return &resource->entry;
11288 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11289 struct mlx5_list_entry *entry)
11291 struct mlx5_flow_dv_dest_array_resource *resource =
11292 container_of(entry, typeof(*resource), entry);
11293 struct rte_eth_dev *dev = resource->dev;
11294 struct mlx5_priv *priv = dev->data->dev_private;
11296 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11300 * Find existing destination array resource or create and register a new one.
11302 * @param[in, out] dev
11303 * Pointer to rte_eth_dev structure.
11305 * Pointer to destination array resource reference.
11306 * @parm[in, out] dev_flow
11307 * Pointer to the dev_flow.
11308 * @param[out] error
11309 * pointer to error structure.
11312 * 0 on success otherwise -errno and errno is set.
11315 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11316 struct mlx5_flow_dv_dest_array_resource *ref,
11317 struct mlx5_flow *dev_flow,
11318 struct rte_flow_error *error)
11320 struct mlx5_flow_dv_dest_array_resource *resource;
11321 struct mlx5_priv *priv = dev->data->dev_private;
11322 struct mlx5_list_entry *entry;
11323 struct mlx5_flow_cb_ctx ctx = {
11329 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11332 resource = container_of(entry, typeof(*resource), entry);
11333 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11334 dev_flow->dv.dest_array_res = resource;
11339 * Convert Sample action to DV specification.
11342 * Pointer to rte_eth_dev structure.
11343 * @param[in] action
11344 * Pointer to sample action structure.
11345 * @param[in, out] dev_flow
11346 * Pointer to the mlx5_flow.
11348 * Pointer to the flow attributes.
11349 * @param[in, out] num_of_dest
11350 * Pointer to the num of destination.
11351 * @param[in, out] sample_actions
11352 * Pointer to sample actions list.
11353 * @param[in, out] res
11354 * Pointer to sample resource.
11355 * @param[out] error
11356 * Pointer to the error structure.
11359 * 0 on success, a negative errno value otherwise and rte_errno is set.
11362 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11363 const struct rte_flow_action_sample *action,
11364 struct mlx5_flow *dev_flow,
11365 const struct rte_flow_attr *attr,
11366 uint32_t *num_of_dest,
11367 void **sample_actions,
11368 struct mlx5_flow_dv_sample_resource *res,
11369 struct rte_flow_error *error)
11371 struct mlx5_priv *priv = dev->data->dev_private;
11372 const struct rte_flow_action *sub_actions;
11373 struct mlx5_flow_sub_actions_list *sample_act;
11374 struct mlx5_flow_sub_actions_idx *sample_idx;
11375 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11376 struct rte_flow *flow = dev_flow->flow;
11377 struct mlx5_flow_rss_desc *rss_desc;
11378 uint64_t action_flags = 0;
11381 rss_desc = &wks->rss_desc;
11382 sample_act = &res->sample_act;
11383 sample_idx = &res->sample_idx;
11384 res->ratio = action->ratio;
11385 sub_actions = action->actions;
11386 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11387 int type = sub_actions->type;
11388 uint32_t pre_rix = 0;
11391 case RTE_FLOW_ACTION_TYPE_QUEUE:
11393 const struct rte_flow_action_queue *queue;
11394 struct mlx5_hrxq *hrxq;
11397 queue = sub_actions->conf;
11398 rss_desc->queue_num = 1;
11399 rss_desc->queue[0] = queue->index;
11400 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11401 rss_desc, &hrxq_idx);
11403 return rte_flow_error_set
11405 RTE_FLOW_ERROR_TYPE_ACTION,
11407 "cannot create fate queue");
11408 sample_act->dr_queue_action = hrxq->action;
11409 sample_idx->rix_hrxq = hrxq_idx;
11410 sample_actions[sample_act->actions_num++] =
11413 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11414 if (action_flags & MLX5_FLOW_ACTION_MARK)
11415 dev_flow->handle->rix_hrxq = hrxq_idx;
11416 dev_flow->handle->fate_action =
11417 MLX5_FLOW_FATE_QUEUE;
11420 case RTE_FLOW_ACTION_TYPE_RSS:
11422 struct mlx5_hrxq *hrxq;
11424 const struct rte_flow_action_rss *rss;
11425 const uint8_t *rss_key;
11427 rss = sub_actions->conf;
11428 memcpy(rss_desc->queue, rss->queue,
11429 rss->queue_num * sizeof(uint16_t));
11430 rss_desc->queue_num = rss->queue_num;
11431 /* NULL RSS key indicates default RSS key. */
11432 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11433 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11435 * rss->level and rss.types should be set in advance
11436 * when expanding items for RSS.
11438 flow_dv_hashfields_set(dev_flow, rss_desc);
11439 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11440 rss_desc, &hrxq_idx);
11442 return rte_flow_error_set
11444 RTE_FLOW_ERROR_TYPE_ACTION,
11446 "cannot create fate queue");
11447 sample_act->dr_queue_action = hrxq->action;
11448 sample_idx->rix_hrxq = hrxq_idx;
11449 sample_actions[sample_act->actions_num++] =
11452 action_flags |= MLX5_FLOW_ACTION_RSS;
11453 if (action_flags & MLX5_FLOW_ACTION_MARK)
11454 dev_flow->handle->rix_hrxq = hrxq_idx;
11455 dev_flow->handle->fate_action =
11456 MLX5_FLOW_FATE_QUEUE;
11459 case RTE_FLOW_ACTION_TYPE_MARK:
11461 uint32_t tag_be = mlx5_flow_mark_set
11462 (((const struct rte_flow_action_mark *)
11463 (sub_actions->conf))->id);
11465 dev_flow->handle->mark = 1;
11466 pre_rix = dev_flow->handle->dvh.rix_tag;
11467 /* Save the mark resource before sample */
11468 pre_r = dev_flow->dv.tag_resource;
11469 if (flow_dv_tag_resource_register(dev, tag_be,
11472 MLX5_ASSERT(dev_flow->dv.tag_resource);
11473 sample_act->dr_tag_action =
11474 dev_flow->dv.tag_resource->action;
11475 sample_idx->rix_tag =
11476 dev_flow->handle->dvh.rix_tag;
11477 sample_actions[sample_act->actions_num++] =
11478 sample_act->dr_tag_action;
11479 /* Recover the mark resource after sample */
11480 dev_flow->dv.tag_resource = pre_r;
11481 dev_flow->handle->dvh.rix_tag = pre_rix;
11482 action_flags |= MLX5_FLOW_ACTION_MARK;
11485 case RTE_FLOW_ACTION_TYPE_COUNT:
11487 if (!flow->counter) {
11489 flow_dv_translate_create_counter(dev,
11490 dev_flow, sub_actions->conf,
11492 if (!flow->counter)
11493 return rte_flow_error_set
11495 RTE_FLOW_ERROR_TYPE_ACTION,
11497 "cannot create counter"
11500 sample_act->dr_cnt_action =
11501 (flow_dv_counter_get_by_idx(dev,
11502 flow->counter, NULL))->action;
11503 sample_actions[sample_act->actions_num++] =
11504 sample_act->dr_cnt_action;
11505 action_flags |= MLX5_FLOW_ACTION_COUNT;
11508 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11509 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11511 struct mlx5_flow_dv_port_id_action_resource
11513 uint32_t port_id = 0;
11515 memset(&port_id_resource, 0, sizeof(port_id_resource));
11516 /* Save the port id resource before sample */
11517 pre_rix = dev_flow->handle->rix_port_id_action;
11518 pre_r = dev_flow->dv.port_id_action;
11519 if (flow_dv_translate_action_port_id(dev, sub_actions,
11522 port_id_resource.port_id = port_id;
11523 if (flow_dv_port_id_action_resource_register
11524 (dev, &port_id_resource, dev_flow, error))
11526 sample_act->dr_port_id_action =
11527 dev_flow->dv.port_id_action->action;
11528 sample_idx->rix_port_id_action =
11529 dev_flow->handle->rix_port_id_action;
11530 sample_actions[sample_act->actions_num++] =
11531 sample_act->dr_port_id_action;
11532 /* Recover the port id resource after sample */
11533 dev_flow->dv.port_id_action = pre_r;
11534 dev_flow->handle->rix_port_id_action = pre_rix;
11536 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11539 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11540 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11541 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11542 /* Save the encap resource before sample */
11543 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11544 pre_r = dev_flow->dv.encap_decap;
11545 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11550 sample_act->dr_encap_action =
11551 dev_flow->dv.encap_decap->action;
11552 sample_idx->rix_encap_decap =
11553 dev_flow->handle->dvh.rix_encap_decap;
11554 sample_actions[sample_act->actions_num++] =
11555 sample_act->dr_encap_action;
11556 /* Recover the encap resource after sample */
11557 dev_flow->dv.encap_decap = pre_r;
11558 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11559 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11562 return rte_flow_error_set(error, EINVAL,
11563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11565 "Not support for sampler action");
11568 sample_act->action_flags = action_flags;
11569 res->ft_id = dev_flow->dv.group;
11570 if (attr->transfer) {
11572 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11573 uint64_t set_action;
11574 } action_ctx = { .set_action = 0 };
11576 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11577 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11578 MLX5_MODIFICATION_TYPE_SET);
11579 MLX5_SET(set_action_in, action_ctx.action_in, field,
11580 MLX5_MODI_META_REG_C_0);
11581 MLX5_SET(set_action_in, action_ctx.action_in, data,
11582 priv->vport_meta_tag);
11583 res->set_action = action_ctx.set_action;
11584 } else if (attr->ingress) {
11585 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11587 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11593 * Convert Sample action to DV specification.
11596 * Pointer to rte_eth_dev structure.
11597 * @param[in, out] dev_flow
11598 * Pointer to the mlx5_flow.
11599 * @param[in] num_of_dest
11600 * The num of destination.
11601 * @param[in, out] res
11602 * Pointer to sample resource.
11603 * @param[in, out] mdest_res
11604 * Pointer to destination array resource.
11605 * @param[in] sample_actions
11606 * Pointer to sample path actions list.
11607 * @param[in] action_flags
11608 * Holds the actions detected until now.
11609 * @param[out] error
11610 * Pointer to the error structure.
11613 * 0 on success, a negative errno value otherwise and rte_errno is set.
11616 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11617 struct mlx5_flow *dev_flow,
11618 uint32_t num_of_dest,
11619 struct mlx5_flow_dv_sample_resource *res,
11620 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11621 void **sample_actions,
11622 uint64_t action_flags,
11623 struct rte_flow_error *error)
11625 /* update normal path action resource into last index of array */
11626 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11627 struct mlx5_flow_sub_actions_list *sample_act =
11628 &mdest_res->sample_act[dest_index];
11629 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11630 struct mlx5_flow_rss_desc *rss_desc;
11631 uint32_t normal_idx = 0;
11632 struct mlx5_hrxq *hrxq;
11636 rss_desc = &wks->rss_desc;
11637 if (num_of_dest > 1) {
11638 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11639 /* Handle QP action for mirroring */
11640 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11641 rss_desc, &hrxq_idx);
11643 return rte_flow_error_set
11645 RTE_FLOW_ERROR_TYPE_ACTION,
11647 "cannot create rx queue");
11649 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11650 sample_act->dr_queue_action = hrxq->action;
11651 if (action_flags & MLX5_FLOW_ACTION_MARK)
11652 dev_flow->handle->rix_hrxq = hrxq_idx;
11653 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11655 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11657 mdest_res->sample_idx[dest_index].rix_encap_decap =
11658 dev_flow->handle->dvh.rix_encap_decap;
11659 sample_act->dr_encap_action =
11660 dev_flow->dv.encap_decap->action;
11661 dev_flow->handle->dvh.rix_encap_decap = 0;
11663 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11665 mdest_res->sample_idx[dest_index].rix_port_id_action =
11666 dev_flow->handle->rix_port_id_action;
11667 sample_act->dr_port_id_action =
11668 dev_flow->dv.port_id_action->action;
11669 dev_flow->handle->rix_port_id_action = 0;
11671 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11673 mdest_res->sample_idx[dest_index].rix_jump =
11674 dev_flow->handle->rix_jump;
11675 sample_act->dr_jump_action =
11676 dev_flow->dv.jump->action;
11677 dev_flow->handle->rix_jump = 0;
11679 sample_act->actions_num = normal_idx;
11680 /* update sample action resource into first index of array */
11681 mdest_res->ft_type = res->ft_type;
11682 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11683 sizeof(struct mlx5_flow_sub_actions_idx));
11684 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11685 sizeof(struct mlx5_flow_sub_actions_list));
11686 mdest_res->num_of_dest = num_of_dest;
11687 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11689 return rte_flow_error_set(error, EINVAL,
11690 RTE_FLOW_ERROR_TYPE_ACTION,
11691 NULL, "can't create sample "
11694 res->sub_actions = sample_actions;
11695 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11696 return rte_flow_error_set(error, EINVAL,
11697 RTE_FLOW_ERROR_TYPE_ACTION,
11699 "can't create sample action");
11705 * Remove an ASO age action from age actions list.
11708 * Pointer to the Ethernet device structure.
11710 * Pointer to the aso age action handler.
11713 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11714 struct mlx5_aso_age_action *age)
11716 struct mlx5_age_info *age_info;
11717 struct mlx5_age_param *age_param = &age->age_params;
11718 struct mlx5_priv *priv = dev->data->dev_private;
11719 uint16_t expected = AGE_CANDIDATE;
11721 age_info = GET_PORT_AGE_INFO(priv);
11722 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11723 AGE_FREE, false, __ATOMIC_RELAXED,
11724 __ATOMIC_RELAXED)) {
11726 * We need the lock even it is age timeout,
11727 * since age action may still in process.
11729 rte_spinlock_lock(&age_info->aged_sl);
11730 LIST_REMOVE(age, next);
11731 rte_spinlock_unlock(&age_info->aged_sl);
11732 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11737 * Release an ASO age action.
11740 * Pointer to the Ethernet device structure.
11741 * @param[in] age_idx
11742 * Index of ASO age action to release.
11744 * True if the release operation is during flow destroy operation.
11745 * False if the release operation is during action destroy operation.
11748 * 0 when age action was removed, otherwise the number of references.
11751 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11753 struct mlx5_priv *priv = dev->data->dev_private;
11754 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11755 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11756 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11759 flow_dv_aso_age_remove_from_age(dev, age);
11760 rte_spinlock_lock(&mng->free_sl);
11761 LIST_INSERT_HEAD(&mng->free, age, next);
11762 rte_spinlock_unlock(&mng->free_sl);
11768 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11771 * Pointer to the Ethernet device structure.
11774 * 0 on success, otherwise negative errno value and rte_errno is set.
11777 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11779 struct mlx5_priv *priv = dev->data->dev_private;
11780 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11781 void *old_pools = mng->pools;
11782 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11783 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11784 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11787 rte_errno = ENOMEM;
11791 memcpy(pools, old_pools,
11792 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11793 mlx5_free(old_pools);
11795 /* First ASO flow hit allocation - starting ASO data-path. */
11796 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11804 mng->pools = pools;
11809 * Create and initialize a new ASO aging pool.
11812 * Pointer to the Ethernet device structure.
11813 * @param[out] age_free
11814 * Where to put the pointer of a new age action.
11817 * The age actions pool pointer and @p age_free is set on success,
11818 * NULL otherwise and rte_errno is set.
11820 static struct mlx5_aso_age_pool *
11821 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11822 struct mlx5_aso_age_action **age_free)
11824 struct mlx5_priv *priv = dev->data->dev_private;
11825 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11826 struct mlx5_aso_age_pool *pool = NULL;
11827 struct mlx5_devx_obj *obj = NULL;
11830 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
11831 priv->sh->cdev->pdn);
11833 rte_errno = ENODATA;
11834 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11837 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11839 claim_zero(mlx5_devx_cmd_destroy(obj));
11840 rte_errno = ENOMEM;
11843 pool->flow_hit_aso_obj = obj;
11844 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11845 rte_spinlock_lock(&mng->resize_sl);
11846 pool->index = mng->next;
11847 /* Resize pools array if there is no room for the new pool in it. */
11848 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11849 claim_zero(mlx5_devx_cmd_destroy(obj));
11851 rte_spinlock_unlock(&mng->resize_sl);
11854 mng->pools[pool->index] = pool;
11856 rte_spinlock_unlock(&mng->resize_sl);
11857 /* Assign the first action in the new pool, the rest go to free list. */
11858 *age_free = &pool->actions[0];
11859 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11860 pool->actions[i].offset = i;
11861 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
11867 * Allocate a ASO aging bit.
11870 * Pointer to the Ethernet device structure.
11871 * @param[out] error
11872 * Pointer to the error structure.
11875 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
11878 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
11880 struct mlx5_priv *priv = dev->data->dev_private;
11881 const struct mlx5_aso_age_pool *pool;
11882 struct mlx5_aso_age_action *age_free = NULL;
11883 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11886 /* Try to get the next free age action bit. */
11887 rte_spinlock_lock(&mng->free_sl);
11888 age_free = LIST_FIRST(&mng->free);
11890 LIST_REMOVE(age_free, next);
11891 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
11892 rte_spinlock_unlock(&mng->free_sl);
11893 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
11894 NULL, "failed to create ASO age pool");
11895 return 0; /* 0 is an error. */
11897 rte_spinlock_unlock(&mng->free_sl);
11898 pool = container_of
11899 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
11900 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
11902 if (!age_free->dr_action) {
11903 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
11907 rte_flow_error_set(error, rte_errno,
11908 RTE_FLOW_ERROR_TYPE_ACTION,
11909 NULL, "failed to get reg_c "
11910 "for ASO flow hit");
11911 return 0; /* 0 is an error. */
11913 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
11914 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
11915 (priv->sh->rx_domain,
11916 pool->flow_hit_aso_obj->obj, age_free->offset,
11917 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
11918 (reg_c - REG_C_0));
11919 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
11920 if (!age_free->dr_action) {
11922 rte_spinlock_lock(&mng->free_sl);
11923 LIST_INSERT_HEAD(&mng->free, age_free, next);
11924 rte_spinlock_unlock(&mng->free_sl);
11925 rte_flow_error_set(error, rte_errno,
11926 RTE_FLOW_ERROR_TYPE_ACTION,
11927 NULL, "failed to create ASO "
11928 "flow hit action");
11929 return 0; /* 0 is an error. */
11932 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
11933 return pool->index | ((age_free->offset + 1) << 16);
11937 * Initialize flow ASO age parameters.
11940 * Pointer to rte_eth_dev structure.
11941 * @param[in] age_idx
11942 * Index of ASO age action.
11943 * @param[in] context
11944 * Pointer to flow counter age context.
11945 * @param[in] timeout
11946 * Aging timeout in seconds.
11950 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
11955 struct mlx5_aso_age_action *aso_age;
11957 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11958 MLX5_ASSERT(aso_age);
11959 aso_age->age_params.context = context;
11960 aso_age->age_params.timeout = timeout;
11961 aso_age->age_params.port_id = dev->data->port_id;
11962 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11964 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11969 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
11970 const struct rte_flow_item_integrity *value,
11971 void *headers_m, void *headers_v)
11974 /* application l4_ok filter aggregates all hardware l4 filters
11975 * therefore hw l4_checksum_ok must be implicitly added here.
11977 struct rte_flow_item_integrity local_item;
11979 local_item.l4_csum_ok = 1;
11980 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
11981 local_item.l4_csum_ok);
11982 if (value->l4_ok) {
11983 /* application l4_ok = 1 matches sets both hw flags
11984 * l4_ok and l4_checksum_ok flags to 1.
11986 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11987 l4_checksum_ok, local_item.l4_csum_ok);
11988 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok,
11990 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok,
11993 /* application l4_ok = 0 matches on hw flag
11994 * l4_checksum_ok = 0 only.
11996 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11997 l4_checksum_ok, 0);
11999 } else if (mask->l4_csum_ok) {
12000 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
12002 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12003 value->l4_csum_ok);
12008 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12009 const struct rte_flow_item_integrity *value,
12010 void *headers_m, void *headers_v, bool is_ipv4)
12013 /* application l3_ok filter aggregates all hardware l3 filters
12014 * therefore hw ipv4_checksum_ok must be implicitly added here.
12016 struct rte_flow_item_integrity local_item;
12018 local_item.ipv4_csum_ok = !!is_ipv4;
12019 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12020 local_item.ipv4_csum_ok);
12021 if (value->l3_ok) {
12022 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12023 ipv4_checksum_ok, local_item.ipv4_csum_ok);
12024 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok,
12026 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12029 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12030 ipv4_checksum_ok, 0);
12032 } else if (mask->ipv4_csum_ok) {
12033 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
12034 mask->ipv4_csum_ok);
12035 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12036 value->ipv4_csum_ok);
12041 set_integrity_bits(void *headers_m, void *headers_v,
12042 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12044 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12045 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12047 /* Integrity bits validation cleared spec pointer */
12048 MLX5_ASSERT(spec != NULL);
12050 mask = &rte_flow_item_integrity_mask;
12051 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12053 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12057 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12059 struct rte_flow_item *integrity_items[2],
12060 uint64_t pattern_flags)
12062 void *headers_m, *headers_v;
12065 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12066 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12068 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12069 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12071 set_integrity_bits(headers_m, headers_v,
12072 integrity_items[1], is_l3_ip4);
12074 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12075 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12077 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12078 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12080 set_integrity_bits(headers_m, headers_v,
12081 integrity_items[0], is_l3_ip4);
12086 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12087 const struct rte_flow_item *integrity_items[2],
12088 uint64_t *last_item)
12090 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12092 /* integrity bits validation cleared spec pointer */
12093 MLX5_ASSERT(spec != NULL);
12094 if (spec->level > 1) {
12095 integrity_items[1] = item;
12096 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12098 integrity_items[0] = item;
12099 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12104 * Prepares DV flow counter with aging configuration.
12105 * Gets it by index when exists, creates a new one when doesn't.
12108 * Pointer to rte_eth_dev structure.
12109 * @param[in] dev_flow
12110 * Pointer to the mlx5_flow.
12111 * @param[in, out] flow
12112 * Pointer to the sub flow.
12114 * Pointer to the counter action configuration.
12116 * Pointer to the aging action configuration.
12117 * @param[out] error
12118 * Pointer to the error structure.
12121 * Pointer to the counter, NULL otherwise.
12123 static struct mlx5_flow_counter *
12124 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12125 struct mlx5_flow *dev_flow,
12126 struct rte_flow *flow,
12127 const struct rte_flow_action_count *count,
12128 const struct rte_flow_action_age *age,
12129 struct rte_flow_error *error)
12131 if (!flow->counter) {
12132 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12134 if (!flow->counter) {
12135 rte_flow_error_set(error, rte_errno,
12136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12137 "cannot create counter object.");
12141 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12145 * Release an ASO CT action by its own device.
12148 * Pointer to the Ethernet device structure.
12150 * Index of ASO CT action to release.
12153 * 0 when CT action was removed, otherwise the number of references.
12156 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12158 struct mlx5_priv *priv = dev->data->dev_private;
12159 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12161 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12162 enum mlx5_aso_ct_state state =
12163 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12165 /* Cannot release when CT is in the ASO SQ. */
12166 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12168 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12170 if (ct->dr_action_orig) {
12171 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12172 claim_zero(mlx5_glue->destroy_flow_action
12173 (ct->dr_action_orig));
12175 ct->dr_action_orig = NULL;
12177 if (ct->dr_action_rply) {
12178 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12179 claim_zero(mlx5_glue->destroy_flow_action
12180 (ct->dr_action_rply));
12182 ct->dr_action_rply = NULL;
12184 /* Clear the state to free, no need in 1st allocation. */
12185 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12186 rte_spinlock_lock(&mng->ct_sl);
12187 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12188 rte_spinlock_unlock(&mng->ct_sl);
12194 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12195 struct rte_flow_error *error)
12197 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12198 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12199 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12202 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12203 if (dev->data->dev_started != 1)
12204 return rte_flow_error_set(error, EAGAIN,
12205 RTE_FLOW_ERROR_TYPE_ACTION,
12207 "Indirect CT action cannot be destroyed when the port is stopped");
12208 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12210 return rte_flow_error_set(error, EAGAIN,
12211 RTE_FLOW_ERROR_TYPE_ACTION,
12213 "Current state prevents indirect CT action from being destroyed");
12218 * Resize the ASO CT pools array by 64 pools.
12221 * Pointer to the Ethernet device structure.
12224 * 0 on success, otherwise negative errno value and rte_errno is set.
12227 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12229 struct mlx5_priv *priv = dev->data->dev_private;
12230 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12231 void *old_pools = mng->pools;
12232 /* Magic number now, need a macro. */
12233 uint32_t resize = mng->n + 64;
12234 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12235 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12238 rte_errno = ENOMEM;
12241 rte_rwlock_write_lock(&mng->resize_rwl);
12242 /* ASO SQ/QP was already initialized in the startup. */
12244 /* Realloc could be an alternative choice. */
12245 rte_memcpy(pools, old_pools,
12246 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12247 mlx5_free(old_pools);
12250 mng->pools = pools;
12251 rte_rwlock_write_unlock(&mng->resize_rwl);
12256 * Create and initialize a new ASO CT pool.
12259 * Pointer to the Ethernet device structure.
12260 * @param[out] ct_free
12261 * Where to put the pointer of a new CT action.
12264 * The CT actions pool pointer and @p ct_free is set on success,
12265 * NULL otherwise and rte_errno is set.
12267 static struct mlx5_aso_ct_pool *
12268 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12269 struct mlx5_aso_ct_action **ct_free)
12271 struct mlx5_priv *priv = dev->data->dev_private;
12272 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12273 struct mlx5_aso_ct_pool *pool = NULL;
12274 struct mlx5_devx_obj *obj = NULL;
12276 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12278 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12279 priv->sh->cdev->pdn,
12282 rte_errno = ENODATA;
12283 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12286 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12288 rte_errno = ENOMEM;
12289 claim_zero(mlx5_devx_cmd_destroy(obj));
12292 pool->devx_obj = obj;
12293 pool->index = mng->next;
12294 /* Resize pools array if there is no room for the new pool in it. */
12295 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12296 claim_zero(mlx5_devx_cmd_destroy(obj));
12300 mng->pools[pool->index] = pool;
12302 /* Assign the first action in the new pool, the rest go to free list. */
12303 *ct_free = &pool->actions[0];
12304 /* Lock outside, the list operation is safe here. */
12305 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12306 /* refcnt is 0 when allocating the memory. */
12307 pool->actions[i].offset = i;
12308 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12314 * Allocate a ASO CT action from free list.
12317 * Pointer to the Ethernet device structure.
12318 * @param[out] error
12319 * Pointer to the error structure.
12322 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12325 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12327 struct mlx5_priv *priv = dev->data->dev_private;
12328 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12329 struct mlx5_aso_ct_action *ct = NULL;
12330 struct mlx5_aso_ct_pool *pool;
12335 if (!priv->sh->devx) {
12336 rte_errno = ENOTSUP;
12339 /* Get a free CT action, if no, a new pool will be created. */
12340 rte_spinlock_lock(&mng->ct_sl);
12341 ct = LIST_FIRST(&mng->free_cts);
12343 LIST_REMOVE(ct, next);
12344 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12345 rte_spinlock_unlock(&mng->ct_sl);
12346 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12347 NULL, "failed to create ASO CT pool");
12350 rte_spinlock_unlock(&mng->ct_sl);
12351 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12352 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12353 /* 0: inactive, 1: created, 2+: used by flows. */
12354 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12355 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12356 if (!ct->dr_action_orig) {
12357 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12358 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12359 (priv->sh->rx_domain, pool->devx_obj->obj,
12361 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12364 RTE_SET_USED(reg_c);
12366 if (!ct->dr_action_orig) {
12367 flow_dv_aso_ct_dev_release(dev, ct_idx);
12368 rte_flow_error_set(error, rte_errno,
12369 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12370 "failed to create ASO CT action");
12374 if (!ct->dr_action_rply) {
12375 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12376 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12377 (priv->sh->rx_domain, pool->devx_obj->obj,
12379 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12382 if (!ct->dr_action_rply) {
12383 flow_dv_aso_ct_dev_release(dev, ct_idx);
12384 rte_flow_error_set(error, rte_errno,
12385 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12386 "failed to create ASO CT action");
12394 * Create a conntrack object with context and actions by using ASO mechanism.
12397 * Pointer to rte_eth_dev structure.
12399 * Pointer to conntrack information profile.
12400 * @param[out] error
12401 * Pointer to the error structure.
12404 * Index to conntrack object on success, 0 otherwise.
12407 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12408 const struct rte_flow_action_conntrack *pro,
12409 struct rte_flow_error *error)
12411 struct mlx5_priv *priv = dev->data->dev_private;
12412 struct mlx5_dev_ctx_shared *sh = priv->sh;
12413 struct mlx5_aso_ct_action *ct;
12416 if (!sh->ct_aso_en)
12417 return rte_flow_error_set(error, ENOTSUP,
12418 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12419 "Connection is not supported");
12420 idx = flow_dv_aso_ct_alloc(dev, error);
12422 return rte_flow_error_set(error, rte_errno,
12423 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12424 "Failed to allocate CT object");
12425 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12426 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12427 return rte_flow_error_set(error, EBUSY,
12428 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12429 "Failed to update CT");
12430 ct->is_original = !!pro->is_original_dir;
12431 ct->peer = pro->peer_port;
12436 * Fill the flow with DV spec, lock free
12437 * (mutex should be acquired by caller).
12440 * Pointer to rte_eth_dev structure.
12441 * @param[in, out] dev_flow
12442 * Pointer to the sub flow.
12444 * Pointer to the flow attributes.
12446 * Pointer to the list of items.
12447 * @param[in] actions
12448 * Pointer to the list of actions.
12449 * @param[out] error
12450 * Pointer to the error structure.
12453 * 0 on success, a negative errno value otherwise and rte_errno is set.
12456 flow_dv_translate(struct rte_eth_dev *dev,
12457 struct mlx5_flow *dev_flow,
12458 const struct rte_flow_attr *attr,
12459 const struct rte_flow_item items[],
12460 const struct rte_flow_action actions[],
12461 struct rte_flow_error *error)
12463 struct mlx5_priv *priv = dev->data->dev_private;
12464 struct mlx5_dev_config *dev_conf = &priv->config;
12465 struct rte_flow *flow = dev_flow->flow;
12466 struct mlx5_flow_handle *handle = dev_flow->handle;
12467 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12468 struct mlx5_flow_rss_desc *rss_desc;
12469 uint64_t item_flags = 0;
12470 uint64_t last_item = 0;
12471 uint64_t action_flags = 0;
12472 struct mlx5_flow_dv_matcher matcher = {
12474 .size = sizeof(matcher.mask.buf),
12478 bool actions_end = false;
12480 struct mlx5_flow_dv_modify_hdr_resource res;
12481 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12482 sizeof(struct mlx5_modification_cmd) *
12483 (MLX5_MAX_MODIFY_NUM + 1)];
12485 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12486 const struct rte_flow_action_count *count = NULL;
12487 const struct rte_flow_action_age *non_shared_age = NULL;
12488 union flow_dv_attr flow_attr = { .attr = 0 };
12490 union mlx5_flow_tbl_key tbl_key;
12491 uint32_t modify_action_position = UINT32_MAX;
12492 void *match_mask = matcher.mask.buf;
12493 void *match_value = dev_flow->dv.value.buf;
12494 uint8_t next_protocol = 0xff;
12495 struct rte_vlan_hdr vlan = { 0 };
12496 struct mlx5_flow_dv_dest_array_resource mdest_res;
12497 struct mlx5_flow_dv_sample_resource sample_res;
12498 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12499 const struct rte_flow_action_sample *sample = NULL;
12500 struct mlx5_flow_sub_actions_list *sample_act;
12501 uint32_t sample_act_pos = UINT32_MAX;
12502 uint32_t age_act_pos = UINT32_MAX;
12503 uint32_t num_of_dest = 0;
12504 int tmp_actions_n = 0;
12507 const struct mlx5_flow_tunnel *tunnel = NULL;
12508 struct flow_grp_info grp_info = {
12509 .external = !!dev_flow->external,
12510 .transfer = !!attr->transfer,
12511 .fdb_def_rule = !!priv->fdb_def_rule,
12512 .skip_scale = dev_flow->skip_scale &
12513 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12514 .std_tbl_fix = true,
12516 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12519 return rte_flow_error_set(error, ENOMEM,
12520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12522 "failed to push flow workspace");
12523 rss_desc = &wks->rss_desc;
12524 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12525 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12526 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12527 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12528 /* update normal path action resource into last index of array */
12529 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12530 if (is_tunnel_offload_active(dev)) {
12531 if (dev_flow->tunnel) {
12532 RTE_VERIFY(dev_flow->tof_type ==
12533 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12534 tunnel = dev_flow->tunnel;
12536 tunnel = mlx5_get_tof(items, actions,
12537 &dev_flow->tof_type);
12538 dev_flow->tunnel = tunnel;
12540 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12541 (dev, attr, tunnel, dev_flow->tof_type);
12543 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12544 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12545 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12549 dev_flow->dv.group = table;
12550 if (attr->transfer)
12551 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12552 /* number of actions must be set to 0 in case of dirty stack. */
12553 mhdr_res->actions_num = 0;
12554 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12556 * do not add decap action if match rule drops packet
12557 * HW rejects rules with decap & drop
12559 * if tunnel match rule was inserted before matching tunnel set
12560 * rule flow table used in the match rule must be registered.
12561 * current implementation handles that in the
12562 * flow_dv_match_register() at the function end.
12564 bool add_decap = true;
12565 const struct rte_flow_action *ptr = actions;
12567 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12568 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12574 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12578 dev_flow->dv.actions[actions_n++] =
12579 dev_flow->dv.encap_decap->action;
12580 action_flags |= MLX5_FLOW_ACTION_DECAP;
12583 for (; !actions_end ; actions++) {
12584 const struct rte_flow_action_queue *queue;
12585 const struct rte_flow_action_rss *rss;
12586 const struct rte_flow_action *action = actions;
12587 const uint8_t *rss_key;
12588 struct mlx5_flow_tbl_resource *tbl;
12589 struct mlx5_aso_age_action *age_act;
12590 struct mlx5_flow_counter *cnt_act;
12591 uint32_t port_id = 0;
12592 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12593 int action_type = actions->type;
12594 const struct rte_flow_action *found_action = NULL;
12595 uint32_t jump_group = 0;
12596 uint32_t owner_idx;
12597 struct mlx5_aso_ct_action *ct;
12599 if (!mlx5_flow_os_action_supported(action_type))
12600 return rte_flow_error_set(error, ENOTSUP,
12601 RTE_FLOW_ERROR_TYPE_ACTION,
12603 "action not supported");
12604 switch (action_type) {
12605 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12606 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12608 case RTE_FLOW_ACTION_TYPE_VOID:
12610 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12611 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12612 if (flow_dv_translate_action_port_id(dev, action,
12615 port_id_resource.port_id = port_id;
12616 MLX5_ASSERT(!handle->rix_port_id_action);
12617 if (flow_dv_port_id_action_resource_register
12618 (dev, &port_id_resource, dev_flow, error))
12620 dev_flow->dv.actions[actions_n++] =
12621 dev_flow->dv.port_id_action->action;
12622 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12623 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12624 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12627 case RTE_FLOW_ACTION_TYPE_FLAG:
12628 action_flags |= MLX5_FLOW_ACTION_FLAG;
12629 dev_flow->handle->mark = 1;
12630 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12631 struct rte_flow_action_mark mark = {
12632 .id = MLX5_FLOW_MARK_DEFAULT,
12635 if (flow_dv_convert_action_mark(dev, &mark,
12639 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12642 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12644 * Only one FLAG or MARK is supported per device flow
12645 * right now. So the pointer to the tag resource must be
12646 * zero before the register process.
12648 MLX5_ASSERT(!handle->dvh.rix_tag);
12649 if (flow_dv_tag_resource_register(dev, tag_be,
12652 MLX5_ASSERT(dev_flow->dv.tag_resource);
12653 dev_flow->dv.actions[actions_n++] =
12654 dev_flow->dv.tag_resource->action;
12656 case RTE_FLOW_ACTION_TYPE_MARK:
12657 action_flags |= MLX5_FLOW_ACTION_MARK;
12658 dev_flow->handle->mark = 1;
12659 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12660 const struct rte_flow_action_mark *mark =
12661 (const struct rte_flow_action_mark *)
12664 if (flow_dv_convert_action_mark(dev, mark,
12668 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12672 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12673 /* Legacy (non-extensive) MARK action. */
12674 tag_be = mlx5_flow_mark_set
12675 (((const struct rte_flow_action_mark *)
12676 (actions->conf))->id);
12677 MLX5_ASSERT(!handle->dvh.rix_tag);
12678 if (flow_dv_tag_resource_register(dev, tag_be,
12681 MLX5_ASSERT(dev_flow->dv.tag_resource);
12682 dev_flow->dv.actions[actions_n++] =
12683 dev_flow->dv.tag_resource->action;
12685 case RTE_FLOW_ACTION_TYPE_SET_META:
12686 if (flow_dv_convert_action_set_meta
12687 (dev, mhdr_res, attr,
12688 (const struct rte_flow_action_set_meta *)
12689 actions->conf, error))
12691 action_flags |= MLX5_FLOW_ACTION_SET_META;
12693 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12694 if (flow_dv_convert_action_set_tag
12696 (const struct rte_flow_action_set_tag *)
12697 actions->conf, error))
12699 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12701 case RTE_FLOW_ACTION_TYPE_DROP:
12702 action_flags |= MLX5_FLOW_ACTION_DROP;
12703 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12705 case RTE_FLOW_ACTION_TYPE_QUEUE:
12706 queue = actions->conf;
12707 rss_desc->queue_num = 1;
12708 rss_desc->queue[0] = queue->index;
12709 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12710 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12711 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12714 case RTE_FLOW_ACTION_TYPE_RSS:
12715 rss = actions->conf;
12716 memcpy(rss_desc->queue, rss->queue,
12717 rss->queue_num * sizeof(uint16_t));
12718 rss_desc->queue_num = rss->queue_num;
12719 /* NULL RSS key indicates default RSS key. */
12720 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12721 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12723 * rss->level and rss.types should be set in advance
12724 * when expanding items for RSS.
12726 action_flags |= MLX5_FLOW_ACTION_RSS;
12727 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12728 MLX5_FLOW_FATE_SHARED_RSS :
12729 MLX5_FLOW_FATE_QUEUE;
12731 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12732 owner_idx = (uint32_t)(uintptr_t)action->conf;
12733 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12734 if (flow->age == 0) {
12735 flow->age = owner_idx;
12736 __atomic_fetch_add(&age_act->refcnt, 1,
12739 age_act_pos = actions_n++;
12740 action_flags |= MLX5_FLOW_ACTION_AGE;
12742 case RTE_FLOW_ACTION_TYPE_AGE:
12743 non_shared_age = action->conf;
12744 age_act_pos = actions_n++;
12745 action_flags |= MLX5_FLOW_ACTION_AGE;
12747 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12748 owner_idx = (uint32_t)(uintptr_t)action->conf;
12749 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12751 MLX5_ASSERT(cnt_act != NULL);
12753 * When creating meter drop flow in drop table, the
12754 * counter should not overwrite the rte flow counter.
12756 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12757 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12758 dev_flow->dv.actions[actions_n++] =
12761 if (flow->counter == 0) {
12762 flow->counter = owner_idx;
12764 (&cnt_act->shared_info.refcnt,
12765 1, __ATOMIC_RELAXED);
12767 /* Save information first, will apply later. */
12768 action_flags |= MLX5_FLOW_ACTION_COUNT;
12771 case RTE_FLOW_ACTION_TYPE_COUNT:
12772 if (!priv->sh->devx) {
12773 return rte_flow_error_set
12775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12777 "count action not supported");
12779 /* Save information first, will apply later. */
12780 count = action->conf;
12781 action_flags |= MLX5_FLOW_ACTION_COUNT;
12783 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12784 dev_flow->dv.actions[actions_n++] =
12785 priv->sh->pop_vlan_action;
12786 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12788 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12789 if (!(action_flags &
12790 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12791 flow_dev_get_vlan_info_from_items(items, &vlan);
12792 vlan.eth_proto = rte_be_to_cpu_16
12793 ((((const struct rte_flow_action_of_push_vlan *)
12794 actions->conf)->ethertype));
12795 found_action = mlx5_flow_find_action
12797 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12799 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12800 found_action = mlx5_flow_find_action
12802 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12804 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12805 if (flow_dv_create_action_push_vlan
12806 (dev, attr, &vlan, dev_flow, error))
12808 dev_flow->dv.actions[actions_n++] =
12809 dev_flow->dv.push_vlan_res->action;
12810 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12812 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12813 /* of_vlan_push action handled this action */
12814 MLX5_ASSERT(action_flags &
12815 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
12817 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
12818 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
12820 flow_dev_get_vlan_info_from_items(items, &vlan);
12821 mlx5_update_vlan_vid_pcp(actions, &vlan);
12822 /* If no VLAN push - this is a modify header action */
12823 if (flow_dv_convert_action_modify_vlan_vid
12824 (mhdr_res, actions, error))
12826 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
12828 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
12829 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
12830 if (flow_dv_create_action_l2_encap(dev, actions,
12835 dev_flow->dv.actions[actions_n++] =
12836 dev_flow->dv.encap_decap->action;
12837 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12838 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12839 sample_act->action_flags |=
12840 MLX5_FLOW_ACTION_ENCAP;
12842 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
12843 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
12844 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12848 dev_flow->dv.actions[actions_n++] =
12849 dev_flow->dv.encap_decap->action;
12850 action_flags |= MLX5_FLOW_ACTION_DECAP;
12852 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
12853 /* Handle encap with preceding decap. */
12854 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
12855 if (flow_dv_create_action_raw_encap
12856 (dev, actions, dev_flow, attr, error))
12858 dev_flow->dv.actions[actions_n++] =
12859 dev_flow->dv.encap_decap->action;
12861 /* Handle encap without preceding decap. */
12862 if (flow_dv_create_action_l2_encap
12863 (dev, actions, dev_flow, attr->transfer,
12866 dev_flow->dv.actions[actions_n++] =
12867 dev_flow->dv.encap_decap->action;
12869 action_flags |= MLX5_FLOW_ACTION_ENCAP;
12870 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
12871 sample_act->action_flags |=
12872 MLX5_FLOW_ACTION_ENCAP;
12874 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
12875 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
12877 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
12878 if (flow_dv_create_action_l2_decap
12879 (dev, dev_flow, attr->transfer, error))
12881 dev_flow->dv.actions[actions_n++] =
12882 dev_flow->dv.encap_decap->action;
12884 /* If decap is followed by encap, handle it at encap. */
12885 action_flags |= MLX5_FLOW_ACTION_DECAP;
12887 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
12888 dev_flow->dv.actions[actions_n++] =
12889 (void *)(uintptr_t)action->conf;
12890 action_flags |= MLX5_FLOW_ACTION_JUMP;
12892 case RTE_FLOW_ACTION_TYPE_JUMP:
12893 jump_group = ((const struct rte_flow_action_jump *)
12894 action->conf)->group;
12895 grp_info.std_tbl_fix = 0;
12896 if (dev_flow->skip_scale &
12897 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
12898 grp_info.skip_scale = 1;
12900 grp_info.skip_scale = 0;
12901 ret = mlx5_flow_group_to_table(dev, tunnel,
12907 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
12909 !!dev_flow->external,
12910 tunnel, jump_group, 0,
12913 return rte_flow_error_set
12915 RTE_FLOW_ERROR_TYPE_ACTION,
12917 "cannot create jump action.");
12918 if (flow_dv_jump_tbl_resource_register
12919 (dev, tbl, dev_flow, error)) {
12920 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12921 return rte_flow_error_set
12923 RTE_FLOW_ERROR_TYPE_ACTION,
12925 "cannot create jump action.");
12927 dev_flow->dv.actions[actions_n++] =
12928 dev_flow->dv.jump->action;
12929 action_flags |= MLX5_FLOW_ACTION_JUMP;
12930 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
12931 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
12934 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
12935 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
12936 if (flow_dv_convert_action_modify_mac
12937 (mhdr_res, actions, error))
12939 action_flags |= actions->type ==
12940 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
12941 MLX5_FLOW_ACTION_SET_MAC_SRC :
12942 MLX5_FLOW_ACTION_SET_MAC_DST;
12944 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
12945 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
12946 if (flow_dv_convert_action_modify_ipv4
12947 (mhdr_res, actions, error))
12949 action_flags |= actions->type ==
12950 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
12951 MLX5_FLOW_ACTION_SET_IPV4_SRC :
12952 MLX5_FLOW_ACTION_SET_IPV4_DST;
12954 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
12955 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
12956 if (flow_dv_convert_action_modify_ipv6
12957 (mhdr_res, actions, error))
12959 action_flags |= actions->type ==
12960 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
12961 MLX5_FLOW_ACTION_SET_IPV6_SRC :
12962 MLX5_FLOW_ACTION_SET_IPV6_DST;
12964 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
12965 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
12966 if (flow_dv_convert_action_modify_tp
12967 (mhdr_res, actions, items,
12968 &flow_attr, dev_flow, !!(action_flags &
12969 MLX5_FLOW_ACTION_DECAP), error))
12971 action_flags |= actions->type ==
12972 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
12973 MLX5_FLOW_ACTION_SET_TP_SRC :
12974 MLX5_FLOW_ACTION_SET_TP_DST;
12976 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
12977 if (flow_dv_convert_action_modify_dec_ttl
12978 (mhdr_res, items, &flow_attr, dev_flow,
12980 MLX5_FLOW_ACTION_DECAP), error))
12982 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
12984 case RTE_FLOW_ACTION_TYPE_SET_TTL:
12985 if (flow_dv_convert_action_modify_ttl
12986 (mhdr_res, actions, items, &flow_attr,
12987 dev_flow, !!(action_flags &
12988 MLX5_FLOW_ACTION_DECAP), error))
12990 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
12992 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
12993 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
12994 if (flow_dv_convert_action_modify_tcp_seq
12995 (mhdr_res, actions, error))
12997 action_flags |= actions->type ==
12998 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
12999 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13000 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13003 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13004 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13005 if (flow_dv_convert_action_modify_tcp_ack
13006 (mhdr_res, actions, error))
13008 action_flags |= actions->type ==
13009 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13010 MLX5_FLOW_ACTION_INC_TCP_ACK :
13011 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13013 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13014 if (flow_dv_convert_action_set_reg
13015 (mhdr_res, actions, error))
13017 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13019 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13020 if (flow_dv_convert_action_copy_mreg
13021 (dev, mhdr_res, actions, error))
13023 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13025 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13026 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13027 dev_flow->handle->fate_action =
13028 MLX5_FLOW_FATE_DEFAULT_MISS;
13030 case RTE_FLOW_ACTION_TYPE_METER:
13032 return rte_flow_error_set(error, rte_errno,
13033 RTE_FLOW_ERROR_TYPE_ACTION,
13034 NULL, "Failed to get meter in flow.");
13035 /* Set the meter action. */
13036 dev_flow->dv.actions[actions_n++] =
13037 wks->fm->meter_action;
13038 action_flags |= MLX5_FLOW_ACTION_METER;
13040 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13041 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13044 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13046 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13047 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13050 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13052 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13053 sample_act_pos = actions_n;
13054 sample = (const struct rte_flow_action_sample *)
13057 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13058 /* put encap action into group if work with port id */
13059 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13060 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13061 sample_act->action_flags |=
13062 MLX5_FLOW_ACTION_ENCAP;
13064 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13065 if (flow_dv_convert_action_modify_field
13066 (dev, mhdr_res, actions, attr, error))
13068 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13070 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13071 owner_idx = (uint32_t)(uintptr_t)action->conf;
13072 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13074 return rte_flow_error_set(error, EINVAL,
13075 RTE_FLOW_ERROR_TYPE_ACTION,
13077 "Failed to get CT object.");
13078 if (mlx5_aso_ct_available(priv->sh, ct))
13079 return rte_flow_error_set(error, rte_errno,
13080 RTE_FLOW_ERROR_TYPE_ACTION,
13082 "CT is unavailable.");
13083 if (ct->is_original)
13084 dev_flow->dv.actions[actions_n] =
13085 ct->dr_action_orig;
13087 dev_flow->dv.actions[actions_n] =
13088 ct->dr_action_rply;
13089 if (flow->ct == 0) {
13090 flow->indirect_type =
13091 MLX5_INDIRECT_ACTION_TYPE_CT;
13092 flow->ct = owner_idx;
13093 __atomic_fetch_add(&ct->refcnt, 1,
13097 action_flags |= MLX5_FLOW_ACTION_CT;
13099 case RTE_FLOW_ACTION_TYPE_END:
13100 actions_end = true;
13101 if (mhdr_res->actions_num) {
13102 /* create modify action if needed. */
13103 if (flow_dv_modify_hdr_resource_register
13104 (dev, mhdr_res, dev_flow, error))
13106 dev_flow->dv.actions[modify_action_position] =
13107 handle->dvh.modify_hdr->action;
13110 * Handle AGE and COUNT action by single HW counter
13111 * when they are not shared.
13113 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13114 if ((non_shared_age && count) ||
13115 !(priv->sh->flow_hit_aso_en &&
13116 (attr->group || attr->transfer))) {
13117 /* Creates age by counters. */
13118 cnt_act = flow_dv_prepare_counter
13125 dev_flow->dv.actions[age_act_pos] =
13129 if (!flow->age && non_shared_age) {
13130 flow->age = flow_dv_aso_age_alloc
13134 flow_dv_aso_age_params_init
13136 non_shared_age->context ?
13137 non_shared_age->context :
13138 (void *)(uintptr_t)
13139 (dev_flow->flow_idx),
13140 non_shared_age->timeout);
13142 age_act = flow_aso_age_get_by_idx(dev,
13144 dev_flow->dv.actions[age_act_pos] =
13145 age_act->dr_action;
13147 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13149 * Create one count action, to be used
13150 * by all sub-flows.
13152 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13157 dev_flow->dv.actions[actions_n++] =
13163 if (mhdr_res->actions_num &&
13164 modify_action_position == UINT32_MAX)
13165 modify_action_position = actions_n++;
13167 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13168 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13169 int item_type = items->type;
13171 if (!mlx5_flow_os_item_supported(item_type))
13172 return rte_flow_error_set(error, ENOTSUP,
13173 RTE_FLOW_ERROR_TYPE_ITEM,
13174 NULL, "item not supported");
13175 switch (item_type) {
13176 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13177 flow_dv_translate_item_port_id
13178 (dev, match_mask, match_value, items, attr);
13179 last_item = MLX5_FLOW_ITEM_PORT_ID;
13181 case RTE_FLOW_ITEM_TYPE_ETH:
13182 flow_dv_translate_item_eth(match_mask, match_value,
13184 dev_flow->dv.group);
13185 matcher.priority = action_flags &
13186 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13187 !dev_flow->external ?
13188 MLX5_PRIORITY_MAP_L3 :
13189 MLX5_PRIORITY_MAP_L2;
13190 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13191 MLX5_FLOW_LAYER_OUTER_L2;
13193 case RTE_FLOW_ITEM_TYPE_VLAN:
13194 flow_dv_translate_item_vlan(dev_flow,
13195 match_mask, match_value,
13197 dev_flow->dv.group);
13198 matcher.priority = MLX5_PRIORITY_MAP_L2;
13199 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13200 MLX5_FLOW_LAYER_INNER_VLAN) :
13201 (MLX5_FLOW_LAYER_OUTER_L2 |
13202 MLX5_FLOW_LAYER_OUTER_VLAN);
13204 case RTE_FLOW_ITEM_TYPE_IPV4:
13205 mlx5_flow_tunnel_ip_check(items, next_protocol,
13206 &item_flags, &tunnel);
13207 flow_dv_translate_item_ipv4(match_mask, match_value,
13209 dev_flow->dv.group);
13210 matcher.priority = MLX5_PRIORITY_MAP_L3;
13211 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13212 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13213 if (items->mask != NULL &&
13214 ((const struct rte_flow_item_ipv4 *)
13215 items->mask)->hdr.next_proto_id) {
13217 ((const struct rte_flow_item_ipv4 *)
13218 (items->spec))->hdr.next_proto_id;
13220 ((const struct rte_flow_item_ipv4 *)
13221 (items->mask))->hdr.next_proto_id;
13223 /* Reset for inner layer. */
13224 next_protocol = 0xff;
13227 case RTE_FLOW_ITEM_TYPE_IPV6:
13228 mlx5_flow_tunnel_ip_check(items, next_protocol,
13229 &item_flags, &tunnel);
13230 flow_dv_translate_item_ipv6(match_mask, match_value,
13232 dev_flow->dv.group);
13233 matcher.priority = MLX5_PRIORITY_MAP_L3;
13234 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13235 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13236 if (items->mask != NULL &&
13237 ((const struct rte_flow_item_ipv6 *)
13238 items->mask)->hdr.proto) {
13240 ((const struct rte_flow_item_ipv6 *)
13241 items->spec)->hdr.proto;
13243 ((const struct rte_flow_item_ipv6 *)
13244 items->mask)->hdr.proto;
13246 /* Reset for inner layer. */
13247 next_protocol = 0xff;
13250 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13251 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13254 last_item = tunnel ?
13255 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13256 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13257 if (items->mask != NULL &&
13258 ((const struct rte_flow_item_ipv6_frag_ext *)
13259 items->mask)->hdr.next_header) {
13261 ((const struct rte_flow_item_ipv6_frag_ext *)
13262 items->spec)->hdr.next_header;
13264 ((const struct rte_flow_item_ipv6_frag_ext *)
13265 items->mask)->hdr.next_header;
13267 /* Reset for inner layer. */
13268 next_protocol = 0xff;
13271 case RTE_FLOW_ITEM_TYPE_TCP:
13272 flow_dv_translate_item_tcp(match_mask, match_value,
13274 matcher.priority = MLX5_PRIORITY_MAP_L4;
13275 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13276 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13278 case RTE_FLOW_ITEM_TYPE_UDP:
13279 flow_dv_translate_item_udp(match_mask, match_value,
13281 matcher.priority = MLX5_PRIORITY_MAP_L4;
13282 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13283 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13285 case RTE_FLOW_ITEM_TYPE_GRE:
13286 flow_dv_translate_item_gre(match_mask, match_value,
13288 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13289 last_item = MLX5_FLOW_LAYER_GRE;
13291 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13292 flow_dv_translate_item_gre_key(match_mask,
13293 match_value, items);
13294 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13296 case RTE_FLOW_ITEM_TYPE_NVGRE:
13297 flow_dv_translate_item_nvgre(match_mask, match_value,
13299 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13300 last_item = MLX5_FLOW_LAYER_GRE;
13302 case RTE_FLOW_ITEM_TYPE_VXLAN:
13303 flow_dv_translate_item_vxlan(dev, attr,
13304 match_mask, match_value,
13306 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13307 last_item = MLX5_FLOW_LAYER_VXLAN;
13309 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13310 flow_dv_translate_item_vxlan_gpe(match_mask,
13311 match_value, items,
13313 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13314 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13316 case RTE_FLOW_ITEM_TYPE_GENEVE:
13317 flow_dv_translate_item_geneve(match_mask, match_value,
13319 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13320 last_item = MLX5_FLOW_LAYER_GENEVE;
13322 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13323 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13327 return rte_flow_error_set(error, -ret,
13328 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13329 "cannot create GENEVE TLV option");
13330 flow->geneve_tlv_option = 1;
13331 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13333 case RTE_FLOW_ITEM_TYPE_MPLS:
13334 flow_dv_translate_item_mpls(match_mask, match_value,
13335 items, last_item, tunnel);
13336 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13337 last_item = MLX5_FLOW_LAYER_MPLS;
13339 case RTE_FLOW_ITEM_TYPE_MARK:
13340 flow_dv_translate_item_mark(dev, match_mask,
13341 match_value, items);
13342 last_item = MLX5_FLOW_ITEM_MARK;
13344 case RTE_FLOW_ITEM_TYPE_META:
13345 flow_dv_translate_item_meta(dev, match_mask,
13346 match_value, attr, items);
13347 last_item = MLX5_FLOW_ITEM_METADATA;
13349 case RTE_FLOW_ITEM_TYPE_ICMP:
13350 flow_dv_translate_item_icmp(match_mask, match_value,
13352 last_item = MLX5_FLOW_LAYER_ICMP;
13354 case RTE_FLOW_ITEM_TYPE_ICMP6:
13355 flow_dv_translate_item_icmp6(match_mask, match_value,
13357 last_item = MLX5_FLOW_LAYER_ICMP6;
13359 case RTE_FLOW_ITEM_TYPE_TAG:
13360 flow_dv_translate_item_tag(dev, match_mask,
13361 match_value, items);
13362 last_item = MLX5_FLOW_ITEM_TAG;
13364 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13365 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13366 match_value, items);
13367 last_item = MLX5_FLOW_ITEM_TAG;
13369 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13370 flow_dv_translate_item_tx_queue(dev, match_mask,
13373 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13375 case RTE_FLOW_ITEM_TYPE_GTP:
13376 flow_dv_translate_item_gtp(match_mask, match_value,
13378 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13379 last_item = MLX5_FLOW_LAYER_GTP;
13381 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13382 ret = flow_dv_translate_item_gtp_psc(match_mask,
13386 return rte_flow_error_set(error, -ret,
13387 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13388 "cannot create GTP PSC item");
13389 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13391 case RTE_FLOW_ITEM_TYPE_ECPRI:
13392 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13393 /* Create it only the first time to be used. */
13394 ret = mlx5_flex_parser_ecpri_alloc(dev);
13396 return rte_flow_error_set
13398 RTE_FLOW_ERROR_TYPE_ITEM,
13400 "cannot create eCPRI parser");
13402 flow_dv_translate_item_ecpri(dev, match_mask,
13403 match_value, items,
13405 /* No other protocol should follow eCPRI layer. */
13406 last_item = MLX5_FLOW_LAYER_ECPRI;
13408 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13409 flow_dv_translate_item_integrity(items, integrity_items,
13412 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13413 flow_dv_translate_item_aso_ct(dev, match_mask,
13414 match_value, items);
13419 item_flags |= last_item;
13422 * When E-Switch mode is enabled, we have two cases where we need to
13423 * set the source port manually.
13424 * The first one, is in case of Nic steering rule, and the second is
13425 * E-Switch rule where no port_id item was found. In both cases
13426 * the source port is set according the current port in use.
13428 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13429 (priv->representor || priv->master)) {
13430 if (flow_dv_translate_item_port_id(dev, match_mask,
13431 match_value, NULL, attr))
13434 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13435 flow_dv_translate_item_integrity_post(match_mask, match_value,
13439 #ifdef RTE_LIBRTE_MLX5_DEBUG
13440 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13441 dev_flow->dv.value.buf));
13444 * Layers may be already initialized from prefix flow if this dev_flow
13445 * is the suffix flow.
13447 handle->layers |= item_flags;
13448 if (action_flags & MLX5_FLOW_ACTION_RSS)
13449 flow_dv_hashfields_set(dev_flow, rss_desc);
13450 /* If has RSS action in the sample action, the Sample/Mirror resource
13451 * should be registered after the hash filed be update.
13453 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13454 ret = flow_dv_translate_action_sample(dev,
13463 ret = flow_dv_create_action_sample(dev,
13472 return rte_flow_error_set
13474 RTE_FLOW_ERROR_TYPE_ACTION,
13476 "cannot create sample action");
13477 if (num_of_dest > 1) {
13478 dev_flow->dv.actions[sample_act_pos] =
13479 dev_flow->dv.dest_array_res->action;
13481 dev_flow->dv.actions[sample_act_pos] =
13482 dev_flow->dv.sample_res->verbs_action;
13486 * For multiple destination (sample action with ratio=1), the encap
13487 * action and port id action will be combined into group action.
13488 * So need remove the original these actions in the flow and only
13489 * use the sample action instead of.
13491 if (num_of_dest > 1 &&
13492 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13494 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13496 for (i = 0; i < actions_n; i++) {
13497 if ((sample_act->dr_encap_action &&
13498 sample_act->dr_encap_action ==
13499 dev_flow->dv.actions[i]) ||
13500 (sample_act->dr_port_id_action &&
13501 sample_act->dr_port_id_action ==
13502 dev_flow->dv.actions[i]) ||
13503 (sample_act->dr_jump_action &&
13504 sample_act->dr_jump_action ==
13505 dev_flow->dv.actions[i]))
13507 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13509 memcpy((void *)dev_flow->dv.actions,
13510 (void *)temp_actions,
13511 tmp_actions_n * sizeof(void *));
13512 actions_n = tmp_actions_n;
13514 dev_flow->dv.actions_n = actions_n;
13515 dev_flow->act_flags = action_flags;
13516 if (wks->skip_matcher_reg)
13518 /* Register matcher. */
13519 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13520 matcher.mask.size);
13521 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13523 dev_flow->external);
13525 * When creating meter drop flow in drop table, using original
13526 * 5-tuple match, the matcher priority should be lower than
13529 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13530 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13531 matcher.priority <= MLX5_REG_BITS)
13532 matcher.priority += MLX5_REG_BITS;
13533 /* reserved field no needs to be set to 0 here. */
13534 tbl_key.is_fdb = attr->transfer;
13535 tbl_key.is_egress = attr->egress;
13536 tbl_key.level = dev_flow->dv.group;
13537 tbl_key.id = dev_flow->dv.table_id;
13538 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13539 tunnel, attr->group, error))
13545 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13548 * @param[in, out] action
13549 * Shred RSS action holding hash RX queue objects.
13550 * @param[in] hash_fields
13551 * Defines combination of packet fields to participate in RX hash.
13552 * @param[in] tunnel
13554 * @param[in] hrxq_idx
13555 * Hash RX queue index to set.
13558 * 0 on success, otherwise negative errno value.
13561 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13562 const uint64_t hash_fields,
13565 uint32_t *hrxqs = action->hrxq;
13567 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13568 case MLX5_RSS_HASH_IPV4:
13569 /* fall-through. */
13570 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13571 /* fall-through. */
13572 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13573 hrxqs[0] = hrxq_idx;
13575 case MLX5_RSS_HASH_IPV4_TCP:
13576 /* fall-through. */
13577 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13578 /* fall-through. */
13579 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13580 hrxqs[1] = hrxq_idx;
13582 case MLX5_RSS_HASH_IPV4_UDP:
13583 /* fall-through. */
13584 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13585 /* fall-through. */
13586 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13587 hrxqs[2] = hrxq_idx;
13589 case MLX5_RSS_HASH_IPV6:
13590 /* fall-through. */
13591 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13592 /* fall-through. */
13593 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13594 hrxqs[3] = hrxq_idx;
13596 case MLX5_RSS_HASH_IPV6_TCP:
13597 /* fall-through. */
13598 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13599 /* fall-through. */
13600 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13601 hrxqs[4] = hrxq_idx;
13603 case MLX5_RSS_HASH_IPV6_UDP:
13604 /* fall-through. */
13605 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13606 /* fall-through. */
13607 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13608 hrxqs[5] = hrxq_idx;
13610 case MLX5_RSS_HASH_NONE:
13611 hrxqs[6] = hrxq_idx;
13619 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13623 * Pointer to the Ethernet device structure.
13625 * Shared RSS action ID holding hash RX queue objects.
13626 * @param[in] hash_fields
13627 * Defines combination of packet fields to participate in RX hash.
13628 * @param[in] tunnel
13632 * Valid hash RX queue index, otherwise 0.
13635 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13636 const uint64_t hash_fields)
13638 struct mlx5_priv *priv = dev->data->dev_private;
13639 struct mlx5_shared_action_rss *shared_rss =
13640 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13641 const uint32_t *hrxqs = shared_rss->hrxq;
13643 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13644 case MLX5_RSS_HASH_IPV4:
13645 /* fall-through. */
13646 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13647 /* fall-through. */
13648 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13650 case MLX5_RSS_HASH_IPV4_TCP:
13651 /* fall-through. */
13652 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13653 /* fall-through. */
13654 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13656 case MLX5_RSS_HASH_IPV4_UDP:
13657 /* fall-through. */
13658 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13659 /* fall-through. */
13660 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13662 case MLX5_RSS_HASH_IPV6:
13663 /* fall-through. */
13664 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13665 /* fall-through. */
13666 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13668 case MLX5_RSS_HASH_IPV6_TCP:
13669 /* fall-through. */
13670 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13671 /* fall-through. */
13672 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13674 case MLX5_RSS_HASH_IPV6_UDP:
13675 /* fall-through. */
13676 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13677 /* fall-through. */
13678 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13680 case MLX5_RSS_HASH_NONE:
13689 * Apply the flow to the NIC, lock free,
13690 * (mutex should be acquired by caller).
13693 * Pointer to the Ethernet device structure.
13694 * @param[in, out] flow
13695 * Pointer to flow structure.
13696 * @param[out] error
13697 * Pointer to error structure.
13700 * 0 on success, a negative errno value otherwise and rte_errno is set.
13703 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13704 struct rte_flow_error *error)
13706 struct mlx5_flow_dv_workspace *dv;
13707 struct mlx5_flow_handle *dh;
13708 struct mlx5_flow_handle_dv *dv_h;
13709 struct mlx5_flow *dev_flow;
13710 struct mlx5_priv *priv = dev->data->dev_private;
13711 uint32_t handle_idx;
13715 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13716 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13720 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13721 dev_flow = &wks->flows[idx];
13722 dv = &dev_flow->dv;
13723 dh = dev_flow->handle;
13726 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13727 if (dv->transfer) {
13728 MLX5_ASSERT(priv->sh->dr_drop_action);
13729 dv->actions[n++] = priv->sh->dr_drop_action;
13731 #ifdef HAVE_MLX5DV_DR
13732 /* DR supports drop action placeholder. */
13733 MLX5_ASSERT(priv->sh->dr_drop_action);
13734 dv->actions[n++] = dv->group ?
13735 priv->sh->dr_drop_action :
13736 priv->root_drop_action;
13738 /* For DV we use the explicit drop queue. */
13739 MLX5_ASSERT(priv->drop_queue.hrxq);
13741 priv->drop_queue.hrxq->action;
13744 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13745 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13746 struct mlx5_hrxq *hrxq;
13749 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13754 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13755 "cannot get hash queue");
13758 dh->rix_hrxq = hrxq_idx;
13759 dv->actions[n++] = hrxq->action;
13760 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13761 struct mlx5_hrxq *hrxq = NULL;
13764 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13765 rss_desc->shared_rss,
13766 dev_flow->hash_fields);
13768 hrxq = mlx5_ipool_get
13769 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13774 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13775 "cannot get hash queue");
13778 dh->rix_srss = rss_desc->shared_rss;
13779 dv->actions[n++] = hrxq->action;
13780 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13781 if (!priv->sh->default_miss_action) {
13784 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13785 "default miss action not be created.");
13788 dv->actions[n++] = priv->sh->default_miss_action;
13790 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13791 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13792 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13793 (void *)&dv->value, n,
13794 dv->actions, &dh->drv_flow);
13798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13800 (!priv->config.allow_duplicate_pattern &&
13802 "duplicating pattern is not allowed" :
13803 "hardware refuses to create flow");
13806 if (priv->vmwa_context &&
13807 dh->vf_vlan.tag && !dh->vf_vlan.created) {
13809 * The rule contains the VLAN pattern.
13810 * For VF we are going to create VLAN
13811 * interface to make hypervisor set correct
13812 * e-Switch vport context.
13814 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
13819 err = rte_errno; /* Save rte_errno before cleanup. */
13820 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
13821 handle_idx, dh, next) {
13822 /* hrxq is union, don't clear it if the flag is not set. */
13823 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
13824 mlx5_hrxq_release(dev, dh->rix_hrxq);
13826 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13829 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13830 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13832 rte_errno = err; /* Restore rte_errno. */
13837 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
13838 struct mlx5_list_entry *entry)
13840 struct mlx5_flow_dv_matcher *resource = container_of(entry,
13844 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
13845 mlx5_free(resource);
13849 * Release the flow matcher.
13852 * Pointer to Ethernet device.
13854 * Index to port ID action resource.
13857 * 1 while a reference on it exists, 0 when freed.
13860 flow_dv_matcher_release(struct rte_eth_dev *dev,
13861 struct mlx5_flow_handle *handle)
13863 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
13864 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
13865 typeof(*tbl), tbl);
13868 MLX5_ASSERT(matcher->matcher_object);
13869 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
13870 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
13875 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13877 struct mlx5_dev_ctx_shared *sh = tool_ctx;
13878 struct mlx5_flow_dv_encap_decap_resource *res =
13879 container_of(entry, typeof(*res), entry);
13881 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13882 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
13886 * Release an encap/decap resource.
13889 * Pointer to Ethernet device.
13890 * @param encap_decap_idx
13891 * Index of encap decap resource.
13894 * 1 while a reference on it exists, 0 when freed.
13897 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
13898 uint32_t encap_decap_idx)
13900 struct mlx5_priv *priv = dev->data->dev_private;
13901 struct mlx5_flow_dv_encap_decap_resource *resource;
13903 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
13907 MLX5_ASSERT(resource->action);
13908 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
13912 * Release an jump to table action resource.
13915 * Pointer to Ethernet device.
13917 * Index to the jump action resource.
13920 * 1 while a reference on it exists, 0 when freed.
13923 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
13926 struct mlx5_priv *priv = dev->data->dev_private;
13927 struct mlx5_flow_tbl_data_entry *tbl_data;
13929 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
13933 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
13937 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13939 struct mlx5_flow_dv_modify_hdr_resource *res =
13940 container_of(entry, typeof(*res), entry);
13941 struct mlx5_dev_ctx_shared *sh = tool_ctx;
13943 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
13944 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
13948 * Release a modify-header resource.
13951 * Pointer to Ethernet device.
13953 * Pointer to mlx5_flow_handle.
13956 * 1 while a reference on it exists, 0 when freed.
13959 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
13960 struct mlx5_flow_handle *handle)
13962 struct mlx5_priv *priv = dev->data->dev_private;
13963 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
13965 MLX5_ASSERT(entry->action);
13966 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
13970 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
13972 struct mlx5_dev_ctx_shared *sh = tool_ctx;
13973 struct mlx5_flow_dv_port_id_action_resource *resource =
13974 container_of(entry, typeof(*resource), entry);
13976 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
13977 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
13981 * Release port ID action resource.
13984 * Pointer to Ethernet device.
13986 * Pointer to mlx5_flow_handle.
13989 * 1 while a reference on it exists, 0 when freed.
13992 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
13995 struct mlx5_priv *priv = dev->data->dev_private;
13996 struct mlx5_flow_dv_port_id_action_resource *resource;
13998 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14001 MLX5_ASSERT(resource->action);
14002 return mlx5_list_unregister(priv->sh->port_id_action_list,
14007 * Release shared RSS action resource.
14010 * Pointer to Ethernet device.
14012 * Shared RSS action index.
14015 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14017 struct mlx5_priv *priv = dev->data->dev_private;
14018 struct mlx5_shared_action_rss *shared_rss;
14020 shared_rss = mlx5_ipool_get
14021 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14022 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14026 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14028 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14029 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14030 container_of(entry, typeof(*resource), entry);
14032 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14033 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14037 * Release push vlan action resource.
14040 * Pointer to Ethernet device.
14042 * Pointer to mlx5_flow_handle.
14045 * 1 while a reference on it exists, 0 when freed.
14048 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14049 struct mlx5_flow_handle *handle)
14051 struct mlx5_priv *priv = dev->data->dev_private;
14052 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14053 uint32_t idx = handle->dvh.rix_push_vlan;
14055 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14058 MLX5_ASSERT(resource->action);
14059 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14064 * Release the fate resource.
14067 * Pointer to Ethernet device.
14069 * Pointer to mlx5_flow_handle.
14072 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14073 struct mlx5_flow_handle *handle)
14075 if (!handle->rix_fate)
14077 switch (handle->fate_action) {
14078 case MLX5_FLOW_FATE_QUEUE:
14079 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14080 mlx5_hrxq_release(dev, handle->rix_hrxq);
14082 case MLX5_FLOW_FATE_JUMP:
14083 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14085 case MLX5_FLOW_FATE_PORT_ID:
14086 flow_dv_port_id_action_resource_release(dev,
14087 handle->rix_port_id_action);
14090 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14093 handle->rix_fate = 0;
14097 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14098 struct mlx5_list_entry *entry)
14100 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14103 struct rte_eth_dev *dev = resource->dev;
14104 struct mlx5_priv *priv = dev->data->dev_private;
14106 if (resource->verbs_action)
14107 claim_zero(mlx5_flow_os_destroy_flow_action
14108 (resource->verbs_action));
14109 if (resource->normal_path_tbl)
14110 flow_dv_tbl_resource_release(MLX5_SH(dev),
14111 resource->normal_path_tbl);
14112 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14113 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14114 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14118 * Release an sample resource.
14121 * Pointer to Ethernet device.
14123 * Pointer to mlx5_flow_handle.
14126 * 1 while a reference on it exists, 0 when freed.
14129 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14130 struct mlx5_flow_handle *handle)
14132 struct mlx5_priv *priv = dev->data->dev_private;
14133 struct mlx5_flow_dv_sample_resource *resource;
14135 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14136 handle->dvh.rix_sample);
14139 MLX5_ASSERT(resource->verbs_action);
14140 return mlx5_list_unregister(priv->sh->sample_action_list,
14145 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14146 struct mlx5_list_entry *entry)
14148 struct mlx5_flow_dv_dest_array_resource *resource =
14149 container_of(entry, typeof(*resource), entry);
14150 struct rte_eth_dev *dev = resource->dev;
14151 struct mlx5_priv *priv = dev->data->dev_private;
14154 MLX5_ASSERT(resource->action);
14155 if (resource->action)
14156 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14157 for (; i < resource->num_of_dest; i++)
14158 flow_dv_sample_sub_actions_release(dev,
14159 &resource->sample_idx[i]);
14160 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14161 DRV_LOG(DEBUG, "destination array resource %p: removed",
14166 * Release an destination array resource.
14169 * Pointer to Ethernet device.
14171 * Pointer to mlx5_flow_handle.
14174 * 1 while a reference on it exists, 0 when freed.
14177 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14178 struct mlx5_flow_handle *handle)
14180 struct mlx5_priv *priv = dev->data->dev_private;
14181 struct mlx5_flow_dv_dest_array_resource *resource;
14183 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14184 handle->dvh.rix_dest_array);
14187 MLX5_ASSERT(resource->action);
14188 return mlx5_list_unregister(priv->sh->dest_array_list,
14193 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14195 struct mlx5_priv *priv = dev->data->dev_private;
14196 struct mlx5_dev_ctx_shared *sh = priv->sh;
14197 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14198 sh->geneve_tlv_option_resource;
14199 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14200 if (geneve_opt_resource) {
14201 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14202 __ATOMIC_RELAXED))) {
14203 claim_zero(mlx5_devx_cmd_destroy
14204 (geneve_opt_resource->obj));
14205 mlx5_free(sh->geneve_tlv_option_resource);
14206 sh->geneve_tlv_option_resource = NULL;
14209 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14213 * Remove the flow from the NIC but keeps it in memory.
14214 * Lock free, (mutex should be acquired by caller).
14217 * Pointer to Ethernet device.
14218 * @param[in, out] flow
14219 * Pointer to flow structure.
14222 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14224 struct mlx5_flow_handle *dh;
14225 uint32_t handle_idx;
14226 struct mlx5_priv *priv = dev->data->dev_private;
14230 handle_idx = flow->dev_handles;
14231 while (handle_idx) {
14232 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14236 if (dh->drv_flow) {
14237 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14238 dh->drv_flow = NULL;
14240 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14241 flow_dv_fate_resource_release(dev, dh);
14242 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14243 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14244 handle_idx = dh->next.next;
14249 * Remove the flow from the NIC and the memory.
14250 * Lock free, (mutex should be acquired by caller).
14253 * Pointer to the Ethernet device structure.
14254 * @param[in, out] flow
14255 * Pointer to flow structure.
14258 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14260 struct mlx5_flow_handle *dev_handle;
14261 struct mlx5_priv *priv = dev->data->dev_private;
14262 struct mlx5_flow_meter_info *fm = NULL;
14267 flow_dv_remove(dev, flow);
14268 if (flow->counter) {
14269 flow_dv_counter_free(dev, flow->counter);
14273 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14275 mlx5_flow_meter_detach(priv, fm);
14278 /* Keep the current age handling by default. */
14279 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14280 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14281 else if (flow->age)
14282 flow_dv_aso_age_release(dev, flow->age);
14283 if (flow->geneve_tlv_option) {
14284 flow_dv_geneve_tlv_option_resource_release(dev);
14285 flow->geneve_tlv_option = 0;
14287 while (flow->dev_handles) {
14288 uint32_t tmp_idx = flow->dev_handles;
14290 dev_handle = mlx5_ipool_get(priv->sh->ipool
14291 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14294 flow->dev_handles = dev_handle->next.next;
14295 if (dev_handle->dvh.matcher)
14296 flow_dv_matcher_release(dev, dev_handle);
14297 if (dev_handle->dvh.rix_sample)
14298 flow_dv_sample_resource_release(dev, dev_handle);
14299 if (dev_handle->dvh.rix_dest_array)
14300 flow_dv_dest_array_resource_release(dev, dev_handle);
14301 if (dev_handle->dvh.rix_encap_decap)
14302 flow_dv_encap_decap_resource_release(dev,
14303 dev_handle->dvh.rix_encap_decap);
14304 if (dev_handle->dvh.modify_hdr)
14305 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14306 if (dev_handle->dvh.rix_push_vlan)
14307 flow_dv_push_vlan_action_resource_release(dev,
14309 if (dev_handle->dvh.rix_tag)
14310 flow_dv_tag_release(dev,
14311 dev_handle->dvh.rix_tag);
14312 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14313 flow_dv_fate_resource_release(dev, dev_handle);
14315 srss = dev_handle->rix_srss;
14316 if (fm && dev_handle->is_meter_flow_id &&
14317 dev_handle->split_flow_id)
14318 mlx5_ipool_free(fm->flow_ipool,
14319 dev_handle->split_flow_id);
14320 else if (dev_handle->split_flow_id &&
14321 !dev_handle->is_meter_flow_id)
14322 mlx5_ipool_free(priv->sh->ipool
14323 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14324 dev_handle->split_flow_id);
14325 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14329 flow_dv_shared_rss_action_release(dev, srss);
14333 * Release array of hash RX queue objects.
14337 * Pointer to the Ethernet device structure.
14338 * @param[in, out] hrxqs
14339 * Array of hash RX queue objects.
14342 * Total number of references to hash RX queue objects in *hrxqs* array
14343 * after this operation.
14346 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14347 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14352 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14353 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14363 * Release all hash RX queue objects representing shared RSS action.
14366 * Pointer to the Ethernet device structure.
14367 * @param[in, out] action
14368 * Shared RSS action to remove hash RX queue objects from.
14371 * Total number of references to hash RX queue objects stored in *action*
14372 * after this operation.
14373 * Expected to be 0 if no external references held.
14376 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14377 struct mlx5_shared_action_rss *shared_rss)
14379 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14383 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14386 * Only one hash value is available for one L3+L4 combination:
14388 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14389 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14390 * same slot in mlx5_rss_hash_fields.
14393 * Pointer to the shared action RSS conf.
14394 * @param[in, out] hash_field
14395 * hash_field variable needed to be adjusted.
14401 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14402 uint64_t *hash_field)
14404 uint64_t rss_types = rss->origin.types;
14406 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14407 case MLX5_RSS_HASH_IPV4:
14408 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14409 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14410 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14411 *hash_field |= IBV_RX_HASH_DST_IPV4;
14412 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14413 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14415 *hash_field |= MLX5_RSS_HASH_IPV4;
14418 case MLX5_RSS_HASH_IPV6:
14419 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14420 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14421 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14422 *hash_field |= IBV_RX_HASH_DST_IPV6;
14423 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14424 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14426 *hash_field |= MLX5_RSS_HASH_IPV6;
14429 case MLX5_RSS_HASH_IPV4_UDP:
14430 /* fall-through. */
14431 case MLX5_RSS_HASH_IPV6_UDP:
14432 if (rss_types & RTE_ETH_RSS_UDP) {
14433 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14434 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14435 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14436 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14437 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14439 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14442 case MLX5_RSS_HASH_IPV4_TCP:
14443 /* fall-through. */
14444 case MLX5_RSS_HASH_IPV6_TCP:
14445 if (rss_types & RTE_ETH_RSS_TCP) {
14446 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14447 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14448 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14449 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14450 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14452 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14461 * Setup shared RSS action.
14462 * Prepare set of hash RX queue objects sufficient to handle all valid
14463 * hash_fields combinations (see enum ibv_rx_hash_fields).
14466 * Pointer to the Ethernet device structure.
14467 * @param[in] action_idx
14468 * Shared RSS action ipool index.
14469 * @param[in, out] action
14470 * Partially initialized shared RSS action.
14471 * @param[out] error
14472 * Perform verbose error reporting if not NULL. Initialized in case of
14476 * 0 on success, otherwise negative errno value.
14479 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14480 uint32_t action_idx,
14481 struct mlx5_shared_action_rss *shared_rss,
14482 struct rte_flow_error *error)
14484 struct mlx5_flow_rss_desc rss_desc = { 0 };
14488 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
14489 return rte_flow_error_set(error, rte_errno,
14490 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14491 "cannot setup indirection table");
14493 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14494 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14495 rss_desc.const_q = shared_rss->origin.queue;
14496 rss_desc.queue_num = shared_rss->origin.queue_num;
14497 /* Set non-zero value to indicate a shared RSS. */
14498 rss_desc.shared_rss = action_idx;
14499 rss_desc.ind_tbl = shared_rss->ind_tbl;
14500 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14502 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14505 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14506 if (shared_rss->origin.level > 1) {
14507 hash_fields |= IBV_RX_HASH_INNER;
14510 rss_desc.tunnel = tunnel;
14511 rss_desc.hash_fields = hash_fields;
14512 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14516 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14517 "cannot get hash queue");
14518 goto error_hrxq_new;
14520 err = __flow_dv_action_rss_hrxq_set
14521 (shared_rss, hash_fields, hrxq_idx);
14527 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14528 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14529 shared_rss->ind_tbl = NULL;
14535 * Create shared RSS action.
14538 * Pointer to the Ethernet device structure.
14540 * Shared action configuration.
14542 * RSS action specification used to create shared action.
14543 * @param[out] error
14544 * Perform verbose error reporting if not NULL. Initialized in case of
14548 * A valid shared action ID in case of success, 0 otherwise and
14549 * rte_errno is set.
14552 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14553 const struct rte_flow_indir_action_conf *conf,
14554 const struct rte_flow_action_rss *rss,
14555 struct rte_flow_error *error)
14557 struct mlx5_priv *priv = dev->data->dev_private;
14558 struct mlx5_shared_action_rss *shared_rss = NULL;
14559 void *queue = NULL;
14560 struct rte_flow_action_rss *origin;
14561 const uint8_t *rss_key;
14562 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14565 RTE_SET_USED(conf);
14566 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14568 shared_rss = mlx5_ipool_zmalloc
14569 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14570 if (!shared_rss || !queue) {
14571 rte_flow_error_set(error, ENOMEM,
14572 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14573 "cannot allocate resource memory");
14574 goto error_rss_init;
14576 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14577 rte_flow_error_set(error, E2BIG,
14578 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14579 "rss action number out of range");
14580 goto error_rss_init;
14582 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14583 sizeof(*shared_rss->ind_tbl),
14585 if (!shared_rss->ind_tbl) {
14586 rte_flow_error_set(error, ENOMEM,
14587 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14588 "cannot allocate resource memory");
14589 goto error_rss_init;
14591 memcpy(queue, rss->queue, queue_size);
14592 shared_rss->ind_tbl->queues = queue;
14593 shared_rss->ind_tbl->queues_n = rss->queue_num;
14594 origin = &shared_rss->origin;
14595 origin->func = rss->func;
14596 origin->level = rss->level;
14597 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14598 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14599 /* NULL RSS key indicates default RSS key. */
14600 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14601 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14602 origin->key = &shared_rss->key[0];
14603 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14604 origin->queue = queue;
14605 origin->queue_num = rss->queue_num;
14606 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14607 goto error_rss_init;
14608 rte_spinlock_init(&shared_rss->action_rss_sl);
14609 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14610 rte_spinlock_lock(&priv->shared_act_sl);
14611 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14612 &priv->rss_shared_actions, idx, shared_rss, next);
14613 rte_spinlock_unlock(&priv->shared_act_sl);
14617 if (shared_rss->ind_tbl)
14618 mlx5_free(shared_rss->ind_tbl);
14619 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14628 * Destroy the shared RSS action.
14629 * Release related hash RX queue objects.
14632 * Pointer to the Ethernet device structure.
14634 * The shared RSS action object ID to be removed.
14635 * @param[out] error
14636 * Perform verbose error reporting if not NULL. Initialized in case of
14640 * 0 on success, otherwise negative errno value.
14643 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14644 struct rte_flow_error *error)
14646 struct mlx5_priv *priv = dev->data->dev_private;
14647 struct mlx5_shared_action_rss *shared_rss =
14648 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14649 uint32_t old_refcnt = 1;
14651 uint16_t *queue = NULL;
14654 return rte_flow_error_set(error, EINVAL,
14655 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14656 "invalid shared action");
14657 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14658 0, 0, __ATOMIC_ACQUIRE,
14660 return rte_flow_error_set(error, EBUSY,
14661 RTE_FLOW_ERROR_TYPE_ACTION,
14663 "shared rss has references");
14664 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14666 return rte_flow_error_set(error, EBUSY,
14667 RTE_FLOW_ERROR_TYPE_ACTION,
14669 "shared rss hrxq has references");
14670 queue = shared_rss->ind_tbl->queues;
14671 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
14673 return rte_flow_error_set(error, EBUSY,
14674 RTE_FLOW_ERROR_TYPE_ACTION,
14676 "shared rss indirection table has"
14679 rte_spinlock_lock(&priv->shared_act_sl);
14680 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14681 &priv->rss_shared_actions, idx, shared_rss, next);
14682 rte_spinlock_unlock(&priv->shared_act_sl);
14683 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14689 * Create indirect action, lock free,
14690 * (mutex should be acquired by caller).
14691 * Dispatcher for action type specific call.
14694 * Pointer to the Ethernet device structure.
14696 * Shared action configuration.
14697 * @param[in] action
14698 * Action specification used to create indirect action.
14699 * @param[out] error
14700 * Perform verbose error reporting if not NULL. Initialized in case of
14704 * A valid shared action handle in case of success, NULL otherwise and
14705 * rte_errno is set.
14707 static struct rte_flow_action_handle *
14708 flow_dv_action_create(struct rte_eth_dev *dev,
14709 const struct rte_flow_indir_action_conf *conf,
14710 const struct rte_flow_action *action,
14711 struct rte_flow_error *err)
14713 struct mlx5_priv *priv = dev->data->dev_private;
14714 uint32_t age_idx = 0;
14718 switch (action->type) {
14719 case RTE_FLOW_ACTION_TYPE_RSS:
14720 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14721 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14722 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14724 case RTE_FLOW_ACTION_TYPE_AGE:
14725 age_idx = flow_dv_aso_age_alloc(dev, err);
14730 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14731 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14732 flow_dv_aso_age_params_init(dev, age_idx,
14733 ((const struct rte_flow_action_age *)
14734 action->conf)->context ?
14735 ((const struct rte_flow_action_age *)
14736 action->conf)->context :
14737 (void *)(uintptr_t)idx,
14738 ((const struct rte_flow_action_age *)
14739 action->conf)->timeout);
14742 case RTE_FLOW_ACTION_TYPE_COUNT:
14743 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14744 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14745 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14747 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14748 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14750 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14753 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14754 NULL, "action type not supported");
14757 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14761 * Destroy the indirect action.
14762 * Release action related resources on the NIC and the memory.
14763 * Lock free, (mutex should be acquired by caller).
14764 * Dispatcher for action type specific call.
14767 * Pointer to the Ethernet device structure.
14768 * @param[in] handle
14769 * The indirect action object handle to be removed.
14770 * @param[out] error
14771 * Perform verbose error reporting if not NULL. Initialized in case of
14775 * 0 on success, otherwise negative errno value.
14778 flow_dv_action_destroy(struct rte_eth_dev *dev,
14779 struct rte_flow_action_handle *handle,
14780 struct rte_flow_error *error)
14782 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14783 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14784 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14785 struct mlx5_flow_counter *cnt;
14786 uint32_t no_flow_refcnt = 1;
14790 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14791 return __flow_dv_action_rss_release(dev, idx, error);
14792 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14793 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
14794 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
14795 &no_flow_refcnt, 1, false,
14798 return rte_flow_error_set(error, EBUSY,
14799 RTE_FLOW_ERROR_TYPE_ACTION,
14801 "Indirect count action has references");
14802 flow_dv_counter_free(dev, idx);
14804 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14805 ret = flow_dv_aso_age_release(dev, idx);
14808 * In this case, the last flow has a reference will
14809 * actually release the age action.
14811 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
14812 " released with references %d.", idx, ret);
14814 case MLX5_INDIRECT_ACTION_TYPE_CT:
14815 ret = flow_dv_aso_ct_release(dev, idx, error);
14819 DRV_LOG(DEBUG, "Connection tracking object %u still "
14820 "has references %d.", idx, ret);
14823 return rte_flow_error_set(error, ENOTSUP,
14824 RTE_FLOW_ERROR_TYPE_ACTION,
14826 "action type not supported");
14831 * Updates in place shared RSS action configuration.
14834 * Pointer to the Ethernet device structure.
14836 * The shared RSS action object ID to be updated.
14837 * @param[in] action_conf
14838 * RSS action specification used to modify *shared_rss*.
14839 * @param[out] error
14840 * Perform verbose error reporting if not NULL. Initialized in case of
14844 * 0 on success, otherwise negative errno value.
14845 * @note: currently only support update of RSS queues.
14848 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
14849 const struct rte_flow_action_rss *action_conf,
14850 struct rte_flow_error *error)
14852 struct mlx5_priv *priv = dev->data->dev_private;
14853 struct mlx5_shared_action_rss *shared_rss =
14854 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14856 void *queue = NULL;
14857 uint16_t *queue_old = NULL;
14858 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
14861 return rte_flow_error_set(error, EINVAL,
14862 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14863 "invalid shared action to update");
14864 if (priv->obj_ops.ind_table_modify == NULL)
14865 return rte_flow_error_set(error, ENOTSUP,
14866 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14867 "cannot modify indirection table");
14868 queue = mlx5_malloc(MLX5_MEM_ZERO,
14869 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14872 return rte_flow_error_set(error, ENOMEM,
14873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14875 "cannot allocate resource memory");
14876 memcpy(queue, action_conf->queue, queue_size);
14877 MLX5_ASSERT(shared_rss->ind_tbl);
14878 rte_spinlock_lock(&shared_rss->action_rss_sl);
14879 queue_old = shared_rss->ind_tbl->queues;
14880 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
14881 queue, action_conf->queue_num, true);
14884 ret = rte_flow_error_set(error, rte_errno,
14885 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14886 "cannot update indirection table");
14888 mlx5_free(queue_old);
14889 shared_rss->origin.queue = queue;
14890 shared_rss->origin.queue_num = action_conf->queue_num;
14892 rte_spinlock_unlock(&shared_rss->action_rss_sl);
14897 * Updates in place conntrack context or direction.
14898 * Context update should be synchronized.
14901 * Pointer to the Ethernet device structure.
14903 * The conntrack object ID to be updated.
14904 * @param[in] update
14905 * Pointer to the structure of information to update.
14906 * @param[out] error
14907 * Perform verbose error reporting if not NULL. Initialized in case of
14911 * 0 on success, otherwise negative errno value.
14914 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
14915 const struct rte_flow_modify_conntrack *update,
14916 struct rte_flow_error *error)
14918 struct mlx5_priv *priv = dev->data->dev_private;
14919 struct mlx5_aso_ct_action *ct;
14920 const struct rte_flow_action_conntrack *new_prf;
14922 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
14925 if (PORT_ID(priv) != owner)
14926 return rte_flow_error_set(error, EACCES,
14927 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14929 "CT object owned by another port");
14930 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
14931 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
14933 return rte_flow_error_set(error, ENOMEM,
14934 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14936 "CT object is inactive");
14937 new_prf = &update->new_ct;
14938 if (update->direction)
14939 ct->is_original = !!new_prf->is_original_dir;
14940 if (update->state) {
14941 /* Only validate the profile when it needs to be updated. */
14942 ret = mlx5_validate_action_ct(dev, new_prf, error);
14945 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
14947 return rte_flow_error_set(error, EIO,
14948 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14950 "Failed to send CT context update WQE");
14951 /* Block until ready or a failure. */
14952 ret = mlx5_aso_ct_available(priv->sh, ct);
14954 rte_flow_error_set(error, rte_errno,
14955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14957 "Timeout to get the CT update");
14963 * Updates in place shared action configuration, lock free,
14964 * (mutex should be acquired by caller).
14967 * Pointer to the Ethernet device structure.
14968 * @param[in] handle
14969 * The indirect action object handle to be updated.
14970 * @param[in] update
14971 * Action specification used to modify the action pointed by *handle*.
14972 * *update* could be of same type with the action pointed by the *handle*
14973 * handle argument, or some other structures like a wrapper, depending on
14974 * the indirect action type.
14975 * @param[out] error
14976 * Perform verbose error reporting if not NULL. Initialized in case of
14980 * 0 on success, otherwise negative errno value.
14983 flow_dv_action_update(struct rte_eth_dev *dev,
14984 struct rte_flow_action_handle *handle,
14985 const void *update,
14986 struct rte_flow_error *err)
14988 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14989 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14990 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14991 const void *action_conf;
14994 case MLX5_INDIRECT_ACTION_TYPE_RSS:
14995 action_conf = ((const struct rte_flow_action *)update)->conf;
14996 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
14997 case MLX5_INDIRECT_ACTION_TYPE_CT:
14998 return __flow_dv_action_ct_update(dev, idx, update, err);
15000 return rte_flow_error_set(err, ENOTSUP,
15001 RTE_FLOW_ERROR_TYPE_ACTION,
15003 "action type update not supported");
15008 * Destroy the meter sub policy table rules.
15009 * Lock free, (mutex should be acquired by caller).
15012 * Pointer to Ethernet device.
15013 * @param[in] sub_policy
15014 * Pointer to meter sub policy table.
15017 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15018 struct mlx5_flow_meter_sub_policy *sub_policy)
15020 struct mlx5_priv *priv = dev->data->dev_private;
15021 struct mlx5_flow_tbl_data_entry *tbl;
15022 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15023 struct mlx5_flow_meter_info *next_fm;
15024 struct mlx5_sub_policy_color_rule *color_rule;
15028 for (i = 0; i < RTE_COLORS; i++) {
15030 if (i == RTE_COLOR_GREEN && policy &&
15031 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15032 next_fm = mlx5_flow_meter_find(priv,
15033 policy->act_cnt[i].next_mtr_id, NULL);
15034 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15036 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15037 tbl = container_of(color_rule->matcher->tbl,
15038 typeof(*tbl), tbl);
15039 mlx5_list_unregister(tbl->matchers,
15040 &color_rule->matcher->entry);
15041 TAILQ_REMOVE(&sub_policy->color_rules[i],
15042 color_rule, next_port);
15043 mlx5_free(color_rule);
15045 mlx5_flow_meter_detach(priv, next_fm);
15048 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15049 if (sub_policy->rix_hrxq[i]) {
15050 if (policy && !policy->is_hierarchy)
15051 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15052 sub_policy->rix_hrxq[i] = 0;
15054 if (sub_policy->jump_tbl[i]) {
15055 flow_dv_tbl_resource_release(MLX5_SH(dev),
15056 sub_policy->jump_tbl[i]);
15057 sub_policy->jump_tbl[i] = NULL;
15060 if (sub_policy->tbl_rsc) {
15061 flow_dv_tbl_resource_release(MLX5_SH(dev),
15062 sub_policy->tbl_rsc);
15063 sub_policy->tbl_rsc = NULL;
15068 * Destroy policy rules, lock free,
15069 * (mutex should be acquired by caller).
15070 * Dispatcher for action type specific call.
15073 * Pointer to the Ethernet device structure.
15074 * @param[in] mtr_policy
15075 * Meter policy struct.
15078 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15079 struct mlx5_flow_meter_policy *mtr_policy)
15082 struct mlx5_flow_meter_sub_policy *sub_policy;
15083 uint16_t sub_policy_num;
15085 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15086 sub_policy_num = (mtr_policy->sub_policy_num >>
15087 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15088 MLX5_MTR_SUB_POLICY_NUM_MASK;
15089 for (j = 0; j < sub_policy_num; j++) {
15090 sub_policy = mtr_policy->sub_policys[i][j];
15092 __flow_dv_destroy_sub_policy_rules(dev,
15099 * Destroy policy action, lock free,
15100 * (mutex should be acquired by caller).
15101 * Dispatcher for action type specific call.
15104 * Pointer to the Ethernet device structure.
15105 * @param[in] mtr_policy
15106 * Meter policy struct.
15109 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15110 struct mlx5_flow_meter_policy *mtr_policy)
15112 struct rte_flow_action *rss_action;
15113 struct mlx5_flow_handle dev_handle;
15116 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15117 if (mtr_policy->act_cnt[i].rix_mark) {
15118 flow_dv_tag_release(dev,
15119 mtr_policy->act_cnt[i].rix_mark);
15120 mtr_policy->act_cnt[i].rix_mark = 0;
15122 if (mtr_policy->act_cnt[i].modify_hdr) {
15123 dev_handle.dvh.modify_hdr =
15124 mtr_policy->act_cnt[i].modify_hdr;
15125 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15127 switch (mtr_policy->act_cnt[i].fate_action) {
15128 case MLX5_FLOW_FATE_SHARED_RSS:
15129 rss_action = mtr_policy->act_cnt[i].rss;
15130 mlx5_free(rss_action);
15132 case MLX5_FLOW_FATE_PORT_ID:
15133 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15134 flow_dv_port_id_action_resource_release(dev,
15135 mtr_policy->act_cnt[i].rix_port_id_action);
15136 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15139 case MLX5_FLOW_FATE_DROP:
15140 case MLX5_FLOW_FATE_JUMP:
15141 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15142 mtr_policy->act_cnt[i].dr_jump_action[j] =
15146 /*Queue action do nothing*/
15150 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15151 mtr_policy->dr_drop_action[j] = NULL;
15155 * Create policy action per domain, lock free,
15156 * (mutex should be acquired by caller).
15157 * Dispatcher for action type specific call.
15160 * Pointer to the Ethernet device structure.
15161 * @param[in] mtr_policy
15162 * Meter policy struct.
15163 * @param[in] action
15164 * Action specification used to create meter actions.
15165 * @param[out] error
15166 * Perform verbose error reporting if not NULL. Initialized in case of
15170 * 0 on success, otherwise negative errno value.
15173 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15174 struct mlx5_flow_meter_policy *mtr_policy,
15175 const struct rte_flow_action *actions[RTE_COLORS],
15176 enum mlx5_meter_domain domain,
15177 struct rte_mtr_error *error)
15179 struct mlx5_priv *priv = dev->data->dev_private;
15180 struct rte_flow_error flow_err;
15181 const struct rte_flow_action *act;
15182 uint64_t action_flags;
15183 struct mlx5_flow_handle dh;
15184 struct mlx5_flow dev_flow;
15185 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15187 uint8_t egress, transfer;
15188 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15190 struct mlx5_flow_dv_modify_hdr_resource res;
15191 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15192 sizeof(struct mlx5_modification_cmd) *
15193 (MLX5_MAX_MODIFY_NUM + 1)];
15195 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15197 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15198 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15199 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15200 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15201 memset(&port_id_action, 0,
15202 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15203 memset(mhdr_res, 0, sizeof(*mhdr_res));
15204 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15205 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15206 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15207 dev_flow.handle = &dh;
15208 dev_flow.dv.port_id_action = &port_id_action;
15209 dev_flow.external = true;
15210 for (i = 0; i < RTE_COLORS; i++) {
15211 if (i < MLX5_MTR_RTE_COLORS)
15212 act_cnt = &mtr_policy->act_cnt[i];
15213 /* Skip the color policy actions creation. */
15214 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15215 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15218 for (act = actions[i];
15219 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15220 switch (act->type) {
15221 case RTE_FLOW_ACTION_TYPE_MARK:
15223 uint32_t tag_be = mlx5_flow_mark_set
15224 (((const struct rte_flow_action_mark *)
15227 if (i >= MLX5_MTR_RTE_COLORS)
15228 return -rte_mtr_error_set(error,
15230 RTE_MTR_ERROR_TYPE_METER_POLICY,
15232 "cannot create policy "
15233 "mark action for this color");
15234 dev_flow.handle->mark = 1;
15235 if (flow_dv_tag_resource_register(dev, tag_be,
15236 &dev_flow, &flow_err))
15237 return -rte_mtr_error_set(error,
15239 RTE_MTR_ERROR_TYPE_METER_POLICY,
15241 "cannot setup policy mark action");
15242 MLX5_ASSERT(dev_flow.dv.tag_resource);
15243 act_cnt->rix_mark =
15244 dev_flow.handle->dvh.rix_tag;
15245 action_flags |= MLX5_FLOW_ACTION_MARK;
15248 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15249 if (i >= MLX5_MTR_RTE_COLORS)
15250 return -rte_mtr_error_set(error,
15252 RTE_MTR_ERROR_TYPE_METER_POLICY,
15254 "cannot create policy "
15255 "set tag action for this color");
15256 if (flow_dv_convert_action_set_tag
15258 (const struct rte_flow_action_set_tag *)
15259 act->conf, &flow_err))
15260 return -rte_mtr_error_set(error,
15262 RTE_MTR_ERROR_TYPE_METER_POLICY,
15263 NULL, "cannot convert policy "
15265 if (!mhdr_res->actions_num)
15266 return -rte_mtr_error_set(error,
15268 RTE_MTR_ERROR_TYPE_METER_POLICY,
15269 NULL, "cannot find policy "
15271 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15273 case RTE_FLOW_ACTION_TYPE_DROP:
15275 struct mlx5_flow_mtr_mng *mtrmng =
15277 struct mlx5_flow_tbl_data_entry *tbl_data;
15280 * Create the drop table with
15281 * METER DROP level.
15283 if (!mtrmng->drop_tbl[domain]) {
15284 mtrmng->drop_tbl[domain] =
15285 flow_dv_tbl_resource_get(dev,
15286 MLX5_FLOW_TABLE_LEVEL_METER,
15287 egress, transfer, false, NULL, 0,
15288 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15289 if (!mtrmng->drop_tbl[domain])
15290 return -rte_mtr_error_set
15292 RTE_MTR_ERROR_TYPE_METER_POLICY,
15294 "Failed to create meter drop table");
15296 tbl_data = container_of
15297 (mtrmng->drop_tbl[domain],
15298 struct mlx5_flow_tbl_data_entry, tbl);
15299 if (i < MLX5_MTR_RTE_COLORS) {
15300 act_cnt->dr_jump_action[domain] =
15301 tbl_data->jump.action;
15302 act_cnt->fate_action =
15303 MLX5_FLOW_FATE_DROP;
15305 if (i == RTE_COLOR_RED)
15306 mtr_policy->dr_drop_action[domain] =
15307 tbl_data->jump.action;
15308 action_flags |= MLX5_FLOW_ACTION_DROP;
15311 case RTE_FLOW_ACTION_TYPE_QUEUE:
15313 if (i >= MLX5_MTR_RTE_COLORS)
15314 return -rte_mtr_error_set(error,
15316 RTE_MTR_ERROR_TYPE_METER_POLICY,
15317 NULL, "cannot create policy "
15318 "fate queue for this color");
15320 ((const struct rte_flow_action_queue *)
15321 (act->conf))->index;
15322 act_cnt->fate_action =
15323 MLX5_FLOW_FATE_QUEUE;
15324 dev_flow.handle->fate_action =
15325 MLX5_FLOW_FATE_QUEUE;
15326 mtr_policy->is_queue = 1;
15327 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15330 case RTE_FLOW_ACTION_TYPE_RSS:
15334 if (i >= MLX5_MTR_RTE_COLORS)
15335 return -rte_mtr_error_set(error,
15337 RTE_MTR_ERROR_TYPE_METER_POLICY,
15339 "cannot create policy "
15340 "rss action for this color");
15342 * Save RSS conf into policy struct
15343 * for translate stage.
15345 rss_size = (int)rte_flow_conv
15346 (RTE_FLOW_CONV_OP_ACTION,
15347 NULL, 0, act, &flow_err);
15349 return -rte_mtr_error_set(error,
15351 RTE_MTR_ERROR_TYPE_METER_POLICY,
15352 NULL, "Get the wrong "
15353 "rss action struct size");
15354 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15355 rss_size, 0, SOCKET_ID_ANY);
15357 return -rte_mtr_error_set(error,
15359 RTE_MTR_ERROR_TYPE_METER_POLICY,
15361 "Fail to malloc rss action memory");
15362 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15363 act_cnt->rss, rss_size,
15366 return -rte_mtr_error_set(error,
15368 RTE_MTR_ERROR_TYPE_METER_POLICY,
15369 NULL, "Fail to save "
15370 "rss action into policy struct");
15371 act_cnt->fate_action =
15372 MLX5_FLOW_FATE_SHARED_RSS;
15373 action_flags |= MLX5_FLOW_ACTION_RSS;
15376 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15377 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15379 struct mlx5_flow_dv_port_id_action_resource
15381 uint32_t port_id = 0;
15383 if (i >= MLX5_MTR_RTE_COLORS)
15384 return -rte_mtr_error_set(error,
15386 RTE_MTR_ERROR_TYPE_METER_POLICY,
15387 NULL, "cannot create policy "
15388 "port action for this color");
15389 memset(&port_id_resource, 0,
15390 sizeof(port_id_resource));
15391 if (flow_dv_translate_action_port_id(dev, act,
15392 &port_id, &flow_err))
15393 return -rte_mtr_error_set(error,
15395 RTE_MTR_ERROR_TYPE_METER_POLICY,
15396 NULL, "cannot translate "
15397 "policy port action");
15398 port_id_resource.port_id = port_id;
15399 if (flow_dv_port_id_action_resource_register
15400 (dev, &port_id_resource,
15401 &dev_flow, &flow_err))
15402 return -rte_mtr_error_set(error,
15404 RTE_MTR_ERROR_TYPE_METER_POLICY,
15405 NULL, "cannot setup "
15406 "policy port action");
15407 act_cnt->rix_port_id_action =
15408 dev_flow.handle->rix_port_id_action;
15409 act_cnt->fate_action =
15410 MLX5_FLOW_FATE_PORT_ID;
15411 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15414 case RTE_FLOW_ACTION_TYPE_JUMP:
15416 uint32_t jump_group = 0;
15417 uint32_t table = 0;
15418 struct mlx5_flow_tbl_data_entry *tbl_data;
15419 struct flow_grp_info grp_info = {
15420 .external = !!dev_flow.external,
15421 .transfer = !!transfer,
15422 .fdb_def_rule = !!priv->fdb_def_rule,
15424 .skip_scale = dev_flow.skip_scale &
15425 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15427 struct mlx5_flow_meter_sub_policy *sub_policy =
15428 mtr_policy->sub_policys[domain][0];
15430 if (i >= MLX5_MTR_RTE_COLORS)
15431 return -rte_mtr_error_set(error,
15433 RTE_MTR_ERROR_TYPE_METER_POLICY,
15435 "cannot create policy "
15436 "jump action for this color");
15438 ((const struct rte_flow_action_jump *)
15440 if (mlx5_flow_group_to_table(dev, NULL,
15443 &grp_info, &flow_err))
15444 return -rte_mtr_error_set(error,
15446 RTE_MTR_ERROR_TYPE_METER_POLICY,
15447 NULL, "cannot setup "
15448 "policy jump action");
15449 sub_policy->jump_tbl[i] =
15450 flow_dv_tbl_resource_get(dev,
15453 !!dev_flow.external,
15454 NULL, jump_group, 0,
15457 (!sub_policy->jump_tbl[i])
15458 return -rte_mtr_error_set(error,
15460 RTE_MTR_ERROR_TYPE_METER_POLICY,
15461 NULL, "cannot create jump action.");
15462 tbl_data = container_of
15463 (sub_policy->jump_tbl[i],
15464 struct mlx5_flow_tbl_data_entry, tbl);
15465 act_cnt->dr_jump_action[domain] =
15466 tbl_data->jump.action;
15467 act_cnt->fate_action =
15468 MLX5_FLOW_FATE_JUMP;
15469 action_flags |= MLX5_FLOW_ACTION_JUMP;
15473 * No need to check meter hierarchy for Y or R colors
15474 * here since it is done in the validation stage.
15476 case RTE_FLOW_ACTION_TYPE_METER:
15478 const struct rte_flow_action_meter *mtr;
15479 struct mlx5_flow_meter_info *next_fm;
15480 struct mlx5_flow_meter_policy *next_policy;
15481 struct rte_flow_action tag_action;
15482 struct mlx5_rte_flow_action_set_tag set_tag;
15483 uint32_t next_mtr_idx = 0;
15486 next_fm = mlx5_flow_meter_find(priv,
15490 return -rte_mtr_error_set(error, EINVAL,
15491 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15492 "Fail to find next meter.");
15493 if (next_fm->def_policy)
15494 return -rte_mtr_error_set(error, EINVAL,
15495 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15496 "Hierarchy only supports termination meter.");
15497 next_policy = mlx5_flow_meter_policy_find(dev,
15498 next_fm->policy_id, NULL);
15499 MLX5_ASSERT(next_policy);
15500 if (next_fm->drop_cnt) {
15503 mlx5_flow_get_reg_id(dev,
15506 (struct rte_flow_error *)error);
15507 set_tag.offset = (priv->mtr_reg_share ?
15508 MLX5_MTR_COLOR_BITS : 0);
15509 set_tag.length = (priv->mtr_reg_share ?
15510 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15512 set_tag.data = next_mtr_idx;
15514 (enum rte_flow_action_type)
15515 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15516 tag_action.conf = &set_tag;
15517 if (flow_dv_convert_action_set_reg
15518 (mhdr_res, &tag_action,
15519 (struct rte_flow_error *)error))
15522 MLX5_FLOW_ACTION_SET_TAG;
15524 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15525 act_cnt->next_mtr_id = next_fm->meter_id;
15526 act_cnt->next_sub_policy = NULL;
15527 mtr_policy->is_hierarchy = 1;
15528 mtr_policy->dev = next_policy->dev;
15530 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15534 return -rte_mtr_error_set(error, ENOTSUP,
15535 RTE_MTR_ERROR_TYPE_METER_POLICY,
15536 NULL, "action type not supported");
15538 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15539 /* create modify action if needed. */
15540 dev_flow.dv.group = 1;
15541 if (flow_dv_modify_hdr_resource_register
15542 (dev, mhdr_res, &dev_flow, &flow_err))
15543 return -rte_mtr_error_set(error,
15545 RTE_MTR_ERROR_TYPE_METER_POLICY,
15546 NULL, "cannot register policy "
15548 act_cnt->modify_hdr =
15549 dev_flow.handle->dvh.modify_hdr;
15557 * Create policy action per domain, lock free,
15558 * (mutex should be acquired by caller).
15559 * Dispatcher for action type specific call.
15562 * Pointer to the Ethernet device structure.
15563 * @param[in] mtr_policy
15564 * Meter policy struct.
15565 * @param[in] action
15566 * Action specification used to create meter actions.
15567 * @param[out] error
15568 * Perform verbose error reporting if not NULL. Initialized in case of
15572 * 0 on success, otherwise negative errno value.
15575 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15576 struct mlx5_flow_meter_policy *mtr_policy,
15577 const struct rte_flow_action *actions[RTE_COLORS],
15578 struct rte_mtr_error *error)
15581 uint16_t sub_policy_num;
15583 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15584 sub_policy_num = (mtr_policy->sub_policy_num >>
15585 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15586 MLX5_MTR_SUB_POLICY_NUM_MASK;
15587 if (sub_policy_num) {
15588 ret = __flow_dv_create_domain_policy_acts(dev,
15589 mtr_policy, actions,
15590 (enum mlx5_meter_domain)i, error);
15591 /* Cleaning resource is done in the caller level. */
15600 * Query a DV flow rule for its statistics via DevX.
15603 * Pointer to Ethernet device.
15604 * @param[in] cnt_idx
15605 * Index to the flow counter.
15607 * Data retrieved by the query.
15608 * @param[out] error
15609 * Perform verbose error reporting if not NULL.
15612 * 0 on success, a negative errno value otherwise and rte_errno is set.
15615 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15616 struct rte_flow_error *error)
15618 struct mlx5_priv *priv = dev->data->dev_private;
15619 struct rte_flow_query_count *qc = data;
15621 if (!priv->sh->devx)
15622 return rte_flow_error_set(error, ENOTSUP,
15623 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15625 "counters are not supported");
15627 uint64_t pkts, bytes;
15628 struct mlx5_flow_counter *cnt;
15629 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15632 return rte_flow_error_set(error, -err,
15633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15634 NULL, "cannot read counters");
15635 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15638 qc->hits = pkts - cnt->hits;
15639 qc->bytes = bytes - cnt->bytes;
15642 cnt->bytes = bytes;
15646 return rte_flow_error_set(error, EINVAL,
15647 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15649 "counters are not available");
15654 * Query counter's action pointer for a DV flow rule via DevX.
15657 * Pointer to Ethernet device.
15658 * @param[in] cnt_idx
15659 * Index to the flow counter.
15660 * @param[out] action_ptr
15661 * Action pointer for counter.
15662 * @param[out] error
15663 * Perform verbose error reporting if not NULL.
15666 * 0 on success, a negative errno value otherwise and rte_errno is set.
15669 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15670 void **action_ptr, struct rte_flow_error *error)
15672 struct mlx5_priv *priv = dev->data->dev_private;
15674 if (!priv->sh->devx || !action_ptr)
15675 return rte_flow_error_set(error, ENOTSUP,
15676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15678 "counters are not supported");
15681 struct mlx5_flow_counter *cnt = NULL;
15682 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15684 *action_ptr = cnt->action;
15688 return rte_flow_error_set(error, EINVAL,
15689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15691 "counters are not available");
15695 flow_dv_action_query(struct rte_eth_dev *dev,
15696 const struct rte_flow_action_handle *handle, void *data,
15697 struct rte_flow_error *error)
15699 struct mlx5_age_param *age_param;
15700 struct rte_flow_query_age *resp;
15701 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15702 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15703 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15704 struct mlx5_priv *priv = dev->data->dev_private;
15705 struct mlx5_aso_ct_action *ct;
15710 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15711 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15713 resp->aged = __atomic_load_n(&age_param->state,
15714 __ATOMIC_RELAXED) == AGE_TMOUT ?
15716 resp->sec_since_last_hit_valid = !resp->aged;
15717 if (resp->sec_since_last_hit_valid)
15718 resp->sec_since_last_hit = __atomic_load_n
15719 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15721 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15722 return flow_dv_query_count(dev, idx, data, error);
15723 case MLX5_INDIRECT_ACTION_TYPE_CT:
15724 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15725 if (owner != PORT_ID(priv))
15726 return rte_flow_error_set(error, EACCES,
15727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15729 "CT object owned by another port");
15730 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15731 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15734 return rte_flow_error_set(error, EFAULT,
15735 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15737 "CT object is inactive");
15738 ((struct rte_flow_action_conntrack *)data)->peer_port =
15740 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15742 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15743 return rte_flow_error_set(error, EIO,
15744 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15746 "Failed to query CT context");
15749 return rte_flow_error_set(error, ENOTSUP,
15750 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15751 "action type query not supported");
15756 * Query a flow rule AGE action for aging information.
15759 * Pointer to Ethernet device.
15761 * Pointer to the sub flow.
15763 * data retrieved by the query.
15764 * @param[out] error
15765 * Perform verbose error reporting if not NULL.
15768 * 0 on success, a negative errno value otherwise and rte_errno is set.
15771 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15772 void *data, struct rte_flow_error *error)
15774 struct rte_flow_query_age *resp = data;
15775 struct mlx5_age_param *age_param;
15778 struct mlx5_aso_age_action *act =
15779 flow_aso_age_get_by_idx(dev, flow->age);
15781 age_param = &act->age_params;
15782 } else if (flow->counter) {
15783 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
15785 if (!age_param || !age_param->timeout)
15786 return rte_flow_error_set
15788 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15789 NULL, "cannot read age data");
15791 return rte_flow_error_set(error, EINVAL,
15792 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15793 NULL, "age data not available");
15795 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
15797 resp->sec_since_last_hit_valid = !resp->aged;
15798 if (resp->sec_since_last_hit_valid)
15799 resp->sec_since_last_hit = __atomic_load_n
15800 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15807 * @see rte_flow_query()
15808 * @see rte_flow_ops
15811 flow_dv_query(struct rte_eth_dev *dev,
15812 struct rte_flow *flow __rte_unused,
15813 const struct rte_flow_action *actions __rte_unused,
15814 void *data __rte_unused,
15815 struct rte_flow_error *error __rte_unused)
15819 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
15820 switch (actions->type) {
15821 case RTE_FLOW_ACTION_TYPE_VOID:
15823 case RTE_FLOW_ACTION_TYPE_COUNT:
15824 ret = flow_dv_query_count(dev, flow->counter, data,
15827 case RTE_FLOW_ACTION_TYPE_AGE:
15828 ret = flow_dv_query_age(dev, flow, data, error);
15831 return rte_flow_error_set(error, ENOTSUP,
15832 RTE_FLOW_ERROR_TYPE_ACTION,
15834 "action not supported");
15841 * Destroy the meter table set.
15842 * Lock free, (mutex should be acquired by caller).
15845 * Pointer to Ethernet device.
15847 * Meter information table.
15850 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
15851 struct mlx5_flow_meter_info *fm)
15853 struct mlx5_priv *priv = dev->data->dev_private;
15856 if (!fm || !priv->config.dv_flow_en)
15858 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15859 if (fm->drop_rule[i]) {
15860 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
15861 fm->drop_rule[i] = NULL;
15867 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
15869 struct mlx5_priv *priv = dev->data->dev_private;
15870 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15871 struct mlx5_flow_tbl_data_entry *tbl;
15874 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15875 if (mtrmng->def_rule[i]) {
15876 claim_zero(mlx5_flow_os_destroy_flow
15877 (mtrmng->def_rule[i]));
15878 mtrmng->def_rule[i] = NULL;
15880 if (mtrmng->def_matcher[i]) {
15881 tbl = container_of(mtrmng->def_matcher[i]->tbl,
15882 struct mlx5_flow_tbl_data_entry, tbl);
15883 mlx5_list_unregister(tbl->matchers,
15884 &mtrmng->def_matcher[i]->entry);
15885 mtrmng->def_matcher[i] = NULL;
15887 for (j = 0; j < MLX5_REG_BITS; j++) {
15888 if (mtrmng->drop_matcher[i][j]) {
15890 container_of(mtrmng->drop_matcher[i][j]->tbl,
15891 struct mlx5_flow_tbl_data_entry,
15893 mlx5_list_unregister(tbl->matchers,
15894 &mtrmng->drop_matcher[i][j]->entry);
15895 mtrmng->drop_matcher[i][j] = NULL;
15898 if (mtrmng->drop_tbl[i]) {
15899 flow_dv_tbl_resource_release(MLX5_SH(dev),
15900 mtrmng->drop_tbl[i]);
15901 mtrmng->drop_tbl[i] = NULL;
15906 /* Number of meter flow actions, count and jump or count and drop. */
15907 #define METER_ACTIONS 2
15910 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
15911 enum mlx5_meter_domain domain)
15913 struct mlx5_priv *priv = dev->data->dev_private;
15914 struct mlx5_flow_meter_def_policy *def_policy =
15915 priv->sh->mtrmng->def_policy[domain];
15917 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
15918 mlx5_free(def_policy);
15919 priv->sh->mtrmng->def_policy[domain] = NULL;
15923 * Destroy the default policy table set.
15926 * Pointer to Ethernet device.
15929 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
15931 struct mlx5_priv *priv = dev->data->dev_private;
15934 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
15935 if (priv->sh->mtrmng->def_policy[i])
15936 __flow_dv_destroy_domain_def_policy(dev,
15937 (enum mlx5_meter_domain)i);
15938 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
15942 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
15943 uint32_t color_reg_c_idx,
15944 enum rte_color color, void *matcher_object,
15945 int actions_n, void *actions,
15946 bool match_src_port, const struct rte_flow_item *item,
15947 void **rule, const struct rte_flow_attr *attr)
15950 struct mlx5_flow_dv_match_params value = {
15951 .size = sizeof(value.buf),
15953 struct mlx5_flow_dv_match_params matcher = {
15954 .size = sizeof(matcher.buf),
15956 struct mlx5_priv *priv = dev->data->dev_private;
15959 if (match_src_port && (priv->representor || priv->master)) {
15960 if (flow_dv_translate_item_port_id(dev, matcher.buf,
15961 value.buf, item, attr)) {
15962 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
15963 " value with port.", color);
15967 flow_dv_match_meta_reg(matcher.buf, value.buf,
15968 (enum modify_reg)color_reg_c_idx,
15969 rte_col_2_mlx5_col(color), UINT32_MAX);
15970 misc_mask = flow_dv_matcher_enable(value.buf);
15971 __flow_dv_adjust_buf_size(&value.size, misc_mask);
15972 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
15973 actions_n, actions, rule);
15975 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
15982 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
15983 uint32_t color_reg_c_idx,
15985 struct mlx5_flow_meter_sub_policy *sub_policy,
15986 const struct rte_flow_attr *attr,
15987 bool match_src_port,
15988 const struct rte_flow_item *item,
15989 struct mlx5_flow_dv_matcher **policy_matcher,
15990 struct rte_flow_error *error)
15992 struct mlx5_list_entry *entry;
15993 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
15994 struct mlx5_flow_dv_matcher matcher = {
15996 .size = sizeof(matcher.mask.buf),
16000 struct mlx5_flow_dv_match_params value = {
16001 .size = sizeof(value.buf),
16003 struct mlx5_flow_cb_ctx ctx = {
16007 struct mlx5_flow_tbl_data_entry *tbl_data;
16008 struct mlx5_priv *priv = dev->data->dev_private;
16009 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16011 if (match_src_port && (priv->representor || priv->master)) {
16012 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16013 value.buf, item, attr)) {
16014 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16015 " with port.", priority);
16019 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16020 if (priority < RTE_COLOR_RED)
16021 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16022 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16023 matcher.priority = priority;
16024 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16025 matcher.mask.size);
16026 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16028 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16032 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16037 * Create the policy rules per domain.
16040 * Pointer to Ethernet device.
16041 * @param[in] sub_policy
16042 * Pointer to sub policy table..
16043 * @param[in] egress
16044 * Direction of the table.
16045 * @param[in] transfer
16046 * E-Switch or NIC flow.
16048 * Pointer to policy action list per color.
16051 * 0 on success, -1 otherwise.
16054 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16055 struct mlx5_flow_meter_sub_policy *sub_policy,
16056 uint8_t egress, uint8_t transfer, bool match_src_port,
16057 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16059 struct mlx5_priv *priv = dev->data->dev_private;
16060 struct rte_flow_error flow_err;
16061 uint32_t color_reg_c_idx;
16062 struct rte_flow_attr attr = {
16063 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16066 .egress = !!egress,
16067 .transfer = !!transfer,
16071 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16072 struct mlx5_sub_policy_color_rule *color_rule;
16074 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16078 /* Create policy table with POLICY level. */
16079 if (!sub_policy->tbl_rsc)
16080 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16081 MLX5_FLOW_TABLE_LEVEL_POLICY,
16082 egress, transfer, false, NULL, 0, 0,
16083 sub_policy->idx, &flow_err);
16084 if (!sub_policy->tbl_rsc) {
16086 "Failed to create meter sub policy table.");
16089 /* Prepare matchers. */
16090 color_reg_c_idx = ret;
16091 for (i = 0; i < RTE_COLORS; i++) {
16092 TAILQ_INIT(&sub_policy->color_rules[i]);
16093 if (!acts[i].actions_n)
16095 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16096 sizeof(struct mlx5_sub_policy_color_rule),
16099 DRV_LOG(ERR, "No memory to create color rule.");
16102 tmp_rules[i] = color_rule;
16103 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16104 color_rule, next_port);
16105 color_rule->src_port = priv->representor_id;
16108 /* Create matchers for colors. */
16109 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16110 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16111 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16112 &attr, svport_match, NULL,
16113 &color_rule->matcher, &flow_err)) {
16114 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16117 /* Create flow, matching color. */
16118 if (__flow_dv_create_policy_flow(dev,
16119 color_reg_c_idx, (enum rte_color)i,
16120 color_rule->matcher->matcher_object,
16121 acts[i].actions_n, acts[i].dv_actions,
16122 svport_match, NULL, &color_rule->rule,
16124 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16130 /* All the policy rules will be cleared. */
16132 color_rule = tmp_rules[i];
16134 if (color_rule->rule)
16135 mlx5_flow_os_destroy_flow(color_rule->rule);
16136 if (color_rule->matcher) {
16137 struct mlx5_flow_tbl_data_entry *tbl =
16138 container_of(color_rule->matcher->tbl,
16139 typeof(*tbl), tbl);
16140 mlx5_list_unregister(tbl->matchers,
16141 &color_rule->matcher->entry);
16143 TAILQ_REMOVE(&sub_policy->color_rules[i],
16144 color_rule, next_port);
16145 mlx5_free(color_rule);
16152 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16153 struct mlx5_flow_meter_policy *mtr_policy,
16154 struct mlx5_flow_meter_sub_policy *sub_policy,
16157 struct mlx5_priv *priv = dev->data->dev_private;
16158 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16159 struct mlx5_flow_dv_tag_resource *tag;
16160 struct mlx5_flow_dv_port_id_action_resource *port_action;
16161 struct mlx5_hrxq *hrxq;
16162 struct mlx5_flow_meter_info *next_fm = NULL;
16163 struct mlx5_flow_meter_policy *next_policy;
16164 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16165 struct mlx5_flow_tbl_data_entry *tbl_data;
16166 struct rte_flow_error error;
16167 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16168 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16169 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16170 bool match_src_port = false;
16173 /* If RSS or Queue, no previous actions / rules is created. */
16174 for (i = 0; i < RTE_COLORS; i++) {
16175 acts[i].actions_n = 0;
16176 if (i == RTE_COLOR_RED) {
16177 /* Only support drop on red. */
16178 acts[i].dv_actions[0] =
16179 mtr_policy->dr_drop_action[domain];
16180 acts[i].actions_n = 1;
16183 if (i == RTE_COLOR_GREEN &&
16184 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16185 struct rte_flow_attr attr = {
16186 .transfer = transfer
16189 next_fm = mlx5_flow_meter_find(priv,
16190 mtr_policy->act_cnt[i].next_mtr_id,
16194 "Failed to get next hierarchy meter.");
16197 if (mlx5_flow_meter_attach(priv, next_fm,
16199 DRV_LOG(ERR, "%s", error.message);
16203 /* Meter action must be the first for TX. */
16205 acts[i].dv_actions[acts[i].actions_n] =
16206 next_fm->meter_action;
16207 acts[i].actions_n++;
16210 if (mtr_policy->act_cnt[i].rix_mark) {
16211 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16212 mtr_policy->act_cnt[i].rix_mark);
16214 DRV_LOG(ERR, "Failed to find "
16215 "mark action for policy.");
16218 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16219 acts[i].actions_n++;
16221 if (mtr_policy->act_cnt[i].modify_hdr) {
16222 acts[i].dv_actions[acts[i].actions_n] =
16223 mtr_policy->act_cnt[i].modify_hdr->action;
16224 acts[i].actions_n++;
16226 if (mtr_policy->act_cnt[i].fate_action) {
16227 switch (mtr_policy->act_cnt[i].fate_action) {
16228 case MLX5_FLOW_FATE_PORT_ID:
16229 port_action = mlx5_ipool_get
16230 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16231 mtr_policy->act_cnt[i].rix_port_id_action);
16232 if (!port_action) {
16233 DRV_LOG(ERR, "Failed to find "
16234 "port action for policy.");
16237 acts[i].dv_actions[acts[i].actions_n] =
16238 port_action->action;
16239 acts[i].actions_n++;
16240 mtr_policy->dev = dev;
16241 match_src_port = true;
16243 case MLX5_FLOW_FATE_DROP:
16244 case MLX5_FLOW_FATE_JUMP:
16245 acts[i].dv_actions[acts[i].actions_n] =
16246 mtr_policy->act_cnt[i].dr_jump_action[domain];
16247 acts[i].actions_n++;
16249 case MLX5_FLOW_FATE_SHARED_RSS:
16250 case MLX5_FLOW_FATE_QUEUE:
16251 hrxq = mlx5_ipool_get
16252 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16253 sub_policy->rix_hrxq[i]);
16255 DRV_LOG(ERR, "Failed to find "
16256 "queue action for policy.");
16259 acts[i].dv_actions[acts[i].actions_n] =
16261 acts[i].actions_n++;
16263 case MLX5_FLOW_FATE_MTR:
16266 "No next hierarchy meter.");
16270 acts[i].dv_actions[acts[i].actions_n] =
16271 next_fm->meter_action;
16272 acts[i].actions_n++;
16274 if (mtr_policy->act_cnt[i].next_sub_policy) {
16276 mtr_policy->act_cnt[i].next_sub_policy;
16279 mlx5_flow_meter_policy_find(dev,
16280 next_fm->policy_id, NULL);
16281 MLX5_ASSERT(next_policy);
16283 next_policy->sub_policys[domain][0];
16286 container_of(next_sub_policy->tbl_rsc,
16287 struct mlx5_flow_tbl_data_entry, tbl);
16288 acts[i].dv_actions[acts[i].actions_n++] =
16289 tbl_data->jump.action;
16290 if (mtr_policy->act_cnt[i].modify_hdr)
16291 match_src_port = !!transfer;
16294 /*Queue action do nothing*/
16299 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16300 egress, transfer, match_src_port, acts)) {
16302 "Failed to create policy rules per domain.");
16308 mlx5_flow_meter_detach(priv, next_fm);
16313 * Create the policy rules.
16316 * Pointer to Ethernet device.
16317 * @param[in,out] mtr_policy
16318 * Pointer to meter policy table.
16321 * 0 on success, -1 otherwise.
16324 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16325 struct mlx5_flow_meter_policy *mtr_policy)
16328 uint16_t sub_policy_num;
16330 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16331 sub_policy_num = (mtr_policy->sub_policy_num >>
16332 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16333 MLX5_MTR_SUB_POLICY_NUM_MASK;
16334 if (!sub_policy_num)
16336 /* Prepare actions list and create policy rules. */
16337 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16338 mtr_policy->sub_policys[i][0], i)) {
16339 DRV_LOG(ERR, "Failed to create policy action "
16340 "list per domain.");
16348 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16350 struct mlx5_priv *priv = dev->data->dev_private;
16351 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16352 struct mlx5_flow_meter_def_policy *def_policy;
16353 struct mlx5_flow_tbl_resource *jump_tbl;
16354 struct mlx5_flow_tbl_data_entry *tbl_data;
16355 uint8_t egress, transfer;
16356 struct rte_flow_error error;
16357 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16360 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16361 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16362 def_policy = mtrmng->def_policy[domain];
16364 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16365 sizeof(struct mlx5_flow_meter_def_policy),
16366 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16368 DRV_LOG(ERR, "Failed to alloc default policy table.");
16369 goto def_policy_error;
16371 mtrmng->def_policy[domain] = def_policy;
16372 /* Create the meter suffix table with SUFFIX level. */
16373 jump_tbl = flow_dv_tbl_resource_get(dev,
16374 MLX5_FLOW_TABLE_LEVEL_METER,
16375 egress, transfer, false, NULL, 0,
16376 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16379 "Failed to create meter suffix table.");
16380 goto def_policy_error;
16382 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16383 tbl_data = container_of(jump_tbl,
16384 struct mlx5_flow_tbl_data_entry, tbl);
16385 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16386 tbl_data->jump.action;
16387 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16388 acts[RTE_COLOR_GREEN].actions_n = 1;
16390 * YELLOW has the same default policy as GREEN does.
16391 * G & Y share the same table and action. The 2nd time of table
16392 * resource getting is just to update the reference count for
16393 * the releasing stage.
16395 jump_tbl = flow_dv_tbl_resource_get(dev,
16396 MLX5_FLOW_TABLE_LEVEL_METER,
16397 egress, transfer, false, NULL, 0,
16398 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16401 "Failed to get meter suffix table.");
16402 goto def_policy_error;
16404 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16405 tbl_data = container_of(jump_tbl,
16406 struct mlx5_flow_tbl_data_entry, tbl);
16407 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16408 tbl_data->jump.action;
16409 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16410 acts[RTE_COLOR_YELLOW].actions_n = 1;
16411 /* Create jump action to the drop table. */
16412 if (!mtrmng->drop_tbl[domain]) {
16413 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16414 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16415 egress, transfer, false, NULL, 0,
16416 0, MLX5_MTR_TABLE_ID_DROP, &error);
16417 if (!mtrmng->drop_tbl[domain]) {
16418 DRV_LOG(ERR, "Failed to create meter "
16419 "drop table for default policy.");
16420 goto def_policy_error;
16423 /* all RED: unique Drop table for jump action. */
16424 tbl_data = container_of(mtrmng->drop_tbl[domain],
16425 struct mlx5_flow_tbl_data_entry, tbl);
16426 def_policy->dr_jump_action[RTE_COLOR_RED] =
16427 tbl_data->jump.action;
16428 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16429 acts[RTE_COLOR_RED].actions_n = 1;
16430 /* Create default policy rules. */
16431 ret = __flow_dv_create_domain_policy_rules(dev,
16432 &def_policy->sub_policy,
16433 egress, transfer, false, acts);
16435 DRV_LOG(ERR, "Failed to create default policy rules.");
16436 goto def_policy_error;
16441 __flow_dv_destroy_domain_def_policy(dev,
16442 (enum mlx5_meter_domain)domain);
16447 * Create the default policy table set.
16450 * Pointer to Ethernet device.
16452 * 0 on success, -1 otherwise.
16455 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16457 struct mlx5_priv *priv = dev->data->dev_private;
16460 /* Non-termination policy table. */
16461 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16462 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16464 if (__flow_dv_create_domain_def_policy(dev, i)) {
16465 DRV_LOG(ERR, "Failed to create default policy");
16466 /* Rollback the created default policies for others. */
16467 flow_dv_destroy_def_policy(dev);
16475 * Create the needed meter tables.
16476 * Lock free, (mutex should be acquired by caller).
16479 * Pointer to Ethernet device.
16481 * Meter information table.
16482 * @param[in] mtr_idx
16484 * @param[in] domain_bitmap
16487 * 0 on success, -1 otherwise.
16490 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16491 struct mlx5_flow_meter_info *fm,
16493 uint8_t domain_bitmap)
16495 struct mlx5_priv *priv = dev->data->dev_private;
16496 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16497 struct rte_flow_error error;
16498 struct mlx5_flow_tbl_data_entry *tbl_data;
16499 uint8_t egress, transfer;
16500 void *actions[METER_ACTIONS];
16501 int domain, ret, i;
16502 struct mlx5_flow_counter *cnt;
16503 struct mlx5_flow_dv_match_params value = {
16504 .size = sizeof(value.buf),
16506 struct mlx5_flow_dv_match_params matcher_para = {
16507 .size = sizeof(matcher_para.buf),
16509 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16511 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16512 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16513 struct mlx5_list_entry *entry;
16514 struct mlx5_flow_dv_matcher matcher = {
16516 .size = sizeof(matcher.mask.buf),
16519 struct mlx5_flow_dv_matcher *drop_matcher;
16520 struct mlx5_flow_cb_ctx ctx = {
16526 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16527 rte_errno = ENOTSUP;
16530 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16531 if (!(domain_bitmap & (1 << domain)) ||
16532 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16534 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16535 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16536 /* Create the drop table with METER DROP level. */
16537 if (!mtrmng->drop_tbl[domain]) {
16538 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16539 MLX5_FLOW_TABLE_LEVEL_METER,
16540 egress, transfer, false, NULL, 0,
16541 0, MLX5_MTR_TABLE_ID_DROP, &error);
16542 if (!mtrmng->drop_tbl[domain]) {
16543 DRV_LOG(ERR, "Failed to create meter drop table.");
16547 /* Create default matcher in drop table. */
16548 matcher.tbl = mtrmng->drop_tbl[domain],
16549 tbl_data = container_of(mtrmng->drop_tbl[domain],
16550 struct mlx5_flow_tbl_data_entry, tbl);
16551 if (!mtrmng->def_matcher[domain]) {
16552 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16553 (enum modify_reg)mtr_id_reg_c,
16555 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16556 matcher.crc = rte_raw_cksum
16557 ((const void *)matcher.mask.buf,
16558 matcher.mask.size);
16559 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16561 DRV_LOG(ERR, "Failed to register meter "
16562 "drop default matcher.");
16565 mtrmng->def_matcher[domain] = container_of(entry,
16566 struct mlx5_flow_dv_matcher, entry);
16568 /* Create default rule in drop table. */
16569 if (!mtrmng->def_rule[domain]) {
16571 actions[i++] = priv->sh->dr_drop_action;
16572 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16573 (enum modify_reg)mtr_id_reg_c, 0, 0);
16574 misc_mask = flow_dv_matcher_enable(value.buf);
16575 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16576 ret = mlx5_flow_os_create_flow
16577 (mtrmng->def_matcher[domain]->matcher_object,
16578 (void *)&value, i, actions,
16579 &mtrmng->def_rule[domain]);
16581 DRV_LOG(ERR, "Failed to create meter "
16582 "default drop rule for drop table.");
16588 MLX5_ASSERT(mtrmng->max_mtr_bits);
16589 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16590 /* Create matchers for Drop. */
16591 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16592 (enum modify_reg)mtr_id_reg_c, 0,
16593 (mtr_id_mask << mtr_id_offset));
16594 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16595 matcher.crc = rte_raw_cksum
16596 ((const void *)matcher.mask.buf,
16597 matcher.mask.size);
16598 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16601 "Failed to register meter drop matcher.");
16604 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16605 container_of(entry, struct mlx5_flow_dv_matcher,
16609 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16610 /* Create drop rule, matching meter_id only. */
16611 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16612 (enum modify_reg)mtr_id_reg_c,
16613 (mtr_idx << mtr_id_offset), UINT32_MAX);
16615 cnt = flow_dv_counter_get_by_idx(dev,
16616 fm->drop_cnt, NULL);
16617 actions[i++] = cnt->action;
16618 actions[i++] = priv->sh->dr_drop_action;
16619 misc_mask = flow_dv_matcher_enable(value.buf);
16620 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16621 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16622 (void *)&value, i, actions,
16623 &fm->drop_rule[domain]);
16625 DRV_LOG(ERR, "Failed to create meter "
16626 "drop rule for drop table.");
16632 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16633 if (fm->drop_rule[i]) {
16634 claim_zero(mlx5_flow_os_destroy_flow
16635 (fm->drop_rule[i]));
16636 fm->drop_rule[i] = NULL;
16642 static struct mlx5_flow_meter_sub_policy *
16643 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16644 struct mlx5_flow_meter_policy *mtr_policy,
16645 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16646 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16649 struct mlx5_priv *priv = dev->data->dev_private;
16650 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16651 uint32_t sub_policy_idx = 0;
16652 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16654 struct mlx5_hrxq *hrxq;
16655 struct mlx5_flow_handle dh;
16656 struct mlx5_meter_policy_action_container *act_cnt;
16657 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16658 uint16_t sub_policy_num;
16660 rte_spinlock_lock(&mtr_policy->sl);
16661 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16664 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16665 if (!hrxq_idx[i]) {
16666 rte_spinlock_unlock(&mtr_policy->sl);
16670 sub_policy_num = (mtr_policy->sub_policy_num >>
16671 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16672 MLX5_MTR_SUB_POLICY_NUM_MASK;
16673 for (j = 0; j < sub_policy_num; j++) {
16674 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16677 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16680 if (i >= MLX5_MTR_RTE_COLORS) {
16682 * Found the sub policy table with
16683 * the same queue per color.
16685 rte_spinlock_unlock(&mtr_policy->sl);
16686 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16687 mlx5_hrxq_release(dev, hrxq_idx[i]);
16689 return mtr_policy->sub_policys[domain][j];
16692 /* Create sub policy. */
16693 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16694 /* Reuse the first pre-allocated sub_policy. */
16695 sub_policy = mtr_policy->sub_policys[domain][0];
16696 sub_policy_idx = sub_policy->idx;
16698 sub_policy = mlx5_ipool_zmalloc
16699 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16702 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16703 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16704 mlx5_hrxq_release(dev, hrxq_idx[i]);
16705 goto rss_sub_policy_error;
16707 sub_policy->idx = sub_policy_idx;
16708 sub_policy->main_policy = mtr_policy;
16710 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16713 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16714 if (mtr_policy->is_hierarchy) {
16715 act_cnt = &mtr_policy->act_cnt[i];
16716 act_cnt->next_sub_policy = next_sub_policy;
16717 mlx5_hrxq_release(dev, hrxq_idx[i]);
16720 * Overwrite the last action from
16721 * RSS action to Queue action.
16723 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16726 DRV_LOG(ERR, "Failed to get policy hrxq");
16727 goto rss_sub_policy_error;
16729 act_cnt = &mtr_policy->act_cnt[i];
16730 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16731 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16732 if (act_cnt->rix_mark)
16734 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16735 dh.rix_hrxq = hrxq_idx[i];
16736 flow_drv_rxq_flags_set(dev, &dh);
16740 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16741 sub_policy, domain)) {
16742 DRV_LOG(ERR, "Failed to create policy "
16743 "rules for ingress domain.");
16744 goto rss_sub_policy_error;
16746 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16747 i = (mtr_policy->sub_policy_num >>
16748 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16749 MLX5_MTR_SUB_POLICY_NUM_MASK;
16750 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16751 DRV_LOG(ERR, "No free sub-policy slot.");
16752 goto rss_sub_policy_error;
16754 mtr_policy->sub_policys[domain][i] = sub_policy;
16756 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16757 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16758 mtr_policy->sub_policy_num |=
16759 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16760 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16762 rte_spinlock_unlock(&mtr_policy->sl);
16765 rss_sub_policy_error:
16767 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16768 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16769 i = (mtr_policy->sub_policy_num >>
16770 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16771 MLX5_MTR_SUB_POLICY_NUM_MASK;
16772 mtr_policy->sub_policys[domain][i] = NULL;
16773 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16777 rte_spinlock_unlock(&mtr_policy->sl);
16782 * Find the policy table for prefix table with RSS.
16785 * Pointer to Ethernet device.
16786 * @param[in] mtr_policy
16787 * Pointer to meter policy table.
16788 * @param[in] rss_desc
16789 * Pointer to rss_desc
16791 * Pointer to table set on success, NULL otherwise and rte_errno is set.
16793 static struct mlx5_flow_meter_sub_policy *
16794 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
16795 struct mlx5_flow_meter_policy *mtr_policy,
16796 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
16798 struct mlx5_priv *priv = dev->data->dev_private;
16799 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16800 struct mlx5_flow_meter_info *next_fm;
16801 struct mlx5_flow_meter_policy *next_policy;
16802 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
16803 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
16804 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
16805 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16806 bool reuse_sub_policy;
16811 /* Iterate hierarchy to get all policies in this hierarchy. */
16812 policies[i++] = mtr_policy;
16813 if (!mtr_policy->is_hierarchy)
16815 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
16816 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
16819 next_fm = mlx5_flow_meter_find(priv,
16820 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16822 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
16826 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
16828 MLX5_ASSERT(next_policy);
16829 mtr_policy = next_policy;
16833 * From last policy to the first one in hierarchy,
16834 * create / get the sub policy for each of them.
16836 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
16840 &reuse_sub_policy);
16842 DRV_LOG(ERR, "Failed to get the sub policy.");
16845 if (!reuse_sub_policy)
16846 sub_policies[j++] = sub_policy;
16847 next_sub_policy = sub_policy;
16852 uint16_t sub_policy_num;
16854 sub_policy = sub_policies[--j];
16855 mtr_policy = sub_policy->main_policy;
16856 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16857 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16858 sub_policy_num = (mtr_policy->sub_policy_num >>
16859 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16860 MLX5_MTR_SUB_POLICY_NUM_MASK;
16861 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
16864 mtr_policy->sub_policy_num &=
16865 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16866 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
16867 mtr_policy->sub_policy_num |=
16868 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16869 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
16870 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16878 * Create the sub policy tag rule for all meters in hierarchy.
16881 * Pointer to Ethernet device.
16883 * Meter information table.
16884 * @param[in] src_port
16885 * The src port this extra rule should use.
16887 * The src port match item.
16888 * @param[out] error
16889 * Perform verbose error reporting if not NULL.
16891 * 0 on success, a negative errno value otherwise and rte_errno is set.
16894 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
16895 struct mlx5_flow_meter_info *fm,
16897 const struct rte_flow_item *item,
16898 struct rte_flow_error *error)
16900 struct mlx5_priv *priv = dev->data->dev_private;
16901 struct mlx5_flow_meter_policy *mtr_policy;
16902 struct mlx5_flow_meter_sub_policy *sub_policy;
16903 struct mlx5_flow_meter_info *next_fm = NULL;
16904 struct mlx5_flow_meter_policy *next_policy;
16905 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16906 struct mlx5_flow_tbl_data_entry *tbl_data;
16907 struct mlx5_sub_policy_color_rule *color_rule;
16908 struct mlx5_meter_policy_acts acts;
16909 uint32_t color_reg_c_idx;
16910 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
16911 struct rte_flow_attr attr = {
16912 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16919 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
16922 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
16923 MLX5_ASSERT(mtr_policy);
16924 if (!mtr_policy->is_hierarchy)
16926 next_fm = mlx5_flow_meter_find(priv,
16927 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
16929 return rte_flow_error_set(error, EINVAL,
16930 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16931 "Failed to find next meter in hierarchy.");
16933 if (!next_fm->drop_cnt)
16935 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
16936 sub_policy = mtr_policy->sub_policys[domain][0];
16937 for (i = 0; i < RTE_COLORS; i++) {
16938 bool rule_exist = false;
16939 struct mlx5_meter_policy_action_container *act_cnt;
16941 if (i >= RTE_COLOR_YELLOW)
16943 TAILQ_FOREACH(color_rule,
16944 &sub_policy->color_rules[i], next_port)
16945 if (color_rule->src_port == src_port) {
16951 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16952 sizeof(struct mlx5_sub_policy_color_rule),
16955 return rte_flow_error_set(error, ENOMEM,
16956 RTE_FLOW_ERROR_TYPE_ACTION,
16957 NULL, "No memory to create tag color rule.");
16958 color_rule->src_port = src_port;
16960 next_policy = mlx5_flow_meter_policy_find(dev,
16961 next_fm->policy_id, NULL);
16962 MLX5_ASSERT(next_policy);
16963 next_sub_policy = next_policy->sub_policys[domain][0];
16964 tbl_data = container_of(next_sub_policy->tbl_rsc,
16965 struct mlx5_flow_tbl_data_entry, tbl);
16966 act_cnt = &mtr_policy->act_cnt[i];
16968 acts.dv_actions[0] = next_fm->meter_action;
16969 acts.dv_actions[1] = act_cnt->modify_hdr->action;
16971 acts.dv_actions[0] = act_cnt->modify_hdr->action;
16972 acts.dv_actions[1] = next_fm->meter_action;
16974 acts.dv_actions[2] = tbl_data->jump.action;
16975 acts.actions_n = 3;
16976 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
16980 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16981 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16983 &color_rule->matcher, error)) {
16984 rte_flow_error_set(error, errno,
16985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16986 "Failed to create hierarchy meter matcher.");
16989 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
16991 color_rule->matcher->matcher_object,
16992 acts.actions_n, acts.dv_actions,
16994 &color_rule->rule, &attr)) {
16995 rte_flow_error_set(error, errno,
16996 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
16997 "Failed to create hierarchy meter rule.");
17000 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17001 color_rule, next_port);
17005 * Recursive call to iterate all meters in hierarchy and
17006 * create needed rules.
17008 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17009 src_port, item, error);
17012 if (color_rule->rule)
17013 mlx5_flow_os_destroy_flow(color_rule->rule);
17014 if (color_rule->matcher) {
17015 struct mlx5_flow_tbl_data_entry *tbl =
17016 container_of(color_rule->matcher->tbl,
17017 typeof(*tbl), tbl);
17018 mlx5_list_unregister(tbl->matchers,
17019 &color_rule->matcher->entry);
17021 mlx5_free(color_rule);
17024 mlx5_flow_meter_detach(priv, next_fm);
17029 * Destroy the sub policy table with RX queue.
17032 * Pointer to Ethernet device.
17033 * @param[in] mtr_policy
17034 * Pointer to meter policy table.
17037 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17038 struct mlx5_flow_meter_policy *mtr_policy)
17040 struct mlx5_priv *priv = dev->data->dev_private;
17041 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17042 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17044 uint16_t sub_policy_num, new_policy_num;
17046 rte_spinlock_lock(&mtr_policy->sl);
17047 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17048 switch (mtr_policy->act_cnt[i].fate_action) {
17049 case MLX5_FLOW_FATE_SHARED_RSS:
17050 sub_policy_num = (mtr_policy->sub_policy_num >>
17051 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17052 MLX5_MTR_SUB_POLICY_NUM_MASK;
17053 new_policy_num = sub_policy_num;
17054 for (j = 0; j < sub_policy_num; j++) {
17056 mtr_policy->sub_policys[domain][j];
17058 __flow_dv_destroy_sub_policy_rules(dev,
17061 mtr_policy->sub_policys[domain][0]) {
17062 mtr_policy->sub_policys[domain][j] =
17065 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17071 if (new_policy_num != sub_policy_num) {
17072 mtr_policy->sub_policy_num &=
17073 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17074 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17075 mtr_policy->sub_policy_num |=
17077 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17078 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17081 case MLX5_FLOW_FATE_QUEUE:
17082 sub_policy = mtr_policy->sub_policys[domain][0];
17083 __flow_dv_destroy_sub_policy_rules(dev,
17087 /*Other actions without queue and do nothing*/
17091 rte_spinlock_unlock(&mtr_policy->sl);
17094 * Check whether the DR drop action is supported on the root table or not.
17096 * Create a simple flow with DR drop action on root table to validate
17097 * if DR drop action on root table is supported or not.
17100 * Pointer to rte_eth_dev structure.
17103 * 0 on success, a negative errno value otherwise and rte_errno is set.
17106 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17108 struct mlx5_priv *priv = dev->data->dev_private;
17109 struct mlx5_dev_ctx_shared *sh = priv->sh;
17110 struct mlx5_flow_dv_match_params mask = {
17111 .size = sizeof(mask.buf),
17113 struct mlx5_flow_dv_match_params value = {
17114 .size = sizeof(value.buf),
17116 struct mlx5dv_flow_matcher_attr dv_attr = {
17117 .type = IBV_FLOW_ATTR_NORMAL,
17119 .match_criteria_enable = 0,
17120 .match_mask = (void *)&mask,
17122 struct mlx5_flow_tbl_resource *tbl = NULL;
17123 void *matcher = NULL;
17127 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17131 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17132 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17133 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17134 tbl->obj, &matcher);
17137 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17138 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17139 &sh->dr_drop_action, &flow);
17142 * If DR drop action is not supported on root table, flow create will
17143 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17147 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17148 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17150 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17153 claim_zero(mlx5_flow_os_destroy_flow(flow));
17156 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17158 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17163 * Validate the batch counter support in root table.
17165 * Create a simple flow with invalid counter and drop action on root table to
17166 * validate if batch counter with offset on root table is supported or not.
17169 * Pointer to rte_eth_dev structure.
17172 * 0 on success, a negative errno value otherwise and rte_errno is set.
17175 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17177 struct mlx5_priv *priv = dev->data->dev_private;
17178 struct mlx5_dev_ctx_shared *sh = priv->sh;
17179 struct mlx5_flow_dv_match_params mask = {
17180 .size = sizeof(mask.buf),
17182 struct mlx5_flow_dv_match_params value = {
17183 .size = sizeof(value.buf),
17185 struct mlx5dv_flow_matcher_attr dv_attr = {
17186 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17188 .match_criteria_enable = 0,
17189 .match_mask = (void *)&mask,
17191 void *actions[2] = { 0 };
17192 struct mlx5_flow_tbl_resource *tbl = NULL;
17193 struct mlx5_devx_obj *dcs = NULL;
17194 void *matcher = NULL;
17198 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17202 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17205 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17209 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17210 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17211 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17212 tbl->obj, &matcher);
17215 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17216 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17220 * If batch counter with offset is not supported, the driver will not
17221 * validate the invalid offset value, flow create should success.
17222 * In this case, it means batch counter is not supported in root table.
17224 * Otherwise, if flow create is failed, counter offset is supported.
17227 DRV_LOG(INFO, "Batch counter is not supported in root "
17228 "table. Switch to fallback mode.");
17229 rte_errno = ENOTSUP;
17231 claim_zero(mlx5_flow_os_destroy_flow(flow));
17233 /* Check matcher to make sure validate fail at flow create. */
17234 if (!matcher || (matcher && errno != EINVAL))
17235 DRV_LOG(ERR, "Unexpected error in counter offset "
17236 "support detection");
17240 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17242 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17244 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17246 claim_zero(mlx5_devx_cmd_destroy(dcs));
17251 * Query a devx counter.
17254 * Pointer to the Ethernet device structure.
17256 * Index to the flow counter.
17258 * Set to clear the counter statistics.
17260 * The statistics value of packets.
17261 * @param[out] bytes
17262 * The statistics value of bytes.
17265 * 0 on success, otherwise return -1.
17268 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17269 uint64_t *pkts, uint64_t *bytes)
17271 struct mlx5_priv *priv = dev->data->dev_private;
17272 struct mlx5_flow_counter *cnt;
17273 uint64_t inn_pkts, inn_bytes;
17276 if (!priv->sh->devx)
17279 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17282 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17283 *pkts = inn_pkts - cnt->hits;
17284 *bytes = inn_bytes - cnt->bytes;
17286 cnt->hits = inn_pkts;
17287 cnt->bytes = inn_bytes;
17293 * Get aged-out flows.
17296 * Pointer to the Ethernet device structure.
17297 * @param[in] context
17298 * The address of an array of pointers to the aged-out flows contexts.
17299 * @param[in] nb_contexts
17300 * The length of context array pointers.
17301 * @param[out] error
17302 * Perform verbose error reporting if not NULL. Initialized in case of
17306 * how many contexts get in success, otherwise negative errno value.
17307 * if nb_contexts is 0, return the amount of all aged contexts.
17308 * if nb_contexts is not 0 , return the amount of aged flows reported
17309 * in the context array.
17310 * @note: only stub for now
17313 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17315 uint32_t nb_contexts,
17316 struct rte_flow_error *error)
17318 struct mlx5_priv *priv = dev->data->dev_private;
17319 struct mlx5_age_info *age_info;
17320 struct mlx5_age_param *age_param;
17321 struct mlx5_flow_counter *counter;
17322 struct mlx5_aso_age_action *act;
17325 if (nb_contexts && !context)
17326 return rte_flow_error_set(error, EINVAL,
17327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17328 NULL, "empty context");
17329 age_info = GET_PORT_AGE_INFO(priv);
17330 rte_spinlock_lock(&age_info->aged_sl);
17331 LIST_FOREACH(act, &age_info->aged_aso, next) {
17334 context[nb_flows - 1] =
17335 act->age_params.context;
17336 if (!(--nb_contexts))
17340 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17343 age_param = MLX5_CNT_TO_AGE(counter);
17344 context[nb_flows - 1] = age_param->context;
17345 if (!(--nb_contexts))
17349 rte_spinlock_unlock(&age_info->aged_sl);
17350 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17355 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17358 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17360 return flow_dv_counter_alloc(dev, 0);
17364 * Validate indirect action.
17365 * Dispatcher for action type specific validation.
17368 * Pointer to the Ethernet device structure.
17370 * Indirect action configuration.
17371 * @param[in] action
17372 * The indirect action object to validate.
17373 * @param[out] error
17374 * Perform verbose error reporting if not NULL. Initialized in case of
17378 * 0 on success, otherwise negative errno value.
17381 flow_dv_action_validate(struct rte_eth_dev *dev,
17382 const struct rte_flow_indir_action_conf *conf,
17383 const struct rte_flow_action *action,
17384 struct rte_flow_error *err)
17386 struct mlx5_priv *priv = dev->data->dev_private;
17388 RTE_SET_USED(conf);
17389 switch (action->type) {
17390 case RTE_FLOW_ACTION_TYPE_RSS:
17392 * priv->obj_ops is set according to driver capabilities.
17393 * When DevX capabilities are
17394 * sufficient, it is set to devx_obj_ops.
17395 * Otherwise, it is set to ibv_obj_ops.
17396 * ibv_obj_ops doesn't support ind_table_modify operation.
17397 * In this case the indirect RSS action can't be used.
17399 if (priv->obj_ops.ind_table_modify == NULL)
17400 return rte_flow_error_set
17402 RTE_FLOW_ERROR_TYPE_ACTION,
17404 "Indirect RSS action not supported");
17405 return mlx5_validate_action_rss(dev, action, err);
17406 case RTE_FLOW_ACTION_TYPE_AGE:
17407 if (!priv->sh->aso_age_mng)
17408 return rte_flow_error_set(err, ENOTSUP,
17409 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17411 "Indirect age action not supported");
17412 return flow_dv_validate_action_age(0, action, dev, err);
17413 case RTE_FLOW_ACTION_TYPE_COUNT:
17414 return flow_dv_validate_action_count(dev, true, 0, err);
17415 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17416 if (!priv->sh->ct_aso_en)
17417 return rte_flow_error_set(err, ENOTSUP,
17418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17419 "ASO CT is not supported");
17420 return mlx5_validate_action_ct(dev, action->conf, err);
17422 return rte_flow_error_set(err, ENOTSUP,
17423 RTE_FLOW_ERROR_TYPE_ACTION,
17425 "action type not supported");
17430 * Check if the RSS configurations for colors of a meter policy match
17431 * each other, except the queues.
17434 * Pointer to the first RSS flow action.
17436 * Pointer to the second RSS flow action.
17439 * 0 on match, 1 on conflict.
17442 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17443 const struct rte_flow_action_rss *r2)
17447 if (r1->func != r2->func || r1->level != r2->level ||
17448 r1->types != r2->types || r1->key_len != r2->key_len ||
17449 memcmp(r1->key, r2->key, r1->key_len))
17455 * Validate the meter hierarchy chain for meter policy.
17458 * Pointer to the Ethernet device structure.
17459 * @param[in] meter_id
17461 * @param[in] action_flags
17462 * Holds the actions detected until now.
17463 * @param[out] is_rss
17465 * @param[out] hierarchy_domain
17466 * The domain bitmap for hierarchy policy.
17467 * @param[out] error
17468 * Perform verbose error reporting if not NULL. Initialized in case of
17472 * 0 on success, otherwise negative errno value with error set.
17475 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17477 uint64_t action_flags,
17479 uint8_t *hierarchy_domain,
17480 struct rte_mtr_error *error)
17482 struct mlx5_priv *priv = dev->data->dev_private;
17483 struct mlx5_flow_meter_info *fm;
17484 struct mlx5_flow_meter_policy *policy;
17487 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17488 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17489 return -rte_mtr_error_set(error, EINVAL,
17490 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17492 "Multiple fate actions not supported.");
17493 *hierarchy_domain = 0;
17495 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17497 return -rte_mtr_error_set(error, EINVAL,
17498 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17499 "Meter not found in meter hierarchy.");
17500 if (fm->def_policy)
17501 return -rte_mtr_error_set(error, EINVAL,
17502 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17503 "Non termination meter not supported in hierarchy.");
17504 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17505 MLX5_ASSERT(policy);
17507 * Only inherit the supported domains of the first meter in
17509 * One meter supports at least one domain.
17511 if (!*hierarchy_domain) {
17512 if (policy->transfer)
17513 *hierarchy_domain |=
17514 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17515 if (policy->ingress)
17516 *hierarchy_domain |=
17517 MLX5_MTR_DOMAIN_INGRESS_BIT;
17518 if (policy->egress)
17519 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17521 if (!policy->is_hierarchy) {
17522 *is_rss = policy->is_rss;
17525 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17526 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17527 return -rte_mtr_error_set(error, EINVAL,
17528 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17529 "Exceed max hierarchy meter number.");
17535 * Validate meter policy actions.
17536 * Dispatcher for action type specific validation.
17539 * Pointer to the Ethernet device structure.
17540 * @param[in] action
17541 * The meter policy action object to validate.
17543 * Attributes of flow to determine steering domain.
17544 * @param[out] error
17545 * Perform verbose error reporting if not NULL. Initialized in case of
17549 * 0 on success, otherwise negative errno value.
17552 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17553 const struct rte_flow_action *actions[RTE_COLORS],
17554 struct rte_flow_attr *attr,
17556 uint8_t *domain_bitmap,
17557 uint8_t *policy_mode,
17558 struct rte_mtr_error *error)
17560 struct mlx5_priv *priv = dev->data->dev_private;
17561 struct mlx5_dev_config *dev_conf = &priv->config;
17562 const struct rte_flow_action *act;
17563 uint64_t action_flags[RTE_COLORS] = {0};
17566 struct rte_flow_error flow_err;
17567 uint8_t domain_color[RTE_COLORS] = {0};
17568 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17569 uint8_t hierarchy_domain = 0;
17570 const struct rte_flow_action_meter *mtr;
17571 bool def_green = false;
17572 bool def_yellow = false;
17573 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17575 if (!priv->config.dv_esw_en)
17576 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17577 *domain_bitmap = def_domain;
17578 /* Red color could only support DROP action. */
17579 if (!actions[RTE_COLOR_RED] ||
17580 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17581 return -rte_mtr_error_set(error, ENOTSUP,
17582 RTE_MTR_ERROR_TYPE_METER_POLICY,
17583 NULL, "Red color only supports drop action.");
17585 * Check default policy actions:
17586 * Green / Yellow: no action, Red: drop action
17587 * Either G or Y will trigger default policy actions to be created.
17589 if (!actions[RTE_COLOR_GREEN] ||
17590 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17592 if (!actions[RTE_COLOR_YELLOW] ||
17593 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17595 if (def_green && def_yellow) {
17596 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17598 } else if (!def_green && def_yellow) {
17599 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17600 } else if (def_green && !def_yellow) {
17601 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17603 /* Set to empty string in case of NULL pointer access by user. */
17604 flow_err.message = "";
17605 for (i = 0; i < RTE_COLORS; i++) {
17607 for (action_flags[i] = 0, actions_n = 0;
17608 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17610 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17611 return -rte_mtr_error_set(error, ENOTSUP,
17612 RTE_MTR_ERROR_TYPE_METER_POLICY,
17613 NULL, "too many actions");
17614 switch (act->type) {
17615 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17616 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17617 if (!priv->config.dv_esw_en)
17618 return -rte_mtr_error_set(error,
17620 RTE_MTR_ERROR_TYPE_METER_POLICY,
17621 NULL, "PORT action validate check"
17622 " fail for ESW disable");
17623 ret = flow_dv_validate_action_port_id(dev,
17625 act, attr, &flow_err);
17627 return -rte_mtr_error_set(error,
17629 RTE_MTR_ERROR_TYPE_METER_POLICY,
17630 NULL, flow_err.message ?
17632 "PORT action validate check fail");
17634 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17636 case RTE_FLOW_ACTION_TYPE_MARK:
17637 ret = flow_dv_validate_action_mark(dev, act,
17641 return -rte_mtr_error_set(error,
17643 RTE_MTR_ERROR_TYPE_METER_POLICY,
17644 NULL, flow_err.message ?
17646 "Mark action validate check fail");
17647 if (dev_conf->dv_xmeta_en !=
17648 MLX5_XMETA_MODE_LEGACY)
17649 return -rte_mtr_error_set(error,
17651 RTE_MTR_ERROR_TYPE_METER_POLICY,
17652 NULL, "Extend MARK action is "
17653 "not supported. Please try use "
17654 "default policy for meter.");
17655 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17658 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17659 ret = flow_dv_validate_action_set_tag(dev,
17660 act, action_flags[i],
17663 return -rte_mtr_error_set(error,
17665 RTE_MTR_ERROR_TYPE_METER_POLICY,
17666 NULL, flow_err.message ?
17668 "Set tag action validate check fail");
17669 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17672 case RTE_FLOW_ACTION_TYPE_DROP:
17673 ret = mlx5_flow_validate_action_drop
17674 (action_flags[i], attr, &flow_err);
17676 return -rte_mtr_error_set(error,
17678 RTE_MTR_ERROR_TYPE_METER_POLICY,
17679 NULL, flow_err.message ?
17681 "Drop action validate check fail");
17682 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17685 case RTE_FLOW_ACTION_TYPE_QUEUE:
17687 * Check whether extensive
17688 * metadata feature is engaged.
17690 if (dev_conf->dv_flow_en &&
17691 (dev_conf->dv_xmeta_en !=
17692 MLX5_XMETA_MODE_LEGACY) &&
17693 mlx5_flow_ext_mreg_supported(dev))
17694 return -rte_mtr_error_set(error,
17696 RTE_MTR_ERROR_TYPE_METER_POLICY,
17697 NULL, "Queue action with meta "
17698 "is not supported. Please try use "
17699 "default policy for meter.");
17700 ret = mlx5_flow_validate_action_queue(act,
17701 action_flags[i], dev,
17704 return -rte_mtr_error_set(error,
17706 RTE_MTR_ERROR_TYPE_METER_POLICY,
17707 NULL, flow_err.message ?
17709 "Queue action validate check fail");
17710 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17713 case RTE_FLOW_ACTION_TYPE_RSS:
17714 if (dev_conf->dv_flow_en &&
17715 (dev_conf->dv_xmeta_en !=
17716 MLX5_XMETA_MODE_LEGACY) &&
17717 mlx5_flow_ext_mreg_supported(dev))
17718 return -rte_mtr_error_set(error,
17720 RTE_MTR_ERROR_TYPE_METER_POLICY,
17721 NULL, "RSS action with meta "
17722 "is not supported. Please try use "
17723 "default policy for meter.");
17724 ret = mlx5_validate_action_rss(dev, act,
17727 return -rte_mtr_error_set(error,
17729 RTE_MTR_ERROR_TYPE_METER_POLICY,
17730 NULL, flow_err.message ?
17732 "RSS action validate check fail");
17733 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17735 /* Either G or Y will set the RSS. */
17736 rss_color[i] = act->conf;
17738 case RTE_FLOW_ACTION_TYPE_JUMP:
17739 ret = flow_dv_validate_action_jump(dev,
17740 NULL, act, action_flags[i],
17741 attr, true, &flow_err);
17743 return -rte_mtr_error_set(error,
17745 RTE_MTR_ERROR_TYPE_METER_POLICY,
17746 NULL, flow_err.message ?
17748 "Jump action validate check fail");
17750 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17753 * Only the last meter in the hierarchy will support
17754 * the YELLOW color steering. Then in the meter policy
17755 * actions list, there should be no other meter inside.
17757 case RTE_FLOW_ACTION_TYPE_METER:
17758 if (i != RTE_COLOR_GREEN)
17759 return -rte_mtr_error_set(error,
17761 RTE_MTR_ERROR_TYPE_METER_POLICY,
17763 "Meter hierarchy only supports GREEN color.");
17764 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17765 return -rte_mtr_error_set(error,
17767 RTE_MTR_ERROR_TYPE_METER_POLICY,
17769 "No yellow policy should be provided in meter hierarchy.");
17771 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
17781 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
17784 return -rte_mtr_error_set(error, ENOTSUP,
17785 RTE_MTR_ERROR_TYPE_METER_POLICY,
17787 "Doesn't support optional action");
17790 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
17791 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
17792 } else if ((action_flags[i] &
17793 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
17794 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
17796 * Only support MLX5_XMETA_MODE_LEGACY
17797 * so MARK action is only in ingress domain.
17799 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
17801 domain_color[i] = def_domain;
17802 if (action_flags[i] &&
17803 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17805 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17807 if (action_flags[i] &
17808 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
17809 domain_color[i] &= hierarchy_domain;
17811 * Non-termination actions only support NIC Tx domain.
17812 * The adjustion should be skipped when there is no
17813 * action or only END is provided. The default domains
17814 * bit-mask is set to find the MIN intersection.
17815 * The action flags checking should also be skipped.
17817 if ((def_green && i == RTE_COLOR_GREEN) ||
17818 (def_yellow && i == RTE_COLOR_YELLOW))
17821 * Validate the drop action mutual exclusion
17822 * with other actions. Drop action is mutually-exclusive
17823 * with any other action, except for Count action.
17825 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
17826 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
17827 return -rte_mtr_error_set(error, ENOTSUP,
17828 RTE_MTR_ERROR_TYPE_METER_POLICY,
17829 NULL, "Drop action is mutually-exclusive "
17830 "with any other action");
17832 /* Eswitch has few restrictions on using items and actions */
17833 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
17834 if (!mlx5_flow_ext_mreg_supported(dev) &&
17835 action_flags[i] & MLX5_FLOW_ACTION_MARK)
17836 return -rte_mtr_error_set(error, ENOTSUP,
17837 RTE_MTR_ERROR_TYPE_METER_POLICY,
17838 NULL, "unsupported action MARK");
17839 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
17840 return -rte_mtr_error_set(error, ENOTSUP,
17841 RTE_MTR_ERROR_TYPE_METER_POLICY,
17842 NULL, "unsupported action QUEUE");
17843 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
17844 return -rte_mtr_error_set(error, ENOTSUP,
17845 RTE_MTR_ERROR_TYPE_METER_POLICY,
17846 NULL, "unsupported action RSS");
17847 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17848 return -rte_mtr_error_set(error, ENOTSUP,
17849 RTE_MTR_ERROR_TYPE_METER_POLICY,
17850 NULL, "no fate action is found");
17852 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
17853 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
17854 if ((domain_color[i] &
17855 MLX5_MTR_DOMAIN_EGRESS_BIT))
17857 MLX5_MTR_DOMAIN_EGRESS_BIT;
17859 return -rte_mtr_error_set(error,
17861 RTE_MTR_ERROR_TYPE_METER_POLICY,
17863 "no fate action is found");
17867 /* If both colors have RSS, the attributes should be the same. */
17868 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
17869 rss_color[RTE_COLOR_YELLOW]))
17870 return -rte_mtr_error_set(error, EINVAL,
17871 RTE_MTR_ERROR_TYPE_METER_POLICY,
17872 NULL, "policy RSS attr conflict");
17873 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
17875 /* "domain_color[C]" is non-zero for each color, default is ALL. */
17876 if (!def_green && !def_yellow &&
17877 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
17878 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
17879 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
17880 return -rte_mtr_error_set(error, EINVAL,
17881 RTE_MTR_ERROR_TYPE_METER_POLICY,
17882 NULL, "policy domains conflict");
17884 * At least one color policy is listed in the actions, the domains
17885 * to be supported should be the intersection.
17887 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
17888 domain_color[RTE_COLOR_YELLOW];
17893 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
17895 struct mlx5_priv *priv = dev->data->dev_private;
17898 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
17899 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
17904 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
17905 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
17909 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
17910 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
17917 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
17918 .validate = flow_dv_validate,
17919 .prepare = flow_dv_prepare,
17920 .translate = flow_dv_translate,
17921 .apply = flow_dv_apply,
17922 .remove = flow_dv_remove,
17923 .destroy = flow_dv_destroy,
17924 .query = flow_dv_query,
17925 .create_mtr_tbls = flow_dv_create_mtr_tbls,
17926 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
17927 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
17928 .create_meter = flow_dv_mtr_alloc,
17929 .free_meter = flow_dv_aso_mtr_release_to_pool,
17930 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
17931 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
17932 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
17933 .create_policy_rules = flow_dv_create_policy_rules,
17934 .destroy_policy_rules = flow_dv_destroy_policy_rules,
17935 .create_def_policy = flow_dv_create_def_policy,
17936 .destroy_def_policy = flow_dv_destroy_def_policy,
17937 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
17938 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
17939 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
17940 .counter_alloc = flow_dv_counter_allocate,
17941 .counter_free = flow_dv_counter_free,
17942 .counter_query = flow_dv_counter_query,
17943 .get_aged_flows = flow_dv_get_aged_flows,
17944 .action_validate = flow_dv_action_validate,
17945 .action_create = flow_dv_action_create,
17946 .action_destroy = flow_dv_action_destroy,
17947 .action_update = flow_dv_action_update,
17948 .action_query = flow_dv_action_query,
17949 .sync_domain = flow_dv_sync_domain,
17952 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */