1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_cycles.h>
30 #include <rte_vxlan.h>
33 #include <mlx5_glue.h>
34 #include <mlx5_devx_cmds.h>
37 #include "mlx5_defs.h"
39 #include "mlx5_common_os.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "mlx5_rxtx.h"
44 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
46 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
47 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
50 #ifndef HAVE_MLX5DV_DR_ESWITCH
51 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
52 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
56 #ifndef HAVE_MLX5DV_DR
57 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
60 /* VLAN header definitions */
61 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
62 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
63 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
64 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
65 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
80 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
81 struct mlx5_flow_tbl_resource *tbl);
84 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
87 * Initialize flow attributes structure according to flow items' types.
89 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
90 * mode. For tunnel mode, the items to be modified are the outermost ones.
93 * Pointer to item specification.
95 * Pointer to flow attributes structure.
97 * Pointer to the sub flow.
98 * @param[in] tunnel_decap
99 * Whether action is after tunnel decapsulation.
102 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
103 struct mlx5_flow *dev_flow, bool tunnel_decap)
105 uint64_t layers = dev_flow->handle->layers;
108 * If layers is already initialized, it means this dev_flow is the
109 * suffix flow, the layers flags is set by the prefix flow. Need to
110 * use the layer flags from prefix flow as the suffix flow may not
111 * have the user defined items as the flow is split.
114 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
116 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
118 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
120 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
125 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
126 uint8_t next_protocol = 0xff;
127 switch (item->type) {
128 case RTE_FLOW_ITEM_TYPE_GRE:
129 case RTE_FLOW_ITEM_TYPE_NVGRE:
130 case RTE_FLOW_ITEM_TYPE_VXLAN:
131 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
132 case RTE_FLOW_ITEM_TYPE_GENEVE:
133 case RTE_FLOW_ITEM_TYPE_MPLS:
137 case RTE_FLOW_ITEM_TYPE_IPV4:
140 if (item->mask != NULL &&
141 ((const struct rte_flow_item_ipv4 *)
142 item->mask)->hdr.next_proto_id)
144 ((const struct rte_flow_item_ipv4 *)
145 (item->spec))->hdr.next_proto_id &
146 ((const struct rte_flow_item_ipv4 *)
147 (item->mask))->hdr.next_proto_id;
148 if ((next_protocol == IPPROTO_IPIP ||
149 next_protocol == IPPROTO_IPV6) && tunnel_decap)
152 case RTE_FLOW_ITEM_TYPE_IPV6:
155 if (item->mask != NULL &&
156 ((const struct rte_flow_item_ipv6 *)
157 item->mask)->hdr.proto)
159 ((const struct rte_flow_item_ipv6 *)
160 (item->spec))->hdr.proto &
161 ((const struct rte_flow_item_ipv6 *)
162 (item->mask))->hdr.proto;
163 if ((next_protocol == IPPROTO_IPIP ||
164 next_protocol == IPPROTO_IPV6) && tunnel_decap)
167 case RTE_FLOW_ITEM_TYPE_UDP:
171 case RTE_FLOW_ITEM_TYPE_TCP:
183 * Convert rte_mtr_color to mlx5 color.
192 rte_col_2_mlx5_col(enum rte_color rcol)
195 case RTE_COLOR_GREEN:
196 return MLX5_FLOW_COLOR_GREEN;
197 case RTE_COLOR_YELLOW:
198 return MLX5_FLOW_COLOR_YELLOW;
200 return MLX5_FLOW_COLOR_RED;
204 return MLX5_FLOW_COLOR_UNDEFINED;
207 struct field_modify_info {
208 uint32_t size; /* Size of field in protocol header, in bytes. */
209 uint32_t offset; /* Offset of field in protocol header, in bytes. */
210 enum mlx5_modification_field id;
213 struct field_modify_info modify_eth[] = {
214 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
215 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
216 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
217 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
221 struct field_modify_info modify_vlan_out_first_vid[] = {
222 /* Size in bits !!! */
223 {12, 0, MLX5_MODI_OUT_FIRST_VID},
227 struct field_modify_info modify_ipv4[] = {
228 {1, 1, MLX5_MODI_OUT_IP_DSCP},
229 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
230 {4, 12, MLX5_MODI_OUT_SIPV4},
231 {4, 16, MLX5_MODI_OUT_DIPV4},
235 struct field_modify_info modify_ipv6[] = {
236 {1, 0, MLX5_MODI_OUT_IP_DSCP},
237 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
238 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
239 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
240 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
241 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
242 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
243 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
244 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
245 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
249 struct field_modify_info modify_udp[] = {
250 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
251 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
255 struct field_modify_info modify_tcp[] = {
256 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
257 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
258 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
259 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
264 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
265 uint8_t next_protocol, uint64_t *item_flags,
268 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
269 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
270 if (next_protocol == IPPROTO_IPIP) {
271 *item_flags |= MLX5_FLOW_LAYER_IPIP;
274 if (next_protocol == IPPROTO_IPV6) {
275 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
281 * Acquire the synchronizing object to protect multithreaded access
282 * to shared dv context. Lock occurs only if context is actually
283 * shared, i.e. we have multiport IB device and representors are
287 * Pointer to the rte_eth_dev structure.
290 flow_dv_shared_lock(struct rte_eth_dev *dev)
292 struct mlx5_priv *priv = dev->data->dev_private;
293 struct mlx5_dev_ctx_shared *sh = priv->sh;
295 if (sh->dv_refcnt > 1) {
298 ret = pthread_mutex_lock(&sh->dv_mutex);
305 flow_dv_shared_unlock(struct rte_eth_dev *dev)
307 struct mlx5_priv *priv = dev->data->dev_private;
308 struct mlx5_dev_ctx_shared *sh = priv->sh;
310 if (sh->dv_refcnt > 1) {
313 ret = pthread_mutex_unlock(&sh->dv_mutex);
319 /* Update VLAN's VID/PCP based on input rte_flow_action.
322 * Pointer to struct rte_flow_action.
324 * Pointer to struct rte_vlan_hdr.
327 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
328 struct rte_vlan_hdr *vlan)
331 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
333 ((const struct rte_flow_action_of_set_vlan_pcp *)
334 action->conf)->vlan_pcp;
335 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
336 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
337 vlan->vlan_tci |= vlan_tci;
338 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
339 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
340 vlan->vlan_tci |= rte_be_to_cpu_16
341 (((const struct rte_flow_action_of_set_vlan_vid *)
342 action->conf)->vlan_vid);
347 * Fetch 1, 2, 3 or 4 byte field from the byte array
348 * and return as unsigned integer in host-endian format.
351 * Pointer to data array.
353 * Size of field to extract.
356 * converted field in host endian format.
358 static inline uint32_t
359 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
368 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
371 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
372 ret = (ret << 8) | *(data + sizeof(uint16_t));
375 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
386 * Convert modify-header action to DV specification.
388 * Data length of each action is determined by provided field description
389 * and the item mask. Data bit offset and width of each action is determined
390 * by provided item mask.
393 * Pointer to item specification.
395 * Pointer to field modification information.
396 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
397 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
398 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
400 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
401 * Negative offset value sets the same offset as source offset.
402 * size field is ignored, value is taken from source field.
403 * @param[in,out] resource
404 * Pointer to the modify-header resource.
406 * Type of modification.
408 * Pointer to the error structure.
411 * 0 on success, a negative errno value otherwise and rte_errno is set.
414 flow_dv_convert_modify_action(struct rte_flow_item *item,
415 struct field_modify_info *field,
416 struct field_modify_info *dcopy,
417 struct mlx5_flow_dv_modify_hdr_resource *resource,
418 uint32_t type, struct rte_flow_error *error)
420 uint32_t i = resource->actions_num;
421 struct mlx5_modification_cmd *actions = resource->actions;
424 * The item and mask are provided in big-endian format.
425 * The fields should be presented as in big-endian format either.
426 * Mask must be always present, it defines the actual field width.
428 MLX5_ASSERT(item->mask);
429 MLX5_ASSERT(field->size);
436 if (i >= MLX5_MAX_MODIFY_NUM)
437 return rte_flow_error_set(error, EINVAL,
438 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
439 "too many items to modify");
440 /* Fetch variable byte size mask from the array. */
441 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
442 field->offset, field->size);
447 /* Deduce actual data width in bits from mask value. */
448 off_b = rte_bsf32(mask);
449 size_b = sizeof(uint32_t) * CHAR_BIT -
450 off_b - __builtin_clz(mask);
452 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
453 actions[i] = (struct mlx5_modification_cmd) {
459 /* Convert entire record to expected big-endian format. */
460 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
461 if (type == MLX5_MODIFICATION_TYPE_COPY) {
463 actions[i].dst_field = dcopy->id;
464 actions[i].dst_offset =
465 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
466 /* Convert entire record to big-endian format. */
467 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
469 MLX5_ASSERT(item->spec);
470 data = flow_dv_fetch_field((const uint8_t *)item->spec +
471 field->offset, field->size);
472 /* Shift out the trailing masked bits from data. */
473 data = (data & mask) >> off_b;
474 actions[i].data1 = rte_cpu_to_be_32(data);
478 } while (field->size);
479 if (resource->actions_num == i)
480 return rte_flow_error_set(error, EINVAL,
481 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
482 "invalid modification flow item");
483 resource->actions_num = i;
488 * Convert modify-header set IPv4 address action to DV specification.
490 * @param[in,out] resource
491 * Pointer to the modify-header resource.
493 * Pointer to action specification.
495 * Pointer to the error structure.
498 * 0 on success, a negative errno value otherwise and rte_errno is set.
501 flow_dv_convert_action_modify_ipv4
502 (struct mlx5_flow_dv_modify_hdr_resource *resource,
503 const struct rte_flow_action *action,
504 struct rte_flow_error *error)
506 const struct rte_flow_action_set_ipv4 *conf =
507 (const struct rte_flow_action_set_ipv4 *)(action->conf);
508 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
509 struct rte_flow_item_ipv4 ipv4;
510 struct rte_flow_item_ipv4 ipv4_mask;
512 memset(&ipv4, 0, sizeof(ipv4));
513 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
514 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
515 ipv4.hdr.src_addr = conf->ipv4_addr;
516 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
518 ipv4.hdr.dst_addr = conf->ipv4_addr;
519 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
522 item.mask = &ipv4_mask;
523 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
524 MLX5_MODIFICATION_TYPE_SET, error);
528 * Convert modify-header set IPv6 address action to DV specification.
530 * @param[in,out] resource
531 * Pointer to the modify-header resource.
533 * Pointer to action specification.
535 * Pointer to the error structure.
538 * 0 on success, a negative errno value otherwise and rte_errno is set.
541 flow_dv_convert_action_modify_ipv6
542 (struct mlx5_flow_dv_modify_hdr_resource *resource,
543 const struct rte_flow_action *action,
544 struct rte_flow_error *error)
546 const struct rte_flow_action_set_ipv6 *conf =
547 (const struct rte_flow_action_set_ipv6 *)(action->conf);
548 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
549 struct rte_flow_item_ipv6 ipv6;
550 struct rte_flow_item_ipv6 ipv6_mask;
552 memset(&ipv6, 0, sizeof(ipv6));
553 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
554 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
555 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
556 sizeof(ipv6.hdr.src_addr));
557 memcpy(&ipv6_mask.hdr.src_addr,
558 &rte_flow_item_ipv6_mask.hdr.src_addr,
559 sizeof(ipv6.hdr.src_addr));
561 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
562 sizeof(ipv6.hdr.dst_addr));
563 memcpy(&ipv6_mask.hdr.dst_addr,
564 &rte_flow_item_ipv6_mask.hdr.dst_addr,
565 sizeof(ipv6.hdr.dst_addr));
568 item.mask = &ipv6_mask;
569 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
570 MLX5_MODIFICATION_TYPE_SET, error);
574 * Convert modify-header set MAC address action to DV specification.
576 * @param[in,out] resource
577 * Pointer to the modify-header resource.
579 * Pointer to action specification.
581 * Pointer to the error structure.
584 * 0 on success, a negative errno value otherwise and rte_errno is set.
587 flow_dv_convert_action_modify_mac
588 (struct mlx5_flow_dv_modify_hdr_resource *resource,
589 const struct rte_flow_action *action,
590 struct rte_flow_error *error)
592 const struct rte_flow_action_set_mac *conf =
593 (const struct rte_flow_action_set_mac *)(action->conf);
594 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
595 struct rte_flow_item_eth eth;
596 struct rte_flow_item_eth eth_mask;
598 memset(ð, 0, sizeof(eth));
599 memset(ð_mask, 0, sizeof(eth_mask));
600 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
601 memcpy(ð.src.addr_bytes, &conf->mac_addr,
602 sizeof(eth.src.addr_bytes));
603 memcpy(ð_mask.src.addr_bytes,
604 &rte_flow_item_eth_mask.src.addr_bytes,
605 sizeof(eth_mask.src.addr_bytes));
607 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
608 sizeof(eth.dst.addr_bytes));
609 memcpy(ð_mask.dst.addr_bytes,
610 &rte_flow_item_eth_mask.dst.addr_bytes,
611 sizeof(eth_mask.dst.addr_bytes));
614 item.mask = ð_mask;
615 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
616 MLX5_MODIFICATION_TYPE_SET, error);
620 * Convert modify-header set VLAN VID action to DV specification.
622 * @param[in,out] resource
623 * Pointer to the modify-header resource.
625 * Pointer to action specification.
627 * Pointer to the error structure.
630 * 0 on success, a negative errno value otherwise and rte_errno is set.
633 flow_dv_convert_action_modify_vlan_vid
634 (struct mlx5_flow_dv_modify_hdr_resource *resource,
635 const struct rte_flow_action *action,
636 struct rte_flow_error *error)
638 const struct rte_flow_action_of_set_vlan_vid *conf =
639 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
640 int i = resource->actions_num;
641 struct mlx5_modification_cmd *actions = resource->actions;
642 struct field_modify_info *field = modify_vlan_out_first_vid;
644 if (i >= MLX5_MAX_MODIFY_NUM)
645 return rte_flow_error_set(error, EINVAL,
646 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
647 "too many items to modify");
648 actions[i] = (struct mlx5_modification_cmd) {
649 .action_type = MLX5_MODIFICATION_TYPE_SET,
651 .length = field->size,
652 .offset = field->offset,
654 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
655 actions[i].data1 = conf->vlan_vid;
656 actions[i].data1 = actions[i].data1 << 16;
657 resource->actions_num = ++i;
662 * Convert modify-header set TP action to DV specification.
664 * @param[in,out] resource
665 * Pointer to the modify-header resource.
667 * Pointer to action specification.
669 * Pointer to rte_flow_item objects list.
671 * Pointer to flow attributes structure.
672 * @param[in] dev_flow
673 * Pointer to the sub flow.
674 * @param[in] tunnel_decap
675 * Whether action is after tunnel decapsulation.
677 * Pointer to the error structure.
680 * 0 on success, a negative errno value otherwise and rte_errno is set.
683 flow_dv_convert_action_modify_tp
684 (struct mlx5_flow_dv_modify_hdr_resource *resource,
685 const struct rte_flow_action *action,
686 const struct rte_flow_item *items,
687 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
688 bool tunnel_decap, struct rte_flow_error *error)
690 const struct rte_flow_action_set_tp *conf =
691 (const struct rte_flow_action_set_tp *)(action->conf);
692 struct rte_flow_item item;
693 struct rte_flow_item_udp udp;
694 struct rte_flow_item_udp udp_mask;
695 struct rte_flow_item_tcp tcp;
696 struct rte_flow_item_tcp tcp_mask;
697 struct field_modify_info *field;
700 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
702 memset(&udp, 0, sizeof(udp));
703 memset(&udp_mask, 0, sizeof(udp_mask));
704 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
705 udp.hdr.src_port = conf->port;
706 udp_mask.hdr.src_port =
707 rte_flow_item_udp_mask.hdr.src_port;
709 udp.hdr.dst_port = conf->port;
710 udp_mask.hdr.dst_port =
711 rte_flow_item_udp_mask.hdr.dst_port;
713 item.type = RTE_FLOW_ITEM_TYPE_UDP;
715 item.mask = &udp_mask;
718 MLX5_ASSERT(attr->tcp);
719 memset(&tcp, 0, sizeof(tcp));
720 memset(&tcp_mask, 0, sizeof(tcp_mask));
721 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
722 tcp.hdr.src_port = conf->port;
723 tcp_mask.hdr.src_port =
724 rte_flow_item_tcp_mask.hdr.src_port;
726 tcp.hdr.dst_port = conf->port;
727 tcp_mask.hdr.dst_port =
728 rte_flow_item_tcp_mask.hdr.dst_port;
730 item.type = RTE_FLOW_ITEM_TYPE_TCP;
732 item.mask = &tcp_mask;
735 return flow_dv_convert_modify_action(&item, field, NULL, resource,
736 MLX5_MODIFICATION_TYPE_SET, error);
740 * Convert modify-header set TTL action to DV specification.
742 * @param[in,out] resource
743 * Pointer to the modify-header resource.
745 * Pointer to action specification.
747 * Pointer to rte_flow_item objects list.
749 * Pointer to flow attributes structure.
750 * @param[in] dev_flow
751 * Pointer to the sub flow.
752 * @param[in] tunnel_decap
753 * Whether action is after tunnel decapsulation.
755 * Pointer to the error structure.
758 * 0 on success, a negative errno value otherwise and rte_errno is set.
761 flow_dv_convert_action_modify_ttl
762 (struct mlx5_flow_dv_modify_hdr_resource *resource,
763 const struct rte_flow_action *action,
764 const struct rte_flow_item *items,
765 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
766 bool tunnel_decap, struct rte_flow_error *error)
768 const struct rte_flow_action_set_ttl *conf =
769 (const struct rte_flow_action_set_ttl *)(action->conf);
770 struct rte_flow_item item;
771 struct rte_flow_item_ipv4 ipv4;
772 struct rte_flow_item_ipv4 ipv4_mask;
773 struct rte_flow_item_ipv6 ipv6;
774 struct rte_flow_item_ipv6 ipv6_mask;
775 struct field_modify_info *field;
778 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
780 memset(&ipv4, 0, sizeof(ipv4));
781 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
782 ipv4.hdr.time_to_live = conf->ttl_value;
783 ipv4_mask.hdr.time_to_live = 0xFF;
784 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
786 item.mask = &ipv4_mask;
789 MLX5_ASSERT(attr->ipv6);
790 memset(&ipv6, 0, sizeof(ipv6));
791 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
792 ipv6.hdr.hop_limits = conf->ttl_value;
793 ipv6_mask.hdr.hop_limits = 0xFF;
794 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
796 item.mask = &ipv6_mask;
799 return flow_dv_convert_modify_action(&item, field, NULL, resource,
800 MLX5_MODIFICATION_TYPE_SET, error);
804 * Convert modify-header decrement TTL action to DV specification.
806 * @param[in,out] resource
807 * Pointer to the modify-header resource.
809 * Pointer to action specification.
811 * Pointer to rte_flow_item objects list.
813 * Pointer to flow attributes structure.
814 * @param[in] dev_flow
815 * Pointer to the sub flow.
816 * @param[in] tunnel_decap
817 * Whether action is after tunnel decapsulation.
819 * Pointer to the error structure.
822 * 0 on success, a negative errno value otherwise and rte_errno is set.
825 flow_dv_convert_action_modify_dec_ttl
826 (struct mlx5_flow_dv_modify_hdr_resource *resource,
827 const struct rte_flow_item *items,
828 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
829 bool tunnel_decap, struct rte_flow_error *error)
831 struct rte_flow_item item;
832 struct rte_flow_item_ipv4 ipv4;
833 struct rte_flow_item_ipv4 ipv4_mask;
834 struct rte_flow_item_ipv6 ipv6;
835 struct rte_flow_item_ipv6 ipv6_mask;
836 struct field_modify_info *field;
839 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
841 memset(&ipv4, 0, sizeof(ipv4));
842 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
843 ipv4.hdr.time_to_live = 0xFF;
844 ipv4_mask.hdr.time_to_live = 0xFF;
845 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
847 item.mask = &ipv4_mask;
850 MLX5_ASSERT(attr->ipv6);
851 memset(&ipv6, 0, sizeof(ipv6));
852 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
853 ipv6.hdr.hop_limits = 0xFF;
854 ipv6_mask.hdr.hop_limits = 0xFF;
855 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
857 item.mask = &ipv6_mask;
860 return flow_dv_convert_modify_action(&item, field, NULL, resource,
861 MLX5_MODIFICATION_TYPE_ADD, error);
865 * Convert modify-header increment/decrement TCP Sequence number
866 * to DV specification.
868 * @param[in,out] resource
869 * Pointer to the modify-header resource.
871 * Pointer to action specification.
873 * Pointer to the error structure.
876 * 0 on success, a negative errno value otherwise and rte_errno is set.
879 flow_dv_convert_action_modify_tcp_seq
880 (struct mlx5_flow_dv_modify_hdr_resource *resource,
881 const struct rte_flow_action *action,
882 struct rte_flow_error *error)
884 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
885 uint64_t value = rte_be_to_cpu_32(*conf);
886 struct rte_flow_item item;
887 struct rte_flow_item_tcp tcp;
888 struct rte_flow_item_tcp tcp_mask;
890 memset(&tcp, 0, sizeof(tcp));
891 memset(&tcp_mask, 0, sizeof(tcp_mask));
892 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
894 * The HW has no decrement operation, only increment operation.
895 * To simulate decrement X from Y using increment operation
896 * we need to add UINT32_MAX X times to Y.
897 * Each adding of UINT32_MAX decrements Y by 1.
900 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
901 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
902 item.type = RTE_FLOW_ITEM_TYPE_TCP;
904 item.mask = &tcp_mask;
905 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
906 MLX5_MODIFICATION_TYPE_ADD, error);
910 * Convert modify-header increment/decrement TCP Acknowledgment number
911 * to DV specification.
913 * @param[in,out] resource
914 * Pointer to the modify-header resource.
916 * Pointer to action specification.
918 * Pointer to the error structure.
921 * 0 on success, a negative errno value otherwise and rte_errno is set.
924 flow_dv_convert_action_modify_tcp_ack
925 (struct mlx5_flow_dv_modify_hdr_resource *resource,
926 const struct rte_flow_action *action,
927 struct rte_flow_error *error)
929 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
930 uint64_t value = rte_be_to_cpu_32(*conf);
931 struct rte_flow_item item;
932 struct rte_flow_item_tcp tcp;
933 struct rte_flow_item_tcp tcp_mask;
935 memset(&tcp, 0, sizeof(tcp));
936 memset(&tcp_mask, 0, sizeof(tcp_mask));
937 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
939 * The HW has no decrement operation, only increment operation.
940 * To simulate decrement X from Y using increment operation
941 * we need to add UINT32_MAX X times to Y.
942 * Each adding of UINT32_MAX decrements Y by 1.
945 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
946 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
947 item.type = RTE_FLOW_ITEM_TYPE_TCP;
949 item.mask = &tcp_mask;
950 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
951 MLX5_MODIFICATION_TYPE_ADD, error);
954 static enum mlx5_modification_field reg_to_field[] = {
955 [REG_NONE] = MLX5_MODI_OUT_NONE,
956 [REG_A] = MLX5_MODI_META_DATA_REG_A,
957 [REG_B] = MLX5_MODI_META_DATA_REG_B,
958 [REG_C_0] = MLX5_MODI_META_REG_C_0,
959 [REG_C_1] = MLX5_MODI_META_REG_C_1,
960 [REG_C_2] = MLX5_MODI_META_REG_C_2,
961 [REG_C_3] = MLX5_MODI_META_REG_C_3,
962 [REG_C_4] = MLX5_MODI_META_REG_C_4,
963 [REG_C_5] = MLX5_MODI_META_REG_C_5,
964 [REG_C_6] = MLX5_MODI_META_REG_C_6,
965 [REG_C_7] = MLX5_MODI_META_REG_C_7,
969 * Convert register set to DV specification.
971 * @param[in,out] resource
972 * Pointer to the modify-header resource.
974 * Pointer to action specification.
976 * Pointer to the error structure.
979 * 0 on success, a negative errno value otherwise and rte_errno is set.
982 flow_dv_convert_action_set_reg
983 (struct mlx5_flow_dv_modify_hdr_resource *resource,
984 const struct rte_flow_action *action,
985 struct rte_flow_error *error)
987 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
988 struct mlx5_modification_cmd *actions = resource->actions;
989 uint32_t i = resource->actions_num;
991 if (i >= MLX5_MAX_MODIFY_NUM)
992 return rte_flow_error_set(error, EINVAL,
993 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
994 "too many items to modify");
995 MLX5_ASSERT(conf->id != REG_NONE);
996 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
997 actions[i] = (struct mlx5_modification_cmd) {
998 .action_type = MLX5_MODIFICATION_TYPE_SET,
999 .field = reg_to_field[conf->id],
1001 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1002 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1004 resource->actions_num = i;
1009 * Convert SET_TAG action to DV specification.
1012 * Pointer to the rte_eth_dev structure.
1013 * @param[in,out] resource
1014 * Pointer to the modify-header resource.
1016 * Pointer to action specification.
1018 * Pointer to the error structure.
1021 * 0 on success, a negative errno value otherwise and rte_errno is set.
1024 flow_dv_convert_action_set_tag
1025 (struct rte_eth_dev *dev,
1026 struct mlx5_flow_dv_modify_hdr_resource *resource,
1027 const struct rte_flow_action_set_tag *conf,
1028 struct rte_flow_error *error)
1030 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1031 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1032 struct rte_flow_item item = {
1036 struct field_modify_info reg_c_x[] = {
1039 enum mlx5_modification_field reg_type;
1042 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1045 MLX5_ASSERT(ret != REG_NONE);
1046 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1047 reg_type = reg_to_field[ret];
1048 MLX5_ASSERT(reg_type > 0);
1049 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1050 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1051 MLX5_MODIFICATION_TYPE_SET, error);
1055 * Convert internal COPY_REG action to DV specification.
1058 * Pointer to the rte_eth_dev structure.
1059 * @param[in,out] res
1060 * Pointer to the modify-header resource.
1062 * Pointer to action specification.
1064 * Pointer to the error structure.
1067 * 0 on success, a negative errno value otherwise and rte_errno is set.
1070 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1071 struct mlx5_flow_dv_modify_hdr_resource *res,
1072 const struct rte_flow_action *action,
1073 struct rte_flow_error *error)
1075 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1076 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1077 struct rte_flow_item item = {
1081 struct field_modify_info reg_src[] = {
1082 {4, 0, reg_to_field[conf->src]},
1085 struct field_modify_info reg_dst = {
1087 .id = reg_to_field[conf->dst],
1089 /* Adjust reg_c[0] usage according to reported mask. */
1090 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1091 struct mlx5_priv *priv = dev->data->dev_private;
1092 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1094 MLX5_ASSERT(reg_c0);
1095 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1096 if (conf->dst == REG_C_0) {
1097 /* Copy to reg_c[0], within mask only. */
1098 reg_dst.offset = rte_bsf32(reg_c0);
1100 * Mask is ignoring the enianness, because
1101 * there is no conversion in datapath.
1103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1104 /* Copy from destination lower bits to reg_c[0]. */
1105 mask = reg_c0 >> reg_dst.offset;
1107 /* Copy from destination upper bits to reg_c[0]. */
1108 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1109 rte_fls_u32(reg_c0));
1112 mask = rte_cpu_to_be_32(reg_c0);
1113 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1114 /* Copy from reg_c[0] to destination lower bits. */
1117 /* Copy from reg_c[0] to destination upper bits. */
1118 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1119 (rte_fls_u32(reg_c0) -
1124 return flow_dv_convert_modify_action(&item,
1125 reg_src, ®_dst, res,
1126 MLX5_MODIFICATION_TYPE_COPY,
1131 * Convert MARK action to DV specification. This routine is used
1132 * in extensive metadata only and requires metadata register to be
1133 * handled. In legacy mode hardware tag resource is engaged.
1136 * Pointer to the rte_eth_dev structure.
1138 * Pointer to MARK action specification.
1139 * @param[in,out] resource
1140 * Pointer to the modify-header resource.
1142 * Pointer to the error structure.
1145 * 0 on success, a negative errno value otherwise and rte_errno is set.
1148 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1149 const struct rte_flow_action_mark *conf,
1150 struct mlx5_flow_dv_modify_hdr_resource *resource,
1151 struct rte_flow_error *error)
1153 struct mlx5_priv *priv = dev->data->dev_private;
1154 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1155 priv->sh->dv_mark_mask);
1156 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1157 struct rte_flow_item item = {
1161 struct field_modify_info reg_c_x[] = {
1162 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1168 return rte_flow_error_set(error, EINVAL,
1169 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1170 NULL, "zero mark action mask");
1171 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1174 MLX5_ASSERT(reg > 0);
1175 if (reg == REG_C_0) {
1176 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1177 uint32_t shl_c0 = rte_bsf32(msk_c0);
1179 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1180 mask = rte_cpu_to_be_32(mask) & msk_c0;
1181 mask = rte_cpu_to_be_32(mask << shl_c0);
1183 reg_c_x[0].id = reg_to_field[reg];
1184 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1185 MLX5_MODIFICATION_TYPE_SET, error);
1189 * Get metadata register index for specified steering domain.
1192 * Pointer to the rte_eth_dev structure.
1194 * Attributes of flow to determine steering domain.
1196 * Pointer to the error structure.
1199 * positive index on success, a negative errno value otherwise
1200 * and rte_errno is set.
1202 static enum modify_reg
1203 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1204 const struct rte_flow_attr *attr,
1205 struct rte_flow_error *error)
1208 mlx5_flow_get_reg_id(dev, attr->transfer ?
1212 MLX5_METADATA_RX, 0, error);
1214 return rte_flow_error_set(error,
1215 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1216 NULL, "unavailable "
1217 "metadata register");
1222 * Convert SET_META action to DV specification.
1225 * Pointer to the rte_eth_dev structure.
1226 * @param[in,out] resource
1227 * Pointer to the modify-header resource.
1229 * Attributes of flow that includes this item.
1231 * Pointer to action specification.
1233 * Pointer to the error structure.
1236 * 0 on success, a negative errno value otherwise and rte_errno is set.
1239 flow_dv_convert_action_set_meta
1240 (struct rte_eth_dev *dev,
1241 struct mlx5_flow_dv_modify_hdr_resource *resource,
1242 const struct rte_flow_attr *attr,
1243 const struct rte_flow_action_set_meta *conf,
1244 struct rte_flow_error *error)
1246 uint32_t data = conf->data;
1247 uint32_t mask = conf->mask;
1248 struct rte_flow_item item = {
1252 struct field_modify_info reg_c_x[] = {
1255 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1260 * In datapath code there is no endianness
1261 * coversions for perfromance reasons, all
1262 * pattern conversions are done in rte_flow.
1264 if (reg == REG_C_0) {
1265 struct mlx5_priv *priv = dev->data->dev_private;
1266 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1269 MLX5_ASSERT(msk_c0);
1270 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1271 shl_c0 = rte_bsf32(msk_c0);
1273 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1277 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1279 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1280 /* The routine expects parameters in memory as big-endian ones. */
1281 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1282 MLX5_MODIFICATION_TYPE_SET, error);
1286 * Convert modify-header set IPv4 DSCP action to DV specification.
1288 * @param[in,out] resource
1289 * Pointer to the modify-header resource.
1291 * Pointer to action specification.
1293 * Pointer to the error structure.
1296 * 0 on success, a negative errno value otherwise and rte_errno is set.
1299 flow_dv_convert_action_modify_ipv4_dscp
1300 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1301 const struct rte_flow_action *action,
1302 struct rte_flow_error *error)
1304 const struct rte_flow_action_set_dscp *conf =
1305 (const struct rte_flow_action_set_dscp *)(action->conf);
1306 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1307 struct rte_flow_item_ipv4 ipv4;
1308 struct rte_flow_item_ipv4 ipv4_mask;
1310 memset(&ipv4, 0, sizeof(ipv4));
1311 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1312 ipv4.hdr.type_of_service = conf->dscp;
1313 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1315 item.mask = &ipv4_mask;
1316 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1317 MLX5_MODIFICATION_TYPE_SET, error);
1321 * Convert modify-header set IPv6 DSCP action to DV specification.
1323 * @param[in,out] resource
1324 * Pointer to the modify-header resource.
1326 * Pointer to action specification.
1328 * Pointer to the error structure.
1331 * 0 on success, a negative errno value otherwise and rte_errno is set.
1334 flow_dv_convert_action_modify_ipv6_dscp
1335 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1336 const struct rte_flow_action *action,
1337 struct rte_flow_error *error)
1339 const struct rte_flow_action_set_dscp *conf =
1340 (const struct rte_flow_action_set_dscp *)(action->conf);
1341 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1342 struct rte_flow_item_ipv6 ipv6;
1343 struct rte_flow_item_ipv6 ipv6_mask;
1345 memset(&ipv6, 0, sizeof(ipv6));
1346 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1348 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1349 * rdma-core only accept the DSCP bits byte aligned start from
1350 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1351 * bits in IPv6 case as rdma-core requires byte aligned value.
1353 ipv6.hdr.vtc_flow = conf->dscp;
1354 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1356 item.mask = &ipv6_mask;
1357 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1358 MLX5_MODIFICATION_TYPE_SET, error);
1362 * Validate MARK item.
1365 * Pointer to the rte_eth_dev structure.
1367 * Item specification.
1369 * Attributes of flow that includes this item.
1371 * Pointer to error structure.
1374 * 0 on success, a negative errno value otherwise and rte_errno is set.
1377 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1378 const struct rte_flow_item *item,
1379 const struct rte_flow_attr *attr __rte_unused,
1380 struct rte_flow_error *error)
1382 struct mlx5_priv *priv = dev->data->dev_private;
1383 struct mlx5_dev_config *config = &priv->config;
1384 const struct rte_flow_item_mark *spec = item->spec;
1385 const struct rte_flow_item_mark *mask = item->mask;
1386 const struct rte_flow_item_mark nic_mask = {
1387 .id = priv->sh->dv_mark_mask,
1391 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata feature"
1396 if (!mlx5_flow_ext_mreg_supported(dev))
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1399 "extended metadata register"
1400 " isn't supported");
1402 return rte_flow_error_set(error, ENOTSUP,
1403 RTE_FLOW_ERROR_TYPE_ITEM, item,
1404 "extended metadata register"
1405 " isn't available");
1406 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1413 "data cannot be empty");
1414 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1418 "mark id exceeds the limit");
1422 return rte_flow_error_set(error, EINVAL,
1423 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1424 "mask cannot be zero");
1426 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1427 (const uint8_t *)&nic_mask,
1428 sizeof(struct rte_flow_item_mark),
1436 * Validate META item.
1439 * Pointer to the rte_eth_dev structure.
1441 * Item specification.
1443 * Attributes of flow that includes this item.
1445 * Pointer to error structure.
1448 * 0 on success, a negative errno value otherwise and rte_errno is set.
1451 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1452 const struct rte_flow_item *item,
1453 const struct rte_flow_attr *attr,
1454 struct rte_flow_error *error)
1456 struct mlx5_priv *priv = dev->data->dev_private;
1457 struct mlx5_dev_config *config = &priv->config;
1458 const struct rte_flow_item_meta *spec = item->spec;
1459 const struct rte_flow_item_meta *mask = item->mask;
1460 struct rte_flow_item_meta nic_mask = {
1467 return rte_flow_error_set(error, EINVAL,
1468 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1470 "data cannot be empty");
1471 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1472 if (!mlx5_flow_ext_mreg_supported(dev))
1473 return rte_flow_error_set(error, ENOTSUP,
1474 RTE_FLOW_ERROR_TYPE_ITEM, item,
1475 "extended metadata register"
1476 " isn't supported");
1477 reg = flow_dv_get_metadata_reg(dev, attr, error);
1481 return rte_flow_error_set(error, ENOTSUP,
1482 RTE_FLOW_ERROR_TYPE_ITEM, item,
1486 nic_mask.data = priv->sh->dv_meta_mask;
1489 mask = &rte_flow_item_meta_mask;
1491 return rte_flow_error_set(error, EINVAL,
1492 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493 "mask cannot be zero");
1495 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496 (const uint8_t *)&nic_mask,
1497 sizeof(struct rte_flow_item_meta),
1503 * Validate TAG item.
1506 * Pointer to the rte_eth_dev structure.
1508 * Item specification.
1510 * Attributes of flow that includes this item.
1512 * Pointer to error structure.
1515 * 0 on success, a negative errno value otherwise and rte_errno is set.
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519 const struct rte_flow_item *item,
1520 const struct rte_flow_attr *attr __rte_unused,
1521 struct rte_flow_error *error)
1523 const struct rte_flow_item_tag *spec = item->spec;
1524 const struct rte_flow_item_tag *mask = item->mask;
1525 const struct rte_flow_item_tag nic_mask = {
1526 .data = RTE_BE32(UINT32_MAX),
1531 if (!mlx5_flow_ext_mreg_supported(dev))
1532 return rte_flow_error_set(error, ENOTSUP,
1533 RTE_FLOW_ERROR_TYPE_ITEM, item,
1534 "extensive metadata register"
1535 " isn't supported");
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1540 "data cannot be empty");
1542 mask = &rte_flow_item_tag_mask;
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546 "mask cannot be zero");
1548 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549 (const uint8_t *)&nic_mask,
1550 sizeof(struct rte_flow_item_tag),
1554 if (mask->index != 0xff)
1555 return rte_flow_error_set(error, EINVAL,
1556 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557 "partial mask for tag index"
1558 " is not supported");
1559 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1562 MLX5_ASSERT(ret != REG_NONE);
1567 * Validate vport item.
1570 * Pointer to the rte_eth_dev structure.
1572 * Item specification.
1574 * Attributes of flow that includes this item.
1575 * @param[in] item_flags
1576 * Bit-fields that holds the items detected until now.
1578 * Pointer to error structure.
1581 * 0 on success, a negative errno value otherwise and rte_errno is set.
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585 const struct rte_flow_item *item,
1586 const struct rte_flow_attr *attr,
1587 uint64_t item_flags,
1588 struct rte_flow_error *error)
1590 const struct rte_flow_item_port_id *spec = item->spec;
1591 const struct rte_flow_item_port_id *mask = item->mask;
1592 const struct rte_flow_item_port_id switch_mask = {
1595 struct mlx5_priv *esw_priv;
1596 struct mlx5_priv *dev_priv;
1599 if (!attr->transfer)
1600 return rte_flow_error_set(error, EINVAL,
1601 RTE_FLOW_ERROR_TYPE_ITEM,
1603 "match on port id is valid only"
1604 " when transfer flag is enabled");
1605 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606 return rte_flow_error_set(error, ENOTSUP,
1607 RTE_FLOW_ERROR_TYPE_ITEM, item,
1608 "multiple source ports are not"
1611 mask = &switch_mask;
1612 if (mask->id != 0xffffffff)
1613 return rte_flow_error_set(error, ENOTSUP,
1614 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1616 "no support for partial mask on"
1618 ret = mlx5_flow_item_acceptable
1619 (item, (const uint8_t *)mask,
1620 (const uint8_t *)&rte_flow_item_port_id_mask,
1621 sizeof(struct rte_flow_item_port_id),
1627 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631 "failed to obtain E-Switch info for"
1633 dev_priv = mlx5_dev_to_eswitch_info(dev);
1635 return rte_flow_error_set(error, rte_errno,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1638 "failed to obtain E-Switch info");
1639 if (esw_priv->domain_id != dev_priv->domain_id)
1640 return rte_flow_error_set(error, EINVAL,
1641 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642 "cannot match on a port from a"
1643 " different E-Switch");
1648 * Validate VLAN item.
1651 * Item specification.
1652 * @param[in] item_flags
1653 * Bit-fields that holds the items detected until now.
1655 * Ethernet device flow is being created on.
1657 * Pointer to error structure.
1660 * 0 on success, a negative errno value otherwise and rte_errno is set.
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664 uint64_t item_flags,
1665 struct rte_eth_dev *dev,
1666 struct rte_flow_error *error)
1668 const struct rte_flow_item_vlan *mask = item->mask;
1669 const struct rte_flow_item_vlan nic_mask = {
1670 .tci = RTE_BE16(UINT16_MAX),
1671 .inner_type = RTE_BE16(UINT16_MAX),
1673 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1675 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676 MLX5_FLOW_LAYER_INNER_L4) :
1677 (MLX5_FLOW_LAYER_OUTER_L3 |
1678 MLX5_FLOW_LAYER_OUTER_L4);
1679 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680 MLX5_FLOW_LAYER_OUTER_VLAN;
1682 if (item_flags & vlanm)
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM, item,
1685 "multiple VLAN layers not supported");
1686 else if ((item_flags & l34m) != 0)
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM, item,
1689 "VLAN cannot follow L3/L4 layer");
1691 mask = &rte_flow_item_vlan_mask;
1692 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693 (const uint8_t *)&nic_mask,
1694 sizeof(struct rte_flow_item_vlan),
1698 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699 struct mlx5_priv *priv = dev->data->dev_private;
1701 if (priv->vmwa_context) {
1703 * Non-NULL context means we have a virtual machine
1704 * and SR-IOV enabled, we have to create VLAN interface
1705 * to make hypervisor to setup E-Switch vport
1706 * context correctly. We avoid creating the multiple
1707 * VLAN interfaces, so we cannot support VLAN tag mask.
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ITEM,
1712 "VLAN tag mask is not"
1713 " supported in virtual"
1721 * GTP flags are contained in 1 byte of the format:
1722 * -------------------------------------------
1723 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1724 * |-----------------------------------------|
1725 * | value | Version | PT | Res | E | S | PN |
1726 * -------------------------------------------
1728 * Matching is supported only for GTP flags E, S, PN.
1730 #define MLX5_GTP_FLAGS_MASK 0x07
1733 * Validate GTP item.
1736 * Pointer to the rte_eth_dev structure.
1738 * Item specification.
1739 * @param[in] item_flags
1740 * Bit-fields that holds the items detected until now.
1742 * Pointer to error structure.
1745 * 0 on success, a negative errno value otherwise and rte_errno is set.
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749 const struct rte_flow_item *item,
1750 uint64_t item_flags,
1751 struct rte_flow_error *error)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 const struct rte_flow_item_gtp *spec = item->spec;
1755 const struct rte_flow_item_gtp *mask = item->mask;
1756 const struct rte_flow_item_gtp nic_mask = {
1757 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1759 .teid = RTE_BE32(0xffffffff),
1762 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763 return rte_flow_error_set(error, ENOTSUP,
1764 RTE_FLOW_ERROR_TYPE_ITEM, item,
1765 "GTP support is not enabled");
1766 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767 return rte_flow_error_set(error, ENOTSUP,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "multiple tunnel layers not"
1771 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772 return rte_flow_error_set(error, EINVAL,
1773 RTE_FLOW_ERROR_TYPE_ITEM, item,
1774 "no outer UDP layer found");
1776 mask = &rte_flow_item_gtp_mask;
1777 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778 return rte_flow_error_set(error, ENOTSUP,
1779 RTE_FLOW_ERROR_TYPE_ITEM, item,
1780 "Match is supported for GTP"
1782 return mlx5_flow_item_acceptable
1783 (item, (const uint8_t *)mask,
1784 (const uint8_t *)&nic_mask,
1785 sizeof(struct rte_flow_item_gtp),
1790 * Validate the pop VLAN action.
1793 * Pointer to the rte_eth_dev structure.
1794 * @param[in] action_flags
1795 * Holds the actions detected until now.
1797 * Pointer to the pop vlan action.
1798 * @param[in] item_flags
1799 * The items found in this flow rule.
1801 * Pointer to flow attributes.
1803 * Pointer to error structure.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810 uint64_t action_flags,
1811 const struct rte_flow_action *action,
1812 uint64_t item_flags,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct mlx5_priv *priv = dev->data->dev_private;
1820 if (!priv->sh->pop_vlan_action)
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1824 "pop vlan action is not supported");
1826 return rte_flow_error_set(error, ENOTSUP,
1827 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1829 "pop vlan action not supported for "
1831 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ACTION, action,
1834 "no support for multiple VLAN "
1836 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1837 return rte_flow_error_set(error, ENOTSUP,
1838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1840 "cannot pop vlan without a "
1841 "match on (outer) vlan in the flow");
1842 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1843 return rte_flow_error_set(error, EINVAL,
1844 RTE_FLOW_ERROR_TYPE_ACTION, action,
1845 "wrong action order, port_id should "
1846 "be after pop VLAN action");
1847 if (!attr->transfer && priv->representor)
1848 return rte_flow_error_set(error, ENOTSUP,
1849 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1850 "pop vlan action for VF representor "
1851 "not supported on NIC table");
1856 * Get VLAN default info from vlan match info.
1859 * the list of item specifications.
1861 * pointer VLAN info to fill to.
1864 * 0 on success, a negative errno value otherwise and rte_errno is set.
1867 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1868 struct rte_vlan_hdr *vlan)
1870 const struct rte_flow_item_vlan nic_mask = {
1871 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1872 MLX5DV_FLOW_VLAN_VID_MASK),
1873 .inner_type = RTE_BE16(0xffff),
1878 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1879 int type = items->type;
1881 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1882 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1885 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1886 const struct rte_flow_item_vlan *vlan_m = items->mask;
1887 const struct rte_flow_item_vlan *vlan_v = items->spec;
1889 /* If VLAN item in pattern doesn't contain data, return here. */
1894 /* Only full match values are accepted */
1895 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1896 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1897 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1899 rte_be_to_cpu_16(vlan_v->tci &
1900 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1902 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1903 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1904 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1906 rte_be_to_cpu_16(vlan_v->tci &
1907 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1909 if (vlan_m->inner_type == nic_mask.inner_type)
1910 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1911 vlan_m->inner_type);
1916 * Validate the push VLAN action.
1919 * Pointer to the rte_eth_dev structure.
1920 * @param[in] action_flags
1921 * Holds the actions detected until now.
1922 * @param[in] item_flags
1923 * The items found in this flow rule.
1925 * Pointer to the action structure.
1927 * Pointer to flow attributes
1929 * Pointer to error structure.
1932 * 0 on success, a negative errno value otherwise and rte_errno is set.
1935 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1936 uint64_t action_flags,
1937 const struct rte_flow_item_vlan *vlan_m,
1938 const struct rte_flow_action *action,
1939 const struct rte_flow_attr *attr,
1940 struct rte_flow_error *error)
1942 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1943 const struct mlx5_priv *priv = dev->data->dev_private;
1945 if (!attr->transfer && attr->ingress)
1946 return rte_flow_error_set(error, ENOTSUP,
1947 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1949 "push VLAN action not supported for "
1951 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1952 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1953 return rte_flow_error_set(error, EINVAL,
1954 RTE_FLOW_ERROR_TYPE_ACTION, action,
1955 "invalid vlan ethertype");
1956 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1957 return rte_flow_error_set(error, ENOTSUP,
1958 RTE_FLOW_ERROR_TYPE_ACTION, action,
1959 "no support for multiple VLAN "
1961 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ACTION, action,
1964 "wrong action order, port_id should "
1965 "be after push VLAN");
1966 if (!attr->transfer && priv->representor)
1967 return rte_flow_error_set(error, ENOTSUP,
1968 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1969 "push vlan action for VF representor "
1970 "not supported on NIC table");
1972 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1973 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1974 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1975 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1976 !(mlx5_flow_find_action
1977 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1978 return rte_flow_error_set(error, EINVAL,
1979 RTE_FLOW_ERROR_TYPE_ACTION, action,
1980 "not full match mask on VLAN PCP and "
1981 "there is no of_set_vlan_pcp action, "
1982 "push VLAN action cannot figure out "
1985 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1986 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1987 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1988 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1989 !(mlx5_flow_find_action
1990 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1991 return rte_flow_error_set(error, EINVAL,
1992 RTE_FLOW_ERROR_TYPE_ACTION, action,
1993 "not full match mask on VLAN VID and "
1994 "there is no of_set_vlan_vid action, "
1995 "push VLAN action cannot figure out "
2002 * Validate the set VLAN PCP.
2004 * @param[in] action_flags
2005 * Holds the actions detected until now.
2006 * @param[in] actions
2007 * Pointer to the list of actions remaining in the flow rule.
2009 * Pointer to error structure.
2012 * 0 on success, a negative errno value otherwise and rte_errno is set.
2015 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2016 const struct rte_flow_action actions[],
2017 struct rte_flow_error *error)
2019 const struct rte_flow_action *action = actions;
2020 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2022 if (conf->vlan_pcp > 7)
2023 return rte_flow_error_set(error, EINVAL,
2024 RTE_FLOW_ERROR_TYPE_ACTION, action,
2025 "VLAN PCP value is too big");
2026 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2027 return rte_flow_error_set(error, ENOTSUP,
2028 RTE_FLOW_ERROR_TYPE_ACTION, action,
2029 "set VLAN PCP action must follow "
2030 "the push VLAN action");
2031 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2032 return rte_flow_error_set(error, ENOTSUP,
2033 RTE_FLOW_ERROR_TYPE_ACTION, action,
2034 "Multiple VLAN PCP modification are "
2036 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2037 return rte_flow_error_set(error, EINVAL,
2038 RTE_FLOW_ERROR_TYPE_ACTION, action,
2039 "wrong action order, port_id should "
2040 "be after set VLAN PCP");
2045 * Validate the set VLAN VID.
2047 * @param[in] item_flags
2048 * Holds the items detected in this rule.
2049 * @param[in] action_flags
2050 * Holds the actions detected until now.
2051 * @param[in] actions
2052 * Pointer to the list of actions remaining in the flow rule.
2054 * Pointer to error structure.
2057 * 0 on success, a negative errno value otherwise and rte_errno is set.
2060 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2061 uint64_t action_flags,
2062 const struct rte_flow_action actions[],
2063 struct rte_flow_error *error)
2065 const struct rte_flow_action *action = actions;
2066 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2068 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ACTION, action,
2071 "VLAN VID value is too big");
2072 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2073 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2074 return rte_flow_error_set(error, ENOTSUP,
2075 RTE_FLOW_ERROR_TYPE_ACTION, action,
2076 "set VLAN VID action must follow push"
2077 " VLAN action or match on VLAN item");
2078 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2079 return rte_flow_error_set(error, ENOTSUP,
2080 RTE_FLOW_ERROR_TYPE_ACTION, action,
2081 "Multiple VLAN VID modifications are "
2083 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2084 return rte_flow_error_set(error, EINVAL,
2085 RTE_FLOW_ERROR_TYPE_ACTION, action,
2086 "wrong action order, port_id should "
2087 "be after set VLAN VID");
2092 * Validate the FLAG action.
2095 * Pointer to the rte_eth_dev structure.
2096 * @param[in] action_flags
2097 * Holds the actions detected until now.
2099 * Pointer to flow attributes
2101 * Pointer to error structure.
2104 * 0 on success, a negative errno value otherwise and rte_errno is set.
2107 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2108 uint64_t action_flags,
2109 const struct rte_flow_attr *attr,
2110 struct rte_flow_error *error)
2112 struct mlx5_priv *priv = dev->data->dev_private;
2113 struct mlx5_dev_config *config = &priv->config;
2116 /* Fall back if no extended metadata register support. */
2117 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2118 return mlx5_flow_validate_action_flag(action_flags, attr,
2120 /* Extensive metadata mode requires registers. */
2121 if (!mlx5_flow_ext_mreg_supported(dev))
2122 return rte_flow_error_set(error, ENOTSUP,
2123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2124 "no metadata registers "
2125 "to support flag action");
2126 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2127 return rte_flow_error_set(error, ENOTSUP,
2128 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2129 "extended metadata register"
2130 " isn't available");
2131 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2134 MLX5_ASSERT(ret > 0);
2135 if (action_flags & MLX5_FLOW_ACTION_MARK)
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2138 "can't mark and flag in same flow");
2139 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2140 return rte_flow_error_set(error, EINVAL,
2141 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2143 " actions in same flow");
2148 * Validate MARK action.
2151 * Pointer to the rte_eth_dev structure.
2153 * Pointer to action.
2154 * @param[in] action_flags
2155 * Holds the actions detected until now.
2157 * Pointer to flow attributes
2159 * Pointer to error structure.
2162 * 0 on success, a negative errno value otherwise and rte_errno is set.
2165 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2166 const struct rte_flow_action *action,
2167 uint64_t action_flags,
2168 const struct rte_flow_attr *attr,
2169 struct rte_flow_error *error)
2171 struct mlx5_priv *priv = dev->data->dev_private;
2172 struct mlx5_dev_config *config = &priv->config;
2173 const struct rte_flow_action_mark *mark = action->conf;
2176 /* Fall back if no extended metadata register support. */
2177 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2178 return mlx5_flow_validate_action_mark(action, action_flags,
2180 /* Extensive metadata mode requires registers. */
2181 if (!mlx5_flow_ext_mreg_supported(dev))
2182 return rte_flow_error_set(error, ENOTSUP,
2183 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184 "no metadata registers "
2185 "to support mark action");
2186 if (!priv->sh->dv_mark_mask)
2187 return rte_flow_error_set(error, ENOTSUP,
2188 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2189 "extended metadata register"
2190 " isn't available");
2191 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2194 MLX5_ASSERT(ret > 0);
2196 return rte_flow_error_set(error, EINVAL,
2197 RTE_FLOW_ERROR_TYPE_ACTION, action,
2198 "configuration cannot be null");
2199 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2200 return rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2203 "mark id exceeds the limit");
2204 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2205 return rte_flow_error_set(error, EINVAL,
2206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2207 "can't flag and mark in same flow");
2208 if (action_flags & MLX5_FLOW_ACTION_MARK)
2209 return rte_flow_error_set(error, EINVAL,
2210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2211 "can't have 2 mark actions in same"
2217 * Validate SET_META action.
2220 * Pointer to the rte_eth_dev structure.
2222 * Pointer to the action structure.
2223 * @param[in] action_flags
2224 * Holds the actions detected until now.
2226 * Pointer to flow attributes
2228 * Pointer to error structure.
2231 * 0 on success, a negative errno value otherwise and rte_errno is set.
2234 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2235 const struct rte_flow_action *action,
2236 uint64_t action_flags __rte_unused,
2237 const struct rte_flow_attr *attr,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_action_set_meta *conf;
2241 uint32_t nic_mask = UINT32_MAX;
2244 if (!mlx5_flow_ext_mreg_supported(dev))
2245 return rte_flow_error_set(error, ENOTSUP,
2246 RTE_FLOW_ERROR_TYPE_ACTION, action,
2247 "extended metadata register"
2248 " isn't supported");
2249 reg = flow_dv_get_metadata_reg(dev, attr, error);
2252 if (reg != REG_A && reg != REG_B) {
2253 struct mlx5_priv *priv = dev->data->dev_private;
2255 nic_mask = priv->sh->dv_meta_mask;
2257 if (!(action->conf))
2258 return rte_flow_error_set(error, EINVAL,
2259 RTE_FLOW_ERROR_TYPE_ACTION, action,
2260 "configuration cannot be null");
2261 conf = (const struct rte_flow_action_set_meta *)action->conf;
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ACTION, action,
2265 "zero mask doesn't have any effect");
2266 if (conf->mask & ~nic_mask)
2267 return rte_flow_error_set(error, EINVAL,
2268 RTE_FLOW_ERROR_TYPE_ACTION, action,
2269 "meta data must be within reg C0");
2274 * Validate SET_TAG action.
2277 * Pointer to the rte_eth_dev structure.
2279 * Pointer to the action structure.
2280 * @param[in] action_flags
2281 * Holds the actions detected until now.
2283 * Pointer to flow attributes
2285 * Pointer to error structure.
2288 * 0 on success, a negative errno value otherwise and rte_errno is set.
2291 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2292 const struct rte_flow_action *action,
2293 uint64_t action_flags,
2294 const struct rte_flow_attr *attr,
2295 struct rte_flow_error *error)
2297 const struct rte_flow_action_set_tag *conf;
2298 const uint64_t terminal_action_flags =
2299 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2300 MLX5_FLOW_ACTION_RSS;
2303 if (!mlx5_flow_ext_mreg_supported(dev))
2304 return rte_flow_error_set(error, ENOTSUP,
2305 RTE_FLOW_ERROR_TYPE_ACTION, action,
2306 "extensive metadata register"
2307 " isn't supported");
2308 if (!(action->conf))
2309 return rte_flow_error_set(error, EINVAL,
2310 RTE_FLOW_ERROR_TYPE_ACTION, action,
2311 "configuration cannot be null");
2312 conf = (const struct rte_flow_action_set_tag *)action->conf;
2314 return rte_flow_error_set(error, EINVAL,
2315 RTE_FLOW_ERROR_TYPE_ACTION, action,
2316 "zero mask doesn't have any effect");
2317 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2320 if (!attr->transfer && attr->ingress &&
2321 (action_flags & terminal_action_flags))
2322 return rte_flow_error_set(error, EINVAL,
2323 RTE_FLOW_ERROR_TYPE_ACTION, action,
2324 "set_tag has no effect"
2325 " with terminal actions");
2330 * Validate count action.
2333 * Pointer to rte_eth_dev structure.
2335 * Pointer to error structure.
2338 * 0 on success, a negative errno value otherwise and rte_errno is set.
2341 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2342 struct rte_flow_error *error)
2344 struct mlx5_priv *priv = dev->data->dev_private;
2346 if (!priv->config.devx)
2348 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2352 return rte_flow_error_set
2354 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2356 "count action not supported");
2360 * Validate the L2 encap action.
2363 * Pointer to the rte_eth_dev structure.
2364 * @param[in] action_flags
2365 * Holds the actions detected until now.
2367 * Pointer to the action structure.
2369 * Pointer to flow attributes.
2371 * Pointer to error structure.
2374 * 0 on success, a negative errno value otherwise and rte_errno is set.
2377 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2378 uint64_t action_flags,
2379 const struct rte_flow_action *action,
2380 const struct rte_flow_attr *attr,
2381 struct rte_flow_error *error)
2383 const struct mlx5_priv *priv = dev->data->dev_private;
2385 if (!(action->conf))
2386 return rte_flow_error_set(error, EINVAL,
2387 RTE_FLOW_ERROR_TYPE_ACTION, action,
2388 "configuration cannot be null");
2389 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2390 return rte_flow_error_set(error, EINVAL,
2391 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2392 "can only have a single encap action "
2394 if (!attr->transfer && priv->representor)
2395 return rte_flow_error_set(error, ENOTSUP,
2396 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2397 "encap action for VF representor "
2398 "not supported on NIC table");
2403 * Validate a decap action.
2406 * Pointer to the rte_eth_dev structure.
2407 * @param[in] action_flags
2408 * Holds the actions detected until now.
2410 * Pointer to flow attributes
2412 * Pointer to error structure.
2415 * 0 on success, a negative errno value otherwise and rte_errno is set.
2418 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2419 uint64_t action_flags,
2420 const struct rte_flow_attr *attr,
2421 struct rte_flow_error *error)
2423 const struct mlx5_priv *priv = dev->data->dev_private;
2425 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2426 return rte_flow_error_set(error, ENOTSUP,
2427 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2429 MLX5_FLOW_ACTION_DECAP ? "can only "
2430 "have a single decap action" : "decap "
2431 "after encap is not supported");
2432 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2433 return rte_flow_error_set(error, EINVAL,
2434 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2435 "can't have decap action after"
2438 return rte_flow_error_set(error, ENOTSUP,
2439 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2441 "decap action not supported for "
2443 if (!attr->transfer && priv->representor)
2444 return rte_flow_error_set(error, ENOTSUP,
2445 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2446 "decap action for VF representor "
2447 "not supported on NIC table");
2451 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2454 * Validate the raw encap and decap actions.
2457 * Pointer to the rte_eth_dev structure.
2459 * Pointer to the decap action.
2461 * Pointer to the encap action.
2463 * Pointer to flow attributes
2464 * @param[in/out] action_flags
2465 * Holds the actions detected until now.
2466 * @param[out] actions_n
2467 * pointer to the number of actions counter.
2469 * Pointer to error structure.
2472 * 0 on success, a negative errno value otherwise and rte_errno is set.
2475 flow_dv_validate_action_raw_encap_decap
2476 (struct rte_eth_dev *dev,
2477 const struct rte_flow_action_raw_decap *decap,
2478 const struct rte_flow_action_raw_encap *encap,
2479 const struct rte_flow_attr *attr, uint64_t *action_flags,
2480 int *actions_n, struct rte_flow_error *error)
2482 const struct mlx5_priv *priv = dev->data->dev_private;
2485 if (encap && (!encap->size || !encap->data))
2486 return rte_flow_error_set(error, EINVAL,
2487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2488 "raw encap data cannot be empty");
2489 if (decap && encap) {
2490 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2491 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2494 else if (encap->size <=
2495 MLX5_ENCAPSULATION_DECISION_SIZE &&
2497 MLX5_ENCAPSULATION_DECISION_SIZE)
2500 else if (encap->size >
2501 MLX5_ENCAPSULATION_DECISION_SIZE &&
2503 MLX5_ENCAPSULATION_DECISION_SIZE)
2504 /* 2 L2 actions: encap and decap. */
2507 return rte_flow_error_set(error,
2509 RTE_FLOW_ERROR_TYPE_ACTION,
2510 NULL, "unsupported too small "
2511 "raw decap and too small raw "
2512 "encap combination");
2515 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2519 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2523 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2524 return rte_flow_error_set(error, ENOTSUP,
2525 RTE_FLOW_ERROR_TYPE_ACTION,
2527 "small raw encap size");
2528 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2529 return rte_flow_error_set(error, EINVAL,
2530 RTE_FLOW_ERROR_TYPE_ACTION,
2532 "more than one encap action");
2533 if (!attr->transfer && priv->representor)
2534 return rte_flow_error_set
2536 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2537 "encap action for VF representor "
2538 "not supported on NIC table");
2539 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2546 * Find existing encap/decap resource or create and register a new one.
2548 * @param[in, out] dev
2549 * Pointer to rte_eth_dev structure.
2550 * @param[in, out] resource
2551 * Pointer to encap/decap resource.
2552 * @parm[in, out] dev_flow
2553 * Pointer to the dev_flow.
2555 * pointer to error structure.
2558 * 0 on success otherwise -errno and errno is set.
2561 flow_dv_encap_decap_resource_register
2562 (struct rte_eth_dev *dev,
2563 struct mlx5_flow_dv_encap_decap_resource *resource,
2564 struct mlx5_flow *dev_flow,
2565 struct rte_flow_error *error)
2567 struct mlx5_priv *priv = dev->data->dev_private;
2568 struct mlx5_dev_ctx_shared *sh = priv->sh;
2569 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2570 struct mlx5dv_dr_domain *domain;
2573 resource->flags = dev_flow->dv.group ? 0 : 1;
2574 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2575 domain = sh->fdb_domain;
2576 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2577 domain = sh->rx_domain;
2579 domain = sh->tx_domain;
2580 /* Lookup a matching resource from cache. */
2581 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2582 cache_resource, next) {
2583 if (resource->reformat_type == cache_resource->reformat_type &&
2584 resource->ft_type == cache_resource->ft_type &&
2585 resource->flags == cache_resource->flags &&
2586 resource->size == cache_resource->size &&
2587 !memcmp((const void *)resource->buf,
2588 (const void *)cache_resource->buf,
2590 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2591 (void *)cache_resource,
2592 rte_atomic32_read(&cache_resource->refcnt));
2593 rte_atomic32_inc(&cache_resource->refcnt);
2594 dev_flow->handle->dvh.rix_encap_decap = idx;
2595 dev_flow->dv.encap_decap = cache_resource;
2599 /* Register new encap/decap resource. */
2600 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2601 &dev_flow->handle->dvh.rix_encap_decap);
2602 if (!cache_resource)
2603 return rte_flow_error_set(error, ENOMEM,
2604 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2605 "cannot allocate resource memory");
2606 *cache_resource = *resource;
2607 cache_resource->action =
2608 mlx5_glue->dv_create_flow_action_packet_reformat
2609 (sh->ctx, cache_resource->reformat_type,
2610 cache_resource->ft_type, domain, cache_resource->flags,
2611 cache_resource->size,
2612 (cache_resource->size ? cache_resource->buf : NULL));
2613 if (!cache_resource->action) {
2614 rte_free(cache_resource);
2615 return rte_flow_error_set(error, ENOMEM,
2616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2617 NULL, "cannot create action");
2619 rte_atomic32_init(&cache_resource->refcnt);
2620 rte_atomic32_inc(&cache_resource->refcnt);
2621 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2622 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2624 dev_flow->dv.encap_decap = cache_resource;
2625 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2626 (void *)cache_resource,
2627 rte_atomic32_read(&cache_resource->refcnt));
2632 * Find existing table jump resource or create and register a new one.
2634 * @param[in, out] dev
2635 * Pointer to rte_eth_dev structure.
2636 * @param[in, out] tbl
2637 * Pointer to flow table resource.
2638 * @parm[in, out] dev_flow
2639 * Pointer to the dev_flow.
2641 * pointer to error structure.
2644 * 0 on success otherwise -errno and errno is set.
2647 flow_dv_jump_tbl_resource_register
2648 (struct rte_eth_dev *dev __rte_unused,
2649 struct mlx5_flow_tbl_resource *tbl,
2650 struct mlx5_flow *dev_flow,
2651 struct rte_flow_error *error)
2653 struct mlx5_flow_tbl_data_entry *tbl_data =
2654 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2658 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2660 tbl_data->jump.action =
2661 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2663 if (!tbl_data->jump.action)
2664 return rte_flow_error_set(error, ENOMEM,
2665 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2666 NULL, "cannot create jump action");
2667 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2668 (void *)&tbl_data->jump, cnt);
2670 /* old jump should not make the table ref++. */
2671 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2672 MLX5_ASSERT(tbl_data->jump.action);
2673 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2674 (void *)&tbl_data->jump, cnt);
2676 rte_atomic32_inc(&tbl_data->jump.refcnt);
2677 dev_flow->handle->rix_jump = tbl_data->idx;
2678 dev_flow->dv.jump = &tbl_data->jump;
2683 * Find existing default miss resource or create and register a new one.
2685 * @param[in, out] dev
2686 * Pointer to rte_eth_dev structure.
2688 * pointer to error structure.
2691 * 0 on success otherwise -errno and errno is set.
2694 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2695 struct rte_flow_error *error)
2697 struct mlx5_priv *priv = dev->data->dev_private;
2698 struct mlx5_dev_ctx_shared *sh = priv->sh;
2699 struct mlx5_flow_default_miss_resource *cache_resource =
2701 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2704 MLX5_ASSERT(cache_resource->action);
2705 cache_resource->action =
2706 mlx5_glue->dr_create_flow_action_default_miss();
2707 if (!cache_resource->action)
2708 return rte_flow_error_set(error, ENOMEM,
2709 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2710 "cannot create default miss action");
2711 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2712 (void *)cache_resource->action, cnt);
2714 rte_atomic32_inc(&cache_resource->refcnt);
2719 * Find existing table port ID resource or create and register a new one.
2721 * @param[in, out] dev
2722 * Pointer to rte_eth_dev structure.
2723 * @param[in, out] resource
2724 * Pointer to port ID action resource.
2725 * @parm[in, out] dev_flow
2726 * Pointer to the dev_flow.
2728 * pointer to error structure.
2731 * 0 on success otherwise -errno and errno is set.
2734 flow_dv_port_id_action_resource_register
2735 (struct rte_eth_dev *dev,
2736 struct mlx5_flow_dv_port_id_action_resource *resource,
2737 struct mlx5_flow *dev_flow,
2738 struct rte_flow_error *error)
2740 struct mlx5_priv *priv = dev->data->dev_private;
2741 struct mlx5_dev_ctx_shared *sh = priv->sh;
2742 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2745 /* Lookup a matching resource from cache. */
2746 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2747 idx, cache_resource, next) {
2748 if (resource->port_id == cache_resource->port_id) {
2749 DRV_LOG(DEBUG, "port id action resource resource %p: "
2751 (void *)cache_resource,
2752 rte_atomic32_read(&cache_resource->refcnt));
2753 rte_atomic32_inc(&cache_resource->refcnt);
2754 dev_flow->handle->rix_port_id_action = idx;
2755 dev_flow->dv.port_id_action = cache_resource;
2759 /* Register new port id action resource. */
2760 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2761 &dev_flow->handle->rix_port_id_action);
2762 if (!cache_resource)
2763 return rte_flow_error_set(error, ENOMEM,
2764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2765 "cannot allocate resource memory");
2766 *cache_resource = *resource;
2768 * Depending on rdma_core version the glue routine calls
2769 * either mlx5dv_dr_action_create_dest_ib_port(domain, dev_port)
2770 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2772 cache_resource->action =
2773 mlx5_glue->dr_create_flow_action_dest_port
2774 (priv->sh->fdb_domain, resource->port_id);
2775 if (!cache_resource->action) {
2776 rte_free(cache_resource);
2777 return rte_flow_error_set(error, ENOMEM,
2778 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2779 NULL, "cannot create action");
2781 rte_atomic32_init(&cache_resource->refcnt);
2782 rte_atomic32_inc(&cache_resource->refcnt);
2783 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2784 dev_flow->handle->rix_port_id_action, cache_resource,
2786 dev_flow->dv.port_id_action = cache_resource;
2787 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2788 (void *)cache_resource,
2789 rte_atomic32_read(&cache_resource->refcnt));
2794 * Find existing push vlan resource or create and register a new one.
2796 * @param [in, out] dev
2797 * Pointer to rte_eth_dev structure.
2798 * @param[in, out] resource
2799 * Pointer to port ID action resource.
2800 * @parm[in, out] dev_flow
2801 * Pointer to the dev_flow.
2803 * pointer to error structure.
2806 * 0 on success otherwise -errno and errno is set.
2809 flow_dv_push_vlan_action_resource_register
2810 (struct rte_eth_dev *dev,
2811 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2812 struct mlx5_flow *dev_flow,
2813 struct rte_flow_error *error)
2815 struct mlx5_priv *priv = dev->data->dev_private;
2816 struct mlx5_dev_ctx_shared *sh = priv->sh;
2817 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2818 struct mlx5dv_dr_domain *domain;
2821 /* Lookup a matching resource from cache. */
2822 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2823 sh->push_vlan_action_list, idx, cache_resource, next) {
2824 if (resource->vlan_tag == cache_resource->vlan_tag &&
2825 resource->ft_type == cache_resource->ft_type) {
2826 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2828 (void *)cache_resource,
2829 rte_atomic32_read(&cache_resource->refcnt));
2830 rte_atomic32_inc(&cache_resource->refcnt);
2831 dev_flow->handle->dvh.rix_push_vlan = idx;
2832 dev_flow->dv.push_vlan_res = cache_resource;
2836 /* Register new push_vlan action resource. */
2837 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2838 &dev_flow->handle->dvh.rix_push_vlan);
2839 if (!cache_resource)
2840 return rte_flow_error_set(error, ENOMEM,
2841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2842 "cannot allocate resource memory");
2843 *cache_resource = *resource;
2844 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2845 domain = sh->fdb_domain;
2846 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2847 domain = sh->rx_domain;
2849 domain = sh->tx_domain;
2850 cache_resource->action =
2851 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2852 resource->vlan_tag);
2853 if (!cache_resource->action) {
2854 rte_free(cache_resource);
2855 return rte_flow_error_set(error, ENOMEM,
2856 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2857 NULL, "cannot create action");
2859 rte_atomic32_init(&cache_resource->refcnt);
2860 rte_atomic32_inc(&cache_resource->refcnt);
2861 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2862 &sh->push_vlan_action_list,
2863 dev_flow->handle->dvh.rix_push_vlan,
2864 cache_resource, next);
2865 dev_flow->dv.push_vlan_res = cache_resource;
2866 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2867 (void *)cache_resource,
2868 rte_atomic32_read(&cache_resource->refcnt));
2872 * Get the size of specific rte_flow_item_type
2874 * @param[in] item_type
2875 * Tested rte_flow_item_type.
2878 * sizeof struct item_type, 0 if void or irrelevant.
2881 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2885 switch (item_type) {
2886 case RTE_FLOW_ITEM_TYPE_ETH:
2887 retval = sizeof(struct rte_flow_item_eth);
2889 case RTE_FLOW_ITEM_TYPE_VLAN:
2890 retval = sizeof(struct rte_flow_item_vlan);
2892 case RTE_FLOW_ITEM_TYPE_IPV4:
2893 retval = sizeof(struct rte_flow_item_ipv4);
2895 case RTE_FLOW_ITEM_TYPE_IPV6:
2896 retval = sizeof(struct rte_flow_item_ipv6);
2898 case RTE_FLOW_ITEM_TYPE_UDP:
2899 retval = sizeof(struct rte_flow_item_udp);
2901 case RTE_FLOW_ITEM_TYPE_TCP:
2902 retval = sizeof(struct rte_flow_item_tcp);
2904 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905 retval = sizeof(struct rte_flow_item_vxlan);
2907 case RTE_FLOW_ITEM_TYPE_GRE:
2908 retval = sizeof(struct rte_flow_item_gre);
2910 case RTE_FLOW_ITEM_TYPE_NVGRE:
2911 retval = sizeof(struct rte_flow_item_nvgre);
2913 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2914 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2916 case RTE_FLOW_ITEM_TYPE_MPLS:
2917 retval = sizeof(struct rte_flow_item_mpls);
2919 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2927 #define MLX5_ENCAP_IPV4_VERSION 0x40
2928 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2929 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2930 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2931 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2932 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2933 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2936 * Convert the encap action data from list of rte_flow_item to raw buffer
2939 * Pointer to rte_flow_item objects list.
2941 * Pointer to the output buffer.
2943 * Pointer to the output buffer size.
2945 * Pointer to the error structure.
2948 * 0 on success, a negative errno value otherwise and rte_errno is set.
2951 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2952 size_t *size, struct rte_flow_error *error)
2954 struct rte_ether_hdr *eth = NULL;
2955 struct rte_vlan_hdr *vlan = NULL;
2956 struct rte_ipv4_hdr *ipv4 = NULL;
2957 struct rte_ipv6_hdr *ipv6 = NULL;
2958 struct rte_udp_hdr *udp = NULL;
2959 struct rte_vxlan_hdr *vxlan = NULL;
2960 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2961 struct rte_gre_hdr *gre = NULL;
2963 size_t temp_size = 0;
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 NULL, "invalid empty data");
2969 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2970 len = flow_dv_get_item_len(items->type);
2971 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2972 return rte_flow_error_set(error, EINVAL,
2973 RTE_FLOW_ERROR_TYPE_ACTION,
2974 (void *)items->type,
2975 "items total size is too big"
2976 " for encap action");
2977 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2978 switch (items->type) {
2979 case RTE_FLOW_ITEM_TYPE_ETH:
2980 eth = (struct rte_ether_hdr *)&buf[temp_size];
2982 case RTE_FLOW_ITEM_TYPE_VLAN:
2983 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2985 return rte_flow_error_set(error, EINVAL,
2986 RTE_FLOW_ERROR_TYPE_ACTION,
2987 (void *)items->type,
2988 "eth header not found");
2989 if (!eth->ether_type)
2990 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2992 case RTE_FLOW_ITEM_TYPE_IPV4:
2993 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2995 return rte_flow_error_set(error, EINVAL,
2996 RTE_FLOW_ERROR_TYPE_ACTION,
2997 (void *)items->type,
2998 "neither eth nor vlan"
3000 if (vlan && !vlan->eth_proto)
3001 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3002 else if (eth && !eth->ether_type)
3003 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3004 if (!ipv4->version_ihl)
3005 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3006 MLX5_ENCAP_IPV4_IHL_MIN;
3007 if (!ipv4->time_to_live)
3008 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3010 case RTE_FLOW_ITEM_TYPE_IPV6:
3011 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3013 return rte_flow_error_set(error, EINVAL,
3014 RTE_FLOW_ERROR_TYPE_ACTION,
3015 (void *)items->type,
3016 "neither eth nor vlan"
3018 if (vlan && !vlan->eth_proto)
3019 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3020 else if (eth && !eth->ether_type)
3021 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3022 if (!ipv6->vtc_flow)
3024 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3025 if (!ipv6->hop_limits)
3026 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3028 case RTE_FLOW_ITEM_TYPE_UDP:
3029 udp = (struct rte_udp_hdr *)&buf[temp_size];
3031 return rte_flow_error_set(error, EINVAL,
3032 RTE_FLOW_ERROR_TYPE_ACTION,
3033 (void *)items->type,
3034 "ip header not found");
3035 if (ipv4 && !ipv4->next_proto_id)
3036 ipv4->next_proto_id = IPPROTO_UDP;
3037 else if (ipv6 && !ipv6->proto)
3038 ipv6->proto = IPPROTO_UDP;
3040 case RTE_FLOW_ITEM_TYPE_VXLAN:
3041 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3043 return rte_flow_error_set(error, EINVAL,
3044 RTE_FLOW_ERROR_TYPE_ACTION,
3045 (void *)items->type,
3046 "udp header not found");
3048 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3049 if (!vxlan->vx_flags)
3051 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3053 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3054 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3056 return rte_flow_error_set(error, EINVAL,
3057 RTE_FLOW_ERROR_TYPE_ACTION,
3058 (void *)items->type,
3059 "udp header not found");
3060 if (!vxlan_gpe->proto)
3061 return rte_flow_error_set(error, EINVAL,
3062 RTE_FLOW_ERROR_TYPE_ACTION,
3063 (void *)items->type,
3064 "next protocol not found");
3067 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3068 if (!vxlan_gpe->vx_flags)
3069 vxlan_gpe->vx_flags =
3070 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3072 case RTE_FLOW_ITEM_TYPE_GRE:
3073 case RTE_FLOW_ITEM_TYPE_NVGRE:
3074 gre = (struct rte_gre_hdr *)&buf[temp_size];
3076 return rte_flow_error_set(error, EINVAL,
3077 RTE_FLOW_ERROR_TYPE_ACTION,
3078 (void *)items->type,
3079 "next protocol not found");
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION,
3083 (void *)items->type,
3084 "ip header not found");
3085 if (ipv4 && !ipv4->next_proto_id)
3086 ipv4->next_proto_id = IPPROTO_GRE;
3087 else if (ipv6 && !ipv6->proto)
3088 ipv6->proto = IPPROTO_GRE;
3090 case RTE_FLOW_ITEM_TYPE_VOID:
3093 return rte_flow_error_set(error, EINVAL,
3094 RTE_FLOW_ERROR_TYPE_ACTION,
3095 (void *)items->type,
3096 "unsupported item type");
3106 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3108 struct rte_ether_hdr *eth = NULL;
3109 struct rte_vlan_hdr *vlan = NULL;
3110 struct rte_ipv6_hdr *ipv6 = NULL;
3111 struct rte_udp_hdr *udp = NULL;
3115 eth = (struct rte_ether_hdr *)data;
3116 next_hdr = (char *)(eth + 1);
3117 proto = RTE_BE16(eth->ether_type);
3120 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3121 vlan = (struct rte_vlan_hdr *)next_hdr;
3122 proto = RTE_BE16(vlan->eth_proto);
3123 next_hdr += sizeof(struct rte_vlan_hdr);
3126 /* HW calculates IPv4 csum. no need to proceed */
3127 if (proto == RTE_ETHER_TYPE_IPV4)
3130 /* non IPv4/IPv6 header. not supported */
3131 if (proto != RTE_ETHER_TYPE_IPV6) {
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION,
3134 NULL, "Cannot offload non IPv4/IPv6");
3137 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3139 /* ignore non UDP */
3140 if (ipv6->proto != IPPROTO_UDP)
3143 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3144 udp->dgram_cksum = 0;
3150 * Convert L2 encap action to DV specification.
3153 * Pointer to rte_eth_dev structure.
3155 * Pointer to action structure.
3156 * @param[in, out] dev_flow
3157 * Pointer to the mlx5_flow.
3158 * @param[in] transfer
3159 * Mark if the flow is E-Switch flow.
3161 * Pointer to the error structure.
3164 * 0 on success, a negative errno value otherwise and rte_errno is set.
3167 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3168 const struct rte_flow_action *action,
3169 struct mlx5_flow *dev_flow,
3171 struct rte_flow_error *error)
3173 const struct rte_flow_item *encap_data;
3174 const struct rte_flow_action_raw_encap *raw_encap_data;
3175 struct mlx5_flow_dv_encap_decap_resource res = {
3177 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3178 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3179 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3182 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3184 (const struct rte_flow_action_raw_encap *)action->conf;
3185 res.size = raw_encap_data->size;
3186 memcpy(res.buf, raw_encap_data->data, res.size);
3188 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3190 ((const struct rte_flow_action_vxlan_encap *)
3191 action->conf)->definition;
3194 ((const struct rte_flow_action_nvgre_encap *)
3195 action->conf)->definition;
3196 if (flow_dv_convert_encap_data(encap_data, res.buf,
3200 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3202 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3203 return rte_flow_error_set(error, EINVAL,
3204 RTE_FLOW_ERROR_TYPE_ACTION,
3205 NULL, "can't create L2 encap action");
3210 * Convert L2 decap action to DV specification.
3213 * Pointer to rte_eth_dev structure.
3214 * @param[in, out] dev_flow
3215 * Pointer to the mlx5_flow.
3216 * @param[in] transfer
3217 * Mark if the flow is E-Switch flow.
3219 * Pointer to the error structure.
3222 * 0 on success, a negative errno value otherwise and rte_errno is set.
3225 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3226 struct mlx5_flow *dev_flow,
3228 struct rte_flow_error *error)
3230 struct mlx5_flow_dv_encap_decap_resource res = {
3233 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3234 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3235 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3238 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3239 return rte_flow_error_set(error, EINVAL,
3240 RTE_FLOW_ERROR_TYPE_ACTION,
3241 NULL, "can't create L2 decap action");
3246 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3249 * Pointer to rte_eth_dev structure.
3251 * Pointer to action structure.
3252 * @param[in, out] dev_flow
3253 * Pointer to the mlx5_flow.
3255 * Pointer to the flow attributes.
3257 * Pointer to the error structure.
3260 * 0 on success, a negative errno value otherwise and rte_errno is set.
3263 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3264 const struct rte_flow_action *action,
3265 struct mlx5_flow *dev_flow,
3266 const struct rte_flow_attr *attr,
3267 struct rte_flow_error *error)
3269 const struct rte_flow_action_raw_encap *encap_data;
3270 struct mlx5_flow_dv_encap_decap_resource res;
3272 memset(&res, 0, sizeof(res));
3273 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3274 res.size = encap_data->size;
3275 memcpy(res.buf, encap_data->data, res.size);
3276 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3277 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3278 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3280 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3283 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3284 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3285 return rte_flow_error_set(error, EINVAL,
3286 RTE_FLOW_ERROR_TYPE_ACTION,
3287 NULL, "can't create encap action");
3292 * Create action push VLAN.
3295 * Pointer to rte_eth_dev structure.
3297 * Pointer to the flow attributes.
3299 * Pointer to the vlan to push to the Ethernet header.
3300 * @param[in, out] dev_flow
3301 * Pointer to the mlx5_flow.
3303 * Pointer to the error structure.
3306 * 0 on success, a negative errno value otherwise and rte_errno is set.
3309 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3310 const struct rte_flow_attr *attr,
3311 const struct rte_vlan_hdr *vlan,
3312 struct mlx5_flow *dev_flow,
3313 struct rte_flow_error *error)
3315 struct mlx5_flow_dv_push_vlan_action_resource res;
3317 memset(&res, 0, sizeof(res));
3319 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3322 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3324 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3325 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3326 return flow_dv_push_vlan_action_resource_register
3327 (dev, &res, dev_flow, error);
3331 * Validate the modify-header actions.
3333 * @param[in] action_flags
3334 * Holds the actions detected until now.
3336 * Pointer to the modify action.
3338 * Pointer to error structure.
3341 * 0 on success, a negative errno value otherwise and rte_errno is set.
3344 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3345 const struct rte_flow_action *action,
3346 struct rte_flow_error *error)
3348 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3349 return rte_flow_error_set(error, EINVAL,
3350 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3351 NULL, "action configuration not set");
3352 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3353 return rte_flow_error_set(error, EINVAL,
3354 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3355 "can't have encap action before"
3361 * Validate the modify-header MAC address actions.
3363 * @param[in] action_flags
3364 * Holds the actions detected until now.
3366 * Pointer to the modify action.
3367 * @param[in] item_flags
3368 * Holds the items detected.
3370 * Pointer to error structure.
3373 * 0 on success, a negative errno value otherwise and rte_errno is set.
3376 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3377 const struct rte_flow_action *action,
3378 const uint64_t item_flags,
3379 struct rte_flow_error *error)
3383 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3385 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3386 return rte_flow_error_set(error, EINVAL,
3387 RTE_FLOW_ERROR_TYPE_ACTION,
3389 "no L2 item in pattern");
3395 * Validate the modify-header IPv4 address actions.
3397 * @param[in] action_flags
3398 * Holds the actions detected until now.
3400 * Pointer to the modify action.
3401 * @param[in] item_flags
3402 * Holds the items detected.
3404 * Pointer to error structure.
3407 * 0 on success, a negative errno value otherwise and rte_errno is set.
3410 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3411 const struct rte_flow_action *action,
3412 const uint64_t item_flags,
3413 struct rte_flow_error *error)
3418 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3420 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3421 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3422 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3423 if (!(item_flags & layer))
3424 return rte_flow_error_set(error, EINVAL,
3425 RTE_FLOW_ERROR_TYPE_ACTION,
3427 "no ipv4 item in pattern");
3433 * Validate the modify-header IPv6 address actions.
3435 * @param[in] action_flags
3436 * Holds the actions detected until now.
3438 * Pointer to the modify action.
3439 * @param[in] item_flags
3440 * Holds the items detected.
3442 * Pointer to error structure.
3445 * 0 on success, a negative errno value otherwise and rte_errno is set.
3448 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3449 const struct rte_flow_action *action,
3450 const uint64_t item_flags,
3451 struct rte_flow_error *error)
3456 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3458 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3459 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3460 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3461 if (!(item_flags & layer))
3462 return rte_flow_error_set(error, EINVAL,
3463 RTE_FLOW_ERROR_TYPE_ACTION,
3465 "no ipv6 item in pattern");
3471 * Validate the modify-header TP actions.
3473 * @param[in] action_flags
3474 * Holds the actions detected until now.
3476 * Pointer to the modify action.
3477 * @param[in] item_flags
3478 * Holds the items detected.
3480 * Pointer to error structure.
3483 * 0 on success, a negative errno value otherwise and rte_errno is set.
3486 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3487 const struct rte_flow_action *action,
3488 const uint64_t item_flags,
3489 struct rte_flow_error *error)
3494 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3496 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497 MLX5_FLOW_LAYER_INNER_L4 :
3498 MLX5_FLOW_LAYER_OUTER_L4;
3499 if (!(item_flags & layer))
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "no transport layer "
3509 * Validate the modify-header actions of increment/decrement
3510 * TCP Sequence-number.
3512 * @param[in] action_flags
3513 * Holds the actions detected until now.
3515 * Pointer to the modify action.
3516 * @param[in] item_flags
3517 * Holds the items detected.
3519 * Pointer to error structure.
3522 * 0 on success, a negative errno value otherwise and rte_errno is set.
3525 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3526 const struct rte_flow_action *action,
3527 const uint64_t item_flags,
3528 struct rte_flow_error *error)
3533 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3535 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3536 MLX5_FLOW_LAYER_INNER_L4_TCP :
3537 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3538 if (!(item_flags & layer))
3539 return rte_flow_error_set(error, EINVAL,
3540 RTE_FLOW_ERROR_TYPE_ACTION,
3541 NULL, "no TCP item in"
3543 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3544 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3545 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3546 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3547 return rte_flow_error_set(error, EINVAL,
3548 RTE_FLOW_ERROR_TYPE_ACTION,
3550 "cannot decrease and increase"
3551 " TCP sequence number"
3552 " at the same time");
3558 * Validate the modify-header actions of increment/decrement
3559 * TCP Acknowledgment number.
3561 * @param[in] action_flags
3562 * Holds the actions detected until now.
3564 * Pointer to the modify action.
3565 * @param[in] item_flags
3566 * Holds the items detected.
3568 * Pointer to error structure.
3571 * 0 on success, a negative errno value otherwise and rte_errno is set.
3574 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3575 const struct rte_flow_action *action,
3576 const uint64_t item_flags,
3577 struct rte_flow_error *error)
3582 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3584 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3585 MLX5_FLOW_LAYER_INNER_L4_TCP :
3586 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3587 if (!(item_flags & layer))
3588 return rte_flow_error_set(error, EINVAL,
3589 RTE_FLOW_ERROR_TYPE_ACTION,
3590 NULL, "no TCP item in"
3592 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3593 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3594 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3595 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3596 return rte_flow_error_set(error, EINVAL,
3597 RTE_FLOW_ERROR_TYPE_ACTION,
3599 "cannot decrease and increase"
3600 " TCP acknowledgment number"
3601 " at the same time");
3607 * Validate the modify-header TTL actions.
3609 * @param[in] action_flags
3610 * Holds the actions detected until now.
3612 * Pointer to the modify action.
3613 * @param[in] item_flags
3614 * Holds the items detected.
3616 * Pointer to error structure.
3619 * 0 on success, a negative errno value otherwise and rte_errno is set.
3622 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3623 const struct rte_flow_action *action,
3624 const uint64_t item_flags,
3625 struct rte_flow_error *error)
3630 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3632 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3633 MLX5_FLOW_LAYER_INNER_L3 :
3634 MLX5_FLOW_LAYER_OUTER_L3;
3635 if (!(item_flags & layer))
3636 return rte_flow_error_set(error, EINVAL,
3637 RTE_FLOW_ERROR_TYPE_ACTION,
3639 "no IP protocol in pattern");
3645 * Validate jump action.
3648 * Pointer to the jump action.
3649 * @param[in] action_flags
3650 * Holds the actions detected until now.
3651 * @param[in] attributes
3652 * Pointer to flow attributes
3653 * @param[in] external
3654 * Action belongs to flow rule created by request external to PMD.
3656 * Pointer to error structure.
3659 * 0 on success, a negative errno value otherwise and rte_errno is set.
3662 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3663 uint64_t action_flags,
3664 const struct rte_flow_attr *attributes,
3665 bool external, struct rte_flow_error *error)
3667 uint32_t target_group, table;
3670 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3671 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3672 return rte_flow_error_set(error, EINVAL,
3673 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3674 "can't have 2 fate actions in"
3676 if (action_flags & MLX5_FLOW_ACTION_METER)
3677 return rte_flow_error_set(error, ENOTSUP,
3678 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3679 "jump with meter not support");
3681 return rte_flow_error_set(error, EINVAL,
3682 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3683 NULL, "action configuration not set");
3685 ((const struct rte_flow_action_jump *)action->conf)->group;
3686 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3687 true, &table, error);
3690 if (attributes->group == target_group)
3691 return rte_flow_error_set(error, EINVAL,
3692 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693 "target group must be other than"
3694 " the current flow group");
3699 * Validate the port_id action.
3702 * Pointer to rte_eth_dev structure.
3703 * @param[in] action_flags
3704 * Bit-fields that holds the actions detected until now.
3706 * Port_id RTE action structure.
3708 * Attributes of flow that includes this action.
3710 * Pointer to error structure.
3713 * 0 on success, a negative errno value otherwise and rte_errno is set.
3716 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3717 uint64_t action_flags,
3718 const struct rte_flow_action *action,
3719 const struct rte_flow_attr *attr,
3720 struct rte_flow_error *error)
3722 const struct rte_flow_action_port_id *port_id;
3723 struct mlx5_priv *act_priv;
3724 struct mlx5_priv *dev_priv;
3727 if (!attr->transfer)
3728 return rte_flow_error_set(error, ENOTSUP,
3729 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3731 "port id action is valid in transfer"
3733 if (!action || !action->conf)
3734 return rte_flow_error_set(error, ENOTSUP,
3735 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3737 "port id action parameters must be"
3739 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3740 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3741 return rte_flow_error_set(error, EINVAL,
3742 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3743 "can have only one fate actions in"
3745 dev_priv = mlx5_dev_to_eswitch_info(dev);
3747 return rte_flow_error_set(error, rte_errno,
3748 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3750 "failed to obtain E-Switch info");
3751 port_id = action->conf;
3752 port = port_id->original ? dev->data->port_id : port_id->id;
3753 act_priv = mlx5_port_to_eswitch_info(port, false);
3755 return rte_flow_error_set
3757 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3758 "failed to obtain E-Switch port id for port");
3759 if (act_priv->domain_id != dev_priv->domain_id)
3760 return rte_flow_error_set
3762 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3763 "port does not belong to"
3764 " E-Switch being configured");
3769 * Get the maximum number of modify header actions.
3772 * Pointer to rte_eth_dev structure.
3774 * Flags bits to check if root level.
3777 * Max number of modify header actions device can support.
3779 static inline unsigned int
3780 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3784 * There's no way to directly query the max capacity from FW.
3785 * The maximal value on root table should be assumed to be supported.
3787 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3788 return MLX5_MAX_MODIFY_NUM;
3790 return MLX5_ROOT_TBL_MODIFY_NUM;
3794 * Validate the meter action.
3797 * Pointer to rte_eth_dev structure.
3798 * @param[in] action_flags
3799 * Bit-fields that holds the actions detected until now.
3801 * Pointer to the meter action.
3803 * Attributes of flow that includes this action.
3805 * Pointer to error structure.
3808 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3811 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3812 uint64_t action_flags,
3813 const struct rte_flow_action *action,
3814 const struct rte_flow_attr *attr,
3815 struct rte_flow_error *error)
3817 struct mlx5_priv *priv = dev->data->dev_private;
3818 const struct rte_flow_action_meter *am = action->conf;
3819 struct mlx5_flow_meter *fm;
3822 return rte_flow_error_set(error, EINVAL,
3823 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3824 "meter action conf is NULL");
3826 if (action_flags & MLX5_FLOW_ACTION_METER)
3827 return rte_flow_error_set(error, ENOTSUP,
3828 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3829 "meter chaining not support");
3830 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3831 return rte_flow_error_set(error, ENOTSUP,
3832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3833 "meter with jump not support");
3835 return rte_flow_error_set(error, ENOTSUP,
3836 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3838 "meter action not supported");
3839 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3844 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3845 (!fm->ingress && !attr->ingress && attr->egress) ||
3846 (!fm->egress && !attr->egress && attr->ingress))))
3847 return rte_flow_error_set(error, EINVAL,
3848 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3849 "Flow attributes are either invalid "
3850 "or have a conflict with current "
3851 "meter attributes");
3856 * Validate the age action.
3858 * @param[in] action_flags
3859 * Holds the actions detected until now.
3861 * Pointer to the age action.
3863 * Pointer to the Ethernet device structure.
3865 * Pointer to error structure.
3868 * 0 on success, a negative errno value otherwise and rte_errno is set.
3871 flow_dv_validate_action_age(uint64_t action_flags,
3872 const struct rte_flow_action *action,
3873 struct rte_eth_dev *dev,
3874 struct rte_flow_error *error)
3876 struct mlx5_priv *priv = dev->data->dev_private;
3877 const struct rte_flow_action_age *age = action->conf;
3879 if (!priv->config.devx || priv->counter_fallback)
3880 return rte_flow_error_set(error, ENOTSUP,
3881 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3883 "age action not supported");
3884 if (!(action->conf))
3885 return rte_flow_error_set(error, EINVAL,
3886 RTE_FLOW_ERROR_TYPE_ACTION, action,
3887 "configuration cannot be null");
3888 if (age->timeout >= UINT16_MAX / 2 / 10)
3889 return rte_flow_error_set(error, ENOTSUP,
3890 RTE_FLOW_ERROR_TYPE_ACTION, action,
3891 "Max age time: 3275 seconds");
3892 if (action_flags & MLX5_FLOW_ACTION_AGE)
3893 return rte_flow_error_set(error, EINVAL,
3894 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3895 "Duplicate age ctions set");
3900 * Validate the modify-header IPv4 DSCP actions.
3902 * @param[in] action_flags
3903 * Holds the actions detected until now.
3905 * Pointer to the modify action.
3906 * @param[in] item_flags
3907 * Holds the items detected.
3909 * Pointer to error structure.
3912 * 0 on success, a negative errno value otherwise and rte_errno is set.
3915 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3916 const struct rte_flow_action *action,
3917 const uint64_t item_flags,
3918 struct rte_flow_error *error)
3922 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3924 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3925 return rte_flow_error_set(error, EINVAL,
3926 RTE_FLOW_ERROR_TYPE_ACTION,
3928 "no ipv4 item in pattern");
3934 * Validate the modify-header IPv6 DSCP actions.
3936 * @param[in] action_flags
3937 * Holds the actions detected until now.
3939 * Pointer to the modify action.
3940 * @param[in] item_flags
3941 * Holds the items detected.
3943 * Pointer to error structure.
3946 * 0 on success, a negative errno value otherwise and rte_errno is set.
3949 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3950 const struct rte_flow_action *action,
3951 const uint64_t item_flags,
3952 struct rte_flow_error *error)
3956 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3958 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3959 return rte_flow_error_set(error, EINVAL,
3960 RTE_FLOW_ERROR_TYPE_ACTION,
3962 "no ipv6 item in pattern");
3968 * Find existing modify-header resource or create and register a new one.
3970 * @param dev[in, out]
3971 * Pointer to rte_eth_dev structure.
3972 * @param[in, out] resource
3973 * Pointer to modify-header resource.
3974 * @parm[in, out] dev_flow
3975 * Pointer to the dev_flow.
3977 * pointer to error structure.
3980 * 0 on success otherwise -errno and errno is set.
3983 flow_dv_modify_hdr_resource_register
3984 (struct rte_eth_dev *dev,
3985 struct mlx5_flow_dv_modify_hdr_resource *resource,
3986 struct mlx5_flow *dev_flow,
3987 struct rte_flow_error *error)
3989 struct mlx5_priv *priv = dev->data->dev_private;
3990 struct mlx5_dev_ctx_shared *sh = priv->sh;
3991 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3992 struct mlx5dv_dr_domain *ns;
3993 uint32_t actions_len;
3995 resource->flags = dev_flow->dv.group ? 0 :
3996 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3997 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3999 return rte_flow_error_set(error, EOVERFLOW,
4000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4001 "too many modify header items");
4002 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4003 ns = sh->fdb_domain;
4004 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4008 /* Lookup a matching resource from cache. */
4009 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4010 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4011 if (resource->ft_type == cache_resource->ft_type &&
4012 resource->actions_num == cache_resource->actions_num &&
4013 resource->flags == cache_resource->flags &&
4014 !memcmp((const void *)resource->actions,
4015 (const void *)cache_resource->actions,
4017 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4018 (void *)cache_resource,
4019 rte_atomic32_read(&cache_resource->refcnt));
4020 rte_atomic32_inc(&cache_resource->refcnt);
4021 dev_flow->handle->dvh.modify_hdr = cache_resource;
4025 /* Register new modify-header resource. */
4026 cache_resource = rte_calloc(__func__, 1,
4027 sizeof(*cache_resource) + actions_len, 0);
4028 if (!cache_resource)
4029 return rte_flow_error_set(error, ENOMEM,
4030 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4031 "cannot allocate resource memory");
4032 *cache_resource = *resource;
4033 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4034 cache_resource->action =
4035 mlx5_glue->dv_create_flow_action_modify_header
4036 (sh->ctx, cache_resource->ft_type, ns,
4037 cache_resource->flags, actions_len,
4038 (uint64_t *)cache_resource->actions);
4039 if (!cache_resource->action) {
4040 rte_free(cache_resource);
4041 return rte_flow_error_set(error, ENOMEM,
4042 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4043 NULL, "cannot create action");
4045 rte_atomic32_init(&cache_resource->refcnt);
4046 rte_atomic32_inc(&cache_resource->refcnt);
4047 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4048 dev_flow->handle->dvh.modify_hdr = cache_resource;
4049 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4050 (void *)cache_resource,
4051 rte_atomic32_read(&cache_resource->refcnt));
4056 * Get DV flow counter by index.
4059 * Pointer to the Ethernet device structure.
4061 * mlx5 flow counter index in the container.
4063 * mlx5 flow counter pool in the container,
4066 * Pointer to the counter, NULL otherwise.
4068 static struct mlx5_flow_counter *
4069 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4071 struct mlx5_flow_counter_pool **ppool)
4073 struct mlx5_priv *priv = dev->data->dev_private;
4074 struct mlx5_pools_container *cont;
4075 struct mlx5_flow_counter_pool *pool;
4076 uint32_t batch = 0, age = 0;
4079 age = MLX_CNT_IS_AGE(idx);
4080 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4081 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4082 idx -= MLX5_CNT_BATCH_OFFSET;
4085 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4086 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4087 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4091 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4095 * Check the devx counter belongs to the pool.
4098 * Pointer to the counter pool.
4100 * The counter devx ID.
4103 * True if counter belongs to the pool, false otherwise.
4106 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4108 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4109 MLX5_COUNTERS_PER_POOL;
4111 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4117 * Get a pool by devx counter ID.
4120 * Pointer to the counter container.
4122 * The counter devx ID.
4125 * The counter pool pointer if exists, NULL otherwise,
4127 static struct mlx5_flow_counter_pool *
4128 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4132 /* Check last used pool. */
4133 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4134 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4135 return cont->pools[cont->last_pool_idx];
4136 /* ID out of range means no suitable pool in the container. */
4137 if (id > cont->max_id || id < cont->min_id)
4140 * Find the pool from the end of the container, since mostly counter
4141 * ID is sequence increasing, and the last pool should be the needed
4144 i = rte_atomic16_read(&cont->n_valid);
4146 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4148 if (flow_dv_is_counter_in_pool(pool, id))
4155 * Allocate a new memory for the counter values wrapped by all the needed
4159 * Pointer to the Ethernet device structure.
4161 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4164 * The new memory management pointer on success, otherwise NULL and rte_errno
4167 static struct mlx5_counter_stats_mem_mng *
4168 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4170 struct mlx5_priv *priv = dev->data->dev_private;
4171 struct mlx5_dev_ctx_shared *sh = priv->sh;
4172 struct mlx5_devx_mkey_attr mkey_attr;
4173 struct mlx5_counter_stats_mem_mng *mem_mng;
4174 volatile struct flow_counter_stats *raw_data;
4175 int size = (sizeof(struct flow_counter_stats) *
4176 MLX5_COUNTERS_PER_POOL +
4177 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4178 sizeof(struct mlx5_counter_stats_mem_mng);
4179 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4186 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4187 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4188 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4189 IBV_ACCESS_LOCAL_WRITE);
4190 if (!mem_mng->umem) {
4195 mkey_attr.addr = (uintptr_t)mem;
4196 mkey_attr.size = size;
4197 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4198 mkey_attr.pd = sh->pdn;
4199 mkey_attr.log_entity_size = 0;
4200 mkey_attr.pg_access = 0;
4201 mkey_attr.klm_array = NULL;
4202 mkey_attr.klm_num = 0;
4203 if (priv->config.hca_attr.relaxed_ordering_write &&
4204 priv->config.hca_attr.relaxed_ordering_read &&
4205 !haswell_broadwell_cpu)
4206 mkey_attr.relaxed_ordering = 1;
4207 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4209 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4214 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4215 raw_data = (volatile struct flow_counter_stats *)mem;
4216 for (i = 0; i < raws_n; ++i) {
4217 mem_mng->raws[i].mem_mng = mem_mng;
4218 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4220 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4225 * Resize a counter container.
4228 * Pointer to the Ethernet device structure.
4230 * Whether the pool is for counter that was allocated by batch command.
4232 * Whether the pool is for Aging counter.
4235 * 0 on success, otherwise negative errno value and rte_errno is set.
4238 flow_dv_container_resize(struct rte_eth_dev *dev,
4239 uint32_t batch, uint32_t age)
4241 struct mlx5_priv *priv = dev->data->dev_private;
4242 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4244 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4245 void *old_pools = cont->pools;
4246 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4247 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4248 void *pools = rte_calloc(__func__, 1, mem_size, 0);
4255 memcpy(pools, old_pools, cont->n *
4256 sizeof(struct mlx5_flow_counter_pool *));
4258 * Fallback mode query the counter directly, no background query
4259 * resources are needed.
4261 if (!priv->counter_fallback) {
4264 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4265 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4270 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4271 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4273 MLX5_CNT_CONTAINER_RESIZE +
4276 rte_spinlock_lock(&cont->resize_sl);
4278 cont->mem_mng = mem_mng;
4279 cont->pools = pools;
4280 rte_spinlock_unlock(&cont->resize_sl);
4282 rte_free(old_pools);
4287 * Query a devx flow counter.
4290 * Pointer to the Ethernet device structure.
4292 * Index to the flow counter.
4294 * The statistics value of packets.
4296 * The statistics value of bytes.
4299 * 0 on success, otherwise a negative errno value and rte_errno is set.
4302 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4305 struct mlx5_priv *priv = dev->data->dev_private;
4306 struct mlx5_flow_counter_pool *pool = NULL;
4307 struct mlx5_flow_counter *cnt;
4308 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4311 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4313 if (counter < MLX5_CNT_BATCH_OFFSET) {
4314 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4315 if (priv->counter_fallback)
4316 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4317 0, pkts, bytes, 0, NULL, NULL, 0);
4320 rte_spinlock_lock(&pool->sl);
4322 * The single counters allocation may allocate smaller ID than the
4323 * current allocated in parallel to the host reading.
4324 * In this case the new counter values must be reported as 0.
4326 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4330 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4331 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4332 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4334 rte_spinlock_unlock(&pool->sl);
4339 * Create and initialize a new counter pool.
4342 * Pointer to the Ethernet device structure.
4344 * The devX counter handle.
4346 * Whether the pool is for counter that was allocated by batch command.
4348 * Whether the pool is for counter that was allocated for aging.
4349 * @param[in/out] cont_cur
4350 * Pointer to the container pointer, it will be update in pool resize.
4353 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4355 static struct mlx5_flow_counter_pool *
4356 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4357 uint32_t batch, uint32_t age)
4359 struct mlx5_priv *priv = dev->data->dev_private;
4360 struct mlx5_flow_counter_pool *pool;
4361 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4363 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4364 uint32_t size = sizeof(*pool);
4366 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4368 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4369 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4370 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4371 pool = rte_calloc(__func__, 1, size, 0);
4376 pool->min_dcs = dcs;
4377 if (!priv->counter_fallback)
4378 pool->raw = cont->mem_mng->raws + n_valid %
4379 MLX5_CNT_CONTAINER_RESIZE;
4380 pool->raw_hw = NULL;
4382 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4383 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4384 pool->query_gen = 0;
4385 rte_spinlock_init(&pool->sl);
4386 TAILQ_INIT(&pool->counters[0]);
4387 TAILQ_INIT(&pool->counters[1]);
4388 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4389 pool->index = n_valid;
4390 cont->pools[n_valid] = pool;
4392 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4394 if (base < cont->min_id)
4395 cont->min_id = base;
4396 if (base > cont->max_id)
4397 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4398 cont->last_pool_idx = pool->index;
4400 /* Pool initialization must be updated before host thread access. */
4402 rte_atomic16_add(&cont->n_valid, 1);
4407 * Update the minimum dcs-id for aged or no-aged counter pool.
4410 * Pointer to the Ethernet device structure.
4412 * Current counter pool.
4414 * Whether the pool is for counter that was allocated by batch command.
4416 * Whether the counter is for aging.
4419 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4420 struct mlx5_flow_counter_pool *pool,
4421 uint32_t batch, uint32_t age)
4423 struct mlx5_priv *priv = dev->data->dev_private;
4424 struct mlx5_flow_counter_pool *other;
4425 struct mlx5_pools_container *cont;
4427 cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4428 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4431 if (pool->min_dcs->id < other->min_dcs->id) {
4432 rte_atomic64_set(&other->a64_dcs,
4433 rte_atomic64_read(&pool->a64_dcs));
4435 rte_atomic64_set(&pool->a64_dcs,
4436 rte_atomic64_read(&other->a64_dcs));
4440 * Prepare a new counter and/or a new counter pool.
4443 * Pointer to the Ethernet device structure.
4444 * @param[out] cnt_free
4445 * Where to put the pointer of a new counter.
4447 * Whether the pool is for counter that was allocated by batch command.
4449 * Whether the pool is for counter that was allocated for aging.
4452 * The counter pool pointer and @p cnt_free is set on success,
4453 * NULL otherwise and rte_errno is set.
4455 static struct mlx5_flow_counter_pool *
4456 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4457 struct mlx5_flow_counter **cnt_free,
4458 uint32_t batch, uint32_t age)
4460 struct mlx5_priv *priv = dev->data->dev_private;
4461 struct mlx5_pools_container *cont;
4462 struct mlx5_flow_counter_pool *pool;
4463 struct mlx5_counters tmp_tq;
4464 struct mlx5_devx_obj *dcs = NULL;
4465 struct mlx5_flow_counter *cnt;
4468 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4470 /* bulk_bitmap must be 0 for single counter allocation. */
4471 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4474 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4476 pool = flow_dv_pool_create(dev, dcs, batch, age);
4478 mlx5_devx_cmd_destroy(dcs);
4481 } else if (dcs->id < pool->min_dcs->id) {
4482 rte_atomic64_set(&pool->a64_dcs,
4483 (int64_t)(uintptr_t)dcs);
4485 flow_dv_counter_update_min_dcs(dev,
4487 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4488 cnt = MLX5_POOL_GET_CNT(pool, i);
4490 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4494 /* bulk_bitmap is in 128 counters units. */
4495 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4496 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4498 rte_errno = ENODATA;
4501 pool = flow_dv_pool_create(dev, dcs, batch, age);
4503 mlx5_devx_cmd_destroy(dcs);
4506 TAILQ_INIT(&tmp_tq);
4507 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4508 cnt = MLX5_POOL_GET_CNT(pool, i);
4510 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4512 rte_spinlock_lock(&cont->csl);
4513 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4514 rte_spinlock_unlock(&cont->csl);
4515 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4516 (*cnt_free)->pool = pool;
4521 * Search for existed shared counter.
4524 * Pointer to the Ethernet device structure.
4526 * The shared counter ID to search.
4528 * mlx5 flow counter pool in the container,
4531 * NULL if not existed, otherwise pointer to the shared extend counter.
4533 static struct mlx5_flow_counter_ext *
4534 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4535 struct mlx5_flow_counter_pool **ppool)
4537 struct mlx5_priv *priv = dev->data->dev_private;
4538 union mlx5_l3t_data data;
4541 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4543 cnt_idx = data.dword;
4545 * Shared counters don't have age info. The counter extend is after
4546 * the counter datat structure.
4548 return (struct mlx5_flow_counter_ext *)
4549 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4553 * Allocate a flow counter.
4556 * Pointer to the Ethernet device structure.
4558 * Indicate if this counter is shared with other flows.
4560 * Counter identifier.
4562 * Counter flow group.
4564 * Whether the counter was allocated for aging.
4567 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4570 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4571 uint16_t group, uint32_t age)
4573 struct mlx5_priv *priv = dev->data->dev_private;
4574 struct mlx5_flow_counter_pool *pool = NULL;
4575 struct mlx5_flow_counter *cnt_free = NULL;
4576 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4578 * Currently group 0 flow counter cannot be assigned to a flow if it is
4579 * not the first one in the batch counter allocation, so it is better
4580 * to allocate counters one by one for these flows in a separate
4582 * A counter can be shared between different groups so need to take
4583 * shared counters from the single container.
4585 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4586 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4590 if (!priv->config.devx) {
4591 rte_errno = ENOTSUP;
4595 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4597 if (cnt_ext->ref_cnt + 1 == 0) {
4602 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4603 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4608 /* Get free counters from container. */
4609 rte_spinlock_lock(&cont->csl);
4610 cnt_free = TAILQ_FIRST(&cont->counters);
4612 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4613 rte_spinlock_unlock(&cont->csl);
4614 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4617 pool = cnt_free->pool;
4619 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4620 /* Create a DV counter action only in the first time usage. */
4621 if (!cnt_free->action) {
4623 struct mlx5_devx_obj *dcs;
4626 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4627 dcs = pool->min_dcs;
4632 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4634 if (!cnt_free->action) {
4639 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4640 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4641 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4642 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4643 /* Update the counter reset values. */
4644 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4648 cnt_ext->shared = shared;
4649 cnt_ext->ref_cnt = 1;
4652 union mlx5_l3t_data data;
4654 data.dword = cnt_idx;
4655 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4659 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4660 /* Start the asynchronous batch query by the host thread. */
4661 mlx5_set_query_alarm(priv->sh);
4665 cnt_free->pool = pool;
4666 rte_spinlock_lock(&cont->csl);
4667 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4668 rte_spinlock_unlock(&cont->csl);
4674 * Get age param from counter index.
4677 * Pointer to the Ethernet device structure.
4678 * @param[in] counter
4679 * Index to the counter handler.
4682 * The aging parameter specified for the counter index.
4684 static struct mlx5_age_param*
4685 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4688 struct mlx5_flow_counter *cnt;
4689 struct mlx5_flow_counter_pool *pool = NULL;
4691 flow_dv_counter_get_by_idx(dev, counter, &pool);
4692 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4693 cnt = MLX5_POOL_GET_CNT(pool, counter);
4694 return MLX5_CNT_TO_AGE(cnt);
4698 * Remove a flow counter from aged counter list.
4701 * Pointer to the Ethernet device structure.
4702 * @param[in] counter
4703 * Index to the counter handler.
4705 * Pointer to the counter handler.
4708 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4709 uint32_t counter, struct mlx5_flow_counter *cnt)
4711 struct mlx5_age_info *age_info;
4712 struct mlx5_age_param *age_param;
4713 struct mlx5_priv *priv = dev->data->dev_private;
4715 age_info = GET_PORT_AGE_INFO(priv);
4716 age_param = flow_dv_counter_idx_get_age(dev, counter);
4717 if (rte_atomic16_cmpset((volatile uint16_t *)
4719 AGE_CANDIDATE, AGE_FREE)
4722 * We need the lock even it is age timeout,
4723 * since counter may still in process.
4725 rte_spinlock_lock(&age_info->aged_sl);
4726 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4727 rte_spinlock_unlock(&age_info->aged_sl);
4729 rte_atomic16_set(&age_param->state, AGE_FREE);
4732 * Release a flow counter.
4735 * Pointer to the Ethernet device structure.
4736 * @param[in] counter
4737 * Index to the counter handler.
4740 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4742 struct mlx5_priv *priv = dev->data->dev_private;
4743 struct mlx5_flow_counter_pool *pool = NULL;
4744 struct mlx5_flow_counter *cnt;
4745 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4749 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4751 if (counter < MLX5_CNT_BATCH_OFFSET) {
4752 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4754 if (--cnt_ext->ref_cnt)
4756 if (cnt_ext->shared)
4757 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4761 if (IS_AGE_POOL(pool))
4762 flow_dv_counter_remove_from_age(dev, counter, cnt);
4765 * Put the counter back to list to be updated in none fallback mode.
4766 * Currently, we are using two list alternately, while one is in query,
4767 * add the freed counter to the other list based on the pool query_gen
4768 * value. After query finishes, add counter the list to the global
4769 * container counter list. The list changes while query starts. In
4770 * this case, lock will not be needed as query callback and release
4771 * function both operate with the different list.
4774 if (!priv->counter_fallback)
4775 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4777 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4778 (priv->sh, 0, 0))->counters),
4783 * Verify the @p attributes will be correctly understood by the NIC and store
4784 * them in the @p flow if everything is correct.
4787 * Pointer to dev struct.
4788 * @param[in] attributes
4789 * Pointer to flow attributes
4790 * @param[in] external
4791 * This flow rule is created by request external to PMD.
4793 * Pointer to error structure.
4796 * - 0 on success and non root table.
4797 * - 1 on success and root table.
4798 * - a negative errno value otherwise and rte_errno is set.
4801 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4802 const struct rte_flow_attr *attributes,
4803 bool external __rte_unused,
4804 struct rte_flow_error *error)
4806 struct mlx5_priv *priv = dev->data->dev_private;
4807 uint32_t priority_max = priv->config.flow_prio - 1;
4810 #ifndef HAVE_MLX5DV_DR
4811 if (attributes->group)
4812 return rte_flow_error_set(error, ENOTSUP,
4813 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4815 "groups are not supported");
4819 ret = mlx5_flow_group_to_table(attributes, external,
4820 attributes->group, !!priv->fdb_def_rule,
4825 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4827 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4828 attributes->priority >= priority_max)
4829 return rte_flow_error_set(error, ENOTSUP,
4830 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4832 "priority out of range");
4833 if (attributes->transfer) {
4834 if (!priv->config.dv_esw_en)
4835 return rte_flow_error_set
4837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4838 "E-Switch dr is not supported");
4839 if (!(priv->representor || priv->master))
4840 return rte_flow_error_set
4841 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4842 NULL, "E-Switch configuration can only be"
4843 " done by a master or a representor device");
4844 if (attributes->egress)
4845 return rte_flow_error_set
4847 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4848 "egress is not supported");
4850 if (!(attributes->egress ^ attributes->ingress))
4851 return rte_flow_error_set(error, ENOTSUP,
4852 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4853 "must specify exactly one of "
4854 "ingress or egress");
4859 * Internal validation function. For validating both actions and items.
4862 * Pointer to the rte_eth_dev structure.
4864 * Pointer to the flow attributes.
4866 * Pointer to the list of items.
4867 * @param[in] actions
4868 * Pointer to the list of actions.
4869 * @param[in] external
4870 * This flow rule is created by request external to PMD.
4871 * @param[in] hairpin
4872 * Number of hairpin TX actions, 0 means classic flow.
4874 * Pointer to the error structure.
4877 * 0 on success, a negative errno value otherwise and rte_errno is set.
4880 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4881 const struct rte_flow_item items[],
4882 const struct rte_flow_action actions[],
4883 bool external, int hairpin, struct rte_flow_error *error)
4886 uint64_t action_flags = 0;
4887 uint64_t item_flags = 0;
4888 uint64_t last_item = 0;
4889 uint8_t next_protocol = 0xff;
4890 uint16_t ether_type = 0;
4892 uint8_t item_ipv6_proto = 0;
4893 const struct rte_flow_item *gre_item = NULL;
4894 const struct rte_flow_action_raw_decap *decap;
4895 const struct rte_flow_action_raw_encap *encap;
4896 const struct rte_flow_action_rss *rss;
4897 const struct rte_flow_item_tcp nic_tcp_mask = {
4900 .src_port = RTE_BE16(UINT16_MAX),
4901 .dst_port = RTE_BE16(UINT16_MAX),
4904 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4906 .src_addr = RTE_BE32(0xffffffff),
4907 .dst_addr = RTE_BE32(0xffffffff),
4908 .type_of_service = 0xff,
4909 .next_proto_id = 0xff,
4910 .time_to_live = 0xff,
4913 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4916 "\xff\xff\xff\xff\xff\xff\xff\xff"
4917 "\xff\xff\xff\xff\xff\xff\xff\xff",
4919 "\xff\xff\xff\xff\xff\xff\xff\xff"
4920 "\xff\xff\xff\xff\xff\xff\xff\xff",
4921 .vtc_flow = RTE_BE32(0xffffffff),
4926 struct mlx5_priv *priv = dev->data->dev_private;
4927 struct mlx5_dev_config *dev_conf = &priv->config;
4928 uint16_t queue_index = 0xFFFF;
4929 const struct rte_flow_item_vlan *vlan_m = NULL;
4930 int16_t rw_act_num = 0;
4935 ret = flow_dv_validate_attributes(dev, attr, external, error);
4938 is_root = (uint64_t)ret;
4939 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4940 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4941 int type = items->type;
4943 if (!mlx5_flow_os_item_supported(type))
4944 return rte_flow_error_set(error, ENOTSUP,
4945 RTE_FLOW_ERROR_TYPE_ITEM,
4946 NULL, "item not supported");
4948 case RTE_FLOW_ITEM_TYPE_VOID:
4950 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4951 ret = flow_dv_validate_item_port_id
4952 (dev, items, attr, item_flags, error);
4955 last_item = MLX5_FLOW_ITEM_PORT_ID;
4957 case RTE_FLOW_ITEM_TYPE_ETH:
4958 ret = mlx5_flow_validate_item_eth(items, item_flags,
4962 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4963 MLX5_FLOW_LAYER_OUTER_L2;
4964 if (items->mask != NULL && items->spec != NULL) {
4966 ((const struct rte_flow_item_eth *)
4969 ((const struct rte_flow_item_eth *)
4971 ether_type = rte_be_to_cpu_16(ether_type);
4976 case RTE_FLOW_ITEM_TYPE_VLAN:
4977 ret = flow_dv_validate_item_vlan(items, item_flags,
4981 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4982 MLX5_FLOW_LAYER_OUTER_VLAN;
4983 if (items->mask != NULL && items->spec != NULL) {
4985 ((const struct rte_flow_item_vlan *)
4986 items->spec)->inner_type;
4988 ((const struct rte_flow_item_vlan *)
4989 items->mask)->inner_type;
4990 ether_type = rte_be_to_cpu_16(ether_type);
4994 /* Store outer VLAN mask for of_push_vlan action. */
4996 vlan_m = items->mask;
4998 case RTE_FLOW_ITEM_TYPE_IPV4:
4999 mlx5_flow_tunnel_ip_check(items, next_protocol,
5000 &item_flags, &tunnel);
5001 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5008 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5009 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5010 if (items->mask != NULL &&
5011 ((const struct rte_flow_item_ipv4 *)
5012 items->mask)->hdr.next_proto_id) {
5014 ((const struct rte_flow_item_ipv4 *)
5015 (items->spec))->hdr.next_proto_id;
5017 ((const struct rte_flow_item_ipv4 *)
5018 (items->mask))->hdr.next_proto_id;
5020 /* Reset for inner layer. */
5021 next_protocol = 0xff;
5024 case RTE_FLOW_ITEM_TYPE_IPV6:
5025 mlx5_flow_tunnel_ip_check(items, next_protocol,
5026 &item_flags, &tunnel);
5027 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5034 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5035 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5036 if (items->mask != NULL &&
5037 ((const struct rte_flow_item_ipv6 *)
5038 items->mask)->hdr.proto) {
5040 ((const struct rte_flow_item_ipv6 *)
5041 items->spec)->hdr.proto;
5043 ((const struct rte_flow_item_ipv6 *)
5044 items->spec)->hdr.proto;
5046 ((const struct rte_flow_item_ipv6 *)
5047 items->mask)->hdr.proto;
5049 /* Reset for inner layer. */
5050 next_protocol = 0xff;
5053 case RTE_FLOW_ITEM_TYPE_TCP:
5054 ret = mlx5_flow_validate_item_tcp
5061 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5062 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5064 case RTE_FLOW_ITEM_TYPE_UDP:
5065 ret = mlx5_flow_validate_item_udp(items, item_flags,
5070 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5071 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5073 case RTE_FLOW_ITEM_TYPE_GRE:
5074 ret = mlx5_flow_validate_item_gre(items, item_flags,
5075 next_protocol, error);
5079 last_item = MLX5_FLOW_LAYER_GRE;
5081 case RTE_FLOW_ITEM_TYPE_NVGRE:
5082 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5087 last_item = MLX5_FLOW_LAYER_NVGRE;
5089 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5090 ret = mlx5_flow_validate_item_gre_key
5091 (items, item_flags, gre_item, error);
5094 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5096 case RTE_FLOW_ITEM_TYPE_VXLAN:
5097 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5101 last_item = MLX5_FLOW_LAYER_VXLAN;
5103 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5104 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5109 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5111 case RTE_FLOW_ITEM_TYPE_GENEVE:
5112 ret = mlx5_flow_validate_item_geneve(items,
5117 last_item = MLX5_FLOW_LAYER_GENEVE;
5119 case RTE_FLOW_ITEM_TYPE_MPLS:
5120 ret = mlx5_flow_validate_item_mpls(dev, items,
5125 last_item = MLX5_FLOW_LAYER_MPLS;
5128 case RTE_FLOW_ITEM_TYPE_MARK:
5129 ret = flow_dv_validate_item_mark(dev, items, attr,
5133 last_item = MLX5_FLOW_ITEM_MARK;
5135 case RTE_FLOW_ITEM_TYPE_META:
5136 ret = flow_dv_validate_item_meta(dev, items, attr,
5140 last_item = MLX5_FLOW_ITEM_METADATA;
5142 case RTE_FLOW_ITEM_TYPE_ICMP:
5143 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5148 last_item = MLX5_FLOW_LAYER_ICMP;
5150 case RTE_FLOW_ITEM_TYPE_ICMP6:
5151 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5156 item_ipv6_proto = IPPROTO_ICMPV6;
5157 last_item = MLX5_FLOW_LAYER_ICMP6;
5159 case RTE_FLOW_ITEM_TYPE_TAG:
5160 ret = flow_dv_validate_item_tag(dev, items,
5164 last_item = MLX5_FLOW_ITEM_TAG;
5166 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5167 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5169 case RTE_FLOW_ITEM_TYPE_GTP:
5170 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5174 last_item = MLX5_FLOW_LAYER_GTP;
5177 return rte_flow_error_set(error, ENOTSUP,
5178 RTE_FLOW_ERROR_TYPE_ITEM,
5179 NULL, "item not supported");
5181 item_flags |= last_item;
5183 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5184 int type = actions->type;
5186 if (!mlx5_flow_os_action_supported(type))
5187 return rte_flow_error_set(error, ENOTSUP,
5188 RTE_FLOW_ERROR_TYPE_ACTION,
5190 "action not supported");
5191 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5192 return rte_flow_error_set(error, ENOTSUP,
5193 RTE_FLOW_ERROR_TYPE_ACTION,
5194 actions, "too many actions");
5196 case RTE_FLOW_ACTION_TYPE_VOID:
5198 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5199 ret = flow_dv_validate_action_port_id(dev,
5206 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5209 case RTE_FLOW_ACTION_TYPE_FLAG:
5210 ret = flow_dv_validate_action_flag(dev, action_flags,
5214 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5215 /* Count all modify-header actions as one. */
5216 if (!(action_flags &
5217 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5219 action_flags |= MLX5_FLOW_ACTION_FLAG |
5220 MLX5_FLOW_ACTION_MARK_EXT;
5222 action_flags |= MLX5_FLOW_ACTION_FLAG;
5225 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5227 case RTE_FLOW_ACTION_TYPE_MARK:
5228 ret = flow_dv_validate_action_mark(dev, actions,
5233 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5234 /* Count all modify-header actions as one. */
5235 if (!(action_flags &
5236 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5238 action_flags |= MLX5_FLOW_ACTION_MARK |
5239 MLX5_FLOW_ACTION_MARK_EXT;
5241 action_flags |= MLX5_FLOW_ACTION_MARK;
5244 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5246 case RTE_FLOW_ACTION_TYPE_SET_META:
5247 ret = flow_dv_validate_action_set_meta(dev, actions,
5252 /* Count all modify-header actions as one action. */
5253 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5255 action_flags |= MLX5_FLOW_ACTION_SET_META;
5256 rw_act_num += MLX5_ACT_NUM_SET_META;
5258 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5259 ret = flow_dv_validate_action_set_tag(dev, actions,
5264 /* Count all modify-header actions as one action. */
5265 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5267 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5268 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5270 case RTE_FLOW_ACTION_TYPE_DROP:
5271 ret = mlx5_flow_validate_action_drop(action_flags,
5275 action_flags |= MLX5_FLOW_ACTION_DROP;
5278 case RTE_FLOW_ACTION_TYPE_QUEUE:
5279 ret = mlx5_flow_validate_action_queue(actions,
5284 queue_index = ((const struct rte_flow_action_queue *)
5285 (actions->conf))->index;
5286 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5289 case RTE_FLOW_ACTION_TYPE_RSS:
5290 rss = actions->conf;
5291 ret = mlx5_flow_validate_action_rss(actions,
5297 if (rss != NULL && rss->queue_num)
5298 queue_index = rss->queue[0];
5299 action_flags |= MLX5_FLOW_ACTION_RSS;
5302 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5304 mlx5_flow_validate_action_default_miss(action_flags,
5308 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5311 case RTE_FLOW_ACTION_TYPE_COUNT:
5312 ret = flow_dv_validate_action_count(dev, error);
5315 action_flags |= MLX5_FLOW_ACTION_COUNT;
5318 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5319 if (flow_dv_validate_action_pop_vlan(dev,
5325 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5328 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5329 ret = flow_dv_validate_action_push_vlan(dev,
5336 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5339 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5340 ret = flow_dv_validate_action_set_vlan_pcp
5341 (action_flags, actions, error);
5344 /* Count PCP with push_vlan command. */
5345 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5347 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5348 ret = flow_dv_validate_action_set_vlan_vid
5349 (item_flags, action_flags,
5353 /* Count VID with push_vlan command. */
5354 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5355 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5357 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5358 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5359 ret = flow_dv_validate_action_l2_encap(dev,
5365 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5368 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5369 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5370 ret = flow_dv_validate_action_decap(dev, action_flags,
5374 action_flags |= MLX5_FLOW_ACTION_DECAP;
5377 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5378 ret = flow_dv_validate_action_raw_encap_decap
5379 (dev, NULL, actions->conf, attr, &action_flags,
5384 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5385 decap = actions->conf;
5386 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5388 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5392 encap = actions->conf;
5394 ret = flow_dv_validate_action_raw_encap_decap
5396 decap ? decap : &empty_decap, encap,
5397 attr, &action_flags, &actions_n,
5402 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5403 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5404 ret = flow_dv_validate_action_modify_mac(action_flags,
5410 /* Count all modify-header actions as one action. */
5411 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5413 action_flags |= actions->type ==
5414 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5415 MLX5_FLOW_ACTION_SET_MAC_SRC :
5416 MLX5_FLOW_ACTION_SET_MAC_DST;
5418 * Even if the source and destination MAC addresses have
5419 * overlap in the header with 4B alignment, the convert
5420 * function will handle them separately and 4 SW actions
5421 * will be created. And 2 actions will be added each
5422 * time no matter how many bytes of address will be set.
5424 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5426 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5427 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5428 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5434 /* Count all modify-header actions as one action. */
5435 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5437 action_flags |= actions->type ==
5438 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5439 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5440 MLX5_FLOW_ACTION_SET_IPV4_DST;
5441 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5443 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5444 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5445 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5451 if (item_ipv6_proto == IPPROTO_ICMPV6)
5452 return rte_flow_error_set(error, ENOTSUP,
5453 RTE_FLOW_ERROR_TYPE_ACTION,
5455 "Can't change header "
5456 "with ICMPv6 proto");
5457 /* Count all modify-header actions as one action. */
5458 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5460 action_flags |= actions->type ==
5461 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5462 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5463 MLX5_FLOW_ACTION_SET_IPV6_DST;
5464 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5466 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5467 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5468 ret = flow_dv_validate_action_modify_tp(action_flags,
5474 /* Count all modify-header actions as one action. */
5475 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5477 action_flags |= actions->type ==
5478 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5479 MLX5_FLOW_ACTION_SET_TP_SRC :
5480 MLX5_FLOW_ACTION_SET_TP_DST;
5481 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5483 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5484 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5485 ret = flow_dv_validate_action_modify_ttl(action_flags,
5491 /* Count all modify-header actions as one action. */
5492 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5494 action_flags |= actions->type ==
5495 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5496 MLX5_FLOW_ACTION_SET_TTL :
5497 MLX5_FLOW_ACTION_DEC_TTL;
5498 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5500 case RTE_FLOW_ACTION_TYPE_JUMP:
5501 ret = flow_dv_validate_action_jump(actions,
5508 action_flags |= MLX5_FLOW_ACTION_JUMP;
5510 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5511 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5512 ret = flow_dv_validate_action_modify_tcp_seq
5519 /* Count all modify-header actions as one action. */
5520 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5522 action_flags |= actions->type ==
5523 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5524 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5525 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5526 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5528 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5529 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5530 ret = flow_dv_validate_action_modify_tcp_ack
5537 /* Count all modify-header actions as one action. */
5538 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5540 action_flags |= actions->type ==
5541 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5542 MLX5_FLOW_ACTION_INC_TCP_ACK :
5543 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5544 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5546 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5548 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5549 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5550 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5552 case RTE_FLOW_ACTION_TYPE_METER:
5553 ret = mlx5_flow_validate_action_meter(dev,
5559 action_flags |= MLX5_FLOW_ACTION_METER;
5561 /* Meter action will add one more TAG action. */
5562 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5564 case RTE_FLOW_ACTION_TYPE_AGE:
5565 ret = flow_dv_validate_action_age(action_flags,
5570 action_flags |= MLX5_FLOW_ACTION_AGE;
5573 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5574 ret = flow_dv_validate_action_modify_ipv4_dscp
5581 /* Count all modify-header actions as one action. */
5582 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5584 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5585 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5587 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5588 ret = flow_dv_validate_action_modify_ipv6_dscp
5595 /* Count all modify-header actions as one action. */
5596 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5598 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5599 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5602 return rte_flow_error_set(error, ENOTSUP,
5603 RTE_FLOW_ERROR_TYPE_ACTION,
5605 "action not supported");
5609 * Validate the drop action mutual exclusion with other actions.
5610 * Drop action is mutually-exclusive with any other action, except for
5613 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5614 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5615 return rte_flow_error_set(error, EINVAL,
5616 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5617 "Drop action is mutually-exclusive "
5618 "with any other action, except for "
5620 /* Eswitch has few restrictions on using items and actions */
5621 if (attr->transfer) {
5622 if (!mlx5_flow_ext_mreg_supported(dev) &&
5623 action_flags & MLX5_FLOW_ACTION_FLAG)
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_ACTION,
5627 "unsupported action FLAG");
5628 if (!mlx5_flow_ext_mreg_supported(dev) &&
5629 action_flags & MLX5_FLOW_ACTION_MARK)
5630 return rte_flow_error_set(error, ENOTSUP,
5631 RTE_FLOW_ERROR_TYPE_ACTION,
5633 "unsupported action MARK");
5634 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5635 return rte_flow_error_set(error, ENOTSUP,
5636 RTE_FLOW_ERROR_TYPE_ACTION,
5638 "unsupported action QUEUE");
5639 if (action_flags & MLX5_FLOW_ACTION_RSS)
5640 return rte_flow_error_set(error, ENOTSUP,
5641 RTE_FLOW_ERROR_TYPE_ACTION,
5643 "unsupported action RSS");
5644 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5645 return rte_flow_error_set(error, EINVAL,
5646 RTE_FLOW_ERROR_TYPE_ACTION,
5648 "no fate action is found");
5650 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5651 return rte_flow_error_set(error, EINVAL,
5652 RTE_FLOW_ERROR_TYPE_ACTION,
5654 "no fate action is found");
5656 /* Continue validation for Xcap actions.*/
5657 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5658 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5659 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5660 MLX5_FLOW_XCAP_ACTIONS)
5661 return rte_flow_error_set(error, ENOTSUP,
5662 RTE_FLOW_ERROR_TYPE_ACTION,
5663 NULL, "encap and decap "
5664 "combination aren't supported");
5665 if (!attr->transfer && attr->ingress && (action_flags &
5666 MLX5_FLOW_ACTION_ENCAP))
5667 return rte_flow_error_set(error, ENOTSUP,
5668 RTE_FLOW_ERROR_TYPE_ACTION,
5669 NULL, "encap is not supported"
5670 " for ingress traffic");
5672 /* Hairpin flow will add one more TAG action. */
5674 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5675 /* extra metadata enabled: one more TAG action will be add. */
5676 if (dev_conf->dv_flow_en &&
5677 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5678 mlx5_flow_ext_mreg_supported(dev))
5679 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5680 if ((uint32_t)rw_act_num >
5681 flow_dv_modify_hdr_action_max(dev, is_root)) {
5682 return rte_flow_error_set(error, ENOTSUP,
5683 RTE_FLOW_ERROR_TYPE_ACTION,
5684 NULL, "too many header modify"
5685 " actions to support");
5691 * Internal preparation function. Allocates the DV flow size,
5692 * this size is constant.
5695 * Pointer to the rte_eth_dev structure.
5697 * Pointer to the flow attributes.
5699 * Pointer to the list of items.
5700 * @param[in] actions
5701 * Pointer to the list of actions.
5703 * Pointer to the error structure.
5706 * Pointer to mlx5_flow object on success,
5707 * otherwise NULL and rte_errno is set.
5709 static struct mlx5_flow *
5710 flow_dv_prepare(struct rte_eth_dev *dev,
5711 const struct rte_flow_attr *attr __rte_unused,
5712 const struct rte_flow_item items[] __rte_unused,
5713 const struct rte_flow_action actions[] __rte_unused,
5714 struct rte_flow_error *error)
5716 uint32_t handle_idx = 0;
5717 struct mlx5_flow *dev_flow;
5718 struct mlx5_flow_handle *dev_handle;
5719 struct mlx5_priv *priv = dev->data->dev_private;
5721 /* In case of corrupting the memory. */
5722 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5723 rte_flow_error_set(error, ENOSPC,
5724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5725 "not free temporary device flow");
5728 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5731 rte_flow_error_set(error, ENOMEM,
5732 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5733 "not enough memory to create flow handle");
5736 /* No multi-thread supporting. */
5737 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5738 dev_flow->handle = dev_handle;
5739 dev_flow->handle_idx = handle_idx;
5740 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5742 * The matching value needs to be cleared to 0 before using. In the
5743 * past, it will be automatically cleared when using rte_*alloc
5744 * API. The time consumption will be almost the same as before.
5746 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5747 dev_flow->ingress = attr->ingress;
5748 dev_flow->dv.transfer = attr->transfer;
5752 #ifdef RTE_LIBRTE_MLX5_DEBUG
5754 * Sanity check for match mask and value. Similar to check_valid_spec() in
5755 * kernel driver. If unmasked bit is present in value, it returns failure.
5758 * pointer to match mask buffer.
5759 * @param match_value
5760 * pointer to match value buffer.
5763 * 0 if valid, -EINVAL otherwise.
5766 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5768 uint8_t *m = match_mask;
5769 uint8_t *v = match_value;
5772 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5775 "match_value differs from match_criteria"
5776 " %p[%u] != %p[%u]",
5777 match_value, i, match_mask, i);
5786 * Add match of ip_version.
5790 * @param[in] headers_v
5791 * Values header pointer.
5792 * @param[in] headers_m
5793 * Masks header pointer.
5794 * @param[in] ip_version
5795 * The IP version to set.
5798 flow_dv_set_match_ip_version(uint32_t group,
5804 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5806 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5808 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5809 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5810 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5814 * Add Ethernet item to matcher and to the value.
5816 * @param[in, out] matcher
5818 * @param[in, out] key
5819 * Flow matcher value.
5821 * Flow pattern to translate.
5823 * Item is inner pattern.
5826 flow_dv_translate_item_eth(void *matcher, void *key,
5827 const struct rte_flow_item *item, int inner,
5830 const struct rte_flow_item_eth *eth_m = item->mask;
5831 const struct rte_flow_item_eth *eth_v = item->spec;
5832 const struct rte_flow_item_eth nic_mask = {
5833 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5834 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5835 .type = RTE_BE16(0xffff),
5847 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5849 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5851 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5853 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5855 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5856 ð_m->dst, sizeof(eth_m->dst));
5857 /* The value must be in the range of the mask. */
5858 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5859 for (i = 0; i < sizeof(eth_m->dst); ++i)
5860 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5861 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5862 ð_m->src, sizeof(eth_m->src));
5863 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5864 /* The value must be in the range of the mask. */
5865 for (i = 0; i < sizeof(eth_m->dst); ++i)
5866 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5868 /* When ethertype is present set mask for tagged VLAN. */
5869 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5870 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5871 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5872 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5873 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5875 /* Return here to avoid setting match on ethertype. */
5880 * HW supports match on one Ethertype, the Ethertype following the last
5881 * VLAN tag of the packet (see PRM).
5882 * Set match on ethertype only if ETH header is not followed by VLAN.
5883 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5884 * ethertype, and use ip_version field instead.
5886 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5887 eth_m->type == 0xFFFF) {
5888 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5889 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5890 eth_m->type == 0xFFFF) {
5891 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5893 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5894 rte_be_to_cpu_16(eth_m->type));
5895 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5897 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5902 * Add VLAN item to matcher and to the value.
5904 * @param[in, out] dev_flow
5906 * @param[in, out] matcher
5908 * @param[in, out] key
5909 * Flow matcher value.
5911 * Flow pattern to translate.
5913 * Item is inner pattern.
5916 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5917 void *matcher, void *key,
5918 const struct rte_flow_item *item,
5919 int inner, uint32_t group)
5921 const struct rte_flow_item_vlan *vlan_m = item->mask;
5922 const struct rte_flow_item_vlan *vlan_v = item->spec;
5929 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5931 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5933 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5935 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5937 * This is workaround, masks are not supported,
5938 * and pre-validated.
5941 dev_flow->handle->vf_vlan.tag =
5942 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5945 * When VLAN item exists in flow, mark packet as tagged,
5946 * even if TCI is not specified.
5948 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5949 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5953 vlan_m = &rte_flow_item_vlan_mask;
5954 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5955 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5956 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5958 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5959 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5960 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5961 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5963 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5964 * ethertype, and use ip_version field instead.
5966 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5967 vlan_m->inner_type == 0xFFFF) {
5968 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5969 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5970 vlan_m->inner_type == 0xFFFF) {
5971 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5973 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5974 rte_be_to_cpu_16(vlan_m->inner_type));
5975 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5976 rte_be_to_cpu_16(vlan_m->inner_type &
5977 vlan_v->inner_type));
5982 * Add IPV4 item to matcher and to the value.
5984 * @param[in, out] matcher
5986 * @param[in, out] key
5987 * Flow matcher value.
5989 * Flow pattern to translate.
5990 * @param[in] item_flags
5991 * Bit-fields that holds the items detected until now.
5993 * Item is inner pattern.
5995 * The group to insert the rule.
5998 flow_dv_translate_item_ipv4(void *matcher, void *key,
5999 const struct rte_flow_item *item,
6000 const uint64_t item_flags,
6001 int inner, uint32_t group)
6003 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6004 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6005 const struct rte_flow_item_ipv4 nic_mask = {
6007 .src_addr = RTE_BE32(0xffffffff),
6008 .dst_addr = RTE_BE32(0xffffffff),
6009 .type_of_service = 0xff,
6010 .next_proto_id = 0xff,
6011 .time_to_live = 0xff,
6021 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6023 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6025 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6027 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6029 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6031 * On outer header (which must contains L2), or inner header with L2,
6032 * set cvlan_tag mask bit to mark this packet as untagged.
6033 * This should be done even if item->spec is empty.
6035 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6036 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6041 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6042 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6043 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6044 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6045 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6046 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6047 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6048 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6049 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6050 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6051 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6052 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6053 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6054 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6055 ipv4_m->hdr.type_of_service);
6056 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6057 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6058 ipv4_m->hdr.type_of_service >> 2);
6059 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6060 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6061 ipv4_m->hdr.next_proto_id);
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6063 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6064 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6065 ipv4_m->hdr.time_to_live);
6066 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6067 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6071 * Add IPV6 item to matcher and to the value.
6073 * @param[in, out] matcher
6075 * @param[in, out] key
6076 * Flow matcher value.
6078 * Flow pattern to translate.
6079 * @param[in] item_flags
6080 * Bit-fields that holds the items detected until now.
6082 * Item is inner pattern.
6084 * The group to insert the rule.
6087 flow_dv_translate_item_ipv6(void *matcher, void *key,
6088 const struct rte_flow_item *item,
6089 const uint64_t item_flags,
6090 int inner, uint32_t group)
6092 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6093 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6094 const struct rte_flow_item_ipv6 nic_mask = {
6097 "\xff\xff\xff\xff\xff\xff\xff\xff"
6098 "\xff\xff\xff\xff\xff\xff\xff\xff",
6100 "\xff\xff\xff\xff\xff\xff\xff\xff"
6101 "\xff\xff\xff\xff\xff\xff\xff\xff",
6102 .vtc_flow = RTE_BE32(0xffffffff),
6109 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6110 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6119 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6121 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6123 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6125 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6127 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6129 * On outer header (which must contains L2), or inner header with L2,
6130 * set cvlan_tag mask bit to mark this packet as untagged.
6131 * This should be done even if item->spec is empty.
6133 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6134 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6139 size = sizeof(ipv6_m->hdr.dst_addr);
6140 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6141 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6142 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6143 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6144 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6145 for (i = 0; i < size; ++i)
6146 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6147 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6148 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6149 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6150 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6151 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6152 for (i = 0; i < size; ++i)
6153 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6155 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6156 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6157 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6158 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6159 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6160 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6163 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6165 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6168 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6170 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6174 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6176 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6177 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6180 ipv6_m->hdr.hop_limits);
6181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6182 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6186 * Add TCP item to matcher and to the value.
6188 * @param[in, out] matcher
6190 * @param[in, out] key
6191 * Flow matcher value.
6193 * Flow pattern to translate.
6195 * Item is inner pattern.
6198 flow_dv_translate_item_tcp(void *matcher, void *key,
6199 const struct rte_flow_item *item,
6202 const struct rte_flow_item_tcp *tcp_m = item->mask;
6203 const struct rte_flow_item_tcp *tcp_v = item->spec;
6208 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6210 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6212 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6214 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6221 tcp_m = &rte_flow_item_tcp_mask;
6222 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6223 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6224 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6225 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6226 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6227 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6228 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6229 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6230 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6231 tcp_m->hdr.tcp_flags);
6232 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6233 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6237 * Add UDP item to matcher and to the value.
6239 * @param[in, out] matcher
6241 * @param[in, out] key
6242 * Flow matcher value.
6244 * Flow pattern to translate.
6246 * Item is inner pattern.
6249 flow_dv_translate_item_udp(void *matcher, void *key,
6250 const struct rte_flow_item *item,
6253 const struct rte_flow_item_udp *udp_m = item->mask;
6254 const struct rte_flow_item_udp *udp_v = item->spec;
6259 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6261 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6263 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6265 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6268 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6272 udp_m = &rte_flow_item_udp_mask;
6273 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6274 rte_be_to_cpu_16(udp_m->hdr.src_port));
6275 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6276 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6277 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6278 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6280 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6284 * Add GRE optional Key item to matcher and to the value.
6286 * @param[in, out] matcher
6288 * @param[in, out] key
6289 * Flow matcher value.
6291 * Flow pattern to translate.
6293 * Item is inner pattern.
6296 flow_dv_translate_item_gre_key(void *matcher, void *key,
6297 const struct rte_flow_item *item)
6299 const rte_be32_t *key_m = item->mask;
6300 const rte_be32_t *key_v = item->spec;
6301 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6302 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6303 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6305 /* GRE K bit must be on and should already be validated */
6306 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6307 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6311 key_m = &gre_key_default_mask;
6312 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6313 rte_be_to_cpu_32(*key_m) >> 8);
6314 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6315 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6316 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6317 rte_be_to_cpu_32(*key_m) & 0xFF);
6318 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6319 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6323 * Add GRE item to matcher and to the value.
6325 * @param[in, out] matcher
6327 * @param[in, out] key
6328 * Flow matcher value.
6330 * Flow pattern to translate.
6332 * Item is inner pattern.
6335 flow_dv_translate_item_gre(void *matcher, void *key,
6336 const struct rte_flow_item *item,
6339 const struct rte_flow_item_gre *gre_m = item->mask;
6340 const struct rte_flow_item_gre *gre_v = item->spec;
6343 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6344 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6351 uint16_t s_present:1;
6352 uint16_t k_present:1;
6353 uint16_t rsvd_bit1:1;
6354 uint16_t c_present:1;
6358 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6361 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6363 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6365 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6367 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6369 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6374 gre_m = &rte_flow_item_gre_mask;
6375 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6376 rte_be_to_cpu_16(gre_m->protocol));
6377 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6378 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6379 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6380 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6381 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6382 gre_crks_rsvd0_ver_m.c_present);
6383 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6384 gre_crks_rsvd0_ver_v.c_present &
6385 gre_crks_rsvd0_ver_m.c_present);
6386 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6387 gre_crks_rsvd0_ver_m.k_present);
6388 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6389 gre_crks_rsvd0_ver_v.k_present &
6390 gre_crks_rsvd0_ver_m.k_present);
6391 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6392 gre_crks_rsvd0_ver_m.s_present);
6393 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6394 gre_crks_rsvd0_ver_v.s_present &
6395 gre_crks_rsvd0_ver_m.s_present);
6399 * Add NVGRE item to matcher and to the value.
6401 * @param[in, out] matcher
6403 * @param[in, out] key
6404 * Flow matcher value.
6406 * Flow pattern to translate.
6408 * Item is inner pattern.
6411 flow_dv_translate_item_nvgre(void *matcher, void *key,
6412 const struct rte_flow_item *item,
6415 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6416 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6417 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6418 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6419 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6420 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6426 /* For NVGRE, GRE header fields must be set with defined values. */
6427 const struct rte_flow_item_gre gre_spec = {
6428 .c_rsvd0_ver = RTE_BE16(0x2000),
6429 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6431 const struct rte_flow_item_gre gre_mask = {
6432 .c_rsvd0_ver = RTE_BE16(0xB000),
6433 .protocol = RTE_BE16(UINT16_MAX),
6435 const struct rte_flow_item gre_item = {
6440 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6444 nvgre_m = &rte_flow_item_nvgre_mask;
6445 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6446 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6447 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6448 memcpy(gre_key_m, tni_flow_id_m, size);
6449 for (i = 0; i < size; ++i)
6450 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6454 * Add VXLAN item to matcher and to the value.
6456 * @param[in, out] matcher
6458 * @param[in, out] key
6459 * Flow matcher value.
6461 * Flow pattern to translate.
6463 * Item is inner pattern.
6466 flow_dv_translate_item_vxlan(void *matcher, void *key,
6467 const struct rte_flow_item *item,
6470 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6471 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6474 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6475 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6483 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6485 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6487 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6489 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6491 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6492 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6493 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6500 vxlan_m = &rte_flow_item_vxlan_mask;
6501 size = sizeof(vxlan_m->vni);
6502 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6503 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6504 memcpy(vni_m, vxlan_m->vni, size);
6505 for (i = 0; i < size; ++i)
6506 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6510 * Add VXLAN-GPE item to matcher and to the value.
6512 * @param[in, out] matcher
6514 * @param[in, out] key
6515 * Flow matcher value.
6517 * Flow pattern to translate.
6519 * Item is inner pattern.
6523 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6524 const struct rte_flow_item *item, int inner)
6526 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6527 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6531 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6533 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6539 uint8_t flags_m = 0xff;
6540 uint8_t flags_v = 0xc;
6543 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6545 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6547 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6549 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6551 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6552 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6553 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6554 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6555 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6560 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6561 size = sizeof(vxlan_m->vni);
6562 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6563 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6564 memcpy(vni_m, vxlan_m->vni, size);
6565 for (i = 0; i < size; ++i)
6566 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6567 if (vxlan_m->flags) {
6568 flags_m = vxlan_m->flags;
6569 flags_v = vxlan_v->flags;
6571 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6572 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6573 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6575 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6580 * Add Geneve item to matcher and to the value.
6582 * @param[in, out] matcher
6584 * @param[in, out] key
6585 * Flow matcher value.
6587 * Flow pattern to translate.
6589 * Item is inner pattern.
6593 flow_dv_translate_item_geneve(void *matcher, void *key,
6594 const struct rte_flow_item *item, int inner)
6596 const struct rte_flow_item_geneve *geneve_m = item->mask;
6597 const struct rte_flow_item_geneve *geneve_v = item->spec;
6600 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6601 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6610 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6612 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6614 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6616 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6618 dport = MLX5_UDP_PORT_GENEVE;
6619 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6620 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6626 geneve_m = &rte_flow_item_geneve_mask;
6627 size = sizeof(geneve_m->vni);
6628 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6629 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6630 memcpy(vni_m, geneve_m->vni, size);
6631 for (i = 0; i < size; ++i)
6632 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6633 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6634 rte_be_to_cpu_16(geneve_m->protocol));
6635 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6636 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6637 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6638 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6639 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6640 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6641 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6642 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6643 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6644 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6645 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6646 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6647 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6651 * Add MPLS item to matcher and to the value.
6653 * @param[in, out] matcher
6655 * @param[in, out] key
6656 * Flow matcher value.
6658 * Flow pattern to translate.
6659 * @param[in] prev_layer
6660 * The protocol layer indicated in previous item.
6662 * Item is inner pattern.
6665 flow_dv_translate_item_mpls(void *matcher, void *key,
6666 const struct rte_flow_item *item,
6667 uint64_t prev_layer,
6670 const uint32_t *in_mpls_m = item->mask;
6671 const uint32_t *in_mpls_v = item->spec;
6672 uint32_t *out_mpls_m = 0;
6673 uint32_t *out_mpls_v = 0;
6674 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6675 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6676 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6678 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6679 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6680 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6682 switch (prev_layer) {
6683 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6685 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6686 MLX5_UDP_PORT_MPLS);
6688 case MLX5_FLOW_LAYER_GRE:
6689 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6690 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6691 RTE_ETHER_TYPE_MPLS);
6694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6702 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6703 switch (prev_layer) {
6704 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6706 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6707 outer_first_mpls_over_udp);
6709 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6710 outer_first_mpls_over_udp);
6712 case MLX5_FLOW_LAYER_GRE:
6714 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6715 outer_first_mpls_over_gre);
6717 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6718 outer_first_mpls_over_gre);
6721 /* Inner MPLS not over GRE is not supported. */
6724 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6728 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6734 if (out_mpls_m && out_mpls_v) {
6735 *out_mpls_m = *in_mpls_m;
6736 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6741 * Add metadata register item to matcher
6743 * @param[in, out] matcher
6745 * @param[in, out] key
6746 * Flow matcher value.
6747 * @param[in] reg_type
6748 * Type of device metadata register
6755 flow_dv_match_meta_reg(void *matcher, void *key,
6756 enum modify_reg reg_type,
6757 uint32_t data, uint32_t mask)
6760 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6762 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6768 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6769 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6772 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6773 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6777 * The metadata register C0 field might be divided into
6778 * source vport index and META item value, we should set
6779 * this field according to specified mask, not as whole one.
6781 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6783 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6784 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6787 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6790 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6791 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6794 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6795 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6798 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6799 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6802 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6803 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6806 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6807 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6810 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6811 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6814 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6815 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6824 * Add MARK item to matcher
6827 * The device to configure through.
6828 * @param[in, out] matcher
6830 * @param[in, out] key
6831 * Flow matcher value.
6833 * Flow pattern to translate.
6836 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6837 void *matcher, void *key,
6838 const struct rte_flow_item *item)
6840 struct mlx5_priv *priv = dev->data->dev_private;
6841 const struct rte_flow_item_mark *mark;
6845 mark = item->mask ? (const void *)item->mask :
6846 &rte_flow_item_mark_mask;
6847 mask = mark->id & priv->sh->dv_mark_mask;
6848 mark = (const void *)item->spec;
6850 value = mark->id & priv->sh->dv_mark_mask & mask;
6852 enum modify_reg reg;
6854 /* Get the metadata register index for the mark. */
6855 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6856 MLX5_ASSERT(reg > 0);
6857 if (reg == REG_C_0) {
6858 struct mlx5_priv *priv = dev->data->dev_private;
6859 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6860 uint32_t shl_c0 = rte_bsf32(msk_c0);
6866 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6871 * Add META item to matcher
6874 * The devich to configure through.
6875 * @param[in, out] matcher
6877 * @param[in, out] key
6878 * Flow matcher value.
6880 * Attributes of flow that includes this item.
6882 * Flow pattern to translate.
6885 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6886 void *matcher, void *key,
6887 const struct rte_flow_attr *attr,
6888 const struct rte_flow_item *item)
6890 const struct rte_flow_item_meta *meta_m;
6891 const struct rte_flow_item_meta *meta_v;
6893 meta_m = (const void *)item->mask;
6895 meta_m = &rte_flow_item_meta_mask;
6896 meta_v = (const void *)item->spec;
6899 uint32_t value = meta_v->data;
6900 uint32_t mask = meta_m->data;
6902 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6906 * In datapath code there is no endianness
6907 * coversions for perfromance reasons, all
6908 * pattern conversions are done in rte_flow.
6910 value = rte_cpu_to_be_32(value);
6911 mask = rte_cpu_to_be_32(mask);
6912 if (reg == REG_C_0) {
6913 struct mlx5_priv *priv = dev->data->dev_private;
6914 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6915 uint32_t shl_c0 = rte_bsf32(msk_c0);
6916 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6917 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6924 MLX5_ASSERT(msk_c0);
6925 MLX5_ASSERT(!(~msk_c0 & mask));
6927 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6932 * Add vport metadata Reg C0 item to matcher
6934 * @param[in, out] matcher
6936 * @param[in, out] key
6937 * Flow matcher value.
6939 * Flow pattern to translate.
6942 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6943 uint32_t value, uint32_t mask)
6945 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6949 * Add tag item to matcher
6952 * The devich to configure through.
6953 * @param[in, out] matcher
6955 * @param[in, out] key
6956 * Flow matcher value.
6958 * Flow pattern to translate.
6961 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6962 void *matcher, void *key,
6963 const struct rte_flow_item *item)
6965 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6966 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6967 uint32_t mask, value;
6970 value = tag_v->data;
6971 mask = tag_m ? tag_m->data : UINT32_MAX;
6972 if (tag_v->id == REG_C_0) {
6973 struct mlx5_priv *priv = dev->data->dev_private;
6974 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6975 uint32_t shl_c0 = rte_bsf32(msk_c0);
6981 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6985 * Add TAG item to matcher
6988 * The devich to configure through.
6989 * @param[in, out] matcher
6991 * @param[in, out] key
6992 * Flow matcher value.
6994 * Flow pattern to translate.
6997 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6998 void *matcher, void *key,
6999 const struct rte_flow_item *item)
7001 const struct rte_flow_item_tag *tag_v = item->spec;
7002 const struct rte_flow_item_tag *tag_m = item->mask;
7003 enum modify_reg reg;
7006 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7007 /* Get the metadata register index for the tag. */
7008 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7009 MLX5_ASSERT(reg > 0);
7010 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7014 * Add source vport match to the specified matcher.
7016 * @param[in, out] matcher
7018 * @param[in, out] key
7019 * Flow matcher value.
7021 * Source vport value to match
7026 flow_dv_translate_item_source_vport(void *matcher, void *key,
7027 int16_t port, uint16_t mask)
7029 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7030 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7032 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7033 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7037 * Translate port-id item to eswitch match on port-id.
7040 * The devich to configure through.
7041 * @param[in, out] matcher
7043 * @param[in, out] key
7044 * Flow matcher value.
7046 * Flow pattern to translate.
7049 * 0 on success, a negative errno value otherwise.
7052 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7053 void *key, const struct rte_flow_item *item)
7055 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7056 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7057 struct mlx5_priv *priv;
7060 mask = pid_m ? pid_m->id : 0xffff;
7061 id = pid_v ? pid_v->id : dev->data->port_id;
7062 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7065 /* Translate to vport field or to metadata, depending on mode. */
7066 if (priv->vport_meta_mask)
7067 flow_dv_translate_item_meta_vport(matcher, key,
7068 priv->vport_meta_tag,
7069 priv->vport_meta_mask);
7071 flow_dv_translate_item_source_vport(matcher, key,
7072 priv->vport_id, mask);
7077 * Add ICMP6 item to matcher and to the value.
7079 * @param[in, out] matcher
7081 * @param[in, out] key
7082 * Flow matcher value.
7084 * Flow pattern to translate.
7086 * Item is inner pattern.
7089 flow_dv_translate_item_icmp6(void *matcher, void *key,
7090 const struct rte_flow_item *item,
7093 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7094 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7097 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7099 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7101 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7103 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7105 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7107 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7109 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7110 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7114 icmp6_m = &rte_flow_item_icmp6_mask;
7116 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7117 * If only the protocol is specified, no need to match the frag.
7119 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7120 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7121 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7122 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7123 icmp6_v->type & icmp6_m->type);
7124 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7125 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7126 icmp6_v->code & icmp6_m->code);
7130 * Add ICMP item to matcher and to the value.
7132 * @param[in, out] matcher
7134 * @param[in, out] key
7135 * Flow matcher value.
7137 * Flow pattern to translate.
7139 * Item is inner pattern.
7142 flow_dv_translate_item_icmp(void *matcher, void *key,
7143 const struct rte_flow_item *item,
7146 const struct rte_flow_item_icmp *icmp_m = item->mask;
7147 const struct rte_flow_item_icmp *icmp_v = item->spec;
7150 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7152 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7154 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7156 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7158 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7160 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7162 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7163 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7167 icmp_m = &rte_flow_item_icmp_mask;
7169 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7170 * If only the protocol is specified, no need to match the frag.
7172 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7173 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7174 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7175 icmp_m->hdr.icmp_type);
7176 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7177 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7178 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7179 icmp_m->hdr.icmp_code);
7180 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7181 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7185 * Add GTP item to matcher and to the value.
7187 * @param[in, out] matcher
7189 * @param[in, out] key
7190 * Flow matcher value.
7192 * Flow pattern to translate.
7194 * Item is inner pattern.
7197 flow_dv_translate_item_gtp(void *matcher, void *key,
7198 const struct rte_flow_item *item, int inner)
7200 const struct rte_flow_item_gtp *gtp_m = item->mask;
7201 const struct rte_flow_item_gtp *gtp_v = item->spec;
7204 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7206 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7207 uint16_t dport = RTE_GTPU_UDP_PORT;
7210 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7212 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7214 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7216 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7218 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7219 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7225 gtp_m = &rte_flow_item_gtp_mask;
7226 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7227 gtp_m->v_pt_rsv_flags);
7228 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7229 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7230 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7231 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7232 gtp_v->msg_type & gtp_m->msg_type);
7233 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7234 rte_be_to_cpu_32(gtp_m->teid));
7235 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7236 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7239 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7241 #define HEADER_IS_ZERO(match_criteria, headers) \
7242 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7243 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7246 * Calculate flow matcher enable bitmap.
7248 * @param match_criteria
7249 * Pointer to flow matcher criteria.
7252 * Bitmap of enabled fields.
7255 flow_dv_matcher_enable(uint32_t *match_criteria)
7257 uint8_t match_criteria_enable;
7259 match_criteria_enable =
7260 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7261 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7262 match_criteria_enable |=
7263 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7264 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7265 match_criteria_enable |=
7266 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7267 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7268 match_criteria_enable |=
7269 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7270 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7271 match_criteria_enable |=
7272 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7273 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7274 return match_criteria_enable;
7281 * @param[in, out] dev
7282 * Pointer to rte_eth_dev structure.
7283 * @param[in] table_id
7286 * Direction of the table.
7287 * @param[in] transfer
7288 * E-Switch or NIC flow.
7290 * pointer to error structure.
7293 * Returns tables resource based on the index, NULL in case of failed.
7295 static struct mlx5_flow_tbl_resource *
7296 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7297 uint32_t table_id, uint8_t egress,
7299 struct rte_flow_error *error)
7301 struct mlx5_priv *priv = dev->data->dev_private;
7302 struct mlx5_dev_ctx_shared *sh = priv->sh;
7303 struct mlx5_flow_tbl_resource *tbl;
7304 union mlx5_flow_tbl_key table_key = {
7306 .table_id = table_id,
7308 .domain = !!transfer,
7309 .direction = !!egress,
7312 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7314 struct mlx5_flow_tbl_data_entry *tbl_data;
7320 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7322 tbl = &tbl_data->tbl;
7323 rte_atomic32_inc(&tbl->refcnt);
7326 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7328 rte_flow_error_set(error, ENOMEM,
7329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7331 "cannot allocate flow table data entry");
7334 tbl_data->idx = idx;
7335 tbl = &tbl_data->tbl;
7336 pos = &tbl_data->entry;
7338 domain = sh->fdb_domain;
7340 domain = sh->tx_domain;
7342 domain = sh->rx_domain;
7343 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7345 rte_flow_error_set(error, ENOMEM,
7346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7347 NULL, "cannot create flow table object");
7348 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7352 * No multi-threads now, but still better to initialize the reference
7353 * count before insert it into the hash list.
7355 rte_atomic32_init(&tbl->refcnt);
7356 /* Jump action reference count is initialized here. */
7357 rte_atomic32_init(&tbl_data->jump.refcnt);
7358 pos->key = table_key.v64;
7359 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7361 rte_flow_error_set(error, -ret,
7362 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7363 "cannot insert flow table data entry");
7364 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7365 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7367 rte_atomic32_inc(&tbl->refcnt);
7372 * Release a flow table.
7375 * Pointer to rte_eth_dev structure.
7377 * Table resource to be released.
7380 * Returns 0 if table was released, else return 1;
7383 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7384 struct mlx5_flow_tbl_resource *tbl)
7386 struct mlx5_priv *priv = dev->data->dev_private;
7387 struct mlx5_dev_ctx_shared *sh = priv->sh;
7388 struct mlx5_flow_tbl_data_entry *tbl_data =
7389 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7393 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7394 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7396 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7398 /* remove the entry from the hash list and free memory. */
7399 mlx5_hlist_remove(sh->flow_tbls, pos);
7400 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7408 * Register the flow matcher.
7410 * @param[in, out] dev
7411 * Pointer to rte_eth_dev structure.
7412 * @param[in, out] matcher
7413 * Pointer to flow matcher.
7414 * @param[in, out] key
7415 * Pointer to flow table key.
7416 * @parm[in, out] dev_flow
7417 * Pointer to the dev_flow.
7419 * pointer to error structure.
7422 * 0 on success otherwise -errno and errno is set.
7425 flow_dv_matcher_register(struct rte_eth_dev *dev,
7426 struct mlx5_flow_dv_matcher *matcher,
7427 union mlx5_flow_tbl_key *key,
7428 struct mlx5_flow *dev_flow,
7429 struct rte_flow_error *error)
7431 struct mlx5_priv *priv = dev->data->dev_private;
7432 struct mlx5_dev_ctx_shared *sh = priv->sh;
7433 struct mlx5_flow_dv_matcher *cache_matcher;
7434 struct mlx5dv_flow_matcher_attr dv_attr = {
7435 .type = IBV_FLOW_ATTR_NORMAL,
7436 .match_mask = (void *)&matcher->mask,
7438 struct mlx5_flow_tbl_resource *tbl;
7439 struct mlx5_flow_tbl_data_entry *tbl_data;
7441 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7442 key->domain, error);
7444 return -rte_errno; /* No need to refill the error info */
7445 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7446 /* Lookup from cache. */
7447 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7448 if (matcher->crc == cache_matcher->crc &&
7449 matcher->priority == cache_matcher->priority &&
7450 !memcmp((const void *)matcher->mask.buf,
7451 (const void *)cache_matcher->mask.buf,
7452 cache_matcher->mask.size)) {
7454 "%s group %u priority %hd use %s "
7455 "matcher %p: refcnt %d++",
7456 key->domain ? "FDB" : "NIC", key->table_id,
7457 cache_matcher->priority,
7458 key->direction ? "tx" : "rx",
7459 (void *)cache_matcher,
7460 rte_atomic32_read(&cache_matcher->refcnt));
7461 rte_atomic32_inc(&cache_matcher->refcnt);
7462 dev_flow->handle->dvh.matcher = cache_matcher;
7463 /* old matcher should not make the table ref++. */
7464 flow_dv_tbl_resource_release(dev, tbl);
7468 /* Register new matcher. */
7469 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7470 if (!cache_matcher) {
7471 flow_dv_tbl_resource_release(dev, tbl);
7472 return rte_flow_error_set(error, ENOMEM,
7473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7474 "cannot allocate matcher memory");
7476 *cache_matcher = *matcher;
7477 dv_attr.match_criteria_enable =
7478 flow_dv_matcher_enable(cache_matcher->mask.buf);
7479 dv_attr.priority = matcher->priority;
7481 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7482 cache_matcher->matcher_object =
7483 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7484 if (!cache_matcher->matcher_object) {
7485 rte_free(cache_matcher);
7486 #ifdef HAVE_MLX5DV_DR
7487 flow_dv_tbl_resource_release(dev, tbl);
7489 return rte_flow_error_set(error, ENOMEM,
7490 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7491 NULL, "cannot create matcher");
7493 /* Save the table information */
7494 cache_matcher->tbl = tbl;
7495 rte_atomic32_init(&cache_matcher->refcnt);
7496 /* only matcher ref++, table ref++ already done above in get API. */
7497 rte_atomic32_inc(&cache_matcher->refcnt);
7498 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7499 dev_flow->handle->dvh.matcher = cache_matcher;
7500 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7501 key->domain ? "FDB" : "NIC", key->table_id,
7502 cache_matcher->priority,
7503 key->direction ? "tx" : "rx", (void *)cache_matcher,
7504 rte_atomic32_read(&cache_matcher->refcnt));
7509 * Find existing tag resource or create and register a new one.
7511 * @param dev[in, out]
7512 * Pointer to rte_eth_dev structure.
7513 * @param[in, out] tag_be24
7514 * Tag value in big endian then R-shift 8.
7515 * @parm[in, out] dev_flow
7516 * Pointer to the dev_flow.
7518 * pointer to error structure.
7521 * 0 on success otherwise -errno and errno is set.
7524 flow_dv_tag_resource_register
7525 (struct rte_eth_dev *dev,
7527 struct mlx5_flow *dev_flow,
7528 struct rte_flow_error *error)
7530 struct mlx5_priv *priv = dev->data->dev_private;
7531 struct mlx5_dev_ctx_shared *sh = priv->sh;
7532 struct mlx5_flow_dv_tag_resource *cache_resource;
7533 struct mlx5_hlist_entry *entry;
7535 /* Lookup a matching resource from cache. */
7536 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7538 cache_resource = container_of
7539 (entry, struct mlx5_flow_dv_tag_resource, entry);
7540 rte_atomic32_inc(&cache_resource->refcnt);
7541 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7542 dev_flow->dv.tag_resource = cache_resource;
7543 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7544 (void *)cache_resource,
7545 rte_atomic32_read(&cache_resource->refcnt));
7548 /* Register new resource. */
7549 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7550 &dev_flow->handle->dvh.rix_tag);
7551 if (!cache_resource)
7552 return rte_flow_error_set(error, ENOMEM,
7553 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7554 "cannot allocate resource memory");
7555 cache_resource->entry.key = (uint64_t)tag_be24;
7556 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7557 if (!cache_resource->action) {
7558 rte_free(cache_resource);
7559 return rte_flow_error_set(error, ENOMEM,
7560 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7561 NULL, "cannot create action");
7563 rte_atomic32_init(&cache_resource->refcnt);
7564 rte_atomic32_inc(&cache_resource->refcnt);
7565 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7566 mlx5_glue->destroy_flow_action(cache_resource->action);
7567 rte_free(cache_resource);
7568 return rte_flow_error_set(error, EEXIST,
7569 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7570 NULL, "cannot insert tag");
7572 dev_flow->dv.tag_resource = cache_resource;
7573 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7574 (void *)cache_resource,
7575 rte_atomic32_read(&cache_resource->refcnt));
7583 * Pointer to Ethernet device.
7588 * 1 while a reference on it exists, 0 when freed.
7591 flow_dv_tag_release(struct rte_eth_dev *dev,
7594 struct mlx5_priv *priv = dev->data->dev_private;
7595 struct mlx5_dev_ctx_shared *sh = priv->sh;
7596 struct mlx5_flow_dv_tag_resource *tag;
7598 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7601 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7602 dev->data->port_id, (void *)tag,
7603 rte_atomic32_read(&tag->refcnt));
7604 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7605 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7606 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7607 DRV_LOG(DEBUG, "port %u tag %p: removed",
7608 dev->data->port_id, (void *)tag);
7609 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7616 * Translate port ID action to vport.
7619 * Pointer to rte_eth_dev structure.
7621 * Pointer to the port ID action.
7622 * @param[out] dst_port_id
7623 * The target port ID.
7625 * Pointer to the error structure.
7628 * 0 on success, a negative errno value otherwise and rte_errno is set.
7631 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7632 const struct rte_flow_action *action,
7633 uint32_t *dst_port_id,
7634 struct rte_flow_error *error)
7637 struct mlx5_priv *priv;
7638 const struct rte_flow_action_port_id *conf =
7639 (const struct rte_flow_action_port_id *)action->conf;
7641 port = conf->original ? dev->data->port_id : conf->id;
7642 priv = mlx5_port_to_eswitch_info(port, false);
7644 return rte_flow_error_set(error, -rte_errno,
7645 RTE_FLOW_ERROR_TYPE_ACTION,
7647 "No eswitch info was found for port");
7648 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7650 * This parameter is transferred to
7651 * mlx5dv_dr_action_create_dest_ib_port().
7653 *dst_port_id = priv->dev_port;
7656 * Legacy mode, no LAG configurations is supported.
7657 * This parameter is transferred to
7658 * mlx5dv_dr_action_create_dest_vport().
7660 *dst_port_id = priv->vport_id;
7666 * Create a counter with aging configuration.
7669 * Pointer to rte_eth_dev structure.
7671 * Pointer to the counter action configuration.
7673 * Pointer to the aging action configuration.
7676 * Index to flow counter on success, 0 otherwise.
7679 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7680 struct mlx5_flow *dev_flow,
7681 const struct rte_flow_action_count *count,
7682 const struct rte_flow_action_age *age)
7685 struct mlx5_age_param *age_param;
7687 counter = flow_dv_counter_alloc(dev,
7688 count ? count->shared : 0,
7689 count ? count->id : 0,
7690 dev_flow->dv.group, !!age);
7691 if (!counter || age == NULL)
7693 age_param = flow_dv_counter_idx_get_age(dev, counter);
7695 * The counter age accuracy may have a bit delay. Have 3/4
7696 * second bias on the timeount in order to let it age in time.
7698 age_param->context = age->context ? age->context :
7699 (void *)(uintptr_t)(dev_flow->flow_idx);
7701 * The counter age accuracy may have a bit delay. Have 3/4
7702 * second bias on the timeount in order to let it age in time.
7704 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7705 /* Set expire time in unit of 0.1 sec. */
7706 age_param->port_id = dev->data->port_id;
7707 age_param->expire = age_param->timeout +
7708 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7709 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7713 * Add Tx queue matcher
7716 * Pointer to the dev struct.
7717 * @param[in, out] matcher
7719 * @param[in, out] key
7720 * Flow matcher value.
7722 * Flow pattern to translate.
7724 * Item is inner pattern.
7727 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7728 void *matcher, void *key,
7729 const struct rte_flow_item *item)
7731 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7732 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7734 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7736 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7737 struct mlx5_txq_ctrl *txq;
7741 queue_m = (const void *)item->mask;
7744 queue_v = (const void *)item->spec;
7747 txq = mlx5_txq_get(dev, queue_v->queue);
7750 queue = txq->obj->sq->id;
7751 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7752 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7753 queue & queue_m->queue);
7754 mlx5_txq_release(dev, queue_v->queue);
7758 * Set the hash fields according to the @p flow information.
7760 * @param[in] dev_flow
7761 * Pointer to the mlx5_flow.
7762 * @param[in] rss_desc
7763 * Pointer to the mlx5_flow_rss_desc.
7766 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7767 struct mlx5_flow_rss_desc *rss_desc)
7769 uint64_t items = dev_flow->handle->layers;
7771 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7773 dev_flow->hash_fields = 0;
7774 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7775 if (rss_desc->level >= 2) {
7776 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7780 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7781 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7782 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7783 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7784 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7785 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7786 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7788 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7790 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7791 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7792 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7793 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7794 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7795 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7796 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7798 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7801 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7802 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7803 if (rss_types & ETH_RSS_UDP) {
7804 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7805 dev_flow->hash_fields |=
7806 IBV_RX_HASH_SRC_PORT_UDP;
7807 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7808 dev_flow->hash_fields |=
7809 IBV_RX_HASH_DST_PORT_UDP;
7811 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7813 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7814 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7815 if (rss_types & ETH_RSS_TCP) {
7816 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7817 dev_flow->hash_fields |=
7818 IBV_RX_HASH_SRC_PORT_TCP;
7819 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7820 dev_flow->hash_fields |=
7821 IBV_RX_HASH_DST_PORT_TCP;
7823 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7829 * Fill the flow with DV spec, lock free
7830 * (mutex should be acquired by caller).
7833 * Pointer to rte_eth_dev structure.
7834 * @param[in, out] dev_flow
7835 * Pointer to the sub flow.
7837 * Pointer to the flow attributes.
7839 * Pointer to the list of items.
7840 * @param[in] actions
7841 * Pointer to the list of actions.
7843 * Pointer to the error structure.
7846 * 0 on success, a negative errno value otherwise and rte_errno is set.
7849 __flow_dv_translate(struct rte_eth_dev *dev,
7850 struct mlx5_flow *dev_flow,
7851 const struct rte_flow_attr *attr,
7852 const struct rte_flow_item items[],
7853 const struct rte_flow_action actions[],
7854 struct rte_flow_error *error)
7856 struct mlx5_priv *priv = dev->data->dev_private;
7857 struct mlx5_dev_config *dev_conf = &priv->config;
7858 struct rte_flow *flow = dev_flow->flow;
7859 struct mlx5_flow_handle *handle = dev_flow->handle;
7860 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7862 [!!priv->flow_nested_idx];
7863 uint64_t item_flags = 0;
7864 uint64_t last_item = 0;
7865 uint64_t action_flags = 0;
7866 uint64_t priority = attr->priority;
7867 struct mlx5_flow_dv_matcher matcher = {
7869 .size = sizeof(matcher.mask.buf),
7873 bool actions_end = false;
7875 struct mlx5_flow_dv_modify_hdr_resource res;
7876 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7877 sizeof(struct mlx5_modification_cmd) *
7878 (MLX5_MAX_MODIFY_NUM + 1)];
7880 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7881 const struct rte_flow_action_count *count = NULL;
7882 const struct rte_flow_action_age *age = NULL;
7883 union flow_dv_attr flow_attr = { .attr = 0 };
7885 union mlx5_flow_tbl_key tbl_key;
7886 uint32_t modify_action_position = UINT32_MAX;
7887 void *match_mask = matcher.mask.buf;
7888 void *match_value = dev_flow->dv.value.buf;
7889 uint8_t next_protocol = 0xff;
7890 struct rte_vlan_hdr vlan = { 0 };
7894 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7895 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7896 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7897 !!priv->fdb_def_rule, &table, error);
7900 dev_flow->dv.group = table;
7902 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7903 if (priority == MLX5_FLOW_PRIO_RSVD)
7904 priority = dev_conf->flow_prio - 1;
7905 /* number of actions must be set to 0 in case of dirty stack. */
7906 mhdr_res->actions_num = 0;
7907 for (; !actions_end ; actions++) {
7908 const struct rte_flow_action_queue *queue;
7909 const struct rte_flow_action_rss *rss;
7910 const struct rte_flow_action *action = actions;
7911 const uint8_t *rss_key;
7912 const struct rte_flow_action_jump *jump_data;
7913 const struct rte_flow_action_meter *mtr;
7914 struct mlx5_flow_tbl_resource *tbl;
7915 uint32_t port_id = 0;
7916 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7917 int action_type = actions->type;
7918 const struct rte_flow_action *found_action = NULL;
7919 struct mlx5_flow_meter *fm = NULL;
7921 if (!mlx5_flow_os_action_supported(action_type))
7922 return rte_flow_error_set(error, ENOTSUP,
7923 RTE_FLOW_ERROR_TYPE_ACTION,
7925 "action not supported");
7926 switch (action_type) {
7927 case RTE_FLOW_ACTION_TYPE_VOID:
7929 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7930 if (flow_dv_translate_action_port_id(dev, action,
7933 port_id_resource.port_id = port_id;
7934 MLX5_ASSERT(!handle->rix_port_id_action);
7935 if (flow_dv_port_id_action_resource_register
7936 (dev, &port_id_resource, dev_flow, error))
7938 dev_flow->dv.actions[actions_n++] =
7939 dev_flow->dv.port_id_action->action;
7940 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7941 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7943 case RTE_FLOW_ACTION_TYPE_FLAG:
7944 action_flags |= MLX5_FLOW_ACTION_FLAG;
7945 dev_flow->handle->mark = 1;
7946 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7947 struct rte_flow_action_mark mark = {
7948 .id = MLX5_FLOW_MARK_DEFAULT,
7951 if (flow_dv_convert_action_mark(dev, &mark,
7955 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7958 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7960 * Only one FLAG or MARK is supported per device flow
7961 * right now. So the pointer to the tag resource must be
7962 * zero before the register process.
7964 MLX5_ASSERT(!handle->dvh.rix_tag);
7965 if (flow_dv_tag_resource_register(dev, tag_be,
7968 MLX5_ASSERT(dev_flow->dv.tag_resource);
7969 dev_flow->dv.actions[actions_n++] =
7970 dev_flow->dv.tag_resource->action;
7972 case RTE_FLOW_ACTION_TYPE_MARK:
7973 action_flags |= MLX5_FLOW_ACTION_MARK;
7974 dev_flow->handle->mark = 1;
7975 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7976 const struct rte_flow_action_mark *mark =
7977 (const struct rte_flow_action_mark *)
7980 if (flow_dv_convert_action_mark(dev, mark,
7984 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7988 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7989 /* Legacy (non-extensive) MARK action. */
7990 tag_be = mlx5_flow_mark_set
7991 (((const struct rte_flow_action_mark *)
7992 (actions->conf))->id);
7993 MLX5_ASSERT(!handle->dvh.rix_tag);
7994 if (flow_dv_tag_resource_register(dev, tag_be,
7997 MLX5_ASSERT(dev_flow->dv.tag_resource);
7998 dev_flow->dv.actions[actions_n++] =
7999 dev_flow->dv.tag_resource->action;
8001 case RTE_FLOW_ACTION_TYPE_SET_META:
8002 if (flow_dv_convert_action_set_meta
8003 (dev, mhdr_res, attr,
8004 (const struct rte_flow_action_set_meta *)
8005 actions->conf, error))
8007 action_flags |= MLX5_FLOW_ACTION_SET_META;
8009 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8010 if (flow_dv_convert_action_set_tag
8012 (const struct rte_flow_action_set_tag *)
8013 actions->conf, error))
8015 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8017 case RTE_FLOW_ACTION_TYPE_DROP:
8018 action_flags |= MLX5_FLOW_ACTION_DROP;
8019 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8021 case RTE_FLOW_ACTION_TYPE_QUEUE:
8022 queue = actions->conf;
8023 rss_desc->queue_num = 1;
8024 rss_desc->queue[0] = queue->index;
8025 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8026 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8028 case RTE_FLOW_ACTION_TYPE_RSS:
8029 rss = actions->conf;
8030 memcpy(rss_desc->queue, rss->queue,
8031 rss->queue_num * sizeof(uint16_t));
8032 rss_desc->queue_num = rss->queue_num;
8033 /* NULL RSS key indicates default RSS key. */
8034 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8035 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8037 * rss->level and rss.types should be set in advance
8038 * when expanding items for RSS.
8040 action_flags |= MLX5_FLOW_ACTION_RSS;
8041 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8043 case RTE_FLOW_ACTION_TYPE_AGE:
8044 case RTE_FLOW_ACTION_TYPE_COUNT:
8045 if (!dev_conf->devx) {
8046 return rte_flow_error_set
8048 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8050 "count action not supported");
8052 /* Save information first, will apply later. */
8053 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8054 count = action->conf;
8057 action_flags |= MLX5_FLOW_ACTION_COUNT;
8059 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8060 dev_flow->dv.actions[actions_n++] =
8061 priv->sh->pop_vlan_action;
8062 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8064 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8065 if (!(action_flags &
8066 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8067 flow_dev_get_vlan_info_from_items(items, &vlan);
8068 vlan.eth_proto = rte_be_to_cpu_16
8069 ((((const struct rte_flow_action_of_push_vlan *)
8070 actions->conf)->ethertype));
8071 found_action = mlx5_flow_find_action
8073 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8075 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8076 found_action = mlx5_flow_find_action
8078 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8080 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8081 if (flow_dv_create_action_push_vlan
8082 (dev, attr, &vlan, dev_flow, error))
8084 dev_flow->dv.actions[actions_n++] =
8085 dev_flow->dv.push_vlan_res->action;
8086 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8088 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8089 /* of_vlan_push action handled this action */
8090 MLX5_ASSERT(action_flags &
8091 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8093 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8094 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8096 flow_dev_get_vlan_info_from_items(items, &vlan);
8097 mlx5_update_vlan_vid_pcp(actions, &vlan);
8098 /* If no VLAN push - this is a modify header action */
8099 if (flow_dv_convert_action_modify_vlan_vid
8100 (mhdr_res, actions, error))
8102 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8104 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8105 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8106 if (flow_dv_create_action_l2_encap(dev, actions,
8111 dev_flow->dv.actions[actions_n++] =
8112 dev_flow->dv.encap_decap->action;
8113 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8115 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8116 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8117 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8121 dev_flow->dv.actions[actions_n++] =
8122 dev_flow->dv.encap_decap->action;
8123 action_flags |= MLX5_FLOW_ACTION_DECAP;
8125 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8126 /* Handle encap with preceding decap. */
8127 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8128 if (flow_dv_create_action_raw_encap
8129 (dev, actions, dev_flow, attr, error))
8131 dev_flow->dv.actions[actions_n++] =
8132 dev_flow->dv.encap_decap->action;
8134 /* Handle encap without preceding decap. */
8135 if (flow_dv_create_action_l2_encap
8136 (dev, actions, dev_flow, attr->transfer,
8139 dev_flow->dv.actions[actions_n++] =
8140 dev_flow->dv.encap_decap->action;
8142 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8144 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8145 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8147 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8148 if (flow_dv_create_action_l2_decap
8149 (dev, dev_flow, attr->transfer, error))
8151 dev_flow->dv.actions[actions_n++] =
8152 dev_flow->dv.encap_decap->action;
8154 /* If decap is followed by encap, handle it at encap. */
8155 action_flags |= MLX5_FLOW_ACTION_DECAP;
8157 case RTE_FLOW_ACTION_TYPE_JUMP:
8158 jump_data = action->conf;
8159 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8161 !!priv->fdb_def_rule,
8165 tbl = flow_dv_tbl_resource_get(dev, table,
8167 attr->transfer, error);
8169 return rte_flow_error_set
8171 RTE_FLOW_ERROR_TYPE_ACTION,
8173 "cannot create jump action.");
8174 if (flow_dv_jump_tbl_resource_register
8175 (dev, tbl, dev_flow, error)) {
8176 flow_dv_tbl_resource_release(dev, tbl);
8177 return rte_flow_error_set
8179 RTE_FLOW_ERROR_TYPE_ACTION,
8181 "cannot create jump action.");
8183 dev_flow->dv.actions[actions_n++] =
8184 dev_flow->dv.jump->action;
8185 action_flags |= MLX5_FLOW_ACTION_JUMP;
8186 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8188 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8189 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8190 if (flow_dv_convert_action_modify_mac
8191 (mhdr_res, actions, error))
8193 action_flags |= actions->type ==
8194 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8195 MLX5_FLOW_ACTION_SET_MAC_SRC :
8196 MLX5_FLOW_ACTION_SET_MAC_DST;
8198 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8199 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8200 if (flow_dv_convert_action_modify_ipv4
8201 (mhdr_res, actions, error))
8203 action_flags |= actions->type ==
8204 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8205 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8206 MLX5_FLOW_ACTION_SET_IPV4_DST;
8208 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8209 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8210 if (flow_dv_convert_action_modify_ipv6
8211 (mhdr_res, actions, error))
8213 action_flags |= actions->type ==
8214 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8215 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8216 MLX5_FLOW_ACTION_SET_IPV6_DST;
8218 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8219 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8220 if (flow_dv_convert_action_modify_tp
8221 (mhdr_res, actions, items,
8222 &flow_attr, dev_flow, !!(action_flags &
8223 MLX5_FLOW_ACTION_DECAP), error))
8225 action_flags |= actions->type ==
8226 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8227 MLX5_FLOW_ACTION_SET_TP_SRC :
8228 MLX5_FLOW_ACTION_SET_TP_DST;
8230 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8231 if (flow_dv_convert_action_modify_dec_ttl
8232 (mhdr_res, items, &flow_attr, dev_flow,
8234 MLX5_FLOW_ACTION_DECAP), error))
8236 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8238 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8239 if (flow_dv_convert_action_modify_ttl
8240 (mhdr_res, actions, items, &flow_attr,
8241 dev_flow, !!(action_flags &
8242 MLX5_FLOW_ACTION_DECAP), error))
8244 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8246 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8247 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8248 if (flow_dv_convert_action_modify_tcp_seq
8249 (mhdr_res, actions, error))
8251 action_flags |= actions->type ==
8252 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8253 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8254 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8257 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8258 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8259 if (flow_dv_convert_action_modify_tcp_ack
8260 (mhdr_res, actions, error))
8262 action_flags |= actions->type ==
8263 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8264 MLX5_FLOW_ACTION_INC_TCP_ACK :
8265 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8267 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8268 if (flow_dv_convert_action_set_reg
8269 (mhdr_res, actions, error))
8271 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8273 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8274 if (flow_dv_convert_action_copy_mreg
8275 (dev, mhdr_res, actions, error))
8277 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8279 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8280 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8281 dev_flow->handle->fate_action =
8282 MLX5_FLOW_FATE_DEFAULT_MISS;
8284 case RTE_FLOW_ACTION_TYPE_METER:
8285 mtr = actions->conf;
8287 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8290 return rte_flow_error_set(error,
8292 RTE_FLOW_ERROR_TYPE_ACTION,
8295 "or invalid parameters");
8296 flow->meter = fm->idx;
8298 /* Set the meter action. */
8300 fm = mlx5_ipool_get(priv->sh->ipool
8301 [MLX5_IPOOL_MTR], flow->meter);
8303 return rte_flow_error_set(error,
8305 RTE_FLOW_ERROR_TYPE_ACTION,
8308 "or invalid parameters");
8310 dev_flow->dv.actions[actions_n++] =
8311 fm->mfts->meter_action;
8312 action_flags |= MLX5_FLOW_ACTION_METER;
8314 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8315 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8318 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8320 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8321 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8324 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8326 case RTE_FLOW_ACTION_TYPE_END:
8328 if (mhdr_res->actions_num) {
8329 /* create modify action if needed. */
8330 if (flow_dv_modify_hdr_resource_register
8331 (dev, mhdr_res, dev_flow, error))
8333 dev_flow->dv.actions[modify_action_position] =
8334 handle->dvh.modify_hdr->action;
8336 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8338 flow_dv_translate_create_counter(dev,
8339 dev_flow, count, age);
8342 return rte_flow_error_set
8344 RTE_FLOW_ERROR_TYPE_ACTION,
8346 "cannot create counter"
8348 dev_flow->dv.actions[actions_n++] =
8349 (flow_dv_counter_get_by_idx(dev,
8350 flow->counter, NULL))->action;
8356 if (mhdr_res->actions_num &&
8357 modify_action_position == UINT32_MAX)
8358 modify_action_position = actions_n++;
8360 dev_flow->dv.actions_n = actions_n;
8361 dev_flow->act_flags = action_flags;
8362 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8363 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8364 int item_type = items->type;
8366 if (!mlx5_flow_os_item_supported(item_type))
8367 return rte_flow_error_set(error, ENOTSUP,
8368 RTE_FLOW_ERROR_TYPE_ITEM,
8369 NULL, "item not supported");
8370 switch (item_type) {
8371 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8372 flow_dv_translate_item_port_id(dev, match_mask,
8373 match_value, items);
8374 last_item = MLX5_FLOW_ITEM_PORT_ID;
8376 case RTE_FLOW_ITEM_TYPE_ETH:
8377 flow_dv_translate_item_eth(match_mask, match_value,
8379 dev_flow->dv.group);
8380 matcher.priority = action_flags &
8381 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8382 !dev_flow->external ?
8383 MLX5_PRIORITY_MAP_L3 :
8384 MLX5_PRIORITY_MAP_L2;
8385 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8386 MLX5_FLOW_LAYER_OUTER_L2;
8388 case RTE_FLOW_ITEM_TYPE_VLAN:
8389 flow_dv_translate_item_vlan(dev_flow,
8390 match_mask, match_value,
8392 dev_flow->dv.group);
8393 matcher.priority = MLX5_PRIORITY_MAP_L2;
8394 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8395 MLX5_FLOW_LAYER_INNER_VLAN) :
8396 (MLX5_FLOW_LAYER_OUTER_L2 |
8397 MLX5_FLOW_LAYER_OUTER_VLAN);
8399 case RTE_FLOW_ITEM_TYPE_IPV4:
8400 mlx5_flow_tunnel_ip_check(items, next_protocol,
8401 &item_flags, &tunnel);
8402 flow_dv_translate_item_ipv4(match_mask, match_value,
8403 items, item_flags, tunnel,
8404 dev_flow->dv.group);
8405 matcher.priority = MLX5_PRIORITY_MAP_L3;
8406 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8407 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8408 if (items->mask != NULL &&
8409 ((const struct rte_flow_item_ipv4 *)
8410 items->mask)->hdr.next_proto_id) {
8412 ((const struct rte_flow_item_ipv4 *)
8413 (items->spec))->hdr.next_proto_id;
8415 ((const struct rte_flow_item_ipv4 *)
8416 (items->mask))->hdr.next_proto_id;
8418 /* Reset for inner layer. */
8419 next_protocol = 0xff;
8422 case RTE_FLOW_ITEM_TYPE_IPV6:
8423 mlx5_flow_tunnel_ip_check(items, next_protocol,
8424 &item_flags, &tunnel);
8425 flow_dv_translate_item_ipv6(match_mask, match_value,
8426 items, item_flags, tunnel,
8427 dev_flow->dv.group);
8428 matcher.priority = MLX5_PRIORITY_MAP_L3;
8429 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8430 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8431 if (items->mask != NULL &&
8432 ((const struct rte_flow_item_ipv6 *)
8433 items->mask)->hdr.proto) {
8435 ((const struct rte_flow_item_ipv6 *)
8436 items->spec)->hdr.proto;
8438 ((const struct rte_flow_item_ipv6 *)
8439 items->mask)->hdr.proto;
8441 /* Reset for inner layer. */
8442 next_protocol = 0xff;
8445 case RTE_FLOW_ITEM_TYPE_TCP:
8446 flow_dv_translate_item_tcp(match_mask, match_value,
8448 matcher.priority = MLX5_PRIORITY_MAP_L4;
8449 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8450 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8452 case RTE_FLOW_ITEM_TYPE_UDP:
8453 flow_dv_translate_item_udp(match_mask, match_value,
8455 matcher.priority = MLX5_PRIORITY_MAP_L4;
8456 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8457 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8459 case RTE_FLOW_ITEM_TYPE_GRE:
8460 flow_dv_translate_item_gre(match_mask, match_value,
8462 matcher.priority = rss_desc->level >= 2 ?
8463 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8464 last_item = MLX5_FLOW_LAYER_GRE;
8466 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8467 flow_dv_translate_item_gre_key(match_mask,
8468 match_value, items);
8469 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8471 case RTE_FLOW_ITEM_TYPE_NVGRE:
8472 flow_dv_translate_item_nvgre(match_mask, match_value,
8474 matcher.priority = rss_desc->level >= 2 ?
8475 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8476 last_item = MLX5_FLOW_LAYER_GRE;
8478 case RTE_FLOW_ITEM_TYPE_VXLAN:
8479 flow_dv_translate_item_vxlan(match_mask, match_value,
8481 matcher.priority = rss_desc->level >= 2 ?
8482 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8483 last_item = MLX5_FLOW_LAYER_VXLAN;
8485 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8486 flow_dv_translate_item_vxlan_gpe(match_mask,
8489 matcher.priority = rss_desc->level >= 2 ?
8490 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8491 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8493 case RTE_FLOW_ITEM_TYPE_GENEVE:
8494 flow_dv_translate_item_geneve(match_mask, match_value,
8496 matcher.priority = rss_desc->level >= 2 ?
8497 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8498 last_item = MLX5_FLOW_LAYER_GENEVE;
8500 case RTE_FLOW_ITEM_TYPE_MPLS:
8501 flow_dv_translate_item_mpls(match_mask, match_value,
8502 items, last_item, tunnel);
8503 matcher.priority = rss_desc->level >= 2 ?
8504 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8505 last_item = MLX5_FLOW_LAYER_MPLS;
8507 case RTE_FLOW_ITEM_TYPE_MARK:
8508 flow_dv_translate_item_mark(dev, match_mask,
8509 match_value, items);
8510 last_item = MLX5_FLOW_ITEM_MARK;
8512 case RTE_FLOW_ITEM_TYPE_META:
8513 flow_dv_translate_item_meta(dev, match_mask,
8514 match_value, attr, items);
8515 last_item = MLX5_FLOW_ITEM_METADATA;
8517 case RTE_FLOW_ITEM_TYPE_ICMP:
8518 flow_dv_translate_item_icmp(match_mask, match_value,
8520 last_item = MLX5_FLOW_LAYER_ICMP;
8522 case RTE_FLOW_ITEM_TYPE_ICMP6:
8523 flow_dv_translate_item_icmp6(match_mask, match_value,
8525 last_item = MLX5_FLOW_LAYER_ICMP6;
8527 case RTE_FLOW_ITEM_TYPE_TAG:
8528 flow_dv_translate_item_tag(dev, match_mask,
8529 match_value, items);
8530 last_item = MLX5_FLOW_ITEM_TAG;
8532 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8533 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8534 match_value, items);
8535 last_item = MLX5_FLOW_ITEM_TAG;
8537 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8538 flow_dv_translate_item_tx_queue(dev, match_mask,
8541 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8543 case RTE_FLOW_ITEM_TYPE_GTP:
8544 flow_dv_translate_item_gtp(match_mask, match_value,
8546 matcher.priority = rss_desc->level >= 2 ?
8547 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8548 last_item = MLX5_FLOW_LAYER_GTP;
8553 item_flags |= last_item;
8556 * When E-Switch mode is enabled, we have two cases where we need to
8557 * set the source port manually.
8558 * The first one, is in case of Nic steering rule, and the second is
8559 * E-Switch rule where no port_id item was found. In both cases
8560 * the source port is set according the current port in use.
8562 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8563 (priv->representor || priv->master)) {
8564 if (flow_dv_translate_item_port_id(dev, match_mask,
8568 #ifdef RTE_LIBRTE_MLX5_DEBUG
8569 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8570 dev_flow->dv.value.buf));
8573 * Layers may be already initialized from prefix flow if this dev_flow
8574 * is the suffix flow.
8576 handle->layers |= item_flags;
8577 if (action_flags & MLX5_FLOW_ACTION_RSS)
8578 flow_dv_hashfields_set(dev_flow, rss_desc);
8579 /* Register matcher. */
8580 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8582 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8584 /* reserved field no needs to be set to 0 here. */
8585 tbl_key.domain = attr->transfer;
8586 tbl_key.direction = attr->egress;
8587 tbl_key.table_id = dev_flow->dv.group;
8588 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8594 * Apply the flow to the NIC, lock free,
8595 * (mutex should be acquired by caller).
8598 * Pointer to the Ethernet device structure.
8599 * @param[in, out] flow
8600 * Pointer to flow structure.
8602 * Pointer to error structure.
8605 * 0 on success, a negative errno value otherwise and rte_errno is set.
8608 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8609 struct rte_flow_error *error)
8611 struct mlx5_flow_dv_workspace *dv;
8612 struct mlx5_flow_handle *dh;
8613 struct mlx5_flow_handle_dv *dv_h;
8614 struct mlx5_flow *dev_flow;
8615 struct mlx5_priv *priv = dev->data->dev_private;
8616 uint32_t handle_idx;
8621 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8622 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8624 dh = dev_flow->handle;
8627 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8629 dv->actions[n++] = priv->sh->esw_drop_action;
8631 struct mlx5_hrxq *drop_hrxq;
8632 drop_hrxq = mlx5_hrxq_drop_new(dev);
8636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8638 "cannot get drop hash queue");
8642 * Drop queues will be released by the specify
8643 * mlx5_hrxq_drop_release() function. Assign
8644 * the special index to hrxq to mark the queue
8645 * has been allocated.
8647 dh->rix_hrxq = UINT32_MAX;
8648 dv->actions[n++] = drop_hrxq->action;
8650 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8651 struct mlx5_hrxq *hrxq;
8653 struct mlx5_flow_rss_desc *rss_desc =
8654 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8655 [!!priv->flow_nested_idx];
8657 MLX5_ASSERT(rss_desc->queue_num);
8658 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8659 MLX5_RSS_HASH_KEY_LEN,
8660 dev_flow->hash_fields,
8662 rss_desc->queue_num);
8664 hrxq_idx = mlx5_hrxq_new
8665 (dev, rss_desc->key,
8666 MLX5_RSS_HASH_KEY_LEN,
8667 dev_flow->hash_fields,
8669 rss_desc->queue_num,
8671 MLX5_FLOW_LAYER_TUNNEL));
8673 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8678 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8679 "cannot get hash queue");
8682 dh->rix_hrxq = hrxq_idx;
8683 dv->actions[n++] = hrxq->action;
8684 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8685 if (flow_dv_default_miss_resource_register
8689 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8690 "cannot create default miss resource");
8691 goto error_default_miss;
8693 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8694 dv->actions[n++] = priv->sh->default_miss.action;
8697 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8698 (void *)&dv->value, n,
8700 if (!dh->drv_flow) {
8701 rte_flow_error_set(error, errno,
8702 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8704 "hardware refuses to create flow");
8707 if (priv->vmwa_context &&
8708 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8710 * The rule contains the VLAN pattern.
8711 * For VF we are going to create VLAN
8712 * interface to make hypervisor set correct
8713 * e-Switch vport context.
8715 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8720 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8721 flow_dv_default_miss_resource_release(dev);
8723 err = rte_errno; /* Save rte_errno before cleanup. */
8724 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8725 handle_idx, dh, next) {
8726 /* hrxq is union, don't clear it if the flag is not set. */
8728 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8729 mlx5_hrxq_drop_release(dev);
8731 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8732 mlx5_hrxq_release(dev, dh->rix_hrxq);
8736 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8737 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8739 rte_errno = err; /* Restore rte_errno. */
8744 * Release the flow matcher.
8747 * Pointer to Ethernet device.
8749 * Pointer to mlx5_flow_handle.
8752 * 1 while a reference on it exists, 0 when freed.
8755 flow_dv_matcher_release(struct rte_eth_dev *dev,
8756 struct mlx5_flow_handle *handle)
8758 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8760 MLX5_ASSERT(matcher->matcher_object);
8761 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8762 dev->data->port_id, (void *)matcher,
8763 rte_atomic32_read(&matcher->refcnt));
8764 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8765 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8766 (matcher->matcher_object));
8767 LIST_REMOVE(matcher, next);
8768 /* table ref-- in release interface. */
8769 flow_dv_tbl_resource_release(dev, matcher->tbl);
8771 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8772 dev->data->port_id, (void *)matcher);
8779 * Release an encap/decap resource.
8782 * Pointer to Ethernet device.
8784 * Pointer to mlx5_flow_handle.
8787 * 1 while a reference on it exists, 0 when freed.
8790 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8791 struct mlx5_flow_handle *handle)
8793 struct mlx5_priv *priv = dev->data->dev_private;
8794 uint32_t idx = handle->dvh.rix_encap_decap;
8795 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8797 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8799 if (!cache_resource)
8801 MLX5_ASSERT(cache_resource->action);
8802 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8803 (void *)cache_resource,
8804 rte_atomic32_read(&cache_resource->refcnt));
8805 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8806 claim_zero(mlx5_glue->destroy_flow_action
8807 (cache_resource->action));
8808 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8809 &priv->sh->encaps_decaps, idx,
8810 cache_resource, next);
8811 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8812 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8813 (void *)cache_resource);
8820 * Release an jump to table action resource.
8823 * Pointer to Ethernet device.
8825 * Pointer to mlx5_flow_handle.
8828 * 1 while a reference on it exists, 0 when freed.
8831 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8832 struct mlx5_flow_handle *handle)
8834 struct mlx5_priv *priv = dev->data->dev_private;
8835 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8836 struct mlx5_flow_tbl_data_entry *tbl_data;
8838 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8842 cache_resource = &tbl_data->jump;
8843 MLX5_ASSERT(cache_resource->action);
8844 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8845 (void *)cache_resource,
8846 rte_atomic32_read(&cache_resource->refcnt));
8847 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8848 claim_zero(mlx5_glue->destroy_flow_action
8849 (cache_resource->action));
8850 /* jump action memory free is inside the table release. */
8851 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8852 DRV_LOG(DEBUG, "jump table resource %p: removed",
8853 (void *)cache_resource);
8860 * Release a default miss resource.
8863 * Pointer to Ethernet device.
8865 * 1 while a reference on it exists, 0 when freed.
8868 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
8870 struct mlx5_priv *priv = dev->data->dev_private;
8871 struct mlx5_dev_ctx_shared *sh = priv->sh;
8872 struct mlx5_flow_default_miss_resource *cache_resource =
8875 MLX5_ASSERT(cache_resource->action);
8876 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
8877 (void *)cache_resource->action,
8878 rte_atomic32_read(&cache_resource->refcnt));
8879 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8880 claim_zero(mlx5_glue->destroy_flow_action
8881 (cache_resource->action));
8882 DRV_LOG(DEBUG, "default miss resource %p: removed",
8883 (void *)cache_resource->action);
8890 * Release a modify-header resource.
8893 * Pointer to mlx5_flow_handle.
8896 * 1 while a reference on it exists, 0 when freed.
8899 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8901 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8902 handle->dvh.modify_hdr;
8904 MLX5_ASSERT(cache_resource->action);
8905 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8906 (void *)cache_resource,
8907 rte_atomic32_read(&cache_resource->refcnt));
8908 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8909 claim_zero(mlx5_glue->destroy_flow_action
8910 (cache_resource->action));
8911 LIST_REMOVE(cache_resource, next);
8912 rte_free(cache_resource);
8913 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8914 (void *)cache_resource);
8921 * Release port ID action resource.
8924 * Pointer to Ethernet device.
8926 * Pointer to mlx5_flow_handle.
8929 * 1 while a reference on it exists, 0 when freed.
8932 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8933 struct mlx5_flow_handle *handle)
8935 struct mlx5_priv *priv = dev->data->dev_private;
8936 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8937 uint32_t idx = handle->rix_port_id_action;
8939 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8941 if (!cache_resource)
8943 MLX5_ASSERT(cache_resource->action);
8944 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8945 (void *)cache_resource,
8946 rte_atomic32_read(&cache_resource->refcnt));
8947 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8948 claim_zero(mlx5_glue->destroy_flow_action
8949 (cache_resource->action));
8950 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8951 &priv->sh->port_id_action_list, idx,
8952 cache_resource, next);
8953 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8954 DRV_LOG(DEBUG, "port id action resource %p: removed",
8955 (void *)cache_resource);
8962 * Release push vlan action resource.
8965 * Pointer to Ethernet device.
8967 * Pointer to mlx5_flow_handle.
8970 * 1 while a reference on it exists, 0 when freed.
8973 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8974 struct mlx5_flow_handle *handle)
8976 struct mlx5_priv *priv = dev->data->dev_private;
8977 uint32_t idx = handle->dvh.rix_push_vlan;
8978 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8980 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8982 if (!cache_resource)
8984 MLX5_ASSERT(cache_resource->action);
8985 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8986 (void *)cache_resource,
8987 rte_atomic32_read(&cache_resource->refcnt));
8988 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8989 claim_zero(mlx5_glue->destroy_flow_action
8990 (cache_resource->action));
8991 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8992 &priv->sh->push_vlan_action_list, idx,
8993 cache_resource, next);
8994 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8995 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8996 (void *)cache_resource);
9003 * Release the fate resource.
9006 * Pointer to Ethernet device.
9008 * Pointer to mlx5_flow_handle.
9011 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9012 struct mlx5_flow_handle *handle)
9014 if (!handle->rix_fate)
9016 switch (handle->fate_action) {
9017 case MLX5_FLOW_FATE_DROP:
9018 mlx5_hrxq_drop_release(dev);
9020 case MLX5_FLOW_FATE_QUEUE:
9021 mlx5_hrxq_release(dev, handle->rix_hrxq);
9023 case MLX5_FLOW_FATE_JUMP:
9024 flow_dv_jump_tbl_resource_release(dev, handle);
9026 case MLX5_FLOW_FATE_PORT_ID:
9027 flow_dv_port_id_action_resource_release(dev, handle);
9029 case MLX5_FLOW_FATE_DEFAULT_MISS:
9030 flow_dv_default_miss_resource_release(dev);
9033 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9036 handle->rix_fate = 0;
9040 * Remove the flow from the NIC but keeps it in memory.
9041 * Lock free, (mutex should be acquired by caller).
9044 * Pointer to Ethernet device.
9045 * @param[in, out] flow
9046 * Pointer to flow structure.
9049 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9051 struct mlx5_flow_handle *dh;
9052 uint32_t handle_idx;
9053 struct mlx5_priv *priv = dev->data->dev_private;
9057 handle_idx = flow->dev_handles;
9058 while (handle_idx) {
9059 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9064 claim_zero(mlx5_glue->dv_destroy_flow(dh->drv_flow));
9065 dh->drv_flow = NULL;
9067 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9068 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9069 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9070 flow_dv_fate_resource_release(dev, dh);
9071 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9072 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9073 handle_idx = dh->next.next;
9078 * Remove the flow from the NIC and the memory.
9079 * Lock free, (mutex should be acquired by caller).
9082 * Pointer to the Ethernet device structure.
9083 * @param[in, out] flow
9084 * Pointer to flow structure.
9087 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9089 struct mlx5_flow_handle *dev_handle;
9090 struct mlx5_priv *priv = dev->data->dev_private;
9094 __flow_dv_remove(dev, flow);
9095 if (flow->counter) {
9096 flow_dv_counter_release(dev, flow->counter);
9100 struct mlx5_flow_meter *fm;
9102 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9105 mlx5_flow_meter_detach(fm);
9108 while (flow->dev_handles) {
9109 uint32_t tmp_idx = flow->dev_handles;
9111 dev_handle = mlx5_ipool_get(priv->sh->ipool
9112 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9115 flow->dev_handles = dev_handle->next.next;
9116 if (dev_handle->dvh.matcher)
9117 flow_dv_matcher_release(dev, dev_handle);
9118 if (dev_handle->dvh.rix_encap_decap)
9119 flow_dv_encap_decap_resource_release(dev, dev_handle);
9120 if (dev_handle->dvh.modify_hdr)
9121 flow_dv_modify_hdr_resource_release(dev_handle);
9122 if (dev_handle->dvh.rix_push_vlan)
9123 flow_dv_push_vlan_action_resource_release(dev,
9125 if (dev_handle->dvh.rix_tag)
9126 flow_dv_tag_release(dev,
9127 dev_handle->dvh.rix_tag);
9128 flow_dv_fate_resource_release(dev, dev_handle);
9129 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9135 * Query a dv flow rule for its statistics via devx.
9138 * Pointer to Ethernet device.
9140 * Pointer to the sub flow.
9142 * data retrieved by the query.
9144 * Perform verbose error reporting if not NULL.
9147 * 0 on success, a negative errno value otherwise and rte_errno is set.
9150 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9151 void *data, struct rte_flow_error *error)
9153 struct mlx5_priv *priv = dev->data->dev_private;
9154 struct rte_flow_query_count *qc = data;
9156 if (!priv->config.devx)
9157 return rte_flow_error_set(error, ENOTSUP,
9158 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9160 "counters are not supported");
9161 if (flow->counter) {
9162 uint64_t pkts, bytes;
9163 struct mlx5_flow_counter *cnt;
9165 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9167 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9171 return rte_flow_error_set(error, -err,
9172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9173 NULL, "cannot read counters");
9176 qc->hits = pkts - cnt->hits;
9177 qc->bytes = bytes - cnt->bytes;
9184 return rte_flow_error_set(error, EINVAL,
9185 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9187 "counters are not available");
9193 * @see rte_flow_query()
9197 flow_dv_query(struct rte_eth_dev *dev,
9198 struct rte_flow *flow __rte_unused,
9199 const struct rte_flow_action *actions __rte_unused,
9200 void *data __rte_unused,
9201 struct rte_flow_error *error __rte_unused)
9205 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9206 switch (actions->type) {
9207 case RTE_FLOW_ACTION_TYPE_VOID:
9209 case RTE_FLOW_ACTION_TYPE_COUNT:
9210 ret = flow_dv_query_count(dev, flow, data, error);
9213 return rte_flow_error_set(error, ENOTSUP,
9214 RTE_FLOW_ERROR_TYPE_ACTION,
9216 "action not supported");
9223 * Destroy the meter table set.
9224 * Lock free, (mutex should be acquired by caller).
9227 * Pointer to Ethernet device.
9229 * Pointer to the meter table set.
9235 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9236 struct mlx5_meter_domains_infos *tbl)
9238 struct mlx5_priv *priv = dev->data->dev_private;
9239 struct mlx5_meter_domains_infos *mtd =
9240 (struct mlx5_meter_domains_infos *)tbl;
9242 if (!mtd || !priv->config.dv_flow_en)
9244 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9245 claim_zero(mlx5_glue->dv_destroy_flow
9246 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9247 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9248 claim_zero(mlx5_glue->dv_destroy_flow
9249 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9250 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9251 claim_zero(mlx5_glue->dv_destroy_flow
9252 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9253 if (mtd->egress.color_matcher)
9254 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9255 (mtd->egress.color_matcher));
9256 if (mtd->egress.any_matcher)
9257 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9258 (mtd->egress.any_matcher));
9259 if (mtd->egress.tbl)
9260 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9261 if (mtd->egress.sfx_tbl)
9262 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9263 if (mtd->ingress.color_matcher)
9264 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9265 (mtd->ingress.color_matcher));
9266 if (mtd->ingress.any_matcher)
9267 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9268 (mtd->ingress.any_matcher));
9269 if (mtd->ingress.tbl)
9270 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9271 if (mtd->ingress.sfx_tbl)
9272 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9273 if (mtd->transfer.color_matcher)
9274 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9275 (mtd->transfer.color_matcher));
9276 if (mtd->transfer.any_matcher)
9277 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9278 (mtd->transfer.any_matcher));
9279 if (mtd->transfer.tbl)
9280 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9281 if (mtd->transfer.sfx_tbl)
9282 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9284 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9289 /* Number of meter flow actions, count and jump or count and drop. */
9290 #define METER_ACTIONS 2
9293 * Create specify domain meter table and suffix table.
9296 * Pointer to Ethernet device.
9297 * @param[in,out] mtb
9298 * Pointer to DV meter table set.
9301 * @param[in] transfer
9303 * @param[in] color_reg_c_idx
9304 * Reg C index for color match.
9307 * 0 on success, -1 otherwise and rte_errno is set.
9310 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9311 struct mlx5_meter_domains_infos *mtb,
9312 uint8_t egress, uint8_t transfer,
9313 uint32_t color_reg_c_idx)
9315 struct mlx5_priv *priv = dev->data->dev_private;
9316 struct mlx5_dev_ctx_shared *sh = priv->sh;
9317 struct mlx5_flow_dv_match_params mask = {
9318 .size = sizeof(mask.buf),
9320 struct mlx5_flow_dv_match_params value = {
9321 .size = sizeof(value.buf),
9323 struct mlx5dv_flow_matcher_attr dv_attr = {
9324 .type = IBV_FLOW_ATTR_NORMAL,
9326 .match_criteria_enable = 0,
9327 .match_mask = (void *)&mask,
9329 void *actions[METER_ACTIONS];
9330 struct mlx5_meter_domain_info *dtb;
9331 struct rte_flow_error error;
9335 dtb = &mtb->transfer;
9339 dtb = &mtb->ingress;
9340 /* Create the meter table with METER level. */
9341 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9342 egress, transfer, &error);
9344 DRV_LOG(ERR, "Failed to create meter policer table.");
9347 /* Create the meter suffix table with SUFFIX level. */
9348 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9349 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9350 egress, transfer, &error);
9351 if (!dtb->sfx_tbl) {
9352 DRV_LOG(ERR, "Failed to create meter suffix table.");
9355 /* Create matchers, Any and Color. */
9356 dv_attr.priority = 3;
9357 dv_attr.match_criteria_enable = 0;
9358 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9361 if (!dtb->any_matcher) {
9362 DRV_LOG(ERR, "Failed to create meter"
9363 " policer default matcher.");
9366 dv_attr.priority = 0;
9367 dv_attr.match_criteria_enable =
9368 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9369 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9370 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9371 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9374 if (!dtb->color_matcher) {
9375 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9378 if (mtb->count_actns[RTE_MTR_DROPPED])
9379 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9380 actions[i++] = mtb->drop_actn;
9381 /* Default rule: lowest priority, match any, actions: drop. */
9382 dtb->policer_rules[RTE_MTR_DROPPED] =
9383 mlx5_glue->dv_create_flow(dtb->any_matcher,
9384 (void *)&value, i, actions);
9385 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9386 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9395 * Create the needed meter and suffix tables.
9396 * Lock free, (mutex should be acquired by caller).
9399 * Pointer to Ethernet device.
9401 * Pointer to the flow meter.
9404 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9406 static struct mlx5_meter_domains_infos *
9407 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9408 const struct mlx5_flow_meter *fm)
9410 struct mlx5_priv *priv = dev->data->dev_private;
9411 struct mlx5_meter_domains_infos *mtb;
9415 if (!priv->mtr_en) {
9416 rte_errno = ENOTSUP;
9419 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9421 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9424 /* Create meter count actions */
9425 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9426 struct mlx5_flow_counter *cnt;
9427 if (!fm->policer_stats.cnt[i])
9429 cnt = flow_dv_counter_get_by_idx(dev,
9430 fm->policer_stats.cnt[i], NULL);
9431 mtb->count_actns[i] = cnt->action;
9433 /* Create drop action. */
9434 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9435 if (!mtb->drop_actn) {
9436 DRV_LOG(ERR, "Failed to create drop action.");
9439 /* Egress meter table. */
9440 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9442 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9445 /* Ingress meter table. */
9446 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9448 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9451 /* FDB meter table. */
9452 if (priv->config.dv_esw_en) {
9453 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9454 priv->mtr_color_reg);
9456 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9462 flow_dv_destroy_mtr_tbl(dev, mtb);
9467 * Destroy domain policer rule.
9470 * Pointer to domain table.
9473 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9477 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9478 if (dt->policer_rules[i]) {
9479 claim_zero(mlx5_glue->dv_destroy_flow
9480 (dt->policer_rules[i]));
9481 dt->policer_rules[i] = NULL;
9484 if (dt->jump_actn) {
9485 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9486 dt->jump_actn = NULL;
9491 * Destroy policer rules.
9494 * Pointer to Ethernet device.
9496 * Pointer to flow meter structure.
9498 * Pointer to flow attributes.
9504 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9505 const struct mlx5_flow_meter *fm,
9506 const struct rte_flow_attr *attr)
9508 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9513 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9515 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9517 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9522 * Create specify domain meter policer rule.
9525 * Pointer to flow meter structure.
9527 * Pointer to DV meter table set.
9528 * @param[in] mtr_reg_c
9529 * Color match REG_C.
9532 * 0 on success, -1 otherwise.
9535 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9536 struct mlx5_meter_domain_info *dtb,
9539 struct mlx5_flow_dv_match_params matcher = {
9540 .size = sizeof(matcher.buf),
9542 struct mlx5_flow_dv_match_params value = {
9543 .size = sizeof(value.buf),
9545 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9546 void *actions[METER_ACTIONS];
9549 /* Create jump action. */
9550 if (!dtb->jump_actn)
9552 mlx5_glue->dr_create_flow_action_dest_flow_tbl
9553 (dtb->sfx_tbl->obj);
9554 if (!dtb->jump_actn) {
9555 DRV_LOG(ERR, "Failed to create policer jump action.");
9558 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9561 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9562 rte_col_2_mlx5_col(i), UINT8_MAX);
9563 if (mtb->count_actns[i])
9564 actions[j++] = mtb->count_actns[i];
9565 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9566 actions[j++] = mtb->drop_actn;
9568 actions[j++] = dtb->jump_actn;
9569 dtb->policer_rules[i] =
9570 mlx5_glue->dv_create_flow(dtb->color_matcher,
9573 if (!dtb->policer_rules[i]) {
9574 DRV_LOG(ERR, "Failed to create policer rule.");
9585 * Create policer rules.
9588 * Pointer to Ethernet device.
9590 * Pointer to flow meter structure.
9592 * Pointer to flow attributes.
9595 * 0 on success, -1 otherwise.
9598 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9599 struct mlx5_flow_meter *fm,
9600 const struct rte_flow_attr *attr)
9602 struct mlx5_priv *priv = dev->data->dev_private;
9603 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9607 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9608 priv->mtr_color_reg);
9610 DRV_LOG(ERR, "Failed to create egress policer.");
9614 if (attr->ingress) {
9615 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9616 priv->mtr_color_reg);
9618 DRV_LOG(ERR, "Failed to create ingress policer.");
9622 if (attr->transfer) {
9623 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9624 priv->mtr_color_reg);
9626 DRV_LOG(ERR, "Failed to create transfer policer.");
9632 flow_dv_destroy_policer_rules(dev, fm, attr);
9637 * Query a devx counter.
9640 * Pointer to the Ethernet device structure.
9642 * Index to the flow counter.
9644 * Set to clear the counter statistics.
9646 * The statistics value of packets.
9648 * The statistics value of bytes.
9651 * 0 on success, otherwise return -1.
9654 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9655 uint64_t *pkts, uint64_t *bytes)
9657 struct mlx5_priv *priv = dev->data->dev_private;
9658 struct mlx5_flow_counter *cnt;
9659 uint64_t inn_pkts, inn_bytes;
9662 if (!priv->config.devx)
9665 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9668 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9669 *pkts = inn_pkts - cnt->hits;
9670 *bytes = inn_bytes - cnt->bytes;
9672 cnt->hits = inn_pkts;
9673 cnt->bytes = inn_bytes;
9679 * Get aged-out flows.
9682 * Pointer to the Ethernet device structure.
9683 * @param[in] context
9684 * The address of an array of pointers to the aged-out flows contexts.
9685 * @param[in] nb_contexts
9686 * The length of context array pointers.
9688 * Perform verbose error reporting if not NULL. Initialized in case of
9692 * how many contexts get in success, otherwise negative errno value.
9693 * if nb_contexts is 0, return the amount of all aged contexts.
9694 * if nb_contexts is not 0 , return the amount of aged flows reported
9695 * in the context array.
9696 * @note: only stub for now
9699 flow_get_aged_flows(struct rte_eth_dev *dev,
9701 uint32_t nb_contexts,
9702 struct rte_flow_error *error)
9704 struct mlx5_priv *priv = dev->data->dev_private;
9705 struct mlx5_age_info *age_info;
9706 struct mlx5_age_param *age_param;
9707 struct mlx5_flow_counter *counter;
9710 if (nb_contexts && !context)
9711 return rte_flow_error_set(error, EINVAL,
9712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9714 "Should assign at least one flow or"
9715 " context to get if nb_contexts != 0");
9716 age_info = GET_PORT_AGE_INFO(priv);
9717 rte_spinlock_lock(&age_info->aged_sl);
9718 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9721 age_param = MLX5_CNT_TO_AGE(counter);
9722 context[nb_flows - 1] = age_param->context;
9723 if (!(--nb_contexts))
9727 rte_spinlock_unlock(&age_info->aged_sl);
9728 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9733 * Mutex-protected thunk to lock-free __flow_dv_translate().
9736 flow_dv_translate(struct rte_eth_dev *dev,
9737 struct mlx5_flow *dev_flow,
9738 const struct rte_flow_attr *attr,
9739 const struct rte_flow_item items[],
9740 const struct rte_flow_action actions[],
9741 struct rte_flow_error *error)
9745 flow_dv_shared_lock(dev);
9746 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9747 flow_dv_shared_unlock(dev);
9752 * Mutex-protected thunk to lock-free __flow_dv_apply().
9755 flow_dv_apply(struct rte_eth_dev *dev,
9756 struct rte_flow *flow,
9757 struct rte_flow_error *error)
9761 flow_dv_shared_lock(dev);
9762 ret = __flow_dv_apply(dev, flow, error);
9763 flow_dv_shared_unlock(dev);
9768 * Mutex-protected thunk to lock-free __flow_dv_remove().
9771 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9773 flow_dv_shared_lock(dev);
9774 __flow_dv_remove(dev, flow);
9775 flow_dv_shared_unlock(dev);
9779 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9782 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9784 flow_dv_shared_lock(dev);
9785 __flow_dv_destroy(dev, flow);
9786 flow_dv_shared_unlock(dev);
9790 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9793 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9797 flow_dv_shared_lock(dev);
9798 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9799 flow_dv_shared_unlock(dev);
9804 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9807 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9809 flow_dv_shared_lock(dev);
9810 flow_dv_counter_release(dev, cnt);
9811 flow_dv_shared_unlock(dev);
9814 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9815 .validate = flow_dv_validate,
9816 .prepare = flow_dv_prepare,
9817 .translate = flow_dv_translate,
9818 .apply = flow_dv_apply,
9819 .remove = flow_dv_remove,
9820 .destroy = flow_dv_destroy,
9821 .query = flow_dv_query,
9822 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9823 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9824 .create_policer_rules = flow_dv_create_policer_rules,
9825 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9826 .counter_alloc = flow_dv_counter_allocate,
9827 .counter_free = flow_dv_counter_free,
9828 .counter_query = flow_dv_counter_query,
9829 .get_aged_flows = flow_get_aged_flows,
9832 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */