1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
100 struct mlx5_common_device *cdev = priv->sh->cdev;
102 if (cdev->config.hca_attr.esw_mgr_vport_id_valid)
103 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id;
105 if (priv->pci_dev == NULL)
107 switch (priv->pci_dev->id.device_id) {
108 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
109 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
110 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
111 return (int16_t)0xfffe;
118 * Initialize flow attributes structure according to flow items' types.
120 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
121 * mode. For tunnel mode, the items to be modified are the outermost ones.
124 * Pointer to item specification.
126 * Pointer to flow attributes structure.
127 * @param[in] dev_flow
128 * Pointer to the sub flow.
129 * @param[in] tunnel_decap
130 * Whether action is after tunnel decapsulation.
133 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
134 struct mlx5_flow *dev_flow, bool tunnel_decap)
136 uint64_t layers = dev_flow->handle->layers;
139 * If layers is already initialized, it means this dev_flow is the
140 * suffix flow, the layers flags is set by the prefix flow. Need to
141 * use the layer flags from prefix flow as the suffix flow may not
142 * have the user defined items as the flow is split.
145 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
149 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
151 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
156 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
157 uint8_t next_protocol = 0xff;
158 switch (item->type) {
159 case RTE_FLOW_ITEM_TYPE_GRE:
160 case RTE_FLOW_ITEM_TYPE_NVGRE:
161 case RTE_FLOW_ITEM_TYPE_VXLAN:
162 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
163 case RTE_FLOW_ITEM_TYPE_GENEVE:
164 case RTE_FLOW_ITEM_TYPE_MPLS:
168 case RTE_FLOW_ITEM_TYPE_IPV4:
171 if (item->mask != NULL &&
172 ((const struct rte_flow_item_ipv4 *)
173 item->mask)->hdr.next_proto_id)
175 ((const struct rte_flow_item_ipv4 *)
176 (item->spec))->hdr.next_proto_id &
177 ((const struct rte_flow_item_ipv4 *)
178 (item->mask))->hdr.next_proto_id;
179 if ((next_protocol == IPPROTO_IPIP ||
180 next_protocol == IPPROTO_IPV6) && tunnel_decap)
183 case RTE_FLOW_ITEM_TYPE_IPV6:
186 if (item->mask != NULL &&
187 ((const struct rte_flow_item_ipv6 *)
188 item->mask)->hdr.proto)
190 ((const struct rte_flow_item_ipv6 *)
191 (item->spec))->hdr.proto &
192 ((const struct rte_flow_item_ipv6 *)
193 (item->mask))->hdr.proto;
194 if ((next_protocol == IPPROTO_IPIP ||
195 next_protocol == IPPROTO_IPV6) && tunnel_decap)
198 case RTE_FLOW_ITEM_TYPE_UDP:
202 case RTE_FLOW_ITEM_TYPE_TCP:
214 * Convert rte_mtr_color to mlx5 color.
223 rte_col_2_mlx5_col(enum rte_color rcol)
226 case RTE_COLOR_GREEN:
227 return MLX5_FLOW_COLOR_GREEN;
228 case RTE_COLOR_YELLOW:
229 return MLX5_FLOW_COLOR_YELLOW;
231 return MLX5_FLOW_COLOR_RED;
235 return MLX5_FLOW_COLOR_UNDEFINED;
238 struct field_modify_info {
239 uint32_t size; /* Size of field in protocol header, in bytes. */
240 uint32_t offset; /* Offset of field in protocol header, in bytes. */
241 enum mlx5_modification_field id;
244 struct field_modify_info modify_eth[] = {
245 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
246 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
247 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
248 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
252 struct field_modify_info modify_vlan_out_first_vid[] = {
253 /* Size in bits !!! */
254 {12, 0, MLX5_MODI_OUT_FIRST_VID},
258 struct field_modify_info modify_ipv4[] = {
259 {1, 1, MLX5_MODI_OUT_IP_DSCP},
260 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
261 {4, 12, MLX5_MODI_OUT_SIPV4},
262 {4, 16, MLX5_MODI_OUT_DIPV4},
266 struct field_modify_info modify_ipv6[] = {
267 {1, 0, MLX5_MODI_OUT_IP_DSCP},
268 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
269 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
270 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
271 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
272 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
273 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
274 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
275 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
276 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
280 struct field_modify_info modify_udp[] = {
281 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
282 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
286 struct field_modify_info modify_tcp[] = {
287 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
288 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
289 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
290 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
295 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
296 uint8_t next_protocol, uint64_t *item_flags,
299 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
300 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
301 if (next_protocol == IPPROTO_IPIP) {
302 *item_flags |= MLX5_FLOW_LAYER_IPIP;
305 if (next_protocol == IPPROTO_IPV6) {
306 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
311 static inline struct mlx5_hlist *
312 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
313 const char *name, uint32_t size, bool direct_key,
314 bool lcores_share, void *ctx,
315 mlx5_list_create_cb cb_create,
316 mlx5_list_match_cb cb_match,
317 mlx5_list_remove_cb cb_remove,
318 mlx5_list_clone_cb cb_clone,
319 mlx5_list_clone_free_cb cb_clone_free,
320 struct rte_flow_error *error)
322 struct mlx5_hlist *hl;
323 struct mlx5_hlist *expected = NULL;
324 char s[MLX5_NAME_SIZE];
326 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
329 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
330 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
331 ctx, cb_create, cb_match, cb_remove, cb_clone,
334 DRV_LOG(ERR, "%s hash creation failed", name);
335 rte_flow_error_set(error, ENOMEM,
336 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
337 "cannot allocate resource memory");
340 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
343 mlx5_hlist_destroy(hl);
344 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
349 /* Update VLAN's VID/PCP based on input rte_flow_action.
352 * Pointer to struct rte_flow_action.
354 * Pointer to struct rte_vlan_hdr.
357 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
358 struct rte_vlan_hdr *vlan)
361 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
363 ((const struct rte_flow_action_of_set_vlan_pcp *)
364 action->conf)->vlan_pcp;
365 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
366 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
367 vlan->vlan_tci |= vlan_tci;
368 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
369 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
370 vlan->vlan_tci |= rte_be_to_cpu_16
371 (((const struct rte_flow_action_of_set_vlan_vid *)
372 action->conf)->vlan_vid);
377 * Fetch 1, 2, 3 or 4 byte field from the byte array
378 * and return as unsigned integer in host-endian format.
381 * Pointer to data array.
383 * Size of field to extract.
386 * converted field in host endian format.
388 static inline uint32_t
389 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
398 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
401 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
402 ret = (ret << 8) | *(data + sizeof(uint16_t));
405 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
416 * Convert modify-header action to DV specification.
418 * Data length of each action is determined by provided field description
419 * and the item mask. Data bit offset and width of each action is determined
420 * by provided item mask.
423 * Pointer to item specification.
425 * Pointer to field modification information.
426 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
427 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
428 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
430 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
431 * Negative offset value sets the same offset as source offset.
432 * size field is ignored, value is taken from source field.
433 * @param[in,out] resource
434 * Pointer to the modify-header resource.
436 * Type of modification.
438 * Pointer to the error structure.
441 * 0 on success, a negative errno value otherwise and rte_errno is set.
444 flow_dv_convert_modify_action(struct rte_flow_item *item,
445 struct field_modify_info *field,
446 struct field_modify_info *dcopy,
447 struct mlx5_flow_dv_modify_hdr_resource *resource,
448 uint32_t type, struct rte_flow_error *error)
450 uint32_t i = resource->actions_num;
451 struct mlx5_modification_cmd *actions = resource->actions;
452 uint32_t carry_b = 0;
455 * The item and mask are provided in big-endian format.
456 * The fields should be presented as in big-endian format either.
457 * Mask must be always present, it defines the actual field width.
459 MLX5_ASSERT(item->mask);
460 MLX5_ASSERT(field->size);
466 bool next_field = true;
467 bool next_dcopy = true;
469 if (i >= MLX5_MAX_MODIFY_NUM)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "too many items to modify");
473 /* Fetch variable byte size mask from the array. */
474 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
475 field->offset, field->size);
480 /* Deduce actual data width in bits from mask value. */
481 off_b = rte_bsf32(mask) + carry_b;
482 size_b = sizeof(uint32_t) * CHAR_BIT -
483 off_b - __builtin_clz(mask);
485 actions[i] = (struct mlx5_modification_cmd) {
489 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
492 if (type == MLX5_MODIFICATION_TYPE_COPY) {
494 actions[i].dst_field = dcopy->id;
495 actions[i].dst_offset =
496 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
497 /* Convert entire record to big-endian format. */
498 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
500 * Destination field overflow. Copy leftovers of
501 * a source field to the next destination field.
504 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
507 dcopy->size * CHAR_BIT - dcopy->offset;
508 carry_b = actions[i].length;
512 * Not enough bits in a source filed to fill a
513 * destination field. Switch to the next source.
515 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
516 (size_b == field->size * CHAR_BIT - off_b)) {
518 field->size * CHAR_BIT - off_b;
519 dcopy->offset += actions[i].length;
525 MLX5_ASSERT(item->spec);
526 data = flow_dv_fetch_field((const uint8_t *)item->spec +
527 field->offset, field->size);
528 /* Shift out the trailing masked bits from data. */
529 data = (data & mask) >> off_b;
530 actions[i].data1 = rte_cpu_to_be_32(data);
532 /* Convert entire record to expected big-endian format. */
533 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
537 } while (field->size);
538 if (resource->actions_num == i)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "invalid modification flow item");
542 resource->actions_num = i;
547 * Convert modify-header set IPv4 address action to DV specification.
549 * @param[in,out] resource
550 * Pointer to the modify-header resource.
552 * Pointer to action specification.
554 * Pointer to the error structure.
557 * 0 on success, a negative errno value otherwise and rte_errno is set.
560 flow_dv_convert_action_modify_ipv4
561 (struct mlx5_flow_dv_modify_hdr_resource *resource,
562 const struct rte_flow_action *action,
563 struct rte_flow_error *error)
565 const struct rte_flow_action_set_ipv4 *conf =
566 (const struct rte_flow_action_set_ipv4 *)(action->conf);
567 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
568 struct rte_flow_item_ipv4 ipv4;
569 struct rte_flow_item_ipv4 ipv4_mask;
571 memset(&ipv4, 0, sizeof(ipv4));
572 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
573 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
574 ipv4.hdr.src_addr = conf->ipv4_addr;
575 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
577 ipv4.hdr.dst_addr = conf->ipv4_addr;
578 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
581 item.mask = &ipv4_mask;
582 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set IPv6 address action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_ipv6
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_set_ipv6 *conf =
606 (const struct rte_flow_action_set_ipv6 *)(action->conf);
607 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
608 struct rte_flow_item_ipv6 ipv6;
609 struct rte_flow_item_ipv6 ipv6_mask;
611 memset(&ipv6, 0, sizeof(ipv6));
612 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
613 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
614 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
615 sizeof(ipv6.hdr.src_addr));
616 memcpy(&ipv6_mask.hdr.src_addr,
617 &rte_flow_item_ipv6_mask.hdr.src_addr,
618 sizeof(ipv6.hdr.src_addr));
620 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
621 sizeof(ipv6.hdr.dst_addr));
622 memcpy(&ipv6_mask.hdr.dst_addr,
623 &rte_flow_item_ipv6_mask.hdr.dst_addr,
624 sizeof(ipv6.hdr.dst_addr));
627 item.mask = &ipv6_mask;
628 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
629 MLX5_MODIFICATION_TYPE_SET, error);
633 * Convert modify-header set MAC address action to DV specification.
635 * @param[in,out] resource
636 * Pointer to the modify-header resource.
638 * Pointer to action specification.
640 * Pointer to the error structure.
643 * 0 on success, a negative errno value otherwise and rte_errno is set.
646 flow_dv_convert_action_modify_mac
647 (struct mlx5_flow_dv_modify_hdr_resource *resource,
648 const struct rte_flow_action *action,
649 struct rte_flow_error *error)
651 const struct rte_flow_action_set_mac *conf =
652 (const struct rte_flow_action_set_mac *)(action->conf);
653 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
654 struct rte_flow_item_eth eth;
655 struct rte_flow_item_eth eth_mask;
657 memset(ð, 0, sizeof(eth));
658 memset(ð_mask, 0, sizeof(eth_mask));
659 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
660 memcpy(ð.src.addr_bytes, &conf->mac_addr,
661 sizeof(eth.src.addr_bytes));
662 memcpy(ð_mask.src.addr_bytes,
663 &rte_flow_item_eth_mask.src.addr_bytes,
664 sizeof(eth_mask.src.addr_bytes));
666 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
667 sizeof(eth.dst.addr_bytes));
668 memcpy(ð_mask.dst.addr_bytes,
669 &rte_flow_item_eth_mask.dst.addr_bytes,
670 sizeof(eth_mask.dst.addr_bytes));
673 item.mask = ð_mask;
674 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
675 MLX5_MODIFICATION_TYPE_SET, error);
679 * Convert modify-header set VLAN VID action to DV specification.
681 * @param[in,out] resource
682 * Pointer to the modify-header resource.
684 * Pointer to action specification.
686 * Pointer to the error structure.
689 * 0 on success, a negative errno value otherwise and rte_errno is set.
692 flow_dv_convert_action_modify_vlan_vid
693 (struct mlx5_flow_dv_modify_hdr_resource *resource,
694 const struct rte_flow_action *action,
695 struct rte_flow_error *error)
697 const struct rte_flow_action_of_set_vlan_vid *conf =
698 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
699 int i = resource->actions_num;
700 struct mlx5_modification_cmd *actions = resource->actions;
701 struct field_modify_info *field = modify_vlan_out_first_vid;
703 if (i >= MLX5_MAX_MODIFY_NUM)
704 return rte_flow_error_set(error, EINVAL,
705 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
706 "too many items to modify");
707 actions[i] = (struct mlx5_modification_cmd) {
708 .action_type = MLX5_MODIFICATION_TYPE_SET,
710 .length = field->size,
711 .offset = field->offset,
713 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
714 actions[i].data1 = conf->vlan_vid;
715 actions[i].data1 = actions[i].data1 << 16;
716 resource->actions_num = ++i;
721 * Convert modify-header set TP action to DV specification.
723 * @param[in,out] resource
724 * Pointer to the modify-header resource.
726 * Pointer to action specification.
728 * Pointer to rte_flow_item objects list.
730 * Pointer to flow attributes structure.
731 * @param[in] dev_flow
732 * Pointer to the sub flow.
733 * @param[in] tunnel_decap
734 * Whether action is after tunnel decapsulation.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_tp
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_action *action,
745 const struct rte_flow_item *items,
746 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
747 bool tunnel_decap, struct rte_flow_error *error)
749 const struct rte_flow_action_set_tp *conf =
750 (const struct rte_flow_action_set_tp *)(action->conf);
751 struct rte_flow_item item;
752 struct rte_flow_item_udp udp;
753 struct rte_flow_item_udp udp_mask;
754 struct rte_flow_item_tcp tcp;
755 struct rte_flow_item_tcp tcp_mask;
756 struct field_modify_info *field;
759 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
761 memset(&udp, 0, sizeof(udp));
762 memset(&udp_mask, 0, sizeof(udp_mask));
763 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
764 udp.hdr.src_port = conf->port;
765 udp_mask.hdr.src_port =
766 rte_flow_item_udp_mask.hdr.src_port;
768 udp.hdr.dst_port = conf->port;
769 udp_mask.hdr.dst_port =
770 rte_flow_item_udp_mask.hdr.dst_port;
772 item.type = RTE_FLOW_ITEM_TYPE_UDP;
774 item.mask = &udp_mask;
777 MLX5_ASSERT(attr->tcp);
778 memset(&tcp, 0, sizeof(tcp));
779 memset(&tcp_mask, 0, sizeof(tcp_mask));
780 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
781 tcp.hdr.src_port = conf->port;
782 tcp_mask.hdr.src_port =
783 rte_flow_item_tcp_mask.hdr.src_port;
785 tcp.hdr.dst_port = conf->port;
786 tcp_mask.hdr.dst_port =
787 rte_flow_item_tcp_mask.hdr.dst_port;
789 item.type = RTE_FLOW_ITEM_TYPE_TCP;
791 item.mask = &tcp_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header set TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_action *action,
823 const struct rte_flow_item *items,
824 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
825 bool tunnel_decap, struct rte_flow_error *error)
827 const struct rte_flow_action_set_ttl *conf =
828 (const struct rte_flow_action_set_ttl *)(action->conf);
829 struct rte_flow_item item;
830 struct rte_flow_item_ipv4 ipv4;
831 struct rte_flow_item_ipv4 ipv4_mask;
832 struct rte_flow_item_ipv6 ipv6;
833 struct rte_flow_item_ipv6 ipv6_mask;
834 struct field_modify_info *field;
837 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
839 memset(&ipv4, 0, sizeof(ipv4));
840 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
841 ipv4.hdr.time_to_live = conf->ttl_value;
842 ipv4_mask.hdr.time_to_live = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
845 item.mask = &ipv4_mask;
848 MLX5_ASSERT(attr->ipv6);
849 memset(&ipv6, 0, sizeof(ipv6));
850 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
851 ipv6.hdr.hop_limits = conf->ttl_value;
852 ipv6_mask.hdr.hop_limits = 0xFF;
853 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
855 item.mask = &ipv6_mask;
858 return flow_dv_convert_modify_action(&item, field, NULL, resource,
859 MLX5_MODIFICATION_TYPE_SET, error);
863 * Convert modify-header decrement TTL action to DV specification.
865 * @param[in,out] resource
866 * Pointer to the modify-header resource.
868 * Pointer to action specification.
870 * Pointer to rte_flow_item objects list.
872 * Pointer to flow attributes structure.
873 * @param[in] dev_flow
874 * Pointer to the sub flow.
875 * @param[in] tunnel_decap
876 * Whether action is after tunnel decapsulation.
878 * Pointer to the error structure.
881 * 0 on success, a negative errno value otherwise and rte_errno is set.
884 flow_dv_convert_action_modify_dec_ttl
885 (struct mlx5_flow_dv_modify_hdr_resource *resource,
886 const struct rte_flow_item *items,
887 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
888 bool tunnel_decap, struct rte_flow_error *error)
890 struct rte_flow_item item;
891 struct rte_flow_item_ipv4 ipv4;
892 struct rte_flow_item_ipv4 ipv4_mask;
893 struct rte_flow_item_ipv6 ipv6;
894 struct rte_flow_item_ipv6 ipv6_mask;
895 struct field_modify_info *field;
898 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
900 memset(&ipv4, 0, sizeof(ipv4));
901 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
902 ipv4.hdr.time_to_live = 0xFF;
903 ipv4_mask.hdr.time_to_live = 0xFF;
904 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
906 item.mask = &ipv4_mask;
909 MLX5_ASSERT(attr->ipv6);
910 memset(&ipv6, 0, sizeof(ipv6));
911 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
912 ipv6.hdr.hop_limits = 0xFF;
913 ipv6_mask.hdr.hop_limits = 0xFF;
914 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
916 item.mask = &ipv6_mask;
919 return flow_dv_convert_modify_action(&item, field, NULL, resource,
920 MLX5_MODIFICATION_TYPE_ADD, error);
924 * Convert modify-header increment/decrement TCP Sequence number
925 * to DV specification.
927 * @param[in,out] resource
928 * Pointer to the modify-header resource.
930 * Pointer to action specification.
932 * Pointer to the error structure.
935 * 0 on success, a negative errno value otherwise and rte_errno is set.
938 flow_dv_convert_action_modify_tcp_seq
939 (struct mlx5_flow_dv_modify_hdr_resource *resource,
940 const struct rte_flow_action *action,
941 struct rte_flow_error *error)
943 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
944 uint64_t value = rte_be_to_cpu_32(*conf);
945 struct rte_flow_item item;
946 struct rte_flow_item_tcp tcp;
947 struct rte_flow_item_tcp tcp_mask;
949 memset(&tcp, 0, sizeof(tcp));
950 memset(&tcp_mask, 0, sizeof(tcp_mask));
951 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
953 * The HW has no decrement operation, only increment operation.
954 * To simulate decrement X from Y using increment operation
955 * we need to add UINT32_MAX X times to Y.
956 * Each adding of UINT32_MAX decrements Y by 1.
959 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
960 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
961 item.type = RTE_FLOW_ITEM_TYPE_TCP;
963 item.mask = &tcp_mask;
964 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
965 MLX5_MODIFICATION_TYPE_ADD, error);
969 * Convert modify-header increment/decrement TCP Acknowledgment number
970 * to DV specification.
972 * @param[in,out] resource
973 * Pointer to the modify-header resource.
975 * Pointer to action specification.
977 * Pointer to the error structure.
980 * 0 on success, a negative errno value otherwise and rte_errno is set.
983 flow_dv_convert_action_modify_tcp_ack
984 (struct mlx5_flow_dv_modify_hdr_resource *resource,
985 const struct rte_flow_action *action,
986 struct rte_flow_error *error)
988 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
989 uint64_t value = rte_be_to_cpu_32(*conf);
990 struct rte_flow_item item;
991 struct rte_flow_item_tcp tcp;
992 struct rte_flow_item_tcp tcp_mask;
994 memset(&tcp, 0, sizeof(tcp));
995 memset(&tcp_mask, 0, sizeof(tcp_mask));
996 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
998 * The HW has no decrement operation, only increment operation.
999 * To simulate decrement X from Y using increment operation
1000 * we need to add UINT32_MAX X times to Y.
1001 * Each adding of UINT32_MAX decrements Y by 1.
1003 value *= UINT32_MAX;
1004 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1005 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1006 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1008 item.mask = &tcp_mask;
1009 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1010 MLX5_MODIFICATION_TYPE_ADD, error);
1013 static enum mlx5_modification_field reg_to_field[] = {
1014 [REG_NON] = MLX5_MODI_OUT_NONE,
1015 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1016 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1017 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1018 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1019 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1020 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1021 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1022 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1023 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1024 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1028 * Convert register set to DV specification.
1030 * @param[in,out] resource
1031 * Pointer to the modify-header resource.
1033 * Pointer to action specification.
1035 * Pointer to the error structure.
1038 * 0 on success, a negative errno value otherwise and rte_errno is set.
1041 flow_dv_convert_action_set_reg
1042 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1043 const struct rte_flow_action *action,
1044 struct rte_flow_error *error)
1046 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1047 struct mlx5_modification_cmd *actions = resource->actions;
1048 uint32_t i = resource->actions_num;
1050 if (i >= MLX5_MAX_MODIFY_NUM)
1051 return rte_flow_error_set(error, EINVAL,
1052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1053 "too many items to modify");
1054 MLX5_ASSERT(conf->id != REG_NON);
1055 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1056 actions[i] = (struct mlx5_modification_cmd) {
1057 .action_type = MLX5_MODIFICATION_TYPE_SET,
1058 .field = reg_to_field[conf->id],
1059 .offset = conf->offset,
1060 .length = conf->length,
1062 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1063 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1065 resource->actions_num = i;
1070 * Convert SET_TAG action to DV specification.
1073 * Pointer to the rte_eth_dev structure.
1074 * @param[in,out] resource
1075 * Pointer to the modify-header resource.
1077 * Pointer to action specification.
1079 * Pointer to the error structure.
1082 * 0 on success, a negative errno value otherwise and rte_errno is set.
1085 flow_dv_convert_action_set_tag
1086 (struct rte_eth_dev *dev,
1087 struct mlx5_flow_dv_modify_hdr_resource *resource,
1088 const struct rte_flow_action_set_tag *conf,
1089 struct rte_flow_error *error)
1091 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1092 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1093 struct rte_flow_item item = {
1097 struct field_modify_info reg_c_x[] = {
1100 enum mlx5_modification_field reg_type;
1103 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1106 MLX5_ASSERT(ret != REG_NON);
1107 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1108 reg_type = reg_to_field[ret];
1109 MLX5_ASSERT(reg_type > 0);
1110 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1111 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1112 MLX5_MODIFICATION_TYPE_SET, error);
1116 * Convert internal COPY_REG action to DV specification.
1119 * Pointer to the rte_eth_dev structure.
1120 * @param[in,out] res
1121 * Pointer to the modify-header resource.
1123 * Pointer to action specification.
1125 * Pointer to the error structure.
1128 * 0 on success, a negative errno value otherwise and rte_errno is set.
1131 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1132 struct mlx5_flow_dv_modify_hdr_resource *res,
1133 const struct rte_flow_action *action,
1134 struct rte_flow_error *error)
1136 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1137 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1138 struct rte_flow_item item = {
1142 struct field_modify_info reg_src[] = {
1143 {4, 0, reg_to_field[conf->src]},
1146 struct field_modify_info reg_dst = {
1148 .id = reg_to_field[conf->dst],
1150 /* Adjust reg_c[0] usage according to reported mask. */
1151 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1155 MLX5_ASSERT(reg_c0);
1156 MLX5_ASSERT(priv->sh->config.dv_xmeta_en !=
1157 MLX5_XMETA_MODE_LEGACY);
1158 if (conf->dst == REG_C_0) {
1159 /* Copy to reg_c[0], within mask only. */
1160 reg_dst.offset = rte_bsf32(reg_c0);
1161 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1164 mask = rte_cpu_to_be_32(reg_c0);
1167 return flow_dv_convert_modify_action(&item,
1168 reg_src, ®_dst, res,
1169 MLX5_MODIFICATION_TYPE_COPY,
1174 * Convert MARK action to DV specification. This routine is used
1175 * in extensive metadata only and requires metadata register to be
1176 * handled. In legacy mode hardware tag resource is engaged.
1179 * Pointer to the rte_eth_dev structure.
1181 * Pointer to MARK action specification.
1182 * @param[in,out] resource
1183 * Pointer to the modify-header resource.
1185 * Pointer to the error structure.
1188 * 0 on success, a negative errno value otherwise and rte_errno is set.
1191 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1192 const struct rte_flow_action_mark *conf,
1193 struct mlx5_flow_dv_modify_hdr_resource *resource,
1194 struct rte_flow_error *error)
1196 struct mlx5_priv *priv = dev->data->dev_private;
1197 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1198 priv->sh->dv_mark_mask);
1199 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1200 struct rte_flow_item item = {
1204 struct field_modify_info reg_c_x[] = {
1210 return rte_flow_error_set(error, EINVAL,
1211 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1212 NULL, "zero mark action mask");
1213 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1216 MLX5_ASSERT(reg > 0);
1217 if (reg == REG_C_0) {
1218 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1219 uint32_t shl_c0 = rte_bsf32(msk_c0);
1221 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1222 mask = rte_cpu_to_be_32(mask) & msk_c0;
1223 mask = rte_cpu_to_be_32(mask << shl_c0);
1225 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1226 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1227 MLX5_MODIFICATION_TYPE_SET, error);
1231 * Get metadata register index for specified steering domain.
1234 * Pointer to the rte_eth_dev structure.
1236 * Attributes of flow to determine steering domain.
1238 * Pointer to the error structure.
1241 * positive index on success, a negative errno value otherwise
1242 * and rte_errno is set.
1244 static enum modify_reg
1245 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1246 const struct rte_flow_attr *attr,
1247 struct rte_flow_error *error)
1250 mlx5_flow_get_reg_id(dev, attr->transfer ?
1254 MLX5_METADATA_RX, 0, error);
1256 return rte_flow_error_set(error,
1257 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1258 NULL, "unavailable "
1259 "metadata register");
1264 * Convert SET_META action to DV specification.
1267 * Pointer to the rte_eth_dev structure.
1268 * @param[in,out] resource
1269 * Pointer to the modify-header resource.
1271 * Attributes of flow that includes this item.
1273 * Pointer to action specification.
1275 * Pointer to the error structure.
1278 * 0 on success, a negative errno value otherwise and rte_errno is set.
1281 flow_dv_convert_action_set_meta
1282 (struct rte_eth_dev *dev,
1283 struct mlx5_flow_dv_modify_hdr_resource *resource,
1284 const struct rte_flow_attr *attr,
1285 const struct rte_flow_action_set_meta *conf,
1286 struct rte_flow_error *error)
1288 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1289 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1290 struct rte_flow_item item = {
1294 struct field_modify_info reg_c_x[] = {
1297 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1301 MLX5_ASSERT(reg != REG_NON);
1302 if (reg == REG_C_0) {
1303 struct mlx5_priv *priv = dev->data->dev_private;
1304 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1305 uint32_t shl_c0 = rte_bsf32(msk_c0);
1307 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1308 mask = rte_cpu_to_be_32(mask) & msk_c0;
1309 mask = rte_cpu_to_be_32(mask << shl_c0);
1311 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1312 /* The routine expects parameters in memory as big-endian ones. */
1313 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1314 MLX5_MODIFICATION_TYPE_SET, error);
1318 * Convert modify-header set IPv4 DSCP action to DV specification.
1320 * @param[in,out] resource
1321 * Pointer to the modify-header resource.
1323 * Pointer to action specification.
1325 * Pointer to the error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_convert_action_modify_ipv4_dscp
1332 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333 const struct rte_flow_action *action,
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action_set_dscp *conf =
1337 (const struct rte_flow_action_set_dscp *)(action->conf);
1338 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1339 struct rte_flow_item_ipv4 ipv4;
1340 struct rte_flow_item_ipv4 ipv4_mask;
1342 memset(&ipv4, 0, sizeof(ipv4));
1343 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1344 ipv4.hdr.type_of_service = conf->dscp;
1345 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1347 item.mask = &ipv4_mask;
1348 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1349 MLX5_MODIFICATION_TYPE_SET, error);
1353 * Convert modify-header set IPv6 DSCP action to DV specification.
1355 * @param[in,out] resource
1356 * Pointer to the modify-header resource.
1358 * Pointer to action specification.
1360 * Pointer to the error structure.
1363 * 0 on success, a negative errno value otherwise and rte_errno is set.
1366 flow_dv_convert_action_modify_ipv6_dscp
1367 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1368 const struct rte_flow_action *action,
1369 struct rte_flow_error *error)
1371 const struct rte_flow_action_set_dscp *conf =
1372 (const struct rte_flow_action_set_dscp *)(action->conf);
1373 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1374 struct rte_flow_item_ipv6 ipv6;
1375 struct rte_flow_item_ipv6 ipv6_mask;
1377 memset(&ipv6, 0, sizeof(ipv6));
1378 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1380 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1381 * rdma-core only accept the DSCP bits byte aligned start from
1382 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1383 * bits in IPv6 case as rdma-core requires byte aligned value.
1385 ipv6.hdr.vtc_flow = conf->dscp;
1386 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1388 item.mask = &ipv6_mask;
1389 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1390 MLX5_MODIFICATION_TYPE_SET, error);
1394 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1395 enum rte_flow_field_id field, int inherit,
1396 const struct rte_flow_attr *attr,
1397 struct rte_flow_error *error)
1399 struct mlx5_priv *priv = dev->data->dev_private;
1402 case RTE_FLOW_FIELD_START:
1404 case RTE_FLOW_FIELD_MAC_DST:
1405 case RTE_FLOW_FIELD_MAC_SRC:
1407 case RTE_FLOW_FIELD_VLAN_TYPE:
1409 case RTE_FLOW_FIELD_VLAN_ID:
1411 case RTE_FLOW_FIELD_MAC_TYPE:
1413 case RTE_FLOW_FIELD_IPV4_DSCP:
1415 case RTE_FLOW_FIELD_IPV4_TTL:
1417 case RTE_FLOW_FIELD_IPV4_SRC:
1418 case RTE_FLOW_FIELD_IPV4_DST:
1420 case RTE_FLOW_FIELD_IPV6_DSCP:
1422 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1424 case RTE_FLOW_FIELD_IPV6_SRC:
1425 case RTE_FLOW_FIELD_IPV6_DST:
1427 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1428 case RTE_FLOW_FIELD_TCP_PORT_DST:
1430 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1431 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1433 case RTE_FLOW_FIELD_TCP_FLAGS:
1435 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1436 case RTE_FLOW_FIELD_UDP_PORT_DST:
1438 case RTE_FLOW_FIELD_VXLAN_VNI:
1439 case RTE_FLOW_FIELD_GENEVE_VNI:
1441 case RTE_FLOW_FIELD_GTP_TEID:
1442 case RTE_FLOW_FIELD_TAG:
1444 case RTE_FLOW_FIELD_MARK:
1445 return __builtin_popcount(priv->sh->dv_mark_mask);
1446 case RTE_FLOW_FIELD_META:
1447 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1448 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1449 case RTE_FLOW_FIELD_POINTER:
1450 case RTE_FLOW_FIELD_VALUE:
1451 return inherit < 0 ? 0 : inherit;
1459 mlx5_flow_field_id_to_modify_info
1460 (const struct rte_flow_action_modify_data *data,
1461 struct field_modify_info *info, uint32_t *mask,
1462 uint32_t width, struct rte_eth_dev *dev,
1463 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1465 struct mlx5_priv *priv = dev->data->dev_private;
1469 switch (data->field) {
1470 case RTE_FLOW_FIELD_START:
1471 /* not supported yet */
1474 case RTE_FLOW_FIELD_MAC_DST:
1475 off = data->offset > 16 ? data->offset - 16 : 0;
1477 if (data->offset < 16) {
1478 info[idx] = (struct field_modify_info){2, 4,
1479 MLX5_MODI_OUT_DMAC_15_0};
1481 mask[1] = rte_cpu_to_be_16(0xffff >>
1485 mask[1] = RTE_BE16(0xffff);
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1494 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1495 (32 - width)) << off);
1497 if (data->offset < 16)
1498 info[idx++] = (struct field_modify_info){2, 0,
1499 MLX5_MODI_OUT_DMAC_15_0};
1500 info[idx] = (struct field_modify_info){4, off,
1501 MLX5_MODI_OUT_DMAC_47_16};
1504 case RTE_FLOW_FIELD_MAC_SRC:
1505 off = data->offset > 16 ? data->offset - 16 : 0;
1507 if (data->offset < 16) {
1508 info[idx] = (struct field_modify_info){2, 4,
1509 MLX5_MODI_OUT_SMAC_15_0};
1511 mask[1] = rte_cpu_to_be_16(0xffff >>
1515 mask[1] = RTE_BE16(0xffff);
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1524 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1525 (32 - width)) << off);
1527 if (data->offset < 16)
1528 info[idx++] = (struct field_modify_info){2, 0,
1529 MLX5_MODI_OUT_SMAC_15_0};
1530 info[idx] = (struct field_modify_info){4, off,
1531 MLX5_MODI_OUT_SMAC_47_16};
1534 case RTE_FLOW_FIELD_VLAN_TYPE:
1535 /* not supported yet */
1537 case RTE_FLOW_FIELD_VLAN_ID:
1538 info[idx] = (struct field_modify_info){2, 0,
1539 MLX5_MODI_OUT_FIRST_VID};
1541 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1543 case RTE_FLOW_FIELD_MAC_TYPE:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_ETHERTYPE};
1547 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1549 case RTE_FLOW_FIELD_IPV4_DSCP:
1550 info[idx] = (struct field_modify_info){1, 0,
1551 MLX5_MODI_OUT_IP_DSCP};
1553 mask[idx] = 0x3f >> (6 - width);
1555 case RTE_FLOW_FIELD_IPV4_TTL:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IPV4_TTL};
1559 mask[idx] = 0xff >> (8 - width);
1561 case RTE_FLOW_FIELD_IPV4_SRC:
1562 info[idx] = (struct field_modify_info){4, 0,
1563 MLX5_MODI_OUT_SIPV4};
1565 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1568 case RTE_FLOW_FIELD_IPV4_DST:
1569 info[idx] = (struct field_modify_info){4, 0,
1570 MLX5_MODI_OUT_DIPV4};
1572 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1575 case RTE_FLOW_FIELD_IPV6_DSCP:
1576 info[idx] = (struct field_modify_info){1, 0,
1577 MLX5_MODI_OUT_IP_DSCP};
1579 mask[idx] = 0x3f >> (6 - width);
1581 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1585 mask[idx] = 0xff >> (8 - width);
1587 case RTE_FLOW_FIELD_IPV6_SRC:
1589 if (data->offset < 32) {
1590 info[idx] = (struct field_modify_info){4, 12,
1591 MLX5_MODI_OUT_SIPV6_31_0};
1594 rte_cpu_to_be_32(0xffffffff >>
1598 mask[3] = RTE_BE32(0xffffffff);
1605 if (data->offset < 64) {
1606 info[idx] = (struct field_modify_info){4, 8,
1607 MLX5_MODI_OUT_SIPV6_63_32};
1610 rte_cpu_to_be_32(0xffffffff >>
1614 mask[2] = RTE_BE32(0xffffffff);
1621 if (data->offset < 96) {
1622 info[idx] = (struct field_modify_info){4, 4,
1623 MLX5_MODI_OUT_SIPV6_95_64};
1626 rte_cpu_to_be_32(0xffffffff >>
1630 mask[1] = RTE_BE32(0xffffffff);
1637 info[idx] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_SIPV6_127_96};
1639 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1641 if (data->offset < 32)
1642 info[idx++] = (struct field_modify_info){4, 0,
1643 MLX5_MODI_OUT_SIPV6_31_0};
1644 if (data->offset < 64)
1645 info[idx++] = (struct field_modify_info){4, 0,
1646 MLX5_MODI_OUT_SIPV6_63_32};
1647 if (data->offset < 96)
1648 info[idx++] = (struct field_modify_info){4, 0,
1649 MLX5_MODI_OUT_SIPV6_95_64};
1650 if (data->offset < 128)
1651 info[idx++] = (struct field_modify_info){4, 0,
1652 MLX5_MODI_OUT_SIPV6_127_96};
1655 case RTE_FLOW_FIELD_IPV6_DST:
1657 if (data->offset < 32) {
1658 info[idx] = (struct field_modify_info){4, 12,
1659 MLX5_MODI_OUT_DIPV6_31_0};
1662 rte_cpu_to_be_32(0xffffffff >>
1666 mask[3] = RTE_BE32(0xffffffff);
1673 if (data->offset < 64) {
1674 info[idx] = (struct field_modify_info){4, 8,
1675 MLX5_MODI_OUT_DIPV6_63_32};
1678 rte_cpu_to_be_32(0xffffffff >>
1682 mask[2] = RTE_BE32(0xffffffff);
1689 if (data->offset < 96) {
1690 info[idx] = (struct field_modify_info){4, 4,
1691 MLX5_MODI_OUT_DIPV6_95_64};
1694 rte_cpu_to_be_32(0xffffffff >>
1698 mask[1] = RTE_BE32(0xffffffff);
1705 info[idx] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_127_96};
1707 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1709 if (data->offset < 32)
1710 info[idx++] = (struct field_modify_info){4, 0,
1711 MLX5_MODI_OUT_DIPV6_31_0};
1712 if (data->offset < 64)
1713 info[idx++] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_OUT_DIPV6_63_32};
1715 if (data->offset < 96)
1716 info[idx++] = (struct field_modify_info){4, 0,
1717 MLX5_MODI_OUT_DIPV6_95_64};
1718 if (data->offset < 128)
1719 info[idx++] = (struct field_modify_info){4, 0,
1720 MLX5_MODI_OUT_DIPV6_127_96};
1723 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1724 info[idx] = (struct field_modify_info){2, 0,
1725 MLX5_MODI_OUT_TCP_SPORT};
1727 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1729 case RTE_FLOW_FIELD_TCP_PORT_DST:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_DPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1736 info[idx] = (struct field_modify_info){4, 0,
1737 MLX5_MODI_OUT_TCP_SEQ_NUM};
1739 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1742 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1743 info[idx] = (struct field_modify_info){4, 0,
1744 MLX5_MODI_OUT_TCP_ACK_NUM};
1746 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1749 case RTE_FLOW_FIELD_TCP_FLAGS:
1750 info[idx] = (struct field_modify_info){2, 0,
1751 MLX5_MODI_OUT_TCP_FLAGS};
1753 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1755 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_UDP_SPORT};
1759 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_DST:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_DPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_VXLAN_VNI:
1768 /* not supported yet */
1770 case RTE_FLOW_FIELD_GENEVE_VNI:
1771 /* not supported yet*/
1773 case RTE_FLOW_FIELD_GTP_TEID:
1774 info[idx] = (struct field_modify_info){4, 0,
1775 MLX5_MODI_GTP_TEID};
1777 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1780 case RTE_FLOW_FIELD_TAG:
1782 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1783 data->level, error);
1786 MLX5_ASSERT(reg != REG_NON);
1787 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1788 info[idx] = (struct field_modify_info){4, 0,
1792 rte_cpu_to_be_32(0xffffffff >>
1796 case RTE_FLOW_FIELD_MARK:
1798 uint32_t mark_mask = priv->sh->dv_mark_mask;
1799 uint32_t mark_count = __builtin_popcount(mark_mask);
1800 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1804 MLX5_ASSERT(reg != REG_NON);
1805 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1806 info[idx] = (struct field_modify_info){4, 0,
1809 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1810 (mark_count - width)) & mark_mask);
1813 case RTE_FLOW_FIELD_META:
1815 uint32_t meta_mask = priv->sh->dv_meta_mask;
1816 uint32_t meta_count = __builtin_popcount(meta_mask);
1817 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1820 MLX5_ASSERT(reg != REG_NON);
1821 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1822 info[idx] = (struct field_modify_info){4, 0,
1825 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1826 (meta_count - width)) & meta_mask);
1829 case RTE_FLOW_FIELD_POINTER:
1830 case RTE_FLOW_FIELD_VALUE:
1838 * Convert modify_field action to DV specification.
1841 * Pointer to the rte_eth_dev structure.
1842 * @param[in,out] resource
1843 * Pointer to the modify-header resource.
1845 * Pointer to action specification.
1847 * Attributes of flow that includes this item.
1849 * Pointer to the error structure.
1852 * 0 on success, a negative errno value otherwise and rte_errno is set.
1855 flow_dv_convert_action_modify_field
1856 (struct rte_eth_dev *dev,
1857 struct mlx5_flow_dv_modify_hdr_resource *resource,
1858 const struct rte_flow_action *action,
1859 const struct rte_flow_attr *attr,
1860 struct rte_flow_error *error)
1862 const struct rte_flow_action_modify_field *conf =
1863 (const struct rte_flow_action_modify_field *)(action->conf);
1864 struct rte_flow_item item = {
1868 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1870 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1872 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1873 uint32_t type, meta = 0;
1875 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1876 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1877 type = MLX5_MODIFICATION_TYPE_SET;
1878 /** For SET fill the destination field (field) first. */
1879 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1882 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1883 (void *)(uintptr_t)conf->src.pvalue :
1884 (void *)(uintptr_t)&conf->src.value;
1885 if (conf->dst.field == RTE_FLOW_FIELD_META) {
1886 meta = *(const unaligned_uint32_t *)item.spec;
1887 meta = rte_cpu_to_be_32(meta);
1891 type = MLX5_MODIFICATION_TYPE_COPY;
1892 /** For COPY fill the destination field (dcopy) without mask. */
1893 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1896 /** Then construct the source field (field) with mask. */
1897 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1902 return flow_dv_convert_modify_action(&item,
1903 field, dcopy, resource, type, error);
1907 * Validate MARK item.
1910 * Pointer to the rte_eth_dev structure.
1912 * Item specification.
1914 * Attributes of flow that includes this item.
1916 * Pointer to error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1923 const struct rte_flow_item *item,
1924 const struct rte_flow_attr *attr __rte_unused,
1925 struct rte_flow_error *error)
1927 struct mlx5_priv *priv = dev->data->dev_private;
1928 struct mlx5_sh_config *config = &priv->sh->config;
1929 const struct rte_flow_item_mark *spec = item->spec;
1930 const struct rte_flow_item_mark *mask = item->mask;
1931 const struct rte_flow_item_mark nic_mask = {
1932 .id = priv->sh->dv_mark_mask,
1936 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "extended metadata feature"
1941 if (!mlx5_flow_ext_mreg_supported(dev))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "extended metadata register"
1945 " isn't supported");
1947 return rte_flow_error_set(error, ENOTSUP,
1948 RTE_FLOW_ERROR_TYPE_ITEM, item,
1949 "extended metadata register"
1950 " isn't available");
1951 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1958 "data cannot be empty");
1959 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1960 return rte_flow_error_set(error, EINVAL,
1961 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1963 "mark id exceeds the limit");
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1969 "mask cannot be zero");
1971 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1972 (const uint8_t *)&nic_mask,
1973 sizeof(struct rte_flow_item_mark),
1974 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1981 * Validate META item.
1984 * Pointer to the rte_eth_dev structure.
1986 * Item specification.
1988 * Attributes of flow that includes this item.
1990 * Pointer to error structure.
1993 * 0 on success, a negative errno value otherwise and rte_errno is set.
1996 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1997 const struct rte_flow_item *item,
1998 const struct rte_flow_attr *attr,
1999 struct rte_flow_error *error)
2001 struct mlx5_priv *priv = dev->data->dev_private;
2002 struct mlx5_sh_config *config = &priv->sh->config;
2003 const struct rte_flow_item_meta *spec = item->spec;
2004 const struct rte_flow_item_meta *mask = item->mask;
2005 struct rte_flow_item_meta nic_mask = {
2012 return rte_flow_error_set(error, EINVAL,
2013 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2015 "data cannot be empty");
2016 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2017 if (!mlx5_flow_ext_mreg_supported(dev))
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ITEM, item,
2020 "extended metadata register"
2021 " isn't supported");
2022 reg = flow_dv_get_metadata_reg(dev, attr, error);
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ITEM, item,
2028 "unavailable extended metadata register");
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 nic_mask.data = priv->sh->dv_meta_mask;
2038 return rte_flow_error_set(error, ENOTSUP,
2039 RTE_FLOW_ERROR_TYPE_ITEM, item,
2040 "extended metadata feature "
2041 "should be enabled when "
2042 "meta item is requested "
2043 "with e-switch mode ");
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "match on metadata for ingress "
2048 "is not supported in legacy "
2052 mask = &rte_flow_item_meta_mask;
2054 return rte_flow_error_set(error, EINVAL,
2055 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2056 "mask cannot be zero");
2058 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2059 (const uint8_t *)&nic_mask,
2060 sizeof(struct rte_flow_item_meta),
2061 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066 * Validate TAG item.
2069 * Pointer to the rte_eth_dev structure.
2071 * Item specification.
2073 * Attributes of flow that includes this item.
2075 * Pointer to error structure.
2078 * 0 on success, a negative errno value otherwise and rte_errno is set.
2081 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2082 const struct rte_flow_item *item,
2083 const struct rte_flow_attr *attr __rte_unused,
2084 struct rte_flow_error *error)
2086 const struct rte_flow_item_tag *spec = item->spec;
2087 const struct rte_flow_item_tag *mask = item->mask;
2088 const struct rte_flow_item_tag nic_mask = {
2089 .data = RTE_BE32(UINT32_MAX),
2094 if (!mlx5_flow_ext_mreg_supported(dev))
2095 return rte_flow_error_set(error, ENOTSUP,
2096 RTE_FLOW_ERROR_TYPE_ITEM, item,
2097 "extensive metadata register"
2098 " isn't supported");
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2103 "data cannot be empty");
2105 mask = &rte_flow_item_tag_mask;
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2109 "mask cannot be zero");
2111 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2112 (const uint8_t *)&nic_mask,
2113 sizeof(struct rte_flow_item_tag),
2114 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2117 if (mask->index != 0xff)
2118 return rte_flow_error_set(error, EINVAL,
2119 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2120 "partial mask for tag index"
2121 " is not supported");
2122 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2125 MLX5_ASSERT(ret != REG_NON);
2130 * Validate vport item.
2133 * Pointer to the rte_eth_dev structure.
2135 * Item specification.
2137 * Attributes of flow that includes this item.
2138 * @param[in] item_flags
2139 * Bit-fields that holds the items detected until now.
2141 * Pointer to error structure.
2144 * 0 on success, a negative errno value otherwise and rte_errno is set.
2147 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2148 const struct rte_flow_item *item,
2149 const struct rte_flow_attr *attr,
2150 uint64_t item_flags,
2151 struct rte_flow_error *error)
2153 const struct rte_flow_item_port_id *spec = item->spec;
2154 const struct rte_flow_item_port_id *mask = item->mask;
2155 const struct rte_flow_item_port_id switch_mask = {
2158 struct mlx5_priv *esw_priv;
2159 struct mlx5_priv *dev_priv;
2162 if (!attr->transfer)
2163 return rte_flow_error_set(error, EINVAL,
2164 RTE_FLOW_ERROR_TYPE_ITEM,
2166 "match on port id is valid only"
2167 " when transfer flag is enabled");
2168 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2169 return rte_flow_error_set(error, ENOTSUP,
2170 RTE_FLOW_ERROR_TYPE_ITEM, item,
2171 "multiple source ports are not"
2174 mask = &switch_mask;
2175 if (mask->id != 0xffffffff)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2179 "no support for partial mask on"
2181 ret = mlx5_flow_item_acceptable
2182 (item, (const uint8_t *)mask,
2183 (const uint8_t *)&rte_flow_item_port_id_mask,
2184 sizeof(struct rte_flow_item_port_id),
2185 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2190 if (spec->id == MLX5_PORT_ESW_MGR)
2192 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2194 return rte_flow_error_set(error, rte_errno,
2195 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2196 "failed to obtain E-Switch info for"
2198 dev_priv = mlx5_dev_to_eswitch_info(dev);
2200 return rte_flow_error_set(error, rte_errno,
2201 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2203 "failed to obtain E-Switch info");
2204 if (esw_priv->domain_id != dev_priv->domain_id)
2205 return rte_flow_error_set(error, EINVAL,
2206 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2207 "cannot match on a port from a"
2208 " different E-Switch");
2213 * Validate VLAN item.
2216 * Item specification.
2217 * @param[in] item_flags
2218 * Bit-fields that holds the items detected until now.
2220 * Ethernet device flow is being created on.
2222 * Pointer to error structure.
2225 * 0 on success, a negative errno value otherwise and rte_errno is set.
2228 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2229 uint64_t item_flags,
2230 struct rte_eth_dev *dev,
2231 struct rte_flow_error *error)
2233 const struct rte_flow_item_vlan *mask = item->mask;
2234 const struct rte_flow_item_vlan nic_mask = {
2235 .tci = RTE_BE16(UINT16_MAX),
2236 .inner_type = RTE_BE16(UINT16_MAX),
2239 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2241 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2242 MLX5_FLOW_LAYER_INNER_L4) :
2243 (MLX5_FLOW_LAYER_OUTER_L3 |
2244 MLX5_FLOW_LAYER_OUTER_L4);
2245 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2246 MLX5_FLOW_LAYER_OUTER_VLAN;
2248 if (item_flags & vlanm)
2249 return rte_flow_error_set(error, EINVAL,
2250 RTE_FLOW_ERROR_TYPE_ITEM, item,
2251 "multiple VLAN layers not supported");
2252 else if ((item_flags & l34m) != 0)
2253 return rte_flow_error_set(error, EINVAL,
2254 RTE_FLOW_ERROR_TYPE_ITEM, item,
2255 "VLAN cannot follow L3/L4 layer");
2257 mask = &rte_flow_item_vlan_mask;
2258 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2259 (const uint8_t *)&nic_mask,
2260 sizeof(struct rte_flow_item_vlan),
2261 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2264 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2265 struct mlx5_priv *priv = dev->data->dev_private;
2267 if (priv->vmwa_context) {
2269 * Non-NULL context means we have a virtual machine
2270 * and SR-IOV enabled, we have to create VLAN interface
2271 * to make hypervisor to setup E-Switch vport
2272 * context correctly. We avoid creating the multiple
2273 * VLAN interfaces, so we cannot support VLAN tag mask.
2275 return rte_flow_error_set(error, EINVAL,
2276 RTE_FLOW_ERROR_TYPE_ITEM,
2278 "VLAN tag mask is not"
2279 " supported in virtual"
2287 * GTP flags are contained in 1 byte of the format:
2288 * -------------------------------------------
2289 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2290 * |-----------------------------------------|
2291 * | value | Version | PT | Res | E | S | PN |
2292 * -------------------------------------------
2294 * Matching is supported only for GTP flags E, S, PN.
2296 #define MLX5_GTP_FLAGS_MASK 0x07
2299 * Validate GTP item.
2302 * Pointer to the rte_eth_dev structure.
2304 * Item specification.
2305 * @param[in] item_flags
2306 * Bit-fields that holds the items detected until now.
2308 * Pointer to error structure.
2311 * 0 on success, a negative errno value otherwise and rte_errno is set.
2314 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2315 const struct rte_flow_item *item,
2316 uint64_t item_flags,
2317 struct rte_flow_error *error)
2319 struct mlx5_priv *priv = dev->data->dev_private;
2320 const struct rte_flow_item_gtp *spec = item->spec;
2321 const struct rte_flow_item_gtp *mask = item->mask;
2322 const struct rte_flow_item_gtp nic_mask = {
2323 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2325 .teid = RTE_BE32(0xffffffff),
2328 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_gtp)
2329 return rte_flow_error_set(error, ENOTSUP,
2330 RTE_FLOW_ERROR_TYPE_ITEM, item,
2331 "GTP support is not enabled");
2332 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2333 return rte_flow_error_set(error, ENOTSUP,
2334 RTE_FLOW_ERROR_TYPE_ITEM, item,
2335 "multiple tunnel layers not"
2337 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2338 return rte_flow_error_set(error, EINVAL,
2339 RTE_FLOW_ERROR_TYPE_ITEM, item,
2340 "no outer UDP layer found");
2342 mask = &rte_flow_item_gtp_mask;
2343 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2344 return rte_flow_error_set(error, ENOTSUP,
2345 RTE_FLOW_ERROR_TYPE_ITEM, item,
2346 "Match is supported for GTP"
2348 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2349 (const uint8_t *)&nic_mask,
2350 sizeof(struct rte_flow_item_gtp),
2351 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2355 * Validate GTP PSC item.
2358 * Item specification.
2359 * @param[in] last_item
2360 * Previous validated item in the pattern items.
2361 * @param[in] gtp_item
2362 * Previous GTP item specification.
2364 * Pointer to flow attributes.
2366 * Pointer to error structure.
2369 * 0 on success, a negative errno value otherwise and rte_errno is set.
2372 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2374 const struct rte_flow_item *gtp_item,
2375 const struct rte_flow_attr *attr,
2376 struct rte_flow_error *error)
2378 const struct rte_flow_item_gtp *gtp_spec;
2379 const struct rte_flow_item_gtp *gtp_mask;
2380 const struct rte_flow_item_gtp_psc *mask;
2381 const struct rte_flow_item_gtp_psc nic_mask = {
2386 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2387 return rte_flow_error_set
2388 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2389 "GTP PSC item must be preceded with GTP item");
2390 gtp_spec = gtp_item->spec;
2391 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2392 /* GTP spec and E flag is requested to match zero. */
2394 (gtp_mask->v_pt_rsv_flags &
2395 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2396 return rte_flow_error_set
2397 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2398 "GTP E flag must be 1 to match GTP PSC");
2399 /* Check the flow is not created in group zero. */
2400 if (!attr->transfer && !attr->group)
2401 return rte_flow_error_set
2402 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2403 "GTP PSC is not supported for group 0");
2404 /* GTP spec is here and E flag is requested to match zero. */
2407 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2408 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2409 (const uint8_t *)&nic_mask,
2410 sizeof(struct rte_flow_item_gtp_psc),
2411 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2415 * Validate IPV4 item.
2416 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2417 * add specific validation of fragment_offset field,
2420 * Item specification.
2421 * @param[in] item_flags
2422 * Bit-fields that holds the items detected until now.
2424 * Pointer to error structure.
2427 * 0 on success, a negative errno value otherwise and rte_errno is set.
2430 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2431 const struct rte_flow_item *item,
2432 uint64_t item_flags, uint64_t last_item,
2433 uint16_t ether_type, struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
2438 const struct rte_flow_item_ipv4 *spec = item->spec;
2439 const struct rte_flow_item_ipv4 *last = item->last;
2440 const struct rte_flow_item_ipv4 *mask = item->mask;
2441 rte_be16_t fragment_offset_spec = 0;
2442 rte_be16_t fragment_offset_last = 0;
2443 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2445 .src_addr = RTE_BE32(0xffffffff),
2446 .dst_addr = RTE_BE32(0xffffffff),
2447 .type_of_service = 0xff,
2448 .fragment_offset = RTE_BE16(0xffff),
2449 .next_proto_id = 0xff,
2450 .time_to_live = 0xff,
2454 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2455 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2456 bool ihl_cap = !tunnel ?
2457 attr->outer_ipv4_ihl : attr->inner_ipv4_ihl;
2459 return rte_flow_error_set(error, ENOTSUP,
2460 RTE_FLOW_ERROR_TYPE_ITEM,
2462 "IPV4 ihl offload not supported");
2463 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2465 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2466 ether_type, &nic_ipv4_mask,
2467 MLX5_ITEM_RANGE_ACCEPTED, error);
2471 fragment_offset_spec = spec->hdr.fragment_offset &
2472 mask->hdr.fragment_offset;
2473 if (!fragment_offset_spec)
2476 * spec and mask are valid, enforce using full mask to make sure the
2477 * complete value is used correctly.
2479 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2480 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2481 return rte_flow_error_set(error, EINVAL,
2482 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483 item, "must use full mask for"
2484 " fragment_offset");
2486 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2487 * indicating this is 1st fragment of fragmented packet.
2488 * This is not yet supported in MLX5, return appropriate error message.
2490 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2491 return rte_flow_error_set(error, ENOTSUP,
2492 RTE_FLOW_ERROR_TYPE_ITEM, item,
2493 "match on first fragment not "
2495 if (fragment_offset_spec && !last)
2496 return rte_flow_error_set(error, ENOTSUP,
2497 RTE_FLOW_ERROR_TYPE_ITEM, item,
2498 "specified value not supported");
2499 /* spec and last are valid, validate the specified range. */
2500 fragment_offset_last = last->hdr.fragment_offset &
2501 mask->hdr.fragment_offset;
2503 * Match on fragment_offset spec 0x2001 and last 0x3fff
2504 * means MF is 1 and frag-offset is > 0.
2505 * This packet is fragment 2nd and onward, excluding last.
2506 * This is not yet supported in MLX5, return appropriate
2509 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2510 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2511 return rte_flow_error_set(error, ENOTSUP,
2512 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2513 last, "match on following "
2514 "fragments not supported");
2516 * Match on fragment_offset spec 0x0001 and last 0x1fff
2517 * means MF is 0 and frag-offset is > 0.
2518 * This packet is last fragment of fragmented packet.
2519 * This is not yet supported in MLX5, return appropriate
2522 if (fragment_offset_spec == RTE_BE16(1) &&
2523 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2524 return rte_flow_error_set(error, ENOTSUP,
2525 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2526 last, "match on last "
2527 "fragment not supported");
2529 * Match on fragment_offset spec 0x0001 and last 0x3fff
2530 * means MF and/or frag-offset is not 0.
2531 * This is a fragmented packet.
2532 * Other range values are invalid and rejected.
2534 if (!(fragment_offset_spec == RTE_BE16(1) &&
2535 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2536 return rte_flow_error_set(error, ENOTSUP,
2537 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2538 "specified range not supported");
2543 * Validate IPV6 fragment extension item.
2546 * Item specification.
2547 * @param[in] item_flags
2548 * Bit-fields that holds the items detected until now.
2550 * Pointer to error structure.
2553 * 0 on success, a negative errno value otherwise and rte_errno is set.
2556 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2557 uint64_t item_flags,
2558 struct rte_flow_error *error)
2560 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2561 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2562 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2563 rte_be16_t frag_data_spec = 0;
2564 rte_be16_t frag_data_last = 0;
2565 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2566 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2567 MLX5_FLOW_LAYER_OUTER_L4;
2569 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2571 .next_header = 0xff,
2572 .frag_data = RTE_BE16(0xffff),
2576 if (item_flags & l4m)
2577 return rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM, item,
2579 "ipv6 fragment extension item cannot "
2581 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2582 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item must "
2586 "follow ipv6 item");
2588 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2589 if (!frag_data_spec)
2592 * spec and mask are valid, enforce using full mask to make sure the
2593 * complete value is used correctly.
2595 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2596 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2597 return rte_flow_error_set(error, EINVAL,
2598 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2599 item, "must use full mask for"
2602 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2603 * This is 1st fragment of fragmented packet.
2605 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2606 return rte_flow_error_set(error, ENOTSUP,
2607 RTE_FLOW_ERROR_TYPE_ITEM, item,
2608 "match on first fragment not "
2610 if (frag_data_spec && !last)
2611 return rte_flow_error_set(error, EINVAL,
2612 RTE_FLOW_ERROR_TYPE_ITEM, item,
2613 "specified value not supported");
2614 ret = mlx5_flow_item_acceptable
2615 (item, (const uint8_t *)mask,
2616 (const uint8_t *)&nic_mask,
2617 sizeof(struct rte_flow_item_ipv6_frag_ext),
2618 MLX5_ITEM_RANGE_ACCEPTED, error);
2621 /* spec and last are valid, validate the specified range. */
2622 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2624 * Match on frag_data spec 0x0009 and last 0xfff9
2625 * means M is 1 and frag-offset is > 0.
2626 * This packet is fragment 2nd and onward, excluding last.
2627 * This is not yet supported in MLX5, return appropriate
2630 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2631 RTE_IPV6_EHDR_MF_MASK) &&
2632 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2633 return rte_flow_error_set(error, ENOTSUP,
2634 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2635 last, "match on following "
2636 "fragments not supported");
2638 * Match on frag_data spec 0x0008 and last 0xfff8
2639 * means M is 0 and frag-offset is > 0.
2640 * This packet is last fragment of fragmented packet.
2641 * This is not yet supported in MLX5, return appropriate
2644 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2645 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2646 return rte_flow_error_set(error, ENOTSUP,
2647 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2648 last, "match on last "
2649 "fragment not supported");
2650 /* Other range values are invalid and rejected. */
2651 return rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2653 "specified range not supported");
2657 * Validate ASO CT item.
2660 * Pointer to the rte_eth_dev structure.
2662 * Item specification.
2663 * @param[in] item_flags
2664 * Pointer to bit-fields that holds the items detected until now.
2666 * Pointer to error structure.
2669 * 0 on success, a negative errno value otherwise and rte_errno is set.
2672 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2673 const struct rte_flow_item *item,
2674 uint64_t *item_flags,
2675 struct rte_flow_error *error)
2677 const struct rte_flow_item_conntrack *spec = item->spec;
2678 const struct rte_flow_item_conntrack *mask = item->mask;
2682 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2683 return rte_flow_error_set(error, EINVAL,
2684 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2685 "Only one CT is supported");
2687 mask = &rte_flow_item_conntrack_mask;
2688 flags = spec->flags & mask->flags;
2689 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2690 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2691 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2692 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2693 return rte_flow_error_set(error, EINVAL,
2694 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2695 "Conflict status bits");
2696 /* State change also needs to be considered. */
2697 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2702 * Validate the pop VLAN action.
2705 * Pointer to the rte_eth_dev structure.
2706 * @param[in] action_flags
2707 * Holds the actions detected until now.
2709 * Pointer to the pop vlan action.
2710 * @param[in] item_flags
2711 * The items found in this flow rule.
2713 * Pointer to flow attributes.
2715 * Pointer to error structure.
2718 * 0 on success, a negative errno value otherwise and rte_errno is set.
2721 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2722 uint64_t action_flags,
2723 const struct rte_flow_action *action,
2724 uint64_t item_flags,
2725 const struct rte_flow_attr *attr,
2726 struct rte_flow_error *error)
2728 const struct mlx5_priv *priv = dev->data->dev_private;
2729 struct mlx5_dev_ctx_shared *sh = priv->sh;
2730 bool direction_error = false;
2732 if (!priv->sh->pop_vlan_action)
2733 return rte_flow_error_set(error, ENOTSUP,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2736 "pop vlan action is not supported");
2737 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2738 if (attr->transfer) {
2739 bool fdb_tx = priv->representor_id != UINT16_MAX;
2740 bool is_cx5 = sh->steering_format_version ==
2741 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2743 if (fdb_tx && is_cx5)
2744 direction_error = true;
2745 } else if (attr->egress) {
2746 direction_error = true;
2748 if (direction_error)
2749 return rte_flow_error_set(error, ENOTSUP,
2750 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2752 "pop vlan action not supported for egress");
2753 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2754 return rte_flow_error_set(error, ENOTSUP,
2755 RTE_FLOW_ERROR_TYPE_ACTION, action,
2756 "no support for multiple VLAN "
2758 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2759 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2760 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2761 return rte_flow_error_set(error, ENOTSUP,
2762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2764 "cannot pop vlan after decap without "
2765 "match on inner vlan in the flow");
2766 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2767 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2768 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2769 return rte_flow_error_set(error, ENOTSUP,
2770 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2772 "cannot pop vlan without a "
2773 "match on (outer) vlan in the flow");
2774 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION, action,
2777 "wrong action order, port_id should "
2778 "be after pop VLAN action");
2779 if (!attr->transfer && priv->representor)
2780 return rte_flow_error_set(error, ENOTSUP,
2781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2782 "pop vlan action for VF representor "
2783 "not supported on NIC table");
2788 * Get VLAN default info from vlan match info.
2791 * the list of item specifications.
2793 * pointer VLAN info to fill to.
2796 * 0 on success, a negative errno value otherwise and rte_errno is set.
2799 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2800 struct rte_vlan_hdr *vlan)
2802 const struct rte_flow_item_vlan nic_mask = {
2803 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2804 MLX5DV_FLOW_VLAN_VID_MASK),
2805 .inner_type = RTE_BE16(0xffff),
2810 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2811 int type = items->type;
2813 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2814 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2817 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2818 const struct rte_flow_item_vlan *vlan_m = items->mask;
2819 const struct rte_flow_item_vlan *vlan_v = items->spec;
2821 /* If VLAN item in pattern doesn't contain data, return here. */
2826 /* Only full match values are accepted */
2827 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2828 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2829 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2831 rte_be_to_cpu_16(vlan_v->tci &
2832 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2834 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2835 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2836 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2838 rte_be_to_cpu_16(vlan_v->tci &
2839 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2841 if (vlan_m->inner_type == nic_mask.inner_type)
2842 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2843 vlan_m->inner_type);
2848 * Validate the push VLAN action.
2851 * Pointer to the rte_eth_dev structure.
2852 * @param[in] action_flags
2853 * Holds the actions detected until now.
2854 * @param[in] item_flags
2855 * The items found in this flow rule.
2857 * Pointer to the action structure.
2859 * Pointer to flow attributes
2861 * Pointer to error structure.
2864 * 0 on success, a negative errno value otherwise and rte_errno is set.
2867 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2868 uint64_t action_flags,
2869 const struct rte_flow_item_vlan *vlan_m,
2870 const struct rte_flow_action *action,
2871 const struct rte_flow_attr *attr,
2872 struct rte_flow_error *error)
2874 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2875 const struct mlx5_priv *priv = dev->data->dev_private;
2877 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2878 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2879 return rte_flow_error_set(error, EINVAL,
2880 RTE_FLOW_ERROR_TYPE_ACTION, action,
2881 "invalid vlan ethertype");
2882 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2883 return rte_flow_error_set(error, EINVAL,
2884 RTE_FLOW_ERROR_TYPE_ACTION, action,
2885 "wrong action order, port_id should "
2886 "be after push VLAN");
2887 if (!attr->transfer && priv->representor)
2888 return rte_flow_error_set(error, ENOTSUP,
2889 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2890 "push vlan action for VF representor "
2891 "not supported on NIC table");
2893 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2894 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2895 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2896 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2897 !(mlx5_flow_find_action
2898 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2899 return rte_flow_error_set(error, EINVAL,
2900 RTE_FLOW_ERROR_TYPE_ACTION, action,
2901 "not full match mask on VLAN PCP and "
2902 "there is no of_set_vlan_pcp action, "
2903 "push VLAN action cannot figure out "
2906 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2907 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2908 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2909 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2910 !(mlx5_flow_find_action
2911 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2912 return rte_flow_error_set(error, EINVAL,
2913 RTE_FLOW_ERROR_TYPE_ACTION, action,
2914 "not full match mask on VLAN VID and "
2915 "there is no of_set_vlan_vid action, "
2916 "push VLAN action cannot figure out "
2923 * Validate the set VLAN PCP.
2925 * @param[in] action_flags
2926 * Holds the actions detected until now.
2927 * @param[in] actions
2928 * Pointer to the list of actions remaining in the flow rule.
2930 * Pointer to error structure.
2933 * 0 on success, a negative errno value otherwise and rte_errno is set.
2936 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2937 const struct rte_flow_action actions[],
2938 struct rte_flow_error *error)
2940 const struct rte_flow_action *action = actions;
2941 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2943 if (conf->vlan_pcp > 7)
2944 return rte_flow_error_set(error, EINVAL,
2945 RTE_FLOW_ERROR_TYPE_ACTION, action,
2946 "VLAN PCP value is too big");
2947 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2948 return rte_flow_error_set(error, ENOTSUP,
2949 RTE_FLOW_ERROR_TYPE_ACTION, action,
2950 "set VLAN PCP action must follow "
2951 "the push VLAN action");
2952 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2953 return rte_flow_error_set(error, ENOTSUP,
2954 RTE_FLOW_ERROR_TYPE_ACTION, action,
2955 "Multiple VLAN PCP modification are "
2957 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2958 return rte_flow_error_set(error, EINVAL,
2959 RTE_FLOW_ERROR_TYPE_ACTION, action,
2960 "wrong action order, port_id should "
2961 "be after set VLAN PCP");
2966 * Validate the set VLAN VID.
2968 * @param[in] item_flags
2969 * Holds the items detected in this rule.
2970 * @param[in] action_flags
2971 * Holds the actions detected until now.
2972 * @param[in] actions
2973 * Pointer to the list of actions remaining in the flow rule.
2975 * Pointer to error structure.
2978 * 0 on success, a negative errno value otherwise and rte_errno is set.
2981 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2982 uint64_t action_flags,
2983 const struct rte_flow_action actions[],
2984 struct rte_flow_error *error)
2986 const struct rte_flow_action *action = actions;
2987 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2989 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2990 return rte_flow_error_set(error, EINVAL,
2991 RTE_FLOW_ERROR_TYPE_ACTION, action,
2992 "VLAN VID value is too big");
2993 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2994 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2995 return rte_flow_error_set(error, ENOTSUP,
2996 RTE_FLOW_ERROR_TYPE_ACTION, action,
2997 "set VLAN VID action must follow push"
2998 " VLAN action or match on VLAN item");
2999 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3000 return rte_flow_error_set(error, ENOTSUP,
3001 RTE_FLOW_ERROR_TYPE_ACTION, action,
3002 "Multiple VLAN VID modifications are "
3004 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3005 return rte_flow_error_set(error, EINVAL,
3006 RTE_FLOW_ERROR_TYPE_ACTION, action,
3007 "wrong action order, port_id should "
3008 "be after set VLAN VID");
3013 * Validate the FLAG action.
3016 * Pointer to the rte_eth_dev structure.
3017 * @param[in] action_flags
3018 * Holds the actions detected until now.
3020 * Pointer to flow attributes
3022 * Pointer to error structure.
3025 * 0 on success, a negative errno value otherwise and rte_errno is set.
3028 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3029 uint64_t action_flags,
3030 const struct rte_flow_attr *attr,
3031 struct rte_flow_error *error)
3033 struct mlx5_priv *priv = dev->data->dev_private;
3034 struct mlx5_sh_config *config = &priv->sh->config;
3037 /* Fall back if no extended metadata register support. */
3038 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3039 return mlx5_flow_validate_action_flag(action_flags, attr,
3041 /* Extensive metadata mode requires registers. */
3042 if (!mlx5_flow_ext_mreg_supported(dev))
3043 return rte_flow_error_set(error, ENOTSUP,
3044 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3045 "no metadata registers "
3046 "to support flag action");
3047 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3048 return rte_flow_error_set(error, ENOTSUP,
3049 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3050 "extended metadata register"
3051 " isn't available");
3052 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3055 MLX5_ASSERT(ret > 0);
3056 if (action_flags & MLX5_FLOW_ACTION_MARK)
3057 return rte_flow_error_set(error, EINVAL,
3058 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3059 "can't mark and flag in same flow");
3060 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3061 return rte_flow_error_set(error, EINVAL,
3062 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3064 " actions in same flow");
3069 * Validate MARK action.
3072 * Pointer to the rte_eth_dev structure.
3074 * Pointer to action.
3075 * @param[in] action_flags
3076 * Holds the actions detected until now.
3078 * Pointer to flow attributes
3080 * Pointer to error structure.
3083 * 0 on success, a negative errno value otherwise and rte_errno is set.
3086 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3087 const struct rte_flow_action *action,
3088 uint64_t action_flags,
3089 const struct rte_flow_attr *attr,
3090 struct rte_flow_error *error)
3092 struct mlx5_priv *priv = dev->data->dev_private;
3093 struct mlx5_sh_config *config = &priv->sh->config;
3094 const struct rte_flow_action_mark *mark = action->conf;
3097 if (is_tunnel_offload_active(dev))
3098 return rte_flow_error_set(error, ENOTSUP,
3099 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3101 "if tunnel offload active");
3102 /* Fall back if no extended metadata register support. */
3103 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3104 return mlx5_flow_validate_action_mark(action, action_flags,
3106 /* Extensive metadata mode requires registers. */
3107 if (!mlx5_flow_ext_mreg_supported(dev))
3108 return rte_flow_error_set(error, ENOTSUP,
3109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3110 "no metadata registers "
3111 "to support mark action");
3112 if (!priv->sh->dv_mark_mask)
3113 return rte_flow_error_set(error, ENOTSUP,
3114 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3115 "extended metadata register"
3116 " isn't available");
3117 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3120 MLX5_ASSERT(ret > 0);
3122 return rte_flow_error_set(error, EINVAL,
3123 RTE_FLOW_ERROR_TYPE_ACTION, action,
3124 "configuration cannot be null");
3125 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3126 return rte_flow_error_set(error, EINVAL,
3127 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3129 "mark id exceeds the limit");
3130 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3131 return rte_flow_error_set(error, EINVAL,
3132 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3133 "can't flag and mark in same flow");
3134 if (action_flags & MLX5_FLOW_ACTION_MARK)
3135 return rte_flow_error_set(error, EINVAL,
3136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3137 "can't have 2 mark actions in same"
3143 * Validate SET_META action.
3146 * Pointer to the rte_eth_dev structure.
3148 * Pointer to the action structure.
3149 * @param[in] action_flags
3150 * Holds the actions detected until now.
3152 * Pointer to flow attributes
3154 * Pointer to error structure.
3157 * 0 on success, a negative errno value otherwise and rte_errno is set.
3160 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3161 const struct rte_flow_action *action,
3162 uint64_t action_flags __rte_unused,
3163 const struct rte_flow_attr *attr,
3164 struct rte_flow_error *error)
3166 struct mlx5_priv *priv = dev->data->dev_private;
3167 struct mlx5_sh_config *config = &priv->sh->config;
3168 const struct rte_flow_action_set_meta *conf;
3169 uint32_t nic_mask = UINT32_MAX;
3172 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3173 !mlx5_flow_ext_mreg_supported(dev))
3174 return rte_flow_error_set(error, ENOTSUP,
3175 RTE_FLOW_ERROR_TYPE_ACTION, action,
3176 "extended metadata register"
3177 " isn't supported");
3178 reg = flow_dv_get_metadata_reg(dev, attr, error);
3182 return rte_flow_error_set(error, ENOTSUP,
3183 RTE_FLOW_ERROR_TYPE_ACTION, action,
3184 "unavailable extended metadata register");
3185 if (reg != REG_A && reg != REG_B) {
3186 struct mlx5_priv *priv = dev->data->dev_private;
3188 nic_mask = priv->sh->dv_meta_mask;
3190 if (!(action->conf))
3191 return rte_flow_error_set(error, EINVAL,
3192 RTE_FLOW_ERROR_TYPE_ACTION, action,
3193 "configuration cannot be null");
3194 conf = (const struct rte_flow_action_set_meta *)action->conf;
3196 return rte_flow_error_set(error, EINVAL,
3197 RTE_FLOW_ERROR_TYPE_ACTION, action,
3198 "zero mask doesn't have any effect");
3199 if (conf->mask & ~nic_mask)
3200 return rte_flow_error_set(error, EINVAL,
3201 RTE_FLOW_ERROR_TYPE_ACTION, action,
3202 "meta data must be within reg C0");
3207 * Validate SET_TAG action.
3210 * Pointer to the rte_eth_dev structure.
3212 * Pointer to the action structure.
3213 * @param[in] action_flags
3214 * Holds the actions detected until now.
3216 * Pointer to flow attributes
3218 * Pointer to error structure.
3221 * 0 on success, a negative errno value otherwise and rte_errno is set.
3224 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3225 const struct rte_flow_action *action,
3226 uint64_t action_flags,
3227 const struct rte_flow_attr *attr,
3228 struct rte_flow_error *error)
3230 const struct rte_flow_action_set_tag *conf;
3231 const uint64_t terminal_action_flags =
3232 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3233 MLX5_FLOW_ACTION_RSS;
3236 if (!mlx5_flow_ext_mreg_supported(dev))
3237 return rte_flow_error_set(error, ENOTSUP,
3238 RTE_FLOW_ERROR_TYPE_ACTION, action,
3239 "extensive metadata register"
3240 " isn't supported");
3241 if (!(action->conf))
3242 return rte_flow_error_set(error, EINVAL,
3243 RTE_FLOW_ERROR_TYPE_ACTION, action,
3244 "configuration cannot be null");
3245 conf = (const struct rte_flow_action_set_tag *)action->conf;
3247 return rte_flow_error_set(error, EINVAL,
3248 RTE_FLOW_ERROR_TYPE_ACTION, action,
3249 "zero mask doesn't have any effect");
3250 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3253 if (!attr->transfer && attr->ingress &&
3254 (action_flags & terminal_action_flags))
3255 return rte_flow_error_set(error, EINVAL,
3256 RTE_FLOW_ERROR_TYPE_ACTION, action,
3257 "set_tag has no effect"
3258 " with terminal actions");
3263 * Indicates whether ASO aging is supported.
3266 * Pointer to shared device context structure.
3268 * Attributes of flow that includes AGE action.
3271 * True when ASO aging is supported, false otherwise.
3274 flow_hit_aso_supported(const struct mlx5_dev_ctx_shared *sh,
3275 const struct rte_flow_attr *attr)
3277 MLX5_ASSERT(sh && attr);
3278 return (sh->flow_hit_aso_en && (attr->transfer || attr->group));
3282 * Validate count action.
3285 * Pointer to rte_eth_dev structure.
3287 * Indicator if action is shared.
3288 * @param[in] action_flags
3289 * Holds the actions detected until now.
3291 * Attributes of flow that includes this action.
3293 * Pointer to error structure.
3296 * 0 on success, a negative errno value otherwise and rte_errno is set.
3299 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3300 uint64_t action_flags,
3301 const struct rte_flow_attr *attr,
3302 struct rte_flow_error *error)
3304 struct mlx5_priv *priv = dev->data->dev_private;
3306 if (!priv->sh->cdev->config.devx)
3308 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311 "duplicate count actions set");
3312 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3313 !flow_hit_aso_supported(priv->sh, attr))
3314 return rte_flow_error_set(error, EINVAL,
3315 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3316 "old age and indirect count combination is not supported");
3317 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3321 return rte_flow_error_set
3323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3325 "count action not supported");
3329 * Validate the L2 encap action.
3332 * Pointer to the rte_eth_dev structure.
3333 * @param[in] action_flags
3334 * Holds the actions detected until now.
3336 * Pointer to the action structure.
3338 * Pointer to flow attributes.
3340 * Pointer to error structure.
3343 * 0 on success, a negative errno value otherwise and rte_errno is set.
3346 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3347 uint64_t action_flags,
3348 const struct rte_flow_action *action,
3349 const struct rte_flow_attr *attr,
3350 struct rte_flow_error *error)
3352 const struct mlx5_priv *priv = dev->data->dev_private;
3354 if (!(action->conf))
3355 return rte_flow_error_set(error, EINVAL,
3356 RTE_FLOW_ERROR_TYPE_ACTION, action,
3357 "configuration cannot be null");
3358 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3359 return rte_flow_error_set(error, EINVAL,
3360 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3361 "can only have a single encap action "
3363 if (!attr->transfer && priv->representor)
3364 return rte_flow_error_set(error, ENOTSUP,
3365 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3366 "encap action for VF representor "
3367 "not supported on NIC table");
3372 * Validate a decap action.
3375 * Pointer to the rte_eth_dev structure.
3376 * @param[in] action_flags
3377 * Holds the actions detected until now.
3379 * Pointer to the action structure.
3380 * @param[in] item_flags
3381 * Holds the items detected.
3383 * Pointer to flow attributes
3385 * Pointer to error structure.
3388 * 0 on success, a negative errno value otherwise and rte_errno is set.
3391 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3392 uint64_t action_flags,
3393 const struct rte_flow_action *action,
3394 const uint64_t item_flags,
3395 const struct rte_flow_attr *attr,
3396 struct rte_flow_error *error)
3398 const struct mlx5_priv *priv = dev->data->dev_private;
3400 if (priv->sh->cdev->config.hca_attr.scatter_fcs_w_decap_disable &&
3401 !priv->sh->config.decap_en)
3402 return rte_flow_error_set(error, ENOTSUP,
3403 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3404 "decap is not enabled");
3405 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3406 return rte_flow_error_set(error, ENOTSUP,
3407 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3409 MLX5_FLOW_ACTION_DECAP ? "can only "
3410 "have a single decap action" : "decap "
3411 "after encap is not supported");
3412 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3413 return rte_flow_error_set(error, EINVAL,
3414 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3415 "can't have decap action after"
3418 return rte_flow_error_set(error, ENOTSUP,
3419 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3421 "decap action not supported for "
3423 if (!attr->transfer && priv->representor)
3424 return rte_flow_error_set(error, ENOTSUP,
3425 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3426 "decap action for VF representor "
3427 "not supported on NIC table");
3428 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3429 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3430 return rte_flow_error_set(error, ENOTSUP,
3431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3432 "VXLAN item should be present for VXLAN decap");
3436 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3439 * Validate the raw encap and decap actions.
3442 * Pointer to the rte_eth_dev structure.
3444 * Pointer to the decap action.
3446 * Pointer to the encap action.
3448 * Pointer to flow attributes
3449 * @param[in/out] action_flags
3450 * Holds the actions detected until now.
3451 * @param[out] actions_n
3452 * pointer to the number of actions counter.
3454 * Pointer to the action structure.
3455 * @param[in] item_flags
3456 * Holds the items detected.
3458 * Pointer to error structure.
3461 * 0 on success, a negative errno value otherwise and rte_errno is set.
3464 flow_dv_validate_action_raw_encap_decap
3465 (struct rte_eth_dev *dev,
3466 const struct rte_flow_action_raw_decap *decap,
3467 const struct rte_flow_action_raw_encap *encap,
3468 const struct rte_flow_attr *attr, uint64_t *action_flags,
3469 int *actions_n, const struct rte_flow_action *action,
3470 uint64_t item_flags, struct rte_flow_error *error)
3472 const struct mlx5_priv *priv = dev->data->dev_private;
3475 if (encap && (!encap->size || !encap->data))
3476 return rte_flow_error_set(error, EINVAL,
3477 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3478 "raw encap data cannot be empty");
3479 if (decap && encap) {
3480 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3481 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3484 else if (encap->size <=
3485 MLX5_ENCAPSULATION_DECISION_SIZE &&
3487 MLX5_ENCAPSULATION_DECISION_SIZE)
3490 else if (encap->size >
3491 MLX5_ENCAPSULATION_DECISION_SIZE &&
3493 MLX5_ENCAPSULATION_DECISION_SIZE)
3494 /* 2 L2 actions: encap and decap. */
3497 return rte_flow_error_set(error,
3499 RTE_FLOW_ERROR_TYPE_ACTION,
3500 NULL, "unsupported too small "
3501 "raw decap and too small raw "
3502 "encap combination");
3505 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3506 item_flags, attr, error);
3509 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3513 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3514 return rte_flow_error_set(error, ENOTSUP,
3515 RTE_FLOW_ERROR_TYPE_ACTION,
3517 "small raw encap size");
3518 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3519 return rte_flow_error_set(error, EINVAL,
3520 RTE_FLOW_ERROR_TYPE_ACTION,
3522 "more than one encap action");
3523 if (!attr->transfer && priv->representor)
3524 return rte_flow_error_set
3526 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3527 "encap action for VF representor "
3528 "not supported on NIC table");
3529 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3536 * Validate the ASO CT action.
3539 * Pointer to the rte_eth_dev structure.
3540 * @param[in] action_flags
3541 * Holds the actions detected until now.
3542 * @param[in] item_flags
3543 * The items found in this flow rule.
3545 * Pointer to flow attributes.
3547 * Pointer to error structure.
3550 * 0 on success, a negative errno value otherwise and rte_errno is set.
3553 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3554 uint64_t action_flags,
3555 uint64_t item_flags,
3556 const struct rte_flow_attr *attr,
3557 struct rte_flow_error *error)
3561 if (attr->group == 0 && !attr->transfer)
3562 return rte_flow_error_set(error, ENOTSUP,
3563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3565 "Only support non-root table");
3566 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3567 return rte_flow_error_set(error, ENOTSUP,
3568 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3569 "CT cannot follow a fate action");
3570 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3571 (action_flags & MLX5_FLOW_ACTION_AGE))
3572 return rte_flow_error_set(error, EINVAL,
3573 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3574 "Only one ASO action is supported");
3575 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3576 return rte_flow_error_set(error, EINVAL,
3577 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3578 "Encap cannot exist before CT");
3579 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3580 return rte_flow_error_set(error, EINVAL,
3581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3582 "Not a outer TCP packet");
3587 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3588 struct mlx5_list_entry *entry, void *cb_ctx)
3590 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3591 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3592 struct mlx5_flow_dv_encap_decap_resource *resource;
3594 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3596 if (resource->reformat_type == ctx_resource->reformat_type &&
3597 resource->ft_type == ctx_resource->ft_type &&
3598 resource->flags == ctx_resource->flags &&
3599 resource->size == ctx_resource->size &&
3600 !memcmp((const void *)resource->buf,
3601 (const void *)ctx_resource->buf,
3607 struct mlx5_list_entry *
3608 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3610 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3611 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3612 struct mlx5dv_dr_domain *domain;
3613 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3614 struct mlx5_flow_dv_encap_decap_resource *resource;
3618 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3619 domain = sh->fdb_domain;
3620 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3621 domain = sh->rx_domain;
3623 domain = sh->tx_domain;
3624 /* Register new encap/decap resource. */
3625 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3627 rte_flow_error_set(ctx->error, ENOMEM,
3628 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3629 "cannot allocate resource memory");
3632 *resource = *ctx_resource;
3633 resource->idx = idx;
3634 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3638 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3639 rte_flow_error_set(ctx->error, ENOMEM,
3640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3641 NULL, "cannot create action");
3645 return &resource->entry;
3648 struct mlx5_list_entry *
3649 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3652 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3653 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3654 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3657 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3659 if (!cache_resource) {
3660 rte_flow_error_set(ctx->error, ENOMEM,
3661 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3662 "cannot allocate resource memory");
3665 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3666 cache_resource->idx = idx;
3667 return &cache_resource->entry;
3671 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3673 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3674 struct mlx5_flow_dv_encap_decap_resource *res =
3675 container_of(entry, typeof(*res), entry);
3677 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3681 * Find existing encap/decap resource or create and register a new one.
3683 * @param[in, out] dev
3684 * Pointer to rte_eth_dev structure.
3685 * @param[in, out] resource
3686 * Pointer to encap/decap resource.
3687 * @parm[in, out] dev_flow
3688 * Pointer to the dev_flow.
3690 * pointer to error structure.
3693 * 0 on success otherwise -errno and errno is set.
3696 flow_dv_encap_decap_resource_register
3697 (struct rte_eth_dev *dev,
3698 struct mlx5_flow_dv_encap_decap_resource *resource,
3699 struct mlx5_flow *dev_flow,
3700 struct rte_flow_error *error)
3702 struct mlx5_priv *priv = dev->data->dev_private;
3703 struct mlx5_dev_ctx_shared *sh = priv->sh;
3704 struct mlx5_list_entry *entry;
3708 uint32_t refmt_type:8;
3710 * Header reformat actions can be shared between
3711 * non-root tables. One bit to indicate non-root
3715 uint32_t reserve:15;
3718 } encap_decap_key = {
3720 .ft_type = resource->ft_type,
3721 .refmt_type = resource->reformat_type,
3722 .is_root = !!dev_flow->dv.group,
3726 struct mlx5_flow_cb_ctx ctx = {
3730 struct mlx5_hlist *encaps_decaps;
3733 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3735 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3737 flow_dv_encap_decap_create_cb,
3738 flow_dv_encap_decap_match_cb,
3739 flow_dv_encap_decap_remove_cb,
3740 flow_dv_encap_decap_clone_cb,
3741 flow_dv_encap_decap_clone_free_cb,
3743 if (unlikely(!encaps_decaps))
3745 resource->flags = dev_flow->dv.group ? 0 : 1;
3746 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3747 sizeof(encap_decap_key.v32), 0);
3748 if (resource->reformat_type !=
3749 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3751 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3752 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3755 resource = container_of(entry, typeof(*resource), entry);
3756 dev_flow->dv.encap_decap = resource;
3757 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3762 * Find existing table jump resource or create and register a new one.
3764 * @param[in, out] dev
3765 * Pointer to rte_eth_dev structure.
3766 * @param[in, out] tbl
3767 * Pointer to flow table resource.
3768 * @parm[in, out] dev_flow
3769 * Pointer to the dev_flow.
3771 * pointer to error structure.
3774 * 0 on success otherwise -errno and errno is set.
3777 flow_dv_jump_tbl_resource_register
3778 (struct rte_eth_dev *dev __rte_unused,
3779 struct mlx5_flow_tbl_resource *tbl,
3780 struct mlx5_flow *dev_flow,
3781 struct rte_flow_error *error __rte_unused)
3783 struct mlx5_flow_tbl_data_entry *tbl_data =
3784 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3787 MLX5_ASSERT(tbl_data->jump.action);
3788 dev_flow->handle->rix_jump = tbl_data->idx;
3789 dev_flow->dv.jump = &tbl_data->jump;
3794 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3795 struct mlx5_list_entry *entry, void *cb_ctx)
3797 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3798 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3799 struct mlx5_flow_dv_port_id_action_resource *res =
3800 container_of(entry, typeof(*res), entry);
3802 return ref->port_id != res->port_id;
3805 struct mlx5_list_entry *
3806 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3808 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3809 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3810 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3811 struct mlx5_flow_dv_port_id_action_resource *resource;
3815 /* Register new port id action resource. */
3816 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3818 rte_flow_error_set(ctx->error, ENOMEM,
3819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3820 "cannot allocate port_id action memory");
3824 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3828 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3829 rte_flow_error_set(ctx->error, ENOMEM,
3830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3831 "cannot create action");
3834 resource->idx = idx;
3835 return &resource->entry;
3838 struct mlx5_list_entry *
3839 flow_dv_port_id_clone_cb(void *tool_ctx,
3840 struct mlx5_list_entry *entry __rte_unused,
3843 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3844 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3845 struct mlx5_flow_dv_port_id_action_resource *resource;
3848 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3850 rte_flow_error_set(ctx->error, ENOMEM,
3851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3852 "cannot allocate port_id action memory");
3855 memcpy(resource, entry, sizeof(*resource));
3856 resource->idx = idx;
3857 return &resource->entry;
3861 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3863 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3864 struct mlx5_flow_dv_port_id_action_resource *resource =
3865 container_of(entry, typeof(*resource), entry);
3867 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3871 * Find existing table port ID resource or create and register a new one.
3873 * @param[in, out] dev
3874 * Pointer to rte_eth_dev structure.
3875 * @param[in, out] ref
3876 * Pointer to port ID action resource reference.
3877 * @parm[in, out] dev_flow
3878 * Pointer to the dev_flow.
3880 * pointer to error structure.
3883 * 0 on success otherwise -errno and errno is set.
3886 flow_dv_port_id_action_resource_register
3887 (struct rte_eth_dev *dev,
3888 struct mlx5_flow_dv_port_id_action_resource *ref,
3889 struct mlx5_flow *dev_flow,
3890 struct rte_flow_error *error)
3892 struct mlx5_priv *priv = dev->data->dev_private;
3893 struct mlx5_list_entry *entry;
3894 struct mlx5_flow_dv_port_id_action_resource *resource;
3895 struct mlx5_flow_cb_ctx ctx = {
3900 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3903 resource = container_of(entry, typeof(*resource), entry);
3904 dev_flow->dv.port_id_action = resource;
3905 dev_flow->handle->rix_port_id_action = resource->idx;
3910 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3911 struct mlx5_list_entry *entry, void *cb_ctx)
3913 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3914 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3915 struct mlx5_flow_dv_push_vlan_action_resource *res =
3916 container_of(entry, typeof(*res), entry);
3918 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3921 struct mlx5_list_entry *
3922 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3924 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3925 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3926 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3927 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3928 struct mlx5dv_dr_domain *domain;
3932 /* Register new port id action resource. */
3933 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3935 rte_flow_error_set(ctx->error, ENOMEM,
3936 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3937 "cannot allocate push_vlan action memory");
3941 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3942 domain = sh->fdb_domain;
3943 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3944 domain = sh->rx_domain;
3946 domain = sh->tx_domain;
3947 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3950 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3951 rte_flow_error_set(ctx->error, ENOMEM,
3952 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3953 "cannot create push vlan action");
3956 resource->idx = idx;
3957 return &resource->entry;
3960 struct mlx5_list_entry *
3961 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3962 struct mlx5_list_entry *entry __rte_unused,
3965 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3966 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3967 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3970 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3972 rte_flow_error_set(ctx->error, ENOMEM,
3973 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3974 "cannot allocate push_vlan action memory");
3977 memcpy(resource, entry, sizeof(*resource));
3978 resource->idx = idx;
3979 return &resource->entry;
3983 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3985 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3986 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3987 container_of(entry, typeof(*resource), entry);
3989 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3993 * Find existing push vlan resource or create and register a new one.
3995 * @param [in, out] dev
3996 * Pointer to rte_eth_dev structure.
3997 * @param[in, out] ref
3998 * Pointer to port ID action resource reference.
3999 * @parm[in, out] dev_flow
4000 * Pointer to the dev_flow.
4002 * pointer to error structure.
4005 * 0 on success otherwise -errno and errno is set.
4008 flow_dv_push_vlan_action_resource_register
4009 (struct rte_eth_dev *dev,
4010 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4011 struct mlx5_flow *dev_flow,
4012 struct rte_flow_error *error)
4014 struct mlx5_priv *priv = dev->data->dev_private;
4015 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4016 struct mlx5_list_entry *entry;
4017 struct mlx5_flow_cb_ctx ctx = {
4022 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4025 resource = container_of(entry, typeof(*resource), entry);
4027 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4028 dev_flow->dv.push_vlan_res = resource;
4033 * Get the size of specific rte_flow_item_type hdr size
4035 * @param[in] item_type
4036 * Tested rte_flow_item_type.
4039 * sizeof struct item_type, 0 if void or irrelevant.
4042 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4046 switch (item_type) {
4047 case RTE_FLOW_ITEM_TYPE_ETH:
4048 retval = sizeof(struct rte_ether_hdr);
4050 case RTE_FLOW_ITEM_TYPE_VLAN:
4051 retval = sizeof(struct rte_vlan_hdr);
4053 case RTE_FLOW_ITEM_TYPE_IPV4:
4054 retval = sizeof(struct rte_ipv4_hdr);
4056 case RTE_FLOW_ITEM_TYPE_IPV6:
4057 retval = sizeof(struct rte_ipv6_hdr);
4059 case RTE_FLOW_ITEM_TYPE_UDP:
4060 retval = sizeof(struct rte_udp_hdr);
4062 case RTE_FLOW_ITEM_TYPE_TCP:
4063 retval = sizeof(struct rte_tcp_hdr);
4065 case RTE_FLOW_ITEM_TYPE_VXLAN:
4066 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4067 retval = sizeof(struct rte_vxlan_hdr);
4069 case RTE_FLOW_ITEM_TYPE_GRE:
4070 case RTE_FLOW_ITEM_TYPE_NVGRE:
4071 retval = sizeof(struct rte_gre_hdr);
4073 case RTE_FLOW_ITEM_TYPE_MPLS:
4074 retval = sizeof(struct rte_mpls_hdr);
4076 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4084 #define MLX5_ENCAP_IPV4_VERSION 0x40
4085 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4086 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4087 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4088 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4089 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4090 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4093 * Convert the encap action data from list of rte_flow_item to raw buffer
4096 * Pointer to rte_flow_item objects list.
4098 * Pointer to the output buffer.
4100 * Pointer to the output buffer size.
4102 * Pointer to the error structure.
4105 * 0 on success, a negative errno value otherwise and rte_errno is set.
4108 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4109 size_t *size, struct rte_flow_error *error)
4111 struct rte_ether_hdr *eth = NULL;
4112 struct rte_vlan_hdr *vlan = NULL;
4113 struct rte_ipv4_hdr *ipv4 = NULL;
4114 struct rte_ipv6_hdr *ipv6 = NULL;
4115 struct rte_udp_hdr *udp = NULL;
4116 struct rte_vxlan_hdr *vxlan = NULL;
4117 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4118 struct rte_gre_hdr *gre = NULL;
4120 size_t temp_size = 0;
4123 return rte_flow_error_set(error, EINVAL,
4124 RTE_FLOW_ERROR_TYPE_ACTION,
4125 NULL, "invalid empty data");
4126 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4127 len = flow_dv_get_item_hdr_len(items->type);
4128 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4129 return rte_flow_error_set(error, EINVAL,
4130 RTE_FLOW_ERROR_TYPE_ACTION,
4131 (void *)items->type,
4132 "items total size is too big"
4133 " for encap action");
4134 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4135 switch (items->type) {
4136 case RTE_FLOW_ITEM_TYPE_ETH:
4137 eth = (struct rte_ether_hdr *)&buf[temp_size];
4139 case RTE_FLOW_ITEM_TYPE_VLAN:
4140 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4142 return rte_flow_error_set(error, EINVAL,
4143 RTE_FLOW_ERROR_TYPE_ACTION,
4144 (void *)items->type,
4145 "eth header not found");
4146 if (!eth->ether_type)
4147 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4149 case RTE_FLOW_ITEM_TYPE_IPV4:
4150 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4152 return rte_flow_error_set(error, EINVAL,
4153 RTE_FLOW_ERROR_TYPE_ACTION,
4154 (void *)items->type,
4155 "neither eth nor vlan"
4157 if (vlan && !vlan->eth_proto)
4158 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4159 else if (eth && !eth->ether_type)
4160 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4161 if (!ipv4->version_ihl)
4162 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4163 MLX5_ENCAP_IPV4_IHL_MIN;
4164 if (!ipv4->time_to_live)
4165 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4167 case RTE_FLOW_ITEM_TYPE_IPV6:
4168 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4170 return rte_flow_error_set(error, EINVAL,
4171 RTE_FLOW_ERROR_TYPE_ACTION,
4172 (void *)items->type,
4173 "neither eth nor vlan"
4175 if (vlan && !vlan->eth_proto)
4176 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4177 else if (eth && !eth->ether_type)
4178 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4179 if (!ipv6->vtc_flow)
4181 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4182 if (!ipv6->hop_limits)
4183 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4185 case RTE_FLOW_ITEM_TYPE_UDP:
4186 udp = (struct rte_udp_hdr *)&buf[temp_size];
4188 return rte_flow_error_set(error, EINVAL,
4189 RTE_FLOW_ERROR_TYPE_ACTION,
4190 (void *)items->type,
4191 "ip header not found");
4192 if (ipv4 && !ipv4->next_proto_id)
4193 ipv4->next_proto_id = IPPROTO_UDP;
4194 else if (ipv6 && !ipv6->proto)
4195 ipv6->proto = IPPROTO_UDP;
4197 case RTE_FLOW_ITEM_TYPE_VXLAN:
4198 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4200 return rte_flow_error_set(error, EINVAL,
4201 RTE_FLOW_ERROR_TYPE_ACTION,
4202 (void *)items->type,
4203 "udp header not found");
4205 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4206 if (!vxlan->vx_flags)
4208 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4210 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4211 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4213 return rte_flow_error_set(error, EINVAL,
4214 RTE_FLOW_ERROR_TYPE_ACTION,
4215 (void *)items->type,
4216 "udp header not found");
4217 if (!vxlan_gpe->proto)
4218 return rte_flow_error_set(error, EINVAL,
4219 RTE_FLOW_ERROR_TYPE_ACTION,
4220 (void *)items->type,
4221 "next protocol not found");
4224 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4225 if (!vxlan_gpe->vx_flags)
4226 vxlan_gpe->vx_flags =
4227 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4229 case RTE_FLOW_ITEM_TYPE_GRE:
4230 case RTE_FLOW_ITEM_TYPE_NVGRE:
4231 gre = (struct rte_gre_hdr *)&buf[temp_size];
4233 return rte_flow_error_set(error, EINVAL,
4234 RTE_FLOW_ERROR_TYPE_ACTION,
4235 (void *)items->type,
4236 "next protocol not found");
4238 return rte_flow_error_set(error, EINVAL,
4239 RTE_FLOW_ERROR_TYPE_ACTION,
4240 (void *)items->type,
4241 "ip header not found");
4242 if (ipv4 && !ipv4->next_proto_id)
4243 ipv4->next_proto_id = IPPROTO_GRE;
4244 else if (ipv6 && !ipv6->proto)
4245 ipv6->proto = IPPROTO_GRE;
4247 case RTE_FLOW_ITEM_TYPE_VOID:
4250 return rte_flow_error_set(error, EINVAL,
4251 RTE_FLOW_ERROR_TYPE_ACTION,
4252 (void *)items->type,
4253 "unsupported item type");
4263 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4265 struct rte_ether_hdr *eth = NULL;
4266 struct rte_vlan_hdr *vlan = NULL;
4267 struct rte_ipv6_hdr *ipv6 = NULL;
4268 struct rte_udp_hdr *udp = NULL;
4272 eth = (struct rte_ether_hdr *)data;
4273 next_hdr = (char *)(eth + 1);
4274 proto = RTE_BE16(eth->ether_type);
4277 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4278 vlan = (struct rte_vlan_hdr *)next_hdr;
4279 proto = RTE_BE16(vlan->eth_proto);
4280 next_hdr += sizeof(struct rte_vlan_hdr);
4283 /* HW calculates IPv4 csum. no need to proceed */
4284 if (proto == RTE_ETHER_TYPE_IPV4)
4287 /* non IPv4/IPv6 header. not supported */
4288 if (proto != RTE_ETHER_TYPE_IPV6) {
4289 return rte_flow_error_set(error, ENOTSUP,
4290 RTE_FLOW_ERROR_TYPE_ACTION,
4291 NULL, "Cannot offload non IPv4/IPv6");
4294 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4296 /* ignore non UDP */
4297 if (ipv6->proto != IPPROTO_UDP)
4300 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4301 udp->dgram_cksum = 0;
4307 * Convert L2 encap action to DV specification.
4310 * Pointer to rte_eth_dev structure.
4312 * Pointer to action structure.
4313 * @param[in, out] dev_flow
4314 * Pointer to the mlx5_flow.
4315 * @param[in] transfer
4316 * Mark if the flow is E-Switch flow.
4318 * Pointer to the error structure.
4321 * 0 on success, a negative errno value otherwise and rte_errno is set.
4324 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4325 const struct rte_flow_action *action,
4326 struct mlx5_flow *dev_flow,
4328 struct rte_flow_error *error)
4330 const struct rte_flow_item *encap_data;
4331 const struct rte_flow_action_raw_encap *raw_encap_data;
4332 struct mlx5_flow_dv_encap_decap_resource res = {
4334 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4335 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4336 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4339 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4341 (const struct rte_flow_action_raw_encap *)action->conf;
4342 res.size = raw_encap_data->size;
4343 memcpy(res.buf, raw_encap_data->data, res.size);
4345 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4347 ((const struct rte_flow_action_vxlan_encap *)
4348 action->conf)->definition;
4351 ((const struct rte_flow_action_nvgre_encap *)
4352 action->conf)->definition;
4353 if (flow_dv_convert_encap_data(encap_data, res.buf,
4357 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4359 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4360 return rte_flow_error_set(error, EINVAL,
4361 RTE_FLOW_ERROR_TYPE_ACTION,
4362 NULL, "can't create L2 encap action");
4367 * Convert L2 decap action to DV specification.
4370 * Pointer to rte_eth_dev structure.
4371 * @param[in, out] dev_flow
4372 * Pointer to the mlx5_flow.
4373 * @param[in] transfer
4374 * Mark if the flow is E-Switch flow.
4376 * Pointer to the error structure.
4379 * 0 on success, a negative errno value otherwise and rte_errno is set.
4382 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4383 struct mlx5_flow *dev_flow,
4385 struct rte_flow_error *error)
4387 struct mlx5_flow_dv_encap_decap_resource res = {
4390 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4391 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4392 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4395 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4396 return rte_flow_error_set(error, EINVAL,
4397 RTE_FLOW_ERROR_TYPE_ACTION,
4398 NULL, "can't create L2 decap action");
4403 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4406 * Pointer to rte_eth_dev structure.
4408 * Pointer to action structure.
4409 * @param[in, out] dev_flow
4410 * Pointer to the mlx5_flow.
4412 * Pointer to the flow attributes.
4414 * Pointer to the error structure.
4417 * 0 on success, a negative errno value otherwise and rte_errno is set.
4420 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4421 const struct rte_flow_action *action,
4422 struct mlx5_flow *dev_flow,
4423 const struct rte_flow_attr *attr,
4424 struct rte_flow_error *error)
4426 const struct rte_flow_action_raw_encap *encap_data;
4427 struct mlx5_flow_dv_encap_decap_resource res;
4429 memset(&res, 0, sizeof(res));
4430 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4431 res.size = encap_data->size;
4432 memcpy(res.buf, encap_data->data, res.size);
4433 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4434 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4437 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4439 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4440 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4441 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4442 return rte_flow_error_set(error, EINVAL,
4443 RTE_FLOW_ERROR_TYPE_ACTION,
4444 NULL, "can't create encap action");
4449 * Create action push VLAN.
4452 * Pointer to rte_eth_dev structure.
4454 * Pointer to the flow attributes.
4456 * Pointer to the vlan to push to the Ethernet header.
4457 * @param[in, out] dev_flow
4458 * Pointer to the mlx5_flow.
4460 * Pointer to the error structure.
4463 * 0 on success, a negative errno value otherwise and rte_errno is set.
4466 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4467 const struct rte_flow_attr *attr,
4468 const struct rte_vlan_hdr *vlan,
4469 struct mlx5_flow *dev_flow,
4470 struct rte_flow_error *error)
4472 struct mlx5_flow_dv_push_vlan_action_resource res;
4474 memset(&res, 0, sizeof(res));
4476 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4479 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4481 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4482 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4483 return flow_dv_push_vlan_action_resource_register
4484 (dev, &res, dev_flow, error);
4488 * Validate the modify-header actions.
4490 * @param[in] action_flags
4491 * Holds the actions detected until now.
4493 * Pointer to the modify action.
4495 * Pointer to error structure.
4498 * 0 on success, a negative errno value otherwise and rte_errno is set.
4501 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4502 const struct rte_flow_action *action,
4503 struct rte_flow_error *error)
4505 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4506 return rte_flow_error_set(error, EINVAL,
4507 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4508 NULL, "action configuration not set");
4509 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4510 return rte_flow_error_set(error, EINVAL,
4511 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4512 "can't have encap action before"
4518 * Validate the modify-header MAC address actions.
4520 * @param[in] action_flags
4521 * Holds the actions detected until now.
4523 * Pointer to the modify action.
4524 * @param[in] item_flags
4525 * Holds the items detected.
4527 * Pointer to error structure.
4530 * 0 on success, a negative errno value otherwise and rte_errno is set.
4533 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4534 const struct rte_flow_action *action,
4535 const uint64_t item_flags,
4536 struct rte_flow_error *error)
4540 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4542 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4543 return rte_flow_error_set(error, EINVAL,
4544 RTE_FLOW_ERROR_TYPE_ACTION,
4546 "no L2 item in pattern");
4552 * Validate the modify-header IPv4 address actions.
4554 * @param[in] action_flags
4555 * Holds the actions detected until now.
4557 * Pointer to the modify action.
4558 * @param[in] item_flags
4559 * Holds the items detected.
4561 * Pointer to error structure.
4564 * 0 on success, a negative errno value otherwise and rte_errno is set.
4567 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4568 const struct rte_flow_action *action,
4569 const uint64_t item_flags,
4570 struct rte_flow_error *error)
4575 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4577 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4578 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4579 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4580 if (!(item_flags & layer))
4581 return rte_flow_error_set(error, EINVAL,
4582 RTE_FLOW_ERROR_TYPE_ACTION,
4584 "no ipv4 item in pattern");
4590 * Validate the modify-header IPv6 address actions.
4592 * @param[in] action_flags
4593 * Holds the actions detected until now.
4595 * Pointer to the modify action.
4596 * @param[in] item_flags
4597 * Holds the items detected.
4599 * Pointer to error structure.
4602 * 0 on success, a negative errno value otherwise and rte_errno is set.
4605 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4606 const struct rte_flow_action *action,
4607 const uint64_t item_flags,
4608 struct rte_flow_error *error)
4613 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4615 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4616 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4617 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4618 if (!(item_flags & layer))
4619 return rte_flow_error_set(error, EINVAL,
4620 RTE_FLOW_ERROR_TYPE_ACTION,
4622 "no ipv6 item in pattern");
4628 * Validate the modify-header TP actions.
4630 * @param[in] action_flags
4631 * Holds the actions detected until now.
4633 * Pointer to the modify action.
4634 * @param[in] item_flags
4635 * Holds the items detected.
4637 * Pointer to error structure.
4640 * 0 on success, a negative errno value otherwise and rte_errno is set.
4643 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4644 const struct rte_flow_action *action,
4645 const uint64_t item_flags,
4646 struct rte_flow_error *error)
4651 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4653 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4654 MLX5_FLOW_LAYER_INNER_L4 :
4655 MLX5_FLOW_LAYER_OUTER_L4;
4656 if (!(item_flags & layer))
4657 return rte_flow_error_set(error, EINVAL,
4658 RTE_FLOW_ERROR_TYPE_ACTION,
4659 NULL, "no transport layer "
4666 * Validate the modify-header actions of increment/decrement
4667 * TCP Sequence-number.
4669 * @param[in] action_flags
4670 * Holds the actions detected until now.
4672 * Pointer to the modify action.
4673 * @param[in] item_flags
4674 * Holds the items detected.
4676 * Pointer to error structure.
4679 * 0 on success, a negative errno value otherwise and rte_errno is set.
4682 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4683 const struct rte_flow_action *action,
4684 const uint64_t item_flags,
4685 struct rte_flow_error *error)
4690 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4692 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4693 MLX5_FLOW_LAYER_INNER_L4_TCP :
4694 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4695 if (!(item_flags & layer))
4696 return rte_flow_error_set(error, EINVAL,
4697 RTE_FLOW_ERROR_TYPE_ACTION,
4698 NULL, "no TCP item in"
4700 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4701 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4702 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4703 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4704 return rte_flow_error_set(error, EINVAL,
4705 RTE_FLOW_ERROR_TYPE_ACTION,
4707 "cannot decrease and increase"
4708 " TCP sequence number"
4709 " at the same time");
4715 * Validate the modify-header actions of increment/decrement
4716 * TCP Acknowledgment number.
4718 * @param[in] action_flags
4719 * Holds the actions detected until now.
4721 * Pointer to the modify action.
4722 * @param[in] item_flags
4723 * Holds the items detected.
4725 * Pointer to error structure.
4728 * 0 on success, a negative errno value otherwise and rte_errno is set.
4731 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4732 const struct rte_flow_action *action,
4733 const uint64_t item_flags,
4734 struct rte_flow_error *error)
4739 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4741 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4742 MLX5_FLOW_LAYER_INNER_L4_TCP :
4743 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4744 if (!(item_flags & layer))
4745 return rte_flow_error_set(error, EINVAL,
4746 RTE_FLOW_ERROR_TYPE_ACTION,
4747 NULL, "no TCP item in"
4749 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4750 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4751 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4752 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4753 return rte_flow_error_set(error, EINVAL,
4754 RTE_FLOW_ERROR_TYPE_ACTION,
4756 "cannot decrease and increase"
4757 " TCP acknowledgment number"
4758 " at the same time");
4764 * Validate the modify-header TTL actions.
4766 * @param[in] action_flags
4767 * Holds the actions detected until now.
4769 * Pointer to the modify action.
4770 * @param[in] item_flags
4771 * Holds the items detected.
4773 * Pointer to error structure.
4776 * 0 on success, a negative errno value otherwise and rte_errno is set.
4779 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4780 const struct rte_flow_action *action,
4781 const uint64_t item_flags,
4782 struct rte_flow_error *error)
4787 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4789 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4790 MLX5_FLOW_LAYER_INNER_L3 :
4791 MLX5_FLOW_LAYER_OUTER_L3;
4792 if (!(item_flags & layer))
4793 return rte_flow_error_set(error, EINVAL,
4794 RTE_FLOW_ERROR_TYPE_ACTION,
4796 "no IP protocol in pattern");
4802 * Validate the generic modify field actions.
4804 * Pointer to the rte_eth_dev structure.
4805 * @param[in] action_flags
4806 * Holds the actions detected until now.
4808 * Pointer to the modify action.
4810 * Pointer to the flow attributes.
4812 * Pointer to error structure.
4815 * Number of header fields to modify (0 or more) on success,
4816 * a negative errno value otherwise and rte_errno is set.
4819 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4820 const uint64_t action_flags,
4821 const struct rte_flow_action *action,
4822 const struct rte_flow_attr *attr,
4823 struct rte_flow_error *error)
4826 struct mlx5_priv *priv = dev->data->dev_private;
4827 struct mlx5_sh_config *config = &priv->sh->config;
4828 const struct rte_flow_action_modify_field *action_modify_field =
4830 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4831 action_modify_field->dst.field,
4833 uint32_t src_width = mlx5_flow_item_field_width(dev,
4834 action_modify_field->src.field,
4835 dst_width, attr, error);
4837 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4841 if (action_modify_field->width == 0)
4842 return rte_flow_error_set(error, EINVAL,
4843 RTE_FLOW_ERROR_TYPE_ACTION, action,
4844 "no bits are requested to be modified");
4845 else if (action_modify_field->width > dst_width ||
4846 action_modify_field->width > src_width)
4847 return rte_flow_error_set(error, EINVAL,
4848 RTE_FLOW_ERROR_TYPE_ACTION, action,
4849 "cannot modify more bits than"
4850 " the width of a field");
4851 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4852 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4853 if ((action_modify_field->dst.offset +
4854 action_modify_field->width > dst_width) ||
4855 (action_modify_field->dst.offset % 32))
4856 return rte_flow_error_set(error, EINVAL,
4857 RTE_FLOW_ERROR_TYPE_ACTION, action,
4858 "destination offset is too big"
4859 " or not aligned to 4 bytes");
4860 if (action_modify_field->dst.level &&
4861 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4862 return rte_flow_error_set(error, ENOTSUP,
4863 RTE_FLOW_ERROR_TYPE_ACTION, action,
4864 "inner header fields modification"
4865 " is not supported");
4867 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4868 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4869 if (!attr->transfer && !attr->group)
4870 return rte_flow_error_set(error, ENOTSUP,
4871 RTE_FLOW_ERROR_TYPE_ACTION, action,
4872 "modify field action is not"
4873 " supported for group 0");
4874 if ((action_modify_field->src.offset +
4875 action_modify_field->width > src_width) ||
4876 (action_modify_field->src.offset % 32))
4877 return rte_flow_error_set(error, EINVAL,
4878 RTE_FLOW_ERROR_TYPE_ACTION, action,
4879 "source offset is too big"
4880 " or not aligned to 4 bytes");
4881 if (action_modify_field->src.level &&
4882 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4883 return rte_flow_error_set(error, ENOTSUP,
4884 RTE_FLOW_ERROR_TYPE_ACTION, action,
4885 "inner header fields modification"
4886 " is not supported");
4888 if ((action_modify_field->dst.field ==
4889 action_modify_field->src.field) &&
4890 (action_modify_field->dst.level ==
4891 action_modify_field->src.level))
4892 return rte_flow_error_set(error, EINVAL,
4893 RTE_FLOW_ERROR_TYPE_ACTION, action,
4894 "source and destination fields"
4895 " cannot be the same");
4896 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4897 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4899 return rte_flow_error_set(error, EINVAL,
4900 RTE_FLOW_ERROR_TYPE_ACTION, action,
4901 "mark, immediate value or a pointer to it"
4902 " cannot be used as a destination");
4903 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4904 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4905 return rte_flow_error_set(error, ENOTSUP,
4906 RTE_FLOW_ERROR_TYPE_ACTION, action,
4907 "modifications of an arbitrary"
4908 " place in a packet is not supported");
4909 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4910 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4911 return rte_flow_error_set(error, ENOTSUP,
4912 RTE_FLOW_ERROR_TYPE_ACTION, action,
4913 "modifications of the 802.1Q Tag"
4914 " Identifier is not supported");
4915 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4916 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4917 return rte_flow_error_set(error, ENOTSUP,
4918 RTE_FLOW_ERROR_TYPE_ACTION, action,
4919 "modifications of the VXLAN Network"
4920 " Identifier is not supported");
4921 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4922 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4923 return rte_flow_error_set(error, ENOTSUP,
4924 RTE_FLOW_ERROR_TYPE_ACTION, action,
4925 "modifications of the GENEVE Network"
4926 " Identifier is not supported");
4927 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4928 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4929 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4930 !mlx5_flow_ext_mreg_supported(dev))
4931 return rte_flow_error_set(error, ENOTSUP,
4932 RTE_FLOW_ERROR_TYPE_ACTION, action,
4933 "cannot modify mark in legacy mode"
4934 " or without extensive registers");
4935 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4936 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4937 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4938 !mlx5_flow_ext_mreg_supported(dev))
4939 return rte_flow_error_set(error, ENOTSUP,
4940 RTE_FLOW_ERROR_TYPE_ACTION, action,
4941 "cannot modify meta without"
4942 " extensive registers support");
4943 ret = flow_dv_get_metadata_reg(dev, attr, error);
4944 if (ret < 0 || ret == REG_NON)
4945 return rte_flow_error_set(error, ENOTSUP,
4946 RTE_FLOW_ERROR_TYPE_ACTION, action,
4947 "cannot modify meta without"
4948 " extensive registers available");
4950 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4951 return rte_flow_error_set(error, ENOTSUP,
4952 RTE_FLOW_ERROR_TYPE_ACTION, action,
4953 "add and sub operations"
4954 " are not supported");
4955 return (action_modify_field->width / 32) +
4956 !!(action_modify_field->width % 32);
4960 * Validate jump action.
4963 * Pointer to the jump action.
4964 * @param[in] action_flags
4965 * Holds the actions detected until now.
4966 * @param[in] attributes
4967 * Pointer to flow attributes
4968 * @param[in] external
4969 * Action belongs to flow rule created by request external to PMD.
4971 * Pointer to error structure.
4974 * 0 on success, a negative errno value otherwise and rte_errno is set.
4977 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4978 const struct mlx5_flow_tunnel *tunnel,
4979 const struct rte_flow_action *action,
4980 uint64_t action_flags,
4981 const struct rte_flow_attr *attributes,
4982 bool external, struct rte_flow_error *error)
4984 uint32_t target_group, table = 0;
4986 struct flow_grp_info grp_info = {
4987 .external = !!external,
4988 .transfer = !!attributes->transfer,
4992 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4993 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4994 return rte_flow_error_set(error, EINVAL,
4995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4996 "can't have 2 fate actions in"
4999 return rte_flow_error_set(error, EINVAL,
5000 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5001 NULL, "action configuration not set");
5003 ((const struct rte_flow_action_jump *)action->conf)->group;
5004 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5008 if (attributes->group == target_group &&
5009 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5010 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5011 return rte_flow_error_set(error, EINVAL,
5012 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5013 "target group must be other than"
5014 " the current flow group");
5016 return rte_flow_error_set(error, EINVAL,
5017 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5018 NULL, "root table shouldn't be destination");
5023 * Validate action PORT_ID / REPRESENTED_PORT.
5026 * Pointer to rte_eth_dev structure.
5027 * @param[in] action_flags
5028 * Bit-fields that holds the actions detected until now.
5030 * PORT_ID / REPRESENTED_PORT action structure.
5032 * Attributes of flow that includes this action.
5034 * Pointer to error structure.
5037 * 0 on success, a negative errno value otherwise and rte_errno is set.
5040 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5041 uint64_t action_flags,
5042 const struct rte_flow_action *action,
5043 const struct rte_flow_attr *attr,
5044 struct rte_flow_error *error)
5046 const struct rte_flow_action_port_id *port_id;
5047 const struct rte_flow_action_ethdev *ethdev;
5048 struct mlx5_priv *act_priv;
5049 struct mlx5_priv *dev_priv;
5052 if (!attr->transfer)
5053 return rte_flow_error_set(error, ENOTSUP,
5054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5056 "port action is valid in transfer"
5058 if (!action || !action->conf)
5059 return rte_flow_error_set(error, ENOTSUP,
5060 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5062 "port action parameters must be"
5064 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5065 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5066 return rte_flow_error_set(error, EINVAL,
5067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5068 "can have only one fate actions in"
5070 dev_priv = mlx5_dev_to_eswitch_info(dev);
5072 return rte_flow_error_set(error, rte_errno,
5073 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5075 "failed to obtain E-Switch info");
5076 switch (action->type) {
5077 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5078 port_id = action->conf;
5079 port = port_id->original ? dev->data->port_id : port_id->id;
5081 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5082 ethdev = action->conf;
5083 port = ethdev->port_id;
5087 return rte_flow_error_set
5089 RTE_FLOW_ERROR_TYPE_ACTION, action,
5090 "unknown E-Switch action");
5092 act_priv = mlx5_port_to_eswitch_info(port, false);
5094 return rte_flow_error_set
5096 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5097 "failed to obtain E-Switch port id for port");
5098 if (act_priv->domain_id != dev_priv->domain_id)
5099 return rte_flow_error_set
5101 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5102 "port does not belong to"
5103 " E-Switch being configured");
5108 * Get the maximum number of modify header actions.
5111 * Pointer to rte_eth_dev structure.
5113 * Whether action is on root table.
5116 * Max number of modify header actions device can support.
5118 static inline unsigned int
5119 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5123 * There's no way to directly query the max capacity from FW.
5124 * The maximal value on root table should be assumed to be supported.
5127 return MLX5_MAX_MODIFY_NUM;
5129 return MLX5_ROOT_TBL_MODIFY_NUM;
5133 * Validate the meter action.
5136 * Pointer to rte_eth_dev structure.
5137 * @param[in] action_flags
5138 * Bit-fields that holds the actions detected until now.
5139 * @param[in] item_flags
5140 * Holds the items detected.
5142 * Pointer to the meter action.
5144 * Attributes of flow that includes this action.
5145 * @param[in] port_id_item
5146 * Pointer to item indicating port id.
5148 * Pointer to error structure.
5151 * 0 on success, a negative errno value otherwise and rte_errno is set.
5154 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5155 uint64_t action_flags, uint64_t item_flags,
5156 const struct rte_flow_action *action,
5157 const struct rte_flow_attr *attr,
5158 const struct rte_flow_item *port_id_item,
5160 struct rte_flow_error *error)
5162 struct mlx5_priv *priv = dev->data->dev_private;
5163 const struct rte_flow_action_meter *am = action->conf;
5164 struct mlx5_flow_meter_info *fm;
5165 struct mlx5_flow_meter_policy *mtr_policy;
5166 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5169 return rte_flow_error_set(error, EINVAL,
5170 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5171 "meter action conf is NULL");
5173 if (action_flags & MLX5_FLOW_ACTION_METER)
5174 return rte_flow_error_set(error, ENOTSUP,
5175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5176 "meter chaining not support");
5177 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5178 return rte_flow_error_set(error, ENOTSUP,
5179 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5180 "meter with jump not support");
5182 return rte_flow_error_set(error, ENOTSUP,
5183 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5185 "meter action not supported");
5186 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5188 return rte_flow_error_set(error, EINVAL,
5189 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5191 /* aso meter can always be shared by different domains */
5192 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5193 !(fm->transfer == attr->transfer ||
5194 (!fm->ingress && !attr->ingress && attr->egress) ||
5195 (!fm->egress && !attr->egress && attr->ingress)))
5196 return rte_flow_error_set(error, EINVAL,
5197 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5198 "Flow attributes domain are either invalid "
5199 "or have a domain conflict with current "
5200 "meter attributes");
5201 if (fm->def_policy) {
5202 if (!((attr->transfer &&
5203 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5205 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5207 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5208 return rte_flow_error_set(error, EINVAL,
5209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5210 "Flow attributes domain "
5211 "have a conflict with current "
5212 "meter domain attributes");
5215 mtr_policy = mlx5_flow_meter_policy_find(dev,
5216 fm->policy_id, NULL);
5218 return rte_flow_error_set(error, EINVAL,
5219 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5220 "Invalid policy id for meter ");
5221 if (!((attr->transfer && mtr_policy->transfer) ||
5222 (attr->egress && mtr_policy->egress) ||
5223 (attr->ingress && mtr_policy->ingress)))
5224 return rte_flow_error_set(error, EINVAL,
5225 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5226 "Flow attributes domain "
5227 "have a conflict with current "
5228 "meter domain attributes");
5229 if (attr->transfer && mtr_policy->dev) {
5231 * When policy has fate action of port_id,
5232 * the flow should have the same src port as policy.
5234 struct mlx5_priv *policy_port_priv =
5235 mtr_policy->dev->data->dev_private;
5236 int32_t flow_src_port = priv->representor_id;
5239 const struct rte_flow_item_port_id *spec =
5241 struct mlx5_priv *port_priv =
5242 mlx5_port_to_eswitch_info(spec->id,
5245 return rte_flow_error_set(error,
5247 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5249 "Failed to get port info.");
5250 flow_src_port = port_priv->representor_id;
5252 if (flow_src_port != policy_port_priv->representor_id)
5253 return rte_flow_error_set(error,
5255 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5257 "Flow and meter policy "
5258 "have different src port.");
5259 } else if (mtr_policy->is_rss) {
5260 struct mlx5_flow_meter_policy *fp;
5261 struct mlx5_meter_policy_action_container *acg;
5262 struct mlx5_meter_policy_action_container *acy;
5263 const struct rte_flow_action *rss_act;
5266 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5269 return rte_flow_error_set(error, EINVAL,
5270 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5271 "Unable to get the final "
5272 "policy in the hierarchy");
5273 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5274 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5275 MLX5_ASSERT(acg->fate_action ==
5276 MLX5_FLOW_FATE_SHARED_RSS ||
5278 MLX5_FLOW_FATE_SHARED_RSS);
5279 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5283 ret = mlx5_flow_validate_action_rss(rss_act,
5284 action_flags, dev, attr,
5289 *def_policy = false;
5295 * Validate the age action.
5297 * @param[in] action_flags
5298 * Holds the actions detected until now.
5300 * Pointer to the age action.
5302 * Pointer to the Ethernet device structure.
5304 * Pointer to error structure.
5307 * 0 on success, a negative errno value otherwise and rte_errno is set.
5310 flow_dv_validate_action_age(uint64_t action_flags,
5311 const struct rte_flow_action *action,
5312 struct rte_eth_dev *dev,
5313 struct rte_flow_error *error)
5315 struct mlx5_priv *priv = dev->data->dev_private;
5316 const struct rte_flow_action_age *age = action->conf;
5318 if (!priv->sh->cdev->config.devx ||
5319 (priv->sh->cmng.counter_fallback && !priv->sh->aso_age_mng))
5320 return rte_flow_error_set(error, ENOTSUP,
5321 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5323 "age action not supported");
5324 if (!(action->conf))
5325 return rte_flow_error_set(error, EINVAL,
5326 RTE_FLOW_ERROR_TYPE_ACTION, action,
5327 "configuration cannot be null");
5328 if (!(age->timeout))
5329 return rte_flow_error_set(error, EINVAL,
5330 RTE_FLOW_ERROR_TYPE_ACTION, action,
5331 "invalid timeout value 0");
5332 if (action_flags & MLX5_FLOW_ACTION_AGE)
5333 return rte_flow_error_set(error, EINVAL,
5334 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5335 "duplicate age actions set");
5340 * Validate the modify-header IPv4 DSCP actions.
5342 * @param[in] action_flags
5343 * Holds the actions detected until now.
5345 * Pointer to the modify action.
5346 * @param[in] item_flags
5347 * Holds the items detected.
5349 * Pointer to error structure.
5352 * 0 on success, a negative errno value otherwise and rte_errno is set.
5355 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5356 const struct rte_flow_action *action,
5357 const uint64_t item_flags,
5358 struct rte_flow_error *error)
5362 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5364 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5365 return rte_flow_error_set(error, EINVAL,
5366 RTE_FLOW_ERROR_TYPE_ACTION,
5368 "no ipv4 item in pattern");
5374 * Validate the modify-header IPv6 DSCP actions.
5376 * @param[in] action_flags
5377 * Holds the actions detected until now.
5379 * Pointer to the modify action.
5380 * @param[in] item_flags
5381 * Holds the items detected.
5383 * Pointer to error structure.
5386 * 0 on success, a negative errno value otherwise and rte_errno is set.
5389 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5390 const struct rte_flow_action *action,
5391 const uint64_t item_flags,
5392 struct rte_flow_error *error)
5396 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5398 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5399 return rte_flow_error_set(error, EINVAL,
5400 RTE_FLOW_ERROR_TYPE_ACTION,
5402 "no ipv6 item in pattern");
5408 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5409 struct mlx5_list_entry *entry, void *cb_ctx)
5411 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5412 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5413 struct mlx5_flow_dv_modify_hdr_resource *resource =
5414 container_of(entry, typeof(*resource), entry);
5415 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5417 key_len += ref->actions_num * sizeof(ref->actions[0]);
5418 return ref->actions_num != resource->actions_num ||
5419 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5422 static struct mlx5_indexed_pool *
5423 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5425 struct mlx5_indexed_pool *ipool = __atomic_load_n
5426 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5429 struct mlx5_indexed_pool *expected = NULL;
5430 struct mlx5_indexed_pool_config cfg =
5431 (struct mlx5_indexed_pool_config) {
5432 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5434 sizeof(struct mlx5_modification_cmd),
5439 .release_mem_en = !!sh->config.reclaim_mode,
5441 sh->config.reclaim_mode ? 0 : (1 << 16),
5442 .malloc = mlx5_malloc,
5444 .type = "mlx5_modify_action_resource",
5447 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5448 ipool = mlx5_ipool_create(&cfg);
5451 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5452 &expected, ipool, false,
5454 __ATOMIC_SEQ_CST)) {
5455 mlx5_ipool_destroy(ipool);
5456 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5463 struct mlx5_list_entry *
5464 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5466 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5467 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5468 struct mlx5dv_dr_domain *ns;
5469 struct mlx5_flow_dv_modify_hdr_resource *entry;
5470 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5471 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5472 ref->actions_num - 1);
5474 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5475 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5478 if (unlikely(!ipool)) {
5479 rte_flow_error_set(ctx->error, ENOMEM,
5480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5481 NULL, "cannot allocate modify ipool");
5484 entry = mlx5_ipool_zmalloc(ipool, &idx);
5486 rte_flow_error_set(ctx->error, ENOMEM,
5487 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5488 "cannot allocate resource memory");
5491 rte_memcpy(&entry->ft_type,
5492 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5493 key_len + data_len);
5494 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5495 ns = sh->fdb_domain;
5496 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5500 ret = mlx5_flow_os_create_flow_action_modify_header
5501 (sh->cdev->ctx, ns, entry,
5502 data_len, &entry->action);
5504 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5505 rte_flow_error_set(ctx->error, ENOMEM,
5506 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5507 NULL, "cannot create modification action");
5511 return &entry->entry;
5514 struct mlx5_list_entry *
5515 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5518 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5519 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5520 struct mlx5_flow_dv_modify_hdr_resource *entry;
5521 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5522 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5525 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5528 rte_flow_error_set(ctx->error, ENOMEM,
5529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5530 "cannot allocate resource memory");
5533 memcpy(entry, oentry, sizeof(*entry) + data_len);
5535 return &entry->entry;
5539 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5541 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5542 struct mlx5_flow_dv_modify_hdr_resource *res =
5543 container_of(entry, typeof(*res), entry);
5545 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5549 * Validate the sample action.
5551 * @param[in, out] action_flags
5552 * Holds the actions detected until now.
5554 * Pointer to the sample action.
5556 * Pointer to the Ethernet device structure.
5558 * Attributes of flow that includes this action.
5559 * @param[in] item_flags
5560 * Holds the items detected.
5562 * Pointer to the RSS action.
5563 * @param[out] sample_rss
5564 * Pointer to the RSS action in sample action list.
5566 * Pointer to the COUNT action in sample action list.
5567 * @param[out] fdb_mirror_limit
5568 * Pointer to the FDB mirror limitation flag.
5570 * Pointer to error structure.
5573 * 0 on success, a negative errno value otherwise and rte_errno is set.
5576 flow_dv_validate_action_sample(uint64_t *action_flags,
5577 const struct rte_flow_action *action,
5578 struct rte_eth_dev *dev,
5579 const struct rte_flow_attr *attr,
5580 uint64_t item_flags,
5581 const struct rte_flow_action_rss *rss,
5582 const struct rte_flow_action_rss **sample_rss,
5583 const struct rte_flow_action_count **count,
5584 int *fdb_mirror_limit,
5585 struct rte_flow_error *error)
5587 struct mlx5_priv *priv = dev->data->dev_private;
5588 struct mlx5_sh_config *dev_conf = &priv->sh->config;
5589 const struct rte_flow_action_sample *sample = action->conf;
5590 const struct rte_flow_action *act;
5591 uint64_t sub_action_flags = 0;
5592 uint16_t queue_index = 0xFFFF;
5597 return rte_flow_error_set(error, EINVAL,
5598 RTE_FLOW_ERROR_TYPE_ACTION, action,
5599 "configuration cannot be NULL");
5600 if (sample->ratio == 0)
5601 return rte_flow_error_set(error, EINVAL,
5602 RTE_FLOW_ERROR_TYPE_ACTION, action,
5603 "ratio value starts from 1");
5604 if (!priv->sh->cdev->config.devx ||
5605 (sample->ratio > 0 && !priv->sampler_en))
5606 return rte_flow_error_set(error, ENOTSUP,
5607 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5609 "sample action not supported");
5610 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5611 return rte_flow_error_set(error, EINVAL,
5612 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5613 "Multiple sample actions not "
5615 if (*action_flags & MLX5_FLOW_ACTION_METER)
5616 return rte_flow_error_set(error, EINVAL,
5617 RTE_FLOW_ERROR_TYPE_ACTION, action,
5618 "wrong action order, meter should "
5619 "be after sample action");
5620 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5621 return rte_flow_error_set(error, EINVAL,
5622 RTE_FLOW_ERROR_TYPE_ACTION, action,
5623 "wrong action order, jump should "
5624 "be after sample action");
5625 if (*action_flags & MLX5_FLOW_ACTION_CT)
5626 return rte_flow_error_set(error, EINVAL,
5627 RTE_FLOW_ERROR_TYPE_ACTION, action,
5628 "Sample after CT not supported");
5629 act = sample->actions;
5630 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5631 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5632 return rte_flow_error_set(error, ENOTSUP,
5633 RTE_FLOW_ERROR_TYPE_ACTION,
5634 act, "too many actions");
5635 switch (act->type) {
5636 case RTE_FLOW_ACTION_TYPE_QUEUE:
5637 ret = mlx5_flow_validate_action_queue(act,
5643 queue_index = ((const struct rte_flow_action_queue *)
5644 (act->conf))->index;
5645 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5648 case RTE_FLOW_ACTION_TYPE_RSS:
5649 *sample_rss = act->conf;
5650 ret = mlx5_flow_validate_action_rss(act,
5657 if (rss && *sample_rss &&
5658 ((*sample_rss)->level != rss->level ||
5659 (*sample_rss)->types != rss->types))
5660 return rte_flow_error_set(error, ENOTSUP,
5661 RTE_FLOW_ERROR_TYPE_ACTION,
5663 "Can't use the different RSS types "
5664 "or level in the same flow");
5665 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5666 queue_index = (*sample_rss)->queue[0];
5667 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5670 case RTE_FLOW_ACTION_TYPE_MARK:
5671 ret = flow_dv_validate_action_mark(dev, act,
5676 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5677 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5678 MLX5_FLOW_ACTION_MARK_EXT;
5680 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5683 case RTE_FLOW_ACTION_TYPE_COUNT:
5684 ret = flow_dv_validate_action_count
5685 (dev, false, *action_flags | sub_action_flags,
5690 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5691 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5694 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5695 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5696 ret = flow_dv_validate_action_port_id(dev,
5703 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5706 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5707 ret = flow_dv_validate_action_raw_encap_decap
5708 (dev, NULL, act->conf, attr, &sub_action_flags,
5709 &actions_n, action, item_flags, error);
5714 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5715 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5716 ret = flow_dv_validate_action_l2_encap(dev,
5722 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5726 return rte_flow_error_set(error, ENOTSUP,
5727 RTE_FLOW_ERROR_TYPE_ACTION,
5729 "Doesn't support optional "
5733 if (attr->ingress && !attr->transfer) {
5734 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5735 MLX5_FLOW_ACTION_RSS)))
5736 return rte_flow_error_set(error, EINVAL,
5737 RTE_FLOW_ERROR_TYPE_ACTION,
5739 "Ingress must has a dest "
5740 "QUEUE for Sample");
5741 } else if (attr->egress && !attr->transfer) {
5742 return rte_flow_error_set(error, ENOTSUP,
5743 RTE_FLOW_ERROR_TYPE_ACTION,
5745 "Sample Only support Ingress "
5747 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5748 MLX5_ASSERT(attr->transfer);
5749 if (sample->ratio > 1)
5750 return rte_flow_error_set(error, ENOTSUP,
5751 RTE_FLOW_ERROR_TYPE_ACTION,
5753 "E-Switch doesn't support "
5754 "any optional action "
5756 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5757 return rte_flow_error_set(error, ENOTSUP,
5758 RTE_FLOW_ERROR_TYPE_ACTION,
5760 "unsupported action QUEUE");
5761 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5762 return rte_flow_error_set(error, ENOTSUP,
5763 RTE_FLOW_ERROR_TYPE_ACTION,
5765 "unsupported action QUEUE");
5766 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5767 return rte_flow_error_set(error, EINVAL,
5768 RTE_FLOW_ERROR_TYPE_ACTION,
5770 "E-Switch must has a dest "
5771 "port for mirroring");
5772 if (!priv->sh->cdev->config.hca_attr.reg_c_preserve &&
5773 priv->representor_id != UINT16_MAX)
5774 *fdb_mirror_limit = 1;
5776 /* Continue validation for Xcap actions.*/
5777 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5778 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index))) {
5779 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5780 MLX5_FLOW_XCAP_ACTIONS)
5781 return rte_flow_error_set(error, ENOTSUP,
5782 RTE_FLOW_ERROR_TYPE_ACTION,
5783 NULL, "encap and decap "
5784 "combination aren't "
5786 if (!attr->transfer && attr->ingress && (sub_action_flags &
5787 MLX5_FLOW_ACTION_ENCAP))
5788 return rte_flow_error_set(error, ENOTSUP,
5789 RTE_FLOW_ERROR_TYPE_ACTION,
5790 NULL, "encap is not supported"
5791 " for ingress traffic");
5797 * Find existing modify-header resource or create and register a new one.
5799 * @param dev[in, out]
5800 * Pointer to rte_eth_dev structure.
5801 * @param[in, out] resource
5802 * Pointer to modify-header resource.
5803 * @parm[in, out] dev_flow
5804 * Pointer to the dev_flow.
5806 * pointer to error structure.
5809 * 0 on success otherwise -errno and errno is set.
5812 flow_dv_modify_hdr_resource_register
5813 (struct rte_eth_dev *dev,
5814 struct mlx5_flow_dv_modify_hdr_resource *resource,
5815 struct mlx5_flow *dev_flow,
5816 struct rte_flow_error *error)
5818 struct mlx5_priv *priv = dev->data->dev_private;
5819 struct mlx5_dev_ctx_shared *sh = priv->sh;
5820 uint32_t key_len = sizeof(*resource) -
5821 offsetof(typeof(*resource), ft_type) +
5822 resource->actions_num * sizeof(resource->actions[0]);
5823 struct mlx5_list_entry *entry;
5824 struct mlx5_flow_cb_ctx ctx = {
5828 struct mlx5_hlist *modify_cmds;
5831 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5833 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5835 flow_dv_modify_create_cb,
5836 flow_dv_modify_match_cb,
5837 flow_dv_modify_remove_cb,
5838 flow_dv_modify_clone_cb,
5839 flow_dv_modify_clone_free_cb,
5841 if (unlikely(!modify_cmds))
5843 resource->root = !dev_flow->dv.group;
5844 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5846 return rte_flow_error_set(error, EOVERFLOW,
5847 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5848 "too many modify header items");
5849 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5850 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5853 resource = container_of(entry, typeof(*resource), entry);
5854 dev_flow->handle->dvh.modify_hdr = resource;
5859 * Get DV flow counter by index.
5862 * Pointer to the Ethernet device structure.
5864 * mlx5 flow counter index in the container.
5866 * mlx5 flow counter pool in the container.
5869 * Pointer to the counter, NULL otherwise.
5871 static struct mlx5_flow_counter *
5872 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5874 struct mlx5_flow_counter_pool **ppool)
5876 struct mlx5_priv *priv = dev->data->dev_private;
5877 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5878 struct mlx5_flow_counter_pool *pool;
5880 /* Decrease to original index and clear shared bit. */
5881 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5882 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5883 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5887 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5891 * Check the devx counter belongs to the pool.
5894 * Pointer to the counter pool.
5896 * The counter devx ID.
5899 * True if counter belongs to the pool, false otherwise.
5902 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5904 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5905 MLX5_COUNTERS_PER_POOL;
5907 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5913 * Get a pool by devx counter ID.
5916 * Pointer to the counter management.
5918 * The counter devx ID.
5921 * The counter pool pointer if exists, NULL otherwise,
5923 static struct mlx5_flow_counter_pool *
5924 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5927 struct mlx5_flow_counter_pool *pool = NULL;
5929 rte_spinlock_lock(&cmng->pool_update_sl);
5930 /* Check last used pool. */
5931 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5932 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5933 pool = cmng->pools[cmng->last_pool_idx];
5936 /* ID out of range means no suitable pool in the container. */
5937 if (id > cmng->max_id || id < cmng->min_id)
5940 * Find the pool from the end of the container, since mostly counter
5941 * ID is sequence increasing, and the last pool should be the needed
5946 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5948 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5954 rte_spinlock_unlock(&cmng->pool_update_sl);
5959 * Resize a counter container.
5962 * Pointer to the Ethernet device structure.
5965 * 0 on success, otherwise negative errno value and rte_errno is set.
5968 flow_dv_container_resize(struct rte_eth_dev *dev)
5970 struct mlx5_priv *priv = dev->data->dev_private;
5971 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5972 void *old_pools = cmng->pools;
5973 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5974 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5975 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5982 memcpy(pools, old_pools, cmng->n *
5983 sizeof(struct mlx5_flow_counter_pool *));
5985 cmng->pools = pools;
5987 mlx5_free(old_pools);
5992 * Query a devx flow counter.
5995 * Pointer to the Ethernet device structure.
5996 * @param[in] counter
5997 * Index to the flow counter.
5999 * The statistics value of packets.
6001 * The statistics value of bytes.
6004 * 0 on success, otherwise a negative errno value and rte_errno is set.
6007 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
6010 struct mlx5_priv *priv = dev->data->dev_private;
6011 struct mlx5_flow_counter_pool *pool = NULL;
6012 struct mlx5_flow_counter *cnt;
6015 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6017 if (priv->sh->cmng.counter_fallback)
6018 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6019 0, pkts, bytes, 0, NULL, NULL, 0);
6020 rte_spinlock_lock(&pool->sl);
6025 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6026 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6027 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6029 rte_spinlock_unlock(&pool->sl);
6034 * Create and initialize a new counter pool.
6037 * Pointer to the Ethernet device structure.
6039 * The devX counter handle.
6041 * Whether the pool is for counter that was allocated for aging.
6042 * @param[in/out] cont_cur
6043 * Pointer to the container pointer, it will be update in pool resize.
6046 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6048 static struct mlx5_flow_counter_pool *
6049 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6052 struct mlx5_priv *priv = dev->data->dev_private;
6053 struct mlx5_flow_counter_pool *pool;
6054 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6055 bool fallback = priv->sh->cmng.counter_fallback;
6056 uint32_t size = sizeof(*pool);
6058 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6059 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6060 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6066 pool->is_aged = !!age;
6067 pool->query_gen = 0;
6068 pool->min_dcs = dcs;
6069 rte_spinlock_init(&pool->sl);
6070 rte_spinlock_init(&pool->csl);
6071 TAILQ_INIT(&pool->counters[0]);
6072 TAILQ_INIT(&pool->counters[1]);
6073 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6074 rte_spinlock_lock(&cmng->pool_update_sl);
6075 pool->index = cmng->n_valid;
6076 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6078 rte_spinlock_unlock(&cmng->pool_update_sl);
6081 cmng->pools[pool->index] = pool;
6083 if (unlikely(fallback)) {
6084 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6086 if (base < cmng->min_id)
6087 cmng->min_id = base;
6088 if (base > cmng->max_id)
6089 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6090 cmng->last_pool_idx = pool->index;
6092 rte_spinlock_unlock(&cmng->pool_update_sl);
6097 * Prepare a new counter and/or a new counter pool.
6100 * Pointer to the Ethernet device structure.
6101 * @param[out] cnt_free
6102 * Where to put the pointer of a new counter.
6104 * Whether the pool is for counter that was allocated for aging.
6107 * The counter pool pointer and @p cnt_free is set on success,
6108 * NULL otherwise and rte_errno is set.
6110 static struct mlx5_flow_counter_pool *
6111 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6112 struct mlx5_flow_counter **cnt_free,
6115 struct mlx5_priv *priv = dev->data->dev_private;
6116 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6117 struct mlx5_flow_counter_pool *pool;
6118 struct mlx5_counters tmp_tq;
6119 struct mlx5_devx_obj *dcs = NULL;
6120 struct mlx5_flow_counter *cnt;
6121 enum mlx5_counter_type cnt_type =
6122 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6123 bool fallback = priv->sh->cmng.counter_fallback;
6127 /* bulk_bitmap must be 0 for single counter allocation. */
6128 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6131 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6133 pool = flow_dv_pool_create(dev, dcs, age);
6135 mlx5_devx_cmd_destroy(dcs);
6139 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6140 cnt = MLX5_POOL_GET_CNT(pool, i);
6142 cnt->dcs_when_free = dcs;
6146 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6148 rte_errno = ENODATA;
6151 pool = flow_dv_pool_create(dev, dcs, age);
6153 mlx5_devx_cmd_destroy(dcs);
6156 TAILQ_INIT(&tmp_tq);
6157 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6158 cnt = MLX5_POOL_GET_CNT(pool, i);
6160 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6162 rte_spinlock_lock(&cmng->csl[cnt_type]);
6163 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6164 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6165 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6166 (*cnt_free)->pool = pool;
6171 * Allocate a flow counter.
6174 * Pointer to the Ethernet device structure.
6176 * Whether the counter was allocated for aging.
6179 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6182 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6184 struct mlx5_priv *priv = dev->data->dev_private;
6185 struct mlx5_flow_counter_pool *pool = NULL;
6186 struct mlx5_flow_counter *cnt_free = NULL;
6187 bool fallback = priv->sh->cmng.counter_fallback;
6188 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6189 enum mlx5_counter_type cnt_type =
6190 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6193 if (!priv->sh->cdev->config.devx) {
6194 rte_errno = ENOTSUP;
6197 /* Get free counters from container. */
6198 rte_spinlock_lock(&cmng->csl[cnt_type]);
6199 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6201 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6202 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6203 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6205 pool = cnt_free->pool;
6207 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6208 /* Create a DV counter action only in the first time usage. */
6209 if (!cnt_free->action) {
6211 struct mlx5_devx_obj *dcs;
6215 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6216 dcs = pool->min_dcs;
6219 dcs = cnt_free->dcs_when_free;
6221 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6228 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6229 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6230 /* Update the counter reset values. */
6231 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6234 if (!fallback && !priv->sh->cmng.query_thread_on)
6235 /* Start the asynchronous batch query by the host thread. */
6236 mlx5_set_query_alarm(priv->sh);
6238 * When the count action isn't shared (by ID), shared_info field is
6239 * used for indirect action API's refcnt.
6240 * When the counter action is not shared neither by ID nor by indirect
6241 * action API, shared info must be 1.
6243 cnt_free->shared_info.refcnt = 1;
6247 cnt_free->pool = pool;
6249 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6250 rte_spinlock_lock(&cmng->csl[cnt_type]);
6251 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6252 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6258 * Get age param from counter index.
6261 * Pointer to the Ethernet device structure.
6262 * @param[in] counter
6263 * Index to the counter handler.
6266 * The aging parameter specified for the counter index.
6268 static struct mlx5_age_param*
6269 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6272 struct mlx5_flow_counter *cnt;
6273 struct mlx5_flow_counter_pool *pool = NULL;
6275 flow_dv_counter_get_by_idx(dev, counter, &pool);
6276 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6277 cnt = MLX5_POOL_GET_CNT(pool, counter);
6278 return MLX5_CNT_TO_AGE(cnt);
6282 * Remove a flow counter from aged counter list.
6285 * Pointer to the Ethernet device structure.
6286 * @param[in] counter
6287 * Index to the counter handler.
6289 * Pointer to the counter handler.
6292 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6293 uint32_t counter, struct mlx5_flow_counter *cnt)
6295 struct mlx5_age_info *age_info;
6296 struct mlx5_age_param *age_param;
6297 struct mlx5_priv *priv = dev->data->dev_private;
6298 uint16_t expected = AGE_CANDIDATE;
6300 age_info = GET_PORT_AGE_INFO(priv);
6301 age_param = flow_dv_counter_idx_get_age(dev, counter);
6302 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6303 AGE_FREE, false, __ATOMIC_RELAXED,
6304 __ATOMIC_RELAXED)) {
6306 * We need the lock even it is age timeout,
6307 * since counter may still in process.
6309 rte_spinlock_lock(&age_info->aged_sl);
6310 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6311 rte_spinlock_unlock(&age_info->aged_sl);
6312 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6317 * Release a flow counter.
6320 * Pointer to the Ethernet device structure.
6321 * @param[in] counter
6322 * Index to the counter handler.
6325 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6327 struct mlx5_priv *priv = dev->data->dev_private;
6328 struct mlx5_flow_counter_pool *pool = NULL;
6329 struct mlx5_flow_counter *cnt;
6330 enum mlx5_counter_type cnt_type;
6334 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6336 if (pool->is_aged) {
6337 flow_dv_counter_remove_from_age(dev, counter, cnt);
6340 * If the counter action is shared by indirect action API,
6341 * the atomic function reduces its references counter.
6342 * If after the reduction the action is still referenced, the
6343 * function returns here and does not release it.
6344 * When the counter action is not shared by
6345 * indirect action API, shared info is 1 before the reduction,
6346 * so this condition is failed and function doesn't return here.
6348 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6354 * Put the counter back to list to be updated in none fallback mode.
6355 * Currently, we are using two list alternately, while one is in query,
6356 * add the freed counter to the other list based on the pool query_gen
6357 * value. After query finishes, add counter the list to the global
6358 * container counter list. The list changes while query starts. In
6359 * this case, lock will not be needed as query callback and release
6360 * function both operate with the different list.
6362 if (!priv->sh->cmng.counter_fallback) {
6363 rte_spinlock_lock(&pool->csl);
6364 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6365 rte_spinlock_unlock(&pool->csl);
6367 cnt->dcs_when_free = cnt->dcs_when_active;
6368 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6369 MLX5_COUNTER_TYPE_ORIGIN;
6370 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6371 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6373 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6378 * Resize a meter id container.
6381 * Pointer to the Ethernet device structure.
6384 * 0 on success, otherwise negative errno value and rte_errno is set.
6387 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6389 struct mlx5_priv *priv = dev->data->dev_private;
6390 struct mlx5_aso_mtr_pools_mng *pools_mng =
6391 &priv->sh->mtrmng->pools_mng;
6392 void *old_pools = pools_mng->pools;
6393 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6394 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6395 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6402 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6407 memcpy(pools, old_pools, pools_mng->n *
6408 sizeof(struct mlx5_aso_mtr_pool *));
6409 pools_mng->n = resize;
6410 pools_mng->pools = pools;
6412 mlx5_free(old_pools);
6417 * Prepare a new meter and/or a new meter pool.
6420 * Pointer to the Ethernet device structure.
6421 * @param[out] mtr_free
6422 * Where to put the pointer of a new meter.g.
6425 * The meter pool pointer and @mtr_free is set on success,
6426 * NULL otherwise and rte_errno is set.
6428 static struct mlx5_aso_mtr_pool *
6429 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6431 struct mlx5_priv *priv = dev->data->dev_private;
6432 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6433 struct mlx5_aso_mtr_pool *pool = NULL;
6434 struct mlx5_devx_obj *dcs = NULL;
6436 uint32_t log_obj_size;
6438 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6439 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6440 priv->sh->cdev->pdn,
6443 rte_errno = ENODATA;
6446 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6449 claim_zero(mlx5_devx_cmd_destroy(dcs));
6452 pool->devx_obj = dcs;
6453 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6454 pool->index = pools_mng->n_valid;
6455 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6457 claim_zero(mlx5_devx_cmd_destroy(dcs));
6458 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6461 pools_mng->pools[pool->index] = pool;
6462 pools_mng->n_valid++;
6463 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6464 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6465 pool->mtrs[i].offset = i;
6466 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6468 pool->mtrs[0].offset = 0;
6469 *mtr_free = &pool->mtrs[0];
6474 * Release a flow meter into pool.
6477 * Pointer to the Ethernet device structure.
6478 * @param[in] mtr_idx
6479 * Index to aso flow meter.
6482 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6484 struct mlx5_priv *priv = dev->data->dev_private;
6485 struct mlx5_aso_mtr_pools_mng *pools_mng =
6486 &priv->sh->mtrmng->pools_mng;
6487 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6489 MLX5_ASSERT(aso_mtr);
6490 rte_spinlock_lock(&pools_mng->mtrsl);
6491 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6492 aso_mtr->state = ASO_METER_FREE;
6493 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6494 rte_spinlock_unlock(&pools_mng->mtrsl);
6498 * Allocate a aso flow meter.
6501 * Pointer to the Ethernet device structure.
6504 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6507 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6509 struct mlx5_priv *priv = dev->data->dev_private;
6510 struct mlx5_aso_mtr *mtr_free = NULL;
6511 struct mlx5_aso_mtr_pools_mng *pools_mng =
6512 &priv->sh->mtrmng->pools_mng;
6513 struct mlx5_aso_mtr_pool *pool;
6514 uint32_t mtr_idx = 0;
6516 if (!priv->sh->cdev->config.devx) {
6517 rte_errno = ENOTSUP;
6520 /* Allocate the flow meter memory. */
6521 /* Get free meters from management. */
6522 rte_spinlock_lock(&pools_mng->mtrsl);
6523 mtr_free = LIST_FIRST(&pools_mng->meters);
6525 LIST_REMOVE(mtr_free, next);
6526 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6527 rte_spinlock_unlock(&pools_mng->mtrsl);
6530 mtr_free->state = ASO_METER_WAIT;
6531 rte_spinlock_unlock(&pools_mng->mtrsl);
6532 pool = container_of(mtr_free,
6533 struct mlx5_aso_mtr_pool,
6534 mtrs[mtr_free->offset]);
6535 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6536 if (!mtr_free->fm.meter_action) {
6537 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6538 struct rte_flow_error error;
6541 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6542 mtr_free->fm.meter_action =
6543 mlx5_glue->dv_create_flow_action_aso
6544 (priv->sh->rx_domain,
6545 pool->devx_obj->obj,
6547 (1 << MLX5_FLOW_COLOR_GREEN),
6549 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6550 if (!mtr_free->fm.meter_action) {
6551 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6559 * Verify the @p attributes will be correctly understood by the NIC and store
6560 * them in the @p flow if everything is correct.
6563 * Pointer to dev struct.
6564 * @param[in] attributes
6565 * Pointer to flow attributes
6566 * @param[in] external
6567 * This flow rule is created by request external to PMD.
6569 * Pointer to error structure.
6572 * - 0 on success and non root table.
6573 * - 1 on success and root table.
6574 * - a negative errno value otherwise and rte_errno is set.
6577 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6578 const struct mlx5_flow_tunnel *tunnel,
6579 const struct rte_flow_attr *attributes,
6580 const struct flow_grp_info *grp_info,
6581 struct rte_flow_error *error)
6583 struct mlx5_priv *priv = dev->data->dev_private;
6584 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6587 #ifndef HAVE_MLX5DV_DR
6588 RTE_SET_USED(tunnel);
6589 RTE_SET_USED(grp_info);
6590 if (attributes->group)
6591 return rte_flow_error_set(error, ENOTSUP,
6592 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6594 "groups are not supported");
6598 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6603 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6605 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6606 attributes->priority > lowest_priority)
6607 return rte_flow_error_set(error, ENOTSUP,
6608 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6610 "priority out of range");
6611 if (attributes->transfer) {
6612 if (!priv->sh->config.dv_esw_en)
6613 return rte_flow_error_set
6615 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6616 "E-Switch dr is not supported");
6617 if (attributes->egress)
6618 return rte_flow_error_set
6620 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6621 "egress is not supported");
6623 if (!(attributes->egress ^ attributes->ingress))
6624 return rte_flow_error_set(error, ENOTSUP,
6625 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6626 "must specify exactly one of "
6627 "ingress or egress");
6632 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6633 int64_t pattern_flags, uint64_t l3_flags,
6634 uint64_t l4_flags, uint64_t ip4_flag,
6635 struct rte_flow_error *error)
6637 if (mask->l3_ok && !(pattern_flags & l3_flags))
6638 return rte_flow_error_set(error, EINVAL,
6639 RTE_FLOW_ERROR_TYPE_ITEM,
6640 NULL, "missing L3 protocol");
6642 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6643 return rte_flow_error_set(error, EINVAL,
6644 RTE_FLOW_ERROR_TYPE_ITEM,
6645 NULL, "missing IPv4 protocol");
6647 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6648 return rte_flow_error_set(error, EINVAL,
6649 RTE_FLOW_ERROR_TYPE_ITEM,
6650 NULL, "missing L4 protocol");
6656 flow_dv_validate_item_integrity_post(const struct
6657 rte_flow_item *integrity_items[2],
6658 int64_t pattern_flags,
6659 struct rte_flow_error *error)
6661 const struct rte_flow_item_integrity *mask;
6664 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6665 mask = (typeof(mask))integrity_items[0]->mask;
6666 ret = validate_integrity_bits(mask, pattern_flags,
6667 MLX5_FLOW_LAYER_OUTER_L3,
6668 MLX5_FLOW_LAYER_OUTER_L4,
6669 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6674 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6675 mask = (typeof(mask))integrity_items[1]->mask;
6676 ret = validate_integrity_bits(mask, pattern_flags,
6677 MLX5_FLOW_LAYER_INNER_L3,
6678 MLX5_FLOW_LAYER_INNER_L4,
6679 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6688 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6689 const struct rte_flow_item *integrity_item,
6690 uint64_t pattern_flags, uint64_t *last_item,
6691 const struct rte_flow_item *integrity_items[2],
6692 struct rte_flow_error *error)
6694 struct mlx5_priv *priv = dev->data->dev_private;
6695 const struct rte_flow_item_integrity *mask = (typeof(mask))
6696 integrity_item->mask;
6697 const struct rte_flow_item_integrity *spec = (typeof(spec))
6698 integrity_item->spec;
6700 if (!priv->sh->cdev->config.hca_attr.pkt_integrity_match)
6701 return rte_flow_error_set(error, ENOTSUP,
6702 RTE_FLOW_ERROR_TYPE_ITEM,
6704 "packet integrity integrity_item not supported");
6706 return rte_flow_error_set(error, ENOTSUP,
6707 RTE_FLOW_ERROR_TYPE_ITEM,
6709 "no spec for integrity item");
6711 mask = &rte_flow_item_integrity_mask;
6712 if (!mlx5_validate_integrity_item(mask))
6713 return rte_flow_error_set(error, ENOTSUP,
6714 RTE_FLOW_ERROR_TYPE_ITEM,
6716 "unsupported integrity filter");
6717 if (spec->level > 1) {
6718 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6719 return rte_flow_error_set
6721 RTE_FLOW_ERROR_TYPE_ITEM,
6722 NULL, "multiple inner integrity items not supported");
6723 integrity_items[1] = integrity_item;
6724 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6726 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6727 return rte_flow_error_set
6729 RTE_FLOW_ERROR_TYPE_ITEM,
6730 NULL, "multiple outer integrity items not supported");
6731 integrity_items[0] = integrity_item;
6732 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6738 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6739 const struct rte_flow_item *item,
6740 uint64_t item_flags,
6741 uint64_t *last_item,
6743 struct rte_flow_error *error)
6745 const struct rte_flow_item_flex *flow_spec = item->spec;
6746 const struct rte_flow_item_flex *flow_mask = item->mask;
6747 struct mlx5_flex_item *flex;
6750 return rte_flow_error_set(error, EINVAL,
6751 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6752 "flex flow item spec cannot be NULL");
6754 return rte_flow_error_set(error, EINVAL,
6755 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6756 "flex flow item mask cannot be NULL");
6758 return rte_flow_error_set(error, ENOTSUP,
6759 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6760 "flex flow item last not supported");
6761 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6762 return rte_flow_error_set(error, EINVAL,
6763 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6764 "invalid flex flow item handle");
6765 flex = (struct mlx5_flex_item *)flow_spec->handle;
6766 switch (flex->tunnel_mode) {
6767 case FLEX_TUNNEL_MODE_SINGLE:
6769 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6770 rte_flow_error_set(error, EINVAL,
6771 RTE_FLOW_ERROR_TYPE_ITEM,
6772 NULL, "multiple flex items not supported");
6774 case FLEX_TUNNEL_MODE_OUTER:
6776 rte_flow_error_set(error, EINVAL,
6777 RTE_FLOW_ERROR_TYPE_ITEM,
6778 NULL, "inner flex item was not configured");
6779 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6780 rte_flow_error_set(error, ENOTSUP,
6781 RTE_FLOW_ERROR_TYPE_ITEM,
6782 NULL, "multiple flex items not supported");
6784 case FLEX_TUNNEL_MODE_INNER:
6786 rte_flow_error_set(error, EINVAL,
6787 RTE_FLOW_ERROR_TYPE_ITEM,
6788 NULL, "outer flex item was not configured");
6789 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6790 rte_flow_error_set(error, EINVAL,
6791 RTE_FLOW_ERROR_TYPE_ITEM,
6792 NULL, "multiple flex items not supported");
6794 case FLEX_TUNNEL_MODE_MULTI:
6795 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6796 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6797 rte_flow_error_set(error, EINVAL,
6798 RTE_FLOW_ERROR_TYPE_ITEM,
6799 NULL, "multiple flex items not supported");
6802 case FLEX_TUNNEL_MODE_TUNNEL:
6803 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6804 rte_flow_error_set(error, EINVAL,
6805 RTE_FLOW_ERROR_TYPE_ITEM,
6806 NULL, "multiple flex tunnel items not supported");
6809 rte_flow_error_set(error, EINVAL,
6810 RTE_FLOW_ERROR_TYPE_ITEM,
6811 NULL, "invalid flex item configuration");
6813 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6814 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6815 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6820 * Internal validation function. For validating both actions and items.
6823 * Pointer to the rte_eth_dev structure.
6825 * Pointer to the flow attributes.
6827 * Pointer to the list of items.
6828 * @param[in] actions
6829 * Pointer to the list of actions.
6830 * @param[in] external
6831 * This flow rule is created by request external to PMD.
6832 * @param[in] hairpin
6833 * Number of hairpin TX actions, 0 means classic flow.
6835 * Pointer to the error structure.
6838 * 0 on success, a negative errno value otherwise and rte_errno is set.
6841 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6842 const struct rte_flow_item items[],
6843 const struct rte_flow_action actions[],
6844 bool external, int hairpin, struct rte_flow_error *error)
6847 uint64_t action_flags = 0;
6848 uint64_t item_flags = 0;
6849 uint64_t last_item = 0;
6850 uint8_t next_protocol = 0xff;
6851 uint16_t ether_type = 0;
6853 uint8_t item_ipv6_proto = 0;
6854 int fdb_mirror_limit = 0;
6855 int modify_after_mirror = 0;
6856 const struct rte_flow_item *geneve_item = NULL;
6857 const struct rte_flow_item *gre_item = NULL;
6858 const struct rte_flow_item *gtp_item = NULL;
6859 const struct rte_flow_action_raw_decap *decap;
6860 const struct rte_flow_action_raw_encap *encap;
6861 const struct rte_flow_action_rss *rss = NULL;
6862 const struct rte_flow_action_rss *sample_rss = NULL;
6863 const struct rte_flow_action_count *sample_count = NULL;
6864 const struct rte_flow_item_tcp nic_tcp_mask = {
6867 .src_port = RTE_BE16(UINT16_MAX),
6868 .dst_port = RTE_BE16(UINT16_MAX),
6871 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6874 "\xff\xff\xff\xff\xff\xff\xff\xff"
6875 "\xff\xff\xff\xff\xff\xff\xff\xff",
6877 "\xff\xff\xff\xff\xff\xff\xff\xff"
6878 "\xff\xff\xff\xff\xff\xff\xff\xff",
6879 .vtc_flow = RTE_BE32(0xffffffff),
6885 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6889 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6893 .dummy[0] = 0xffffffff,
6896 struct mlx5_priv *priv = dev->data->dev_private;
6897 struct mlx5_sh_config *dev_conf = &priv->sh->config;
6898 uint16_t queue_index = 0xFFFF;
6899 const struct rte_flow_item_vlan *vlan_m = NULL;
6900 uint32_t rw_act_num = 0;
6902 const struct mlx5_flow_tunnel *tunnel;
6903 enum mlx5_tof_rule_type tof_rule_type;
6904 struct flow_grp_info grp_info = {
6905 .external = !!external,
6906 .transfer = !!attr->transfer,
6907 .fdb_def_rule = !!priv->fdb_def_rule,
6908 .std_tbl_fix = true,
6910 const struct rte_eth_hairpin_conf *conf;
6911 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6912 const struct rte_flow_item *port_id_item = NULL;
6913 bool def_policy = false;
6914 bool shared_count = false;
6915 uint16_t udp_dport = 0;
6916 uint32_t tag_id = 0;
6920 tunnel = is_tunnel_offload_active(dev) ?
6921 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6923 if (!dev_conf->dv_flow_en)
6924 return rte_flow_error_set
6926 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6927 NULL, "tunnel offload requires DV flow interface");
6928 if (priv->representor)
6929 return rte_flow_error_set
6931 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6932 NULL, "decap not supported for VF representor");
6933 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6934 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6935 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6936 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6937 MLX5_FLOW_ACTION_DECAP;
6938 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6939 (dev, attr, tunnel, tof_rule_type);
6941 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6944 is_root = (uint64_t)ret;
6945 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6946 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6947 int type = items->type;
6949 if (!mlx5_flow_os_item_supported(type))
6950 return rte_flow_error_set(error, ENOTSUP,
6951 RTE_FLOW_ERROR_TYPE_ITEM,
6952 NULL, "item not supported");
6954 case RTE_FLOW_ITEM_TYPE_VOID:
6956 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6957 ret = flow_dv_validate_item_port_id
6958 (dev, items, attr, item_flags, error);
6961 last_item = MLX5_FLOW_ITEM_PORT_ID;
6962 port_id_item = items;
6964 case RTE_FLOW_ITEM_TYPE_ETH:
6965 ret = mlx5_flow_validate_item_eth(items, item_flags,
6969 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6970 MLX5_FLOW_LAYER_OUTER_L2;
6971 if (items->mask != NULL && items->spec != NULL) {
6973 ((const struct rte_flow_item_eth *)
6976 ((const struct rte_flow_item_eth *)
6978 ether_type = rte_be_to_cpu_16(ether_type);
6983 case RTE_FLOW_ITEM_TYPE_VLAN:
6984 ret = flow_dv_validate_item_vlan(items, item_flags,
6988 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6989 MLX5_FLOW_LAYER_OUTER_VLAN;
6990 if (items->mask != NULL && items->spec != NULL) {
6992 ((const struct rte_flow_item_vlan *)
6993 items->spec)->inner_type;
6995 ((const struct rte_flow_item_vlan *)
6996 items->mask)->inner_type;
6997 ether_type = rte_be_to_cpu_16(ether_type);
7001 /* Store outer VLAN mask for of_push_vlan action. */
7003 vlan_m = items->mask;
7005 case RTE_FLOW_ITEM_TYPE_IPV4:
7006 mlx5_flow_tunnel_ip_check(items, next_protocol,
7007 &item_flags, &tunnel);
7008 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7009 last_item, ether_type,
7013 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7014 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7015 if (items->mask != NULL &&
7016 ((const struct rte_flow_item_ipv4 *)
7017 items->mask)->hdr.next_proto_id) {
7019 ((const struct rte_flow_item_ipv4 *)
7020 (items->spec))->hdr.next_proto_id;
7022 ((const struct rte_flow_item_ipv4 *)
7023 (items->mask))->hdr.next_proto_id;
7025 /* Reset for inner layer. */
7026 next_protocol = 0xff;
7029 case RTE_FLOW_ITEM_TYPE_IPV6:
7030 mlx5_flow_tunnel_ip_check(items, next_protocol,
7031 &item_flags, &tunnel);
7032 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7039 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7040 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7041 if (items->mask != NULL &&
7042 ((const struct rte_flow_item_ipv6 *)
7043 items->mask)->hdr.proto) {
7045 ((const struct rte_flow_item_ipv6 *)
7046 items->spec)->hdr.proto;
7048 ((const struct rte_flow_item_ipv6 *)
7049 items->spec)->hdr.proto;
7051 ((const struct rte_flow_item_ipv6 *)
7052 items->mask)->hdr.proto;
7054 /* Reset for inner layer. */
7055 next_protocol = 0xff;
7058 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7059 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7064 last_item = tunnel ?
7065 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7066 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7067 if (items->mask != NULL &&
7068 ((const struct rte_flow_item_ipv6_frag_ext *)
7069 items->mask)->hdr.next_header) {
7071 ((const struct rte_flow_item_ipv6_frag_ext *)
7072 items->spec)->hdr.next_header;
7074 ((const struct rte_flow_item_ipv6_frag_ext *)
7075 items->mask)->hdr.next_header;
7077 /* Reset for inner layer. */
7078 next_protocol = 0xff;
7081 case RTE_FLOW_ITEM_TYPE_TCP:
7082 ret = mlx5_flow_validate_item_tcp
7089 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7090 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7092 case RTE_FLOW_ITEM_TYPE_UDP:
7093 ret = mlx5_flow_validate_item_udp(items, item_flags,
7096 const struct rte_flow_item_udp *spec = items->spec;
7097 const struct rte_flow_item_udp *mask = items->mask;
7099 mask = &rte_flow_item_udp_mask;
7101 udp_dport = rte_be_to_cpu_16
7102 (spec->hdr.dst_port &
7103 mask->hdr.dst_port);
7106 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7107 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7109 case RTE_FLOW_ITEM_TYPE_GRE:
7110 ret = mlx5_flow_validate_item_gre(items, item_flags,
7111 next_protocol, error);
7115 last_item = MLX5_FLOW_LAYER_GRE;
7117 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
7118 ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
7119 attr, gre_item, error);
7122 last_item = MLX5_FLOW_LAYER_GRE;
7124 case RTE_FLOW_ITEM_TYPE_NVGRE:
7125 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7130 last_item = MLX5_FLOW_LAYER_NVGRE;
7132 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7133 ret = mlx5_flow_validate_item_gre_key
7134 (items, item_flags, gre_item, error);
7137 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7139 case RTE_FLOW_ITEM_TYPE_VXLAN:
7140 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7145 last_item = MLX5_FLOW_LAYER_VXLAN;
7147 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7148 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7153 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7155 case RTE_FLOW_ITEM_TYPE_GENEVE:
7156 ret = mlx5_flow_validate_item_geneve(items,
7161 geneve_item = items;
7162 last_item = MLX5_FLOW_LAYER_GENEVE;
7164 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7165 ret = mlx5_flow_validate_item_geneve_opt(items,
7172 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7174 case RTE_FLOW_ITEM_TYPE_MPLS:
7175 ret = mlx5_flow_validate_item_mpls(dev, items,
7180 last_item = MLX5_FLOW_LAYER_MPLS;
7183 case RTE_FLOW_ITEM_TYPE_MARK:
7184 ret = flow_dv_validate_item_mark(dev, items, attr,
7188 last_item = MLX5_FLOW_ITEM_MARK;
7190 case RTE_FLOW_ITEM_TYPE_META:
7191 ret = flow_dv_validate_item_meta(dev, items, attr,
7195 last_item = MLX5_FLOW_ITEM_METADATA;
7197 case RTE_FLOW_ITEM_TYPE_ICMP:
7198 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7203 last_item = MLX5_FLOW_LAYER_ICMP;
7205 case RTE_FLOW_ITEM_TYPE_ICMP6:
7206 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7211 item_ipv6_proto = IPPROTO_ICMPV6;
7212 last_item = MLX5_FLOW_LAYER_ICMP6;
7214 case RTE_FLOW_ITEM_TYPE_TAG:
7215 ret = flow_dv_validate_item_tag(dev, items,
7219 last_item = MLX5_FLOW_ITEM_TAG;
7221 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7222 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7224 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7226 case RTE_FLOW_ITEM_TYPE_GTP:
7227 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7232 last_item = MLX5_FLOW_LAYER_GTP;
7234 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7235 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7240 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7242 case RTE_FLOW_ITEM_TYPE_ECPRI:
7243 /* Capacity will be checked in the translate stage. */
7244 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7251 last_item = MLX5_FLOW_LAYER_ECPRI;
7253 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7254 ret = flow_dv_validate_item_integrity(dev, items,
7262 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7263 ret = flow_dv_validate_item_aso_ct(dev, items,
7264 &item_flags, error);
7268 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7269 /* tunnel offload item was processed before
7270 * list it here as a supported type
7273 case RTE_FLOW_ITEM_TYPE_FLEX:
7274 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7276 tunnel != 0, error);
7281 return rte_flow_error_set(error, ENOTSUP,
7282 RTE_FLOW_ERROR_TYPE_ITEM,
7283 NULL, "item not supported");
7285 item_flags |= last_item;
7287 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7288 ret = flow_dv_validate_item_integrity_post(integrity_items,
7293 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7294 int type = actions->type;
7296 if (!mlx5_flow_os_action_supported(type))
7297 return rte_flow_error_set(error, ENOTSUP,
7298 RTE_FLOW_ERROR_TYPE_ACTION,
7300 "action not supported");
7301 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7302 return rte_flow_error_set(error, ENOTSUP,
7303 RTE_FLOW_ERROR_TYPE_ACTION,
7304 actions, "too many actions");
7306 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7307 return rte_flow_error_set(error, ENOTSUP,
7308 RTE_FLOW_ERROR_TYPE_ACTION,
7309 NULL, "meter action with policy "
7310 "must be the last action");
7312 case RTE_FLOW_ACTION_TYPE_VOID:
7314 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7315 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7316 ret = flow_dv_validate_action_port_id(dev,
7323 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7326 case RTE_FLOW_ACTION_TYPE_FLAG:
7327 ret = flow_dv_validate_action_flag(dev, action_flags,
7331 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7332 /* Count all modify-header actions as one. */
7333 if (!(action_flags &
7334 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7336 action_flags |= MLX5_FLOW_ACTION_FLAG |
7337 MLX5_FLOW_ACTION_MARK_EXT;
7338 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7339 modify_after_mirror = 1;
7342 action_flags |= MLX5_FLOW_ACTION_FLAG;
7345 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7347 case RTE_FLOW_ACTION_TYPE_MARK:
7348 ret = flow_dv_validate_action_mark(dev, actions,
7353 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7354 /* Count all modify-header actions as one. */
7355 if (!(action_flags &
7356 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7358 action_flags |= MLX5_FLOW_ACTION_MARK |
7359 MLX5_FLOW_ACTION_MARK_EXT;
7360 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7361 modify_after_mirror = 1;
7363 action_flags |= MLX5_FLOW_ACTION_MARK;
7366 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7368 case RTE_FLOW_ACTION_TYPE_SET_META:
7369 ret = flow_dv_validate_action_set_meta(dev, actions,
7374 /* Count all modify-header actions as one action. */
7375 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7377 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7378 modify_after_mirror = 1;
7379 action_flags |= MLX5_FLOW_ACTION_SET_META;
7380 rw_act_num += MLX5_ACT_NUM_SET_META;
7382 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7383 ret = flow_dv_validate_action_set_tag(dev, actions,
7388 /* Count all modify-header actions as one action. */
7389 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7391 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7392 modify_after_mirror = 1;
7393 tag_id = ((const struct rte_flow_action_set_tag *)
7394 actions->conf)->index;
7395 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7396 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7398 case RTE_FLOW_ACTION_TYPE_DROP:
7399 ret = mlx5_flow_validate_action_drop(action_flags,
7403 action_flags |= MLX5_FLOW_ACTION_DROP;
7406 case RTE_FLOW_ACTION_TYPE_QUEUE:
7407 ret = mlx5_flow_validate_action_queue(actions,
7412 queue_index = ((const struct rte_flow_action_queue *)
7413 (actions->conf))->index;
7414 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7417 case RTE_FLOW_ACTION_TYPE_RSS:
7418 rss = actions->conf;
7419 ret = mlx5_flow_validate_action_rss(actions,
7425 if (rss && sample_rss &&
7426 (sample_rss->level != rss->level ||
7427 sample_rss->types != rss->types))
7428 return rte_flow_error_set(error, ENOTSUP,
7429 RTE_FLOW_ERROR_TYPE_ACTION,
7431 "Can't use the different RSS types "
7432 "or level in the same flow");
7433 if (rss != NULL && rss->queue_num)
7434 queue_index = rss->queue[0];
7435 action_flags |= MLX5_FLOW_ACTION_RSS;
7438 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7440 mlx5_flow_validate_action_default_miss(action_flags,
7444 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7447 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7448 shared_count = true;
7450 case RTE_FLOW_ACTION_TYPE_COUNT:
7451 ret = flow_dv_validate_action_count(dev, shared_count,
7456 action_flags |= MLX5_FLOW_ACTION_COUNT;
7459 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7460 if (flow_dv_validate_action_pop_vlan(dev,
7466 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7467 modify_after_mirror = 1;
7468 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7471 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7472 ret = flow_dv_validate_action_push_vlan(dev,
7479 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7480 modify_after_mirror = 1;
7481 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7484 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7485 ret = flow_dv_validate_action_set_vlan_pcp
7486 (action_flags, actions, error);
7489 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7490 modify_after_mirror = 1;
7491 /* Count PCP with push_vlan command. */
7492 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7494 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7495 ret = flow_dv_validate_action_set_vlan_vid
7496 (item_flags, action_flags,
7500 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7501 modify_after_mirror = 1;
7502 /* Count VID with push_vlan command. */
7503 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7504 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7506 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7507 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7508 ret = flow_dv_validate_action_l2_encap(dev,
7514 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7517 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7518 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7519 ret = flow_dv_validate_action_decap(dev, action_flags,
7520 actions, item_flags,
7524 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7525 modify_after_mirror = 1;
7526 action_flags |= MLX5_FLOW_ACTION_DECAP;
7529 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7530 ret = flow_dv_validate_action_raw_encap_decap
7531 (dev, NULL, actions->conf, attr, &action_flags,
7532 &actions_n, actions, item_flags, error);
7536 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7537 decap = actions->conf;
7538 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7540 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7544 encap = actions->conf;
7546 ret = flow_dv_validate_action_raw_encap_decap
7548 decap ? decap : &empty_decap, encap,
7549 attr, &action_flags, &actions_n,
7550 actions, item_flags, error);
7553 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7554 (action_flags & MLX5_FLOW_ACTION_DECAP))
7555 modify_after_mirror = 1;
7557 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7558 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7559 ret = flow_dv_validate_action_modify_mac(action_flags,
7565 /* Count all modify-header actions as one action. */
7566 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7568 action_flags |= actions->type ==
7569 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7570 MLX5_FLOW_ACTION_SET_MAC_SRC :
7571 MLX5_FLOW_ACTION_SET_MAC_DST;
7572 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7573 modify_after_mirror = 1;
7575 * Even if the source and destination MAC addresses have
7576 * overlap in the header with 4B alignment, the convert
7577 * function will handle them separately and 4 SW actions
7578 * will be created. And 2 actions will be added each
7579 * time no matter how many bytes of address will be set.
7581 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7583 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7584 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7585 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7591 /* Count all modify-header actions as one action. */
7592 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7594 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7595 modify_after_mirror = 1;
7596 action_flags |= actions->type ==
7597 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7598 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7599 MLX5_FLOW_ACTION_SET_IPV4_DST;
7600 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7602 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7603 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7604 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7610 if (item_ipv6_proto == IPPROTO_ICMPV6)
7611 return rte_flow_error_set(error, ENOTSUP,
7612 RTE_FLOW_ERROR_TYPE_ACTION,
7614 "Can't change header "
7615 "with ICMPv6 proto");
7616 /* Count all modify-header actions as one action. */
7617 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7619 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7620 modify_after_mirror = 1;
7621 action_flags |= actions->type ==
7622 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7623 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7624 MLX5_FLOW_ACTION_SET_IPV6_DST;
7625 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7627 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7628 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7629 ret = flow_dv_validate_action_modify_tp(action_flags,
7635 /* Count all modify-header actions as one action. */
7636 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7638 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7639 modify_after_mirror = 1;
7640 action_flags |= actions->type ==
7641 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7642 MLX5_FLOW_ACTION_SET_TP_SRC :
7643 MLX5_FLOW_ACTION_SET_TP_DST;
7644 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7646 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7647 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7648 ret = flow_dv_validate_action_modify_ttl(action_flags,
7654 /* Count all modify-header actions as one action. */
7655 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7657 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7658 modify_after_mirror = 1;
7659 action_flags |= actions->type ==
7660 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7661 MLX5_FLOW_ACTION_SET_TTL :
7662 MLX5_FLOW_ACTION_DEC_TTL;
7663 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7665 case RTE_FLOW_ACTION_TYPE_JUMP:
7666 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7672 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7674 return rte_flow_error_set(error, EINVAL,
7675 RTE_FLOW_ERROR_TYPE_ACTION,
7677 "sample and jump action combination is not supported");
7679 action_flags |= MLX5_FLOW_ACTION_JUMP;
7681 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7682 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7683 ret = flow_dv_validate_action_modify_tcp_seq
7690 /* Count all modify-header actions as one action. */
7691 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7693 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7694 modify_after_mirror = 1;
7695 action_flags |= actions->type ==
7696 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7697 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7698 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7699 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7701 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7702 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7703 ret = flow_dv_validate_action_modify_tcp_ack
7710 /* Count all modify-header actions as one action. */
7711 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7713 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7714 modify_after_mirror = 1;
7715 action_flags |= actions->type ==
7716 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7717 MLX5_FLOW_ACTION_INC_TCP_ACK :
7718 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7719 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7721 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7723 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7724 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7725 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7727 case RTE_FLOW_ACTION_TYPE_METER:
7728 ret = mlx5_flow_validate_action_meter(dev,
7737 action_flags |= MLX5_FLOW_ACTION_METER;
7740 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7742 /* Meter action will add one more TAG action. */
7743 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7745 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7746 if (!attr->transfer && !attr->group)
7747 return rte_flow_error_set(error, ENOTSUP,
7748 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7750 "Shared ASO age action is not supported for group 0");
7751 if (action_flags & MLX5_FLOW_ACTION_AGE)
7752 return rte_flow_error_set
7754 RTE_FLOW_ERROR_TYPE_ACTION,
7756 "duplicate age actions set");
7757 action_flags |= MLX5_FLOW_ACTION_AGE;
7760 case RTE_FLOW_ACTION_TYPE_AGE:
7761 ret = flow_dv_validate_action_age(action_flags,
7767 * Validate the regular AGE action (using counter)
7768 * mutual exclusion with indirect counter actions.
7770 if (!flow_hit_aso_supported(priv->sh, attr)) {
7772 return rte_flow_error_set
7774 RTE_FLOW_ERROR_TYPE_ACTION,
7776 "old age and indirect count combination is not supported");
7778 return rte_flow_error_set
7780 RTE_FLOW_ERROR_TYPE_ACTION,
7782 "old age action and count must be in the same sub flow");
7784 action_flags |= MLX5_FLOW_ACTION_AGE;
7787 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7788 ret = flow_dv_validate_action_modify_ipv4_dscp
7795 /* Count all modify-header actions as one action. */
7796 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7798 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7799 modify_after_mirror = 1;
7800 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7801 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7803 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7804 ret = flow_dv_validate_action_modify_ipv6_dscp
7811 /* Count all modify-header actions as one action. */
7812 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7814 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7815 modify_after_mirror = 1;
7816 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7817 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7819 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7820 ret = flow_dv_validate_action_sample(&action_flags,
7829 if ((action_flags & MLX5_FLOW_ACTION_SET_TAG) &&
7830 tag_id == 0 && priv->mtr_color_reg == REG_NON)
7831 return rte_flow_error_set(error, EINVAL,
7832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7833 "sample after tag action causes metadata tag index 0 corruption");
7834 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7837 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7838 ret = flow_dv_validate_action_modify_field(dev,
7845 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7846 modify_after_mirror = 1;
7847 /* Count all modify-header actions as one action. */
7848 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7850 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7853 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7854 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7859 action_flags |= MLX5_FLOW_ACTION_CT;
7861 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7862 /* tunnel offload action was processed before
7863 * list it here as a supported type
7867 return rte_flow_error_set(error, ENOTSUP,
7868 RTE_FLOW_ERROR_TYPE_ACTION,
7870 "action not supported");
7874 * Validate actions in flow rules
7875 * - Explicit decap action is prohibited by the tunnel offload API.
7876 * - Drop action in tunnel steer rule is prohibited by the API.
7877 * - Application cannot use MARK action because it's value can mask
7878 * tunnel default miss notification.
7879 * - JUMP in tunnel match rule has no support in current PMD
7881 * - TAG & META are reserved for future uses.
7883 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7884 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7885 MLX5_FLOW_ACTION_MARK |
7886 MLX5_FLOW_ACTION_SET_TAG |
7887 MLX5_FLOW_ACTION_SET_META |
7888 MLX5_FLOW_ACTION_DROP;
7890 if (action_flags & bad_actions_mask)
7891 return rte_flow_error_set
7893 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7894 "Invalid RTE action in tunnel "
7896 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7897 return rte_flow_error_set
7899 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7900 "tunnel set decap rule must terminate "
7903 return rte_flow_error_set
7905 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7906 "tunnel flows for ingress traffic only");
7908 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7909 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7910 MLX5_FLOW_ACTION_MARK |
7911 MLX5_FLOW_ACTION_SET_TAG |
7912 MLX5_FLOW_ACTION_SET_META;
7914 if (action_flags & bad_actions_mask)
7915 return rte_flow_error_set
7917 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7918 "Invalid RTE action in tunnel "
7922 * Validate the drop action mutual exclusion with other actions.
7923 * Drop action is mutually-exclusive with any other action, except for
7925 * Drop action compatibility with tunnel offload was already validated.
7927 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7928 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7929 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7930 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7931 return rte_flow_error_set(error, EINVAL,
7932 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7933 "Drop action is mutually-exclusive "
7934 "with any other action, except for "
7936 /* Eswitch has few restrictions on using items and actions */
7937 if (attr->transfer) {
7938 if (!mlx5_flow_ext_mreg_supported(dev) &&
7939 action_flags & MLX5_FLOW_ACTION_FLAG)
7940 return rte_flow_error_set(error, ENOTSUP,
7941 RTE_FLOW_ERROR_TYPE_ACTION,
7943 "unsupported action FLAG");
7944 if (!mlx5_flow_ext_mreg_supported(dev) &&
7945 action_flags & MLX5_FLOW_ACTION_MARK)
7946 return rte_flow_error_set(error, ENOTSUP,
7947 RTE_FLOW_ERROR_TYPE_ACTION,
7949 "unsupported action MARK");
7950 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7951 return rte_flow_error_set(error, ENOTSUP,
7952 RTE_FLOW_ERROR_TYPE_ACTION,
7954 "unsupported action QUEUE");
7955 if (action_flags & MLX5_FLOW_ACTION_RSS)
7956 return rte_flow_error_set(error, ENOTSUP,
7957 RTE_FLOW_ERROR_TYPE_ACTION,
7959 "unsupported action RSS");
7960 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7961 return rte_flow_error_set(error, EINVAL,
7962 RTE_FLOW_ERROR_TYPE_ACTION,
7964 "no fate action is found");
7966 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7967 return rte_flow_error_set(error, EINVAL,
7968 RTE_FLOW_ERROR_TYPE_ACTION,
7970 "no fate action is found");
7973 * Continue validation for Xcap and VLAN actions.
7974 * If hairpin is working in explicit TX rule mode, there is no actions
7975 * splitting and the validation of hairpin ingress flow should be the
7976 * same as other standard flows.
7978 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7979 MLX5_FLOW_VLAN_ACTIONS)) &&
7980 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index) ||
7981 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7982 conf->tx_explicit != 0))) {
7983 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7984 MLX5_FLOW_XCAP_ACTIONS)
7985 return rte_flow_error_set(error, ENOTSUP,
7986 RTE_FLOW_ERROR_TYPE_ACTION,
7987 NULL, "encap and decap "
7988 "combination aren't supported");
7989 /* Push VLAN is not supported in ingress except for NICs newer than CX5. */
7990 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
7991 struct mlx5_dev_ctx_shared *sh = priv->sh;
7992 bool direction_error = false;
7994 if (attr->transfer) {
7995 bool fdb_tx = priv->representor_id != UINT16_MAX;
7996 bool is_cx5 = sh->steering_format_version ==
7997 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
7999 if (!fdb_tx && is_cx5)
8000 direction_error = true;
8001 } else if (attr->ingress) {
8002 direction_error = true;
8004 if (direction_error)
8005 return rte_flow_error_set(error, ENOTSUP,
8006 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
8008 "push VLAN action not supported "
8011 if (!attr->transfer && attr->ingress) {
8012 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8013 return rte_flow_error_set
8015 RTE_FLOW_ERROR_TYPE_ACTION,
8016 NULL, "encap is not supported"
8017 " for ingress traffic");
8018 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
8019 MLX5_FLOW_VLAN_ACTIONS)
8020 return rte_flow_error_set
8022 RTE_FLOW_ERROR_TYPE_ACTION,
8023 NULL, "no support for "
8024 "multiple VLAN actions");
8027 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
8028 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
8029 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
8031 return rte_flow_error_set
8033 RTE_FLOW_ERROR_TYPE_ACTION,
8034 NULL, "fate action not supported for "
8035 "meter with policy");
8037 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
8038 return rte_flow_error_set
8040 RTE_FLOW_ERROR_TYPE_ACTION,
8041 NULL, "modify header action in egress "
8042 "cannot be done before meter action");
8043 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8044 return rte_flow_error_set
8046 RTE_FLOW_ERROR_TYPE_ACTION,
8047 NULL, "encap action in egress "
8048 "cannot be done before meter action");
8049 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8050 return rte_flow_error_set
8052 RTE_FLOW_ERROR_TYPE_ACTION,
8053 NULL, "push vlan action in egress "
8054 "cannot be done before meter action");
8058 * Hairpin flow will add one more TAG action in TX implicit mode.
8059 * In TX explicit mode, there will be no hairpin flow ID.
8062 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8063 /* extra metadata enabled: one more TAG action will be add. */
8064 if (dev_conf->dv_flow_en &&
8065 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8066 mlx5_flow_ext_mreg_supported(dev))
8067 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8069 flow_dv_modify_hdr_action_max(dev, is_root)) {
8070 return rte_flow_error_set(error, ENOTSUP,
8071 RTE_FLOW_ERROR_TYPE_ACTION,
8072 NULL, "too many header modify"
8073 " actions to support");
8075 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8076 if (fdb_mirror_limit && modify_after_mirror)
8077 return rte_flow_error_set(error, EINVAL,
8078 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8079 "sample before modify action is not supported");
8081 * Validation the NIC Egress flow on representor, except implicit
8082 * hairpin default egress flow with TX_QUEUE item, other flows not
8083 * work due to metadata regC0 mismatch.
8085 if ((!attr->transfer && attr->egress) && priv->representor &&
8086 !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))
8087 return rte_flow_error_set(error, EINVAL,
8088 RTE_FLOW_ERROR_TYPE_ITEM,
8090 "NIC egress rules on representors"
8091 " is not supported");
8096 * Internal preparation function. Allocates the DV flow size,
8097 * this size is constant.
8100 * Pointer to the rte_eth_dev structure.
8102 * Pointer to the flow attributes.
8104 * Pointer to the list of items.
8105 * @param[in] actions
8106 * Pointer to the list of actions.
8108 * Pointer to the error structure.
8111 * Pointer to mlx5_flow object on success,
8112 * otherwise NULL and rte_errno is set.
8114 static struct mlx5_flow *
8115 flow_dv_prepare(struct rte_eth_dev *dev,
8116 const struct rte_flow_attr *attr __rte_unused,
8117 const struct rte_flow_item items[] __rte_unused,
8118 const struct rte_flow_action actions[] __rte_unused,
8119 struct rte_flow_error *error)
8121 uint32_t handle_idx = 0;
8122 struct mlx5_flow *dev_flow;
8123 struct mlx5_flow_handle *dev_handle;
8124 struct mlx5_priv *priv = dev->data->dev_private;
8125 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8128 wks->skip_matcher_reg = 0;
8130 wks->final_policy = NULL;
8131 /* In case of corrupting the memory. */
8132 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8133 rte_flow_error_set(error, ENOSPC,
8134 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8135 "not free temporary device flow");
8138 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8141 rte_flow_error_set(error, ENOMEM,
8142 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8143 "not enough memory to create flow handle");
8146 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8147 dev_flow = &wks->flows[wks->flow_idx++];
8148 memset(dev_flow, 0, sizeof(*dev_flow));
8149 dev_flow->handle = dev_handle;
8150 dev_flow->handle_idx = handle_idx;
8151 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8152 dev_flow->ingress = attr->ingress;
8153 dev_flow->dv.transfer = attr->transfer;
8157 #ifdef RTE_LIBRTE_MLX5_DEBUG
8159 * Sanity check for match mask and value. Similar to check_valid_spec() in
8160 * kernel driver. If unmasked bit is present in value, it returns failure.
8163 * pointer to match mask buffer.
8164 * @param match_value
8165 * pointer to match value buffer.
8168 * 0 if valid, -EINVAL otherwise.
8171 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8173 uint8_t *m = match_mask;
8174 uint8_t *v = match_value;
8177 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8180 "match_value differs from match_criteria"
8181 " %p[%u] != %p[%u]",
8182 match_value, i, match_mask, i);
8191 * Add match of ip_version.
8195 * @param[in] headers_v
8196 * Values header pointer.
8197 * @param[in] headers_m
8198 * Masks header pointer.
8199 * @param[in] ip_version
8200 * The IP version to set.
8203 flow_dv_set_match_ip_version(uint32_t group,
8209 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8211 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8214 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8215 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8219 * Add Ethernet item to matcher and to the value.
8221 * @param[in, out] matcher
8223 * @param[in, out] key
8224 * Flow matcher value.
8226 * Flow pattern to translate.
8228 * Item is inner pattern.
8231 flow_dv_translate_item_eth(void *matcher, void *key,
8232 const struct rte_flow_item *item, int inner,
8235 const struct rte_flow_item_eth *eth_m = item->mask;
8236 const struct rte_flow_item_eth *eth_v = item->spec;
8237 const struct rte_flow_item_eth nic_mask = {
8238 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8239 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8240 .type = RTE_BE16(0xffff),
8253 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8255 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8257 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8259 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8261 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8262 ð_m->dst, sizeof(eth_m->dst));
8263 /* The value must be in the range of the mask. */
8264 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8265 for (i = 0; i < sizeof(eth_m->dst); ++i)
8266 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8267 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8268 ð_m->src, sizeof(eth_m->src));
8269 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8270 /* The value must be in the range of the mask. */
8271 for (i = 0; i < sizeof(eth_m->dst); ++i)
8272 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8274 * HW supports match on one Ethertype, the Ethertype following the last
8275 * VLAN tag of the packet (see PRM).
8276 * Set match on ethertype only if ETH header is not followed by VLAN.
8277 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8278 * ethertype, and use ip_version field instead.
8279 * eCPRI over Ether layer will use type value 0xAEFE.
8281 if (eth_m->type == 0xFFFF) {
8282 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8283 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8284 switch (eth_v->type) {
8285 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8286 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8288 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8289 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8290 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8292 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8293 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8295 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8296 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8302 if (eth_m->has_vlan) {
8303 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8304 if (eth_v->has_vlan) {
8306 * Here, when also has_more_vlan field in VLAN item is
8307 * not set, only single-tagged packets will be matched.
8309 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8313 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8314 rte_be_to_cpu_16(eth_m->type));
8315 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8316 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8320 * Add VLAN item to matcher and to the value.
8322 * @param[in, out] dev_flow
8324 * @param[in, out] matcher
8326 * @param[in, out] key
8327 * Flow matcher value.
8329 * Flow pattern to translate.
8331 * Item is inner pattern.
8334 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8335 void *matcher, void *key,
8336 const struct rte_flow_item *item,
8337 int inner, uint32_t group)
8339 const struct rte_flow_item_vlan *vlan_m = item->mask;
8340 const struct rte_flow_item_vlan *vlan_v = item->spec;
8347 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8349 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8351 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8353 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8355 * This is workaround, masks are not supported,
8356 * and pre-validated.
8359 dev_flow->handle->vf_vlan.tag =
8360 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8363 * When VLAN item exists in flow, mark packet as tagged,
8364 * even if TCI is not specified.
8366 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8367 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8368 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8373 vlan_m = &rte_flow_item_vlan_mask;
8374 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8375 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8376 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8377 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8378 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8379 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8380 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8381 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8383 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8384 * ethertype, and use ip_version field instead.
8386 if (vlan_m->inner_type == 0xFFFF) {
8387 switch (vlan_v->inner_type) {
8388 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8389 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8390 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8391 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8393 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8394 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8396 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8397 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8403 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8404 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8405 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8406 /* Only one vlan_tag bit can be set. */
8407 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8410 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8411 rte_be_to_cpu_16(vlan_m->inner_type));
8412 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8413 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8417 * Add IPV4 item to matcher and to the value.
8419 * @param[in, out] matcher
8421 * @param[in, out] key
8422 * Flow matcher value.
8424 * Flow pattern to translate.
8426 * Item is inner pattern.
8428 * The group to insert the rule.
8431 flow_dv_translate_item_ipv4(void *matcher, void *key,
8432 const struct rte_flow_item *item,
8433 int inner, uint32_t group)
8435 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8436 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8437 const struct rte_flow_item_ipv4 nic_mask = {
8439 .src_addr = RTE_BE32(0xffffffff),
8440 .dst_addr = RTE_BE32(0xffffffff),
8441 .type_of_service = 0xff,
8442 .next_proto_id = 0xff,
8443 .time_to_live = 0xff,
8450 uint8_t tos, ihl_m, ihl_v;
8453 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8455 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8457 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8459 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8461 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8466 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8467 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8468 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8469 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8470 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8471 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8472 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8473 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8474 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8475 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8476 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8477 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8478 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8479 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8480 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8481 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8482 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8483 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8484 ipv4_m->hdr.type_of_service);
8485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8486 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8487 ipv4_m->hdr.type_of_service >> 2);
8488 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8489 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8490 ipv4_m->hdr.next_proto_id);
8491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8492 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8494 ipv4_m->hdr.time_to_live);
8495 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8496 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8498 !!(ipv4_m->hdr.fragment_offset));
8499 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8500 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8504 * Add IPV6 item to matcher and to the value.
8506 * @param[in, out] matcher
8508 * @param[in, out] key
8509 * Flow matcher value.
8511 * Flow pattern to translate.
8513 * Item is inner pattern.
8515 * The group to insert the rule.
8518 flow_dv_translate_item_ipv6(void *matcher, void *key,
8519 const struct rte_flow_item *item,
8520 int inner, uint32_t group)
8522 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8523 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8524 const struct rte_flow_item_ipv6 nic_mask = {
8527 "\xff\xff\xff\xff\xff\xff\xff\xff"
8528 "\xff\xff\xff\xff\xff\xff\xff\xff",
8530 "\xff\xff\xff\xff\xff\xff\xff\xff"
8531 "\xff\xff\xff\xff\xff\xff\xff\xff",
8532 .vtc_flow = RTE_BE32(0xffffffff),
8539 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8540 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8549 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8551 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8553 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8555 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8557 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8562 size = sizeof(ipv6_m->hdr.dst_addr);
8563 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8564 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8565 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8566 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8567 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8568 for (i = 0; i < size; ++i)
8569 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8570 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8571 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8572 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8573 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8574 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8575 for (i = 0; i < size; ++i)
8576 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8578 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8579 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8580 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8581 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8582 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8583 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8586 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8588 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8591 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8593 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8597 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8599 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8600 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8602 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8603 ipv6_m->hdr.hop_limits);
8604 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8605 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8606 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8607 !!(ipv6_m->has_frag_ext));
8608 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8609 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8613 * Add IPV6 fragment extension item to matcher and to the value.
8615 * @param[in, out] matcher
8617 * @param[in, out] key
8618 * Flow matcher value.
8620 * Flow pattern to translate.
8622 * Item is inner pattern.
8625 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8626 const struct rte_flow_item *item,
8629 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8630 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8631 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8633 .next_header = 0xff,
8634 .frag_data = RTE_BE16(0xffff),
8641 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8643 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8645 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8647 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8649 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8652 if (!ipv6_frag_ext_v)
8654 if (!ipv6_frag_ext_m)
8655 ipv6_frag_ext_m = &nic_mask;
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8657 ipv6_frag_ext_m->hdr.next_header);
8658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8659 ipv6_frag_ext_v->hdr.next_header &
8660 ipv6_frag_ext_m->hdr.next_header);
8664 * Add TCP item to matcher and to the value.
8666 * @param[in, out] matcher
8668 * @param[in, out] key
8669 * Flow matcher value.
8671 * Flow pattern to translate.
8673 * Item is inner pattern.
8676 flow_dv_translate_item_tcp(void *matcher, void *key,
8677 const struct rte_flow_item *item,
8680 const struct rte_flow_item_tcp *tcp_m = item->mask;
8681 const struct rte_flow_item_tcp *tcp_v = item->spec;
8686 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8688 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8690 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8692 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8699 tcp_m = &rte_flow_item_tcp_mask;
8700 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8701 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8703 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8704 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8705 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8706 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8707 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8708 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8709 tcp_m->hdr.tcp_flags);
8710 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8711 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8715 * Add UDP item to matcher and to the value.
8717 * @param[in, out] matcher
8719 * @param[in, out] key
8720 * Flow matcher value.
8722 * Flow pattern to translate.
8724 * Item is inner pattern.
8727 flow_dv_translate_item_udp(void *matcher, void *key,
8728 const struct rte_flow_item *item,
8731 const struct rte_flow_item_udp *udp_m = item->mask;
8732 const struct rte_flow_item_udp *udp_v = item->spec;
8737 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8739 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8741 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8743 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8745 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8750 udp_m = &rte_flow_item_udp_mask;
8751 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8752 rte_be_to_cpu_16(udp_m->hdr.src_port));
8753 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8754 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8755 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8756 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8757 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8758 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8762 * Add GRE optional Key item to matcher and to the value.
8764 * @param[in, out] matcher
8766 * @param[in, out] key
8767 * Flow matcher value.
8769 * Flow pattern to translate.
8771 * Item is inner pattern.
8774 flow_dv_translate_item_gre_key(void *matcher, void *key,
8775 const struct rte_flow_item *item)
8777 const rte_be32_t *key_m = item->mask;
8778 const rte_be32_t *key_v = item->spec;
8779 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8780 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8781 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8783 /* GRE K bit must be on and should already be validated */
8784 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8785 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8789 key_m = &gre_key_default_mask;
8790 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8791 rte_be_to_cpu_32(*key_m) >> 8);
8792 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8793 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8794 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8795 rte_be_to_cpu_32(*key_m) & 0xFF);
8796 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8797 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8801 * Add GRE item to matcher and to the value.
8803 * @param[in, out] matcher
8805 * @param[in, out] key
8806 * Flow matcher value.
8808 * Flow pattern to translate.
8809 * @param[in] pattern_flags
8810 * Accumulated pattern flags.
8813 flow_dv_translate_item_gre(void *matcher, void *key,
8814 const struct rte_flow_item *item,
8815 uint64_t pattern_flags)
8817 static const struct rte_flow_item_gre empty_gre = {0,};
8818 const struct rte_flow_item_gre *gre_m = item->mask;
8819 const struct rte_flow_item_gre *gre_v = item->spec;
8820 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8821 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8822 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8823 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8830 uint16_t s_present:1;
8831 uint16_t k_present:1;
8832 uint16_t rsvd_bit1:1;
8833 uint16_t c_present:1;
8837 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8838 uint16_t protocol_m, protocol_v;
8840 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8841 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8847 gre_m = &rte_flow_item_gre_mask;
8849 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8850 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8851 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8852 gre_crks_rsvd0_ver_m.c_present);
8853 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8854 gre_crks_rsvd0_ver_v.c_present &
8855 gre_crks_rsvd0_ver_m.c_present);
8856 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8857 gre_crks_rsvd0_ver_m.k_present);
8858 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8859 gre_crks_rsvd0_ver_v.k_present &
8860 gre_crks_rsvd0_ver_m.k_present);
8861 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8862 gre_crks_rsvd0_ver_m.s_present);
8863 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8864 gre_crks_rsvd0_ver_v.s_present &
8865 gre_crks_rsvd0_ver_m.s_present);
8866 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8867 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8869 /* Force next protocol to prevent matchers duplication */
8870 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8872 protocol_m = 0xFFFF;
8874 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8875 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8876 protocol_m & protocol_v);
8880 * Add GRE optional items to matcher and to the value.
8882 * @param[in, out] matcher
8884 * @param[in, out] key
8885 * Flow matcher value.
8887 * Flow pattern to translate.
8888 * @param[in] gre_item
8889 * Pointer to gre_item.
8890 * @param[in] pattern_flags
8891 * Accumulated pattern flags.
8894 flow_dv_translate_item_gre_option(void *matcher, void *key,
8895 const struct rte_flow_item *item,
8896 const struct rte_flow_item *gre_item,
8897 uint64_t pattern_flags)
8899 const struct rte_flow_item_gre_opt *option_m = item->mask;
8900 const struct rte_flow_item_gre_opt *option_v = item->spec;
8901 const struct rte_flow_item_gre *gre_m = gre_item->mask;
8902 const struct rte_flow_item_gre *gre_v = gre_item->spec;
8903 static const struct rte_flow_item_gre empty_gre = {0};
8904 struct rte_flow_item gre_key_item;
8905 uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
8906 uint16_t protocol_m, protocol_v;
8911 * If only match key field, keep using misc for matching.
8912 * If need to match checksum or sequence, using misc5 and do
8913 * not need using misc.
8915 if (!(option_m->sequence.sequence ||
8916 option_m->checksum_rsvd.checksum)) {
8917 flow_dv_translate_item_gre(matcher, key, gre_item,
8919 gre_key_item.spec = &option_v->key.key;
8920 gre_key_item.mask = &option_m->key.key;
8921 flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
8929 gre_m = &rte_flow_item_gre_mask;
8931 protocol_v = gre_v->protocol;
8932 protocol_m = gre_m->protocol;
8934 /* Force next protocol to prevent matchers duplication */
8935 uint16_t ether_type =
8936 mlx5_translate_tunnel_etypes(pattern_flags);
8938 protocol_v = rte_be_to_cpu_16(ether_type);
8939 protocol_m = UINT16_MAX;
8942 c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
8943 c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
8944 if (option_m->sequence.sequence) {
8945 c_rsvd0_ver_v |= RTE_BE16(0x1000);
8946 c_rsvd0_ver_m |= RTE_BE16(0x1000);
8948 if (option_m->key.key) {
8949 c_rsvd0_ver_v |= RTE_BE16(0x2000);
8950 c_rsvd0_ver_m |= RTE_BE16(0x2000);
8952 if (option_m->checksum_rsvd.checksum) {
8953 c_rsvd0_ver_v |= RTE_BE16(0x8000);
8954 c_rsvd0_ver_m |= RTE_BE16(0x8000);
8957 * Hardware parses GRE optional field into the fixed location,
8958 * do not need to adjust the tunnel dword indices.
8960 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8961 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8962 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
8963 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
8964 (c_rsvd0_ver_m | protocol_m << 16)));
8965 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
8966 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
8967 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
8968 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
8969 option_m->checksum_rsvd.checksum));
8970 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
8971 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
8972 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
8973 rte_be_to_cpu_32(option_v->key.key & option_m->key.key));
8974 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
8975 rte_be_to_cpu_32(option_m->key.key));
8976 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
8977 rte_be_to_cpu_32(option_v->sequence.sequence &
8978 option_m->sequence.sequence));
8979 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
8980 rte_be_to_cpu_32(option_m->sequence.sequence));
8984 * Add NVGRE item to matcher and to the value.
8986 * @param[in, out] matcher
8988 * @param[in, out] key
8989 * Flow matcher value.
8991 * Flow pattern to translate.
8992 * @param[in] pattern_flags
8993 * Accumulated pattern flags.
8996 flow_dv_translate_item_nvgre(void *matcher, void *key,
8997 const struct rte_flow_item *item,
8998 unsigned long pattern_flags)
9000 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
9001 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
9002 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9003 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9004 const char *tni_flow_id_m;
9005 const char *tni_flow_id_v;
9011 /* For NVGRE, GRE header fields must be set with defined values. */
9012 const struct rte_flow_item_gre gre_spec = {
9013 .c_rsvd0_ver = RTE_BE16(0x2000),
9014 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
9016 const struct rte_flow_item_gre gre_mask = {
9017 .c_rsvd0_ver = RTE_BE16(0xB000),
9018 .protocol = RTE_BE16(UINT16_MAX),
9020 const struct rte_flow_item gre_item = {
9025 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
9029 nvgre_m = &rte_flow_item_nvgre_mask;
9030 tni_flow_id_m = (const char *)nvgre_m->tni;
9031 tni_flow_id_v = (const char *)nvgre_v->tni;
9032 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
9033 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
9034 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
9035 memcpy(gre_key_m, tni_flow_id_m, size);
9036 for (i = 0; i < size; ++i)
9037 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
9041 * Add VXLAN item to matcher and to the value.
9044 * Pointer to the Ethernet device structure.
9046 * Flow rule attributes.
9047 * @param[in, out] matcher
9049 * @param[in, out] key
9050 * Flow matcher value.
9052 * Flow pattern to translate.
9054 * Item is inner pattern.
9057 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
9058 const struct rte_flow_attr *attr,
9059 void *matcher, void *key,
9060 const struct rte_flow_item *item,
9063 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
9064 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
9069 uint32_t *tunnel_header_v;
9070 uint32_t *tunnel_header_m;
9072 struct mlx5_priv *priv = dev->data->dev_private;
9073 const struct rte_flow_item_vxlan nic_mask = {
9074 .vni = "\xff\xff\xff",
9079 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9081 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9083 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9085 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9087 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
9088 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
9089 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9090 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9091 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9093 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
9097 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
9098 (attr->group && !priv->sh->misc5_cap))
9099 vxlan_m = &rte_flow_item_vxlan_mask;
9101 vxlan_m = &nic_mask;
9103 if ((priv->sh->steering_format_version ==
9104 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
9105 dport != MLX5_UDP_PORT_VXLAN) ||
9106 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
9107 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
9114 misc_m = MLX5_ADDR_OF(fte_match_param,
9115 matcher, misc_parameters);
9116 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9117 size = sizeof(vxlan_m->vni);
9118 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
9119 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
9120 memcpy(vni_m, vxlan_m->vni, size);
9121 for (i = 0; i < size; ++i)
9122 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9125 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
9126 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
9127 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9130 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9133 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
9134 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
9135 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
9136 if (*tunnel_header_v)
9137 *tunnel_header_m = vxlan_m->vni[0] |
9138 vxlan_m->vni[1] << 8 |
9139 vxlan_m->vni[2] << 16;
9141 *tunnel_header_m = 0x0;
9142 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
9143 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
9144 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
9148 * Add VXLAN-GPE item to matcher and to the value.
9150 * @param[in, out] matcher
9152 * @param[in, out] key
9153 * Flow matcher value.
9155 * Flow pattern to translate.
9157 * Item is inner pattern.
9161 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9162 const struct rte_flow_item *item,
9163 const uint64_t pattern_flags)
9165 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9166 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9167 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9168 /* The item was validated to be on the outer side */
9169 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9170 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9172 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9174 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9176 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9178 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9179 int i, size = sizeof(vxlan_m->vni);
9180 uint8_t flags_m = 0xff;
9181 uint8_t flags_v = 0xc;
9182 uint8_t m_protocol, v_protocol;
9184 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9185 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9186 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9187 MLX5_UDP_PORT_VXLAN_GPE);
9190 vxlan_v = &dummy_vxlan_gpe_hdr;
9191 vxlan_m = &dummy_vxlan_gpe_hdr;
9194 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9196 memcpy(vni_m, vxlan_m->vni, size);
9197 for (i = 0; i < size; ++i)
9198 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9199 if (vxlan_m->flags) {
9200 flags_m = vxlan_m->flags;
9201 flags_v = vxlan_v->flags;
9203 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9204 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9205 m_protocol = vxlan_m->protocol;
9206 v_protocol = vxlan_v->protocol;
9208 /* Force next protocol to ensure next headers parsing. */
9209 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9210 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9211 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9212 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9213 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9214 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9218 MLX5_SET(fte_match_set_misc3, misc_m,
9219 outer_vxlan_gpe_next_protocol, m_protocol);
9220 MLX5_SET(fte_match_set_misc3, misc_v,
9221 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9225 * Add Geneve item to matcher and to the value.
9227 * @param[in, out] matcher
9229 * @param[in, out] key
9230 * Flow matcher value.
9232 * Flow pattern to translate.
9234 * Item is inner pattern.
9238 flow_dv_translate_item_geneve(void *matcher, void *key,
9239 const struct rte_flow_item *item,
9240 uint64_t pattern_flags)
9242 static const struct rte_flow_item_geneve empty_geneve = {0,};
9243 const struct rte_flow_item_geneve *geneve_m = item->mask;
9244 const struct rte_flow_item_geneve *geneve_v = item->spec;
9245 /* GENEVE flow item validation allows single tunnel item */
9246 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9247 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9248 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9249 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9252 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9253 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9254 size_t size = sizeof(geneve_m->vni), i;
9255 uint16_t protocol_m, protocol_v;
9257 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9258 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9259 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9260 MLX5_UDP_PORT_GENEVE);
9263 geneve_v = &empty_geneve;
9264 geneve_m = &empty_geneve;
9267 geneve_m = &rte_flow_item_geneve_mask;
9269 memcpy(vni_m, geneve_m->vni, size);
9270 for (i = 0; i < size; ++i)
9271 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9272 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9273 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9274 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9275 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9276 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9277 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9278 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9279 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9280 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9281 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9282 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9283 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9284 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9286 /* Force next protocol to prevent matchers duplication */
9287 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9289 protocol_m = 0xFFFF;
9291 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9292 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9293 protocol_m & protocol_v);
9297 * Create Geneve TLV option resource.
9299 * @param dev[in, out]
9300 * Pointer to rte_eth_dev structure.
9301 * @param[in, out] tag_be24
9302 * Tag value in big endian then R-shift 8.
9303 * @parm[in, out] dev_flow
9304 * Pointer to the dev_flow.
9306 * pointer to error structure.
9309 * 0 on success otherwise -errno and errno is set.
9313 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9314 const struct rte_flow_item *item,
9315 struct rte_flow_error *error)
9317 struct mlx5_priv *priv = dev->data->dev_private;
9318 struct mlx5_dev_ctx_shared *sh = priv->sh;
9319 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9320 sh->geneve_tlv_option_resource;
9321 struct mlx5_devx_obj *obj;
9322 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9327 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9328 if (geneve_opt_resource != NULL) {
9329 if (geneve_opt_resource->option_class ==
9330 geneve_opt_v->option_class &&
9331 geneve_opt_resource->option_type ==
9332 geneve_opt_v->option_type &&
9333 geneve_opt_resource->length ==
9334 geneve_opt_v->option_len) {
9335 /* We already have GENEVE TLV option obj allocated. */
9336 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9339 ret = rte_flow_error_set(error, ENOMEM,
9340 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9341 "Only one GENEVE TLV option supported");
9345 /* Create a GENEVE TLV object and resource. */
9346 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9347 geneve_opt_v->option_class,
9348 geneve_opt_v->option_type,
9349 geneve_opt_v->option_len);
9351 ret = rte_flow_error_set(error, ENODATA,
9352 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9353 "Failed to create GENEVE TLV Devx object");
9356 sh->geneve_tlv_option_resource =
9357 mlx5_malloc(MLX5_MEM_ZERO,
9358 sizeof(*geneve_opt_resource),
9360 if (!sh->geneve_tlv_option_resource) {
9361 claim_zero(mlx5_devx_cmd_destroy(obj));
9362 ret = rte_flow_error_set(error, ENOMEM,
9363 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9364 "GENEVE TLV object memory allocation failed");
9367 geneve_opt_resource = sh->geneve_tlv_option_resource;
9368 geneve_opt_resource->obj = obj;
9369 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9370 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9371 geneve_opt_resource->length = geneve_opt_v->option_len;
9372 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9376 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9381 * Add Geneve TLV option item to matcher.
9383 * @param[in, out] dev
9384 * Pointer to rte_eth_dev structure.
9385 * @param[in, out] matcher
9387 * @param[in, out] key
9388 * Flow matcher value.
9390 * Flow pattern to translate.
9392 * Pointer to error structure.
9395 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9396 void *key, const struct rte_flow_item *item,
9397 struct rte_flow_error *error)
9399 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9400 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9401 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9402 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9403 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9405 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9406 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9412 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9413 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9416 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9420 * Set the option length in GENEVE header if not requested.
9421 * The GENEVE TLV option length is expressed by the option length field
9422 * in the GENEVE header.
9423 * If the option length was not requested but the GENEVE TLV option item
9424 * is present we set the option length field implicitly.
9426 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9427 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9428 MLX5_GENEVE_OPTLEN_MASK);
9429 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9430 geneve_opt_v->option_len + 1);
9432 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9433 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9435 if (geneve_opt_v->data) {
9436 memcpy(&opt_data_key, geneve_opt_v->data,
9437 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9438 sizeof(opt_data_key)));
9439 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9440 sizeof(opt_data_key));
9441 memcpy(&opt_data_mask, geneve_opt_m->data,
9442 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9443 sizeof(opt_data_mask)));
9444 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9445 sizeof(opt_data_mask));
9446 MLX5_SET(fte_match_set_misc3, misc3_m,
9447 geneve_tlv_option_0_data,
9448 rte_be_to_cpu_32(opt_data_mask));
9449 MLX5_SET(fte_match_set_misc3, misc3_v,
9450 geneve_tlv_option_0_data,
9451 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9457 * Add MPLS item to matcher and to the value.
9459 * @param[in, out] matcher
9461 * @param[in, out] key
9462 * Flow matcher value.
9464 * Flow pattern to translate.
9465 * @param[in] prev_layer
9466 * The protocol layer indicated in previous item.
9468 * Item is inner pattern.
9471 flow_dv_translate_item_mpls(void *matcher, void *key,
9472 const struct rte_flow_item *item,
9473 uint64_t prev_layer,
9476 const uint32_t *in_mpls_m = item->mask;
9477 const uint32_t *in_mpls_v = item->spec;
9478 uint32_t *out_mpls_m = 0;
9479 uint32_t *out_mpls_v = 0;
9480 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9481 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9482 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9484 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9485 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9486 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9488 switch (prev_layer) {
9489 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9490 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9491 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9494 MLX5_UDP_PORT_MPLS);
9497 case MLX5_FLOW_LAYER_GRE:
9499 case MLX5_FLOW_LAYER_GRE_KEY:
9500 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9501 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9503 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9504 RTE_ETHER_TYPE_MPLS);
9513 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9514 switch (prev_layer) {
9515 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9517 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9518 outer_first_mpls_over_udp);
9520 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9521 outer_first_mpls_over_udp);
9523 case MLX5_FLOW_LAYER_GRE:
9525 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9526 outer_first_mpls_over_gre);
9528 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9529 outer_first_mpls_over_gre);
9532 /* Inner MPLS not over GRE is not supported. */
9535 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9539 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9545 if (out_mpls_m && out_mpls_v) {
9546 *out_mpls_m = *in_mpls_m;
9547 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9552 * Add metadata register item to matcher
9554 * @param[in, out] matcher
9556 * @param[in, out] key
9557 * Flow matcher value.
9558 * @param[in] reg_type
9559 * Type of device metadata register
9566 flow_dv_match_meta_reg(void *matcher, void *key,
9567 enum modify_reg reg_type,
9568 uint32_t data, uint32_t mask)
9571 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9573 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9579 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9580 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9583 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9584 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9588 * The metadata register C0 field might be divided into
9589 * source vport index and META item value, we should set
9590 * this field according to specified mask, not as whole one.
9592 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9594 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9595 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9598 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9601 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9602 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9605 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9606 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9609 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9610 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9613 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9614 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9617 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9618 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9621 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9622 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9625 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9626 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9635 * Add MARK item to matcher
9638 * The device to configure through.
9639 * @param[in, out] matcher
9641 * @param[in, out] key
9642 * Flow matcher value.
9644 * Flow pattern to translate.
9647 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9648 void *matcher, void *key,
9649 const struct rte_flow_item *item)
9651 struct mlx5_priv *priv = dev->data->dev_private;
9652 const struct rte_flow_item_mark *mark;
9656 mark = item->mask ? (const void *)item->mask :
9657 &rte_flow_item_mark_mask;
9658 mask = mark->id & priv->sh->dv_mark_mask;
9659 mark = (const void *)item->spec;
9661 value = mark->id & priv->sh->dv_mark_mask & mask;
9663 enum modify_reg reg;
9665 /* Get the metadata register index for the mark. */
9666 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9667 MLX5_ASSERT(reg > 0);
9668 if (reg == REG_C_0) {
9669 struct mlx5_priv *priv = dev->data->dev_private;
9670 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9671 uint32_t shl_c0 = rte_bsf32(msk_c0);
9677 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9682 * Add META item to matcher
9685 * The devich to configure through.
9686 * @param[in, out] matcher
9688 * @param[in, out] key
9689 * Flow matcher value.
9691 * Attributes of flow that includes this item.
9693 * Flow pattern to translate.
9696 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9697 void *matcher, void *key,
9698 const struct rte_flow_attr *attr,
9699 const struct rte_flow_item *item)
9701 const struct rte_flow_item_meta *meta_m;
9702 const struct rte_flow_item_meta *meta_v;
9704 meta_m = (const void *)item->mask;
9706 meta_m = &rte_flow_item_meta_mask;
9707 meta_v = (const void *)item->spec;
9710 uint32_t value = meta_v->data;
9711 uint32_t mask = meta_m->data;
9713 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9716 MLX5_ASSERT(reg != REG_NON);
9717 if (reg == REG_C_0) {
9718 struct mlx5_priv *priv = dev->data->dev_private;
9719 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9720 uint32_t shl_c0 = rte_bsf32(msk_c0);
9726 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9731 * Add vport metadata Reg C0 item to matcher
9733 * @param[in, out] matcher
9735 * @param[in, out] key
9736 * Flow matcher value.
9738 * Flow pattern to translate.
9741 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9742 uint32_t value, uint32_t mask)
9744 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9748 * Add tag item to matcher
9751 * The devich to configure through.
9752 * @param[in, out] matcher
9754 * @param[in, out] key
9755 * Flow matcher value.
9757 * Flow pattern to translate.
9760 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9761 void *matcher, void *key,
9762 const struct rte_flow_item *item)
9764 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9765 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9766 uint32_t mask, value;
9769 value = tag_v->data;
9770 mask = tag_m ? tag_m->data : UINT32_MAX;
9771 if (tag_v->id == REG_C_0) {
9772 struct mlx5_priv *priv = dev->data->dev_private;
9773 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9774 uint32_t shl_c0 = rte_bsf32(msk_c0);
9780 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9784 * Add TAG item to matcher
9787 * The devich to configure through.
9788 * @param[in, out] matcher
9790 * @param[in, out] key
9791 * Flow matcher value.
9793 * Flow pattern to translate.
9796 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9797 void *matcher, void *key,
9798 const struct rte_flow_item *item)
9800 const struct rte_flow_item_tag *tag_v = item->spec;
9801 const struct rte_flow_item_tag *tag_m = item->mask;
9802 enum modify_reg reg;
9805 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9806 /* Get the metadata register index for the tag. */
9807 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9808 MLX5_ASSERT(reg > 0);
9809 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9813 * Add source vport match to the specified matcher.
9815 * @param[in, out] matcher
9817 * @param[in, out] key
9818 * Flow matcher value.
9820 * Source vport value to match
9825 flow_dv_translate_item_source_vport(void *matcher, void *key,
9826 int16_t port, uint16_t mask)
9828 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9829 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9831 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9832 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9836 * Translate port-id item to eswitch match on port-id.
9839 * The devich to configure through.
9840 * @param[in, out] matcher
9842 * @param[in, out] key
9843 * Flow matcher value.
9845 * Flow pattern to translate.
9850 * 0 on success, a negative errno value otherwise.
9853 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9854 void *key, const struct rte_flow_item *item,
9855 const struct rte_flow_attr *attr)
9857 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9858 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9859 struct mlx5_priv *priv;
9862 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9863 flow_dv_translate_item_source_vport(matcher, key,
9864 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9867 mask = pid_m ? pid_m->id : 0xffff;
9868 id = pid_v ? pid_v->id : dev->data->port_id;
9869 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9873 * Translate to vport field or to metadata, depending on mode.
9874 * Kernel can use either misc.source_port or half of C0 metadata
9877 if (priv->vport_meta_mask) {
9879 * Provide the hint for SW steering library
9880 * to insert the flow into ingress domain and
9881 * save the extra vport match.
9883 if (mask == 0xffff && priv->vport_id == 0xffff &&
9884 priv->pf_bond < 0 && attr->transfer)
9885 flow_dv_translate_item_source_vport
9886 (matcher, key, priv->vport_id, mask);
9888 * We should always set the vport metadata register,
9889 * otherwise the SW steering library can drop
9890 * the rule if wire vport metadata value is not zero,
9891 * it depends on kernel configuration.
9893 flow_dv_translate_item_meta_vport(matcher, key,
9894 priv->vport_meta_tag,
9895 priv->vport_meta_mask);
9897 flow_dv_translate_item_source_vport(matcher, key,
9898 priv->vport_id, mask);
9904 * Add ICMP6 item to matcher and to the value.
9906 * @param[in, out] matcher
9908 * @param[in, out] key
9909 * Flow matcher value.
9911 * Flow pattern to translate.
9913 * Item is inner pattern.
9916 flow_dv_translate_item_icmp6(void *matcher, void *key,
9917 const struct rte_flow_item *item,
9920 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9921 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9924 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9926 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9928 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9930 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9932 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9934 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9936 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9937 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9941 icmp6_m = &rte_flow_item_icmp6_mask;
9942 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9943 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9944 icmp6_v->type & icmp6_m->type);
9945 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9946 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9947 icmp6_v->code & icmp6_m->code);
9951 * Add ICMP item to matcher and to the value.
9953 * @param[in, out] matcher
9955 * @param[in, out] key
9956 * Flow matcher value.
9958 * Flow pattern to translate.
9960 * Item is inner pattern.
9963 flow_dv_translate_item_icmp(void *matcher, void *key,
9964 const struct rte_flow_item *item,
9967 const struct rte_flow_item_icmp *icmp_m = item->mask;
9968 const struct rte_flow_item_icmp *icmp_v = item->spec;
9969 uint32_t icmp_header_data_m = 0;
9970 uint32_t icmp_header_data_v = 0;
9973 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9975 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9977 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9979 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9981 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9983 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9985 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9990 icmp_m = &rte_flow_item_icmp_mask;
9991 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9992 icmp_m->hdr.icmp_type);
9993 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9994 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9995 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9996 icmp_m->hdr.icmp_code);
9997 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9998 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9999 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
10000 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
10001 if (icmp_header_data_m) {
10002 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
10003 icmp_header_data_v |=
10004 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
10005 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
10006 icmp_header_data_m);
10007 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
10008 icmp_header_data_v & icmp_header_data_m);
10013 * Add GTP item to matcher and to the value.
10015 * @param[in, out] matcher
10017 * @param[in, out] key
10018 * Flow matcher value.
10020 * Flow pattern to translate.
10022 * Item is inner pattern.
10025 flow_dv_translate_item_gtp(void *matcher, void *key,
10026 const struct rte_flow_item *item, int inner)
10028 const struct rte_flow_item_gtp *gtp_m = item->mask;
10029 const struct rte_flow_item_gtp *gtp_v = item->spec;
10032 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10033 misc_parameters_3);
10034 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10035 uint16_t dport = RTE_GTPU_UDP_PORT;
10038 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10040 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
10042 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10044 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10046 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
10047 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
10048 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
10053 gtp_m = &rte_flow_item_gtp_mask;
10054 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
10055 gtp_m->v_pt_rsv_flags);
10056 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
10057 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
10058 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
10059 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
10060 gtp_v->msg_type & gtp_m->msg_type);
10061 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
10062 rte_be_to_cpu_32(gtp_m->teid));
10063 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
10064 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
10068 * Add GTP PSC item to matcher.
10070 * @param[in, out] matcher
10072 * @param[in, out] key
10073 * Flow matcher value.
10075 * Flow pattern to translate.
10078 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
10079 const struct rte_flow_item *item)
10081 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
10082 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
10083 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10084 misc_parameters_3);
10085 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10091 uint8_t next_ext_header_type;
10096 /* Always set E-flag match on one, regardless of GTP item settings. */
10097 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
10098 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10099 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
10100 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
10101 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10102 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
10103 /*Set next extension header type. */
10106 dw_2.next_ext_header_type = 0xff;
10107 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
10108 rte_cpu_to_be_32(dw_2.w32));
10111 dw_2.next_ext_header_type = 0x85;
10112 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
10113 rte_cpu_to_be_32(dw_2.w32));
10119 uint8_t type_flags;
10125 /*Set extension header PDU type and Qos. */
10127 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
10129 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
10130 dw_0.qfi = gtp_psc_m->hdr.qfi;
10131 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
10132 rte_cpu_to_be_32(dw_0.w32));
10134 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
10135 gtp_psc_m->hdr.type);
10136 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
10137 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
10138 rte_cpu_to_be_32(dw_0.w32));
10144 * Add eCPRI item to matcher and to the value.
10147 * The devich to configure through.
10148 * @param[in, out] matcher
10150 * @param[in, out] key
10151 * Flow matcher value.
10153 * Flow pattern to translate.
10154 * @param[in] last_item
10158 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10159 void *key, const struct rte_flow_item *item,
10160 uint64_t last_item)
10162 struct mlx5_priv *priv = dev->data->dev_private;
10163 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10164 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10165 struct rte_ecpri_common_hdr common;
10166 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10167 misc_parameters_4);
10168 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10174 * In case of eCPRI over Ethernet, if EtherType is not specified,
10175 * match on eCPRI EtherType implicitly.
10177 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10178 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10180 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10181 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10182 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10183 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10184 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10185 *(uint16_t *)l2m = UINT16_MAX;
10186 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10192 ecpri_m = &rte_flow_item_ecpri_mask;
10194 * Maximal four DW samples are supported in a single matching now.
10195 * Two are used now for a eCPRI matching:
10196 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10197 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10200 if (!ecpri_m->hdr.common.u32)
10202 samples = priv->sh->ecpri_parser.ids;
10203 /* Need to take the whole DW as the mask to fill the entry. */
10204 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10205 prog_sample_field_value_0);
10206 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10207 prog_sample_field_value_0);
10208 /* Already big endian (network order) in the header. */
10209 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10210 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10211 /* Sample#0, used for matching type, offset 0. */
10212 MLX5_SET(fte_match_set_misc4, misc4_m,
10213 prog_sample_field_id_0, samples[0]);
10214 /* It makes no sense to set the sample ID in the mask field. */
10215 MLX5_SET(fte_match_set_misc4, misc4_v,
10216 prog_sample_field_id_0, samples[0]);
10218 * Checking if message body part needs to be matched.
10219 * Some wildcard rules only matching type field should be supported.
10221 if (ecpri_m->hdr.dummy[0]) {
10222 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10223 switch (common.type) {
10224 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10225 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10226 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10227 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10228 prog_sample_field_value_1);
10229 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10230 prog_sample_field_value_1);
10231 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10232 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10233 ecpri_m->hdr.dummy[0];
10234 /* Sample#1, to match message body, offset 4. */
10235 MLX5_SET(fte_match_set_misc4, misc4_m,
10236 prog_sample_field_id_1, samples[1]);
10237 MLX5_SET(fte_match_set_misc4, misc4_v,
10238 prog_sample_field_id_1, samples[1]);
10241 /* Others, do not match any sample ID. */
10248 * Add connection tracking status item to matcher
10251 * The devich to configure through.
10252 * @param[in, out] matcher
10254 * @param[in, out] key
10255 * Flow matcher value.
10257 * Flow pattern to translate.
10260 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10261 void *matcher, void *key,
10262 const struct rte_flow_item *item)
10264 uint32_t reg_value = 0;
10266 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10267 uint32_t reg_mask = 0;
10268 const struct rte_flow_item_conntrack *spec = item->spec;
10269 const struct rte_flow_item_conntrack *mask = item->mask;
10271 struct rte_flow_error error;
10274 mask = &rte_flow_item_conntrack_mask;
10275 if (!spec || !mask->flags)
10277 flags = spec->flags & mask->flags;
10278 /* The conflict should be checked in the validation. */
10279 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10280 reg_value |= MLX5_CT_SYNDROME_VALID;
10281 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10282 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10283 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10284 reg_value |= MLX5_CT_SYNDROME_INVALID;
10285 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10286 reg_value |= MLX5_CT_SYNDROME_TRAP;
10287 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10288 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10289 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10290 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10291 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10293 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10294 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10295 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10296 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10297 /* The REG_C_x value could be saved during startup. */
10298 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10299 if (reg_id == REG_NON)
10301 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10302 reg_value, reg_mask);
10306 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10307 const struct rte_flow_item *item,
10308 struct mlx5_flow *dev_flow, bool is_inner)
10310 const struct rte_flow_item_flex *spec =
10311 (const struct rte_flow_item_flex *)item->spec;
10312 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10314 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10317 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10318 /* Don't count both inner and outer flex items in one rule. */
10319 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10320 MLX5_ASSERT(false);
10321 dev_flow->handle->flex_item |= (uint8_t)RTE_BIT32(index);
10323 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10326 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10328 #define HEADER_IS_ZERO(match_criteria, headers) \
10329 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10330 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10333 * Calculate flow matcher enable bitmap.
10335 * @param match_criteria
10336 * Pointer to flow matcher criteria.
10339 * Bitmap of enabled fields.
10342 flow_dv_matcher_enable(uint32_t *match_criteria)
10344 uint8_t match_criteria_enable;
10346 match_criteria_enable =
10347 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10348 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10349 match_criteria_enable |=
10350 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10351 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10352 match_criteria_enable |=
10353 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10354 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10355 match_criteria_enable |=
10356 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10357 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10358 match_criteria_enable |=
10359 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10360 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10361 match_criteria_enable |=
10362 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10363 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10364 match_criteria_enable |=
10365 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10366 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10367 return match_criteria_enable;
10371 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10374 * Check flow matching criteria first, subtract misc5/4 length if flow
10375 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10376 * misc5/4 are not supported, and matcher creation failure is expected
10377 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10378 * misc5 is right after misc4.
10380 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10381 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10382 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10383 if (!(match_criteria & (1 <<
10384 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10385 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10390 static struct mlx5_list_entry *
10391 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10392 struct mlx5_list_entry *entry, void *cb_ctx)
10394 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10395 struct mlx5_flow_dv_matcher *ref = ctx->data;
10396 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10397 typeof(*tbl), tbl);
10398 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10403 rte_flow_error_set(ctx->error, ENOMEM,
10404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10405 "cannot create matcher");
10408 memcpy(resource, entry, sizeof(*resource));
10409 resource->tbl = &tbl->tbl;
10410 return &resource->entry;
10414 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10415 struct mlx5_list_entry *entry)
10420 struct mlx5_list_entry *
10421 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10423 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10424 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10425 struct rte_eth_dev *dev = ctx->dev;
10426 struct mlx5_flow_tbl_data_entry *tbl_data;
10427 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10428 struct rte_flow_error *error = ctx->error;
10429 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10430 struct mlx5_flow_tbl_resource *tbl;
10435 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10437 rte_flow_error_set(error, ENOMEM,
10438 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10440 "cannot allocate flow table data entry");
10443 tbl_data->idx = idx;
10444 tbl_data->tunnel = tt_prm->tunnel;
10445 tbl_data->group_id = tt_prm->group_id;
10446 tbl_data->external = !!tt_prm->external;
10447 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10448 tbl_data->is_egress = !!key.is_egress;
10449 tbl_data->is_transfer = !!key.is_fdb;
10450 tbl_data->dummy = !!key.dummy;
10451 tbl_data->level = key.level;
10452 tbl_data->id = key.id;
10453 tbl = &tbl_data->tbl;
10455 return &tbl_data->entry;
10457 domain = sh->fdb_domain;
10458 else if (key.is_egress)
10459 domain = sh->tx_domain;
10461 domain = sh->rx_domain;
10462 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10464 rte_flow_error_set(error, ENOMEM,
10465 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10466 NULL, "cannot create flow table object");
10467 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10470 if (key.level != 0) {
10471 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10472 (tbl->obj, &tbl_data->jump.action);
10474 rte_flow_error_set(error, ENOMEM,
10475 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10477 "cannot create flow jump action");
10478 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10479 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10483 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10484 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10485 key.level, key.id);
10486 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10487 flow_dv_matcher_create_cb,
10488 flow_dv_matcher_match_cb,
10489 flow_dv_matcher_remove_cb,
10490 flow_dv_matcher_clone_cb,
10491 flow_dv_matcher_clone_free_cb);
10492 if (!tbl_data->matchers) {
10493 rte_flow_error_set(error, ENOMEM,
10494 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10496 "cannot create tbl matcher list");
10497 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10498 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10499 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10502 return &tbl_data->entry;
10506 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10509 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10510 struct mlx5_flow_tbl_data_entry *tbl_data =
10511 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10512 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10514 return tbl_data->level != key.level ||
10515 tbl_data->id != key.id ||
10516 tbl_data->dummy != key.dummy ||
10517 tbl_data->is_transfer != !!key.is_fdb ||
10518 tbl_data->is_egress != !!key.is_egress;
10521 struct mlx5_list_entry *
10522 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10525 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10526 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10527 struct mlx5_flow_tbl_data_entry *tbl_data;
10528 struct rte_flow_error *error = ctx->error;
10531 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10533 rte_flow_error_set(error, ENOMEM,
10534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10536 "cannot allocate flow table data entry");
10539 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10540 tbl_data->idx = idx;
10541 return &tbl_data->entry;
10545 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10547 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10548 struct mlx5_flow_tbl_data_entry *tbl_data =
10549 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10551 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10555 * Get a flow table.
10557 * @param[in, out] dev
10558 * Pointer to rte_eth_dev structure.
10559 * @param[in] table_level
10560 * Table level to use.
10561 * @param[in] egress
10562 * Direction of the table.
10563 * @param[in] transfer
10564 * E-Switch or NIC flow.
10566 * Dummy entry for dv API.
10567 * @param[in] table_id
10569 * @param[out] error
10570 * pointer to error structure.
10573 * Returns tables resource based on the index, NULL in case of failed.
10575 struct mlx5_flow_tbl_resource *
10576 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10577 uint32_t table_level, uint8_t egress,
10580 const struct mlx5_flow_tunnel *tunnel,
10581 uint32_t group_id, uint8_t dummy,
10583 struct rte_flow_error *error)
10585 struct mlx5_priv *priv = dev->data->dev_private;
10586 union mlx5_flow_tbl_key table_key = {
10588 .level = table_level,
10592 .is_fdb = !!transfer,
10593 .is_egress = !!egress,
10596 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10598 .group_id = group_id,
10599 .external = external,
10601 struct mlx5_flow_cb_ctx ctx = {
10604 .data = &table_key.v64,
10607 struct mlx5_list_entry *entry;
10608 struct mlx5_flow_tbl_data_entry *tbl_data;
10610 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10612 rte_flow_error_set(error, ENOMEM,
10613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10614 "cannot get table");
10617 DRV_LOG(DEBUG, "table_level %u table_id %u "
10618 "tunnel %u group %u registered.",
10619 table_level, table_id,
10620 tunnel ? tunnel->tunnel_id : 0, group_id);
10621 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10622 return &tbl_data->tbl;
10626 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10628 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10629 struct mlx5_flow_tbl_data_entry *tbl_data =
10630 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10632 MLX5_ASSERT(entry && sh);
10633 if (tbl_data->jump.action)
10634 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10635 if (tbl_data->tbl.obj)
10636 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10637 if (tbl_data->tunnel_offload && tbl_data->external) {
10638 struct mlx5_list_entry *he;
10639 struct mlx5_hlist *tunnel_grp_hash;
10640 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10641 union tunnel_tbl_key tunnel_key = {
10642 .tunnel_id = tbl_data->tunnel ?
10643 tbl_data->tunnel->tunnel_id : 0,
10644 .group = tbl_data->group_id
10646 uint32_t table_level = tbl_data->level;
10647 struct mlx5_flow_cb_ctx ctx = {
10648 .data = (void *)&tunnel_key.val,
10651 tunnel_grp_hash = tbl_data->tunnel ?
10652 tbl_data->tunnel->groups :
10654 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10656 mlx5_hlist_unregister(tunnel_grp_hash, he);
10658 "table_level %u id %u tunnel %u group %u released.",
10662 tbl_data->tunnel->tunnel_id : 0,
10663 tbl_data->group_id);
10665 if (tbl_data->matchers)
10666 mlx5_list_destroy(tbl_data->matchers);
10667 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10671 * Release a flow table.
10674 * Pointer to device shared structure.
10676 * Table resource to be released.
10679 * Returns 0 if table was released, else return 1;
10682 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10683 struct mlx5_flow_tbl_resource *tbl)
10685 struct mlx5_flow_tbl_data_entry *tbl_data =
10686 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10690 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10694 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10695 struct mlx5_list_entry *entry, void *cb_ctx)
10697 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10698 struct mlx5_flow_dv_matcher *ref = ctx->data;
10699 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10702 return cur->crc != ref->crc ||
10703 cur->priority != ref->priority ||
10704 memcmp((const void *)cur->mask.buf,
10705 (const void *)ref->mask.buf, ref->mask.size);
10708 struct mlx5_list_entry *
10709 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10711 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10712 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10713 struct mlx5_flow_dv_matcher *ref = ctx->data;
10714 struct mlx5_flow_dv_matcher *resource;
10715 struct mlx5dv_flow_matcher_attr dv_attr = {
10716 .type = IBV_FLOW_ATTR_NORMAL,
10717 .match_mask = (void *)&ref->mask,
10719 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10720 typeof(*tbl), tbl);
10723 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10726 rte_flow_error_set(ctx->error, ENOMEM,
10727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10728 "cannot create matcher");
10732 dv_attr.match_criteria_enable =
10733 flow_dv_matcher_enable(resource->mask.buf);
10734 __flow_dv_adjust_buf_size(&ref->mask.size,
10735 dv_attr.match_criteria_enable);
10736 dv_attr.priority = ref->priority;
10737 if (tbl->is_egress)
10738 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10739 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10741 &resource->matcher_object);
10743 mlx5_free(resource);
10744 rte_flow_error_set(ctx->error, ENOMEM,
10745 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10746 "cannot create matcher");
10749 return &resource->entry;
10753 * Register the flow matcher.
10755 * @param[in, out] dev
10756 * Pointer to rte_eth_dev structure.
10757 * @param[in, out] matcher
10758 * Pointer to flow matcher.
10759 * @param[in, out] key
10760 * Pointer to flow table key.
10761 * @parm[in, out] dev_flow
10762 * Pointer to the dev_flow.
10763 * @param[out] error
10764 * pointer to error structure.
10767 * 0 on success otherwise -errno and errno is set.
10770 flow_dv_matcher_register(struct rte_eth_dev *dev,
10771 struct mlx5_flow_dv_matcher *ref,
10772 union mlx5_flow_tbl_key *key,
10773 struct mlx5_flow *dev_flow,
10774 const struct mlx5_flow_tunnel *tunnel,
10776 struct rte_flow_error *error)
10778 struct mlx5_list_entry *entry;
10779 struct mlx5_flow_dv_matcher *resource;
10780 struct mlx5_flow_tbl_resource *tbl;
10781 struct mlx5_flow_tbl_data_entry *tbl_data;
10782 struct mlx5_flow_cb_ctx ctx = {
10787 * tunnel offload API requires this registration for cases when
10788 * tunnel match rule was inserted before tunnel set rule.
10790 tbl = flow_dv_tbl_resource_get(dev, key->level,
10791 key->is_egress, key->is_fdb,
10792 dev_flow->external, tunnel,
10793 group_id, 0, key->id, error);
10795 return -rte_errno; /* No need to refill the error info */
10796 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10798 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10800 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10801 return rte_flow_error_set(error, ENOMEM,
10802 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10803 "cannot allocate ref memory");
10805 resource = container_of(entry, typeof(*resource), entry);
10806 dev_flow->handle->dvh.matcher = resource;
10810 struct mlx5_list_entry *
10811 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10813 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10814 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10815 struct mlx5_flow_dv_tag_resource *entry;
10819 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10821 rte_flow_error_set(ctx->error, ENOMEM,
10822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10823 "cannot allocate resource memory");
10827 entry->tag_id = *(uint32_t *)(ctx->data);
10828 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10831 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10832 rte_flow_error_set(ctx->error, ENOMEM,
10833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10834 NULL, "cannot create action");
10837 return &entry->entry;
10841 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10844 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10845 struct mlx5_flow_dv_tag_resource *tag =
10846 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10848 return *(uint32_t *)(ctx->data) != tag->tag_id;
10851 struct mlx5_list_entry *
10852 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10855 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10856 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10857 struct mlx5_flow_dv_tag_resource *entry;
10860 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10862 rte_flow_error_set(ctx->error, ENOMEM,
10863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10864 "cannot allocate tag resource memory");
10867 memcpy(entry, oentry, sizeof(*entry));
10869 return &entry->entry;
10873 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10875 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10876 struct mlx5_flow_dv_tag_resource *tag =
10877 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10879 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10883 * Find existing tag resource or create and register a new one.
10885 * @param dev[in, out]
10886 * Pointer to rte_eth_dev structure.
10887 * @param[in, out] tag_be24
10888 * Tag value in big endian then R-shift 8.
10889 * @parm[in, out] dev_flow
10890 * Pointer to the dev_flow.
10891 * @param[out] error
10892 * pointer to error structure.
10895 * 0 on success otherwise -errno and errno is set.
10898 flow_dv_tag_resource_register
10899 (struct rte_eth_dev *dev,
10901 struct mlx5_flow *dev_flow,
10902 struct rte_flow_error *error)
10904 struct mlx5_priv *priv = dev->data->dev_private;
10905 struct mlx5_flow_dv_tag_resource *resource;
10906 struct mlx5_list_entry *entry;
10907 struct mlx5_flow_cb_ctx ctx = {
10911 struct mlx5_hlist *tag_table;
10913 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10915 MLX5_TAGS_HLIST_ARRAY_SIZE,
10916 false, false, priv->sh,
10917 flow_dv_tag_create_cb,
10918 flow_dv_tag_match_cb,
10919 flow_dv_tag_remove_cb,
10920 flow_dv_tag_clone_cb,
10921 flow_dv_tag_clone_free_cb,
10923 if (unlikely(!tag_table))
10925 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10927 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10929 dev_flow->handle->dvh.rix_tag = resource->idx;
10930 dev_flow->dv.tag_resource = resource;
10937 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10939 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10940 struct mlx5_flow_dv_tag_resource *tag =
10941 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10943 MLX5_ASSERT(tag && sh && tag->action);
10944 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10945 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10946 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10953 * Pointer to Ethernet device.
10958 * 1 while a reference on it exists, 0 when freed.
10961 flow_dv_tag_release(struct rte_eth_dev *dev,
10964 struct mlx5_priv *priv = dev->data->dev_private;
10965 struct mlx5_flow_dv_tag_resource *tag;
10967 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10970 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10971 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10972 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10976 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10979 * Pointer to rte_eth_dev structure.
10980 * @param[in] action
10981 * Pointer to action PORT_ID / REPRESENTED_PORT.
10982 * @param[out] dst_port_id
10983 * The target port ID.
10984 * @param[out] error
10985 * Pointer to the error structure.
10988 * 0 on success, a negative errno value otherwise and rte_errno is set.
10991 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10992 const struct rte_flow_action *action,
10993 uint32_t *dst_port_id,
10994 struct rte_flow_error *error)
10997 struct mlx5_priv *priv;
10999 switch (action->type) {
11000 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
11001 const struct rte_flow_action_port_id *conf;
11003 conf = (const struct rte_flow_action_port_id *)action->conf;
11004 port = conf->original ? dev->data->port_id : conf->id;
11007 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
11008 const struct rte_flow_action_ethdev *ethdev;
11010 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
11011 port = ethdev->port_id;
11015 MLX5_ASSERT(false);
11016 return rte_flow_error_set(error, EINVAL,
11017 RTE_FLOW_ERROR_TYPE_ACTION, action,
11018 "unknown E-Switch action");
11021 priv = mlx5_port_to_eswitch_info(port, false);
11023 return rte_flow_error_set(error, -rte_errno,
11024 RTE_FLOW_ERROR_TYPE_ACTION,
11026 "No eswitch info was found for port");
11027 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
11029 * This parameter is transferred to
11030 * mlx5dv_dr_action_create_dest_ib_port().
11032 *dst_port_id = priv->dev_port;
11035 * Legacy mode, no LAG configurations is supported.
11036 * This parameter is transferred to
11037 * mlx5dv_dr_action_create_dest_vport().
11039 *dst_port_id = priv->vport_id;
11045 * Create a counter with aging configuration.
11048 * Pointer to rte_eth_dev structure.
11049 * @param[in] dev_flow
11050 * Pointer to the mlx5_flow.
11051 * @param[out] count
11052 * Pointer to the counter action configuration.
11054 * Pointer to the aging action configuration.
11057 * Index to flow counter on success, 0 otherwise.
11060 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
11061 struct mlx5_flow *dev_flow,
11062 const struct rte_flow_action_count *count
11064 const struct rte_flow_action_age *age)
11067 struct mlx5_age_param *age_param;
11069 counter = flow_dv_counter_alloc(dev, !!age);
11070 if (!counter || age == NULL)
11072 age_param = flow_dv_counter_idx_get_age(dev, counter);
11073 age_param->context = age->context ? age->context :
11074 (void *)(uintptr_t)(dev_flow->flow_idx);
11075 age_param->timeout = age->timeout;
11076 age_param->port_id = dev->data->port_id;
11077 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
11078 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
11083 * Add Tx queue matcher
11086 * Pointer to the dev struct.
11087 * @param[in, out] matcher
11089 * @param[in, out] key
11090 * Flow matcher value.
11092 * Flow pattern to translate.
11094 * Item is inner pattern.
11097 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
11098 void *matcher, void *key,
11099 const struct rte_flow_item *item)
11101 const struct mlx5_rte_flow_item_tx_queue *queue_m;
11102 const struct mlx5_rte_flow_item_tx_queue *queue_v;
11103 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
11104 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
11105 struct mlx5_txq_ctrl *txq;
11106 uint32_t queue, mask;
11108 queue_m = (const void *)item->mask;
11109 queue_v = (const void *)item->spec;
11112 txq = mlx5_txq_get(dev, queue_v->queue);
11115 if (txq->is_hairpin)
11116 queue = txq->obj->sq->id;
11118 queue = txq->obj->sq_obj.sq->id;
11119 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
11120 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
11121 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
11122 mlx5_txq_release(dev, queue_v->queue);
11126 * Set the hash fields according to the @p flow information.
11128 * @param[in] item_flags
11129 * The match pattern item flags.
11130 * @param[in] rss_desc
11131 * Pointer to the mlx5_flow_rss_desc.
11132 * @param[out] hash_fields
11133 * Pointer to the RSS hash fields.
11136 flow_dv_hashfields_set(uint64_t item_flags,
11137 struct mlx5_flow_rss_desc *rss_desc,
11138 uint64_t *hash_fields)
11140 uint64_t items = item_flags;
11141 uint64_t fields = 0;
11143 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
11146 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
11147 if (rss_desc->level >= 2)
11150 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
11151 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||
11153 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
11154 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11155 fields |= IBV_RX_HASH_SRC_IPV4;
11156 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11157 fields |= IBV_RX_HASH_DST_IPV4;
11159 fields |= MLX5_IPV4_IBV_RX_HASH;
11161 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
11162 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||
11164 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11165 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11166 fields |= IBV_RX_HASH_SRC_IPV6;
11167 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11168 fields |= IBV_RX_HASH_DST_IPV6;
11170 fields |= MLX5_IPV6_IBV_RX_HASH;
11175 * There is no match between the RSS types and the
11176 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11179 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11180 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||
11182 if (rss_types & RTE_ETH_RSS_UDP) {
11183 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11184 fields |= IBV_RX_HASH_SRC_PORT_UDP;
11185 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11186 fields |= IBV_RX_HASH_DST_PORT_UDP;
11188 fields |= MLX5_UDP_IBV_RX_HASH;
11190 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11191 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||
11193 if (rss_types & RTE_ETH_RSS_TCP) {
11194 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11195 fields |= IBV_RX_HASH_SRC_PORT_TCP;
11196 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11197 fields |= IBV_RX_HASH_DST_PORT_TCP;
11199 fields |= MLX5_TCP_IBV_RX_HASH;
11203 fields |= IBV_RX_HASH_INNER;
11204 *hash_fields = fields;
11208 * Prepare an Rx Hash queue.
11211 * Pointer to Ethernet device.
11212 * @param[in] dev_flow
11213 * Pointer to the mlx5_flow.
11214 * @param[in] rss_desc
11215 * Pointer to the mlx5_flow_rss_desc.
11216 * @param[out] hrxq_idx
11217 * Hash Rx queue index.
11220 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11222 static struct mlx5_hrxq *
11223 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11224 struct mlx5_flow *dev_flow,
11225 struct mlx5_flow_rss_desc *rss_desc,
11226 uint32_t *hrxq_idx)
11228 struct mlx5_flow_handle *dh = dev_flow->handle;
11229 uint32_t shared_rss = rss_desc->shared_rss;
11230 struct mlx5_hrxq *hrxq;
11232 MLX5_ASSERT(rss_desc->queue_num);
11233 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11234 rss_desc->hash_fields = dev_flow->hash_fields;
11235 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11236 rss_desc->shared_rss = 0;
11237 if (rss_desc->hash_fields == 0)
11238 rss_desc->queue_num = 1;
11239 hrxq = mlx5_hrxq_get(dev, rss_desc);
11240 *hrxq_idx = hrxq ? hrxq->idx : 0;
11241 rss_desc->shared_rss = shared_rss;
11246 * Release sample sub action resource.
11248 * @param[in, out] dev
11249 * Pointer to rte_eth_dev structure.
11250 * @param[in] act_res
11251 * Pointer to sample sub action resource.
11254 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11255 struct mlx5_flow_sub_actions_idx *act_res)
11257 if (act_res->rix_hrxq) {
11258 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11259 act_res->rix_hrxq = 0;
11261 if (act_res->rix_encap_decap) {
11262 flow_dv_encap_decap_resource_release(dev,
11263 act_res->rix_encap_decap);
11264 act_res->rix_encap_decap = 0;
11266 if (act_res->rix_port_id_action) {
11267 flow_dv_port_id_action_resource_release(dev,
11268 act_res->rix_port_id_action);
11269 act_res->rix_port_id_action = 0;
11271 if (act_res->rix_tag) {
11272 flow_dv_tag_release(dev, act_res->rix_tag);
11273 act_res->rix_tag = 0;
11275 if (act_res->rix_jump) {
11276 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11277 act_res->rix_jump = 0;
11282 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11283 struct mlx5_list_entry *entry, void *cb_ctx)
11285 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11286 struct rte_eth_dev *dev = ctx->dev;
11287 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11288 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11292 if (ctx_resource->ratio == resource->ratio &&
11293 ctx_resource->ft_type == resource->ft_type &&
11294 ctx_resource->ft_id == resource->ft_id &&
11295 ctx_resource->set_action == resource->set_action &&
11296 !memcmp((void *)&ctx_resource->sample_act,
11297 (void *)&resource->sample_act,
11298 sizeof(struct mlx5_flow_sub_actions_list))) {
11300 * Existing sample action should release the prepared
11301 * sub-actions reference counter.
11303 flow_dv_sample_sub_actions_release(dev,
11304 &ctx_resource->sample_idx);
11310 struct mlx5_list_entry *
11311 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11313 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11314 struct rte_eth_dev *dev = ctx->dev;
11315 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11316 void **sample_dv_actions = ctx_resource->sub_actions;
11317 struct mlx5_flow_dv_sample_resource *resource;
11318 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11319 struct mlx5_priv *priv = dev->data->dev_private;
11320 struct mlx5_dev_ctx_shared *sh = priv->sh;
11321 struct mlx5_flow_tbl_resource *tbl;
11323 const uint32_t next_ft_step = 1;
11324 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11325 uint8_t is_egress = 0;
11326 uint8_t is_transfer = 0;
11327 struct rte_flow_error *error = ctx->error;
11329 /* Register new sample resource. */
11330 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11332 rte_flow_error_set(error, ENOMEM,
11333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11335 "cannot allocate resource memory");
11338 *resource = *ctx_resource;
11339 /* Create normal path table level */
11340 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11342 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11344 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11345 is_egress, is_transfer,
11346 true, NULL, 0, 0, 0, error);
11348 rte_flow_error_set(error, ENOMEM,
11349 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11351 "fail to create normal path table "
11355 resource->normal_path_tbl = tbl;
11356 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11357 if (!sh->default_miss_action) {
11358 rte_flow_error_set(error, ENOMEM,
11359 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11361 "default miss action was not "
11365 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11366 sh->default_miss_action;
11368 /* Create a DR sample action */
11369 sampler_attr.sample_ratio = resource->ratio;
11370 sampler_attr.default_next_table = tbl->obj;
11371 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11372 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11373 &sample_dv_actions[0];
11374 sampler_attr.action = resource->set_action;
11375 if (mlx5_os_flow_dr_create_flow_action_sampler
11376 (&sampler_attr, &resource->verbs_action)) {
11377 rte_flow_error_set(error, ENOMEM,
11378 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11379 NULL, "cannot create sample action");
11382 resource->idx = idx;
11383 resource->dev = dev;
11384 return &resource->entry;
11386 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11387 flow_dv_sample_sub_actions_release(dev,
11388 &resource->sample_idx);
11389 if (resource->normal_path_tbl)
11390 flow_dv_tbl_resource_release(MLX5_SH(dev),
11391 resource->normal_path_tbl);
11392 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11397 struct mlx5_list_entry *
11398 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11399 struct mlx5_list_entry *entry __rte_unused,
11402 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11403 struct rte_eth_dev *dev = ctx->dev;
11404 struct mlx5_flow_dv_sample_resource *resource;
11405 struct mlx5_priv *priv = dev->data->dev_private;
11406 struct mlx5_dev_ctx_shared *sh = priv->sh;
11409 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11411 rte_flow_error_set(ctx->error, ENOMEM,
11412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11414 "cannot allocate resource memory");
11417 memcpy(resource, entry, sizeof(*resource));
11418 resource->idx = idx;
11419 resource->dev = dev;
11420 return &resource->entry;
11424 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11425 struct mlx5_list_entry *entry)
11427 struct mlx5_flow_dv_sample_resource *resource =
11428 container_of(entry, typeof(*resource), entry);
11429 struct rte_eth_dev *dev = resource->dev;
11430 struct mlx5_priv *priv = dev->data->dev_private;
11432 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11436 * Find existing sample resource or create and register a new one.
11438 * @param[in, out] dev
11439 * Pointer to rte_eth_dev structure.
11441 * Pointer to sample resource reference.
11442 * @parm[in, out] dev_flow
11443 * Pointer to the dev_flow.
11444 * @param[out] error
11445 * pointer to error structure.
11448 * 0 on success otherwise -errno and errno is set.
11451 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11452 struct mlx5_flow_dv_sample_resource *ref,
11453 struct mlx5_flow *dev_flow,
11454 struct rte_flow_error *error)
11456 struct mlx5_flow_dv_sample_resource *resource;
11457 struct mlx5_list_entry *entry;
11458 struct mlx5_priv *priv = dev->data->dev_private;
11459 struct mlx5_flow_cb_ctx ctx = {
11465 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11468 resource = container_of(entry, typeof(*resource), entry);
11469 dev_flow->handle->dvh.rix_sample = resource->idx;
11470 dev_flow->dv.sample_res = resource;
11475 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11476 struct mlx5_list_entry *entry, void *cb_ctx)
11478 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11479 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11480 struct rte_eth_dev *dev = ctx->dev;
11481 struct mlx5_flow_dv_dest_array_resource *resource =
11482 container_of(entry, typeof(*resource), entry);
11485 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11486 ctx_resource->ft_type == resource->ft_type &&
11487 !memcmp((void *)resource->sample_act,
11488 (void *)ctx_resource->sample_act,
11489 (ctx_resource->num_of_dest *
11490 sizeof(struct mlx5_flow_sub_actions_list)))) {
11492 * Existing sample action should release the prepared
11493 * sub-actions reference counter.
11495 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11496 flow_dv_sample_sub_actions_release(dev,
11497 &ctx_resource->sample_idx[idx]);
11503 struct mlx5_list_entry *
11504 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11506 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11507 struct rte_eth_dev *dev = ctx->dev;
11508 struct mlx5_flow_dv_dest_array_resource *resource;
11509 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11510 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11511 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11512 struct mlx5_priv *priv = dev->data->dev_private;
11513 struct mlx5_dev_ctx_shared *sh = priv->sh;
11514 struct mlx5_flow_sub_actions_list *sample_act;
11515 struct mlx5dv_dr_domain *domain;
11516 uint32_t idx = 0, res_idx = 0;
11517 struct rte_flow_error *error = ctx->error;
11518 uint64_t action_flags;
11521 /* Register new destination array resource. */
11522 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11525 rte_flow_error_set(error, ENOMEM,
11526 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11528 "cannot allocate resource memory");
11531 *resource = *ctx_resource;
11532 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11533 domain = sh->fdb_domain;
11534 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11535 domain = sh->rx_domain;
11537 domain = sh->tx_domain;
11538 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11539 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11540 mlx5_malloc(MLX5_MEM_ZERO,
11541 sizeof(struct mlx5dv_dr_action_dest_attr),
11543 if (!dest_attr[idx]) {
11544 rte_flow_error_set(error, ENOMEM,
11545 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11547 "cannot allocate resource memory");
11550 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11551 sample_act = &ctx_resource->sample_act[idx];
11552 action_flags = sample_act->action_flags;
11553 switch (action_flags) {
11554 case MLX5_FLOW_ACTION_QUEUE:
11555 dest_attr[idx]->dest = sample_act->dr_queue_action;
11557 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11558 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11559 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11560 dest_attr[idx]->dest_reformat->reformat =
11561 sample_act->dr_encap_action;
11562 dest_attr[idx]->dest_reformat->dest =
11563 sample_act->dr_port_id_action;
11565 case MLX5_FLOW_ACTION_PORT_ID:
11566 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11568 case MLX5_FLOW_ACTION_JUMP:
11569 dest_attr[idx]->dest = sample_act->dr_jump_action;
11572 rte_flow_error_set(error, EINVAL,
11573 RTE_FLOW_ERROR_TYPE_ACTION,
11575 "unsupported actions type");
11579 /* create a dest array action */
11580 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11582 resource->num_of_dest,
11584 &resource->action);
11586 rte_flow_error_set(error, ENOMEM,
11587 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11589 "cannot create destination array action");
11592 resource->idx = res_idx;
11593 resource->dev = dev;
11594 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11595 mlx5_free(dest_attr[idx]);
11596 return &resource->entry;
11598 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11599 flow_dv_sample_sub_actions_release(dev,
11600 &resource->sample_idx[idx]);
11601 if (dest_attr[idx])
11602 mlx5_free(dest_attr[idx]);
11604 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11608 struct mlx5_list_entry *
11609 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11610 struct mlx5_list_entry *entry __rte_unused,
11613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11614 struct rte_eth_dev *dev = ctx->dev;
11615 struct mlx5_flow_dv_dest_array_resource *resource;
11616 struct mlx5_priv *priv = dev->data->dev_private;
11617 struct mlx5_dev_ctx_shared *sh = priv->sh;
11618 uint32_t res_idx = 0;
11619 struct rte_flow_error *error = ctx->error;
11621 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11624 rte_flow_error_set(error, ENOMEM,
11625 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11627 "cannot allocate dest-array memory");
11630 memcpy(resource, entry, sizeof(*resource));
11631 resource->idx = res_idx;
11632 resource->dev = dev;
11633 return &resource->entry;
11637 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11638 struct mlx5_list_entry *entry)
11640 struct mlx5_flow_dv_dest_array_resource *resource =
11641 container_of(entry, typeof(*resource), entry);
11642 struct rte_eth_dev *dev = resource->dev;
11643 struct mlx5_priv *priv = dev->data->dev_private;
11645 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11649 * Find existing destination array resource or create and register a new one.
11651 * @param[in, out] dev
11652 * Pointer to rte_eth_dev structure.
11654 * Pointer to destination array resource reference.
11655 * @parm[in, out] dev_flow
11656 * Pointer to the dev_flow.
11657 * @param[out] error
11658 * pointer to error structure.
11661 * 0 on success otherwise -errno and errno is set.
11664 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11665 struct mlx5_flow_dv_dest_array_resource *ref,
11666 struct mlx5_flow *dev_flow,
11667 struct rte_flow_error *error)
11669 struct mlx5_flow_dv_dest_array_resource *resource;
11670 struct mlx5_priv *priv = dev->data->dev_private;
11671 struct mlx5_list_entry *entry;
11672 struct mlx5_flow_cb_ctx ctx = {
11678 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11681 resource = container_of(entry, typeof(*resource), entry);
11682 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11683 dev_flow->dv.dest_array_res = resource;
11688 * Convert Sample action to DV specification.
11691 * Pointer to rte_eth_dev structure.
11692 * @param[in] action
11693 * Pointer to sample action structure.
11694 * @param[in, out] dev_flow
11695 * Pointer to the mlx5_flow.
11697 * Pointer to the flow attributes.
11698 * @param[in, out] num_of_dest
11699 * Pointer to the num of destination.
11700 * @param[in, out] sample_actions
11701 * Pointer to sample actions list.
11702 * @param[in, out] res
11703 * Pointer to sample resource.
11704 * @param[out] error
11705 * Pointer to the error structure.
11708 * 0 on success, a negative errno value otherwise and rte_errno is set.
11711 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11712 const struct rte_flow_action_sample *action,
11713 struct mlx5_flow *dev_flow,
11714 const struct rte_flow_attr *attr,
11715 uint32_t *num_of_dest,
11716 void **sample_actions,
11717 struct mlx5_flow_dv_sample_resource *res,
11718 struct rte_flow_error *error)
11720 struct mlx5_priv *priv = dev->data->dev_private;
11721 const struct rte_flow_action *sub_actions;
11722 struct mlx5_flow_sub_actions_list *sample_act;
11723 struct mlx5_flow_sub_actions_idx *sample_idx;
11724 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11725 struct rte_flow *flow = dev_flow->flow;
11726 struct mlx5_flow_rss_desc *rss_desc;
11727 uint64_t action_flags = 0;
11730 rss_desc = &wks->rss_desc;
11731 sample_act = &res->sample_act;
11732 sample_idx = &res->sample_idx;
11733 res->ratio = action->ratio;
11734 sub_actions = action->actions;
11735 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11736 int type = sub_actions->type;
11737 uint32_t pre_rix = 0;
11740 case RTE_FLOW_ACTION_TYPE_QUEUE:
11742 const struct rte_flow_action_queue *queue;
11743 struct mlx5_hrxq *hrxq;
11746 queue = sub_actions->conf;
11747 rss_desc->queue_num = 1;
11748 rss_desc->queue[0] = queue->index;
11749 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11750 rss_desc, &hrxq_idx);
11752 return rte_flow_error_set
11754 RTE_FLOW_ERROR_TYPE_ACTION,
11756 "cannot create fate queue");
11757 sample_act->dr_queue_action = hrxq->action;
11758 sample_idx->rix_hrxq = hrxq_idx;
11759 sample_actions[sample_act->actions_num++] =
11762 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11763 if (action_flags & MLX5_FLOW_ACTION_MARK)
11764 dev_flow->handle->rix_hrxq = hrxq_idx;
11765 dev_flow->handle->fate_action =
11766 MLX5_FLOW_FATE_QUEUE;
11769 case RTE_FLOW_ACTION_TYPE_RSS:
11771 struct mlx5_hrxq *hrxq;
11773 const struct rte_flow_action_rss *rss;
11774 const uint8_t *rss_key;
11776 rss = sub_actions->conf;
11777 memcpy(rss_desc->queue, rss->queue,
11778 rss->queue_num * sizeof(uint16_t));
11779 rss_desc->queue_num = rss->queue_num;
11780 /* NULL RSS key indicates default RSS key. */
11781 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11782 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11784 * rss->level and rss.types should be set in advance
11785 * when expanding items for RSS.
11787 flow_dv_hashfields_set(dev_flow->handle->layers,
11789 &dev_flow->hash_fields);
11790 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11791 rss_desc, &hrxq_idx);
11793 return rte_flow_error_set
11795 RTE_FLOW_ERROR_TYPE_ACTION,
11797 "cannot create fate queue");
11798 sample_act->dr_queue_action = hrxq->action;
11799 sample_idx->rix_hrxq = hrxq_idx;
11800 sample_actions[sample_act->actions_num++] =
11803 action_flags |= MLX5_FLOW_ACTION_RSS;
11804 if (action_flags & MLX5_FLOW_ACTION_MARK)
11805 dev_flow->handle->rix_hrxq = hrxq_idx;
11806 dev_flow->handle->fate_action =
11807 MLX5_FLOW_FATE_QUEUE;
11810 case RTE_FLOW_ACTION_TYPE_MARK:
11812 uint32_t tag_be = mlx5_flow_mark_set
11813 (((const struct rte_flow_action_mark *)
11814 (sub_actions->conf))->id);
11817 pre_rix = dev_flow->handle->dvh.rix_tag;
11818 /* Save the mark resource before sample */
11819 pre_r = dev_flow->dv.tag_resource;
11820 if (flow_dv_tag_resource_register(dev, tag_be,
11823 MLX5_ASSERT(dev_flow->dv.tag_resource);
11824 sample_act->dr_tag_action =
11825 dev_flow->dv.tag_resource->action;
11826 sample_idx->rix_tag =
11827 dev_flow->handle->dvh.rix_tag;
11828 sample_actions[sample_act->actions_num++] =
11829 sample_act->dr_tag_action;
11830 /* Recover the mark resource after sample */
11831 dev_flow->dv.tag_resource = pre_r;
11832 dev_flow->handle->dvh.rix_tag = pre_rix;
11833 action_flags |= MLX5_FLOW_ACTION_MARK;
11836 case RTE_FLOW_ACTION_TYPE_COUNT:
11838 if (!flow->counter) {
11840 flow_dv_translate_create_counter(dev,
11841 dev_flow, sub_actions->conf,
11843 if (!flow->counter)
11844 return rte_flow_error_set
11846 RTE_FLOW_ERROR_TYPE_ACTION,
11848 "cannot create counter"
11851 sample_act->dr_cnt_action =
11852 (flow_dv_counter_get_by_idx(dev,
11853 flow->counter, NULL))->action;
11854 sample_actions[sample_act->actions_num++] =
11855 sample_act->dr_cnt_action;
11856 action_flags |= MLX5_FLOW_ACTION_COUNT;
11859 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11860 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11862 struct mlx5_flow_dv_port_id_action_resource
11864 uint32_t port_id = 0;
11866 memset(&port_id_resource, 0, sizeof(port_id_resource));
11867 /* Save the port id resource before sample */
11868 pre_rix = dev_flow->handle->rix_port_id_action;
11869 pre_r = dev_flow->dv.port_id_action;
11870 if (flow_dv_translate_action_port_id(dev, sub_actions,
11873 port_id_resource.port_id = port_id;
11874 if (flow_dv_port_id_action_resource_register
11875 (dev, &port_id_resource, dev_flow, error))
11877 sample_act->dr_port_id_action =
11878 dev_flow->dv.port_id_action->action;
11879 sample_idx->rix_port_id_action =
11880 dev_flow->handle->rix_port_id_action;
11881 sample_actions[sample_act->actions_num++] =
11882 sample_act->dr_port_id_action;
11883 /* Recover the port id resource after sample */
11884 dev_flow->dv.port_id_action = pre_r;
11885 dev_flow->handle->rix_port_id_action = pre_rix;
11887 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11890 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11891 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11892 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11893 /* Save the encap resource before sample */
11894 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11895 pre_r = dev_flow->dv.encap_decap;
11896 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11901 sample_act->dr_encap_action =
11902 dev_flow->dv.encap_decap->action;
11903 sample_idx->rix_encap_decap =
11904 dev_flow->handle->dvh.rix_encap_decap;
11905 sample_actions[sample_act->actions_num++] =
11906 sample_act->dr_encap_action;
11907 /* Recover the encap resource after sample */
11908 dev_flow->dv.encap_decap = pre_r;
11909 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11910 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11913 return rte_flow_error_set(error, EINVAL,
11914 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11916 "Not support for sampler action");
11919 sample_act->action_flags = action_flags;
11920 res->ft_id = dev_flow->dv.group;
11921 if (attr->transfer) {
11923 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11924 uint64_t set_action;
11925 } action_ctx = { .set_action = 0 };
11927 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11928 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11929 MLX5_MODIFICATION_TYPE_SET);
11930 MLX5_SET(set_action_in, action_ctx.action_in, field,
11931 MLX5_MODI_META_REG_C_0);
11932 MLX5_SET(set_action_in, action_ctx.action_in, data,
11933 priv->vport_meta_tag);
11934 res->set_action = action_ctx.set_action;
11935 } else if (attr->ingress) {
11936 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11938 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11944 * Convert Sample action to DV specification.
11947 * Pointer to rte_eth_dev structure.
11948 * @param[in, out] dev_flow
11949 * Pointer to the mlx5_flow.
11950 * @param[in] num_of_dest
11951 * The num of destination.
11952 * @param[in, out] res
11953 * Pointer to sample resource.
11954 * @param[in, out] mdest_res
11955 * Pointer to destination array resource.
11956 * @param[in] sample_actions
11957 * Pointer to sample path actions list.
11958 * @param[in] action_flags
11959 * Holds the actions detected until now.
11960 * @param[out] error
11961 * Pointer to the error structure.
11964 * 0 on success, a negative errno value otherwise and rte_errno is set.
11967 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11968 struct mlx5_flow *dev_flow,
11969 uint32_t num_of_dest,
11970 struct mlx5_flow_dv_sample_resource *res,
11971 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11972 void **sample_actions,
11973 uint64_t action_flags,
11974 struct rte_flow_error *error)
11976 /* update normal path action resource into last index of array */
11977 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11978 struct mlx5_flow_sub_actions_list *sample_act =
11979 &mdest_res->sample_act[dest_index];
11980 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11981 struct mlx5_flow_rss_desc *rss_desc;
11982 uint32_t normal_idx = 0;
11983 struct mlx5_hrxq *hrxq;
11987 rss_desc = &wks->rss_desc;
11988 if (num_of_dest > 1) {
11989 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11990 /* Handle QP action for mirroring */
11991 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11992 rss_desc, &hrxq_idx);
11994 return rte_flow_error_set
11996 RTE_FLOW_ERROR_TYPE_ACTION,
11998 "cannot create rx queue");
12000 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
12001 sample_act->dr_queue_action = hrxq->action;
12002 if (action_flags & MLX5_FLOW_ACTION_MARK)
12003 dev_flow->handle->rix_hrxq = hrxq_idx;
12004 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12006 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
12008 mdest_res->sample_idx[dest_index].rix_encap_decap =
12009 dev_flow->handle->dvh.rix_encap_decap;
12010 sample_act->dr_encap_action =
12011 dev_flow->dv.encap_decap->action;
12012 dev_flow->handle->dvh.rix_encap_decap = 0;
12014 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
12016 mdest_res->sample_idx[dest_index].rix_port_id_action =
12017 dev_flow->handle->rix_port_id_action;
12018 sample_act->dr_port_id_action =
12019 dev_flow->dv.port_id_action->action;
12020 dev_flow->handle->rix_port_id_action = 0;
12022 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
12024 mdest_res->sample_idx[dest_index].rix_jump =
12025 dev_flow->handle->rix_jump;
12026 sample_act->dr_jump_action =
12027 dev_flow->dv.jump->action;
12028 dev_flow->handle->rix_jump = 0;
12030 sample_act->actions_num = normal_idx;
12031 /* update sample action resource into first index of array */
12032 mdest_res->ft_type = res->ft_type;
12033 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
12034 sizeof(struct mlx5_flow_sub_actions_idx));
12035 memcpy(&mdest_res->sample_act[0], &res->sample_act,
12036 sizeof(struct mlx5_flow_sub_actions_list));
12037 mdest_res->num_of_dest = num_of_dest;
12038 if (flow_dv_dest_array_resource_register(dev, mdest_res,
12040 return rte_flow_error_set(error, EINVAL,
12041 RTE_FLOW_ERROR_TYPE_ACTION,
12042 NULL, "can't create sample "
12045 res->sub_actions = sample_actions;
12046 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
12047 return rte_flow_error_set(error, EINVAL,
12048 RTE_FLOW_ERROR_TYPE_ACTION,
12050 "can't create sample action");
12056 * Remove an ASO age action from age actions list.
12059 * Pointer to the Ethernet device structure.
12061 * Pointer to the aso age action handler.
12064 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
12065 struct mlx5_aso_age_action *age)
12067 struct mlx5_age_info *age_info;
12068 struct mlx5_age_param *age_param = &age->age_params;
12069 struct mlx5_priv *priv = dev->data->dev_private;
12070 uint16_t expected = AGE_CANDIDATE;
12072 age_info = GET_PORT_AGE_INFO(priv);
12073 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
12074 AGE_FREE, false, __ATOMIC_RELAXED,
12075 __ATOMIC_RELAXED)) {
12077 * We need the lock even it is age timeout,
12078 * since age action may still in process.
12080 rte_spinlock_lock(&age_info->aged_sl);
12081 LIST_REMOVE(age, next);
12082 rte_spinlock_unlock(&age_info->aged_sl);
12083 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
12088 * Release an ASO age action.
12091 * Pointer to the Ethernet device structure.
12092 * @param[in] age_idx
12093 * Index of ASO age action to release.
12095 * True if the release operation is during flow destroy operation.
12096 * False if the release operation is during action destroy operation.
12099 * 0 when age action was removed, otherwise the number of references.
12102 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
12104 struct mlx5_priv *priv = dev->data->dev_private;
12105 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12106 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
12107 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
12110 flow_dv_aso_age_remove_from_age(dev, age);
12111 rte_spinlock_lock(&mng->free_sl);
12112 LIST_INSERT_HEAD(&mng->free, age, next);
12113 rte_spinlock_unlock(&mng->free_sl);
12119 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
12122 * Pointer to the Ethernet device structure.
12125 * 0 on success, otherwise negative errno value and rte_errno is set.
12128 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
12130 struct mlx5_priv *priv = dev->data->dev_private;
12131 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12132 void *old_pools = mng->pools;
12133 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
12134 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
12135 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12138 rte_errno = ENOMEM;
12142 memcpy(pools, old_pools,
12143 mng->n * sizeof(struct mlx5_flow_counter_pool *));
12144 mlx5_free(old_pools);
12146 /* First ASO flow hit allocation - starting ASO data-path. */
12147 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
12155 mng->pools = pools;
12160 * Create and initialize a new ASO aging pool.
12163 * Pointer to the Ethernet device structure.
12164 * @param[out] age_free
12165 * Where to put the pointer of a new age action.
12168 * The age actions pool pointer and @p age_free is set on success,
12169 * NULL otherwise and rte_errno is set.
12171 static struct mlx5_aso_age_pool *
12172 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12173 struct mlx5_aso_age_action **age_free)
12175 struct mlx5_priv *priv = dev->data->dev_private;
12176 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12177 struct mlx5_aso_age_pool *pool = NULL;
12178 struct mlx5_devx_obj *obj = NULL;
12181 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12182 priv->sh->cdev->pdn);
12184 rte_errno = ENODATA;
12185 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12188 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12190 claim_zero(mlx5_devx_cmd_destroy(obj));
12191 rte_errno = ENOMEM;
12194 pool->flow_hit_aso_obj = obj;
12195 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12196 rte_rwlock_write_lock(&mng->resize_rwl);
12197 pool->index = mng->next;
12198 /* Resize pools array if there is no room for the new pool in it. */
12199 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12200 claim_zero(mlx5_devx_cmd_destroy(obj));
12202 rte_rwlock_write_unlock(&mng->resize_rwl);
12205 mng->pools[pool->index] = pool;
12207 rte_rwlock_write_unlock(&mng->resize_rwl);
12208 /* Assign the first action in the new pool, the rest go to free list. */
12209 *age_free = &pool->actions[0];
12210 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12211 pool->actions[i].offset = i;
12212 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12218 * Allocate a ASO aging bit.
12221 * Pointer to the Ethernet device structure.
12222 * @param[out] error
12223 * Pointer to the error structure.
12226 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12229 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12231 struct mlx5_priv *priv = dev->data->dev_private;
12232 const struct mlx5_aso_age_pool *pool;
12233 struct mlx5_aso_age_action *age_free = NULL;
12234 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12237 /* Try to get the next free age action bit. */
12238 rte_spinlock_lock(&mng->free_sl);
12239 age_free = LIST_FIRST(&mng->free);
12241 LIST_REMOVE(age_free, next);
12242 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12243 rte_spinlock_unlock(&mng->free_sl);
12244 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12245 NULL, "failed to create ASO age pool");
12246 return 0; /* 0 is an error. */
12248 rte_spinlock_unlock(&mng->free_sl);
12249 pool = container_of
12250 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12251 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12253 if (!age_free->dr_action) {
12254 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12258 rte_flow_error_set(error, rte_errno,
12259 RTE_FLOW_ERROR_TYPE_ACTION,
12260 NULL, "failed to get reg_c "
12261 "for ASO flow hit");
12262 return 0; /* 0 is an error. */
12264 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12265 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12266 (priv->sh->rx_domain,
12267 pool->flow_hit_aso_obj->obj, age_free->offset,
12268 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12269 (reg_c - REG_C_0));
12270 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12271 if (!age_free->dr_action) {
12273 rte_spinlock_lock(&mng->free_sl);
12274 LIST_INSERT_HEAD(&mng->free, age_free, next);
12275 rte_spinlock_unlock(&mng->free_sl);
12276 rte_flow_error_set(error, rte_errno,
12277 RTE_FLOW_ERROR_TYPE_ACTION,
12278 NULL, "failed to create ASO "
12279 "flow hit action");
12280 return 0; /* 0 is an error. */
12283 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12284 return pool->index | ((age_free->offset + 1) << 16);
12288 * Initialize flow ASO age parameters.
12291 * Pointer to rte_eth_dev structure.
12292 * @param[in] age_idx
12293 * Index of ASO age action.
12294 * @param[in] context
12295 * Pointer to flow counter age context.
12296 * @param[in] timeout
12297 * Aging timeout in seconds.
12301 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12306 struct mlx5_aso_age_action *aso_age;
12308 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12309 MLX5_ASSERT(aso_age);
12310 aso_age->age_params.context = context;
12311 aso_age->age_params.timeout = timeout;
12312 aso_age->age_params.port_id = dev->data->port_id;
12313 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12315 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12320 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12321 const struct rte_flow_item_integrity *value,
12322 void *headers_m, void *headers_v)
12325 /* RTE l4_ok filter aggregates hardware l4_ok and
12326 * l4_checksum_ok filters.
12327 * Positive RTE l4_ok match requires hardware match on both L4
12328 * hardware integrity bits.
12329 * For negative match, check hardware l4_checksum_ok bit only,
12330 * because hardware sets that bit to 0 for all packets
12333 if (value->l4_ok) {
12334 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12337 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12338 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12341 if (mask->l4_csum_ok) {
12342 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12344 value->l4_csum_ok);
12349 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12350 const struct rte_flow_item_integrity *value,
12351 void *headers_m, void *headers_v, bool is_ipv4)
12354 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12355 * ipv4_csum_ok filters.
12356 * Positive RTE l3_ok match requires hardware match on both L3
12357 * hardware integrity bits.
12358 * For negative match, check hardware l3_csum_ok bit only,
12359 * because hardware sets that bit to 0 for all packets
12363 if (value->l3_ok) {
12364 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12366 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12369 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12370 ipv4_checksum_ok, 1);
12371 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12372 ipv4_checksum_ok, !!value->l3_ok);
12374 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12375 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12379 if (mask->ipv4_csum_ok) {
12380 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12381 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12382 value->ipv4_csum_ok);
12387 set_integrity_bits(void *headers_m, void *headers_v,
12388 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12390 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12391 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12393 /* Integrity bits validation cleared spec pointer */
12394 MLX5_ASSERT(spec != NULL);
12396 mask = &rte_flow_item_integrity_mask;
12397 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12399 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12403 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12405 struct rte_flow_item *integrity_items[2],
12406 uint64_t pattern_flags)
12408 void *headers_m, *headers_v;
12411 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12412 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12414 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12415 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12417 set_integrity_bits(headers_m, headers_v,
12418 integrity_items[1], is_l3_ip4);
12420 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12421 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12423 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12424 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12426 set_integrity_bits(headers_m, headers_v,
12427 integrity_items[0], is_l3_ip4);
12432 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12433 const struct rte_flow_item *integrity_items[2],
12434 uint64_t *last_item)
12436 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12438 /* integrity bits validation cleared spec pointer */
12439 MLX5_ASSERT(spec != NULL);
12440 if (spec->level > 1) {
12441 integrity_items[1] = item;
12442 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12444 integrity_items[0] = item;
12445 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12450 * Prepares DV flow counter with aging configuration.
12451 * Gets it by index when exists, creates a new one when doesn't.
12454 * Pointer to rte_eth_dev structure.
12455 * @param[in] dev_flow
12456 * Pointer to the mlx5_flow.
12457 * @param[in, out] flow
12458 * Pointer to the sub flow.
12460 * Pointer to the counter action configuration.
12462 * Pointer to the aging action configuration.
12463 * @param[out] error
12464 * Pointer to the error structure.
12467 * Pointer to the counter, NULL otherwise.
12469 static struct mlx5_flow_counter *
12470 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12471 struct mlx5_flow *dev_flow,
12472 struct rte_flow *flow,
12473 const struct rte_flow_action_count *count,
12474 const struct rte_flow_action_age *age,
12475 struct rte_flow_error *error)
12477 if (!flow->counter) {
12478 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12480 if (!flow->counter) {
12481 rte_flow_error_set(error, rte_errno,
12482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12483 "cannot create counter object.");
12487 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12491 * Release an ASO CT action by its own device.
12494 * Pointer to the Ethernet device structure.
12496 * Index of ASO CT action to release.
12499 * 0 when CT action was removed, otherwise the number of references.
12502 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12504 struct mlx5_priv *priv = dev->data->dev_private;
12505 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12507 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12508 enum mlx5_aso_ct_state state =
12509 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12511 /* Cannot release when CT is in the ASO SQ. */
12512 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12514 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12516 if (ct->dr_action_orig) {
12517 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12518 claim_zero(mlx5_glue->destroy_flow_action
12519 (ct->dr_action_orig));
12521 ct->dr_action_orig = NULL;
12523 if (ct->dr_action_rply) {
12524 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12525 claim_zero(mlx5_glue->destroy_flow_action
12526 (ct->dr_action_rply));
12528 ct->dr_action_rply = NULL;
12530 /* Clear the state to free, no need in 1st allocation. */
12531 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12532 rte_spinlock_lock(&mng->ct_sl);
12533 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12534 rte_spinlock_unlock(&mng->ct_sl);
12540 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12541 struct rte_flow_error *error)
12543 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12544 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12545 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12548 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12549 if (dev->data->dev_started != 1)
12550 return rte_flow_error_set(error, EAGAIN,
12551 RTE_FLOW_ERROR_TYPE_ACTION,
12553 "Indirect CT action cannot be destroyed when the port is stopped");
12554 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12556 return rte_flow_error_set(error, EAGAIN,
12557 RTE_FLOW_ERROR_TYPE_ACTION,
12559 "Current state prevents indirect CT action from being destroyed");
12564 * Resize the ASO CT pools array by 64 pools.
12567 * Pointer to the Ethernet device structure.
12570 * 0 on success, otherwise negative errno value and rte_errno is set.
12573 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12575 struct mlx5_priv *priv = dev->data->dev_private;
12576 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12577 void *old_pools = mng->pools;
12578 /* Magic number now, need a macro. */
12579 uint32_t resize = mng->n + 64;
12580 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12581 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12584 rte_errno = ENOMEM;
12587 rte_rwlock_write_lock(&mng->resize_rwl);
12588 /* ASO SQ/QP was already initialized in the startup. */
12590 /* Realloc could be an alternative choice. */
12591 rte_memcpy(pools, old_pools,
12592 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12593 mlx5_free(old_pools);
12596 mng->pools = pools;
12597 rte_rwlock_write_unlock(&mng->resize_rwl);
12602 * Create and initialize a new ASO CT pool.
12605 * Pointer to the Ethernet device structure.
12606 * @param[out] ct_free
12607 * Where to put the pointer of a new CT action.
12610 * The CT actions pool pointer and @p ct_free is set on success,
12611 * NULL otherwise and rte_errno is set.
12613 static struct mlx5_aso_ct_pool *
12614 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12615 struct mlx5_aso_ct_action **ct_free)
12617 struct mlx5_priv *priv = dev->data->dev_private;
12618 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12619 struct mlx5_aso_ct_pool *pool = NULL;
12620 struct mlx5_devx_obj *obj = NULL;
12622 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12624 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12625 priv->sh->cdev->pdn,
12628 rte_errno = ENODATA;
12629 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12632 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12634 rte_errno = ENOMEM;
12635 claim_zero(mlx5_devx_cmd_destroy(obj));
12638 pool->devx_obj = obj;
12639 pool->index = mng->next;
12640 /* Resize pools array if there is no room for the new pool in it. */
12641 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12642 claim_zero(mlx5_devx_cmd_destroy(obj));
12646 mng->pools[pool->index] = pool;
12648 /* Assign the first action in the new pool, the rest go to free list. */
12649 *ct_free = &pool->actions[0];
12650 /* Lock outside, the list operation is safe here. */
12651 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12652 /* refcnt is 0 when allocating the memory. */
12653 pool->actions[i].offset = i;
12654 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12660 * Allocate a ASO CT action from free list.
12663 * Pointer to the Ethernet device structure.
12664 * @param[out] error
12665 * Pointer to the error structure.
12668 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12671 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12673 struct mlx5_priv *priv = dev->data->dev_private;
12674 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12675 struct mlx5_aso_ct_action *ct = NULL;
12676 struct mlx5_aso_ct_pool *pool;
12681 if (!priv->sh->cdev->config.devx) {
12682 rte_errno = ENOTSUP;
12685 /* Get a free CT action, if no, a new pool will be created. */
12686 rte_spinlock_lock(&mng->ct_sl);
12687 ct = LIST_FIRST(&mng->free_cts);
12689 LIST_REMOVE(ct, next);
12690 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12691 rte_spinlock_unlock(&mng->ct_sl);
12692 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12693 NULL, "failed to create ASO CT pool");
12696 rte_spinlock_unlock(&mng->ct_sl);
12697 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12698 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12699 /* 0: inactive, 1: created, 2+: used by flows. */
12700 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12701 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12702 if (!ct->dr_action_orig) {
12703 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12704 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12705 (priv->sh->rx_domain, pool->devx_obj->obj,
12707 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12710 RTE_SET_USED(reg_c);
12712 if (!ct->dr_action_orig) {
12713 flow_dv_aso_ct_dev_release(dev, ct_idx);
12714 rte_flow_error_set(error, rte_errno,
12715 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12716 "failed to create ASO CT action");
12720 if (!ct->dr_action_rply) {
12721 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12722 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12723 (priv->sh->rx_domain, pool->devx_obj->obj,
12725 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12728 if (!ct->dr_action_rply) {
12729 flow_dv_aso_ct_dev_release(dev, ct_idx);
12730 rte_flow_error_set(error, rte_errno,
12731 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12732 "failed to create ASO CT action");
12740 * Create a conntrack object with context and actions by using ASO mechanism.
12743 * Pointer to rte_eth_dev structure.
12745 * Pointer to conntrack information profile.
12746 * @param[out] error
12747 * Pointer to the error structure.
12750 * Index to conntrack object on success, 0 otherwise.
12753 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12754 const struct rte_flow_action_conntrack *pro,
12755 struct rte_flow_error *error)
12757 struct mlx5_priv *priv = dev->data->dev_private;
12758 struct mlx5_dev_ctx_shared *sh = priv->sh;
12759 struct mlx5_aso_ct_action *ct;
12762 if (!sh->ct_aso_en)
12763 return rte_flow_error_set(error, ENOTSUP,
12764 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12765 "Connection is not supported");
12766 idx = flow_dv_aso_ct_alloc(dev, error);
12768 return rte_flow_error_set(error, rte_errno,
12769 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12770 "Failed to allocate CT object");
12771 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12772 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12773 return rte_flow_error_set(error, EBUSY,
12774 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12775 "Failed to update CT");
12776 ct->is_original = !!pro->is_original_dir;
12777 ct->peer = pro->peer_port;
12782 * Fill the flow with DV spec, lock free
12783 * (mutex should be acquired by caller).
12786 * Pointer to rte_eth_dev structure.
12787 * @param[in, out] dev_flow
12788 * Pointer to the sub flow.
12790 * Pointer to the flow attributes.
12792 * Pointer to the list of items.
12793 * @param[in] actions
12794 * Pointer to the list of actions.
12795 * @param[out] error
12796 * Pointer to the error structure.
12799 * 0 on success, a negative errno value otherwise and rte_errno is set.
12802 flow_dv_translate(struct rte_eth_dev *dev,
12803 struct mlx5_flow *dev_flow,
12804 const struct rte_flow_attr *attr,
12805 const struct rte_flow_item items[],
12806 const struct rte_flow_action actions[],
12807 struct rte_flow_error *error)
12809 struct mlx5_priv *priv = dev->data->dev_private;
12810 struct mlx5_sh_config *dev_conf = &priv->sh->config;
12811 struct rte_flow *flow = dev_flow->flow;
12812 struct mlx5_flow_handle *handle = dev_flow->handle;
12813 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12814 struct mlx5_flow_rss_desc *rss_desc;
12815 uint64_t item_flags = 0;
12816 uint64_t last_item = 0;
12817 uint64_t action_flags = 0;
12818 struct mlx5_flow_dv_matcher matcher = {
12820 .size = sizeof(matcher.mask.buf),
12824 bool actions_end = false;
12826 struct mlx5_flow_dv_modify_hdr_resource res;
12827 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12828 sizeof(struct mlx5_modification_cmd) *
12829 (MLX5_MAX_MODIFY_NUM + 1)];
12831 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12832 const struct rte_flow_action_count *count = NULL;
12833 const struct rte_flow_action_age *non_shared_age = NULL;
12834 union flow_dv_attr flow_attr = { .attr = 0 };
12836 union mlx5_flow_tbl_key tbl_key;
12837 uint32_t modify_action_position = UINT32_MAX;
12838 void *match_mask = matcher.mask.buf;
12839 void *match_value = dev_flow->dv.value.buf;
12840 uint8_t next_protocol = 0xff;
12841 struct rte_vlan_hdr vlan = { 0 };
12842 struct mlx5_flow_dv_dest_array_resource mdest_res;
12843 struct mlx5_flow_dv_sample_resource sample_res;
12844 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12845 const struct rte_flow_action_sample *sample = NULL;
12846 struct mlx5_flow_sub_actions_list *sample_act;
12847 uint32_t sample_act_pos = UINT32_MAX;
12848 uint32_t age_act_pos = UINT32_MAX;
12849 uint32_t num_of_dest = 0;
12850 int tmp_actions_n = 0;
12853 const struct mlx5_flow_tunnel *tunnel = NULL;
12854 struct flow_grp_info grp_info = {
12855 .external = !!dev_flow->external,
12856 .transfer = !!attr->transfer,
12857 .fdb_def_rule = !!priv->fdb_def_rule,
12858 .skip_scale = dev_flow->skip_scale &
12859 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12860 .std_tbl_fix = true,
12862 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12863 const struct rte_flow_item *tunnel_item = NULL;
12864 const struct rte_flow_item *gre_item = NULL;
12867 return rte_flow_error_set(error, ENOMEM,
12868 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12870 "failed to push flow workspace");
12871 rss_desc = &wks->rss_desc;
12872 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12873 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12874 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12875 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12876 /* update normal path action resource into last index of array */
12877 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12878 if (is_tunnel_offload_active(dev)) {
12879 if (dev_flow->tunnel) {
12880 RTE_VERIFY(dev_flow->tof_type ==
12881 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12882 tunnel = dev_flow->tunnel;
12884 tunnel = mlx5_get_tof(items, actions,
12885 &dev_flow->tof_type);
12886 dev_flow->tunnel = tunnel;
12888 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12889 (dev, attr, tunnel, dev_flow->tof_type);
12891 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12892 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12893 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12897 dev_flow->dv.group = table;
12898 if (attr->transfer)
12899 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12900 /* number of actions must be set to 0 in case of dirty stack. */
12901 mhdr_res->actions_num = 0;
12902 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12904 * do not add decap action if match rule drops packet
12905 * HW rejects rules with decap & drop
12907 * if tunnel match rule was inserted before matching tunnel set
12908 * rule flow table used in the match rule must be registered.
12909 * current implementation handles that in the
12910 * flow_dv_match_register() at the function end.
12912 bool add_decap = true;
12913 const struct rte_flow_action *ptr = actions;
12915 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12916 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12922 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12926 dev_flow->dv.actions[actions_n++] =
12927 dev_flow->dv.encap_decap->action;
12928 action_flags |= MLX5_FLOW_ACTION_DECAP;
12931 for (; !actions_end ; actions++) {
12932 const struct rte_flow_action_queue *queue;
12933 const struct rte_flow_action_rss *rss;
12934 const struct rte_flow_action *action = actions;
12935 const uint8_t *rss_key;
12936 struct mlx5_flow_tbl_resource *tbl;
12937 struct mlx5_aso_age_action *age_act;
12938 struct mlx5_flow_counter *cnt_act;
12939 uint32_t port_id = 0;
12940 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12941 int action_type = actions->type;
12942 const struct rte_flow_action *found_action = NULL;
12943 uint32_t jump_group = 0;
12944 uint32_t owner_idx;
12945 struct mlx5_aso_ct_action *ct;
12947 if (!mlx5_flow_os_action_supported(action_type))
12948 return rte_flow_error_set(error, ENOTSUP,
12949 RTE_FLOW_ERROR_TYPE_ACTION,
12951 "action not supported");
12952 switch (action_type) {
12953 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12954 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12956 case RTE_FLOW_ACTION_TYPE_VOID:
12958 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12959 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12960 if (flow_dv_translate_action_port_id(dev, action,
12963 port_id_resource.port_id = port_id;
12964 MLX5_ASSERT(!handle->rix_port_id_action);
12965 if (flow_dv_port_id_action_resource_register
12966 (dev, &port_id_resource, dev_flow, error))
12968 dev_flow->dv.actions[actions_n++] =
12969 dev_flow->dv.port_id_action->action;
12970 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12971 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12972 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12975 case RTE_FLOW_ACTION_TYPE_FLAG:
12976 action_flags |= MLX5_FLOW_ACTION_FLAG;
12978 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12979 struct rte_flow_action_mark mark = {
12980 .id = MLX5_FLOW_MARK_DEFAULT,
12983 if (flow_dv_convert_action_mark(dev, &mark,
12987 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12990 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12992 * Only one FLAG or MARK is supported per device flow
12993 * right now. So the pointer to the tag resource must be
12994 * zero before the register process.
12996 MLX5_ASSERT(!handle->dvh.rix_tag);
12997 if (flow_dv_tag_resource_register(dev, tag_be,
13000 MLX5_ASSERT(dev_flow->dv.tag_resource);
13001 dev_flow->dv.actions[actions_n++] =
13002 dev_flow->dv.tag_resource->action;
13004 case RTE_FLOW_ACTION_TYPE_MARK:
13005 action_flags |= MLX5_FLOW_ACTION_MARK;
13007 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
13008 const struct rte_flow_action_mark *mark =
13009 (const struct rte_flow_action_mark *)
13012 if (flow_dv_convert_action_mark(dev, mark,
13016 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
13020 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
13021 /* Legacy (non-extensive) MARK action. */
13022 tag_be = mlx5_flow_mark_set
13023 (((const struct rte_flow_action_mark *)
13024 (actions->conf))->id);
13025 MLX5_ASSERT(!handle->dvh.rix_tag);
13026 if (flow_dv_tag_resource_register(dev, tag_be,
13029 MLX5_ASSERT(dev_flow->dv.tag_resource);
13030 dev_flow->dv.actions[actions_n++] =
13031 dev_flow->dv.tag_resource->action;
13033 case RTE_FLOW_ACTION_TYPE_SET_META:
13034 if (flow_dv_convert_action_set_meta
13035 (dev, mhdr_res, attr,
13036 (const struct rte_flow_action_set_meta *)
13037 actions->conf, error))
13039 action_flags |= MLX5_FLOW_ACTION_SET_META;
13041 case RTE_FLOW_ACTION_TYPE_SET_TAG:
13042 if (flow_dv_convert_action_set_tag
13044 (const struct rte_flow_action_set_tag *)
13045 actions->conf, error))
13047 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13049 case RTE_FLOW_ACTION_TYPE_DROP:
13050 action_flags |= MLX5_FLOW_ACTION_DROP;
13051 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
13053 case RTE_FLOW_ACTION_TYPE_QUEUE:
13054 queue = actions->conf;
13055 rss_desc->queue_num = 1;
13056 rss_desc->queue[0] = queue->index;
13057 action_flags |= MLX5_FLOW_ACTION_QUEUE;
13058 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
13059 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
13062 case RTE_FLOW_ACTION_TYPE_RSS:
13063 rss = actions->conf;
13064 memcpy(rss_desc->queue, rss->queue,
13065 rss->queue_num * sizeof(uint16_t));
13066 rss_desc->queue_num = rss->queue_num;
13067 /* NULL RSS key indicates default RSS key. */
13068 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13069 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13071 * rss->level and rss.types should be set in advance
13072 * when expanding items for RSS.
13074 action_flags |= MLX5_FLOW_ACTION_RSS;
13075 dev_flow->handle->fate_action = rss_desc->shared_rss ?
13076 MLX5_FLOW_FATE_SHARED_RSS :
13077 MLX5_FLOW_FATE_QUEUE;
13079 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
13080 owner_idx = (uint32_t)(uintptr_t)action->conf;
13081 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
13082 if (flow->age == 0) {
13083 flow->age = owner_idx;
13084 __atomic_fetch_add(&age_act->refcnt, 1,
13087 age_act_pos = actions_n++;
13088 action_flags |= MLX5_FLOW_ACTION_AGE;
13090 case RTE_FLOW_ACTION_TYPE_AGE:
13091 non_shared_age = action->conf;
13092 age_act_pos = actions_n++;
13093 action_flags |= MLX5_FLOW_ACTION_AGE;
13095 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
13096 owner_idx = (uint32_t)(uintptr_t)action->conf;
13097 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
13099 MLX5_ASSERT(cnt_act != NULL);
13101 * When creating meter drop flow in drop table, the
13102 * counter should not overwrite the rte flow counter.
13104 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13105 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
13106 dev_flow->dv.actions[actions_n++] =
13109 if (flow->counter == 0) {
13110 flow->counter = owner_idx;
13112 (&cnt_act->shared_info.refcnt,
13113 1, __ATOMIC_RELAXED);
13115 /* Save information first, will apply later. */
13116 action_flags |= MLX5_FLOW_ACTION_COUNT;
13119 case RTE_FLOW_ACTION_TYPE_COUNT:
13120 if (!priv->sh->cdev->config.devx) {
13121 return rte_flow_error_set
13123 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13125 "count action not supported");
13127 /* Save information first, will apply later. */
13128 count = action->conf;
13129 action_flags |= MLX5_FLOW_ACTION_COUNT;
13131 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
13132 dev_flow->dv.actions[actions_n++] =
13133 priv->sh->pop_vlan_action;
13134 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
13136 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
13137 if (!(action_flags &
13138 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
13139 flow_dev_get_vlan_info_from_items(items, &vlan);
13140 vlan.eth_proto = rte_be_to_cpu_16
13141 ((((const struct rte_flow_action_of_push_vlan *)
13142 actions->conf)->ethertype));
13143 found_action = mlx5_flow_find_action
13145 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
13147 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13148 found_action = mlx5_flow_find_action
13150 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
13152 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13153 if (flow_dv_create_action_push_vlan
13154 (dev, attr, &vlan, dev_flow, error))
13156 dev_flow->dv.actions[actions_n++] =
13157 dev_flow->dv.push_vlan_res->action;
13158 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
13160 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
13161 /* of_vlan_push action handled this action */
13162 MLX5_ASSERT(action_flags &
13163 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13165 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13166 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13168 flow_dev_get_vlan_info_from_items(items, &vlan);
13169 mlx5_update_vlan_vid_pcp(actions, &vlan);
13170 /* If no VLAN push - this is a modify header action */
13171 if (flow_dv_convert_action_modify_vlan_vid
13172 (mhdr_res, actions, error))
13174 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13176 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13177 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13178 if (flow_dv_create_action_l2_encap(dev, actions,
13183 dev_flow->dv.actions[actions_n++] =
13184 dev_flow->dv.encap_decap->action;
13185 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13186 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13187 sample_act->action_flags |=
13188 MLX5_FLOW_ACTION_ENCAP;
13190 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13191 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13192 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13196 dev_flow->dv.actions[actions_n++] =
13197 dev_flow->dv.encap_decap->action;
13198 action_flags |= MLX5_FLOW_ACTION_DECAP;
13200 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13201 /* Handle encap with preceding decap. */
13202 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13203 if (flow_dv_create_action_raw_encap
13204 (dev, actions, dev_flow, attr, error))
13206 dev_flow->dv.actions[actions_n++] =
13207 dev_flow->dv.encap_decap->action;
13209 /* Handle encap without preceding decap. */
13210 if (flow_dv_create_action_l2_encap
13211 (dev, actions, dev_flow, attr->transfer,
13214 dev_flow->dv.actions[actions_n++] =
13215 dev_flow->dv.encap_decap->action;
13217 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13218 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13219 sample_act->action_flags |=
13220 MLX5_FLOW_ACTION_ENCAP;
13222 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13223 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13225 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13226 if (flow_dv_create_action_l2_decap
13227 (dev, dev_flow, attr->transfer, error))
13229 dev_flow->dv.actions[actions_n++] =
13230 dev_flow->dv.encap_decap->action;
13232 /* If decap is followed by encap, handle it at encap. */
13233 action_flags |= MLX5_FLOW_ACTION_DECAP;
13235 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13236 dev_flow->dv.actions[actions_n++] =
13237 (void *)(uintptr_t)action->conf;
13238 action_flags |= MLX5_FLOW_ACTION_JUMP;
13240 case RTE_FLOW_ACTION_TYPE_JUMP:
13241 jump_group = ((const struct rte_flow_action_jump *)
13242 action->conf)->group;
13243 grp_info.std_tbl_fix = 0;
13244 if (dev_flow->skip_scale &
13245 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13246 grp_info.skip_scale = 1;
13248 grp_info.skip_scale = 0;
13249 ret = mlx5_flow_group_to_table(dev, tunnel,
13255 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13257 !!dev_flow->external,
13258 tunnel, jump_group, 0,
13261 return rte_flow_error_set
13263 RTE_FLOW_ERROR_TYPE_ACTION,
13265 "cannot create jump action.");
13266 if (flow_dv_jump_tbl_resource_register
13267 (dev, tbl, dev_flow, error)) {
13268 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13269 return rte_flow_error_set
13271 RTE_FLOW_ERROR_TYPE_ACTION,
13273 "cannot create jump action.");
13275 dev_flow->dv.actions[actions_n++] =
13276 dev_flow->dv.jump->action;
13277 action_flags |= MLX5_FLOW_ACTION_JUMP;
13278 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13279 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13282 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13283 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13284 if (flow_dv_convert_action_modify_mac
13285 (mhdr_res, actions, error))
13287 action_flags |= actions->type ==
13288 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13289 MLX5_FLOW_ACTION_SET_MAC_SRC :
13290 MLX5_FLOW_ACTION_SET_MAC_DST;
13292 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13293 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13294 if (flow_dv_convert_action_modify_ipv4
13295 (mhdr_res, actions, error))
13297 action_flags |= actions->type ==
13298 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13299 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13300 MLX5_FLOW_ACTION_SET_IPV4_DST;
13302 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13303 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13304 if (flow_dv_convert_action_modify_ipv6
13305 (mhdr_res, actions, error))
13307 action_flags |= actions->type ==
13308 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13309 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13310 MLX5_FLOW_ACTION_SET_IPV6_DST;
13312 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13313 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13314 if (flow_dv_convert_action_modify_tp
13315 (mhdr_res, actions, items,
13316 &flow_attr, dev_flow, !!(action_flags &
13317 MLX5_FLOW_ACTION_DECAP), error))
13319 action_flags |= actions->type ==
13320 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13321 MLX5_FLOW_ACTION_SET_TP_SRC :
13322 MLX5_FLOW_ACTION_SET_TP_DST;
13324 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13325 if (flow_dv_convert_action_modify_dec_ttl
13326 (mhdr_res, items, &flow_attr, dev_flow,
13328 MLX5_FLOW_ACTION_DECAP), error))
13330 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13332 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13333 if (flow_dv_convert_action_modify_ttl
13334 (mhdr_res, actions, items, &flow_attr,
13335 dev_flow, !!(action_flags &
13336 MLX5_FLOW_ACTION_DECAP), error))
13338 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13340 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13341 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13342 if (flow_dv_convert_action_modify_tcp_seq
13343 (mhdr_res, actions, error))
13345 action_flags |= actions->type ==
13346 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13347 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13348 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13351 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13352 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13353 if (flow_dv_convert_action_modify_tcp_ack
13354 (mhdr_res, actions, error))
13356 action_flags |= actions->type ==
13357 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13358 MLX5_FLOW_ACTION_INC_TCP_ACK :
13359 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13361 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13362 if (flow_dv_convert_action_set_reg
13363 (mhdr_res, actions, error))
13365 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13367 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13368 if (flow_dv_convert_action_copy_mreg
13369 (dev, mhdr_res, actions, error))
13371 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13373 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13374 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13375 dev_flow->handle->fate_action =
13376 MLX5_FLOW_FATE_DEFAULT_MISS;
13378 case RTE_FLOW_ACTION_TYPE_METER:
13380 return rte_flow_error_set(error, rte_errno,
13381 RTE_FLOW_ERROR_TYPE_ACTION,
13382 NULL, "Failed to get meter in flow.");
13383 /* Set the meter action. */
13384 dev_flow->dv.actions[actions_n++] =
13385 wks->fm->meter_action;
13386 action_flags |= MLX5_FLOW_ACTION_METER;
13388 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13389 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13392 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13394 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13395 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13398 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13400 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13401 sample_act_pos = actions_n;
13402 sample = (const struct rte_flow_action_sample *)
13405 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13406 /* put encap action into group if work with port id */
13407 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13408 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13409 sample_act->action_flags |=
13410 MLX5_FLOW_ACTION_ENCAP;
13412 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13413 if (flow_dv_convert_action_modify_field
13414 (dev, mhdr_res, actions, attr, error))
13416 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13418 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13419 owner_idx = (uint32_t)(uintptr_t)action->conf;
13420 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13422 return rte_flow_error_set(error, EINVAL,
13423 RTE_FLOW_ERROR_TYPE_ACTION,
13425 "Failed to get CT object.");
13426 if (mlx5_aso_ct_available(priv->sh, ct))
13427 return rte_flow_error_set(error, rte_errno,
13428 RTE_FLOW_ERROR_TYPE_ACTION,
13430 "CT is unavailable.");
13431 if (ct->is_original)
13432 dev_flow->dv.actions[actions_n] =
13433 ct->dr_action_orig;
13435 dev_flow->dv.actions[actions_n] =
13436 ct->dr_action_rply;
13437 if (flow->ct == 0) {
13438 flow->indirect_type =
13439 MLX5_INDIRECT_ACTION_TYPE_CT;
13440 flow->ct = owner_idx;
13441 __atomic_fetch_add(&ct->refcnt, 1,
13445 action_flags |= MLX5_FLOW_ACTION_CT;
13447 case RTE_FLOW_ACTION_TYPE_END:
13448 actions_end = true;
13449 if (mhdr_res->actions_num) {
13450 /* create modify action if needed. */
13451 if (flow_dv_modify_hdr_resource_register
13452 (dev, mhdr_res, dev_flow, error))
13454 dev_flow->dv.actions[modify_action_position] =
13455 handle->dvh.modify_hdr->action;
13458 * Handle AGE and COUNT action by single HW counter
13459 * when they are not shared.
13461 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13462 if ((non_shared_age && count) ||
13463 !flow_hit_aso_supported(priv->sh, attr)) {
13464 /* Creates age by counters. */
13465 cnt_act = flow_dv_prepare_counter
13472 dev_flow->dv.actions[age_act_pos] =
13476 if (!flow->age && non_shared_age) {
13477 flow->age = flow_dv_aso_age_alloc
13481 flow_dv_aso_age_params_init
13483 non_shared_age->context ?
13484 non_shared_age->context :
13485 (void *)(uintptr_t)
13486 (dev_flow->flow_idx),
13487 non_shared_age->timeout);
13489 age_act = flow_aso_age_get_by_idx(dev,
13491 dev_flow->dv.actions[age_act_pos] =
13492 age_act->dr_action;
13494 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13496 * Create one count action, to be used
13497 * by all sub-flows.
13499 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13504 dev_flow->dv.actions[actions_n++] =
13510 if (mhdr_res->actions_num &&
13511 modify_action_position == UINT32_MAX)
13512 modify_action_position = actions_n++;
13514 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13515 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13516 int item_type = items->type;
13518 if (!mlx5_flow_os_item_supported(item_type))
13519 return rte_flow_error_set(error, ENOTSUP,
13520 RTE_FLOW_ERROR_TYPE_ITEM,
13521 NULL, "item not supported");
13522 switch (item_type) {
13523 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13524 flow_dv_translate_item_port_id
13525 (dev, match_mask, match_value, items, attr);
13526 last_item = MLX5_FLOW_ITEM_PORT_ID;
13528 case RTE_FLOW_ITEM_TYPE_ETH:
13529 flow_dv_translate_item_eth(match_mask, match_value,
13531 dev_flow->dv.group);
13532 matcher.priority = action_flags &
13533 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13534 !dev_flow->external ?
13535 MLX5_PRIORITY_MAP_L3 :
13536 MLX5_PRIORITY_MAP_L2;
13537 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13538 MLX5_FLOW_LAYER_OUTER_L2;
13540 case RTE_FLOW_ITEM_TYPE_VLAN:
13541 flow_dv_translate_item_vlan(dev_flow,
13542 match_mask, match_value,
13544 dev_flow->dv.group);
13545 matcher.priority = MLX5_PRIORITY_MAP_L2;
13546 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13547 MLX5_FLOW_LAYER_INNER_VLAN) :
13548 (MLX5_FLOW_LAYER_OUTER_L2 |
13549 MLX5_FLOW_LAYER_OUTER_VLAN);
13551 case RTE_FLOW_ITEM_TYPE_IPV4:
13552 mlx5_flow_tunnel_ip_check(items, next_protocol,
13553 &item_flags, &tunnel);
13554 flow_dv_translate_item_ipv4(match_mask, match_value,
13556 dev_flow->dv.group);
13557 matcher.priority = MLX5_PRIORITY_MAP_L3;
13558 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13559 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13560 if (items->mask != NULL &&
13561 ((const struct rte_flow_item_ipv4 *)
13562 items->mask)->hdr.next_proto_id) {
13564 ((const struct rte_flow_item_ipv4 *)
13565 (items->spec))->hdr.next_proto_id;
13567 ((const struct rte_flow_item_ipv4 *)
13568 (items->mask))->hdr.next_proto_id;
13570 /* Reset for inner layer. */
13571 next_protocol = 0xff;
13574 case RTE_FLOW_ITEM_TYPE_IPV6:
13575 mlx5_flow_tunnel_ip_check(items, next_protocol,
13576 &item_flags, &tunnel);
13577 flow_dv_translate_item_ipv6(match_mask, match_value,
13579 dev_flow->dv.group);
13580 matcher.priority = MLX5_PRIORITY_MAP_L3;
13581 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13582 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13583 if (items->mask != NULL &&
13584 ((const struct rte_flow_item_ipv6 *)
13585 items->mask)->hdr.proto) {
13587 ((const struct rte_flow_item_ipv6 *)
13588 items->spec)->hdr.proto;
13590 ((const struct rte_flow_item_ipv6 *)
13591 items->mask)->hdr.proto;
13593 /* Reset for inner layer. */
13594 next_protocol = 0xff;
13597 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13598 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13601 last_item = tunnel ?
13602 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13603 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13604 if (items->mask != NULL &&
13605 ((const struct rte_flow_item_ipv6_frag_ext *)
13606 items->mask)->hdr.next_header) {
13608 ((const struct rte_flow_item_ipv6_frag_ext *)
13609 items->spec)->hdr.next_header;
13611 ((const struct rte_flow_item_ipv6_frag_ext *)
13612 items->mask)->hdr.next_header;
13614 /* Reset for inner layer. */
13615 next_protocol = 0xff;
13618 case RTE_FLOW_ITEM_TYPE_TCP:
13619 flow_dv_translate_item_tcp(match_mask, match_value,
13621 matcher.priority = MLX5_PRIORITY_MAP_L4;
13622 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13623 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13625 case RTE_FLOW_ITEM_TYPE_UDP:
13626 flow_dv_translate_item_udp(match_mask, match_value,
13628 matcher.priority = MLX5_PRIORITY_MAP_L4;
13629 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13630 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13632 case RTE_FLOW_ITEM_TYPE_GRE:
13633 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13634 last_item = MLX5_FLOW_LAYER_GRE;
13635 tunnel_item = items;
13638 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13639 flow_dv_translate_item_gre_key(match_mask,
13640 match_value, items);
13641 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13643 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
13644 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13645 last_item = MLX5_FLOW_LAYER_GRE;
13646 tunnel_item = items;
13648 case RTE_FLOW_ITEM_TYPE_NVGRE:
13649 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13650 last_item = MLX5_FLOW_LAYER_GRE;
13651 tunnel_item = items;
13653 case RTE_FLOW_ITEM_TYPE_VXLAN:
13654 flow_dv_translate_item_vxlan(dev, attr,
13655 match_mask, match_value,
13657 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13658 last_item = MLX5_FLOW_LAYER_VXLAN;
13660 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13661 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13662 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13663 tunnel_item = items;
13665 case RTE_FLOW_ITEM_TYPE_GENEVE:
13666 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13667 last_item = MLX5_FLOW_LAYER_GENEVE;
13668 tunnel_item = items;
13670 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13671 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13675 return rte_flow_error_set(error, -ret,
13676 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13677 "cannot create GENEVE TLV option");
13678 flow->geneve_tlv_option = 1;
13679 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13681 case RTE_FLOW_ITEM_TYPE_MPLS:
13682 flow_dv_translate_item_mpls(match_mask, match_value,
13683 items, last_item, tunnel);
13684 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13685 last_item = MLX5_FLOW_LAYER_MPLS;
13687 case RTE_FLOW_ITEM_TYPE_MARK:
13688 flow_dv_translate_item_mark(dev, match_mask,
13689 match_value, items);
13690 last_item = MLX5_FLOW_ITEM_MARK;
13692 case RTE_FLOW_ITEM_TYPE_META:
13693 flow_dv_translate_item_meta(dev, match_mask,
13694 match_value, attr, items);
13695 last_item = MLX5_FLOW_ITEM_METADATA;
13697 case RTE_FLOW_ITEM_TYPE_ICMP:
13698 flow_dv_translate_item_icmp(match_mask, match_value,
13700 matcher.priority = MLX5_PRIORITY_MAP_L4;
13701 last_item = MLX5_FLOW_LAYER_ICMP;
13703 case RTE_FLOW_ITEM_TYPE_ICMP6:
13704 flow_dv_translate_item_icmp6(match_mask, match_value,
13706 matcher.priority = MLX5_PRIORITY_MAP_L4;
13707 last_item = MLX5_FLOW_LAYER_ICMP6;
13709 case RTE_FLOW_ITEM_TYPE_TAG:
13710 flow_dv_translate_item_tag(dev, match_mask,
13711 match_value, items);
13712 last_item = MLX5_FLOW_ITEM_TAG;
13714 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13715 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13716 match_value, items);
13717 last_item = MLX5_FLOW_ITEM_TAG;
13719 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13720 flow_dv_translate_item_tx_queue(dev, match_mask,
13723 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13725 case RTE_FLOW_ITEM_TYPE_GTP:
13726 flow_dv_translate_item_gtp(match_mask, match_value,
13728 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13729 last_item = MLX5_FLOW_LAYER_GTP;
13731 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13732 ret = flow_dv_translate_item_gtp_psc(match_mask,
13736 return rte_flow_error_set(error, -ret,
13737 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13738 "cannot create GTP PSC item");
13739 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13741 case RTE_FLOW_ITEM_TYPE_ECPRI:
13742 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13743 /* Create it only the first time to be used. */
13744 ret = mlx5_flex_parser_ecpri_alloc(dev);
13746 return rte_flow_error_set
13748 RTE_FLOW_ERROR_TYPE_ITEM,
13750 "cannot create eCPRI parser");
13752 flow_dv_translate_item_ecpri(dev, match_mask,
13753 match_value, items,
13755 /* No other protocol should follow eCPRI layer. */
13756 last_item = MLX5_FLOW_LAYER_ECPRI;
13758 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13759 flow_dv_translate_item_integrity(items, integrity_items,
13762 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13763 flow_dv_translate_item_aso_ct(dev, match_mask,
13764 match_value, items);
13766 case RTE_FLOW_ITEM_TYPE_FLEX:
13767 flow_dv_translate_item_flex(dev, match_mask,
13768 match_value, items,
13769 dev_flow, tunnel != 0);
13770 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13771 MLX5_FLOW_ITEM_OUTER_FLEX;
13776 item_flags |= last_item;
13779 * When E-Switch mode is enabled, we have two cases where we need to
13780 * set the source port manually.
13781 * The first one, is in case of NIC ingress steering rule, and the
13782 * second is E-Switch rule where no port_id item was found.
13783 * In both cases the source port is set according the current port
13786 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode &&
13787 !(attr->egress && !attr->transfer)) {
13788 if (flow_dv_translate_item_port_id(dev, match_mask,
13789 match_value, NULL, attr))
13792 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13793 flow_dv_translate_item_integrity_post(match_mask, match_value,
13797 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13798 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13799 tunnel_item, item_flags);
13800 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13801 flow_dv_translate_item_geneve(match_mask, match_value,
13802 tunnel_item, item_flags);
13803 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13804 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13805 flow_dv_translate_item_gre(match_mask, match_value,
13806 tunnel_item, item_flags);
13807 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13808 flow_dv_translate_item_nvgre(match_mask, match_value,
13809 tunnel_item, item_flags);
13810 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
13811 flow_dv_translate_item_gre_option(match_mask, match_value,
13812 tunnel_item, gre_item, item_flags);
13814 MLX5_ASSERT(false);
13816 #ifdef RTE_LIBRTE_MLX5_DEBUG
13817 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13818 dev_flow->dv.value.buf));
13821 * Layers may be already initialized from prefix flow if this dev_flow
13822 * is the suffix flow.
13824 handle->layers |= item_flags;
13825 if (action_flags & MLX5_FLOW_ACTION_RSS)
13826 flow_dv_hashfields_set(dev_flow->handle->layers,
13828 &dev_flow->hash_fields);
13829 /* If has RSS action in the sample action, the Sample/Mirror resource
13830 * should be registered after the hash filed be update.
13832 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13833 ret = flow_dv_translate_action_sample(dev,
13842 ret = flow_dv_create_action_sample(dev,
13851 return rte_flow_error_set
13853 RTE_FLOW_ERROR_TYPE_ACTION,
13855 "cannot create sample action");
13856 if (num_of_dest > 1) {
13857 dev_flow->dv.actions[sample_act_pos] =
13858 dev_flow->dv.dest_array_res->action;
13860 dev_flow->dv.actions[sample_act_pos] =
13861 dev_flow->dv.sample_res->verbs_action;
13865 * For multiple destination (sample action with ratio=1), the encap
13866 * action and port id action will be combined into group action.
13867 * So need remove the original these actions in the flow and only
13868 * use the sample action instead of.
13870 if (num_of_dest > 1 &&
13871 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13873 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13875 for (i = 0; i < actions_n; i++) {
13876 if ((sample_act->dr_encap_action &&
13877 sample_act->dr_encap_action ==
13878 dev_flow->dv.actions[i]) ||
13879 (sample_act->dr_port_id_action &&
13880 sample_act->dr_port_id_action ==
13881 dev_flow->dv.actions[i]) ||
13882 (sample_act->dr_jump_action &&
13883 sample_act->dr_jump_action ==
13884 dev_flow->dv.actions[i]))
13886 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13888 memcpy((void *)dev_flow->dv.actions,
13889 (void *)temp_actions,
13890 tmp_actions_n * sizeof(void *));
13891 actions_n = tmp_actions_n;
13893 dev_flow->dv.actions_n = actions_n;
13894 dev_flow->act_flags = action_flags;
13895 if (wks->skip_matcher_reg)
13897 /* Register matcher. */
13898 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13899 matcher.mask.size);
13900 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13902 dev_flow->external);
13904 * When creating meter drop flow in drop table, using original
13905 * 5-tuple match, the matcher priority should be lower than
13908 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13909 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13910 matcher.priority <= MLX5_REG_BITS)
13911 matcher.priority += MLX5_REG_BITS;
13912 /* reserved field no needs to be set to 0 here. */
13913 tbl_key.is_fdb = attr->transfer;
13914 tbl_key.is_egress = attr->egress;
13915 tbl_key.level = dev_flow->dv.group;
13916 tbl_key.id = dev_flow->dv.table_id;
13917 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13918 tunnel, attr->group, error))
13924 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13927 * @param[in, out] action
13928 * Shred RSS action holding hash RX queue objects.
13929 * @param[in] hash_fields
13930 * Defines combination of packet fields to participate in RX hash.
13931 * @param[in] tunnel
13933 * @param[in] hrxq_idx
13934 * Hash RX queue index to set.
13937 * 0 on success, otherwise negative errno value.
13940 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13941 const uint64_t hash_fields,
13944 uint32_t *hrxqs = action->hrxq;
13946 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13947 case MLX5_RSS_HASH_IPV4:
13948 /* fall-through. */
13949 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13950 /* fall-through. */
13951 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13952 hrxqs[0] = hrxq_idx;
13954 case MLX5_RSS_HASH_IPV4_TCP:
13955 /* fall-through. */
13956 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13957 /* fall-through. */
13958 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13959 hrxqs[1] = hrxq_idx;
13961 case MLX5_RSS_HASH_IPV4_UDP:
13962 /* fall-through. */
13963 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13964 /* fall-through. */
13965 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13966 hrxqs[2] = hrxq_idx;
13968 case MLX5_RSS_HASH_IPV6:
13969 /* fall-through. */
13970 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13971 /* fall-through. */
13972 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13973 hrxqs[3] = hrxq_idx;
13975 case MLX5_RSS_HASH_IPV6_TCP:
13976 /* fall-through. */
13977 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13978 /* fall-through. */
13979 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13980 hrxqs[4] = hrxq_idx;
13982 case MLX5_RSS_HASH_IPV6_UDP:
13983 /* fall-through. */
13984 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13985 /* fall-through. */
13986 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13987 hrxqs[5] = hrxq_idx;
13989 case MLX5_RSS_HASH_NONE:
13990 hrxqs[6] = hrxq_idx;
13998 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
14002 * Pointer to the Ethernet device structure.
14004 * Shared RSS action ID holding hash RX queue objects.
14005 * @param[in] hash_fields
14006 * Defines combination of packet fields to participate in RX hash.
14007 * @param[in] tunnel
14011 * Valid hash RX queue index, otherwise 0.
14014 flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
14015 const uint64_t hash_fields)
14017 struct mlx5_priv *priv = dev->data->dev_private;
14018 struct mlx5_shared_action_rss *shared_rss =
14019 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14020 const uint32_t *hrxqs = shared_rss->hrxq;
14022 switch (hash_fields & ~IBV_RX_HASH_INNER) {
14023 case MLX5_RSS_HASH_IPV4:
14024 /* fall-through. */
14025 case MLX5_RSS_HASH_IPV4_DST_ONLY:
14026 /* fall-through. */
14027 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
14029 case MLX5_RSS_HASH_IPV4_TCP:
14030 /* fall-through. */
14031 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
14032 /* fall-through. */
14033 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
14035 case MLX5_RSS_HASH_IPV4_UDP:
14036 /* fall-through. */
14037 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
14038 /* fall-through. */
14039 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
14041 case MLX5_RSS_HASH_IPV6:
14042 /* fall-through. */
14043 case MLX5_RSS_HASH_IPV6_DST_ONLY:
14044 /* fall-through. */
14045 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
14047 case MLX5_RSS_HASH_IPV6_TCP:
14048 /* fall-through. */
14049 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
14050 /* fall-through. */
14051 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
14053 case MLX5_RSS_HASH_IPV6_UDP:
14054 /* fall-through. */
14055 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
14056 /* fall-through. */
14057 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
14059 case MLX5_RSS_HASH_NONE:
14068 * Apply the flow to the NIC, lock free,
14069 * (mutex should be acquired by caller).
14072 * Pointer to the Ethernet device structure.
14073 * @param[in, out] flow
14074 * Pointer to flow structure.
14075 * @param[out] error
14076 * Pointer to error structure.
14079 * 0 on success, a negative errno value otherwise and rte_errno is set.
14082 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
14083 struct rte_flow_error *error)
14085 struct mlx5_flow_dv_workspace *dv;
14086 struct mlx5_flow_handle *dh;
14087 struct mlx5_flow_handle_dv *dv_h;
14088 struct mlx5_flow *dev_flow;
14089 struct mlx5_priv *priv = dev->data->dev_private;
14090 uint32_t handle_idx;
14094 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
14095 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
14099 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
14100 dev_flow = &wks->flows[idx];
14101 dv = &dev_flow->dv;
14102 dh = dev_flow->handle;
14105 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
14106 if (dv->transfer) {
14107 MLX5_ASSERT(priv->sh->dr_drop_action);
14108 dv->actions[n++] = priv->sh->dr_drop_action;
14110 #ifdef HAVE_MLX5DV_DR
14111 /* DR supports drop action placeholder. */
14112 MLX5_ASSERT(priv->sh->dr_drop_action);
14113 dv->actions[n++] = dv->group ?
14114 priv->sh->dr_drop_action :
14115 priv->root_drop_action;
14117 /* For DV we use the explicit drop queue. */
14118 MLX5_ASSERT(priv->drop_queue.hrxq);
14120 priv->drop_queue.hrxq->action;
14123 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
14124 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
14125 struct mlx5_hrxq *hrxq;
14128 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
14133 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14134 "cannot get hash queue");
14137 dh->rix_hrxq = hrxq_idx;
14138 dv->actions[n++] = hrxq->action;
14139 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14140 struct mlx5_hrxq *hrxq = NULL;
14143 hrxq_idx = flow_dv_action_rss_hrxq_lookup(dev,
14144 rss_desc->shared_rss,
14145 dev_flow->hash_fields);
14147 hrxq = mlx5_ipool_get
14148 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
14153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14154 "cannot get hash queue");
14157 dh->rix_srss = rss_desc->shared_rss;
14158 dv->actions[n++] = hrxq->action;
14159 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
14160 if (!priv->sh->default_miss_action) {
14163 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14164 "default miss action not be created.");
14167 dv->actions[n++] = priv->sh->default_miss_action;
14169 misc_mask = flow_dv_matcher_enable(dv->value.buf);
14170 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
14171 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
14172 (void *)&dv->value, n,
14173 dv->actions, &dh->drv_flow);
14177 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14179 (!priv->sh->config.allow_duplicate_pattern &&
14181 "duplicating pattern is not allowed" :
14182 "hardware refuses to create flow");
14185 if (priv->vmwa_context &&
14186 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14188 * The rule contains the VLAN pattern.
14189 * For VF we are going to create VLAN
14190 * interface to make hypervisor set correct
14191 * e-Switch vport context.
14193 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14198 err = rte_errno; /* Save rte_errno before cleanup. */
14199 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14200 handle_idx, dh, next) {
14201 /* hrxq is union, don't clear it if the flag is not set. */
14202 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14203 mlx5_hrxq_release(dev, dh->rix_hrxq);
14205 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14208 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14209 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14211 rte_errno = err; /* Restore rte_errno. */
14216 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14217 struct mlx5_list_entry *entry)
14219 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14223 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14224 mlx5_free(resource);
14228 * Release the flow matcher.
14231 * Pointer to Ethernet device.
14233 * Index to port ID action resource.
14236 * 1 while a reference on it exists, 0 when freed.
14239 flow_dv_matcher_release(struct rte_eth_dev *dev,
14240 struct mlx5_flow_handle *handle)
14242 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14243 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14244 typeof(*tbl), tbl);
14247 MLX5_ASSERT(matcher->matcher_object);
14248 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14249 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14254 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14256 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14257 struct mlx5_flow_dv_encap_decap_resource *res =
14258 container_of(entry, typeof(*res), entry);
14260 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14261 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14265 * Release an encap/decap resource.
14268 * Pointer to Ethernet device.
14269 * @param encap_decap_idx
14270 * Index of encap decap resource.
14273 * 1 while a reference on it exists, 0 when freed.
14276 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14277 uint32_t encap_decap_idx)
14279 struct mlx5_priv *priv = dev->data->dev_private;
14280 struct mlx5_flow_dv_encap_decap_resource *resource;
14282 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14286 MLX5_ASSERT(resource->action);
14287 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14291 * Release an jump to table action resource.
14294 * Pointer to Ethernet device.
14296 * Index to the jump action resource.
14299 * 1 while a reference on it exists, 0 when freed.
14302 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14305 struct mlx5_priv *priv = dev->data->dev_private;
14306 struct mlx5_flow_tbl_data_entry *tbl_data;
14308 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14312 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14316 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14318 struct mlx5_flow_dv_modify_hdr_resource *res =
14319 container_of(entry, typeof(*res), entry);
14320 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14322 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14323 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14327 * Release a modify-header resource.
14330 * Pointer to Ethernet device.
14332 * Pointer to mlx5_flow_handle.
14335 * 1 while a reference on it exists, 0 when freed.
14338 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14339 struct mlx5_flow_handle *handle)
14341 struct mlx5_priv *priv = dev->data->dev_private;
14342 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14344 MLX5_ASSERT(entry->action);
14345 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14349 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14351 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14352 struct mlx5_flow_dv_port_id_action_resource *resource =
14353 container_of(entry, typeof(*resource), entry);
14355 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14356 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14360 * Release port ID action resource.
14363 * Pointer to Ethernet device.
14365 * Pointer to mlx5_flow_handle.
14368 * 1 while a reference on it exists, 0 when freed.
14371 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14374 struct mlx5_priv *priv = dev->data->dev_private;
14375 struct mlx5_flow_dv_port_id_action_resource *resource;
14377 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14380 MLX5_ASSERT(resource->action);
14381 return mlx5_list_unregister(priv->sh->port_id_action_list,
14386 * Release shared RSS action resource.
14389 * Pointer to Ethernet device.
14391 * Shared RSS action index.
14394 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14396 struct mlx5_priv *priv = dev->data->dev_private;
14397 struct mlx5_shared_action_rss *shared_rss;
14399 shared_rss = mlx5_ipool_get
14400 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14401 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14405 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14407 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14408 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14409 container_of(entry, typeof(*resource), entry);
14411 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14412 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14416 * Release push vlan action resource.
14419 * Pointer to Ethernet device.
14421 * Pointer to mlx5_flow_handle.
14424 * 1 while a reference on it exists, 0 when freed.
14427 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14428 struct mlx5_flow_handle *handle)
14430 struct mlx5_priv *priv = dev->data->dev_private;
14431 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14432 uint32_t idx = handle->dvh.rix_push_vlan;
14434 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14437 MLX5_ASSERT(resource->action);
14438 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14443 * Release the fate resource.
14446 * Pointer to Ethernet device.
14448 * Pointer to mlx5_flow_handle.
14451 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14452 struct mlx5_flow_handle *handle)
14454 if (!handle->rix_fate)
14456 switch (handle->fate_action) {
14457 case MLX5_FLOW_FATE_QUEUE:
14458 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14459 mlx5_hrxq_release(dev, handle->rix_hrxq);
14461 case MLX5_FLOW_FATE_JUMP:
14462 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14464 case MLX5_FLOW_FATE_PORT_ID:
14465 flow_dv_port_id_action_resource_release(dev,
14466 handle->rix_port_id_action);
14469 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14472 handle->rix_fate = 0;
14476 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14477 struct mlx5_list_entry *entry)
14479 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14482 struct rte_eth_dev *dev = resource->dev;
14483 struct mlx5_priv *priv = dev->data->dev_private;
14485 if (resource->verbs_action)
14486 claim_zero(mlx5_flow_os_destroy_flow_action
14487 (resource->verbs_action));
14488 if (resource->normal_path_tbl)
14489 flow_dv_tbl_resource_release(MLX5_SH(dev),
14490 resource->normal_path_tbl);
14491 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14492 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14493 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14497 * Release an sample resource.
14500 * Pointer to Ethernet device.
14502 * Pointer to mlx5_flow_handle.
14505 * 1 while a reference on it exists, 0 when freed.
14508 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14509 struct mlx5_flow_handle *handle)
14511 struct mlx5_priv *priv = dev->data->dev_private;
14512 struct mlx5_flow_dv_sample_resource *resource;
14514 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14515 handle->dvh.rix_sample);
14518 MLX5_ASSERT(resource->verbs_action);
14519 return mlx5_list_unregister(priv->sh->sample_action_list,
14524 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14525 struct mlx5_list_entry *entry)
14527 struct mlx5_flow_dv_dest_array_resource *resource =
14528 container_of(entry, typeof(*resource), entry);
14529 struct rte_eth_dev *dev = resource->dev;
14530 struct mlx5_priv *priv = dev->data->dev_private;
14533 MLX5_ASSERT(resource->action);
14534 if (resource->action)
14535 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14536 for (; i < resource->num_of_dest; i++)
14537 flow_dv_sample_sub_actions_release(dev,
14538 &resource->sample_idx[i]);
14539 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14540 DRV_LOG(DEBUG, "destination array resource %p: removed",
14545 * Release an destination array resource.
14548 * Pointer to Ethernet device.
14550 * Pointer to mlx5_flow_handle.
14553 * 1 while a reference on it exists, 0 when freed.
14556 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14557 struct mlx5_flow_handle *handle)
14559 struct mlx5_priv *priv = dev->data->dev_private;
14560 struct mlx5_flow_dv_dest_array_resource *resource;
14562 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14563 handle->dvh.rix_dest_array);
14566 MLX5_ASSERT(resource->action);
14567 return mlx5_list_unregister(priv->sh->dest_array_list,
14572 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14574 struct mlx5_priv *priv = dev->data->dev_private;
14575 struct mlx5_dev_ctx_shared *sh = priv->sh;
14576 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14577 sh->geneve_tlv_option_resource;
14578 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14579 if (geneve_opt_resource) {
14580 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14581 __ATOMIC_RELAXED))) {
14582 claim_zero(mlx5_devx_cmd_destroy
14583 (geneve_opt_resource->obj));
14584 mlx5_free(sh->geneve_tlv_option_resource);
14585 sh->geneve_tlv_option_resource = NULL;
14588 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14592 * Remove the flow from the NIC but keeps it in memory.
14593 * Lock free, (mutex should be acquired by caller).
14596 * Pointer to Ethernet device.
14597 * @param[in, out] flow
14598 * Pointer to flow structure.
14601 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14603 struct mlx5_flow_handle *dh;
14604 uint32_t handle_idx;
14605 struct mlx5_priv *priv = dev->data->dev_private;
14609 handle_idx = flow->dev_handles;
14610 while (handle_idx) {
14611 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14615 if (dh->drv_flow) {
14616 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14617 dh->drv_flow = NULL;
14619 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14620 flow_dv_fate_resource_release(dev, dh);
14621 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14622 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14623 handle_idx = dh->next.next;
14628 * Remove the flow from the NIC and the memory.
14629 * Lock free, (mutex should be acquired by caller).
14632 * Pointer to the Ethernet device structure.
14633 * @param[in, out] flow
14634 * Pointer to flow structure.
14637 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14639 struct mlx5_flow_handle *dev_handle;
14640 struct mlx5_priv *priv = dev->data->dev_private;
14641 struct mlx5_flow_meter_info *fm = NULL;
14646 flow_dv_remove(dev, flow);
14647 if (flow->counter) {
14648 flow_dv_counter_free(dev, flow->counter);
14652 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14654 mlx5_flow_meter_detach(priv, fm);
14657 /* Keep the current age handling by default. */
14658 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14659 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14660 else if (flow->age)
14661 flow_dv_aso_age_release(dev, flow->age);
14662 if (flow->geneve_tlv_option) {
14663 flow_dv_geneve_tlv_option_resource_release(dev);
14664 flow->geneve_tlv_option = 0;
14666 while (flow->dev_handles) {
14667 uint32_t tmp_idx = flow->dev_handles;
14669 dev_handle = mlx5_ipool_get(priv->sh->ipool
14670 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14673 flow->dev_handles = dev_handle->next.next;
14674 while (dev_handle->flex_item) {
14675 int index = rte_bsf32(dev_handle->flex_item);
14677 mlx5_flex_release_index(dev, index);
14678 dev_handle->flex_item &= ~(uint8_t)RTE_BIT32(index);
14680 if (dev_handle->dvh.matcher)
14681 flow_dv_matcher_release(dev, dev_handle);
14682 if (dev_handle->dvh.rix_sample)
14683 flow_dv_sample_resource_release(dev, dev_handle);
14684 if (dev_handle->dvh.rix_dest_array)
14685 flow_dv_dest_array_resource_release(dev, dev_handle);
14686 if (dev_handle->dvh.rix_encap_decap)
14687 flow_dv_encap_decap_resource_release(dev,
14688 dev_handle->dvh.rix_encap_decap);
14689 if (dev_handle->dvh.modify_hdr)
14690 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14691 if (dev_handle->dvh.rix_push_vlan)
14692 flow_dv_push_vlan_action_resource_release(dev,
14694 if (dev_handle->dvh.rix_tag)
14695 flow_dv_tag_release(dev,
14696 dev_handle->dvh.rix_tag);
14697 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14698 flow_dv_fate_resource_release(dev, dev_handle);
14700 srss = dev_handle->rix_srss;
14701 if (fm && dev_handle->is_meter_flow_id &&
14702 dev_handle->split_flow_id)
14703 mlx5_ipool_free(fm->flow_ipool,
14704 dev_handle->split_flow_id);
14705 else if (dev_handle->split_flow_id &&
14706 !dev_handle->is_meter_flow_id)
14707 mlx5_ipool_free(priv->sh->ipool
14708 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14709 dev_handle->split_flow_id);
14710 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14714 flow_dv_shared_rss_action_release(dev, srss);
14718 * Release array of hash RX queue objects.
14722 * Pointer to the Ethernet device structure.
14723 * @param[in, out] hrxqs
14724 * Array of hash RX queue objects.
14727 * Total number of references to hash RX queue objects in *hrxqs* array
14728 * after this operation.
14731 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14732 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14737 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14738 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14748 * Release all hash RX queue objects representing shared RSS action.
14751 * Pointer to the Ethernet device structure.
14752 * @param[in, out] action
14753 * Shared RSS action to remove hash RX queue objects from.
14756 * Total number of references to hash RX queue objects stored in *action*
14757 * after this operation.
14758 * Expected to be 0 if no external references held.
14761 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14762 struct mlx5_shared_action_rss *shared_rss)
14764 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14768 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14771 * Only one hash value is available for one L3+L4 combination:
14773 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14774 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14775 * same slot in mlx5_rss_hash_fields.
14777 * @param[in] rss_types
14779 * @param[in, out] hash_field
14780 * hash_field variable needed to be adjusted.
14786 flow_dv_action_rss_l34_hash_adjust(uint64_t rss_types,
14787 uint64_t *hash_field)
14789 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14790 case MLX5_RSS_HASH_IPV4:
14791 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14792 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14793 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14794 *hash_field |= IBV_RX_HASH_DST_IPV4;
14795 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14796 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14798 *hash_field |= MLX5_RSS_HASH_IPV4;
14801 case MLX5_RSS_HASH_IPV6:
14802 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14803 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14804 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14805 *hash_field |= IBV_RX_HASH_DST_IPV6;
14806 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14807 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14809 *hash_field |= MLX5_RSS_HASH_IPV6;
14812 case MLX5_RSS_HASH_IPV4_UDP:
14813 /* fall-through. */
14814 case MLX5_RSS_HASH_IPV6_UDP:
14815 if (rss_types & RTE_ETH_RSS_UDP) {
14816 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14817 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14818 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14819 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14820 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14822 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14825 case MLX5_RSS_HASH_IPV4_TCP:
14826 /* fall-through. */
14827 case MLX5_RSS_HASH_IPV6_TCP:
14828 if (rss_types & RTE_ETH_RSS_TCP) {
14829 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14830 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14831 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14832 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14833 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14835 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14844 * Setup shared RSS action.
14845 * Prepare set of hash RX queue objects sufficient to handle all valid
14846 * hash_fields combinations (see enum ibv_rx_hash_fields).
14849 * Pointer to the Ethernet device structure.
14850 * @param[in] action_idx
14851 * Shared RSS action ipool index.
14852 * @param[in, out] action
14853 * Partially initialized shared RSS action.
14854 * @param[out] error
14855 * Perform verbose error reporting if not NULL. Initialized in case of
14859 * 0 on success, otherwise negative errno value.
14862 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14863 uint32_t action_idx,
14864 struct mlx5_shared_action_rss *shared_rss,
14865 struct rte_flow_error *error)
14867 struct mlx5_priv *priv = dev->data->dev_private;
14868 struct mlx5_flow_rss_desc rss_desc = { 0 };
14872 shared_rss->ind_tbl = mlx5_ind_table_obj_new
14873 (dev, shared_rss->origin.queue,
14874 shared_rss->origin.queue_num,
14876 !!dev->data->dev_started);
14877 if (!shared_rss->ind_tbl)
14878 return rte_flow_error_set(error, rte_errno,
14879 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14880 "cannot setup indirection table");
14881 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14882 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14883 rss_desc.const_q = shared_rss->origin.queue;
14884 rss_desc.queue_num = shared_rss->origin.queue_num;
14885 /* Set non-zero value to indicate a shared RSS. */
14886 rss_desc.shared_rss = action_idx;
14887 rss_desc.ind_tbl = shared_rss->ind_tbl;
14888 if (priv->sh->config.dv_flow_en == 2)
14889 rss_desc.hws_flags = MLX5DR_ACTION_FLAG_HWS_RX;
14890 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14891 struct mlx5_hrxq *hrxq;
14892 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14895 flow_dv_action_rss_l34_hash_adjust(shared_rss->origin.types,
14897 if (shared_rss->origin.level > 1) {
14898 hash_fields |= IBV_RX_HASH_INNER;
14901 rss_desc.tunnel = tunnel;
14902 rss_desc.hash_fields = hash_fields;
14903 hrxq = mlx5_hrxq_get(dev, &rss_desc);
14907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14908 "cannot get hash queue");
14909 goto error_hrxq_new;
14911 err = __flow_dv_action_rss_hrxq_set
14912 (shared_rss, hash_fields, hrxq->idx);
14918 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14919 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14920 shared_rss->ind_tbl = NULL;
14926 * Create shared RSS action.
14929 * Pointer to the Ethernet device structure.
14931 * Shared action configuration.
14933 * RSS action specification used to create shared action.
14934 * @param[out] error
14935 * Perform verbose error reporting if not NULL. Initialized in case of
14939 * A valid shared action ID in case of success, 0 otherwise and
14940 * rte_errno is set.
14943 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14944 const struct rte_flow_indir_action_conf *conf,
14945 const struct rte_flow_action_rss *rss,
14946 struct rte_flow_error *error)
14948 struct mlx5_priv *priv = dev->data->dev_private;
14949 struct mlx5_shared_action_rss *shared_rss = NULL;
14950 struct rte_flow_action_rss *origin;
14951 const uint8_t *rss_key;
14954 RTE_SET_USED(conf);
14955 shared_rss = mlx5_ipool_zmalloc
14956 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14958 rte_flow_error_set(error, ENOMEM,
14959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14960 "cannot allocate resource memory");
14961 goto error_rss_init;
14963 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14964 rte_flow_error_set(error, E2BIG,
14965 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14966 "rss action number out of range");
14967 goto error_rss_init;
14969 origin = &shared_rss->origin;
14970 origin->func = rss->func;
14971 origin->level = rss->level;
14972 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14973 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14974 /* NULL RSS key indicates default RSS key. */
14975 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14976 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14977 origin->key = &shared_rss->key[0];
14978 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14979 origin->queue = rss->queue;
14980 origin->queue_num = rss->queue_num;
14981 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14982 goto error_rss_init;
14983 /* Update queue with indirect table queue memoyr. */
14984 origin->queue = shared_rss->ind_tbl->queues;
14985 rte_spinlock_init(&shared_rss->action_rss_sl);
14986 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14987 rte_spinlock_lock(&priv->shared_act_sl);
14988 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14989 &priv->rss_shared_actions, idx, shared_rss, next);
14990 rte_spinlock_unlock(&priv->shared_act_sl);
14994 if (shared_rss->ind_tbl)
14995 mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
14996 !!dev->data->dev_started);
14997 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15004 * Destroy the shared RSS action.
15005 * Release related hash RX queue objects.
15008 * Pointer to the Ethernet device structure.
15010 * The shared RSS action object ID to be removed.
15011 * @param[out] error
15012 * Perform verbose error reporting if not NULL. Initialized in case of
15016 * 0 on success, otherwise negative errno value.
15019 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
15020 struct rte_flow_error *error)
15022 struct mlx5_priv *priv = dev->data->dev_private;
15023 struct mlx5_shared_action_rss *shared_rss =
15024 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15025 uint32_t old_refcnt = 1;
15029 return rte_flow_error_set(error, EINVAL,
15030 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15031 "invalid shared action");
15032 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
15033 0, 0, __ATOMIC_ACQUIRE,
15035 return rte_flow_error_set(error, EBUSY,
15036 RTE_FLOW_ERROR_TYPE_ACTION,
15038 "shared rss has references");
15039 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
15041 return rte_flow_error_set(error, EBUSY,
15042 RTE_FLOW_ERROR_TYPE_ACTION,
15044 "shared rss hrxq has references");
15045 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
15046 !!dev->data->dev_started);
15048 return rte_flow_error_set(error, EBUSY,
15049 RTE_FLOW_ERROR_TYPE_ACTION,
15051 "shared rss indirection table has"
15053 rte_spinlock_lock(&priv->shared_act_sl);
15054 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15055 &priv->rss_shared_actions, idx, shared_rss, next);
15056 rte_spinlock_unlock(&priv->shared_act_sl);
15057 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15063 * Create indirect action, lock free,
15064 * (mutex should be acquired by caller).
15065 * Dispatcher for action type specific call.
15068 * Pointer to the Ethernet device structure.
15070 * Shared action configuration.
15071 * @param[in] action
15072 * Action specification used to create indirect action.
15073 * @param[out] error
15074 * Perform verbose error reporting if not NULL. Initialized in case of
15078 * A valid shared action handle in case of success, NULL otherwise and
15079 * rte_errno is set.
15081 struct rte_flow_action_handle *
15082 flow_dv_action_create(struct rte_eth_dev *dev,
15083 const struct rte_flow_indir_action_conf *conf,
15084 const struct rte_flow_action *action,
15085 struct rte_flow_error *err)
15087 struct mlx5_priv *priv = dev->data->dev_private;
15088 uint32_t age_idx = 0;
15092 switch (action->type) {
15093 case RTE_FLOW_ACTION_TYPE_RSS:
15094 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
15095 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
15096 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15098 case RTE_FLOW_ACTION_TYPE_AGE:
15099 age_idx = flow_dv_aso_age_alloc(dev, err);
15104 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
15105 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
15106 flow_dv_aso_age_params_init(dev, age_idx,
15107 ((const struct rte_flow_action_age *)
15108 action->conf)->context ?
15109 ((const struct rte_flow_action_age *)
15110 action->conf)->context :
15111 (void *)(uintptr_t)idx,
15112 ((const struct rte_flow_action_age *)
15113 action->conf)->timeout);
15116 case RTE_FLOW_ACTION_TYPE_COUNT:
15117 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
15118 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
15119 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15121 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
15122 ret = flow_dv_translate_create_conntrack(dev, action->conf,
15124 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
15127 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
15128 NULL, "action type not supported");
15131 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
15135 * Destroy the indirect action.
15136 * Release action related resources on the NIC and the memory.
15137 * Lock free, (mutex should be acquired by caller).
15138 * Dispatcher for action type specific call.
15141 * Pointer to the Ethernet device structure.
15142 * @param[in] handle
15143 * The indirect action object handle to be removed.
15144 * @param[out] error
15145 * Perform verbose error reporting if not NULL. Initialized in case of
15149 * 0 on success, otherwise negative errno value.
15152 flow_dv_action_destroy(struct rte_eth_dev *dev,
15153 struct rte_flow_action_handle *handle,
15154 struct rte_flow_error *error)
15156 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15157 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15158 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15159 struct mlx5_flow_counter *cnt;
15160 uint32_t no_flow_refcnt = 1;
15164 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15165 return __flow_dv_action_rss_release(dev, idx, error);
15166 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15167 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15168 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15169 &no_flow_refcnt, 1, false,
15172 return rte_flow_error_set(error, EBUSY,
15173 RTE_FLOW_ERROR_TYPE_ACTION,
15175 "Indirect count action has references");
15176 flow_dv_counter_free(dev, idx);
15178 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15179 ret = flow_dv_aso_age_release(dev, idx);
15182 * In this case, the last flow has a reference will
15183 * actually release the age action.
15185 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15186 " released with references %d.", idx, ret);
15188 case MLX5_INDIRECT_ACTION_TYPE_CT:
15189 ret = flow_dv_aso_ct_release(dev, idx, error);
15193 DRV_LOG(DEBUG, "Connection tracking object %u still "
15194 "has references %d.", idx, ret);
15197 return rte_flow_error_set(error, ENOTSUP,
15198 RTE_FLOW_ERROR_TYPE_ACTION,
15200 "action type not supported");
15205 * Updates in place shared RSS action configuration.
15208 * Pointer to the Ethernet device structure.
15210 * The shared RSS action object ID to be updated.
15211 * @param[in] action_conf
15212 * RSS action specification used to modify *shared_rss*.
15213 * @param[out] error
15214 * Perform verbose error reporting if not NULL. Initialized in case of
15218 * 0 on success, otherwise negative errno value.
15219 * @note: currently only support update of RSS queues.
15222 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15223 const struct rte_flow_action_rss *action_conf,
15224 struct rte_flow_error *error)
15226 struct mlx5_priv *priv = dev->data->dev_private;
15227 struct mlx5_shared_action_rss *shared_rss =
15228 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15230 void *queue = NULL;
15231 void *queue_i = NULL;
15232 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15233 bool dev_started = !!dev->data->dev_started;
15236 return rte_flow_error_set(error, EINVAL,
15237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15238 "invalid shared action to update");
15239 if (priv->obj_ops.ind_table_modify == NULL)
15240 return rte_flow_error_set(error, ENOTSUP,
15241 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15242 "cannot modify indirection table");
15243 queue = mlx5_malloc(MLX5_MEM_ZERO,
15244 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15247 return rte_flow_error_set(error, ENOMEM,
15248 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15250 "cannot allocate resource memory");
15251 memcpy(queue, action_conf->queue, queue_size);
15252 MLX5_ASSERT(shared_rss->ind_tbl);
15253 rte_spinlock_lock(&shared_rss->action_rss_sl);
15254 queue_i = shared_rss->ind_tbl->queues;
15255 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15256 queue, action_conf->queue_num,
15257 true /* standalone */,
15258 dev_started /* ref_new_qs */,
15259 dev_started /* deref_old_qs */);
15261 ret = rte_flow_error_set(error, rte_errno,
15262 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15263 "cannot update indirection table");
15265 /* Restore the queue to indirect table internal queue. */
15266 memcpy(queue_i, queue, queue_size);
15267 shared_rss->ind_tbl->queues = queue_i;
15268 shared_rss->origin.queue_num = action_conf->queue_num;
15271 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15276 * Updates in place conntrack context or direction.
15277 * Context update should be synchronized.
15280 * Pointer to the Ethernet device structure.
15282 * The conntrack object ID to be updated.
15283 * @param[in] update
15284 * Pointer to the structure of information to update.
15285 * @param[out] error
15286 * Perform verbose error reporting if not NULL. Initialized in case of
15290 * 0 on success, otherwise negative errno value.
15293 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15294 const struct rte_flow_modify_conntrack *update,
15295 struct rte_flow_error *error)
15297 struct mlx5_priv *priv = dev->data->dev_private;
15298 struct mlx5_aso_ct_action *ct;
15299 const struct rte_flow_action_conntrack *new_prf;
15301 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15304 if (PORT_ID(priv) != owner)
15305 return rte_flow_error_set(error, EACCES,
15306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15308 "CT object owned by another port");
15309 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15310 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15312 return rte_flow_error_set(error, ENOMEM,
15313 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15315 "CT object is inactive");
15316 new_prf = &update->new_ct;
15317 if (update->direction)
15318 ct->is_original = !!new_prf->is_original_dir;
15319 if (update->state) {
15320 /* Only validate the profile when it needs to be updated. */
15321 ret = mlx5_validate_action_ct(dev, new_prf, error);
15324 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15326 return rte_flow_error_set(error, EIO,
15327 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15329 "Failed to send CT context update WQE");
15330 /* Block until ready or a failure. */
15331 ret = mlx5_aso_ct_available(priv->sh, ct);
15333 rte_flow_error_set(error, rte_errno,
15334 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15336 "Timeout to get the CT update");
15342 * Updates in place shared action configuration, lock free,
15343 * (mutex should be acquired by caller).
15346 * Pointer to the Ethernet device structure.
15347 * @param[in] handle
15348 * The indirect action object handle to be updated.
15349 * @param[in] update
15350 * Action specification used to modify the action pointed by *handle*.
15351 * *update* could be of same type with the action pointed by the *handle*
15352 * handle argument, or some other structures like a wrapper, depending on
15353 * the indirect action type.
15354 * @param[out] error
15355 * Perform verbose error reporting if not NULL. Initialized in case of
15359 * 0 on success, otherwise negative errno value.
15362 flow_dv_action_update(struct rte_eth_dev *dev,
15363 struct rte_flow_action_handle *handle,
15364 const void *update,
15365 struct rte_flow_error *err)
15367 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15368 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15369 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15370 const void *action_conf;
15373 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15374 action_conf = ((const struct rte_flow_action *)update)->conf;
15375 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15376 case MLX5_INDIRECT_ACTION_TYPE_CT:
15377 return __flow_dv_action_ct_update(dev, idx, update, err);
15379 return rte_flow_error_set(err, ENOTSUP,
15380 RTE_FLOW_ERROR_TYPE_ACTION,
15382 "action type update not supported");
15387 * Destroy the meter sub policy table rules.
15388 * Lock free, (mutex should be acquired by caller).
15391 * Pointer to Ethernet device.
15392 * @param[in] sub_policy
15393 * Pointer to meter sub policy table.
15396 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15397 struct mlx5_flow_meter_sub_policy *sub_policy)
15399 struct mlx5_priv *priv = dev->data->dev_private;
15400 struct mlx5_flow_tbl_data_entry *tbl;
15401 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15402 struct mlx5_flow_meter_info *next_fm;
15403 struct mlx5_sub_policy_color_rule *color_rule;
15407 for (i = 0; i < RTE_COLORS; i++) {
15409 if (i == RTE_COLOR_GREEN && policy &&
15410 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15411 next_fm = mlx5_flow_meter_find(priv,
15412 policy->act_cnt[i].next_mtr_id, NULL);
15413 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15415 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15416 tbl = container_of(color_rule->matcher->tbl,
15417 typeof(*tbl), tbl);
15418 mlx5_list_unregister(tbl->matchers,
15419 &color_rule->matcher->entry);
15420 TAILQ_REMOVE(&sub_policy->color_rules[i],
15421 color_rule, next_port);
15422 mlx5_free(color_rule);
15424 mlx5_flow_meter_detach(priv, next_fm);
15427 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15428 if (sub_policy->rix_hrxq[i]) {
15429 if (policy && !policy->is_hierarchy)
15430 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15431 sub_policy->rix_hrxq[i] = 0;
15433 if (sub_policy->jump_tbl[i]) {
15434 flow_dv_tbl_resource_release(MLX5_SH(dev),
15435 sub_policy->jump_tbl[i]);
15436 sub_policy->jump_tbl[i] = NULL;
15439 if (sub_policy->tbl_rsc) {
15440 flow_dv_tbl_resource_release(MLX5_SH(dev),
15441 sub_policy->tbl_rsc);
15442 sub_policy->tbl_rsc = NULL;
15447 * Destroy policy rules, lock free,
15448 * (mutex should be acquired by caller).
15449 * Dispatcher for action type specific call.
15452 * Pointer to the Ethernet device structure.
15453 * @param[in] mtr_policy
15454 * Meter policy struct.
15457 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15458 struct mlx5_flow_meter_policy *mtr_policy)
15461 struct mlx5_flow_meter_sub_policy *sub_policy;
15462 uint16_t sub_policy_num;
15464 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15465 sub_policy_num = (mtr_policy->sub_policy_num >>
15466 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15467 MLX5_MTR_SUB_POLICY_NUM_MASK;
15468 for (j = 0; j < sub_policy_num; j++) {
15469 sub_policy = mtr_policy->sub_policys[i][j];
15471 __flow_dv_destroy_sub_policy_rules(dev,
15478 * Destroy policy action, lock free,
15479 * (mutex should be acquired by caller).
15480 * Dispatcher for action type specific call.
15483 * Pointer to the Ethernet device structure.
15484 * @param[in] mtr_policy
15485 * Meter policy struct.
15488 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15489 struct mlx5_flow_meter_policy *mtr_policy)
15491 struct rte_flow_action *rss_action;
15492 struct mlx5_flow_handle dev_handle;
15495 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15496 if (mtr_policy->act_cnt[i].rix_mark) {
15497 flow_dv_tag_release(dev,
15498 mtr_policy->act_cnt[i].rix_mark);
15499 mtr_policy->act_cnt[i].rix_mark = 0;
15501 if (mtr_policy->act_cnt[i].modify_hdr) {
15502 dev_handle.dvh.modify_hdr =
15503 mtr_policy->act_cnt[i].modify_hdr;
15504 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15506 switch (mtr_policy->act_cnt[i].fate_action) {
15507 case MLX5_FLOW_FATE_SHARED_RSS:
15508 rss_action = mtr_policy->act_cnt[i].rss;
15509 mlx5_free(rss_action);
15511 case MLX5_FLOW_FATE_PORT_ID:
15512 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15513 flow_dv_port_id_action_resource_release(dev,
15514 mtr_policy->act_cnt[i].rix_port_id_action);
15515 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15518 case MLX5_FLOW_FATE_DROP:
15519 case MLX5_FLOW_FATE_JUMP:
15520 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15521 mtr_policy->act_cnt[i].dr_jump_action[j] =
15525 /*Queue action do nothing*/
15529 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15530 mtr_policy->dr_drop_action[j] = NULL;
15534 * Create policy action per domain, lock free,
15535 * (mutex should be acquired by caller).
15536 * Dispatcher for action type specific call.
15539 * Pointer to the Ethernet device structure.
15540 * @param[in] mtr_policy
15541 * Meter policy struct.
15542 * @param[in] action
15543 * Action specification used to create meter actions.
15544 * @param[out] error
15545 * Perform verbose error reporting if not NULL. Initialized in case of
15549 * 0 on success, otherwise negative errno value.
15552 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15553 struct mlx5_flow_meter_policy *mtr_policy,
15554 const struct rte_flow_action *actions[RTE_COLORS],
15555 enum mlx5_meter_domain domain,
15556 struct rte_mtr_error *error)
15558 struct mlx5_priv *priv = dev->data->dev_private;
15559 struct rte_flow_error flow_err;
15560 const struct rte_flow_action *act;
15561 uint64_t action_flags;
15562 struct mlx5_flow_handle dh;
15563 struct mlx5_flow dev_flow;
15564 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15566 uint8_t egress, transfer;
15567 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15569 struct mlx5_flow_dv_modify_hdr_resource res;
15570 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15571 sizeof(struct mlx5_modification_cmd) *
15572 (MLX5_MAX_MODIFY_NUM + 1)];
15574 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15576 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15577 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15578 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15579 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15580 memset(&port_id_action, 0,
15581 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15582 memset(mhdr_res, 0, sizeof(*mhdr_res));
15583 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15584 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15585 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15586 dev_flow.handle = &dh;
15587 dev_flow.dv.port_id_action = &port_id_action;
15588 dev_flow.external = true;
15589 for (i = 0; i < RTE_COLORS; i++) {
15590 if (i < MLX5_MTR_RTE_COLORS)
15591 act_cnt = &mtr_policy->act_cnt[i];
15592 /* Skip the color policy actions creation. */
15593 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15594 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15597 for (act = actions[i];
15598 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15599 switch (act->type) {
15600 case RTE_FLOW_ACTION_TYPE_MARK:
15602 uint32_t tag_be = mlx5_flow_mark_set
15603 (((const struct rte_flow_action_mark *)
15606 if (i >= MLX5_MTR_RTE_COLORS)
15607 return -rte_mtr_error_set(error,
15609 RTE_MTR_ERROR_TYPE_METER_POLICY,
15611 "cannot create policy "
15612 "mark action for this color");
15613 if (flow_dv_tag_resource_register(dev, tag_be,
15614 &dev_flow, &flow_err))
15615 return -rte_mtr_error_set(error,
15617 RTE_MTR_ERROR_TYPE_METER_POLICY,
15619 "cannot setup policy mark action");
15620 MLX5_ASSERT(dev_flow.dv.tag_resource);
15621 act_cnt->rix_mark =
15622 dev_flow.handle->dvh.rix_tag;
15623 action_flags |= MLX5_FLOW_ACTION_MARK;
15624 mtr_policy->mark = 1;
15627 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15628 if (i >= MLX5_MTR_RTE_COLORS)
15629 return -rte_mtr_error_set(error,
15631 RTE_MTR_ERROR_TYPE_METER_POLICY,
15633 "cannot create policy "
15634 "set tag action for this color");
15635 if (flow_dv_convert_action_set_tag
15637 (const struct rte_flow_action_set_tag *)
15638 act->conf, &flow_err))
15639 return -rte_mtr_error_set(error,
15641 RTE_MTR_ERROR_TYPE_METER_POLICY,
15642 NULL, "cannot convert policy "
15644 if (!mhdr_res->actions_num)
15645 return -rte_mtr_error_set(error,
15647 RTE_MTR_ERROR_TYPE_METER_POLICY,
15648 NULL, "cannot find policy "
15650 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15652 case RTE_FLOW_ACTION_TYPE_DROP:
15654 struct mlx5_flow_mtr_mng *mtrmng =
15656 struct mlx5_flow_tbl_data_entry *tbl_data;
15659 * Create the drop table with
15660 * METER DROP level.
15662 if (!mtrmng->drop_tbl[domain]) {
15663 mtrmng->drop_tbl[domain] =
15664 flow_dv_tbl_resource_get(dev,
15665 MLX5_FLOW_TABLE_LEVEL_METER,
15666 egress, transfer, false, NULL, 0,
15667 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15668 if (!mtrmng->drop_tbl[domain])
15669 return -rte_mtr_error_set
15671 RTE_MTR_ERROR_TYPE_METER_POLICY,
15673 "Failed to create meter drop table");
15675 tbl_data = container_of
15676 (mtrmng->drop_tbl[domain],
15677 struct mlx5_flow_tbl_data_entry, tbl);
15678 if (i < MLX5_MTR_RTE_COLORS) {
15679 act_cnt->dr_jump_action[domain] =
15680 tbl_data->jump.action;
15681 act_cnt->fate_action =
15682 MLX5_FLOW_FATE_DROP;
15684 if (i == RTE_COLOR_RED)
15685 mtr_policy->dr_drop_action[domain] =
15686 tbl_data->jump.action;
15687 action_flags |= MLX5_FLOW_ACTION_DROP;
15690 case RTE_FLOW_ACTION_TYPE_QUEUE:
15692 if (i >= MLX5_MTR_RTE_COLORS)
15693 return -rte_mtr_error_set(error,
15695 RTE_MTR_ERROR_TYPE_METER_POLICY,
15696 NULL, "cannot create policy "
15697 "fate queue for this color");
15699 ((const struct rte_flow_action_queue *)
15700 (act->conf))->index;
15701 act_cnt->fate_action =
15702 MLX5_FLOW_FATE_QUEUE;
15703 dev_flow.handle->fate_action =
15704 MLX5_FLOW_FATE_QUEUE;
15705 mtr_policy->is_queue = 1;
15706 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15709 case RTE_FLOW_ACTION_TYPE_RSS:
15713 if (i >= MLX5_MTR_RTE_COLORS)
15714 return -rte_mtr_error_set(error,
15716 RTE_MTR_ERROR_TYPE_METER_POLICY,
15718 "cannot create policy "
15719 "rss action for this color");
15721 * Save RSS conf into policy struct
15722 * for translate stage.
15724 rss_size = (int)rte_flow_conv
15725 (RTE_FLOW_CONV_OP_ACTION,
15726 NULL, 0, act, &flow_err);
15728 return -rte_mtr_error_set(error,
15730 RTE_MTR_ERROR_TYPE_METER_POLICY,
15731 NULL, "Get the wrong "
15732 "rss action struct size");
15733 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15734 rss_size, 0, SOCKET_ID_ANY);
15736 return -rte_mtr_error_set(error,
15738 RTE_MTR_ERROR_TYPE_METER_POLICY,
15740 "Fail to malloc rss action memory");
15741 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15742 act_cnt->rss, rss_size,
15745 return -rte_mtr_error_set(error,
15747 RTE_MTR_ERROR_TYPE_METER_POLICY,
15748 NULL, "Fail to save "
15749 "rss action into policy struct");
15750 act_cnt->fate_action =
15751 MLX5_FLOW_FATE_SHARED_RSS;
15752 action_flags |= MLX5_FLOW_ACTION_RSS;
15755 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15756 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15758 struct mlx5_flow_dv_port_id_action_resource
15760 uint32_t port_id = 0;
15762 if (i >= MLX5_MTR_RTE_COLORS)
15763 return -rte_mtr_error_set(error,
15765 RTE_MTR_ERROR_TYPE_METER_POLICY,
15766 NULL, "cannot create policy "
15767 "port action for this color");
15768 memset(&port_id_resource, 0,
15769 sizeof(port_id_resource));
15770 if (flow_dv_translate_action_port_id(dev, act,
15771 &port_id, &flow_err))
15772 return -rte_mtr_error_set(error,
15774 RTE_MTR_ERROR_TYPE_METER_POLICY,
15775 NULL, "cannot translate "
15776 "policy port action");
15777 port_id_resource.port_id = port_id;
15778 if (flow_dv_port_id_action_resource_register
15779 (dev, &port_id_resource,
15780 &dev_flow, &flow_err))
15781 return -rte_mtr_error_set(error,
15783 RTE_MTR_ERROR_TYPE_METER_POLICY,
15784 NULL, "cannot setup "
15785 "policy port action");
15786 act_cnt->rix_port_id_action =
15787 dev_flow.handle->rix_port_id_action;
15788 act_cnt->fate_action =
15789 MLX5_FLOW_FATE_PORT_ID;
15790 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15793 case RTE_FLOW_ACTION_TYPE_JUMP:
15795 uint32_t jump_group = 0;
15796 uint32_t table = 0;
15797 struct mlx5_flow_tbl_data_entry *tbl_data;
15798 struct flow_grp_info grp_info = {
15799 .external = !!dev_flow.external,
15800 .transfer = !!transfer,
15801 .fdb_def_rule = !!priv->fdb_def_rule,
15803 .skip_scale = dev_flow.skip_scale &
15804 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15806 struct mlx5_flow_meter_sub_policy *sub_policy =
15807 mtr_policy->sub_policys[domain][0];
15809 if (i >= MLX5_MTR_RTE_COLORS)
15810 return -rte_mtr_error_set(error,
15812 RTE_MTR_ERROR_TYPE_METER_POLICY,
15814 "cannot create policy "
15815 "jump action for this color");
15817 ((const struct rte_flow_action_jump *)
15819 if (mlx5_flow_group_to_table(dev, NULL,
15822 &grp_info, &flow_err))
15823 return -rte_mtr_error_set(error,
15825 RTE_MTR_ERROR_TYPE_METER_POLICY,
15826 NULL, "cannot setup "
15827 "policy jump action");
15828 sub_policy->jump_tbl[i] =
15829 flow_dv_tbl_resource_get(dev,
15832 !!dev_flow.external,
15833 NULL, jump_group, 0,
15836 (!sub_policy->jump_tbl[i])
15837 return -rte_mtr_error_set(error,
15839 RTE_MTR_ERROR_TYPE_METER_POLICY,
15840 NULL, "cannot create jump action.");
15841 tbl_data = container_of
15842 (sub_policy->jump_tbl[i],
15843 struct mlx5_flow_tbl_data_entry, tbl);
15844 act_cnt->dr_jump_action[domain] =
15845 tbl_data->jump.action;
15846 act_cnt->fate_action =
15847 MLX5_FLOW_FATE_JUMP;
15848 action_flags |= MLX5_FLOW_ACTION_JUMP;
15852 * No need to check meter hierarchy for Y or R colors
15853 * here since it is done in the validation stage.
15855 case RTE_FLOW_ACTION_TYPE_METER:
15857 const struct rte_flow_action_meter *mtr;
15858 struct mlx5_flow_meter_info *next_fm;
15859 struct mlx5_flow_meter_policy *next_policy;
15860 struct rte_flow_action tag_action;
15861 struct mlx5_rte_flow_action_set_tag set_tag;
15862 uint32_t next_mtr_idx = 0;
15865 next_fm = mlx5_flow_meter_find(priv,
15869 return -rte_mtr_error_set(error, EINVAL,
15870 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15871 "Fail to find next meter.");
15872 if (next_fm->def_policy)
15873 return -rte_mtr_error_set(error, EINVAL,
15874 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15875 "Hierarchy only supports termination meter.");
15876 next_policy = mlx5_flow_meter_policy_find(dev,
15877 next_fm->policy_id, NULL);
15878 MLX5_ASSERT(next_policy);
15879 if (next_fm->drop_cnt) {
15882 mlx5_flow_get_reg_id(dev,
15885 (struct rte_flow_error *)error);
15886 set_tag.offset = (priv->mtr_reg_share ?
15887 MLX5_MTR_COLOR_BITS : 0);
15888 set_tag.length = (priv->mtr_reg_share ?
15889 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15891 set_tag.data = next_mtr_idx;
15893 (enum rte_flow_action_type)
15894 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15895 tag_action.conf = &set_tag;
15896 if (flow_dv_convert_action_set_reg
15897 (mhdr_res, &tag_action,
15898 (struct rte_flow_error *)error))
15901 MLX5_FLOW_ACTION_SET_TAG;
15903 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15904 act_cnt->next_mtr_id = next_fm->meter_id;
15905 act_cnt->next_sub_policy = NULL;
15906 mtr_policy->is_hierarchy = 1;
15907 mtr_policy->dev = next_policy->dev;
15908 if (next_policy->mark)
15909 mtr_policy->mark = 1;
15911 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15915 return -rte_mtr_error_set(error, ENOTSUP,
15916 RTE_MTR_ERROR_TYPE_METER_POLICY,
15917 NULL, "action type not supported");
15919 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15920 /* create modify action if needed. */
15921 dev_flow.dv.group = 1;
15922 if (flow_dv_modify_hdr_resource_register
15923 (dev, mhdr_res, &dev_flow, &flow_err))
15924 return -rte_mtr_error_set(error,
15926 RTE_MTR_ERROR_TYPE_METER_POLICY,
15927 NULL, "cannot register policy "
15929 act_cnt->modify_hdr =
15930 dev_flow.handle->dvh.modify_hdr;
15938 * Create policy action per domain, lock free,
15939 * (mutex should be acquired by caller).
15940 * Dispatcher for action type specific call.
15943 * Pointer to the Ethernet device structure.
15944 * @param[in] mtr_policy
15945 * Meter policy struct.
15946 * @param[in] action
15947 * Action specification used to create meter actions.
15948 * @param[out] error
15949 * Perform verbose error reporting if not NULL. Initialized in case of
15953 * 0 on success, otherwise negative errno value.
15956 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15957 struct mlx5_flow_meter_policy *mtr_policy,
15958 const struct rte_flow_action *actions[RTE_COLORS],
15959 struct rte_mtr_error *error)
15962 uint16_t sub_policy_num;
15964 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15965 sub_policy_num = (mtr_policy->sub_policy_num >>
15966 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15967 MLX5_MTR_SUB_POLICY_NUM_MASK;
15968 if (sub_policy_num) {
15969 ret = __flow_dv_create_domain_policy_acts(dev,
15970 mtr_policy, actions,
15971 (enum mlx5_meter_domain)i, error);
15972 /* Cleaning resource is done in the caller level. */
15981 * Query a DV flow rule for its statistics via DevX.
15984 * Pointer to Ethernet device.
15985 * @param[in] cnt_idx
15986 * Index to the flow counter.
15988 * Data retrieved by the query.
15989 * @param[out] error
15990 * Perform verbose error reporting if not NULL.
15993 * 0 on success, a negative errno value otherwise and rte_errno is set.
15996 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15997 struct rte_flow_error *error)
15999 struct mlx5_priv *priv = dev->data->dev_private;
16000 struct rte_flow_query_count *qc = data;
16002 if (!priv->sh->cdev->config.devx)
16003 return rte_flow_error_set(error, ENOTSUP,
16004 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16006 "counters are not supported");
16008 uint64_t pkts, bytes;
16009 struct mlx5_flow_counter *cnt;
16010 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
16013 return rte_flow_error_set(error, -err,
16014 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16015 NULL, "cannot read counters");
16016 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
16019 qc->hits = pkts - cnt->hits;
16020 qc->bytes = bytes - cnt->bytes;
16023 cnt->bytes = bytes;
16027 return rte_flow_error_set(error, EINVAL,
16028 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16030 "counters are not available");
16034 flow_dv_action_query(struct rte_eth_dev *dev,
16035 const struct rte_flow_action_handle *handle, void *data,
16036 struct rte_flow_error *error)
16038 struct mlx5_age_param *age_param;
16039 struct rte_flow_query_age *resp;
16040 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
16041 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
16042 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
16043 struct mlx5_priv *priv = dev->data->dev_private;
16044 struct mlx5_aso_ct_action *ct;
16049 case MLX5_INDIRECT_ACTION_TYPE_AGE:
16050 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
16052 resp->aged = __atomic_load_n(&age_param->state,
16053 __ATOMIC_RELAXED) == AGE_TMOUT ?
16055 resp->sec_since_last_hit_valid = !resp->aged;
16056 if (resp->sec_since_last_hit_valid)
16057 resp->sec_since_last_hit = __atomic_load_n
16058 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16060 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
16061 return flow_dv_query_count(dev, idx, data, error);
16062 case MLX5_INDIRECT_ACTION_TYPE_CT:
16063 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
16064 if (owner != PORT_ID(priv))
16065 return rte_flow_error_set(error, EACCES,
16066 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16068 "CT object owned by another port");
16069 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
16070 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
16073 return rte_flow_error_set(error, EFAULT,
16074 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16076 "CT object is inactive");
16077 ((struct rte_flow_action_conntrack *)data)->peer_port =
16079 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
16081 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
16082 return rte_flow_error_set(error, EIO,
16083 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16085 "Failed to query CT context");
16088 return rte_flow_error_set(error, ENOTSUP,
16089 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16090 "action type query not supported");
16095 * Query a flow rule AGE action for aging information.
16098 * Pointer to Ethernet device.
16100 * Pointer to the sub flow.
16102 * data retrieved by the query.
16103 * @param[out] error
16104 * Perform verbose error reporting if not NULL.
16107 * 0 on success, a negative errno value otherwise and rte_errno is set.
16110 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
16111 void *data, struct rte_flow_error *error)
16113 struct rte_flow_query_age *resp = data;
16114 struct mlx5_age_param *age_param;
16117 struct mlx5_aso_age_action *act =
16118 flow_aso_age_get_by_idx(dev, flow->age);
16120 age_param = &act->age_params;
16121 } else if (flow->counter) {
16122 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16124 if (!age_param || !age_param->timeout)
16125 return rte_flow_error_set
16127 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16128 NULL, "cannot read age data");
16130 return rte_flow_error_set(error, EINVAL,
16131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16132 NULL, "age data not available");
16134 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16136 resp->sec_since_last_hit_valid = !resp->aged;
16137 if (resp->sec_since_last_hit_valid)
16138 resp->sec_since_last_hit = __atomic_load_n
16139 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16146 * @see rte_flow_query()
16147 * @see rte_flow_ops
16150 flow_dv_query(struct rte_eth_dev *dev,
16151 struct rte_flow *flow __rte_unused,
16152 const struct rte_flow_action *actions __rte_unused,
16153 void *data __rte_unused,
16154 struct rte_flow_error *error __rte_unused)
16158 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16159 switch (actions->type) {
16160 case RTE_FLOW_ACTION_TYPE_VOID:
16162 case RTE_FLOW_ACTION_TYPE_COUNT:
16163 ret = flow_dv_query_count(dev, flow->counter, data,
16166 case RTE_FLOW_ACTION_TYPE_AGE:
16167 ret = flow_dv_query_age(dev, flow, data, error);
16170 return rte_flow_error_set(error, ENOTSUP,
16171 RTE_FLOW_ERROR_TYPE_ACTION,
16173 "action not supported");
16180 * Destroy the meter table set.
16181 * Lock free, (mutex should be acquired by caller).
16184 * Pointer to Ethernet device.
16186 * Meter information table.
16189 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16190 struct mlx5_flow_meter_info *fm)
16192 struct mlx5_priv *priv = dev->data->dev_private;
16195 if (!fm || !priv->sh->config.dv_flow_en)
16197 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16198 if (fm->drop_rule[i]) {
16199 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16200 fm->drop_rule[i] = NULL;
16206 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16208 struct mlx5_priv *priv = dev->data->dev_private;
16209 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16210 struct mlx5_flow_tbl_data_entry *tbl;
16213 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16214 if (mtrmng->def_rule[i]) {
16215 claim_zero(mlx5_flow_os_destroy_flow
16216 (mtrmng->def_rule[i]));
16217 mtrmng->def_rule[i] = NULL;
16219 if (mtrmng->def_matcher[i]) {
16220 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16221 struct mlx5_flow_tbl_data_entry, tbl);
16222 mlx5_list_unregister(tbl->matchers,
16223 &mtrmng->def_matcher[i]->entry);
16224 mtrmng->def_matcher[i] = NULL;
16226 for (j = 0; j < MLX5_REG_BITS; j++) {
16227 if (mtrmng->drop_matcher[i][j]) {
16229 container_of(mtrmng->drop_matcher[i][j]->tbl,
16230 struct mlx5_flow_tbl_data_entry,
16232 mlx5_list_unregister(tbl->matchers,
16233 &mtrmng->drop_matcher[i][j]->entry);
16234 mtrmng->drop_matcher[i][j] = NULL;
16237 if (mtrmng->drop_tbl[i]) {
16238 flow_dv_tbl_resource_release(MLX5_SH(dev),
16239 mtrmng->drop_tbl[i]);
16240 mtrmng->drop_tbl[i] = NULL;
16245 /* Number of meter flow actions, count and jump or count and drop. */
16246 #define METER_ACTIONS 2
16249 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16250 enum mlx5_meter_domain domain)
16252 struct mlx5_priv *priv = dev->data->dev_private;
16253 struct mlx5_flow_meter_def_policy *def_policy =
16254 priv->sh->mtrmng->def_policy[domain];
16256 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16257 mlx5_free(def_policy);
16258 priv->sh->mtrmng->def_policy[domain] = NULL;
16262 * Destroy the default policy table set.
16265 * Pointer to Ethernet device.
16268 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16270 struct mlx5_priv *priv = dev->data->dev_private;
16273 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16274 if (priv->sh->mtrmng->def_policy[i])
16275 __flow_dv_destroy_domain_def_policy(dev,
16276 (enum mlx5_meter_domain)i);
16277 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16281 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16282 uint32_t color_reg_c_idx,
16283 enum rte_color color, void *matcher_object,
16284 int actions_n, void *actions,
16285 bool match_src_port, const struct rte_flow_item *item,
16286 void **rule, const struct rte_flow_attr *attr)
16289 struct mlx5_flow_dv_match_params value = {
16290 .size = sizeof(value.buf),
16292 struct mlx5_flow_dv_match_params matcher = {
16293 .size = sizeof(matcher.buf),
16295 struct mlx5_priv *priv = dev->data->dev_private;
16298 if (match_src_port && priv->sh->esw_mode) {
16299 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16300 value.buf, item, attr)) {
16301 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16302 " value with port.", color);
16306 flow_dv_match_meta_reg(matcher.buf, value.buf,
16307 (enum modify_reg)color_reg_c_idx,
16308 rte_col_2_mlx5_col(color), UINT32_MAX);
16309 misc_mask = flow_dv_matcher_enable(value.buf);
16310 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16311 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16312 actions_n, actions, rule);
16314 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16321 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16322 uint32_t color_reg_c_idx,
16324 struct mlx5_flow_meter_sub_policy *sub_policy,
16325 const struct rte_flow_attr *attr,
16326 bool match_src_port,
16327 const struct rte_flow_item *item,
16328 struct mlx5_flow_dv_matcher **policy_matcher,
16329 struct rte_flow_error *error)
16331 struct mlx5_list_entry *entry;
16332 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16333 struct mlx5_flow_dv_matcher matcher = {
16335 .size = sizeof(matcher.mask.buf),
16339 struct mlx5_flow_dv_match_params value = {
16340 .size = sizeof(value.buf),
16342 struct mlx5_flow_cb_ctx ctx = {
16346 struct mlx5_flow_tbl_data_entry *tbl_data;
16347 struct mlx5_priv *priv = dev->data->dev_private;
16348 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16350 if (match_src_port && priv->sh->esw_mode) {
16351 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16352 value.buf, item, attr)) {
16353 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16354 " with port.", priority);
16358 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16359 if (priority < RTE_COLOR_RED)
16360 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16361 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16362 matcher.priority = priority;
16363 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16364 matcher.mask.size);
16365 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16367 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16371 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16376 * Create the policy rules per domain.
16379 * Pointer to Ethernet device.
16380 * @param[in] sub_policy
16381 * Pointer to sub policy table..
16382 * @param[in] egress
16383 * Direction of the table.
16384 * @param[in] transfer
16385 * E-Switch or NIC flow.
16387 * Pointer to policy action list per color.
16390 * 0 on success, -1 otherwise.
16393 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16394 struct mlx5_flow_meter_sub_policy *sub_policy,
16395 uint8_t egress, uint8_t transfer, bool match_src_port,
16396 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16398 struct mlx5_priv *priv = dev->data->dev_private;
16399 struct rte_flow_error flow_err;
16400 uint32_t color_reg_c_idx;
16401 struct rte_flow_attr attr = {
16402 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16405 .egress = !!egress,
16406 .transfer = !!transfer,
16410 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16411 struct mlx5_sub_policy_color_rule *color_rule;
16413 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16417 /* Create policy table with POLICY level. */
16418 if (!sub_policy->tbl_rsc)
16419 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16420 MLX5_FLOW_TABLE_LEVEL_POLICY,
16421 egress, transfer, false, NULL, 0, 0,
16422 sub_policy->idx, &flow_err);
16423 if (!sub_policy->tbl_rsc) {
16425 "Failed to create meter sub policy table.");
16428 /* Prepare matchers. */
16429 color_reg_c_idx = ret;
16430 for (i = 0; i < RTE_COLORS; i++) {
16431 TAILQ_INIT(&sub_policy->color_rules[i]);
16432 if (!acts[i].actions_n)
16434 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16435 sizeof(struct mlx5_sub_policy_color_rule),
16438 DRV_LOG(ERR, "No memory to create color rule.");
16441 tmp_rules[i] = color_rule;
16442 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16443 color_rule, next_port);
16444 color_rule->src_port = priv->representor_id;
16447 /* Create matchers for colors. */
16448 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16449 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16450 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16451 &attr, svport_match, NULL,
16452 &color_rule->matcher, &flow_err)) {
16453 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16456 /* Create flow, matching color. */
16457 if (__flow_dv_create_policy_flow(dev,
16458 color_reg_c_idx, (enum rte_color)i,
16459 color_rule->matcher->matcher_object,
16460 acts[i].actions_n, acts[i].dv_actions,
16461 svport_match, NULL, &color_rule->rule,
16463 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16469 /* All the policy rules will be cleared. */
16471 color_rule = tmp_rules[i];
16473 if (color_rule->rule)
16474 mlx5_flow_os_destroy_flow(color_rule->rule);
16475 if (color_rule->matcher) {
16476 struct mlx5_flow_tbl_data_entry *tbl =
16477 container_of(color_rule->matcher->tbl,
16478 typeof(*tbl), tbl);
16479 mlx5_list_unregister(tbl->matchers,
16480 &color_rule->matcher->entry);
16482 TAILQ_REMOVE(&sub_policy->color_rules[i],
16483 color_rule, next_port);
16484 mlx5_free(color_rule);
16491 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16492 struct mlx5_flow_meter_policy *mtr_policy,
16493 struct mlx5_flow_meter_sub_policy *sub_policy,
16496 struct mlx5_priv *priv = dev->data->dev_private;
16497 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16498 struct mlx5_flow_dv_tag_resource *tag;
16499 struct mlx5_flow_dv_port_id_action_resource *port_action;
16500 struct mlx5_hrxq *hrxq;
16501 struct mlx5_flow_meter_info *next_fm = NULL;
16502 struct mlx5_flow_meter_policy *next_policy;
16503 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16504 struct mlx5_flow_tbl_data_entry *tbl_data;
16505 struct rte_flow_error error;
16506 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16507 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16508 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16509 bool match_src_port = false;
16512 /* If RSS or Queue, no previous actions / rules is created. */
16513 for (i = 0; i < RTE_COLORS; i++) {
16514 acts[i].actions_n = 0;
16515 if (i == RTE_COLOR_RED) {
16516 /* Only support drop on red. */
16517 acts[i].dv_actions[0] =
16518 mtr_policy->dr_drop_action[domain];
16519 acts[i].actions_n = 1;
16522 if (i == RTE_COLOR_GREEN &&
16523 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16524 struct rte_flow_attr attr = {
16525 .transfer = transfer
16528 next_fm = mlx5_flow_meter_find(priv,
16529 mtr_policy->act_cnt[i].next_mtr_id,
16533 "Failed to get next hierarchy meter.");
16536 if (mlx5_flow_meter_attach(priv, next_fm,
16538 DRV_LOG(ERR, "%s", error.message);
16542 /* Meter action must be the first for TX. */
16544 acts[i].dv_actions[acts[i].actions_n] =
16545 next_fm->meter_action;
16546 acts[i].actions_n++;
16549 if (mtr_policy->act_cnt[i].rix_mark) {
16550 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16551 mtr_policy->act_cnt[i].rix_mark);
16553 DRV_LOG(ERR, "Failed to find "
16554 "mark action for policy.");
16557 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16558 acts[i].actions_n++;
16560 if (mtr_policy->act_cnt[i].modify_hdr) {
16561 acts[i].dv_actions[acts[i].actions_n] =
16562 mtr_policy->act_cnt[i].modify_hdr->action;
16563 acts[i].actions_n++;
16565 if (mtr_policy->act_cnt[i].fate_action) {
16566 switch (mtr_policy->act_cnt[i].fate_action) {
16567 case MLX5_FLOW_FATE_PORT_ID:
16568 port_action = mlx5_ipool_get
16569 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16570 mtr_policy->act_cnt[i].rix_port_id_action);
16571 if (!port_action) {
16572 DRV_LOG(ERR, "Failed to find "
16573 "port action for policy.");
16576 acts[i].dv_actions[acts[i].actions_n] =
16577 port_action->action;
16578 acts[i].actions_n++;
16579 mtr_policy->dev = dev;
16580 match_src_port = true;
16582 case MLX5_FLOW_FATE_DROP:
16583 case MLX5_FLOW_FATE_JUMP:
16584 acts[i].dv_actions[acts[i].actions_n] =
16585 mtr_policy->act_cnt[i].dr_jump_action[domain];
16586 acts[i].actions_n++;
16588 case MLX5_FLOW_FATE_SHARED_RSS:
16589 case MLX5_FLOW_FATE_QUEUE:
16590 hrxq = mlx5_ipool_get
16591 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16592 sub_policy->rix_hrxq[i]);
16594 DRV_LOG(ERR, "Failed to find "
16595 "queue action for policy.");
16598 acts[i].dv_actions[acts[i].actions_n] =
16600 acts[i].actions_n++;
16602 case MLX5_FLOW_FATE_MTR:
16605 "No next hierarchy meter.");
16609 acts[i].dv_actions[acts[i].actions_n] =
16610 next_fm->meter_action;
16611 acts[i].actions_n++;
16613 if (mtr_policy->act_cnt[i].next_sub_policy) {
16615 mtr_policy->act_cnt[i].next_sub_policy;
16618 mlx5_flow_meter_policy_find(dev,
16619 next_fm->policy_id, NULL);
16620 MLX5_ASSERT(next_policy);
16622 next_policy->sub_policys[domain][0];
16625 container_of(next_sub_policy->tbl_rsc,
16626 struct mlx5_flow_tbl_data_entry, tbl);
16627 acts[i].dv_actions[acts[i].actions_n++] =
16628 tbl_data->jump.action;
16629 if (mtr_policy->act_cnt[i].modify_hdr)
16630 match_src_port = !!transfer;
16633 /*Queue action do nothing*/
16638 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16639 egress, transfer, match_src_port, acts)) {
16641 "Failed to create policy rules per domain.");
16647 mlx5_flow_meter_detach(priv, next_fm);
16652 * Create the policy rules.
16655 * Pointer to Ethernet device.
16656 * @param[in,out] mtr_policy
16657 * Pointer to meter policy table.
16660 * 0 on success, -1 otherwise.
16663 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16664 struct mlx5_flow_meter_policy *mtr_policy)
16667 uint16_t sub_policy_num;
16669 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16670 sub_policy_num = (mtr_policy->sub_policy_num >>
16671 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16672 MLX5_MTR_SUB_POLICY_NUM_MASK;
16673 if (!sub_policy_num)
16675 /* Prepare actions list and create policy rules. */
16676 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16677 mtr_policy->sub_policys[i][0], i)) {
16678 DRV_LOG(ERR, "Failed to create policy action "
16679 "list per domain.");
16687 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16689 struct mlx5_priv *priv = dev->data->dev_private;
16690 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16691 struct mlx5_flow_meter_def_policy *def_policy;
16692 struct mlx5_flow_tbl_resource *jump_tbl;
16693 struct mlx5_flow_tbl_data_entry *tbl_data;
16694 uint8_t egress, transfer;
16695 struct rte_flow_error error;
16696 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16699 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16700 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16701 def_policy = mtrmng->def_policy[domain];
16703 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16704 sizeof(struct mlx5_flow_meter_def_policy),
16705 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16707 DRV_LOG(ERR, "Failed to alloc default policy table.");
16708 goto def_policy_error;
16710 mtrmng->def_policy[domain] = def_policy;
16711 /* Create the meter suffix table with SUFFIX level. */
16712 jump_tbl = flow_dv_tbl_resource_get(dev,
16713 MLX5_FLOW_TABLE_LEVEL_METER,
16714 egress, transfer, false, NULL, 0,
16715 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16718 "Failed to create meter suffix table.");
16719 goto def_policy_error;
16721 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16722 tbl_data = container_of(jump_tbl,
16723 struct mlx5_flow_tbl_data_entry, tbl);
16724 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16725 tbl_data->jump.action;
16726 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16727 acts[RTE_COLOR_GREEN].actions_n = 1;
16729 * YELLOW has the same default policy as GREEN does.
16730 * G & Y share the same table and action. The 2nd time of table
16731 * resource getting is just to update the reference count for
16732 * the releasing stage.
16734 jump_tbl = flow_dv_tbl_resource_get(dev,
16735 MLX5_FLOW_TABLE_LEVEL_METER,
16736 egress, transfer, false, NULL, 0,
16737 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16740 "Failed to get meter suffix table.");
16741 goto def_policy_error;
16743 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16744 tbl_data = container_of(jump_tbl,
16745 struct mlx5_flow_tbl_data_entry, tbl);
16746 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16747 tbl_data->jump.action;
16748 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16749 acts[RTE_COLOR_YELLOW].actions_n = 1;
16750 /* Create jump action to the drop table. */
16751 if (!mtrmng->drop_tbl[domain]) {
16752 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16753 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16754 egress, transfer, false, NULL, 0,
16755 0, MLX5_MTR_TABLE_ID_DROP, &error);
16756 if (!mtrmng->drop_tbl[domain]) {
16757 DRV_LOG(ERR, "Failed to create meter "
16758 "drop table for default policy.");
16759 goto def_policy_error;
16762 /* all RED: unique Drop table for jump action. */
16763 tbl_data = container_of(mtrmng->drop_tbl[domain],
16764 struct mlx5_flow_tbl_data_entry, tbl);
16765 def_policy->dr_jump_action[RTE_COLOR_RED] =
16766 tbl_data->jump.action;
16767 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16768 acts[RTE_COLOR_RED].actions_n = 1;
16769 /* Create default policy rules. */
16770 ret = __flow_dv_create_domain_policy_rules(dev,
16771 &def_policy->sub_policy,
16772 egress, transfer, false, acts);
16774 DRV_LOG(ERR, "Failed to create default policy rules.");
16775 goto def_policy_error;
16780 __flow_dv_destroy_domain_def_policy(dev,
16781 (enum mlx5_meter_domain)domain);
16786 * Create the default policy table set.
16789 * Pointer to Ethernet device.
16791 * 0 on success, -1 otherwise.
16794 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16796 struct mlx5_priv *priv = dev->data->dev_private;
16799 /* Non-termination policy table. */
16800 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16801 if (!priv->sh->config.dv_esw_en &&
16802 i == MLX5_MTR_DOMAIN_TRANSFER)
16804 if (__flow_dv_create_domain_def_policy(dev, i)) {
16805 DRV_LOG(ERR, "Failed to create default policy");
16806 /* Rollback the created default policies for others. */
16807 flow_dv_destroy_def_policy(dev);
16815 * Create the needed meter tables.
16816 * Lock free, (mutex should be acquired by caller).
16819 * Pointer to Ethernet device.
16821 * Meter information table.
16822 * @param[in] mtr_idx
16824 * @param[in] domain_bitmap
16827 * 0 on success, -1 otherwise.
16830 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16831 struct mlx5_flow_meter_info *fm,
16833 uint8_t domain_bitmap)
16835 struct mlx5_priv *priv = dev->data->dev_private;
16836 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16837 struct rte_flow_error error;
16838 struct mlx5_flow_tbl_data_entry *tbl_data;
16839 uint8_t egress, transfer;
16840 void *actions[METER_ACTIONS];
16841 int domain, ret, i;
16842 struct mlx5_flow_counter *cnt;
16843 struct mlx5_flow_dv_match_params value = {
16844 .size = sizeof(value.buf),
16846 struct mlx5_flow_dv_match_params matcher_para = {
16847 .size = sizeof(matcher_para.buf),
16849 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16851 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16852 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16853 struct mlx5_list_entry *entry;
16854 struct mlx5_flow_dv_matcher matcher = {
16856 .size = sizeof(matcher.mask.buf),
16859 struct mlx5_flow_dv_matcher *drop_matcher;
16860 struct mlx5_flow_cb_ctx ctx = {
16866 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16867 rte_errno = ENOTSUP;
16870 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16871 if (!(domain_bitmap & (1 << domain)) ||
16872 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16874 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16875 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16876 /* Create the drop table with METER DROP level. */
16877 if (!mtrmng->drop_tbl[domain]) {
16878 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16879 MLX5_FLOW_TABLE_LEVEL_METER,
16880 egress, transfer, false, NULL, 0,
16881 0, MLX5_MTR_TABLE_ID_DROP, &error);
16882 if (!mtrmng->drop_tbl[domain]) {
16883 DRV_LOG(ERR, "Failed to create meter drop table.");
16887 /* Create default matcher in drop table. */
16888 matcher.tbl = mtrmng->drop_tbl[domain],
16889 tbl_data = container_of(mtrmng->drop_tbl[domain],
16890 struct mlx5_flow_tbl_data_entry, tbl);
16891 if (!mtrmng->def_matcher[domain]) {
16892 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16893 (enum modify_reg)mtr_id_reg_c,
16895 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16896 matcher.crc = rte_raw_cksum
16897 ((const void *)matcher.mask.buf,
16898 matcher.mask.size);
16899 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16901 DRV_LOG(ERR, "Failed to register meter "
16902 "drop default matcher.");
16905 mtrmng->def_matcher[domain] = container_of(entry,
16906 struct mlx5_flow_dv_matcher, entry);
16908 /* Create default rule in drop table. */
16909 if (!mtrmng->def_rule[domain]) {
16911 actions[i++] = priv->sh->dr_drop_action;
16912 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16913 (enum modify_reg)mtr_id_reg_c, 0, 0);
16914 misc_mask = flow_dv_matcher_enable(value.buf);
16915 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16916 ret = mlx5_flow_os_create_flow
16917 (mtrmng->def_matcher[domain]->matcher_object,
16918 (void *)&value, i, actions,
16919 &mtrmng->def_rule[domain]);
16921 DRV_LOG(ERR, "Failed to create meter "
16922 "default drop rule for drop table.");
16928 MLX5_ASSERT(mtrmng->max_mtr_bits);
16929 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16930 /* Create matchers for Drop. */
16931 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16932 (enum modify_reg)mtr_id_reg_c, 0,
16933 (mtr_id_mask << mtr_id_offset));
16934 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16935 matcher.crc = rte_raw_cksum
16936 ((const void *)matcher.mask.buf,
16937 matcher.mask.size);
16938 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16941 "Failed to register meter drop matcher.");
16944 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16945 container_of(entry, struct mlx5_flow_dv_matcher,
16949 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16950 /* Create drop rule, matching meter_id only. */
16951 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16952 (enum modify_reg)mtr_id_reg_c,
16953 (mtr_idx << mtr_id_offset), UINT32_MAX);
16955 cnt = flow_dv_counter_get_by_idx(dev,
16956 fm->drop_cnt, NULL);
16957 actions[i++] = cnt->action;
16958 actions[i++] = priv->sh->dr_drop_action;
16959 misc_mask = flow_dv_matcher_enable(value.buf);
16960 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16961 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16962 (void *)&value, i, actions,
16963 &fm->drop_rule[domain]);
16965 DRV_LOG(ERR, "Failed to create meter "
16966 "drop rule for drop table.");
16972 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16973 if (fm->drop_rule[i]) {
16974 claim_zero(mlx5_flow_os_destroy_flow
16975 (fm->drop_rule[i]));
16976 fm->drop_rule[i] = NULL;
16982 static struct mlx5_flow_meter_sub_policy *
16983 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16984 struct mlx5_flow_meter_policy *mtr_policy,
16985 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16986 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16989 struct mlx5_priv *priv = dev->data->dev_private;
16990 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16991 uint32_t sub_policy_idx = 0;
16992 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16994 struct mlx5_hrxq *hrxq;
16995 struct mlx5_flow_handle dh;
16996 struct mlx5_meter_policy_action_container *act_cnt;
16997 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16998 uint16_t sub_policy_num;
16999 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
17002 rte_spinlock_lock(&mtr_policy->sl);
17003 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17006 hrxq = mlx5_hrxq_get(dev, rss_desc[i]);
17008 rte_spinlock_unlock(&mtr_policy->sl);
17011 hrxq_idx[i] = hrxq->idx;
17013 sub_policy_num = (mtr_policy->sub_policy_num >>
17014 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17015 MLX5_MTR_SUB_POLICY_NUM_MASK;
17016 for (j = 0; j < sub_policy_num; j++) {
17017 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17020 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
17023 if (i >= MLX5_MTR_RTE_COLORS) {
17025 * Found the sub policy table with
17026 * the same queue per color.
17028 rte_spinlock_unlock(&mtr_policy->sl);
17029 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17030 mlx5_hrxq_release(dev, hrxq_idx[i]);
17032 return mtr_policy->sub_policys[domain][j];
17035 /* Create sub policy. */
17036 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
17037 /* Reuse the first pre-allocated sub_policy. */
17038 sub_policy = mtr_policy->sub_policys[domain][0];
17039 sub_policy_idx = sub_policy->idx;
17041 sub_policy = mlx5_ipool_zmalloc
17042 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17045 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
17046 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17047 mlx5_hrxq_release(dev, hrxq_idx[i]);
17048 goto rss_sub_policy_error;
17050 sub_policy->idx = sub_policy_idx;
17051 sub_policy->main_policy = mtr_policy;
17053 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17056 sub_policy->rix_hrxq[i] = hrxq_idx[i];
17057 if (mtr_policy->is_hierarchy) {
17058 act_cnt = &mtr_policy->act_cnt[i];
17059 act_cnt->next_sub_policy = next_sub_policy;
17060 mlx5_hrxq_release(dev, hrxq_idx[i]);
17063 * Overwrite the last action from
17064 * RSS action to Queue action.
17066 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
17069 DRV_LOG(ERR, "Failed to get policy hrxq");
17070 goto rss_sub_policy_error;
17072 act_cnt = &mtr_policy->act_cnt[i];
17073 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
17074 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
17075 if (act_cnt->rix_mark)
17077 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
17078 dh.rix_hrxq = hrxq_idx[i];
17079 flow_drv_rxq_flags_set(dev, &dh);
17083 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
17084 sub_policy, domain)) {
17085 DRV_LOG(ERR, "Failed to create policy "
17086 "rules for ingress domain.");
17087 goto rss_sub_policy_error;
17089 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17090 i = (mtr_policy->sub_policy_num >>
17091 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17092 MLX5_MTR_SUB_POLICY_NUM_MASK;
17093 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
17094 DRV_LOG(ERR, "No free sub-policy slot.");
17095 goto rss_sub_policy_error;
17097 mtr_policy->sub_policys[domain][i] = sub_policy;
17099 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17100 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17101 mtr_policy->sub_policy_num |=
17102 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17103 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17105 rte_spinlock_unlock(&mtr_policy->sl);
17108 rss_sub_policy_error:
17110 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17111 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17112 i = (mtr_policy->sub_policy_num >>
17113 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17114 MLX5_MTR_SUB_POLICY_NUM_MASK;
17115 mtr_policy->sub_policys[domain][i] = NULL;
17116 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17120 rte_spinlock_unlock(&mtr_policy->sl);
17125 * Find the policy table for prefix table with RSS.
17128 * Pointer to Ethernet device.
17129 * @param[in] mtr_policy
17130 * Pointer to meter policy table.
17131 * @param[in] rss_desc
17132 * Pointer to rss_desc
17134 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17136 static struct mlx5_flow_meter_sub_policy *
17137 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17138 struct mlx5_flow_meter_policy *mtr_policy,
17139 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17141 struct mlx5_priv *priv = dev->data->dev_private;
17142 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17143 struct mlx5_flow_meter_info *next_fm;
17144 struct mlx5_flow_meter_policy *next_policy;
17145 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17146 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17147 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17148 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17149 bool reuse_sub_policy;
17154 /* Iterate hierarchy to get all policies in this hierarchy. */
17155 policies[i++] = mtr_policy;
17156 if (!mtr_policy->is_hierarchy)
17158 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17159 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17162 next_fm = mlx5_flow_meter_find(priv,
17163 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17165 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17169 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17171 MLX5_ASSERT(next_policy);
17172 mtr_policy = next_policy;
17176 * From last policy to the first one in hierarchy,
17177 * create / get the sub policy for each of them.
17179 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17183 &reuse_sub_policy);
17185 DRV_LOG(ERR, "Failed to get the sub policy.");
17188 if (!reuse_sub_policy)
17189 sub_policies[j++] = sub_policy;
17190 next_sub_policy = sub_policy;
17195 uint16_t sub_policy_num;
17197 sub_policy = sub_policies[--j];
17198 mtr_policy = sub_policy->main_policy;
17199 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17200 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17201 sub_policy_num = (mtr_policy->sub_policy_num >>
17202 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17203 MLX5_MTR_SUB_POLICY_NUM_MASK;
17204 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17207 mtr_policy->sub_policy_num &=
17208 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17209 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17210 mtr_policy->sub_policy_num |=
17211 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17212 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17213 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17221 * Create the sub policy tag rule for all meters in hierarchy.
17224 * Pointer to Ethernet device.
17226 * Meter information table.
17227 * @param[in] src_port
17228 * The src port this extra rule should use.
17230 * The src port match item.
17231 * @param[out] error
17232 * Perform verbose error reporting if not NULL.
17234 * 0 on success, a negative errno value otherwise and rte_errno is set.
17237 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17238 struct mlx5_flow_meter_info *fm,
17240 const struct rte_flow_item *item,
17241 struct rte_flow_error *error)
17243 struct mlx5_priv *priv = dev->data->dev_private;
17244 struct mlx5_flow_meter_policy *mtr_policy;
17245 struct mlx5_flow_meter_sub_policy *sub_policy;
17246 struct mlx5_flow_meter_info *next_fm = NULL;
17247 struct mlx5_flow_meter_policy *next_policy;
17248 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17249 struct mlx5_flow_tbl_data_entry *tbl_data;
17250 struct mlx5_sub_policy_color_rule *color_rule;
17251 struct mlx5_meter_policy_acts acts;
17252 uint32_t color_reg_c_idx;
17253 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17254 struct rte_flow_attr attr = {
17255 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17262 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17265 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17266 MLX5_ASSERT(mtr_policy);
17267 if (!mtr_policy->is_hierarchy)
17269 next_fm = mlx5_flow_meter_find(priv,
17270 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17272 return rte_flow_error_set(error, EINVAL,
17273 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17274 "Failed to find next meter in hierarchy.");
17276 if (!next_fm->drop_cnt)
17278 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17279 sub_policy = mtr_policy->sub_policys[domain][0];
17280 for (i = 0; i < RTE_COLORS; i++) {
17281 bool rule_exist = false;
17282 struct mlx5_meter_policy_action_container *act_cnt;
17284 if (i >= RTE_COLOR_YELLOW)
17286 TAILQ_FOREACH(color_rule,
17287 &sub_policy->color_rules[i], next_port)
17288 if (color_rule->src_port == src_port) {
17294 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17295 sizeof(struct mlx5_sub_policy_color_rule),
17298 return rte_flow_error_set(error, ENOMEM,
17299 RTE_FLOW_ERROR_TYPE_ACTION,
17300 NULL, "No memory to create tag color rule.");
17301 color_rule->src_port = src_port;
17303 next_policy = mlx5_flow_meter_policy_find(dev,
17304 next_fm->policy_id, NULL);
17305 MLX5_ASSERT(next_policy);
17306 next_sub_policy = next_policy->sub_policys[domain][0];
17307 tbl_data = container_of(next_sub_policy->tbl_rsc,
17308 struct mlx5_flow_tbl_data_entry, tbl);
17309 act_cnt = &mtr_policy->act_cnt[i];
17311 acts.dv_actions[0] = next_fm->meter_action;
17312 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17314 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17315 acts.dv_actions[1] = next_fm->meter_action;
17317 acts.dv_actions[2] = tbl_data->jump.action;
17318 acts.actions_n = 3;
17319 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17323 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17324 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17326 &color_rule->matcher, error)) {
17327 rte_flow_error_set(error, errno,
17328 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17329 "Failed to create hierarchy meter matcher.");
17332 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17334 color_rule->matcher->matcher_object,
17335 acts.actions_n, acts.dv_actions,
17337 &color_rule->rule, &attr)) {
17338 rte_flow_error_set(error, errno,
17339 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17340 "Failed to create hierarchy meter rule.");
17343 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17344 color_rule, next_port);
17348 * Recursive call to iterate all meters in hierarchy and
17349 * create needed rules.
17351 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17352 src_port, item, error);
17355 if (color_rule->rule)
17356 mlx5_flow_os_destroy_flow(color_rule->rule);
17357 if (color_rule->matcher) {
17358 struct mlx5_flow_tbl_data_entry *tbl =
17359 container_of(color_rule->matcher->tbl,
17360 typeof(*tbl), tbl);
17361 mlx5_list_unregister(tbl->matchers,
17362 &color_rule->matcher->entry);
17364 mlx5_free(color_rule);
17367 mlx5_flow_meter_detach(priv, next_fm);
17372 * Destroy the sub policy table with RX queue.
17375 * Pointer to Ethernet device.
17376 * @param[in] mtr_policy
17377 * Pointer to meter policy table.
17380 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17381 struct mlx5_flow_meter_policy *mtr_policy)
17383 struct mlx5_priv *priv = dev->data->dev_private;
17384 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17385 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17387 uint16_t sub_policy_num, new_policy_num;
17389 rte_spinlock_lock(&mtr_policy->sl);
17390 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17391 switch (mtr_policy->act_cnt[i].fate_action) {
17392 case MLX5_FLOW_FATE_SHARED_RSS:
17393 sub_policy_num = (mtr_policy->sub_policy_num >>
17394 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17395 MLX5_MTR_SUB_POLICY_NUM_MASK;
17396 new_policy_num = sub_policy_num;
17397 for (j = 0; j < sub_policy_num; j++) {
17399 mtr_policy->sub_policys[domain][j];
17401 __flow_dv_destroy_sub_policy_rules(dev,
17404 mtr_policy->sub_policys[domain][0]) {
17405 mtr_policy->sub_policys[domain][j] =
17408 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17414 if (new_policy_num != sub_policy_num) {
17415 mtr_policy->sub_policy_num &=
17416 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17417 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17418 mtr_policy->sub_policy_num |=
17420 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17421 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17424 case MLX5_FLOW_FATE_QUEUE:
17425 sub_policy = mtr_policy->sub_policys[domain][0];
17426 __flow_dv_destroy_sub_policy_rules(dev,
17430 /*Other actions without queue and do nothing*/
17434 rte_spinlock_unlock(&mtr_policy->sl);
17437 * Check whether the DR drop action is supported on the root table or not.
17439 * Create a simple flow with DR drop action on root table to validate
17440 * if DR drop action on root table is supported or not.
17443 * Pointer to rte_eth_dev structure.
17446 * 0 on success, a negative errno value otherwise and rte_errno is set.
17449 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17451 struct mlx5_priv *priv = dev->data->dev_private;
17452 struct mlx5_dev_ctx_shared *sh = priv->sh;
17453 struct mlx5_flow_dv_match_params mask = {
17454 .size = sizeof(mask.buf),
17456 struct mlx5_flow_dv_match_params value = {
17457 .size = sizeof(value.buf),
17459 struct mlx5dv_flow_matcher_attr dv_attr = {
17460 .type = IBV_FLOW_ATTR_NORMAL,
17462 .match_criteria_enable = 0,
17463 .match_mask = (void *)&mask,
17465 struct mlx5_flow_tbl_resource *tbl = NULL;
17466 void *matcher = NULL;
17470 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17474 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17475 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17476 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17477 tbl->obj, &matcher);
17480 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17481 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17482 &sh->dr_drop_action, &flow);
17485 * If DR drop action is not supported on root table, flow create will
17486 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17490 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17491 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17493 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17496 claim_zero(mlx5_flow_os_destroy_flow(flow));
17499 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17501 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17506 * Validate the batch counter support in root table.
17508 * Create a simple flow with invalid counter and drop action on root table to
17509 * validate if batch counter with offset on root table is supported or not.
17512 * Pointer to rte_eth_dev structure.
17515 * 0 on success, a negative errno value otherwise and rte_errno is set.
17518 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17520 struct mlx5_priv *priv = dev->data->dev_private;
17521 struct mlx5_dev_ctx_shared *sh = priv->sh;
17522 struct mlx5_flow_dv_match_params mask = {
17523 .size = sizeof(mask.buf),
17525 struct mlx5_flow_dv_match_params value = {
17526 .size = sizeof(value.buf),
17528 struct mlx5dv_flow_matcher_attr dv_attr = {
17529 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17531 .match_criteria_enable = 0,
17532 .match_mask = (void *)&mask,
17534 void *actions[2] = { 0 };
17535 struct mlx5_flow_tbl_resource *tbl = NULL;
17536 struct mlx5_devx_obj *dcs = NULL;
17537 void *matcher = NULL;
17541 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17545 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17548 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17552 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17553 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17554 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17555 tbl->obj, &matcher);
17558 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17559 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17563 * If batch counter with offset is not supported, the driver will not
17564 * validate the invalid offset value, flow create should success.
17565 * In this case, it means batch counter is not supported in root table.
17567 * Otherwise, if flow create is failed, counter offset is supported.
17570 DRV_LOG(INFO, "Batch counter is not supported in root "
17571 "table. Switch to fallback mode.");
17572 rte_errno = ENOTSUP;
17574 claim_zero(mlx5_flow_os_destroy_flow(flow));
17576 /* Check matcher to make sure validate fail at flow create. */
17577 if (!matcher || (matcher && errno != EINVAL))
17578 DRV_LOG(ERR, "Unexpected error in counter offset "
17579 "support detection");
17583 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17585 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17587 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17589 claim_zero(mlx5_devx_cmd_destroy(dcs));
17594 * Query a devx counter.
17597 * Pointer to the Ethernet device structure.
17599 * Index to the flow counter.
17601 * Set to clear the counter statistics.
17603 * The statistics value of packets.
17604 * @param[out] bytes
17605 * The statistics value of bytes.
17608 * 0 on success, otherwise return -1.
17611 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17612 uint64_t *pkts, uint64_t *bytes, void **action)
17614 struct mlx5_priv *priv = dev->data->dev_private;
17615 struct mlx5_flow_counter *cnt;
17616 uint64_t inn_pkts, inn_bytes;
17619 if (!priv->sh->cdev->config.devx)
17622 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17625 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17627 *action = cnt->action;
17629 *pkts = inn_pkts - cnt->hits;
17630 *bytes = inn_bytes - cnt->bytes;
17632 cnt->hits = inn_pkts;
17633 cnt->bytes = inn_bytes;
17639 * Get aged-out flows.
17642 * Pointer to the Ethernet device structure.
17643 * @param[in] context
17644 * The address of an array of pointers to the aged-out flows contexts.
17645 * @param[in] nb_contexts
17646 * The length of context array pointers.
17647 * @param[out] error
17648 * Perform verbose error reporting if not NULL. Initialized in case of
17652 * how many contexts get in success, otherwise negative errno value.
17653 * if nb_contexts is 0, return the amount of all aged contexts.
17654 * if nb_contexts is not 0 , return the amount of aged flows reported
17655 * in the context array.
17656 * @note: only stub for now
17659 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17661 uint32_t nb_contexts,
17662 struct rte_flow_error *error)
17664 struct mlx5_priv *priv = dev->data->dev_private;
17665 struct mlx5_age_info *age_info;
17666 struct mlx5_age_param *age_param;
17667 struct mlx5_flow_counter *counter;
17668 struct mlx5_aso_age_action *act;
17671 if (nb_contexts && !context)
17672 return rte_flow_error_set(error, EINVAL,
17673 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17674 NULL, "empty context");
17675 age_info = GET_PORT_AGE_INFO(priv);
17676 rte_spinlock_lock(&age_info->aged_sl);
17677 LIST_FOREACH(act, &age_info->aged_aso, next) {
17680 context[nb_flows - 1] =
17681 act->age_params.context;
17682 if (!(--nb_contexts))
17686 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17689 age_param = MLX5_CNT_TO_AGE(counter);
17690 context[nb_flows - 1] = age_param->context;
17691 if (!(--nb_contexts))
17695 rte_spinlock_unlock(&age_info->aged_sl);
17696 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17701 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17704 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17706 return flow_dv_counter_alloc(dev, 0);
17710 * Validate indirect action.
17711 * Dispatcher for action type specific validation.
17714 * Pointer to the Ethernet device structure.
17716 * Indirect action configuration.
17717 * @param[in] action
17718 * The indirect action object to validate.
17719 * @param[out] error
17720 * Perform verbose error reporting if not NULL. Initialized in case of
17724 * 0 on success, otherwise negative errno value.
17727 flow_dv_action_validate(struct rte_eth_dev *dev,
17728 const struct rte_flow_indir_action_conf *conf,
17729 const struct rte_flow_action *action,
17730 struct rte_flow_error *err)
17732 struct mlx5_priv *priv = dev->data->dev_private;
17734 RTE_SET_USED(conf);
17735 switch (action->type) {
17736 case RTE_FLOW_ACTION_TYPE_RSS:
17738 * priv->obj_ops is set according to driver capabilities.
17739 * When DevX capabilities are
17740 * sufficient, it is set to devx_obj_ops.
17741 * Otherwise, it is set to ibv_obj_ops.
17742 * ibv_obj_ops doesn't support ind_table_modify operation.
17743 * In this case the indirect RSS action can't be used.
17745 if (priv->obj_ops.ind_table_modify == NULL)
17746 return rte_flow_error_set
17748 RTE_FLOW_ERROR_TYPE_ACTION,
17750 "Indirect RSS action not supported");
17751 return mlx5_validate_action_rss(dev, action, err);
17752 case RTE_FLOW_ACTION_TYPE_AGE:
17753 if (!priv->sh->aso_age_mng)
17754 return rte_flow_error_set(err, ENOTSUP,
17755 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17757 "Indirect age action not supported");
17758 return flow_dv_validate_action_age(0, action, dev, err);
17759 case RTE_FLOW_ACTION_TYPE_COUNT:
17760 return flow_dv_validate_action_count(dev, true, 0, NULL, err);
17761 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17762 if (!priv->sh->ct_aso_en)
17763 return rte_flow_error_set(err, ENOTSUP,
17764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17765 "ASO CT is not supported");
17766 return mlx5_validate_action_ct(dev, action->conf, err);
17768 return rte_flow_error_set(err, ENOTSUP,
17769 RTE_FLOW_ERROR_TYPE_ACTION,
17771 "action type not supported");
17776 * Check if the RSS configurations for colors of a meter policy match
17777 * each other, except the queues.
17780 * Pointer to the first RSS flow action.
17782 * Pointer to the second RSS flow action.
17785 * 0 on match, 1 on conflict.
17788 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17789 const struct rte_flow_action_rss *r2)
17791 if (r1 == NULL || r2 == NULL)
17793 if (!(r1->level <= 1 && r2->level <= 1) &&
17794 !(r1->level > 1 && r2->level > 1))
17796 if (r1->types != r2->types &&
17797 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17798 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17800 if (r1->key || r2->key) {
17801 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17802 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17804 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17811 * Validate the meter hierarchy chain for meter policy.
17814 * Pointer to the Ethernet device structure.
17815 * @param[in] meter_id
17817 * @param[in] action_flags
17818 * Holds the actions detected until now.
17819 * @param[out] is_rss
17821 * @param[out] hierarchy_domain
17822 * The domain bitmap for hierarchy policy.
17823 * @param[out] error
17824 * Perform verbose error reporting if not NULL. Initialized in case of
17828 * 0 on success, otherwise negative errno value with error set.
17831 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17833 uint64_t action_flags,
17835 uint8_t *hierarchy_domain,
17836 struct rte_mtr_error *error)
17838 struct mlx5_priv *priv = dev->data->dev_private;
17839 struct mlx5_flow_meter_info *fm;
17840 struct mlx5_flow_meter_policy *policy;
17843 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17844 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17845 return -rte_mtr_error_set(error, EINVAL,
17846 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17848 "Multiple fate actions not supported.");
17849 *hierarchy_domain = 0;
17851 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17853 return -rte_mtr_error_set(error, EINVAL,
17854 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17855 "Meter not found in meter hierarchy.");
17856 if (fm->def_policy)
17857 return -rte_mtr_error_set(error, EINVAL,
17858 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17859 "Non termination meter not supported in hierarchy.");
17860 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17861 MLX5_ASSERT(policy);
17863 * Only inherit the supported domains of the first meter in
17865 * One meter supports at least one domain.
17867 if (!*hierarchy_domain) {
17868 if (policy->transfer)
17869 *hierarchy_domain |=
17870 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17871 if (policy->ingress)
17872 *hierarchy_domain |=
17873 MLX5_MTR_DOMAIN_INGRESS_BIT;
17874 if (policy->egress)
17875 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17877 if (!policy->is_hierarchy) {
17878 *is_rss = policy->is_rss;
17881 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17882 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17883 return -rte_mtr_error_set(error, EINVAL,
17884 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17885 "Exceed max hierarchy meter number.");
17891 * Validate meter policy actions.
17892 * Dispatcher for action type specific validation.
17895 * Pointer to the Ethernet device structure.
17896 * @param[in] action
17897 * The meter policy action object to validate.
17899 * Attributes of flow to determine steering domain.
17900 * @param[out] error
17901 * Perform verbose error reporting if not NULL. Initialized in case of
17905 * 0 on success, otherwise negative errno value.
17908 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17909 const struct rte_flow_action *actions[RTE_COLORS],
17910 struct rte_flow_attr *attr,
17912 uint8_t *domain_bitmap,
17913 uint8_t *policy_mode,
17914 struct rte_mtr_error *error)
17916 struct mlx5_priv *priv = dev->data->dev_private;
17917 struct mlx5_sh_config *dev_conf = &priv->sh->config;
17918 const struct rte_flow_action *act;
17919 uint64_t action_flags[RTE_COLORS] = {0};
17922 struct rte_flow_error flow_err;
17923 uint8_t domain_color[RTE_COLORS] = {0};
17924 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17925 uint8_t hierarchy_domain = 0;
17926 const struct rte_flow_action_meter *mtr;
17927 bool def_green = false;
17928 bool def_yellow = false;
17929 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17931 if (!dev_conf->dv_esw_en)
17932 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17933 *domain_bitmap = def_domain;
17934 /* Red color could only support DROP action. */
17935 if (!actions[RTE_COLOR_RED] ||
17936 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17937 return -rte_mtr_error_set(error, ENOTSUP,
17938 RTE_MTR_ERROR_TYPE_METER_POLICY,
17939 NULL, "Red color only supports drop action.");
17941 * Check default policy actions:
17942 * Green / Yellow: no action, Red: drop action
17943 * Either G or Y will trigger default policy actions to be created.
17945 if (!actions[RTE_COLOR_GREEN] ||
17946 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17948 if (!actions[RTE_COLOR_YELLOW] ||
17949 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17951 if (def_green && def_yellow) {
17952 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17954 } else if (!def_green && def_yellow) {
17955 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17956 } else if (def_green && !def_yellow) {
17957 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17959 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17961 /* Set to empty string in case of NULL pointer access by user. */
17962 flow_err.message = "";
17963 for (i = 0; i < RTE_COLORS; i++) {
17965 for (action_flags[i] = 0, actions_n = 0;
17966 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17968 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17969 return -rte_mtr_error_set(error, ENOTSUP,
17970 RTE_MTR_ERROR_TYPE_METER_POLICY,
17971 NULL, "too many actions");
17972 switch (act->type) {
17973 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17974 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17975 if (!dev_conf->dv_esw_en)
17976 return -rte_mtr_error_set(error,
17978 RTE_MTR_ERROR_TYPE_METER_POLICY,
17979 NULL, "PORT action validate check"
17980 " fail for ESW disable");
17981 ret = flow_dv_validate_action_port_id(dev,
17983 act, attr, &flow_err);
17985 return -rte_mtr_error_set(error,
17987 RTE_MTR_ERROR_TYPE_METER_POLICY,
17988 NULL, flow_err.message ?
17990 "PORT action validate check fail");
17992 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17994 case RTE_FLOW_ACTION_TYPE_MARK:
17995 ret = flow_dv_validate_action_mark(dev, act,
17999 return -rte_mtr_error_set(error,
18001 RTE_MTR_ERROR_TYPE_METER_POLICY,
18002 NULL, flow_err.message ?
18004 "Mark action validate check fail");
18005 if (dev_conf->dv_xmeta_en !=
18006 MLX5_XMETA_MODE_LEGACY)
18007 return -rte_mtr_error_set(error,
18009 RTE_MTR_ERROR_TYPE_METER_POLICY,
18010 NULL, "Extend MARK action is "
18011 "not supported. Please try use "
18012 "default policy for meter.");
18013 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
18016 case RTE_FLOW_ACTION_TYPE_SET_TAG:
18017 ret = flow_dv_validate_action_set_tag(dev,
18018 act, action_flags[i],
18021 return -rte_mtr_error_set(error,
18023 RTE_MTR_ERROR_TYPE_METER_POLICY,
18024 NULL, flow_err.message ?
18026 "Set tag action validate check fail");
18027 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
18030 case RTE_FLOW_ACTION_TYPE_DROP:
18031 ret = mlx5_flow_validate_action_drop
18032 (action_flags[i], attr, &flow_err);
18034 return -rte_mtr_error_set(error,
18036 RTE_MTR_ERROR_TYPE_METER_POLICY,
18037 NULL, flow_err.message ?
18039 "Drop action validate check fail");
18040 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
18043 case RTE_FLOW_ACTION_TYPE_QUEUE:
18045 * Check whether extensive
18046 * metadata feature is engaged.
18048 if (dev_conf->dv_flow_en &&
18049 (dev_conf->dv_xmeta_en !=
18050 MLX5_XMETA_MODE_LEGACY) &&
18051 mlx5_flow_ext_mreg_supported(dev))
18052 return -rte_mtr_error_set(error,
18054 RTE_MTR_ERROR_TYPE_METER_POLICY,
18055 NULL, "Queue action with meta "
18056 "is not supported. Please try use "
18057 "default policy for meter.");
18058 ret = mlx5_flow_validate_action_queue(act,
18059 action_flags[i], dev,
18062 return -rte_mtr_error_set(error,
18064 RTE_MTR_ERROR_TYPE_METER_POLICY,
18065 NULL, flow_err.message ?
18067 "Queue action validate check fail");
18068 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
18071 case RTE_FLOW_ACTION_TYPE_RSS:
18072 if (dev_conf->dv_flow_en &&
18073 (dev_conf->dv_xmeta_en !=
18074 MLX5_XMETA_MODE_LEGACY) &&
18075 mlx5_flow_ext_mreg_supported(dev))
18076 return -rte_mtr_error_set(error,
18078 RTE_MTR_ERROR_TYPE_METER_POLICY,
18079 NULL, "RSS action with meta "
18080 "is not supported. Please try use "
18081 "default policy for meter.");
18082 ret = mlx5_validate_action_rss(dev, act,
18085 return -rte_mtr_error_set(error,
18087 RTE_MTR_ERROR_TYPE_METER_POLICY,
18088 NULL, flow_err.message ?
18090 "RSS action validate check fail");
18091 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
18093 /* Either G or Y will set the RSS. */
18094 rss_color[i] = act->conf;
18096 case RTE_FLOW_ACTION_TYPE_JUMP:
18097 ret = flow_dv_validate_action_jump(dev,
18098 NULL, act, action_flags[i],
18099 attr, true, &flow_err);
18101 return -rte_mtr_error_set(error,
18103 RTE_MTR_ERROR_TYPE_METER_POLICY,
18104 NULL, flow_err.message ?
18106 "Jump action validate check fail");
18108 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
18111 * Only the last meter in the hierarchy will support
18112 * the YELLOW color steering. Then in the meter policy
18113 * actions list, there should be no other meter inside.
18115 case RTE_FLOW_ACTION_TYPE_METER:
18116 if (i != RTE_COLOR_GREEN)
18117 return -rte_mtr_error_set(error,
18119 RTE_MTR_ERROR_TYPE_METER_POLICY,
18121 "Meter hierarchy only supports GREEN color.");
18122 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
18123 return -rte_mtr_error_set(error,
18125 RTE_MTR_ERROR_TYPE_METER_POLICY,
18127 "No yellow policy should be provided in meter hierarchy.");
18129 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18139 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18142 return -rte_mtr_error_set(error, ENOTSUP,
18143 RTE_MTR_ERROR_TYPE_METER_POLICY,
18145 "Doesn't support optional action");
18148 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18149 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18150 } else if ((action_flags[i] &
18151 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18152 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18154 * Only support MLX5_XMETA_MODE_LEGACY
18155 * so MARK action is only in ingress domain.
18157 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18159 domain_color[i] = def_domain;
18160 if (action_flags[i] &&
18161 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18163 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18165 if (action_flags[i] &
18166 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18167 domain_color[i] &= hierarchy_domain;
18169 * Non-termination actions only support NIC Tx domain.
18170 * The adjustion should be skipped when there is no
18171 * action or only END is provided. The default domains
18172 * bit-mask is set to find the MIN intersection.
18173 * The action flags checking should also be skipped.
18175 if ((def_green && i == RTE_COLOR_GREEN) ||
18176 (def_yellow && i == RTE_COLOR_YELLOW))
18179 * Validate the drop action mutual exclusion
18180 * with other actions. Drop action is mutually-exclusive
18181 * with any other action, except for Count action.
18183 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18184 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18185 return -rte_mtr_error_set(error, ENOTSUP,
18186 RTE_MTR_ERROR_TYPE_METER_POLICY,
18187 NULL, "Drop action is mutually-exclusive "
18188 "with any other action");
18190 /* Eswitch has few restrictions on using items and actions */
18191 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18192 if (!mlx5_flow_ext_mreg_supported(dev) &&
18193 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18194 return -rte_mtr_error_set(error, ENOTSUP,
18195 RTE_MTR_ERROR_TYPE_METER_POLICY,
18196 NULL, "unsupported action MARK");
18197 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18198 return -rte_mtr_error_set(error, ENOTSUP,
18199 RTE_MTR_ERROR_TYPE_METER_POLICY,
18200 NULL, "unsupported action QUEUE");
18201 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18202 return -rte_mtr_error_set(error, ENOTSUP,
18203 RTE_MTR_ERROR_TYPE_METER_POLICY,
18204 NULL, "unsupported action RSS");
18205 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18206 return -rte_mtr_error_set(error, ENOTSUP,
18207 RTE_MTR_ERROR_TYPE_METER_POLICY,
18208 NULL, "no fate action is found");
18210 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18211 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18212 if ((domain_color[i] &
18213 MLX5_MTR_DOMAIN_EGRESS_BIT))
18215 MLX5_MTR_DOMAIN_EGRESS_BIT;
18217 return -rte_mtr_error_set(error,
18219 RTE_MTR_ERROR_TYPE_METER_POLICY,
18221 "no fate action is found");
18225 /* If both colors have RSS, the attributes should be the same. */
18226 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18227 rss_color[RTE_COLOR_YELLOW]))
18228 return -rte_mtr_error_set(error, EINVAL,
18229 RTE_MTR_ERROR_TYPE_METER_POLICY,
18230 NULL, "policy RSS attr conflict");
18231 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18233 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18234 if (!def_green && !def_yellow &&
18235 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18236 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18237 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18238 return -rte_mtr_error_set(error, EINVAL,
18239 RTE_MTR_ERROR_TYPE_METER_POLICY,
18240 NULL, "policy domains conflict");
18242 * At least one color policy is listed in the actions, the domains
18243 * to be supported should be the intersection.
18245 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18246 domain_color[RTE_COLOR_YELLOW];
18251 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18253 struct mlx5_priv *priv = dev->data->dev_private;
18256 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18257 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18262 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18263 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18267 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18268 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18276 * Discover the number of available flow priorities
18277 * by trying to create a flow with the highest priority value
18278 * for each possible number.
18283 * List of possible number of available priorities.
18284 * @param[in] vprio_n
18285 * Size of @p vprio array.
18287 * On success, number of available flow priorities.
18288 * On failure, a negative errno-style code and rte_errno is set.
18291 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18292 const uint16_t *vprio, int vprio_n)
18294 struct mlx5_priv *priv = dev->data->dev_private;
18295 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18296 struct rte_flow_item_eth eth;
18297 struct rte_flow_item item = {
18298 .type = RTE_FLOW_ITEM_TYPE_ETH,
18302 struct mlx5_flow_dv_matcher matcher = {
18304 .size = sizeof(matcher.mask.buf),
18307 union mlx5_flow_tbl_key tbl_key;
18308 struct mlx5_flow flow;
18310 struct rte_flow_error error;
18312 int i, err, ret = -ENOTSUP;
18315 * Prepare a flow with a catch-all pattern and a drop action.
18316 * Use drop queue, because shared drop action may be unavailable.
18318 action = priv->drop_queue.hrxq->action;
18319 if (action == NULL) {
18320 DRV_LOG(ERR, "Priority discovery requires a drop action");
18321 rte_errno = ENOTSUP;
18324 memset(&flow, 0, sizeof(flow));
18325 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18326 if (flow.handle == NULL) {
18327 DRV_LOG(ERR, "Cannot create flow handle");
18328 rte_errno = ENOMEM;
18331 flow.ingress = true;
18332 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18333 flow.dv.actions[0] = action;
18334 flow.dv.actions_n = 1;
18335 memset(ð, 0, sizeof(eth));
18336 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18337 &item, /* inner */ false, /* group */ 0);
18338 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18339 for (i = 0; i < vprio_n; i++) {
18340 /* Configure the next proposed maximum priority. */
18341 matcher.priority = vprio[i] - 1;
18342 memset(&tbl_key, 0, sizeof(tbl_key));
18343 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18348 /* This action is pure SW and must always succeed. */
18349 DRV_LOG(ERR, "Cannot register matcher");
18353 /* Try to apply the flow to HW. */
18354 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18355 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18356 err = mlx5_flow_os_create_flow
18357 (flow.handle->dvh.matcher->matcher_object,
18358 (void *)&flow.dv.value, flow.dv.actions_n,
18359 flow.dv.actions, &flow.handle->drv_flow);
18361 claim_zero(mlx5_flow_os_destroy_flow
18362 (flow.handle->drv_flow));
18363 flow.handle->drv_flow = NULL;
18365 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18370 mlx5_ipool_free(pool, flow.handle_idx);
18371 /* Set rte_errno if no expected priority value matched. */
18377 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18378 .validate = flow_dv_validate,
18379 .prepare = flow_dv_prepare,
18380 .translate = flow_dv_translate,
18381 .apply = flow_dv_apply,
18382 .remove = flow_dv_remove,
18383 .destroy = flow_dv_destroy,
18384 .query = flow_dv_query,
18385 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18386 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18387 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18388 .create_meter = flow_dv_mtr_alloc,
18389 .free_meter = flow_dv_aso_mtr_release_to_pool,
18390 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18391 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18392 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18393 .create_policy_rules = flow_dv_create_policy_rules,
18394 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18395 .create_def_policy = flow_dv_create_def_policy,
18396 .destroy_def_policy = flow_dv_destroy_def_policy,
18397 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18398 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18399 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18400 .counter_alloc = flow_dv_counter_allocate,
18401 .counter_free = flow_dv_counter_free,
18402 .counter_query = flow_dv_counter_query,
18403 .get_aged_flows = flow_dv_get_aged_flows,
18404 .action_validate = flow_dv_action_validate,
18405 .action_create = flow_dv_action_create,
18406 .action_destroy = flow_dv_action_destroy,
18407 .action_update = flow_dv_action_update,
18408 .action_query = flow_dv_action_query,
18409 .sync_domain = flow_dv_sync_domain,
18410 .discover_priorities = flow_dv_discover_priorities,
18411 .item_create = flow_dv_item_create,
18412 .item_release = flow_dv_item_release,
18415 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */