1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
216 * Convert modify-header action to DV specification.
219 * Pointer to item specification.
221 * Pointer to field modification information.
222 * @param[in,out] resource
223 * Pointer to the modify-header resource.
225 * Type of modification.
227 * Pointer to the error structure.
230 * 0 on success, a negative errno value otherwise and rte_errno is set.
233 flow_dv_convert_modify_action(struct rte_flow_item *item,
234 struct field_modify_info *field,
235 struct mlx5_flow_dv_modify_hdr_resource *resource,
237 struct rte_flow_error *error)
239 uint32_t i = resource->actions_num;
240 struct mlx5_modification_cmd *actions = resource->actions;
241 const uint8_t *spec = item->spec;
242 const uint8_t *mask = item->mask;
245 while (field->size) {
247 /* Generate modify command for each mask segment. */
248 memcpy(&set, &mask[field->offset], field->size);
250 if (i >= MLX5_MODIFY_NUM)
251 return rte_flow_error_set(error, EINVAL,
252 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
253 "too many items to modify");
254 actions[i].action_type = type;
255 actions[i].field = field->id;
256 actions[i].length = field->size ==
257 4 ? 0 : field->size * 8;
258 rte_memcpy(&actions[i].data[4 - field->size],
259 &spec[field->offset], field->size);
260 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
263 if (resource->actions_num != i)
264 resource->actions_num = i;
267 if (!resource->actions_num)
268 return rte_flow_error_set(error, EINVAL,
269 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
270 "invalid modification flow item");
275 * Convert modify-header set IPv4 address action to DV specification.
277 * @param[in,out] resource
278 * Pointer to the modify-header resource.
280 * Pointer to action specification.
282 * Pointer to the error structure.
285 * 0 on success, a negative errno value otherwise and rte_errno is set.
288 flow_dv_convert_action_modify_ipv4
289 (struct mlx5_flow_dv_modify_hdr_resource *resource,
290 const struct rte_flow_action *action,
291 struct rte_flow_error *error)
293 const struct rte_flow_action_set_ipv4 *conf =
294 (const struct rte_flow_action_set_ipv4 *)(action->conf);
295 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
296 struct rte_flow_item_ipv4 ipv4;
297 struct rte_flow_item_ipv4 ipv4_mask;
299 memset(&ipv4, 0, sizeof(ipv4));
300 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
301 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
302 ipv4.hdr.src_addr = conf->ipv4_addr;
303 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
305 ipv4.hdr.dst_addr = conf->ipv4_addr;
306 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
309 item.mask = &ipv4_mask;
310 return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
311 MLX5_MODIFICATION_TYPE_SET, error);
315 * Convert modify-header set IPv6 address action to DV specification.
317 * @param[in,out] resource
318 * Pointer to the modify-header resource.
320 * Pointer to action specification.
322 * Pointer to the error structure.
325 * 0 on success, a negative errno value otherwise and rte_errno is set.
328 flow_dv_convert_action_modify_ipv6
329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
330 const struct rte_flow_action *action,
331 struct rte_flow_error *error)
333 const struct rte_flow_action_set_ipv6 *conf =
334 (const struct rte_flow_action_set_ipv6 *)(action->conf);
335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
336 struct rte_flow_item_ipv6 ipv6;
337 struct rte_flow_item_ipv6 ipv6_mask;
339 memset(&ipv6, 0, sizeof(ipv6));
340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
341 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
342 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
343 sizeof(ipv6.hdr.src_addr));
344 memcpy(&ipv6_mask.hdr.src_addr,
345 &rte_flow_item_ipv6_mask.hdr.src_addr,
346 sizeof(ipv6.hdr.src_addr));
348 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
349 sizeof(ipv6.hdr.dst_addr));
350 memcpy(&ipv6_mask.hdr.dst_addr,
351 &rte_flow_item_ipv6_mask.hdr.dst_addr,
352 sizeof(ipv6.hdr.dst_addr));
355 item.mask = &ipv6_mask;
356 return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
357 MLX5_MODIFICATION_TYPE_SET, error);
361 * Convert modify-header set MAC address action to DV specification.
363 * @param[in,out] resource
364 * Pointer to the modify-header resource.
366 * Pointer to action specification.
368 * Pointer to the error structure.
371 * 0 on success, a negative errno value otherwise and rte_errno is set.
374 flow_dv_convert_action_modify_mac
375 (struct mlx5_flow_dv_modify_hdr_resource *resource,
376 const struct rte_flow_action *action,
377 struct rte_flow_error *error)
379 const struct rte_flow_action_set_mac *conf =
380 (const struct rte_flow_action_set_mac *)(action->conf);
381 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
382 struct rte_flow_item_eth eth;
383 struct rte_flow_item_eth eth_mask;
385 memset(ð, 0, sizeof(eth));
386 memset(ð_mask, 0, sizeof(eth_mask));
387 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
388 memcpy(ð.src.addr_bytes, &conf->mac_addr,
389 sizeof(eth.src.addr_bytes));
390 memcpy(ð_mask.src.addr_bytes,
391 &rte_flow_item_eth_mask.src.addr_bytes,
392 sizeof(eth_mask.src.addr_bytes));
394 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
395 sizeof(eth.dst.addr_bytes));
396 memcpy(ð_mask.dst.addr_bytes,
397 &rte_flow_item_eth_mask.dst.addr_bytes,
398 sizeof(eth_mask.dst.addr_bytes));
401 item.mask = ð_mask;
402 return flow_dv_convert_modify_action(&item, modify_eth, resource,
403 MLX5_MODIFICATION_TYPE_SET, error);
407 * Convert modify-header set VLAN VID action to DV specification.
409 * @param[in,out] resource
410 * Pointer to the modify-header resource.
412 * Pointer to action specification.
414 * Pointer to the error structure.
417 * 0 on success, a negative errno value otherwise and rte_errno is set.
420 flow_dv_convert_action_modify_vlan_vid
421 (struct mlx5_flow_dv_modify_hdr_resource *resource,
422 const struct rte_flow_action *action,
423 struct rte_flow_error *error)
425 const struct rte_flow_action_of_set_vlan_vid *conf =
426 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
427 int i = resource->actions_num;
428 struct mlx5_modification_cmd *actions = &resource->actions[i];
429 struct field_modify_info *field = modify_vlan_out_first_vid;
431 if (i >= MLX5_MODIFY_NUM)
432 return rte_flow_error_set(error, EINVAL,
433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434 "too many items to modify");
435 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
436 actions[i].field = field->id;
437 actions[i].length = field->size;
438 actions[i].offset = field->offset;
439 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
440 actions[i].data1 = conf->vlan_vid;
441 actions[i].data1 = actions[i].data1 << 16;
442 resource->actions_num = ++i;
447 * Convert modify-header set TP action to DV specification.
449 * @param[in,out] resource
450 * Pointer to the modify-header resource.
452 * Pointer to action specification.
454 * Pointer to rte_flow_item objects list.
456 * Pointer to flow attributes structure.
458 * Pointer to the error structure.
461 * 0 on success, a negative errno value otherwise and rte_errno is set.
464 flow_dv_convert_action_modify_tp
465 (struct mlx5_flow_dv_modify_hdr_resource *resource,
466 const struct rte_flow_action *action,
467 const struct rte_flow_item *items,
468 union flow_dv_attr *attr,
469 struct rte_flow_error *error)
471 const struct rte_flow_action_set_tp *conf =
472 (const struct rte_flow_action_set_tp *)(action->conf);
473 struct rte_flow_item item;
474 struct rte_flow_item_udp udp;
475 struct rte_flow_item_udp udp_mask;
476 struct rte_flow_item_tcp tcp;
477 struct rte_flow_item_tcp tcp_mask;
478 struct field_modify_info *field;
481 flow_dv_attr_init(items, attr);
483 memset(&udp, 0, sizeof(udp));
484 memset(&udp_mask, 0, sizeof(udp_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
486 udp.hdr.src_port = conf->port;
487 udp_mask.hdr.src_port =
488 rte_flow_item_udp_mask.hdr.src_port;
490 udp.hdr.dst_port = conf->port;
491 udp_mask.hdr.dst_port =
492 rte_flow_item_udp_mask.hdr.dst_port;
494 item.type = RTE_FLOW_ITEM_TYPE_UDP;
496 item.mask = &udp_mask;
500 memset(&tcp, 0, sizeof(tcp));
501 memset(&tcp_mask, 0, sizeof(tcp_mask));
502 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
503 tcp.hdr.src_port = conf->port;
504 tcp_mask.hdr.src_port =
505 rte_flow_item_tcp_mask.hdr.src_port;
507 tcp.hdr.dst_port = conf->port;
508 tcp_mask.hdr.dst_port =
509 rte_flow_item_tcp_mask.hdr.dst_port;
511 item.type = RTE_FLOW_ITEM_TYPE_TCP;
513 item.mask = &tcp_mask;
516 return flow_dv_convert_modify_action(&item, field, resource,
517 MLX5_MODIFICATION_TYPE_SET, error);
521 * Convert modify-header set TTL action to DV specification.
523 * @param[in,out] resource
524 * Pointer to the modify-header resource.
526 * Pointer to action specification.
528 * Pointer to rte_flow_item objects list.
530 * Pointer to flow attributes structure.
532 * Pointer to the error structure.
535 * 0 on success, a negative errno value otherwise and rte_errno is set.
538 flow_dv_convert_action_modify_ttl
539 (struct mlx5_flow_dv_modify_hdr_resource *resource,
540 const struct rte_flow_action *action,
541 const struct rte_flow_item *items,
542 union flow_dv_attr *attr,
543 struct rte_flow_error *error)
545 const struct rte_flow_action_set_ttl *conf =
546 (const struct rte_flow_action_set_ttl *)(action->conf);
547 struct rte_flow_item item;
548 struct rte_flow_item_ipv4 ipv4;
549 struct rte_flow_item_ipv4 ipv4_mask;
550 struct rte_flow_item_ipv6 ipv6;
551 struct rte_flow_item_ipv6 ipv6_mask;
552 struct field_modify_info *field;
555 flow_dv_attr_init(items, attr);
557 memset(&ipv4, 0, sizeof(ipv4));
558 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
559 ipv4.hdr.time_to_live = conf->ttl_value;
560 ipv4_mask.hdr.time_to_live = 0xFF;
561 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
563 item.mask = &ipv4_mask;
567 memset(&ipv6, 0, sizeof(ipv6));
568 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
569 ipv6.hdr.hop_limits = conf->ttl_value;
570 ipv6_mask.hdr.hop_limits = 0xFF;
571 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
573 item.mask = &ipv6_mask;
576 return flow_dv_convert_modify_action(&item, field, resource,
577 MLX5_MODIFICATION_TYPE_SET, error);
581 * Convert modify-header decrement TTL action to DV specification.
583 * @param[in,out] resource
584 * Pointer to the modify-header resource.
586 * Pointer to action specification.
588 * Pointer to rte_flow_item objects list.
590 * Pointer to flow attributes structure.
592 * Pointer to the error structure.
595 * 0 on success, a negative errno value otherwise and rte_errno is set.
598 flow_dv_convert_action_modify_dec_ttl
599 (struct mlx5_flow_dv_modify_hdr_resource *resource,
600 const struct rte_flow_item *items,
601 union flow_dv_attr *attr,
602 struct rte_flow_error *error)
604 struct rte_flow_item item;
605 struct rte_flow_item_ipv4 ipv4;
606 struct rte_flow_item_ipv4 ipv4_mask;
607 struct rte_flow_item_ipv6 ipv6;
608 struct rte_flow_item_ipv6 ipv6_mask;
609 struct field_modify_info *field;
612 flow_dv_attr_init(items, attr);
614 memset(&ipv4, 0, sizeof(ipv4));
615 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
616 ipv4.hdr.time_to_live = 0xFF;
617 ipv4_mask.hdr.time_to_live = 0xFF;
618 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
620 item.mask = &ipv4_mask;
624 memset(&ipv6, 0, sizeof(ipv6));
625 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
626 ipv6.hdr.hop_limits = 0xFF;
627 ipv6_mask.hdr.hop_limits = 0xFF;
628 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
630 item.mask = &ipv6_mask;
633 return flow_dv_convert_modify_action(&item, field, resource,
634 MLX5_MODIFICATION_TYPE_ADD, error);
638 * Convert modify-header increment/decrement TCP Sequence number
639 * to DV specification.
641 * @param[in,out] resource
642 * Pointer to the modify-header resource.
644 * Pointer to action specification.
646 * Pointer to the error structure.
649 * 0 on success, a negative errno value otherwise and rte_errno is set.
652 flow_dv_convert_action_modify_tcp_seq
653 (struct mlx5_flow_dv_modify_hdr_resource *resource,
654 const struct rte_flow_action *action,
655 struct rte_flow_error *error)
657 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
658 uint64_t value = rte_be_to_cpu_32(*conf);
659 struct rte_flow_item item;
660 struct rte_flow_item_tcp tcp;
661 struct rte_flow_item_tcp tcp_mask;
663 memset(&tcp, 0, sizeof(tcp));
664 memset(&tcp_mask, 0, sizeof(tcp_mask));
665 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
667 * The HW has no decrement operation, only increment operation.
668 * To simulate decrement X from Y using increment operation
669 * we need to add UINT32_MAX X times to Y.
670 * Each adding of UINT32_MAX decrements Y by 1.
673 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
674 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
675 item.type = RTE_FLOW_ITEM_TYPE_TCP;
677 item.mask = &tcp_mask;
678 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
679 MLX5_MODIFICATION_TYPE_ADD, error);
683 * Convert modify-header increment/decrement TCP Acknowledgment number
684 * to DV specification.
686 * @param[in,out] resource
687 * Pointer to the modify-header resource.
689 * Pointer to action specification.
691 * Pointer to the error structure.
694 * 0 on success, a negative errno value otherwise and rte_errno is set.
697 flow_dv_convert_action_modify_tcp_ack
698 (struct mlx5_flow_dv_modify_hdr_resource *resource,
699 const struct rte_flow_action *action,
700 struct rte_flow_error *error)
702 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
703 uint64_t value = rte_be_to_cpu_32(*conf);
704 struct rte_flow_item item;
705 struct rte_flow_item_tcp tcp;
706 struct rte_flow_item_tcp tcp_mask;
708 memset(&tcp, 0, sizeof(tcp));
709 memset(&tcp_mask, 0, sizeof(tcp_mask));
710 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
712 * The HW has no decrement operation, only increment operation.
713 * To simulate decrement X from Y using increment operation
714 * we need to add UINT32_MAX X times to Y.
715 * Each adding of UINT32_MAX decrements Y by 1.
718 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
719 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
720 item.type = RTE_FLOW_ITEM_TYPE_TCP;
722 item.mask = &tcp_mask;
723 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
724 MLX5_MODIFICATION_TYPE_ADD, error);
727 static enum mlx5_modification_field reg_to_field[] = {
728 [REG_A] = MLX5_MODI_META_DATA_REG_A,
729 [REG_B] = MLX5_MODI_META_DATA_REG_B,
730 [REG_C_0] = MLX5_MODI_META_REG_C_0,
731 [REG_C_1] = MLX5_MODI_META_REG_C_1,
732 [REG_C_2] = MLX5_MODI_META_REG_C_2,
733 [REG_C_3] = MLX5_MODI_META_REG_C_3,
734 [REG_C_4] = MLX5_MODI_META_REG_C_4,
735 [REG_C_5] = MLX5_MODI_META_REG_C_5,
736 [REG_C_6] = MLX5_MODI_META_REG_C_6,
737 [REG_C_7] = MLX5_MODI_META_REG_C_7,
741 * Convert register set to DV specification.
743 * @param[in,out] resource
744 * Pointer to the modify-header resource.
746 * Pointer to action specification.
748 * Pointer to the error structure.
751 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 flow_dv_convert_action_set_reg
755 (struct mlx5_flow_dv_modify_hdr_resource *resource,
756 const struct rte_flow_action *action,
757 struct rte_flow_error *error)
759 const struct mlx5_rte_flow_action_set_tag *conf = (action->conf);
760 struct mlx5_modification_cmd *actions = resource->actions;
761 uint32_t i = resource->actions_num;
763 if (i >= MLX5_MODIFY_NUM)
764 return rte_flow_error_set(error, EINVAL,
765 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
766 "too many items to modify");
767 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
768 actions[i].field = reg_to_field[conf->id];
769 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
770 actions[i].data1 = conf->data;
772 resource->actions_num = i;
773 if (!resource->actions_num)
774 return rte_flow_error_set(error, EINVAL,
775 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
776 "invalid modification flow item");
781 * Validate META item.
784 * Pointer to the rte_eth_dev structure.
786 * Item specification.
788 * Attributes of flow that includes this item.
790 * Pointer to error structure.
793 * 0 on success, a negative errno value otherwise and rte_errno is set.
796 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
797 const struct rte_flow_item *item,
798 const struct rte_flow_attr *attr,
799 struct rte_flow_error *error)
801 const struct rte_flow_item_meta *spec = item->spec;
802 const struct rte_flow_item_meta *mask = item->mask;
803 const struct rte_flow_item_meta nic_mask = {
804 .data = RTE_BE32(UINT32_MAX)
807 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
809 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
810 return rte_flow_error_set(error, EPERM,
811 RTE_FLOW_ERROR_TYPE_ITEM,
813 "match on metadata offload "
814 "configuration is off for this port");
816 return rte_flow_error_set(error, EINVAL,
817 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
819 "data cannot be empty");
821 return rte_flow_error_set(error, EINVAL,
822 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
824 "data cannot be zero");
826 mask = &rte_flow_item_meta_mask;
827 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
828 (const uint8_t *)&nic_mask,
829 sizeof(struct rte_flow_item_meta),
834 return rte_flow_error_set(error, ENOTSUP,
835 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
837 "pattern not supported for ingress");
842 * Validate vport item.
845 * Pointer to the rte_eth_dev structure.
847 * Item specification.
849 * Attributes of flow that includes this item.
850 * @param[in] item_flags
851 * Bit-fields that holds the items detected until now.
853 * Pointer to error structure.
856 * 0 on success, a negative errno value otherwise and rte_errno is set.
859 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
860 const struct rte_flow_item *item,
861 const struct rte_flow_attr *attr,
863 struct rte_flow_error *error)
865 const struct rte_flow_item_port_id *spec = item->spec;
866 const struct rte_flow_item_port_id *mask = item->mask;
867 const struct rte_flow_item_port_id switch_mask = {
870 struct mlx5_priv *esw_priv;
871 struct mlx5_priv *dev_priv;
875 return rte_flow_error_set(error, EINVAL,
876 RTE_FLOW_ERROR_TYPE_ITEM,
878 "match on port id is valid only"
879 " when transfer flag is enabled");
880 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
881 return rte_flow_error_set(error, ENOTSUP,
882 RTE_FLOW_ERROR_TYPE_ITEM, item,
883 "multiple source ports are not"
887 if (mask->id != 0xffffffff)
888 return rte_flow_error_set(error, ENOTSUP,
889 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
891 "no support for partial mask on"
893 ret = mlx5_flow_item_acceptable
894 (item, (const uint8_t *)mask,
895 (const uint8_t *)&rte_flow_item_port_id_mask,
896 sizeof(struct rte_flow_item_port_id),
902 esw_priv = mlx5_port_to_eswitch_info(spec->id);
904 return rte_flow_error_set(error, rte_errno,
905 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
906 "failed to obtain E-Switch info for"
908 dev_priv = mlx5_dev_to_eswitch_info(dev);
910 return rte_flow_error_set(error, rte_errno,
911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
913 "failed to obtain E-Switch info");
914 if (esw_priv->domain_id != dev_priv->domain_id)
915 return rte_flow_error_set(error, EINVAL,
916 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
917 "cannot match on a port from a"
918 " different E-Switch");
923 * Validate the pop VLAN action.
926 * Pointer to the rte_eth_dev structure.
927 * @param[in] action_flags
928 * Holds the actions detected until now.
930 * Pointer to the pop vlan action.
931 * @param[in] item_flags
932 * The items found in this flow rule.
934 * Pointer to flow attributes.
936 * Pointer to error structure.
939 * 0 on success, a negative errno value otherwise and rte_errno is set.
942 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
943 uint64_t action_flags,
944 const struct rte_flow_action *action,
946 const struct rte_flow_attr *attr,
947 struct rte_flow_error *error)
949 struct mlx5_priv *priv = dev->data->dev_private;
953 if (!priv->sh->pop_vlan_action)
954 return rte_flow_error_set(error, ENOTSUP,
955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
957 "pop vlan action is not supported");
959 * Check for inconsistencies:
960 * fail strip_vlan in a flow that matches packets without VLAN tags.
961 * fail strip_vlan in a flow that matches packets without explicitly a
962 * matching on VLAN tag ?
964 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
965 return rte_flow_error_set(error, ENOTSUP,
966 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
968 "no support for multiple vlan pop "
970 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
971 return rte_flow_error_set(error, ENOTSUP,
972 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
974 "cannot pop vlan without a "
975 "match on (outer) vlan in the flow");
980 * Get VLAN default info from vlan match info.
983 * Pointer to the rte_eth_dev structure.
985 * the list of item specifications.
987 * pointer VLAN info to fill to.
989 * Pointer to error structure.
992 * 0 on success, a negative errno value otherwise and rte_errno is set.
995 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
996 struct rte_vlan_hdr *vlan)
998 const struct rte_flow_item_vlan nic_mask = {
999 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1000 MLX5DV_FLOW_VLAN_VID_MASK),
1001 .inner_type = RTE_BE16(0xffff),
1006 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1007 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1009 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1010 const struct rte_flow_item_vlan *vlan_m = items->mask;
1011 const struct rte_flow_item_vlan *vlan_v = items->spec;
1015 /* Only full match values are accepted */
1016 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1017 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1018 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1020 rte_be_to_cpu_16(vlan_v->tci &
1021 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1023 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1024 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1025 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1027 rte_be_to_cpu_16(vlan_v->tci &
1028 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1030 if (vlan_m->inner_type == nic_mask.inner_type)
1031 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1032 vlan_m->inner_type);
1037 * Validate the push VLAN action.
1039 * @param[in] action_flags
1040 * Holds the actions detected until now.
1042 * Pointer to the encap action.
1044 * Pointer to flow attributes
1046 * Pointer to error structure.
1049 * 0 on success, a negative errno value otherwise and rte_errno is set.
1052 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1053 const struct rte_flow_action *action,
1054 const struct rte_flow_attr *attr,
1055 struct rte_flow_error *error)
1057 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1059 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1060 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1061 return rte_flow_error_set(error, EINVAL,
1062 RTE_FLOW_ERROR_TYPE_ACTION, action,
1063 "invalid vlan ethertype");
1065 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1066 return rte_flow_error_set(error, ENOTSUP,
1067 RTE_FLOW_ERROR_TYPE_ACTION, action,
1068 "no support for multiple VLAN "
1075 * Validate the set VLAN PCP.
1077 * @param[in] action_flags
1078 * Holds the actions detected until now.
1079 * @param[in] actions
1080 * Pointer to the list of actions remaining in the flow rule.
1082 * Pointer to flow attributes
1084 * Pointer to error structure.
1087 * 0 on success, a negative errno value otherwise and rte_errno is set.
1090 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1091 const struct rte_flow_action actions[],
1092 struct rte_flow_error *error)
1094 const struct rte_flow_action *action = actions;
1095 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1097 if (conf->vlan_pcp > 7)
1098 return rte_flow_error_set(error, EINVAL,
1099 RTE_FLOW_ERROR_TYPE_ACTION, action,
1100 "VLAN PCP value is too big");
1101 if (mlx5_flow_find_action(actions,
1102 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) == NULL)
1103 return rte_flow_error_set(error, ENOTSUP,
1104 RTE_FLOW_ERROR_TYPE_ACTION, action,
1105 "set VLAN PCP can only be used "
1106 "with push VLAN action");
1107 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
1108 return rte_flow_error_set(error, ENOTSUP,
1109 RTE_FLOW_ERROR_TYPE_ACTION, action,
1110 "set VLAN PCP action must precede "
1111 "the push VLAN action");
1116 * Validate the set VLAN VID.
1118 * @param[in] item_flags
1119 * Holds the items detected in this rule.
1120 * @param[in] actions
1121 * Pointer to the list of actions remaining in the flow rule.
1123 * Pointer to flow attributes
1125 * Pointer to error structure.
1128 * 0 on success, a negative errno value otherwise and rte_errno is set.
1131 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1132 const struct rte_flow_action actions[],
1133 struct rte_flow_error *error)
1135 const struct rte_flow_action *action = actions;
1136 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1138 if (conf->vlan_vid > RTE_BE16(0xFFE))
1139 return rte_flow_error_set(error, EINVAL,
1140 RTE_FLOW_ERROR_TYPE_ACTION, action,
1141 "VLAN VID value is too big");
1142 /* If a push VLAN action follows then it will handle this action */
1143 if (mlx5_flow_find_action(actions,
1144 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
1148 * Action is on an existing VLAN header:
1149 * Need to verify this is a single modify CID action.
1150 * Rule mast include a match on outer VLAN.
1152 if (mlx5_flow_find_action(++action,
1153 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1154 return rte_flow_error_set(error, ENOTSUP,
1155 RTE_FLOW_ERROR_TYPE_ACTION, action,
1156 "Multiple VLAN VID modifications are "
1158 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1159 return rte_flow_error_set(error, EINVAL,
1160 RTE_FLOW_ERROR_TYPE_ACTION, action,
1161 "match on VLAN is required in order "
1167 * Validate count action.
1172 * Pointer to error structure.
1175 * 0 on success, a negative errno value otherwise and rte_errno is set.
1178 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1179 struct rte_flow_error *error)
1181 struct mlx5_priv *priv = dev->data->dev_private;
1183 if (!priv->config.devx)
1185 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1189 return rte_flow_error_set
1191 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1193 "count action not supported");
1197 * Validate the L2 encap action.
1199 * @param[in] action_flags
1200 * Holds the actions detected until now.
1202 * Pointer to the encap action.
1204 * Pointer to flow attributes
1206 * Pointer to error structure.
1209 * 0 on success, a negative errno value otherwise and rte_errno is set.
1212 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1213 const struct rte_flow_action *action,
1214 const struct rte_flow_attr *attr,
1215 struct rte_flow_error *error)
1217 if (!(action->conf))
1218 return rte_flow_error_set(error, EINVAL,
1219 RTE_FLOW_ERROR_TYPE_ACTION, action,
1220 "configuration cannot be null");
1221 if (action_flags & MLX5_FLOW_ACTION_DROP)
1222 return rte_flow_error_set(error, EINVAL,
1223 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1224 "can't drop and encap in same flow");
1225 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1226 return rte_flow_error_set(error, EINVAL,
1227 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1228 "can only have a single encap or"
1229 " decap action in a flow");
1230 if (!attr->transfer && attr->ingress)
1231 return rte_flow_error_set(error, ENOTSUP,
1232 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1234 "encap action not supported for "
1240 * Validate the L2 decap action.
1242 * @param[in] action_flags
1243 * Holds the actions detected until now.
1245 * Pointer to flow attributes
1247 * Pointer to error structure.
1250 * 0 on success, a negative errno value otherwise and rte_errno is set.
1253 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1254 const struct rte_flow_attr *attr,
1255 struct rte_flow_error *error)
1257 if (action_flags & MLX5_FLOW_ACTION_DROP)
1258 return rte_flow_error_set(error, EINVAL,
1259 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1260 "can't drop and decap in same flow");
1261 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1262 return rte_flow_error_set(error, EINVAL,
1263 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1264 "can only have a single encap or"
1265 " decap action in a flow");
1266 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1267 return rte_flow_error_set(error, EINVAL,
1268 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1269 "can't have decap action after"
1272 return rte_flow_error_set(error, ENOTSUP,
1273 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1275 "decap action not supported for "
1281 * Validate the raw encap action.
1283 * @param[in] action_flags
1284 * Holds the actions detected until now.
1286 * Pointer to the encap action.
1288 * Pointer to flow attributes
1290 * Pointer to error structure.
1293 * 0 on success, a negative errno value otherwise and rte_errno is set.
1296 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1297 const struct rte_flow_action *action,
1298 const struct rte_flow_attr *attr,
1299 struct rte_flow_error *error)
1301 const struct rte_flow_action_raw_encap *raw_encap =
1302 (const struct rte_flow_action_raw_encap *)action->conf;
1303 if (!(action->conf))
1304 return rte_flow_error_set(error, EINVAL,
1305 RTE_FLOW_ERROR_TYPE_ACTION, action,
1306 "configuration cannot be null");
1307 if (action_flags & MLX5_FLOW_ACTION_DROP)
1308 return rte_flow_error_set(error, EINVAL,
1309 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1310 "can't drop and encap in same flow");
1311 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1312 return rte_flow_error_set(error, EINVAL,
1313 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1314 "can only have a single encap"
1315 " action in a flow");
1316 /* encap without preceding decap is not supported for ingress */
1317 if (!attr->transfer && attr->ingress &&
1318 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1319 return rte_flow_error_set(error, ENOTSUP,
1320 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1322 "encap action not supported for "
1324 if (!raw_encap->size || !raw_encap->data)
1325 return rte_flow_error_set(error, EINVAL,
1326 RTE_FLOW_ERROR_TYPE_ACTION, action,
1327 "raw encap data cannot be empty");
1332 * Validate the raw decap action.
1334 * @param[in] action_flags
1335 * Holds the actions detected until now.
1337 * Pointer to the encap action.
1339 * Pointer to flow attributes
1341 * Pointer to error structure.
1344 * 0 on success, a negative errno value otherwise and rte_errno is set.
1347 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1348 const struct rte_flow_action *action,
1349 const struct rte_flow_attr *attr,
1350 struct rte_flow_error *error)
1352 if (action_flags & MLX5_FLOW_ACTION_DROP)
1353 return rte_flow_error_set(error, EINVAL,
1354 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1355 "can't drop and decap in same flow");
1356 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1357 return rte_flow_error_set(error, EINVAL,
1358 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1359 "can't have encap action before"
1361 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1362 return rte_flow_error_set(error, EINVAL,
1363 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1364 "can only have a single decap"
1365 " action in a flow");
1366 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1367 return rte_flow_error_set(error, EINVAL,
1368 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1369 "can't have decap action after"
1371 /* decap action is valid on egress only if it is followed by encap */
1373 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1374 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1377 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1378 return rte_flow_error_set
1380 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1381 NULL, "decap action not supported"
1388 * Find existing encap/decap resource or create and register a new one.
1390 * @param dev[in, out]
1391 * Pointer to rte_eth_dev structure.
1392 * @param[in, out] resource
1393 * Pointer to encap/decap resource.
1394 * @parm[in, out] dev_flow
1395 * Pointer to the dev_flow.
1397 * pointer to error structure.
1400 * 0 on success otherwise -errno and errno is set.
1403 flow_dv_encap_decap_resource_register
1404 (struct rte_eth_dev *dev,
1405 struct mlx5_flow_dv_encap_decap_resource *resource,
1406 struct mlx5_flow *dev_flow,
1407 struct rte_flow_error *error)
1409 struct mlx5_priv *priv = dev->data->dev_private;
1410 struct mlx5_ibv_shared *sh = priv->sh;
1411 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1412 struct rte_flow *flow = dev_flow->flow;
1413 struct mlx5dv_dr_domain *domain;
1415 resource->flags = flow->group ? 0 : 1;
1416 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1417 domain = sh->fdb_domain;
1418 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1419 domain = sh->rx_domain;
1421 domain = sh->tx_domain;
1423 /* Lookup a matching resource from cache. */
1424 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1425 if (resource->reformat_type == cache_resource->reformat_type &&
1426 resource->ft_type == cache_resource->ft_type &&
1427 resource->flags == cache_resource->flags &&
1428 resource->size == cache_resource->size &&
1429 !memcmp((const void *)resource->buf,
1430 (const void *)cache_resource->buf,
1432 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1433 (void *)cache_resource,
1434 rte_atomic32_read(&cache_resource->refcnt));
1435 rte_atomic32_inc(&cache_resource->refcnt);
1436 dev_flow->dv.encap_decap = cache_resource;
1440 /* Register new encap/decap resource. */
1441 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1442 if (!cache_resource)
1443 return rte_flow_error_set(error, ENOMEM,
1444 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1445 "cannot allocate resource memory");
1446 *cache_resource = *resource;
1447 cache_resource->verbs_action =
1448 mlx5_glue->dv_create_flow_action_packet_reformat
1449 (sh->ctx, cache_resource->reformat_type,
1450 cache_resource->ft_type, domain, cache_resource->flags,
1451 cache_resource->size,
1452 (cache_resource->size ? cache_resource->buf : NULL));
1453 if (!cache_resource->verbs_action) {
1454 rte_free(cache_resource);
1455 return rte_flow_error_set(error, ENOMEM,
1456 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1457 NULL, "cannot create action");
1459 rte_atomic32_init(&cache_resource->refcnt);
1460 rte_atomic32_inc(&cache_resource->refcnt);
1461 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1462 dev_flow->dv.encap_decap = cache_resource;
1463 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1464 (void *)cache_resource,
1465 rte_atomic32_read(&cache_resource->refcnt));
1470 * Find existing table jump resource or create and register a new one.
1472 * @param dev[in, out]
1473 * Pointer to rte_eth_dev structure.
1474 * @param[in, out] resource
1475 * Pointer to jump table resource.
1476 * @parm[in, out] dev_flow
1477 * Pointer to the dev_flow.
1479 * pointer to error structure.
1482 * 0 on success otherwise -errno and errno is set.
1485 flow_dv_jump_tbl_resource_register
1486 (struct rte_eth_dev *dev,
1487 struct mlx5_flow_dv_jump_tbl_resource *resource,
1488 struct mlx5_flow *dev_flow,
1489 struct rte_flow_error *error)
1491 struct mlx5_priv *priv = dev->data->dev_private;
1492 struct mlx5_ibv_shared *sh = priv->sh;
1493 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1495 /* Lookup a matching resource from cache. */
1496 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1497 if (resource->tbl == cache_resource->tbl) {
1498 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1499 (void *)cache_resource,
1500 rte_atomic32_read(&cache_resource->refcnt));
1501 rte_atomic32_inc(&cache_resource->refcnt);
1502 dev_flow->dv.jump = cache_resource;
1506 /* Register new jump table resource. */
1507 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1508 if (!cache_resource)
1509 return rte_flow_error_set(error, ENOMEM,
1510 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1511 "cannot allocate resource memory");
1512 *cache_resource = *resource;
1513 cache_resource->action =
1514 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1515 (resource->tbl->obj);
1516 if (!cache_resource->action) {
1517 rte_free(cache_resource);
1518 return rte_flow_error_set(error, ENOMEM,
1519 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1520 NULL, "cannot create action");
1522 rte_atomic32_init(&cache_resource->refcnt);
1523 rte_atomic32_inc(&cache_resource->refcnt);
1524 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1525 dev_flow->dv.jump = cache_resource;
1526 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1527 (void *)cache_resource,
1528 rte_atomic32_read(&cache_resource->refcnt));
1533 * Find existing table port ID resource or create and register a new one.
1535 * @param dev[in, out]
1536 * Pointer to rte_eth_dev structure.
1537 * @param[in, out] resource
1538 * Pointer to port ID action resource.
1539 * @parm[in, out] dev_flow
1540 * Pointer to the dev_flow.
1542 * pointer to error structure.
1545 * 0 on success otherwise -errno and errno is set.
1548 flow_dv_port_id_action_resource_register
1549 (struct rte_eth_dev *dev,
1550 struct mlx5_flow_dv_port_id_action_resource *resource,
1551 struct mlx5_flow *dev_flow,
1552 struct rte_flow_error *error)
1554 struct mlx5_priv *priv = dev->data->dev_private;
1555 struct mlx5_ibv_shared *sh = priv->sh;
1556 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1558 /* Lookup a matching resource from cache. */
1559 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1560 if (resource->port_id == cache_resource->port_id) {
1561 DRV_LOG(DEBUG, "port id action resource resource %p: "
1563 (void *)cache_resource,
1564 rte_atomic32_read(&cache_resource->refcnt));
1565 rte_atomic32_inc(&cache_resource->refcnt);
1566 dev_flow->dv.port_id_action = cache_resource;
1570 /* Register new port id action resource. */
1571 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1572 if (!cache_resource)
1573 return rte_flow_error_set(error, ENOMEM,
1574 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1575 "cannot allocate resource memory");
1576 *cache_resource = *resource;
1577 cache_resource->action =
1578 mlx5_glue->dr_create_flow_action_dest_vport
1579 (priv->sh->fdb_domain, resource->port_id);
1580 if (!cache_resource->action) {
1581 rte_free(cache_resource);
1582 return rte_flow_error_set(error, ENOMEM,
1583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1584 NULL, "cannot create action");
1586 rte_atomic32_init(&cache_resource->refcnt);
1587 rte_atomic32_inc(&cache_resource->refcnt);
1588 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1589 dev_flow->dv.port_id_action = cache_resource;
1590 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1591 (void *)cache_resource,
1592 rte_atomic32_read(&cache_resource->refcnt));
1597 * Find existing push vlan resource or create and register a new one.
1599 * @param dev[in, out]
1600 * Pointer to rte_eth_dev structure.
1601 * @param[in, out] resource
1602 * Pointer to port ID action resource.
1603 * @parm[in, out] dev_flow
1604 * Pointer to the dev_flow.
1606 * pointer to error structure.
1609 * 0 on success otherwise -errno and errno is set.
1612 flow_dv_push_vlan_action_resource_register
1613 (struct rte_eth_dev *dev,
1614 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1615 struct mlx5_flow *dev_flow,
1616 struct rte_flow_error *error)
1618 struct mlx5_priv *priv = dev->data->dev_private;
1619 struct mlx5_ibv_shared *sh = priv->sh;
1620 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1621 struct mlx5dv_dr_domain *domain;
1623 /* Lookup a matching resource from cache. */
1624 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1625 if (resource->vlan_tag == cache_resource->vlan_tag &&
1626 resource->ft_type == cache_resource->ft_type) {
1627 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1629 (void *)cache_resource,
1630 rte_atomic32_read(&cache_resource->refcnt));
1631 rte_atomic32_inc(&cache_resource->refcnt);
1632 dev_flow->dv.push_vlan_res = cache_resource;
1636 /* Register new push_vlan action resource. */
1637 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1638 if (!cache_resource)
1639 return rte_flow_error_set(error, ENOMEM,
1640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1641 "cannot allocate resource memory");
1642 *cache_resource = *resource;
1643 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1644 domain = sh->fdb_domain;
1645 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1646 domain = sh->rx_domain;
1648 domain = sh->tx_domain;
1649 cache_resource->action =
1650 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1651 resource->vlan_tag);
1652 if (!cache_resource->action) {
1653 rte_free(cache_resource);
1654 return rte_flow_error_set(error, ENOMEM,
1655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1656 NULL, "cannot create action");
1658 rte_atomic32_init(&cache_resource->refcnt);
1659 rte_atomic32_inc(&cache_resource->refcnt);
1660 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1661 dev_flow->dv.push_vlan_res = cache_resource;
1662 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1663 (void *)cache_resource,
1664 rte_atomic32_read(&cache_resource->refcnt));
1668 * Get the size of specific rte_flow_item_type
1670 * @param[in] item_type
1671 * Tested rte_flow_item_type.
1674 * sizeof struct item_type, 0 if void or irrelevant.
1677 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1681 switch (item_type) {
1682 case RTE_FLOW_ITEM_TYPE_ETH:
1683 retval = sizeof(struct rte_flow_item_eth);
1685 case RTE_FLOW_ITEM_TYPE_VLAN:
1686 retval = sizeof(struct rte_flow_item_vlan);
1688 case RTE_FLOW_ITEM_TYPE_IPV4:
1689 retval = sizeof(struct rte_flow_item_ipv4);
1691 case RTE_FLOW_ITEM_TYPE_IPV6:
1692 retval = sizeof(struct rte_flow_item_ipv6);
1694 case RTE_FLOW_ITEM_TYPE_UDP:
1695 retval = sizeof(struct rte_flow_item_udp);
1697 case RTE_FLOW_ITEM_TYPE_TCP:
1698 retval = sizeof(struct rte_flow_item_tcp);
1700 case RTE_FLOW_ITEM_TYPE_VXLAN:
1701 retval = sizeof(struct rte_flow_item_vxlan);
1703 case RTE_FLOW_ITEM_TYPE_GRE:
1704 retval = sizeof(struct rte_flow_item_gre);
1706 case RTE_FLOW_ITEM_TYPE_NVGRE:
1707 retval = sizeof(struct rte_flow_item_nvgre);
1709 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1710 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1712 case RTE_FLOW_ITEM_TYPE_MPLS:
1713 retval = sizeof(struct rte_flow_item_mpls);
1715 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1723 #define MLX5_ENCAP_IPV4_VERSION 0x40
1724 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1725 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1726 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1727 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1728 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1729 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1732 * Convert the encap action data from list of rte_flow_item to raw buffer
1735 * Pointer to rte_flow_item objects list.
1737 * Pointer to the output buffer.
1739 * Pointer to the output buffer size.
1741 * Pointer to the error structure.
1744 * 0 on success, a negative errno value otherwise and rte_errno is set.
1747 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1748 size_t *size, struct rte_flow_error *error)
1750 struct rte_ether_hdr *eth = NULL;
1751 struct rte_vlan_hdr *vlan = NULL;
1752 struct rte_ipv4_hdr *ipv4 = NULL;
1753 struct rte_ipv6_hdr *ipv6 = NULL;
1754 struct rte_udp_hdr *udp = NULL;
1755 struct rte_vxlan_hdr *vxlan = NULL;
1756 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1757 struct rte_gre_hdr *gre = NULL;
1759 size_t temp_size = 0;
1762 return rte_flow_error_set(error, EINVAL,
1763 RTE_FLOW_ERROR_TYPE_ACTION,
1764 NULL, "invalid empty data");
1765 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1766 len = flow_dv_get_item_len(items->type);
1767 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1768 return rte_flow_error_set(error, EINVAL,
1769 RTE_FLOW_ERROR_TYPE_ACTION,
1770 (void *)items->type,
1771 "items total size is too big"
1772 " for encap action");
1773 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1774 switch (items->type) {
1775 case RTE_FLOW_ITEM_TYPE_ETH:
1776 eth = (struct rte_ether_hdr *)&buf[temp_size];
1778 case RTE_FLOW_ITEM_TYPE_VLAN:
1779 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1781 return rte_flow_error_set(error, EINVAL,
1782 RTE_FLOW_ERROR_TYPE_ACTION,
1783 (void *)items->type,
1784 "eth header not found");
1785 if (!eth->ether_type)
1786 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1788 case RTE_FLOW_ITEM_TYPE_IPV4:
1789 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1791 return rte_flow_error_set(error, EINVAL,
1792 RTE_FLOW_ERROR_TYPE_ACTION,
1793 (void *)items->type,
1794 "neither eth nor vlan"
1796 if (vlan && !vlan->eth_proto)
1797 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1798 else if (eth && !eth->ether_type)
1799 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1800 if (!ipv4->version_ihl)
1801 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1802 MLX5_ENCAP_IPV4_IHL_MIN;
1803 if (!ipv4->time_to_live)
1804 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1806 case RTE_FLOW_ITEM_TYPE_IPV6:
1807 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1809 return rte_flow_error_set(error, EINVAL,
1810 RTE_FLOW_ERROR_TYPE_ACTION,
1811 (void *)items->type,
1812 "neither eth nor vlan"
1814 if (vlan && !vlan->eth_proto)
1815 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1816 else if (eth && !eth->ether_type)
1817 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1818 if (!ipv6->vtc_flow)
1820 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1821 if (!ipv6->hop_limits)
1822 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1824 case RTE_FLOW_ITEM_TYPE_UDP:
1825 udp = (struct rte_udp_hdr *)&buf[temp_size];
1827 return rte_flow_error_set(error, EINVAL,
1828 RTE_FLOW_ERROR_TYPE_ACTION,
1829 (void *)items->type,
1830 "ip header not found");
1831 if (ipv4 && !ipv4->next_proto_id)
1832 ipv4->next_proto_id = IPPROTO_UDP;
1833 else if (ipv6 && !ipv6->proto)
1834 ipv6->proto = IPPROTO_UDP;
1836 case RTE_FLOW_ITEM_TYPE_VXLAN:
1837 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1839 return rte_flow_error_set(error, EINVAL,
1840 RTE_FLOW_ERROR_TYPE_ACTION,
1841 (void *)items->type,
1842 "udp header not found");
1844 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1845 if (!vxlan->vx_flags)
1847 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1849 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1850 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION,
1854 (void *)items->type,
1855 "udp header not found");
1856 if (!vxlan_gpe->proto)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION,
1859 (void *)items->type,
1860 "next protocol not found");
1863 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1864 if (!vxlan_gpe->vx_flags)
1865 vxlan_gpe->vx_flags =
1866 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1868 case RTE_FLOW_ITEM_TYPE_GRE:
1869 case RTE_FLOW_ITEM_TYPE_NVGRE:
1870 gre = (struct rte_gre_hdr *)&buf[temp_size];
1872 return rte_flow_error_set(error, EINVAL,
1873 RTE_FLOW_ERROR_TYPE_ACTION,
1874 (void *)items->type,
1875 "next protocol not found");
1877 return rte_flow_error_set(error, EINVAL,
1878 RTE_FLOW_ERROR_TYPE_ACTION,
1879 (void *)items->type,
1880 "ip header not found");
1881 if (ipv4 && !ipv4->next_proto_id)
1882 ipv4->next_proto_id = IPPROTO_GRE;
1883 else if (ipv6 && !ipv6->proto)
1884 ipv6->proto = IPPROTO_GRE;
1886 case RTE_FLOW_ITEM_TYPE_VOID:
1889 return rte_flow_error_set(error, EINVAL,
1890 RTE_FLOW_ERROR_TYPE_ACTION,
1891 (void *)items->type,
1892 "unsupported item type");
1902 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1904 struct rte_ether_hdr *eth = NULL;
1905 struct rte_vlan_hdr *vlan = NULL;
1906 struct rte_ipv6_hdr *ipv6 = NULL;
1907 struct rte_udp_hdr *udp = NULL;
1911 eth = (struct rte_ether_hdr *)data;
1912 next_hdr = (char *)(eth + 1);
1913 proto = RTE_BE16(eth->ether_type);
1916 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1917 vlan = (struct rte_vlan_hdr *)next_hdr;
1918 proto = RTE_BE16(vlan->eth_proto);
1919 next_hdr += sizeof(struct rte_vlan_hdr);
1922 /* HW calculates IPv4 csum. no need to proceed */
1923 if (proto == RTE_ETHER_TYPE_IPV4)
1926 /* non IPv4/IPv6 header. not supported */
1927 if (proto != RTE_ETHER_TYPE_IPV6) {
1928 return rte_flow_error_set(error, ENOTSUP,
1929 RTE_FLOW_ERROR_TYPE_ACTION,
1930 NULL, "Cannot offload non IPv4/IPv6");
1933 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1935 /* ignore non UDP */
1936 if (ipv6->proto != IPPROTO_UDP)
1939 udp = (struct rte_udp_hdr *)(ipv6 + 1);
1940 udp->dgram_cksum = 0;
1946 * Convert L2 encap action to DV specification.
1949 * Pointer to rte_eth_dev structure.
1951 * Pointer to action structure.
1952 * @param[in, out] dev_flow
1953 * Pointer to the mlx5_flow.
1954 * @param[in] transfer
1955 * Mark if the flow is E-Switch flow.
1957 * Pointer to the error structure.
1960 * 0 on success, a negative errno value otherwise and rte_errno is set.
1963 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
1964 const struct rte_flow_action *action,
1965 struct mlx5_flow *dev_flow,
1967 struct rte_flow_error *error)
1969 const struct rte_flow_item *encap_data;
1970 const struct rte_flow_action_raw_encap *raw_encap_data;
1971 struct mlx5_flow_dv_encap_decap_resource res = {
1973 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
1974 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1975 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
1978 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1980 (const struct rte_flow_action_raw_encap *)action->conf;
1981 res.size = raw_encap_data->size;
1982 memcpy(res.buf, raw_encap_data->data, res.size);
1983 if (flow_dv_zero_encap_udp_csum(res.buf, error))
1986 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
1988 ((const struct rte_flow_action_vxlan_encap *)
1989 action->conf)->definition;
1992 ((const struct rte_flow_action_nvgre_encap *)
1993 action->conf)->definition;
1994 if (flow_dv_convert_encap_data(encap_data, res.buf,
1998 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1999 return rte_flow_error_set(error, EINVAL,
2000 RTE_FLOW_ERROR_TYPE_ACTION,
2001 NULL, "can't create L2 encap action");
2006 * Convert L2 decap action to DV specification.
2009 * Pointer to rte_eth_dev structure.
2010 * @param[in, out] dev_flow
2011 * Pointer to the mlx5_flow.
2012 * @param[in] transfer
2013 * Mark if the flow is E-Switch flow.
2015 * Pointer to the error structure.
2018 * 0 on success, a negative errno value otherwise and rte_errno is set.
2021 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2022 struct mlx5_flow *dev_flow,
2024 struct rte_flow_error *error)
2026 struct mlx5_flow_dv_encap_decap_resource res = {
2029 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2030 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2031 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2034 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2035 return rte_flow_error_set(error, EINVAL,
2036 RTE_FLOW_ERROR_TYPE_ACTION,
2037 NULL, "can't create L2 decap action");
2042 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2045 * Pointer to rte_eth_dev structure.
2047 * Pointer to action structure.
2048 * @param[in, out] dev_flow
2049 * Pointer to the mlx5_flow.
2051 * Pointer to the flow attributes.
2053 * Pointer to the error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2060 const struct rte_flow_action *action,
2061 struct mlx5_flow *dev_flow,
2062 const struct rte_flow_attr *attr,
2063 struct rte_flow_error *error)
2065 const struct rte_flow_action_raw_encap *encap_data;
2066 struct mlx5_flow_dv_encap_decap_resource res;
2068 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2069 res.size = encap_data->size;
2070 memcpy(res.buf, encap_data->data, res.size);
2071 res.reformat_type = attr->egress ?
2072 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2073 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2075 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2077 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2078 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2079 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2080 return rte_flow_error_set(error, EINVAL,
2081 RTE_FLOW_ERROR_TYPE_ACTION,
2082 NULL, "can't create encap action");
2087 * Create action push VLAN.
2090 * Pointer to rte_eth_dev structure.
2091 * @param[in] vlan_tag
2092 * the vlan tag to push to the Ethernet header.
2093 * @param[in, out] dev_flow
2094 * Pointer to the mlx5_flow.
2096 * Pointer to the flow attributes.
2098 * Pointer to the error structure.
2101 * 0 on success, a negative errno value otherwise and rte_errno is set.
2104 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2105 const struct rte_flow_attr *attr,
2106 const struct rte_vlan_hdr *vlan,
2107 struct mlx5_flow *dev_flow,
2108 struct rte_flow_error *error)
2110 struct mlx5_flow_dv_push_vlan_action_resource res;
2113 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2116 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2118 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2119 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2120 return flow_dv_push_vlan_action_resource_register
2121 (dev, &res, dev_flow, error);
2125 * Validate the modify-header actions.
2127 * @param[in] action_flags
2128 * Holds the actions detected until now.
2130 * Pointer to the modify action.
2132 * Pointer to error structure.
2135 * 0 on success, a negative errno value otherwise and rte_errno is set.
2138 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2139 const struct rte_flow_action *action,
2140 struct rte_flow_error *error)
2142 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2143 return rte_flow_error_set(error, EINVAL,
2144 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2145 NULL, "action configuration not set");
2146 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2147 return rte_flow_error_set(error, EINVAL,
2148 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2149 "can't have encap action before"
2155 * Validate the modify-header MAC address actions.
2157 * @param[in] action_flags
2158 * Holds the actions detected until now.
2160 * Pointer to the modify action.
2161 * @param[in] item_flags
2162 * Holds the items detected.
2164 * Pointer to error structure.
2167 * 0 on success, a negative errno value otherwise and rte_errno is set.
2170 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2171 const struct rte_flow_action *action,
2172 const uint64_t item_flags,
2173 struct rte_flow_error *error)
2177 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2179 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2180 return rte_flow_error_set(error, EINVAL,
2181 RTE_FLOW_ERROR_TYPE_ACTION,
2183 "no L2 item in pattern");
2189 * Validate the modify-header IPv4 address actions.
2191 * @param[in] action_flags
2192 * Holds the actions detected until now.
2194 * Pointer to the modify action.
2195 * @param[in] item_flags
2196 * Holds the items detected.
2198 * Pointer to error structure.
2201 * 0 on success, a negative errno value otherwise and rte_errno is set.
2204 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2205 const struct rte_flow_action *action,
2206 const uint64_t item_flags,
2207 struct rte_flow_error *error)
2211 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2213 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2214 return rte_flow_error_set(error, EINVAL,
2215 RTE_FLOW_ERROR_TYPE_ACTION,
2217 "no ipv4 item in pattern");
2223 * Validate the modify-header IPv6 address actions.
2225 * @param[in] action_flags
2226 * Holds the actions detected until now.
2228 * Pointer to the modify action.
2229 * @param[in] item_flags
2230 * Holds the items detected.
2232 * Pointer to error structure.
2235 * 0 on success, a negative errno value otherwise and rte_errno is set.
2238 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2239 const struct rte_flow_action *action,
2240 const uint64_t item_flags,
2241 struct rte_flow_error *error)
2245 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2247 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2248 return rte_flow_error_set(error, EINVAL,
2249 RTE_FLOW_ERROR_TYPE_ACTION,
2251 "no ipv6 item in pattern");
2257 * Validate the modify-header TP actions.
2259 * @param[in] action_flags
2260 * Holds the actions detected until now.
2262 * Pointer to the modify action.
2263 * @param[in] item_flags
2264 * Holds the items detected.
2266 * Pointer to error structure.
2269 * 0 on success, a negative errno value otherwise and rte_errno is set.
2272 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2273 const struct rte_flow_action *action,
2274 const uint64_t item_flags,
2275 struct rte_flow_error *error)
2279 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2281 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ACTION,
2284 NULL, "no transport layer "
2291 * Validate the modify-header actions of increment/decrement
2292 * TCP Sequence-number.
2294 * @param[in] action_flags
2295 * Holds the actions detected until now.
2297 * Pointer to the modify action.
2298 * @param[in] item_flags
2299 * Holds the items detected.
2301 * Pointer to error structure.
2304 * 0 on success, a negative errno value otherwise and rte_errno is set.
2307 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2308 const struct rte_flow_action *action,
2309 const uint64_t item_flags,
2310 struct rte_flow_error *error)
2314 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2316 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2317 return rte_flow_error_set(error, EINVAL,
2318 RTE_FLOW_ERROR_TYPE_ACTION,
2319 NULL, "no TCP item in"
2321 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2322 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2323 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2324 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2325 return rte_flow_error_set(error, EINVAL,
2326 RTE_FLOW_ERROR_TYPE_ACTION,
2328 "cannot decrease and increase"
2329 " TCP sequence number"
2330 " at the same time");
2336 * Validate the modify-header actions of increment/decrement
2337 * TCP Acknowledgment number.
2339 * @param[in] action_flags
2340 * Holds the actions detected until now.
2342 * Pointer to the modify action.
2343 * @param[in] item_flags
2344 * Holds the items detected.
2346 * Pointer to error structure.
2349 * 0 on success, a negative errno value otherwise and rte_errno is set.
2352 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2353 const struct rte_flow_action *action,
2354 const uint64_t item_flags,
2355 struct rte_flow_error *error)
2359 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2361 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2362 return rte_flow_error_set(error, EINVAL,
2363 RTE_FLOW_ERROR_TYPE_ACTION,
2364 NULL, "no TCP item in"
2366 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2367 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2368 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2369 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2370 return rte_flow_error_set(error, EINVAL,
2371 RTE_FLOW_ERROR_TYPE_ACTION,
2373 "cannot decrease and increase"
2374 " TCP acknowledgment number"
2375 " at the same time");
2381 * Validate the modify-header TTL actions.
2383 * @param[in] action_flags
2384 * Holds the actions detected until now.
2386 * Pointer to the modify action.
2387 * @param[in] item_flags
2388 * Holds the items detected.
2390 * Pointer to error structure.
2393 * 0 on success, a negative errno value otherwise and rte_errno is set.
2396 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2397 const struct rte_flow_action *action,
2398 const uint64_t item_flags,
2399 struct rte_flow_error *error)
2403 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2405 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2406 return rte_flow_error_set(error, EINVAL,
2407 RTE_FLOW_ERROR_TYPE_ACTION,
2409 "no IP protocol in pattern");
2415 * Validate jump action.
2418 * Pointer to the jump action.
2419 * @param[in] action_flags
2420 * Holds the actions detected until now.
2421 * @param[in] attributes
2422 * Pointer to flow attributes
2423 * @param[in] external
2424 * Action belongs to flow rule created by request external to PMD.
2426 * Pointer to error structure.
2429 * 0 on success, a negative errno value otherwise and rte_errno is set.
2432 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2433 uint64_t action_flags,
2434 const struct rte_flow_attr *attributes,
2435 bool external, struct rte_flow_error *error)
2437 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2439 uint32_t target_group, table;
2442 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2443 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2444 return rte_flow_error_set(error, EINVAL,
2445 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2446 "can't have 2 fate actions in"
2449 return rte_flow_error_set(error, EINVAL,
2450 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2451 NULL, "action configuration not set");
2453 ((const struct rte_flow_action_jump *)action->conf)->group;
2454 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2458 if (table >= max_group)
2459 return rte_flow_error_set(error, EINVAL,
2460 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2461 "target group index out of range");
2462 if (attributes->group >= target_group)
2463 return rte_flow_error_set(error, EINVAL,
2464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2465 "target group must be higher than"
2466 " the current flow group");
2471 * Validate the port_id action.
2474 * Pointer to rte_eth_dev structure.
2475 * @param[in] action_flags
2476 * Bit-fields that holds the actions detected until now.
2478 * Port_id RTE action structure.
2480 * Attributes of flow that includes this action.
2482 * Pointer to error structure.
2485 * 0 on success, a negative errno value otherwise and rte_errno is set.
2488 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2489 uint64_t action_flags,
2490 const struct rte_flow_action *action,
2491 const struct rte_flow_attr *attr,
2492 struct rte_flow_error *error)
2494 const struct rte_flow_action_port_id *port_id;
2495 struct mlx5_priv *act_priv;
2496 struct mlx5_priv *dev_priv;
2499 if (!attr->transfer)
2500 return rte_flow_error_set(error, ENOTSUP,
2501 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2503 "port id action is valid in transfer"
2505 if (!action || !action->conf)
2506 return rte_flow_error_set(error, ENOTSUP,
2507 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2509 "port id action parameters must be"
2511 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2512 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2513 return rte_flow_error_set(error, EINVAL,
2514 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2515 "can have only one fate actions in"
2517 dev_priv = mlx5_dev_to_eswitch_info(dev);
2519 return rte_flow_error_set(error, rte_errno,
2520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2522 "failed to obtain E-Switch info");
2523 port_id = action->conf;
2524 port = port_id->original ? dev->data->port_id : port_id->id;
2525 act_priv = mlx5_port_to_eswitch_info(port);
2527 return rte_flow_error_set
2529 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2530 "failed to obtain E-Switch port id for port");
2531 if (act_priv->domain_id != dev_priv->domain_id)
2532 return rte_flow_error_set
2534 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2535 "port does not belong to"
2536 " E-Switch being configured");
2541 * Find existing modify-header resource or create and register a new one.
2543 * @param dev[in, out]
2544 * Pointer to rte_eth_dev structure.
2545 * @param[in, out] resource
2546 * Pointer to modify-header resource.
2547 * @parm[in, out] dev_flow
2548 * Pointer to the dev_flow.
2550 * pointer to error structure.
2553 * 0 on success otherwise -errno and errno is set.
2556 flow_dv_modify_hdr_resource_register
2557 (struct rte_eth_dev *dev,
2558 struct mlx5_flow_dv_modify_hdr_resource *resource,
2559 struct mlx5_flow *dev_flow,
2560 struct rte_flow_error *error)
2562 struct mlx5_priv *priv = dev->data->dev_private;
2563 struct mlx5_ibv_shared *sh = priv->sh;
2564 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2565 struct mlx5dv_dr_domain *ns;
2567 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2568 ns = sh->fdb_domain;
2569 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2574 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2575 /* Lookup a matching resource from cache. */
2576 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2577 if (resource->ft_type == cache_resource->ft_type &&
2578 resource->actions_num == cache_resource->actions_num &&
2579 resource->flags == cache_resource->flags &&
2580 !memcmp((const void *)resource->actions,
2581 (const void *)cache_resource->actions,
2582 (resource->actions_num *
2583 sizeof(resource->actions[0])))) {
2584 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2585 (void *)cache_resource,
2586 rte_atomic32_read(&cache_resource->refcnt));
2587 rte_atomic32_inc(&cache_resource->refcnt);
2588 dev_flow->dv.modify_hdr = cache_resource;
2592 /* Register new modify-header resource. */
2593 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2594 if (!cache_resource)
2595 return rte_flow_error_set(error, ENOMEM,
2596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597 "cannot allocate resource memory");
2598 *cache_resource = *resource;
2599 cache_resource->verbs_action =
2600 mlx5_glue->dv_create_flow_action_modify_header
2601 (sh->ctx, cache_resource->ft_type,
2602 ns, cache_resource->flags,
2603 cache_resource->actions_num *
2604 sizeof(cache_resource->actions[0]),
2605 (uint64_t *)cache_resource->actions);
2606 if (!cache_resource->verbs_action) {
2607 rte_free(cache_resource);
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2610 NULL, "cannot create action");
2612 rte_atomic32_init(&cache_resource->refcnt);
2613 rte_atomic32_inc(&cache_resource->refcnt);
2614 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2615 dev_flow->dv.modify_hdr = cache_resource;
2616 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2617 (void *)cache_resource,
2618 rte_atomic32_read(&cache_resource->refcnt));
2622 #define MLX5_CNT_CONTAINER_RESIZE 64
2625 * Get or create a flow counter.
2628 * Pointer to the Ethernet device structure.
2630 * Indicate if this counter is shared with other flows.
2632 * Counter identifier.
2635 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2637 static struct mlx5_flow_counter *
2638 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2641 struct mlx5_priv *priv = dev->data->dev_private;
2642 struct mlx5_flow_counter *cnt = NULL;
2643 struct mlx5_devx_obj *dcs = NULL;
2645 if (!priv->config.devx) {
2646 rte_errno = ENOTSUP;
2650 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2651 if (cnt->shared && cnt->id == id) {
2657 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2660 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2662 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2666 struct mlx5_flow_counter tmpl = {
2672 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2674 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2680 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2685 * Release a flow counter.
2688 * Pointer to the Ethernet device structure.
2689 * @param[in] counter
2690 * Pointer to the counter handler.
2693 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2694 struct mlx5_flow_counter *counter)
2696 struct mlx5_priv *priv = dev->data->dev_private;
2700 if (--counter->ref_cnt == 0) {
2701 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2702 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2708 * Query a devx flow counter.
2711 * Pointer to the Ethernet device structure.
2713 * Pointer to the flow counter.
2715 * The statistics value of packets.
2717 * The statistics value of bytes.
2720 * 0 on success, otherwise a negative errno value and rte_errno is set.
2723 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2724 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2727 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2732 * Get a pool by a counter.
2735 * Pointer to the counter.
2740 static struct mlx5_flow_counter_pool *
2741 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2744 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2745 return (struct mlx5_flow_counter_pool *)cnt - 1;
2751 * Get a pool by devx counter ID.
2754 * Pointer to the counter container.
2756 * The counter devx ID.
2759 * The counter pool pointer if exists, NULL otherwise,
2761 static struct mlx5_flow_counter_pool *
2762 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2764 struct mlx5_flow_counter_pool *pool;
2766 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2767 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2768 MLX5_COUNTERS_PER_POOL;
2770 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2777 * Allocate a new memory for the counter values wrapped by all the needed
2781 * Pointer to the Ethernet device structure.
2783 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2786 * The new memory management pointer on success, otherwise NULL and rte_errno
2789 static struct mlx5_counter_stats_mem_mng *
2790 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2792 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2793 (dev->data->dev_private))->sh;
2794 struct mlx5_devx_mkey_attr mkey_attr;
2795 struct mlx5_counter_stats_mem_mng *mem_mng;
2796 volatile struct flow_counter_stats *raw_data;
2797 int size = (sizeof(struct flow_counter_stats) *
2798 MLX5_COUNTERS_PER_POOL +
2799 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2800 sizeof(struct mlx5_counter_stats_mem_mng);
2801 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2808 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2809 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2810 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2811 IBV_ACCESS_LOCAL_WRITE);
2812 if (!mem_mng->umem) {
2817 mkey_attr.addr = (uintptr_t)mem;
2818 mkey_attr.size = size;
2819 mkey_attr.umem_id = mem_mng->umem->umem_id;
2820 mkey_attr.pd = sh->pdn;
2821 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2823 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2828 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2829 raw_data = (volatile struct flow_counter_stats *)mem;
2830 for (i = 0; i < raws_n; ++i) {
2831 mem_mng->raws[i].mem_mng = mem_mng;
2832 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2834 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2839 * Resize a counter container.
2842 * Pointer to the Ethernet device structure.
2844 * Whether the pool is for counter that was allocated by batch command.
2847 * The new container pointer on success, otherwise NULL and rte_errno is set.
2849 static struct mlx5_pools_container *
2850 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2852 struct mlx5_priv *priv = dev->data->dev_private;
2853 struct mlx5_pools_container *cont =
2854 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2855 struct mlx5_pools_container *new_cont =
2856 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2857 struct mlx5_counter_stats_mem_mng *mem_mng;
2858 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2859 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2862 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2863 /* The last resize still hasn't detected by the host thread. */
2867 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2868 if (!new_cont->pools) {
2873 memcpy(new_cont->pools, cont->pools, cont->n *
2874 sizeof(struct mlx5_flow_counter_pool *));
2875 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2876 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2878 rte_free(new_cont->pools);
2881 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2882 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2883 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2885 new_cont->n = resize;
2886 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2887 TAILQ_INIT(&new_cont->pool_list);
2888 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2889 new_cont->init_mem_mng = mem_mng;
2891 /* Flip the master container. */
2892 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2897 * Query a devx flow counter.
2900 * Pointer to the Ethernet device structure.
2902 * Pointer to the flow counter.
2904 * The statistics value of packets.
2906 * The statistics value of bytes.
2909 * 0 on success, otherwise a negative errno value and rte_errno is set.
2912 _flow_dv_query_count(struct rte_eth_dev *dev,
2913 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2916 struct mlx5_priv *priv = dev->data->dev_private;
2917 struct mlx5_flow_counter_pool *pool =
2918 flow_dv_counter_pool_get(cnt);
2919 int offset = cnt - &pool->counters_raw[0];
2921 if (priv->counter_fallback)
2922 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2924 rte_spinlock_lock(&pool->sl);
2926 * The single counters allocation may allocate smaller ID than the
2927 * current allocated in parallel to the host reading.
2928 * In this case the new counter values must be reported as 0.
2930 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2934 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2935 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2937 rte_spinlock_unlock(&pool->sl);
2942 * Create and initialize a new counter pool.
2945 * Pointer to the Ethernet device structure.
2947 * The devX counter handle.
2949 * Whether the pool is for counter that was allocated by batch command.
2952 * A new pool pointer on success, NULL otherwise and rte_errno is set.
2954 static struct mlx5_flow_counter_pool *
2955 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
2958 struct mlx5_priv *priv = dev->data->dev_private;
2959 struct mlx5_flow_counter_pool *pool;
2960 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2962 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
2965 if (cont->n == n_valid) {
2966 cont = flow_dv_container_resize(dev, batch);
2970 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
2971 sizeof(struct mlx5_flow_counter);
2972 pool = rte_calloc(__func__, 1, size, 0);
2977 pool->min_dcs = dcs;
2978 pool->raw = cont->init_mem_mng->raws + n_valid %
2979 MLX5_CNT_CONTAINER_RESIZE;
2980 pool->raw_hw = NULL;
2981 rte_spinlock_init(&pool->sl);
2983 * The generation of the new allocated counters in this pool is 0, 2 in
2984 * the pool generation makes all the counters valid for allocation.
2986 rte_atomic64_set(&pool->query_gen, 0x2);
2987 TAILQ_INIT(&pool->counters);
2988 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2989 cont->pools[n_valid] = pool;
2990 /* Pool initialization must be updated before host thread access. */
2992 rte_atomic16_add(&cont->n_valid, 1);
2997 * Prepare a new counter and/or a new counter pool.
3000 * Pointer to the Ethernet device structure.
3001 * @param[out] cnt_free
3002 * Where to put the pointer of a new counter.
3004 * Whether the pool is for counter that was allocated by batch command.
3007 * The free counter pool pointer and @p cnt_free is set on success,
3008 * NULL otherwise and rte_errno is set.
3010 static struct mlx5_flow_counter_pool *
3011 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3012 struct mlx5_flow_counter **cnt_free,
3015 struct mlx5_priv *priv = dev->data->dev_private;
3016 struct mlx5_flow_counter_pool *pool;
3017 struct mlx5_devx_obj *dcs = NULL;
3018 struct mlx5_flow_counter *cnt;
3022 /* bulk_bitmap must be 0 for single counter allocation. */
3023 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3026 pool = flow_dv_find_pool_by_id
3027 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3029 pool = flow_dv_pool_create(dev, dcs, batch);
3031 mlx5_devx_cmd_destroy(dcs);
3034 } else if (dcs->id < pool->min_dcs->id) {
3035 rte_atomic64_set(&pool->a64_dcs,
3036 (int64_t)(uintptr_t)dcs);
3038 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3039 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3044 /* bulk_bitmap is in 128 counters units. */
3045 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3046 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3048 rte_errno = ENODATA;
3051 pool = flow_dv_pool_create(dev, dcs, batch);
3053 mlx5_devx_cmd_destroy(dcs);
3056 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3057 cnt = &pool->counters_raw[i];
3059 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3061 *cnt_free = &pool->counters_raw[0];
3066 * Search for existed shared counter.
3069 * Pointer to the relevant counter pool container.
3071 * The shared counter ID to search.
3074 * NULL if not existed, otherwise pointer to the shared counter.
3076 static struct mlx5_flow_counter *
3077 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3080 static struct mlx5_flow_counter *cnt;
3081 struct mlx5_flow_counter_pool *pool;
3084 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3085 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3086 cnt = &pool->counters_raw[i];
3087 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3095 * Allocate a flow counter.
3098 * Pointer to the Ethernet device structure.
3100 * Indicate if this counter is shared with other flows.
3102 * Counter identifier.
3104 * Counter flow group.
3107 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3109 static struct mlx5_flow_counter *
3110 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3113 struct mlx5_priv *priv = dev->data->dev_private;
3114 struct mlx5_flow_counter_pool *pool = NULL;
3115 struct mlx5_flow_counter *cnt_free = NULL;
3117 * Currently group 0 flow counter cannot be assigned to a flow if it is
3118 * not the first one in the batch counter allocation, so it is better
3119 * to allocate counters one by one for these flows in a separate
3121 * A counter can be shared between different groups so need to take
3122 * shared counters from the single container.
3124 uint32_t batch = (group && !shared) ? 1 : 0;
3125 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3128 if (priv->counter_fallback)
3129 return flow_dv_counter_alloc_fallback(dev, shared, id);
3130 if (!priv->config.devx) {
3131 rte_errno = ENOTSUP;
3135 cnt_free = flow_dv_counter_shared_search(cont, id);
3137 if (cnt_free->ref_cnt + 1 == 0) {
3141 cnt_free->ref_cnt++;
3145 /* Pools which has a free counters are in the start. */
3146 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3148 * The free counter reset values must be updated between the
3149 * counter release to the counter allocation, so, at least one
3150 * query must be done in this time. ensure it by saving the
3151 * query generation in the release time.
3152 * The free list is sorted according to the generation - so if
3153 * the first one is not updated, all the others are not
3156 cnt_free = TAILQ_FIRST(&pool->counters);
3157 if (cnt_free && cnt_free->query_gen + 1 <
3158 rte_atomic64_read(&pool->query_gen))
3163 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3167 cnt_free->batch = batch;
3168 /* Create a DV counter action only in the first time usage. */
3169 if (!cnt_free->action) {
3171 struct mlx5_devx_obj *dcs;
3174 offset = cnt_free - &pool->counters_raw[0];
3175 dcs = pool->min_dcs;
3178 dcs = cnt_free->dcs;
3180 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3182 if (!cnt_free->action) {
3187 /* Update the counter reset values. */
3188 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3191 cnt_free->shared = shared;
3192 cnt_free->ref_cnt = 1;
3194 if (!priv->sh->cmng.query_thread_on)
3195 /* Start the asynchronous batch query by the host thread. */
3196 mlx5_set_query_alarm(priv->sh);
3197 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3198 if (TAILQ_EMPTY(&pool->counters)) {
3199 /* Move the pool to the end of the container pool list. */
3200 TAILQ_REMOVE(&cont->pool_list, pool, next);
3201 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3207 * Release a flow counter.
3210 * Pointer to the Ethernet device structure.
3211 * @param[in] counter
3212 * Pointer to the counter handler.
3215 flow_dv_counter_release(struct rte_eth_dev *dev,
3216 struct mlx5_flow_counter *counter)
3218 struct mlx5_priv *priv = dev->data->dev_private;
3222 if (priv->counter_fallback) {
3223 flow_dv_counter_release_fallback(dev, counter);
3226 if (--counter->ref_cnt == 0) {
3227 struct mlx5_flow_counter_pool *pool =
3228 flow_dv_counter_pool_get(counter);
3230 /* Put the counter in the end - the last updated one. */
3231 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3232 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3237 * Verify the @p attributes will be correctly understood by the NIC and store
3238 * them in the @p flow if everything is correct.
3241 * Pointer to dev struct.
3242 * @param[in] attributes
3243 * Pointer to flow attributes
3244 * @param[in] external
3245 * This flow rule is created by request external to PMD.
3247 * Pointer to error structure.
3250 * 0 on success, a negative errno value otherwise and rte_errno is set.
3253 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3254 const struct rte_flow_attr *attributes,
3255 bool external __rte_unused,
3256 struct rte_flow_error *error)
3258 struct mlx5_priv *priv = dev->data->dev_private;
3259 uint32_t priority_max = priv->config.flow_prio - 1;
3261 #ifndef HAVE_MLX5DV_DR
3262 if (attributes->group)
3263 return rte_flow_error_set(error, ENOTSUP,
3264 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3266 "groups are not supported");
3268 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3273 ret = mlx5_flow_group_to_table(attributes, external,
3278 if (table >= max_group)
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3281 "group index out of range");
3283 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3284 attributes->priority >= priority_max)
3285 return rte_flow_error_set(error, ENOTSUP,
3286 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3288 "priority out of range");
3289 if (attributes->transfer) {
3290 if (!priv->config.dv_esw_en)
3291 return rte_flow_error_set
3293 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3294 "E-Switch dr is not supported");
3295 if (!(priv->representor || priv->master))
3296 return rte_flow_error_set
3297 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3298 NULL, "E-Switch configuration can only be"
3299 " done by a master or a representor device");
3300 if (attributes->egress)
3301 return rte_flow_error_set
3303 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3304 "egress is not supported");
3306 if (!(attributes->egress ^ attributes->ingress))
3307 return rte_flow_error_set(error, ENOTSUP,
3308 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3309 "must specify exactly one of "
3310 "ingress or egress");
3315 * Internal validation function. For validating both actions and items.
3318 * Pointer to the rte_eth_dev structure.
3320 * Pointer to the flow attributes.
3322 * Pointer to the list of items.
3323 * @param[in] actions
3324 * Pointer to the list of actions.
3325 * @param[in] external
3326 * This flow rule is created by request external to PMD.
3328 * Pointer to the error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3335 const struct rte_flow_item items[],
3336 const struct rte_flow_action actions[],
3337 bool external, struct rte_flow_error *error)
3340 uint64_t action_flags = 0;
3341 uint64_t item_flags = 0;
3342 uint64_t last_item = 0;
3343 uint8_t next_protocol = 0xff;
3345 const struct rte_flow_item *gre_item = NULL;
3346 struct rte_flow_item_tcp nic_tcp_mask = {
3349 .src_port = RTE_BE16(UINT16_MAX),
3350 .dst_port = RTE_BE16(UINT16_MAX),
3356 ret = flow_dv_validate_attributes(dev, attr, external, error);
3359 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3360 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3361 int type = items->type;
3364 case RTE_FLOW_ITEM_TYPE_VOID:
3366 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3367 ret = flow_dv_validate_item_port_id
3368 (dev, items, attr, item_flags, error);
3371 last_item = MLX5_FLOW_ITEM_PORT_ID;
3373 case RTE_FLOW_ITEM_TYPE_ETH:
3374 ret = mlx5_flow_validate_item_eth(items, item_flags,
3378 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3379 MLX5_FLOW_LAYER_OUTER_L2;
3381 case RTE_FLOW_ITEM_TYPE_VLAN:
3382 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3386 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3387 MLX5_FLOW_LAYER_OUTER_VLAN;
3389 case RTE_FLOW_ITEM_TYPE_IPV4:
3390 mlx5_flow_tunnel_ip_check(items, next_protocol,
3391 &item_flags, &tunnel);
3392 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3396 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3397 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3398 if (items->mask != NULL &&
3399 ((const struct rte_flow_item_ipv4 *)
3400 items->mask)->hdr.next_proto_id) {
3402 ((const struct rte_flow_item_ipv4 *)
3403 (items->spec))->hdr.next_proto_id;
3405 ((const struct rte_flow_item_ipv4 *)
3406 (items->mask))->hdr.next_proto_id;
3408 /* Reset for inner layer. */
3409 next_protocol = 0xff;
3412 case RTE_FLOW_ITEM_TYPE_IPV6:
3413 mlx5_flow_tunnel_ip_check(items, next_protocol,
3414 &item_flags, &tunnel);
3415 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3419 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3420 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3421 if (items->mask != NULL &&
3422 ((const struct rte_flow_item_ipv6 *)
3423 items->mask)->hdr.proto) {
3425 ((const struct rte_flow_item_ipv6 *)
3426 items->spec)->hdr.proto;
3428 ((const struct rte_flow_item_ipv6 *)
3429 items->mask)->hdr.proto;
3431 /* Reset for inner layer. */
3432 next_protocol = 0xff;
3435 case RTE_FLOW_ITEM_TYPE_TCP:
3436 ret = mlx5_flow_validate_item_tcp
3443 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3444 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3446 case RTE_FLOW_ITEM_TYPE_UDP:
3447 ret = mlx5_flow_validate_item_udp(items, item_flags,
3452 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3453 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3455 case RTE_FLOW_ITEM_TYPE_GRE:
3456 ret = mlx5_flow_validate_item_gre(items, item_flags,
3457 next_protocol, error);
3461 last_item = MLX5_FLOW_LAYER_GRE;
3463 case RTE_FLOW_ITEM_TYPE_NVGRE:
3464 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3469 last_item = MLX5_FLOW_LAYER_NVGRE;
3471 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3472 ret = mlx5_flow_validate_item_gre_key
3473 (items, item_flags, gre_item, error);
3476 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3478 case RTE_FLOW_ITEM_TYPE_VXLAN:
3479 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3483 last_item = MLX5_FLOW_LAYER_VXLAN;
3485 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3486 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3491 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3493 case RTE_FLOW_ITEM_TYPE_GENEVE:
3494 ret = mlx5_flow_validate_item_geneve(items,
3499 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3501 case RTE_FLOW_ITEM_TYPE_MPLS:
3502 ret = mlx5_flow_validate_item_mpls(dev, items,
3507 last_item = MLX5_FLOW_LAYER_MPLS;
3509 case RTE_FLOW_ITEM_TYPE_META:
3510 ret = flow_dv_validate_item_meta(dev, items, attr,
3514 last_item = MLX5_FLOW_ITEM_METADATA;
3516 case RTE_FLOW_ITEM_TYPE_ICMP:
3517 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3522 last_item = MLX5_FLOW_LAYER_ICMP;
3524 case RTE_FLOW_ITEM_TYPE_ICMP6:
3525 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3530 last_item = MLX5_FLOW_LAYER_ICMP6;
3532 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3533 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3536 return rte_flow_error_set(error, ENOTSUP,
3537 RTE_FLOW_ERROR_TYPE_ITEM,
3538 NULL, "item not supported");
3540 item_flags |= last_item;
3542 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3543 int type = actions->type;
3544 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3545 return rte_flow_error_set(error, ENOTSUP,
3546 RTE_FLOW_ERROR_TYPE_ACTION,
3547 actions, "too many actions");
3549 case RTE_FLOW_ACTION_TYPE_VOID:
3551 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3552 ret = flow_dv_validate_action_port_id(dev,
3559 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3562 case RTE_FLOW_ACTION_TYPE_FLAG:
3563 ret = mlx5_flow_validate_action_flag(action_flags,
3567 action_flags |= MLX5_FLOW_ACTION_FLAG;
3570 case RTE_FLOW_ACTION_TYPE_MARK:
3571 ret = mlx5_flow_validate_action_mark(actions,
3576 action_flags |= MLX5_FLOW_ACTION_MARK;
3579 case RTE_FLOW_ACTION_TYPE_DROP:
3580 ret = mlx5_flow_validate_action_drop(action_flags,
3584 action_flags |= MLX5_FLOW_ACTION_DROP;
3587 case RTE_FLOW_ACTION_TYPE_QUEUE:
3588 ret = mlx5_flow_validate_action_queue(actions,
3593 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3596 case RTE_FLOW_ACTION_TYPE_RSS:
3597 ret = mlx5_flow_validate_action_rss(actions,
3603 action_flags |= MLX5_FLOW_ACTION_RSS;
3606 case RTE_FLOW_ACTION_TYPE_COUNT:
3607 ret = flow_dv_validate_action_count(dev, error);
3610 action_flags |= MLX5_FLOW_ACTION_COUNT;
3613 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3614 if (flow_dv_validate_action_pop_vlan(dev,
3620 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3623 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3624 ret = flow_dv_validate_action_push_vlan(action_flags,
3629 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3632 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3633 ret = flow_dv_validate_action_set_vlan_pcp
3634 (action_flags, actions, error);
3637 /* Count PCP with push_vlan command. */
3639 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3640 ret = flow_dv_validate_action_set_vlan_vid
3641 (item_flags, actions, error);
3644 /* Count VID with push_vlan command. */
3646 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3647 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3648 ret = flow_dv_validate_action_l2_encap(action_flags,
3653 action_flags |= actions->type ==
3654 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3655 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3656 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3659 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3660 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3661 ret = flow_dv_validate_action_l2_decap(action_flags,
3665 action_flags |= actions->type ==
3666 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3667 MLX5_FLOW_ACTION_VXLAN_DECAP :
3668 MLX5_FLOW_ACTION_NVGRE_DECAP;
3671 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3672 ret = flow_dv_validate_action_raw_encap(action_flags,
3677 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3680 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3681 ret = flow_dv_validate_action_raw_decap(action_flags,
3686 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3689 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3690 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3691 ret = flow_dv_validate_action_modify_mac(action_flags,
3697 /* Count all modify-header actions as one action. */
3698 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3700 action_flags |= actions->type ==
3701 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3702 MLX5_FLOW_ACTION_SET_MAC_SRC :
3703 MLX5_FLOW_ACTION_SET_MAC_DST;
3706 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3707 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3708 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3714 /* Count all modify-header actions as one action. */
3715 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3717 action_flags |= actions->type ==
3718 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3719 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3720 MLX5_FLOW_ACTION_SET_IPV4_DST;
3722 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3723 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3724 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3730 /* Count all modify-header actions as one action. */
3731 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3733 action_flags |= actions->type ==
3734 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3735 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3736 MLX5_FLOW_ACTION_SET_IPV6_DST;
3738 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3739 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3740 ret = flow_dv_validate_action_modify_tp(action_flags,
3746 /* Count all modify-header actions as one action. */
3747 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3749 action_flags |= actions->type ==
3750 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3751 MLX5_FLOW_ACTION_SET_TP_SRC :
3752 MLX5_FLOW_ACTION_SET_TP_DST;
3754 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3755 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3756 ret = flow_dv_validate_action_modify_ttl(action_flags,
3762 /* Count all modify-header actions as one action. */
3763 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3765 action_flags |= actions->type ==
3766 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3767 MLX5_FLOW_ACTION_SET_TTL :
3768 MLX5_FLOW_ACTION_DEC_TTL;
3770 case RTE_FLOW_ACTION_TYPE_JUMP:
3771 ret = flow_dv_validate_action_jump(actions,
3778 action_flags |= MLX5_FLOW_ACTION_JUMP;
3780 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3781 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3782 ret = flow_dv_validate_action_modify_tcp_seq
3789 /* Count all modify-header actions as one action. */
3790 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3792 action_flags |= actions->type ==
3793 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3794 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3795 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3797 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3798 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3799 ret = flow_dv_validate_action_modify_tcp_ack
3806 /* Count all modify-header actions as one action. */
3807 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3809 action_flags |= actions->type ==
3810 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3811 MLX5_FLOW_ACTION_INC_TCP_ACK :
3812 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3814 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
3817 return rte_flow_error_set(error, ENOTSUP,
3818 RTE_FLOW_ERROR_TYPE_ACTION,
3820 "action not supported");
3823 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3824 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3825 return rte_flow_error_set(error, ENOTSUP,
3826 RTE_FLOW_ERROR_TYPE_ACTION,
3828 "can't have vxlan and vlan"
3829 " actions in the same rule");
3830 /* Eswitch has few restrictions on using items and actions */
3831 if (attr->transfer) {
3832 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3833 return rte_flow_error_set(error, ENOTSUP,
3834 RTE_FLOW_ERROR_TYPE_ACTION,
3836 "unsupported action FLAG");
3837 if (action_flags & MLX5_FLOW_ACTION_MARK)
3838 return rte_flow_error_set(error, ENOTSUP,
3839 RTE_FLOW_ERROR_TYPE_ACTION,
3841 "unsupported action MARK");
3842 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3843 return rte_flow_error_set(error, ENOTSUP,
3844 RTE_FLOW_ERROR_TYPE_ACTION,
3846 "unsupported action QUEUE");
3847 if (action_flags & MLX5_FLOW_ACTION_RSS)
3848 return rte_flow_error_set(error, ENOTSUP,
3849 RTE_FLOW_ERROR_TYPE_ACTION,
3851 "unsupported action RSS");
3852 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3853 return rte_flow_error_set(error, EINVAL,
3854 RTE_FLOW_ERROR_TYPE_ACTION,
3856 "no fate action is found");
3858 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3859 return rte_flow_error_set(error, EINVAL,
3860 RTE_FLOW_ERROR_TYPE_ACTION,
3862 "no fate action is found");
3868 * Internal preparation function. Allocates the DV flow size,
3869 * this size is constant.
3872 * Pointer to the flow attributes.
3874 * Pointer to the list of items.
3875 * @param[in] actions
3876 * Pointer to the list of actions.
3878 * Pointer to the error structure.
3881 * Pointer to mlx5_flow object on success,
3882 * otherwise NULL and rte_errno is set.
3884 static struct mlx5_flow *
3885 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3886 const struct rte_flow_item items[] __rte_unused,
3887 const struct rte_flow_action actions[] __rte_unused,
3888 struct rte_flow_error *error)
3890 uint32_t size = sizeof(struct mlx5_flow);
3891 struct mlx5_flow *flow;
3893 flow = rte_calloc(__func__, 1, size, 0);
3895 rte_flow_error_set(error, ENOMEM,
3896 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3897 "not enough memory to create flow");
3900 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3906 * Sanity check for match mask and value. Similar to check_valid_spec() in
3907 * kernel driver. If unmasked bit is present in value, it returns failure.
3910 * pointer to match mask buffer.
3911 * @param match_value
3912 * pointer to match value buffer.
3915 * 0 if valid, -EINVAL otherwise.
3918 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3920 uint8_t *m = match_mask;
3921 uint8_t *v = match_value;
3924 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3927 "match_value differs from match_criteria"
3928 " %p[%u] != %p[%u]",
3929 match_value, i, match_mask, i);
3938 * Add Ethernet item to matcher and to the value.
3940 * @param[in, out] matcher
3942 * @param[in, out] key
3943 * Flow matcher value.
3945 * Flow pattern to translate.
3947 * Item is inner pattern.
3950 flow_dv_translate_item_eth(void *matcher, void *key,
3951 const struct rte_flow_item *item, int inner)
3953 const struct rte_flow_item_eth *eth_m = item->mask;
3954 const struct rte_flow_item_eth *eth_v = item->spec;
3955 const struct rte_flow_item_eth nic_mask = {
3956 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3957 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3958 .type = RTE_BE16(0xffff),
3970 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3972 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3974 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3976 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3978 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
3979 ð_m->dst, sizeof(eth_m->dst));
3980 /* The value must be in the range of the mask. */
3981 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
3982 for (i = 0; i < sizeof(eth_m->dst); ++i)
3983 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
3984 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
3985 ð_m->src, sizeof(eth_m->src));
3986 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
3987 /* The value must be in the range of the mask. */
3988 for (i = 0; i < sizeof(eth_m->dst); ++i)
3989 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
3990 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3991 rte_be_to_cpu_16(eth_m->type));
3992 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
3993 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
3997 * Add VLAN item to matcher and to the value.
3999 * @param[in, out] dev_flow
4001 * @param[in, out] matcher
4003 * @param[in, out] key
4004 * Flow matcher value.
4006 * Flow pattern to translate.
4008 * Item is inner pattern.
4011 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4012 void *matcher, void *key,
4013 const struct rte_flow_item *item,
4016 const struct rte_flow_item_vlan *vlan_m = item->mask;
4017 const struct rte_flow_item_vlan *vlan_v = item->spec;
4026 vlan_m = &rte_flow_item_vlan_mask;
4028 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4030 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4032 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4034 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4036 * This is workaround, masks are not supported,
4037 * and pre-validated.
4039 dev_flow->dv.vf_vlan.tag =
4040 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4042 tci_m = rte_be_to_cpu_16(vlan_m->tci);
4043 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4044 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4045 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4046 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4047 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4048 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4049 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4050 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4051 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4052 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4053 rte_be_to_cpu_16(vlan_m->inner_type));
4054 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4055 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4059 * Add IPV4 item to matcher and to the value.
4061 * @param[in, out] matcher
4063 * @param[in, out] key
4064 * Flow matcher value.
4066 * Flow pattern to translate.
4068 * Item is inner pattern.
4070 * The group to insert the rule.
4073 flow_dv_translate_item_ipv4(void *matcher, void *key,
4074 const struct rte_flow_item *item,
4075 int inner, uint32_t group)
4077 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4078 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4079 const struct rte_flow_item_ipv4 nic_mask = {
4081 .src_addr = RTE_BE32(0xffffffff),
4082 .dst_addr = RTE_BE32(0xffffffff),
4083 .type_of_service = 0xff,
4084 .next_proto_id = 0xff,
4094 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4096 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4098 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4100 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4103 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4105 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4106 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4111 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4112 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4113 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4114 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4115 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4116 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4117 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4118 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4119 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4120 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4121 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4122 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4123 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4124 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4125 ipv4_m->hdr.type_of_service);
4126 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4127 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4128 ipv4_m->hdr.type_of_service >> 2);
4129 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4130 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4131 ipv4_m->hdr.next_proto_id);
4132 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4133 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4137 * Add IPV6 item to matcher and to the value.
4139 * @param[in, out] matcher
4141 * @param[in, out] key
4142 * Flow matcher value.
4144 * Flow pattern to translate.
4146 * Item is inner pattern.
4148 * The group to insert the rule.
4151 flow_dv_translate_item_ipv6(void *matcher, void *key,
4152 const struct rte_flow_item *item,
4153 int inner, uint32_t group)
4155 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4156 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4157 const struct rte_flow_item_ipv6 nic_mask = {
4160 "\xff\xff\xff\xff\xff\xff\xff\xff"
4161 "\xff\xff\xff\xff\xff\xff\xff\xff",
4163 "\xff\xff\xff\xff\xff\xff\xff\xff"
4164 "\xff\xff\xff\xff\xff\xff\xff\xff",
4165 .vtc_flow = RTE_BE32(0xffffffff),
4172 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4173 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4182 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4184 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4186 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4188 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4191 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4193 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4194 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4199 size = sizeof(ipv6_m->hdr.dst_addr);
4200 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4201 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4202 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4203 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4204 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4205 for (i = 0; i < size; ++i)
4206 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4207 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4208 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4209 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4210 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4211 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4212 for (i = 0; i < size; ++i)
4213 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4215 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4216 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4217 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4219 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4223 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4225 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4228 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4230 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4236 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4237 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4241 * Add TCP item to matcher and to the value.
4243 * @param[in, out] matcher
4245 * @param[in, out] key
4246 * Flow matcher value.
4248 * Flow pattern to translate.
4250 * Item is inner pattern.
4253 flow_dv_translate_item_tcp(void *matcher, void *key,
4254 const struct rte_flow_item *item,
4257 const struct rte_flow_item_tcp *tcp_m = item->mask;
4258 const struct rte_flow_item_tcp *tcp_v = item->spec;
4263 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4265 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4267 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4269 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4271 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4272 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4276 tcp_m = &rte_flow_item_tcp_mask;
4277 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4278 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4279 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4280 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4281 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4282 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4283 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4284 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4286 tcp_m->hdr.tcp_flags);
4287 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4288 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4292 * Add UDP item to matcher and to the value.
4294 * @param[in, out] matcher
4296 * @param[in, out] key
4297 * Flow matcher value.
4299 * Flow pattern to translate.
4301 * Item is inner pattern.
4304 flow_dv_translate_item_udp(void *matcher, void *key,
4305 const struct rte_flow_item *item,
4308 const struct rte_flow_item_udp *udp_m = item->mask;
4309 const struct rte_flow_item_udp *udp_v = item->spec;
4314 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4316 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4318 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4320 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4322 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4323 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4327 udp_m = &rte_flow_item_udp_mask;
4328 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4329 rte_be_to_cpu_16(udp_m->hdr.src_port));
4330 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4331 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4332 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4333 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4335 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4339 * Add GRE optional Key item to matcher and to the value.
4341 * @param[in, out] matcher
4343 * @param[in, out] key
4344 * Flow matcher value.
4346 * Flow pattern to translate.
4348 * Item is inner pattern.
4351 flow_dv_translate_item_gre_key(void *matcher, void *key,
4352 const struct rte_flow_item *item)
4354 const rte_be32_t *key_m = item->mask;
4355 const rte_be32_t *key_v = item->spec;
4356 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4357 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4358 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4363 key_m = &gre_key_default_mask;
4364 /* GRE K bit must be on and should already be validated */
4365 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4366 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4367 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4368 rte_be_to_cpu_32(*key_m) >> 8);
4369 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4370 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4371 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4372 rte_be_to_cpu_32(*key_m) & 0xFF);
4373 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4374 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4378 * Add GRE item to matcher and to the value.
4380 * @param[in, out] matcher
4382 * @param[in, out] key
4383 * Flow matcher value.
4385 * Flow pattern to translate.
4387 * Item is inner pattern.
4390 flow_dv_translate_item_gre(void *matcher, void *key,
4391 const struct rte_flow_item *item,
4394 const struct rte_flow_item_gre *gre_m = item->mask;
4395 const struct rte_flow_item_gre *gre_v = item->spec;
4398 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4399 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4406 uint16_t s_present:1;
4407 uint16_t k_present:1;
4408 uint16_t rsvd_bit1:1;
4409 uint16_t c_present:1;
4413 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4416 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4418 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4420 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4422 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4424 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4425 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4429 gre_m = &rte_flow_item_gre_mask;
4430 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4431 rte_be_to_cpu_16(gre_m->protocol));
4432 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4433 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4434 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4435 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4436 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4437 gre_crks_rsvd0_ver_m.c_present);
4438 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4439 gre_crks_rsvd0_ver_v.c_present &
4440 gre_crks_rsvd0_ver_m.c_present);
4441 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4442 gre_crks_rsvd0_ver_m.k_present);
4443 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4444 gre_crks_rsvd0_ver_v.k_present &
4445 gre_crks_rsvd0_ver_m.k_present);
4446 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4447 gre_crks_rsvd0_ver_m.s_present);
4448 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4449 gre_crks_rsvd0_ver_v.s_present &
4450 gre_crks_rsvd0_ver_m.s_present);
4454 * Add NVGRE item to matcher and to the value.
4456 * @param[in, out] matcher
4458 * @param[in, out] key
4459 * Flow matcher value.
4461 * Flow pattern to translate.
4463 * Item is inner pattern.
4466 flow_dv_translate_item_nvgre(void *matcher, void *key,
4467 const struct rte_flow_item *item,
4470 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4471 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4472 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4473 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4474 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4475 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4481 /* For NVGRE, GRE header fields must be set with defined values. */
4482 const struct rte_flow_item_gre gre_spec = {
4483 .c_rsvd0_ver = RTE_BE16(0x2000),
4484 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4486 const struct rte_flow_item_gre gre_mask = {
4487 .c_rsvd0_ver = RTE_BE16(0xB000),
4488 .protocol = RTE_BE16(UINT16_MAX),
4490 const struct rte_flow_item gre_item = {
4495 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4499 nvgre_m = &rte_flow_item_nvgre_mask;
4500 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4501 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4502 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4503 memcpy(gre_key_m, tni_flow_id_m, size);
4504 for (i = 0; i < size; ++i)
4505 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4509 * Add VXLAN item to matcher and to the value.
4511 * @param[in, out] matcher
4513 * @param[in, out] key
4514 * Flow matcher value.
4516 * Flow pattern to translate.
4518 * Item is inner pattern.
4521 flow_dv_translate_item_vxlan(void *matcher, void *key,
4522 const struct rte_flow_item *item,
4525 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4526 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4529 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4530 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4538 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4540 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4542 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4544 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4546 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4547 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4548 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4549 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4550 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4555 vxlan_m = &rte_flow_item_vxlan_mask;
4556 size = sizeof(vxlan_m->vni);
4557 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4558 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4559 memcpy(vni_m, vxlan_m->vni, size);
4560 for (i = 0; i < size; ++i)
4561 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4565 * Add Geneve item to matcher and to the value.
4567 * @param[in, out] matcher
4569 * @param[in, out] key
4570 * Flow matcher value.
4572 * Flow pattern to translate.
4574 * Item is inner pattern.
4578 flow_dv_translate_item_geneve(void *matcher, void *key,
4579 const struct rte_flow_item *item, int inner)
4581 const struct rte_flow_item_geneve *geneve_m = item->mask;
4582 const struct rte_flow_item_geneve *geneve_v = item->spec;
4585 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4586 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4595 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4597 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4599 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4601 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4603 dport = MLX5_UDP_PORT_GENEVE;
4604 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4605 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4606 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4611 geneve_m = &rte_flow_item_geneve_mask;
4612 size = sizeof(geneve_m->vni);
4613 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4614 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4615 memcpy(vni_m, geneve_m->vni, size);
4616 for (i = 0; i < size; ++i)
4617 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4618 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4619 rte_be_to_cpu_16(geneve_m->protocol));
4620 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4621 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4622 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4623 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4624 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4625 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4626 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4627 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4628 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4629 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4630 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4631 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4632 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4636 * Add MPLS item to matcher and to the value.
4638 * @param[in, out] matcher
4640 * @param[in, out] key
4641 * Flow matcher value.
4643 * Flow pattern to translate.
4644 * @param[in] prev_layer
4645 * The protocol layer indicated in previous item.
4647 * Item is inner pattern.
4650 flow_dv_translate_item_mpls(void *matcher, void *key,
4651 const struct rte_flow_item *item,
4652 uint64_t prev_layer,
4655 const uint32_t *in_mpls_m = item->mask;
4656 const uint32_t *in_mpls_v = item->spec;
4657 uint32_t *out_mpls_m = 0;
4658 uint32_t *out_mpls_v = 0;
4659 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4660 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4661 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4663 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4664 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4665 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4667 switch (prev_layer) {
4668 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4671 MLX5_UDP_PORT_MPLS);
4673 case MLX5_FLOW_LAYER_GRE:
4674 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4675 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4676 RTE_ETHER_TYPE_MPLS);
4679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4687 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4688 switch (prev_layer) {
4689 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4691 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4692 outer_first_mpls_over_udp);
4694 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4695 outer_first_mpls_over_udp);
4697 case MLX5_FLOW_LAYER_GRE:
4699 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4700 outer_first_mpls_over_gre);
4702 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4703 outer_first_mpls_over_gre);
4706 /* Inner MPLS not over GRE is not supported. */
4709 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4713 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4719 if (out_mpls_m && out_mpls_v) {
4720 *out_mpls_m = *in_mpls_m;
4721 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4726 * Add META item to matcher
4728 * @param[in, out] matcher
4730 * @param[in, out] key
4731 * Flow matcher value.
4733 * Flow pattern to translate.
4735 * Item is inner pattern.
4738 flow_dv_translate_item_meta(void *matcher, void *key,
4739 const struct rte_flow_item *item)
4741 const struct rte_flow_item_meta *meta_m;
4742 const struct rte_flow_item_meta *meta_v;
4744 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4746 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4748 meta_m = (const void *)item->mask;
4750 meta_m = &rte_flow_item_meta_mask;
4751 meta_v = (const void *)item->spec;
4753 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4754 rte_be_to_cpu_32(meta_m->data));
4755 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4756 rte_be_to_cpu_32(meta_v->data & meta_m->data));
4761 * Add vport metadata Reg C0 item to matcher
4763 * @param[in, out] matcher
4765 * @param[in, out] key
4766 * Flow matcher value.
4768 * Flow pattern to translate.
4771 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4772 uint32_t value, uint32_t mask)
4775 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4777 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4779 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4780 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4784 * Add tag item to matcher
4786 * @param[in, out] matcher
4788 * @param[in, out] key
4789 * Flow matcher value.
4791 * Flow pattern to translate.
4794 flow_dv_translate_item_tag(void *matcher, void *key,
4795 const struct rte_flow_item *item)
4798 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4800 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4801 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
4802 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
4803 enum modify_reg reg = tag_v->id;
4804 rte_be32_t value = tag_v->data;
4805 rte_be32_t mask = tag_m->data;
4809 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4810 rte_be_to_cpu_32(mask));
4811 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4812 rte_be_to_cpu_32(value));
4815 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
4816 rte_be_to_cpu_32(mask));
4817 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
4818 rte_be_to_cpu_32(value));
4821 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
4822 rte_be_to_cpu_32(mask));
4823 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
4824 rte_be_to_cpu_32(value));
4827 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
4828 rte_be_to_cpu_32(mask));
4829 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
4830 rte_be_to_cpu_32(value));
4833 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
4834 rte_be_to_cpu_32(mask));
4835 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
4836 rte_be_to_cpu_32(value));
4839 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
4840 rte_be_to_cpu_32(mask));
4841 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
4842 rte_be_to_cpu_32(value));
4845 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
4846 rte_be_to_cpu_32(mask));
4847 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
4848 rte_be_to_cpu_32(value));
4851 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
4852 rte_be_to_cpu_32(mask));
4853 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
4854 rte_be_to_cpu_32(value));
4857 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
4858 rte_be_to_cpu_32(mask));
4859 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
4860 rte_be_to_cpu_32(value));
4863 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
4864 rte_be_to_cpu_32(mask));
4865 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
4866 rte_be_to_cpu_32(value));
4872 * Add source vport match to the specified matcher.
4874 * @param[in, out] matcher
4876 * @param[in, out] key
4877 * Flow matcher value.
4879 * Source vport value to match
4884 flow_dv_translate_item_source_vport(void *matcher, void *key,
4885 int16_t port, uint16_t mask)
4887 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4888 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4890 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4891 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4895 * Translate port-id item to eswitch match on port-id.
4898 * The devich to configure through.
4899 * @param[in, out] matcher
4901 * @param[in, out] key
4902 * Flow matcher value.
4904 * Flow pattern to translate.
4907 * 0 on success, a negative errno value otherwise.
4910 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4911 void *key, const struct rte_flow_item *item)
4913 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4914 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4915 struct mlx5_priv *priv;
4918 mask = pid_m ? pid_m->id : 0xffff;
4919 id = pid_v ? pid_v->id : dev->data->port_id;
4920 priv = mlx5_port_to_eswitch_info(id);
4923 /* Translate to vport field or to metadata, depending on mode. */
4924 if (priv->vport_meta_mask)
4925 flow_dv_translate_item_meta_vport(matcher, key,
4926 priv->vport_meta_tag,
4927 priv->vport_meta_mask);
4929 flow_dv_translate_item_source_vport(matcher, key,
4930 priv->vport_id, mask);
4935 * Add ICMP6 item to matcher and to the value.
4937 * @param[in, out] matcher
4939 * @param[in, out] key
4940 * Flow matcher value.
4942 * Flow pattern to translate.
4944 * Item is inner pattern.
4947 flow_dv_translate_item_icmp6(void *matcher, void *key,
4948 const struct rte_flow_item *item,
4951 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
4952 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
4955 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4957 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4959 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4961 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4963 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4965 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4967 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4968 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
4972 icmp6_m = &rte_flow_item_icmp6_mask;
4973 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
4974 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
4975 icmp6_v->type & icmp6_m->type);
4976 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
4977 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
4978 icmp6_v->code & icmp6_m->code);
4982 * Add ICMP item to matcher and to the value.
4984 * @param[in, out] matcher
4986 * @param[in, out] key
4987 * Flow matcher value.
4989 * Flow pattern to translate.
4991 * Item is inner pattern.
4994 flow_dv_translate_item_icmp(void *matcher, void *key,
4995 const struct rte_flow_item *item,
4998 const struct rte_flow_item_icmp *icmp_m = item->mask;
4999 const struct rte_flow_item_icmp *icmp_v = item->spec;
5002 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5004 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5006 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5008 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5010 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5012 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5014 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5015 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5019 icmp_m = &rte_flow_item_icmp_mask;
5020 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5021 icmp_m->hdr.icmp_type);
5022 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5023 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5024 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5025 icmp_m->hdr.icmp_code);
5026 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5027 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5030 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5032 #define HEADER_IS_ZERO(match_criteria, headers) \
5033 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
5034 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5037 * Calculate flow matcher enable bitmap.
5039 * @param match_criteria
5040 * Pointer to flow matcher criteria.
5043 * Bitmap of enabled fields.
5046 flow_dv_matcher_enable(uint32_t *match_criteria)
5048 uint8_t match_criteria_enable;
5050 match_criteria_enable =
5051 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5052 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5053 match_criteria_enable |=
5054 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5055 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5056 match_criteria_enable |=
5057 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5058 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5059 match_criteria_enable |=
5060 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5061 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5062 match_criteria_enable |=
5063 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5064 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5065 return match_criteria_enable;
5072 * @param dev[in, out]
5073 * Pointer to rte_eth_dev structure.
5074 * @param[in] table_id
5077 * Direction of the table.
5078 * @param[in] transfer
5079 * E-Switch or NIC flow.
5081 * pointer to error structure.
5084 * Returns tables resource based on the index, NULL in case of failed.
5086 static struct mlx5_flow_tbl_resource *
5087 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5088 uint32_t table_id, uint8_t egress,
5090 struct rte_flow_error *error)
5092 struct mlx5_priv *priv = dev->data->dev_private;
5093 struct mlx5_ibv_shared *sh = priv->sh;
5094 struct mlx5_flow_tbl_resource *tbl;
5096 #ifdef HAVE_MLX5DV_DR
5098 tbl = &sh->fdb_tbl[table_id];
5100 tbl->obj = mlx5_glue->dr_create_flow_tbl
5101 (sh->fdb_domain, table_id);
5102 } else if (egress) {
5103 tbl = &sh->tx_tbl[table_id];
5105 tbl->obj = mlx5_glue->dr_create_flow_tbl
5106 (sh->tx_domain, table_id);
5108 tbl = &sh->rx_tbl[table_id];
5110 tbl->obj = mlx5_glue->dr_create_flow_tbl
5111 (sh->rx_domain, table_id);
5114 rte_flow_error_set(error, ENOMEM,
5115 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5116 NULL, "cannot create table");
5119 rte_atomic32_inc(&tbl->refcnt);
5125 return &sh->fdb_tbl[table_id];
5127 return &sh->tx_tbl[table_id];
5129 return &sh->rx_tbl[table_id];
5134 * Release a flow table.
5137 * Table resource to be released.
5140 * Returns 0 if table was released, else return 1;
5143 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5147 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5148 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5156 * Register the flow matcher.
5158 * @param dev[in, out]
5159 * Pointer to rte_eth_dev structure.
5160 * @param[in, out] matcher
5161 * Pointer to flow matcher.
5162 * @parm[in, out] dev_flow
5163 * Pointer to the dev_flow.
5165 * pointer to error structure.
5168 * 0 on success otherwise -errno and errno is set.
5171 flow_dv_matcher_register(struct rte_eth_dev *dev,
5172 struct mlx5_flow_dv_matcher *matcher,
5173 struct mlx5_flow *dev_flow,
5174 struct rte_flow_error *error)
5176 struct mlx5_priv *priv = dev->data->dev_private;
5177 struct mlx5_ibv_shared *sh = priv->sh;
5178 struct mlx5_flow_dv_matcher *cache_matcher;
5179 struct mlx5dv_flow_matcher_attr dv_attr = {
5180 .type = IBV_FLOW_ATTR_NORMAL,
5181 .match_mask = (void *)&matcher->mask,
5183 struct mlx5_flow_tbl_resource *tbl = NULL;
5185 /* Lookup from cache. */
5186 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5187 if (matcher->crc == cache_matcher->crc &&
5188 matcher->priority == cache_matcher->priority &&
5189 matcher->egress == cache_matcher->egress &&
5190 matcher->group == cache_matcher->group &&
5191 matcher->transfer == cache_matcher->transfer &&
5192 !memcmp((const void *)matcher->mask.buf,
5193 (const void *)cache_matcher->mask.buf,
5194 cache_matcher->mask.size)) {
5196 "priority %hd use %s matcher %p: refcnt %d++",
5197 cache_matcher->priority,
5198 cache_matcher->egress ? "tx" : "rx",
5199 (void *)cache_matcher,
5200 rte_atomic32_read(&cache_matcher->refcnt));
5201 rte_atomic32_inc(&cache_matcher->refcnt);
5202 dev_flow->dv.matcher = cache_matcher;
5206 /* Register new matcher. */
5207 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5209 return rte_flow_error_set(error, ENOMEM,
5210 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5211 "cannot allocate matcher memory");
5212 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5213 matcher->egress, matcher->transfer,
5216 rte_free(cache_matcher);
5217 return rte_flow_error_set(error, ENOMEM,
5218 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5219 NULL, "cannot create table");
5221 *cache_matcher = *matcher;
5222 dv_attr.match_criteria_enable =
5223 flow_dv_matcher_enable(cache_matcher->mask.buf);
5224 dv_attr.priority = matcher->priority;
5225 if (matcher->egress)
5226 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5227 cache_matcher->matcher_object =
5228 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5229 if (!cache_matcher->matcher_object) {
5230 rte_free(cache_matcher);
5231 #ifdef HAVE_MLX5DV_DR
5232 flow_dv_tbl_resource_release(tbl);
5234 return rte_flow_error_set(error, ENOMEM,
5235 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5236 NULL, "cannot create matcher");
5238 rte_atomic32_inc(&cache_matcher->refcnt);
5239 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5240 dev_flow->dv.matcher = cache_matcher;
5241 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5242 cache_matcher->priority,
5243 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5244 rte_atomic32_read(&cache_matcher->refcnt));
5245 rte_atomic32_inc(&tbl->refcnt);
5250 * Find existing tag resource or create and register a new one.
5252 * @param dev[in, out]
5253 * Pointer to rte_eth_dev structure.
5254 * @param[in, out] resource
5255 * Pointer to tag resource.
5256 * @parm[in, out] dev_flow
5257 * Pointer to the dev_flow.
5259 * pointer to error structure.
5262 * 0 on success otherwise -errno and errno is set.
5265 flow_dv_tag_resource_register
5266 (struct rte_eth_dev *dev,
5267 struct mlx5_flow_dv_tag_resource *resource,
5268 struct mlx5_flow *dev_flow,
5269 struct rte_flow_error *error)
5271 struct mlx5_priv *priv = dev->data->dev_private;
5272 struct mlx5_ibv_shared *sh = priv->sh;
5273 struct mlx5_flow_dv_tag_resource *cache_resource;
5275 /* Lookup a matching resource from cache. */
5276 LIST_FOREACH(cache_resource, &sh->tags, next) {
5277 if (resource->tag == cache_resource->tag) {
5278 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5279 (void *)cache_resource,
5280 rte_atomic32_read(&cache_resource->refcnt));
5281 rte_atomic32_inc(&cache_resource->refcnt);
5282 dev_flow->flow->tag_resource = cache_resource;
5286 /* Register new resource. */
5287 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5288 if (!cache_resource)
5289 return rte_flow_error_set(error, ENOMEM,
5290 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5291 "cannot allocate resource memory");
5292 *cache_resource = *resource;
5293 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5295 if (!cache_resource->action) {
5296 rte_free(cache_resource);
5297 return rte_flow_error_set(error, ENOMEM,
5298 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5299 NULL, "cannot create action");
5301 rte_atomic32_init(&cache_resource->refcnt);
5302 rte_atomic32_inc(&cache_resource->refcnt);
5303 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5304 dev_flow->flow->tag_resource = cache_resource;
5305 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5306 (void *)cache_resource,
5307 rte_atomic32_read(&cache_resource->refcnt));
5315 * Pointer to Ethernet device.
5317 * Pointer to mlx5_flow.
5320 * 1 while a reference on it exists, 0 when freed.
5323 flow_dv_tag_release(struct rte_eth_dev *dev,
5324 struct mlx5_flow_dv_tag_resource *tag)
5327 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5328 dev->data->port_id, (void *)tag,
5329 rte_atomic32_read(&tag->refcnt));
5330 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5331 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5332 LIST_REMOVE(tag, next);
5333 DRV_LOG(DEBUG, "port %u tag %p: removed",
5334 dev->data->port_id, (void *)tag);
5342 * Translate port ID action to vport.
5345 * Pointer to rte_eth_dev structure.
5347 * Pointer to the port ID action.
5348 * @param[out] dst_port_id
5349 * The target port ID.
5351 * Pointer to the error structure.
5354 * 0 on success, a negative errno value otherwise and rte_errno is set.
5357 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5358 const struct rte_flow_action *action,
5359 uint32_t *dst_port_id,
5360 struct rte_flow_error *error)
5363 struct mlx5_priv *priv;
5364 const struct rte_flow_action_port_id *conf =
5365 (const struct rte_flow_action_port_id *)action->conf;
5367 port = conf->original ? dev->data->port_id : conf->id;
5368 priv = mlx5_port_to_eswitch_info(port);
5370 return rte_flow_error_set(error, -rte_errno,
5371 RTE_FLOW_ERROR_TYPE_ACTION,
5373 "No eswitch info was found for port");
5374 if (priv->vport_meta_mask)
5375 *dst_port_id = priv->vport_meta_tag;
5377 *dst_port_id = priv->vport_id;
5382 * Add Tx queue matcher
5385 * Pointer to the dev struct.
5386 * @param[in, out] matcher
5388 * @param[in, out] key
5389 * Flow matcher value.
5391 * Flow pattern to translate.
5393 * Item is inner pattern.
5396 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5397 void *matcher, void *key,
5398 const struct rte_flow_item *item)
5400 const struct mlx5_rte_flow_item_tx_queue *queue_m;
5401 const struct mlx5_rte_flow_item_tx_queue *queue_v;
5403 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5405 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5406 struct mlx5_txq_ctrl *txq;
5410 queue_m = (const void *)item->mask;
5413 queue_v = (const void *)item->spec;
5416 txq = mlx5_txq_get(dev, queue_v->queue);
5419 queue = txq->obj->sq->id;
5420 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5421 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5422 queue & queue_m->queue);
5423 mlx5_txq_release(dev, queue_v->queue);
5427 * Fill the flow with DV spec.
5430 * Pointer to rte_eth_dev structure.
5431 * @param[in, out] dev_flow
5432 * Pointer to the sub flow.
5434 * Pointer to the flow attributes.
5436 * Pointer to the list of items.
5437 * @param[in] actions
5438 * Pointer to the list of actions.
5440 * Pointer to the error structure.
5443 * 0 on success, a negative errno value otherwise and rte_errno is set.
5446 flow_dv_translate(struct rte_eth_dev *dev,
5447 struct mlx5_flow *dev_flow,
5448 const struct rte_flow_attr *attr,
5449 const struct rte_flow_item items[],
5450 const struct rte_flow_action actions[],
5451 struct rte_flow_error *error)
5453 struct mlx5_priv *priv = dev->data->dev_private;
5454 struct rte_flow *flow = dev_flow->flow;
5455 uint64_t item_flags = 0;
5456 uint64_t last_item = 0;
5457 uint64_t action_flags = 0;
5458 uint64_t priority = attr->priority;
5459 struct mlx5_flow_dv_matcher matcher = {
5461 .size = sizeof(matcher.mask.buf),
5465 bool actions_end = false;
5466 struct mlx5_flow_dv_modify_hdr_resource res = {
5467 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5468 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5470 union flow_dv_attr flow_attr = { .attr = 0 };
5471 struct mlx5_flow_dv_tag_resource tag_resource;
5472 uint32_t modify_action_position = UINT32_MAX;
5473 void *match_mask = matcher.mask.buf;
5474 void *match_value = dev_flow->dv.value.buf;
5475 uint8_t next_protocol = 0xff;
5476 struct rte_vlan_hdr vlan = { 0 };
5477 bool vlan_inherited = false;
5482 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5486 flow->group = table;
5488 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5489 if (priority == MLX5_FLOW_PRIO_RSVD)
5490 priority = priv->config.flow_prio - 1;
5491 for (; !actions_end ; actions++) {
5492 const struct rte_flow_action_queue *queue;
5493 const struct rte_flow_action_rss *rss;
5494 const struct rte_flow_action *action = actions;
5495 const struct rte_flow_action_count *count = action->conf;
5496 const uint8_t *rss_key;
5497 const struct rte_flow_action_jump *jump_data;
5498 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5499 struct mlx5_flow_tbl_resource *tbl;
5500 uint32_t port_id = 0;
5501 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5502 int action_type = actions->type;
5504 switch (action_type) {
5505 case RTE_FLOW_ACTION_TYPE_VOID:
5507 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5508 if (flow_dv_translate_action_port_id(dev, action,
5511 port_id_resource.port_id = port_id;
5512 if (flow_dv_port_id_action_resource_register
5513 (dev, &port_id_resource, dev_flow, error))
5515 dev_flow->dv.actions[actions_n++] =
5516 dev_flow->dv.port_id_action->action;
5517 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5519 case RTE_FLOW_ACTION_TYPE_FLAG:
5521 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5522 if (!flow->tag_resource)
5523 if (flow_dv_tag_resource_register
5524 (dev, &tag_resource, dev_flow, error))
5526 dev_flow->dv.actions[actions_n++] =
5527 flow->tag_resource->action;
5528 action_flags |= MLX5_FLOW_ACTION_FLAG;
5530 case RTE_FLOW_ACTION_TYPE_MARK:
5531 tag_resource.tag = mlx5_flow_mark_set
5532 (((const struct rte_flow_action_mark *)
5533 (actions->conf))->id);
5534 if (!flow->tag_resource)
5535 if (flow_dv_tag_resource_register
5536 (dev, &tag_resource, dev_flow, error))
5538 dev_flow->dv.actions[actions_n++] =
5539 flow->tag_resource->action;
5540 action_flags |= MLX5_FLOW_ACTION_MARK;
5542 case RTE_FLOW_ACTION_TYPE_DROP:
5543 action_flags |= MLX5_FLOW_ACTION_DROP;
5545 case RTE_FLOW_ACTION_TYPE_QUEUE:
5546 queue = actions->conf;
5547 flow->rss.queue_num = 1;
5548 (*flow->queue)[0] = queue->index;
5549 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5551 case RTE_FLOW_ACTION_TYPE_RSS:
5552 rss = actions->conf;
5554 memcpy((*flow->queue), rss->queue,
5555 rss->queue_num * sizeof(uint16_t));
5556 flow->rss.queue_num = rss->queue_num;
5557 /* NULL RSS key indicates default RSS key. */
5558 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5559 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5560 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5561 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5562 flow->rss.level = rss->level;
5563 action_flags |= MLX5_FLOW_ACTION_RSS;
5565 case RTE_FLOW_ACTION_TYPE_COUNT:
5566 if (!priv->config.devx) {
5567 rte_errno = ENOTSUP;
5570 flow->counter = flow_dv_counter_alloc(dev,
5574 if (flow->counter == NULL)
5576 dev_flow->dv.actions[actions_n++] =
5577 flow->counter->action;
5578 action_flags |= MLX5_FLOW_ACTION_COUNT;
5581 if (rte_errno == ENOTSUP)
5582 return rte_flow_error_set
5584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5586 "count action not supported");
5588 return rte_flow_error_set
5590 RTE_FLOW_ERROR_TYPE_ACTION,
5592 "cannot create counter"
5595 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5596 dev_flow->dv.actions[actions_n++] =
5597 priv->sh->pop_vlan_action;
5598 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5600 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5601 if (!vlan_inherited) {
5602 flow_dev_get_vlan_info_from_items(items, &vlan);
5603 vlan_inherited = true;
5605 vlan.eth_proto = rte_be_to_cpu_16
5606 ((((const struct rte_flow_action_of_push_vlan *)
5607 actions->conf)->ethertype));
5608 if (flow_dv_create_action_push_vlan
5609 (dev, attr, &vlan, dev_flow, error))
5611 dev_flow->dv.actions[actions_n++] =
5612 dev_flow->dv.push_vlan_res->action;
5613 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5614 /* Push VLAN command is also handling this VLAN_VID */
5615 action_flags &= ~MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5617 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5618 if (!vlan_inherited) {
5619 flow_dev_get_vlan_info_from_items(items, &vlan);
5620 vlan_inherited = true;
5623 ((const struct rte_flow_action_of_set_vlan_pcp *)
5624 actions->conf)->vlan_pcp;
5625 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
5626 vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
5627 vlan.vlan_tci |= vlan_tci;
5628 /* Push VLAN command will use this value */
5630 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5631 if (!vlan_inherited) {
5632 flow_dev_get_vlan_info_from_items(items, &vlan);
5633 vlan_inherited = true;
5635 vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
5636 vlan.vlan_tci |= rte_be_to_cpu_16
5637 (((const struct rte_flow_action_of_set_vlan_vid *)
5638 actions->conf)->vlan_vid);
5639 /* Push VLAN command will use this value */
5640 if (mlx5_flow_find_action
5642 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
5644 /* If no VLAN push - this is a modify header action */
5645 if (flow_dv_convert_action_modify_vlan_vid
5646 (&res, actions, error))
5648 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5650 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5651 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5652 if (flow_dv_create_action_l2_encap(dev, actions,
5657 dev_flow->dv.actions[actions_n++] =
5658 dev_flow->dv.encap_decap->verbs_action;
5659 action_flags |= actions->type ==
5660 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5661 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5662 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5664 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5665 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5666 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5670 dev_flow->dv.actions[actions_n++] =
5671 dev_flow->dv.encap_decap->verbs_action;
5672 action_flags |= actions->type ==
5673 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5674 MLX5_FLOW_ACTION_VXLAN_DECAP :
5675 MLX5_FLOW_ACTION_NVGRE_DECAP;
5677 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5678 /* Handle encap with preceding decap. */
5679 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5680 if (flow_dv_create_action_raw_encap
5681 (dev, actions, dev_flow, attr, error))
5683 dev_flow->dv.actions[actions_n++] =
5684 dev_flow->dv.encap_decap->verbs_action;
5686 /* Handle encap without preceding decap. */
5687 if (flow_dv_create_action_l2_encap
5688 (dev, actions, dev_flow, attr->transfer,
5691 dev_flow->dv.actions[actions_n++] =
5692 dev_flow->dv.encap_decap->verbs_action;
5694 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5696 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5697 /* Check if this decap is followed by encap. */
5698 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5699 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5702 /* Handle decap only if it isn't followed by encap. */
5703 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5704 if (flow_dv_create_action_l2_decap
5705 (dev, dev_flow, attr->transfer, error))
5707 dev_flow->dv.actions[actions_n++] =
5708 dev_flow->dv.encap_decap->verbs_action;
5710 /* If decap is followed by encap, handle it at encap. */
5711 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5713 case RTE_FLOW_ACTION_TYPE_JUMP:
5714 jump_data = action->conf;
5715 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5716 jump_data->group, &table,
5720 tbl = flow_dv_tbl_resource_get(dev, table,
5722 attr->transfer, error);
5724 return rte_flow_error_set
5726 RTE_FLOW_ERROR_TYPE_ACTION,
5728 "cannot create jump action.");
5729 jump_tbl_resource.tbl = tbl;
5730 if (flow_dv_jump_tbl_resource_register
5731 (dev, &jump_tbl_resource, dev_flow, error)) {
5732 flow_dv_tbl_resource_release(tbl);
5733 return rte_flow_error_set
5735 RTE_FLOW_ERROR_TYPE_ACTION,
5737 "cannot create jump action.");
5739 dev_flow->dv.actions[actions_n++] =
5740 dev_flow->dv.jump->action;
5741 action_flags |= MLX5_FLOW_ACTION_JUMP;
5743 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5744 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5745 if (flow_dv_convert_action_modify_mac(&res, actions,
5748 action_flags |= actions->type ==
5749 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5750 MLX5_FLOW_ACTION_SET_MAC_SRC :
5751 MLX5_FLOW_ACTION_SET_MAC_DST;
5753 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5754 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5755 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5758 action_flags |= actions->type ==
5759 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5760 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5761 MLX5_FLOW_ACTION_SET_IPV4_DST;
5763 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5764 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5765 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5768 action_flags |= actions->type ==
5769 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5770 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5771 MLX5_FLOW_ACTION_SET_IPV6_DST;
5773 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5774 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5775 if (flow_dv_convert_action_modify_tp(&res, actions,
5779 action_flags |= actions->type ==
5780 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5781 MLX5_FLOW_ACTION_SET_TP_SRC :
5782 MLX5_FLOW_ACTION_SET_TP_DST;
5784 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5785 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5789 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5791 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5792 if (flow_dv_convert_action_modify_ttl(&res, actions,
5796 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5798 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5799 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5800 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5803 action_flags |= actions->type ==
5804 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5805 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5806 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5809 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5810 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5811 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5814 action_flags |= actions->type ==
5815 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5816 MLX5_FLOW_ACTION_INC_TCP_ACK :
5817 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5819 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5820 if (flow_dv_convert_action_set_reg(&res, actions,
5823 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5825 case RTE_FLOW_ACTION_TYPE_END:
5827 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5828 /* create modify action if needed. */
5829 if (flow_dv_modify_hdr_resource_register
5834 dev_flow->dv.actions[modify_action_position] =
5835 dev_flow->dv.modify_hdr->verbs_action;
5841 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5842 modify_action_position == UINT32_MAX)
5843 modify_action_position = actions_n++;
5845 dev_flow->dv.actions_n = actions_n;
5846 dev_flow->actions = action_flags;
5847 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5848 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5849 int item_type = items->type;
5851 switch (item_type) {
5852 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5853 flow_dv_translate_item_port_id(dev, match_mask,
5854 match_value, items);
5855 last_item = MLX5_FLOW_ITEM_PORT_ID;
5857 case RTE_FLOW_ITEM_TYPE_ETH:
5858 flow_dv_translate_item_eth(match_mask, match_value,
5860 matcher.priority = MLX5_PRIORITY_MAP_L2;
5861 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5862 MLX5_FLOW_LAYER_OUTER_L2;
5864 case RTE_FLOW_ITEM_TYPE_VLAN:
5865 flow_dv_translate_item_vlan(dev_flow,
5866 match_mask, match_value,
5868 matcher.priority = MLX5_PRIORITY_MAP_L2;
5869 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5870 MLX5_FLOW_LAYER_INNER_VLAN) :
5871 (MLX5_FLOW_LAYER_OUTER_L2 |
5872 MLX5_FLOW_LAYER_OUTER_VLAN);
5874 case RTE_FLOW_ITEM_TYPE_IPV4:
5875 mlx5_flow_tunnel_ip_check(items, next_protocol,
5876 &item_flags, &tunnel);
5877 flow_dv_translate_item_ipv4(match_mask, match_value,
5878 items, tunnel, flow->group);
5879 matcher.priority = MLX5_PRIORITY_MAP_L3;
5880 dev_flow->dv.hash_fields |=
5881 mlx5_flow_hashfields_adjust
5883 MLX5_IPV4_LAYER_TYPES,
5884 MLX5_IPV4_IBV_RX_HASH);
5885 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5886 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5887 if (items->mask != NULL &&
5888 ((const struct rte_flow_item_ipv4 *)
5889 items->mask)->hdr.next_proto_id) {
5891 ((const struct rte_flow_item_ipv4 *)
5892 (items->spec))->hdr.next_proto_id;
5894 ((const struct rte_flow_item_ipv4 *)
5895 (items->mask))->hdr.next_proto_id;
5897 /* Reset for inner layer. */
5898 next_protocol = 0xff;
5901 case RTE_FLOW_ITEM_TYPE_IPV6:
5902 mlx5_flow_tunnel_ip_check(items, next_protocol,
5903 &item_flags, &tunnel);
5904 flow_dv_translate_item_ipv6(match_mask, match_value,
5905 items, tunnel, flow->group);
5906 matcher.priority = MLX5_PRIORITY_MAP_L3;
5907 dev_flow->dv.hash_fields |=
5908 mlx5_flow_hashfields_adjust
5910 MLX5_IPV6_LAYER_TYPES,
5911 MLX5_IPV6_IBV_RX_HASH);
5912 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5913 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5914 if (items->mask != NULL &&
5915 ((const struct rte_flow_item_ipv6 *)
5916 items->mask)->hdr.proto) {
5918 ((const struct rte_flow_item_ipv6 *)
5919 items->spec)->hdr.proto;
5921 ((const struct rte_flow_item_ipv6 *)
5922 items->mask)->hdr.proto;
5924 /* Reset for inner layer. */
5925 next_protocol = 0xff;
5928 case RTE_FLOW_ITEM_TYPE_TCP:
5929 flow_dv_translate_item_tcp(match_mask, match_value,
5931 matcher.priority = MLX5_PRIORITY_MAP_L4;
5932 dev_flow->dv.hash_fields |=
5933 mlx5_flow_hashfields_adjust
5934 (dev_flow, tunnel, ETH_RSS_TCP,
5935 IBV_RX_HASH_SRC_PORT_TCP |
5936 IBV_RX_HASH_DST_PORT_TCP);
5937 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5938 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5940 case RTE_FLOW_ITEM_TYPE_UDP:
5941 flow_dv_translate_item_udp(match_mask, match_value,
5943 matcher.priority = MLX5_PRIORITY_MAP_L4;
5944 dev_flow->dv.hash_fields |=
5945 mlx5_flow_hashfields_adjust
5946 (dev_flow, tunnel, ETH_RSS_UDP,
5947 IBV_RX_HASH_SRC_PORT_UDP |
5948 IBV_RX_HASH_DST_PORT_UDP);
5949 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5950 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5952 case RTE_FLOW_ITEM_TYPE_GRE:
5953 flow_dv_translate_item_gre(match_mask, match_value,
5955 last_item = MLX5_FLOW_LAYER_GRE;
5957 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5958 flow_dv_translate_item_gre_key(match_mask,
5959 match_value, items);
5960 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5962 case RTE_FLOW_ITEM_TYPE_NVGRE:
5963 flow_dv_translate_item_nvgre(match_mask, match_value,
5965 last_item = MLX5_FLOW_LAYER_GRE;
5967 case RTE_FLOW_ITEM_TYPE_VXLAN:
5968 flow_dv_translate_item_vxlan(match_mask, match_value,
5970 last_item = MLX5_FLOW_LAYER_VXLAN;
5972 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5973 flow_dv_translate_item_vxlan(match_mask, match_value,
5975 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5977 case RTE_FLOW_ITEM_TYPE_GENEVE:
5978 flow_dv_translate_item_geneve(match_mask, match_value,
5980 last_item = MLX5_FLOW_LAYER_GENEVE;
5982 case RTE_FLOW_ITEM_TYPE_MPLS:
5983 flow_dv_translate_item_mpls(match_mask, match_value,
5984 items, last_item, tunnel);
5985 last_item = MLX5_FLOW_LAYER_MPLS;
5987 case RTE_FLOW_ITEM_TYPE_META:
5988 flow_dv_translate_item_meta(match_mask, match_value,
5990 last_item = MLX5_FLOW_ITEM_METADATA;
5992 case RTE_FLOW_ITEM_TYPE_ICMP:
5993 flow_dv_translate_item_icmp(match_mask, match_value,
5995 last_item = MLX5_FLOW_LAYER_ICMP;
5997 case RTE_FLOW_ITEM_TYPE_ICMP6:
5998 flow_dv_translate_item_icmp6(match_mask, match_value,
6000 last_item = MLX5_FLOW_LAYER_ICMP6;
6002 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6003 flow_dv_translate_item_tag(match_mask, match_value,
6005 last_item = MLX5_FLOW_ITEM_TAG;
6007 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6008 flow_dv_translate_item_tx_queue(dev, match_mask,
6011 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6016 item_flags |= last_item;
6019 * In case of ingress traffic when E-Switch mode is enabled,
6020 * we have two cases where we need to set the source port manually.
6021 * The first one, is in case of Nic steering rule, and the second is
6022 * E-Switch rule where no port_id item was found. In both cases
6023 * the source port is set according the current port in use.
6025 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6026 (priv->representor || priv->master)) {
6027 if (flow_dv_translate_item_port_id(dev, match_mask,
6031 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6032 dev_flow->dv.value.buf));
6033 dev_flow->layers = item_flags;
6034 /* Register matcher. */
6035 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6037 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6039 matcher.egress = attr->egress;
6040 matcher.group = flow->group;
6041 matcher.transfer = attr->transfer;
6042 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6048 * Apply the flow to the NIC.
6051 * Pointer to the Ethernet device structure.
6052 * @param[in, out] flow
6053 * Pointer to flow structure.
6055 * Pointer to error structure.
6058 * 0 on success, a negative errno value otherwise and rte_errno is set.
6061 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6062 struct rte_flow_error *error)
6064 struct mlx5_flow_dv *dv;
6065 struct mlx5_flow *dev_flow;
6066 struct mlx5_priv *priv = dev->data->dev_private;
6070 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6073 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6074 if (flow->transfer) {
6075 dv->actions[n++] = priv->sh->esw_drop_action;
6077 dv->hrxq = mlx5_hrxq_drop_new(dev);
6081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6083 "cannot get drop hash queue");
6086 dv->actions[n++] = dv->hrxq->action;
6088 } else if (dev_flow->actions &
6089 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6090 struct mlx5_hrxq *hrxq;
6092 hrxq = mlx5_hrxq_get(dev, flow->key,
6093 MLX5_RSS_HASH_KEY_LEN,
6096 flow->rss.queue_num);
6098 hrxq = mlx5_hrxq_new
6099 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6100 dv->hash_fields, (*flow->queue),
6101 flow->rss.queue_num,
6102 !!(dev_flow->layers &
6103 MLX5_FLOW_LAYER_TUNNEL));
6108 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6109 "cannot get hash queue");
6113 dv->actions[n++] = dv->hrxq->action;
6116 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6117 (void *)&dv->value, n,
6120 rte_flow_error_set(error, errno,
6121 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6123 "hardware refuses to create flow");
6126 if (priv->vmwa_context &&
6127 dev_flow->dv.vf_vlan.tag &&
6128 !dev_flow->dv.vf_vlan.created) {
6130 * The rule contains the VLAN pattern.
6131 * For VF we are going to create VLAN
6132 * interface to make hypervisor set correct
6133 * e-Switch vport context.
6135 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6140 err = rte_errno; /* Save rte_errno before cleanup. */
6141 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6142 struct mlx5_flow_dv *dv = &dev_flow->dv;
6144 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6145 mlx5_hrxq_drop_release(dev);
6147 mlx5_hrxq_release(dev, dv->hrxq);
6150 if (dev_flow->dv.vf_vlan.tag &&
6151 dev_flow->dv.vf_vlan.created)
6152 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6154 rte_errno = err; /* Restore rte_errno. */
6159 * Release the flow matcher.
6162 * Pointer to Ethernet device.
6164 * Pointer to mlx5_flow.
6167 * 1 while a reference on it exists, 0 when freed.
6170 flow_dv_matcher_release(struct rte_eth_dev *dev,
6171 struct mlx5_flow *flow)
6173 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6174 struct mlx5_priv *priv = dev->data->dev_private;
6175 struct mlx5_ibv_shared *sh = priv->sh;
6176 struct mlx5_flow_tbl_resource *tbl;
6178 assert(matcher->matcher_object);
6179 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6180 dev->data->port_id, (void *)matcher,
6181 rte_atomic32_read(&matcher->refcnt));
6182 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6183 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6184 (matcher->matcher_object));
6185 LIST_REMOVE(matcher, next);
6186 if (matcher->egress)
6187 tbl = &sh->tx_tbl[matcher->group];
6189 tbl = &sh->rx_tbl[matcher->group];
6190 flow_dv_tbl_resource_release(tbl);
6192 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6193 dev->data->port_id, (void *)matcher);
6200 * Release an encap/decap resource.
6203 * Pointer to mlx5_flow.
6206 * 1 while a reference on it exists, 0 when freed.
6209 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6211 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6212 flow->dv.encap_decap;
6214 assert(cache_resource->verbs_action);
6215 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6216 (void *)cache_resource,
6217 rte_atomic32_read(&cache_resource->refcnt));
6218 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6219 claim_zero(mlx5_glue->destroy_flow_action
6220 (cache_resource->verbs_action));
6221 LIST_REMOVE(cache_resource, next);
6222 rte_free(cache_resource);
6223 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6224 (void *)cache_resource);
6231 * Release an jump to table action resource.
6234 * Pointer to mlx5_flow.
6237 * 1 while a reference on it exists, 0 when freed.
6240 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6242 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6245 assert(cache_resource->action);
6246 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6247 (void *)cache_resource,
6248 rte_atomic32_read(&cache_resource->refcnt));
6249 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6250 claim_zero(mlx5_glue->destroy_flow_action
6251 (cache_resource->action));
6252 LIST_REMOVE(cache_resource, next);
6253 flow_dv_tbl_resource_release(cache_resource->tbl);
6254 rte_free(cache_resource);
6255 DRV_LOG(DEBUG, "jump table resource %p: removed",
6256 (void *)cache_resource);
6263 * Release a modify-header resource.
6266 * Pointer to mlx5_flow.
6269 * 1 while a reference on it exists, 0 when freed.
6272 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6274 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6275 flow->dv.modify_hdr;
6277 assert(cache_resource->verbs_action);
6278 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6279 (void *)cache_resource,
6280 rte_atomic32_read(&cache_resource->refcnt));
6281 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6282 claim_zero(mlx5_glue->destroy_flow_action
6283 (cache_resource->verbs_action));
6284 LIST_REMOVE(cache_resource, next);
6285 rte_free(cache_resource);
6286 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6287 (void *)cache_resource);
6294 * Release port ID action resource.
6297 * Pointer to mlx5_flow.
6300 * 1 while a reference on it exists, 0 when freed.
6303 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6305 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6306 flow->dv.port_id_action;
6308 assert(cache_resource->action);
6309 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6310 (void *)cache_resource,
6311 rte_atomic32_read(&cache_resource->refcnt));
6312 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6313 claim_zero(mlx5_glue->destroy_flow_action
6314 (cache_resource->action));
6315 LIST_REMOVE(cache_resource, next);
6316 rte_free(cache_resource);
6317 DRV_LOG(DEBUG, "port id action resource %p: removed",
6318 (void *)cache_resource);
6325 * Release push vlan action resource.
6328 * Pointer to mlx5_flow.
6331 * 1 while a reference on it exists, 0 when freed.
6334 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6336 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6337 flow->dv.push_vlan_res;
6339 assert(cache_resource->action);
6340 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6341 (void *)cache_resource,
6342 rte_atomic32_read(&cache_resource->refcnt));
6343 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6344 claim_zero(mlx5_glue->destroy_flow_action
6345 (cache_resource->action));
6346 LIST_REMOVE(cache_resource, next);
6347 rte_free(cache_resource);
6348 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6349 (void *)cache_resource);
6356 * Remove the flow from the NIC but keeps it in memory.
6359 * Pointer to Ethernet device.
6360 * @param[in, out] flow
6361 * Pointer to flow structure.
6364 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6366 struct mlx5_flow_dv *dv;
6367 struct mlx5_flow *dev_flow;
6371 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6374 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6378 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6379 mlx5_hrxq_drop_release(dev);
6381 mlx5_hrxq_release(dev, dv->hrxq);
6384 if (dev_flow->dv.vf_vlan.tag &&
6385 dev_flow->dv.vf_vlan.created)
6386 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6391 * Remove the flow from the NIC and the memory.
6394 * Pointer to the Ethernet device structure.
6395 * @param[in, out] flow
6396 * Pointer to flow structure.
6399 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6401 struct mlx5_flow *dev_flow;
6405 flow_dv_remove(dev, flow);
6406 if (flow->counter) {
6407 flow_dv_counter_release(dev, flow->counter);
6408 flow->counter = NULL;
6410 if (flow->tag_resource) {
6411 flow_dv_tag_release(dev, flow->tag_resource);
6412 flow->tag_resource = NULL;
6414 while (!LIST_EMPTY(&flow->dev_flows)) {
6415 dev_flow = LIST_FIRST(&flow->dev_flows);
6416 LIST_REMOVE(dev_flow, next);
6417 if (dev_flow->dv.matcher)
6418 flow_dv_matcher_release(dev, dev_flow);
6419 if (dev_flow->dv.encap_decap)
6420 flow_dv_encap_decap_resource_release(dev_flow);
6421 if (dev_flow->dv.modify_hdr)
6422 flow_dv_modify_hdr_resource_release(dev_flow);
6423 if (dev_flow->dv.jump)
6424 flow_dv_jump_tbl_resource_release(dev_flow);
6425 if (dev_flow->dv.port_id_action)
6426 flow_dv_port_id_action_resource_release(dev_flow);
6427 if (dev_flow->dv.push_vlan_res)
6428 flow_dv_push_vlan_action_resource_release(dev_flow);
6434 * Query a dv flow rule for its statistics via devx.
6437 * Pointer to Ethernet device.
6439 * Pointer to the sub flow.
6441 * data retrieved by the query.
6443 * Perform verbose error reporting if not NULL.
6446 * 0 on success, a negative errno value otherwise and rte_errno is set.
6449 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6450 void *data, struct rte_flow_error *error)
6452 struct mlx5_priv *priv = dev->data->dev_private;
6453 struct rte_flow_query_count *qc = data;
6455 if (!priv->config.devx)
6456 return rte_flow_error_set(error, ENOTSUP,
6457 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6459 "counters are not supported");
6460 if (flow->counter) {
6461 uint64_t pkts, bytes;
6462 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6466 return rte_flow_error_set(error, -err,
6467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6468 NULL, "cannot read counters");
6471 qc->hits = pkts - flow->counter->hits;
6472 qc->bytes = bytes - flow->counter->bytes;
6474 flow->counter->hits = pkts;
6475 flow->counter->bytes = bytes;
6479 return rte_flow_error_set(error, EINVAL,
6480 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6482 "counters are not available");
6488 * @see rte_flow_query()
6492 flow_dv_query(struct rte_eth_dev *dev,
6493 struct rte_flow *flow __rte_unused,
6494 const struct rte_flow_action *actions __rte_unused,
6495 void *data __rte_unused,
6496 struct rte_flow_error *error __rte_unused)
6500 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6501 switch (actions->type) {
6502 case RTE_FLOW_ACTION_TYPE_VOID:
6504 case RTE_FLOW_ACTION_TYPE_COUNT:
6505 ret = flow_dv_query_count(dev, flow, data, error);
6508 return rte_flow_error_set(error, ENOTSUP,
6509 RTE_FLOW_ERROR_TYPE_ACTION,
6511 "action not supported");
6518 * Mutex-protected thunk to flow_dv_translate().
6521 flow_d_translate(struct rte_eth_dev *dev,
6522 struct mlx5_flow *dev_flow,
6523 const struct rte_flow_attr *attr,
6524 const struct rte_flow_item items[],
6525 const struct rte_flow_action actions[],
6526 struct rte_flow_error *error)
6530 flow_d_shared_lock(dev);
6531 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6532 flow_d_shared_unlock(dev);
6537 * Mutex-protected thunk to flow_dv_apply().
6540 flow_d_apply(struct rte_eth_dev *dev,
6541 struct rte_flow *flow,
6542 struct rte_flow_error *error)
6546 flow_d_shared_lock(dev);
6547 ret = flow_dv_apply(dev, flow, error);
6548 flow_d_shared_unlock(dev);
6553 * Mutex-protected thunk to flow_dv_remove().
6556 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6558 flow_d_shared_lock(dev);
6559 flow_dv_remove(dev, flow);
6560 flow_d_shared_unlock(dev);
6564 * Mutex-protected thunk to flow_dv_destroy().
6567 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6569 flow_d_shared_lock(dev);
6570 flow_dv_destroy(dev, flow);
6571 flow_d_shared_unlock(dev);
6574 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6575 .validate = flow_dv_validate,
6576 .prepare = flow_dv_prepare,
6577 .translate = flow_d_translate,
6578 .apply = flow_d_apply,
6579 .remove = flow_d_remove,
6580 .destroy = flow_d_destroy,
6581 .query = flow_dv_query,
6584 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */