1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
37 #include "rte_pmd_mlx5.h"
39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 /* VLAN header definitions */
56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
76 struct mlx5_flow_tbl_resource *tbl);
79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
80 uint32_t encap_decap_idx);
83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
93 * Initialize flow attributes structure according to flow items' types.
95 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
96 * mode. For tunnel mode, the items to be modified are the outermost ones.
99 * Pointer to item specification.
101 * Pointer to flow attributes structure.
102 * @param[in] dev_flow
103 * Pointer to the sub flow.
104 * @param[in] tunnel_decap
105 * Whether action is after tunnel decapsulation.
108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
109 struct mlx5_flow *dev_flow, bool tunnel_decap)
111 uint64_t layers = dev_flow->handle->layers;
114 * If layers is already initialized, it means this dev_flow is the
115 * suffix flow, the layers flags is set by the prefix flow. Need to
116 * use the layer flags from prefix flow as the suffix flow may not
117 * have the user defined items as the flow is split.
120 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
122 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
124 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
126 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
131 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
132 uint8_t next_protocol = 0xff;
133 switch (item->type) {
134 case RTE_FLOW_ITEM_TYPE_GRE:
135 case RTE_FLOW_ITEM_TYPE_NVGRE:
136 case RTE_FLOW_ITEM_TYPE_VXLAN:
137 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
138 case RTE_FLOW_ITEM_TYPE_GENEVE:
139 case RTE_FLOW_ITEM_TYPE_MPLS:
143 case RTE_FLOW_ITEM_TYPE_IPV4:
146 if (item->mask != NULL &&
147 ((const struct rte_flow_item_ipv4 *)
148 item->mask)->hdr.next_proto_id)
150 ((const struct rte_flow_item_ipv4 *)
151 (item->spec))->hdr.next_proto_id &
152 ((const struct rte_flow_item_ipv4 *)
153 (item->mask))->hdr.next_proto_id;
154 if ((next_protocol == IPPROTO_IPIP ||
155 next_protocol == IPPROTO_IPV6) && tunnel_decap)
158 case RTE_FLOW_ITEM_TYPE_IPV6:
161 if (item->mask != NULL &&
162 ((const struct rte_flow_item_ipv6 *)
163 item->mask)->hdr.proto)
165 ((const struct rte_flow_item_ipv6 *)
166 (item->spec))->hdr.proto &
167 ((const struct rte_flow_item_ipv6 *)
168 (item->mask))->hdr.proto;
169 if ((next_protocol == IPPROTO_IPIP ||
170 next_protocol == IPPROTO_IPV6) && tunnel_decap)
173 case RTE_FLOW_ITEM_TYPE_UDP:
177 case RTE_FLOW_ITEM_TYPE_TCP:
189 * Convert rte_mtr_color to mlx5 color.
198 rte_col_2_mlx5_col(enum rte_color rcol)
201 case RTE_COLOR_GREEN:
202 return MLX5_FLOW_COLOR_GREEN;
203 case RTE_COLOR_YELLOW:
204 return MLX5_FLOW_COLOR_YELLOW;
206 return MLX5_FLOW_COLOR_RED;
210 return MLX5_FLOW_COLOR_UNDEFINED;
213 struct field_modify_info {
214 uint32_t size; /* Size of field in protocol header, in bytes. */
215 uint32_t offset; /* Offset of field in protocol header, in bytes. */
216 enum mlx5_modification_field id;
219 struct field_modify_info modify_eth[] = {
220 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
221 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
222 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
223 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
227 struct field_modify_info modify_vlan_out_first_vid[] = {
228 /* Size in bits !!! */
229 {12, 0, MLX5_MODI_OUT_FIRST_VID},
233 struct field_modify_info modify_ipv4[] = {
234 {1, 1, MLX5_MODI_OUT_IP_DSCP},
235 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
236 {4, 12, MLX5_MODI_OUT_SIPV4},
237 {4, 16, MLX5_MODI_OUT_DIPV4},
241 struct field_modify_info modify_ipv6[] = {
242 {1, 0, MLX5_MODI_OUT_IP_DSCP},
243 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
244 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
245 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
246 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
247 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
248 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
249 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
250 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
251 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
255 struct field_modify_info modify_udp[] = {
256 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
257 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
261 struct field_modify_info modify_tcp[] = {
262 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
263 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
264 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
265 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
271 uint8_t next_protocol, uint64_t *item_flags,
274 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
275 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
276 if (next_protocol == IPPROTO_IPIP) {
277 *item_flags |= MLX5_FLOW_LAYER_IPIP;
280 if (next_protocol == IPPROTO_IPV6) {
281 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
286 /* Update VLAN's VID/PCP based on input rte_flow_action.
289 * Pointer to struct rte_flow_action.
291 * Pointer to struct rte_vlan_hdr.
294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
295 struct rte_vlan_hdr *vlan)
298 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
300 ((const struct rte_flow_action_of_set_vlan_pcp *)
301 action->conf)->vlan_pcp;
302 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
303 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
304 vlan->vlan_tci |= vlan_tci;
305 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
306 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
307 vlan->vlan_tci |= rte_be_to_cpu_16
308 (((const struct rte_flow_action_of_set_vlan_vid *)
309 action->conf)->vlan_vid);
314 * Fetch 1, 2, 3 or 4 byte field from the byte array
315 * and return as unsigned integer in host-endian format.
318 * Pointer to data array.
320 * Size of field to extract.
323 * converted field in host endian format.
325 static inline uint32_t
326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
335 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
339 ret = (ret << 8) | *(data + sizeof(uint16_t));
342 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
353 * Convert modify-header action to DV specification.
355 * Data length of each action is determined by provided field description
356 * and the item mask. Data bit offset and width of each action is determined
357 * by provided item mask.
360 * Pointer to item specification.
362 * Pointer to field modification information.
363 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
365 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
367 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
368 * Negative offset value sets the same offset as source offset.
369 * size field is ignored, value is taken from source field.
370 * @param[in,out] resource
371 * Pointer to the modify-header resource.
373 * Type of modification.
375 * Pointer to the error structure.
378 * 0 on success, a negative errno value otherwise and rte_errno is set.
381 flow_dv_convert_modify_action(struct rte_flow_item *item,
382 struct field_modify_info *field,
383 struct field_modify_info *dcopy,
384 struct mlx5_flow_dv_modify_hdr_resource *resource,
385 uint32_t type, struct rte_flow_error *error)
387 uint32_t i = resource->actions_num;
388 struct mlx5_modification_cmd *actions = resource->actions;
391 * The item and mask are provided in big-endian format.
392 * The fields should be presented as in big-endian format either.
393 * Mask must be always present, it defines the actual field width.
395 MLX5_ASSERT(item->mask);
396 MLX5_ASSERT(field->size);
403 if (i >= MLX5_MAX_MODIFY_NUM)
404 return rte_flow_error_set(error, EINVAL,
405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
406 "too many items to modify");
407 /* Fetch variable byte size mask from the array. */
408 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
409 field->offset, field->size);
414 /* Deduce actual data width in bits from mask value. */
415 off_b = rte_bsf32(mask);
416 size_b = sizeof(uint32_t) * CHAR_BIT -
417 off_b - __builtin_clz(mask);
419 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
420 actions[i] = (struct mlx5_modification_cmd) {
426 /* Convert entire record to expected big-endian format. */
427 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
428 if (type == MLX5_MODIFICATION_TYPE_COPY) {
430 actions[i].dst_field = dcopy->id;
431 actions[i].dst_offset =
432 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
433 /* Convert entire record to big-endian format. */
434 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
437 MLX5_ASSERT(item->spec);
438 data = flow_dv_fetch_field((const uint8_t *)item->spec +
439 field->offset, field->size);
440 /* Shift out the trailing masked bits from data. */
441 data = (data & mask) >> off_b;
442 actions[i].data1 = rte_cpu_to_be_32(data);
446 } while (field->size);
447 if (resource->actions_num == i)
448 return rte_flow_error_set(error, EINVAL,
449 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
450 "invalid modification flow item");
451 resource->actions_num = i;
456 * Convert modify-header set IPv4 address action to DV specification.
458 * @param[in,out] resource
459 * Pointer to the modify-header resource.
461 * Pointer to action specification.
463 * Pointer to the error structure.
466 * 0 on success, a negative errno value otherwise and rte_errno is set.
469 flow_dv_convert_action_modify_ipv4
470 (struct mlx5_flow_dv_modify_hdr_resource *resource,
471 const struct rte_flow_action *action,
472 struct rte_flow_error *error)
474 const struct rte_flow_action_set_ipv4 *conf =
475 (const struct rte_flow_action_set_ipv4 *)(action->conf);
476 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
477 struct rte_flow_item_ipv4 ipv4;
478 struct rte_flow_item_ipv4 ipv4_mask;
480 memset(&ipv4, 0, sizeof(ipv4));
481 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
482 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
483 ipv4.hdr.src_addr = conf->ipv4_addr;
484 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
486 ipv4.hdr.dst_addr = conf->ipv4_addr;
487 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
490 item.mask = &ipv4_mask;
491 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
492 MLX5_MODIFICATION_TYPE_SET, error);
496 * Convert modify-header set IPv6 address action to DV specification.
498 * @param[in,out] resource
499 * Pointer to the modify-header resource.
501 * Pointer to action specification.
503 * Pointer to the error structure.
506 * 0 on success, a negative errno value otherwise and rte_errno is set.
509 flow_dv_convert_action_modify_ipv6
510 (struct mlx5_flow_dv_modify_hdr_resource *resource,
511 const struct rte_flow_action *action,
512 struct rte_flow_error *error)
514 const struct rte_flow_action_set_ipv6 *conf =
515 (const struct rte_flow_action_set_ipv6 *)(action->conf);
516 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
517 struct rte_flow_item_ipv6 ipv6;
518 struct rte_flow_item_ipv6 ipv6_mask;
520 memset(&ipv6, 0, sizeof(ipv6));
521 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
522 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
523 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
524 sizeof(ipv6.hdr.src_addr));
525 memcpy(&ipv6_mask.hdr.src_addr,
526 &rte_flow_item_ipv6_mask.hdr.src_addr,
527 sizeof(ipv6.hdr.src_addr));
529 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
530 sizeof(ipv6.hdr.dst_addr));
531 memcpy(&ipv6_mask.hdr.dst_addr,
532 &rte_flow_item_ipv6_mask.hdr.dst_addr,
533 sizeof(ipv6.hdr.dst_addr));
536 item.mask = &ipv6_mask;
537 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
538 MLX5_MODIFICATION_TYPE_SET, error);
542 * Convert modify-header set MAC address action to DV specification.
544 * @param[in,out] resource
545 * Pointer to the modify-header resource.
547 * Pointer to action specification.
549 * Pointer to the error structure.
552 * 0 on success, a negative errno value otherwise and rte_errno is set.
555 flow_dv_convert_action_modify_mac
556 (struct mlx5_flow_dv_modify_hdr_resource *resource,
557 const struct rte_flow_action *action,
558 struct rte_flow_error *error)
560 const struct rte_flow_action_set_mac *conf =
561 (const struct rte_flow_action_set_mac *)(action->conf);
562 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
563 struct rte_flow_item_eth eth;
564 struct rte_flow_item_eth eth_mask;
566 memset(ð, 0, sizeof(eth));
567 memset(ð_mask, 0, sizeof(eth_mask));
568 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
569 memcpy(ð.src.addr_bytes, &conf->mac_addr,
570 sizeof(eth.src.addr_bytes));
571 memcpy(ð_mask.src.addr_bytes,
572 &rte_flow_item_eth_mask.src.addr_bytes,
573 sizeof(eth_mask.src.addr_bytes));
575 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
576 sizeof(eth.dst.addr_bytes));
577 memcpy(ð_mask.dst.addr_bytes,
578 &rte_flow_item_eth_mask.dst.addr_bytes,
579 sizeof(eth_mask.dst.addr_bytes));
582 item.mask = ð_mask;
583 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
584 MLX5_MODIFICATION_TYPE_SET, error);
588 * Convert modify-header set VLAN VID action to DV specification.
590 * @param[in,out] resource
591 * Pointer to the modify-header resource.
593 * Pointer to action specification.
595 * Pointer to the error structure.
598 * 0 on success, a negative errno value otherwise and rte_errno is set.
601 flow_dv_convert_action_modify_vlan_vid
602 (struct mlx5_flow_dv_modify_hdr_resource *resource,
603 const struct rte_flow_action *action,
604 struct rte_flow_error *error)
606 const struct rte_flow_action_of_set_vlan_vid *conf =
607 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
608 int i = resource->actions_num;
609 struct mlx5_modification_cmd *actions = resource->actions;
610 struct field_modify_info *field = modify_vlan_out_first_vid;
612 if (i >= MLX5_MAX_MODIFY_NUM)
613 return rte_flow_error_set(error, EINVAL,
614 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
615 "too many items to modify");
616 actions[i] = (struct mlx5_modification_cmd) {
617 .action_type = MLX5_MODIFICATION_TYPE_SET,
619 .length = field->size,
620 .offset = field->offset,
622 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
623 actions[i].data1 = conf->vlan_vid;
624 actions[i].data1 = actions[i].data1 << 16;
625 resource->actions_num = ++i;
630 * Convert modify-header set TP action to DV specification.
632 * @param[in,out] resource
633 * Pointer to the modify-header resource.
635 * Pointer to action specification.
637 * Pointer to rte_flow_item objects list.
639 * Pointer to flow attributes structure.
640 * @param[in] dev_flow
641 * Pointer to the sub flow.
642 * @param[in] tunnel_decap
643 * Whether action is after tunnel decapsulation.
645 * Pointer to the error structure.
648 * 0 on success, a negative errno value otherwise and rte_errno is set.
651 flow_dv_convert_action_modify_tp
652 (struct mlx5_flow_dv_modify_hdr_resource *resource,
653 const struct rte_flow_action *action,
654 const struct rte_flow_item *items,
655 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
656 bool tunnel_decap, struct rte_flow_error *error)
658 const struct rte_flow_action_set_tp *conf =
659 (const struct rte_flow_action_set_tp *)(action->conf);
660 struct rte_flow_item item;
661 struct rte_flow_item_udp udp;
662 struct rte_flow_item_udp udp_mask;
663 struct rte_flow_item_tcp tcp;
664 struct rte_flow_item_tcp tcp_mask;
665 struct field_modify_info *field;
668 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
670 memset(&udp, 0, sizeof(udp));
671 memset(&udp_mask, 0, sizeof(udp_mask));
672 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
673 udp.hdr.src_port = conf->port;
674 udp_mask.hdr.src_port =
675 rte_flow_item_udp_mask.hdr.src_port;
677 udp.hdr.dst_port = conf->port;
678 udp_mask.hdr.dst_port =
679 rte_flow_item_udp_mask.hdr.dst_port;
681 item.type = RTE_FLOW_ITEM_TYPE_UDP;
683 item.mask = &udp_mask;
686 MLX5_ASSERT(attr->tcp);
687 memset(&tcp, 0, sizeof(tcp));
688 memset(&tcp_mask, 0, sizeof(tcp_mask));
689 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
690 tcp.hdr.src_port = conf->port;
691 tcp_mask.hdr.src_port =
692 rte_flow_item_tcp_mask.hdr.src_port;
694 tcp.hdr.dst_port = conf->port;
695 tcp_mask.hdr.dst_port =
696 rte_flow_item_tcp_mask.hdr.dst_port;
698 item.type = RTE_FLOW_ITEM_TYPE_TCP;
700 item.mask = &tcp_mask;
703 return flow_dv_convert_modify_action(&item, field, NULL, resource,
704 MLX5_MODIFICATION_TYPE_SET, error);
708 * Convert modify-header set TTL action to DV specification.
710 * @param[in,out] resource
711 * Pointer to the modify-header resource.
713 * Pointer to action specification.
715 * Pointer to rte_flow_item objects list.
717 * Pointer to flow attributes structure.
718 * @param[in] dev_flow
719 * Pointer to the sub flow.
720 * @param[in] tunnel_decap
721 * Whether action is after tunnel decapsulation.
723 * Pointer to the error structure.
726 * 0 on success, a negative errno value otherwise and rte_errno is set.
729 flow_dv_convert_action_modify_ttl
730 (struct mlx5_flow_dv_modify_hdr_resource *resource,
731 const struct rte_flow_action *action,
732 const struct rte_flow_item *items,
733 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
734 bool tunnel_decap, struct rte_flow_error *error)
736 const struct rte_flow_action_set_ttl *conf =
737 (const struct rte_flow_action_set_ttl *)(action->conf);
738 struct rte_flow_item item;
739 struct rte_flow_item_ipv4 ipv4;
740 struct rte_flow_item_ipv4 ipv4_mask;
741 struct rte_flow_item_ipv6 ipv6;
742 struct rte_flow_item_ipv6 ipv6_mask;
743 struct field_modify_info *field;
746 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
748 memset(&ipv4, 0, sizeof(ipv4));
749 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
750 ipv4.hdr.time_to_live = conf->ttl_value;
751 ipv4_mask.hdr.time_to_live = 0xFF;
752 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
754 item.mask = &ipv4_mask;
757 MLX5_ASSERT(attr->ipv6);
758 memset(&ipv6, 0, sizeof(ipv6));
759 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
760 ipv6.hdr.hop_limits = conf->ttl_value;
761 ipv6_mask.hdr.hop_limits = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
764 item.mask = &ipv6_mask;
767 return flow_dv_convert_modify_action(&item, field, NULL, resource,
768 MLX5_MODIFICATION_TYPE_SET, error);
772 * Convert modify-header decrement TTL action to DV specification.
774 * @param[in,out] resource
775 * Pointer to the modify-header resource.
777 * Pointer to action specification.
779 * Pointer to rte_flow_item objects list.
781 * Pointer to flow attributes structure.
782 * @param[in] dev_flow
783 * Pointer to the sub flow.
784 * @param[in] tunnel_decap
785 * Whether action is after tunnel decapsulation.
787 * Pointer to the error structure.
790 * 0 on success, a negative errno value otherwise and rte_errno is set.
793 flow_dv_convert_action_modify_dec_ttl
794 (struct mlx5_flow_dv_modify_hdr_resource *resource,
795 const struct rte_flow_item *items,
796 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
797 bool tunnel_decap, struct rte_flow_error *error)
799 struct rte_flow_item item;
800 struct rte_flow_item_ipv4 ipv4;
801 struct rte_flow_item_ipv4 ipv4_mask;
802 struct rte_flow_item_ipv6 ipv6;
803 struct rte_flow_item_ipv6 ipv6_mask;
804 struct field_modify_info *field;
807 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
809 memset(&ipv4, 0, sizeof(ipv4));
810 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
811 ipv4.hdr.time_to_live = 0xFF;
812 ipv4_mask.hdr.time_to_live = 0xFF;
813 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
815 item.mask = &ipv4_mask;
818 MLX5_ASSERT(attr->ipv6);
819 memset(&ipv6, 0, sizeof(ipv6));
820 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
821 ipv6.hdr.hop_limits = 0xFF;
822 ipv6_mask.hdr.hop_limits = 0xFF;
823 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
825 item.mask = &ipv6_mask;
828 return flow_dv_convert_modify_action(&item, field, NULL, resource,
829 MLX5_MODIFICATION_TYPE_ADD, error);
833 * Convert modify-header increment/decrement TCP Sequence number
834 * to DV specification.
836 * @param[in,out] resource
837 * Pointer to the modify-header resource.
839 * Pointer to action specification.
841 * Pointer to the error structure.
844 * 0 on success, a negative errno value otherwise and rte_errno is set.
847 flow_dv_convert_action_modify_tcp_seq
848 (struct mlx5_flow_dv_modify_hdr_resource *resource,
849 const struct rte_flow_action *action,
850 struct rte_flow_error *error)
852 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
853 uint64_t value = rte_be_to_cpu_32(*conf);
854 struct rte_flow_item item;
855 struct rte_flow_item_tcp tcp;
856 struct rte_flow_item_tcp tcp_mask;
858 memset(&tcp, 0, sizeof(tcp));
859 memset(&tcp_mask, 0, sizeof(tcp_mask));
860 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
862 * The HW has no decrement operation, only increment operation.
863 * To simulate decrement X from Y using increment operation
864 * we need to add UINT32_MAX X times to Y.
865 * Each adding of UINT32_MAX decrements Y by 1.
868 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
869 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
870 item.type = RTE_FLOW_ITEM_TYPE_TCP;
872 item.mask = &tcp_mask;
873 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
874 MLX5_MODIFICATION_TYPE_ADD, error);
878 * Convert modify-header increment/decrement TCP Acknowledgment number
879 * to DV specification.
881 * @param[in,out] resource
882 * Pointer to the modify-header resource.
884 * Pointer to action specification.
886 * Pointer to the error structure.
889 * 0 on success, a negative errno value otherwise and rte_errno is set.
892 flow_dv_convert_action_modify_tcp_ack
893 (struct mlx5_flow_dv_modify_hdr_resource *resource,
894 const struct rte_flow_action *action,
895 struct rte_flow_error *error)
897 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
898 uint64_t value = rte_be_to_cpu_32(*conf);
899 struct rte_flow_item item;
900 struct rte_flow_item_tcp tcp;
901 struct rte_flow_item_tcp tcp_mask;
903 memset(&tcp, 0, sizeof(tcp));
904 memset(&tcp_mask, 0, sizeof(tcp_mask));
905 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
907 * The HW has no decrement operation, only increment operation.
908 * To simulate decrement X from Y using increment operation
909 * we need to add UINT32_MAX X times to Y.
910 * Each adding of UINT32_MAX decrements Y by 1.
913 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
914 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
915 item.type = RTE_FLOW_ITEM_TYPE_TCP;
917 item.mask = &tcp_mask;
918 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
919 MLX5_MODIFICATION_TYPE_ADD, error);
922 static enum mlx5_modification_field reg_to_field[] = {
923 [REG_NON] = MLX5_MODI_OUT_NONE,
924 [REG_A] = MLX5_MODI_META_DATA_REG_A,
925 [REG_B] = MLX5_MODI_META_DATA_REG_B,
926 [REG_C_0] = MLX5_MODI_META_REG_C_0,
927 [REG_C_1] = MLX5_MODI_META_REG_C_1,
928 [REG_C_2] = MLX5_MODI_META_REG_C_2,
929 [REG_C_3] = MLX5_MODI_META_REG_C_3,
930 [REG_C_4] = MLX5_MODI_META_REG_C_4,
931 [REG_C_5] = MLX5_MODI_META_REG_C_5,
932 [REG_C_6] = MLX5_MODI_META_REG_C_6,
933 [REG_C_7] = MLX5_MODI_META_REG_C_7,
937 * Convert register set to DV specification.
939 * @param[in,out] resource
940 * Pointer to the modify-header resource.
942 * Pointer to action specification.
944 * Pointer to the error structure.
947 * 0 on success, a negative errno value otherwise and rte_errno is set.
950 flow_dv_convert_action_set_reg
951 (struct mlx5_flow_dv_modify_hdr_resource *resource,
952 const struct rte_flow_action *action,
953 struct rte_flow_error *error)
955 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
956 struct mlx5_modification_cmd *actions = resource->actions;
957 uint32_t i = resource->actions_num;
959 if (i >= MLX5_MAX_MODIFY_NUM)
960 return rte_flow_error_set(error, EINVAL,
961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
962 "too many items to modify");
963 MLX5_ASSERT(conf->id != REG_NON);
964 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
965 actions[i] = (struct mlx5_modification_cmd) {
966 .action_type = MLX5_MODIFICATION_TYPE_SET,
967 .field = reg_to_field[conf->id],
969 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
970 actions[i].data1 = rte_cpu_to_be_32(conf->data);
972 resource->actions_num = i;
977 * Convert SET_TAG action to DV specification.
980 * Pointer to the rte_eth_dev structure.
981 * @param[in,out] resource
982 * Pointer to the modify-header resource.
984 * Pointer to action specification.
986 * Pointer to the error structure.
989 * 0 on success, a negative errno value otherwise and rte_errno is set.
992 flow_dv_convert_action_set_tag
993 (struct rte_eth_dev *dev,
994 struct mlx5_flow_dv_modify_hdr_resource *resource,
995 const struct rte_flow_action_set_tag *conf,
996 struct rte_flow_error *error)
998 rte_be32_t data = rte_cpu_to_be_32(conf->data);
999 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1000 struct rte_flow_item item = {
1004 struct field_modify_info reg_c_x[] = {
1007 enum mlx5_modification_field reg_type;
1010 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1013 MLX5_ASSERT(ret != REG_NON);
1014 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1015 reg_type = reg_to_field[ret];
1016 MLX5_ASSERT(reg_type > 0);
1017 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1018 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1019 MLX5_MODIFICATION_TYPE_SET, error);
1023 * Convert internal COPY_REG action to DV specification.
1026 * Pointer to the rte_eth_dev structure.
1027 * @param[in,out] res
1028 * Pointer to the modify-header resource.
1030 * Pointer to action specification.
1032 * Pointer to the error structure.
1035 * 0 on success, a negative errno value otherwise and rte_errno is set.
1038 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1039 struct mlx5_flow_dv_modify_hdr_resource *res,
1040 const struct rte_flow_action *action,
1041 struct rte_flow_error *error)
1043 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1044 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1045 struct rte_flow_item item = {
1049 struct field_modify_info reg_src[] = {
1050 {4, 0, reg_to_field[conf->src]},
1053 struct field_modify_info reg_dst = {
1055 .id = reg_to_field[conf->dst],
1057 /* Adjust reg_c[0] usage according to reported mask. */
1058 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1059 struct mlx5_priv *priv = dev->data->dev_private;
1060 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1062 MLX5_ASSERT(reg_c0);
1063 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1064 if (conf->dst == REG_C_0) {
1065 /* Copy to reg_c[0], within mask only. */
1066 reg_dst.offset = rte_bsf32(reg_c0);
1068 * Mask is ignoring the enianness, because
1069 * there is no conversion in datapath.
1071 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1072 /* Copy from destination lower bits to reg_c[0]. */
1073 mask = reg_c0 >> reg_dst.offset;
1075 /* Copy from destination upper bits to reg_c[0]. */
1076 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1077 rte_fls_u32(reg_c0));
1080 mask = rte_cpu_to_be_32(reg_c0);
1081 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1082 /* Copy from reg_c[0] to destination lower bits. */
1085 /* Copy from reg_c[0] to destination upper bits. */
1086 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1087 (rte_fls_u32(reg_c0) -
1092 return flow_dv_convert_modify_action(&item,
1093 reg_src, ®_dst, res,
1094 MLX5_MODIFICATION_TYPE_COPY,
1099 * Convert MARK action to DV specification. This routine is used
1100 * in extensive metadata only and requires metadata register to be
1101 * handled. In legacy mode hardware tag resource is engaged.
1104 * Pointer to the rte_eth_dev structure.
1106 * Pointer to MARK action specification.
1107 * @param[in,out] resource
1108 * Pointer to the modify-header resource.
1110 * Pointer to the error structure.
1113 * 0 on success, a negative errno value otherwise and rte_errno is set.
1116 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1117 const struct rte_flow_action_mark *conf,
1118 struct mlx5_flow_dv_modify_hdr_resource *resource,
1119 struct rte_flow_error *error)
1121 struct mlx5_priv *priv = dev->data->dev_private;
1122 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1123 priv->sh->dv_mark_mask);
1124 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1125 struct rte_flow_item item = {
1129 struct field_modify_info reg_c_x[] = {
1135 return rte_flow_error_set(error, EINVAL,
1136 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1137 NULL, "zero mark action mask");
1138 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1141 MLX5_ASSERT(reg > 0);
1142 if (reg == REG_C_0) {
1143 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1144 uint32_t shl_c0 = rte_bsf32(msk_c0);
1146 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1147 mask = rte_cpu_to_be_32(mask) & msk_c0;
1148 mask = rte_cpu_to_be_32(mask << shl_c0);
1150 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1151 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1152 MLX5_MODIFICATION_TYPE_SET, error);
1156 * Get metadata register index for specified steering domain.
1159 * Pointer to the rte_eth_dev structure.
1161 * Attributes of flow to determine steering domain.
1163 * Pointer to the error structure.
1166 * positive index on success, a negative errno value otherwise
1167 * and rte_errno is set.
1169 static enum modify_reg
1170 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1171 const struct rte_flow_attr *attr,
1172 struct rte_flow_error *error)
1175 mlx5_flow_get_reg_id(dev, attr->transfer ?
1179 MLX5_METADATA_RX, 0, error);
1181 return rte_flow_error_set(error,
1182 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1183 NULL, "unavailable "
1184 "metadata register");
1189 * Convert SET_META action to DV specification.
1192 * Pointer to the rte_eth_dev structure.
1193 * @param[in,out] resource
1194 * Pointer to the modify-header resource.
1196 * Attributes of flow that includes this item.
1198 * Pointer to action specification.
1200 * Pointer to the error structure.
1203 * 0 on success, a negative errno value otherwise and rte_errno is set.
1206 flow_dv_convert_action_set_meta
1207 (struct rte_eth_dev *dev,
1208 struct mlx5_flow_dv_modify_hdr_resource *resource,
1209 const struct rte_flow_attr *attr,
1210 const struct rte_flow_action_set_meta *conf,
1211 struct rte_flow_error *error)
1213 uint32_t data = conf->data;
1214 uint32_t mask = conf->mask;
1215 struct rte_flow_item item = {
1219 struct field_modify_info reg_c_x[] = {
1222 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1226 MLX5_ASSERT(reg != REG_NON);
1228 * In datapath code there is no endianness
1229 * coversions for perfromance reasons, all
1230 * pattern conversions are done in rte_flow.
1232 if (reg == REG_C_0) {
1233 struct mlx5_priv *priv = dev->data->dev_private;
1234 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1237 MLX5_ASSERT(msk_c0);
1238 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1239 shl_c0 = rte_bsf32(msk_c0);
1241 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1245 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1247 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1248 /* The routine expects parameters in memory as big-endian ones. */
1249 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1250 MLX5_MODIFICATION_TYPE_SET, error);
1254 * Convert modify-header set IPv4 DSCP action to DV specification.
1256 * @param[in,out] resource
1257 * Pointer to the modify-header resource.
1259 * Pointer to action specification.
1261 * Pointer to the error structure.
1264 * 0 on success, a negative errno value otherwise and rte_errno is set.
1267 flow_dv_convert_action_modify_ipv4_dscp
1268 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1269 const struct rte_flow_action *action,
1270 struct rte_flow_error *error)
1272 const struct rte_flow_action_set_dscp *conf =
1273 (const struct rte_flow_action_set_dscp *)(action->conf);
1274 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1275 struct rte_flow_item_ipv4 ipv4;
1276 struct rte_flow_item_ipv4 ipv4_mask;
1278 memset(&ipv4, 0, sizeof(ipv4));
1279 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1280 ipv4.hdr.type_of_service = conf->dscp;
1281 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1283 item.mask = &ipv4_mask;
1284 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1285 MLX5_MODIFICATION_TYPE_SET, error);
1289 * Convert modify-header set IPv6 DSCP action to DV specification.
1291 * @param[in,out] resource
1292 * Pointer to the modify-header resource.
1294 * Pointer to action specification.
1296 * Pointer to the error structure.
1299 * 0 on success, a negative errno value otherwise and rte_errno is set.
1302 flow_dv_convert_action_modify_ipv6_dscp
1303 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1304 const struct rte_flow_action *action,
1305 struct rte_flow_error *error)
1307 const struct rte_flow_action_set_dscp *conf =
1308 (const struct rte_flow_action_set_dscp *)(action->conf);
1309 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1310 struct rte_flow_item_ipv6 ipv6;
1311 struct rte_flow_item_ipv6 ipv6_mask;
1313 memset(&ipv6, 0, sizeof(ipv6));
1314 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1316 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1317 * rdma-core only accept the DSCP bits byte aligned start from
1318 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1319 * bits in IPv6 case as rdma-core requires byte aligned value.
1321 ipv6.hdr.vtc_flow = conf->dscp;
1322 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1324 item.mask = &ipv6_mask;
1325 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1326 MLX5_MODIFICATION_TYPE_SET, error);
1330 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1333 case RTE_FLOW_FIELD_START:
1335 case RTE_FLOW_FIELD_MAC_DST:
1336 case RTE_FLOW_FIELD_MAC_SRC:
1338 case RTE_FLOW_FIELD_VLAN_TYPE:
1340 case RTE_FLOW_FIELD_VLAN_ID:
1342 case RTE_FLOW_FIELD_MAC_TYPE:
1344 case RTE_FLOW_FIELD_IPV4_DSCP:
1346 case RTE_FLOW_FIELD_IPV4_TTL:
1348 case RTE_FLOW_FIELD_IPV4_SRC:
1349 case RTE_FLOW_FIELD_IPV4_DST:
1351 case RTE_FLOW_FIELD_IPV6_DSCP:
1353 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1355 case RTE_FLOW_FIELD_IPV6_SRC:
1356 case RTE_FLOW_FIELD_IPV6_DST:
1358 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1359 case RTE_FLOW_FIELD_TCP_PORT_DST:
1361 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1362 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1364 case RTE_FLOW_FIELD_TCP_FLAGS:
1366 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1367 case RTE_FLOW_FIELD_UDP_PORT_DST:
1369 case RTE_FLOW_FIELD_VXLAN_VNI:
1370 case RTE_FLOW_FIELD_GENEVE_VNI:
1372 case RTE_FLOW_FIELD_GTP_TEID:
1373 case RTE_FLOW_FIELD_TAG:
1375 case RTE_FLOW_FIELD_MARK:
1377 case RTE_FLOW_FIELD_META:
1379 case RTE_FLOW_FIELD_POINTER:
1380 case RTE_FLOW_FIELD_VALUE:
1389 mlx5_flow_field_id_to_modify_info
1390 (const struct rte_flow_action_modify_data *data,
1391 struct field_modify_info *info,
1392 uint32_t *mask, uint32_t *value,
1393 uint32_t width, uint32_t dst_width,
1394 struct rte_eth_dev *dev,
1395 const struct rte_flow_attr *attr,
1396 struct rte_flow_error *error)
1400 switch (data->field) {
1401 case RTE_FLOW_FIELD_START:
1402 /* not supported yet */
1405 case RTE_FLOW_FIELD_MAC_DST:
1407 if (data->offset < 32) {
1408 info[idx] = (struct field_modify_info){4, 0,
1409 MLX5_MODI_OUT_DMAC_47_16};
1412 rte_cpu_to_be_32(0xffffffff >>
1416 mask[idx] = RTE_BE32(0xffffffff);
1423 info[idx] = (struct field_modify_info){2, 4 * idx,
1424 MLX5_MODI_OUT_DMAC_15_0};
1425 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1427 if (data->offset < 32)
1428 info[idx++] = (struct field_modify_info){4, 0,
1429 MLX5_MODI_OUT_DMAC_47_16};
1430 info[idx] = (struct field_modify_info){2, 0,
1431 MLX5_MODI_OUT_DMAC_15_0};
1434 case RTE_FLOW_FIELD_MAC_SRC:
1436 if (data->offset < 32) {
1437 info[idx] = (struct field_modify_info){4, 0,
1438 MLX5_MODI_OUT_SMAC_47_16};
1441 rte_cpu_to_be_32(0xffffffff >>
1445 mask[idx] = RTE_BE32(0xffffffff);
1452 info[idx] = (struct field_modify_info){2, 4 * idx,
1453 MLX5_MODI_OUT_SMAC_15_0};
1454 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1456 if (data->offset < 32)
1457 info[idx++] = (struct field_modify_info){4, 0,
1458 MLX5_MODI_OUT_SMAC_47_16};
1459 info[idx] = (struct field_modify_info){2, 0,
1460 MLX5_MODI_OUT_SMAC_15_0};
1463 case RTE_FLOW_FIELD_VLAN_TYPE:
1464 /* not supported yet */
1466 case RTE_FLOW_FIELD_VLAN_ID:
1467 info[idx] = (struct field_modify_info){2, 0,
1468 MLX5_MODI_OUT_FIRST_VID};
1470 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1472 case RTE_FLOW_FIELD_MAC_TYPE:
1473 info[idx] = (struct field_modify_info){2, 0,
1474 MLX5_MODI_OUT_ETHERTYPE};
1476 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1478 case RTE_FLOW_FIELD_IPV4_DSCP:
1479 info[idx] = (struct field_modify_info){1, 0,
1480 MLX5_MODI_OUT_IP_DSCP};
1482 mask[idx] = 0x3f >> (6 - width);
1484 case RTE_FLOW_FIELD_IPV4_TTL:
1485 info[idx] = (struct field_modify_info){1, 0,
1486 MLX5_MODI_OUT_IPV4_TTL};
1488 mask[idx] = 0xff >> (8 - width);
1490 case RTE_FLOW_FIELD_IPV4_SRC:
1491 info[idx] = (struct field_modify_info){4, 0,
1492 MLX5_MODI_OUT_SIPV4};
1494 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1497 case RTE_FLOW_FIELD_IPV4_DST:
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DIPV4};
1501 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1504 case RTE_FLOW_FIELD_IPV6_DSCP:
1505 info[idx] = (struct field_modify_info){1, 0,
1506 MLX5_MODI_OUT_IP_DSCP};
1508 mask[idx] = 0x3f >> (6 - width);
1510 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1511 info[idx] = (struct field_modify_info){1, 0,
1512 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1514 mask[idx] = 0xff >> (8 - width);
1516 case RTE_FLOW_FIELD_IPV6_SRC:
1518 if (data->offset < 32) {
1519 info[idx] = (struct field_modify_info){4,
1521 MLX5_MODI_OUT_SIPV6_31_0};
1524 rte_cpu_to_be_32(0xffffffff >>
1528 mask[idx] = RTE_BE32(0xffffffff);
1535 if (data->offset < 64) {
1536 info[idx] = (struct field_modify_info){4,
1538 MLX5_MODI_OUT_SIPV6_63_32};
1541 rte_cpu_to_be_32(0xffffffff >>
1545 mask[idx] = RTE_BE32(0xffffffff);
1552 if (data->offset < 96) {
1553 info[idx] = (struct field_modify_info){4,
1555 MLX5_MODI_OUT_SIPV6_95_64};
1558 rte_cpu_to_be_32(0xffffffff >>
1562 mask[idx] = RTE_BE32(0xffffffff);
1569 info[idx] = (struct field_modify_info){4, 4 * idx,
1570 MLX5_MODI_OUT_SIPV6_127_96};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 if (data->offset < 32)
1575 info[idx++] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_SIPV6_31_0};
1577 if (data->offset < 64)
1578 info[idx++] = (struct field_modify_info){4, 0,
1579 MLX5_MODI_OUT_SIPV6_63_32};
1580 if (data->offset < 96)
1581 info[idx++] = (struct field_modify_info){4, 0,
1582 MLX5_MODI_OUT_SIPV6_95_64};
1583 if (data->offset < 128)
1584 info[idx++] = (struct field_modify_info){4, 0,
1585 MLX5_MODI_OUT_SIPV6_127_96};
1588 case RTE_FLOW_FIELD_IPV6_DST:
1590 if (data->offset < 32) {
1591 info[idx] = (struct field_modify_info){4,
1593 MLX5_MODI_OUT_DIPV6_31_0};
1596 rte_cpu_to_be_32(0xffffffff >>
1600 mask[idx] = RTE_BE32(0xffffffff);
1607 if (data->offset < 64) {
1608 info[idx] = (struct field_modify_info){4,
1610 MLX5_MODI_OUT_DIPV6_63_32};
1613 rte_cpu_to_be_32(0xffffffff >>
1617 mask[idx] = RTE_BE32(0xffffffff);
1624 if (data->offset < 96) {
1625 info[idx] = (struct field_modify_info){4,
1627 MLX5_MODI_OUT_DIPV6_95_64};
1630 rte_cpu_to_be_32(0xffffffff >>
1634 mask[idx] = RTE_BE32(0xffffffff);
1641 info[idx] = (struct field_modify_info){4, 4 * idx,
1642 MLX5_MODI_OUT_DIPV6_127_96};
1643 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1646 if (data->offset < 32)
1647 info[idx++] = (struct field_modify_info){4, 0,
1648 MLX5_MODI_OUT_DIPV6_31_0};
1649 if (data->offset < 64)
1650 info[idx++] = (struct field_modify_info){4, 0,
1651 MLX5_MODI_OUT_DIPV6_63_32};
1652 if (data->offset < 96)
1653 info[idx++] = (struct field_modify_info){4, 0,
1654 MLX5_MODI_OUT_DIPV6_95_64};
1655 if (data->offset < 128)
1656 info[idx++] = (struct field_modify_info){4, 0,
1657 MLX5_MODI_OUT_DIPV6_127_96};
1660 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1661 info[idx] = (struct field_modify_info){2, 0,
1662 MLX5_MODI_OUT_TCP_SPORT};
1664 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1666 case RTE_FLOW_FIELD_TCP_PORT_DST:
1667 info[idx] = (struct field_modify_info){2, 0,
1668 MLX5_MODI_OUT_TCP_DPORT};
1670 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1672 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1673 info[idx] = (struct field_modify_info){4, 0,
1674 MLX5_MODI_OUT_TCP_SEQ_NUM};
1676 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1679 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1680 info[idx] = (struct field_modify_info){4, 0,
1681 MLX5_MODI_OUT_TCP_ACK_NUM};
1683 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1686 case RTE_FLOW_FIELD_TCP_FLAGS:
1687 info[idx] = (struct field_modify_info){1, 0,
1688 MLX5_MODI_OUT_TCP_FLAGS};
1690 mask[idx] = 0x3f >> (6 - width);
1692 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1693 info[idx] = (struct field_modify_info){2, 0,
1694 MLX5_MODI_OUT_UDP_SPORT};
1696 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1698 case RTE_FLOW_FIELD_UDP_PORT_DST:
1699 info[idx] = (struct field_modify_info){2, 0,
1700 MLX5_MODI_OUT_UDP_DPORT};
1702 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1704 case RTE_FLOW_FIELD_VXLAN_VNI:
1705 /* not supported yet */
1707 case RTE_FLOW_FIELD_GENEVE_VNI:
1708 /* not supported yet*/
1710 case RTE_FLOW_FIELD_GTP_TEID:
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_GTP_TEID};
1714 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1717 case RTE_FLOW_FIELD_TAG:
1719 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1720 data->level, error);
1723 MLX5_ASSERT(reg != REG_NON);
1724 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1725 info[idx] = (struct field_modify_info){4, 0,
1729 rte_cpu_to_be_32(0xffffffff >>
1733 case RTE_FLOW_FIELD_MARK:
1735 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1739 MLX5_ASSERT(reg != REG_NON);
1740 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1741 info[idx] = (struct field_modify_info){4, 0,
1745 rte_cpu_to_be_32(0xffffffff >>
1749 case RTE_FLOW_FIELD_META:
1751 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1754 MLX5_ASSERT(reg != REG_NON);
1755 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1756 info[idx] = (struct field_modify_info){4, 0,
1760 rte_cpu_to_be_32(0xffffffff >>
1764 case RTE_FLOW_FIELD_POINTER:
1765 case RTE_FLOW_FIELD_VALUE:
1766 if (data->field == RTE_FLOW_FIELD_POINTER)
1767 memcpy(&val, (void *)(uintptr_t)data->value,
1771 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1773 if (dst_width > 16) {
1774 value[idx] = rte_cpu_to_be_32(val);
1776 } else if (dst_width > 8) {
1777 value[idx] = rte_cpu_to_be_16(val);
1780 value[idx] = (uint8_t)val;
1795 * Convert modify_field action to DV specification.
1798 * Pointer to the rte_eth_dev structure.
1799 * @param[in,out] resource
1800 * Pointer to the modify-header resource.
1802 * Pointer to action specification.
1804 * Attributes of flow that includes this item.
1806 * Pointer to the error structure.
1809 * 0 on success, a negative errno value otherwise and rte_errno is set.
1812 flow_dv_convert_action_modify_field
1813 (struct rte_eth_dev *dev,
1814 struct mlx5_flow_dv_modify_hdr_resource *resource,
1815 const struct rte_flow_action *action,
1816 const struct rte_flow_attr *attr,
1817 struct rte_flow_error *error)
1819 const struct rte_flow_action_modify_field *conf =
1820 (const struct rte_flow_action_modify_field *)(action->conf);
1821 struct rte_flow_item item;
1822 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1824 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1826 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1827 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829 uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1831 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1832 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1833 type = MLX5_MODIFICATION_TYPE_SET;
1834 /** For SET fill the destination field (field) first. */
1835 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1836 value, conf->width, dst_width, dev, attr, error);
1837 /** Then copy immediate value from source as per mask. */
1838 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1839 value, conf->width, dst_width, dev, attr, error);
1842 type = MLX5_MODIFICATION_TYPE_COPY;
1843 /** For COPY fill the destination field (dcopy) without mask. */
1844 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1845 value, conf->width, dst_width, dev, attr, error);
1846 /** Then construct the source field (field) with mask. */
1847 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1848 value, conf->width, dst_width, dev, attr, error);
1851 return flow_dv_convert_modify_action(&item,
1852 field, dcopy, resource, type, error);
1856 * Validate MARK item.
1859 * Pointer to the rte_eth_dev structure.
1861 * Item specification.
1863 * Attributes of flow that includes this item.
1865 * Pointer to error structure.
1868 * 0 on success, a negative errno value otherwise and rte_errno is set.
1871 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1872 const struct rte_flow_item *item,
1873 const struct rte_flow_attr *attr __rte_unused,
1874 struct rte_flow_error *error)
1876 struct mlx5_priv *priv = dev->data->dev_private;
1877 struct mlx5_dev_config *config = &priv->config;
1878 const struct rte_flow_item_mark *spec = item->spec;
1879 const struct rte_flow_item_mark *mask = item->mask;
1880 const struct rte_flow_item_mark nic_mask = {
1881 .id = priv->sh->dv_mark_mask,
1885 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1886 return rte_flow_error_set(error, ENOTSUP,
1887 RTE_FLOW_ERROR_TYPE_ITEM, item,
1888 "extended metadata feature"
1890 if (!mlx5_flow_ext_mreg_supported(dev))
1891 return rte_flow_error_set(error, ENOTSUP,
1892 RTE_FLOW_ERROR_TYPE_ITEM, item,
1893 "extended metadata register"
1894 " isn't supported");
1896 return rte_flow_error_set(error, ENOTSUP,
1897 RTE_FLOW_ERROR_TYPE_ITEM, item,
1898 "extended metadata register"
1899 " isn't available");
1900 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1904 return rte_flow_error_set(error, EINVAL,
1905 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1907 "data cannot be empty");
1908 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1909 return rte_flow_error_set(error, EINVAL,
1910 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1912 "mark id exceeds the limit");
1916 return rte_flow_error_set(error, EINVAL,
1917 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1918 "mask cannot be zero");
1920 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1921 (const uint8_t *)&nic_mask,
1922 sizeof(struct rte_flow_item_mark),
1923 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1930 * Validate META item.
1933 * Pointer to the rte_eth_dev structure.
1935 * Item specification.
1937 * Attributes of flow that includes this item.
1939 * Pointer to error structure.
1942 * 0 on success, a negative errno value otherwise and rte_errno is set.
1945 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1946 const struct rte_flow_item *item,
1947 const struct rte_flow_attr *attr,
1948 struct rte_flow_error *error)
1950 struct mlx5_priv *priv = dev->data->dev_private;
1951 struct mlx5_dev_config *config = &priv->config;
1952 const struct rte_flow_item_meta *spec = item->spec;
1953 const struct rte_flow_item_meta *mask = item->mask;
1954 struct rte_flow_item_meta nic_mask = {
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1964 "data cannot be empty");
1965 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1966 if (!mlx5_flow_ext_mreg_supported(dev))
1967 return rte_flow_error_set(error, ENOTSUP,
1968 RTE_FLOW_ERROR_TYPE_ITEM, item,
1969 "extended metadata register"
1970 " isn't supported");
1971 reg = flow_dv_get_metadata_reg(dev, attr, error);
1975 return rte_flow_error_set(error, ENOTSUP,
1976 RTE_FLOW_ERROR_TYPE_ITEM, item,
1977 "unavalable extended metadata register");
1979 return rte_flow_error_set(error, ENOTSUP,
1980 RTE_FLOW_ERROR_TYPE_ITEM, item,
1984 nic_mask.data = priv->sh->dv_meta_mask;
1987 return rte_flow_error_set(error, ENOTSUP,
1988 RTE_FLOW_ERROR_TYPE_ITEM, item,
1989 "extended metadata feature "
1990 "should be enabled when "
1991 "meta item is requested "
1992 "with e-switch mode ");
1994 return rte_flow_error_set(error, ENOTSUP,
1995 RTE_FLOW_ERROR_TYPE_ITEM, item,
1996 "match on metadata for ingress "
1997 "is not supported in legacy "
2001 mask = &rte_flow_item_meta_mask;
2003 return rte_flow_error_set(error, EINVAL,
2004 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2005 "mask cannot be zero");
2007 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2008 (const uint8_t *)&nic_mask,
2009 sizeof(struct rte_flow_item_meta),
2010 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2015 * Validate TAG item.
2018 * Pointer to the rte_eth_dev structure.
2020 * Item specification.
2022 * Attributes of flow that includes this item.
2024 * Pointer to error structure.
2027 * 0 on success, a negative errno value otherwise and rte_errno is set.
2030 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2031 const struct rte_flow_item *item,
2032 const struct rte_flow_attr *attr __rte_unused,
2033 struct rte_flow_error *error)
2035 const struct rte_flow_item_tag *spec = item->spec;
2036 const struct rte_flow_item_tag *mask = item->mask;
2037 const struct rte_flow_item_tag nic_mask = {
2038 .data = RTE_BE32(UINT32_MAX),
2043 if (!mlx5_flow_ext_mreg_supported(dev))
2044 return rte_flow_error_set(error, ENOTSUP,
2045 RTE_FLOW_ERROR_TYPE_ITEM, item,
2046 "extensive metadata register"
2047 " isn't supported");
2049 return rte_flow_error_set(error, EINVAL,
2050 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2052 "data cannot be empty");
2054 mask = &rte_flow_item_tag_mask;
2056 return rte_flow_error_set(error, EINVAL,
2057 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2058 "mask cannot be zero");
2060 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2061 (const uint8_t *)&nic_mask,
2062 sizeof(struct rte_flow_item_tag),
2063 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066 if (mask->index != 0xff)
2067 return rte_flow_error_set(error, EINVAL,
2068 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2069 "partial mask for tag index"
2070 " is not supported");
2071 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2074 MLX5_ASSERT(ret != REG_NON);
2079 * Validate vport item.
2082 * Pointer to the rte_eth_dev structure.
2084 * Item specification.
2086 * Attributes of flow that includes this item.
2087 * @param[in] item_flags
2088 * Bit-fields that holds the items detected until now.
2090 * Pointer to error structure.
2093 * 0 on success, a negative errno value otherwise and rte_errno is set.
2096 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2097 const struct rte_flow_item *item,
2098 const struct rte_flow_attr *attr,
2099 uint64_t item_flags,
2100 struct rte_flow_error *error)
2102 const struct rte_flow_item_port_id *spec = item->spec;
2103 const struct rte_flow_item_port_id *mask = item->mask;
2104 const struct rte_flow_item_port_id switch_mask = {
2107 struct mlx5_priv *esw_priv;
2108 struct mlx5_priv *dev_priv;
2111 if (!attr->transfer)
2112 return rte_flow_error_set(error, EINVAL,
2113 RTE_FLOW_ERROR_TYPE_ITEM,
2115 "match on port id is valid only"
2116 " when transfer flag is enabled");
2117 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2118 return rte_flow_error_set(error, ENOTSUP,
2119 RTE_FLOW_ERROR_TYPE_ITEM, item,
2120 "multiple source ports are not"
2123 mask = &switch_mask;
2124 if (mask->id != 0xffffffff)
2125 return rte_flow_error_set(error, ENOTSUP,
2126 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2128 "no support for partial mask on"
2130 ret = mlx5_flow_item_acceptable
2131 (item, (const uint8_t *)mask,
2132 (const uint8_t *)&rte_flow_item_port_id_mask,
2133 sizeof(struct rte_flow_item_port_id),
2134 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2139 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2141 return rte_flow_error_set(error, rte_errno,
2142 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2143 "failed to obtain E-Switch info for"
2145 dev_priv = mlx5_dev_to_eswitch_info(dev);
2147 return rte_flow_error_set(error, rte_errno,
2148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2150 "failed to obtain E-Switch info");
2151 if (esw_priv->domain_id != dev_priv->domain_id)
2152 return rte_flow_error_set(error, EINVAL,
2153 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2154 "cannot match on a port from a"
2155 " different E-Switch");
2160 * Validate VLAN item.
2163 * Item specification.
2164 * @param[in] item_flags
2165 * Bit-fields that holds the items detected until now.
2167 * Ethernet device flow is being created on.
2169 * Pointer to error structure.
2172 * 0 on success, a negative errno value otherwise and rte_errno is set.
2175 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2176 uint64_t item_flags,
2177 struct rte_eth_dev *dev,
2178 struct rte_flow_error *error)
2180 const struct rte_flow_item_vlan *mask = item->mask;
2181 const struct rte_flow_item_vlan nic_mask = {
2182 .tci = RTE_BE16(UINT16_MAX),
2183 .inner_type = RTE_BE16(UINT16_MAX),
2186 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2188 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2189 MLX5_FLOW_LAYER_INNER_L4) :
2190 (MLX5_FLOW_LAYER_OUTER_L3 |
2191 MLX5_FLOW_LAYER_OUTER_L4);
2192 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2193 MLX5_FLOW_LAYER_OUTER_VLAN;
2195 if (item_flags & vlanm)
2196 return rte_flow_error_set(error, EINVAL,
2197 RTE_FLOW_ERROR_TYPE_ITEM, item,
2198 "multiple VLAN layers not supported");
2199 else if ((item_flags & l34m) != 0)
2200 return rte_flow_error_set(error, EINVAL,
2201 RTE_FLOW_ERROR_TYPE_ITEM, item,
2202 "VLAN cannot follow L3/L4 layer");
2204 mask = &rte_flow_item_vlan_mask;
2205 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2206 (const uint8_t *)&nic_mask,
2207 sizeof(struct rte_flow_item_vlan),
2208 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2211 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2212 struct mlx5_priv *priv = dev->data->dev_private;
2214 if (priv->vmwa_context) {
2216 * Non-NULL context means we have a virtual machine
2217 * and SR-IOV enabled, we have to create VLAN interface
2218 * to make hypervisor to setup E-Switch vport
2219 * context correctly. We avoid creating the multiple
2220 * VLAN interfaces, so we cannot support VLAN tag mask.
2222 return rte_flow_error_set(error, EINVAL,
2223 RTE_FLOW_ERROR_TYPE_ITEM,
2225 "VLAN tag mask is not"
2226 " supported in virtual"
2234 * GTP flags are contained in 1 byte of the format:
2235 * -------------------------------------------
2236 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2237 * |-----------------------------------------|
2238 * | value | Version | PT | Res | E | S | PN |
2239 * -------------------------------------------
2241 * Matching is supported only for GTP flags E, S, PN.
2243 #define MLX5_GTP_FLAGS_MASK 0x07
2246 * Validate GTP item.
2249 * Pointer to the rte_eth_dev structure.
2251 * Item specification.
2252 * @param[in] item_flags
2253 * Bit-fields that holds the items detected until now.
2255 * Pointer to error structure.
2258 * 0 on success, a negative errno value otherwise and rte_errno is set.
2261 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2262 const struct rte_flow_item *item,
2263 uint64_t item_flags,
2264 struct rte_flow_error *error)
2266 struct mlx5_priv *priv = dev->data->dev_private;
2267 const struct rte_flow_item_gtp *spec = item->spec;
2268 const struct rte_flow_item_gtp *mask = item->mask;
2269 const struct rte_flow_item_gtp nic_mask = {
2270 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2272 .teid = RTE_BE32(0xffffffff),
2275 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2276 return rte_flow_error_set(error, ENOTSUP,
2277 RTE_FLOW_ERROR_TYPE_ITEM, item,
2278 "GTP support is not enabled");
2279 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2280 return rte_flow_error_set(error, ENOTSUP,
2281 RTE_FLOW_ERROR_TYPE_ITEM, item,
2282 "multiple tunnel layers not"
2284 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2285 return rte_flow_error_set(error, EINVAL,
2286 RTE_FLOW_ERROR_TYPE_ITEM, item,
2287 "no outer UDP layer found");
2289 mask = &rte_flow_item_gtp_mask;
2290 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2291 return rte_flow_error_set(error, ENOTSUP,
2292 RTE_FLOW_ERROR_TYPE_ITEM, item,
2293 "Match is supported for GTP"
2295 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2296 (const uint8_t *)&nic_mask,
2297 sizeof(struct rte_flow_item_gtp),
2298 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2302 * Validate GTP PSC item.
2305 * Item specification.
2306 * @param[in] last_item
2307 * Previous validated item in the pattern items.
2308 * @param[in] gtp_item
2309 * Previous GTP item specification.
2311 * Pointer to flow attributes.
2313 * Pointer to error structure.
2316 * 0 on success, a negative errno value otherwise and rte_errno is set.
2319 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2321 const struct rte_flow_item *gtp_item,
2322 const struct rte_flow_attr *attr,
2323 struct rte_flow_error *error)
2325 const struct rte_flow_item_gtp *gtp_spec;
2326 const struct rte_flow_item_gtp *gtp_mask;
2327 const struct rte_flow_item_gtp_psc *spec;
2328 const struct rte_flow_item_gtp_psc *mask;
2329 const struct rte_flow_item_gtp_psc nic_mask = {
2334 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2335 return rte_flow_error_set
2336 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2337 "GTP PSC item must be preceded with GTP item");
2338 gtp_spec = gtp_item->spec;
2339 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2340 /* GTP spec and E flag is requested to match zero. */
2342 (gtp_mask->v_pt_rsv_flags &
2343 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2344 return rte_flow_error_set
2345 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2346 "GTP E flag must be 1 to match GTP PSC");
2347 /* Check the flow is not created in group zero. */
2348 if (!attr->transfer && !attr->group)
2349 return rte_flow_error_set
2350 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2351 "GTP PSC is not supported for group 0");
2352 /* GTP spec is here and E flag is requested to match zero. */
2356 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2357 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2358 return rte_flow_error_set
2359 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2360 "PDU type should be smaller than 16");
2361 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2362 (const uint8_t *)&nic_mask,
2363 sizeof(struct rte_flow_item_gtp_psc),
2364 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2368 * Validate IPV4 item.
2369 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2370 * add specific validation of fragment_offset field,
2373 * Item specification.
2374 * @param[in] item_flags
2375 * Bit-fields that holds the items detected until now.
2377 * Pointer to error structure.
2380 * 0 on success, a negative errno value otherwise and rte_errno is set.
2383 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2384 uint64_t item_flags,
2386 uint16_t ether_type,
2387 struct rte_flow_error *error)
2390 const struct rte_flow_item_ipv4 *spec = item->spec;
2391 const struct rte_flow_item_ipv4 *last = item->last;
2392 const struct rte_flow_item_ipv4 *mask = item->mask;
2393 rte_be16_t fragment_offset_spec = 0;
2394 rte_be16_t fragment_offset_last = 0;
2395 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2397 .src_addr = RTE_BE32(0xffffffff),
2398 .dst_addr = RTE_BE32(0xffffffff),
2399 .type_of_service = 0xff,
2400 .fragment_offset = RTE_BE16(0xffff),
2401 .next_proto_id = 0xff,
2402 .time_to_live = 0xff,
2406 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2407 ether_type, &nic_ipv4_mask,
2408 MLX5_ITEM_RANGE_ACCEPTED, error);
2412 fragment_offset_spec = spec->hdr.fragment_offset &
2413 mask->hdr.fragment_offset;
2414 if (!fragment_offset_spec)
2417 * spec and mask are valid, enforce using full mask to make sure the
2418 * complete value is used correctly.
2420 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2421 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2422 return rte_flow_error_set(error, EINVAL,
2423 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2424 item, "must use full mask for"
2425 " fragment_offset");
2427 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2428 * indicating this is 1st fragment of fragmented packet.
2429 * This is not yet supported in MLX5, return appropriate error message.
2431 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2432 return rte_flow_error_set(error, ENOTSUP,
2433 RTE_FLOW_ERROR_TYPE_ITEM, item,
2434 "match on first fragment not "
2436 if (fragment_offset_spec && !last)
2437 return rte_flow_error_set(error, ENOTSUP,
2438 RTE_FLOW_ERROR_TYPE_ITEM, item,
2439 "specified value not supported");
2440 /* spec and last are valid, validate the specified range. */
2441 fragment_offset_last = last->hdr.fragment_offset &
2442 mask->hdr.fragment_offset;
2444 * Match on fragment_offset spec 0x2001 and last 0x3fff
2445 * means MF is 1 and frag-offset is > 0.
2446 * This packet is fragment 2nd and onward, excluding last.
2447 * This is not yet supported in MLX5, return appropriate
2450 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2451 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2452 return rte_flow_error_set(error, ENOTSUP,
2453 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2454 last, "match on following "
2455 "fragments not supported");
2457 * Match on fragment_offset spec 0x0001 and last 0x1fff
2458 * means MF is 0 and frag-offset is > 0.
2459 * This packet is last fragment of fragmented packet.
2460 * This is not yet supported in MLX5, return appropriate
2463 if (fragment_offset_spec == RTE_BE16(1) &&
2464 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2467 last, "match on last "
2468 "fragment not supported");
2470 * Match on fragment_offset spec 0x0001 and last 0x3fff
2471 * means MF and/or frag-offset is not 0.
2472 * This is a fragmented packet.
2473 * Other range values are invalid and rejected.
2475 if (!(fragment_offset_spec == RTE_BE16(1) &&
2476 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2477 return rte_flow_error_set(error, ENOTSUP,
2478 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2479 "specified range not supported");
2484 * Validate IPV6 fragment extension item.
2487 * Item specification.
2488 * @param[in] item_flags
2489 * Bit-fields that holds the items detected until now.
2491 * Pointer to error structure.
2494 * 0 on success, a negative errno value otherwise and rte_errno is set.
2497 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2498 uint64_t item_flags,
2499 struct rte_flow_error *error)
2501 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2502 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2503 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2504 rte_be16_t frag_data_spec = 0;
2505 rte_be16_t frag_data_last = 0;
2506 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2507 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2508 MLX5_FLOW_LAYER_OUTER_L4;
2510 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2512 .next_header = 0xff,
2513 .frag_data = RTE_BE16(0xffff),
2517 if (item_flags & l4m)
2518 return rte_flow_error_set(error, EINVAL,
2519 RTE_FLOW_ERROR_TYPE_ITEM, item,
2520 "ipv6 fragment extension item cannot "
2522 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2523 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2524 return rte_flow_error_set(error, EINVAL,
2525 RTE_FLOW_ERROR_TYPE_ITEM, item,
2526 "ipv6 fragment extension item must "
2527 "follow ipv6 item");
2529 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2530 if (!frag_data_spec)
2533 * spec and mask are valid, enforce using full mask to make sure the
2534 * complete value is used correctly.
2536 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2537 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2538 return rte_flow_error_set(error, EINVAL,
2539 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2540 item, "must use full mask for"
2543 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2544 * This is 1st fragment of fragmented packet.
2546 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2547 return rte_flow_error_set(error, ENOTSUP,
2548 RTE_FLOW_ERROR_TYPE_ITEM, item,
2549 "match on first fragment not "
2551 if (frag_data_spec && !last)
2552 return rte_flow_error_set(error, EINVAL,
2553 RTE_FLOW_ERROR_TYPE_ITEM, item,
2554 "specified value not supported");
2555 ret = mlx5_flow_item_acceptable
2556 (item, (const uint8_t *)mask,
2557 (const uint8_t *)&nic_mask,
2558 sizeof(struct rte_flow_item_ipv6_frag_ext),
2559 MLX5_ITEM_RANGE_ACCEPTED, error);
2562 /* spec and last are valid, validate the specified range. */
2563 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2565 * Match on frag_data spec 0x0009 and last 0xfff9
2566 * means M is 1 and frag-offset is > 0.
2567 * This packet is fragment 2nd and onward, excluding last.
2568 * This is not yet supported in MLX5, return appropriate
2571 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2572 RTE_IPV6_EHDR_MF_MASK) &&
2573 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2574 return rte_flow_error_set(error, ENOTSUP,
2575 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2576 last, "match on following "
2577 "fragments not supported");
2579 * Match on frag_data spec 0x0008 and last 0xfff8
2580 * means M is 0 and frag-offset is > 0.
2581 * This packet is last fragment of fragmented packet.
2582 * This is not yet supported in MLX5, return appropriate
2585 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2586 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2587 return rte_flow_error_set(error, ENOTSUP,
2588 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2589 last, "match on last "
2590 "fragment not supported");
2591 /* Other range values are invalid and rejected. */
2592 return rte_flow_error_set(error, EINVAL,
2593 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2594 "specified range not supported");
2598 * Validate the pop VLAN action.
2601 * Pointer to the rte_eth_dev structure.
2602 * @param[in] action_flags
2603 * Holds the actions detected until now.
2605 * Pointer to the pop vlan action.
2606 * @param[in] item_flags
2607 * The items found in this flow rule.
2609 * Pointer to flow attributes.
2611 * Pointer to error structure.
2614 * 0 on success, a negative errno value otherwise and rte_errno is set.
2617 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2618 uint64_t action_flags,
2619 const struct rte_flow_action *action,
2620 uint64_t item_flags,
2621 const struct rte_flow_attr *attr,
2622 struct rte_flow_error *error)
2624 const struct mlx5_priv *priv = dev->data->dev_private;
2628 if (!priv->sh->pop_vlan_action)
2629 return rte_flow_error_set(error, ENOTSUP,
2630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2632 "pop vlan action is not supported");
2634 return rte_flow_error_set(error, ENOTSUP,
2635 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2637 "pop vlan action not supported for "
2639 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2640 return rte_flow_error_set(error, ENOTSUP,
2641 RTE_FLOW_ERROR_TYPE_ACTION, action,
2642 "no support for multiple VLAN "
2644 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2645 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2646 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2647 return rte_flow_error_set(error, ENOTSUP,
2648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2650 "cannot pop vlan after decap without "
2651 "match on inner vlan in the flow");
2652 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2653 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2654 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2655 return rte_flow_error_set(error, ENOTSUP,
2656 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2658 "cannot pop vlan without a "
2659 "match on (outer) vlan in the flow");
2660 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2661 return rte_flow_error_set(error, EINVAL,
2662 RTE_FLOW_ERROR_TYPE_ACTION, action,
2663 "wrong action order, port_id should "
2664 "be after pop VLAN action");
2665 if (!attr->transfer && priv->representor)
2666 return rte_flow_error_set(error, ENOTSUP,
2667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2668 "pop vlan action for VF representor "
2669 "not supported on NIC table");
2674 * Get VLAN default info from vlan match info.
2677 * the list of item specifications.
2679 * pointer VLAN info to fill to.
2682 * 0 on success, a negative errno value otherwise and rte_errno is set.
2685 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2686 struct rte_vlan_hdr *vlan)
2688 const struct rte_flow_item_vlan nic_mask = {
2689 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2690 MLX5DV_FLOW_VLAN_VID_MASK),
2691 .inner_type = RTE_BE16(0xffff),
2696 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2697 int type = items->type;
2699 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2700 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2703 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2704 const struct rte_flow_item_vlan *vlan_m = items->mask;
2705 const struct rte_flow_item_vlan *vlan_v = items->spec;
2707 /* If VLAN item in pattern doesn't contain data, return here. */
2712 /* Only full match values are accepted */
2713 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2714 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2715 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2717 rte_be_to_cpu_16(vlan_v->tci &
2718 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2720 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2721 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2722 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2724 rte_be_to_cpu_16(vlan_v->tci &
2725 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2727 if (vlan_m->inner_type == nic_mask.inner_type)
2728 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2729 vlan_m->inner_type);
2734 * Validate the push VLAN action.
2737 * Pointer to the rte_eth_dev structure.
2738 * @param[in] action_flags
2739 * Holds the actions detected until now.
2740 * @param[in] item_flags
2741 * The items found in this flow rule.
2743 * Pointer to the action structure.
2745 * Pointer to flow attributes
2747 * Pointer to error structure.
2750 * 0 on success, a negative errno value otherwise and rte_errno is set.
2753 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2754 uint64_t action_flags,
2755 const struct rte_flow_item_vlan *vlan_m,
2756 const struct rte_flow_action *action,
2757 const struct rte_flow_attr *attr,
2758 struct rte_flow_error *error)
2760 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2761 const struct mlx5_priv *priv = dev->data->dev_private;
2763 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2764 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2765 return rte_flow_error_set(error, EINVAL,
2766 RTE_FLOW_ERROR_TYPE_ACTION, action,
2767 "invalid vlan ethertype");
2768 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2769 return rte_flow_error_set(error, EINVAL,
2770 RTE_FLOW_ERROR_TYPE_ACTION, action,
2771 "wrong action order, port_id should "
2772 "be after push VLAN");
2773 if (!attr->transfer && priv->representor)
2774 return rte_flow_error_set(error, ENOTSUP,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776 "push vlan action for VF representor "
2777 "not supported on NIC table");
2779 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2780 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2781 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2782 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2783 !(mlx5_flow_find_action
2784 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2785 return rte_flow_error_set(error, EINVAL,
2786 RTE_FLOW_ERROR_TYPE_ACTION, action,
2787 "not full match mask on VLAN PCP and "
2788 "there is no of_set_vlan_pcp action, "
2789 "push VLAN action cannot figure out "
2792 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2793 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2794 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2795 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2796 !(mlx5_flow_find_action
2797 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2798 return rte_flow_error_set(error, EINVAL,
2799 RTE_FLOW_ERROR_TYPE_ACTION, action,
2800 "not full match mask on VLAN VID and "
2801 "there is no of_set_vlan_vid action, "
2802 "push VLAN action cannot figure out "
2809 * Validate the set VLAN PCP.
2811 * @param[in] action_flags
2812 * Holds the actions detected until now.
2813 * @param[in] actions
2814 * Pointer to the list of actions remaining in the flow rule.
2816 * Pointer to error structure.
2819 * 0 on success, a negative errno value otherwise and rte_errno is set.
2822 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2823 const struct rte_flow_action actions[],
2824 struct rte_flow_error *error)
2826 const struct rte_flow_action *action = actions;
2827 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2829 if (conf->vlan_pcp > 7)
2830 return rte_flow_error_set(error, EINVAL,
2831 RTE_FLOW_ERROR_TYPE_ACTION, action,
2832 "VLAN PCP value is too big");
2833 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2834 return rte_flow_error_set(error, ENOTSUP,
2835 RTE_FLOW_ERROR_TYPE_ACTION, action,
2836 "set VLAN PCP action must follow "
2837 "the push VLAN action");
2838 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2839 return rte_flow_error_set(error, ENOTSUP,
2840 RTE_FLOW_ERROR_TYPE_ACTION, action,
2841 "Multiple VLAN PCP modification are "
2843 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2844 return rte_flow_error_set(error, EINVAL,
2845 RTE_FLOW_ERROR_TYPE_ACTION, action,
2846 "wrong action order, port_id should "
2847 "be after set VLAN PCP");
2852 * Validate the set VLAN VID.
2854 * @param[in] item_flags
2855 * Holds the items detected in this rule.
2856 * @param[in] action_flags
2857 * Holds the actions detected until now.
2858 * @param[in] actions
2859 * Pointer to the list of actions remaining in the flow rule.
2861 * Pointer to error structure.
2864 * 0 on success, a negative errno value otherwise and rte_errno is set.
2867 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2868 uint64_t action_flags,
2869 const struct rte_flow_action actions[],
2870 struct rte_flow_error *error)
2872 const struct rte_flow_action *action = actions;
2873 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2875 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2876 return rte_flow_error_set(error, EINVAL,
2877 RTE_FLOW_ERROR_TYPE_ACTION, action,
2878 "VLAN VID value is too big");
2879 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2880 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2881 return rte_flow_error_set(error, ENOTSUP,
2882 RTE_FLOW_ERROR_TYPE_ACTION, action,
2883 "set VLAN VID action must follow push"
2884 " VLAN action or match on VLAN item");
2885 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2886 return rte_flow_error_set(error, ENOTSUP,
2887 RTE_FLOW_ERROR_TYPE_ACTION, action,
2888 "Multiple VLAN VID modifications are "
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after set VLAN VID");
2899 * Validate the FLAG action.
2902 * Pointer to the rte_eth_dev structure.
2903 * @param[in] action_flags
2904 * Holds the actions detected until now.
2906 * Pointer to flow attributes
2908 * Pointer to error structure.
2911 * 0 on success, a negative errno value otherwise and rte_errno is set.
2914 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2915 uint64_t action_flags,
2916 const struct rte_flow_attr *attr,
2917 struct rte_flow_error *error)
2919 struct mlx5_priv *priv = dev->data->dev_private;
2920 struct mlx5_dev_config *config = &priv->config;
2923 /* Fall back if no extended metadata register support. */
2924 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2925 return mlx5_flow_validate_action_flag(action_flags, attr,
2927 /* Extensive metadata mode requires registers. */
2928 if (!mlx5_flow_ext_mreg_supported(dev))
2929 return rte_flow_error_set(error, ENOTSUP,
2930 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2931 "no metadata registers "
2932 "to support flag action");
2933 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2934 return rte_flow_error_set(error, ENOTSUP,
2935 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2936 "extended metadata register"
2937 " isn't available");
2938 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2941 MLX5_ASSERT(ret > 0);
2942 if (action_flags & MLX5_FLOW_ACTION_MARK)
2943 return rte_flow_error_set(error, EINVAL,
2944 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2945 "can't mark and flag in same flow");
2946 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2947 return rte_flow_error_set(error, EINVAL,
2948 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2950 " actions in same flow");
2955 * Validate MARK action.
2958 * Pointer to the rte_eth_dev structure.
2960 * Pointer to action.
2961 * @param[in] action_flags
2962 * Holds the actions detected until now.
2964 * Pointer to flow attributes
2966 * Pointer to error structure.
2969 * 0 on success, a negative errno value otherwise and rte_errno is set.
2972 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2973 const struct rte_flow_action *action,
2974 uint64_t action_flags,
2975 const struct rte_flow_attr *attr,
2976 struct rte_flow_error *error)
2978 struct mlx5_priv *priv = dev->data->dev_private;
2979 struct mlx5_dev_config *config = &priv->config;
2980 const struct rte_flow_action_mark *mark = action->conf;
2983 if (is_tunnel_offload_active(dev))
2984 return rte_flow_error_set(error, ENOTSUP,
2985 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2987 "if tunnel offload active");
2988 /* Fall back if no extended metadata register support. */
2989 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2990 return mlx5_flow_validate_action_mark(action, action_flags,
2992 /* Extensive metadata mode requires registers. */
2993 if (!mlx5_flow_ext_mreg_supported(dev))
2994 return rte_flow_error_set(error, ENOTSUP,
2995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2996 "no metadata registers "
2997 "to support mark action");
2998 if (!priv->sh->dv_mark_mask)
2999 return rte_flow_error_set(error, ENOTSUP,
3000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3001 "extended metadata register"
3002 " isn't available");
3003 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3006 MLX5_ASSERT(ret > 0);
3008 return rte_flow_error_set(error, EINVAL,
3009 RTE_FLOW_ERROR_TYPE_ACTION, action,
3010 "configuration cannot be null");
3011 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3012 return rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3015 "mark id exceeds the limit");
3016 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3019 "can't flag and mark in same flow");
3020 if (action_flags & MLX5_FLOW_ACTION_MARK)
3021 return rte_flow_error_set(error, EINVAL,
3022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3023 "can't have 2 mark actions in same"
3029 * Validate SET_META action.
3032 * Pointer to the rte_eth_dev structure.
3034 * Pointer to the action structure.
3035 * @param[in] action_flags
3036 * Holds the actions detected until now.
3038 * Pointer to flow attributes
3040 * Pointer to error structure.
3043 * 0 on success, a negative errno value otherwise and rte_errno is set.
3046 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3047 const struct rte_flow_action *action,
3048 uint64_t action_flags __rte_unused,
3049 const struct rte_flow_attr *attr,
3050 struct rte_flow_error *error)
3052 const struct rte_flow_action_set_meta *conf;
3053 uint32_t nic_mask = UINT32_MAX;
3056 if (!mlx5_flow_ext_mreg_supported(dev))
3057 return rte_flow_error_set(error, ENOTSUP,
3058 RTE_FLOW_ERROR_TYPE_ACTION, action,
3059 "extended metadata register"
3060 " isn't supported");
3061 reg = flow_dv_get_metadata_reg(dev, attr, error);
3065 return rte_flow_error_set(error, ENOTSUP,
3066 RTE_FLOW_ERROR_TYPE_ACTION, action,
3067 "unavalable extended metadata register");
3068 if (reg != REG_A && reg != REG_B) {
3069 struct mlx5_priv *priv = dev->data->dev_private;
3071 nic_mask = priv->sh->dv_meta_mask;
3073 if (!(action->conf))
3074 return rte_flow_error_set(error, EINVAL,
3075 RTE_FLOW_ERROR_TYPE_ACTION, action,
3076 "configuration cannot be null");
3077 conf = (const struct rte_flow_action_set_meta *)action->conf;
3079 return rte_flow_error_set(error, EINVAL,
3080 RTE_FLOW_ERROR_TYPE_ACTION, action,
3081 "zero mask doesn't have any effect");
3082 if (conf->mask & ~nic_mask)
3083 return rte_flow_error_set(error, EINVAL,
3084 RTE_FLOW_ERROR_TYPE_ACTION, action,
3085 "meta data must be within reg C0");
3090 * Validate SET_TAG action.
3093 * Pointer to the rte_eth_dev structure.
3095 * Pointer to the action structure.
3096 * @param[in] action_flags
3097 * Holds the actions detected until now.
3099 * Pointer to flow attributes
3101 * Pointer to error structure.
3104 * 0 on success, a negative errno value otherwise and rte_errno is set.
3107 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3108 const struct rte_flow_action *action,
3109 uint64_t action_flags,
3110 const struct rte_flow_attr *attr,
3111 struct rte_flow_error *error)
3113 const struct rte_flow_action_set_tag *conf;
3114 const uint64_t terminal_action_flags =
3115 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3116 MLX5_FLOW_ACTION_RSS;
3119 if (!mlx5_flow_ext_mreg_supported(dev))
3120 return rte_flow_error_set(error, ENOTSUP,
3121 RTE_FLOW_ERROR_TYPE_ACTION, action,
3122 "extensive metadata register"
3123 " isn't supported");
3124 if (!(action->conf))
3125 return rte_flow_error_set(error, EINVAL,
3126 RTE_FLOW_ERROR_TYPE_ACTION, action,
3127 "configuration cannot be null");
3128 conf = (const struct rte_flow_action_set_tag *)action->conf;
3130 return rte_flow_error_set(error, EINVAL,
3131 RTE_FLOW_ERROR_TYPE_ACTION, action,
3132 "zero mask doesn't have any effect");
3133 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3136 if (!attr->transfer && attr->ingress &&
3137 (action_flags & terminal_action_flags))
3138 return rte_flow_error_set(error, EINVAL,
3139 RTE_FLOW_ERROR_TYPE_ACTION, action,
3140 "set_tag has no effect"
3141 " with terminal actions");
3146 * Validate count action.
3149 * Pointer to rte_eth_dev structure.
3151 * Pointer to the action structure.
3152 * @param[in] action_flags
3153 * Holds the actions detected until now.
3155 * Pointer to error structure.
3158 * 0 on success, a negative errno value otherwise and rte_errno is set.
3161 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3162 const struct rte_flow_action *action,
3163 uint64_t action_flags,
3164 struct rte_flow_error *error)
3166 struct mlx5_priv *priv = dev->data->dev_private;
3167 const struct rte_flow_action_count *count;
3169 if (!priv->config.devx)
3171 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3172 return rte_flow_error_set(error, EINVAL,
3173 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3174 "duplicate count actions set");
3175 count = (const struct rte_flow_action_count *)action->conf;
3176 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3177 !priv->sh->flow_hit_aso_en)
3178 return rte_flow_error_set(error, EINVAL,
3179 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3180 "old age and shared count combination is not supported");
3181 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3185 return rte_flow_error_set
3187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3189 "count action not supported");
3193 * Validate the L2 encap action.
3196 * Pointer to the rte_eth_dev structure.
3197 * @param[in] action_flags
3198 * Holds the actions detected until now.
3200 * Pointer to the action structure.
3202 * Pointer to flow attributes.
3204 * Pointer to error structure.
3207 * 0 on success, a negative errno value otherwise and rte_errno is set.
3210 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3211 uint64_t action_flags,
3212 const struct rte_flow_action *action,
3213 const struct rte_flow_attr *attr,
3214 struct rte_flow_error *error)
3216 const struct mlx5_priv *priv = dev->data->dev_private;
3218 if (!(action->conf))
3219 return rte_flow_error_set(error, EINVAL,
3220 RTE_FLOW_ERROR_TYPE_ACTION, action,
3221 "configuration cannot be null");
3222 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3223 return rte_flow_error_set(error, EINVAL,
3224 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3225 "can only have a single encap action "
3227 if (!attr->transfer && priv->representor)
3228 return rte_flow_error_set(error, ENOTSUP,
3229 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3230 "encap action for VF representor "
3231 "not supported on NIC table");
3236 * Validate a decap action.
3239 * Pointer to the rte_eth_dev structure.
3240 * @param[in] action_flags
3241 * Holds the actions detected until now.
3243 * Pointer to the action structure.
3244 * @param[in] item_flags
3245 * Holds the items detected.
3247 * Pointer to flow attributes
3249 * Pointer to error structure.
3252 * 0 on success, a negative errno value otherwise and rte_errno is set.
3255 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3256 uint64_t action_flags,
3257 const struct rte_flow_action *action,
3258 const uint64_t item_flags,
3259 const struct rte_flow_attr *attr,
3260 struct rte_flow_error *error)
3262 const struct mlx5_priv *priv = dev->data->dev_private;
3264 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3265 !priv->config.decap_en)
3266 return rte_flow_error_set(error, ENOTSUP,
3267 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3268 "decap is not enabled");
3269 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3270 return rte_flow_error_set(error, ENOTSUP,
3271 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3273 MLX5_FLOW_ACTION_DECAP ? "can only "
3274 "have a single decap action" : "decap "
3275 "after encap is not supported");
3276 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3277 return rte_flow_error_set(error, EINVAL,
3278 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3279 "can't have decap action after"
3282 return rte_flow_error_set(error, ENOTSUP,
3283 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3285 "decap action not supported for "
3287 if (!attr->transfer && priv->representor)
3288 return rte_flow_error_set(error, ENOTSUP,
3289 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3290 "decap action for VF representor "
3291 "not supported on NIC table");
3292 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3293 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3294 return rte_flow_error_set(error, ENOTSUP,
3295 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3296 "VXLAN item should be present for VXLAN decap");
3300 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3303 * Validate the raw encap and decap actions.
3306 * Pointer to the rte_eth_dev structure.
3308 * Pointer to the decap action.
3310 * Pointer to the encap action.
3312 * Pointer to flow attributes
3313 * @param[in/out] action_flags
3314 * Holds the actions detected until now.
3315 * @param[out] actions_n
3316 * pointer to the number of actions counter.
3318 * Pointer to the action structure.
3319 * @param[in] item_flags
3320 * Holds the items detected.
3322 * Pointer to error structure.
3325 * 0 on success, a negative errno value otherwise and rte_errno is set.
3328 flow_dv_validate_action_raw_encap_decap
3329 (struct rte_eth_dev *dev,
3330 const struct rte_flow_action_raw_decap *decap,
3331 const struct rte_flow_action_raw_encap *encap,
3332 const struct rte_flow_attr *attr, uint64_t *action_flags,
3333 int *actions_n, const struct rte_flow_action *action,
3334 uint64_t item_flags, struct rte_flow_error *error)
3336 const struct mlx5_priv *priv = dev->data->dev_private;
3339 if (encap && (!encap->size || !encap->data))
3340 return rte_flow_error_set(error, EINVAL,
3341 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3342 "raw encap data cannot be empty");
3343 if (decap && encap) {
3344 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3345 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3348 else if (encap->size <=
3349 MLX5_ENCAPSULATION_DECISION_SIZE &&
3351 MLX5_ENCAPSULATION_DECISION_SIZE)
3354 else if (encap->size >
3355 MLX5_ENCAPSULATION_DECISION_SIZE &&
3357 MLX5_ENCAPSULATION_DECISION_SIZE)
3358 /* 2 L2 actions: encap and decap. */
3361 return rte_flow_error_set(error,
3363 RTE_FLOW_ERROR_TYPE_ACTION,
3364 NULL, "unsupported too small "
3365 "raw decap and too small raw "
3366 "encap combination");
3369 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3370 item_flags, attr, error);
3373 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3377 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3378 return rte_flow_error_set(error, ENOTSUP,
3379 RTE_FLOW_ERROR_TYPE_ACTION,
3381 "small raw encap size");
3382 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3383 return rte_flow_error_set(error, EINVAL,
3384 RTE_FLOW_ERROR_TYPE_ACTION,
3386 "more than one encap action");
3387 if (!attr->transfer && priv->representor)
3388 return rte_flow_error_set
3390 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3391 "encap action for VF representor "
3392 "not supported on NIC table");
3393 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3400 * Match encap_decap resource.
3403 * Pointer to the hash list.
3405 * Pointer to exist resource entry object.
3407 * Key of the new entry.
3409 * Pointer to new encap_decap resource.
3412 * 0 on matching, none-zero otherwise.
3415 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3416 struct mlx5_hlist_entry *entry,
3417 uint64_t key __rte_unused, void *cb_ctx)
3419 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3420 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3421 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3423 cache_resource = container_of(entry,
3424 struct mlx5_flow_dv_encap_decap_resource,
3426 if (resource->reformat_type == cache_resource->reformat_type &&
3427 resource->ft_type == cache_resource->ft_type &&
3428 resource->flags == cache_resource->flags &&
3429 resource->size == cache_resource->size &&
3430 !memcmp((const void *)resource->buf,
3431 (const void *)cache_resource->buf,
3438 * Allocate encap_decap resource.
3441 * Pointer to the hash list.
3443 * Pointer to exist resource entry object.
3445 * Pointer to new encap_decap resource.
3448 * 0 on matching, none-zero otherwise.
3450 struct mlx5_hlist_entry *
3451 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3452 uint64_t key __rte_unused,
3455 struct mlx5_dev_ctx_shared *sh = list->ctx;
3456 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3457 struct mlx5dv_dr_domain *domain;
3458 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3459 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3463 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3464 domain = sh->fdb_domain;
3465 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3466 domain = sh->rx_domain;
3468 domain = sh->tx_domain;
3469 /* Register new encap/decap resource. */
3470 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3472 if (!cache_resource) {
3473 rte_flow_error_set(ctx->error, ENOMEM,
3474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3475 "cannot allocate resource memory");
3478 *cache_resource = *resource;
3479 cache_resource->idx = idx;
3480 ret = mlx5_flow_os_create_flow_action_packet_reformat
3481 (sh->ctx, domain, cache_resource,
3482 &cache_resource->action);
3484 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3485 rte_flow_error_set(ctx->error, ENOMEM,
3486 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3487 NULL, "cannot create action");
3491 return &cache_resource->entry;
3495 * Find existing encap/decap resource or create and register a new one.
3497 * @param[in, out] dev
3498 * Pointer to rte_eth_dev structure.
3499 * @param[in, out] resource
3500 * Pointer to encap/decap resource.
3501 * @parm[in, out] dev_flow
3502 * Pointer to the dev_flow.
3504 * pointer to error structure.
3507 * 0 on success otherwise -errno and errno is set.
3510 flow_dv_encap_decap_resource_register
3511 (struct rte_eth_dev *dev,
3512 struct mlx5_flow_dv_encap_decap_resource *resource,
3513 struct mlx5_flow *dev_flow,
3514 struct rte_flow_error *error)
3516 struct mlx5_priv *priv = dev->data->dev_private;
3517 struct mlx5_dev_ctx_shared *sh = priv->sh;
3518 struct mlx5_hlist_entry *entry;
3522 uint32_t refmt_type:8;
3524 * Header reformat actions can be shared between
3525 * non-root tables. One bit to indicate non-root
3529 uint32_t reserve:15;
3532 } encap_decap_key = {
3534 .ft_type = resource->ft_type,
3535 .refmt_type = resource->reformat_type,
3536 .is_root = !!dev_flow->dv.group,
3540 struct mlx5_flow_cb_ctx ctx = {
3546 resource->flags = dev_flow->dv.group ? 0 : 1;
3547 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3548 sizeof(encap_decap_key.v32), 0);
3549 if (resource->reformat_type !=
3550 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3552 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3553 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3556 resource = container_of(entry, typeof(*resource), entry);
3557 dev_flow->dv.encap_decap = resource;
3558 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3563 * Find existing table jump resource or create and register a new one.
3565 * @param[in, out] dev
3566 * Pointer to rte_eth_dev structure.
3567 * @param[in, out] tbl
3568 * Pointer to flow table resource.
3569 * @parm[in, out] dev_flow
3570 * Pointer to the dev_flow.
3572 * pointer to error structure.
3575 * 0 on success otherwise -errno and errno is set.
3578 flow_dv_jump_tbl_resource_register
3579 (struct rte_eth_dev *dev __rte_unused,
3580 struct mlx5_flow_tbl_resource *tbl,
3581 struct mlx5_flow *dev_flow,
3582 struct rte_flow_error *error __rte_unused)
3584 struct mlx5_flow_tbl_data_entry *tbl_data =
3585 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3588 MLX5_ASSERT(tbl_data->jump.action);
3589 dev_flow->handle->rix_jump = tbl_data->idx;
3590 dev_flow->dv.jump = &tbl_data->jump;
3595 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3596 struct mlx5_cache_entry *entry, void *cb_ctx)
3598 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3599 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3600 struct mlx5_flow_dv_port_id_action_resource *res =
3601 container_of(entry, typeof(*res), entry);
3603 return ref->port_id != res->port_id;
3606 struct mlx5_cache_entry *
3607 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3608 struct mlx5_cache_entry *entry __rte_unused,
3611 struct mlx5_dev_ctx_shared *sh = list->ctx;
3612 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3613 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3614 struct mlx5_flow_dv_port_id_action_resource *cache;
3618 /* Register new port id action resource. */
3619 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3621 rte_flow_error_set(ctx->error, ENOMEM,
3622 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3623 "cannot allocate port_id action cache memory");
3627 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3631 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3632 rte_flow_error_set(ctx->error, ENOMEM,
3633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3634 "cannot create action");
3638 return &cache->entry;
3642 * Find existing table port ID resource or create and register a new one.
3644 * @param[in, out] dev
3645 * Pointer to rte_eth_dev structure.
3646 * @param[in, out] resource
3647 * Pointer to port ID action resource.
3648 * @parm[in, out] dev_flow
3649 * Pointer to the dev_flow.
3651 * pointer to error structure.
3654 * 0 on success otherwise -errno and errno is set.
3657 flow_dv_port_id_action_resource_register
3658 (struct rte_eth_dev *dev,
3659 struct mlx5_flow_dv_port_id_action_resource *resource,
3660 struct mlx5_flow *dev_flow,
3661 struct rte_flow_error *error)
3663 struct mlx5_priv *priv = dev->data->dev_private;
3664 struct mlx5_cache_entry *entry;
3665 struct mlx5_flow_dv_port_id_action_resource *cache;
3666 struct mlx5_flow_cb_ctx ctx = {
3671 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3674 cache = container_of(entry, typeof(*cache), entry);
3675 dev_flow->dv.port_id_action = cache;
3676 dev_flow->handle->rix_port_id_action = cache->idx;
3681 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3682 struct mlx5_cache_entry *entry, void *cb_ctx)
3684 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3685 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3686 struct mlx5_flow_dv_push_vlan_action_resource *res =
3687 container_of(entry, typeof(*res), entry);
3689 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3692 struct mlx5_cache_entry *
3693 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3694 struct mlx5_cache_entry *entry __rte_unused,
3697 struct mlx5_dev_ctx_shared *sh = list->ctx;
3698 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3699 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3700 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3701 struct mlx5dv_dr_domain *domain;
3705 /* Register new port id action resource. */
3706 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3708 rte_flow_error_set(ctx->error, ENOMEM,
3709 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3710 "cannot allocate push_vlan action cache memory");
3714 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3715 domain = sh->fdb_domain;
3716 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3717 domain = sh->rx_domain;
3719 domain = sh->tx_domain;
3720 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3723 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3724 rte_flow_error_set(ctx->error, ENOMEM,
3725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3726 "cannot create push vlan action");
3730 return &cache->entry;
3734 * Find existing push vlan resource or create and register a new one.
3736 * @param [in, out] dev
3737 * Pointer to rte_eth_dev structure.
3738 * @param[in, out] resource
3739 * Pointer to port ID action resource.
3740 * @parm[in, out] dev_flow
3741 * Pointer to the dev_flow.
3743 * pointer to error structure.
3746 * 0 on success otherwise -errno and errno is set.
3749 flow_dv_push_vlan_action_resource_register
3750 (struct rte_eth_dev *dev,
3751 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3752 struct mlx5_flow *dev_flow,
3753 struct rte_flow_error *error)
3755 struct mlx5_priv *priv = dev->data->dev_private;
3756 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3757 struct mlx5_cache_entry *entry;
3758 struct mlx5_flow_cb_ctx ctx = {
3763 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3766 cache = container_of(entry, typeof(*cache), entry);
3768 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3769 dev_flow->dv.push_vlan_res = cache;
3774 * Get the size of specific rte_flow_item_type hdr size
3776 * @param[in] item_type
3777 * Tested rte_flow_item_type.
3780 * sizeof struct item_type, 0 if void or irrelevant.
3783 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3787 switch (item_type) {
3788 case RTE_FLOW_ITEM_TYPE_ETH:
3789 retval = sizeof(struct rte_ether_hdr);
3791 case RTE_FLOW_ITEM_TYPE_VLAN:
3792 retval = sizeof(struct rte_vlan_hdr);
3794 case RTE_FLOW_ITEM_TYPE_IPV4:
3795 retval = sizeof(struct rte_ipv4_hdr);
3797 case RTE_FLOW_ITEM_TYPE_IPV6:
3798 retval = sizeof(struct rte_ipv6_hdr);
3800 case RTE_FLOW_ITEM_TYPE_UDP:
3801 retval = sizeof(struct rte_udp_hdr);
3803 case RTE_FLOW_ITEM_TYPE_TCP:
3804 retval = sizeof(struct rte_tcp_hdr);
3806 case RTE_FLOW_ITEM_TYPE_VXLAN:
3807 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3808 retval = sizeof(struct rte_vxlan_hdr);
3810 case RTE_FLOW_ITEM_TYPE_GRE:
3811 case RTE_FLOW_ITEM_TYPE_NVGRE:
3812 retval = sizeof(struct rte_gre_hdr);
3814 case RTE_FLOW_ITEM_TYPE_MPLS:
3815 retval = sizeof(struct rte_mpls_hdr);
3817 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3825 #define MLX5_ENCAP_IPV4_VERSION 0x40
3826 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3827 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3828 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3829 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3830 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3831 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3834 * Convert the encap action data from list of rte_flow_item to raw buffer
3837 * Pointer to rte_flow_item objects list.
3839 * Pointer to the output buffer.
3841 * Pointer to the output buffer size.
3843 * Pointer to the error structure.
3846 * 0 on success, a negative errno value otherwise and rte_errno is set.
3849 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3850 size_t *size, struct rte_flow_error *error)
3852 struct rte_ether_hdr *eth = NULL;
3853 struct rte_vlan_hdr *vlan = NULL;
3854 struct rte_ipv4_hdr *ipv4 = NULL;
3855 struct rte_ipv6_hdr *ipv6 = NULL;
3856 struct rte_udp_hdr *udp = NULL;
3857 struct rte_vxlan_hdr *vxlan = NULL;
3858 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3859 struct rte_gre_hdr *gre = NULL;
3861 size_t temp_size = 0;
3864 return rte_flow_error_set(error, EINVAL,
3865 RTE_FLOW_ERROR_TYPE_ACTION,
3866 NULL, "invalid empty data");
3867 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3868 len = flow_dv_get_item_hdr_len(items->type);
3869 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3870 return rte_flow_error_set(error, EINVAL,
3871 RTE_FLOW_ERROR_TYPE_ACTION,
3872 (void *)items->type,
3873 "items total size is too big"
3874 " for encap action");
3875 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3876 switch (items->type) {
3877 case RTE_FLOW_ITEM_TYPE_ETH:
3878 eth = (struct rte_ether_hdr *)&buf[temp_size];
3880 case RTE_FLOW_ITEM_TYPE_VLAN:
3881 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3883 return rte_flow_error_set(error, EINVAL,
3884 RTE_FLOW_ERROR_TYPE_ACTION,
3885 (void *)items->type,
3886 "eth header not found");
3887 if (!eth->ether_type)
3888 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3890 case RTE_FLOW_ITEM_TYPE_IPV4:
3891 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3893 return rte_flow_error_set(error, EINVAL,
3894 RTE_FLOW_ERROR_TYPE_ACTION,
3895 (void *)items->type,
3896 "neither eth nor vlan"
3898 if (vlan && !vlan->eth_proto)
3899 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3900 else if (eth && !eth->ether_type)
3901 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902 if (!ipv4->version_ihl)
3903 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3904 MLX5_ENCAP_IPV4_IHL_MIN;
3905 if (!ipv4->time_to_live)
3906 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3908 case RTE_FLOW_ITEM_TYPE_IPV6:
3909 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3911 return rte_flow_error_set(error, EINVAL,
3912 RTE_FLOW_ERROR_TYPE_ACTION,
3913 (void *)items->type,
3914 "neither eth nor vlan"
3916 if (vlan && !vlan->eth_proto)
3917 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3918 else if (eth && !eth->ether_type)
3919 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920 if (!ipv6->vtc_flow)
3922 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3923 if (!ipv6->hop_limits)
3924 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3926 case RTE_FLOW_ITEM_TYPE_UDP:
3927 udp = (struct rte_udp_hdr *)&buf[temp_size];
3929 return rte_flow_error_set(error, EINVAL,
3930 RTE_FLOW_ERROR_TYPE_ACTION,
3931 (void *)items->type,
3932 "ip header not found");
3933 if (ipv4 && !ipv4->next_proto_id)
3934 ipv4->next_proto_id = IPPROTO_UDP;
3935 else if (ipv6 && !ipv6->proto)
3936 ipv6->proto = IPPROTO_UDP;
3938 case RTE_FLOW_ITEM_TYPE_VXLAN:
3939 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3941 return rte_flow_error_set(error, EINVAL,
3942 RTE_FLOW_ERROR_TYPE_ACTION,
3943 (void *)items->type,
3944 "udp header not found");
3946 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3947 if (!vxlan->vx_flags)
3949 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3951 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3952 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3954 return rte_flow_error_set(error, EINVAL,
3955 RTE_FLOW_ERROR_TYPE_ACTION,
3956 (void *)items->type,
3957 "udp header not found");
3958 if (!vxlan_gpe->proto)
3959 return rte_flow_error_set(error, EINVAL,
3960 RTE_FLOW_ERROR_TYPE_ACTION,
3961 (void *)items->type,
3962 "next protocol not found");
3965 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3966 if (!vxlan_gpe->vx_flags)
3967 vxlan_gpe->vx_flags =
3968 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3970 case RTE_FLOW_ITEM_TYPE_GRE:
3971 case RTE_FLOW_ITEM_TYPE_NVGRE:
3972 gre = (struct rte_gre_hdr *)&buf[temp_size];
3974 return rte_flow_error_set(error, EINVAL,
3975 RTE_FLOW_ERROR_TYPE_ACTION,
3976 (void *)items->type,
3977 "next protocol not found");
3979 return rte_flow_error_set(error, EINVAL,
3980 RTE_FLOW_ERROR_TYPE_ACTION,
3981 (void *)items->type,
3982 "ip header not found");
3983 if (ipv4 && !ipv4->next_proto_id)
3984 ipv4->next_proto_id = IPPROTO_GRE;
3985 else if (ipv6 && !ipv6->proto)
3986 ipv6->proto = IPPROTO_GRE;
3988 case RTE_FLOW_ITEM_TYPE_VOID:
3991 return rte_flow_error_set(error, EINVAL,
3992 RTE_FLOW_ERROR_TYPE_ACTION,
3993 (void *)items->type,
3994 "unsupported item type");
4004 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4006 struct rte_ether_hdr *eth = NULL;
4007 struct rte_vlan_hdr *vlan = NULL;
4008 struct rte_ipv6_hdr *ipv6 = NULL;
4009 struct rte_udp_hdr *udp = NULL;
4013 eth = (struct rte_ether_hdr *)data;
4014 next_hdr = (char *)(eth + 1);
4015 proto = RTE_BE16(eth->ether_type);
4018 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4019 vlan = (struct rte_vlan_hdr *)next_hdr;
4020 proto = RTE_BE16(vlan->eth_proto);
4021 next_hdr += sizeof(struct rte_vlan_hdr);
4024 /* HW calculates IPv4 csum. no need to proceed */
4025 if (proto == RTE_ETHER_TYPE_IPV4)
4028 /* non IPv4/IPv6 header. not supported */
4029 if (proto != RTE_ETHER_TYPE_IPV6) {
4030 return rte_flow_error_set(error, ENOTSUP,
4031 RTE_FLOW_ERROR_TYPE_ACTION,
4032 NULL, "Cannot offload non IPv4/IPv6");
4035 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4037 /* ignore non UDP */
4038 if (ipv6->proto != IPPROTO_UDP)
4041 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4042 udp->dgram_cksum = 0;
4048 * Convert L2 encap action to DV specification.
4051 * Pointer to rte_eth_dev structure.
4053 * Pointer to action structure.
4054 * @param[in, out] dev_flow
4055 * Pointer to the mlx5_flow.
4056 * @param[in] transfer
4057 * Mark if the flow is E-Switch flow.
4059 * Pointer to the error structure.
4062 * 0 on success, a negative errno value otherwise and rte_errno is set.
4065 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4066 const struct rte_flow_action *action,
4067 struct mlx5_flow *dev_flow,
4069 struct rte_flow_error *error)
4071 const struct rte_flow_item *encap_data;
4072 const struct rte_flow_action_raw_encap *raw_encap_data;
4073 struct mlx5_flow_dv_encap_decap_resource res = {
4075 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4076 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4077 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4080 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4082 (const struct rte_flow_action_raw_encap *)action->conf;
4083 res.size = raw_encap_data->size;
4084 memcpy(res.buf, raw_encap_data->data, res.size);
4086 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4088 ((const struct rte_flow_action_vxlan_encap *)
4089 action->conf)->definition;
4092 ((const struct rte_flow_action_nvgre_encap *)
4093 action->conf)->definition;
4094 if (flow_dv_convert_encap_data(encap_data, res.buf,
4098 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4100 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4101 return rte_flow_error_set(error, EINVAL,
4102 RTE_FLOW_ERROR_TYPE_ACTION,
4103 NULL, "can't create L2 encap action");
4108 * Convert L2 decap action to DV specification.
4111 * Pointer to rte_eth_dev structure.
4112 * @param[in, out] dev_flow
4113 * Pointer to the mlx5_flow.
4114 * @param[in] transfer
4115 * Mark if the flow is E-Switch flow.
4117 * Pointer to the error structure.
4120 * 0 on success, a negative errno value otherwise and rte_errno is set.
4123 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4124 struct mlx5_flow *dev_flow,
4126 struct rte_flow_error *error)
4128 struct mlx5_flow_dv_encap_decap_resource res = {
4131 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4132 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4133 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4136 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4137 return rte_flow_error_set(error, EINVAL,
4138 RTE_FLOW_ERROR_TYPE_ACTION,
4139 NULL, "can't create L2 decap action");
4144 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4147 * Pointer to rte_eth_dev structure.
4149 * Pointer to action structure.
4150 * @param[in, out] dev_flow
4151 * Pointer to the mlx5_flow.
4153 * Pointer to the flow attributes.
4155 * Pointer to the error structure.
4158 * 0 on success, a negative errno value otherwise and rte_errno is set.
4161 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4162 const struct rte_flow_action *action,
4163 struct mlx5_flow *dev_flow,
4164 const struct rte_flow_attr *attr,
4165 struct rte_flow_error *error)
4167 const struct rte_flow_action_raw_encap *encap_data;
4168 struct mlx5_flow_dv_encap_decap_resource res;
4170 memset(&res, 0, sizeof(res));
4171 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4172 res.size = encap_data->size;
4173 memcpy(res.buf, encap_data->data, res.size);
4174 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4175 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4176 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4178 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4180 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4181 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4182 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4183 return rte_flow_error_set(error, EINVAL,
4184 RTE_FLOW_ERROR_TYPE_ACTION,
4185 NULL, "can't create encap action");
4190 * Create action push VLAN.
4193 * Pointer to rte_eth_dev structure.
4195 * Pointer to the flow attributes.
4197 * Pointer to the vlan to push to the Ethernet header.
4198 * @param[in, out] dev_flow
4199 * Pointer to the mlx5_flow.
4201 * Pointer to the error structure.
4204 * 0 on success, a negative errno value otherwise and rte_errno is set.
4207 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4208 const struct rte_flow_attr *attr,
4209 const struct rte_vlan_hdr *vlan,
4210 struct mlx5_flow *dev_flow,
4211 struct rte_flow_error *error)
4213 struct mlx5_flow_dv_push_vlan_action_resource res;
4215 memset(&res, 0, sizeof(res));
4217 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4220 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4222 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4223 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4224 return flow_dv_push_vlan_action_resource_register
4225 (dev, &res, dev_flow, error);
4229 * Validate the modify-header actions.
4231 * @param[in] action_flags
4232 * Holds the actions detected until now.
4234 * Pointer to the modify action.
4236 * Pointer to error structure.
4239 * 0 on success, a negative errno value otherwise and rte_errno is set.
4242 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4243 const struct rte_flow_action *action,
4244 struct rte_flow_error *error)
4246 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4247 return rte_flow_error_set(error, EINVAL,
4248 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4249 NULL, "action configuration not set");
4250 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4253 "can't have encap action before"
4259 * Validate the modify-header MAC address actions.
4261 * @param[in] action_flags
4262 * Holds the actions detected until now.
4264 * Pointer to the modify action.
4265 * @param[in] item_flags
4266 * Holds the items detected.
4268 * Pointer to error structure.
4271 * 0 on success, a negative errno value otherwise and rte_errno is set.
4274 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4275 const struct rte_flow_action *action,
4276 const uint64_t item_flags,
4277 struct rte_flow_error *error)
4281 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4283 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4284 return rte_flow_error_set(error, EINVAL,
4285 RTE_FLOW_ERROR_TYPE_ACTION,
4287 "no L2 item in pattern");
4293 * Validate the modify-header IPv4 address actions.
4295 * @param[in] action_flags
4296 * Holds the actions detected until now.
4298 * Pointer to the modify action.
4299 * @param[in] item_flags
4300 * Holds the items detected.
4302 * Pointer to error structure.
4305 * 0 on success, a negative errno value otherwise and rte_errno is set.
4308 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4309 const struct rte_flow_action *action,
4310 const uint64_t item_flags,
4311 struct rte_flow_error *error)
4316 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4318 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4319 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4320 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4321 if (!(item_flags & layer))
4322 return rte_flow_error_set(error, EINVAL,
4323 RTE_FLOW_ERROR_TYPE_ACTION,
4325 "no ipv4 item in pattern");
4331 * Validate the modify-header IPv6 address actions.
4333 * @param[in] action_flags
4334 * Holds the actions detected until now.
4336 * Pointer to the modify action.
4337 * @param[in] item_flags
4338 * Holds the items detected.
4340 * Pointer to error structure.
4343 * 0 on success, a negative errno value otherwise and rte_errno is set.
4346 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4347 const struct rte_flow_action *action,
4348 const uint64_t item_flags,
4349 struct rte_flow_error *error)
4354 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4356 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4357 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4358 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4359 if (!(item_flags & layer))
4360 return rte_flow_error_set(error, EINVAL,
4361 RTE_FLOW_ERROR_TYPE_ACTION,
4363 "no ipv6 item in pattern");
4369 * Validate the modify-header TP actions.
4371 * @param[in] action_flags
4372 * Holds the actions detected until now.
4374 * Pointer to the modify action.
4375 * @param[in] item_flags
4376 * Holds the items detected.
4378 * Pointer to error structure.
4381 * 0 on success, a negative errno value otherwise and rte_errno is set.
4384 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4385 const struct rte_flow_action *action,
4386 const uint64_t item_flags,
4387 struct rte_flow_error *error)
4392 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4394 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4395 MLX5_FLOW_LAYER_INNER_L4 :
4396 MLX5_FLOW_LAYER_OUTER_L4;
4397 if (!(item_flags & layer))
4398 return rte_flow_error_set(error, EINVAL,
4399 RTE_FLOW_ERROR_TYPE_ACTION,
4400 NULL, "no transport layer "
4407 * Validate the modify-header actions of increment/decrement
4408 * TCP Sequence-number.
4410 * @param[in] action_flags
4411 * Holds the actions detected until now.
4413 * Pointer to the modify action.
4414 * @param[in] item_flags
4415 * Holds the items detected.
4417 * Pointer to error structure.
4420 * 0 on success, a negative errno value otherwise and rte_errno is set.
4423 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4424 const struct rte_flow_action *action,
4425 const uint64_t item_flags,
4426 struct rte_flow_error *error)
4431 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4433 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4434 MLX5_FLOW_LAYER_INNER_L4_TCP :
4435 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4436 if (!(item_flags & layer))
4437 return rte_flow_error_set(error, EINVAL,
4438 RTE_FLOW_ERROR_TYPE_ACTION,
4439 NULL, "no TCP item in"
4441 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4442 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4443 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4444 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4445 return rte_flow_error_set(error, EINVAL,
4446 RTE_FLOW_ERROR_TYPE_ACTION,
4448 "cannot decrease and increase"
4449 " TCP sequence number"
4450 " at the same time");
4456 * Validate the modify-header actions of increment/decrement
4457 * TCP Acknowledgment number.
4459 * @param[in] action_flags
4460 * Holds the actions detected until now.
4462 * Pointer to the modify action.
4463 * @param[in] item_flags
4464 * Holds the items detected.
4466 * Pointer to error structure.
4469 * 0 on success, a negative errno value otherwise and rte_errno is set.
4472 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4473 const struct rte_flow_action *action,
4474 const uint64_t item_flags,
4475 struct rte_flow_error *error)
4480 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4482 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4483 MLX5_FLOW_LAYER_INNER_L4_TCP :
4484 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4485 if (!(item_flags & layer))
4486 return rte_flow_error_set(error, EINVAL,
4487 RTE_FLOW_ERROR_TYPE_ACTION,
4488 NULL, "no TCP item in"
4490 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4491 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4492 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4493 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4494 return rte_flow_error_set(error, EINVAL,
4495 RTE_FLOW_ERROR_TYPE_ACTION,
4497 "cannot decrease and increase"
4498 " TCP acknowledgment number"
4499 " at the same time");
4505 * Validate the modify-header TTL actions.
4507 * @param[in] action_flags
4508 * Holds the actions detected until now.
4510 * Pointer to the modify action.
4511 * @param[in] item_flags
4512 * Holds the items detected.
4514 * Pointer to error structure.
4517 * 0 on success, a negative errno value otherwise and rte_errno is set.
4520 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4521 const struct rte_flow_action *action,
4522 const uint64_t item_flags,
4523 struct rte_flow_error *error)
4528 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4530 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4531 MLX5_FLOW_LAYER_INNER_L3 :
4532 MLX5_FLOW_LAYER_OUTER_L3;
4533 if (!(item_flags & layer))
4534 return rte_flow_error_set(error, EINVAL,
4535 RTE_FLOW_ERROR_TYPE_ACTION,
4537 "no IP protocol in pattern");
4543 * Validate the generic modify field actions.
4545 * Pointer to the rte_eth_dev structure.
4546 * @param[in] action_flags
4547 * Holds the actions detected until now.
4549 * Pointer to the modify action.
4551 * Pointer to the flow attributes.
4553 * Pointer to error structure.
4556 * Number of header fields to modify (0 or more) on success,
4557 * a negative errno value otherwise and rte_errno is set.
4560 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4561 const uint64_t action_flags,
4562 const struct rte_flow_action *action,
4563 const struct rte_flow_attr *attr,
4564 struct rte_flow_error *error)
4567 struct mlx5_priv *priv = dev->data->dev_private;
4568 struct mlx5_dev_config *config = &priv->config;
4569 const struct rte_flow_action_modify_field *action_modify_field =
4571 uint32_t dst_width =
4572 mlx5_flow_item_field_width(action_modify_field->dst.field);
4573 uint32_t src_width =
4574 mlx5_flow_item_field_width(action_modify_field->src.field);
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4580 if (action_modify_field->width == 0)
4581 return rte_flow_error_set(error, EINVAL,
4582 RTE_FLOW_ERROR_TYPE_ACTION, action,
4583 "no bits are requested to be modified");
4584 else if (action_modify_field->width > dst_width ||
4585 action_modify_field->width > src_width)
4586 return rte_flow_error_set(error, EINVAL,
4587 RTE_FLOW_ERROR_TYPE_ACTION, action,
4588 "cannot modify more bits than"
4589 " the width of a field");
4590 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4591 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4592 if ((action_modify_field->dst.offset +
4593 action_modify_field->width > dst_width) ||
4594 (action_modify_field->dst.offset % 32))
4595 return rte_flow_error_set(error, EINVAL,
4596 RTE_FLOW_ERROR_TYPE_ACTION, action,
4597 "destination offset is too big"
4598 " or not aligned to 4 bytes");
4599 if (action_modify_field->dst.level &&
4600 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4601 return rte_flow_error_set(error, ENOTSUP,
4602 RTE_FLOW_ERROR_TYPE_ACTION, action,
4603 "inner header fields modification"
4604 " is not supported");
4606 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4607 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4608 if (!attr->transfer && !attr->group)
4609 return rte_flow_error_set(error, ENOTSUP,
4610 RTE_FLOW_ERROR_TYPE_ACTION, action,
4611 "modify field action is not"
4612 " supported for group 0");
4613 if ((action_modify_field->src.offset +
4614 action_modify_field->width > src_width) ||
4615 (action_modify_field->src.offset % 32))
4616 return rte_flow_error_set(error, EINVAL,
4617 RTE_FLOW_ERROR_TYPE_ACTION, action,
4618 "source offset is too big"
4619 " or not aligned to 4 bytes");
4620 if (action_modify_field->src.level &&
4621 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4622 return rte_flow_error_set(error, ENOTSUP,
4623 RTE_FLOW_ERROR_TYPE_ACTION, action,
4624 "inner header fields modification"
4625 " is not supported");
4627 if (action_modify_field->dst.field ==
4628 action_modify_field->src.field)
4629 return rte_flow_error_set(error, EINVAL,
4630 RTE_FLOW_ERROR_TYPE_ACTION, action,
4631 "source and destination fields"
4632 " cannot be the same");
4633 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4634 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4635 return rte_flow_error_set(error, EINVAL,
4636 RTE_FLOW_ERROR_TYPE_ACTION, action,
4637 "immediate value or a pointer to it"
4638 " cannot be used as a destination");
4639 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4640 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4641 return rte_flow_error_set(error, ENOTSUP,
4642 RTE_FLOW_ERROR_TYPE_ACTION, action,
4643 "modifications of an arbitrary"
4644 " place in a packet is not supported");
4645 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4646 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4647 return rte_flow_error_set(error, ENOTSUP,
4648 RTE_FLOW_ERROR_TYPE_ACTION, action,
4649 "modifications of the 802.1Q Tag"
4650 " Identifier is not supported");
4651 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4652 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4653 return rte_flow_error_set(error, ENOTSUP,
4654 RTE_FLOW_ERROR_TYPE_ACTION, action,
4655 "modifications of the VXLAN Network"
4656 " Identifier is not supported");
4657 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4658 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4659 return rte_flow_error_set(error, ENOTSUP,
4660 RTE_FLOW_ERROR_TYPE_ACTION, action,
4661 "modifications of the GENEVE Network"
4662 " Identifier is not supported");
4663 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4664 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4665 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4666 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4667 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4668 !mlx5_flow_ext_mreg_supported(dev))
4669 return rte_flow_error_set(error, ENOTSUP,
4670 RTE_FLOW_ERROR_TYPE_ACTION, action,
4671 "cannot modify mark or metadata without"
4672 " extended metadata register support");
4674 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4675 return rte_flow_error_set(error, ENOTSUP,
4676 RTE_FLOW_ERROR_TYPE_ACTION, action,
4677 "add and sub operations"
4678 " are not supported");
4679 return (action_modify_field->width / 32) +
4680 !!(action_modify_field->width % 32);
4684 * Validate jump action.
4687 * Pointer to the jump action.
4688 * @param[in] action_flags
4689 * Holds the actions detected until now.
4690 * @param[in] attributes
4691 * Pointer to flow attributes
4692 * @param[in] external
4693 * Action belongs to flow rule created by request external to PMD.
4695 * Pointer to error structure.
4698 * 0 on success, a negative errno value otherwise and rte_errno is set.
4701 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4702 const struct mlx5_flow_tunnel *tunnel,
4703 const struct rte_flow_action *action,
4704 uint64_t action_flags,
4705 const struct rte_flow_attr *attributes,
4706 bool external, struct rte_flow_error *error)
4708 uint32_t target_group, table;
4710 struct flow_grp_info grp_info = {
4711 .external = !!external,
4712 .transfer = !!attributes->transfer,
4716 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4717 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4718 return rte_flow_error_set(error, EINVAL,
4719 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4720 "can't have 2 fate actions in"
4722 if (action_flags & MLX5_FLOW_ACTION_METER)
4723 return rte_flow_error_set(error, ENOTSUP,
4724 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4725 "jump with meter not support");
4727 return rte_flow_error_set(error, EINVAL,
4728 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4729 NULL, "action configuration not set");
4731 ((const struct rte_flow_action_jump *)action->conf)->group;
4732 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4736 if (attributes->group == target_group &&
4737 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4738 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4739 return rte_flow_error_set(error, EINVAL,
4740 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4741 "target group must be other than"
4742 " the current flow group");
4747 * Validate the port_id action.
4750 * Pointer to rte_eth_dev structure.
4751 * @param[in] action_flags
4752 * Bit-fields that holds the actions detected until now.
4754 * Port_id RTE action structure.
4756 * Attributes of flow that includes this action.
4758 * Pointer to error structure.
4761 * 0 on success, a negative errno value otherwise and rte_errno is set.
4764 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4765 uint64_t action_flags,
4766 const struct rte_flow_action *action,
4767 const struct rte_flow_attr *attr,
4768 struct rte_flow_error *error)
4770 const struct rte_flow_action_port_id *port_id;
4771 struct mlx5_priv *act_priv;
4772 struct mlx5_priv *dev_priv;
4775 if (!attr->transfer)
4776 return rte_flow_error_set(error, ENOTSUP,
4777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4779 "port id action is valid in transfer"
4781 if (!action || !action->conf)
4782 return rte_flow_error_set(error, ENOTSUP,
4783 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4785 "port id action parameters must be"
4787 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4788 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4789 return rte_flow_error_set(error, EINVAL,
4790 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4791 "can have only one fate actions in"
4793 dev_priv = mlx5_dev_to_eswitch_info(dev);
4795 return rte_flow_error_set(error, rte_errno,
4796 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4798 "failed to obtain E-Switch info");
4799 port_id = action->conf;
4800 port = port_id->original ? dev->data->port_id : port_id->id;
4801 act_priv = mlx5_port_to_eswitch_info(port, false);
4803 return rte_flow_error_set
4805 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4806 "failed to obtain E-Switch port id for port");
4807 if (act_priv->domain_id != dev_priv->domain_id)
4808 return rte_flow_error_set
4810 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4811 "port does not belong to"
4812 " E-Switch being configured");
4817 * Get the maximum number of modify header actions.
4820 * Pointer to rte_eth_dev structure.
4822 * Flags bits to check if root level.
4825 * Max number of modify header actions device can support.
4827 static inline unsigned int
4828 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4832 * There's no way to directly query the max capacity from FW.
4833 * The maximal value on root table should be assumed to be supported.
4835 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4836 return MLX5_MAX_MODIFY_NUM;
4838 return MLX5_ROOT_TBL_MODIFY_NUM;
4842 * Validate the meter action.
4845 * Pointer to rte_eth_dev structure.
4846 * @param[in] action_flags
4847 * Bit-fields that holds the actions detected until now.
4849 * Pointer to the meter action.
4851 * Attributes of flow that includes this action.
4853 * Pointer to error structure.
4856 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4859 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4860 uint64_t action_flags,
4861 const struct rte_flow_action *action,
4862 const struct rte_flow_attr *attr,
4863 struct rte_flow_error *error)
4865 struct mlx5_priv *priv = dev->data->dev_private;
4866 const struct rte_flow_action_meter *am = action->conf;
4867 struct mlx5_flow_meter *fm;
4870 return rte_flow_error_set(error, EINVAL,
4871 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4872 "meter action conf is NULL");
4874 if (action_flags & MLX5_FLOW_ACTION_METER)
4875 return rte_flow_error_set(error, ENOTSUP,
4876 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4877 "meter chaining not support");
4878 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4879 return rte_flow_error_set(error, ENOTSUP,
4880 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4881 "meter with jump not support");
4883 return rte_flow_error_set(error, ENOTSUP,
4884 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4886 "meter action not supported");
4887 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4889 return rte_flow_error_set(error, EINVAL,
4890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4892 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4893 (!fm->ingress && !attr->ingress && attr->egress) ||
4894 (!fm->egress && !attr->egress && attr->ingress))))
4895 return rte_flow_error_set(error, EINVAL,
4896 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4897 "Flow attributes are either invalid "
4898 "or have a conflict with current "
4899 "meter attributes");
4904 * Validate the age action.
4906 * @param[in] action_flags
4907 * Holds the actions detected until now.
4909 * Pointer to the age action.
4911 * Pointer to the Ethernet device structure.
4913 * Pointer to error structure.
4916 * 0 on success, a negative errno value otherwise and rte_errno is set.
4919 flow_dv_validate_action_age(uint64_t action_flags,
4920 const struct rte_flow_action *action,
4921 struct rte_eth_dev *dev,
4922 struct rte_flow_error *error)
4924 struct mlx5_priv *priv = dev->data->dev_private;
4925 const struct rte_flow_action_age *age = action->conf;
4927 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4928 !priv->sh->aso_age_mng))
4929 return rte_flow_error_set(error, ENOTSUP,
4930 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4932 "age action not supported");
4933 if (!(action->conf))
4934 return rte_flow_error_set(error, EINVAL,
4935 RTE_FLOW_ERROR_TYPE_ACTION, action,
4936 "configuration cannot be null");
4937 if (!(age->timeout))
4938 return rte_flow_error_set(error, EINVAL,
4939 RTE_FLOW_ERROR_TYPE_ACTION, action,
4940 "invalid timeout value 0");
4941 if (action_flags & MLX5_FLOW_ACTION_AGE)
4942 return rte_flow_error_set(error, EINVAL,
4943 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4944 "duplicate age actions set");
4949 * Validate the modify-header IPv4 DSCP actions.
4951 * @param[in] action_flags
4952 * Holds the actions detected until now.
4954 * Pointer to the modify action.
4955 * @param[in] item_flags
4956 * Holds the items detected.
4958 * Pointer to error structure.
4961 * 0 on success, a negative errno value otherwise and rte_errno is set.
4964 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4965 const struct rte_flow_action *action,
4966 const uint64_t item_flags,
4967 struct rte_flow_error *error)
4971 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4973 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4974 return rte_flow_error_set(error, EINVAL,
4975 RTE_FLOW_ERROR_TYPE_ACTION,
4977 "no ipv4 item in pattern");
4983 * Validate the modify-header IPv6 DSCP actions.
4985 * @param[in] action_flags
4986 * Holds the actions detected until now.
4988 * Pointer to the modify action.
4989 * @param[in] item_flags
4990 * Holds the items detected.
4992 * Pointer to error structure.
4995 * 0 on success, a negative errno value otherwise and rte_errno is set.
4998 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4999 const struct rte_flow_action *action,
5000 const uint64_t item_flags,
5001 struct rte_flow_error *error)
5005 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5007 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5008 return rte_flow_error_set(error, EINVAL,
5009 RTE_FLOW_ERROR_TYPE_ACTION,
5011 "no ipv6 item in pattern");
5017 * Match modify-header resource.
5020 * Pointer to the hash list.
5022 * Pointer to exist resource entry object.
5024 * Key of the new entry.
5026 * Pointer to new modify-header resource.
5029 * 0 on matching, non-zero otherwise.
5032 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5033 struct mlx5_hlist_entry *entry,
5034 uint64_t key __rte_unused, void *cb_ctx)
5036 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5037 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5038 struct mlx5_flow_dv_modify_hdr_resource *resource =
5039 container_of(entry, typeof(*resource), entry);
5040 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5042 key_len += ref->actions_num * sizeof(ref->actions[0]);
5043 return ref->actions_num != resource->actions_num ||
5044 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5047 struct mlx5_hlist_entry *
5048 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5051 struct mlx5_dev_ctx_shared *sh = list->ctx;
5052 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5053 struct mlx5dv_dr_domain *ns;
5054 struct mlx5_flow_dv_modify_hdr_resource *entry;
5055 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5057 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5058 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5060 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5063 rte_flow_error_set(ctx->error, ENOMEM,
5064 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5065 "cannot allocate resource memory");
5068 rte_memcpy(&entry->ft_type,
5069 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5070 key_len + data_len);
5071 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5072 ns = sh->fdb_domain;
5073 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5077 ret = mlx5_flow_os_create_flow_action_modify_header
5078 (sh->ctx, ns, entry,
5079 data_len, &entry->action);
5082 rte_flow_error_set(ctx->error, ENOMEM,
5083 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5084 NULL, "cannot create modification action");
5087 return &entry->entry;
5091 * Validate the sample action.
5093 * @param[in, out] action_flags
5094 * Holds the actions detected until now.
5096 * Pointer to the sample action.
5098 * Pointer to the Ethernet device structure.
5100 * Attributes of flow that includes this action.
5101 * @param[in] item_flags
5102 * Holds the items detected.
5104 * Pointer to the RSS action.
5105 * @param[out] sample_rss
5106 * Pointer to the RSS action in sample action list.
5108 * Pointer to the COUNT action in sample action list.
5109 * @param[out] fdb_mirror_limit
5110 * Pointer to the FDB mirror limitation flag.
5112 * Pointer to error structure.
5115 * 0 on success, a negative errno value otherwise and rte_errno is set.
5118 flow_dv_validate_action_sample(uint64_t *action_flags,
5119 const struct rte_flow_action *action,
5120 struct rte_eth_dev *dev,
5121 const struct rte_flow_attr *attr,
5122 uint64_t item_flags,
5123 const struct rte_flow_action_rss *rss,
5124 const struct rte_flow_action_rss **sample_rss,
5125 const struct rte_flow_action_count **count,
5126 int *fdb_mirror_limit,
5127 struct rte_flow_error *error)
5129 struct mlx5_priv *priv = dev->data->dev_private;
5130 struct mlx5_dev_config *dev_conf = &priv->config;
5131 const struct rte_flow_action_sample *sample = action->conf;
5132 const struct rte_flow_action *act;
5133 uint64_t sub_action_flags = 0;
5134 uint16_t queue_index = 0xFFFF;
5139 return rte_flow_error_set(error, EINVAL,
5140 RTE_FLOW_ERROR_TYPE_ACTION, action,
5141 "configuration cannot be NULL");
5142 if (sample->ratio == 0)
5143 return rte_flow_error_set(error, EINVAL,
5144 RTE_FLOW_ERROR_TYPE_ACTION, action,
5145 "ratio value starts from 1");
5146 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5147 return rte_flow_error_set(error, ENOTSUP,
5148 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5150 "sample action not supported");
5151 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5152 return rte_flow_error_set(error, EINVAL,
5153 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5154 "Multiple sample actions not "
5156 if (*action_flags & MLX5_FLOW_ACTION_METER)
5157 return rte_flow_error_set(error, EINVAL,
5158 RTE_FLOW_ERROR_TYPE_ACTION, action,
5159 "wrong action order, meter should "
5160 "be after sample action");
5161 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5162 return rte_flow_error_set(error, EINVAL,
5163 RTE_FLOW_ERROR_TYPE_ACTION, action,
5164 "wrong action order, jump should "
5165 "be after sample action");
5166 act = sample->actions;
5167 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5168 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5169 return rte_flow_error_set(error, ENOTSUP,
5170 RTE_FLOW_ERROR_TYPE_ACTION,
5171 act, "too many actions");
5172 switch (act->type) {
5173 case RTE_FLOW_ACTION_TYPE_QUEUE:
5174 ret = mlx5_flow_validate_action_queue(act,
5180 queue_index = ((const struct rte_flow_action_queue *)
5181 (act->conf))->index;
5182 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5185 case RTE_FLOW_ACTION_TYPE_RSS:
5186 *sample_rss = act->conf;
5187 ret = mlx5_flow_validate_action_rss(act,
5194 if (rss && *sample_rss &&
5195 ((*sample_rss)->level != rss->level ||
5196 (*sample_rss)->types != rss->types))
5197 return rte_flow_error_set(error, ENOTSUP,
5198 RTE_FLOW_ERROR_TYPE_ACTION,
5200 "Can't use the different RSS types "
5201 "or level in the same flow");
5202 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5203 queue_index = (*sample_rss)->queue[0];
5204 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5207 case RTE_FLOW_ACTION_TYPE_MARK:
5208 ret = flow_dv_validate_action_mark(dev, act,
5213 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5214 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5215 MLX5_FLOW_ACTION_MARK_EXT;
5217 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5220 case RTE_FLOW_ACTION_TYPE_COUNT:
5221 ret = flow_dv_validate_action_count
5223 *action_flags | sub_action_flags,
5228 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5229 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5232 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5233 ret = flow_dv_validate_action_port_id(dev,
5240 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5243 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5244 ret = flow_dv_validate_action_raw_encap_decap
5245 (dev, NULL, act->conf, attr, &sub_action_flags,
5246 &actions_n, action, item_flags, error);
5251 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5252 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5253 ret = flow_dv_validate_action_l2_encap(dev,
5259 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5263 return rte_flow_error_set(error, ENOTSUP,
5264 RTE_FLOW_ERROR_TYPE_ACTION,
5266 "Doesn't support optional "
5270 if (attr->ingress && !attr->transfer) {
5271 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5272 MLX5_FLOW_ACTION_RSS)))
5273 return rte_flow_error_set(error, EINVAL,
5274 RTE_FLOW_ERROR_TYPE_ACTION,
5276 "Ingress must has a dest "
5277 "QUEUE for Sample");
5278 } else if (attr->egress && !attr->transfer) {
5279 return rte_flow_error_set(error, ENOTSUP,
5280 RTE_FLOW_ERROR_TYPE_ACTION,
5282 "Sample Only support Ingress "
5284 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5285 MLX5_ASSERT(attr->transfer);
5286 if (sample->ratio > 1)
5287 return rte_flow_error_set(error, ENOTSUP,
5288 RTE_FLOW_ERROR_TYPE_ACTION,
5290 "E-Switch doesn't support "
5291 "any optional action "
5293 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5294 return rte_flow_error_set(error, ENOTSUP,
5295 RTE_FLOW_ERROR_TYPE_ACTION,
5297 "unsupported action QUEUE");
5298 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5299 return rte_flow_error_set(error, ENOTSUP,
5300 RTE_FLOW_ERROR_TYPE_ACTION,
5302 "unsupported action QUEUE");
5303 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5304 return rte_flow_error_set(error, EINVAL,
5305 RTE_FLOW_ERROR_TYPE_ACTION,
5307 "E-Switch must has a dest "
5308 "port for mirroring");
5309 if (!priv->config.hca_attr.reg_c_preserve &&
5310 priv->representor_id != -1)
5311 *fdb_mirror_limit = 1;
5313 /* Continue validation for Xcap actions.*/
5314 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5315 (queue_index == 0xFFFF ||
5316 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5317 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5318 MLX5_FLOW_XCAP_ACTIONS)
5319 return rte_flow_error_set(error, ENOTSUP,
5320 RTE_FLOW_ERROR_TYPE_ACTION,
5321 NULL, "encap and decap "
5322 "combination aren't "
5324 if (!attr->transfer && attr->ingress && (sub_action_flags &
5325 MLX5_FLOW_ACTION_ENCAP))
5326 return rte_flow_error_set(error, ENOTSUP,
5327 RTE_FLOW_ERROR_TYPE_ACTION,
5328 NULL, "encap is not supported"
5329 " for ingress traffic");
5335 * Find existing modify-header resource or create and register a new one.
5337 * @param dev[in, out]
5338 * Pointer to rte_eth_dev structure.
5339 * @param[in, out] resource
5340 * Pointer to modify-header resource.
5341 * @parm[in, out] dev_flow
5342 * Pointer to the dev_flow.
5344 * pointer to error structure.
5347 * 0 on success otherwise -errno and errno is set.
5350 flow_dv_modify_hdr_resource_register
5351 (struct rte_eth_dev *dev,
5352 struct mlx5_flow_dv_modify_hdr_resource *resource,
5353 struct mlx5_flow *dev_flow,
5354 struct rte_flow_error *error)
5356 struct mlx5_priv *priv = dev->data->dev_private;
5357 struct mlx5_dev_ctx_shared *sh = priv->sh;
5358 uint32_t key_len = sizeof(*resource) -
5359 offsetof(typeof(*resource), ft_type) +
5360 resource->actions_num * sizeof(resource->actions[0]);
5361 struct mlx5_hlist_entry *entry;
5362 struct mlx5_flow_cb_ctx ctx = {
5368 resource->flags = dev_flow->dv.group ? 0 :
5369 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5370 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5372 return rte_flow_error_set(error, EOVERFLOW,
5373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5374 "too many modify header items");
5375 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5376 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5379 resource = container_of(entry, typeof(*resource), entry);
5380 dev_flow->handle->dvh.modify_hdr = resource;
5385 * Get DV flow counter by index.
5388 * Pointer to the Ethernet device structure.
5390 * mlx5 flow counter index in the container.
5392 * mlx5 flow counter pool in the container,
5395 * Pointer to the counter, NULL otherwise.
5397 static struct mlx5_flow_counter *
5398 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5400 struct mlx5_flow_counter_pool **ppool)
5402 struct mlx5_priv *priv = dev->data->dev_private;
5403 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5404 struct mlx5_flow_counter_pool *pool;
5406 /* Decrease to original index and clear shared bit. */
5407 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5408 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5409 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5413 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5417 * Check the devx counter belongs to the pool.
5420 * Pointer to the counter pool.
5422 * The counter devx ID.
5425 * True if counter belongs to the pool, false otherwise.
5428 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5430 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5431 MLX5_COUNTERS_PER_POOL;
5433 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5439 * Get a pool by devx counter ID.
5442 * Pointer to the counter management.
5444 * The counter devx ID.
5447 * The counter pool pointer if exists, NULL otherwise,
5449 static struct mlx5_flow_counter_pool *
5450 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5453 struct mlx5_flow_counter_pool *pool = NULL;
5455 rte_spinlock_lock(&cmng->pool_update_sl);
5456 /* Check last used pool. */
5457 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5458 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5459 pool = cmng->pools[cmng->last_pool_idx];
5462 /* ID out of range means no suitable pool in the container. */
5463 if (id > cmng->max_id || id < cmng->min_id)
5466 * Find the pool from the end of the container, since mostly counter
5467 * ID is sequence increasing, and the last pool should be the needed
5472 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5474 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5480 rte_spinlock_unlock(&cmng->pool_update_sl);
5485 * Resize a counter container.
5488 * Pointer to the Ethernet device structure.
5491 * 0 on success, otherwise negative errno value and rte_errno is set.
5494 flow_dv_container_resize(struct rte_eth_dev *dev)
5496 struct mlx5_priv *priv = dev->data->dev_private;
5497 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5498 void *old_pools = cmng->pools;
5499 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5500 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5501 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5508 memcpy(pools, old_pools, cmng->n *
5509 sizeof(struct mlx5_flow_counter_pool *));
5511 cmng->pools = pools;
5513 mlx5_free(old_pools);
5518 * Query a devx flow counter.
5521 * Pointer to the Ethernet device structure.
5523 * Index to the flow counter.
5525 * The statistics value of packets.
5527 * The statistics value of bytes.
5530 * 0 on success, otherwise a negative errno value and rte_errno is set.
5533 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5536 struct mlx5_priv *priv = dev->data->dev_private;
5537 struct mlx5_flow_counter_pool *pool = NULL;
5538 struct mlx5_flow_counter *cnt;
5541 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5543 if (priv->sh->cmng.counter_fallback)
5544 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5545 0, pkts, bytes, 0, NULL, NULL, 0);
5546 rte_spinlock_lock(&pool->sl);
5551 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5552 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5553 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5555 rte_spinlock_unlock(&pool->sl);
5560 * Create and initialize a new counter pool.
5563 * Pointer to the Ethernet device structure.
5565 * The devX counter handle.
5567 * Whether the pool is for counter that was allocated for aging.
5568 * @param[in/out] cont_cur
5569 * Pointer to the container pointer, it will be update in pool resize.
5572 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5574 static struct mlx5_flow_counter_pool *
5575 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5578 struct mlx5_priv *priv = dev->data->dev_private;
5579 struct mlx5_flow_counter_pool *pool;
5580 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5581 bool fallback = priv->sh->cmng.counter_fallback;
5582 uint32_t size = sizeof(*pool);
5584 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5585 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5586 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5592 pool->is_aged = !!age;
5593 pool->query_gen = 0;
5594 pool->min_dcs = dcs;
5595 rte_spinlock_init(&pool->sl);
5596 rte_spinlock_init(&pool->csl);
5597 TAILQ_INIT(&pool->counters[0]);
5598 TAILQ_INIT(&pool->counters[1]);
5599 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5600 rte_spinlock_lock(&cmng->pool_update_sl);
5601 pool->index = cmng->n_valid;
5602 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5604 rte_spinlock_unlock(&cmng->pool_update_sl);
5607 cmng->pools[pool->index] = pool;
5609 if (unlikely(fallback)) {
5610 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5612 if (base < cmng->min_id)
5613 cmng->min_id = base;
5614 if (base > cmng->max_id)
5615 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5616 cmng->last_pool_idx = pool->index;
5618 rte_spinlock_unlock(&cmng->pool_update_sl);
5623 * Prepare a new counter and/or a new counter pool.
5626 * Pointer to the Ethernet device structure.
5627 * @param[out] cnt_free
5628 * Where to put the pointer of a new counter.
5630 * Whether the pool is for counter that was allocated for aging.
5633 * The counter pool pointer and @p cnt_free is set on success,
5634 * NULL otherwise and rte_errno is set.
5636 static struct mlx5_flow_counter_pool *
5637 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5638 struct mlx5_flow_counter **cnt_free,
5641 struct mlx5_priv *priv = dev->data->dev_private;
5642 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5643 struct mlx5_flow_counter_pool *pool;
5644 struct mlx5_counters tmp_tq;
5645 struct mlx5_devx_obj *dcs = NULL;
5646 struct mlx5_flow_counter *cnt;
5647 enum mlx5_counter_type cnt_type =
5648 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5649 bool fallback = priv->sh->cmng.counter_fallback;
5653 /* bulk_bitmap must be 0 for single counter allocation. */
5654 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5657 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5659 pool = flow_dv_pool_create(dev, dcs, age);
5661 mlx5_devx_cmd_destroy(dcs);
5665 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5666 cnt = MLX5_POOL_GET_CNT(pool, i);
5668 cnt->dcs_when_free = dcs;
5672 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5674 rte_errno = ENODATA;
5677 pool = flow_dv_pool_create(dev, dcs, age);
5679 mlx5_devx_cmd_destroy(dcs);
5682 TAILQ_INIT(&tmp_tq);
5683 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5684 cnt = MLX5_POOL_GET_CNT(pool, i);
5686 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5688 rte_spinlock_lock(&cmng->csl[cnt_type]);
5689 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5690 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5691 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5692 (*cnt_free)->pool = pool;
5697 * Allocate a flow counter.
5700 * Pointer to the Ethernet device structure.
5702 * Whether the counter was allocated for aging.
5705 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5708 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5710 struct mlx5_priv *priv = dev->data->dev_private;
5711 struct mlx5_flow_counter_pool *pool = NULL;
5712 struct mlx5_flow_counter *cnt_free = NULL;
5713 bool fallback = priv->sh->cmng.counter_fallback;
5714 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5715 enum mlx5_counter_type cnt_type =
5716 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5719 if (!priv->config.devx) {
5720 rte_errno = ENOTSUP;
5723 /* Get free counters from container. */
5724 rte_spinlock_lock(&cmng->csl[cnt_type]);
5725 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5727 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5728 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5729 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5731 pool = cnt_free->pool;
5733 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5734 /* Create a DV counter action only in the first time usage. */
5735 if (!cnt_free->action) {
5737 struct mlx5_devx_obj *dcs;
5741 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5742 dcs = pool->min_dcs;
5745 dcs = cnt_free->dcs_when_free;
5747 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5754 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5755 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5756 /* Update the counter reset values. */
5757 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5760 if (!fallback && !priv->sh->cmng.query_thread_on)
5761 /* Start the asynchronous batch query by the host thread. */
5762 mlx5_set_query_alarm(priv->sh);
5766 cnt_free->pool = pool;
5768 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5769 rte_spinlock_lock(&cmng->csl[cnt_type]);
5770 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5771 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5777 * Allocate a shared flow counter.
5780 * Pointer to the shared counter configuration.
5782 * Pointer to save the allocated counter index.
5785 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5789 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5791 struct mlx5_shared_counter_conf *conf = ctx;
5792 struct rte_eth_dev *dev = conf->dev;
5793 struct mlx5_flow_counter *cnt;
5795 data->dword = flow_dv_counter_alloc(dev, 0);
5796 data->dword |= MLX5_CNT_SHARED_OFFSET;
5797 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5798 cnt->shared_info.id = conf->id;
5803 * Get a shared flow counter.
5806 * Pointer to the Ethernet device structure.
5808 * Counter identifier.
5811 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5814 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5816 struct mlx5_priv *priv = dev->data->dev_private;
5817 struct mlx5_shared_counter_conf conf = {
5821 union mlx5_l3t_data data = {
5825 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5826 flow_dv_counter_alloc_shared_cb, &conf);
5831 * Get age param from counter index.
5834 * Pointer to the Ethernet device structure.
5835 * @param[in] counter
5836 * Index to the counter handler.
5839 * The aging parameter specified for the counter index.
5841 static struct mlx5_age_param*
5842 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5845 struct mlx5_flow_counter *cnt;
5846 struct mlx5_flow_counter_pool *pool = NULL;
5848 flow_dv_counter_get_by_idx(dev, counter, &pool);
5849 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5850 cnt = MLX5_POOL_GET_CNT(pool, counter);
5851 return MLX5_CNT_TO_AGE(cnt);
5855 * Remove a flow counter from aged counter list.
5858 * Pointer to the Ethernet device structure.
5859 * @param[in] counter
5860 * Index to the counter handler.
5862 * Pointer to the counter handler.
5865 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5866 uint32_t counter, struct mlx5_flow_counter *cnt)
5868 struct mlx5_age_info *age_info;
5869 struct mlx5_age_param *age_param;
5870 struct mlx5_priv *priv = dev->data->dev_private;
5871 uint16_t expected = AGE_CANDIDATE;
5873 age_info = GET_PORT_AGE_INFO(priv);
5874 age_param = flow_dv_counter_idx_get_age(dev, counter);
5875 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5876 AGE_FREE, false, __ATOMIC_RELAXED,
5877 __ATOMIC_RELAXED)) {
5879 * We need the lock even it is age timeout,
5880 * since counter may still in process.
5882 rte_spinlock_lock(&age_info->aged_sl);
5883 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5884 rte_spinlock_unlock(&age_info->aged_sl);
5885 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5890 * Release a flow counter.
5893 * Pointer to the Ethernet device structure.
5894 * @param[in] counter
5895 * Index to the counter handler.
5898 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5900 struct mlx5_priv *priv = dev->data->dev_private;
5901 struct mlx5_flow_counter_pool *pool = NULL;
5902 struct mlx5_flow_counter *cnt;
5903 enum mlx5_counter_type cnt_type;
5907 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5909 if (IS_SHARED_CNT(counter) &&
5910 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5913 flow_dv_counter_remove_from_age(dev, counter, cnt);
5916 * Put the counter back to list to be updated in none fallback mode.
5917 * Currently, we are using two list alternately, while one is in query,
5918 * add the freed counter to the other list based on the pool query_gen
5919 * value. After query finishes, add counter the list to the global
5920 * container counter list. The list changes while query starts. In
5921 * this case, lock will not be needed as query callback and release
5922 * function both operate with the different list.
5925 if (!priv->sh->cmng.counter_fallback) {
5926 rte_spinlock_lock(&pool->csl);
5927 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5928 rte_spinlock_unlock(&pool->csl);
5930 cnt->dcs_when_free = cnt->dcs_when_active;
5931 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5932 MLX5_COUNTER_TYPE_ORIGIN;
5933 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5934 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5936 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5941 * Verify the @p attributes will be correctly understood by the NIC and store
5942 * them in the @p flow if everything is correct.
5945 * Pointer to dev struct.
5946 * @param[in] attributes
5947 * Pointer to flow attributes
5948 * @param[in] external
5949 * This flow rule is created by request external to PMD.
5951 * Pointer to error structure.
5954 * - 0 on success and non root table.
5955 * - 1 on success and root table.
5956 * - a negative errno value otherwise and rte_errno is set.
5959 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5960 const struct mlx5_flow_tunnel *tunnel,
5961 const struct rte_flow_attr *attributes,
5962 const struct flow_grp_info *grp_info,
5963 struct rte_flow_error *error)
5965 struct mlx5_priv *priv = dev->data->dev_private;
5966 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5969 #ifndef HAVE_MLX5DV_DR
5970 RTE_SET_USED(tunnel);
5971 RTE_SET_USED(grp_info);
5972 if (attributes->group)
5973 return rte_flow_error_set(error, ENOTSUP,
5974 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5976 "groups are not supported");
5980 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5985 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5987 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5988 attributes->priority > lowest_priority)
5989 return rte_flow_error_set(error, ENOTSUP,
5990 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5992 "priority out of range");
5993 if (attributes->transfer) {
5994 if (!priv->config.dv_esw_en)
5995 return rte_flow_error_set
5997 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5998 "E-Switch dr is not supported");
5999 if (!(priv->representor || priv->master))
6000 return rte_flow_error_set
6001 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6002 NULL, "E-Switch configuration can only be"
6003 " done by a master or a representor device");
6004 if (attributes->egress)
6005 return rte_flow_error_set
6007 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6008 "egress is not supported");
6010 if (!(attributes->egress ^ attributes->ingress))
6011 return rte_flow_error_set(error, ENOTSUP,
6012 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6013 "must specify exactly one of "
6014 "ingress or egress");
6019 * Internal validation function. For validating both actions and items.
6022 * Pointer to the rte_eth_dev structure.
6024 * Pointer to the flow attributes.
6026 * Pointer to the list of items.
6027 * @param[in] actions
6028 * Pointer to the list of actions.
6029 * @param[in] external
6030 * This flow rule is created by request external to PMD.
6031 * @param[in] hairpin
6032 * Number of hairpin TX actions, 0 means classic flow.
6034 * Pointer to the error structure.
6037 * 0 on success, a negative errno value otherwise and rte_errno is set.
6040 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6041 const struct rte_flow_item items[],
6042 const struct rte_flow_action actions[],
6043 bool external, int hairpin, struct rte_flow_error *error)
6046 uint64_t action_flags = 0;
6047 uint64_t item_flags = 0;
6048 uint64_t last_item = 0;
6049 uint8_t next_protocol = 0xff;
6050 uint16_t ether_type = 0;
6052 uint8_t item_ipv6_proto = 0;
6053 int fdb_mirror_limit = 0;
6054 int modify_after_mirror = 0;
6055 const struct rte_flow_item *geneve_item = NULL;
6056 const struct rte_flow_item *gre_item = NULL;
6057 const struct rte_flow_item *gtp_item = NULL;
6058 const struct rte_flow_action_raw_decap *decap;
6059 const struct rte_flow_action_raw_encap *encap;
6060 const struct rte_flow_action_rss *rss = NULL;
6061 const struct rte_flow_action_rss *sample_rss = NULL;
6062 const struct rte_flow_action_count *count = NULL;
6063 const struct rte_flow_action_count *sample_count = NULL;
6064 const struct rte_flow_item_tcp nic_tcp_mask = {
6067 .src_port = RTE_BE16(UINT16_MAX),
6068 .dst_port = RTE_BE16(UINT16_MAX),
6071 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6074 "\xff\xff\xff\xff\xff\xff\xff\xff"
6075 "\xff\xff\xff\xff\xff\xff\xff\xff",
6077 "\xff\xff\xff\xff\xff\xff\xff\xff"
6078 "\xff\xff\xff\xff\xff\xff\xff\xff",
6079 .vtc_flow = RTE_BE32(0xffffffff),
6085 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6089 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6093 .dummy[0] = 0xffffffff,
6096 struct mlx5_priv *priv = dev->data->dev_private;
6097 struct mlx5_dev_config *dev_conf = &priv->config;
6098 uint16_t queue_index = 0xFFFF;
6099 const struct rte_flow_item_vlan *vlan_m = NULL;
6100 uint32_t rw_act_num = 0;
6102 const struct mlx5_flow_tunnel *tunnel;
6103 struct flow_grp_info grp_info = {
6104 .external = !!external,
6105 .transfer = !!attr->transfer,
6106 .fdb_def_rule = !!priv->fdb_def_rule,
6108 const struct rte_eth_hairpin_conf *conf;
6112 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6113 tunnel = flow_items_to_tunnel(items);
6114 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6115 MLX5_FLOW_ACTION_DECAP;
6116 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6117 tunnel = flow_actions_to_tunnel(actions);
6118 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6122 if (tunnel && priv->representor)
6123 return rte_flow_error_set(error, ENOTSUP,
6124 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6125 "decap not supported "
6126 "for VF representor");
6127 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6128 (dev, tunnel, attr, items, actions);
6129 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6132 is_root = (uint64_t)ret;
6133 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6134 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6135 int type = items->type;
6137 if (!mlx5_flow_os_item_supported(type))
6138 return rte_flow_error_set(error, ENOTSUP,
6139 RTE_FLOW_ERROR_TYPE_ITEM,
6140 NULL, "item not supported");
6142 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6143 if (items[0].type != (typeof(items[0].type))
6144 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6145 return rte_flow_error_set
6147 RTE_FLOW_ERROR_TYPE_ITEM,
6148 NULL, "MLX5 private items "
6149 "must be the first");
6151 case RTE_FLOW_ITEM_TYPE_VOID:
6153 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6154 ret = flow_dv_validate_item_port_id
6155 (dev, items, attr, item_flags, error);
6158 last_item = MLX5_FLOW_ITEM_PORT_ID;
6160 case RTE_FLOW_ITEM_TYPE_ETH:
6161 ret = mlx5_flow_validate_item_eth(items, item_flags,
6165 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6166 MLX5_FLOW_LAYER_OUTER_L2;
6167 if (items->mask != NULL && items->spec != NULL) {
6169 ((const struct rte_flow_item_eth *)
6172 ((const struct rte_flow_item_eth *)
6174 ether_type = rte_be_to_cpu_16(ether_type);
6179 case RTE_FLOW_ITEM_TYPE_VLAN:
6180 ret = flow_dv_validate_item_vlan(items, item_flags,
6184 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6185 MLX5_FLOW_LAYER_OUTER_VLAN;
6186 if (items->mask != NULL && items->spec != NULL) {
6188 ((const struct rte_flow_item_vlan *)
6189 items->spec)->inner_type;
6191 ((const struct rte_flow_item_vlan *)
6192 items->mask)->inner_type;
6193 ether_type = rte_be_to_cpu_16(ether_type);
6197 /* Store outer VLAN mask for of_push_vlan action. */
6199 vlan_m = items->mask;
6201 case RTE_FLOW_ITEM_TYPE_IPV4:
6202 mlx5_flow_tunnel_ip_check(items, next_protocol,
6203 &item_flags, &tunnel);
6204 ret = flow_dv_validate_item_ipv4(items, item_flags,
6205 last_item, ether_type,
6209 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6210 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6211 if (items->mask != NULL &&
6212 ((const struct rte_flow_item_ipv4 *)
6213 items->mask)->hdr.next_proto_id) {
6215 ((const struct rte_flow_item_ipv4 *)
6216 (items->spec))->hdr.next_proto_id;
6218 ((const struct rte_flow_item_ipv4 *)
6219 (items->mask))->hdr.next_proto_id;
6221 /* Reset for inner layer. */
6222 next_protocol = 0xff;
6225 case RTE_FLOW_ITEM_TYPE_IPV6:
6226 mlx5_flow_tunnel_ip_check(items, next_protocol,
6227 &item_flags, &tunnel);
6228 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6235 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6236 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6237 if (items->mask != NULL &&
6238 ((const struct rte_flow_item_ipv6 *)
6239 items->mask)->hdr.proto) {
6241 ((const struct rte_flow_item_ipv6 *)
6242 items->spec)->hdr.proto;
6244 ((const struct rte_flow_item_ipv6 *)
6245 items->spec)->hdr.proto;
6247 ((const struct rte_flow_item_ipv6 *)
6248 items->mask)->hdr.proto;
6250 /* Reset for inner layer. */
6251 next_protocol = 0xff;
6254 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6255 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6260 last_item = tunnel ?
6261 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6262 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6263 if (items->mask != NULL &&
6264 ((const struct rte_flow_item_ipv6_frag_ext *)
6265 items->mask)->hdr.next_header) {
6267 ((const struct rte_flow_item_ipv6_frag_ext *)
6268 items->spec)->hdr.next_header;
6270 ((const struct rte_flow_item_ipv6_frag_ext *)
6271 items->mask)->hdr.next_header;
6273 /* Reset for inner layer. */
6274 next_protocol = 0xff;
6277 case RTE_FLOW_ITEM_TYPE_TCP:
6278 ret = mlx5_flow_validate_item_tcp
6285 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6286 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6288 case RTE_FLOW_ITEM_TYPE_UDP:
6289 ret = mlx5_flow_validate_item_udp(items, item_flags,
6294 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6295 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6297 case RTE_FLOW_ITEM_TYPE_GRE:
6298 ret = mlx5_flow_validate_item_gre(items, item_flags,
6299 next_protocol, error);
6303 last_item = MLX5_FLOW_LAYER_GRE;
6305 case RTE_FLOW_ITEM_TYPE_NVGRE:
6306 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6311 last_item = MLX5_FLOW_LAYER_NVGRE;
6313 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6314 ret = mlx5_flow_validate_item_gre_key
6315 (items, item_flags, gre_item, error);
6318 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6320 case RTE_FLOW_ITEM_TYPE_VXLAN:
6321 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6325 last_item = MLX5_FLOW_LAYER_VXLAN;
6327 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6328 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6333 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6335 case RTE_FLOW_ITEM_TYPE_GENEVE:
6336 ret = mlx5_flow_validate_item_geneve(items,
6341 geneve_item = items;
6342 last_item = MLX5_FLOW_LAYER_GENEVE;
6344 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6345 ret = mlx5_flow_validate_item_geneve_opt(items,
6352 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6354 case RTE_FLOW_ITEM_TYPE_MPLS:
6355 ret = mlx5_flow_validate_item_mpls(dev, items,
6360 last_item = MLX5_FLOW_LAYER_MPLS;
6363 case RTE_FLOW_ITEM_TYPE_MARK:
6364 ret = flow_dv_validate_item_mark(dev, items, attr,
6368 last_item = MLX5_FLOW_ITEM_MARK;
6370 case RTE_FLOW_ITEM_TYPE_META:
6371 ret = flow_dv_validate_item_meta(dev, items, attr,
6375 last_item = MLX5_FLOW_ITEM_METADATA;
6377 case RTE_FLOW_ITEM_TYPE_ICMP:
6378 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6383 last_item = MLX5_FLOW_LAYER_ICMP;
6385 case RTE_FLOW_ITEM_TYPE_ICMP6:
6386 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6391 item_ipv6_proto = IPPROTO_ICMPV6;
6392 last_item = MLX5_FLOW_LAYER_ICMP6;
6394 case RTE_FLOW_ITEM_TYPE_TAG:
6395 ret = flow_dv_validate_item_tag(dev, items,
6399 last_item = MLX5_FLOW_ITEM_TAG;
6401 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6402 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6404 case RTE_FLOW_ITEM_TYPE_GTP:
6405 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6410 last_item = MLX5_FLOW_LAYER_GTP;
6412 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6413 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6418 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6420 case RTE_FLOW_ITEM_TYPE_ECPRI:
6421 /* Capacity will be checked in the translate stage. */
6422 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6429 last_item = MLX5_FLOW_LAYER_ECPRI;
6432 return rte_flow_error_set(error, ENOTSUP,
6433 RTE_FLOW_ERROR_TYPE_ITEM,
6434 NULL, "item not supported");
6436 item_flags |= last_item;
6438 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6439 int type = actions->type;
6441 if (!mlx5_flow_os_action_supported(type))
6442 return rte_flow_error_set(error, ENOTSUP,
6443 RTE_FLOW_ERROR_TYPE_ACTION,
6445 "action not supported");
6446 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6447 return rte_flow_error_set(error, ENOTSUP,
6448 RTE_FLOW_ERROR_TYPE_ACTION,
6449 actions, "too many actions");
6451 case RTE_FLOW_ACTION_TYPE_VOID:
6453 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6454 ret = flow_dv_validate_action_port_id(dev,
6461 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6464 case RTE_FLOW_ACTION_TYPE_FLAG:
6465 ret = flow_dv_validate_action_flag(dev, action_flags,
6469 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6470 /* Count all modify-header actions as one. */
6471 if (!(action_flags &
6472 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6474 action_flags |= MLX5_FLOW_ACTION_FLAG |
6475 MLX5_FLOW_ACTION_MARK_EXT;
6476 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6477 modify_after_mirror = 1;
6480 action_flags |= MLX5_FLOW_ACTION_FLAG;
6483 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6485 case RTE_FLOW_ACTION_TYPE_MARK:
6486 ret = flow_dv_validate_action_mark(dev, actions,
6491 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6492 /* Count all modify-header actions as one. */
6493 if (!(action_flags &
6494 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6496 action_flags |= MLX5_FLOW_ACTION_MARK |
6497 MLX5_FLOW_ACTION_MARK_EXT;
6498 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6499 modify_after_mirror = 1;
6501 action_flags |= MLX5_FLOW_ACTION_MARK;
6504 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6506 case RTE_FLOW_ACTION_TYPE_SET_META:
6507 ret = flow_dv_validate_action_set_meta(dev, actions,
6512 /* Count all modify-header actions as one action. */
6513 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6515 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6516 modify_after_mirror = 1;
6517 action_flags |= MLX5_FLOW_ACTION_SET_META;
6518 rw_act_num += MLX5_ACT_NUM_SET_META;
6520 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6521 ret = flow_dv_validate_action_set_tag(dev, actions,
6526 /* Count all modify-header actions as one action. */
6527 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6529 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6530 modify_after_mirror = 1;
6531 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6532 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6534 case RTE_FLOW_ACTION_TYPE_DROP:
6535 ret = mlx5_flow_validate_action_drop(action_flags,
6539 action_flags |= MLX5_FLOW_ACTION_DROP;
6542 case RTE_FLOW_ACTION_TYPE_QUEUE:
6543 ret = mlx5_flow_validate_action_queue(actions,
6548 queue_index = ((const struct rte_flow_action_queue *)
6549 (actions->conf))->index;
6550 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6553 case RTE_FLOW_ACTION_TYPE_RSS:
6554 rss = actions->conf;
6555 ret = mlx5_flow_validate_action_rss(actions,
6561 if (rss && sample_rss &&
6562 (sample_rss->level != rss->level ||
6563 sample_rss->types != rss->types))
6564 return rte_flow_error_set(error, ENOTSUP,
6565 RTE_FLOW_ERROR_TYPE_ACTION,
6567 "Can't use the different RSS types "
6568 "or level in the same flow");
6569 if (rss != NULL && rss->queue_num)
6570 queue_index = rss->queue[0];
6571 action_flags |= MLX5_FLOW_ACTION_RSS;
6574 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6576 mlx5_flow_validate_action_default_miss(action_flags,
6580 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6583 case RTE_FLOW_ACTION_TYPE_COUNT:
6584 ret = flow_dv_validate_action_count(dev, actions,
6589 count = actions->conf;
6590 action_flags |= MLX5_FLOW_ACTION_COUNT;
6593 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6594 if (flow_dv_validate_action_pop_vlan(dev,
6600 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6603 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6604 ret = flow_dv_validate_action_push_vlan(dev,
6611 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6614 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6615 ret = flow_dv_validate_action_set_vlan_pcp
6616 (action_flags, actions, error);
6619 /* Count PCP with push_vlan command. */
6620 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6622 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6623 ret = flow_dv_validate_action_set_vlan_vid
6624 (item_flags, action_flags,
6628 /* Count VID with push_vlan command. */
6629 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6630 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6632 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6633 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6634 ret = flow_dv_validate_action_l2_encap(dev,
6640 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6643 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6644 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6645 ret = flow_dv_validate_action_decap(dev, action_flags,
6646 actions, item_flags,
6650 action_flags |= MLX5_FLOW_ACTION_DECAP;
6653 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6654 ret = flow_dv_validate_action_raw_encap_decap
6655 (dev, NULL, actions->conf, attr, &action_flags,
6656 &actions_n, actions, item_flags, error);
6660 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6661 decap = actions->conf;
6662 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6664 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6668 encap = actions->conf;
6670 ret = flow_dv_validate_action_raw_encap_decap
6672 decap ? decap : &empty_decap, encap,
6673 attr, &action_flags, &actions_n,
6674 actions, item_flags, error);
6678 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6679 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6680 ret = flow_dv_validate_action_modify_mac(action_flags,
6686 /* Count all modify-header actions as one action. */
6687 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6689 action_flags |= actions->type ==
6690 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6691 MLX5_FLOW_ACTION_SET_MAC_SRC :
6692 MLX5_FLOW_ACTION_SET_MAC_DST;
6693 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6694 modify_after_mirror = 1;
6696 * Even if the source and destination MAC addresses have
6697 * overlap in the header with 4B alignment, the convert
6698 * function will handle them separately and 4 SW actions
6699 * will be created. And 2 actions will be added each
6700 * time no matter how many bytes of address will be set.
6702 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6704 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6705 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6706 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6712 /* Count all modify-header actions as one action. */
6713 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6715 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6716 modify_after_mirror = 1;
6717 action_flags |= actions->type ==
6718 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6719 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6720 MLX5_FLOW_ACTION_SET_IPV4_DST;
6721 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6723 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6724 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6725 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6731 if (item_ipv6_proto == IPPROTO_ICMPV6)
6732 return rte_flow_error_set(error, ENOTSUP,
6733 RTE_FLOW_ERROR_TYPE_ACTION,
6735 "Can't change header "
6736 "with ICMPv6 proto");
6737 /* Count all modify-header actions as one action. */
6738 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6740 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6741 modify_after_mirror = 1;
6742 action_flags |= actions->type ==
6743 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6744 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6745 MLX5_FLOW_ACTION_SET_IPV6_DST;
6746 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6748 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6749 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6750 ret = flow_dv_validate_action_modify_tp(action_flags,
6756 /* Count all modify-header actions as one action. */
6757 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6759 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6760 modify_after_mirror = 1;
6761 action_flags |= actions->type ==
6762 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6763 MLX5_FLOW_ACTION_SET_TP_SRC :
6764 MLX5_FLOW_ACTION_SET_TP_DST;
6765 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6767 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6768 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6769 ret = flow_dv_validate_action_modify_ttl(action_flags,
6775 /* Count all modify-header actions as one action. */
6776 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6778 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6779 modify_after_mirror = 1;
6780 action_flags |= actions->type ==
6781 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6782 MLX5_FLOW_ACTION_SET_TTL :
6783 MLX5_FLOW_ACTION_DEC_TTL;
6784 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6786 case RTE_FLOW_ACTION_TYPE_JUMP:
6787 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6793 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6795 return rte_flow_error_set(error, EINVAL,
6796 RTE_FLOW_ERROR_TYPE_ACTION,
6798 "sample and jump action combination is not supported");
6800 action_flags |= MLX5_FLOW_ACTION_JUMP;
6802 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6803 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6804 ret = flow_dv_validate_action_modify_tcp_seq
6811 /* Count all modify-header actions as one action. */
6812 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6814 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6815 modify_after_mirror = 1;
6816 action_flags |= actions->type ==
6817 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6818 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6819 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6820 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6822 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6823 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6824 ret = flow_dv_validate_action_modify_tcp_ack
6831 /* Count all modify-header actions as one action. */
6832 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6834 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6835 modify_after_mirror = 1;
6836 action_flags |= actions->type ==
6837 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6838 MLX5_FLOW_ACTION_INC_TCP_ACK :
6839 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6840 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6842 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6844 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6845 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6846 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6848 case RTE_FLOW_ACTION_TYPE_METER:
6849 ret = mlx5_flow_validate_action_meter(dev,
6855 action_flags |= MLX5_FLOW_ACTION_METER;
6857 /* Meter action will add one more TAG action. */
6858 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6860 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6861 if (!attr->transfer && !attr->group)
6862 return rte_flow_error_set(error, ENOTSUP,
6863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6865 "Shared ASO age action is not supported for group 0");
6866 action_flags |= MLX5_FLOW_ACTION_AGE;
6869 case RTE_FLOW_ACTION_TYPE_AGE:
6870 ret = flow_dv_validate_action_age(action_flags,
6876 * Validate the regular AGE action (using counter)
6877 * mutual exclusion with share counter actions.
6879 if (!priv->sh->flow_hit_aso_en) {
6880 if (count && count->shared)
6881 return rte_flow_error_set
6883 RTE_FLOW_ERROR_TYPE_ACTION,
6885 "old age and shared count combination is not supported");
6887 return rte_flow_error_set
6889 RTE_FLOW_ERROR_TYPE_ACTION,
6891 "old age action and count must be in the same sub flow");
6893 action_flags |= MLX5_FLOW_ACTION_AGE;
6896 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6897 ret = flow_dv_validate_action_modify_ipv4_dscp
6904 /* Count all modify-header actions as one action. */
6905 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6907 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6908 modify_after_mirror = 1;
6909 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6910 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6912 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6913 ret = flow_dv_validate_action_modify_ipv6_dscp
6920 /* Count all modify-header actions as one action. */
6921 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6923 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6924 modify_after_mirror = 1;
6925 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6926 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6928 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6929 ret = flow_dv_validate_action_sample(&action_flags,
6938 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6941 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6942 if (actions[0].type != (typeof(actions[0].type))
6943 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6944 return rte_flow_error_set
6946 RTE_FLOW_ERROR_TYPE_ACTION,
6947 NULL, "MLX5 private action "
6948 "must be the first");
6950 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6952 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6953 ret = flow_dv_validate_action_modify_field(dev,
6960 /* Count all modify-header actions as one action. */
6961 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6963 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6967 return rte_flow_error_set(error, ENOTSUP,
6968 RTE_FLOW_ERROR_TYPE_ACTION,
6970 "action not supported");
6974 * Validate actions in flow rules
6975 * - Explicit decap action is prohibited by the tunnel offload API.
6976 * - Drop action in tunnel steer rule is prohibited by the API.
6977 * - Application cannot use MARK action because it's value can mask
6978 * tunnel default miss nitification.
6979 * - JUMP in tunnel match rule has no support in current PMD
6981 * - TAG & META are reserved for future uses.
6983 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6984 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6985 MLX5_FLOW_ACTION_MARK |
6986 MLX5_FLOW_ACTION_SET_TAG |
6987 MLX5_FLOW_ACTION_SET_META |
6988 MLX5_FLOW_ACTION_DROP;
6990 if (action_flags & bad_actions_mask)
6991 return rte_flow_error_set
6993 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6994 "Invalid RTE action in tunnel "
6996 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6997 return rte_flow_error_set
6999 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7000 "tunnel set decap rule must terminate "
7003 return rte_flow_error_set
7005 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7006 "tunnel flows for ingress traffic only");
7008 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7009 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7010 MLX5_FLOW_ACTION_MARK |
7011 MLX5_FLOW_ACTION_SET_TAG |
7012 MLX5_FLOW_ACTION_SET_META;
7014 if (action_flags & bad_actions_mask)
7015 return rte_flow_error_set
7017 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7018 "Invalid RTE action in tunnel "
7022 * Validate the drop action mutual exclusion with other actions.
7023 * Drop action is mutually-exclusive with any other action, except for
7025 * Drop action compatibility with tunnel offload was already validated.
7027 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7028 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7029 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7030 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7031 return rte_flow_error_set(error, EINVAL,
7032 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7033 "Drop action is mutually-exclusive "
7034 "with any other action, except for "
7036 /* Eswitch has few restrictions on using items and actions */
7037 if (attr->transfer) {
7038 if (!mlx5_flow_ext_mreg_supported(dev) &&
7039 action_flags & MLX5_FLOW_ACTION_FLAG)
7040 return rte_flow_error_set(error, ENOTSUP,
7041 RTE_FLOW_ERROR_TYPE_ACTION,
7043 "unsupported action FLAG");
7044 if (!mlx5_flow_ext_mreg_supported(dev) &&
7045 action_flags & MLX5_FLOW_ACTION_MARK)
7046 return rte_flow_error_set(error, ENOTSUP,
7047 RTE_FLOW_ERROR_TYPE_ACTION,
7049 "unsupported action MARK");
7050 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7051 return rte_flow_error_set(error, ENOTSUP,
7052 RTE_FLOW_ERROR_TYPE_ACTION,
7054 "unsupported action QUEUE");
7055 if (action_flags & MLX5_FLOW_ACTION_RSS)
7056 return rte_flow_error_set(error, ENOTSUP,
7057 RTE_FLOW_ERROR_TYPE_ACTION,
7059 "unsupported action RSS");
7060 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7061 return rte_flow_error_set(error, EINVAL,
7062 RTE_FLOW_ERROR_TYPE_ACTION,
7064 "no fate action is found");
7066 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7067 return rte_flow_error_set(error, EINVAL,
7068 RTE_FLOW_ERROR_TYPE_ACTION,
7070 "no fate action is found");
7073 * Continue validation for Xcap and VLAN actions.
7074 * If hairpin is working in explicit TX rule mode, there is no actions
7075 * splitting and the validation of hairpin ingress flow should be the
7076 * same as other standard flows.
7078 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7079 MLX5_FLOW_VLAN_ACTIONS)) &&
7080 (queue_index == 0xFFFF ||
7081 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7082 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7083 conf->tx_explicit != 0))) {
7084 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7085 MLX5_FLOW_XCAP_ACTIONS)
7086 return rte_flow_error_set(error, ENOTSUP,
7087 RTE_FLOW_ERROR_TYPE_ACTION,
7088 NULL, "encap and decap "
7089 "combination aren't supported");
7090 if (!attr->transfer && attr->ingress) {
7091 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7092 return rte_flow_error_set
7094 RTE_FLOW_ERROR_TYPE_ACTION,
7095 NULL, "encap is not supported"
7096 " for ingress traffic");
7097 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7098 return rte_flow_error_set
7100 RTE_FLOW_ERROR_TYPE_ACTION,
7101 NULL, "push VLAN action not "
7102 "supported for ingress");
7103 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7104 MLX5_FLOW_VLAN_ACTIONS)
7105 return rte_flow_error_set
7107 RTE_FLOW_ERROR_TYPE_ACTION,
7108 NULL, "no support for "
7109 "multiple VLAN actions");
7113 * Hairpin flow will add one more TAG action in TX implicit mode.
7114 * In TX explicit mode, there will be no hairpin flow ID.
7117 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7118 /* extra metadata enabled: one more TAG action will be add. */
7119 if (dev_conf->dv_flow_en &&
7120 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7121 mlx5_flow_ext_mreg_supported(dev))
7122 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7124 flow_dv_modify_hdr_action_max(dev, is_root)) {
7125 return rte_flow_error_set(error, ENOTSUP,
7126 RTE_FLOW_ERROR_TYPE_ACTION,
7127 NULL, "too many header modify"
7128 " actions to support");
7130 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7131 if (fdb_mirror_limit && modify_after_mirror)
7132 return rte_flow_error_set(error, EINVAL,
7133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7134 "sample before modify action is not supported");
7139 * Internal preparation function. Allocates the DV flow size,
7140 * this size is constant.
7143 * Pointer to the rte_eth_dev structure.
7145 * Pointer to the flow attributes.
7147 * Pointer to the list of items.
7148 * @param[in] actions
7149 * Pointer to the list of actions.
7151 * Pointer to the error structure.
7154 * Pointer to mlx5_flow object on success,
7155 * otherwise NULL and rte_errno is set.
7157 static struct mlx5_flow *
7158 flow_dv_prepare(struct rte_eth_dev *dev,
7159 const struct rte_flow_attr *attr __rte_unused,
7160 const struct rte_flow_item items[] __rte_unused,
7161 const struct rte_flow_action actions[] __rte_unused,
7162 struct rte_flow_error *error)
7164 uint32_t handle_idx = 0;
7165 struct mlx5_flow *dev_flow;
7166 struct mlx5_flow_handle *dev_handle;
7167 struct mlx5_priv *priv = dev->data->dev_private;
7168 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7171 /* In case of corrupting the memory. */
7172 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7173 rte_flow_error_set(error, ENOSPC,
7174 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7175 "not free temporary device flow");
7178 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7181 rte_flow_error_set(error, ENOMEM,
7182 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7183 "not enough memory to create flow handle");
7186 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7187 dev_flow = &wks->flows[wks->flow_idx++];
7188 memset(dev_flow, 0, sizeof(*dev_flow));
7189 dev_flow->handle = dev_handle;
7190 dev_flow->handle_idx = handle_idx;
7192 * In some old rdma-core releases, before continuing, a check of the
7193 * length of matching parameter will be done at first. It needs to use
7194 * the length without misc4 param. If the flow has misc4 support, then
7195 * the length needs to be adjusted accordingly. Each param member is
7196 * aligned with a 64B boundary naturally.
7198 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7199 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7200 dev_flow->ingress = attr->ingress;
7201 dev_flow->dv.transfer = attr->transfer;
7205 #ifdef RTE_LIBRTE_MLX5_DEBUG
7207 * Sanity check for match mask and value. Similar to check_valid_spec() in
7208 * kernel driver. If unmasked bit is present in value, it returns failure.
7211 * pointer to match mask buffer.
7212 * @param match_value
7213 * pointer to match value buffer.
7216 * 0 if valid, -EINVAL otherwise.
7219 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7221 uint8_t *m = match_mask;
7222 uint8_t *v = match_value;
7225 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7228 "match_value differs from match_criteria"
7229 " %p[%u] != %p[%u]",
7230 match_value, i, match_mask, i);
7239 * Add match of ip_version.
7243 * @param[in] headers_v
7244 * Values header pointer.
7245 * @param[in] headers_m
7246 * Masks header pointer.
7247 * @param[in] ip_version
7248 * The IP version to set.
7251 flow_dv_set_match_ip_version(uint32_t group,
7257 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7259 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7261 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7263 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7267 * Add Ethernet item to matcher and to the value.
7269 * @param[in, out] matcher
7271 * @param[in, out] key
7272 * Flow matcher value.
7274 * Flow pattern to translate.
7276 * Item is inner pattern.
7279 flow_dv_translate_item_eth(void *matcher, void *key,
7280 const struct rte_flow_item *item, int inner,
7283 const struct rte_flow_item_eth *eth_m = item->mask;
7284 const struct rte_flow_item_eth *eth_v = item->spec;
7285 const struct rte_flow_item_eth nic_mask = {
7286 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7287 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7288 .type = RTE_BE16(0xffff),
7301 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7303 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7305 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7307 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7309 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7310 ð_m->dst, sizeof(eth_m->dst));
7311 /* The value must be in the range of the mask. */
7312 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7313 for (i = 0; i < sizeof(eth_m->dst); ++i)
7314 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7315 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7316 ð_m->src, sizeof(eth_m->src));
7317 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7318 /* The value must be in the range of the mask. */
7319 for (i = 0; i < sizeof(eth_m->dst); ++i)
7320 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7322 * HW supports match on one Ethertype, the Ethertype following the last
7323 * VLAN tag of the packet (see PRM).
7324 * Set match on ethertype only if ETH header is not followed by VLAN.
7325 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7326 * ethertype, and use ip_version field instead.
7327 * eCPRI over Ether layer will use type value 0xAEFE.
7329 if (eth_m->type == 0xFFFF) {
7330 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7331 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7332 switch (eth_v->type) {
7333 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7336 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7338 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7340 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7341 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7343 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7344 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7350 if (eth_m->has_vlan) {
7351 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7352 if (eth_v->has_vlan) {
7354 * Here, when also has_more_vlan field in VLAN item is
7355 * not set, only single-tagged packets will be matched.
7357 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7361 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7362 rte_be_to_cpu_16(eth_m->type));
7363 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7364 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7368 * Add VLAN item to matcher and to the value.
7370 * @param[in, out] dev_flow
7372 * @param[in, out] matcher
7374 * @param[in, out] key
7375 * Flow matcher value.
7377 * Flow pattern to translate.
7379 * Item is inner pattern.
7382 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7383 void *matcher, void *key,
7384 const struct rte_flow_item *item,
7385 int inner, uint32_t group)
7387 const struct rte_flow_item_vlan *vlan_m = item->mask;
7388 const struct rte_flow_item_vlan *vlan_v = item->spec;
7395 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7397 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7399 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7401 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7403 * This is workaround, masks are not supported,
7404 * and pre-validated.
7407 dev_flow->handle->vf_vlan.tag =
7408 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7411 * When VLAN item exists in flow, mark packet as tagged,
7412 * even if TCI is not specified.
7414 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7415 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7416 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7421 vlan_m = &rte_flow_item_vlan_mask;
7422 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7423 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7424 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7425 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7426 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7427 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7428 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7429 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7431 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7432 * ethertype, and use ip_version field instead.
7434 if (vlan_m->inner_type == 0xFFFF) {
7435 switch (vlan_v->inner_type) {
7436 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7437 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7438 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7439 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7441 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7442 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7444 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7445 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7451 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7452 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7453 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7454 /* Only one vlan_tag bit can be set. */
7455 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7458 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7459 rte_be_to_cpu_16(vlan_m->inner_type));
7460 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7461 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7465 * Add IPV4 item to matcher and to the value.
7467 * @param[in, out] matcher
7469 * @param[in, out] key
7470 * Flow matcher value.
7472 * Flow pattern to translate.
7474 * Item is inner pattern.
7476 * The group to insert the rule.
7479 flow_dv_translate_item_ipv4(void *matcher, void *key,
7480 const struct rte_flow_item *item,
7481 int inner, uint32_t group)
7483 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7484 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7485 const struct rte_flow_item_ipv4 nic_mask = {
7487 .src_addr = RTE_BE32(0xffffffff),
7488 .dst_addr = RTE_BE32(0xffffffff),
7489 .type_of_service = 0xff,
7490 .next_proto_id = 0xff,
7491 .time_to_live = 0xff,
7501 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7503 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7505 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7507 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7509 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7514 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7515 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7516 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7517 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7518 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7519 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7520 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7521 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7522 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7523 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7524 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7525 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7526 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7528 ipv4_m->hdr.type_of_service);
7529 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7531 ipv4_m->hdr.type_of_service >> 2);
7532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7533 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7534 ipv4_m->hdr.next_proto_id);
7535 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7536 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7537 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7538 ipv4_m->hdr.time_to_live);
7539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7540 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7542 !!(ipv4_m->hdr.fragment_offset));
7543 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7544 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7548 * Add IPV6 item to matcher and to the value.
7550 * @param[in, out] matcher
7552 * @param[in, out] key
7553 * Flow matcher value.
7555 * Flow pattern to translate.
7557 * Item is inner pattern.
7559 * The group to insert the rule.
7562 flow_dv_translate_item_ipv6(void *matcher, void *key,
7563 const struct rte_flow_item *item,
7564 int inner, uint32_t group)
7566 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7567 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7568 const struct rte_flow_item_ipv6 nic_mask = {
7571 "\xff\xff\xff\xff\xff\xff\xff\xff"
7572 "\xff\xff\xff\xff\xff\xff\xff\xff",
7574 "\xff\xff\xff\xff\xff\xff\xff\xff"
7575 "\xff\xff\xff\xff\xff\xff\xff\xff",
7576 .vtc_flow = RTE_BE32(0xffffffff),
7583 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7584 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7593 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7595 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7599 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7601 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7606 size = sizeof(ipv6_m->hdr.dst_addr);
7607 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7608 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7609 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7610 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7611 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7612 for (i = 0; i < size; ++i)
7613 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7614 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7615 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7616 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7617 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7618 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7619 for (i = 0; i < size; ++i)
7620 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7622 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7623 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7625 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7626 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7627 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7630 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7632 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7635 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7637 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7643 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7644 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7646 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7647 ipv6_m->hdr.hop_limits);
7648 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7649 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7651 !!(ipv6_m->has_frag_ext));
7652 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7653 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7657 * Add IPV6 fragment extension item to matcher and to the value.
7659 * @param[in, out] matcher
7661 * @param[in, out] key
7662 * Flow matcher value.
7664 * Flow pattern to translate.
7666 * Item is inner pattern.
7669 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7670 const struct rte_flow_item *item,
7673 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7674 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7675 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7677 .next_header = 0xff,
7678 .frag_data = RTE_BE16(0xffff),
7685 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7687 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7689 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7691 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7693 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7696 if (!ipv6_frag_ext_v)
7698 if (!ipv6_frag_ext_m)
7699 ipv6_frag_ext_m = &nic_mask;
7700 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7701 ipv6_frag_ext_m->hdr.next_header);
7702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7703 ipv6_frag_ext_v->hdr.next_header &
7704 ipv6_frag_ext_m->hdr.next_header);
7708 * Add TCP item to matcher and to the value.
7710 * @param[in, out] matcher
7712 * @param[in, out] key
7713 * Flow matcher value.
7715 * Flow pattern to translate.
7717 * Item is inner pattern.
7720 flow_dv_translate_item_tcp(void *matcher, void *key,
7721 const struct rte_flow_item *item,
7724 const struct rte_flow_item_tcp *tcp_m = item->mask;
7725 const struct rte_flow_item_tcp *tcp_v = item->spec;
7730 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7732 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7734 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7736 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7738 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7743 tcp_m = &rte_flow_item_tcp_mask;
7744 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7745 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7746 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7747 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7748 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7749 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7750 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7751 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7752 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7753 tcp_m->hdr.tcp_flags);
7754 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7755 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7759 * Add UDP item to matcher and to the value.
7761 * @param[in, out] matcher
7763 * @param[in, out] key
7764 * Flow matcher value.
7766 * Flow pattern to translate.
7768 * Item is inner pattern.
7771 flow_dv_translate_item_udp(void *matcher, void *key,
7772 const struct rte_flow_item *item,
7775 const struct rte_flow_item_udp *udp_m = item->mask;
7776 const struct rte_flow_item_udp *udp_v = item->spec;
7781 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7783 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7785 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7787 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7789 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7790 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7794 udp_m = &rte_flow_item_udp_mask;
7795 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7796 rte_be_to_cpu_16(udp_m->hdr.src_port));
7797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7798 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7799 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7800 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7801 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7802 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7806 * Add GRE optional Key item to matcher and to the value.
7808 * @param[in, out] matcher
7810 * @param[in, out] key
7811 * Flow matcher value.
7813 * Flow pattern to translate.
7815 * Item is inner pattern.
7818 flow_dv_translate_item_gre_key(void *matcher, void *key,
7819 const struct rte_flow_item *item)
7821 const rte_be32_t *key_m = item->mask;
7822 const rte_be32_t *key_v = item->spec;
7823 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7824 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7825 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7827 /* GRE K bit must be on and should already be validated */
7828 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7829 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7833 key_m = &gre_key_default_mask;
7834 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7835 rte_be_to_cpu_32(*key_m) >> 8);
7836 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7837 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7838 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7839 rte_be_to_cpu_32(*key_m) & 0xFF);
7840 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7841 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7845 * Add GRE item to matcher and to the value.
7847 * @param[in, out] matcher
7849 * @param[in, out] key
7850 * Flow matcher value.
7852 * Flow pattern to translate.
7854 * Item is inner pattern.
7857 flow_dv_translate_item_gre(void *matcher, void *key,
7858 const struct rte_flow_item *item,
7861 const struct rte_flow_item_gre *gre_m = item->mask;
7862 const struct rte_flow_item_gre *gre_v = item->spec;
7865 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7866 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7873 uint16_t s_present:1;
7874 uint16_t k_present:1;
7875 uint16_t rsvd_bit1:1;
7876 uint16_t c_present:1;
7880 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7883 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7885 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7887 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7889 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7891 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7892 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7896 gre_m = &rte_flow_item_gre_mask;
7897 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7898 rte_be_to_cpu_16(gre_m->protocol));
7899 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7900 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7901 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7902 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7903 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7904 gre_crks_rsvd0_ver_m.c_present);
7905 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7906 gre_crks_rsvd0_ver_v.c_present &
7907 gre_crks_rsvd0_ver_m.c_present);
7908 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7909 gre_crks_rsvd0_ver_m.k_present);
7910 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7911 gre_crks_rsvd0_ver_v.k_present &
7912 gre_crks_rsvd0_ver_m.k_present);
7913 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7914 gre_crks_rsvd0_ver_m.s_present);
7915 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7916 gre_crks_rsvd0_ver_v.s_present &
7917 gre_crks_rsvd0_ver_m.s_present);
7921 * Add NVGRE item to matcher and to the value.
7923 * @param[in, out] matcher
7925 * @param[in, out] key
7926 * Flow matcher value.
7928 * Flow pattern to translate.
7930 * Item is inner pattern.
7933 flow_dv_translate_item_nvgre(void *matcher, void *key,
7934 const struct rte_flow_item *item,
7937 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7938 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7939 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7940 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7941 const char *tni_flow_id_m;
7942 const char *tni_flow_id_v;
7948 /* For NVGRE, GRE header fields must be set with defined values. */
7949 const struct rte_flow_item_gre gre_spec = {
7950 .c_rsvd0_ver = RTE_BE16(0x2000),
7951 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7953 const struct rte_flow_item_gre gre_mask = {
7954 .c_rsvd0_ver = RTE_BE16(0xB000),
7955 .protocol = RTE_BE16(UINT16_MAX),
7957 const struct rte_flow_item gre_item = {
7962 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7966 nvgre_m = &rte_flow_item_nvgre_mask;
7967 tni_flow_id_m = (const char *)nvgre_m->tni;
7968 tni_flow_id_v = (const char *)nvgre_v->tni;
7969 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7970 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7971 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7972 memcpy(gre_key_m, tni_flow_id_m, size);
7973 for (i = 0; i < size; ++i)
7974 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7978 * Add VXLAN item to matcher and to the value.
7980 * @param[in, out] matcher
7982 * @param[in, out] key
7983 * Flow matcher value.
7985 * Flow pattern to translate.
7987 * Item is inner pattern.
7990 flow_dv_translate_item_vxlan(void *matcher, void *key,
7991 const struct rte_flow_item *item,
7994 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7995 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7998 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7999 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8007 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8009 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8011 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8013 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8015 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8016 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8017 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8018 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8019 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8024 vxlan_m = &rte_flow_item_vxlan_mask;
8025 size = sizeof(vxlan_m->vni);
8026 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8027 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8028 memcpy(vni_m, vxlan_m->vni, size);
8029 for (i = 0; i < size; ++i)
8030 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8034 * Add VXLAN-GPE item to matcher and to the value.
8036 * @param[in, out] matcher
8038 * @param[in, out] key
8039 * Flow matcher value.
8041 * Flow pattern to translate.
8043 * Item is inner pattern.
8047 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8048 const struct rte_flow_item *item, int inner)
8050 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8051 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8055 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8057 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8063 uint8_t flags_m = 0xff;
8064 uint8_t flags_v = 0xc;
8067 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8069 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8071 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8073 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8075 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8076 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8077 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8078 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8084 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8085 size = sizeof(vxlan_m->vni);
8086 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8087 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8088 memcpy(vni_m, vxlan_m->vni, size);
8089 for (i = 0; i < size; ++i)
8090 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8091 if (vxlan_m->flags) {
8092 flags_m = vxlan_m->flags;
8093 flags_v = vxlan_v->flags;
8095 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8096 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8097 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8099 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8104 * Add Geneve item to matcher and to the value.
8106 * @param[in, out] matcher
8108 * @param[in, out] key
8109 * Flow matcher value.
8111 * Flow pattern to translate.
8113 * Item is inner pattern.
8117 flow_dv_translate_item_geneve(void *matcher, void *key,
8118 const struct rte_flow_item *item, int inner)
8120 const struct rte_flow_item_geneve *geneve_m = item->mask;
8121 const struct rte_flow_item_geneve *geneve_v = item->spec;
8124 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8125 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8134 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8136 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8138 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8140 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8142 dport = MLX5_UDP_PORT_GENEVE;
8143 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8144 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8145 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8150 geneve_m = &rte_flow_item_geneve_mask;
8151 size = sizeof(geneve_m->vni);
8152 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8153 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8154 memcpy(vni_m, geneve_m->vni, size);
8155 for (i = 0; i < size; ++i)
8156 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8157 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8158 rte_be_to_cpu_16(geneve_m->protocol));
8159 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8160 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8161 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8162 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8163 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8164 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8165 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8166 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8167 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8168 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8169 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8170 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8171 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8175 * Create Geneve TLV option resource.
8177 * @param dev[in, out]
8178 * Pointer to rte_eth_dev structure.
8179 * @param[in, out] tag_be24
8180 * Tag value in big endian then R-shift 8.
8181 * @parm[in, out] dev_flow
8182 * Pointer to the dev_flow.
8184 * pointer to error structure.
8187 * 0 on success otherwise -errno and errno is set.
8191 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8192 const struct rte_flow_item *item,
8193 struct rte_flow_error *error)
8195 struct mlx5_priv *priv = dev->data->dev_private;
8196 struct mlx5_dev_ctx_shared *sh = priv->sh;
8197 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8198 sh->geneve_tlv_option_resource;
8199 struct mlx5_devx_obj *obj;
8200 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8205 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8206 if (geneve_opt_resource != NULL) {
8207 if (geneve_opt_resource->option_class ==
8208 geneve_opt_v->option_class &&
8209 geneve_opt_resource->option_type ==
8210 geneve_opt_v->option_type &&
8211 geneve_opt_resource->length ==
8212 geneve_opt_v->option_len) {
8213 /* We already have GENVE TLV option obj allocated. */
8214 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8217 ret = rte_flow_error_set(error, ENOMEM,
8218 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8219 "Only one GENEVE TLV option supported");
8223 /* Create a GENEVE TLV object and resource. */
8224 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8225 geneve_opt_v->option_class,
8226 geneve_opt_v->option_type,
8227 geneve_opt_v->option_len);
8229 ret = rte_flow_error_set(error, ENODATA,
8230 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8231 "Failed to create GENEVE TLV Devx object");
8234 sh->geneve_tlv_option_resource =
8235 mlx5_malloc(MLX5_MEM_ZERO,
8236 sizeof(*geneve_opt_resource),
8238 if (!sh->geneve_tlv_option_resource) {
8239 claim_zero(mlx5_devx_cmd_destroy(obj));
8240 ret = rte_flow_error_set(error, ENOMEM,
8241 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8242 "GENEVE TLV object memory allocation failed");
8245 geneve_opt_resource = sh->geneve_tlv_option_resource;
8246 geneve_opt_resource->obj = obj;
8247 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8248 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8249 geneve_opt_resource->length = geneve_opt_v->option_len;
8250 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8254 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8259 * Add Geneve TLV option item to matcher.
8261 * @param[in, out] dev
8262 * Pointer to rte_eth_dev structure.
8263 * @param[in, out] matcher
8265 * @param[in, out] key
8266 * Flow matcher value.
8268 * Flow pattern to translate.
8270 * Pointer to error structure.
8273 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8274 void *key, const struct rte_flow_item *item,
8275 struct rte_flow_error *error)
8277 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8278 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8279 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8280 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8281 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8283 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8284 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8290 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8291 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8294 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8298 * Set the option length in GENEVE header if not requested.
8299 * The GENEVE TLV option length is expressed by the option length field
8300 * in the GENEVE header.
8301 * If the option length was not requested but the GENEVE TLV option item
8302 * is present we set the option length field implicitly.
8304 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8305 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8306 MLX5_GENEVE_OPTLEN_MASK);
8307 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8308 geneve_opt_v->option_len + 1);
8311 if (geneve_opt_v->data) {
8312 memcpy(&opt_data_key, geneve_opt_v->data,
8313 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8314 sizeof(opt_data_key)));
8315 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8316 sizeof(opt_data_key));
8317 memcpy(&opt_data_mask, geneve_opt_m->data,
8318 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8319 sizeof(opt_data_mask)));
8320 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8321 sizeof(opt_data_mask));
8322 MLX5_SET(fte_match_set_misc3, misc3_m,
8323 geneve_tlv_option_0_data,
8324 rte_be_to_cpu_32(opt_data_mask));
8325 MLX5_SET(fte_match_set_misc3, misc3_v,
8326 geneve_tlv_option_0_data,
8327 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8333 * Add MPLS item to matcher and to the value.
8335 * @param[in, out] matcher
8337 * @param[in, out] key
8338 * Flow matcher value.
8340 * Flow pattern to translate.
8341 * @param[in] prev_layer
8342 * The protocol layer indicated in previous item.
8344 * Item is inner pattern.
8347 flow_dv_translate_item_mpls(void *matcher, void *key,
8348 const struct rte_flow_item *item,
8349 uint64_t prev_layer,
8352 const uint32_t *in_mpls_m = item->mask;
8353 const uint32_t *in_mpls_v = item->spec;
8354 uint32_t *out_mpls_m = 0;
8355 uint32_t *out_mpls_v = 0;
8356 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8357 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8358 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8360 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8361 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8362 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8364 switch (prev_layer) {
8365 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8366 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8367 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8368 MLX5_UDP_PORT_MPLS);
8370 case MLX5_FLOW_LAYER_GRE:
8371 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8372 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8373 RTE_ETHER_TYPE_MPLS);
8376 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8377 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8384 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8385 switch (prev_layer) {
8386 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8388 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8389 outer_first_mpls_over_udp);
8391 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8392 outer_first_mpls_over_udp);
8394 case MLX5_FLOW_LAYER_GRE:
8396 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8397 outer_first_mpls_over_gre);
8399 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8400 outer_first_mpls_over_gre);
8403 /* Inner MPLS not over GRE is not supported. */
8406 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8410 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8416 if (out_mpls_m && out_mpls_v) {
8417 *out_mpls_m = *in_mpls_m;
8418 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8423 * Add metadata register item to matcher
8425 * @param[in, out] matcher
8427 * @param[in, out] key
8428 * Flow matcher value.
8429 * @param[in] reg_type
8430 * Type of device metadata register
8437 flow_dv_match_meta_reg(void *matcher, void *key,
8438 enum modify_reg reg_type,
8439 uint32_t data, uint32_t mask)
8442 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8444 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8450 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8451 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8454 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8455 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8459 * The metadata register C0 field might be divided into
8460 * source vport index and META item value, we should set
8461 * this field according to specified mask, not as whole one.
8463 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8465 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8466 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8469 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8472 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8473 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8476 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8477 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8480 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8481 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8484 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8485 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8488 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8489 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8492 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8493 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8496 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8497 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8506 * Add MARK item to matcher
8509 * The device to configure through.
8510 * @param[in, out] matcher
8512 * @param[in, out] key
8513 * Flow matcher value.
8515 * Flow pattern to translate.
8518 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8519 void *matcher, void *key,
8520 const struct rte_flow_item *item)
8522 struct mlx5_priv *priv = dev->data->dev_private;
8523 const struct rte_flow_item_mark *mark;
8527 mark = item->mask ? (const void *)item->mask :
8528 &rte_flow_item_mark_mask;
8529 mask = mark->id & priv->sh->dv_mark_mask;
8530 mark = (const void *)item->spec;
8532 value = mark->id & priv->sh->dv_mark_mask & mask;
8534 enum modify_reg reg;
8536 /* Get the metadata register index for the mark. */
8537 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8538 MLX5_ASSERT(reg > 0);
8539 if (reg == REG_C_0) {
8540 struct mlx5_priv *priv = dev->data->dev_private;
8541 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8542 uint32_t shl_c0 = rte_bsf32(msk_c0);
8548 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8553 * Add META item to matcher
8556 * The devich to configure through.
8557 * @param[in, out] matcher
8559 * @param[in, out] key
8560 * Flow matcher value.
8562 * Attributes of flow that includes this item.
8564 * Flow pattern to translate.
8567 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8568 void *matcher, void *key,
8569 const struct rte_flow_attr *attr,
8570 const struct rte_flow_item *item)
8572 const struct rte_flow_item_meta *meta_m;
8573 const struct rte_flow_item_meta *meta_v;
8575 meta_m = (const void *)item->mask;
8577 meta_m = &rte_flow_item_meta_mask;
8578 meta_v = (const void *)item->spec;
8581 uint32_t value = meta_v->data;
8582 uint32_t mask = meta_m->data;
8584 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8587 MLX5_ASSERT(reg != REG_NON);
8589 * In datapath code there is no endianness
8590 * coversions for perfromance reasons, all
8591 * pattern conversions are done in rte_flow.
8593 value = rte_cpu_to_be_32(value);
8594 mask = rte_cpu_to_be_32(mask);
8595 if (reg == REG_C_0) {
8596 struct mlx5_priv *priv = dev->data->dev_private;
8597 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8598 uint32_t shl_c0 = rte_bsf32(msk_c0);
8599 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8600 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8607 MLX5_ASSERT(msk_c0);
8608 MLX5_ASSERT(!(~msk_c0 & mask));
8610 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8615 * Add vport metadata Reg C0 item to matcher
8617 * @param[in, out] matcher
8619 * @param[in, out] key
8620 * Flow matcher value.
8622 * Flow pattern to translate.
8625 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8626 uint32_t value, uint32_t mask)
8628 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8632 * Add tag item to matcher
8635 * The devich to configure through.
8636 * @param[in, out] matcher
8638 * @param[in, out] key
8639 * Flow matcher value.
8641 * Flow pattern to translate.
8644 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8645 void *matcher, void *key,
8646 const struct rte_flow_item *item)
8648 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8649 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8650 uint32_t mask, value;
8653 value = tag_v->data;
8654 mask = tag_m ? tag_m->data : UINT32_MAX;
8655 if (tag_v->id == REG_C_0) {
8656 struct mlx5_priv *priv = dev->data->dev_private;
8657 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8658 uint32_t shl_c0 = rte_bsf32(msk_c0);
8664 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8668 * Add TAG item to matcher
8671 * The devich to configure through.
8672 * @param[in, out] matcher
8674 * @param[in, out] key
8675 * Flow matcher value.
8677 * Flow pattern to translate.
8680 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8681 void *matcher, void *key,
8682 const struct rte_flow_item *item)
8684 const struct rte_flow_item_tag *tag_v = item->spec;
8685 const struct rte_flow_item_tag *tag_m = item->mask;
8686 enum modify_reg reg;
8689 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8690 /* Get the metadata register index for the tag. */
8691 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8692 MLX5_ASSERT(reg > 0);
8693 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8697 * Add source vport match to the specified matcher.
8699 * @param[in, out] matcher
8701 * @param[in, out] key
8702 * Flow matcher value.
8704 * Source vport value to match
8709 flow_dv_translate_item_source_vport(void *matcher, void *key,
8710 int16_t port, uint16_t mask)
8712 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8713 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8715 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8716 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8720 * Translate port-id item to eswitch match on port-id.
8723 * The devich to configure through.
8724 * @param[in, out] matcher
8726 * @param[in, out] key
8727 * Flow matcher value.
8729 * Flow pattern to translate.
8734 * 0 on success, a negative errno value otherwise.
8737 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8738 void *key, const struct rte_flow_item *item,
8739 const struct rte_flow_attr *attr)
8741 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8742 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8743 struct mlx5_priv *priv;
8746 mask = pid_m ? pid_m->id : 0xffff;
8747 id = pid_v ? pid_v->id : dev->data->port_id;
8748 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8752 * Translate to vport field or to metadata, depending on mode.
8753 * Kernel can use either misc.source_port or half of C0 metadata
8756 if (priv->vport_meta_mask) {
8758 * Provide the hint for SW steering library
8759 * to insert the flow into ingress domain and
8760 * save the extra vport match.
8762 if (mask == 0xffff && priv->vport_id == 0xffff &&
8763 priv->pf_bond < 0 && attr->transfer)
8764 flow_dv_translate_item_source_vport
8765 (matcher, key, priv->vport_id, mask);
8767 * We should always set the vport metadata register,
8768 * otherwise the SW steering library can drop
8769 * the rule if wire vport metadata value is not zero,
8770 * it depends on kernel configuration.
8772 flow_dv_translate_item_meta_vport(matcher, key,
8773 priv->vport_meta_tag,
8774 priv->vport_meta_mask);
8776 flow_dv_translate_item_source_vport(matcher, key,
8777 priv->vport_id, mask);
8783 * Add ICMP6 item to matcher and to the value.
8785 * @param[in, out] matcher
8787 * @param[in, out] key
8788 * Flow matcher value.
8790 * Flow pattern to translate.
8792 * Item is inner pattern.
8795 flow_dv_translate_item_icmp6(void *matcher, void *key,
8796 const struct rte_flow_item *item,
8799 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8800 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8803 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8805 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8807 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8809 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8811 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8813 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8815 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8816 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8820 icmp6_m = &rte_flow_item_icmp6_mask;
8821 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8822 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8823 icmp6_v->type & icmp6_m->type);
8824 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8825 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8826 icmp6_v->code & icmp6_m->code);
8830 * Add ICMP item to matcher and to the value.
8832 * @param[in, out] matcher
8834 * @param[in, out] key
8835 * Flow matcher value.
8837 * Flow pattern to translate.
8839 * Item is inner pattern.
8842 flow_dv_translate_item_icmp(void *matcher, void *key,
8843 const struct rte_flow_item *item,
8846 const struct rte_flow_item_icmp *icmp_m = item->mask;
8847 const struct rte_flow_item_icmp *icmp_v = item->spec;
8848 uint32_t icmp_header_data_m = 0;
8849 uint32_t icmp_header_data_v = 0;
8852 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8854 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8856 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8858 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8860 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8862 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8864 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8865 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8869 icmp_m = &rte_flow_item_icmp_mask;
8870 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8871 icmp_m->hdr.icmp_type);
8872 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8873 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8874 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8875 icmp_m->hdr.icmp_code);
8876 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8877 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8878 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8879 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8880 if (icmp_header_data_m) {
8881 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8882 icmp_header_data_v |=
8883 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8884 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8885 icmp_header_data_m);
8886 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8887 icmp_header_data_v & icmp_header_data_m);
8892 * Add GTP item to matcher and to the value.
8894 * @param[in, out] matcher
8896 * @param[in, out] key
8897 * Flow matcher value.
8899 * Flow pattern to translate.
8901 * Item is inner pattern.
8904 flow_dv_translate_item_gtp(void *matcher, void *key,
8905 const struct rte_flow_item *item, int inner)
8907 const struct rte_flow_item_gtp *gtp_m = item->mask;
8908 const struct rte_flow_item_gtp *gtp_v = item->spec;
8911 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8913 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8914 uint16_t dport = RTE_GTPU_UDP_PORT;
8917 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8919 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8921 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8923 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8925 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8926 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8927 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8932 gtp_m = &rte_flow_item_gtp_mask;
8933 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8934 gtp_m->v_pt_rsv_flags);
8935 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8936 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8937 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8938 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8939 gtp_v->msg_type & gtp_m->msg_type);
8940 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8941 rte_be_to_cpu_32(gtp_m->teid));
8942 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8943 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8947 * Add GTP PSC item to matcher.
8949 * @param[in, out] matcher
8951 * @param[in, out] key
8952 * Flow matcher value.
8954 * Flow pattern to translate.
8957 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8958 const struct rte_flow_item *item)
8960 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8961 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8962 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8964 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8970 uint8_t next_ext_header_type;
8975 /* Always set E-flag match on one, regardless of GTP item settings. */
8976 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8977 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8978 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8979 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8980 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8981 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8982 /*Set next extension header type. */
8985 dw_2.next_ext_header_type = 0xff;
8986 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8987 rte_cpu_to_be_32(dw_2.w32));
8990 dw_2.next_ext_header_type = 0x85;
8991 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8992 rte_cpu_to_be_32(dw_2.w32));
9004 /*Set extension header PDU type and Qos. */
9006 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9008 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9009 dw_0.qfi = gtp_psc_m->qfi;
9010 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9011 rte_cpu_to_be_32(dw_0.w32));
9013 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9014 gtp_psc_m->pdu_type);
9015 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9016 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9017 rte_cpu_to_be_32(dw_0.w32));
9023 * Add eCPRI item to matcher and to the value.
9026 * The devich to configure through.
9027 * @param[in, out] matcher
9029 * @param[in, out] key
9030 * Flow matcher value.
9032 * Flow pattern to translate.
9033 * @param[in] samples
9034 * Sample IDs to be used in the matching.
9037 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9038 void *key, const struct rte_flow_item *item)
9040 struct mlx5_priv *priv = dev->data->dev_private;
9041 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9042 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9043 struct rte_ecpri_common_hdr common;
9044 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9046 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9054 ecpri_m = &rte_flow_item_ecpri_mask;
9056 * Maximal four DW samples are supported in a single matching now.
9057 * Two are used now for a eCPRI matching:
9058 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9059 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9062 if (!ecpri_m->hdr.common.u32)
9064 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9065 /* Need to take the whole DW as the mask to fill the entry. */
9066 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9067 prog_sample_field_value_0);
9068 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9069 prog_sample_field_value_0);
9070 /* Already big endian (network order) in the header. */
9071 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9072 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9073 /* Sample#0, used for matching type, offset 0. */
9074 MLX5_SET(fte_match_set_misc4, misc4_m,
9075 prog_sample_field_id_0, samples[0]);
9076 /* It makes no sense to set the sample ID in the mask field. */
9077 MLX5_SET(fte_match_set_misc4, misc4_v,
9078 prog_sample_field_id_0, samples[0]);
9080 * Checking if message body part needs to be matched.
9081 * Some wildcard rules only matching type field should be supported.
9083 if (ecpri_m->hdr.dummy[0]) {
9084 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9085 switch (common.type) {
9086 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9087 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9088 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9089 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9090 prog_sample_field_value_1);
9091 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9092 prog_sample_field_value_1);
9093 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9094 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9095 ecpri_m->hdr.dummy[0];
9096 /* Sample#1, to match message body, offset 4. */
9097 MLX5_SET(fte_match_set_misc4, misc4_m,
9098 prog_sample_field_id_1, samples[1]);
9099 MLX5_SET(fte_match_set_misc4, misc4_v,
9100 prog_sample_field_id_1, samples[1]);
9103 /* Others, do not match any sample ID. */
9109 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9111 #define HEADER_IS_ZERO(match_criteria, headers) \
9112 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9113 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9116 * Calculate flow matcher enable bitmap.
9118 * @param match_criteria
9119 * Pointer to flow matcher criteria.
9122 * Bitmap of enabled fields.
9125 flow_dv_matcher_enable(uint32_t *match_criteria)
9127 uint8_t match_criteria_enable;
9129 match_criteria_enable =
9130 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9131 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9132 match_criteria_enable |=
9133 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9134 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9135 match_criteria_enable |=
9136 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9137 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9138 match_criteria_enable |=
9139 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9140 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9141 match_criteria_enable |=
9142 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9143 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9144 match_criteria_enable |=
9145 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9146 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9147 return match_criteria_enable;
9150 struct mlx5_hlist_entry *
9151 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9153 struct mlx5_dev_ctx_shared *sh = list->ctx;
9154 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9155 struct rte_eth_dev *dev = ctx->dev;
9156 struct mlx5_flow_tbl_data_entry *tbl_data;
9157 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9158 struct rte_flow_error *error = ctx->error;
9159 union mlx5_flow_tbl_key key = { .v64 = key64 };
9160 struct mlx5_flow_tbl_resource *tbl;
9165 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9167 rte_flow_error_set(error, ENOMEM,
9168 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9170 "cannot allocate flow table data entry");
9173 tbl_data->idx = idx;
9174 tbl_data->tunnel = tt_prm->tunnel;
9175 tbl_data->group_id = tt_prm->group_id;
9176 tbl_data->external = !!tt_prm->external;
9177 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9178 tbl_data->is_egress = !!key.direction;
9179 tbl_data->is_transfer = !!key.domain;
9180 tbl_data->dummy = !!key.dummy;
9181 tbl_data->table_id = key.table_id;
9182 tbl = &tbl_data->tbl;
9184 return &tbl_data->entry;
9186 domain = sh->fdb_domain;
9187 else if (key.direction)
9188 domain = sh->tx_domain;
9190 domain = sh->rx_domain;
9191 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9193 rte_flow_error_set(error, ENOMEM,
9194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9195 NULL, "cannot create flow table object");
9196 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9200 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9201 (tbl->obj, &tbl_data->jump.action);
9203 rte_flow_error_set(error, ENOMEM,
9204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9206 "cannot create flow jump action");
9207 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9208 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9212 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9213 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9215 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9216 flow_dv_matcher_create_cb,
9217 flow_dv_matcher_match_cb,
9218 flow_dv_matcher_remove_cb);
9219 return &tbl_data->entry;
9223 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9224 struct mlx5_hlist_entry *entry, uint64_t key64,
9225 void *cb_ctx __rte_unused)
9227 struct mlx5_flow_tbl_data_entry *tbl_data =
9228 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9229 union mlx5_flow_tbl_key key = { .v64 = key64 };
9231 return tbl_data->table_id != key.table_id ||
9232 tbl_data->dummy != key.dummy ||
9233 tbl_data->is_transfer != key.domain ||
9234 tbl_data->is_egress != key.direction;
9240 * @param[in, out] dev
9241 * Pointer to rte_eth_dev structure.
9242 * @param[in] table_id
9245 * Direction of the table.
9246 * @param[in] transfer
9247 * E-Switch or NIC flow.
9249 * Dummy entry for dv API.
9251 * pointer to error structure.
9254 * Returns tables resource based on the index, NULL in case of failed.
9256 struct mlx5_flow_tbl_resource *
9257 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9258 uint32_t table_id, uint8_t egress,
9261 const struct mlx5_flow_tunnel *tunnel,
9262 uint32_t group_id, uint8_t dummy,
9263 struct rte_flow_error *error)
9265 struct mlx5_priv *priv = dev->data->dev_private;
9266 union mlx5_flow_tbl_key table_key = {
9268 .table_id = table_id,
9270 .domain = !!transfer,
9271 .direction = !!egress,
9274 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9276 .group_id = group_id,
9277 .external = external,
9279 struct mlx5_flow_cb_ctx ctx = {
9284 struct mlx5_hlist_entry *entry;
9285 struct mlx5_flow_tbl_data_entry *tbl_data;
9287 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9289 rte_flow_error_set(error, ENOMEM,
9290 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9291 "cannot get table");
9294 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9295 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9296 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9297 return &tbl_data->tbl;
9301 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9302 struct mlx5_hlist_entry *entry)
9304 struct mlx5_dev_ctx_shared *sh = list->ctx;
9305 struct mlx5_flow_tbl_data_entry *tbl_data =
9306 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9308 MLX5_ASSERT(entry && sh);
9309 if (tbl_data->jump.action)
9310 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9311 if (tbl_data->tbl.obj)
9312 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9313 if (tbl_data->tunnel_offload && tbl_data->external) {
9314 struct mlx5_hlist_entry *he;
9315 struct mlx5_hlist *tunnel_grp_hash;
9316 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9317 union tunnel_tbl_key tunnel_key = {
9318 .tunnel_id = tbl_data->tunnel ?
9319 tbl_data->tunnel->tunnel_id : 0,
9320 .group = tbl_data->group_id
9322 uint32_t table_id = tbl_data->table_id;
9324 tunnel_grp_hash = tbl_data->tunnel ?
9325 tbl_data->tunnel->groups :
9327 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9329 mlx5_hlist_unregister(tunnel_grp_hash, he);
9331 "Table_id %u tunnel %u group %u released.",
9334 tbl_data->tunnel->tunnel_id : 0,
9335 tbl_data->group_id);
9337 mlx5_cache_list_destroy(&tbl_data->matchers);
9338 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9342 * Release a flow table.
9345 * Pointer to device shared structure.
9347 * Table resource to be released.
9350 * Returns 0 if table was released, else return 1;
9353 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9354 struct mlx5_flow_tbl_resource *tbl)
9356 struct mlx5_flow_tbl_data_entry *tbl_data =
9357 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9361 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9365 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9366 struct mlx5_cache_entry *entry, void *cb_ctx)
9368 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9369 struct mlx5_flow_dv_matcher *ref = ctx->data;
9370 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9373 return cur->crc != ref->crc ||
9374 cur->priority != ref->priority ||
9375 memcmp((const void *)cur->mask.buf,
9376 (const void *)ref->mask.buf, ref->mask.size);
9379 struct mlx5_cache_entry *
9380 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9381 struct mlx5_cache_entry *entry __rte_unused,
9384 struct mlx5_dev_ctx_shared *sh = list->ctx;
9385 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9386 struct mlx5_flow_dv_matcher *ref = ctx->data;
9387 struct mlx5_flow_dv_matcher *cache;
9388 struct mlx5dv_flow_matcher_attr dv_attr = {
9389 .type = IBV_FLOW_ATTR_NORMAL,
9390 .match_mask = (void *)&ref->mask,
9392 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9396 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9398 rte_flow_error_set(ctx->error, ENOMEM,
9399 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9400 "cannot create matcher");
9404 dv_attr.match_criteria_enable =
9405 flow_dv_matcher_enable(cache->mask.buf);
9406 dv_attr.priority = ref->priority;
9408 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9409 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9410 &cache->matcher_object);
9413 rte_flow_error_set(ctx->error, ENOMEM,
9414 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9415 "cannot create matcher");
9418 return &cache->entry;
9422 * Register the flow matcher.
9424 * @param[in, out] dev
9425 * Pointer to rte_eth_dev structure.
9426 * @param[in, out] matcher
9427 * Pointer to flow matcher.
9428 * @param[in, out] key
9429 * Pointer to flow table key.
9430 * @parm[in, out] dev_flow
9431 * Pointer to the dev_flow.
9433 * pointer to error structure.
9436 * 0 on success otherwise -errno and errno is set.
9439 flow_dv_matcher_register(struct rte_eth_dev *dev,
9440 struct mlx5_flow_dv_matcher *ref,
9441 union mlx5_flow_tbl_key *key,
9442 struct mlx5_flow *dev_flow,
9443 const struct mlx5_flow_tunnel *tunnel,
9445 struct rte_flow_error *error)
9447 struct mlx5_cache_entry *entry;
9448 struct mlx5_flow_dv_matcher *cache;
9449 struct mlx5_flow_tbl_resource *tbl;
9450 struct mlx5_flow_tbl_data_entry *tbl_data;
9451 struct mlx5_flow_cb_ctx ctx = {
9457 * tunnel offload API requires this registration for cases when
9458 * tunnel match rule was inserted before tunnel set rule.
9460 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9461 key->direction, key->domain,
9462 dev_flow->external, tunnel,
9463 group_id, 0, error);
9465 return -rte_errno; /* No need to refill the error info */
9466 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9468 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9470 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9471 return rte_flow_error_set(error, ENOMEM,
9472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9473 "cannot allocate ref memory");
9475 cache = container_of(entry, typeof(*cache), entry);
9476 dev_flow->handle->dvh.matcher = cache;
9480 struct mlx5_hlist_entry *
9481 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9483 struct mlx5_dev_ctx_shared *sh = list->ctx;
9484 struct rte_flow_error *error = ctx;
9485 struct mlx5_flow_dv_tag_resource *entry;
9489 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9491 rte_flow_error_set(error, ENOMEM,
9492 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9493 "cannot allocate resource memory");
9497 entry->tag_id = key;
9498 ret = mlx5_flow_os_create_flow_action_tag(key,
9501 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9502 rte_flow_error_set(error, ENOMEM,
9503 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9504 NULL, "cannot create action");
9507 return &entry->entry;
9511 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9512 struct mlx5_hlist_entry *entry, uint64_t key,
9513 void *cb_ctx __rte_unused)
9515 struct mlx5_flow_dv_tag_resource *tag =
9516 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9518 return key != tag->tag_id;
9522 * Find existing tag resource or create and register a new one.
9524 * @param dev[in, out]
9525 * Pointer to rte_eth_dev structure.
9526 * @param[in, out] tag_be24
9527 * Tag value in big endian then R-shift 8.
9528 * @parm[in, out] dev_flow
9529 * Pointer to the dev_flow.
9531 * pointer to error structure.
9534 * 0 on success otherwise -errno and errno is set.
9537 flow_dv_tag_resource_register
9538 (struct rte_eth_dev *dev,
9540 struct mlx5_flow *dev_flow,
9541 struct rte_flow_error *error)
9543 struct mlx5_priv *priv = dev->data->dev_private;
9544 struct mlx5_flow_dv_tag_resource *cache_resource;
9545 struct mlx5_hlist_entry *entry;
9547 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9549 cache_resource = container_of
9550 (entry, struct mlx5_flow_dv_tag_resource, entry);
9551 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9552 dev_flow->dv.tag_resource = cache_resource;
9559 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9560 struct mlx5_hlist_entry *entry)
9562 struct mlx5_dev_ctx_shared *sh = list->ctx;
9563 struct mlx5_flow_dv_tag_resource *tag =
9564 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9566 MLX5_ASSERT(tag && sh && tag->action);
9567 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9568 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9569 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9576 * Pointer to Ethernet device.
9581 * 1 while a reference on it exists, 0 when freed.
9584 flow_dv_tag_release(struct rte_eth_dev *dev,
9587 struct mlx5_priv *priv = dev->data->dev_private;
9588 struct mlx5_flow_dv_tag_resource *tag;
9590 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9593 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9594 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9595 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9599 * Translate port ID action to vport.
9602 * Pointer to rte_eth_dev structure.
9604 * Pointer to the port ID action.
9605 * @param[out] dst_port_id
9606 * The target port ID.
9608 * Pointer to the error structure.
9611 * 0 on success, a negative errno value otherwise and rte_errno is set.
9614 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9615 const struct rte_flow_action *action,
9616 uint32_t *dst_port_id,
9617 struct rte_flow_error *error)
9620 struct mlx5_priv *priv;
9621 const struct rte_flow_action_port_id *conf =
9622 (const struct rte_flow_action_port_id *)action->conf;
9624 port = conf->original ? dev->data->port_id : conf->id;
9625 priv = mlx5_port_to_eswitch_info(port, false);
9627 return rte_flow_error_set(error, -rte_errno,
9628 RTE_FLOW_ERROR_TYPE_ACTION,
9630 "No eswitch info was found for port");
9631 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9633 * This parameter is transferred to
9634 * mlx5dv_dr_action_create_dest_ib_port().
9636 *dst_port_id = priv->dev_port;
9639 * Legacy mode, no LAG configurations is supported.
9640 * This parameter is transferred to
9641 * mlx5dv_dr_action_create_dest_vport().
9643 *dst_port_id = priv->vport_id;
9649 * Create a counter with aging configuration.
9652 * Pointer to rte_eth_dev structure.
9654 * Pointer to the counter action configuration.
9656 * Pointer to the aging action configuration.
9659 * Index to flow counter on success, 0 otherwise.
9662 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9663 struct mlx5_flow *dev_flow,
9664 const struct rte_flow_action_count *count,
9665 const struct rte_flow_action_age *age)
9668 struct mlx5_age_param *age_param;
9670 if (count && count->shared)
9671 counter = flow_dv_counter_get_shared(dev, count->id);
9673 counter = flow_dv_counter_alloc(dev, !!age);
9674 if (!counter || age == NULL)
9676 age_param = flow_dv_counter_idx_get_age(dev, counter);
9677 age_param->context = age->context ? age->context :
9678 (void *)(uintptr_t)(dev_flow->flow_idx);
9679 age_param->timeout = age->timeout;
9680 age_param->port_id = dev->data->port_id;
9681 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9682 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9687 * Add Tx queue matcher
9690 * Pointer to the dev struct.
9691 * @param[in, out] matcher
9693 * @param[in, out] key
9694 * Flow matcher value.
9696 * Flow pattern to translate.
9698 * Item is inner pattern.
9701 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9702 void *matcher, void *key,
9703 const struct rte_flow_item *item)
9705 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9706 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9708 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9710 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9711 struct mlx5_txq_ctrl *txq;
9715 queue_m = (const void *)item->mask;
9718 queue_v = (const void *)item->spec;
9721 txq = mlx5_txq_get(dev, queue_v->queue);
9724 queue = txq->obj->sq->id;
9725 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9726 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9727 queue & queue_m->queue);
9728 mlx5_txq_release(dev, queue_v->queue);
9732 * Set the hash fields according to the @p flow information.
9734 * @param[in] dev_flow
9735 * Pointer to the mlx5_flow.
9736 * @param[in] rss_desc
9737 * Pointer to the mlx5_flow_rss_desc.
9740 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9741 struct mlx5_flow_rss_desc *rss_desc)
9743 uint64_t items = dev_flow->handle->layers;
9745 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9747 dev_flow->hash_fields = 0;
9748 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9749 if (rss_desc->level >= 2) {
9750 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9754 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9755 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9756 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9757 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9758 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9759 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9760 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9762 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9764 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9765 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9766 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9767 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9768 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9769 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9770 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9772 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9775 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9776 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9777 if (rss_types & ETH_RSS_UDP) {
9778 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9779 dev_flow->hash_fields |=
9780 IBV_RX_HASH_SRC_PORT_UDP;
9781 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9782 dev_flow->hash_fields |=
9783 IBV_RX_HASH_DST_PORT_UDP;
9785 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9787 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9788 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9789 if (rss_types & ETH_RSS_TCP) {
9790 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9791 dev_flow->hash_fields |=
9792 IBV_RX_HASH_SRC_PORT_TCP;
9793 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9794 dev_flow->hash_fields |=
9795 IBV_RX_HASH_DST_PORT_TCP;
9797 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9803 * Prepare an Rx Hash queue.
9806 * Pointer to Ethernet device.
9807 * @param[in] dev_flow
9808 * Pointer to the mlx5_flow.
9809 * @param[in] rss_desc
9810 * Pointer to the mlx5_flow_rss_desc.
9811 * @param[out] hrxq_idx
9812 * Hash Rx queue index.
9815 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9817 static struct mlx5_hrxq *
9818 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9819 struct mlx5_flow *dev_flow,
9820 struct mlx5_flow_rss_desc *rss_desc,
9823 struct mlx5_priv *priv = dev->data->dev_private;
9824 struct mlx5_flow_handle *dh = dev_flow->handle;
9825 struct mlx5_hrxq *hrxq;
9827 MLX5_ASSERT(rss_desc->queue_num);
9828 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9829 rss_desc->hash_fields = dev_flow->hash_fields;
9830 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9831 rss_desc->shared_rss = 0;
9832 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9835 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9841 * Release sample sub action resource.
9843 * @param[in, out] dev
9844 * Pointer to rte_eth_dev structure.
9845 * @param[in] act_res
9846 * Pointer to sample sub action resource.
9849 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9850 struct mlx5_flow_sub_actions_idx *act_res)
9852 if (act_res->rix_hrxq) {
9853 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9854 act_res->rix_hrxq = 0;
9856 if (act_res->rix_encap_decap) {
9857 flow_dv_encap_decap_resource_release(dev,
9858 act_res->rix_encap_decap);
9859 act_res->rix_encap_decap = 0;
9861 if (act_res->rix_port_id_action) {
9862 flow_dv_port_id_action_resource_release(dev,
9863 act_res->rix_port_id_action);
9864 act_res->rix_port_id_action = 0;
9866 if (act_res->rix_tag) {
9867 flow_dv_tag_release(dev, act_res->rix_tag);
9868 act_res->rix_tag = 0;
9870 if (act_res->rix_jump) {
9871 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9872 act_res->rix_jump = 0;
9877 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9878 struct mlx5_cache_entry *entry, void *cb_ctx)
9880 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9881 struct rte_eth_dev *dev = ctx->dev;
9882 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9883 struct mlx5_flow_dv_sample_resource *cache_resource =
9884 container_of(entry, typeof(*cache_resource), entry);
9886 if (resource->ratio == cache_resource->ratio &&
9887 resource->ft_type == cache_resource->ft_type &&
9888 resource->ft_id == cache_resource->ft_id &&
9889 resource->set_action == cache_resource->set_action &&
9890 !memcmp((void *)&resource->sample_act,
9891 (void *)&cache_resource->sample_act,
9892 sizeof(struct mlx5_flow_sub_actions_list))) {
9894 * Existing sample action should release the prepared
9895 * sub-actions reference counter.
9897 flow_dv_sample_sub_actions_release(dev,
9898 &resource->sample_idx);
9904 struct mlx5_cache_entry *
9905 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9906 struct mlx5_cache_entry *entry __rte_unused,
9909 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9910 struct rte_eth_dev *dev = ctx->dev;
9911 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9912 void **sample_dv_actions = resource->sub_actions;
9913 struct mlx5_flow_dv_sample_resource *cache_resource;
9914 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9915 struct mlx5_priv *priv = dev->data->dev_private;
9916 struct mlx5_dev_ctx_shared *sh = priv->sh;
9917 struct mlx5_flow_tbl_resource *tbl;
9919 const uint32_t next_ft_step = 1;
9920 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9921 uint8_t is_egress = 0;
9922 uint8_t is_transfer = 0;
9923 struct rte_flow_error *error = ctx->error;
9925 /* Register new sample resource. */
9926 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9927 if (!cache_resource) {
9928 rte_flow_error_set(error, ENOMEM,
9929 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9931 "cannot allocate resource memory");
9934 *cache_resource = *resource;
9935 /* Create normal path table level */
9936 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9938 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9940 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9941 is_egress, is_transfer,
9942 true, NULL, 0, 0, error);
9944 rte_flow_error_set(error, ENOMEM,
9945 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9947 "fail to create normal path table "
9951 cache_resource->normal_path_tbl = tbl;
9952 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9953 if (!sh->default_miss_action) {
9954 rte_flow_error_set(error, ENOMEM,
9955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9957 "default miss action was not "
9961 sample_dv_actions[resource->sample_act.actions_num++] =
9962 sh->default_miss_action;
9964 /* Create a DR sample action */
9965 sampler_attr.sample_ratio = cache_resource->ratio;
9966 sampler_attr.default_next_table = tbl->obj;
9967 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9968 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9969 &sample_dv_actions[0];
9970 sampler_attr.action = cache_resource->set_action;
9971 if (mlx5_os_flow_dr_create_flow_action_sampler
9972 (&sampler_attr, &cache_resource->verbs_action)) {
9973 rte_flow_error_set(error, ENOMEM,
9974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9975 NULL, "cannot create sample action");
9978 cache_resource->idx = idx;
9979 cache_resource->dev = dev;
9980 return &cache_resource->entry;
9982 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9983 flow_dv_sample_sub_actions_release(dev,
9984 &cache_resource->sample_idx);
9985 if (cache_resource->normal_path_tbl)
9986 flow_dv_tbl_resource_release(MLX5_SH(dev),
9987 cache_resource->normal_path_tbl);
9988 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9994 * Find existing sample resource or create and register a new one.
9996 * @param[in, out] dev
9997 * Pointer to rte_eth_dev structure.
9998 * @param[in] resource
9999 * Pointer to sample resource.
10000 * @parm[in, out] dev_flow
10001 * Pointer to the dev_flow.
10002 * @param[out] error
10003 * pointer to error structure.
10006 * 0 on success otherwise -errno and errno is set.
10009 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10010 struct mlx5_flow_dv_sample_resource *resource,
10011 struct mlx5_flow *dev_flow,
10012 struct rte_flow_error *error)
10014 struct mlx5_flow_dv_sample_resource *cache_resource;
10015 struct mlx5_cache_entry *entry;
10016 struct mlx5_priv *priv = dev->data->dev_private;
10017 struct mlx5_flow_cb_ctx ctx = {
10023 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10026 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10027 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10028 dev_flow->dv.sample_res = cache_resource;
10033 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10034 struct mlx5_cache_entry *entry, void *cb_ctx)
10036 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10037 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10038 struct rte_eth_dev *dev = ctx->dev;
10039 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10040 container_of(entry, typeof(*cache_resource), entry);
10043 if (resource->num_of_dest == cache_resource->num_of_dest &&
10044 resource->ft_type == cache_resource->ft_type &&
10045 !memcmp((void *)cache_resource->sample_act,
10046 (void *)resource->sample_act,
10047 (resource->num_of_dest *
10048 sizeof(struct mlx5_flow_sub_actions_list)))) {
10050 * Existing sample action should release the prepared
10051 * sub-actions reference counter.
10053 for (idx = 0; idx < resource->num_of_dest; idx++)
10054 flow_dv_sample_sub_actions_release(dev,
10055 &resource->sample_idx[idx]);
10061 struct mlx5_cache_entry *
10062 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10063 struct mlx5_cache_entry *entry __rte_unused,
10066 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10067 struct rte_eth_dev *dev = ctx->dev;
10068 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10069 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10070 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10071 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10072 struct mlx5_priv *priv = dev->data->dev_private;
10073 struct mlx5_dev_ctx_shared *sh = priv->sh;
10074 struct mlx5_flow_sub_actions_list *sample_act;
10075 struct mlx5dv_dr_domain *domain;
10076 uint32_t idx = 0, res_idx = 0;
10077 struct rte_flow_error *error = ctx->error;
10078 uint64_t action_flags;
10081 /* Register new destination array resource. */
10082 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10084 if (!cache_resource) {
10085 rte_flow_error_set(error, ENOMEM,
10086 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10088 "cannot allocate resource memory");
10091 *cache_resource = *resource;
10092 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10093 domain = sh->fdb_domain;
10094 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10095 domain = sh->rx_domain;
10097 domain = sh->tx_domain;
10098 for (idx = 0; idx < resource->num_of_dest; idx++) {
10099 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10100 mlx5_malloc(MLX5_MEM_ZERO,
10101 sizeof(struct mlx5dv_dr_action_dest_attr),
10103 if (!dest_attr[idx]) {
10104 rte_flow_error_set(error, ENOMEM,
10105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10107 "cannot allocate resource memory");
10110 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10111 sample_act = &resource->sample_act[idx];
10112 action_flags = sample_act->action_flags;
10113 switch (action_flags) {
10114 case MLX5_FLOW_ACTION_QUEUE:
10115 dest_attr[idx]->dest = sample_act->dr_queue_action;
10117 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10118 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10119 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10120 dest_attr[idx]->dest_reformat->reformat =
10121 sample_act->dr_encap_action;
10122 dest_attr[idx]->dest_reformat->dest =
10123 sample_act->dr_port_id_action;
10125 case MLX5_FLOW_ACTION_PORT_ID:
10126 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10128 case MLX5_FLOW_ACTION_JUMP:
10129 dest_attr[idx]->dest = sample_act->dr_jump_action;
10132 rte_flow_error_set(error, EINVAL,
10133 RTE_FLOW_ERROR_TYPE_ACTION,
10135 "unsupported actions type");
10139 /* create a dest array actioin */
10140 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10142 cache_resource->num_of_dest,
10144 &cache_resource->action);
10146 rte_flow_error_set(error, ENOMEM,
10147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10149 "cannot create destination array action");
10152 cache_resource->idx = res_idx;
10153 cache_resource->dev = dev;
10154 for (idx = 0; idx < resource->num_of_dest; idx++)
10155 mlx5_free(dest_attr[idx]);
10156 return &cache_resource->entry;
10158 for (idx = 0; idx < resource->num_of_dest; idx++) {
10159 flow_dv_sample_sub_actions_release(dev,
10160 &cache_resource->sample_idx[idx]);
10161 if (dest_attr[idx])
10162 mlx5_free(dest_attr[idx]);
10165 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10170 * Find existing destination array resource or create and register a new one.
10172 * @param[in, out] dev
10173 * Pointer to rte_eth_dev structure.
10174 * @param[in] resource
10175 * Pointer to destination array resource.
10176 * @parm[in, out] dev_flow
10177 * Pointer to the dev_flow.
10178 * @param[out] error
10179 * pointer to error structure.
10182 * 0 on success otherwise -errno and errno is set.
10185 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10186 struct mlx5_flow_dv_dest_array_resource *resource,
10187 struct mlx5_flow *dev_flow,
10188 struct rte_flow_error *error)
10190 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10191 struct mlx5_priv *priv = dev->data->dev_private;
10192 struct mlx5_cache_entry *entry;
10193 struct mlx5_flow_cb_ctx ctx = {
10199 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10202 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10203 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10204 dev_flow->dv.dest_array_res = cache_resource;
10209 * Convert Sample action to DV specification.
10212 * Pointer to rte_eth_dev structure.
10213 * @param[in] action
10214 * Pointer to sample action structure.
10215 * @param[in, out] dev_flow
10216 * Pointer to the mlx5_flow.
10218 * Pointer to the flow attributes.
10219 * @param[in, out] num_of_dest
10220 * Pointer to the num of destination.
10221 * @param[in, out] sample_actions
10222 * Pointer to sample actions list.
10223 * @param[in, out] res
10224 * Pointer to sample resource.
10225 * @param[out] error
10226 * Pointer to the error structure.
10229 * 0 on success, a negative errno value otherwise and rte_errno is set.
10232 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10233 const struct rte_flow_action_sample *action,
10234 struct mlx5_flow *dev_flow,
10235 const struct rte_flow_attr *attr,
10236 uint32_t *num_of_dest,
10237 void **sample_actions,
10238 struct mlx5_flow_dv_sample_resource *res,
10239 struct rte_flow_error *error)
10241 struct mlx5_priv *priv = dev->data->dev_private;
10242 const struct rte_flow_action *sub_actions;
10243 struct mlx5_flow_sub_actions_list *sample_act;
10244 struct mlx5_flow_sub_actions_idx *sample_idx;
10245 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10246 struct rte_flow *flow = dev_flow->flow;
10247 struct mlx5_flow_rss_desc *rss_desc;
10248 uint64_t action_flags = 0;
10251 rss_desc = &wks->rss_desc;
10252 sample_act = &res->sample_act;
10253 sample_idx = &res->sample_idx;
10254 res->ratio = action->ratio;
10255 sub_actions = action->actions;
10256 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10257 int type = sub_actions->type;
10258 uint32_t pre_rix = 0;
10261 case RTE_FLOW_ACTION_TYPE_QUEUE:
10263 const struct rte_flow_action_queue *queue;
10264 struct mlx5_hrxq *hrxq;
10267 queue = sub_actions->conf;
10268 rss_desc->queue_num = 1;
10269 rss_desc->queue[0] = queue->index;
10270 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10271 rss_desc, &hrxq_idx);
10273 return rte_flow_error_set
10275 RTE_FLOW_ERROR_TYPE_ACTION,
10277 "cannot create fate queue");
10278 sample_act->dr_queue_action = hrxq->action;
10279 sample_idx->rix_hrxq = hrxq_idx;
10280 sample_actions[sample_act->actions_num++] =
10283 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10284 if (action_flags & MLX5_FLOW_ACTION_MARK)
10285 dev_flow->handle->rix_hrxq = hrxq_idx;
10286 dev_flow->handle->fate_action =
10287 MLX5_FLOW_FATE_QUEUE;
10290 case RTE_FLOW_ACTION_TYPE_RSS:
10292 struct mlx5_hrxq *hrxq;
10294 const struct rte_flow_action_rss *rss;
10295 const uint8_t *rss_key;
10297 rss = sub_actions->conf;
10298 memcpy(rss_desc->queue, rss->queue,
10299 rss->queue_num * sizeof(uint16_t));
10300 rss_desc->queue_num = rss->queue_num;
10301 /* NULL RSS key indicates default RSS key. */
10302 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10303 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10305 * rss->level and rss.types should be set in advance
10306 * when expanding items for RSS.
10308 flow_dv_hashfields_set(dev_flow, rss_desc);
10309 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10310 rss_desc, &hrxq_idx);
10312 return rte_flow_error_set
10314 RTE_FLOW_ERROR_TYPE_ACTION,
10316 "cannot create fate queue");
10317 sample_act->dr_queue_action = hrxq->action;
10318 sample_idx->rix_hrxq = hrxq_idx;
10319 sample_actions[sample_act->actions_num++] =
10322 action_flags |= MLX5_FLOW_ACTION_RSS;
10323 if (action_flags & MLX5_FLOW_ACTION_MARK)
10324 dev_flow->handle->rix_hrxq = hrxq_idx;
10325 dev_flow->handle->fate_action =
10326 MLX5_FLOW_FATE_QUEUE;
10329 case RTE_FLOW_ACTION_TYPE_MARK:
10331 uint32_t tag_be = mlx5_flow_mark_set
10332 (((const struct rte_flow_action_mark *)
10333 (sub_actions->conf))->id);
10335 dev_flow->handle->mark = 1;
10336 pre_rix = dev_flow->handle->dvh.rix_tag;
10337 /* Save the mark resource before sample */
10338 pre_r = dev_flow->dv.tag_resource;
10339 if (flow_dv_tag_resource_register(dev, tag_be,
10342 MLX5_ASSERT(dev_flow->dv.tag_resource);
10343 sample_act->dr_tag_action =
10344 dev_flow->dv.tag_resource->action;
10345 sample_idx->rix_tag =
10346 dev_flow->handle->dvh.rix_tag;
10347 sample_actions[sample_act->actions_num++] =
10348 sample_act->dr_tag_action;
10349 /* Recover the mark resource after sample */
10350 dev_flow->dv.tag_resource = pre_r;
10351 dev_flow->handle->dvh.rix_tag = pre_rix;
10352 action_flags |= MLX5_FLOW_ACTION_MARK;
10355 case RTE_FLOW_ACTION_TYPE_COUNT:
10357 if (!flow->counter) {
10359 flow_dv_translate_create_counter(dev,
10360 dev_flow, sub_actions->conf,
10362 if (!flow->counter)
10363 return rte_flow_error_set
10365 RTE_FLOW_ERROR_TYPE_ACTION,
10367 "cannot create counter"
10370 sample_act->dr_cnt_action =
10371 (flow_dv_counter_get_by_idx(dev,
10372 flow->counter, NULL))->action;
10373 sample_actions[sample_act->actions_num++] =
10374 sample_act->dr_cnt_action;
10375 action_flags |= MLX5_FLOW_ACTION_COUNT;
10378 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10380 struct mlx5_flow_dv_port_id_action_resource
10382 uint32_t port_id = 0;
10384 memset(&port_id_resource, 0, sizeof(port_id_resource));
10385 /* Save the port id resource before sample */
10386 pre_rix = dev_flow->handle->rix_port_id_action;
10387 pre_r = dev_flow->dv.port_id_action;
10388 if (flow_dv_translate_action_port_id(dev, sub_actions,
10391 port_id_resource.port_id = port_id;
10392 if (flow_dv_port_id_action_resource_register
10393 (dev, &port_id_resource, dev_flow, error))
10395 sample_act->dr_port_id_action =
10396 dev_flow->dv.port_id_action->action;
10397 sample_idx->rix_port_id_action =
10398 dev_flow->handle->rix_port_id_action;
10399 sample_actions[sample_act->actions_num++] =
10400 sample_act->dr_port_id_action;
10401 /* Recover the port id resource after sample */
10402 dev_flow->dv.port_id_action = pre_r;
10403 dev_flow->handle->rix_port_id_action = pre_rix;
10405 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10408 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10409 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10410 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10411 /* Save the encap resource before sample */
10412 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10413 pre_r = dev_flow->dv.encap_decap;
10414 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10419 sample_act->dr_encap_action =
10420 dev_flow->dv.encap_decap->action;
10421 sample_idx->rix_encap_decap =
10422 dev_flow->handle->dvh.rix_encap_decap;
10423 sample_actions[sample_act->actions_num++] =
10424 sample_act->dr_encap_action;
10425 /* Recover the encap resource after sample */
10426 dev_flow->dv.encap_decap = pre_r;
10427 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10428 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10431 return rte_flow_error_set(error, EINVAL,
10432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10434 "Not support for sampler action");
10437 sample_act->action_flags = action_flags;
10438 res->ft_id = dev_flow->dv.group;
10439 if (attr->transfer) {
10441 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10442 uint64_t set_action;
10443 } action_ctx = { .set_action = 0 };
10445 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10446 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10447 MLX5_MODIFICATION_TYPE_SET);
10448 MLX5_SET(set_action_in, action_ctx.action_in, field,
10449 MLX5_MODI_META_REG_C_0);
10450 MLX5_SET(set_action_in, action_ctx.action_in, data,
10451 priv->vport_meta_tag);
10452 res->set_action = action_ctx.set_action;
10453 } else if (attr->ingress) {
10454 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10456 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10462 * Convert Sample action to DV specification.
10465 * Pointer to rte_eth_dev structure.
10466 * @param[in, out] dev_flow
10467 * Pointer to the mlx5_flow.
10468 * @param[in] num_of_dest
10469 * The num of destination.
10470 * @param[in, out] res
10471 * Pointer to sample resource.
10472 * @param[in, out] mdest_res
10473 * Pointer to destination array resource.
10474 * @param[in] sample_actions
10475 * Pointer to sample path actions list.
10476 * @param[in] action_flags
10477 * Holds the actions detected until now.
10478 * @param[out] error
10479 * Pointer to the error structure.
10482 * 0 on success, a negative errno value otherwise and rte_errno is set.
10485 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10486 struct mlx5_flow *dev_flow,
10487 uint32_t num_of_dest,
10488 struct mlx5_flow_dv_sample_resource *res,
10489 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10490 void **sample_actions,
10491 uint64_t action_flags,
10492 struct rte_flow_error *error)
10494 /* update normal path action resource into last index of array */
10495 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10496 struct mlx5_flow_sub_actions_list *sample_act =
10497 &mdest_res->sample_act[dest_index];
10498 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10499 struct mlx5_flow_rss_desc *rss_desc;
10500 uint32_t normal_idx = 0;
10501 struct mlx5_hrxq *hrxq;
10505 rss_desc = &wks->rss_desc;
10506 if (num_of_dest > 1) {
10507 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10508 /* Handle QP action for mirroring */
10509 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10510 rss_desc, &hrxq_idx);
10512 return rte_flow_error_set
10514 RTE_FLOW_ERROR_TYPE_ACTION,
10516 "cannot create rx queue");
10518 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10519 sample_act->dr_queue_action = hrxq->action;
10520 if (action_flags & MLX5_FLOW_ACTION_MARK)
10521 dev_flow->handle->rix_hrxq = hrxq_idx;
10522 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10524 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10526 mdest_res->sample_idx[dest_index].rix_encap_decap =
10527 dev_flow->handle->dvh.rix_encap_decap;
10528 sample_act->dr_encap_action =
10529 dev_flow->dv.encap_decap->action;
10530 dev_flow->handle->dvh.rix_encap_decap = 0;
10532 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10534 mdest_res->sample_idx[dest_index].rix_port_id_action =
10535 dev_flow->handle->rix_port_id_action;
10536 sample_act->dr_port_id_action =
10537 dev_flow->dv.port_id_action->action;
10538 dev_flow->handle->rix_port_id_action = 0;
10540 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10542 mdest_res->sample_idx[dest_index].rix_jump =
10543 dev_flow->handle->rix_jump;
10544 sample_act->dr_jump_action =
10545 dev_flow->dv.jump->action;
10546 dev_flow->handle->rix_jump = 0;
10548 sample_act->actions_num = normal_idx;
10549 /* update sample action resource into first index of array */
10550 mdest_res->ft_type = res->ft_type;
10551 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10552 sizeof(struct mlx5_flow_sub_actions_idx));
10553 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10554 sizeof(struct mlx5_flow_sub_actions_list));
10555 mdest_res->num_of_dest = num_of_dest;
10556 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10558 return rte_flow_error_set(error, EINVAL,
10559 RTE_FLOW_ERROR_TYPE_ACTION,
10560 NULL, "can't create sample "
10563 res->sub_actions = sample_actions;
10564 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10565 return rte_flow_error_set(error, EINVAL,
10566 RTE_FLOW_ERROR_TYPE_ACTION,
10568 "can't create sample action");
10574 * Remove an ASO age action from age actions list.
10577 * Pointer to the Ethernet device structure.
10579 * Pointer to the aso age action handler.
10582 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10583 struct mlx5_aso_age_action *age)
10585 struct mlx5_age_info *age_info;
10586 struct mlx5_age_param *age_param = &age->age_params;
10587 struct mlx5_priv *priv = dev->data->dev_private;
10588 uint16_t expected = AGE_CANDIDATE;
10590 age_info = GET_PORT_AGE_INFO(priv);
10591 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10592 AGE_FREE, false, __ATOMIC_RELAXED,
10593 __ATOMIC_RELAXED)) {
10595 * We need the lock even it is age timeout,
10596 * since age action may still in process.
10598 rte_spinlock_lock(&age_info->aged_sl);
10599 LIST_REMOVE(age, next);
10600 rte_spinlock_unlock(&age_info->aged_sl);
10601 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10606 * Release an ASO age action.
10609 * Pointer to the Ethernet device structure.
10610 * @param[in] age_idx
10611 * Index of ASO age action to release.
10613 * True if the release operation is during flow destroy operation.
10614 * False if the release operation is during action destroy operation.
10617 * 0 when age action was removed, otherwise the number of references.
10620 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10622 struct mlx5_priv *priv = dev->data->dev_private;
10623 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10624 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10625 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10628 flow_dv_aso_age_remove_from_age(dev, age);
10629 rte_spinlock_lock(&mng->free_sl);
10630 LIST_INSERT_HEAD(&mng->free, age, next);
10631 rte_spinlock_unlock(&mng->free_sl);
10637 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10640 * Pointer to the Ethernet device structure.
10643 * 0 on success, otherwise negative errno value and rte_errno is set.
10646 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10648 struct mlx5_priv *priv = dev->data->dev_private;
10649 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10650 void *old_pools = mng->pools;
10651 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10652 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10653 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10656 rte_errno = ENOMEM;
10660 memcpy(pools, old_pools,
10661 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10662 mlx5_free(old_pools);
10664 /* First ASO flow hit allocation - starting ASO data-path. */
10665 int ret = mlx5_aso_queue_start(priv->sh);
10673 mng->pools = pools;
10678 * Create and initialize a new ASO aging pool.
10681 * Pointer to the Ethernet device structure.
10682 * @param[out] age_free
10683 * Where to put the pointer of a new age action.
10686 * The age actions pool pointer and @p age_free is set on success,
10687 * NULL otherwise and rte_errno is set.
10689 static struct mlx5_aso_age_pool *
10690 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10691 struct mlx5_aso_age_action **age_free)
10693 struct mlx5_priv *priv = dev->data->dev_private;
10694 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10695 struct mlx5_aso_age_pool *pool = NULL;
10696 struct mlx5_devx_obj *obj = NULL;
10699 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10702 rte_errno = ENODATA;
10703 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10706 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10708 claim_zero(mlx5_devx_cmd_destroy(obj));
10709 rte_errno = ENOMEM;
10712 pool->flow_hit_aso_obj = obj;
10713 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10714 rte_spinlock_lock(&mng->resize_sl);
10715 pool->index = mng->next;
10716 /* Resize pools array if there is no room for the new pool in it. */
10717 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10718 claim_zero(mlx5_devx_cmd_destroy(obj));
10720 rte_spinlock_unlock(&mng->resize_sl);
10723 mng->pools[pool->index] = pool;
10725 rte_spinlock_unlock(&mng->resize_sl);
10726 /* Assign the first action in the new pool, the rest go to free list. */
10727 *age_free = &pool->actions[0];
10728 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10729 pool->actions[i].offset = i;
10730 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10736 * Allocate a ASO aging bit.
10739 * Pointer to the Ethernet device structure.
10740 * @param[out] error
10741 * Pointer to the error structure.
10744 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10747 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10749 struct mlx5_priv *priv = dev->data->dev_private;
10750 const struct mlx5_aso_age_pool *pool;
10751 struct mlx5_aso_age_action *age_free = NULL;
10752 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10755 /* Try to get the next free age action bit. */
10756 rte_spinlock_lock(&mng->free_sl);
10757 age_free = LIST_FIRST(&mng->free);
10759 LIST_REMOVE(age_free, next);
10760 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10761 rte_spinlock_unlock(&mng->free_sl);
10762 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10763 NULL, "failed to create ASO age pool");
10764 return 0; /* 0 is an error. */
10766 rte_spinlock_unlock(&mng->free_sl);
10767 pool = container_of
10768 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10769 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10771 if (!age_free->dr_action) {
10772 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10776 rte_flow_error_set(error, rte_errno,
10777 RTE_FLOW_ERROR_TYPE_ACTION,
10778 NULL, "failed to get reg_c "
10779 "for ASO flow hit");
10780 return 0; /* 0 is an error. */
10782 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10783 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10784 (priv->sh->rx_domain,
10785 pool->flow_hit_aso_obj->obj, age_free->offset,
10786 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10787 (reg_c - REG_C_0));
10788 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10789 if (!age_free->dr_action) {
10791 rte_spinlock_lock(&mng->free_sl);
10792 LIST_INSERT_HEAD(&mng->free, age_free, next);
10793 rte_spinlock_unlock(&mng->free_sl);
10794 rte_flow_error_set(error, rte_errno,
10795 RTE_FLOW_ERROR_TYPE_ACTION,
10796 NULL, "failed to create ASO "
10797 "flow hit action");
10798 return 0; /* 0 is an error. */
10801 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10802 return pool->index | ((age_free->offset + 1) << 16);
10806 * Create a age action using ASO mechanism.
10809 * Pointer to rte_eth_dev structure.
10811 * Pointer to the aging action configuration.
10812 * @param[out] error
10813 * Pointer to the error structure.
10816 * Index to flow counter on success, 0 otherwise.
10819 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10820 const struct rte_flow_action_age *age,
10821 struct rte_flow_error *error)
10823 uint32_t age_idx = 0;
10824 struct mlx5_aso_age_action *aso_age;
10826 age_idx = flow_dv_aso_age_alloc(dev, error);
10829 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10830 aso_age->age_params.context = age->context;
10831 aso_age->age_params.timeout = age->timeout;
10832 aso_age->age_params.port_id = dev->data->port_id;
10833 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10835 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10841 * Fill the flow with DV spec, lock free
10842 * (mutex should be acquired by caller).
10845 * Pointer to rte_eth_dev structure.
10846 * @param[in, out] dev_flow
10847 * Pointer to the sub flow.
10849 * Pointer to the flow attributes.
10851 * Pointer to the list of items.
10852 * @param[in] actions
10853 * Pointer to the list of actions.
10854 * @param[out] error
10855 * Pointer to the error structure.
10858 * 0 on success, a negative errno value otherwise and rte_errno is set.
10861 flow_dv_translate(struct rte_eth_dev *dev,
10862 struct mlx5_flow *dev_flow,
10863 const struct rte_flow_attr *attr,
10864 const struct rte_flow_item items[],
10865 const struct rte_flow_action actions[],
10866 struct rte_flow_error *error)
10868 struct mlx5_priv *priv = dev->data->dev_private;
10869 struct mlx5_dev_config *dev_conf = &priv->config;
10870 struct rte_flow *flow = dev_flow->flow;
10871 struct mlx5_flow_handle *handle = dev_flow->handle;
10872 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10873 struct mlx5_flow_rss_desc *rss_desc;
10874 uint64_t item_flags = 0;
10875 uint64_t last_item = 0;
10876 uint64_t action_flags = 0;
10877 struct mlx5_flow_dv_matcher matcher = {
10879 .size = sizeof(matcher.mask.buf) -
10880 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10884 bool actions_end = false;
10886 struct mlx5_flow_dv_modify_hdr_resource res;
10887 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10888 sizeof(struct mlx5_modification_cmd) *
10889 (MLX5_MAX_MODIFY_NUM + 1)];
10891 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10892 const struct rte_flow_action_count *count = NULL;
10893 const struct rte_flow_action_age *age = NULL;
10894 union flow_dv_attr flow_attr = { .attr = 0 };
10896 union mlx5_flow_tbl_key tbl_key;
10897 uint32_t modify_action_position = UINT32_MAX;
10898 void *match_mask = matcher.mask.buf;
10899 void *match_value = dev_flow->dv.value.buf;
10900 uint8_t next_protocol = 0xff;
10901 struct rte_vlan_hdr vlan = { 0 };
10902 struct mlx5_flow_dv_dest_array_resource mdest_res;
10903 struct mlx5_flow_dv_sample_resource sample_res;
10904 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10905 const struct rte_flow_action_sample *sample = NULL;
10906 struct mlx5_flow_sub_actions_list *sample_act;
10907 uint32_t sample_act_pos = UINT32_MAX;
10908 uint32_t num_of_dest = 0;
10909 int tmp_actions_n = 0;
10912 const struct mlx5_flow_tunnel *tunnel;
10913 struct flow_grp_info grp_info = {
10914 .external = !!dev_flow->external,
10915 .transfer = !!attr->transfer,
10916 .fdb_def_rule = !!priv->fdb_def_rule,
10917 .skip_scale = dev_flow->skip_scale &
10918 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10922 return rte_flow_error_set(error, ENOMEM,
10923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10925 "failed to push flow workspace");
10926 rss_desc = &wks->rss_desc;
10927 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10928 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10929 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10930 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10931 /* update normal path action resource into last index of array */
10932 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10933 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10934 flow_items_to_tunnel(items) :
10935 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10936 flow_actions_to_tunnel(actions) :
10937 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10938 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10939 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10940 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10941 (dev, tunnel, attr, items, actions);
10942 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10946 dev_flow->dv.group = table;
10947 if (attr->transfer)
10948 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10949 /* number of actions must be set to 0 in case of dirty stack. */
10950 mhdr_res->actions_num = 0;
10951 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10953 * do not add decap action if match rule drops packet
10954 * HW rejects rules with decap & drop
10956 * if tunnel match rule was inserted before matching tunnel set
10957 * rule flow table used in the match rule must be registered.
10958 * current implementation handles that in the
10959 * flow_dv_match_register() at the function end.
10961 bool add_decap = true;
10962 const struct rte_flow_action *ptr = actions;
10964 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10965 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10971 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10975 dev_flow->dv.actions[actions_n++] =
10976 dev_flow->dv.encap_decap->action;
10977 action_flags |= MLX5_FLOW_ACTION_DECAP;
10980 for (; !actions_end ; actions++) {
10981 const struct rte_flow_action_queue *queue;
10982 const struct rte_flow_action_rss *rss;
10983 const struct rte_flow_action *action = actions;
10984 const uint8_t *rss_key;
10985 const struct rte_flow_action_meter *mtr;
10986 struct mlx5_flow_tbl_resource *tbl;
10987 struct mlx5_aso_age_action *age_act;
10988 uint32_t port_id = 0;
10989 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10990 int action_type = actions->type;
10991 const struct rte_flow_action *found_action = NULL;
10992 struct mlx5_flow_meter *fm = NULL;
10993 uint32_t jump_group = 0;
10995 if (!mlx5_flow_os_action_supported(action_type))
10996 return rte_flow_error_set(error, ENOTSUP,
10997 RTE_FLOW_ERROR_TYPE_ACTION,
10999 "action not supported");
11000 switch (action_type) {
11001 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11002 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11004 case RTE_FLOW_ACTION_TYPE_VOID:
11006 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11007 if (flow_dv_translate_action_port_id(dev, action,
11010 port_id_resource.port_id = port_id;
11011 MLX5_ASSERT(!handle->rix_port_id_action);
11012 if (flow_dv_port_id_action_resource_register
11013 (dev, &port_id_resource, dev_flow, error))
11015 dev_flow->dv.actions[actions_n++] =
11016 dev_flow->dv.port_id_action->action;
11017 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11018 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11019 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11022 case RTE_FLOW_ACTION_TYPE_FLAG:
11023 action_flags |= MLX5_FLOW_ACTION_FLAG;
11024 dev_flow->handle->mark = 1;
11025 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11026 struct rte_flow_action_mark mark = {
11027 .id = MLX5_FLOW_MARK_DEFAULT,
11030 if (flow_dv_convert_action_mark(dev, &mark,
11034 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11037 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11039 * Only one FLAG or MARK is supported per device flow
11040 * right now. So the pointer to the tag resource must be
11041 * zero before the register process.
11043 MLX5_ASSERT(!handle->dvh.rix_tag);
11044 if (flow_dv_tag_resource_register(dev, tag_be,
11047 MLX5_ASSERT(dev_flow->dv.tag_resource);
11048 dev_flow->dv.actions[actions_n++] =
11049 dev_flow->dv.tag_resource->action;
11051 case RTE_FLOW_ACTION_TYPE_MARK:
11052 action_flags |= MLX5_FLOW_ACTION_MARK;
11053 dev_flow->handle->mark = 1;
11054 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11055 const struct rte_flow_action_mark *mark =
11056 (const struct rte_flow_action_mark *)
11059 if (flow_dv_convert_action_mark(dev, mark,
11063 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11067 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11068 /* Legacy (non-extensive) MARK action. */
11069 tag_be = mlx5_flow_mark_set
11070 (((const struct rte_flow_action_mark *)
11071 (actions->conf))->id);
11072 MLX5_ASSERT(!handle->dvh.rix_tag);
11073 if (flow_dv_tag_resource_register(dev, tag_be,
11076 MLX5_ASSERT(dev_flow->dv.tag_resource);
11077 dev_flow->dv.actions[actions_n++] =
11078 dev_flow->dv.tag_resource->action;
11080 case RTE_FLOW_ACTION_TYPE_SET_META:
11081 if (flow_dv_convert_action_set_meta
11082 (dev, mhdr_res, attr,
11083 (const struct rte_flow_action_set_meta *)
11084 actions->conf, error))
11086 action_flags |= MLX5_FLOW_ACTION_SET_META;
11088 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11089 if (flow_dv_convert_action_set_tag
11091 (const struct rte_flow_action_set_tag *)
11092 actions->conf, error))
11094 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11096 case RTE_FLOW_ACTION_TYPE_DROP:
11097 action_flags |= MLX5_FLOW_ACTION_DROP;
11098 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11100 case RTE_FLOW_ACTION_TYPE_QUEUE:
11101 queue = actions->conf;
11102 rss_desc->queue_num = 1;
11103 rss_desc->queue[0] = queue->index;
11104 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11105 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11106 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11109 case RTE_FLOW_ACTION_TYPE_RSS:
11110 rss = actions->conf;
11111 memcpy(rss_desc->queue, rss->queue,
11112 rss->queue_num * sizeof(uint16_t));
11113 rss_desc->queue_num = rss->queue_num;
11114 /* NULL RSS key indicates default RSS key. */
11115 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11116 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11118 * rss->level and rss.types should be set in advance
11119 * when expanding items for RSS.
11121 action_flags |= MLX5_FLOW_ACTION_RSS;
11122 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11123 MLX5_FLOW_FATE_SHARED_RSS :
11124 MLX5_FLOW_FATE_QUEUE;
11126 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11127 flow->age = (uint32_t)(uintptr_t)(action->conf);
11128 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11129 __atomic_fetch_add(&age_act->refcnt, 1,
11131 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11132 action_flags |= MLX5_FLOW_ACTION_AGE;
11134 case RTE_FLOW_ACTION_TYPE_AGE:
11135 if (priv->sh->flow_hit_aso_en && attr->group) {
11137 * Create one shared age action, to be used
11138 * by all sub-flows.
11142 flow_dv_translate_create_aso_age
11143 (dev, action->conf,
11146 return rte_flow_error_set
11148 RTE_FLOW_ERROR_TYPE_ACTION,
11150 "can't create ASO age action");
11152 dev_flow->dv.actions[actions_n++] =
11153 (flow_aso_age_get_by_idx
11154 (dev, flow->age))->dr_action;
11155 action_flags |= MLX5_FLOW_ACTION_AGE;
11159 case RTE_FLOW_ACTION_TYPE_COUNT:
11160 if (!dev_conf->devx) {
11161 return rte_flow_error_set
11163 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11165 "count action not supported");
11167 /* Save information first, will apply later. */
11168 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11169 count = action->conf;
11171 age = action->conf;
11172 action_flags |= MLX5_FLOW_ACTION_COUNT;
11174 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11175 dev_flow->dv.actions[actions_n++] =
11176 priv->sh->pop_vlan_action;
11177 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11179 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11180 if (!(action_flags &
11181 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11182 flow_dev_get_vlan_info_from_items(items, &vlan);
11183 vlan.eth_proto = rte_be_to_cpu_16
11184 ((((const struct rte_flow_action_of_push_vlan *)
11185 actions->conf)->ethertype));
11186 found_action = mlx5_flow_find_action
11188 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11190 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11191 found_action = mlx5_flow_find_action
11193 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11195 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11196 if (flow_dv_create_action_push_vlan
11197 (dev, attr, &vlan, dev_flow, error))
11199 dev_flow->dv.actions[actions_n++] =
11200 dev_flow->dv.push_vlan_res->action;
11201 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11203 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11204 /* of_vlan_push action handled this action */
11205 MLX5_ASSERT(action_flags &
11206 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11208 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11209 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11211 flow_dev_get_vlan_info_from_items(items, &vlan);
11212 mlx5_update_vlan_vid_pcp(actions, &vlan);
11213 /* If no VLAN push - this is a modify header action */
11214 if (flow_dv_convert_action_modify_vlan_vid
11215 (mhdr_res, actions, error))
11217 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11219 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11220 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11221 if (flow_dv_create_action_l2_encap(dev, actions,
11226 dev_flow->dv.actions[actions_n++] =
11227 dev_flow->dv.encap_decap->action;
11228 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11229 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11230 sample_act->action_flags |=
11231 MLX5_FLOW_ACTION_ENCAP;
11233 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11234 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11235 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11239 dev_flow->dv.actions[actions_n++] =
11240 dev_flow->dv.encap_decap->action;
11241 action_flags |= MLX5_FLOW_ACTION_DECAP;
11243 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11244 /* Handle encap with preceding decap. */
11245 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11246 if (flow_dv_create_action_raw_encap
11247 (dev, actions, dev_flow, attr, error))
11249 dev_flow->dv.actions[actions_n++] =
11250 dev_flow->dv.encap_decap->action;
11252 /* Handle encap without preceding decap. */
11253 if (flow_dv_create_action_l2_encap
11254 (dev, actions, dev_flow, attr->transfer,
11257 dev_flow->dv.actions[actions_n++] =
11258 dev_flow->dv.encap_decap->action;
11260 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11261 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11262 sample_act->action_flags |=
11263 MLX5_FLOW_ACTION_ENCAP;
11265 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11266 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11268 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11269 if (flow_dv_create_action_l2_decap
11270 (dev, dev_flow, attr->transfer, error))
11272 dev_flow->dv.actions[actions_n++] =
11273 dev_flow->dv.encap_decap->action;
11275 /* If decap is followed by encap, handle it at encap. */
11276 action_flags |= MLX5_FLOW_ACTION_DECAP;
11278 case RTE_FLOW_ACTION_TYPE_JUMP:
11279 jump_group = ((const struct rte_flow_action_jump *)
11280 action->conf)->group;
11281 grp_info.std_tbl_fix = 0;
11282 if (dev_flow->skip_scale &
11283 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11284 grp_info.skip_scale = 1;
11286 grp_info.skip_scale = 0;
11287 ret = mlx5_flow_group_to_table(dev, tunnel,
11293 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11295 !!dev_flow->external,
11296 tunnel, jump_group, 0,
11299 return rte_flow_error_set
11301 RTE_FLOW_ERROR_TYPE_ACTION,
11303 "cannot create jump action.");
11304 if (flow_dv_jump_tbl_resource_register
11305 (dev, tbl, dev_flow, error)) {
11306 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11307 return rte_flow_error_set
11309 RTE_FLOW_ERROR_TYPE_ACTION,
11311 "cannot create jump action.");
11313 dev_flow->dv.actions[actions_n++] =
11314 dev_flow->dv.jump->action;
11315 action_flags |= MLX5_FLOW_ACTION_JUMP;
11316 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11317 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11320 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11321 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11322 if (flow_dv_convert_action_modify_mac
11323 (mhdr_res, actions, error))
11325 action_flags |= actions->type ==
11326 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11327 MLX5_FLOW_ACTION_SET_MAC_SRC :
11328 MLX5_FLOW_ACTION_SET_MAC_DST;
11330 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11331 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11332 if (flow_dv_convert_action_modify_ipv4
11333 (mhdr_res, actions, error))
11335 action_flags |= actions->type ==
11336 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11337 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11338 MLX5_FLOW_ACTION_SET_IPV4_DST;
11340 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11341 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11342 if (flow_dv_convert_action_modify_ipv6
11343 (mhdr_res, actions, error))
11345 action_flags |= actions->type ==
11346 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11347 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11348 MLX5_FLOW_ACTION_SET_IPV6_DST;
11350 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11351 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11352 if (flow_dv_convert_action_modify_tp
11353 (mhdr_res, actions, items,
11354 &flow_attr, dev_flow, !!(action_flags &
11355 MLX5_FLOW_ACTION_DECAP), error))
11357 action_flags |= actions->type ==
11358 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11359 MLX5_FLOW_ACTION_SET_TP_SRC :
11360 MLX5_FLOW_ACTION_SET_TP_DST;
11362 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11363 if (flow_dv_convert_action_modify_dec_ttl
11364 (mhdr_res, items, &flow_attr, dev_flow,
11366 MLX5_FLOW_ACTION_DECAP), error))
11368 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11370 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11371 if (flow_dv_convert_action_modify_ttl
11372 (mhdr_res, actions, items, &flow_attr,
11373 dev_flow, !!(action_flags &
11374 MLX5_FLOW_ACTION_DECAP), error))
11376 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11378 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11379 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11380 if (flow_dv_convert_action_modify_tcp_seq
11381 (mhdr_res, actions, error))
11383 action_flags |= actions->type ==
11384 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11385 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11386 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11389 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11390 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11391 if (flow_dv_convert_action_modify_tcp_ack
11392 (mhdr_res, actions, error))
11394 action_flags |= actions->type ==
11395 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11396 MLX5_FLOW_ACTION_INC_TCP_ACK :
11397 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11399 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11400 if (flow_dv_convert_action_set_reg
11401 (mhdr_res, actions, error))
11403 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11405 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11406 if (flow_dv_convert_action_copy_mreg
11407 (dev, mhdr_res, actions, error))
11409 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11411 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11412 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11413 dev_flow->handle->fate_action =
11414 MLX5_FLOW_FATE_DEFAULT_MISS;
11416 case RTE_FLOW_ACTION_TYPE_METER:
11417 mtr = actions->conf;
11418 if (!flow->meter) {
11419 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11422 return rte_flow_error_set(error,
11424 RTE_FLOW_ERROR_TYPE_ACTION,
11427 "or invalid parameters");
11428 flow->meter = fm->idx;
11430 /* Set the meter action. */
11432 fm = mlx5_ipool_get(priv->sh->ipool
11433 [MLX5_IPOOL_MTR], flow->meter);
11435 return rte_flow_error_set(error,
11437 RTE_FLOW_ERROR_TYPE_ACTION,
11440 "or invalid parameters");
11442 dev_flow->dv.actions[actions_n++] =
11443 fm->mfts->meter_action;
11444 action_flags |= MLX5_FLOW_ACTION_METER;
11446 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11447 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11450 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11452 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11453 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11456 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11458 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11459 sample_act_pos = actions_n;
11460 sample = (const struct rte_flow_action_sample *)
11463 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11464 /* put encap action into group if work with port id */
11465 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11466 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11467 sample_act->action_flags |=
11468 MLX5_FLOW_ACTION_ENCAP;
11470 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11471 if (flow_dv_convert_action_modify_field
11472 (dev, mhdr_res, actions, attr, error))
11474 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11476 case RTE_FLOW_ACTION_TYPE_END:
11477 actions_end = true;
11478 if (mhdr_res->actions_num) {
11479 /* create modify action if needed. */
11480 if (flow_dv_modify_hdr_resource_register
11481 (dev, mhdr_res, dev_flow, error))
11483 dev_flow->dv.actions[modify_action_position] =
11484 handle->dvh.modify_hdr->action;
11486 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11488 * Create one count action, to be used
11489 * by all sub-flows.
11491 if (!flow->counter) {
11493 flow_dv_translate_create_counter
11494 (dev, dev_flow, count,
11496 if (!flow->counter)
11497 return rte_flow_error_set
11499 RTE_FLOW_ERROR_TYPE_ACTION,
11500 NULL, "cannot create counter"
11503 dev_flow->dv.actions[actions_n] =
11504 (flow_dv_counter_get_by_idx(dev,
11505 flow->counter, NULL))->action;
11511 if (mhdr_res->actions_num &&
11512 modify_action_position == UINT32_MAX)
11513 modify_action_position = actions_n++;
11515 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11516 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11517 int item_type = items->type;
11519 if (!mlx5_flow_os_item_supported(item_type))
11520 return rte_flow_error_set(error, ENOTSUP,
11521 RTE_FLOW_ERROR_TYPE_ITEM,
11522 NULL, "item not supported");
11523 switch (item_type) {
11524 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11525 flow_dv_translate_item_port_id
11526 (dev, match_mask, match_value, items, attr);
11527 last_item = MLX5_FLOW_ITEM_PORT_ID;
11529 case RTE_FLOW_ITEM_TYPE_ETH:
11530 flow_dv_translate_item_eth(match_mask, match_value,
11532 dev_flow->dv.group);
11533 matcher.priority = action_flags &
11534 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11535 !dev_flow->external ?
11536 MLX5_PRIORITY_MAP_L3 :
11537 MLX5_PRIORITY_MAP_L2;
11538 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11539 MLX5_FLOW_LAYER_OUTER_L2;
11541 case RTE_FLOW_ITEM_TYPE_VLAN:
11542 flow_dv_translate_item_vlan(dev_flow,
11543 match_mask, match_value,
11545 dev_flow->dv.group);
11546 matcher.priority = MLX5_PRIORITY_MAP_L2;
11547 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11548 MLX5_FLOW_LAYER_INNER_VLAN) :
11549 (MLX5_FLOW_LAYER_OUTER_L2 |
11550 MLX5_FLOW_LAYER_OUTER_VLAN);
11552 case RTE_FLOW_ITEM_TYPE_IPV4:
11553 mlx5_flow_tunnel_ip_check(items, next_protocol,
11554 &item_flags, &tunnel);
11555 flow_dv_translate_item_ipv4(match_mask, match_value,
11557 dev_flow->dv.group);
11558 matcher.priority = MLX5_PRIORITY_MAP_L3;
11559 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11560 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11561 if (items->mask != NULL &&
11562 ((const struct rte_flow_item_ipv4 *)
11563 items->mask)->hdr.next_proto_id) {
11565 ((const struct rte_flow_item_ipv4 *)
11566 (items->spec))->hdr.next_proto_id;
11568 ((const struct rte_flow_item_ipv4 *)
11569 (items->mask))->hdr.next_proto_id;
11571 /* Reset for inner layer. */
11572 next_protocol = 0xff;
11575 case RTE_FLOW_ITEM_TYPE_IPV6:
11576 mlx5_flow_tunnel_ip_check(items, next_protocol,
11577 &item_flags, &tunnel);
11578 flow_dv_translate_item_ipv6(match_mask, match_value,
11580 dev_flow->dv.group);
11581 matcher.priority = MLX5_PRIORITY_MAP_L3;
11582 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11583 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11584 if (items->mask != NULL &&
11585 ((const struct rte_flow_item_ipv6 *)
11586 items->mask)->hdr.proto) {
11588 ((const struct rte_flow_item_ipv6 *)
11589 items->spec)->hdr.proto;
11591 ((const struct rte_flow_item_ipv6 *)
11592 items->mask)->hdr.proto;
11594 /* Reset for inner layer. */
11595 next_protocol = 0xff;
11598 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11599 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11602 last_item = tunnel ?
11603 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11604 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11605 if (items->mask != NULL &&
11606 ((const struct rte_flow_item_ipv6_frag_ext *)
11607 items->mask)->hdr.next_header) {
11609 ((const struct rte_flow_item_ipv6_frag_ext *)
11610 items->spec)->hdr.next_header;
11612 ((const struct rte_flow_item_ipv6_frag_ext *)
11613 items->mask)->hdr.next_header;
11615 /* Reset for inner layer. */
11616 next_protocol = 0xff;
11619 case RTE_FLOW_ITEM_TYPE_TCP:
11620 flow_dv_translate_item_tcp(match_mask, match_value,
11622 matcher.priority = MLX5_PRIORITY_MAP_L4;
11623 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11624 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11626 case RTE_FLOW_ITEM_TYPE_UDP:
11627 flow_dv_translate_item_udp(match_mask, match_value,
11629 matcher.priority = MLX5_PRIORITY_MAP_L4;
11630 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11631 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11633 case RTE_FLOW_ITEM_TYPE_GRE:
11634 flow_dv_translate_item_gre(match_mask, match_value,
11636 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11637 last_item = MLX5_FLOW_LAYER_GRE;
11639 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11640 flow_dv_translate_item_gre_key(match_mask,
11641 match_value, items);
11642 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11644 case RTE_FLOW_ITEM_TYPE_NVGRE:
11645 flow_dv_translate_item_nvgre(match_mask, match_value,
11647 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11648 last_item = MLX5_FLOW_LAYER_GRE;
11650 case RTE_FLOW_ITEM_TYPE_VXLAN:
11651 flow_dv_translate_item_vxlan(match_mask, match_value,
11653 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11654 last_item = MLX5_FLOW_LAYER_VXLAN;
11656 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11657 flow_dv_translate_item_vxlan_gpe(match_mask,
11658 match_value, items,
11660 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11661 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11663 case RTE_FLOW_ITEM_TYPE_GENEVE:
11664 flow_dv_translate_item_geneve(match_mask, match_value,
11666 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11667 last_item = MLX5_FLOW_LAYER_GENEVE;
11669 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11670 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11674 return rte_flow_error_set(error, -ret,
11675 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11676 "cannot create GENEVE TLV option");
11677 flow->geneve_tlv_option = 1;
11678 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11680 case RTE_FLOW_ITEM_TYPE_MPLS:
11681 flow_dv_translate_item_mpls(match_mask, match_value,
11682 items, last_item, tunnel);
11683 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11684 last_item = MLX5_FLOW_LAYER_MPLS;
11686 case RTE_FLOW_ITEM_TYPE_MARK:
11687 flow_dv_translate_item_mark(dev, match_mask,
11688 match_value, items);
11689 last_item = MLX5_FLOW_ITEM_MARK;
11691 case RTE_FLOW_ITEM_TYPE_META:
11692 flow_dv_translate_item_meta(dev, match_mask,
11693 match_value, attr, items);
11694 last_item = MLX5_FLOW_ITEM_METADATA;
11696 case RTE_FLOW_ITEM_TYPE_ICMP:
11697 flow_dv_translate_item_icmp(match_mask, match_value,
11699 last_item = MLX5_FLOW_LAYER_ICMP;
11701 case RTE_FLOW_ITEM_TYPE_ICMP6:
11702 flow_dv_translate_item_icmp6(match_mask, match_value,
11704 last_item = MLX5_FLOW_LAYER_ICMP6;
11706 case RTE_FLOW_ITEM_TYPE_TAG:
11707 flow_dv_translate_item_tag(dev, match_mask,
11708 match_value, items);
11709 last_item = MLX5_FLOW_ITEM_TAG;
11711 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11712 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11713 match_value, items);
11714 last_item = MLX5_FLOW_ITEM_TAG;
11716 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11717 flow_dv_translate_item_tx_queue(dev, match_mask,
11720 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11722 case RTE_FLOW_ITEM_TYPE_GTP:
11723 flow_dv_translate_item_gtp(match_mask, match_value,
11725 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11726 last_item = MLX5_FLOW_LAYER_GTP;
11728 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11729 ret = flow_dv_translate_item_gtp_psc(match_mask,
11733 return rte_flow_error_set(error, -ret,
11734 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11735 "cannot create GTP PSC item");
11736 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11738 case RTE_FLOW_ITEM_TYPE_ECPRI:
11739 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11740 /* Create it only the first time to be used. */
11741 ret = mlx5_flex_parser_ecpri_alloc(dev);
11743 return rte_flow_error_set
11745 RTE_FLOW_ERROR_TYPE_ITEM,
11747 "cannot create eCPRI parser");
11749 /* Adjust the length matcher and device flow value. */
11750 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11751 dev_flow->dv.value.size =
11752 MLX5_ST_SZ_BYTES(fte_match_param);
11753 flow_dv_translate_item_ecpri(dev, match_mask,
11754 match_value, items);
11755 /* No other protocol should follow eCPRI layer. */
11756 last_item = MLX5_FLOW_LAYER_ECPRI;
11761 item_flags |= last_item;
11764 * When E-Switch mode is enabled, we have two cases where we need to
11765 * set the source port manually.
11766 * The first one, is in case of Nic steering rule, and the second is
11767 * E-Switch rule where no port_id item was found. In both cases
11768 * the source port is set according the current port in use.
11770 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11771 (priv->representor || priv->master)) {
11772 if (flow_dv_translate_item_port_id(dev, match_mask,
11773 match_value, NULL, attr))
11776 #ifdef RTE_LIBRTE_MLX5_DEBUG
11777 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11778 dev_flow->dv.value.buf));
11781 * Layers may be already initialized from prefix flow if this dev_flow
11782 * is the suffix flow.
11784 handle->layers |= item_flags;
11785 if (action_flags & MLX5_FLOW_ACTION_RSS)
11786 flow_dv_hashfields_set(dev_flow, rss_desc);
11787 /* If has RSS action in the sample action, the Sample/Mirror resource
11788 * should be registered after the hash filed be update.
11790 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11791 ret = flow_dv_translate_action_sample(dev,
11800 ret = flow_dv_create_action_sample(dev,
11809 return rte_flow_error_set
11811 RTE_FLOW_ERROR_TYPE_ACTION,
11813 "cannot create sample action");
11814 if (num_of_dest > 1) {
11815 dev_flow->dv.actions[sample_act_pos] =
11816 dev_flow->dv.dest_array_res->action;
11818 dev_flow->dv.actions[sample_act_pos] =
11819 dev_flow->dv.sample_res->verbs_action;
11823 * For multiple destination (sample action with ratio=1), the encap
11824 * action and port id action will be combined into group action.
11825 * So need remove the original these actions in the flow and only
11826 * use the sample action instead of.
11828 if (num_of_dest > 1 &&
11829 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11831 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11833 for (i = 0; i < actions_n; i++) {
11834 if ((sample_act->dr_encap_action &&
11835 sample_act->dr_encap_action ==
11836 dev_flow->dv.actions[i]) ||
11837 (sample_act->dr_port_id_action &&
11838 sample_act->dr_port_id_action ==
11839 dev_flow->dv.actions[i]) ||
11840 (sample_act->dr_jump_action &&
11841 sample_act->dr_jump_action ==
11842 dev_flow->dv.actions[i]))
11844 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11846 memcpy((void *)dev_flow->dv.actions,
11847 (void *)temp_actions,
11848 tmp_actions_n * sizeof(void *));
11849 actions_n = tmp_actions_n;
11851 dev_flow->dv.actions_n = actions_n;
11852 dev_flow->act_flags = action_flags;
11853 /* Register matcher. */
11854 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11855 matcher.mask.size);
11856 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11858 /* reserved field no needs to be set to 0 here. */
11859 tbl_key.domain = attr->transfer;
11860 tbl_key.direction = attr->egress;
11861 tbl_key.table_id = dev_flow->dv.group;
11862 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11863 tunnel, attr->group, error))
11869 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11872 * @param[in, out] action
11873 * Shred RSS action holding hash RX queue objects.
11874 * @param[in] hash_fields
11875 * Defines combination of packet fields to participate in RX hash.
11876 * @param[in] tunnel
11878 * @param[in] hrxq_idx
11879 * Hash RX queue index to set.
11882 * 0 on success, otherwise negative errno value.
11885 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11886 const uint64_t hash_fields,
11889 uint32_t *hrxqs = action->hrxq;
11891 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11892 case MLX5_RSS_HASH_IPV4:
11893 /* fall-through. */
11894 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11895 /* fall-through. */
11896 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11897 hrxqs[0] = hrxq_idx;
11899 case MLX5_RSS_HASH_IPV4_TCP:
11900 /* fall-through. */
11901 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11902 /* fall-through. */
11903 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11904 hrxqs[1] = hrxq_idx;
11906 case MLX5_RSS_HASH_IPV4_UDP:
11907 /* fall-through. */
11908 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11909 /* fall-through. */
11910 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11911 hrxqs[2] = hrxq_idx;
11913 case MLX5_RSS_HASH_IPV6:
11914 /* fall-through. */
11915 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11916 /* fall-through. */
11917 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11918 hrxqs[3] = hrxq_idx;
11920 case MLX5_RSS_HASH_IPV6_TCP:
11921 /* fall-through. */
11922 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11923 /* fall-through. */
11924 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11925 hrxqs[4] = hrxq_idx;
11927 case MLX5_RSS_HASH_IPV6_UDP:
11928 /* fall-through. */
11929 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11930 /* fall-through. */
11931 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11932 hrxqs[5] = hrxq_idx;
11934 case MLX5_RSS_HASH_NONE:
11935 hrxqs[6] = hrxq_idx;
11943 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11947 * Pointer to the Ethernet device structure.
11949 * Shared RSS action ID holding hash RX queue objects.
11950 * @param[in] hash_fields
11951 * Defines combination of packet fields to participate in RX hash.
11952 * @param[in] tunnel
11956 * Valid hash RX queue index, otherwise 0.
11959 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11960 const uint64_t hash_fields)
11962 struct mlx5_priv *priv = dev->data->dev_private;
11963 struct mlx5_shared_action_rss *shared_rss =
11964 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11965 const uint32_t *hrxqs = shared_rss->hrxq;
11967 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11968 case MLX5_RSS_HASH_IPV4:
11969 /* fall-through. */
11970 case MLX5_RSS_HASH_IPV4_DST_ONLY:
11971 /* fall-through. */
11972 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11974 case MLX5_RSS_HASH_IPV4_TCP:
11975 /* fall-through. */
11976 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11977 /* fall-through. */
11978 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11980 case MLX5_RSS_HASH_IPV4_UDP:
11981 /* fall-through. */
11982 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11983 /* fall-through. */
11984 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11986 case MLX5_RSS_HASH_IPV6:
11987 /* fall-through. */
11988 case MLX5_RSS_HASH_IPV6_DST_ONLY:
11989 /* fall-through. */
11990 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11992 case MLX5_RSS_HASH_IPV6_TCP:
11993 /* fall-through. */
11994 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11995 /* fall-through. */
11996 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11998 case MLX5_RSS_HASH_IPV6_UDP:
11999 /* fall-through. */
12000 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12001 /* fall-through. */
12002 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12004 case MLX5_RSS_HASH_NONE:
12013 * Apply the flow to the NIC, lock free,
12014 * (mutex should be acquired by caller).
12017 * Pointer to the Ethernet device structure.
12018 * @param[in, out] flow
12019 * Pointer to flow structure.
12020 * @param[out] error
12021 * Pointer to error structure.
12024 * 0 on success, a negative errno value otherwise and rte_errno is set.
12027 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12028 struct rte_flow_error *error)
12030 struct mlx5_flow_dv_workspace *dv;
12031 struct mlx5_flow_handle *dh;
12032 struct mlx5_flow_handle_dv *dv_h;
12033 struct mlx5_flow *dev_flow;
12034 struct mlx5_priv *priv = dev->data->dev_private;
12035 uint32_t handle_idx;
12039 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12040 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12043 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12044 dev_flow = &wks->flows[idx];
12045 dv = &dev_flow->dv;
12046 dh = dev_flow->handle;
12049 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12050 if (dv->transfer) {
12051 MLX5_ASSERT(priv->sh->dr_drop_action);
12052 dv->actions[n++] = priv->sh->dr_drop_action;
12054 #ifdef HAVE_MLX5DV_DR
12055 /* DR supports drop action placeholder. */
12056 MLX5_ASSERT(priv->sh->dr_drop_action);
12057 dv->actions[n++] = priv->sh->dr_drop_action;
12059 /* For DV we use the explicit drop queue. */
12060 MLX5_ASSERT(priv->drop_queue.hrxq);
12062 priv->drop_queue.hrxq->action;
12065 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12066 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12067 struct mlx5_hrxq *hrxq;
12070 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12075 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12076 "cannot get hash queue");
12079 dh->rix_hrxq = hrxq_idx;
12080 dv->actions[n++] = hrxq->action;
12081 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12082 struct mlx5_hrxq *hrxq = NULL;
12085 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12086 rss_desc->shared_rss,
12087 dev_flow->hash_fields);
12089 hrxq = mlx5_ipool_get
12090 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12096 "cannot get hash queue");
12099 dh->rix_srss = rss_desc->shared_rss;
12100 dv->actions[n++] = hrxq->action;
12101 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12102 if (!priv->sh->default_miss_action) {
12105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12106 "default miss action not be created.");
12109 dv->actions[n++] = priv->sh->default_miss_action;
12111 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12112 (void *)&dv->value, n,
12113 dv->actions, &dh->drv_flow);
12115 rte_flow_error_set(error, errno,
12116 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12118 "hardware refuses to create flow");
12121 if (priv->vmwa_context &&
12122 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12124 * The rule contains the VLAN pattern.
12125 * For VF we are going to create VLAN
12126 * interface to make hypervisor set correct
12127 * e-Switch vport context.
12129 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12134 err = rte_errno; /* Save rte_errno before cleanup. */
12135 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12136 handle_idx, dh, next) {
12137 /* hrxq is union, don't clear it if the flag is not set. */
12138 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12139 mlx5_hrxq_release(dev, dh->rix_hrxq);
12141 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12144 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12145 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12147 rte_errno = err; /* Restore rte_errno. */
12152 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12153 struct mlx5_cache_entry *entry)
12155 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12158 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12163 * Release the flow matcher.
12166 * Pointer to Ethernet device.
12168 * Index to port ID action resource.
12171 * 1 while a reference on it exists, 0 when freed.
12174 flow_dv_matcher_release(struct rte_eth_dev *dev,
12175 struct mlx5_flow_handle *handle)
12177 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12178 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12179 typeof(*tbl), tbl);
12182 MLX5_ASSERT(matcher->matcher_object);
12183 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12184 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12189 * Release encap_decap resource.
12192 * Pointer to the hash list.
12194 * Pointer to exist resource entry object.
12197 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12198 struct mlx5_hlist_entry *entry)
12200 struct mlx5_dev_ctx_shared *sh = list->ctx;
12201 struct mlx5_flow_dv_encap_decap_resource *res =
12202 container_of(entry, typeof(*res), entry);
12204 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12205 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12209 * Release an encap/decap resource.
12212 * Pointer to Ethernet device.
12213 * @param encap_decap_idx
12214 * Index of encap decap resource.
12217 * 1 while a reference on it exists, 0 when freed.
12220 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12221 uint32_t encap_decap_idx)
12223 struct mlx5_priv *priv = dev->data->dev_private;
12224 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12226 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12228 if (!cache_resource)
12230 MLX5_ASSERT(cache_resource->action);
12231 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12232 &cache_resource->entry);
12236 * Release an jump to table action resource.
12239 * Pointer to Ethernet device.
12241 * Index to the jump action resource.
12244 * 1 while a reference on it exists, 0 when freed.
12247 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12250 struct mlx5_priv *priv = dev->data->dev_private;
12251 struct mlx5_flow_tbl_data_entry *tbl_data;
12253 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12257 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12261 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12262 struct mlx5_hlist_entry *entry)
12264 struct mlx5_flow_dv_modify_hdr_resource *res =
12265 container_of(entry, typeof(*res), entry);
12267 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12272 * Release a modify-header resource.
12275 * Pointer to Ethernet device.
12277 * Pointer to mlx5_flow_handle.
12280 * 1 while a reference on it exists, 0 when freed.
12283 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12284 struct mlx5_flow_handle *handle)
12286 struct mlx5_priv *priv = dev->data->dev_private;
12287 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12289 MLX5_ASSERT(entry->action);
12290 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12294 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12295 struct mlx5_cache_entry *entry)
12297 struct mlx5_dev_ctx_shared *sh = list->ctx;
12298 struct mlx5_flow_dv_port_id_action_resource *cache =
12299 container_of(entry, typeof(*cache), entry);
12301 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12302 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12306 * Release port ID action resource.
12309 * Pointer to Ethernet device.
12311 * Pointer to mlx5_flow_handle.
12314 * 1 while a reference on it exists, 0 when freed.
12317 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12320 struct mlx5_priv *priv = dev->data->dev_private;
12321 struct mlx5_flow_dv_port_id_action_resource *cache;
12323 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12326 MLX5_ASSERT(cache->action);
12327 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12332 * Release shared RSS action resource.
12335 * Pointer to Ethernet device.
12337 * Shared RSS action index.
12340 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12342 struct mlx5_priv *priv = dev->data->dev_private;
12343 struct mlx5_shared_action_rss *shared_rss;
12345 shared_rss = mlx5_ipool_get
12346 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12347 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12351 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12352 struct mlx5_cache_entry *entry)
12354 struct mlx5_dev_ctx_shared *sh = list->ctx;
12355 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12356 container_of(entry, typeof(*cache), entry);
12358 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12359 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12363 * Release push vlan action resource.
12366 * Pointer to Ethernet device.
12368 * Pointer to mlx5_flow_handle.
12371 * 1 while a reference on it exists, 0 when freed.
12374 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12375 struct mlx5_flow_handle *handle)
12377 struct mlx5_priv *priv = dev->data->dev_private;
12378 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12379 uint32_t idx = handle->dvh.rix_push_vlan;
12381 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12384 MLX5_ASSERT(cache->action);
12385 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12390 * Release the fate resource.
12393 * Pointer to Ethernet device.
12395 * Pointer to mlx5_flow_handle.
12398 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12399 struct mlx5_flow_handle *handle)
12401 if (!handle->rix_fate)
12403 switch (handle->fate_action) {
12404 case MLX5_FLOW_FATE_QUEUE:
12405 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12406 mlx5_hrxq_release(dev, handle->rix_hrxq);
12408 case MLX5_FLOW_FATE_JUMP:
12409 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12411 case MLX5_FLOW_FATE_PORT_ID:
12412 flow_dv_port_id_action_resource_release(dev,
12413 handle->rix_port_id_action);
12416 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12419 handle->rix_fate = 0;
12423 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12424 struct mlx5_cache_entry *entry)
12426 struct mlx5_flow_dv_sample_resource *cache_resource =
12427 container_of(entry, typeof(*cache_resource), entry);
12428 struct rte_eth_dev *dev = cache_resource->dev;
12429 struct mlx5_priv *priv = dev->data->dev_private;
12431 if (cache_resource->verbs_action)
12432 claim_zero(mlx5_flow_os_destroy_flow_action
12433 (cache_resource->verbs_action));
12434 if (cache_resource->normal_path_tbl)
12435 flow_dv_tbl_resource_release(MLX5_SH(dev),
12436 cache_resource->normal_path_tbl);
12437 flow_dv_sample_sub_actions_release(dev,
12438 &cache_resource->sample_idx);
12439 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12440 cache_resource->idx);
12441 DRV_LOG(DEBUG, "sample resource %p: removed",
12442 (void *)cache_resource);
12446 * Release an sample resource.
12449 * Pointer to Ethernet device.
12451 * Pointer to mlx5_flow_handle.
12454 * 1 while a reference on it exists, 0 when freed.
12457 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12458 struct mlx5_flow_handle *handle)
12460 struct mlx5_priv *priv = dev->data->dev_private;
12461 struct mlx5_flow_dv_sample_resource *cache_resource;
12463 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12464 handle->dvh.rix_sample);
12465 if (!cache_resource)
12467 MLX5_ASSERT(cache_resource->verbs_action);
12468 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12469 &cache_resource->entry);
12473 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12474 struct mlx5_cache_entry *entry)
12476 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12477 container_of(entry, typeof(*cache_resource), entry);
12478 struct rte_eth_dev *dev = cache_resource->dev;
12479 struct mlx5_priv *priv = dev->data->dev_private;
12482 MLX5_ASSERT(cache_resource->action);
12483 if (cache_resource->action)
12484 claim_zero(mlx5_flow_os_destroy_flow_action
12485 (cache_resource->action));
12486 for (; i < cache_resource->num_of_dest; i++)
12487 flow_dv_sample_sub_actions_release(dev,
12488 &cache_resource->sample_idx[i]);
12489 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12490 cache_resource->idx);
12491 DRV_LOG(DEBUG, "destination array resource %p: removed",
12492 (void *)cache_resource);
12496 * Release an destination array resource.
12499 * Pointer to Ethernet device.
12501 * Pointer to mlx5_flow_handle.
12504 * 1 while a reference on it exists, 0 when freed.
12507 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12508 struct mlx5_flow_handle *handle)
12510 struct mlx5_priv *priv = dev->data->dev_private;
12511 struct mlx5_flow_dv_dest_array_resource *cache;
12513 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12514 handle->dvh.rix_dest_array);
12517 MLX5_ASSERT(cache->action);
12518 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12523 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12525 struct mlx5_priv *priv = dev->data->dev_private;
12526 struct mlx5_dev_ctx_shared *sh = priv->sh;
12527 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12528 sh->geneve_tlv_option_resource;
12529 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12530 if (geneve_opt_resource) {
12531 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12532 __ATOMIC_RELAXED))) {
12533 claim_zero(mlx5_devx_cmd_destroy
12534 (geneve_opt_resource->obj));
12535 mlx5_free(sh->geneve_tlv_option_resource);
12536 sh->geneve_tlv_option_resource = NULL;
12539 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12543 * Remove the flow from the NIC but keeps it in memory.
12544 * Lock free, (mutex should be acquired by caller).
12547 * Pointer to Ethernet device.
12548 * @param[in, out] flow
12549 * Pointer to flow structure.
12552 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12554 struct mlx5_flow_handle *dh;
12555 uint32_t handle_idx;
12556 struct mlx5_priv *priv = dev->data->dev_private;
12560 handle_idx = flow->dev_handles;
12561 while (handle_idx) {
12562 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12566 if (dh->drv_flow) {
12567 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12568 dh->drv_flow = NULL;
12570 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12571 flow_dv_fate_resource_release(dev, dh);
12572 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12573 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12574 handle_idx = dh->next.next;
12579 * Remove the flow from the NIC and the memory.
12580 * Lock free, (mutex should be acquired by caller).
12583 * Pointer to the Ethernet device structure.
12584 * @param[in, out] flow
12585 * Pointer to flow structure.
12588 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12590 struct mlx5_flow_handle *dev_handle;
12591 struct mlx5_priv *priv = dev->data->dev_private;
12596 flow_dv_remove(dev, flow);
12597 if (flow->counter) {
12598 flow_dv_counter_free(dev, flow->counter);
12602 struct mlx5_flow_meter *fm;
12604 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12607 mlx5_flow_meter_detach(fm);
12611 flow_dv_aso_age_release(dev, flow->age);
12612 if (flow->geneve_tlv_option) {
12613 flow_dv_geneve_tlv_option_resource_release(dev);
12614 flow->geneve_tlv_option = 0;
12616 while (flow->dev_handles) {
12617 uint32_t tmp_idx = flow->dev_handles;
12619 dev_handle = mlx5_ipool_get(priv->sh->ipool
12620 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12623 flow->dev_handles = dev_handle->next.next;
12624 if (dev_handle->dvh.matcher)
12625 flow_dv_matcher_release(dev, dev_handle);
12626 if (dev_handle->dvh.rix_sample)
12627 flow_dv_sample_resource_release(dev, dev_handle);
12628 if (dev_handle->dvh.rix_dest_array)
12629 flow_dv_dest_array_resource_release(dev, dev_handle);
12630 if (dev_handle->dvh.rix_encap_decap)
12631 flow_dv_encap_decap_resource_release(dev,
12632 dev_handle->dvh.rix_encap_decap);
12633 if (dev_handle->dvh.modify_hdr)
12634 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12635 if (dev_handle->dvh.rix_push_vlan)
12636 flow_dv_push_vlan_action_resource_release(dev,
12638 if (dev_handle->dvh.rix_tag)
12639 flow_dv_tag_release(dev,
12640 dev_handle->dvh.rix_tag);
12641 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12642 flow_dv_fate_resource_release(dev, dev_handle);
12644 srss = dev_handle->rix_srss;
12645 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12649 flow_dv_shared_rss_action_release(dev, srss);
12653 * Release array of hash RX queue objects.
12657 * Pointer to the Ethernet device structure.
12658 * @param[in, out] hrxqs
12659 * Array of hash RX queue objects.
12662 * Total number of references to hash RX queue objects in *hrxqs* array
12663 * after this operation.
12666 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12667 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12672 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12673 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12683 * Release all hash RX queue objects representing shared RSS action.
12686 * Pointer to the Ethernet device structure.
12687 * @param[in, out] action
12688 * Shared RSS action to remove hash RX queue objects from.
12691 * Total number of references to hash RX queue objects stored in *action*
12692 * after this operation.
12693 * Expected to be 0 if no external references held.
12696 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12697 struct mlx5_shared_action_rss *shared_rss)
12699 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12703 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12706 * Only one hash value is available for one L3+L4 combination:
12708 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12709 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12710 * same slot in mlx5_rss_hash_fields.
12713 * Pointer to the shared action RSS conf.
12714 * @param[in, out] hash_field
12715 * hash_field variable needed to be adjusted.
12721 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12722 uint64_t *hash_field)
12724 uint64_t rss_types = rss->origin.types;
12726 switch (*hash_field & ~IBV_RX_HASH_INNER) {
12727 case MLX5_RSS_HASH_IPV4:
12728 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12729 *hash_field &= ~MLX5_RSS_HASH_IPV4;
12730 if (rss_types & ETH_RSS_L3_DST_ONLY)
12731 *hash_field |= IBV_RX_HASH_DST_IPV4;
12732 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12733 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12735 *hash_field |= MLX5_RSS_HASH_IPV4;
12738 case MLX5_RSS_HASH_IPV6:
12739 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12740 *hash_field &= ~MLX5_RSS_HASH_IPV6;
12741 if (rss_types & ETH_RSS_L3_DST_ONLY)
12742 *hash_field |= IBV_RX_HASH_DST_IPV6;
12743 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12744 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12746 *hash_field |= MLX5_RSS_HASH_IPV6;
12749 case MLX5_RSS_HASH_IPV4_UDP:
12750 /* fall-through. */
12751 case MLX5_RSS_HASH_IPV6_UDP:
12752 if (rss_types & ETH_RSS_UDP) {
12753 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12754 if (rss_types & ETH_RSS_L4_DST_ONLY)
12755 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12756 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12757 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12759 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12762 case MLX5_RSS_HASH_IPV4_TCP:
12763 /* fall-through. */
12764 case MLX5_RSS_HASH_IPV6_TCP:
12765 if (rss_types & ETH_RSS_TCP) {
12766 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12767 if (rss_types & ETH_RSS_L4_DST_ONLY)
12768 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12769 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12770 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12772 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12781 * Setup shared RSS action.
12782 * Prepare set of hash RX queue objects sufficient to handle all valid
12783 * hash_fields combinations (see enum ibv_rx_hash_fields).
12786 * Pointer to the Ethernet device structure.
12787 * @param[in] action_idx
12788 * Shared RSS action ipool index.
12789 * @param[in, out] action
12790 * Partially initialized shared RSS action.
12791 * @param[out] error
12792 * Perform verbose error reporting if not NULL. Initialized in case of
12796 * 0 on success, otherwise negative errno value.
12799 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12800 uint32_t action_idx,
12801 struct mlx5_shared_action_rss *shared_rss,
12802 struct rte_flow_error *error)
12804 struct mlx5_flow_rss_desc rss_desc = { 0 };
12808 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12809 return rte_flow_error_set(error, rte_errno,
12810 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12811 "cannot setup indirection table");
12813 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12814 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12815 rss_desc.const_q = shared_rss->origin.queue;
12816 rss_desc.queue_num = shared_rss->origin.queue_num;
12817 /* Set non-zero value to indicate a shared RSS. */
12818 rss_desc.shared_rss = action_idx;
12819 rss_desc.ind_tbl = shared_rss->ind_tbl;
12820 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12822 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12825 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12826 if (shared_rss->origin.level > 1) {
12827 hash_fields |= IBV_RX_HASH_INNER;
12830 rss_desc.tunnel = tunnel;
12831 rss_desc.hash_fields = hash_fields;
12832 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12836 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12837 "cannot get hash queue");
12838 goto error_hrxq_new;
12840 err = __flow_dv_action_rss_hrxq_set
12841 (shared_rss, hash_fields, hrxq_idx);
12847 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12848 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12849 shared_rss->ind_tbl = NULL;
12855 * Create shared RSS action.
12858 * Pointer to the Ethernet device structure.
12860 * Shared action configuration.
12862 * RSS action specification used to create shared action.
12863 * @param[out] error
12864 * Perform verbose error reporting if not NULL. Initialized in case of
12868 * A valid shared action ID in case of success, 0 otherwise and
12869 * rte_errno is set.
12872 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12873 const struct rte_flow_shared_action_conf *conf,
12874 const struct rte_flow_action_rss *rss,
12875 struct rte_flow_error *error)
12877 struct mlx5_priv *priv = dev->data->dev_private;
12878 struct mlx5_shared_action_rss *shared_rss = NULL;
12879 void *queue = NULL;
12880 struct rte_flow_action_rss *origin;
12881 const uint8_t *rss_key;
12882 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12885 RTE_SET_USED(conf);
12886 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12888 shared_rss = mlx5_ipool_zmalloc
12889 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12890 if (!shared_rss || !queue) {
12891 rte_flow_error_set(error, ENOMEM,
12892 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12893 "cannot allocate resource memory");
12894 goto error_rss_init;
12896 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12897 rte_flow_error_set(error, E2BIG,
12898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12899 "rss action number out of range");
12900 goto error_rss_init;
12902 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12903 sizeof(*shared_rss->ind_tbl),
12905 if (!shared_rss->ind_tbl) {
12906 rte_flow_error_set(error, ENOMEM,
12907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12908 "cannot allocate resource memory");
12909 goto error_rss_init;
12911 memcpy(queue, rss->queue, queue_size);
12912 shared_rss->ind_tbl->queues = queue;
12913 shared_rss->ind_tbl->queues_n = rss->queue_num;
12914 origin = &shared_rss->origin;
12915 origin->func = rss->func;
12916 origin->level = rss->level;
12917 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12918 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12919 /* NULL RSS key indicates default RSS key. */
12920 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12921 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12922 origin->key = &shared_rss->key[0];
12923 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12924 origin->queue = queue;
12925 origin->queue_num = rss->queue_num;
12926 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12927 goto error_rss_init;
12928 rte_spinlock_init(&shared_rss->action_rss_sl);
12929 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12930 rte_spinlock_lock(&priv->shared_act_sl);
12931 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12932 &priv->rss_shared_actions, idx, shared_rss, next);
12933 rte_spinlock_unlock(&priv->shared_act_sl);
12937 if (shared_rss->ind_tbl)
12938 mlx5_free(shared_rss->ind_tbl);
12939 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12948 * Destroy the shared RSS action.
12949 * Release related hash RX queue objects.
12952 * Pointer to the Ethernet device structure.
12954 * The shared RSS action object ID to be removed.
12955 * @param[out] error
12956 * Perform verbose error reporting if not NULL. Initialized in case of
12960 * 0 on success, otherwise negative errno value.
12963 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12964 struct rte_flow_error *error)
12966 struct mlx5_priv *priv = dev->data->dev_private;
12967 struct mlx5_shared_action_rss *shared_rss =
12968 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12969 uint32_t old_refcnt = 1;
12971 uint16_t *queue = NULL;
12974 return rte_flow_error_set(error, EINVAL,
12975 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12976 "invalid shared action");
12977 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12979 return rte_flow_error_set(error, EBUSY,
12980 RTE_FLOW_ERROR_TYPE_ACTION,
12982 "shared rss hrxq has references");
12983 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12984 0, 0, __ATOMIC_ACQUIRE,
12986 return rte_flow_error_set(error, EBUSY,
12987 RTE_FLOW_ERROR_TYPE_ACTION,
12989 "shared rss has references");
12990 queue = shared_rss->ind_tbl->queues;
12991 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12993 return rte_flow_error_set(error, EBUSY,
12994 RTE_FLOW_ERROR_TYPE_ACTION,
12996 "shared rss indirection table has"
12999 rte_spinlock_lock(&priv->shared_act_sl);
13000 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13001 &priv->rss_shared_actions, idx, shared_rss, next);
13002 rte_spinlock_unlock(&priv->shared_act_sl);
13003 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13009 * Create shared action, lock free,
13010 * (mutex should be acquired by caller).
13011 * Dispatcher for action type specific call.
13014 * Pointer to the Ethernet device structure.
13016 * Shared action configuration.
13017 * @param[in] action
13018 * Action specification used to create shared action.
13019 * @param[out] error
13020 * Perform verbose error reporting if not NULL. Initialized in case of
13024 * A valid shared action handle in case of success, NULL otherwise and
13025 * rte_errno is set.
13027 static struct rte_flow_shared_action *
13028 flow_dv_action_create(struct rte_eth_dev *dev,
13029 const struct rte_flow_shared_action_conf *conf,
13030 const struct rte_flow_action *action,
13031 struct rte_flow_error *err)
13036 switch (action->type) {
13037 case RTE_FLOW_ACTION_TYPE_RSS:
13038 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13039 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13040 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13042 case RTE_FLOW_ACTION_TYPE_AGE:
13043 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13044 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13045 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13047 struct mlx5_aso_age_action *aso_age =
13048 flow_aso_age_get_by_idx(dev, ret);
13050 if (!aso_age->age_params.context)
13051 aso_age->age_params.context =
13052 (void *)(uintptr_t)idx;
13056 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13057 NULL, "action type not supported");
13060 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13064 * Destroy the shared action.
13065 * Release action related resources on the NIC and the memory.
13066 * Lock free, (mutex should be acquired by caller).
13067 * Dispatcher for action type specific call.
13070 * Pointer to the Ethernet device structure.
13071 * @param[in] action
13072 * The shared action object to be removed.
13073 * @param[out] error
13074 * Perform verbose error reporting if not NULL. Initialized in case of
13078 * 0 on success, otherwise negative errno value.
13081 flow_dv_action_destroy(struct rte_eth_dev *dev,
13082 struct rte_flow_shared_action *action,
13083 struct rte_flow_error *error)
13085 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13086 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13087 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13091 case MLX5_SHARED_ACTION_TYPE_RSS:
13092 return __flow_dv_action_rss_release(dev, idx, error);
13093 case MLX5_SHARED_ACTION_TYPE_AGE:
13094 ret = flow_dv_aso_age_release(dev, idx);
13097 * In this case, the last flow has a reference will
13098 * actually release the age action.
13100 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13101 " released with references %d.", idx, ret);
13104 return rte_flow_error_set(error, ENOTSUP,
13105 RTE_FLOW_ERROR_TYPE_ACTION,
13107 "action type not supported");
13112 * Updates in place shared RSS action configuration.
13115 * Pointer to the Ethernet device structure.
13117 * The shared RSS action object ID to be updated.
13118 * @param[in] action_conf
13119 * RSS action specification used to modify *shared_rss*.
13120 * @param[out] error
13121 * Perform verbose error reporting if not NULL. Initialized in case of
13125 * 0 on success, otherwise negative errno value.
13126 * @note: currently only support update of RSS queues.
13129 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13130 const struct rte_flow_action_rss *action_conf,
13131 struct rte_flow_error *error)
13133 struct mlx5_priv *priv = dev->data->dev_private;
13134 struct mlx5_shared_action_rss *shared_rss =
13135 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13137 void *queue = NULL;
13138 uint16_t *queue_old = NULL;
13139 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13142 return rte_flow_error_set(error, EINVAL,
13143 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13144 "invalid shared action to update");
13145 if (priv->obj_ops.ind_table_modify == NULL)
13146 return rte_flow_error_set(error, ENOTSUP,
13147 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13148 "cannot modify indirection table");
13149 queue = mlx5_malloc(MLX5_MEM_ZERO,
13150 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13153 return rte_flow_error_set(error, ENOMEM,
13154 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13156 "cannot allocate resource memory");
13157 memcpy(queue, action_conf->queue, queue_size);
13158 MLX5_ASSERT(shared_rss->ind_tbl);
13159 rte_spinlock_lock(&shared_rss->action_rss_sl);
13160 queue_old = shared_rss->ind_tbl->queues;
13161 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13162 queue, action_conf->queue_num, true);
13165 ret = rte_flow_error_set(error, rte_errno,
13166 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13167 "cannot update indirection table");
13169 mlx5_free(queue_old);
13170 shared_rss->origin.queue = queue;
13171 shared_rss->origin.queue_num = action_conf->queue_num;
13173 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13178 * Updates in place shared action configuration, lock free,
13179 * (mutex should be acquired by caller).
13182 * Pointer to the Ethernet device structure.
13183 * @param[in] action
13184 * The shared action object to be updated.
13185 * @param[in] action_conf
13186 * Action specification used to modify *action*.
13187 * *action_conf* should be of type correlating with type of the *action*,
13188 * otherwise considered as invalid.
13189 * @param[out] error
13190 * Perform verbose error reporting if not NULL. Initialized in case of
13194 * 0 on success, otherwise negative errno value.
13197 flow_dv_action_update(struct rte_eth_dev *dev,
13198 struct rte_flow_shared_action *action,
13199 const void *action_conf,
13200 struct rte_flow_error *err)
13202 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13203 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13204 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13207 case MLX5_SHARED_ACTION_TYPE_RSS:
13208 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13210 return rte_flow_error_set(err, ENOTSUP,
13211 RTE_FLOW_ERROR_TYPE_ACTION,
13213 "action type update not supported");
13218 flow_dv_action_query(struct rte_eth_dev *dev,
13219 const struct rte_flow_shared_action *action, void *data,
13220 struct rte_flow_error *error)
13222 struct mlx5_age_param *age_param;
13223 struct rte_flow_query_age *resp;
13224 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13225 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13226 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13229 case MLX5_SHARED_ACTION_TYPE_AGE:
13230 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13232 resp->aged = __atomic_load_n(&age_param->state,
13233 __ATOMIC_RELAXED) == AGE_TMOUT ?
13235 resp->sec_since_last_hit_valid = !resp->aged;
13236 if (resp->sec_since_last_hit_valid)
13237 resp->sec_since_last_hit = __atomic_load_n
13238 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13241 return rte_flow_error_set(error, ENOTSUP,
13242 RTE_FLOW_ERROR_TYPE_ACTION,
13244 "action type query not supported");
13249 * Query a dv flow rule for its statistics via devx.
13252 * Pointer to Ethernet device.
13254 * Pointer to the sub flow.
13256 * data retrieved by the query.
13257 * @param[out] error
13258 * Perform verbose error reporting if not NULL.
13261 * 0 on success, a negative errno value otherwise and rte_errno is set.
13264 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13265 void *data, struct rte_flow_error *error)
13267 struct mlx5_priv *priv = dev->data->dev_private;
13268 struct rte_flow_query_count *qc = data;
13270 if (!priv->config.devx)
13271 return rte_flow_error_set(error, ENOTSUP,
13272 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13274 "counters are not supported");
13275 if (flow->counter) {
13276 uint64_t pkts, bytes;
13277 struct mlx5_flow_counter *cnt;
13279 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13281 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13285 return rte_flow_error_set(error, -err,
13286 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13287 NULL, "cannot read counters");
13290 qc->hits = pkts - cnt->hits;
13291 qc->bytes = bytes - cnt->bytes;
13294 cnt->bytes = bytes;
13298 return rte_flow_error_set(error, EINVAL,
13299 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13301 "counters are not available");
13305 * Query a flow rule AGE action for aging information.
13308 * Pointer to Ethernet device.
13310 * Pointer to the sub flow.
13312 * data retrieved by the query.
13313 * @param[out] error
13314 * Perform verbose error reporting if not NULL.
13317 * 0 on success, a negative errno value otherwise and rte_errno is set.
13320 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13321 void *data, struct rte_flow_error *error)
13323 struct rte_flow_query_age *resp = data;
13324 struct mlx5_age_param *age_param;
13327 struct mlx5_aso_age_action *act =
13328 flow_aso_age_get_by_idx(dev, flow->age);
13330 age_param = &act->age_params;
13331 } else if (flow->counter) {
13332 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13334 if (!age_param || !age_param->timeout)
13335 return rte_flow_error_set
13337 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13338 NULL, "cannot read age data");
13340 return rte_flow_error_set(error, EINVAL,
13341 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13342 NULL, "age data not available");
13344 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13346 resp->sec_since_last_hit_valid = !resp->aged;
13347 if (resp->sec_since_last_hit_valid)
13348 resp->sec_since_last_hit = __atomic_load_n
13349 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13356 * @see rte_flow_query()
13357 * @see rte_flow_ops
13360 flow_dv_query(struct rte_eth_dev *dev,
13361 struct rte_flow *flow __rte_unused,
13362 const struct rte_flow_action *actions __rte_unused,
13363 void *data __rte_unused,
13364 struct rte_flow_error *error __rte_unused)
13368 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13369 switch (actions->type) {
13370 case RTE_FLOW_ACTION_TYPE_VOID:
13372 case RTE_FLOW_ACTION_TYPE_COUNT:
13373 ret = flow_dv_query_count(dev, flow, data, error);
13375 case RTE_FLOW_ACTION_TYPE_AGE:
13376 ret = flow_dv_query_age(dev, flow, data, error);
13379 return rte_flow_error_set(error, ENOTSUP,
13380 RTE_FLOW_ERROR_TYPE_ACTION,
13382 "action not supported");
13389 * Destroy the meter table set.
13390 * Lock free, (mutex should be acquired by caller).
13393 * Pointer to Ethernet device.
13395 * Pointer to the meter table set.
13401 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13402 struct mlx5_meter_domains_infos *tbl)
13404 struct mlx5_priv *priv = dev->data->dev_private;
13405 struct mlx5_meter_domains_infos *mtd =
13406 (struct mlx5_meter_domains_infos *)tbl;
13408 if (!mtd || !priv->config.dv_flow_en)
13410 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13411 claim_zero(mlx5_flow_os_destroy_flow
13412 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13413 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13414 claim_zero(mlx5_flow_os_destroy_flow
13415 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13416 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13417 claim_zero(mlx5_flow_os_destroy_flow
13418 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13419 if (mtd->egress.color_matcher)
13420 claim_zero(mlx5_flow_os_destroy_flow_matcher
13421 (mtd->egress.color_matcher));
13422 if (mtd->egress.any_matcher)
13423 claim_zero(mlx5_flow_os_destroy_flow_matcher
13424 (mtd->egress.any_matcher));
13425 if (mtd->egress.tbl)
13426 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13427 if (mtd->egress.sfx_tbl)
13428 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13429 if (mtd->ingress.color_matcher)
13430 claim_zero(mlx5_flow_os_destroy_flow_matcher
13431 (mtd->ingress.color_matcher));
13432 if (mtd->ingress.any_matcher)
13433 claim_zero(mlx5_flow_os_destroy_flow_matcher
13434 (mtd->ingress.any_matcher));
13435 if (mtd->ingress.tbl)
13436 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13437 if (mtd->ingress.sfx_tbl)
13438 flow_dv_tbl_resource_release(MLX5_SH(dev),
13439 mtd->ingress.sfx_tbl);
13440 if (mtd->transfer.color_matcher)
13441 claim_zero(mlx5_flow_os_destroy_flow_matcher
13442 (mtd->transfer.color_matcher));
13443 if (mtd->transfer.any_matcher)
13444 claim_zero(mlx5_flow_os_destroy_flow_matcher
13445 (mtd->transfer.any_matcher));
13446 if (mtd->transfer.tbl)
13447 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13448 if (mtd->transfer.sfx_tbl)
13449 flow_dv_tbl_resource_release(MLX5_SH(dev),
13450 mtd->transfer.sfx_tbl);
13451 if (mtd->drop_actn)
13452 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13457 /* Number of meter flow actions, count and jump or count and drop. */
13458 #define METER_ACTIONS 2
13461 * Create specify domain meter table and suffix table.
13464 * Pointer to Ethernet device.
13465 * @param[in,out] mtb
13466 * Pointer to DV meter table set.
13467 * @param[in] egress
13469 * @param[in] transfer
13471 * @param[in] color_reg_c_idx
13472 * Reg C index for color match.
13475 * 0 on success, -1 otherwise and rte_errno is set.
13478 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13479 struct mlx5_meter_domains_infos *mtb,
13480 uint8_t egress, uint8_t transfer,
13481 uint32_t color_reg_c_idx)
13483 struct mlx5_priv *priv = dev->data->dev_private;
13484 struct mlx5_dev_ctx_shared *sh = priv->sh;
13485 struct mlx5_flow_dv_match_params mask = {
13486 .size = sizeof(mask.buf),
13488 struct mlx5_flow_dv_match_params value = {
13489 .size = sizeof(value.buf),
13491 struct mlx5dv_flow_matcher_attr dv_attr = {
13492 .type = IBV_FLOW_ATTR_NORMAL,
13494 .match_criteria_enable = 0,
13495 .match_mask = (void *)&mask,
13497 void *actions[METER_ACTIONS];
13498 struct mlx5_meter_domain_info *dtb;
13499 struct rte_flow_error error;
13504 dtb = &mtb->transfer;
13506 dtb = &mtb->egress;
13508 dtb = &mtb->ingress;
13509 /* Create the meter table with METER level. */
13510 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13511 egress, transfer, false, NULL, 0,
13514 DRV_LOG(ERR, "Failed to create meter policer table.");
13517 /* Create the meter suffix table with SUFFIX level. */
13518 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13519 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13520 egress, transfer, false, NULL, 0,
13522 if (!dtb->sfx_tbl) {
13523 DRV_LOG(ERR, "Failed to create meter suffix table.");
13526 /* Create matchers, Any and Color. */
13527 dv_attr.priority = 3;
13528 dv_attr.match_criteria_enable = 0;
13529 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13530 &dtb->any_matcher);
13532 DRV_LOG(ERR, "Failed to create meter"
13533 " policer default matcher.");
13536 dv_attr.priority = 0;
13537 dv_attr.match_criteria_enable =
13538 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13539 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13540 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13541 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13542 &dtb->color_matcher);
13544 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13547 if (mtb->count_actns[RTE_MTR_DROPPED])
13548 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13549 actions[i++] = mtb->drop_actn;
13550 /* Default rule: lowest priority, match any, actions: drop. */
13551 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13553 &dtb->policer_rules[RTE_MTR_DROPPED]);
13555 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13564 * Create the needed meter and suffix tables.
13565 * Lock free, (mutex should be acquired by caller).
13568 * Pointer to Ethernet device.
13570 * Pointer to the flow meter.
13573 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13575 static struct mlx5_meter_domains_infos *
13576 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13577 const struct mlx5_flow_meter *fm)
13579 struct mlx5_priv *priv = dev->data->dev_private;
13580 struct mlx5_meter_domains_infos *mtb;
13584 if (!priv->mtr_en) {
13585 rte_errno = ENOTSUP;
13588 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13590 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13593 /* Create meter count actions */
13594 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13595 struct mlx5_flow_counter *cnt;
13596 if (!fm->policer_stats.cnt[i])
13598 cnt = flow_dv_counter_get_by_idx(dev,
13599 fm->policer_stats.cnt[i], NULL);
13600 mtb->count_actns[i] = cnt->action;
13602 /* Create drop action. */
13603 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13605 DRV_LOG(ERR, "Failed to create drop action.");
13608 /* Egress meter table. */
13609 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13611 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13614 /* Ingress meter table. */
13615 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13617 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13620 /* FDB meter table. */
13621 if (priv->config.dv_esw_en) {
13622 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13623 priv->mtr_color_reg);
13625 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13631 flow_dv_destroy_mtr_tbl(dev, mtb);
13636 * Destroy domain policer rule.
13639 * Pointer to domain table.
13642 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13646 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13647 if (dt->policer_rules[i]) {
13648 claim_zero(mlx5_flow_os_destroy_flow
13649 (dt->policer_rules[i]));
13650 dt->policer_rules[i] = NULL;
13653 if (dt->jump_actn) {
13654 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13655 dt->jump_actn = NULL;
13660 * Destroy policer rules.
13663 * Pointer to Ethernet device.
13665 * Pointer to flow meter structure.
13667 * Pointer to flow attributes.
13673 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13674 const struct mlx5_flow_meter *fm,
13675 const struct rte_flow_attr *attr)
13677 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13682 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13684 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13685 if (attr->transfer)
13686 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13691 * Create specify domain meter policer rule.
13694 * Pointer to flow meter structure.
13696 * Pointer to DV meter table set.
13697 * @param[in] mtr_reg_c
13698 * Color match REG_C.
13701 * 0 on success, -1 otherwise.
13704 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13705 struct mlx5_meter_domain_info *dtb,
13708 struct mlx5_flow_dv_match_params matcher = {
13709 .size = sizeof(matcher.buf),
13711 struct mlx5_flow_dv_match_params value = {
13712 .size = sizeof(value.buf),
13714 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13715 void *actions[METER_ACTIONS];
13719 /* Create jump action. */
13720 if (!dtb->jump_actn)
13721 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13722 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13724 DRV_LOG(ERR, "Failed to create policer jump action.");
13727 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13730 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13731 rte_col_2_mlx5_col(i), UINT8_MAX);
13732 if (mtb->count_actns[i])
13733 actions[j++] = mtb->count_actns[i];
13734 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13735 actions[j++] = mtb->drop_actn;
13737 actions[j++] = dtb->jump_actn;
13738 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13739 (void *)&value, j, actions,
13740 &dtb->policer_rules[i]);
13742 DRV_LOG(ERR, "Failed to create policer rule.");
13753 * Create policer rules.
13756 * Pointer to Ethernet device.
13758 * Pointer to flow meter structure.
13760 * Pointer to flow attributes.
13763 * 0 on success, -1 otherwise.
13766 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13767 struct mlx5_flow_meter *fm,
13768 const struct rte_flow_attr *attr)
13770 struct mlx5_priv *priv = dev->data->dev_private;
13771 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13774 if (attr->egress) {
13775 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13776 priv->mtr_color_reg);
13778 DRV_LOG(ERR, "Failed to create egress policer.");
13782 if (attr->ingress) {
13783 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13784 priv->mtr_color_reg);
13786 DRV_LOG(ERR, "Failed to create ingress policer.");
13790 if (attr->transfer) {
13791 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13792 priv->mtr_color_reg);
13794 DRV_LOG(ERR, "Failed to create transfer policer.");
13800 flow_dv_destroy_policer_rules(dev, fm, attr);
13805 * Validate the batch counter support in root table.
13807 * Create a simple flow with invalid counter and drop action on root table to
13808 * validate if batch counter with offset on root table is supported or not.
13811 * Pointer to rte_eth_dev structure.
13814 * 0 on success, a negative errno value otherwise and rte_errno is set.
13817 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13819 struct mlx5_priv *priv = dev->data->dev_private;
13820 struct mlx5_dev_ctx_shared *sh = priv->sh;
13821 struct mlx5_flow_dv_match_params mask = {
13822 .size = sizeof(mask.buf),
13824 struct mlx5_flow_dv_match_params value = {
13825 .size = sizeof(value.buf),
13827 struct mlx5dv_flow_matcher_attr dv_attr = {
13828 .type = IBV_FLOW_ATTR_NORMAL,
13830 .match_criteria_enable = 0,
13831 .match_mask = (void *)&mask,
13833 void *actions[2] = { 0 };
13834 struct mlx5_flow_tbl_resource *tbl = NULL;
13835 struct mlx5_devx_obj *dcs = NULL;
13836 void *matcher = NULL;
13840 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13843 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13846 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13850 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13851 priv->drop_queue.hrxq->action;
13852 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13853 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13857 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13861 * If batch counter with offset is not supported, the driver will not
13862 * validate the invalid offset value, flow create should success.
13863 * In this case, it means batch counter is not supported in root table.
13865 * Otherwise, if flow create is failed, counter offset is supported.
13868 DRV_LOG(INFO, "Batch counter is not supported in root "
13869 "table. Switch to fallback mode.");
13870 rte_errno = ENOTSUP;
13872 claim_zero(mlx5_flow_os_destroy_flow(flow));
13874 /* Check matcher to make sure validate fail at flow create. */
13875 if (!matcher || (matcher && errno != EINVAL))
13876 DRV_LOG(ERR, "Unexpected error in counter offset "
13877 "support detection");
13881 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13883 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13885 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13887 claim_zero(mlx5_devx_cmd_destroy(dcs));
13892 * Query a devx counter.
13895 * Pointer to the Ethernet device structure.
13897 * Index to the flow counter.
13899 * Set to clear the counter statistics.
13901 * The statistics value of packets.
13902 * @param[out] bytes
13903 * The statistics value of bytes.
13906 * 0 on success, otherwise return -1.
13909 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13910 uint64_t *pkts, uint64_t *bytes)
13912 struct mlx5_priv *priv = dev->data->dev_private;
13913 struct mlx5_flow_counter *cnt;
13914 uint64_t inn_pkts, inn_bytes;
13917 if (!priv->config.devx)
13920 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13923 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13924 *pkts = inn_pkts - cnt->hits;
13925 *bytes = inn_bytes - cnt->bytes;
13927 cnt->hits = inn_pkts;
13928 cnt->bytes = inn_bytes;
13934 * Get aged-out flows.
13937 * Pointer to the Ethernet device structure.
13938 * @param[in] context
13939 * The address of an array of pointers to the aged-out flows contexts.
13940 * @param[in] nb_contexts
13941 * The length of context array pointers.
13942 * @param[out] error
13943 * Perform verbose error reporting if not NULL. Initialized in case of
13947 * how many contexts get in success, otherwise negative errno value.
13948 * if nb_contexts is 0, return the amount of all aged contexts.
13949 * if nb_contexts is not 0 , return the amount of aged flows reported
13950 * in the context array.
13951 * @note: only stub for now
13954 flow_get_aged_flows(struct rte_eth_dev *dev,
13956 uint32_t nb_contexts,
13957 struct rte_flow_error *error)
13959 struct mlx5_priv *priv = dev->data->dev_private;
13960 struct mlx5_age_info *age_info;
13961 struct mlx5_age_param *age_param;
13962 struct mlx5_flow_counter *counter;
13963 struct mlx5_aso_age_action *act;
13966 if (nb_contexts && !context)
13967 return rte_flow_error_set(error, EINVAL,
13968 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13969 NULL, "empty context");
13970 age_info = GET_PORT_AGE_INFO(priv);
13971 rte_spinlock_lock(&age_info->aged_sl);
13972 LIST_FOREACH(act, &age_info->aged_aso, next) {
13975 context[nb_flows - 1] =
13976 act->age_params.context;
13977 if (!(--nb_contexts))
13981 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13984 age_param = MLX5_CNT_TO_AGE(counter);
13985 context[nb_flows - 1] = age_param->context;
13986 if (!(--nb_contexts))
13990 rte_spinlock_unlock(&age_info->aged_sl);
13991 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13996 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13999 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14001 return flow_dv_counter_alloc(dev, 0);
14005 * Validate shared action.
14006 * Dispatcher for action type specific validation.
14009 * Pointer to the Ethernet device structure.
14011 * Shared action configuration.
14012 * @param[in] action
14013 * The shared action object to validate.
14014 * @param[out] error
14015 * Perform verbose error reporting if not NULL. Initialized in case of
14019 * 0 on success, otherwise negative errno value.
14022 flow_dv_action_validate(struct rte_eth_dev *dev,
14023 const struct rte_flow_shared_action_conf *conf,
14024 const struct rte_flow_action *action,
14025 struct rte_flow_error *err)
14027 struct mlx5_priv *priv = dev->data->dev_private;
14029 RTE_SET_USED(conf);
14030 switch (action->type) {
14031 case RTE_FLOW_ACTION_TYPE_RSS:
14033 * priv->obj_ops is set according to driver capabilities.
14034 * When DevX capabilities are
14035 * sufficient, it is set to devx_obj_ops.
14036 * Otherwise, it is set to ibv_obj_ops.
14037 * ibv_obj_ops doesn't support ind_table_modify operation.
14038 * In this case the shared RSS action can't be used.
14040 if (priv->obj_ops.ind_table_modify == NULL)
14041 return rte_flow_error_set
14043 RTE_FLOW_ERROR_TYPE_ACTION,
14045 "shared RSS action not supported");
14046 return mlx5_validate_action_rss(dev, action, err);
14047 case RTE_FLOW_ACTION_TYPE_AGE:
14048 if (!priv->sh->aso_age_mng)
14049 return rte_flow_error_set(err, ENOTSUP,
14050 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14052 "shared age action not supported");
14053 return flow_dv_validate_action_age(0, action, dev, err);
14055 return rte_flow_error_set(err, ENOTSUP,
14056 RTE_FLOW_ERROR_TYPE_ACTION,
14058 "action type not supported");
14063 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14065 struct mlx5_priv *priv = dev->data->dev_private;
14068 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14069 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14074 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14075 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14079 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14080 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14087 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14088 .validate = flow_dv_validate,
14089 .prepare = flow_dv_prepare,
14090 .translate = flow_dv_translate,
14091 .apply = flow_dv_apply,
14092 .remove = flow_dv_remove,
14093 .destroy = flow_dv_destroy,
14094 .query = flow_dv_query,
14095 .create_mtr_tbls = flow_dv_create_mtr_tbl,
14096 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14097 .create_policer_rules = flow_dv_create_policer_rules,
14098 .destroy_policer_rules = flow_dv_destroy_policer_rules,
14099 .counter_alloc = flow_dv_counter_allocate,
14100 .counter_free = flow_dv_counter_free,
14101 .counter_query = flow_dv_counter_query,
14102 .get_aged_flows = flow_get_aged_flows,
14103 .action_validate = flow_dv_action_validate,
14104 .action_create = flow_dv_action_create,
14105 .action_destroy = flow_dv_action_destroy,
14106 .action_update = flow_dv_action_update,
14107 .action_query = flow_dv_action_query,
14108 .sync_domain = flow_dv_sync_domain,
14111 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */