1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include "mlx5_defs.h"
33 #include "mlx5_glue.h"
34 #include "mlx5_flow.h"
36 #include "mlx5_rxtx.h"
38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 * Initialize flow attributes structure according to flow items' types.
77 * Pointer to item specification.
79 * Pointer to flow attributes structure.
82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
84 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
86 case RTE_FLOW_ITEM_TYPE_IPV4:
89 case RTE_FLOW_ITEM_TYPE_IPV6:
92 case RTE_FLOW_ITEM_TYPE_UDP:
95 case RTE_FLOW_ITEM_TYPE_TCP:
105 struct field_modify_info {
106 uint32_t size; /* Size of field in protocol header, in bytes. */
107 uint32_t offset; /* Offset of field in protocol header, in bytes. */
108 enum mlx5_modification_field id;
111 struct field_modify_info modify_eth[] = {
112 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
113 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
114 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
115 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
119 struct field_modify_info modify_vlan_out_first_vid[] = {
120 /* Size in bits !!! */
121 {12, 0, MLX5_MODI_OUT_FIRST_VID},
125 struct field_modify_info modify_ipv4[] = {
126 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
127 {4, 12, MLX5_MODI_OUT_SIPV4},
128 {4, 16, MLX5_MODI_OUT_DIPV4},
132 struct field_modify_info modify_ipv6[] = {
133 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
134 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
135 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
136 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
137 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
138 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
139 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
140 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
141 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
145 struct field_modify_info modify_udp[] = {
146 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
147 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
151 struct field_modify_info modify_tcp[] = {
152 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
153 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
154 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
155 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
161 uint8_t next_protocol, uint64_t *item_flags,
164 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
165 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
166 if (next_protocol == IPPROTO_IPIP) {
167 *item_flags |= MLX5_FLOW_LAYER_IPIP;
170 if (next_protocol == IPPROTO_IPV6) {
171 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
177 * Acquire the synchronizing object to protect multithreaded access
178 * to shared dv context. Lock occurs only if context is actually
179 * shared, i.e. we have multiport IB device and representors are
183 * Pointer to the rte_eth_dev structure.
186 flow_d_shared_lock(struct rte_eth_dev *dev)
188 struct mlx5_priv *priv = dev->data->dev_private;
189 struct mlx5_ibv_shared *sh = priv->sh;
191 if (sh->dv_refcnt > 1) {
194 ret = pthread_mutex_lock(&sh->dv_mutex);
201 flow_d_shared_unlock(struct rte_eth_dev *dev)
203 struct mlx5_priv *priv = dev->data->dev_private;
204 struct mlx5_ibv_shared *sh = priv->sh;
206 if (sh->dv_refcnt > 1) {
209 ret = pthread_mutex_unlock(&sh->dv_mutex);
216 * Convert modify-header action to DV specification.
219 * Pointer to item specification.
221 * Pointer to field modification information.
222 * @param[in,out] resource
223 * Pointer to the modify-header resource.
225 * Type of modification.
227 * Pointer to the error structure.
230 * 0 on success, a negative errno value otherwise and rte_errno is set.
233 flow_dv_convert_modify_action(struct rte_flow_item *item,
234 struct field_modify_info *field,
235 struct mlx5_flow_dv_modify_hdr_resource *resource,
237 struct rte_flow_error *error)
239 uint32_t i = resource->actions_num;
240 struct mlx5_modification_cmd *actions = resource->actions;
241 const uint8_t *spec = item->spec;
242 const uint8_t *mask = item->mask;
245 while (field->size) {
247 /* Generate modify command for each mask segment. */
248 memcpy(&set, &mask[field->offset], field->size);
250 if (i >= MLX5_MODIFY_NUM)
251 return rte_flow_error_set(error, EINVAL,
252 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
253 "too many items to modify");
254 actions[i].action_type = type;
255 actions[i].field = field->id;
256 actions[i].length = field->size ==
257 4 ? 0 : field->size * 8;
258 rte_memcpy(&actions[i].data[4 - field->size],
259 &spec[field->offset], field->size);
260 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
263 if (resource->actions_num != i)
264 resource->actions_num = i;
267 if (!resource->actions_num)
268 return rte_flow_error_set(error, EINVAL,
269 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
270 "invalid modification flow item");
275 * Convert modify-header set IPv4 address action to DV specification.
277 * @param[in,out] resource
278 * Pointer to the modify-header resource.
280 * Pointer to action specification.
282 * Pointer to the error structure.
285 * 0 on success, a negative errno value otherwise and rte_errno is set.
288 flow_dv_convert_action_modify_ipv4
289 (struct mlx5_flow_dv_modify_hdr_resource *resource,
290 const struct rte_flow_action *action,
291 struct rte_flow_error *error)
293 const struct rte_flow_action_set_ipv4 *conf =
294 (const struct rte_flow_action_set_ipv4 *)(action->conf);
295 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
296 struct rte_flow_item_ipv4 ipv4;
297 struct rte_flow_item_ipv4 ipv4_mask;
299 memset(&ipv4, 0, sizeof(ipv4));
300 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
301 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
302 ipv4.hdr.src_addr = conf->ipv4_addr;
303 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
305 ipv4.hdr.dst_addr = conf->ipv4_addr;
306 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
309 item.mask = &ipv4_mask;
310 return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
311 MLX5_MODIFICATION_TYPE_SET, error);
315 * Convert modify-header set IPv6 address action to DV specification.
317 * @param[in,out] resource
318 * Pointer to the modify-header resource.
320 * Pointer to action specification.
322 * Pointer to the error structure.
325 * 0 on success, a negative errno value otherwise and rte_errno is set.
328 flow_dv_convert_action_modify_ipv6
329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
330 const struct rte_flow_action *action,
331 struct rte_flow_error *error)
333 const struct rte_flow_action_set_ipv6 *conf =
334 (const struct rte_flow_action_set_ipv6 *)(action->conf);
335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
336 struct rte_flow_item_ipv6 ipv6;
337 struct rte_flow_item_ipv6 ipv6_mask;
339 memset(&ipv6, 0, sizeof(ipv6));
340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
341 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
342 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
343 sizeof(ipv6.hdr.src_addr));
344 memcpy(&ipv6_mask.hdr.src_addr,
345 &rte_flow_item_ipv6_mask.hdr.src_addr,
346 sizeof(ipv6.hdr.src_addr));
348 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
349 sizeof(ipv6.hdr.dst_addr));
350 memcpy(&ipv6_mask.hdr.dst_addr,
351 &rte_flow_item_ipv6_mask.hdr.dst_addr,
352 sizeof(ipv6.hdr.dst_addr));
355 item.mask = &ipv6_mask;
356 return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
357 MLX5_MODIFICATION_TYPE_SET, error);
361 * Convert modify-header set MAC address action to DV specification.
363 * @param[in,out] resource
364 * Pointer to the modify-header resource.
366 * Pointer to action specification.
368 * Pointer to the error structure.
371 * 0 on success, a negative errno value otherwise and rte_errno is set.
374 flow_dv_convert_action_modify_mac
375 (struct mlx5_flow_dv_modify_hdr_resource *resource,
376 const struct rte_flow_action *action,
377 struct rte_flow_error *error)
379 const struct rte_flow_action_set_mac *conf =
380 (const struct rte_flow_action_set_mac *)(action->conf);
381 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
382 struct rte_flow_item_eth eth;
383 struct rte_flow_item_eth eth_mask;
385 memset(ð, 0, sizeof(eth));
386 memset(ð_mask, 0, sizeof(eth_mask));
387 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
388 memcpy(ð.src.addr_bytes, &conf->mac_addr,
389 sizeof(eth.src.addr_bytes));
390 memcpy(ð_mask.src.addr_bytes,
391 &rte_flow_item_eth_mask.src.addr_bytes,
392 sizeof(eth_mask.src.addr_bytes));
394 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
395 sizeof(eth.dst.addr_bytes));
396 memcpy(ð_mask.dst.addr_bytes,
397 &rte_flow_item_eth_mask.dst.addr_bytes,
398 sizeof(eth_mask.dst.addr_bytes));
401 item.mask = ð_mask;
402 return flow_dv_convert_modify_action(&item, modify_eth, resource,
403 MLX5_MODIFICATION_TYPE_SET, error);
407 * Convert modify-header set VLAN VID action to DV specification.
409 * @param[in,out] resource
410 * Pointer to the modify-header resource.
412 * Pointer to action specification.
414 * Pointer to the error structure.
417 * 0 on success, a negative errno value otherwise and rte_errno is set.
420 flow_dv_convert_action_modify_vlan_vid
421 (struct mlx5_flow_dv_modify_hdr_resource *resource,
422 const struct rte_flow_action *action,
423 struct rte_flow_error *error)
425 const struct rte_flow_action_of_set_vlan_vid *conf =
426 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
427 int i = resource->actions_num;
428 struct mlx5_modification_cmd *actions = &resource->actions[i];
429 struct field_modify_info *field = modify_vlan_out_first_vid;
431 if (i >= MLX5_MODIFY_NUM)
432 return rte_flow_error_set(error, EINVAL,
433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434 "too many items to modify");
435 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
436 actions[i].field = field->id;
437 actions[i].length = field->size;
438 actions[i].offset = field->offset;
439 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
440 actions[i].data1 = conf->vlan_vid;
441 actions[i].data1 = actions[i].data1 << 16;
442 resource->actions_num = ++i;
447 * Convert modify-header set TP action to DV specification.
449 * @param[in,out] resource
450 * Pointer to the modify-header resource.
452 * Pointer to action specification.
454 * Pointer to rte_flow_item objects list.
456 * Pointer to flow attributes structure.
458 * Pointer to the error structure.
461 * 0 on success, a negative errno value otherwise and rte_errno is set.
464 flow_dv_convert_action_modify_tp
465 (struct mlx5_flow_dv_modify_hdr_resource *resource,
466 const struct rte_flow_action *action,
467 const struct rte_flow_item *items,
468 union flow_dv_attr *attr,
469 struct rte_flow_error *error)
471 const struct rte_flow_action_set_tp *conf =
472 (const struct rte_flow_action_set_tp *)(action->conf);
473 struct rte_flow_item item;
474 struct rte_flow_item_udp udp;
475 struct rte_flow_item_udp udp_mask;
476 struct rte_flow_item_tcp tcp;
477 struct rte_flow_item_tcp tcp_mask;
478 struct field_modify_info *field;
481 flow_dv_attr_init(items, attr);
483 memset(&udp, 0, sizeof(udp));
484 memset(&udp_mask, 0, sizeof(udp_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
486 udp.hdr.src_port = conf->port;
487 udp_mask.hdr.src_port =
488 rte_flow_item_udp_mask.hdr.src_port;
490 udp.hdr.dst_port = conf->port;
491 udp_mask.hdr.dst_port =
492 rte_flow_item_udp_mask.hdr.dst_port;
494 item.type = RTE_FLOW_ITEM_TYPE_UDP;
496 item.mask = &udp_mask;
500 memset(&tcp, 0, sizeof(tcp));
501 memset(&tcp_mask, 0, sizeof(tcp_mask));
502 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
503 tcp.hdr.src_port = conf->port;
504 tcp_mask.hdr.src_port =
505 rte_flow_item_tcp_mask.hdr.src_port;
507 tcp.hdr.dst_port = conf->port;
508 tcp_mask.hdr.dst_port =
509 rte_flow_item_tcp_mask.hdr.dst_port;
511 item.type = RTE_FLOW_ITEM_TYPE_TCP;
513 item.mask = &tcp_mask;
516 return flow_dv_convert_modify_action(&item, field, resource,
517 MLX5_MODIFICATION_TYPE_SET, error);
521 * Convert modify-header set TTL action to DV specification.
523 * @param[in,out] resource
524 * Pointer to the modify-header resource.
526 * Pointer to action specification.
528 * Pointer to rte_flow_item objects list.
530 * Pointer to flow attributes structure.
532 * Pointer to the error structure.
535 * 0 on success, a negative errno value otherwise and rte_errno is set.
538 flow_dv_convert_action_modify_ttl
539 (struct mlx5_flow_dv_modify_hdr_resource *resource,
540 const struct rte_flow_action *action,
541 const struct rte_flow_item *items,
542 union flow_dv_attr *attr,
543 struct rte_flow_error *error)
545 const struct rte_flow_action_set_ttl *conf =
546 (const struct rte_flow_action_set_ttl *)(action->conf);
547 struct rte_flow_item item;
548 struct rte_flow_item_ipv4 ipv4;
549 struct rte_flow_item_ipv4 ipv4_mask;
550 struct rte_flow_item_ipv6 ipv6;
551 struct rte_flow_item_ipv6 ipv6_mask;
552 struct field_modify_info *field;
555 flow_dv_attr_init(items, attr);
557 memset(&ipv4, 0, sizeof(ipv4));
558 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
559 ipv4.hdr.time_to_live = conf->ttl_value;
560 ipv4_mask.hdr.time_to_live = 0xFF;
561 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
563 item.mask = &ipv4_mask;
567 memset(&ipv6, 0, sizeof(ipv6));
568 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
569 ipv6.hdr.hop_limits = conf->ttl_value;
570 ipv6_mask.hdr.hop_limits = 0xFF;
571 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
573 item.mask = &ipv6_mask;
576 return flow_dv_convert_modify_action(&item, field, resource,
577 MLX5_MODIFICATION_TYPE_SET, error);
581 * Convert modify-header decrement TTL action to DV specification.
583 * @param[in,out] resource
584 * Pointer to the modify-header resource.
586 * Pointer to action specification.
588 * Pointer to rte_flow_item objects list.
590 * Pointer to flow attributes structure.
592 * Pointer to the error structure.
595 * 0 on success, a negative errno value otherwise and rte_errno is set.
598 flow_dv_convert_action_modify_dec_ttl
599 (struct mlx5_flow_dv_modify_hdr_resource *resource,
600 const struct rte_flow_item *items,
601 union flow_dv_attr *attr,
602 struct rte_flow_error *error)
604 struct rte_flow_item item;
605 struct rte_flow_item_ipv4 ipv4;
606 struct rte_flow_item_ipv4 ipv4_mask;
607 struct rte_flow_item_ipv6 ipv6;
608 struct rte_flow_item_ipv6 ipv6_mask;
609 struct field_modify_info *field;
612 flow_dv_attr_init(items, attr);
614 memset(&ipv4, 0, sizeof(ipv4));
615 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
616 ipv4.hdr.time_to_live = 0xFF;
617 ipv4_mask.hdr.time_to_live = 0xFF;
618 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
620 item.mask = &ipv4_mask;
624 memset(&ipv6, 0, sizeof(ipv6));
625 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
626 ipv6.hdr.hop_limits = 0xFF;
627 ipv6_mask.hdr.hop_limits = 0xFF;
628 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
630 item.mask = &ipv6_mask;
633 return flow_dv_convert_modify_action(&item, field, resource,
634 MLX5_MODIFICATION_TYPE_ADD, error);
638 * Convert modify-header increment/decrement TCP Sequence number
639 * to DV specification.
641 * @param[in,out] resource
642 * Pointer to the modify-header resource.
644 * Pointer to action specification.
646 * Pointer to the error structure.
649 * 0 on success, a negative errno value otherwise and rte_errno is set.
652 flow_dv_convert_action_modify_tcp_seq
653 (struct mlx5_flow_dv_modify_hdr_resource *resource,
654 const struct rte_flow_action *action,
655 struct rte_flow_error *error)
657 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
658 uint64_t value = rte_be_to_cpu_32(*conf);
659 struct rte_flow_item item;
660 struct rte_flow_item_tcp tcp;
661 struct rte_flow_item_tcp tcp_mask;
663 memset(&tcp, 0, sizeof(tcp));
664 memset(&tcp_mask, 0, sizeof(tcp_mask));
665 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
667 * The HW has no decrement operation, only increment operation.
668 * To simulate decrement X from Y using increment operation
669 * we need to add UINT32_MAX X times to Y.
670 * Each adding of UINT32_MAX decrements Y by 1.
673 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
674 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
675 item.type = RTE_FLOW_ITEM_TYPE_TCP;
677 item.mask = &tcp_mask;
678 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
679 MLX5_MODIFICATION_TYPE_ADD, error);
683 * Convert modify-header increment/decrement TCP Acknowledgment number
684 * to DV specification.
686 * @param[in,out] resource
687 * Pointer to the modify-header resource.
689 * Pointer to action specification.
691 * Pointer to the error structure.
694 * 0 on success, a negative errno value otherwise and rte_errno is set.
697 flow_dv_convert_action_modify_tcp_ack
698 (struct mlx5_flow_dv_modify_hdr_resource *resource,
699 const struct rte_flow_action *action,
700 struct rte_flow_error *error)
702 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
703 uint64_t value = rte_be_to_cpu_32(*conf);
704 struct rte_flow_item item;
705 struct rte_flow_item_tcp tcp;
706 struct rte_flow_item_tcp tcp_mask;
708 memset(&tcp, 0, sizeof(tcp));
709 memset(&tcp_mask, 0, sizeof(tcp_mask));
710 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
712 * The HW has no decrement operation, only increment operation.
713 * To simulate decrement X from Y using increment operation
714 * we need to add UINT32_MAX X times to Y.
715 * Each adding of UINT32_MAX decrements Y by 1.
718 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
719 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
720 item.type = RTE_FLOW_ITEM_TYPE_TCP;
722 item.mask = &tcp_mask;
723 return flow_dv_convert_modify_action(&item, modify_tcp, resource,
724 MLX5_MODIFICATION_TYPE_ADD, error);
728 * Validate META item.
731 * Pointer to the rte_eth_dev structure.
733 * Item specification.
735 * Attributes of flow that includes this item.
737 * Pointer to error structure.
740 * 0 on success, a negative errno value otherwise and rte_errno is set.
743 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
744 const struct rte_flow_item *item,
745 const struct rte_flow_attr *attr,
746 struct rte_flow_error *error)
748 const struct rte_flow_item_meta *spec = item->spec;
749 const struct rte_flow_item_meta *mask = item->mask;
750 const struct rte_flow_item_meta nic_mask = {
751 .data = RTE_BE32(UINT32_MAX)
754 uint64_t offloads = dev->data->dev_conf.txmode.offloads;
756 if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
757 return rte_flow_error_set(error, EPERM,
758 RTE_FLOW_ERROR_TYPE_ITEM,
760 "match on metadata offload "
761 "configuration is off for this port");
763 return rte_flow_error_set(error, EINVAL,
764 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
766 "data cannot be empty");
768 return rte_flow_error_set(error, EINVAL,
769 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
771 "data cannot be zero");
773 mask = &rte_flow_item_meta_mask;
774 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
775 (const uint8_t *)&nic_mask,
776 sizeof(struct rte_flow_item_meta),
781 return rte_flow_error_set(error, ENOTSUP,
782 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
784 "pattern not supported for ingress");
789 * Validate vport item.
792 * Pointer to the rte_eth_dev structure.
794 * Item specification.
796 * Attributes of flow that includes this item.
797 * @param[in] item_flags
798 * Bit-fields that holds the items detected until now.
800 * Pointer to error structure.
803 * 0 on success, a negative errno value otherwise and rte_errno is set.
806 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
807 const struct rte_flow_item *item,
808 const struct rte_flow_attr *attr,
810 struct rte_flow_error *error)
812 const struct rte_flow_item_port_id *spec = item->spec;
813 const struct rte_flow_item_port_id *mask = item->mask;
814 const struct rte_flow_item_port_id switch_mask = {
817 struct mlx5_priv *esw_priv;
818 struct mlx5_priv *dev_priv;
822 return rte_flow_error_set(error, EINVAL,
823 RTE_FLOW_ERROR_TYPE_ITEM,
825 "match on port id is valid only"
826 " when transfer flag is enabled");
827 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
828 return rte_flow_error_set(error, ENOTSUP,
829 RTE_FLOW_ERROR_TYPE_ITEM, item,
830 "multiple source ports are not"
834 if (mask->id != 0xffffffff)
835 return rte_flow_error_set(error, ENOTSUP,
836 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
838 "no support for partial mask on"
840 ret = mlx5_flow_item_acceptable
841 (item, (const uint8_t *)mask,
842 (const uint8_t *)&rte_flow_item_port_id_mask,
843 sizeof(struct rte_flow_item_port_id),
849 esw_priv = mlx5_port_to_eswitch_info(spec->id);
851 return rte_flow_error_set(error, rte_errno,
852 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
853 "failed to obtain E-Switch info for"
855 dev_priv = mlx5_dev_to_eswitch_info(dev);
857 return rte_flow_error_set(error, rte_errno,
858 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
860 "failed to obtain E-Switch info");
861 if (esw_priv->domain_id != dev_priv->domain_id)
862 return rte_flow_error_set(error, EINVAL,
863 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
864 "cannot match on a port from a"
865 " different E-Switch");
870 * Validate the pop VLAN action.
873 * Pointer to the rte_eth_dev structure.
874 * @param[in] action_flags
875 * Holds the actions detected until now.
877 * Pointer to the pop vlan action.
878 * @param[in] item_flags
879 * The items found in this flow rule.
881 * Pointer to flow attributes.
883 * Pointer to error structure.
886 * 0 on success, a negative errno value otherwise and rte_errno is set.
889 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
890 uint64_t action_flags,
891 const struct rte_flow_action *action,
893 const struct rte_flow_attr *attr,
894 struct rte_flow_error *error)
896 struct mlx5_priv *priv = dev->data->dev_private;
900 if (!priv->sh->pop_vlan_action)
901 return rte_flow_error_set(error, ENOTSUP,
902 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
904 "pop vlan action is not supported");
906 * Check for inconsistencies:
907 * fail strip_vlan in a flow that matches packets without VLAN tags.
908 * fail strip_vlan in a flow that matches packets without explicitly a
909 * matching on VLAN tag ?
911 if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
912 return rte_flow_error_set(error, ENOTSUP,
913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
915 "no support for multiple vlan pop "
917 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
918 return rte_flow_error_set(error, ENOTSUP,
919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
921 "cannot pop vlan without a "
922 "match on (outer) vlan in the flow");
927 * Get VLAN default info from vlan match info.
930 * Pointer to the rte_eth_dev structure.
932 * the list of item specifications.
934 * pointer VLAN info to fill to.
936 * Pointer to error structure.
939 * 0 on success, a negative errno value otherwise and rte_errno is set.
942 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
943 struct rte_vlan_hdr *vlan)
945 const struct rte_flow_item_vlan nic_mask = {
946 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
947 MLX5DV_FLOW_VLAN_VID_MASK),
948 .inner_type = RTE_BE16(0xffff),
953 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
954 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
956 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
957 const struct rte_flow_item_vlan *vlan_m = items->mask;
958 const struct rte_flow_item_vlan *vlan_v = items->spec;
962 /* Only full match values are accepted */
963 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
964 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
965 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
967 rte_be_to_cpu_16(vlan_v->tci &
968 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
970 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
971 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
972 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
974 rte_be_to_cpu_16(vlan_v->tci &
975 MLX5DV_FLOW_VLAN_VID_MASK_BE);
977 if (vlan_m->inner_type == nic_mask.inner_type)
978 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
984 * Validate the push VLAN action.
986 * @param[in] action_flags
987 * Holds the actions detected until now.
989 * Pointer to the encap action.
991 * Pointer to flow attributes
993 * Pointer to error structure.
996 * 0 on success, a negative errno value otherwise and rte_errno is set.
999 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1000 const struct rte_flow_action *action,
1001 const struct rte_flow_attr *attr,
1002 struct rte_flow_error *error)
1004 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1006 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1007 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1008 return rte_flow_error_set(error, EINVAL,
1009 RTE_FLOW_ERROR_TYPE_ACTION, action,
1010 "invalid vlan ethertype");
1012 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1013 return rte_flow_error_set(error, ENOTSUP,
1014 RTE_FLOW_ERROR_TYPE_ACTION, action,
1015 "no support for multiple VLAN "
1022 * Validate the set VLAN PCP.
1024 * @param[in] action_flags
1025 * Holds the actions detected until now.
1026 * @param[in] actions
1027 * Pointer to the list of actions remaining in the flow rule.
1029 * Pointer to flow attributes
1031 * Pointer to error structure.
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1038 const struct rte_flow_action actions[],
1039 struct rte_flow_error *error)
1041 const struct rte_flow_action *action = actions;
1042 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1044 if (conf->vlan_pcp > 7)
1045 return rte_flow_error_set(error, EINVAL,
1046 RTE_FLOW_ERROR_TYPE_ACTION, action,
1047 "VLAN PCP value is too big");
1048 if (mlx5_flow_find_action(actions,
1049 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) == NULL)
1050 return rte_flow_error_set(error, ENOTSUP,
1051 RTE_FLOW_ERROR_TYPE_ACTION, action,
1052 "set VLAN PCP can only be used "
1053 "with push VLAN action");
1054 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
1055 return rte_flow_error_set(error, ENOTSUP,
1056 RTE_FLOW_ERROR_TYPE_ACTION, action,
1057 "set VLAN PCP action must precede "
1058 "the push VLAN action");
1063 * Validate the set VLAN VID.
1065 * @param[in] item_flags
1066 * Holds the items detected in this rule.
1067 * @param[in] actions
1068 * Pointer to the list of actions remaining in the flow rule.
1070 * Pointer to flow attributes
1072 * Pointer to error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1079 const struct rte_flow_action actions[],
1080 struct rte_flow_error *error)
1082 const struct rte_flow_action *action = actions;
1083 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1085 if (conf->vlan_vid > RTE_BE16(0xFFE))
1086 return rte_flow_error_set(error, EINVAL,
1087 RTE_FLOW_ERROR_TYPE_ACTION, action,
1088 "VLAN VID value is too big");
1089 /* If a push VLAN action follows then it will handle this action */
1090 if (mlx5_flow_find_action(actions,
1091 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
1095 * Action is on an existing VLAN header:
1096 * Need to verify this is a single modify CID action.
1097 * Rule mast include a match on outer VLAN.
1099 if (mlx5_flow_find_action(++action,
1100 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1101 return rte_flow_error_set(error, ENOTSUP,
1102 RTE_FLOW_ERROR_TYPE_ACTION, action,
1103 "Multiple VLAN VID modifications are "
1105 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1106 return rte_flow_error_set(error, EINVAL,
1107 RTE_FLOW_ERROR_TYPE_ACTION, action,
1108 "match on VLAN is required in order "
1114 * Validate count action.
1119 * Pointer to error structure.
1122 * 0 on success, a negative errno value otherwise and rte_errno is set.
1125 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1126 struct rte_flow_error *error)
1128 struct mlx5_priv *priv = dev->data->dev_private;
1130 if (!priv->config.devx)
1132 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1136 return rte_flow_error_set
1138 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1140 "count action not supported");
1144 * Validate the L2 encap action.
1146 * @param[in] action_flags
1147 * Holds the actions detected until now.
1149 * Pointer to the encap action.
1151 * Pointer to flow attributes
1153 * Pointer to error structure.
1156 * 0 on success, a negative errno value otherwise and rte_errno is set.
1159 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1160 const struct rte_flow_action *action,
1161 const struct rte_flow_attr *attr,
1162 struct rte_flow_error *error)
1164 if (!(action->conf))
1165 return rte_flow_error_set(error, EINVAL,
1166 RTE_FLOW_ERROR_TYPE_ACTION, action,
1167 "configuration cannot be null");
1168 if (action_flags & MLX5_FLOW_ACTION_DROP)
1169 return rte_flow_error_set(error, EINVAL,
1170 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1171 "can't drop and encap in same flow");
1172 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1173 return rte_flow_error_set(error, EINVAL,
1174 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1175 "can only have a single encap or"
1176 " decap action in a flow");
1177 if (!attr->transfer && attr->ingress)
1178 return rte_flow_error_set(error, ENOTSUP,
1179 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1181 "encap action not supported for "
1187 * Validate the L2 decap action.
1189 * @param[in] action_flags
1190 * Holds the actions detected until now.
1192 * Pointer to flow attributes
1194 * Pointer to error structure.
1197 * 0 on success, a negative errno value otherwise and rte_errno is set.
1200 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1201 const struct rte_flow_attr *attr,
1202 struct rte_flow_error *error)
1204 if (action_flags & MLX5_FLOW_ACTION_DROP)
1205 return rte_flow_error_set(error, EINVAL,
1206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1207 "can't drop and decap in same flow");
1208 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1209 return rte_flow_error_set(error, EINVAL,
1210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1211 "can only have a single encap or"
1212 " decap action in a flow");
1213 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1214 return rte_flow_error_set(error, EINVAL,
1215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1216 "can't have decap action after"
1219 return rte_flow_error_set(error, ENOTSUP,
1220 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1222 "decap action not supported for "
1228 * Validate the raw encap action.
1230 * @param[in] action_flags
1231 * Holds the actions detected until now.
1233 * Pointer to the encap action.
1235 * Pointer to flow attributes
1237 * Pointer to error structure.
1240 * 0 on success, a negative errno value otherwise and rte_errno is set.
1243 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1244 const struct rte_flow_action *action,
1245 const struct rte_flow_attr *attr,
1246 struct rte_flow_error *error)
1248 const struct rte_flow_action_raw_encap *raw_encap =
1249 (const struct rte_flow_action_raw_encap *)action->conf;
1250 if (!(action->conf))
1251 return rte_flow_error_set(error, EINVAL,
1252 RTE_FLOW_ERROR_TYPE_ACTION, action,
1253 "configuration cannot be null");
1254 if (action_flags & MLX5_FLOW_ACTION_DROP)
1255 return rte_flow_error_set(error, EINVAL,
1256 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1257 "can't drop and encap in same flow");
1258 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1259 return rte_flow_error_set(error, EINVAL,
1260 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1261 "can only have a single encap"
1262 " action in a flow");
1263 /* encap without preceding decap is not supported for ingress */
1264 if (!attr->transfer && attr->ingress &&
1265 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1266 return rte_flow_error_set(error, ENOTSUP,
1267 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1269 "encap action not supported for "
1271 if (!raw_encap->size || !raw_encap->data)
1272 return rte_flow_error_set(error, EINVAL,
1273 RTE_FLOW_ERROR_TYPE_ACTION, action,
1274 "raw encap data cannot be empty");
1279 * Validate the raw decap action.
1281 * @param[in] action_flags
1282 * Holds the actions detected until now.
1284 * Pointer to the encap action.
1286 * Pointer to flow attributes
1288 * Pointer to error structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1295 const struct rte_flow_action *action,
1296 const struct rte_flow_attr *attr,
1297 struct rte_flow_error *error)
1299 if (action_flags & MLX5_FLOW_ACTION_DROP)
1300 return rte_flow_error_set(error, EINVAL,
1301 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1302 "can't drop and decap in same flow");
1303 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1304 return rte_flow_error_set(error, EINVAL,
1305 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1306 "can't have encap action before"
1308 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1309 return rte_flow_error_set(error, EINVAL,
1310 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1311 "can only have a single decap"
1312 " action in a flow");
1313 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1314 return rte_flow_error_set(error, EINVAL,
1315 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1316 "can't have decap action after"
1318 /* decap action is valid on egress only if it is followed by encap */
1320 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1321 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1324 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1325 return rte_flow_error_set
1327 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1328 NULL, "decap action not supported"
1335 * Find existing encap/decap resource or create and register a new one.
1337 * @param dev[in, out]
1338 * Pointer to rte_eth_dev structure.
1339 * @param[in, out] resource
1340 * Pointer to encap/decap resource.
1341 * @parm[in, out] dev_flow
1342 * Pointer to the dev_flow.
1344 * pointer to error structure.
1347 * 0 on success otherwise -errno and errno is set.
1350 flow_dv_encap_decap_resource_register
1351 (struct rte_eth_dev *dev,
1352 struct mlx5_flow_dv_encap_decap_resource *resource,
1353 struct mlx5_flow *dev_flow,
1354 struct rte_flow_error *error)
1356 struct mlx5_priv *priv = dev->data->dev_private;
1357 struct mlx5_ibv_shared *sh = priv->sh;
1358 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1359 struct rte_flow *flow = dev_flow->flow;
1360 struct mlx5dv_dr_domain *domain;
1362 resource->flags = flow->group ? 0 : 1;
1363 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1364 domain = sh->fdb_domain;
1365 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1366 domain = sh->rx_domain;
1368 domain = sh->tx_domain;
1370 /* Lookup a matching resource from cache. */
1371 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1372 if (resource->reformat_type == cache_resource->reformat_type &&
1373 resource->ft_type == cache_resource->ft_type &&
1374 resource->flags == cache_resource->flags &&
1375 resource->size == cache_resource->size &&
1376 !memcmp((const void *)resource->buf,
1377 (const void *)cache_resource->buf,
1379 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1380 (void *)cache_resource,
1381 rte_atomic32_read(&cache_resource->refcnt));
1382 rte_atomic32_inc(&cache_resource->refcnt);
1383 dev_flow->dv.encap_decap = cache_resource;
1387 /* Register new encap/decap resource. */
1388 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1389 if (!cache_resource)
1390 return rte_flow_error_set(error, ENOMEM,
1391 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1392 "cannot allocate resource memory");
1393 *cache_resource = *resource;
1394 cache_resource->verbs_action =
1395 mlx5_glue->dv_create_flow_action_packet_reformat
1396 (sh->ctx, cache_resource->reformat_type,
1397 cache_resource->ft_type, domain, cache_resource->flags,
1398 cache_resource->size,
1399 (cache_resource->size ? cache_resource->buf : NULL));
1400 if (!cache_resource->verbs_action) {
1401 rte_free(cache_resource);
1402 return rte_flow_error_set(error, ENOMEM,
1403 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1404 NULL, "cannot create action");
1406 rte_atomic32_init(&cache_resource->refcnt);
1407 rte_atomic32_inc(&cache_resource->refcnt);
1408 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1409 dev_flow->dv.encap_decap = cache_resource;
1410 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1411 (void *)cache_resource,
1412 rte_atomic32_read(&cache_resource->refcnt));
1417 * Find existing table jump resource or create and register a new one.
1419 * @param dev[in, out]
1420 * Pointer to rte_eth_dev structure.
1421 * @param[in, out] resource
1422 * Pointer to jump table resource.
1423 * @parm[in, out] dev_flow
1424 * Pointer to the dev_flow.
1426 * pointer to error structure.
1429 * 0 on success otherwise -errno and errno is set.
1432 flow_dv_jump_tbl_resource_register
1433 (struct rte_eth_dev *dev,
1434 struct mlx5_flow_dv_jump_tbl_resource *resource,
1435 struct mlx5_flow *dev_flow,
1436 struct rte_flow_error *error)
1438 struct mlx5_priv *priv = dev->data->dev_private;
1439 struct mlx5_ibv_shared *sh = priv->sh;
1440 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1442 /* Lookup a matching resource from cache. */
1443 LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1444 if (resource->tbl == cache_resource->tbl) {
1445 DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1446 (void *)cache_resource,
1447 rte_atomic32_read(&cache_resource->refcnt));
1448 rte_atomic32_inc(&cache_resource->refcnt);
1449 dev_flow->dv.jump = cache_resource;
1453 /* Register new jump table resource. */
1454 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1455 if (!cache_resource)
1456 return rte_flow_error_set(error, ENOMEM,
1457 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1458 "cannot allocate resource memory");
1459 *cache_resource = *resource;
1460 cache_resource->action =
1461 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1462 (resource->tbl->obj);
1463 if (!cache_resource->action) {
1464 rte_free(cache_resource);
1465 return rte_flow_error_set(error, ENOMEM,
1466 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1467 NULL, "cannot create action");
1469 rte_atomic32_init(&cache_resource->refcnt);
1470 rte_atomic32_inc(&cache_resource->refcnt);
1471 LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1472 dev_flow->dv.jump = cache_resource;
1473 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
1474 (void *)cache_resource,
1475 rte_atomic32_read(&cache_resource->refcnt));
1480 * Find existing table port ID resource or create and register a new one.
1482 * @param dev[in, out]
1483 * Pointer to rte_eth_dev structure.
1484 * @param[in, out] resource
1485 * Pointer to port ID action resource.
1486 * @parm[in, out] dev_flow
1487 * Pointer to the dev_flow.
1489 * pointer to error structure.
1492 * 0 on success otherwise -errno and errno is set.
1495 flow_dv_port_id_action_resource_register
1496 (struct rte_eth_dev *dev,
1497 struct mlx5_flow_dv_port_id_action_resource *resource,
1498 struct mlx5_flow *dev_flow,
1499 struct rte_flow_error *error)
1501 struct mlx5_priv *priv = dev->data->dev_private;
1502 struct mlx5_ibv_shared *sh = priv->sh;
1503 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1505 /* Lookup a matching resource from cache. */
1506 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1507 if (resource->port_id == cache_resource->port_id) {
1508 DRV_LOG(DEBUG, "port id action resource resource %p: "
1510 (void *)cache_resource,
1511 rte_atomic32_read(&cache_resource->refcnt));
1512 rte_atomic32_inc(&cache_resource->refcnt);
1513 dev_flow->dv.port_id_action = cache_resource;
1517 /* Register new port id action resource. */
1518 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1519 if (!cache_resource)
1520 return rte_flow_error_set(error, ENOMEM,
1521 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1522 "cannot allocate resource memory");
1523 *cache_resource = *resource;
1524 cache_resource->action =
1525 mlx5_glue->dr_create_flow_action_dest_vport
1526 (priv->sh->fdb_domain, resource->port_id);
1527 if (!cache_resource->action) {
1528 rte_free(cache_resource);
1529 return rte_flow_error_set(error, ENOMEM,
1530 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1531 NULL, "cannot create action");
1533 rte_atomic32_init(&cache_resource->refcnt);
1534 rte_atomic32_inc(&cache_resource->refcnt);
1535 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1536 dev_flow->dv.port_id_action = cache_resource;
1537 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1538 (void *)cache_resource,
1539 rte_atomic32_read(&cache_resource->refcnt));
1544 * Find existing push vlan resource or create and register a new one.
1546 * @param dev[in, out]
1547 * Pointer to rte_eth_dev structure.
1548 * @param[in, out] resource
1549 * Pointer to port ID action resource.
1550 * @parm[in, out] dev_flow
1551 * Pointer to the dev_flow.
1553 * pointer to error structure.
1556 * 0 on success otherwise -errno and errno is set.
1559 flow_dv_push_vlan_action_resource_register
1560 (struct rte_eth_dev *dev,
1561 struct mlx5_flow_dv_push_vlan_action_resource *resource,
1562 struct mlx5_flow *dev_flow,
1563 struct rte_flow_error *error)
1565 struct mlx5_priv *priv = dev->data->dev_private;
1566 struct mlx5_ibv_shared *sh = priv->sh;
1567 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1568 struct mlx5dv_dr_domain *domain;
1570 /* Lookup a matching resource from cache. */
1571 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1572 if (resource->vlan_tag == cache_resource->vlan_tag &&
1573 resource->ft_type == cache_resource->ft_type) {
1574 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1576 (void *)cache_resource,
1577 rte_atomic32_read(&cache_resource->refcnt));
1578 rte_atomic32_inc(&cache_resource->refcnt);
1579 dev_flow->dv.push_vlan_res = cache_resource;
1583 /* Register new push_vlan action resource. */
1584 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1585 if (!cache_resource)
1586 return rte_flow_error_set(error, ENOMEM,
1587 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1588 "cannot allocate resource memory");
1589 *cache_resource = *resource;
1590 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1591 domain = sh->fdb_domain;
1592 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1593 domain = sh->rx_domain;
1595 domain = sh->tx_domain;
1596 cache_resource->action =
1597 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1598 resource->vlan_tag);
1599 if (!cache_resource->action) {
1600 rte_free(cache_resource);
1601 return rte_flow_error_set(error, ENOMEM,
1602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1603 NULL, "cannot create action");
1605 rte_atomic32_init(&cache_resource->refcnt);
1606 rte_atomic32_inc(&cache_resource->refcnt);
1607 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1608 dev_flow->dv.push_vlan_res = cache_resource;
1609 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1610 (void *)cache_resource,
1611 rte_atomic32_read(&cache_resource->refcnt));
1615 * Get the size of specific rte_flow_item_type
1617 * @param[in] item_type
1618 * Tested rte_flow_item_type.
1621 * sizeof struct item_type, 0 if void or irrelevant.
1624 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1628 switch (item_type) {
1629 case RTE_FLOW_ITEM_TYPE_ETH:
1630 retval = sizeof(struct rte_flow_item_eth);
1632 case RTE_FLOW_ITEM_TYPE_VLAN:
1633 retval = sizeof(struct rte_flow_item_vlan);
1635 case RTE_FLOW_ITEM_TYPE_IPV4:
1636 retval = sizeof(struct rte_flow_item_ipv4);
1638 case RTE_FLOW_ITEM_TYPE_IPV6:
1639 retval = sizeof(struct rte_flow_item_ipv6);
1641 case RTE_FLOW_ITEM_TYPE_UDP:
1642 retval = sizeof(struct rte_flow_item_udp);
1644 case RTE_FLOW_ITEM_TYPE_TCP:
1645 retval = sizeof(struct rte_flow_item_tcp);
1647 case RTE_FLOW_ITEM_TYPE_VXLAN:
1648 retval = sizeof(struct rte_flow_item_vxlan);
1650 case RTE_FLOW_ITEM_TYPE_GRE:
1651 retval = sizeof(struct rte_flow_item_gre);
1653 case RTE_FLOW_ITEM_TYPE_NVGRE:
1654 retval = sizeof(struct rte_flow_item_nvgre);
1656 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1657 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1659 case RTE_FLOW_ITEM_TYPE_MPLS:
1660 retval = sizeof(struct rte_flow_item_mpls);
1662 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1670 #define MLX5_ENCAP_IPV4_VERSION 0x40
1671 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
1672 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
1673 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
1674 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
1675 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
1676 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
1679 * Convert the encap action data from list of rte_flow_item to raw buffer
1682 * Pointer to rte_flow_item objects list.
1684 * Pointer to the output buffer.
1686 * Pointer to the output buffer size.
1688 * Pointer to the error structure.
1691 * 0 on success, a negative errno value otherwise and rte_errno is set.
1694 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1695 size_t *size, struct rte_flow_error *error)
1697 struct rte_ether_hdr *eth = NULL;
1698 struct rte_vlan_hdr *vlan = NULL;
1699 struct rte_ipv4_hdr *ipv4 = NULL;
1700 struct rte_ipv6_hdr *ipv6 = NULL;
1701 struct rte_udp_hdr *udp = NULL;
1702 struct rte_vxlan_hdr *vxlan = NULL;
1703 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1704 struct rte_gre_hdr *gre = NULL;
1706 size_t temp_size = 0;
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ACTION,
1711 NULL, "invalid empty data");
1712 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1713 len = flow_dv_get_item_len(items->type);
1714 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1715 return rte_flow_error_set(error, EINVAL,
1716 RTE_FLOW_ERROR_TYPE_ACTION,
1717 (void *)items->type,
1718 "items total size is too big"
1719 " for encap action");
1720 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1721 switch (items->type) {
1722 case RTE_FLOW_ITEM_TYPE_ETH:
1723 eth = (struct rte_ether_hdr *)&buf[temp_size];
1725 case RTE_FLOW_ITEM_TYPE_VLAN:
1726 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1728 return rte_flow_error_set(error, EINVAL,
1729 RTE_FLOW_ERROR_TYPE_ACTION,
1730 (void *)items->type,
1731 "eth header not found");
1732 if (!eth->ether_type)
1733 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1735 case RTE_FLOW_ITEM_TYPE_IPV4:
1736 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1738 return rte_flow_error_set(error, EINVAL,
1739 RTE_FLOW_ERROR_TYPE_ACTION,
1740 (void *)items->type,
1741 "neither eth nor vlan"
1743 if (vlan && !vlan->eth_proto)
1744 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1745 else if (eth && !eth->ether_type)
1746 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1747 if (!ipv4->version_ihl)
1748 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1749 MLX5_ENCAP_IPV4_IHL_MIN;
1750 if (!ipv4->time_to_live)
1751 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1753 case RTE_FLOW_ITEM_TYPE_IPV6:
1754 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1756 return rte_flow_error_set(error, EINVAL,
1757 RTE_FLOW_ERROR_TYPE_ACTION,
1758 (void *)items->type,
1759 "neither eth nor vlan"
1761 if (vlan && !vlan->eth_proto)
1762 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1763 else if (eth && !eth->ether_type)
1764 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1765 if (!ipv6->vtc_flow)
1767 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1768 if (!ipv6->hop_limits)
1769 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1771 case RTE_FLOW_ITEM_TYPE_UDP:
1772 udp = (struct rte_udp_hdr *)&buf[temp_size];
1774 return rte_flow_error_set(error, EINVAL,
1775 RTE_FLOW_ERROR_TYPE_ACTION,
1776 (void *)items->type,
1777 "ip header not found");
1778 if (ipv4 && !ipv4->next_proto_id)
1779 ipv4->next_proto_id = IPPROTO_UDP;
1780 else if (ipv6 && !ipv6->proto)
1781 ipv6->proto = IPPROTO_UDP;
1783 case RTE_FLOW_ITEM_TYPE_VXLAN:
1784 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1786 return rte_flow_error_set(error, EINVAL,
1787 RTE_FLOW_ERROR_TYPE_ACTION,
1788 (void *)items->type,
1789 "udp header not found");
1791 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1792 if (!vxlan->vx_flags)
1794 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1796 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1797 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1799 return rte_flow_error_set(error, EINVAL,
1800 RTE_FLOW_ERROR_TYPE_ACTION,
1801 (void *)items->type,
1802 "udp header not found");
1803 if (!vxlan_gpe->proto)
1804 return rte_flow_error_set(error, EINVAL,
1805 RTE_FLOW_ERROR_TYPE_ACTION,
1806 (void *)items->type,
1807 "next protocol not found");
1810 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1811 if (!vxlan_gpe->vx_flags)
1812 vxlan_gpe->vx_flags =
1813 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1815 case RTE_FLOW_ITEM_TYPE_GRE:
1816 case RTE_FLOW_ITEM_TYPE_NVGRE:
1817 gre = (struct rte_gre_hdr *)&buf[temp_size];
1819 return rte_flow_error_set(error, EINVAL,
1820 RTE_FLOW_ERROR_TYPE_ACTION,
1821 (void *)items->type,
1822 "next protocol not found");
1824 return rte_flow_error_set(error, EINVAL,
1825 RTE_FLOW_ERROR_TYPE_ACTION,
1826 (void *)items->type,
1827 "ip header not found");
1828 if (ipv4 && !ipv4->next_proto_id)
1829 ipv4->next_proto_id = IPPROTO_GRE;
1830 else if (ipv6 && !ipv6->proto)
1831 ipv6->proto = IPPROTO_GRE;
1833 case RTE_FLOW_ITEM_TYPE_VOID:
1836 return rte_flow_error_set(error, EINVAL,
1837 RTE_FLOW_ERROR_TYPE_ACTION,
1838 (void *)items->type,
1839 "unsupported item type");
1849 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1851 struct rte_ether_hdr *eth = NULL;
1852 struct rte_vlan_hdr *vlan = NULL;
1853 struct rte_ipv6_hdr *ipv6 = NULL;
1854 struct rte_udp_hdr *udp = NULL;
1858 eth = (struct rte_ether_hdr *)data;
1859 next_hdr = (char *)(eth + 1);
1860 proto = RTE_BE16(eth->ether_type);
1863 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1864 vlan = (struct rte_vlan_hdr *)next_hdr;
1865 proto = RTE_BE16(vlan->eth_proto);
1866 next_hdr += sizeof(struct rte_vlan_hdr);
1869 /* HW calculates IPv4 csum. no need to proceed */
1870 if (proto == RTE_ETHER_TYPE_IPV4)
1873 /* non IPv4/IPv6 header. not supported */
1874 if (proto != RTE_ETHER_TYPE_IPV6) {
1875 return rte_flow_error_set(error, ENOTSUP,
1876 RTE_FLOW_ERROR_TYPE_ACTION,
1877 NULL, "Cannot offload non IPv4/IPv6");
1880 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1882 /* ignore non UDP */
1883 if (ipv6->proto != IPPROTO_UDP)
1886 udp = (struct rte_udp_hdr *)(ipv6 + 1);
1887 udp->dgram_cksum = 0;
1893 * Convert L2 encap action to DV specification.
1896 * Pointer to rte_eth_dev structure.
1898 * Pointer to action structure.
1899 * @param[in, out] dev_flow
1900 * Pointer to the mlx5_flow.
1901 * @param[in] transfer
1902 * Mark if the flow is E-Switch flow.
1904 * Pointer to the error structure.
1907 * 0 on success, a negative errno value otherwise and rte_errno is set.
1910 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
1911 const struct rte_flow_action *action,
1912 struct mlx5_flow *dev_flow,
1914 struct rte_flow_error *error)
1916 const struct rte_flow_item *encap_data;
1917 const struct rte_flow_action_raw_encap *raw_encap_data;
1918 struct mlx5_flow_dv_encap_decap_resource res = {
1920 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
1921 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1922 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
1925 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1927 (const struct rte_flow_action_raw_encap *)action->conf;
1928 res.size = raw_encap_data->size;
1929 memcpy(res.buf, raw_encap_data->data, res.size);
1930 if (flow_dv_zero_encap_udp_csum(res.buf, error))
1933 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
1935 ((const struct rte_flow_action_vxlan_encap *)
1936 action->conf)->definition;
1939 ((const struct rte_flow_action_nvgre_encap *)
1940 action->conf)->definition;
1941 if (flow_dv_convert_encap_data(encap_data, res.buf,
1945 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1946 return rte_flow_error_set(error, EINVAL,
1947 RTE_FLOW_ERROR_TYPE_ACTION,
1948 NULL, "can't create L2 encap action");
1953 * Convert L2 decap action to DV specification.
1956 * Pointer to rte_eth_dev structure.
1957 * @param[in, out] dev_flow
1958 * Pointer to the mlx5_flow.
1959 * @param[in] transfer
1960 * Mark if the flow is E-Switch flow.
1962 * Pointer to the error structure.
1965 * 0 on success, a negative errno value otherwise and rte_errno is set.
1968 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
1969 struct mlx5_flow *dev_flow,
1971 struct rte_flow_error *error)
1973 struct mlx5_flow_dv_encap_decap_resource res = {
1976 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
1977 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
1978 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
1981 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION,
1984 NULL, "can't create L2 decap action");
1989 * Convert raw decap/encap (L3 tunnel) action to DV specification.
1992 * Pointer to rte_eth_dev structure.
1994 * Pointer to action structure.
1995 * @param[in, out] dev_flow
1996 * Pointer to the mlx5_flow.
1998 * Pointer to the flow attributes.
2000 * Pointer to the error structure.
2003 * 0 on success, a negative errno value otherwise and rte_errno is set.
2006 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2007 const struct rte_flow_action *action,
2008 struct mlx5_flow *dev_flow,
2009 const struct rte_flow_attr *attr,
2010 struct rte_flow_error *error)
2012 const struct rte_flow_action_raw_encap *encap_data;
2013 struct mlx5_flow_dv_encap_decap_resource res;
2015 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2016 res.size = encap_data->size;
2017 memcpy(res.buf, encap_data->data, res.size);
2018 res.reformat_type = attr->egress ?
2019 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2020 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2022 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2024 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2025 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2026 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2027 return rte_flow_error_set(error, EINVAL,
2028 RTE_FLOW_ERROR_TYPE_ACTION,
2029 NULL, "can't create encap action");
2034 * Create action push VLAN.
2037 * Pointer to rte_eth_dev structure.
2038 * @param[in] vlan_tag
2039 * the vlan tag to push to the Ethernet header.
2040 * @param[in, out] dev_flow
2041 * Pointer to the mlx5_flow.
2043 * Pointer to the flow attributes.
2045 * Pointer to the error structure.
2048 * 0 on success, a negative errno value otherwise and rte_errno is set.
2051 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2052 const struct rte_flow_attr *attr,
2053 const struct rte_vlan_hdr *vlan,
2054 struct mlx5_flow *dev_flow,
2055 struct rte_flow_error *error)
2057 struct mlx5_flow_dv_push_vlan_action_resource res;
2060 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2063 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2065 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2066 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2067 return flow_dv_push_vlan_action_resource_register
2068 (dev, &res, dev_flow, error);
2072 * Validate the modify-header actions.
2074 * @param[in] action_flags
2075 * Holds the actions detected until now.
2077 * Pointer to the modify action.
2079 * Pointer to error structure.
2082 * 0 on success, a negative errno value otherwise and rte_errno is set.
2085 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2086 const struct rte_flow_action *action,
2087 struct rte_flow_error *error)
2089 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2090 return rte_flow_error_set(error, EINVAL,
2091 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2092 NULL, "action configuration not set");
2093 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2094 return rte_flow_error_set(error, EINVAL,
2095 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2096 "can't have encap action before"
2102 * Validate the modify-header MAC address actions.
2104 * @param[in] action_flags
2105 * Holds the actions detected until now.
2107 * Pointer to the modify action.
2108 * @param[in] item_flags
2109 * Holds the items detected.
2111 * Pointer to error structure.
2114 * 0 on success, a negative errno value otherwise and rte_errno is set.
2117 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2118 const struct rte_flow_action *action,
2119 const uint64_t item_flags,
2120 struct rte_flow_error *error)
2124 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2126 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2127 return rte_flow_error_set(error, EINVAL,
2128 RTE_FLOW_ERROR_TYPE_ACTION,
2130 "no L2 item in pattern");
2136 * Validate the modify-header IPv4 address actions.
2138 * @param[in] action_flags
2139 * Holds the actions detected until now.
2141 * Pointer to the modify action.
2142 * @param[in] item_flags
2143 * Holds the items detected.
2145 * Pointer to error structure.
2148 * 0 on success, a negative errno value otherwise and rte_errno is set.
2151 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2152 const struct rte_flow_action *action,
2153 const uint64_t item_flags,
2154 struct rte_flow_error *error)
2158 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2160 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2161 return rte_flow_error_set(error, EINVAL,
2162 RTE_FLOW_ERROR_TYPE_ACTION,
2164 "no ipv4 item in pattern");
2170 * Validate the modify-header IPv6 address actions.
2172 * @param[in] action_flags
2173 * Holds the actions detected until now.
2175 * Pointer to the modify action.
2176 * @param[in] item_flags
2177 * Holds the items detected.
2179 * Pointer to error structure.
2182 * 0 on success, a negative errno value otherwise and rte_errno is set.
2185 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2186 const struct rte_flow_action *action,
2187 const uint64_t item_flags,
2188 struct rte_flow_error *error)
2192 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2194 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION,
2198 "no ipv6 item in pattern");
2204 * Validate the modify-header TP actions.
2206 * @param[in] action_flags
2207 * Holds the actions detected until now.
2209 * Pointer to the modify action.
2210 * @param[in] item_flags
2211 * Holds the items detected.
2213 * Pointer to error structure.
2216 * 0 on success, a negative errno value otherwise and rte_errno is set.
2219 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2220 const struct rte_flow_action *action,
2221 const uint64_t item_flags,
2222 struct rte_flow_error *error)
2226 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2228 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2229 return rte_flow_error_set(error, EINVAL,
2230 RTE_FLOW_ERROR_TYPE_ACTION,
2231 NULL, "no transport layer "
2238 * Validate the modify-header actions of increment/decrement
2239 * TCP Sequence-number.
2241 * @param[in] action_flags
2242 * Holds the actions detected until now.
2244 * Pointer to the modify action.
2245 * @param[in] item_flags
2246 * Holds the items detected.
2248 * Pointer to error structure.
2251 * 0 on success, a negative errno value otherwise and rte_errno is set.
2254 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2255 const struct rte_flow_action *action,
2256 const uint64_t item_flags,
2257 struct rte_flow_error *error)
2261 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2263 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2264 return rte_flow_error_set(error, EINVAL,
2265 RTE_FLOW_ERROR_TYPE_ACTION,
2266 NULL, "no TCP item in"
2268 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2269 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2270 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2271 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2272 return rte_flow_error_set(error, EINVAL,
2273 RTE_FLOW_ERROR_TYPE_ACTION,
2275 "cannot decrease and increase"
2276 " TCP sequence number"
2277 " at the same time");
2283 * Validate the modify-header actions of increment/decrement
2284 * TCP Acknowledgment number.
2286 * @param[in] action_flags
2287 * Holds the actions detected until now.
2289 * Pointer to the modify action.
2290 * @param[in] item_flags
2291 * Holds the items detected.
2293 * Pointer to error structure.
2296 * 0 on success, a negative errno value otherwise and rte_errno is set.
2299 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2300 const struct rte_flow_action *action,
2301 const uint64_t item_flags,
2302 struct rte_flow_error *error)
2306 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2308 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2309 return rte_flow_error_set(error, EINVAL,
2310 RTE_FLOW_ERROR_TYPE_ACTION,
2311 NULL, "no TCP item in"
2313 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2314 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2315 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2316 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2317 return rte_flow_error_set(error, EINVAL,
2318 RTE_FLOW_ERROR_TYPE_ACTION,
2320 "cannot decrease and increase"
2321 " TCP acknowledgment number"
2322 " at the same time");
2328 * Validate the modify-header TTL actions.
2330 * @param[in] action_flags
2331 * Holds the actions detected until now.
2333 * Pointer to the modify action.
2334 * @param[in] item_flags
2335 * Holds the items detected.
2337 * Pointer to error structure.
2340 * 0 on success, a negative errno value otherwise and rte_errno is set.
2343 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2344 const struct rte_flow_action *action,
2345 const uint64_t item_flags,
2346 struct rte_flow_error *error)
2350 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2352 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2353 return rte_flow_error_set(error, EINVAL,
2354 RTE_FLOW_ERROR_TYPE_ACTION,
2356 "no IP protocol in pattern");
2362 * Validate jump action.
2365 * Pointer to the jump action.
2366 * @param[in] action_flags
2367 * Holds the actions detected until now.
2368 * @param[in] attributes
2369 * Pointer to flow attributes
2370 * @param[in] external
2371 * Action belongs to flow rule created by request external to PMD.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2380 uint64_t action_flags,
2381 const struct rte_flow_attr *attributes,
2382 bool external, struct rte_flow_error *error)
2384 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2386 uint32_t target_group, table;
2389 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2390 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2391 return rte_flow_error_set(error, EINVAL,
2392 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2393 "can't have 2 fate actions in"
2396 return rte_flow_error_set(error, EINVAL,
2397 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2398 NULL, "action configuration not set");
2400 ((const struct rte_flow_action_jump *)action->conf)->group;
2401 ret = mlx5_flow_group_to_table(attributes, external, target_group,
2405 if (table >= max_group)
2406 return rte_flow_error_set(error, EINVAL,
2407 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2408 "target group index out of range");
2409 if (attributes->group >= target_group)
2410 return rte_flow_error_set(error, EINVAL,
2411 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2412 "target group must be higher than"
2413 " the current flow group");
2418 * Validate the port_id action.
2421 * Pointer to rte_eth_dev structure.
2422 * @param[in] action_flags
2423 * Bit-fields that holds the actions detected until now.
2425 * Port_id RTE action structure.
2427 * Attributes of flow that includes this action.
2429 * Pointer to error structure.
2432 * 0 on success, a negative errno value otherwise and rte_errno is set.
2435 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2436 uint64_t action_flags,
2437 const struct rte_flow_action *action,
2438 const struct rte_flow_attr *attr,
2439 struct rte_flow_error *error)
2441 const struct rte_flow_action_port_id *port_id;
2442 struct mlx5_priv *act_priv;
2443 struct mlx5_priv *dev_priv;
2446 if (!attr->transfer)
2447 return rte_flow_error_set(error, ENOTSUP,
2448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2450 "port id action is valid in transfer"
2452 if (!action || !action->conf)
2453 return rte_flow_error_set(error, ENOTSUP,
2454 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2456 "port id action parameters must be"
2458 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2459 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2460 return rte_flow_error_set(error, EINVAL,
2461 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2462 "can have only one fate actions in"
2464 dev_priv = mlx5_dev_to_eswitch_info(dev);
2466 return rte_flow_error_set(error, rte_errno,
2467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2469 "failed to obtain E-Switch info");
2470 port_id = action->conf;
2471 port = port_id->original ? dev->data->port_id : port_id->id;
2472 act_priv = mlx5_port_to_eswitch_info(port);
2474 return rte_flow_error_set
2476 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2477 "failed to obtain E-Switch port id for port");
2478 if (act_priv->domain_id != dev_priv->domain_id)
2479 return rte_flow_error_set
2481 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2482 "port does not belong to"
2483 " E-Switch being configured");
2488 * Find existing modify-header resource or create and register a new one.
2490 * @param dev[in, out]
2491 * Pointer to rte_eth_dev structure.
2492 * @param[in, out] resource
2493 * Pointer to modify-header resource.
2494 * @parm[in, out] dev_flow
2495 * Pointer to the dev_flow.
2497 * pointer to error structure.
2500 * 0 on success otherwise -errno and errno is set.
2503 flow_dv_modify_hdr_resource_register
2504 (struct rte_eth_dev *dev,
2505 struct mlx5_flow_dv_modify_hdr_resource *resource,
2506 struct mlx5_flow *dev_flow,
2507 struct rte_flow_error *error)
2509 struct mlx5_priv *priv = dev->data->dev_private;
2510 struct mlx5_ibv_shared *sh = priv->sh;
2511 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2512 struct mlx5dv_dr_domain *ns;
2514 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2515 ns = sh->fdb_domain;
2516 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2521 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2522 /* Lookup a matching resource from cache. */
2523 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2524 if (resource->ft_type == cache_resource->ft_type &&
2525 resource->actions_num == cache_resource->actions_num &&
2526 resource->flags == cache_resource->flags &&
2527 !memcmp((const void *)resource->actions,
2528 (const void *)cache_resource->actions,
2529 (resource->actions_num *
2530 sizeof(resource->actions[0])))) {
2531 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2532 (void *)cache_resource,
2533 rte_atomic32_read(&cache_resource->refcnt));
2534 rte_atomic32_inc(&cache_resource->refcnt);
2535 dev_flow->dv.modify_hdr = cache_resource;
2539 /* Register new modify-header resource. */
2540 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2541 if (!cache_resource)
2542 return rte_flow_error_set(error, ENOMEM,
2543 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2544 "cannot allocate resource memory");
2545 *cache_resource = *resource;
2546 cache_resource->verbs_action =
2547 mlx5_glue->dv_create_flow_action_modify_header
2548 (sh->ctx, cache_resource->ft_type,
2549 ns, cache_resource->flags,
2550 cache_resource->actions_num *
2551 sizeof(cache_resource->actions[0]),
2552 (uint64_t *)cache_resource->actions);
2553 if (!cache_resource->verbs_action) {
2554 rte_free(cache_resource);
2555 return rte_flow_error_set(error, ENOMEM,
2556 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2557 NULL, "cannot create action");
2559 rte_atomic32_init(&cache_resource->refcnt);
2560 rte_atomic32_inc(&cache_resource->refcnt);
2561 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2562 dev_flow->dv.modify_hdr = cache_resource;
2563 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2564 (void *)cache_resource,
2565 rte_atomic32_read(&cache_resource->refcnt));
2569 #define MLX5_CNT_CONTAINER_RESIZE 64
2572 * Get or create a flow counter.
2575 * Pointer to the Ethernet device structure.
2577 * Indicate if this counter is shared with other flows.
2579 * Counter identifier.
2582 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
2584 static struct mlx5_flow_counter *
2585 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2588 struct mlx5_priv *priv = dev->data->dev_private;
2589 struct mlx5_flow_counter *cnt = NULL;
2590 struct mlx5_devx_obj *dcs = NULL;
2592 if (!priv->config.devx) {
2593 rte_errno = ENOTSUP;
2597 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2598 if (cnt->shared && cnt->id == id) {
2604 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2607 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2609 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2613 struct mlx5_flow_counter tmpl = {
2619 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2621 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2627 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2632 * Release a flow counter.
2635 * Pointer to the Ethernet device structure.
2636 * @param[in] counter
2637 * Pointer to the counter handler.
2640 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2641 struct mlx5_flow_counter *counter)
2643 struct mlx5_priv *priv = dev->data->dev_private;
2647 if (--counter->ref_cnt == 0) {
2648 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2649 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2655 * Query a devx flow counter.
2658 * Pointer to the Ethernet device structure.
2660 * Pointer to the flow counter.
2662 * The statistics value of packets.
2664 * The statistics value of bytes.
2667 * 0 on success, otherwise a negative errno value and rte_errno is set.
2670 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2671 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2674 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2679 * Get a pool by a counter.
2682 * Pointer to the counter.
2687 static struct mlx5_flow_counter_pool *
2688 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2691 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2692 return (struct mlx5_flow_counter_pool *)cnt - 1;
2698 * Get a pool by devx counter ID.
2701 * Pointer to the counter container.
2703 * The counter devx ID.
2706 * The counter pool pointer if exists, NULL otherwise,
2708 static struct mlx5_flow_counter_pool *
2709 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2711 struct mlx5_flow_counter_pool *pool;
2713 TAILQ_FOREACH(pool, &cont->pool_list, next) {
2714 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2715 MLX5_COUNTERS_PER_POOL;
2717 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2724 * Allocate a new memory for the counter values wrapped by all the needed
2728 * Pointer to the Ethernet device structure.
2730 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2733 * The new memory management pointer on success, otherwise NULL and rte_errno
2736 static struct mlx5_counter_stats_mem_mng *
2737 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2739 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2740 (dev->data->dev_private))->sh;
2741 struct mlx5_devx_mkey_attr mkey_attr;
2742 struct mlx5_counter_stats_mem_mng *mem_mng;
2743 volatile struct flow_counter_stats *raw_data;
2744 int size = (sizeof(struct flow_counter_stats) *
2745 MLX5_COUNTERS_PER_POOL +
2746 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2747 sizeof(struct mlx5_counter_stats_mem_mng);
2748 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2755 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2756 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2757 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2758 IBV_ACCESS_LOCAL_WRITE);
2759 if (!mem_mng->umem) {
2764 mkey_attr.addr = (uintptr_t)mem;
2765 mkey_attr.size = size;
2766 mkey_attr.umem_id = mem_mng->umem->umem_id;
2767 mkey_attr.pd = sh->pdn;
2768 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2770 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2775 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2776 raw_data = (volatile struct flow_counter_stats *)mem;
2777 for (i = 0; i < raws_n; ++i) {
2778 mem_mng->raws[i].mem_mng = mem_mng;
2779 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2781 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2786 * Resize a counter container.
2789 * Pointer to the Ethernet device structure.
2791 * Whether the pool is for counter that was allocated by batch command.
2794 * The new container pointer on success, otherwise NULL and rte_errno is set.
2796 static struct mlx5_pools_container *
2797 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2799 struct mlx5_priv *priv = dev->data->dev_private;
2800 struct mlx5_pools_container *cont =
2801 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2802 struct mlx5_pools_container *new_cont =
2803 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2804 struct mlx5_counter_stats_mem_mng *mem_mng;
2805 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2806 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2809 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2810 /* The last resize still hasn't detected by the host thread. */
2814 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2815 if (!new_cont->pools) {
2820 memcpy(new_cont->pools, cont->pools, cont->n *
2821 sizeof(struct mlx5_flow_counter_pool *));
2822 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2823 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2825 rte_free(new_cont->pools);
2828 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2829 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2830 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2832 new_cont->n = resize;
2833 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2834 TAILQ_INIT(&new_cont->pool_list);
2835 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2836 new_cont->init_mem_mng = mem_mng;
2838 /* Flip the master container. */
2839 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2844 * Query a devx flow counter.
2847 * Pointer to the Ethernet device structure.
2849 * Pointer to the flow counter.
2851 * The statistics value of packets.
2853 * The statistics value of bytes.
2856 * 0 on success, otherwise a negative errno value and rte_errno is set.
2859 _flow_dv_query_count(struct rte_eth_dev *dev,
2860 struct mlx5_flow_counter *cnt, uint64_t *pkts,
2863 struct mlx5_priv *priv = dev->data->dev_private;
2864 struct mlx5_flow_counter_pool *pool =
2865 flow_dv_counter_pool_get(cnt);
2866 int offset = cnt - &pool->counters_raw[0];
2868 if (priv->counter_fallback)
2869 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2871 rte_spinlock_lock(&pool->sl);
2873 * The single counters allocation may allocate smaller ID than the
2874 * current allocated in parallel to the host reading.
2875 * In this case the new counter values must be reported as 0.
2877 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2881 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2882 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2884 rte_spinlock_unlock(&pool->sl);
2889 * Create and initialize a new counter pool.
2892 * Pointer to the Ethernet device structure.
2894 * The devX counter handle.
2896 * Whether the pool is for counter that was allocated by batch command.
2899 * A new pool pointer on success, NULL otherwise and rte_errno is set.
2901 static struct mlx5_flow_counter_pool *
2902 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
2905 struct mlx5_priv *priv = dev->data->dev_private;
2906 struct mlx5_flow_counter_pool *pool;
2907 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
2909 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
2912 if (cont->n == n_valid) {
2913 cont = flow_dv_container_resize(dev, batch);
2917 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
2918 sizeof(struct mlx5_flow_counter);
2919 pool = rte_calloc(__func__, 1, size, 0);
2924 pool->min_dcs = dcs;
2925 pool->raw = cont->init_mem_mng->raws + n_valid %
2926 MLX5_CNT_CONTAINER_RESIZE;
2927 pool->raw_hw = NULL;
2928 rte_spinlock_init(&pool->sl);
2930 * The generation of the new allocated counters in this pool is 0, 2 in
2931 * the pool generation makes all the counters valid for allocation.
2933 rte_atomic64_set(&pool->query_gen, 0x2);
2934 TAILQ_INIT(&pool->counters);
2935 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
2936 cont->pools[n_valid] = pool;
2937 /* Pool initialization must be updated before host thread access. */
2939 rte_atomic16_add(&cont->n_valid, 1);
2944 * Prepare a new counter and/or a new counter pool.
2947 * Pointer to the Ethernet device structure.
2948 * @param[out] cnt_free
2949 * Where to put the pointer of a new counter.
2951 * Whether the pool is for counter that was allocated by batch command.
2954 * The free counter pool pointer and @p cnt_free is set on success,
2955 * NULL otherwise and rte_errno is set.
2957 static struct mlx5_flow_counter_pool *
2958 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
2959 struct mlx5_flow_counter **cnt_free,
2962 struct mlx5_priv *priv = dev->data->dev_private;
2963 struct mlx5_flow_counter_pool *pool;
2964 struct mlx5_devx_obj *dcs = NULL;
2965 struct mlx5_flow_counter *cnt;
2969 /* bulk_bitmap must be 0 for single counter allocation. */
2970 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2973 pool = flow_dv_find_pool_by_id
2974 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
2976 pool = flow_dv_pool_create(dev, dcs, batch);
2978 mlx5_devx_cmd_destroy(dcs);
2981 } else if (dcs->id < pool->min_dcs->id) {
2982 rte_atomic64_set(&pool->a64_dcs,
2983 (int64_t)(uintptr_t)dcs);
2985 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
2986 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
2991 /* bulk_bitmap is in 128 counters units. */
2992 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
2993 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
2995 rte_errno = ENODATA;
2998 pool = flow_dv_pool_create(dev, dcs, batch);
3000 mlx5_devx_cmd_destroy(dcs);
3003 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3004 cnt = &pool->counters_raw[i];
3006 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3008 *cnt_free = &pool->counters_raw[0];
3013 * Search for existed shared counter.
3016 * Pointer to the relevant counter pool container.
3018 * The shared counter ID to search.
3021 * NULL if not existed, otherwise pointer to the shared counter.
3023 static struct mlx5_flow_counter *
3024 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3027 static struct mlx5_flow_counter *cnt;
3028 struct mlx5_flow_counter_pool *pool;
3031 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3032 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3033 cnt = &pool->counters_raw[i];
3034 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3042 * Allocate a flow counter.
3045 * Pointer to the Ethernet device structure.
3047 * Indicate if this counter is shared with other flows.
3049 * Counter identifier.
3051 * Counter flow group.
3054 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3056 static struct mlx5_flow_counter *
3057 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3060 struct mlx5_priv *priv = dev->data->dev_private;
3061 struct mlx5_flow_counter_pool *pool = NULL;
3062 struct mlx5_flow_counter *cnt_free = NULL;
3064 * Currently group 0 flow counter cannot be assigned to a flow if it is
3065 * not the first one in the batch counter allocation, so it is better
3066 * to allocate counters one by one for these flows in a separate
3068 * A counter can be shared between different groups so need to take
3069 * shared counters from the single container.
3071 uint32_t batch = (group && !shared) ? 1 : 0;
3072 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3075 if (priv->counter_fallback)
3076 return flow_dv_counter_alloc_fallback(dev, shared, id);
3077 if (!priv->config.devx) {
3078 rte_errno = ENOTSUP;
3082 cnt_free = flow_dv_counter_shared_search(cont, id);
3084 if (cnt_free->ref_cnt + 1 == 0) {
3088 cnt_free->ref_cnt++;
3092 /* Pools which has a free counters are in the start. */
3093 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3095 * The free counter reset values must be updated between the
3096 * counter release to the counter allocation, so, at least one
3097 * query must be done in this time. ensure it by saving the
3098 * query generation in the release time.
3099 * The free list is sorted according to the generation - so if
3100 * the first one is not updated, all the others are not
3103 cnt_free = TAILQ_FIRST(&pool->counters);
3104 if (cnt_free && cnt_free->query_gen + 1 <
3105 rte_atomic64_read(&pool->query_gen))
3110 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3114 cnt_free->batch = batch;
3115 /* Create a DV counter action only in the first time usage. */
3116 if (!cnt_free->action) {
3118 struct mlx5_devx_obj *dcs;
3121 offset = cnt_free - &pool->counters_raw[0];
3122 dcs = pool->min_dcs;
3125 dcs = cnt_free->dcs;
3127 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3129 if (!cnt_free->action) {
3134 /* Update the counter reset values. */
3135 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3138 cnt_free->shared = shared;
3139 cnt_free->ref_cnt = 1;
3141 if (!priv->sh->cmng.query_thread_on)
3142 /* Start the asynchronous batch query by the host thread. */
3143 mlx5_set_query_alarm(priv->sh);
3144 TAILQ_REMOVE(&pool->counters, cnt_free, next);
3145 if (TAILQ_EMPTY(&pool->counters)) {
3146 /* Move the pool to the end of the container pool list. */
3147 TAILQ_REMOVE(&cont->pool_list, pool, next);
3148 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3154 * Release a flow counter.
3157 * Pointer to the Ethernet device structure.
3158 * @param[in] counter
3159 * Pointer to the counter handler.
3162 flow_dv_counter_release(struct rte_eth_dev *dev,
3163 struct mlx5_flow_counter *counter)
3165 struct mlx5_priv *priv = dev->data->dev_private;
3169 if (priv->counter_fallback) {
3170 flow_dv_counter_release_fallback(dev, counter);
3173 if (--counter->ref_cnt == 0) {
3174 struct mlx5_flow_counter_pool *pool =
3175 flow_dv_counter_pool_get(counter);
3177 /* Put the counter in the end - the last updated one. */
3178 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3179 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3184 * Verify the @p attributes will be correctly understood by the NIC and store
3185 * them in the @p flow if everything is correct.
3188 * Pointer to dev struct.
3189 * @param[in] attributes
3190 * Pointer to flow attributes
3191 * @param[in] external
3192 * This flow rule is created by request external to PMD.
3194 * Pointer to error structure.
3197 * 0 on success, a negative errno value otherwise and rte_errno is set.
3200 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3201 const struct rte_flow_attr *attributes,
3202 bool external __rte_unused,
3203 struct rte_flow_error *error)
3205 struct mlx5_priv *priv = dev->data->dev_private;
3206 uint32_t priority_max = priv->config.flow_prio - 1;
3208 #ifndef HAVE_MLX5DV_DR
3209 if (attributes->group)
3210 return rte_flow_error_set(error, ENOTSUP,
3211 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3213 "groups are not supported");
3215 uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3220 ret = mlx5_flow_group_to_table(attributes, external,
3225 if (table >= max_group)
3226 return rte_flow_error_set(error, EINVAL,
3227 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3228 "group index out of range");
3230 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3231 attributes->priority >= priority_max)
3232 return rte_flow_error_set(error, ENOTSUP,
3233 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3235 "priority out of range");
3236 if (attributes->transfer) {
3237 if (!priv->config.dv_esw_en)
3238 return rte_flow_error_set
3240 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3241 "E-Switch dr is not supported");
3242 if (!(priv->representor || priv->master))
3243 return rte_flow_error_set
3244 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3245 NULL, "E-Switch configuration can only be"
3246 " done by a master or a representor device");
3247 if (attributes->egress)
3248 return rte_flow_error_set
3250 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3251 "egress is not supported");
3253 if (!(attributes->egress ^ attributes->ingress))
3254 return rte_flow_error_set(error, ENOTSUP,
3255 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3256 "must specify exactly one of "
3257 "ingress or egress");
3262 * Internal validation function. For validating both actions and items.
3265 * Pointer to the rte_eth_dev structure.
3267 * Pointer to the flow attributes.
3269 * Pointer to the list of items.
3270 * @param[in] actions
3271 * Pointer to the list of actions.
3272 * @param[in] external
3273 * This flow rule is created by request external to PMD.
3275 * Pointer to the error structure.
3278 * 0 on success, a negative errno value otherwise and rte_errno is set.
3281 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3282 const struct rte_flow_item items[],
3283 const struct rte_flow_action actions[],
3284 bool external, struct rte_flow_error *error)
3287 uint64_t action_flags = 0;
3288 uint64_t item_flags = 0;
3289 uint64_t last_item = 0;
3290 uint8_t next_protocol = 0xff;
3292 const struct rte_flow_item *gre_item = NULL;
3293 struct rte_flow_item_tcp nic_tcp_mask = {
3296 .src_port = RTE_BE16(UINT16_MAX),
3297 .dst_port = RTE_BE16(UINT16_MAX),
3303 ret = flow_dv_validate_attributes(dev, attr, external, error);
3306 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3307 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3308 switch (items->type) {
3309 case RTE_FLOW_ITEM_TYPE_VOID:
3311 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3312 ret = flow_dv_validate_item_port_id
3313 (dev, items, attr, item_flags, error);
3316 last_item = MLX5_FLOW_ITEM_PORT_ID;
3318 case RTE_FLOW_ITEM_TYPE_ETH:
3319 ret = mlx5_flow_validate_item_eth(items, item_flags,
3323 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3324 MLX5_FLOW_LAYER_OUTER_L2;
3326 case RTE_FLOW_ITEM_TYPE_VLAN:
3327 ret = mlx5_flow_validate_item_vlan(items, item_flags,
3331 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3332 MLX5_FLOW_LAYER_OUTER_VLAN;
3334 case RTE_FLOW_ITEM_TYPE_IPV4:
3335 mlx5_flow_tunnel_ip_check(items, next_protocol,
3336 &item_flags, &tunnel);
3337 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3341 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3342 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3343 if (items->mask != NULL &&
3344 ((const struct rte_flow_item_ipv4 *)
3345 items->mask)->hdr.next_proto_id) {
3347 ((const struct rte_flow_item_ipv4 *)
3348 (items->spec))->hdr.next_proto_id;
3350 ((const struct rte_flow_item_ipv4 *)
3351 (items->mask))->hdr.next_proto_id;
3353 /* Reset for inner layer. */
3354 next_protocol = 0xff;
3357 case RTE_FLOW_ITEM_TYPE_IPV6:
3358 mlx5_flow_tunnel_ip_check(items, next_protocol,
3359 &item_flags, &tunnel);
3360 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3364 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3365 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3366 if (items->mask != NULL &&
3367 ((const struct rte_flow_item_ipv6 *)
3368 items->mask)->hdr.proto) {
3370 ((const struct rte_flow_item_ipv6 *)
3371 items->spec)->hdr.proto;
3373 ((const struct rte_flow_item_ipv6 *)
3374 items->mask)->hdr.proto;
3376 /* Reset for inner layer. */
3377 next_protocol = 0xff;
3380 case RTE_FLOW_ITEM_TYPE_TCP:
3381 ret = mlx5_flow_validate_item_tcp
3388 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3389 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3391 case RTE_FLOW_ITEM_TYPE_UDP:
3392 ret = mlx5_flow_validate_item_udp(items, item_flags,
3397 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3398 MLX5_FLOW_LAYER_OUTER_L4_UDP;
3400 case RTE_FLOW_ITEM_TYPE_GRE:
3401 ret = mlx5_flow_validate_item_gre(items, item_flags,
3402 next_protocol, error);
3406 last_item = MLX5_FLOW_LAYER_GRE;
3408 case RTE_FLOW_ITEM_TYPE_NVGRE:
3409 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3414 last_item = MLX5_FLOW_LAYER_NVGRE;
3416 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3417 ret = mlx5_flow_validate_item_gre_key
3418 (items, item_flags, gre_item, error);
3421 last_item = MLX5_FLOW_LAYER_GRE_KEY;
3423 case RTE_FLOW_ITEM_TYPE_VXLAN:
3424 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3428 last_item = MLX5_FLOW_LAYER_VXLAN;
3430 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3431 ret = mlx5_flow_validate_item_vxlan_gpe(items,
3436 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3438 case RTE_FLOW_ITEM_TYPE_GENEVE:
3439 ret = mlx5_flow_validate_item_geneve(items,
3444 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3446 case RTE_FLOW_ITEM_TYPE_MPLS:
3447 ret = mlx5_flow_validate_item_mpls(dev, items,
3452 last_item = MLX5_FLOW_LAYER_MPLS;
3454 case RTE_FLOW_ITEM_TYPE_META:
3455 ret = flow_dv_validate_item_meta(dev, items, attr,
3459 last_item = MLX5_FLOW_ITEM_METADATA;
3461 case RTE_FLOW_ITEM_TYPE_ICMP:
3462 ret = mlx5_flow_validate_item_icmp(items, item_flags,
3467 last_item = MLX5_FLOW_LAYER_ICMP;
3469 case RTE_FLOW_ITEM_TYPE_ICMP6:
3470 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3475 last_item = MLX5_FLOW_LAYER_ICMP6;
3478 return rte_flow_error_set(error, ENOTSUP,
3479 RTE_FLOW_ERROR_TYPE_ITEM,
3480 NULL, "item not supported");
3482 item_flags |= last_item;
3484 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3485 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3486 return rte_flow_error_set(error, ENOTSUP,
3487 RTE_FLOW_ERROR_TYPE_ACTION,
3488 actions, "too many actions");
3489 switch (actions->type) {
3490 case RTE_FLOW_ACTION_TYPE_VOID:
3492 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3493 ret = flow_dv_validate_action_port_id(dev,
3500 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3503 case RTE_FLOW_ACTION_TYPE_FLAG:
3504 ret = mlx5_flow_validate_action_flag(action_flags,
3508 action_flags |= MLX5_FLOW_ACTION_FLAG;
3511 case RTE_FLOW_ACTION_TYPE_MARK:
3512 ret = mlx5_flow_validate_action_mark(actions,
3517 action_flags |= MLX5_FLOW_ACTION_MARK;
3520 case RTE_FLOW_ACTION_TYPE_DROP:
3521 ret = mlx5_flow_validate_action_drop(action_flags,
3525 action_flags |= MLX5_FLOW_ACTION_DROP;
3528 case RTE_FLOW_ACTION_TYPE_QUEUE:
3529 ret = mlx5_flow_validate_action_queue(actions,
3534 action_flags |= MLX5_FLOW_ACTION_QUEUE;
3537 case RTE_FLOW_ACTION_TYPE_RSS:
3538 ret = mlx5_flow_validate_action_rss(actions,
3544 action_flags |= MLX5_FLOW_ACTION_RSS;
3547 case RTE_FLOW_ACTION_TYPE_COUNT:
3548 ret = flow_dv_validate_action_count(dev, error);
3551 action_flags |= MLX5_FLOW_ACTION_COUNT;
3554 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3555 if (flow_dv_validate_action_pop_vlan(dev,
3561 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3564 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3565 ret = flow_dv_validate_action_push_vlan(action_flags,
3570 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3573 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3574 ret = flow_dv_validate_action_set_vlan_pcp
3575 (action_flags, actions, error);
3578 /* Count PCP with push_vlan command. */
3580 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3581 ret = flow_dv_validate_action_set_vlan_vid
3582 (item_flags, actions, error);
3585 /* Count VID with push_vlan command. */
3587 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3588 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3589 ret = flow_dv_validate_action_l2_encap(action_flags,
3594 action_flags |= actions->type ==
3595 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3596 MLX5_FLOW_ACTION_VXLAN_ENCAP :
3597 MLX5_FLOW_ACTION_NVGRE_ENCAP;
3600 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3601 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3602 ret = flow_dv_validate_action_l2_decap(action_flags,
3606 action_flags |= actions->type ==
3607 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3608 MLX5_FLOW_ACTION_VXLAN_DECAP :
3609 MLX5_FLOW_ACTION_NVGRE_DECAP;
3612 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3613 ret = flow_dv_validate_action_raw_encap(action_flags,
3618 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3621 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3622 ret = flow_dv_validate_action_raw_decap(action_flags,
3627 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3630 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3631 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3632 ret = flow_dv_validate_action_modify_mac(action_flags,
3638 /* Count all modify-header actions as one action. */
3639 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3641 action_flags |= actions->type ==
3642 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3643 MLX5_FLOW_ACTION_SET_MAC_SRC :
3644 MLX5_FLOW_ACTION_SET_MAC_DST;
3647 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3648 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3649 ret = flow_dv_validate_action_modify_ipv4(action_flags,
3655 /* Count all modify-header actions as one action. */
3656 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3658 action_flags |= actions->type ==
3659 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3660 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3661 MLX5_FLOW_ACTION_SET_IPV4_DST;
3663 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3664 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3665 ret = flow_dv_validate_action_modify_ipv6(action_flags,
3671 /* Count all modify-header actions as one action. */
3672 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3674 action_flags |= actions->type ==
3675 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3676 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3677 MLX5_FLOW_ACTION_SET_IPV6_DST;
3679 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3680 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3681 ret = flow_dv_validate_action_modify_tp(action_flags,
3687 /* Count all modify-header actions as one action. */
3688 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3690 action_flags |= actions->type ==
3691 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3692 MLX5_FLOW_ACTION_SET_TP_SRC :
3693 MLX5_FLOW_ACTION_SET_TP_DST;
3695 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3696 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3697 ret = flow_dv_validate_action_modify_ttl(action_flags,
3703 /* Count all modify-header actions as one action. */
3704 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3706 action_flags |= actions->type ==
3707 RTE_FLOW_ACTION_TYPE_SET_TTL ?
3708 MLX5_FLOW_ACTION_SET_TTL :
3709 MLX5_FLOW_ACTION_DEC_TTL;
3711 case RTE_FLOW_ACTION_TYPE_JUMP:
3712 ret = flow_dv_validate_action_jump(actions,
3719 action_flags |= MLX5_FLOW_ACTION_JUMP;
3721 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3722 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3723 ret = flow_dv_validate_action_modify_tcp_seq
3730 /* Count all modify-header actions as one action. */
3731 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3733 action_flags |= actions->type ==
3734 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3735 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3736 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3738 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3739 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3740 ret = flow_dv_validate_action_modify_tcp_ack
3747 /* Count all modify-header actions as one action. */
3748 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3750 action_flags |= actions->type ==
3751 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3752 MLX5_FLOW_ACTION_INC_TCP_ACK :
3753 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3756 return rte_flow_error_set(error, ENOTSUP,
3757 RTE_FLOW_ERROR_TYPE_ACTION,
3759 "action not supported");
3762 if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3763 (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3764 return rte_flow_error_set(error, ENOTSUP,
3765 RTE_FLOW_ERROR_TYPE_ACTION,
3767 "can't have vxlan and vlan"
3768 " actions in the same rule");
3769 /* Eswitch has few restrictions on using items and actions */
3770 if (attr->transfer) {
3771 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3772 return rte_flow_error_set(error, ENOTSUP,
3773 RTE_FLOW_ERROR_TYPE_ACTION,
3775 "unsupported action FLAG");
3776 if (action_flags & MLX5_FLOW_ACTION_MARK)
3777 return rte_flow_error_set(error, ENOTSUP,
3778 RTE_FLOW_ERROR_TYPE_ACTION,
3780 "unsupported action MARK");
3781 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3782 return rte_flow_error_set(error, ENOTSUP,
3783 RTE_FLOW_ERROR_TYPE_ACTION,
3785 "unsupported action QUEUE");
3786 if (action_flags & MLX5_FLOW_ACTION_RSS)
3787 return rte_flow_error_set(error, ENOTSUP,
3788 RTE_FLOW_ERROR_TYPE_ACTION,
3790 "unsupported action RSS");
3791 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3792 return rte_flow_error_set(error, EINVAL,
3793 RTE_FLOW_ERROR_TYPE_ACTION,
3795 "no fate action is found");
3797 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3798 return rte_flow_error_set(error, EINVAL,
3799 RTE_FLOW_ERROR_TYPE_ACTION,
3801 "no fate action is found");
3807 * Internal preparation function. Allocates the DV flow size,
3808 * this size is constant.
3811 * Pointer to the flow attributes.
3813 * Pointer to the list of items.
3814 * @param[in] actions
3815 * Pointer to the list of actions.
3817 * Pointer to the error structure.
3820 * Pointer to mlx5_flow object on success,
3821 * otherwise NULL and rte_errno is set.
3823 static struct mlx5_flow *
3824 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3825 const struct rte_flow_item items[] __rte_unused,
3826 const struct rte_flow_action actions[] __rte_unused,
3827 struct rte_flow_error *error)
3829 uint32_t size = sizeof(struct mlx5_flow);
3830 struct mlx5_flow *flow;
3832 flow = rte_calloc(__func__, 1, size, 0);
3834 rte_flow_error_set(error, ENOMEM,
3835 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3836 "not enough memory to create flow");
3839 flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3845 * Sanity check for match mask and value. Similar to check_valid_spec() in
3846 * kernel driver. If unmasked bit is present in value, it returns failure.
3849 * pointer to match mask buffer.
3850 * @param match_value
3851 * pointer to match value buffer.
3854 * 0 if valid, -EINVAL otherwise.
3857 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3859 uint8_t *m = match_mask;
3860 uint8_t *v = match_value;
3863 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3866 "match_value differs from match_criteria"
3867 " %p[%u] != %p[%u]",
3868 match_value, i, match_mask, i);
3877 * Add Ethernet item to matcher and to the value.
3879 * @param[in, out] matcher
3881 * @param[in, out] key
3882 * Flow matcher value.
3884 * Flow pattern to translate.
3886 * Item is inner pattern.
3889 flow_dv_translate_item_eth(void *matcher, void *key,
3890 const struct rte_flow_item *item, int inner)
3892 const struct rte_flow_item_eth *eth_m = item->mask;
3893 const struct rte_flow_item_eth *eth_v = item->spec;
3894 const struct rte_flow_item_eth nic_mask = {
3895 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3896 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
3897 .type = RTE_BE16(0xffff),
3909 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3911 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3913 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3915 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3917 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
3918 ð_m->dst, sizeof(eth_m->dst));
3919 /* The value must be in the range of the mask. */
3920 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
3921 for (i = 0; i < sizeof(eth_m->dst); ++i)
3922 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
3923 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
3924 ð_m->src, sizeof(eth_m->src));
3925 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
3926 /* The value must be in the range of the mask. */
3927 for (i = 0; i < sizeof(eth_m->dst); ++i)
3928 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
3929 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3930 rte_be_to_cpu_16(eth_m->type));
3931 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
3932 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
3936 * Add VLAN item to matcher and to the value.
3938 * @param[in, out] dev_flow
3940 * @param[in, out] matcher
3942 * @param[in, out] key
3943 * Flow matcher value.
3945 * Flow pattern to translate.
3947 * Item is inner pattern.
3950 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
3951 void *matcher, void *key,
3952 const struct rte_flow_item *item,
3955 const struct rte_flow_item_vlan *vlan_m = item->mask;
3956 const struct rte_flow_item_vlan *vlan_v = item->spec;
3965 vlan_m = &rte_flow_item_vlan_mask;
3967 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3969 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
3971 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
3973 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
3975 * This is workaround, masks are not supported,
3976 * and pre-validated.
3978 dev_flow->dv.vf_vlan.tag =
3979 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
3981 tci_m = rte_be_to_cpu_16(vlan_m->tci);
3982 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
3983 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
3984 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
3985 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
3986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
3987 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
3988 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
3989 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
3990 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
3991 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
3992 rte_be_to_cpu_16(vlan_m->inner_type));
3993 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
3994 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
3998 * Add IPV4 item to matcher and to the value.
4000 * @param[in, out] matcher
4002 * @param[in, out] key
4003 * Flow matcher value.
4005 * Flow pattern to translate.
4007 * Item is inner pattern.
4009 * The group to insert the rule.
4012 flow_dv_translate_item_ipv4(void *matcher, void *key,
4013 const struct rte_flow_item *item,
4014 int inner, uint32_t group)
4016 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4017 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4018 const struct rte_flow_item_ipv4 nic_mask = {
4020 .src_addr = RTE_BE32(0xffffffff),
4021 .dst_addr = RTE_BE32(0xffffffff),
4022 .type_of_service = 0xff,
4023 .next_proto_id = 0xff,
4033 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4035 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4037 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4039 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4042 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4044 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4045 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4050 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4051 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4052 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4053 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4054 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4055 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4056 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4057 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4058 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4059 src_ipv4_src_ipv6.ipv4_layout.ipv4);
4060 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4061 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4062 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4063 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4064 ipv4_m->hdr.type_of_service);
4065 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4066 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4067 ipv4_m->hdr.type_of_service >> 2);
4068 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4069 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4070 ipv4_m->hdr.next_proto_id);
4071 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4072 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4076 * Add IPV6 item to matcher and to the value.
4078 * @param[in, out] matcher
4080 * @param[in, out] key
4081 * Flow matcher value.
4083 * Flow pattern to translate.
4085 * Item is inner pattern.
4087 * The group to insert the rule.
4090 flow_dv_translate_item_ipv6(void *matcher, void *key,
4091 const struct rte_flow_item *item,
4092 int inner, uint32_t group)
4094 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4095 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4096 const struct rte_flow_item_ipv6 nic_mask = {
4099 "\xff\xff\xff\xff\xff\xff\xff\xff"
4100 "\xff\xff\xff\xff\xff\xff\xff\xff",
4102 "\xff\xff\xff\xff\xff\xff\xff\xff"
4103 "\xff\xff\xff\xff\xff\xff\xff\xff",
4104 .vtc_flow = RTE_BE32(0xffffffff),
4111 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4112 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4121 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4123 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4125 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4127 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4130 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4132 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4133 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4138 size = sizeof(ipv6_m->hdr.dst_addr);
4139 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4140 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4141 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4142 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4143 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4144 for (i = 0; i < size; ++i)
4145 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4146 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4147 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4148 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4149 src_ipv4_src_ipv6.ipv6_layout.ipv6);
4150 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4151 for (i = 0; i < size; ++i)
4152 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4154 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4155 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4156 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4157 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4158 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4159 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4162 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4164 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4167 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4169 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4173 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4175 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4176 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4180 * Add TCP item to matcher and to the value.
4182 * @param[in, out] matcher
4184 * @param[in, out] key
4185 * Flow matcher value.
4187 * Flow pattern to translate.
4189 * Item is inner pattern.
4192 flow_dv_translate_item_tcp(void *matcher, void *key,
4193 const struct rte_flow_item *item,
4196 const struct rte_flow_item_tcp *tcp_m = item->mask;
4197 const struct rte_flow_item_tcp *tcp_v = item->spec;
4202 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4204 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4206 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4208 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4210 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4215 tcp_m = &rte_flow_item_tcp_mask;
4216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4217 rte_be_to_cpu_16(tcp_m->hdr.src_port));
4218 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4219 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4220 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4221 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4222 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4223 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4224 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4225 tcp_m->hdr.tcp_flags);
4226 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4227 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4231 * Add UDP item to matcher and to the value.
4233 * @param[in, out] matcher
4235 * @param[in, out] key
4236 * Flow matcher value.
4238 * Flow pattern to translate.
4240 * Item is inner pattern.
4243 flow_dv_translate_item_udp(void *matcher, void *key,
4244 const struct rte_flow_item *item,
4247 const struct rte_flow_item_udp *udp_m = item->mask;
4248 const struct rte_flow_item_udp *udp_v = item->spec;
4253 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4255 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4257 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4259 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4266 udp_m = &rte_flow_item_udp_mask;
4267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4268 rte_be_to_cpu_16(udp_m->hdr.src_port));
4269 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4270 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4271 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4272 rte_be_to_cpu_16(udp_m->hdr.dst_port));
4273 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4274 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4278 * Add GRE optional Key item to matcher and to the value.
4280 * @param[in, out] matcher
4282 * @param[in, out] key
4283 * Flow matcher value.
4285 * Flow pattern to translate.
4287 * Item is inner pattern.
4290 flow_dv_translate_item_gre_key(void *matcher, void *key,
4291 const struct rte_flow_item *item)
4293 const rte_be32_t *key_m = item->mask;
4294 const rte_be32_t *key_v = item->spec;
4295 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4296 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4297 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4302 key_m = &gre_key_default_mask;
4303 /* GRE K bit must be on and should already be validated */
4304 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4305 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4306 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4307 rte_be_to_cpu_32(*key_m) >> 8);
4308 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4309 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4310 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4311 rte_be_to_cpu_32(*key_m) & 0xFF);
4312 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4313 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4317 * Add GRE item to matcher and to the value.
4319 * @param[in, out] matcher
4321 * @param[in, out] key
4322 * Flow matcher value.
4324 * Flow pattern to translate.
4326 * Item is inner pattern.
4329 flow_dv_translate_item_gre(void *matcher, void *key,
4330 const struct rte_flow_item *item,
4333 const struct rte_flow_item_gre *gre_m = item->mask;
4334 const struct rte_flow_item_gre *gre_v = item->spec;
4337 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4338 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4345 uint16_t s_present:1;
4346 uint16_t k_present:1;
4347 uint16_t rsvd_bit1:1;
4348 uint16_t c_present:1;
4352 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4355 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4357 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4359 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4361 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4363 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4364 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4368 gre_m = &rte_flow_item_gre_mask;
4369 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4370 rte_be_to_cpu_16(gre_m->protocol));
4371 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4372 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4373 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4374 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4375 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4376 gre_crks_rsvd0_ver_m.c_present);
4377 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4378 gre_crks_rsvd0_ver_v.c_present &
4379 gre_crks_rsvd0_ver_m.c_present);
4380 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4381 gre_crks_rsvd0_ver_m.k_present);
4382 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4383 gre_crks_rsvd0_ver_v.k_present &
4384 gre_crks_rsvd0_ver_m.k_present);
4385 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4386 gre_crks_rsvd0_ver_m.s_present);
4387 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4388 gre_crks_rsvd0_ver_v.s_present &
4389 gre_crks_rsvd0_ver_m.s_present);
4393 * Add NVGRE item to matcher and to the value.
4395 * @param[in, out] matcher
4397 * @param[in, out] key
4398 * Flow matcher value.
4400 * Flow pattern to translate.
4402 * Item is inner pattern.
4405 flow_dv_translate_item_nvgre(void *matcher, void *key,
4406 const struct rte_flow_item *item,
4409 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4410 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4411 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4412 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4413 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4414 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4420 /* For NVGRE, GRE header fields must be set with defined values. */
4421 const struct rte_flow_item_gre gre_spec = {
4422 .c_rsvd0_ver = RTE_BE16(0x2000),
4423 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4425 const struct rte_flow_item_gre gre_mask = {
4426 .c_rsvd0_ver = RTE_BE16(0xB000),
4427 .protocol = RTE_BE16(UINT16_MAX),
4429 const struct rte_flow_item gre_item = {
4434 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4438 nvgre_m = &rte_flow_item_nvgre_mask;
4439 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4440 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4441 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4442 memcpy(gre_key_m, tni_flow_id_m, size);
4443 for (i = 0; i < size; ++i)
4444 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4448 * Add VXLAN item to matcher and to the value.
4450 * @param[in, out] matcher
4452 * @param[in, out] key
4453 * Flow matcher value.
4455 * Flow pattern to translate.
4457 * Item is inner pattern.
4460 flow_dv_translate_item_vxlan(void *matcher, void *key,
4461 const struct rte_flow_item *item,
4464 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4465 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4468 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4469 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4477 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4479 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4481 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4483 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4485 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4486 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4487 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4494 vxlan_m = &rte_flow_item_vxlan_mask;
4495 size = sizeof(vxlan_m->vni);
4496 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4497 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4498 memcpy(vni_m, vxlan_m->vni, size);
4499 for (i = 0; i < size; ++i)
4500 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4504 * Add Geneve item to matcher and to the value.
4506 * @param[in, out] matcher
4508 * @param[in, out] key
4509 * Flow matcher value.
4511 * Flow pattern to translate.
4513 * Item is inner pattern.
4517 flow_dv_translate_item_geneve(void *matcher, void *key,
4518 const struct rte_flow_item *item, int inner)
4520 const struct rte_flow_item_geneve *geneve_m = item->mask;
4521 const struct rte_flow_item_geneve *geneve_v = item->spec;
4524 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4525 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4534 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4536 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4538 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4540 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4542 dport = MLX5_UDP_PORT_GENEVE;
4543 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4544 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4545 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4550 geneve_m = &rte_flow_item_geneve_mask;
4551 size = sizeof(geneve_m->vni);
4552 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4553 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4554 memcpy(vni_m, geneve_m->vni, size);
4555 for (i = 0; i < size; ++i)
4556 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4557 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4558 rte_be_to_cpu_16(geneve_m->protocol));
4559 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4560 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4561 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4562 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4563 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4564 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4565 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4566 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4567 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4568 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4569 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4570 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4571 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4575 * Add MPLS item to matcher and to the value.
4577 * @param[in, out] matcher
4579 * @param[in, out] key
4580 * Flow matcher value.
4582 * Flow pattern to translate.
4583 * @param[in] prev_layer
4584 * The protocol layer indicated in previous item.
4586 * Item is inner pattern.
4589 flow_dv_translate_item_mpls(void *matcher, void *key,
4590 const struct rte_flow_item *item,
4591 uint64_t prev_layer,
4594 const uint32_t *in_mpls_m = item->mask;
4595 const uint32_t *in_mpls_v = item->spec;
4596 uint32_t *out_mpls_m = 0;
4597 uint32_t *out_mpls_v = 0;
4598 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4599 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4600 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4602 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4603 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4604 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4606 switch (prev_layer) {
4607 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4608 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4609 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4610 MLX5_UDP_PORT_MPLS);
4612 case MLX5_FLOW_LAYER_GRE:
4613 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4614 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4615 RTE_ETHER_TYPE_MPLS);
4618 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4619 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4626 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4627 switch (prev_layer) {
4628 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4630 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4631 outer_first_mpls_over_udp);
4633 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4634 outer_first_mpls_over_udp);
4636 case MLX5_FLOW_LAYER_GRE:
4638 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4639 outer_first_mpls_over_gre);
4641 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4642 outer_first_mpls_over_gre);
4645 /* Inner MPLS not over GRE is not supported. */
4648 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4652 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4658 if (out_mpls_m && out_mpls_v) {
4659 *out_mpls_m = *in_mpls_m;
4660 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4665 * Add META item to matcher
4667 * @param[in, out] matcher
4669 * @param[in, out] key
4670 * Flow matcher value.
4672 * Flow pattern to translate.
4674 * Item is inner pattern.
4677 flow_dv_translate_item_meta(void *matcher, void *key,
4678 const struct rte_flow_item *item)
4680 const struct rte_flow_item_meta *meta_m;
4681 const struct rte_flow_item_meta *meta_v;
4683 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4685 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4687 meta_m = (const void *)item->mask;
4689 meta_m = &rte_flow_item_meta_mask;
4690 meta_v = (const void *)item->spec;
4692 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4693 rte_be_to_cpu_32(meta_m->data));
4694 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4695 rte_be_to_cpu_32(meta_v->data & meta_m->data));
4700 * Add vport metadata Reg C0 item to matcher
4702 * @param[in, out] matcher
4704 * @param[in, out] key
4705 * Flow matcher value.
4707 * Flow pattern to translate.
4710 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4711 uint32_t value, uint32_t mask)
4714 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4716 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4718 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4719 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4723 * Add source vport match to the specified matcher.
4725 * @param[in, out] matcher
4727 * @param[in, out] key
4728 * Flow matcher value.
4730 * Source vport value to match
4735 flow_dv_translate_item_source_vport(void *matcher, void *key,
4736 int16_t port, uint16_t mask)
4738 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4739 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4741 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4742 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4746 * Translate port-id item to eswitch match on port-id.
4749 * The devich to configure through.
4750 * @param[in, out] matcher
4752 * @param[in, out] key
4753 * Flow matcher value.
4755 * Flow pattern to translate.
4758 * 0 on success, a negative errno value otherwise.
4761 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4762 void *key, const struct rte_flow_item *item)
4764 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4765 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4766 struct mlx5_priv *priv;
4769 mask = pid_m ? pid_m->id : 0xffff;
4770 id = pid_v ? pid_v->id : dev->data->port_id;
4771 priv = mlx5_port_to_eswitch_info(id);
4774 /* Translate to vport field or to metadata, depending on mode. */
4775 if (priv->vport_meta_mask)
4776 flow_dv_translate_item_meta_vport(matcher, key,
4777 priv->vport_meta_tag,
4778 priv->vport_meta_mask);
4780 flow_dv_translate_item_source_vport(matcher, key,
4781 priv->vport_id, mask);
4786 * Add ICMP6 item to matcher and to the value.
4788 * @param[in, out] matcher
4790 * @param[in, out] key
4791 * Flow matcher value.
4793 * Flow pattern to translate.
4795 * Item is inner pattern.
4798 flow_dv_translate_item_icmp6(void *matcher, void *key,
4799 const struct rte_flow_item *item,
4802 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
4803 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
4806 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4808 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4810 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4812 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4814 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4816 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4818 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4819 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
4823 icmp6_m = &rte_flow_item_icmp6_mask;
4824 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
4825 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
4826 icmp6_v->type & icmp6_m->type);
4827 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
4828 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
4829 icmp6_v->code & icmp6_m->code);
4833 * Add ICMP item to matcher and to the value.
4835 * @param[in, out] matcher
4837 * @param[in, out] key
4838 * Flow matcher value.
4840 * Flow pattern to translate.
4842 * Item is inner pattern.
4845 flow_dv_translate_item_icmp(void *matcher, void *key,
4846 const struct rte_flow_item *item,
4849 const struct rte_flow_item_icmp *icmp_m = item->mask;
4850 const struct rte_flow_item_icmp *icmp_v = item->spec;
4853 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
4855 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
4857 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4859 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4861 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4863 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4865 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
4866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
4870 icmp_m = &rte_flow_item_icmp_mask;
4871 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
4872 icmp_m->hdr.icmp_type);
4873 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
4874 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
4875 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
4876 icmp_m->hdr.icmp_code);
4877 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
4878 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
4881 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
4883 #define HEADER_IS_ZERO(match_criteria, headers) \
4884 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
4885 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
4888 * Calculate flow matcher enable bitmap.
4890 * @param match_criteria
4891 * Pointer to flow matcher criteria.
4894 * Bitmap of enabled fields.
4897 flow_dv_matcher_enable(uint32_t *match_criteria)
4899 uint8_t match_criteria_enable;
4901 match_criteria_enable =
4902 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
4903 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
4904 match_criteria_enable |=
4905 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
4906 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
4907 match_criteria_enable |=
4908 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
4909 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
4910 match_criteria_enable |=
4911 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
4912 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
4913 match_criteria_enable |=
4914 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
4915 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
4916 return match_criteria_enable;
4923 * @param dev[in, out]
4924 * Pointer to rte_eth_dev structure.
4925 * @param[in] table_id
4928 * Direction of the table.
4929 * @param[in] transfer
4930 * E-Switch or NIC flow.
4932 * pointer to error structure.
4935 * Returns tables resource based on the index, NULL in case of failed.
4937 static struct mlx5_flow_tbl_resource *
4938 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
4939 uint32_t table_id, uint8_t egress,
4941 struct rte_flow_error *error)
4943 struct mlx5_priv *priv = dev->data->dev_private;
4944 struct mlx5_ibv_shared *sh = priv->sh;
4945 struct mlx5_flow_tbl_resource *tbl;
4947 #ifdef HAVE_MLX5DV_DR
4949 tbl = &sh->fdb_tbl[table_id];
4951 tbl->obj = mlx5_glue->dr_create_flow_tbl
4952 (sh->fdb_domain, table_id);
4953 } else if (egress) {
4954 tbl = &sh->tx_tbl[table_id];
4956 tbl->obj = mlx5_glue->dr_create_flow_tbl
4957 (sh->tx_domain, table_id);
4959 tbl = &sh->rx_tbl[table_id];
4961 tbl->obj = mlx5_glue->dr_create_flow_tbl
4962 (sh->rx_domain, table_id);
4965 rte_flow_error_set(error, ENOMEM,
4966 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4967 NULL, "cannot create table");
4970 rte_atomic32_inc(&tbl->refcnt);
4976 return &sh->fdb_tbl[table_id];
4978 return &sh->tx_tbl[table_id];
4980 return &sh->rx_tbl[table_id];
4985 * Release a flow table.
4988 * Table resource to be released.
4991 * Returns 0 if table was released, else return 1;
4994 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
4998 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
4999 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5007 * Register the flow matcher.
5009 * @param dev[in, out]
5010 * Pointer to rte_eth_dev structure.
5011 * @param[in, out] matcher
5012 * Pointer to flow matcher.
5013 * @parm[in, out] dev_flow
5014 * Pointer to the dev_flow.
5016 * pointer to error structure.
5019 * 0 on success otherwise -errno and errno is set.
5022 flow_dv_matcher_register(struct rte_eth_dev *dev,
5023 struct mlx5_flow_dv_matcher *matcher,
5024 struct mlx5_flow *dev_flow,
5025 struct rte_flow_error *error)
5027 struct mlx5_priv *priv = dev->data->dev_private;
5028 struct mlx5_ibv_shared *sh = priv->sh;
5029 struct mlx5_flow_dv_matcher *cache_matcher;
5030 struct mlx5dv_flow_matcher_attr dv_attr = {
5031 .type = IBV_FLOW_ATTR_NORMAL,
5032 .match_mask = (void *)&matcher->mask,
5034 struct mlx5_flow_tbl_resource *tbl = NULL;
5036 /* Lookup from cache. */
5037 LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5038 if (matcher->crc == cache_matcher->crc &&
5039 matcher->priority == cache_matcher->priority &&
5040 matcher->egress == cache_matcher->egress &&
5041 matcher->group == cache_matcher->group &&
5042 matcher->transfer == cache_matcher->transfer &&
5043 !memcmp((const void *)matcher->mask.buf,
5044 (const void *)cache_matcher->mask.buf,
5045 cache_matcher->mask.size)) {
5047 "priority %hd use %s matcher %p: refcnt %d++",
5048 cache_matcher->priority,
5049 cache_matcher->egress ? "tx" : "rx",
5050 (void *)cache_matcher,
5051 rte_atomic32_read(&cache_matcher->refcnt));
5052 rte_atomic32_inc(&cache_matcher->refcnt);
5053 dev_flow->dv.matcher = cache_matcher;
5057 /* Register new matcher. */
5058 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5060 return rte_flow_error_set(error, ENOMEM,
5061 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5062 "cannot allocate matcher memory");
5063 tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5064 matcher->egress, matcher->transfer,
5067 rte_free(cache_matcher);
5068 return rte_flow_error_set(error, ENOMEM,
5069 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5070 NULL, "cannot create table");
5072 *cache_matcher = *matcher;
5073 dv_attr.match_criteria_enable =
5074 flow_dv_matcher_enable(cache_matcher->mask.buf);
5075 dv_attr.priority = matcher->priority;
5076 if (matcher->egress)
5077 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5078 cache_matcher->matcher_object =
5079 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5080 if (!cache_matcher->matcher_object) {
5081 rte_free(cache_matcher);
5082 #ifdef HAVE_MLX5DV_DR
5083 flow_dv_tbl_resource_release(tbl);
5085 return rte_flow_error_set(error, ENOMEM,
5086 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5087 NULL, "cannot create matcher");
5089 rte_atomic32_inc(&cache_matcher->refcnt);
5090 LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5091 dev_flow->dv.matcher = cache_matcher;
5092 DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5093 cache_matcher->priority,
5094 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5095 rte_atomic32_read(&cache_matcher->refcnt));
5096 rte_atomic32_inc(&tbl->refcnt);
5101 * Find existing tag resource or create and register a new one.
5103 * @param dev[in, out]
5104 * Pointer to rte_eth_dev structure.
5105 * @param[in, out] resource
5106 * Pointer to tag resource.
5107 * @parm[in, out] dev_flow
5108 * Pointer to the dev_flow.
5110 * pointer to error structure.
5113 * 0 on success otherwise -errno and errno is set.
5116 flow_dv_tag_resource_register
5117 (struct rte_eth_dev *dev,
5118 struct mlx5_flow_dv_tag_resource *resource,
5119 struct mlx5_flow *dev_flow,
5120 struct rte_flow_error *error)
5122 struct mlx5_priv *priv = dev->data->dev_private;
5123 struct mlx5_ibv_shared *sh = priv->sh;
5124 struct mlx5_flow_dv_tag_resource *cache_resource;
5126 /* Lookup a matching resource from cache. */
5127 LIST_FOREACH(cache_resource, &sh->tags, next) {
5128 if (resource->tag == cache_resource->tag) {
5129 DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5130 (void *)cache_resource,
5131 rte_atomic32_read(&cache_resource->refcnt));
5132 rte_atomic32_inc(&cache_resource->refcnt);
5133 dev_flow->flow->tag_resource = cache_resource;
5137 /* Register new resource. */
5138 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5139 if (!cache_resource)
5140 return rte_flow_error_set(error, ENOMEM,
5141 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5142 "cannot allocate resource memory");
5143 *cache_resource = *resource;
5144 cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5146 if (!cache_resource->action) {
5147 rte_free(cache_resource);
5148 return rte_flow_error_set(error, ENOMEM,
5149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5150 NULL, "cannot create action");
5152 rte_atomic32_init(&cache_resource->refcnt);
5153 rte_atomic32_inc(&cache_resource->refcnt);
5154 LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5155 dev_flow->flow->tag_resource = cache_resource;
5156 DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5157 (void *)cache_resource,
5158 rte_atomic32_read(&cache_resource->refcnt));
5166 * Pointer to Ethernet device.
5168 * Pointer to mlx5_flow.
5171 * 1 while a reference on it exists, 0 when freed.
5174 flow_dv_tag_release(struct rte_eth_dev *dev,
5175 struct mlx5_flow_dv_tag_resource *tag)
5178 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5179 dev->data->port_id, (void *)tag,
5180 rte_atomic32_read(&tag->refcnt));
5181 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5182 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5183 LIST_REMOVE(tag, next);
5184 DRV_LOG(DEBUG, "port %u tag %p: removed",
5185 dev->data->port_id, (void *)tag);
5193 * Translate port ID action to vport.
5196 * Pointer to rte_eth_dev structure.
5198 * Pointer to the port ID action.
5199 * @param[out] dst_port_id
5200 * The target port ID.
5202 * Pointer to the error structure.
5205 * 0 on success, a negative errno value otherwise and rte_errno is set.
5208 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5209 const struct rte_flow_action *action,
5210 uint32_t *dst_port_id,
5211 struct rte_flow_error *error)
5214 struct mlx5_priv *priv;
5215 const struct rte_flow_action_port_id *conf =
5216 (const struct rte_flow_action_port_id *)action->conf;
5218 port = conf->original ? dev->data->port_id : conf->id;
5219 priv = mlx5_port_to_eswitch_info(port);
5221 return rte_flow_error_set(error, -rte_errno,
5222 RTE_FLOW_ERROR_TYPE_ACTION,
5224 "No eswitch info was found for port");
5225 if (priv->vport_meta_mask)
5226 *dst_port_id = priv->vport_meta_tag;
5228 *dst_port_id = priv->vport_id;
5233 * Fill the flow with DV spec.
5236 * Pointer to rte_eth_dev structure.
5237 * @param[in, out] dev_flow
5238 * Pointer to the sub flow.
5240 * Pointer to the flow attributes.
5242 * Pointer to the list of items.
5243 * @param[in] actions
5244 * Pointer to the list of actions.
5246 * Pointer to the error structure.
5249 * 0 on success, a negative errno value otherwise and rte_errno is set.
5252 flow_dv_translate(struct rte_eth_dev *dev,
5253 struct mlx5_flow *dev_flow,
5254 const struct rte_flow_attr *attr,
5255 const struct rte_flow_item items[],
5256 const struct rte_flow_action actions[],
5257 struct rte_flow_error *error)
5259 struct mlx5_priv *priv = dev->data->dev_private;
5260 struct rte_flow *flow = dev_flow->flow;
5261 uint64_t item_flags = 0;
5262 uint64_t last_item = 0;
5263 uint64_t action_flags = 0;
5264 uint64_t priority = attr->priority;
5265 struct mlx5_flow_dv_matcher matcher = {
5267 .size = sizeof(matcher.mask.buf),
5271 bool actions_end = false;
5272 struct mlx5_flow_dv_modify_hdr_resource res = {
5273 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5274 MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5276 union flow_dv_attr flow_attr = { .attr = 0 };
5277 struct mlx5_flow_dv_tag_resource tag_resource;
5278 uint32_t modify_action_position = UINT32_MAX;
5279 void *match_mask = matcher.mask.buf;
5280 void *match_value = dev_flow->dv.value.buf;
5281 uint8_t next_protocol = 0xff;
5282 struct rte_vlan_hdr vlan = { 0 };
5283 bool vlan_inherited = false;
5288 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5292 flow->group = table;
5294 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5295 if (priority == MLX5_FLOW_PRIO_RSVD)
5296 priority = priv->config.flow_prio - 1;
5297 for (; !actions_end ; actions++) {
5298 const struct rte_flow_action_queue *queue;
5299 const struct rte_flow_action_rss *rss;
5300 const struct rte_flow_action *action = actions;
5301 const struct rte_flow_action_count *count = action->conf;
5302 const uint8_t *rss_key;
5303 const struct rte_flow_action_jump *jump_data;
5304 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5305 struct mlx5_flow_tbl_resource *tbl;
5306 uint32_t port_id = 0;
5307 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5309 switch (actions->type) {
5310 case RTE_FLOW_ACTION_TYPE_VOID:
5312 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5313 if (flow_dv_translate_action_port_id(dev, action,
5316 port_id_resource.port_id = port_id;
5317 if (flow_dv_port_id_action_resource_register
5318 (dev, &port_id_resource, dev_flow, error))
5320 dev_flow->dv.actions[actions_n++] =
5321 dev_flow->dv.port_id_action->action;
5322 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5324 case RTE_FLOW_ACTION_TYPE_FLAG:
5326 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5327 if (!flow->tag_resource)
5328 if (flow_dv_tag_resource_register
5329 (dev, &tag_resource, dev_flow, error))
5331 dev_flow->dv.actions[actions_n++] =
5332 flow->tag_resource->action;
5333 action_flags |= MLX5_FLOW_ACTION_FLAG;
5335 case RTE_FLOW_ACTION_TYPE_MARK:
5336 tag_resource.tag = mlx5_flow_mark_set
5337 (((const struct rte_flow_action_mark *)
5338 (actions->conf))->id);
5339 if (!flow->tag_resource)
5340 if (flow_dv_tag_resource_register
5341 (dev, &tag_resource, dev_flow, error))
5343 dev_flow->dv.actions[actions_n++] =
5344 flow->tag_resource->action;
5345 action_flags |= MLX5_FLOW_ACTION_MARK;
5347 case RTE_FLOW_ACTION_TYPE_DROP:
5348 action_flags |= MLX5_FLOW_ACTION_DROP;
5350 case RTE_FLOW_ACTION_TYPE_QUEUE:
5351 queue = actions->conf;
5352 flow->rss.queue_num = 1;
5353 (*flow->queue)[0] = queue->index;
5354 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5356 case RTE_FLOW_ACTION_TYPE_RSS:
5357 rss = actions->conf;
5359 memcpy((*flow->queue), rss->queue,
5360 rss->queue_num * sizeof(uint16_t));
5361 flow->rss.queue_num = rss->queue_num;
5362 /* NULL RSS key indicates default RSS key. */
5363 rss_key = !rss->key ? rss_hash_default_key : rss->key;
5364 memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5365 /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5366 flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5367 flow->rss.level = rss->level;
5368 action_flags |= MLX5_FLOW_ACTION_RSS;
5370 case RTE_FLOW_ACTION_TYPE_COUNT:
5371 if (!priv->config.devx) {
5372 rte_errno = ENOTSUP;
5375 flow->counter = flow_dv_counter_alloc(dev,
5379 if (flow->counter == NULL)
5381 dev_flow->dv.actions[actions_n++] =
5382 flow->counter->action;
5383 action_flags |= MLX5_FLOW_ACTION_COUNT;
5386 if (rte_errno == ENOTSUP)
5387 return rte_flow_error_set
5389 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5391 "count action not supported");
5393 return rte_flow_error_set
5395 RTE_FLOW_ERROR_TYPE_ACTION,
5397 "cannot create counter"
5400 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5401 dev_flow->dv.actions[actions_n++] =
5402 priv->sh->pop_vlan_action;
5403 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5405 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5406 if (!vlan_inherited) {
5407 flow_dev_get_vlan_info_from_items(items, &vlan);
5408 vlan_inherited = true;
5410 vlan.eth_proto = rte_be_to_cpu_16
5411 ((((const struct rte_flow_action_of_push_vlan *)
5412 actions->conf)->ethertype));
5413 if (flow_dv_create_action_push_vlan
5414 (dev, attr, &vlan, dev_flow, error))
5416 dev_flow->dv.actions[actions_n++] =
5417 dev_flow->dv.push_vlan_res->action;
5418 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5419 /* Push VLAN command is also handling this VLAN_VID */
5420 action_flags &= ~MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5422 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5423 if (!vlan_inherited) {
5424 flow_dev_get_vlan_info_from_items(items, &vlan);
5425 vlan_inherited = true;
5428 ((const struct rte_flow_action_of_set_vlan_pcp *)
5429 actions->conf)->vlan_pcp;
5430 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
5431 vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
5432 vlan.vlan_tci |= vlan_tci;
5433 /* Push VLAN command will use this value */
5435 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5436 if (!vlan_inherited) {
5437 flow_dev_get_vlan_info_from_items(items, &vlan);
5438 vlan_inherited = true;
5440 vlan.vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
5441 vlan.vlan_tci |= rte_be_to_cpu_16
5442 (((const struct rte_flow_action_of_set_vlan_vid *)
5443 actions->conf)->vlan_vid);
5444 /* Push VLAN command will use this value */
5445 if (mlx5_flow_find_action
5447 RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN))
5449 /* If no VLAN push - this is a modify header action */
5450 if (flow_dv_convert_action_modify_vlan_vid
5451 (&res, actions, error))
5453 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5455 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5456 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5457 if (flow_dv_create_action_l2_encap(dev, actions,
5462 dev_flow->dv.actions[actions_n++] =
5463 dev_flow->dv.encap_decap->verbs_action;
5464 action_flags |= actions->type ==
5465 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5466 MLX5_FLOW_ACTION_VXLAN_ENCAP :
5467 MLX5_FLOW_ACTION_NVGRE_ENCAP;
5469 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5470 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5471 if (flow_dv_create_action_l2_decap(dev, dev_flow,
5475 dev_flow->dv.actions[actions_n++] =
5476 dev_flow->dv.encap_decap->verbs_action;
5477 action_flags |= actions->type ==
5478 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5479 MLX5_FLOW_ACTION_VXLAN_DECAP :
5480 MLX5_FLOW_ACTION_NVGRE_DECAP;
5482 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5483 /* Handle encap with preceding decap. */
5484 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5485 if (flow_dv_create_action_raw_encap
5486 (dev, actions, dev_flow, attr, error))
5488 dev_flow->dv.actions[actions_n++] =
5489 dev_flow->dv.encap_decap->verbs_action;
5491 /* Handle encap without preceding decap. */
5492 if (flow_dv_create_action_l2_encap
5493 (dev, actions, dev_flow, attr->transfer,
5496 dev_flow->dv.actions[actions_n++] =
5497 dev_flow->dv.encap_decap->verbs_action;
5499 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5501 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5502 /* Check if this decap is followed by encap. */
5503 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5504 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5507 /* Handle decap only if it isn't followed by encap. */
5508 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5509 if (flow_dv_create_action_l2_decap
5510 (dev, dev_flow, attr->transfer, error))
5512 dev_flow->dv.actions[actions_n++] =
5513 dev_flow->dv.encap_decap->verbs_action;
5515 /* If decap is followed by encap, handle it at encap. */
5516 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5518 case RTE_FLOW_ACTION_TYPE_JUMP:
5519 jump_data = action->conf;
5520 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5521 jump_data->group, &table,
5525 tbl = flow_dv_tbl_resource_get(dev, table,
5527 attr->transfer, error);
5529 return rte_flow_error_set
5531 RTE_FLOW_ERROR_TYPE_ACTION,
5533 "cannot create jump action.");
5534 jump_tbl_resource.tbl = tbl;
5535 if (flow_dv_jump_tbl_resource_register
5536 (dev, &jump_tbl_resource, dev_flow, error)) {
5537 flow_dv_tbl_resource_release(tbl);
5538 return rte_flow_error_set
5540 RTE_FLOW_ERROR_TYPE_ACTION,
5542 "cannot create jump action.");
5544 dev_flow->dv.actions[actions_n++] =
5545 dev_flow->dv.jump->action;
5546 action_flags |= MLX5_FLOW_ACTION_JUMP;
5548 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5549 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5550 if (flow_dv_convert_action_modify_mac(&res, actions,
5553 action_flags |= actions->type ==
5554 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5555 MLX5_FLOW_ACTION_SET_MAC_SRC :
5556 MLX5_FLOW_ACTION_SET_MAC_DST;
5558 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5559 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5560 if (flow_dv_convert_action_modify_ipv4(&res, actions,
5563 action_flags |= actions->type ==
5564 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5565 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5566 MLX5_FLOW_ACTION_SET_IPV4_DST;
5568 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5569 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5570 if (flow_dv_convert_action_modify_ipv6(&res, actions,
5573 action_flags |= actions->type ==
5574 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5575 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5576 MLX5_FLOW_ACTION_SET_IPV6_DST;
5578 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5579 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5580 if (flow_dv_convert_action_modify_tp(&res, actions,
5584 action_flags |= actions->type ==
5585 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5586 MLX5_FLOW_ACTION_SET_TP_SRC :
5587 MLX5_FLOW_ACTION_SET_TP_DST;
5589 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5590 if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5594 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5596 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5597 if (flow_dv_convert_action_modify_ttl(&res, actions,
5601 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5603 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5604 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5605 if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5608 action_flags |= actions->type ==
5609 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5610 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5611 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5614 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5615 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5616 if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5619 action_flags |= actions->type ==
5620 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5621 MLX5_FLOW_ACTION_INC_TCP_ACK :
5622 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5624 case RTE_FLOW_ACTION_TYPE_END:
5626 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5627 /* create modify action if needed. */
5628 if (flow_dv_modify_hdr_resource_register
5633 dev_flow->dv.actions[modify_action_position] =
5634 dev_flow->dv.modify_hdr->verbs_action;
5640 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5641 modify_action_position == UINT32_MAX)
5642 modify_action_position = actions_n++;
5644 dev_flow->dv.actions_n = actions_n;
5645 flow->actions = action_flags;
5646 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5647 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5649 switch (items->type) {
5650 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5651 flow_dv_translate_item_port_id(dev, match_mask,
5652 match_value, items);
5653 last_item = MLX5_FLOW_ITEM_PORT_ID;
5655 case RTE_FLOW_ITEM_TYPE_ETH:
5656 flow_dv_translate_item_eth(match_mask, match_value,
5658 matcher.priority = MLX5_PRIORITY_MAP_L2;
5659 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5660 MLX5_FLOW_LAYER_OUTER_L2;
5662 case RTE_FLOW_ITEM_TYPE_VLAN:
5663 flow_dv_translate_item_vlan(dev_flow,
5664 match_mask, match_value,
5666 matcher.priority = MLX5_PRIORITY_MAP_L2;
5667 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5668 MLX5_FLOW_LAYER_INNER_VLAN) :
5669 (MLX5_FLOW_LAYER_OUTER_L2 |
5670 MLX5_FLOW_LAYER_OUTER_VLAN);
5672 case RTE_FLOW_ITEM_TYPE_IPV4:
5673 mlx5_flow_tunnel_ip_check(items, next_protocol,
5674 &item_flags, &tunnel);
5675 flow_dv_translate_item_ipv4(match_mask, match_value,
5676 items, tunnel, flow->group);
5677 matcher.priority = MLX5_PRIORITY_MAP_L3;
5678 dev_flow->dv.hash_fields |=
5679 mlx5_flow_hashfields_adjust
5681 MLX5_IPV4_LAYER_TYPES,
5682 MLX5_IPV4_IBV_RX_HASH);
5683 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5684 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5685 if (items->mask != NULL &&
5686 ((const struct rte_flow_item_ipv4 *)
5687 items->mask)->hdr.next_proto_id) {
5689 ((const struct rte_flow_item_ipv4 *)
5690 (items->spec))->hdr.next_proto_id;
5692 ((const struct rte_flow_item_ipv4 *)
5693 (items->mask))->hdr.next_proto_id;
5695 /* Reset for inner layer. */
5696 next_protocol = 0xff;
5699 case RTE_FLOW_ITEM_TYPE_IPV6:
5700 mlx5_flow_tunnel_ip_check(items, next_protocol,
5701 &item_flags, &tunnel);
5702 flow_dv_translate_item_ipv6(match_mask, match_value,
5703 items, tunnel, flow->group);
5704 matcher.priority = MLX5_PRIORITY_MAP_L3;
5705 dev_flow->dv.hash_fields |=
5706 mlx5_flow_hashfields_adjust
5708 MLX5_IPV6_LAYER_TYPES,
5709 MLX5_IPV6_IBV_RX_HASH);
5710 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5711 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5712 if (items->mask != NULL &&
5713 ((const struct rte_flow_item_ipv6 *)
5714 items->mask)->hdr.proto) {
5716 ((const struct rte_flow_item_ipv6 *)
5717 items->spec)->hdr.proto;
5719 ((const struct rte_flow_item_ipv6 *)
5720 items->mask)->hdr.proto;
5722 /* Reset for inner layer. */
5723 next_protocol = 0xff;
5726 case RTE_FLOW_ITEM_TYPE_TCP:
5727 flow_dv_translate_item_tcp(match_mask, match_value,
5729 matcher.priority = MLX5_PRIORITY_MAP_L4;
5730 dev_flow->dv.hash_fields |=
5731 mlx5_flow_hashfields_adjust
5732 (dev_flow, tunnel, ETH_RSS_TCP,
5733 IBV_RX_HASH_SRC_PORT_TCP |
5734 IBV_RX_HASH_DST_PORT_TCP);
5735 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5736 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5738 case RTE_FLOW_ITEM_TYPE_UDP:
5739 flow_dv_translate_item_udp(match_mask, match_value,
5741 matcher.priority = MLX5_PRIORITY_MAP_L4;
5742 dev_flow->dv.hash_fields |=
5743 mlx5_flow_hashfields_adjust
5744 (dev_flow, tunnel, ETH_RSS_UDP,
5745 IBV_RX_HASH_SRC_PORT_UDP |
5746 IBV_RX_HASH_DST_PORT_UDP);
5747 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5748 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5750 case RTE_FLOW_ITEM_TYPE_GRE:
5751 flow_dv_translate_item_gre(match_mask, match_value,
5753 last_item = MLX5_FLOW_LAYER_GRE;
5755 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5756 flow_dv_translate_item_gre_key(match_mask,
5757 match_value, items);
5758 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5760 case RTE_FLOW_ITEM_TYPE_NVGRE:
5761 flow_dv_translate_item_nvgre(match_mask, match_value,
5763 last_item = MLX5_FLOW_LAYER_GRE;
5765 case RTE_FLOW_ITEM_TYPE_VXLAN:
5766 flow_dv_translate_item_vxlan(match_mask, match_value,
5768 last_item = MLX5_FLOW_LAYER_VXLAN;
5770 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5771 flow_dv_translate_item_vxlan(match_mask, match_value,
5773 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5775 case RTE_FLOW_ITEM_TYPE_GENEVE:
5776 flow_dv_translate_item_geneve(match_mask, match_value,
5778 last_item = MLX5_FLOW_LAYER_GENEVE;
5780 case RTE_FLOW_ITEM_TYPE_MPLS:
5781 flow_dv_translate_item_mpls(match_mask, match_value,
5782 items, last_item, tunnel);
5783 last_item = MLX5_FLOW_LAYER_MPLS;
5785 case RTE_FLOW_ITEM_TYPE_META:
5786 flow_dv_translate_item_meta(match_mask, match_value,
5788 last_item = MLX5_FLOW_ITEM_METADATA;
5790 case RTE_FLOW_ITEM_TYPE_ICMP:
5791 flow_dv_translate_item_icmp(match_mask, match_value,
5793 last_item = MLX5_FLOW_LAYER_ICMP;
5795 case RTE_FLOW_ITEM_TYPE_ICMP6:
5796 flow_dv_translate_item_icmp6(match_mask, match_value,
5798 last_item = MLX5_FLOW_LAYER_ICMP6;
5803 item_flags |= last_item;
5806 * In case of ingress traffic when E-Switch mode is enabled,
5807 * we have two cases where we need to set the source port manually.
5808 * The first one, is in case of Nic steering rule, and the second is
5809 * E-Switch rule where no port_id item was found. In both cases
5810 * the source port is set according the current port in use.
5812 if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
5813 (priv->representor || priv->master)) {
5814 if (flow_dv_translate_item_port_id(dev, match_mask,
5818 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
5819 dev_flow->dv.value.buf));
5820 dev_flow->layers = item_flags;
5821 /* Register matcher. */
5822 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
5824 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
5826 matcher.egress = attr->egress;
5827 matcher.group = flow->group;
5828 matcher.transfer = attr->transfer;
5829 if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
5835 * Apply the flow to the NIC.
5838 * Pointer to the Ethernet device structure.
5839 * @param[in, out] flow
5840 * Pointer to flow structure.
5842 * Pointer to error structure.
5845 * 0 on success, a negative errno value otherwise and rte_errno is set.
5848 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
5849 struct rte_flow_error *error)
5851 struct mlx5_flow_dv *dv;
5852 struct mlx5_flow *dev_flow;
5853 struct mlx5_priv *priv = dev->data->dev_private;
5857 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5860 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
5861 if (flow->transfer) {
5862 dv->actions[n++] = priv->sh->esw_drop_action;
5864 dv->hrxq = mlx5_hrxq_drop_new(dev);
5868 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5870 "cannot get drop hash queue");
5873 dv->actions[n++] = dv->hrxq->action;
5875 } else if (flow->actions &
5876 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
5877 struct mlx5_hrxq *hrxq;
5879 hrxq = mlx5_hrxq_get(dev, flow->key,
5880 MLX5_RSS_HASH_KEY_LEN,
5883 flow->rss.queue_num);
5885 hrxq = mlx5_hrxq_new
5886 (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
5887 dv->hash_fields, (*flow->queue),
5888 flow->rss.queue_num,
5889 !!(dev_flow->layers &
5890 MLX5_FLOW_LAYER_TUNNEL));
5895 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5896 "cannot get hash queue");
5900 dv->actions[n++] = dv->hrxq->action;
5903 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
5904 (void *)&dv->value, n,
5907 rte_flow_error_set(error, errno,
5908 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5910 "hardware refuses to create flow");
5913 if (priv->vmwa_context &&
5914 dev_flow->dv.vf_vlan.tag &&
5915 !dev_flow->dv.vf_vlan.created) {
5917 * The rule contains the VLAN pattern.
5918 * For VF we are going to create VLAN
5919 * interface to make hypervisor set correct
5920 * e-Switch vport context.
5922 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
5927 err = rte_errno; /* Save rte_errno before cleanup. */
5928 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
5929 struct mlx5_flow_dv *dv = &dev_flow->dv;
5931 if (flow->actions & MLX5_FLOW_ACTION_DROP)
5932 mlx5_hrxq_drop_release(dev);
5934 mlx5_hrxq_release(dev, dv->hrxq);
5937 if (dev_flow->dv.vf_vlan.tag &&
5938 dev_flow->dv.vf_vlan.created)
5939 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
5941 rte_errno = err; /* Restore rte_errno. */
5946 * Release the flow matcher.
5949 * Pointer to Ethernet device.
5951 * Pointer to mlx5_flow.
5954 * 1 while a reference on it exists, 0 when freed.
5957 flow_dv_matcher_release(struct rte_eth_dev *dev,
5958 struct mlx5_flow *flow)
5960 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
5961 struct mlx5_priv *priv = dev->data->dev_private;
5962 struct mlx5_ibv_shared *sh = priv->sh;
5963 struct mlx5_flow_tbl_resource *tbl;
5965 assert(matcher->matcher_object);
5966 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
5967 dev->data->port_id, (void *)matcher,
5968 rte_atomic32_read(&matcher->refcnt));
5969 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
5970 claim_zero(mlx5_glue->dv_destroy_flow_matcher
5971 (matcher->matcher_object));
5972 LIST_REMOVE(matcher, next);
5973 if (matcher->egress)
5974 tbl = &sh->tx_tbl[matcher->group];
5976 tbl = &sh->rx_tbl[matcher->group];
5977 flow_dv_tbl_resource_release(tbl);
5979 DRV_LOG(DEBUG, "port %u matcher %p: removed",
5980 dev->data->port_id, (void *)matcher);
5987 * Release an encap/decap resource.
5990 * Pointer to mlx5_flow.
5993 * 1 while a reference on it exists, 0 when freed.
5996 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
5998 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
5999 flow->dv.encap_decap;
6001 assert(cache_resource->verbs_action);
6002 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6003 (void *)cache_resource,
6004 rte_atomic32_read(&cache_resource->refcnt));
6005 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6006 claim_zero(mlx5_glue->destroy_flow_action
6007 (cache_resource->verbs_action));
6008 LIST_REMOVE(cache_resource, next);
6009 rte_free(cache_resource);
6010 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6011 (void *)cache_resource);
6018 * Release an jump to table action resource.
6021 * Pointer to mlx5_flow.
6024 * 1 while a reference on it exists, 0 when freed.
6027 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6029 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6032 assert(cache_resource->action);
6033 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6034 (void *)cache_resource,
6035 rte_atomic32_read(&cache_resource->refcnt));
6036 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6037 claim_zero(mlx5_glue->destroy_flow_action
6038 (cache_resource->action));
6039 LIST_REMOVE(cache_resource, next);
6040 flow_dv_tbl_resource_release(cache_resource->tbl);
6041 rte_free(cache_resource);
6042 DRV_LOG(DEBUG, "jump table resource %p: removed",
6043 (void *)cache_resource);
6050 * Release a modify-header resource.
6053 * Pointer to mlx5_flow.
6056 * 1 while a reference on it exists, 0 when freed.
6059 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6061 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6062 flow->dv.modify_hdr;
6064 assert(cache_resource->verbs_action);
6065 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6066 (void *)cache_resource,
6067 rte_atomic32_read(&cache_resource->refcnt));
6068 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6069 claim_zero(mlx5_glue->destroy_flow_action
6070 (cache_resource->verbs_action));
6071 LIST_REMOVE(cache_resource, next);
6072 rte_free(cache_resource);
6073 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6074 (void *)cache_resource);
6081 * Release port ID action resource.
6084 * Pointer to mlx5_flow.
6087 * 1 while a reference on it exists, 0 when freed.
6090 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6092 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6093 flow->dv.port_id_action;
6095 assert(cache_resource->action);
6096 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6097 (void *)cache_resource,
6098 rte_atomic32_read(&cache_resource->refcnt));
6099 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6100 claim_zero(mlx5_glue->destroy_flow_action
6101 (cache_resource->action));
6102 LIST_REMOVE(cache_resource, next);
6103 rte_free(cache_resource);
6104 DRV_LOG(DEBUG, "port id action resource %p: removed",
6105 (void *)cache_resource);
6112 * Release push vlan action resource.
6115 * Pointer to mlx5_flow.
6118 * 1 while a reference on it exists, 0 when freed.
6121 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6123 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6124 flow->dv.push_vlan_res;
6126 assert(cache_resource->action);
6127 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6128 (void *)cache_resource,
6129 rte_atomic32_read(&cache_resource->refcnt));
6130 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6131 claim_zero(mlx5_glue->destroy_flow_action
6132 (cache_resource->action));
6133 LIST_REMOVE(cache_resource, next);
6134 rte_free(cache_resource);
6135 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6136 (void *)cache_resource);
6143 * Remove the flow from the NIC but keeps it in memory.
6146 * Pointer to Ethernet device.
6147 * @param[in, out] flow
6148 * Pointer to flow structure.
6151 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6153 struct mlx5_flow_dv *dv;
6154 struct mlx5_flow *dev_flow;
6158 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6161 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6165 if (flow->actions & MLX5_FLOW_ACTION_DROP)
6166 mlx5_hrxq_drop_release(dev);
6168 mlx5_hrxq_release(dev, dv->hrxq);
6171 if (dev_flow->dv.vf_vlan.tag &&
6172 dev_flow->dv.vf_vlan.created)
6173 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6178 * Remove the flow from the NIC and the memory.
6181 * Pointer to the Ethernet device structure.
6182 * @param[in, out] flow
6183 * Pointer to flow structure.
6186 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6188 struct mlx5_flow *dev_flow;
6192 flow_dv_remove(dev, flow);
6193 if (flow->counter) {
6194 flow_dv_counter_release(dev, flow->counter);
6195 flow->counter = NULL;
6197 if (flow->tag_resource) {
6198 flow_dv_tag_release(dev, flow->tag_resource);
6199 flow->tag_resource = NULL;
6201 while (!LIST_EMPTY(&flow->dev_flows)) {
6202 dev_flow = LIST_FIRST(&flow->dev_flows);
6203 LIST_REMOVE(dev_flow, next);
6204 if (dev_flow->dv.matcher)
6205 flow_dv_matcher_release(dev, dev_flow);
6206 if (dev_flow->dv.encap_decap)
6207 flow_dv_encap_decap_resource_release(dev_flow);
6208 if (dev_flow->dv.modify_hdr)
6209 flow_dv_modify_hdr_resource_release(dev_flow);
6210 if (dev_flow->dv.jump)
6211 flow_dv_jump_tbl_resource_release(dev_flow);
6212 if (dev_flow->dv.port_id_action)
6213 flow_dv_port_id_action_resource_release(dev_flow);
6214 if (dev_flow->dv.push_vlan_res)
6215 flow_dv_push_vlan_action_resource_release(dev_flow);
6221 * Query a dv flow rule for its statistics via devx.
6224 * Pointer to Ethernet device.
6226 * Pointer to the sub flow.
6228 * data retrieved by the query.
6230 * Perform verbose error reporting if not NULL.
6233 * 0 on success, a negative errno value otherwise and rte_errno is set.
6236 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6237 void *data, struct rte_flow_error *error)
6239 struct mlx5_priv *priv = dev->data->dev_private;
6240 struct rte_flow_query_count *qc = data;
6242 if (!priv->config.devx)
6243 return rte_flow_error_set(error, ENOTSUP,
6244 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6246 "counters are not supported");
6247 if (flow->counter) {
6248 uint64_t pkts, bytes;
6249 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6253 return rte_flow_error_set(error, -err,
6254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6255 NULL, "cannot read counters");
6258 qc->hits = pkts - flow->counter->hits;
6259 qc->bytes = bytes - flow->counter->bytes;
6261 flow->counter->hits = pkts;
6262 flow->counter->bytes = bytes;
6266 return rte_flow_error_set(error, EINVAL,
6267 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6269 "counters are not available");
6275 * @see rte_flow_query()
6279 flow_dv_query(struct rte_eth_dev *dev,
6280 struct rte_flow *flow __rte_unused,
6281 const struct rte_flow_action *actions __rte_unused,
6282 void *data __rte_unused,
6283 struct rte_flow_error *error __rte_unused)
6287 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6288 switch (actions->type) {
6289 case RTE_FLOW_ACTION_TYPE_VOID:
6291 case RTE_FLOW_ACTION_TYPE_COUNT:
6292 ret = flow_dv_query_count(dev, flow, data, error);
6295 return rte_flow_error_set(error, ENOTSUP,
6296 RTE_FLOW_ERROR_TYPE_ACTION,
6298 "action not supported");
6305 * Mutex-protected thunk to flow_dv_translate().
6308 flow_d_translate(struct rte_eth_dev *dev,
6309 struct mlx5_flow *dev_flow,
6310 const struct rte_flow_attr *attr,
6311 const struct rte_flow_item items[],
6312 const struct rte_flow_action actions[],
6313 struct rte_flow_error *error)
6317 flow_d_shared_lock(dev);
6318 ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6319 flow_d_shared_unlock(dev);
6324 * Mutex-protected thunk to flow_dv_apply().
6327 flow_d_apply(struct rte_eth_dev *dev,
6328 struct rte_flow *flow,
6329 struct rte_flow_error *error)
6333 flow_d_shared_lock(dev);
6334 ret = flow_dv_apply(dev, flow, error);
6335 flow_d_shared_unlock(dev);
6340 * Mutex-protected thunk to flow_dv_remove().
6343 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6345 flow_d_shared_lock(dev);
6346 flow_dv_remove(dev, flow);
6347 flow_d_shared_unlock(dev);
6351 * Mutex-protected thunk to flow_dv_destroy().
6354 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6356 flow_d_shared_lock(dev);
6357 flow_dv_destroy(dev, flow);
6358 flow_d_shared_unlock(dev);
6361 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6362 .validate = flow_dv_validate,
6363 .prepare = flow_dv_prepare,
6364 .translate = flow_d_translate,
6365 .apply = flow_d_apply,
6366 .remove = flow_d_remove,
6367 .destroy = flow_d_destroy,
6368 .query = flow_dv_query,
6371 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */