1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
96 * If layers is already initialized, it means this dev_flow is the
97 * suffix flow, the layers flags is set by the prefix flow. Need to
98 * use the layer flags from prefix flow as the suffix flow may not
99 * have the user defined items as the flow is split.
101 if (dev_flow->layers) {
102 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
104 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
106 if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
108 else if (dev_flow->layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
113 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
114 uint8_t next_protocol = 0xff;
115 switch (item->type) {
116 case RTE_FLOW_ITEM_TYPE_GRE:
117 case RTE_FLOW_ITEM_TYPE_NVGRE:
118 case RTE_FLOW_ITEM_TYPE_VXLAN:
119 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
120 case RTE_FLOW_ITEM_TYPE_GENEVE:
121 case RTE_FLOW_ITEM_TYPE_MPLS:
125 case RTE_FLOW_ITEM_TYPE_IPV4:
128 if (item->mask != NULL &&
129 ((const struct rte_flow_item_ipv4 *)
130 item->mask)->hdr.next_proto_id)
132 ((const struct rte_flow_item_ipv4 *)
133 (item->spec))->hdr.next_proto_id &
134 ((const struct rte_flow_item_ipv4 *)
135 (item->mask))->hdr.next_proto_id;
136 if ((next_protocol == IPPROTO_IPIP ||
137 next_protocol == IPPROTO_IPV6) && tunnel_decap)
140 case RTE_FLOW_ITEM_TYPE_IPV6:
143 if (item->mask != NULL &&
144 ((const struct rte_flow_item_ipv6 *)
145 item->mask)->hdr.proto)
147 ((const struct rte_flow_item_ipv6 *)
148 (item->spec))->hdr.proto &
149 ((const struct rte_flow_item_ipv6 *)
150 (item->mask))->hdr.proto;
151 if ((next_protocol == IPPROTO_IPIP ||
152 next_protocol == IPPROTO_IPV6) && tunnel_decap)
155 case RTE_FLOW_ITEM_TYPE_UDP:
159 case RTE_FLOW_ITEM_TYPE_TCP:
171 * Convert rte_mtr_color to mlx5 color.
180 rte_col_2_mlx5_col(enum rte_color rcol)
183 case RTE_COLOR_GREEN:
184 return MLX5_FLOW_COLOR_GREEN;
185 case RTE_COLOR_YELLOW:
186 return MLX5_FLOW_COLOR_YELLOW;
188 return MLX5_FLOW_COLOR_RED;
192 return MLX5_FLOW_COLOR_UNDEFINED;
195 struct field_modify_info {
196 uint32_t size; /* Size of field in protocol header, in bytes. */
197 uint32_t offset; /* Offset of field in protocol header, in bytes. */
198 enum mlx5_modification_field id;
201 struct field_modify_info modify_eth[] = {
202 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
203 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
204 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
205 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
209 struct field_modify_info modify_vlan_out_first_vid[] = {
210 /* Size in bits !!! */
211 {12, 0, MLX5_MODI_OUT_FIRST_VID},
215 struct field_modify_info modify_ipv4[] = {
216 {1, 1, MLX5_MODI_OUT_IP_DSCP},
217 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
218 {4, 12, MLX5_MODI_OUT_SIPV4},
219 {4, 16, MLX5_MODI_OUT_DIPV4},
223 struct field_modify_info modify_ipv6[] = {
224 {1, 0, MLX5_MODI_OUT_IP_DSCP},
225 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
226 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
227 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
228 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
229 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
230 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
231 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
232 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
233 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
237 struct field_modify_info modify_udp[] = {
238 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
239 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
243 struct field_modify_info modify_tcp[] = {
244 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
245 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
246 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
247 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
252 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
253 uint8_t next_protocol, uint64_t *item_flags,
256 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
257 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
258 if (next_protocol == IPPROTO_IPIP) {
259 *item_flags |= MLX5_FLOW_LAYER_IPIP;
262 if (next_protocol == IPPROTO_IPV6) {
263 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
269 * Acquire the synchronizing object to protect multithreaded access
270 * to shared dv context. Lock occurs only if context is actually
271 * shared, i.e. we have multiport IB device and representors are
275 * Pointer to the rte_eth_dev structure.
278 flow_dv_shared_lock(struct rte_eth_dev *dev)
280 struct mlx5_priv *priv = dev->data->dev_private;
281 struct mlx5_ibv_shared *sh = priv->sh;
283 if (sh->dv_refcnt > 1) {
286 ret = pthread_mutex_lock(&sh->dv_mutex);
293 flow_dv_shared_unlock(struct rte_eth_dev *dev)
295 struct mlx5_priv *priv = dev->data->dev_private;
296 struct mlx5_ibv_shared *sh = priv->sh;
298 if (sh->dv_refcnt > 1) {
301 ret = pthread_mutex_unlock(&sh->dv_mutex);
307 /* Update VLAN's VID/PCP based on input rte_flow_action.
310 * Pointer to struct rte_flow_action.
312 * Pointer to struct rte_vlan_hdr.
315 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
316 struct rte_vlan_hdr *vlan)
319 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
321 ((const struct rte_flow_action_of_set_vlan_pcp *)
322 action->conf)->vlan_pcp;
323 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
324 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
325 vlan->vlan_tci |= vlan_tci;
326 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
327 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
328 vlan->vlan_tci |= rte_be_to_cpu_16
329 (((const struct rte_flow_action_of_set_vlan_vid *)
330 action->conf)->vlan_vid);
335 * Fetch 1, 2, 3 or 4 byte field from the byte array
336 * and return as unsigned integer in host-endian format.
339 * Pointer to data array.
341 * Size of field to extract.
344 * converted field in host endian format.
346 static inline uint32_t
347 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
356 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
359 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
360 ret = (ret << 8) | *(data + sizeof(uint16_t));
363 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
374 * Convert modify-header action to DV specification.
376 * Data length of each action is determined by provided field description
377 * and the item mask. Data bit offset and width of each action is determined
378 * by provided item mask.
381 * Pointer to item specification.
383 * Pointer to field modification information.
384 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
385 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
386 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
388 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
389 * Negative offset value sets the same offset as source offset.
390 * size field is ignored, value is taken from source field.
391 * @param[in,out] resource
392 * Pointer to the modify-header resource.
394 * Type of modification.
396 * Pointer to the error structure.
399 * 0 on success, a negative errno value otherwise and rte_errno is set.
402 flow_dv_convert_modify_action(struct rte_flow_item *item,
403 struct field_modify_info *field,
404 struct field_modify_info *dcopy,
405 struct mlx5_flow_dv_modify_hdr_resource *resource,
406 uint32_t type, struct rte_flow_error *error)
408 uint32_t i = resource->actions_num;
409 struct mlx5_modification_cmd *actions = resource->actions;
412 * The item and mask are provided in big-endian format.
413 * The fields should be presented as in big-endian format either.
414 * Mask must be always present, it defines the actual field width.
416 MLX5_ASSERT(item->mask);
417 MLX5_ASSERT(field->size);
424 if (i >= MLX5_MAX_MODIFY_NUM)
425 return rte_flow_error_set(error, EINVAL,
426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
427 "too many items to modify");
428 /* Fetch variable byte size mask from the array. */
429 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
430 field->offset, field->size);
435 /* Deduce actual data width in bits from mask value. */
436 off_b = rte_bsf32(mask);
437 size_b = sizeof(uint32_t) * CHAR_BIT -
438 off_b - __builtin_clz(mask);
440 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
441 actions[i] = (struct mlx5_modification_cmd) {
447 /* Convert entire record to expected big-endian format. */
448 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
449 if (type == MLX5_MODIFICATION_TYPE_COPY) {
451 actions[i].dst_field = dcopy->id;
452 actions[i].dst_offset =
453 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
454 /* Convert entire record to big-endian format. */
455 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
457 MLX5_ASSERT(item->spec);
458 data = flow_dv_fetch_field((const uint8_t *)item->spec +
459 field->offset, field->size);
460 /* Shift out the trailing masked bits from data. */
461 data = (data & mask) >> off_b;
462 actions[i].data1 = rte_cpu_to_be_32(data);
466 } while (field->size);
467 if (resource->actions_num == i)
468 return rte_flow_error_set(error, EINVAL,
469 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
470 "invalid modification flow item");
471 resource->actions_num = i;
476 * Convert modify-header set IPv4 address action to DV specification.
478 * @param[in,out] resource
479 * Pointer to the modify-header resource.
481 * Pointer to action specification.
483 * Pointer to the error structure.
486 * 0 on success, a negative errno value otherwise and rte_errno is set.
489 flow_dv_convert_action_modify_ipv4
490 (struct mlx5_flow_dv_modify_hdr_resource *resource,
491 const struct rte_flow_action *action,
492 struct rte_flow_error *error)
494 const struct rte_flow_action_set_ipv4 *conf =
495 (const struct rte_flow_action_set_ipv4 *)(action->conf);
496 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
497 struct rte_flow_item_ipv4 ipv4;
498 struct rte_flow_item_ipv4 ipv4_mask;
500 memset(&ipv4, 0, sizeof(ipv4));
501 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
502 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
503 ipv4.hdr.src_addr = conf->ipv4_addr;
504 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
506 ipv4.hdr.dst_addr = conf->ipv4_addr;
507 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
510 item.mask = &ipv4_mask;
511 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
512 MLX5_MODIFICATION_TYPE_SET, error);
516 * Convert modify-header set IPv6 address action to DV specification.
518 * @param[in,out] resource
519 * Pointer to the modify-header resource.
521 * Pointer to action specification.
523 * Pointer to the error structure.
526 * 0 on success, a negative errno value otherwise and rte_errno is set.
529 flow_dv_convert_action_modify_ipv6
530 (struct mlx5_flow_dv_modify_hdr_resource *resource,
531 const struct rte_flow_action *action,
532 struct rte_flow_error *error)
534 const struct rte_flow_action_set_ipv6 *conf =
535 (const struct rte_flow_action_set_ipv6 *)(action->conf);
536 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
537 struct rte_flow_item_ipv6 ipv6;
538 struct rte_flow_item_ipv6 ipv6_mask;
540 memset(&ipv6, 0, sizeof(ipv6));
541 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
542 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
543 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
544 sizeof(ipv6.hdr.src_addr));
545 memcpy(&ipv6_mask.hdr.src_addr,
546 &rte_flow_item_ipv6_mask.hdr.src_addr,
547 sizeof(ipv6.hdr.src_addr));
549 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.dst_addr));
551 memcpy(&ipv6_mask.hdr.dst_addr,
552 &rte_flow_item_ipv6_mask.hdr.dst_addr,
553 sizeof(ipv6.hdr.dst_addr));
556 item.mask = &ipv6_mask;
557 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
558 MLX5_MODIFICATION_TYPE_SET, error);
562 * Convert modify-header set MAC address action to DV specification.
564 * @param[in,out] resource
565 * Pointer to the modify-header resource.
567 * Pointer to action specification.
569 * Pointer to the error structure.
572 * 0 on success, a negative errno value otherwise and rte_errno is set.
575 flow_dv_convert_action_modify_mac
576 (struct mlx5_flow_dv_modify_hdr_resource *resource,
577 const struct rte_flow_action *action,
578 struct rte_flow_error *error)
580 const struct rte_flow_action_set_mac *conf =
581 (const struct rte_flow_action_set_mac *)(action->conf);
582 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
583 struct rte_flow_item_eth eth;
584 struct rte_flow_item_eth eth_mask;
586 memset(ð, 0, sizeof(eth));
587 memset(ð_mask, 0, sizeof(eth_mask));
588 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
589 memcpy(ð.src.addr_bytes, &conf->mac_addr,
590 sizeof(eth.src.addr_bytes));
591 memcpy(ð_mask.src.addr_bytes,
592 &rte_flow_item_eth_mask.src.addr_bytes,
593 sizeof(eth_mask.src.addr_bytes));
595 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
596 sizeof(eth.dst.addr_bytes));
597 memcpy(ð_mask.dst.addr_bytes,
598 &rte_flow_item_eth_mask.dst.addr_bytes,
599 sizeof(eth_mask.dst.addr_bytes));
602 item.mask = ð_mask;
603 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
604 MLX5_MODIFICATION_TYPE_SET, error);
608 * Convert modify-header set VLAN VID action to DV specification.
610 * @param[in,out] resource
611 * Pointer to the modify-header resource.
613 * Pointer to action specification.
615 * Pointer to the error structure.
618 * 0 on success, a negative errno value otherwise and rte_errno is set.
621 flow_dv_convert_action_modify_vlan_vid
622 (struct mlx5_flow_dv_modify_hdr_resource *resource,
623 const struct rte_flow_action *action,
624 struct rte_flow_error *error)
626 const struct rte_flow_action_of_set_vlan_vid *conf =
627 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
628 int i = resource->actions_num;
629 struct mlx5_modification_cmd *actions = resource->actions;
630 struct field_modify_info *field = modify_vlan_out_first_vid;
632 if (i >= MLX5_MAX_MODIFY_NUM)
633 return rte_flow_error_set(error, EINVAL,
634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
635 "too many items to modify");
636 actions[i] = (struct mlx5_modification_cmd) {
637 .action_type = MLX5_MODIFICATION_TYPE_SET,
639 .length = field->size,
640 .offset = field->offset,
642 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
643 actions[i].data1 = conf->vlan_vid;
644 actions[i].data1 = actions[i].data1 << 16;
645 resource->actions_num = ++i;
650 * Convert modify-header set TP action to DV specification.
652 * @param[in,out] resource
653 * Pointer to the modify-header resource.
655 * Pointer to action specification.
657 * Pointer to rte_flow_item objects list.
659 * Pointer to flow attributes structure.
660 * @param[in] dev_flow
661 * Pointer to the sub flow.
662 * @param[in] tunnel_decap
663 * Whether action is after tunnel decapsulation.
665 * Pointer to the error structure.
668 * 0 on success, a negative errno value otherwise and rte_errno is set.
671 flow_dv_convert_action_modify_tp
672 (struct mlx5_flow_dv_modify_hdr_resource *resource,
673 const struct rte_flow_action *action,
674 const struct rte_flow_item *items,
675 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
676 bool tunnel_decap, struct rte_flow_error *error)
678 const struct rte_flow_action_set_tp *conf =
679 (const struct rte_flow_action_set_tp *)(action->conf);
680 struct rte_flow_item item;
681 struct rte_flow_item_udp udp;
682 struct rte_flow_item_udp udp_mask;
683 struct rte_flow_item_tcp tcp;
684 struct rte_flow_item_tcp tcp_mask;
685 struct field_modify_info *field;
688 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
690 memset(&udp, 0, sizeof(udp));
691 memset(&udp_mask, 0, sizeof(udp_mask));
692 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
693 udp.hdr.src_port = conf->port;
694 udp_mask.hdr.src_port =
695 rte_flow_item_udp_mask.hdr.src_port;
697 udp.hdr.dst_port = conf->port;
698 udp_mask.hdr.dst_port =
699 rte_flow_item_udp_mask.hdr.dst_port;
701 item.type = RTE_FLOW_ITEM_TYPE_UDP;
703 item.mask = &udp_mask;
707 memset(&tcp, 0, sizeof(tcp));
708 memset(&tcp_mask, 0, sizeof(tcp_mask));
709 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
710 tcp.hdr.src_port = conf->port;
711 tcp_mask.hdr.src_port =
712 rte_flow_item_tcp_mask.hdr.src_port;
714 tcp.hdr.dst_port = conf->port;
715 tcp_mask.hdr.dst_port =
716 rte_flow_item_tcp_mask.hdr.dst_port;
718 item.type = RTE_FLOW_ITEM_TYPE_TCP;
720 item.mask = &tcp_mask;
723 return flow_dv_convert_modify_action(&item, field, NULL, resource,
724 MLX5_MODIFICATION_TYPE_SET, error);
728 * Convert modify-header set TTL action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_ttl
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_ttl *conf =
757 (const struct rte_flow_action_set_ttl *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_ipv4 ipv4;
760 struct rte_flow_item_ipv4 ipv4_mask;
761 struct rte_flow_item_ipv6 ipv6;
762 struct rte_flow_item_ipv6 ipv6_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&ipv4, 0, sizeof(ipv4));
769 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
770 ipv4.hdr.time_to_live = conf->ttl_value;
771 ipv4_mask.hdr.time_to_live = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
774 item.mask = &ipv4_mask;
778 memset(&ipv6, 0, sizeof(ipv6));
779 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
780 ipv6.hdr.hop_limits = conf->ttl_value;
781 ipv6_mask.hdr.hop_limits = 0xFF;
782 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
784 item.mask = &ipv6_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header decrement TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_dec_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_item *items,
816 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
817 bool tunnel_decap, struct rte_flow_error *error)
819 struct rte_flow_item item;
820 struct rte_flow_item_ipv4 ipv4;
821 struct rte_flow_item_ipv4 ipv4_mask;
822 struct rte_flow_item_ipv6 ipv6;
823 struct rte_flow_item_ipv6 ipv6_mask;
824 struct field_modify_info *field;
827 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
829 memset(&ipv4, 0, sizeof(ipv4));
830 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
831 ipv4.hdr.time_to_live = 0xFF;
832 ipv4_mask.hdr.time_to_live = 0xFF;
833 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
835 item.mask = &ipv4_mask;
839 memset(&ipv6, 0, sizeof(ipv6));
840 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
841 ipv6.hdr.hop_limits = 0xFF;
842 ipv6_mask.hdr.hop_limits = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
845 item.mask = &ipv6_mask;
848 return flow_dv_convert_modify_action(&item, field, NULL, resource,
849 MLX5_MODIFICATION_TYPE_ADD, error);
853 * Convert modify-header increment/decrement TCP Sequence number
854 * to DV specification.
856 * @param[in,out] resource
857 * Pointer to the modify-header resource.
859 * Pointer to action specification.
861 * Pointer to the error structure.
864 * 0 on success, a negative errno value otherwise and rte_errno is set.
867 flow_dv_convert_action_modify_tcp_seq
868 (struct mlx5_flow_dv_modify_hdr_resource *resource,
869 const struct rte_flow_action *action,
870 struct rte_flow_error *error)
872 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
873 uint64_t value = rte_be_to_cpu_32(*conf);
874 struct rte_flow_item item;
875 struct rte_flow_item_tcp tcp;
876 struct rte_flow_item_tcp tcp_mask;
878 memset(&tcp, 0, sizeof(tcp));
879 memset(&tcp_mask, 0, sizeof(tcp_mask));
880 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
882 * The HW has no decrement operation, only increment operation.
883 * To simulate decrement X from Y using increment operation
884 * we need to add UINT32_MAX X times to Y.
885 * Each adding of UINT32_MAX decrements Y by 1.
888 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
889 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
890 item.type = RTE_FLOW_ITEM_TYPE_TCP;
892 item.mask = &tcp_mask;
893 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
894 MLX5_MODIFICATION_TYPE_ADD, error);
898 * Convert modify-header increment/decrement TCP Acknowledgment number
899 * to DV specification.
901 * @param[in,out] resource
902 * Pointer to the modify-header resource.
904 * Pointer to action specification.
906 * Pointer to the error structure.
909 * 0 on success, a negative errno value otherwise and rte_errno is set.
912 flow_dv_convert_action_modify_tcp_ack
913 (struct mlx5_flow_dv_modify_hdr_resource *resource,
914 const struct rte_flow_action *action,
915 struct rte_flow_error *error)
917 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
918 uint64_t value = rte_be_to_cpu_32(*conf);
919 struct rte_flow_item item;
920 struct rte_flow_item_tcp tcp;
921 struct rte_flow_item_tcp tcp_mask;
923 memset(&tcp, 0, sizeof(tcp));
924 memset(&tcp_mask, 0, sizeof(tcp_mask));
925 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
927 * The HW has no decrement operation, only increment operation.
928 * To simulate decrement X from Y using increment operation
929 * we need to add UINT32_MAX X times to Y.
930 * Each adding of UINT32_MAX decrements Y by 1.
933 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
934 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
935 item.type = RTE_FLOW_ITEM_TYPE_TCP;
937 item.mask = &tcp_mask;
938 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
939 MLX5_MODIFICATION_TYPE_ADD, error);
942 static enum mlx5_modification_field reg_to_field[] = {
943 [REG_NONE] = MLX5_MODI_OUT_NONE,
944 [REG_A] = MLX5_MODI_META_DATA_REG_A,
945 [REG_B] = MLX5_MODI_META_DATA_REG_B,
946 [REG_C_0] = MLX5_MODI_META_REG_C_0,
947 [REG_C_1] = MLX5_MODI_META_REG_C_1,
948 [REG_C_2] = MLX5_MODI_META_REG_C_2,
949 [REG_C_3] = MLX5_MODI_META_REG_C_3,
950 [REG_C_4] = MLX5_MODI_META_REG_C_4,
951 [REG_C_5] = MLX5_MODI_META_REG_C_5,
952 [REG_C_6] = MLX5_MODI_META_REG_C_6,
953 [REG_C_7] = MLX5_MODI_META_REG_C_7,
957 * Convert register set to DV specification.
959 * @param[in,out] resource
960 * Pointer to the modify-header resource.
962 * Pointer to action specification.
964 * Pointer to the error structure.
967 * 0 on success, a negative errno value otherwise and rte_errno is set.
970 flow_dv_convert_action_set_reg
971 (struct mlx5_flow_dv_modify_hdr_resource *resource,
972 const struct rte_flow_action *action,
973 struct rte_flow_error *error)
975 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
976 struct mlx5_modification_cmd *actions = resource->actions;
977 uint32_t i = resource->actions_num;
979 if (i >= MLX5_MAX_MODIFY_NUM)
980 return rte_flow_error_set(error, EINVAL,
981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
982 "too many items to modify");
983 MLX5_ASSERT(conf->id != REG_NONE);
984 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
985 actions[i] = (struct mlx5_modification_cmd) {
986 .action_type = MLX5_MODIFICATION_TYPE_SET,
987 .field = reg_to_field[conf->id],
989 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
990 actions[i].data1 = rte_cpu_to_be_32(conf->data);
992 resource->actions_num = i;
997 * Convert SET_TAG action to DV specification.
1000 * Pointer to the rte_eth_dev structure.
1001 * @param[in,out] resource
1002 * Pointer to the modify-header resource.
1004 * Pointer to action specification.
1006 * Pointer to the error structure.
1009 * 0 on success, a negative errno value otherwise and rte_errno is set.
1012 flow_dv_convert_action_set_tag
1013 (struct rte_eth_dev *dev,
1014 struct mlx5_flow_dv_modify_hdr_resource *resource,
1015 const struct rte_flow_action_set_tag *conf,
1016 struct rte_flow_error *error)
1018 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1019 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1020 struct rte_flow_item item = {
1024 struct field_modify_info reg_c_x[] = {
1027 enum mlx5_modification_field reg_type;
1030 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1033 MLX5_ASSERT(ret != REG_NONE);
1034 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1035 reg_type = reg_to_field[ret];
1036 MLX5_ASSERT(reg_type > 0);
1037 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1038 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1039 MLX5_MODIFICATION_TYPE_SET, error);
1043 * Convert internal COPY_REG action to DV specification.
1046 * Pointer to the rte_eth_dev structure.
1047 * @param[in,out] res
1048 * Pointer to the modify-header resource.
1050 * Pointer to action specification.
1052 * Pointer to the error structure.
1055 * 0 on success, a negative errno value otherwise and rte_errno is set.
1058 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1059 struct mlx5_flow_dv_modify_hdr_resource *res,
1060 const struct rte_flow_action *action,
1061 struct rte_flow_error *error)
1063 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1064 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1065 struct rte_flow_item item = {
1069 struct field_modify_info reg_src[] = {
1070 {4, 0, reg_to_field[conf->src]},
1073 struct field_modify_info reg_dst = {
1075 .id = reg_to_field[conf->dst],
1077 /* Adjust reg_c[0] usage according to reported mask. */
1078 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1079 struct mlx5_priv *priv = dev->data->dev_private;
1080 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1082 MLX5_ASSERT(reg_c0);
1083 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1084 if (conf->dst == REG_C_0) {
1085 /* Copy to reg_c[0], within mask only. */
1086 reg_dst.offset = rte_bsf32(reg_c0);
1088 * Mask is ignoring the enianness, because
1089 * there is no conversion in datapath.
1091 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1092 /* Copy from destination lower bits to reg_c[0]. */
1093 mask = reg_c0 >> reg_dst.offset;
1095 /* Copy from destination upper bits to reg_c[0]. */
1096 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1097 rte_fls_u32(reg_c0));
1100 mask = rte_cpu_to_be_32(reg_c0);
1101 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1102 /* Copy from reg_c[0] to destination lower bits. */
1105 /* Copy from reg_c[0] to destination upper bits. */
1106 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1107 (rte_fls_u32(reg_c0) -
1112 return flow_dv_convert_modify_action(&item,
1113 reg_src, ®_dst, res,
1114 MLX5_MODIFICATION_TYPE_COPY,
1119 * Convert MARK action to DV specification. This routine is used
1120 * in extensive metadata only and requires metadata register to be
1121 * handled. In legacy mode hardware tag resource is engaged.
1124 * Pointer to the rte_eth_dev structure.
1126 * Pointer to MARK action specification.
1127 * @param[in,out] resource
1128 * Pointer to the modify-header resource.
1130 * Pointer to the error structure.
1133 * 0 on success, a negative errno value otherwise and rte_errno is set.
1136 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1137 const struct rte_flow_action_mark *conf,
1138 struct mlx5_flow_dv_modify_hdr_resource *resource,
1139 struct rte_flow_error *error)
1141 struct mlx5_priv *priv = dev->data->dev_private;
1142 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1143 priv->sh->dv_mark_mask);
1144 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_c_x[] = {
1150 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1156 return rte_flow_error_set(error, EINVAL,
1157 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1158 NULL, "zero mark action mask");
1159 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1162 MLX5_ASSERT(reg > 0);
1163 if (reg == REG_C_0) {
1164 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1165 uint32_t shl_c0 = rte_bsf32(msk_c0);
1167 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1168 mask = rte_cpu_to_be_32(mask) & msk_c0;
1169 mask = rte_cpu_to_be_32(mask << shl_c0);
1171 reg_c_x[0].id = reg_to_field[reg];
1172 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1173 MLX5_MODIFICATION_TYPE_SET, error);
1177 * Get metadata register index for specified steering domain.
1180 * Pointer to the rte_eth_dev structure.
1182 * Attributes of flow to determine steering domain.
1184 * Pointer to the error structure.
1187 * positive index on success, a negative errno value otherwise
1188 * and rte_errno is set.
1190 static enum modify_reg
1191 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1192 const struct rte_flow_attr *attr,
1193 struct rte_flow_error *error)
1196 mlx5_flow_get_reg_id(dev, attr->transfer ?
1200 MLX5_METADATA_RX, 0, error);
1202 return rte_flow_error_set(error,
1203 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1204 NULL, "unavailable "
1205 "metadata register");
1210 * Convert SET_META action to DV specification.
1213 * Pointer to the rte_eth_dev structure.
1214 * @param[in,out] resource
1215 * Pointer to the modify-header resource.
1217 * Attributes of flow that includes this item.
1219 * Pointer to action specification.
1221 * Pointer to the error structure.
1224 * 0 on success, a negative errno value otherwise and rte_errno is set.
1227 flow_dv_convert_action_set_meta
1228 (struct rte_eth_dev *dev,
1229 struct mlx5_flow_dv_modify_hdr_resource *resource,
1230 const struct rte_flow_attr *attr,
1231 const struct rte_flow_action_set_meta *conf,
1232 struct rte_flow_error *error)
1234 uint32_t data = conf->data;
1235 uint32_t mask = conf->mask;
1236 struct rte_flow_item item = {
1240 struct field_modify_info reg_c_x[] = {
1243 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1248 * In datapath code there is no endianness
1249 * coversions for perfromance reasons, all
1250 * pattern conversions are done in rte_flow.
1252 if (reg == REG_C_0) {
1253 struct mlx5_priv *priv = dev->data->dev_private;
1254 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1257 MLX5_ASSERT(msk_c0);
1258 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1259 shl_c0 = rte_bsf32(msk_c0);
1261 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1265 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1267 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1268 /* The routine expects parameters in memory as big-endian ones. */
1269 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1270 MLX5_MODIFICATION_TYPE_SET, error);
1274 * Convert modify-header set IPv4 DSCP action to DV specification.
1276 * @param[in,out] resource
1277 * Pointer to the modify-header resource.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_modify_ipv4_dscp
1288 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1289 const struct rte_flow_action *action,
1290 struct rte_flow_error *error)
1292 const struct rte_flow_action_set_dscp *conf =
1293 (const struct rte_flow_action_set_dscp *)(action->conf);
1294 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1295 struct rte_flow_item_ipv4 ipv4;
1296 struct rte_flow_item_ipv4 ipv4_mask;
1298 memset(&ipv4, 0, sizeof(ipv4));
1299 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1300 ipv4.hdr.type_of_service = conf->dscp;
1301 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1303 item.mask = &ipv4_mask;
1304 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1305 MLX5_MODIFICATION_TYPE_SET, error);
1309 * Convert modify-header set IPv6 DSCP action to DV specification.
1311 * @param[in,out] resource
1312 * Pointer to the modify-header resource.
1314 * Pointer to action specification.
1316 * Pointer to the error structure.
1319 * 0 on success, a negative errno value otherwise and rte_errno is set.
1322 flow_dv_convert_action_modify_ipv6_dscp
1323 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1324 const struct rte_flow_action *action,
1325 struct rte_flow_error *error)
1327 const struct rte_flow_action_set_dscp *conf =
1328 (const struct rte_flow_action_set_dscp *)(action->conf);
1329 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1330 struct rte_flow_item_ipv6 ipv6;
1331 struct rte_flow_item_ipv6 ipv6_mask;
1333 memset(&ipv6, 0, sizeof(ipv6));
1334 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1336 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1337 * rdma-core only accept the DSCP bits byte aligned start from
1338 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1339 * bits in IPv6 case as rdma-core requires byte aligned value.
1341 ipv6.hdr.vtc_flow = conf->dscp;
1342 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1344 item.mask = &ipv6_mask;
1345 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1346 MLX5_MODIFICATION_TYPE_SET, error);
1350 * Validate MARK item.
1353 * Pointer to the rte_eth_dev structure.
1355 * Item specification.
1357 * Attributes of flow that includes this item.
1359 * Pointer to error structure.
1362 * 0 on success, a negative errno value otherwise and rte_errno is set.
1365 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1366 const struct rte_flow_item *item,
1367 const struct rte_flow_attr *attr __rte_unused,
1368 struct rte_flow_error *error)
1370 struct mlx5_priv *priv = dev->data->dev_private;
1371 struct mlx5_dev_config *config = &priv->config;
1372 const struct rte_flow_item_mark *spec = item->spec;
1373 const struct rte_flow_item_mark *mask = item->mask;
1374 const struct rte_flow_item_mark nic_mask = {
1375 .id = priv->sh->dv_mark_mask,
1379 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1380 return rte_flow_error_set(error, ENOTSUP,
1381 RTE_FLOW_ERROR_TYPE_ITEM, item,
1382 "extended metadata feature"
1384 if (!mlx5_flow_ext_mreg_supported(dev))
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata register"
1388 " isn't supported");
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't available");
1394 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1398 return rte_flow_error_set(error, EINVAL,
1399 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1401 "data cannot be empty");
1402 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1406 "mark id exceeds the limit");
1409 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1410 (const uint8_t *)&nic_mask,
1411 sizeof(struct rte_flow_item_mark),
1419 * Validate META item.
1422 * Pointer to the rte_eth_dev structure.
1424 * Item specification.
1426 * Attributes of flow that includes this item.
1428 * Pointer to error structure.
1431 * 0 on success, a negative errno value otherwise and rte_errno is set.
1434 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1435 const struct rte_flow_item *item,
1436 const struct rte_flow_attr *attr,
1437 struct rte_flow_error *error)
1439 struct mlx5_priv *priv = dev->data->dev_private;
1440 struct mlx5_dev_config *config = &priv->config;
1441 const struct rte_flow_item_meta *spec = item->spec;
1442 const struct rte_flow_item_meta *mask = item->mask;
1443 struct rte_flow_item_meta nic_mask = {
1450 return rte_flow_error_set(error, EINVAL,
1451 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1453 "data cannot be empty");
1455 return rte_flow_error_set(error, EINVAL,
1456 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1457 "data cannot be zero");
1458 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1459 if (!mlx5_flow_ext_mreg_supported(dev))
1460 return rte_flow_error_set(error, ENOTSUP,
1461 RTE_FLOW_ERROR_TYPE_ITEM, item,
1462 "extended metadata register"
1463 " isn't supported");
1464 reg = flow_dv_get_metadata_reg(dev, attr, error);
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ITEM, item,
1473 nic_mask.data = priv->sh->dv_meta_mask;
1476 mask = &rte_flow_item_meta_mask;
1477 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1478 (const uint8_t *)&nic_mask,
1479 sizeof(struct rte_flow_item_meta),
1485 * Validate TAG item.
1488 * Pointer to the rte_eth_dev structure.
1490 * Item specification.
1492 * Attributes of flow that includes this item.
1494 * Pointer to error structure.
1497 * 0 on success, a negative errno value otherwise and rte_errno is set.
1500 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1501 const struct rte_flow_item *item,
1502 const struct rte_flow_attr *attr __rte_unused,
1503 struct rte_flow_error *error)
1505 const struct rte_flow_item_tag *spec = item->spec;
1506 const struct rte_flow_item_tag *mask = item->mask;
1507 const struct rte_flow_item_tag nic_mask = {
1508 .data = RTE_BE32(UINT32_MAX),
1513 if (!mlx5_flow_ext_mreg_supported(dev))
1514 return rte_flow_error_set(error, ENOTSUP,
1515 RTE_FLOW_ERROR_TYPE_ITEM, item,
1516 "extensive metadata register"
1517 " isn't supported");
1519 return rte_flow_error_set(error, EINVAL,
1520 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1522 "data cannot be empty");
1524 mask = &rte_flow_item_tag_mask;
1525 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1526 (const uint8_t *)&nic_mask,
1527 sizeof(struct rte_flow_item_tag),
1531 if (mask->index != 0xff)
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1534 "partial mask for tag index"
1535 " is not supported");
1536 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1539 MLX5_ASSERT(ret != REG_NONE);
1544 * Validate vport item.
1547 * Pointer to the rte_eth_dev structure.
1549 * Item specification.
1551 * Attributes of flow that includes this item.
1552 * @param[in] item_flags
1553 * Bit-fields that holds the items detected until now.
1555 * Pointer to error structure.
1558 * 0 on success, a negative errno value otherwise and rte_errno is set.
1561 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1562 const struct rte_flow_item *item,
1563 const struct rte_flow_attr *attr,
1564 uint64_t item_flags,
1565 struct rte_flow_error *error)
1567 const struct rte_flow_item_port_id *spec = item->spec;
1568 const struct rte_flow_item_port_id *mask = item->mask;
1569 const struct rte_flow_item_port_id switch_mask = {
1572 struct mlx5_priv *esw_priv;
1573 struct mlx5_priv *dev_priv;
1576 if (!attr->transfer)
1577 return rte_flow_error_set(error, EINVAL,
1578 RTE_FLOW_ERROR_TYPE_ITEM,
1580 "match on port id is valid only"
1581 " when transfer flag is enabled");
1582 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1583 return rte_flow_error_set(error, ENOTSUP,
1584 RTE_FLOW_ERROR_TYPE_ITEM, item,
1585 "multiple source ports are not"
1588 mask = &switch_mask;
1589 if (mask->id != 0xffffffff)
1590 return rte_flow_error_set(error, ENOTSUP,
1591 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1593 "no support for partial mask on"
1595 ret = mlx5_flow_item_acceptable
1596 (item, (const uint8_t *)mask,
1597 (const uint8_t *)&rte_flow_item_port_id_mask,
1598 sizeof(struct rte_flow_item_port_id),
1604 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1606 return rte_flow_error_set(error, rte_errno,
1607 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1608 "failed to obtain E-Switch info for"
1610 dev_priv = mlx5_dev_to_eswitch_info(dev);
1612 return rte_flow_error_set(error, rte_errno,
1613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1615 "failed to obtain E-Switch info");
1616 if (esw_priv->domain_id != dev_priv->domain_id)
1617 return rte_flow_error_set(error, EINVAL,
1618 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1619 "cannot match on a port from a"
1620 " different E-Switch");
1625 * Validate GTP item.
1628 * Pointer to the rte_eth_dev structure.
1630 * Item specification.
1631 * @param[in] item_flags
1632 * Bit-fields that holds the items detected until now.
1634 * Pointer to error structure.
1637 * 0 on success, a negative errno value otherwise and rte_errno is set.
1640 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1641 const struct rte_flow_item *item,
1642 uint64_t item_flags,
1643 struct rte_flow_error *error)
1645 struct mlx5_priv *priv = dev->data->dev_private;
1646 const struct rte_flow_item_gtp *mask = item->mask;
1647 const struct rte_flow_item_gtp nic_mask = {
1649 .teid = RTE_BE32(0xffffffff),
1652 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1653 return rte_flow_error_set(error, ENOTSUP,
1654 RTE_FLOW_ERROR_TYPE_ITEM, item,
1655 "GTP support is not enabled");
1656 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1657 return rte_flow_error_set(error, ENOTSUP,
1658 RTE_FLOW_ERROR_TYPE_ITEM, item,
1659 "multiple tunnel layers not"
1661 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1662 return rte_flow_error_set(error, EINVAL,
1663 RTE_FLOW_ERROR_TYPE_ITEM, item,
1664 "no outer UDP layer found");
1666 mask = &rte_flow_item_gtp_mask;
1667 return mlx5_flow_item_acceptable
1668 (item, (const uint8_t *)mask,
1669 (const uint8_t *)&nic_mask,
1670 sizeof(struct rte_flow_item_gtp),
1675 * Validate the pop VLAN action.
1678 * Pointer to the rte_eth_dev structure.
1679 * @param[in] action_flags
1680 * Holds the actions detected until now.
1682 * Pointer to the pop vlan action.
1683 * @param[in] item_flags
1684 * The items found in this flow rule.
1686 * Pointer to flow attributes.
1688 * Pointer to error structure.
1691 * 0 on success, a negative errno value otherwise and rte_errno is set.
1694 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1695 uint64_t action_flags,
1696 const struct rte_flow_action *action,
1697 uint64_t item_flags,
1698 const struct rte_flow_attr *attr,
1699 struct rte_flow_error *error)
1701 struct mlx5_priv *priv = dev->data->dev_private;
1705 if (!priv->sh->pop_vlan_action)
1706 return rte_flow_error_set(error, ENOTSUP,
1707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1709 "pop vlan action is not supported");
1711 return rte_flow_error_set(error, ENOTSUP,
1712 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1714 "pop vlan action not supported for "
1716 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1717 return rte_flow_error_set(error, ENOTSUP,
1718 RTE_FLOW_ERROR_TYPE_ACTION, action,
1719 "no support for multiple VLAN "
1721 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1722 return rte_flow_error_set(error, ENOTSUP,
1723 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1725 "cannot pop vlan without a "
1726 "match on (outer) vlan in the flow");
1727 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1728 return rte_flow_error_set(error, EINVAL,
1729 RTE_FLOW_ERROR_TYPE_ACTION, action,
1730 "wrong action order, port_id should "
1731 "be after pop VLAN action");
1736 * Get VLAN default info from vlan match info.
1739 * the list of item specifications.
1741 * pointer VLAN info to fill to.
1744 * 0 on success, a negative errno value otherwise and rte_errno is set.
1747 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1748 struct rte_vlan_hdr *vlan)
1750 const struct rte_flow_item_vlan nic_mask = {
1751 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1752 MLX5DV_FLOW_VLAN_VID_MASK),
1753 .inner_type = RTE_BE16(0xffff),
1758 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1759 int type = items->type;
1761 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1762 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1765 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1766 const struct rte_flow_item_vlan *vlan_m = items->mask;
1767 const struct rte_flow_item_vlan *vlan_v = items->spec;
1771 /* Only full match values are accepted */
1772 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1773 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1774 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1776 rte_be_to_cpu_16(vlan_v->tci &
1777 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1779 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1780 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1781 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1783 rte_be_to_cpu_16(vlan_v->tci &
1784 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1786 if (vlan_m->inner_type == nic_mask.inner_type)
1787 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1788 vlan_m->inner_type);
1793 * Validate the push VLAN action.
1795 * @param[in] action_flags
1796 * Holds the actions detected until now.
1797 * @param[in] item_flags
1798 * The items found in this flow rule.
1800 * Pointer to the action structure.
1802 * Pointer to flow attributes
1804 * Pointer to error structure.
1807 * 0 on success, a negative errno value otherwise and rte_errno is set.
1810 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1811 uint64_t item_flags __rte_unused,
1812 const struct rte_flow_action *action,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1818 if (!attr->transfer && attr->ingress)
1819 return rte_flow_error_set(error, ENOTSUP,
1820 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1822 "push VLAN action not supported for "
1824 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1825 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1826 return rte_flow_error_set(error, EINVAL,
1827 RTE_FLOW_ERROR_TYPE_ACTION, action,
1828 "invalid vlan ethertype");
1829 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1830 return rte_flow_error_set(error, ENOTSUP,
1831 RTE_FLOW_ERROR_TYPE_ACTION, action,
1832 "no support for multiple VLAN "
1834 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1835 return rte_flow_error_set(error, EINVAL,
1836 RTE_FLOW_ERROR_TYPE_ACTION, action,
1837 "wrong action order, port_id should "
1838 "be after push VLAN");
1844 * Validate the set VLAN PCP.
1846 * @param[in] action_flags
1847 * Holds the actions detected until now.
1848 * @param[in] actions
1849 * Pointer to the list of actions remaining in the flow rule.
1851 * Pointer to error structure.
1854 * 0 on success, a negative errno value otherwise and rte_errno is set.
1857 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1858 const struct rte_flow_action actions[],
1859 struct rte_flow_error *error)
1861 const struct rte_flow_action *action = actions;
1862 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1864 if (conf->vlan_pcp > 7)
1865 return rte_flow_error_set(error, EINVAL,
1866 RTE_FLOW_ERROR_TYPE_ACTION, action,
1867 "VLAN PCP value is too big");
1868 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1869 return rte_flow_error_set(error, ENOTSUP,
1870 RTE_FLOW_ERROR_TYPE_ACTION, action,
1871 "set VLAN PCP action must follow "
1872 "the push VLAN action");
1873 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1874 return rte_flow_error_set(error, ENOTSUP,
1875 RTE_FLOW_ERROR_TYPE_ACTION, action,
1876 "Multiple VLAN PCP modification are "
1878 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1879 return rte_flow_error_set(error, EINVAL,
1880 RTE_FLOW_ERROR_TYPE_ACTION, action,
1881 "wrong action order, port_id should "
1882 "be after set VLAN PCP");
1887 * Validate the set VLAN VID.
1889 * @param[in] item_flags
1890 * Holds the items detected in this rule.
1891 * @param[in] action_flags
1892 * Holds the actions detected until now.
1893 * @param[in] actions
1894 * Pointer to the list of actions remaining in the flow rule.
1896 * Pointer to error structure.
1899 * 0 on success, a negative errno value otherwise and rte_errno is set.
1902 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1903 uint64_t action_flags,
1904 const struct rte_flow_action actions[],
1905 struct rte_flow_error *error)
1907 const struct rte_flow_action *action = actions;
1908 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1910 if (conf->vlan_vid > RTE_BE16(0xFFE))
1911 return rte_flow_error_set(error, EINVAL,
1912 RTE_FLOW_ERROR_TYPE_ACTION, action,
1913 "VLAN VID value is too big");
1914 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1915 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1916 return rte_flow_error_set(error, ENOTSUP,
1917 RTE_FLOW_ERROR_TYPE_ACTION, action,
1918 "set VLAN VID action must follow push"
1919 " VLAN action or match on VLAN item");
1920 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1921 return rte_flow_error_set(error, ENOTSUP,
1922 RTE_FLOW_ERROR_TYPE_ACTION, action,
1923 "Multiple VLAN VID modifications are "
1925 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1926 return rte_flow_error_set(error, EINVAL,
1927 RTE_FLOW_ERROR_TYPE_ACTION, action,
1928 "wrong action order, port_id should "
1929 "be after set VLAN VID");
1934 * Validate the FLAG action.
1937 * Pointer to the rte_eth_dev structure.
1938 * @param[in] action_flags
1939 * Holds the actions detected until now.
1941 * Pointer to flow attributes
1943 * Pointer to error structure.
1946 * 0 on success, a negative errno value otherwise and rte_errno is set.
1949 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1950 uint64_t action_flags,
1951 const struct rte_flow_attr *attr,
1952 struct rte_flow_error *error)
1954 struct mlx5_priv *priv = dev->data->dev_private;
1955 struct mlx5_dev_config *config = &priv->config;
1958 /* Fall back if no extended metadata register support. */
1959 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1960 return mlx5_flow_validate_action_flag(action_flags, attr,
1962 /* Extensive metadata mode requires registers. */
1963 if (!mlx5_flow_ext_mreg_supported(dev))
1964 return rte_flow_error_set(error, ENOTSUP,
1965 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1966 "no metadata registers "
1967 "to support flag action");
1968 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1969 return rte_flow_error_set(error, ENOTSUP,
1970 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1971 "extended metadata register"
1972 " isn't available");
1973 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1976 MLX5_ASSERT(ret > 0);
1977 if (action_flags & MLX5_FLOW_ACTION_MARK)
1978 return rte_flow_error_set(error, EINVAL,
1979 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1980 "can't mark and flag in same flow");
1981 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1982 return rte_flow_error_set(error, EINVAL,
1983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1985 " actions in same flow");
1990 * Validate MARK action.
1993 * Pointer to the rte_eth_dev structure.
1995 * Pointer to action.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1999 * Pointer to flow attributes
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2008 const struct rte_flow_action *action,
2009 uint64_t action_flags,
2010 const struct rte_flow_attr *attr,
2011 struct rte_flow_error *error)
2013 struct mlx5_priv *priv = dev->data->dev_private;
2014 struct mlx5_dev_config *config = &priv->config;
2015 const struct rte_flow_action_mark *mark = action->conf;
2018 /* Fall back if no extended metadata register support. */
2019 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2020 return mlx5_flow_validate_action_mark(action, action_flags,
2022 /* Extensive metadata mode requires registers. */
2023 if (!mlx5_flow_ext_mreg_supported(dev))
2024 return rte_flow_error_set(error, ENOTSUP,
2025 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2026 "no metadata registers "
2027 "to support mark action");
2028 if (!priv->sh->dv_mark_mask)
2029 return rte_flow_error_set(error, ENOTSUP,
2030 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2031 "extended metadata register"
2032 " isn't available");
2033 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2036 MLX5_ASSERT(ret > 0);
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ACTION, action,
2040 "configuration cannot be null");
2041 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2042 return rte_flow_error_set(error, EINVAL,
2043 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2045 "mark id exceeds the limit");
2046 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2047 return rte_flow_error_set(error, EINVAL,
2048 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2049 "can't flag and mark in same flow");
2050 if (action_flags & MLX5_FLOW_ACTION_MARK)
2051 return rte_flow_error_set(error, EINVAL,
2052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2053 "can't have 2 mark actions in same"
2059 * Validate SET_META action.
2062 * Pointer to the rte_eth_dev structure.
2064 * Pointer to the action structure.
2065 * @param[in] action_flags
2066 * Holds the actions detected until now.
2068 * Pointer to flow attributes
2070 * Pointer to error structure.
2073 * 0 on success, a negative errno value otherwise and rte_errno is set.
2076 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2077 const struct rte_flow_action *action,
2078 uint64_t action_flags __rte_unused,
2079 const struct rte_flow_attr *attr,
2080 struct rte_flow_error *error)
2082 const struct rte_flow_action_set_meta *conf;
2083 uint32_t nic_mask = UINT32_MAX;
2086 if (!mlx5_flow_ext_mreg_supported(dev))
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ACTION, action,
2089 "extended metadata register"
2090 " isn't supported");
2091 reg = flow_dv_get_metadata_reg(dev, attr, error);
2094 if (reg != REG_A && reg != REG_B) {
2095 struct mlx5_priv *priv = dev->data->dev_private;
2097 nic_mask = priv->sh->dv_meta_mask;
2099 if (!(action->conf))
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ACTION, action,
2102 "configuration cannot be null");
2103 conf = (const struct rte_flow_action_set_meta *)action->conf;
2105 return rte_flow_error_set(error, EINVAL,
2106 RTE_FLOW_ERROR_TYPE_ACTION, action,
2107 "zero mask doesn't have any effect");
2108 if (conf->mask & ~nic_mask)
2109 return rte_flow_error_set(error, EINVAL,
2110 RTE_FLOW_ERROR_TYPE_ACTION, action,
2111 "meta data must be within reg C0");
2112 if (!(conf->data & conf->mask))
2113 return rte_flow_error_set(error, EINVAL,
2114 RTE_FLOW_ERROR_TYPE_ACTION, action,
2115 "zero value has no effect");
2120 * Validate SET_TAG action.
2123 * Pointer to the rte_eth_dev structure.
2125 * Pointer to the action structure.
2126 * @param[in] action_flags
2127 * Holds the actions detected until now.
2129 * Pointer to flow attributes
2131 * Pointer to error structure.
2134 * 0 on success, a negative errno value otherwise and rte_errno is set.
2137 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2138 const struct rte_flow_action *action,
2139 uint64_t action_flags,
2140 const struct rte_flow_attr *attr,
2141 struct rte_flow_error *error)
2143 const struct rte_flow_action_set_tag *conf;
2144 const uint64_t terminal_action_flags =
2145 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2146 MLX5_FLOW_ACTION_RSS;
2149 if (!mlx5_flow_ext_mreg_supported(dev))
2150 return rte_flow_error_set(error, ENOTSUP,
2151 RTE_FLOW_ERROR_TYPE_ACTION, action,
2152 "extensive metadata register"
2153 " isn't supported");
2154 if (!(action->conf))
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ACTION, action,
2157 "configuration cannot be null");
2158 conf = (const struct rte_flow_action_set_tag *)action->conf;
2160 return rte_flow_error_set(error, EINVAL,
2161 RTE_FLOW_ERROR_TYPE_ACTION, action,
2162 "zero mask doesn't have any effect");
2163 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2166 if (!attr->transfer && attr->ingress &&
2167 (action_flags & terminal_action_flags))
2168 return rte_flow_error_set(error, EINVAL,
2169 RTE_FLOW_ERROR_TYPE_ACTION, action,
2170 "set_tag has no effect"
2171 " with terminal actions");
2176 * Validate count action.
2179 * Pointer to rte_eth_dev structure.
2181 * Pointer to error structure.
2184 * 0 on success, a negative errno value otherwise and rte_errno is set.
2187 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2188 struct rte_flow_error *error)
2190 struct mlx5_priv *priv = dev->data->dev_private;
2192 if (!priv->config.devx)
2194 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2198 return rte_flow_error_set
2200 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2202 "count action not supported");
2206 * Validate the L2 encap action.
2208 * @param[in] action_flags
2209 * Holds the actions detected until now.
2211 * Pointer to the action structure.
2213 * Pointer to error structure.
2216 * 0 on success, a negative errno value otherwise and rte_errno is set.
2219 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2220 const struct rte_flow_action *action,
2221 struct rte_flow_error *error)
2223 if (!(action->conf))
2224 return rte_flow_error_set(error, EINVAL,
2225 RTE_FLOW_ERROR_TYPE_ACTION, action,
2226 "configuration cannot be null");
2227 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2228 return rte_flow_error_set(error, EINVAL,
2229 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2230 "can only have a single encap action "
2236 * Validate a decap action.
2238 * @param[in] action_flags
2239 * Holds the actions detected until now.
2241 * Pointer to flow attributes
2243 * Pointer to error structure.
2246 * 0 on success, a negative errno value otherwise and rte_errno is set.
2249 flow_dv_validate_action_decap(uint64_t action_flags,
2250 const struct rte_flow_attr *attr,
2251 struct rte_flow_error *error)
2253 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2254 return rte_flow_error_set(error, ENOTSUP,
2255 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2257 MLX5_FLOW_ACTION_DECAP ? "can only "
2258 "have a single decap action" : "decap "
2259 "after encap is not supported");
2260 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2261 return rte_flow_error_set(error, EINVAL,
2262 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2263 "can't have decap action after"
2266 return rte_flow_error_set(error, ENOTSUP,
2267 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2269 "decap action not supported for "
2274 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2277 * Validate the raw encap and decap actions.
2280 * Pointer to the decap action.
2282 * Pointer to the encap action.
2284 * Pointer to flow attributes
2285 * @param[in/out] action_flags
2286 * Holds the actions detected until now.
2287 * @param[out] actions_n
2288 * pointer to the number of actions counter.
2290 * Pointer to error structure.
2293 * 0 on success, a negative errno value otherwise and rte_errno is set.
2296 flow_dv_validate_action_raw_encap_decap
2297 (const struct rte_flow_action_raw_decap *decap,
2298 const struct rte_flow_action_raw_encap *encap,
2299 const struct rte_flow_attr *attr, uint64_t *action_flags,
2300 int *actions_n, struct rte_flow_error *error)
2304 if (encap && (!encap->size || !encap->data))
2305 return rte_flow_error_set(error, EINVAL,
2306 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2307 "raw encap data cannot be empty");
2308 if (decap && encap) {
2309 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2310 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2313 else if (encap->size <=
2314 MLX5_ENCAPSULATION_DECISION_SIZE &&
2316 MLX5_ENCAPSULATION_DECISION_SIZE)
2319 else if (encap->size >
2320 MLX5_ENCAPSULATION_DECISION_SIZE &&
2322 MLX5_ENCAPSULATION_DECISION_SIZE)
2323 /* 2 L2 actions: encap and decap. */
2326 return rte_flow_error_set(error,
2328 RTE_FLOW_ERROR_TYPE_ACTION,
2329 NULL, "unsupported too small "
2330 "raw decap and too small raw "
2331 "encap combination");
2334 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2337 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2341 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2342 return rte_flow_error_set(error, ENOTSUP,
2343 RTE_FLOW_ERROR_TYPE_ACTION,
2345 "small raw encap size");
2346 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2347 return rte_flow_error_set(error, EINVAL,
2348 RTE_FLOW_ERROR_TYPE_ACTION,
2350 "more than one encap action");
2351 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2358 * Find existing encap/decap resource or create and register a new one.
2360 * @param[in, out] dev
2361 * Pointer to rte_eth_dev structure.
2362 * @param[in, out] resource
2363 * Pointer to encap/decap resource.
2364 * @parm[in, out] dev_flow
2365 * Pointer to the dev_flow.
2367 * pointer to error structure.
2370 * 0 on success otherwise -errno and errno is set.
2373 flow_dv_encap_decap_resource_register
2374 (struct rte_eth_dev *dev,
2375 struct mlx5_flow_dv_encap_decap_resource *resource,
2376 struct mlx5_flow *dev_flow,
2377 struct rte_flow_error *error)
2379 struct mlx5_priv *priv = dev->data->dev_private;
2380 struct mlx5_ibv_shared *sh = priv->sh;
2381 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2382 struct mlx5dv_dr_domain *domain;
2384 resource->flags = dev_flow->group ? 0 : 1;
2385 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2386 domain = sh->fdb_domain;
2387 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2388 domain = sh->rx_domain;
2390 domain = sh->tx_domain;
2391 /* Lookup a matching resource from cache. */
2392 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2393 if (resource->reformat_type == cache_resource->reformat_type &&
2394 resource->ft_type == cache_resource->ft_type &&
2395 resource->flags == cache_resource->flags &&
2396 resource->size == cache_resource->size &&
2397 !memcmp((const void *)resource->buf,
2398 (const void *)cache_resource->buf,
2400 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2401 (void *)cache_resource,
2402 rte_atomic32_read(&cache_resource->refcnt));
2403 rte_atomic32_inc(&cache_resource->refcnt);
2404 dev_flow->dv.encap_decap = cache_resource;
2408 /* Register new encap/decap resource. */
2409 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2410 if (!cache_resource)
2411 return rte_flow_error_set(error, ENOMEM,
2412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2413 "cannot allocate resource memory");
2414 *cache_resource = *resource;
2415 cache_resource->verbs_action =
2416 mlx5_glue->dv_create_flow_action_packet_reformat
2417 (sh->ctx, cache_resource->reformat_type,
2418 cache_resource->ft_type, domain, cache_resource->flags,
2419 cache_resource->size,
2420 (cache_resource->size ? cache_resource->buf : NULL));
2421 if (!cache_resource->verbs_action) {
2422 rte_free(cache_resource);
2423 return rte_flow_error_set(error, ENOMEM,
2424 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2425 NULL, "cannot create action");
2427 rte_atomic32_init(&cache_resource->refcnt);
2428 rte_atomic32_inc(&cache_resource->refcnt);
2429 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2430 dev_flow->dv.encap_decap = cache_resource;
2431 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2432 (void *)cache_resource,
2433 rte_atomic32_read(&cache_resource->refcnt));
2438 * Find existing table jump resource or create and register a new one.
2440 * @param[in, out] dev
2441 * Pointer to rte_eth_dev structure.
2442 * @param[in, out] tbl
2443 * Pointer to flow table resource.
2444 * @parm[in, out] dev_flow
2445 * Pointer to the dev_flow.
2447 * pointer to error structure.
2450 * 0 on success otherwise -errno and errno is set.
2453 flow_dv_jump_tbl_resource_register
2454 (struct rte_eth_dev *dev __rte_unused,
2455 struct mlx5_flow_tbl_resource *tbl,
2456 struct mlx5_flow *dev_flow,
2457 struct rte_flow_error *error)
2459 struct mlx5_flow_tbl_data_entry *tbl_data =
2460 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2464 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2466 tbl_data->jump.action =
2467 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2469 if (!tbl_data->jump.action)
2470 return rte_flow_error_set(error, ENOMEM,
2471 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2472 NULL, "cannot create jump action");
2473 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2474 (void *)&tbl_data->jump, cnt);
2476 MLX5_ASSERT(tbl_data->jump.action);
2477 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2478 (void *)&tbl_data->jump, cnt);
2480 rte_atomic32_inc(&tbl_data->jump.refcnt);
2481 dev_flow->dv.jump = &tbl_data->jump;
2486 * Find existing table port ID resource or create and register a new one.
2488 * @param[in, out] dev
2489 * Pointer to rte_eth_dev structure.
2490 * @param[in, out] resource
2491 * Pointer to port ID action resource.
2492 * @parm[in, out] dev_flow
2493 * Pointer to the dev_flow.
2495 * pointer to error structure.
2498 * 0 on success otherwise -errno and errno is set.
2501 flow_dv_port_id_action_resource_register
2502 (struct rte_eth_dev *dev,
2503 struct mlx5_flow_dv_port_id_action_resource *resource,
2504 struct mlx5_flow *dev_flow,
2505 struct rte_flow_error *error)
2507 struct mlx5_priv *priv = dev->data->dev_private;
2508 struct mlx5_ibv_shared *sh = priv->sh;
2509 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2511 /* Lookup a matching resource from cache. */
2512 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2513 if (resource->port_id == cache_resource->port_id) {
2514 DRV_LOG(DEBUG, "port id action resource resource %p: "
2516 (void *)cache_resource,
2517 rte_atomic32_read(&cache_resource->refcnt));
2518 rte_atomic32_inc(&cache_resource->refcnt);
2519 dev_flow->dv.port_id_action = cache_resource;
2523 /* Register new port id action resource. */
2524 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2525 if (!cache_resource)
2526 return rte_flow_error_set(error, ENOMEM,
2527 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2528 "cannot allocate resource memory");
2529 *cache_resource = *resource;
2531 * Depending on rdma_core version the glue routine calls
2532 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2533 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2535 cache_resource->action =
2536 mlx5_glue->dr_create_flow_action_dest_port
2537 (priv->sh->fdb_domain, resource->port_id);
2538 if (!cache_resource->action) {
2539 rte_free(cache_resource);
2540 return rte_flow_error_set(error, ENOMEM,
2541 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2542 NULL, "cannot create action");
2544 rte_atomic32_init(&cache_resource->refcnt);
2545 rte_atomic32_inc(&cache_resource->refcnt);
2546 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2547 dev_flow->dv.port_id_action = cache_resource;
2548 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2549 (void *)cache_resource,
2550 rte_atomic32_read(&cache_resource->refcnt));
2555 * Find existing push vlan resource or create and register a new one.
2557 * @param [in, out] dev
2558 * Pointer to rte_eth_dev structure.
2559 * @param[in, out] resource
2560 * Pointer to port ID action resource.
2561 * @parm[in, out] dev_flow
2562 * Pointer to the dev_flow.
2564 * pointer to error structure.
2567 * 0 on success otherwise -errno and errno is set.
2570 flow_dv_push_vlan_action_resource_register
2571 (struct rte_eth_dev *dev,
2572 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2573 struct mlx5_flow *dev_flow,
2574 struct rte_flow_error *error)
2576 struct mlx5_priv *priv = dev->data->dev_private;
2577 struct mlx5_ibv_shared *sh = priv->sh;
2578 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2579 struct mlx5dv_dr_domain *domain;
2581 /* Lookup a matching resource from cache. */
2582 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2583 if (resource->vlan_tag == cache_resource->vlan_tag &&
2584 resource->ft_type == cache_resource->ft_type) {
2585 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2587 (void *)cache_resource,
2588 rte_atomic32_read(&cache_resource->refcnt));
2589 rte_atomic32_inc(&cache_resource->refcnt);
2590 dev_flow->dv.push_vlan_res = cache_resource;
2594 /* Register new push_vlan action resource. */
2595 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2596 if (!cache_resource)
2597 return rte_flow_error_set(error, ENOMEM,
2598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2599 "cannot allocate resource memory");
2600 *cache_resource = *resource;
2601 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2602 domain = sh->fdb_domain;
2603 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2604 domain = sh->rx_domain;
2606 domain = sh->tx_domain;
2607 cache_resource->action =
2608 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2609 resource->vlan_tag);
2610 if (!cache_resource->action) {
2611 rte_free(cache_resource);
2612 return rte_flow_error_set(error, ENOMEM,
2613 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2614 NULL, "cannot create action");
2616 rte_atomic32_init(&cache_resource->refcnt);
2617 rte_atomic32_inc(&cache_resource->refcnt);
2618 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2619 dev_flow->dv.push_vlan_res = cache_resource;
2620 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2621 (void *)cache_resource,
2622 rte_atomic32_read(&cache_resource->refcnt));
2626 * Get the size of specific rte_flow_item_type
2628 * @param[in] item_type
2629 * Tested rte_flow_item_type.
2632 * sizeof struct item_type, 0 if void or irrelevant.
2635 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2639 switch (item_type) {
2640 case RTE_FLOW_ITEM_TYPE_ETH:
2641 retval = sizeof(struct rte_flow_item_eth);
2643 case RTE_FLOW_ITEM_TYPE_VLAN:
2644 retval = sizeof(struct rte_flow_item_vlan);
2646 case RTE_FLOW_ITEM_TYPE_IPV4:
2647 retval = sizeof(struct rte_flow_item_ipv4);
2649 case RTE_FLOW_ITEM_TYPE_IPV6:
2650 retval = sizeof(struct rte_flow_item_ipv6);
2652 case RTE_FLOW_ITEM_TYPE_UDP:
2653 retval = sizeof(struct rte_flow_item_udp);
2655 case RTE_FLOW_ITEM_TYPE_TCP:
2656 retval = sizeof(struct rte_flow_item_tcp);
2658 case RTE_FLOW_ITEM_TYPE_VXLAN:
2659 retval = sizeof(struct rte_flow_item_vxlan);
2661 case RTE_FLOW_ITEM_TYPE_GRE:
2662 retval = sizeof(struct rte_flow_item_gre);
2664 case RTE_FLOW_ITEM_TYPE_NVGRE:
2665 retval = sizeof(struct rte_flow_item_nvgre);
2667 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2668 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2670 case RTE_FLOW_ITEM_TYPE_MPLS:
2671 retval = sizeof(struct rte_flow_item_mpls);
2673 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2681 #define MLX5_ENCAP_IPV4_VERSION 0x40
2682 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2683 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2684 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2685 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2686 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2687 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2690 * Convert the encap action data from list of rte_flow_item to raw buffer
2693 * Pointer to rte_flow_item objects list.
2695 * Pointer to the output buffer.
2697 * Pointer to the output buffer size.
2699 * Pointer to the error structure.
2702 * 0 on success, a negative errno value otherwise and rte_errno is set.
2705 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2706 size_t *size, struct rte_flow_error *error)
2708 struct rte_ether_hdr *eth = NULL;
2709 struct rte_vlan_hdr *vlan = NULL;
2710 struct rte_ipv4_hdr *ipv4 = NULL;
2711 struct rte_ipv6_hdr *ipv6 = NULL;
2712 struct rte_udp_hdr *udp = NULL;
2713 struct rte_vxlan_hdr *vxlan = NULL;
2714 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2715 struct rte_gre_hdr *gre = NULL;
2717 size_t temp_size = 0;
2720 return rte_flow_error_set(error, EINVAL,
2721 RTE_FLOW_ERROR_TYPE_ACTION,
2722 NULL, "invalid empty data");
2723 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2724 len = flow_dv_get_item_len(items->type);
2725 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2726 return rte_flow_error_set(error, EINVAL,
2727 RTE_FLOW_ERROR_TYPE_ACTION,
2728 (void *)items->type,
2729 "items total size is too big"
2730 " for encap action");
2731 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2732 switch (items->type) {
2733 case RTE_FLOW_ITEM_TYPE_ETH:
2734 eth = (struct rte_ether_hdr *)&buf[temp_size];
2736 case RTE_FLOW_ITEM_TYPE_VLAN:
2737 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2739 return rte_flow_error_set(error, EINVAL,
2740 RTE_FLOW_ERROR_TYPE_ACTION,
2741 (void *)items->type,
2742 "eth header not found");
2743 if (!eth->ether_type)
2744 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2746 case RTE_FLOW_ITEM_TYPE_IPV4:
2747 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2749 return rte_flow_error_set(error, EINVAL,
2750 RTE_FLOW_ERROR_TYPE_ACTION,
2751 (void *)items->type,
2752 "neither eth nor vlan"
2754 if (vlan && !vlan->eth_proto)
2755 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2756 else if (eth && !eth->ether_type)
2757 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2758 if (!ipv4->version_ihl)
2759 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2760 MLX5_ENCAP_IPV4_IHL_MIN;
2761 if (!ipv4->time_to_live)
2762 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2764 case RTE_FLOW_ITEM_TYPE_IPV6:
2765 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2767 return rte_flow_error_set(error, EINVAL,
2768 RTE_FLOW_ERROR_TYPE_ACTION,
2769 (void *)items->type,
2770 "neither eth nor vlan"
2772 if (vlan && !vlan->eth_proto)
2773 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2774 else if (eth && !eth->ether_type)
2775 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2776 if (!ipv6->vtc_flow)
2778 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2779 if (!ipv6->hop_limits)
2780 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2782 case RTE_FLOW_ITEM_TYPE_UDP:
2783 udp = (struct rte_udp_hdr *)&buf[temp_size];
2785 return rte_flow_error_set(error, EINVAL,
2786 RTE_FLOW_ERROR_TYPE_ACTION,
2787 (void *)items->type,
2788 "ip header not found");
2789 if (ipv4 && !ipv4->next_proto_id)
2790 ipv4->next_proto_id = IPPROTO_UDP;
2791 else if (ipv6 && !ipv6->proto)
2792 ipv6->proto = IPPROTO_UDP;
2794 case RTE_FLOW_ITEM_TYPE_VXLAN:
2795 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2797 return rte_flow_error_set(error, EINVAL,
2798 RTE_FLOW_ERROR_TYPE_ACTION,
2799 (void *)items->type,
2800 "udp header not found");
2802 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2803 if (!vxlan->vx_flags)
2805 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2807 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2808 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2810 return rte_flow_error_set(error, EINVAL,
2811 RTE_FLOW_ERROR_TYPE_ACTION,
2812 (void *)items->type,
2813 "udp header not found");
2814 if (!vxlan_gpe->proto)
2815 return rte_flow_error_set(error, EINVAL,
2816 RTE_FLOW_ERROR_TYPE_ACTION,
2817 (void *)items->type,
2818 "next protocol not found");
2821 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2822 if (!vxlan_gpe->vx_flags)
2823 vxlan_gpe->vx_flags =
2824 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2826 case RTE_FLOW_ITEM_TYPE_GRE:
2827 case RTE_FLOW_ITEM_TYPE_NVGRE:
2828 gre = (struct rte_gre_hdr *)&buf[temp_size];
2830 return rte_flow_error_set(error, EINVAL,
2831 RTE_FLOW_ERROR_TYPE_ACTION,
2832 (void *)items->type,
2833 "next protocol not found");
2835 return rte_flow_error_set(error, EINVAL,
2836 RTE_FLOW_ERROR_TYPE_ACTION,
2837 (void *)items->type,
2838 "ip header not found");
2839 if (ipv4 && !ipv4->next_proto_id)
2840 ipv4->next_proto_id = IPPROTO_GRE;
2841 else if (ipv6 && !ipv6->proto)
2842 ipv6->proto = IPPROTO_GRE;
2844 case RTE_FLOW_ITEM_TYPE_VOID:
2847 return rte_flow_error_set(error, EINVAL,
2848 RTE_FLOW_ERROR_TYPE_ACTION,
2849 (void *)items->type,
2850 "unsupported item type");
2860 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2862 struct rte_ether_hdr *eth = NULL;
2863 struct rte_vlan_hdr *vlan = NULL;
2864 struct rte_ipv6_hdr *ipv6 = NULL;
2865 struct rte_udp_hdr *udp = NULL;
2869 eth = (struct rte_ether_hdr *)data;
2870 next_hdr = (char *)(eth + 1);
2871 proto = RTE_BE16(eth->ether_type);
2874 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2875 vlan = (struct rte_vlan_hdr *)next_hdr;
2876 proto = RTE_BE16(vlan->eth_proto);
2877 next_hdr += sizeof(struct rte_vlan_hdr);
2880 /* HW calculates IPv4 csum. no need to proceed */
2881 if (proto == RTE_ETHER_TYPE_IPV4)
2884 /* non IPv4/IPv6 header. not supported */
2885 if (proto != RTE_ETHER_TYPE_IPV6) {
2886 return rte_flow_error_set(error, ENOTSUP,
2887 RTE_FLOW_ERROR_TYPE_ACTION,
2888 NULL, "Cannot offload non IPv4/IPv6");
2891 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2893 /* ignore non UDP */
2894 if (ipv6->proto != IPPROTO_UDP)
2897 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2898 udp->dgram_cksum = 0;
2904 * Convert L2 encap action to DV specification.
2907 * Pointer to rte_eth_dev structure.
2909 * Pointer to action structure.
2910 * @param[in, out] dev_flow
2911 * Pointer to the mlx5_flow.
2912 * @param[in] transfer
2913 * Mark if the flow is E-Switch flow.
2915 * Pointer to the error structure.
2918 * 0 on success, a negative errno value otherwise and rte_errno is set.
2921 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2922 const struct rte_flow_action *action,
2923 struct mlx5_flow *dev_flow,
2925 struct rte_flow_error *error)
2927 const struct rte_flow_item *encap_data;
2928 const struct rte_flow_action_raw_encap *raw_encap_data;
2929 struct mlx5_flow_dv_encap_decap_resource res = {
2931 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2932 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2933 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2936 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2938 (const struct rte_flow_action_raw_encap *)action->conf;
2939 res.size = raw_encap_data->size;
2940 memcpy(res.buf, raw_encap_data->data, res.size);
2942 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2944 ((const struct rte_flow_action_vxlan_encap *)
2945 action->conf)->definition;
2948 ((const struct rte_flow_action_nvgre_encap *)
2949 action->conf)->definition;
2950 if (flow_dv_convert_encap_data(encap_data, res.buf,
2954 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2956 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2957 return rte_flow_error_set(error, EINVAL,
2958 RTE_FLOW_ERROR_TYPE_ACTION,
2959 NULL, "can't create L2 encap action");
2964 * Convert L2 decap action to DV specification.
2967 * Pointer to rte_eth_dev structure.
2968 * @param[in, out] dev_flow
2969 * Pointer to the mlx5_flow.
2970 * @param[in] transfer
2971 * Mark if the flow is E-Switch flow.
2973 * Pointer to the error structure.
2976 * 0 on success, a negative errno value otherwise and rte_errno is set.
2979 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2980 struct mlx5_flow *dev_flow,
2982 struct rte_flow_error *error)
2984 struct mlx5_flow_dv_encap_decap_resource res = {
2987 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2988 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2989 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2992 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2993 return rte_flow_error_set(error, EINVAL,
2994 RTE_FLOW_ERROR_TYPE_ACTION,
2995 NULL, "can't create L2 decap action");
3000 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3003 * Pointer to rte_eth_dev structure.
3005 * Pointer to action structure.
3006 * @param[in, out] dev_flow
3007 * Pointer to the mlx5_flow.
3009 * Pointer to the flow attributes.
3011 * Pointer to the error structure.
3014 * 0 on success, a negative errno value otherwise and rte_errno is set.
3017 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3018 const struct rte_flow_action *action,
3019 struct mlx5_flow *dev_flow,
3020 const struct rte_flow_attr *attr,
3021 struct rte_flow_error *error)
3023 const struct rte_flow_action_raw_encap *encap_data;
3024 struct mlx5_flow_dv_encap_decap_resource res;
3026 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3027 res.size = encap_data->size;
3028 memcpy(res.buf, encap_data->data, res.size);
3029 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3030 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3031 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3033 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3035 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3036 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3037 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3038 return rte_flow_error_set(error, EINVAL,
3039 RTE_FLOW_ERROR_TYPE_ACTION,
3040 NULL, "can't create encap action");
3045 * Create action push VLAN.
3048 * Pointer to rte_eth_dev structure.
3050 * Pointer to the flow attributes.
3052 * Pointer to the vlan to push to the Ethernet header.
3053 * @param[in, out] dev_flow
3054 * Pointer to the mlx5_flow.
3056 * Pointer to the error structure.
3059 * 0 on success, a negative errno value otherwise and rte_errno is set.
3062 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3063 const struct rte_flow_attr *attr,
3064 const struct rte_vlan_hdr *vlan,
3065 struct mlx5_flow *dev_flow,
3066 struct rte_flow_error *error)
3068 struct mlx5_flow_dv_push_vlan_action_resource res;
3071 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3074 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3076 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3077 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3078 return flow_dv_push_vlan_action_resource_register
3079 (dev, &res, dev_flow, error);
3083 * Validate the modify-header actions.
3085 * @param[in] action_flags
3086 * Holds the actions detected until now.
3088 * Pointer to the modify action.
3090 * Pointer to error structure.
3093 * 0 on success, a negative errno value otherwise and rte_errno is set.
3096 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3097 const struct rte_flow_action *action,
3098 struct rte_flow_error *error)
3100 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3101 return rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3103 NULL, "action configuration not set");
3104 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3105 return rte_flow_error_set(error, EINVAL,
3106 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3107 "can't have encap action before"
3113 * Validate the modify-header MAC address actions.
3115 * @param[in] action_flags
3116 * Holds the actions detected until now.
3118 * Pointer to the modify action.
3119 * @param[in] item_flags
3120 * Holds the items detected.
3122 * Pointer to error structure.
3125 * 0 on success, a negative errno value otherwise and rte_errno is set.
3128 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3129 const struct rte_flow_action *action,
3130 const uint64_t item_flags,
3131 struct rte_flow_error *error)
3135 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3137 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3138 return rte_flow_error_set(error, EINVAL,
3139 RTE_FLOW_ERROR_TYPE_ACTION,
3141 "no L2 item in pattern");
3147 * Validate the modify-header IPv4 address actions.
3149 * @param[in] action_flags
3150 * Holds the actions detected until now.
3152 * Pointer to the modify action.
3153 * @param[in] item_flags
3154 * Holds the items detected.
3156 * Pointer to error structure.
3159 * 0 on success, a negative errno value otherwise and rte_errno is set.
3162 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3163 const struct rte_flow_action *action,
3164 const uint64_t item_flags,
3165 struct rte_flow_error *error)
3170 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3172 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3173 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3174 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3175 if (!(item_flags & layer))
3176 return rte_flow_error_set(error, EINVAL,
3177 RTE_FLOW_ERROR_TYPE_ACTION,
3179 "no ipv4 item in pattern");
3185 * Validate the modify-header IPv6 address actions.
3187 * @param[in] action_flags
3188 * Holds the actions detected until now.
3190 * Pointer to the modify action.
3191 * @param[in] item_flags
3192 * Holds the items detected.
3194 * Pointer to error structure.
3197 * 0 on success, a negative errno value otherwise and rte_errno is set.
3200 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3201 const struct rte_flow_action *action,
3202 const uint64_t item_flags,
3203 struct rte_flow_error *error)
3208 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3210 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3211 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3212 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3213 if (!(item_flags & layer))
3214 return rte_flow_error_set(error, EINVAL,
3215 RTE_FLOW_ERROR_TYPE_ACTION,
3217 "no ipv6 item in pattern");
3223 * Validate the modify-header TP actions.
3225 * @param[in] action_flags
3226 * Holds the actions detected until now.
3228 * Pointer to the modify action.
3229 * @param[in] item_flags
3230 * Holds the items detected.
3232 * Pointer to error structure.
3235 * 0 on success, a negative errno value otherwise and rte_errno is set.
3238 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3239 const struct rte_flow_action *action,
3240 const uint64_t item_flags,
3241 struct rte_flow_error *error)
3246 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3248 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3249 MLX5_FLOW_LAYER_INNER_L4 :
3250 MLX5_FLOW_LAYER_OUTER_L4;
3251 if (!(item_flags & layer))
3252 return rte_flow_error_set(error, EINVAL,
3253 RTE_FLOW_ERROR_TYPE_ACTION,
3254 NULL, "no transport layer "
3261 * Validate the modify-header actions of increment/decrement
3262 * TCP Sequence-number.
3264 * @param[in] action_flags
3265 * Holds the actions detected until now.
3267 * Pointer to the modify action.
3268 * @param[in] item_flags
3269 * Holds the items detected.
3271 * Pointer to error structure.
3274 * 0 on success, a negative errno value otherwise and rte_errno is set.
3277 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3278 const struct rte_flow_action *action,
3279 const uint64_t item_flags,
3280 struct rte_flow_error *error)
3285 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3287 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3288 MLX5_FLOW_LAYER_INNER_L4_TCP :
3289 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3290 if (!(item_flags & layer))
3291 return rte_flow_error_set(error, EINVAL,
3292 RTE_FLOW_ERROR_TYPE_ACTION,
3293 NULL, "no TCP item in"
3295 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3296 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3297 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3298 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3299 return rte_flow_error_set(error, EINVAL,
3300 RTE_FLOW_ERROR_TYPE_ACTION,
3302 "cannot decrease and increase"
3303 " TCP sequence number"
3304 " at the same time");
3310 * Validate the modify-header actions of increment/decrement
3311 * TCP Acknowledgment number.
3313 * @param[in] action_flags
3314 * Holds the actions detected until now.
3316 * Pointer to the modify action.
3317 * @param[in] item_flags
3318 * Holds the items detected.
3320 * Pointer to error structure.
3323 * 0 on success, a negative errno value otherwise and rte_errno is set.
3326 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3327 const struct rte_flow_action *action,
3328 const uint64_t item_flags,
3329 struct rte_flow_error *error)
3334 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3336 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3337 MLX5_FLOW_LAYER_INNER_L4_TCP :
3338 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3339 if (!(item_flags & layer))
3340 return rte_flow_error_set(error, EINVAL,
3341 RTE_FLOW_ERROR_TYPE_ACTION,
3342 NULL, "no TCP item in"
3344 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3345 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3346 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3347 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3348 return rte_flow_error_set(error, EINVAL,
3349 RTE_FLOW_ERROR_TYPE_ACTION,
3351 "cannot decrease and increase"
3352 " TCP acknowledgment number"
3353 " at the same time");
3359 * Validate the modify-header TTL actions.
3361 * @param[in] action_flags
3362 * Holds the actions detected until now.
3364 * Pointer to the modify action.
3365 * @param[in] item_flags
3366 * Holds the items detected.
3368 * Pointer to error structure.
3371 * 0 on success, a negative errno value otherwise and rte_errno is set.
3374 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3375 const struct rte_flow_action *action,
3376 const uint64_t item_flags,
3377 struct rte_flow_error *error)
3382 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3384 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3385 MLX5_FLOW_LAYER_INNER_L3 :
3386 MLX5_FLOW_LAYER_OUTER_L3;
3387 if (!(item_flags & layer))
3388 return rte_flow_error_set(error, EINVAL,
3389 RTE_FLOW_ERROR_TYPE_ACTION,
3391 "no IP protocol in pattern");
3397 * Validate jump action.
3400 * Pointer to the jump action.
3401 * @param[in] action_flags
3402 * Holds the actions detected until now.
3403 * @param[in] attributes
3404 * Pointer to flow attributes
3405 * @param[in] external
3406 * Action belongs to flow rule created by request external to PMD.
3408 * Pointer to error structure.
3411 * 0 on success, a negative errno value otherwise and rte_errno is set.
3414 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3415 uint64_t action_flags,
3416 const struct rte_flow_attr *attributes,
3417 bool external, struct rte_flow_error *error)
3419 uint32_t target_group, table;
3422 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3423 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3424 return rte_flow_error_set(error, EINVAL,
3425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3426 "can't have 2 fate actions in"
3428 if (action_flags & MLX5_FLOW_ACTION_METER)
3429 return rte_flow_error_set(error, ENOTSUP,
3430 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3431 "jump with meter not support");
3433 return rte_flow_error_set(error, EINVAL,
3434 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3435 NULL, "action configuration not set");
3437 ((const struct rte_flow_action_jump *)action->conf)->group;
3438 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3439 true, &table, error);
3442 if (attributes->group == target_group)
3443 return rte_flow_error_set(error, EINVAL,
3444 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3445 "target group must be other than"
3446 " the current flow group");
3451 * Validate the port_id action.
3454 * Pointer to rte_eth_dev structure.
3455 * @param[in] action_flags
3456 * Bit-fields that holds the actions detected until now.
3458 * Port_id RTE action structure.
3460 * Attributes of flow that includes this action.
3462 * Pointer to error structure.
3465 * 0 on success, a negative errno value otherwise and rte_errno is set.
3468 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3469 uint64_t action_flags,
3470 const struct rte_flow_action *action,
3471 const struct rte_flow_attr *attr,
3472 struct rte_flow_error *error)
3474 const struct rte_flow_action_port_id *port_id;
3475 struct mlx5_priv *act_priv;
3476 struct mlx5_priv *dev_priv;
3479 if (!attr->transfer)
3480 return rte_flow_error_set(error, ENOTSUP,
3481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3483 "port id action is valid in transfer"
3485 if (!action || !action->conf)
3486 return rte_flow_error_set(error, ENOTSUP,
3487 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3489 "port id action parameters must be"
3491 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3492 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3493 return rte_flow_error_set(error, EINVAL,
3494 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3495 "can have only one fate actions in"
3497 dev_priv = mlx5_dev_to_eswitch_info(dev);
3499 return rte_flow_error_set(error, rte_errno,
3500 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3502 "failed to obtain E-Switch info");
3503 port_id = action->conf;
3504 port = port_id->original ? dev->data->port_id : port_id->id;
3505 act_priv = mlx5_port_to_eswitch_info(port, false);
3507 return rte_flow_error_set
3509 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3510 "failed to obtain E-Switch port id for port");
3511 if (act_priv->domain_id != dev_priv->domain_id)
3512 return rte_flow_error_set
3514 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3515 "port does not belong to"
3516 " E-Switch being configured");
3521 * Get the maximum number of modify header actions.
3524 * Pointer to rte_eth_dev structure.
3526 * Flags bits to check if root level.
3529 * Max number of modify header actions device can support.
3532 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3535 * There's no way to directly query the max cap. Although it has to be
3536 * acquried by iterative trial, it is a safe assumption that more
3537 * actions are supported by FW if extensive metadata register is
3538 * supported. (Only in the root table)
3540 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3541 return MLX5_MAX_MODIFY_NUM;
3543 return mlx5_flow_ext_mreg_supported(dev) ?
3544 MLX5_ROOT_TBL_MODIFY_NUM :
3545 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3549 * Validate the meter action.
3552 * Pointer to rte_eth_dev structure.
3553 * @param[in] action_flags
3554 * Bit-fields that holds the actions detected until now.
3556 * Pointer to the meter action.
3558 * Attributes of flow that includes this action.
3560 * Pointer to error structure.
3563 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3566 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3567 uint64_t action_flags,
3568 const struct rte_flow_action *action,
3569 const struct rte_flow_attr *attr,
3570 struct rte_flow_error *error)
3572 struct mlx5_priv *priv = dev->data->dev_private;
3573 const struct rte_flow_action_meter *am = action->conf;
3574 struct mlx5_flow_meter *fm;
3577 return rte_flow_error_set(error, EINVAL,
3578 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3579 "meter action conf is NULL");
3581 if (action_flags & MLX5_FLOW_ACTION_METER)
3582 return rte_flow_error_set(error, ENOTSUP,
3583 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3584 "meter chaining not support");
3585 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3586 return rte_flow_error_set(error, ENOTSUP,
3587 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3588 "meter with jump not support");
3590 return rte_flow_error_set(error, ENOTSUP,
3591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3593 "meter action not supported");
3594 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3596 return rte_flow_error_set(error, EINVAL,
3597 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3599 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3600 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3601 (!fm->attr.egress && !attr->egress && attr->ingress))))
3602 return rte_flow_error_set(error, EINVAL,
3603 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3604 "Flow attributes are either invalid "
3605 "or have a conflict with current "
3606 "meter attributes");
3611 * Validate the modify-header IPv4 DSCP actions.
3613 * @param[in] action_flags
3614 * Holds the actions detected until now.
3616 * Pointer to the modify action.
3617 * @param[in] item_flags
3618 * Holds the items detected.
3620 * Pointer to error structure.
3623 * 0 on success, a negative errno value otherwise and rte_errno is set.
3626 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3627 const struct rte_flow_action *action,
3628 const uint64_t item_flags,
3629 struct rte_flow_error *error)
3633 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3635 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3636 return rte_flow_error_set(error, EINVAL,
3637 RTE_FLOW_ERROR_TYPE_ACTION,
3639 "no ipv4 item in pattern");
3645 * Validate the modify-header IPv6 DSCP actions.
3647 * @param[in] action_flags
3648 * Holds the actions detected until now.
3650 * Pointer to the modify action.
3651 * @param[in] item_flags
3652 * Holds the items detected.
3654 * Pointer to error structure.
3657 * 0 on success, a negative errno value otherwise and rte_errno is set.
3660 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3661 const struct rte_flow_action *action,
3662 const uint64_t item_flags,
3663 struct rte_flow_error *error)
3667 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3669 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3670 return rte_flow_error_set(error, EINVAL,
3671 RTE_FLOW_ERROR_TYPE_ACTION,
3673 "no ipv6 item in pattern");
3679 * Find existing modify-header resource or create and register a new one.
3681 * @param dev[in, out]
3682 * Pointer to rte_eth_dev structure.
3683 * @param[in, out] resource
3684 * Pointer to modify-header resource.
3685 * @parm[in, out] dev_flow
3686 * Pointer to the dev_flow.
3688 * pointer to error structure.
3691 * 0 on success otherwise -errno and errno is set.
3694 flow_dv_modify_hdr_resource_register
3695 (struct rte_eth_dev *dev,
3696 struct mlx5_flow_dv_modify_hdr_resource *resource,
3697 struct mlx5_flow *dev_flow,
3698 struct rte_flow_error *error)
3700 struct mlx5_priv *priv = dev->data->dev_private;
3701 struct mlx5_ibv_shared *sh = priv->sh;
3702 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3703 struct mlx5dv_dr_domain *ns;
3704 uint32_t actions_len;
3707 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3708 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3710 return rte_flow_error_set(error, EOVERFLOW,
3711 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3712 "too many modify header items");
3713 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3714 ns = sh->fdb_domain;
3715 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3719 /* Lookup a matching resource from cache. */
3720 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3721 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3722 if (resource->ft_type == cache_resource->ft_type &&
3723 resource->actions_num == cache_resource->actions_num &&
3724 resource->flags == cache_resource->flags &&
3725 !memcmp((const void *)resource->actions,
3726 (const void *)cache_resource->actions,
3728 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3729 (void *)cache_resource,
3730 rte_atomic32_read(&cache_resource->refcnt));
3731 rte_atomic32_inc(&cache_resource->refcnt);
3732 dev_flow->dv.modify_hdr = cache_resource;
3736 /* Register new modify-header resource. */
3737 cache_resource = rte_calloc(__func__, 1,
3738 sizeof(*cache_resource) + actions_len, 0);
3739 if (!cache_resource)
3740 return rte_flow_error_set(error, ENOMEM,
3741 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3742 "cannot allocate resource memory");
3743 *cache_resource = *resource;
3744 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3745 cache_resource->verbs_action =
3746 mlx5_glue->dv_create_flow_action_modify_header
3747 (sh->ctx, cache_resource->ft_type, ns,
3748 cache_resource->flags, actions_len,
3749 (uint64_t *)cache_resource->actions);
3750 if (!cache_resource->verbs_action) {
3751 rte_free(cache_resource);
3752 return rte_flow_error_set(error, ENOMEM,
3753 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3754 NULL, "cannot create action");
3756 rte_atomic32_init(&cache_resource->refcnt);
3757 rte_atomic32_inc(&cache_resource->refcnt);
3758 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3759 dev_flow->dv.modify_hdr = cache_resource;
3760 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3761 (void *)cache_resource,
3762 rte_atomic32_read(&cache_resource->refcnt));
3766 #define MLX5_CNT_CONTAINER_RESIZE 64
3769 * Get or create a flow counter.
3772 * Pointer to the Ethernet device structure.
3774 * Indicate if this counter is shared with other flows.
3776 * Counter identifier.
3779 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3781 static struct mlx5_flow_counter *
3782 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3785 struct mlx5_priv *priv = dev->data->dev_private;
3786 struct mlx5_flow_counter *cnt = NULL;
3787 struct mlx5_devx_obj *dcs = NULL;
3789 if (!priv->config.devx) {
3790 rte_errno = ENOTSUP;
3794 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3795 if (cnt->shared && cnt->id == id) {
3801 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3804 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3806 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3810 struct mlx5_flow_counter tmpl = {
3816 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3818 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3824 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3829 * Release a flow counter.
3832 * Pointer to the Ethernet device structure.
3833 * @param[in] counter
3834 * Pointer to the counter handler.
3837 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3838 struct mlx5_flow_counter *counter)
3840 struct mlx5_priv *priv = dev->data->dev_private;
3844 if (--counter->ref_cnt == 0) {
3845 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3846 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3852 * Query a devx flow counter.
3855 * Pointer to the Ethernet device structure.
3857 * Pointer to the flow counter.
3859 * The statistics value of packets.
3861 * The statistics value of bytes.
3864 * 0 on success, otherwise a negative errno value and rte_errno is set.
3867 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3868 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3871 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3876 * Get a pool by a counter.
3879 * Pointer to the counter.
3884 static struct mlx5_flow_counter_pool *
3885 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3888 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3889 return (struct mlx5_flow_counter_pool *)cnt - 1;
3895 * Get a pool by devx counter ID.
3898 * Pointer to the counter container.
3900 * The counter devx ID.
3903 * The counter pool pointer if exists, NULL otherwise,
3905 static struct mlx5_flow_counter_pool *
3906 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3908 struct mlx5_flow_counter_pool *pool;
3910 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3911 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3912 MLX5_COUNTERS_PER_POOL;
3914 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3921 * Allocate a new memory for the counter values wrapped by all the needed
3925 * Pointer to the Ethernet device structure.
3927 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3930 * The new memory management pointer on success, otherwise NULL and rte_errno
3933 static struct mlx5_counter_stats_mem_mng *
3934 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3936 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3937 (dev->data->dev_private))->sh;
3938 struct mlx5_devx_mkey_attr mkey_attr;
3939 struct mlx5_counter_stats_mem_mng *mem_mng;
3940 volatile struct flow_counter_stats *raw_data;
3941 int size = (sizeof(struct flow_counter_stats) *
3942 MLX5_COUNTERS_PER_POOL +
3943 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3944 sizeof(struct mlx5_counter_stats_mem_mng);
3945 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3952 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3953 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3954 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3955 IBV_ACCESS_LOCAL_WRITE);
3956 if (!mem_mng->umem) {
3961 mkey_attr.addr = (uintptr_t)mem;
3962 mkey_attr.size = size;
3963 mkey_attr.umem_id = mem_mng->umem->umem_id;
3964 mkey_attr.pd = sh->pdn;
3965 mkey_attr.log_entity_size = 0;
3966 mkey_attr.pg_access = 0;
3967 mkey_attr.klm_array = NULL;
3968 mkey_attr.klm_num = 0;
3969 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3971 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3976 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3977 raw_data = (volatile struct flow_counter_stats *)mem;
3978 for (i = 0; i < raws_n; ++i) {
3979 mem_mng->raws[i].mem_mng = mem_mng;
3980 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3982 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3987 * Resize a counter container.
3990 * Pointer to the Ethernet device structure.
3992 * Whether the pool is for counter that was allocated by batch command.
3995 * The new container pointer on success, otherwise NULL and rte_errno is set.
3997 static struct mlx5_pools_container *
3998 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4000 struct mlx5_priv *priv = dev->data->dev_private;
4001 struct mlx5_pools_container *cont =
4002 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4003 struct mlx5_pools_container *new_cont =
4004 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4005 struct mlx5_counter_stats_mem_mng *mem_mng;
4006 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4007 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4010 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4011 /* The last resize still hasn't detected by the host thread. */
4015 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4016 if (!new_cont->pools) {
4021 memcpy(new_cont->pools, cont->pools, cont->n *
4022 sizeof(struct mlx5_flow_counter_pool *));
4023 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4024 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4026 rte_free(new_cont->pools);
4029 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4030 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4031 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4033 new_cont->n = resize;
4034 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4035 TAILQ_INIT(&new_cont->pool_list);
4036 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4037 new_cont->init_mem_mng = mem_mng;
4039 /* Flip the master container. */
4040 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4045 * Query a devx flow counter.
4048 * Pointer to the Ethernet device structure.
4050 * Pointer to the flow counter.
4052 * The statistics value of packets.
4054 * The statistics value of bytes.
4057 * 0 on success, otherwise a negative errno value and rte_errno is set.
4060 _flow_dv_query_count(struct rte_eth_dev *dev,
4061 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4064 struct mlx5_priv *priv = dev->data->dev_private;
4065 struct mlx5_flow_counter_pool *pool =
4066 flow_dv_counter_pool_get(cnt);
4067 int offset = cnt - &pool->counters_raw[0];
4069 if (priv->counter_fallback)
4070 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4072 rte_spinlock_lock(&pool->sl);
4074 * The single counters allocation may allocate smaller ID than the
4075 * current allocated in parallel to the host reading.
4076 * In this case the new counter values must be reported as 0.
4078 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4082 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4083 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4085 rte_spinlock_unlock(&pool->sl);
4090 * Create and initialize a new counter pool.
4093 * Pointer to the Ethernet device structure.
4095 * The devX counter handle.
4097 * Whether the pool is for counter that was allocated by batch command.
4100 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4102 static struct mlx5_flow_counter_pool *
4103 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4106 struct mlx5_priv *priv = dev->data->dev_private;
4107 struct mlx5_flow_counter_pool *pool;
4108 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4110 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4113 if (cont->n == n_valid) {
4114 cont = flow_dv_container_resize(dev, batch);
4118 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4119 sizeof(struct mlx5_flow_counter);
4120 pool = rte_calloc(__func__, 1, size, 0);
4125 pool->min_dcs = dcs;
4126 pool->raw = cont->init_mem_mng->raws + n_valid %
4127 MLX5_CNT_CONTAINER_RESIZE;
4128 pool->raw_hw = NULL;
4129 rte_spinlock_init(&pool->sl);
4131 * The generation of the new allocated counters in this pool is 0, 2 in
4132 * the pool generation makes all the counters valid for allocation.
4134 rte_atomic64_set(&pool->query_gen, 0x2);
4135 TAILQ_INIT(&pool->counters);
4136 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4137 cont->pools[n_valid] = pool;
4138 /* Pool initialization must be updated before host thread access. */
4140 rte_atomic16_add(&cont->n_valid, 1);
4145 * Prepare a new counter and/or a new counter pool.
4148 * Pointer to the Ethernet device structure.
4149 * @param[out] cnt_free
4150 * Where to put the pointer of a new counter.
4152 * Whether the pool is for counter that was allocated by batch command.
4155 * The free counter pool pointer and @p cnt_free is set on success,
4156 * NULL otherwise and rte_errno is set.
4158 static struct mlx5_flow_counter_pool *
4159 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4160 struct mlx5_flow_counter **cnt_free,
4163 struct mlx5_priv *priv = dev->data->dev_private;
4164 struct mlx5_flow_counter_pool *pool;
4165 struct mlx5_devx_obj *dcs = NULL;
4166 struct mlx5_flow_counter *cnt;
4170 /* bulk_bitmap must be 0 for single counter allocation. */
4171 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4174 pool = flow_dv_find_pool_by_id
4175 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4177 pool = flow_dv_pool_create(dev, dcs, batch);
4179 mlx5_devx_cmd_destroy(dcs);
4182 } else if (dcs->id < pool->min_dcs->id) {
4183 rte_atomic64_set(&pool->a64_dcs,
4184 (int64_t)(uintptr_t)dcs);
4186 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4187 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4192 /* bulk_bitmap is in 128 counters units. */
4193 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4194 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4196 rte_errno = ENODATA;
4199 pool = flow_dv_pool_create(dev, dcs, batch);
4201 mlx5_devx_cmd_destroy(dcs);
4204 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4205 cnt = &pool->counters_raw[i];
4207 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4209 *cnt_free = &pool->counters_raw[0];
4214 * Search for existed shared counter.
4217 * Pointer to the relevant counter pool container.
4219 * The shared counter ID to search.
4222 * NULL if not existed, otherwise pointer to the shared counter.
4224 static struct mlx5_flow_counter *
4225 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4228 static struct mlx5_flow_counter *cnt;
4229 struct mlx5_flow_counter_pool *pool;
4232 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4233 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4234 cnt = &pool->counters_raw[i];
4235 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4243 * Allocate a flow counter.
4246 * Pointer to the Ethernet device structure.
4248 * Indicate if this counter is shared with other flows.
4250 * Counter identifier.
4252 * Counter flow group.
4255 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4257 static struct mlx5_flow_counter *
4258 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4261 struct mlx5_priv *priv = dev->data->dev_private;
4262 struct mlx5_flow_counter_pool *pool = NULL;
4263 struct mlx5_flow_counter *cnt_free = NULL;
4265 * Currently group 0 flow counter cannot be assigned to a flow if it is
4266 * not the first one in the batch counter allocation, so it is better
4267 * to allocate counters one by one for these flows in a separate
4269 * A counter can be shared between different groups so need to take
4270 * shared counters from the single container.
4272 uint32_t batch = (group && !shared) ? 1 : 0;
4273 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4276 if (priv->counter_fallback)
4277 return flow_dv_counter_alloc_fallback(dev, shared, id);
4278 if (!priv->config.devx) {
4279 rte_errno = ENOTSUP;
4283 cnt_free = flow_dv_counter_shared_search(cont, id);
4285 if (cnt_free->ref_cnt + 1 == 0) {
4289 cnt_free->ref_cnt++;
4293 /* Pools which has a free counters are in the start. */
4294 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4296 * The free counter reset values must be updated between the
4297 * counter release to the counter allocation, so, at least one
4298 * query must be done in this time. ensure it by saving the
4299 * query generation in the release time.
4300 * The free list is sorted according to the generation - so if
4301 * the first one is not updated, all the others are not
4304 cnt_free = TAILQ_FIRST(&pool->counters);
4305 if (cnt_free && cnt_free->query_gen + 1 <
4306 rte_atomic64_read(&pool->query_gen))
4311 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4315 cnt_free->batch = batch;
4316 /* Create a DV counter action only in the first time usage. */
4317 if (!cnt_free->action) {
4319 struct mlx5_devx_obj *dcs;
4322 offset = cnt_free - &pool->counters_raw[0];
4323 dcs = pool->min_dcs;
4326 dcs = cnt_free->dcs;
4328 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4330 if (!cnt_free->action) {
4335 /* Update the counter reset values. */
4336 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4339 cnt_free->shared = shared;
4340 cnt_free->ref_cnt = 1;
4342 if (!priv->sh->cmng.query_thread_on)
4343 /* Start the asynchronous batch query by the host thread. */
4344 mlx5_set_query_alarm(priv->sh);
4345 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4346 if (TAILQ_EMPTY(&pool->counters)) {
4347 /* Move the pool to the end of the container pool list. */
4348 TAILQ_REMOVE(&cont->pool_list, pool, next);
4349 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4355 * Release a flow counter.
4358 * Pointer to the Ethernet device structure.
4359 * @param[in] counter
4360 * Pointer to the counter handler.
4363 flow_dv_counter_release(struct rte_eth_dev *dev,
4364 struct mlx5_flow_counter *counter)
4366 struct mlx5_priv *priv = dev->data->dev_private;
4370 if (priv->counter_fallback) {
4371 flow_dv_counter_release_fallback(dev, counter);
4374 if (--counter->ref_cnt == 0) {
4375 struct mlx5_flow_counter_pool *pool =
4376 flow_dv_counter_pool_get(counter);
4378 /* Put the counter in the end - the last updated one. */
4379 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4380 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4385 * Verify the @p attributes will be correctly understood by the NIC and store
4386 * them in the @p flow if everything is correct.
4389 * Pointer to dev struct.
4390 * @param[in] attributes
4391 * Pointer to flow attributes
4392 * @param[in] external
4393 * This flow rule is created by request external to PMD.
4395 * Pointer to error structure.
4398 * 0 on success, a negative errno value otherwise and rte_errno is set.
4401 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4402 const struct rte_flow_attr *attributes,
4403 bool external __rte_unused,
4404 struct rte_flow_error *error)
4406 struct mlx5_priv *priv = dev->data->dev_private;
4407 uint32_t priority_max = priv->config.flow_prio - 1;
4409 #ifndef HAVE_MLX5DV_DR
4410 if (attributes->group)
4411 return rte_flow_error_set(error, ENOTSUP,
4412 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4414 "groups are not supported");
4419 ret = mlx5_flow_group_to_table(attributes, external,
4420 attributes->group, !!priv->fdb_def_rule,
4425 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4426 attributes->priority >= priority_max)
4427 return rte_flow_error_set(error, ENOTSUP,
4428 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4430 "priority out of range");
4431 if (attributes->transfer) {
4432 if (!priv->config.dv_esw_en)
4433 return rte_flow_error_set
4435 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4436 "E-Switch dr is not supported");
4437 if (!(priv->representor || priv->master))
4438 return rte_flow_error_set
4439 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4440 NULL, "E-Switch configuration can only be"
4441 " done by a master or a representor device");
4442 if (attributes->egress)
4443 return rte_flow_error_set
4445 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4446 "egress is not supported");
4448 if (!(attributes->egress ^ attributes->ingress))
4449 return rte_flow_error_set(error, ENOTSUP,
4450 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4451 "must specify exactly one of "
4452 "ingress or egress");
4457 * Internal validation function. For validating both actions and items.
4460 * Pointer to the rte_eth_dev structure.
4462 * Pointer to the flow attributes.
4464 * Pointer to the list of items.
4465 * @param[in] actions
4466 * Pointer to the list of actions.
4467 * @param[in] external
4468 * This flow rule is created by request external to PMD.
4470 * Pointer to the error structure.
4473 * 0 on success, a negative errno value otherwise and rte_errno is set.
4476 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4477 const struct rte_flow_item items[],
4478 const struct rte_flow_action actions[],
4479 bool external, struct rte_flow_error *error)
4482 uint64_t action_flags = 0;
4483 uint64_t item_flags = 0;
4484 uint64_t last_item = 0;
4485 uint8_t next_protocol = 0xff;
4486 uint16_t ether_type = 0;
4488 uint8_t item_ipv6_proto = 0;
4489 const struct rte_flow_item *gre_item = NULL;
4490 const struct rte_flow_action_raw_decap *decap;
4491 const struct rte_flow_action_raw_encap *encap;
4492 const struct rte_flow_action_rss *rss;
4493 const struct rte_flow_item_tcp nic_tcp_mask = {
4496 .src_port = RTE_BE16(UINT16_MAX),
4497 .dst_port = RTE_BE16(UINT16_MAX),
4500 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4502 .src_addr = RTE_BE32(0xffffffff),
4503 .dst_addr = RTE_BE32(0xffffffff),
4504 .type_of_service = 0xff,
4505 .next_proto_id = 0xff,
4506 .time_to_live = 0xff,
4509 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4512 "\xff\xff\xff\xff\xff\xff\xff\xff"
4513 "\xff\xff\xff\xff\xff\xff\xff\xff",
4515 "\xff\xff\xff\xff\xff\xff\xff\xff"
4516 "\xff\xff\xff\xff\xff\xff\xff\xff",
4517 .vtc_flow = RTE_BE32(0xffffffff),
4522 struct mlx5_priv *priv = dev->data->dev_private;
4523 struct mlx5_dev_config *dev_conf = &priv->config;
4524 uint16_t queue_index = 0xFFFF;
4528 ret = flow_dv_validate_attributes(dev, attr, external, error);
4531 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4532 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4533 int type = items->type;
4536 case RTE_FLOW_ITEM_TYPE_VOID:
4538 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4539 ret = flow_dv_validate_item_port_id
4540 (dev, items, attr, item_flags, error);
4543 last_item = MLX5_FLOW_ITEM_PORT_ID;
4545 case RTE_FLOW_ITEM_TYPE_ETH:
4546 ret = mlx5_flow_validate_item_eth(items, item_flags,
4550 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4551 MLX5_FLOW_LAYER_OUTER_L2;
4552 if (items->mask != NULL && items->spec != NULL) {
4554 ((const struct rte_flow_item_eth *)
4557 ((const struct rte_flow_item_eth *)
4559 ether_type = rte_be_to_cpu_16(ether_type);
4564 case RTE_FLOW_ITEM_TYPE_VLAN:
4565 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4569 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4570 MLX5_FLOW_LAYER_OUTER_VLAN;
4571 if (items->mask != NULL && items->spec != NULL) {
4573 ((const struct rte_flow_item_vlan *)
4574 items->spec)->inner_type;
4576 ((const struct rte_flow_item_vlan *)
4577 items->mask)->inner_type;
4578 ether_type = rte_be_to_cpu_16(ether_type);
4583 case RTE_FLOW_ITEM_TYPE_IPV4:
4584 mlx5_flow_tunnel_ip_check(items, next_protocol,
4585 &item_flags, &tunnel);
4586 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4593 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4594 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4595 if (items->mask != NULL &&
4596 ((const struct rte_flow_item_ipv4 *)
4597 items->mask)->hdr.next_proto_id) {
4599 ((const struct rte_flow_item_ipv4 *)
4600 (items->spec))->hdr.next_proto_id;
4602 ((const struct rte_flow_item_ipv4 *)
4603 (items->mask))->hdr.next_proto_id;
4605 /* Reset for inner layer. */
4606 next_protocol = 0xff;
4609 case RTE_FLOW_ITEM_TYPE_IPV6:
4610 mlx5_flow_tunnel_ip_check(items, next_protocol,
4611 &item_flags, &tunnel);
4612 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4619 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4620 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4621 if (items->mask != NULL &&
4622 ((const struct rte_flow_item_ipv6 *)
4623 items->mask)->hdr.proto) {
4625 ((const struct rte_flow_item_ipv6 *)
4626 items->spec)->hdr.proto;
4628 ((const struct rte_flow_item_ipv6 *)
4629 items->spec)->hdr.proto;
4631 ((const struct rte_flow_item_ipv6 *)
4632 items->mask)->hdr.proto;
4634 /* Reset for inner layer. */
4635 next_protocol = 0xff;
4638 case RTE_FLOW_ITEM_TYPE_TCP:
4639 ret = mlx5_flow_validate_item_tcp
4646 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4647 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4649 case RTE_FLOW_ITEM_TYPE_UDP:
4650 ret = mlx5_flow_validate_item_udp(items, item_flags,
4655 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4656 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4658 case RTE_FLOW_ITEM_TYPE_GRE:
4659 ret = mlx5_flow_validate_item_gre(items, item_flags,
4660 next_protocol, error);
4664 last_item = MLX5_FLOW_LAYER_GRE;
4666 case RTE_FLOW_ITEM_TYPE_NVGRE:
4667 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4672 last_item = MLX5_FLOW_LAYER_NVGRE;
4674 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4675 ret = mlx5_flow_validate_item_gre_key
4676 (items, item_flags, gre_item, error);
4679 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4681 case RTE_FLOW_ITEM_TYPE_VXLAN:
4682 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4686 last_item = MLX5_FLOW_LAYER_VXLAN;
4688 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4689 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4694 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4696 case RTE_FLOW_ITEM_TYPE_GENEVE:
4697 ret = mlx5_flow_validate_item_geneve(items,
4702 last_item = MLX5_FLOW_LAYER_GENEVE;
4704 case RTE_FLOW_ITEM_TYPE_MPLS:
4705 ret = mlx5_flow_validate_item_mpls(dev, items,
4710 last_item = MLX5_FLOW_LAYER_MPLS;
4713 case RTE_FLOW_ITEM_TYPE_MARK:
4714 ret = flow_dv_validate_item_mark(dev, items, attr,
4718 last_item = MLX5_FLOW_ITEM_MARK;
4720 case RTE_FLOW_ITEM_TYPE_META:
4721 ret = flow_dv_validate_item_meta(dev, items, attr,
4725 last_item = MLX5_FLOW_ITEM_METADATA;
4727 case RTE_FLOW_ITEM_TYPE_ICMP:
4728 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4733 last_item = MLX5_FLOW_LAYER_ICMP;
4735 case RTE_FLOW_ITEM_TYPE_ICMP6:
4736 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4741 item_ipv6_proto = IPPROTO_ICMPV6;
4742 last_item = MLX5_FLOW_LAYER_ICMP6;
4744 case RTE_FLOW_ITEM_TYPE_TAG:
4745 ret = flow_dv_validate_item_tag(dev, items,
4749 last_item = MLX5_FLOW_ITEM_TAG;
4751 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4752 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4754 case RTE_FLOW_ITEM_TYPE_GTP:
4755 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4759 last_item = MLX5_FLOW_LAYER_GTP;
4762 return rte_flow_error_set(error, ENOTSUP,
4763 RTE_FLOW_ERROR_TYPE_ITEM,
4764 NULL, "item not supported");
4766 item_flags |= last_item;
4768 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4769 int type = actions->type;
4770 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4771 return rte_flow_error_set(error, ENOTSUP,
4772 RTE_FLOW_ERROR_TYPE_ACTION,
4773 actions, "too many actions");
4775 case RTE_FLOW_ACTION_TYPE_VOID:
4777 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4778 ret = flow_dv_validate_action_port_id(dev,
4785 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4788 case RTE_FLOW_ACTION_TYPE_FLAG:
4789 ret = flow_dv_validate_action_flag(dev, action_flags,
4793 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4794 /* Count all modify-header actions as one. */
4795 if (!(action_flags &
4796 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4798 action_flags |= MLX5_FLOW_ACTION_FLAG |
4799 MLX5_FLOW_ACTION_MARK_EXT;
4801 action_flags |= MLX5_FLOW_ACTION_FLAG;
4805 case RTE_FLOW_ACTION_TYPE_MARK:
4806 ret = flow_dv_validate_action_mark(dev, actions,
4811 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4812 /* Count all modify-header actions as one. */
4813 if (!(action_flags &
4814 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4816 action_flags |= MLX5_FLOW_ACTION_MARK |
4817 MLX5_FLOW_ACTION_MARK_EXT;
4819 action_flags |= MLX5_FLOW_ACTION_MARK;
4823 case RTE_FLOW_ACTION_TYPE_SET_META:
4824 ret = flow_dv_validate_action_set_meta(dev, actions,
4829 /* Count all modify-header actions as one action. */
4830 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4832 action_flags |= MLX5_FLOW_ACTION_SET_META;
4834 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4835 ret = flow_dv_validate_action_set_tag(dev, actions,
4840 /* Count all modify-header actions as one action. */
4841 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4843 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4845 case RTE_FLOW_ACTION_TYPE_DROP:
4846 ret = mlx5_flow_validate_action_drop(action_flags,
4850 action_flags |= MLX5_FLOW_ACTION_DROP;
4853 case RTE_FLOW_ACTION_TYPE_QUEUE:
4854 ret = mlx5_flow_validate_action_queue(actions,
4859 queue_index = ((const struct rte_flow_action_queue *)
4860 (actions->conf))->index;
4861 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4864 case RTE_FLOW_ACTION_TYPE_RSS:
4865 rss = actions->conf;
4866 ret = mlx5_flow_validate_action_rss(actions,
4872 if (rss != NULL && rss->queue_num)
4873 queue_index = rss->queue[0];
4874 action_flags |= MLX5_FLOW_ACTION_RSS;
4877 case RTE_FLOW_ACTION_TYPE_COUNT:
4878 ret = flow_dv_validate_action_count(dev, error);
4881 action_flags |= MLX5_FLOW_ACTION_COUNT;
4884 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4885 if (flow_dv_validate_action_pop_vlan(dev,
4891 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4894 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4895 ret = flow_dv_validate_action_push_vlan(action_flags,
4901 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4904 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4905 ret = flow_dv_validate_action_set_vlan_pcp
4906 (action_flags, actions, error);
4909 /* Count PCP with push_vlan command. */
4910 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4912 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4913 ret = flow_dv_validate_action_set_vlan_vid
4914 (item_flags, action_flags,
4918 /* Count VID with push_vlan command. */
4919 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4921 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4922 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4923 ret = flow_dv_validate_action_l2_encap(action_flags,
4927 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4930 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4931 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4932 ret = flow_dv_validate_action_decap(action_flags, attr,
4936 action_flags |= MLX5_FLOW_ACTION_DECAP;
4939 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4940 ret = flow_dv_validate_action_raw_encap_decap
4941 (NULL, actions->conf, attr, &action_flags,
4946 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4947 decap = actions->conf;
4948 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4950 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4954 encap = actions->conf;
4956 ret = flow_dv_validate_action_raw_encap_decap
4957 (decap ? decap : &empty_decap, encap,
4958 attr, &action_flags, &actions_n,
4963 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4964 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4965 ret = flow_dv_validate_action_modify_mac(action_flags,
4971 /* Count all modify-header actions as one action. */
4972 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4974 action_flags |= actions->type ==
4975 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4976 MLX5_FLOW_ACTION_SET_MAC_SRC :
4977 MLX5_FLOW_ACTION_SET_MAC_DST;
4980 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4981 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4982 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4988 /* Count all modify-header actions as one action. */
4989 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4991 action_flags |= actions->type ==
4992 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4993 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4994 MLX5_FLOW_ACTION_SET_IPV4_DST;
4996 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4997 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4998 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5004 if (item_ipv6_proto == IPPROTO_ICMPV6)
5005 return rte_flow_error_set(error, ENOTSUP,
5006 RTE_FLOW_ERROR_TYPE_ACTION,
5008 "Can't change header "
5009 "with ICMPv6 proto");
5010 /* Count all modify-header actions as one action. */
5011 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5013 action_flags |= actions->type ==
5014 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5015 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5016 MLX5_FLOW_ACTION_SET_IPV6_DST;
5018 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5019 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5020 ret = flow_dv_validate_action_modify_tp(action_flags,
5026 /* Count all modify-header actions as one action. */
5027 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5029 action_flags |= actions->type ==
5030 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5031 MLX5_FLOW_ACTION_SET_TP_SRC :
5032 MLX5_FLOW_ACTION_SET_TP_DST;
5034 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5035 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5036 ret = flow_dv_validate_action_modify_ttl(action_flags,
5042 /* Count all modify-header actions as one action. */
5043 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5045 action_flags |= actions->type ==
5046 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5047 MLX5_FLOW_ACTION_SET_TTL :
5048 MLX5_FLOW_ACTION_DEC_TTL;
5050 case RTE_FLOW_ACTION_TYPE_JUMP:
5051 ret = flow_dv_validate_action_jump(actions,
5058 action_flags |= MLX5_FLOW_ACTION_JUMP;
5060 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5061 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5062 ret = flow_dv_validate_action_modify_tcp_seq
5069 /* Count all modify-header actions as one action. */
5070 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5072 action_flags |= actions->type ==
5073 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5074 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5075 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5077 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5078 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5079 ret = flow_dv_validate_action_modify_tcp_ack
5086 /* Count all modify-header actions as one action. */
5087 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5089 action_flags |= actions->type ==
5090 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5091 MLX5_FLOW_ACTION_INC_TCP_ACK :
5092 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5094 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5095 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5096 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5098 case RTE_FLOW_ACTION_TYPE_METER:
5099 ret = mlx5_flow_validate_action_meter(dev,
5105 action_flags |= MLX5_FLOW_ACTION_METER;
5108 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5109 ret = flow_dv_validate_action_modify_ipv4_dscp
5116 /* Count all modify-header actions as one action. */
5117 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5119 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5121 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5122 ret = flow_dv_validate_action_modify_ipv6_dscp
5129 /* Count all modify-header actions as one action. */
5130 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5132 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5135 return rte_flow_error_set(error, ENOTSUP,
5136 RTE_FLOW_ERROR_TYPE_ACTION,
5138 "action not supported");
5142 * Validate the drop action mutual exclusion with other actions.
5143 * Drop action is mutually-exclusive with any other action, except for
5146 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5147 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5148 return rte_flow_error_set(error, EINVAL,
5149 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5150 "Drop action is mutually-exclusive "
5151 "with any other action, except for "
5153 /* Eswitch has few restrictions on using items and actions */
5154 if (attr->transfer) {
5155 if (!mlx5_flow_ext_mreg_supported(dev) &&
5156 action_flags & MLX5_FLOW_ACTION_FLAG)
5157 return rte_flow_error_set(error, ENOTSUP,
5158 RTE_FLOW_ERROR_TYPE_ACTION,
5160 "unsupported action FLAG");
5161 if (!mlx5_flow_ext_mreg_supported(dev) &&
5162 action_flags & MLX5_FLOW_ACTION_MARK)
5163 return rte_flow_error_set(error, ENOTSUP,
5164 RTE_FLOW_ERROR_TYPE_ACTION,
5166 "unsupported action MARK");
5167 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5168 return rte_flow_error_set(error, ENOTSUP,
5169 RTE_FLOW_ERROR_TYPE_ACTION,
5171 "unsupported action QUEUE");
5172 if (action_flags & MLX5_FLOW_ACTION_RSS)
5173 return rte_flow_error_set(error, ENOTSUP,
5174 RTE_FLOW_ERROR_TYPE_ACTION,
5176 "unsupported action RSS");
5177 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5178 return rte_flow_error_set(error, EINVAL,
5179 RTE_FLOW_ERROR_TYPE_ACTION,
5181 "no fate action is found");
5183 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5184 return rte_flow_error_set(error, EINVAL,
5185 RTE_FLOW_ERROR_TYPE_ACTION,
5187 "no fate action is found");
5189 /* Continue validation for Xcap actions.*/
5190 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5191 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5192 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5193 MLX5_FLOW_XCAP_ACTIONS)
5194 return rte_flow_error_set(error, ENOTSUP,
5195 RTE_FLOW_ERROR_TYPE_ACTION,
5196 NULL, "encap and decap "
5197 "combination aren't supported");
5198 if (!attr->transfer && attr->ingress && (action_flags &
5199 MLX5_FLOW_ACTION_ENCAP))
5200 return rte_flow_error_set(error, ENOTSUP,
5201 RTE_FLOW_ERROR_TYPE_ACTION,
5202 NULL, "encap is not supported"
5203 " for ingress traffic");
5209 * Internal preparation function. Allocates the DV flow size,
5210 * this size is constant.
5213 * Pointer to the flow attributes.
5215 * Pointer to the list of items.
5216 * @param[in] actions
5217 * Pointer to the list of actions.
5219 * Pointer to the error structure.
5222 * Pointer to mlx5_flow object on success,
5223 * otherwise NULL and rte_errno is set.
5225 static struct mlx5_flow *
5226 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5227 const struct rte_flow_item items[] __rte_unused,
5228 const struct rte_flow_action actions[] __rte_unused,
5229 struct rte_flow_error *error)
5231 size_t size = sizeof(struct mlx5_flow);
5232 struct mlx5_flow *dev_flow;
5234 dev_flow = rte_calloc(__func__, 1, size, 0);
5236 rte_flow_error_set(error, ENOMEM,
5237 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5238 "not enough memory to create flow");
5241 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5242 dev_flow->ingress = attr->ingress;
5243 dev_flow->transfer = attr->transfer;
5247 #ifdef RTE_LIBRTE_MLX5_DEBUG
5249 * Sanity check for match mask and value. Similar to check_valid_spec() in
5250 * kernel driver. If unmasked bit is present in value, it returns failure.
5253 * pointer to match mask buffer.
5254 * @param match_value
5255 * pointer to match value buffer.
5258 * 0 if valid, -EINVAL otherwise.
5261 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5263 uint8_t *m = match_mask;
5264 uint8_t *v = match_value;
5267 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5270 "match_value differs from match_criteria"
5271 " %p[%u] != %p[%u]",
5272 match_value, i, match_mask, i);
5281 * Add Ethernet item to matcher and to the value.
5283 * @param[in, out] matcher
5285 * @param[in, out] key
5286 * Flow matcher value.
5288 * Flow pattern to translate.
5290 * Item is inner pattern.
5293 flow_dv_translate_item_eth(void *matcher, void *key,
5294 const struct rte_flow_item *item, int inner)
5296 const struct rte_flow_item_eth *eth_m = item->mask;
5297 const struct rte_flow_item_eth *eth_v = item->spec;
5298 const struct rte_flow_item_eth nic_mask = {
5299 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5300 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5301 .type = RTE_BE16(0xffff),
5313 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5315 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5317 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5319 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5321 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5322 ð_m->dst, sizeof(eth_m->dst));
5323 /* The value must be in the range of the mask. */
5324 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5325 for (i = 0; i < sizeof(eth_m->dst); ++i)
5326 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5327 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5328 ð_m->src, sizeof(eth_m->src));
5329 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5330 /* The value must be in the range of the mask. */
5331 for (i = 0; i < sizeof(eth_m->dst); ++i)
5332 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5334 /* When ethertype is present set mask for tagged VLAN. */
5335 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5336 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5337 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5338 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5339 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5341 /* Return here to avoid setting match on ethertype. */
5346 * HW supports match on one Ethertype, the Ethertype following the last
5347 * VLAN tag of the packet (see PRM).
5348 * Set match on ethertype only if ETH header is not followed by VLAN.
5350 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5351 rte_be_to_cpu_16(eth_m->type));
5352 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5353 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5357 * Add VLAN item to matcher and to the value.
5359 * @param[in, out] dev_flow
5361 * @param[in, out] matcher
5363 * @param[in, out] key
5364 * Flow matcher value.
5366 * Flow pattern to translate.
5368 * Item is inner pattern.
5371 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5372 void *matcher, void *key,
5373 const struct rte_flow_item *item,
5376 const struct rte_flow_item_vlan *vlan_m = item->mask;
5377 const struct rte_flow_item_vlan *vlan_v = item->spec;
5386 vlan_m = &rte_flow_item_vlan_mask;
5388 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5390 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5392 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5394 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5396 * This is workaround, masks are not supported,
5397 * and pre-validated.
5399 dev_flow->dv.vf_vlan.tag =
5400 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5402 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5403 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5404 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5406 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5408 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5409 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5410 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5412 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5413 rte_be_to_cpu_16(vlan_m->inner_type));
5414 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5415 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5419 * Add IPV4 item to matcher and to the value.
5421 * @param[in, out] matcher
5423 * @param[in, out] key
5424 * Flow matcher value.
5426 * Flow pattern to translate.
5427 * @param[in] item_flags
5428 * Bit-fields that holds the items detected until now.
5430 * Item is inner pattern.
5432 * The group to insert the rule.
5435 flow_dv_translate_item_ipv4(void *matcher, void *key,
5436 const struct rte_flow_item *item,
5437 const uint64_t item_flags,
5438 int inner, uint32_t group)
5440 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5441 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5442 const struct rte_flow_item_ipv4 nic_mask = {
5444 .src_addr = RTE_BE32(0xffffffff),
5445 .dst_addr = RTE_BE32(0xffffffff),
5446 .type_of_service = 0xff,
5447 .next_proto_id = 0xff,
5448 .time_to_live = 0xff,
5458 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5460 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5462 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5464 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5467 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5469 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5470 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5475 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5476 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5477 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5478 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5479 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5480 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5481 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5482 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5483 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5484 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5485 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5486 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5487 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5489 ipv4_m->hdr.type_of_service);
5490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5491 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5492 ipv4_m->hdr.type_of_service >> 2);
5493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5495 ipv4_m->hdr.next_proto_id);
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5497 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5498 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5499 ipv4_m->hdr.time_to_live);
5500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5501 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5503 * On outer header (which must contains L2), or inner header with L2,
5504 * set cvlan_tag mask bit to mark this packet as untagged.
5506 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5507 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5511 * Add IPV6 item to matcher and to the value.
5513 * @param[in, out] matcher
5515 * @param[in, out] key
5516 * Flow matcher value.
5518 * Flow pattern to translate.
5519 * @param[in] item_flags
5520 * Bit-fields that holds the items detected until now.
5522 * Item is inner pattern.
5524 * The group to insert the rule.
5527 flow_dv_translate_item_ipv6(void *matcher, void *key,
5528 const struct rte_flow_item *item,
5529 const uint64_t item_flags,
5530 int inner, uint32_t group)
5532 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5533 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5534 const struct rte_flow_item_ipv6 nic_mask = {
5537 "\xff\xff\xff\xff\xff\xff\xff\xff"
5538 "\xff\xff\xff\xff\xff\xff\xff\xff",
5540 "\xff\xff\xff\xff\xff\xff\xff\xff"
5541 "\xff\xff\xff\xff\xff\xff\xff\xff",
5542 .vtc_flow = RTE_BE32(0xffffffff),
5549 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5550 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5559 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5561 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5563 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5565 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5568 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5570 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5571 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5576 size = sizeof(ipv6_m->hdr.dst_addr);
5577 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5578 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5579 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5580 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5581 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5582 for (i = 0; i < size; ++i)
5583 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5584 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5585 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5586 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5587 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5588 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5589 for (i = 0; i < size; ++i)
5590 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5592 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5593 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5594 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5595 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5596 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5597 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5600 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5602 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5605 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5607 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5611 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5613 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5614 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5616 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5617 ipv6_m->hdr.hop_limits);
5618 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5619 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5621 * On outer header (which must contains L2), or inner header with L2,
5622 * set cvlan_tag mask bit to mark this packet as untagged.
5624 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5625 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5629 * Add TCP item to matcher and to the value.
5631 * @param[in, out] matcher
5633 * @param[in, out] key
5634 * Flow matcher value.
5636 * Flow pattern to translate.
5638 * Item is inner pattern.
5641 flow_dv_translate_item_tcp(void *matcher, void *key,
5642 const struct rte_flow_item *item,
5645 const struct rte_flow_item_tcp *tcp_m = item->mask;
5646 const struct rte_flow_item_tcp *tcp_v = item->spec;
5651 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5653 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5655 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5657 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5659 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5660 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5664 tcp_m = &rte_flow_item_tcp_mask;
5665 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5666 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5668 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5670 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5672 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5673 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5674 tcp_m->hdr.tcp_flags);
5675 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5676 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5680 * Add UDP item to matcher and to the value.
5682 * @param[in, out] matcher
5684 * @param[in, out] key
5685 * Flow matcher value.
5687 * Flow pattern to translate.
5689 * Item is inner pattern.
5692 flow_dv_translate_item_udp(void *matcher, void *key,
5693 const struct rte_flow_item *item,
5696 const struct rte_flow_item_udp *udp_m = item->mask;
5697 const struct rte_flow_item_udp *udp_v = item->spec;
5702 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5704 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5706 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5708 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5710 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5711 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5715 udp_m = &rte_flow_item_udp_mask;
5716 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5717 rte_be_to_cpu_16(udp_m->hdr.src_port));
5718 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5719 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5720 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5721 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5722 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5723 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5727 * Add GRE optional Key item to matcher and to the value.
5729 * @param[in, out] matcher
5731 * @param[in, out] key
5732 * Flow matcher value.
5734 * Flow pattern to translate.
5736 * Item is inner pattern.
5739 flow_dv_translate_item_gre_key(void *matcher, void *key,
5740 const struct rte_flow_item *item)
5742 const rte_be32_t *key_m = item->mask;
5743 const rte_be32_t *key_v = item->spec;
5744 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5745 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5746 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5748 /* GRE K bit must be on and should already be validated */
5749 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5750 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5754 key_m = &gre_key_default_mask;
5755 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5756 rte_be_to_cpu_32(*key_m) >> 8);
5757 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5758 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5759 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5760 rte_be_to_cpu_32(*key_m) & 0xFF);
5761 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5762 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5766 * Add GRE item to matcher and to the value.
5768 * @param[in, out] matcher
5770 * @param[in, out] key
5771 * Flow matcher value.
5773 * Flow pattern to translate.
5775 * Item is inner pattern.
5778 flow_dv_translate_item_gre(void *matcher, void *key,
5779 const struct rte_flow_item *item,
5782 const struct rte_flow_item_gre *gre_m = item->mask;
5783 const struct rte_flow_item_gre *gre_v = item->spec;
5786 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5787 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5794 uint16_t s_present:1;
5795 uint16_t k_present:1;
5796 uint16_t rsvd_bit1:1;
5797 uint16_t c_present:1;
5801 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5804 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5806 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5808 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5810 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5812 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5813 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5817 gre_m = &rte_flow_item_gre_mask;
5818 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5819 rte_be_to_cpu_16(gre_m->protocol));
5820 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5821 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5822 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5823 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5824 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5825 gre_crks_rsvd0_ver_m.c_present);
5826 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5827 gre_crks_rsvd0_ver_v.c_present &
5828 gre_crks_rsvd0_ver_m.c_present);
5829 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5830 gre_crks_rsvd0_ver_m.k_present);
5831 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5832 gre_crks_rsvd0_ver_v.k_present &
5833 gre_crks_rsvd0_ver_m.k_present);
5834 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5835 gre_crks_rsvd0_ver_m.s_present);
5836 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5837 gre_crks_rsvd0_ver_v.s_present &
5838 gre_crks_rsvd0_ver_m.s_present);
5842 * Add NVGRE item to matcher and to the value.
5844 * @param[in, out] matcher
5846 * @param[in, out] key
5847 * Flow matcher value.
5849 * Flow pattern to translate.
5851 * Item is inner pattern.
5854 flow_dv_translate_item_nvgre(void *matcher, void *key,
5855 const struct rte_flow_item *item,
5858 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5859 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5860 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5861 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5862 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5863 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5869 /* For NVGRE, GRE header fields must be set with defined values. */
5870 const struct rte_flow_item_gre gre_spec = {
5871 .c_rsvd0_ver = RTE_BE16(0x2000),
5872 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5874 const struct rte_flow_item_gre gre_mask = {
5875 .c_rsvd0_ver = RTE_BE16(0xB000),
5876 .protocol = RTE_BE16(UINT16_MAX),
5878 const struct rte_flow_item gre_item = {
5883 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5887 nvgre_m = &rte_flow_item_nvgre_mask;
5888 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5889 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5890 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5891 memcpy(gre_key_m, tni_flow_id_m, size);
5892 for (i = 0; i < size; ++i)
5893 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5897 * Add VXLAN item to matcher and to the value.
5899 * @param[in, out] matcher
5901 * @param[in, out] key
5902 * Flow matcher value.
5904 * Flow pattern to translate.
5906 * Item is inner pattern.
5909 flow_dv_translate_item_vxlan(void *matcher, void *key,
5910 const struct rte_flow_item *item,
5913 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5914 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5917 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5918 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5926 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5928 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5930 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5932 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5934 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5935 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5936 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5938 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5943 vxlan_m = &rte_flow_item_vxlan_mask;
5944 size = sizeof(vxlan_m->vni);
5945 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5946 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5947 memcpy(vni_m, vxlan_m->vni, size);
5948 for (i = 0; i < size; ++i)
5949 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5953 * Add VXLAN-GPE item to matcher and to the value.
5955 * @param[in, out] matcher
5957 * @param[in, out] key
5958 * Flow matcher value.
5960 * Flow pattern to translate.
5962 * Item is inner pattern.
5966 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5967 const struct rte_flow_item *item, int inner)
5969 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5970 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5974 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5976 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5982 uint8_t flags_m = 0xff;
5983 uint8_t flags_v = 0xc;
5986 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5988 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5990 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5992 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5994 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5995 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5996 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5997 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5998 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6003 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6004 size = sizeof(vxlan_m->vni);
6005 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6006 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6007 memcpy(vni_m, vxlan_m->vni, size);
6008 for (i = 0; i < size; ++i)
6009 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6010 if (vxlan_m->flags) {
6011 flags_m = vxlan_m->flags;
6012 flags_v = vxlan_v->flags;
6014 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6015 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6016 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6018 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6023 * Add Geneve item to matcher and to the value.
6025 * @param[in, out] matcher
6027 * @param[in, out] key
6028 * Flow matcher value.
6030 * Flow pattern to translate.
6032 * Item is inner pattern.
6036 flow_dv_translate_item_geneve(void *matcher, void *key,
6037 const struct rte_flow_item *item, int inner)
6039 const struct rte_flow_item_geneve *geneve_m = item->mask;
6040 const struct rte_flow_item_geneve *geneve_v = item->spec;
6043 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6044 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6053 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6055 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6059 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6061 dport = MLX5_UDP_PORT_GENEVE;
6062 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6063 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6064 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6069 geneve_m = &rte_flow_item_geneve_mask;
6070 size = sizeof(geneve_m->vni);
6071 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6072 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6073 memcpy(vni_m, geneve_m->vni, size);
6074 for (i = 0; i < size; ++i)
6075 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6076 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6077 rte_be_to_cpu_16(geneve_m->protocol));
6078 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6079 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6080 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6081 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6082 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6083 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6084 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6085 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6086 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6087 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6088 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6089 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6090 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6094 * Add MPLS item to matcher and to the value.
6096 * @param[in, out] matcher
6098 * @param[in, out] key
6099 * Flow matcher value.
6101 * Flow pattern to translate.
6102 * @param[in] prev_layer
6103 * The protocol layer indicated in previous item.
6105 * Item is inner pattern.
6108 flow_dv_translate_item_mpls(void *matcher, void *key,
6109 const struct rte_flow_item *item,
6110 uint64_t prev_layer,
6113 const uint32_t *in_mpls_m = item->mask;
6114 const uint32_t *in_mpls_v = item->spec;
6115 uint32_t *out_mpls_m = 0;
6116 uint32_t *out_mpls_v = 0;
6117 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6118 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6119 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6121 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6122 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6123 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6125 switch (prev_layer) {
6126 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6127 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6128 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6129 MLX5_UDP_PORT_MPLS);
6131 case MLX5_FLOW_LAYER_GRE:
6132 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6133 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6134 RTE_ETHER_TYPE_MPLS);
6137 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6145 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6146 switch (prev_layer) {
6147 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6149 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6150 outer_first_mpls_over_udp);
6152 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6153 outer_first_mpls_over_udp);
6155 case MLX5_FLOW_LAYER_GRE:
6157 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6158 outer_first_mpls_over_gre);
6160 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6161 outer_first_mpls_over_gre);
6164 /* Inner MPLS not over GRE is not supported. */
6167 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6171 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6177 if (out_mpls_m && out_mpls_v) {
6178 *out_mpls_m = *in_mpls_m;
6179 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6184 * Add metadata register item to matcher
6186 * @param[in, out] matcher
6188 * @param[in, out] key
6189 * Flow matcher value.
6190 * @param[in] reg_type
6191 * Type of device metadata register
6198 flow_dv_match_meta_reg(void *matcher, void *key,
6199 enum modify_reg reg_type,
6200 uint32_t data, uint32_t mask)
6203 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6205 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6211 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6212 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6215 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6216 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6220 * The metadata register C0 field might be divided into
6221 * source vport index and META item value, we should set
6222 * this field according to specified mask, not as whole one.
6224 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6226 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6227 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6230 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6233 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6234 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6237 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6238 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6241 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6242 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6245 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6246 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6249 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6250 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6253 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6254 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6257 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6258 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6267 * Add MARK item to matcher
6270 * The device to configure through.
6271 * @param[in, out] matcher
6273 * @param[in, out] key
6274 * Flow matcher value.
6276 * Flow pattern to translate.
6279 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6280 void *matcher, void *key,
6281 const struct rte_flow_item *item)
6283 struct mlx5_priv *priv = dev->data->dev_private;
6284 const struct rte_flow_item_mark *mark;
6288 mark = item->mask ? (const void *)item->mask :
6289 &rte_flow_item_mark_mask;
6290 mask = mark->id & priv->sh->dv_mark_mask;
6291 mark = (const void *)item->spec;
6293 value = mark->id & priv->sh->dv_mark_mask & mask;
6295 enum modify_reg reg;
6297 /* Get the metadata register index for the mark. */
6298 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6299 MLX5_ASSERT(reg > 0);
6300 if (reg == REG_C_0) {
6301 struct mlx5_priv *priv = dev->data->dev_private;
6302 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6303 uint32_t shl_c0 = rte_bsf32(msk_c0);
6309 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6314 * Add META item to matcher
6317 * The devich to configure through.
6318 * @param[in, out] matcher
6320 * @param[in, out] key
6321 * Flow matcher value.
6323 * Attributes of flow that includes this item.
6325 * Flow pattern to translate.
6328 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6329 void *matcher, void *key,
6330 const struct rte_flow_attr *attr,
6331 const struct rte_flow_item *item)
6333 const struct rte_flow_item_meta *meta_m;
6334 const struct rte_flow_item_meta *meta_v;
6336 meta_m = (const void *)item->mask;
6338 meta_m = &rte_flow_item_meta_mask;
6339 meta_v = (const void *)item->spec;
6342 uint32_t value = meta_v->data;
6343 uint32_t mask = meta_m->data;
6345 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6349 * In datapath code there is no endianness
6350 * coversions for perfromance reasons, all
6351 * pattern conversions are done in rte_flow.
6353 value = rte_cpu_to_be_32(value);
6354 mask = rte_cpu_to_be_32(mask);
6355 if (reg == REG_C_0) {
6356 struct mlx5_priv *priv = dev->data->dev_private;
6357 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6358 uint32_t shl_c0 = rte_bsf32(msk_c0);
6359 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6360 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6367 MLX5_ASSERT(msk_c0);
6368 MLX5_ASSERT(!(~msk_c0 & mask));
6370 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6375 * Add vport metadata Reg C0 item to matcher
6377 * @param[in, out] matcher
6379 * @param[in, out] key
6380 * Flow matcher value.
6382 * Flow pattern to translate.
6385 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6386 uint32_t value, uint32_t mask)
6388 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6392 * Add tag item to matcher
6395 * The devich to configure through.
6396 * @param[in, out] matcher
6398 * @param[in, out] key
6399 * Flow matcher value.
6401 * Flow pattern to translate.
6404 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6405 void *matcher, void *key,
6406 const struct rte_flow_item *item)
6408 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6409 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6410 uint32_t mask, value;
6413 value = tag_v->data;
6414 mask = tag_m ? tag_m->data : UINT32_MAX;
6415 if (tag_v->id == REG_C_0) {
6416 struct mlx5_priv *priv = dev->data->dev_private;
6417 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6418 uint32_t shl_c0 = rte_bsf32(msk_c0);
6424 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6428 * Add TAG item to matcher
6431 * The devich to configure through.
6432 * @param[in, out] matcher
6434 * @param[in, out] key
6435 * Flow matcher value.
6437 * Flow pattern to translate.
6440 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6441 void *matcher, void *key,
6442 const struct rte_flow_item *item)
6444 const struct rte_flow_item_tag *tag_v = item->spec;
6445 const struct rte_flow_item_tag *tag_m = item->mask;
6446 enum modify_reg reg;
6449 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6450 /* Get the metadata register index for the tag. */
6451 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6452 MLX5_ASSERT(reg > 0);
6453 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6457 * Add source vport match to the specified matcher.
6459 * @param[in, out] matcher
6461 * @param[in, out] key
6462 * Flow matcher value.
6464 * Source vport value to match
6469 flow_dv_translate_item_source_vport(void *matcher, void *key,
6470 int16_t port, uint16_t mask)
6472 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6473 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6475 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6476 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6480 * Translate port-id item to eswitch match on port-id.
6483 * The devich to configure through.
6484 * @param[in, out] matcher
6486 * @param[in, out] key
6487 * Flow matcher value.
6489 * Flow pattern to translate.
6492 * 0 on success, a negative errno value otherwise.
6495 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6496 void *key, const struct rte_flow_item *item)
6498 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6499 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6500 struct mlx5_priv *priv;
6503 mask = pid_m ? pid_m->id : 0xffff;
6504 id = pid_v ? pid_v->id : dev->data->port_id;
6505 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6508 /* Translate to vport field or to metadata, depending on mode. */
6509 if (priv->vport_meta_mask)
6510 flow_dv_translate_item_meta_vport(matcher, key,
6511 priv->vport_meta_tag,
6512 priv->vport_meta_mask);
6514 flow_dv_translate_item_source_vport(matcher, key,
6515 priv->vport_id, mask);
6520 * Add ICMP6 item to matcher and to the value.
6522 * @param[in, out] matcher
6524 * @param[in, out] key
6525 * Flow matcher value.
6527 * Flow pattern to translate.
6529 * Item is inner pattern.
6532 flow_dv_translate_item_icmp6(void *matcher, void *key,
6533 const struct rte_flow_item *item,
6536 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6537 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6540 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6542 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6544 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6546 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6548 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6550 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6552 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6553 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6557 icmp6_m = &rte_flow_item_icmp6_mask;
6559 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6560 * If only the protocol is specified, no need to match the frag.
6562 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6564 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6565 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6566 icmp6_v->type & icmp6_m->type);
6567 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6568 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6569 icmp6_v->code & icmp6_m->code);
6573 * Add ICMP item to matcher and to the value.
6575 * @param[in, out] matcher
6577 * @param[in, out] key
6578 * Flow matcher value.
6580 * Flow pattern to translate.
6582 * Item is inner pattern.
6585 flow_dv_translate_item_icmp(void *matcher, void *key,
6586 const struct rte_flow_item *item,
6589 const struct rte_flow_item_icmp *icmp_m = item->mask;
6590 const struct rte_flow_item_icmp *icmp_v = item->spec;
6593 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6595 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6599 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6601 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6603 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6605 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6606 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6610 icmp_m = &rte_flow_item_icmp_mask;
6612 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6613 * If only the protocol is specified, no need to match the frag.
6615 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6617 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6618 icmp_m->hdr.icmp_type);
6619 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6620 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6621 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6622 icmp_m->hdr.icmp_code);
6623 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6624 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6628 * Add GTP item to matcher and to the value.
6630 * @param[in, out] matcher
6632 * @param[in, out] key
6633 * Flow matcher value.
6635 * Flow pattern to translate.
6637 * Item is inner pattern.
6640 flow_dv_translate_item_gtp(void *matcher, void *key,
6641 const struct rte_flow_item *item, int inner)
6643 const struct rte_flow_item_gtp *gtp_m = item->mask;
6644 const struct rte_flow_item_gtp *gtp_v = item->spec;
6647 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6649 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6650 uint16_t dport = RTE_GTPU_UDP_PORT;
6653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6655 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6657 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6659 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6661 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6662 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6663 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6668 gtp_m = &rte_flow_item_gtp_mask;
6669 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6670 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6671 gtp_v->msg_type & gtp_m->msg_type);
6672 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6673 rte_be_to_cpu_32(gtp_m->teid));
6674 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6675 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6678 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6680 #define HEADER_IS_ZERO(match_criteria, headers) \
6681 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6682 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6685 * Calculate flow matcher enable bitmap.
6687 * @param match_criteria
6688 * Pointer to flow matcher criteria.
6691 * Bitmap of enabled fields.
6694 flow_dv_matcher_enable(uint32_t *match_criteria)
6696 uint8_t match_criteria_enable;
6698 match_criteria_enable =
6699 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6700 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6701 match_criteria_enable |=
6702 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6703 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6704 match_criteria_enable |=
6705 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6706 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6707 match_criteria_enable |=
6708 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6709 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6710 match_criteria_enable |=
6711 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6712 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6713 return match_criteria_enable;
6720 * @param[in, out] dev
6721 * Pointer to rte_eth_dev structure.
6722 * @param[in] table_id
6725 * Direction of the table.
6726 * @param[in] transfer
6727 * E-Switch or NIC flow.
6729 * pointer to error structure.
6732 * Returns tables resource based on the index, NULL in case of failed.
6734 static struct mlx5_flow_tbl_resource *
6735 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6736 uint32_t table_id, uint8_t egress,
6738 struct rte_flow_error *error)
6740 struct mlx5_priv *priv = dev->data->dev_private;
6741 struct mlx5_ibv_shared *sh = priv->sh;
6742 struct mlx5_flow_tbl_resource *tbl;
6743 union mlx5_flow_tbl_key table_key = {
6745 .table_id = table_id,
6747 .domain = !!transfer,
6748 .direction = !!egress,
6751 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6753 struct mlx5_flow_tbl_data_entry *tbl_data;
6758 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6760 tbl = &tbl_data->tbl;
6761 rte_atomic32_inc(&tbl->refcnt);
6764 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6766 rte_flow_error_set(error, ENOMEM,
6767 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6769 "cannot allocate flow table data entry");
6772 tbl = &tbl_data->tbl;
6773 pos = &tbl_data->entry;
6775 domain = sh->fdb_domain;
6777 domain = sh->tx_domain;
6779 domain = sh->rx_domain;
6780 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6782 rte_flow_error_set(error, ENOMEM,
6783 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6784 NULL, "cannot create flow table object");
6789 * No multi-threads now, but still better to initialize the reference
6790 * count before insert it into the hash list.
6792 rte_atomic32_init(&tbl->refcnt);
6793 /* Jump action reference count is initialized here. */
6794 rte_atomic32_init(&tbl_data->jump.refcnt);
6795 pos->key = table_key.v64;
6796 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6798 rte_flow_error_set(error, -ret,
6799 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6800 "cannot insert flow table data entry");
6801 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6804 rte_atomic32_inc(&tbl->refcnt);
6809 * Release a flow table.
6812 * Pointer to rte_eth_dev structure.
6814 * Table resource to be released.
6817 * Returns 0 if table was released, else return 1;
6820 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6821 struct mlx5_flow_tbl_resource *tbl)
6823 struct mlx5_priv *priv = dev->data->dev_private;
6824 struct mlx5_ibv_shared *sh = priv->sh;
6825 struct mlx5_flow_tbl_data_entry *tbl_data =
6826 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6830 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6831 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6833 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6835 /* remove the entry from the hash list and free memory. */
6836 mlx5_hlist_remove(sh->flow_tbls, pos);
6844 * Register the flow matcher.
6846 * @param[in, out] dev
6847 * Pointer to rte_eth_dev structure.
6848 * @param[in, out] matcher
6849 * Pointer to flow matcher.
6850 * @param[in, out] key
6851 * Pointer to flow table key.
6852 * @parm[in, out] dev_flow
6853 * Pointer to the dev_flow.
6855 * pointer to error structure.
6858 * 0 on success otherwise -errno and errno is set.
6861 flow_dv_matcher_register(struct rte_eth_dev *dev,
6862 struct mlx5_flow_dv_matcher *matcher,
6863 union mlx5_flow_tbl_key *key,
6864 struct mlx5_flow *dev_flow,
6865 struct rte_flow_error *error)
6867 struct mlx5_priv *priv = dev->data->dev_private;
6868 struct mlx5_ibv_shared *sh = priv->sh;
6869 struct mlx5_flow_dv_matcher *cache_matcher;
6870 struct mlx5dv_flow_matcher_attr dv_attr = {
6871 .type = IBV_FLOW_ATTR_NORMAL,
6872 .match_mask = (void *)&matcher->mask,
6874 struct mlx5_flow_tbl_resource *tbl;
6875 struct mlx5_flow_tbl_data_entry *tbl_data;
6877 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6878 key->domain, error);
6880 return -rte_errno; /* No need to refill the error info */
6881 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6882 /* Lookup from cache. */
6883 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6884 if (matcher->crc == cache_matcher->crc &&
6885 matcher->priority == cache_matcher->priority &&
6886 !memcmp((const void *)matcher->mask.buf,
6887 (const void *)cache_matcher->mask.buf,
6888 cache_matcher->mask.size)) {
6890 "%s group %u priority %hd use %s "
6891 "matcher %p: refcnt %d++",
6892 key->domain ? "FDB" : "NIC", key->table_id,
6893 cache_matcher->priority,
6894 key->direction ? "tx" : "rx",
6895 (void *)cache_matcher,
6896 rte_atomic32_read(&cache_matcher->refcnt));
6897 rte_atomic32_inc(&cache_matcher->refcnt);
6898 dev_flow->dv.matcher = cache_matcher;
6899 /* old matcher should not make the table ref++. */
6900 flow_dv_tbl_resource_release(dev, tbl);
6904 /* Register new matcher. */
6905 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6906 if (!cache_matcher) {
6907 flow_dv_tbl_resource_release(dev, tbl);
6908 return rte_flow_error_set(error, ENOMEM,
6909 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6910 "cannot allocate matcher memory");
6912 *cache_matcher = *matcher;
6913 dv_attr.match_criteria_enable =
6914 flow_dv_matcher_enable(cache_matcher->mask.buf);
6915 dv_attr.priority = matcher->priority;
6917 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6918 cache_matcher->matcher_object =
6919 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6920 if (!cache_matcher->matcher_object) {
6921 rte_free(cache_matcher);
6922 #ifdef HAVE_MLX5DV_DR
6923 flow_dv_tbl_resource_release(dev, tbl);
6925 return rte_flow_error_set(error, ENOMEM,
6926 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6927 NULL, "cannot create matcher");
6929 /* Save the table information */
6930 cache_matcher->tbl = tbl;
6931 rte_atomic32_init(&cache_matcher->refcnt);
6932 /* only matcher ref++, table ref++ already done above in get API. */
6933 rte_atomic32_inc(&cache_matcher->refcnt);
6934 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6935 dev_flow->dv.matcher = cache_matcher;
6936 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6937 key->domain ? "FDB" : "NIC", key->table_id,
6938 cache_matcher->priority,
6939 key->direction ? "tx" : "rx", (void *)cache_matcher,
6940 rte_atomic32_read(&cache_matcher->refcnt));
6945 * Find existing tag resource or create and register a new one.
6947 * @param dev[in, out]
6948 * Pointer to rte_eth_dev structure.
6949 * @param[in, out] tag_be24
6950 * Tag value in big endian then R-shift 8.
6951 * @parm[in, out] dev_flow
6952 * Pointer to the dev_flow.
6954 * pointer to error structure.
6957 * 0 on success otherwise -errno and errno is set.
6960 flow_dv_tag_resource_register
6961 (struct rte_eth_dev *dev,
6963 struct mlx5_flow *dev_flow,
6964 struct rte_flow_error *error)
6966 struct mlx5_priv *priv = dev->data->dev_private;
6967 struct mlx5_ibv_shared *sh = priv->sh;
6968 struct mlx5_flow_dv_tag_resource *cache_resource;
6969 struct mlx5_hlist_entry *entry;
6971 /* Lookup a matching resource from cache. */
6972 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6974 cache_resource = container_of
6975 (entry, struct mlx5_flow_dv_tag_resource, entry);
6976 rte_atomic32_inc(&cache_resource->refcnt);
6977 dev_flow->dv.tag_resource = cache_resource;
6978 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6979 (void *)cache_resource,
6980 rte_atomic32_read(&cache_resource->refcnt));
6983 /* Register new resource. */
6984 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6985 if (!cache_resource)
6986 return rte_flow_error_set(error, ENOMEM,
6987 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6988 "cannot allocate resource memory");
6989 cache_resource->entry.key = (uint64_t)tag_be24;
6990 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6991 if (!cache_resource->action) {
6992 rte_free(cache_resource);
6993 return rte_flow_error_set(error, ENOMEM,
6994 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6995 NULL, "cannot create action");
6997 rte_atomic32_init(&cache_resource->refcnt);
6998 rte_atomic32_inc(&cache_resource->refcnt);
6999 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7000 mlx5_glue->destroy_flow_action(cache_resource->action);
7001 rte_free(cache_resource);
7002 return rte_flow_error_set(error, EEXIST,
7003 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7004 NULL, "cannot insert tag");
7006 dev_flow->dv.tag_resource = cache_resource;
7007 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7008 (void *)cache_resource,
7009 rte_atomic32_read(&cache_resource->refcnt));
7017 * Pointer to Ethernet device.
7019 * Pointer to mlx5_flow.
7022 * 1 while a reference on it exists, 0 when freed.
7025 flow_dv_tag_release(struct rte_eth_dev *dev,
7026 struct mlx5_flow_dv_tag_resource *tag)
7028 struct mlx5_priv *priv = dev->data->dev_private;
7029 struct mlx5_ibv_shared *sh = priv->sh;
7032 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7033 dev->data->port_id, (void *)tag,
7034 rte_atomic32_read(&tag->refcnt));
7035 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7036 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7037 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7038 DRV_LOG(DEBUG, "port %u tag %p: removed",
7039 dev->data->port_id, (void *)tag);
7047 * Translate port ID action to vport.
7050 * Pointer to rte_eth_dev structure.
7052 * Pointer to the port ID action.
7053 * @param[out] dst_port_id
7054 * The target port ID.
7056 * Pointer to the error structure.
7059 * 0 on success, a negative errno value otherwise and rte_errno is set.
7062 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7063 const struct rte_flow_action *action,
7064 uint32_t *dst_port_id,
7065 struct rte_flow_error *error)
7068 struct mlx5_priv *priv;
7069 const struct rte_flow_action_port_id *conf =
7070 (const struct rte_flow_action_port_id *)action->conf;
7072 port = conf->original ? dev->data->port_id : conf->id;
7073 priv = mlx5_port_to_eswitch_info(port, false);
7075 return rte_flow_error_set(error, -rte_errno,
7076 RTE_FLOW_ERROR_TYPE_ACTION,
7078 "No eswitch info was found for port");
7079 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7081 * This parameter is transferred to
7082 * mlx5dv_dr_action_create_dest_ib_port().
7084 *dst_port_id = priv->ibv_port;
7087 * Legacy mode, no LAG configurations is supported.
7088 * This parameter is transferred to
7089 * mlx5dv_dr_action_create_dest_vport().
7091 *dst_port_id = priv->vport_id;
7097 * Add Tx queue matcher
7100 * Pointer to the dev struct.
7101 * @param[in, out] matcher
7103 * @param[in, out] key
7104 * Flow matcher value.
7106 * Flow pattern to translate.
7108 * Item is inner pattern.
7111 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7112 void *matcher, void *key,
7113 const struct rte_flow_item *item)
7115 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7116 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7118 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7120 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7121 struct mlx5_txq_ctrl *txq;
7125 queue_m = (const void *)item->mask;
7128 queue_v = (const void *)item->spec;
7131 txq = mlx5_txq_get(dev, queue_v->queue);
7134 queue = txq->obj->sq->id;
7135 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7136 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7137 queue & queue_m->queue);
7138 mlx5_txq_release(dev, queue_v->queue);
7142 * Set the hash fields according to the @p flow information.
7144 * @param[in] dev_flow
7145 * Pointer to the mlx5_flow.
7148 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7150 struct rte_flow *flow = dev_flow->flow;
7151 uint64_t items = dev_flow->layers;
7153 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7155 dev_flow->hash_fields = 0;
7156 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7157 if (flow->rss.level >= 2) {
7158 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7162 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7163 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7164 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7165 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7166 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7167 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7168 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7170 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7172 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7173 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7174 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7175 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7176 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7177 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7178 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7180 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7183 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7184 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7185 if (rss_types & ETH_RSS_UDP) {
7186 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7187 dev_flow->hash_fields |=
7188 IBV_RX_HASH_SRC_PORT_UDP;
7189 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7190 dev_flow->hash_fields |=
7191 IBV_RX_HASH_DST_PORT_UDP;
7193 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7195 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7196 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7197 if (rss_types & ETH_RSS_TCP) {
7198 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7199 dev_flow->hash_fields |=
7200 IBV_RX_HASH_SRC_PORT_TCP;
7201 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7202 dev_flow->hash_fields |=
7203 IBV_RX_HASH_DST_PORT_TCP;
7205 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7211 * Fill the flow with DV spec, lock free
7212 * (mutex should be acquired by caller).
7215 * Pointer to rte_eth_dev structure.
7216 * @param[in, out] dev_flow
7217 * Pointer to the sub flow.
7219 * Pointer to the flow attributes.
7221 * Pointer to the list of items.
7222 * @param[in] actions
7223 * Pointer to the list of actions.
7225 * Pointer to the error structure.
7228 * 0 on success, a negative errno value otherwise and rte_errno is set.
7231 __flow_dv_translate(struct rte_eth_dev *dev,
7232 struct mlx5_flow *dev_flow,
7233 const struct rte_flow_attr *attr,
7234 const struct rte_flow_item items[],
7235 const struct rte_flow_action actions[],
7236 struct rte_flow_error *error)
7238 struct mlx5_priv *priv = dev->data->dev_private;
7239 struct mlx5_dev_config *dev_conf = &priv->config;
7240 struct rte_flow *flow = dev_flow->flow;
7241 uint64_t item_flags = 0;
7242 uint64_t last_item = 0;
7243 uint64_t action_flags = 0;
7244 uint64_t priority = attr->priority;
7245 struct mlx5_flow_dv_matcher matcher = {
7247 .size = sizeof(matcher.mask.buf),
7251 bool actions_end = false;
7253 struct mlx5_flow_dv_modify_hdr_resource res;
7254 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7255 sizeof(struct mlx5_modification_cmd) *
7256 (MLX5_MAX_MODIFY_NUM + 1)];
7258 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7259 union flow_dv_attr flow_attr = { .attr = 0 };
7261 union mlx5_flow_tbl_key tbl_key;
7262 uint32_t modify_action_position = UINT32_MAX;
7263 void *match_mask = matcher.mask.buf;
7264 void *match_value = dev_flow->dv.value.buf;
7265 uint8_t next_protocol = 0xff;
7266 struct rte_vlan_hdr vlan = { 0 };
7270 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7271 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7272 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7273 !!priv->fdb_def_rule, &table, error);
7276 dev_flow->group = table;
7278 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7279 if (priority == MLX5_FLOW_PRIO_RSVD)
7280 priority = dev_conf->flow_prio - 1;
7281 /* number of actions must be set to 0 in case of dirty stack. */
7282 mhdr_res->actions_num = 0;
7283 for (; !actions_end ; actions++) {
7284 const struct rte_flow_action_queue *queue;
7285 const struct rte_flow_action_rss *rss;
7286 const struct rte_flow_action *action = actions;
7287 const struct rte_flow_action_count *count = action->conf;
7288 const uint8_t *rss_key;
7289 const struct rte_flow_action_jump *jump_data;
7290 const struct rte_flow_action_meter *mtr;
7291 struct mlx5_flow_tbl_resource *tbl;
7292 uint32_t port_id = 0;
7293 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7294 int action_type = actions->type;
7295 const struct rte_flow_action *found_action = NULL;
7297 switch (action_type) {
7298 case RTE_FLOW_ACTION_TYPE_VOID:
7300 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7301 if (flow_dv_translate_action_port_id(dev, action,
7304 port_id_resource.port_id = port_id;
7305 if (flow_dv_port_id_action_resource_register
7306 (dev, &port_id_resource, dev_flow, error))
7308 dev_flow->dv.actions[actions_n++] =
7309 dev_flow->dv.port_id_action->action;
7310 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7312 case RTE_FLOW_ACTION_TYPE_FLAG:
7313 action_flags |= MLX5_FLOW_ACTION_FLAG;
7314 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7315 struct rte_flow_action_mark mark = {
7316 .id = MLX5_FLOW_MARK_DEFAULT,
7319 if (flow_dv_convert_action_mark(dev, &mark,
7323 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7326 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7327 if (!dev_flow->dv.tag_resource)
7328 if (flow_dv_tag_resource_register
7329 (dev, tag_be, dev_flow, error))
7331 dev_flow->dv.actions[actions_n++] =
7332 dev_flow->dv.tag_resource->action;
7334 case RTE_FLOW_ACTION_TYPE_MARK:
7335 action_flags |= MLX5_FLOW_ACTION_MARK;
7336 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7337 const struct rte_flow_action_mark *mark =
7338 (const struct rte_flow_action_mark *)
7341 if (flow_dv_convert_action_mark(dev, mark,
7345 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7349 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7350 /* Legacy (non-extensive) MARK action. */
7351 tag_be = mlx5_flow_mark_set
7352 (((const struct rte_flow_action_mark *)
7353 (actions->conf))->id);
7354 if (!dev_flow->dv.tag_resource)
7355 if (flow_dv_tag_resource_register
7356 (dev, tag_be, dev_flow, error))
7358 dev_flow->dv.actions[actions_n++] =
7359 dev_flow->dv.tag_resource->action;
7361 case RTE_FLOW_ACTION_TYPE_SET_META:
7362 if (flow_dv_convert_action_set_meta
7363 (dev, mhdr_res, attr,
7364 (const struct rte_flow_action_set_meta *)
7365 actions->conf, error))
7367 action_flags |= MLX5_FLOW_ACTION_SET_META;
7369 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7370 if (flow_dv_convert_action_set_tag
7372 (const struct rte_flow_action_set_tag *)
7373 actions->conf, error))
7375 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7377 case RTE_FLOW_ACTION_TYPE_DROP:
7378 action_flags |= MLX5_FLOW_ACTION_DROP;
7380 case RTE_FLOW_ACTION_TYPE_QUEUE:
7381 MLX5_ASSERT(flow->rss.queue);
7382 queue = actions->conf;
7383 flow->rss.queue_num = 1;
7384 (*flow->rss.queue)[0] = queue->index;
7385 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7387 case RTE_FLOW_ACTION_TYPE_RSS:
7388 MLX5_ASSERT(flow->rss.queue);
7389 rss = actions->conf;
7390 if (flow->rss.queue)
7391 memcpy((*flow->rss.queue), rss->queue,
7392 rss->queue_num * sizeof(uint16_t));
7393 flow->rss.queue_num = rss->queue_num;
7394 /* NULL RSS key indicates default RSS key. */
7395 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7396 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7398 * rss->level and rss.types should be set in advance
7399 * when expanding items for RSS.
7401 action_flags |= MLX5_FLOW_ACTION_RSS;
7403 case RTE_FLOW_ACTION_TYPE_COUNT:
7404 if (!dev_conf->devx) {
7405 rte_errno = ENOTSUP;
7408 flow->counter = flow_dv_counter_alloc(dev,
7412 if (flow->counter == NULL)
7414 dev_flow->dv.actions[actions_n++] =
7415 flow->counter->action;
7416 action_flags |= MLX5_FLOW_ACTION_COUNT;
7419 if (rte_errno == ENOTSUP)
7420 return rte_flow_error_set
7422 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7424 "count action not supported");
7426 return rte_flow_error_set
7428 RTE_FLOW_ERROR_TYPE_ACTION,
7430 "cannot create counter"
7433 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7434 dev_flow->dv.actions[actions_n++] =
7435 priv->sh->pop_vlan_action;
7436 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7438 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7439 flow_dev_get_vlan_info_from_items(items, &vlan);
7440 vlan.eth_proto = rte_be_to_cpu_16
7441 ((((const struct rte_flow_action_of_push_vlan *)
7442 actions->conf)->ethertype));
7443 found_action = mlx5_flow_find_action
7445 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7447 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7448 found_action = mlx5_flow_find_action
7450 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7452 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7453 if (flow_dv_create_action_push_vlan
7454 (dev, attr, &vlan, dev_flow, error))
7456 dev_flow->dv.actions[actions_n++] =
7457 dev_flow->dv.push_vlan_res->action;
7458 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7460 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7461 /* of_vlan_push action handled this action */
7462 MLX5_ASSERT(action_flags &
7463 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7465 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7466 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7468 flow_dev_get_vlan_info_from_items(items, &vlan);
7469 mlx5_update_vlan_vid_pcp(actions, &vlan);
7470 /* If no VLAN push - this is a modify header action */
7471 if (flow_dv_convert_action_modify_vlan_vid
7472 (mhdr_res, actions, error))
7474 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7476 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7477 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7478 if (flow_dv_create_action_l2_encap(dev, actions,
7483 dev_flow->dv.actions[actions_n++] =
7484 dev_flow->dv.encap_decap->verbs_action;
7485 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7487 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7488 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7489 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7493 dev_flow->dv.actions[actions_n++] =
7494 dev_flow->dv.encap_decap->verbs_action;
7495 action_flags |= MLX5_FLOW_ACTION_DECAP;
7497 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7498 /* Handle encap with preceding decap. */
7499 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7500 if (flow_dv_create_action_raw_encap
7501 (dev, actions, dev_flow, attr, error))
7503 dev_flow->dv.actions[actions_n++] =
7504 dev_flow->dv.encap_decap->verbs_action;
7506 /* Handle encap without preceding decap. */
7507 if (flow_dv_create_action_l2_encap
7508 (dev, actions, dev_flow, attr->transfer,
7511 dev_flow->dv.actions[actions_n++] =
7512 dev_flow->dv.encap_decap->verbs_action;
7514 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7516 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7517 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7519 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7520 if (flow_dv_create_action_l2_decap
7521 (dev, dev_flow, attr->transfer, error))
7523 dev_flow->dv.actions[actions_n++] =
7524 dev_flow->dv.encap_decap->verbs_action;
7526 /* If decap is followed by encap, handle it at encap. */
7527 action_flags |= MLX5_FLOW_ACTION_DECAP;
7529 case RTE_FLOW_ACTION_TYPE_JUMP:
7530 jump_data = action->conf;
7531 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7533 !!priv->fdb_def_rule,
7537 tbl = flow_dv_tbl_resource_get(dev, table,
7539 attr->transfer, error);
7541 return rte_flow_error_set
7543 RTE_FLOW_ERROR_TYPE_ACTION,
7545 "cannot create jump action.");
7546 if (flow_dv_jump_tbl_resource_register
7547 (dev, tbl, dev_flow, error)) {
7548 flow_dv_tbl_resource_release(dev, tbl);
7549 return rte_flow_error_set
7551 RTE_FLOW_ERROR_TYPE_ACTION,
7553 "cannot create jump action.");
7555 dev_flow->dv.actions[actions_n++] =
7556 dev_flow->dv.jump->action;
7557 action_flags |= MLX5_FLOW_ACTION_JUMP;
7559 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7560 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7561 if (flow_dv_convert_action_modify_mac
7562 (mhdr_res, actions, error))
7564 action_flags |= actions->type ==
7565 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7566 MLX5_FLOW_ACTION_SET_MAC_SRC :
7567 MLX5_FLOW_ACTION_SET_MAC_DST;
7569 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7570 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7571 if (flow_dv_convert_action_modify_ipv4
7572 (mhdr_res, actions, error))
7574 action_flags |= actions->type ==
7575 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7576 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7577 MLX5_FLOW_ACTION_SET_IPV4_DST;
7579 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7580 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7581 if (flow_dv_convert_action_modify_ipv6
7582 (mhdr_res, actions, error))
7584 action_flags |= actions->type ==
7585 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7586 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7587 MLX5_FLOW_ACTION_SET_IPV6_DST;
7589 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7590 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7591 if (flow_dv_convert_action_modify_tp
7592 (mhdr_res, actions, items,
7593 &flow_attr, dev_flow, !!(action_flags &
7594 MLX5_FLOW_ACTION_DECAP), error))
7596 action_flags |= actions->type ==
7597 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7598 MLX5_FLOW_ACTION_SET_TP_SRC :
7599 MLX5_FLOW_ACTION_SET_TP_DST;
7601 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7602 if (flow_dv_convert_action_modify_dec_ttl
7603 (mhdr_res, items, &flow_attr, dev_flow,
7605 MLX5_FLOW_ACTION_DECAP), error))
7607 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7609 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7610 if (flow_dv_convert_action_modify_ttl
7611 (mhdr_res, actions, items, &flow_attr,
7612 dev_flow, !!(action_flags &
7613 MLX5_FLOW_ACTION_DECAP), error))
7615 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7617 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7618 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7619 if (flow_dv_convert_action_modify_tcp_seq
7620 (mhdr_res, actions, error))
7622 action_flags |= actions->type ==
7623 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7624 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7625 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7628 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7629 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7630 if (flow_dv_convert_action_modify_tcp_ack
7631 (mhdr_res, actions, error))
7633 action_flags |= actions->type ==
7634 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7635 MLX5_FLOW_ACTION_INC_TCP_ACK :
7636 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7638 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7639 if (flow_dv_convert_action_set_reg
7640 (mhdr_res, actions, error))
7642 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7644 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7645 if (flow_dv_convert_action_copy_mreg
7646 (dev, mhdr_res, actions, error))
7648 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7650 case RTE_FLOW_ACTION_TYPE_METER:
7651 mtr = actions->conf;
7653 flow->meter = mlx5_flow_meter_attach(priv,
7657 return rte_flow_error_set(error,
7659 RTE_FLOW_ERROR_TYPE_ACTION,
7662 "or invalid parameters");
7664 /* Set the meter action. */
7665 dev_flow->dv.actions[actions_n++] =
7666 flow->meter->mfts->meter_action;
7667 action_flags |= MLX5_FLOW_ACTION_METER;
7669 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7670 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7673 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7675 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7676 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7679 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7681 case RTE_FLOW_ACTION_TYPE_END:
7683 if (mhdr_res->actions_num) {
7684 /* create modify action if needed. */
7685 if (flow_dv_modify_hdr_resource_register
7686 (dev, mhdr_res, dev_flow, error))
7688 dev_flow->dv.actions[modify_action_position] =
7689 dev_flow->dv.modify_hdr->verbs_action;
7695 if (mhdr_res->actions_num &&
7696 modify_action_position == UINT32_MAX)
7697 modify_action_position = actions_n++;
7699 dev_flow->dv.actions_n = actions_n;
7700 dev_flow->actions = action_flags;
7701 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7702 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7703 int item_type = items->type;
7705 switch (item_type) {
7706 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7707 flow_dv_translate_item_port_id(dev, match_mask,
7708 match_value, items);
7709 last_item = MLX5_FLOW_ITEM_PORT_ID;
7711 case RTE_FLOW_ITEM_TYPE_ETH:
7712 flow_dv_translate_item_eth(match_mask, match_value,
7714 matcher.priority = MLX5_PRIORITY_MAP_L2;
7715 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7716 MLX5_FLOW_LAYER_OUTER_L2;
7718 case RTE_FLOW_ITEM_TYPE_VLAN:
7719 flow_dv_translate_item_vlan(dev_flow,
7720 match_mask, match_value,
7722 matcher.priority = MLX5_PRIORITY_MAP_L2;
7723 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7724 MLX5_FLOW_LAYER_INNER_VLAN) :
7725 (MLX5_FLOW_LAYER_OUTER_L2 |
7726 MLX5_FLOW_LAYER_OUTER_VLAN);
7728 case RTE_FLOW_ITEM_TYPE_IPV4:
7729 mlx5_flow_tunnel_ip_check(items, next_protocol,
7730 &item_flags, &tunnel);
7731 flow_dv_translate_item_ipv4(match_mask, match_value,
7732 items, item_flags, tunnel,
7734 matcher.priority = MLX5_PRIORITY_MAP_L3;
7735 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7736 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7737 if (items->mask != NULL &&
7738 ((const struct rte_flow_item_ipv4 *)
7739 items->mask)->hdr.next_proto_id) {
7741 ((const struct rte_flow_item_ipv4 *)
7742 (items->spec))->hdr.next_proto_id;
7744 ((const struct rte_flow_item_ipv4 *)
7745 (items->mask))->hdr.next_proto_id;
7747 /* Reset for inner layer. */
7748 next_protocol = 0xff;
7751 case RTE_FLOW_ITEM_TYPE_IPV6:
7752 mlx5_flow_tunnel_ip_check(items, next_protocol,
7753 &item_flags, &tunnel);
7754 flow_dv_translate_item_ipv6(match_mask, match_value,
7755 items, item_flags, tunnel,
7757 matcher.priority = MLX5_PRIORITY_MAP_L3;
7758 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7759 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7760 if (items->mask != NULL &&
7761 ((const struct rte_flow_item_ipv6 *)
7762 items->mask)->hdr.proto) {
7764 ((const struct rte_flow_item_ipv6 *)
7765 items->spec)->hdr.proto;
7767 ((const struct rte_flow_item_ipv6 *)
7768 items->mask)->hdr.proto;
7770 /* Reset for inner layer. */
7771 next_protocol = 0xff;
7774 case RTE_FLOW_ITEM_TYPE_TCP:
7775 flow_dv_translate_item_tcp(match_mask, match_value,
7777 matcher.priority = MLX5_PRIORITY_MAP_L4;
7778 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7779 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7781 case RTE_FLOW_ITEM_TYPE_UDP:
7782 flow_dv_translate_item_udp(match_mask, match_value,
7784 matcher.priority = MLX5_PRIORITY_MAP_L4;
7785 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7786 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7788 case RTE_FLOW_ITEM_TYPE_GRE:
7789 flow_dv_translate_item_gre(match_mask, match_value,
7791 matcher.priority = flow->rss.level >= 2 ?
7792 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7793 last_item = MLX5_FLOW_LAYER_GRE;
7795 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7796 flow_dv_translate_item_gre_key(match_mask,
7797 match_value, items);
7798 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7800 case RTE_FLOW_ITEM_TYPE_NVGRE:
7801 flow_dv_translate_item_nvgre(match_mask, match_value,
7803 matcher.priority = flow->rss.level >= 2 ?
7804 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7805 last_item = MLX5_FLOW_LAYER_GRE;
7807 case RTE_FLOW_ITEM_TYPE_VXLAN:
7808 flow_dv_translate_item_vxlan(match_mask, match_value,
7810 matcher.priority = flow->rss.level >= 2 ?
7811 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7812 last_item = MLX5_FLOW_LAYER_VXLAN;
7814 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7815 flow_dv_translate_item_vxlan_gpe(match_mask,
7818 matcher.priority = flow->rss.level >= 2 ?
7819 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7820 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7822 case RTE_FLOW_ITEM_TYPE_GENEVE:
7823 flow_dv_translate_item_geneve(match_mask, match_value,
7825 matcher.priority = flow->rss.level >= 2 ?
7826 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7827 last_item = MLX5_FLOW_LAYER_GENEVE;
7829 case RTE_FLOW_ITEM_TYPE_MPLS:
7830 flow_dv_translate_item_mpls(match_mask, match_value,
7831 items, last_item, tunnel);
7832 matcher.priority = flow->rss.level >= 2 ?
7833 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7834 last_item = MLX5_FLOW_LAYER_MPLS;
7836 case RTE_FLOW_ITEM_TYPE_MARK:
7837 flow_dv_translate_item_mark(dev, match_mask,
7838 match_value, items);
7839 last_item = MLX5_FLOW_ITEM_MARK;
7841 case RTE_FLOW_ITEM_TYPE_META:
7842 flow_dv_translate_item_meta(dev, match_mask,
7843 match_value, attr, items);
7844 last_item = MLX5_FLOW_ITEM_METADATA;
7846 case RTE_FLOW_ITEM_TYPE_ICMP:
7847 flow_dv_translate_item_icmp(match_mask, match_value,
7849 last_item = MLX5_FLOW_LAYER_ICMP;
7851 case RTE_FLOW_ITEM_TYPE_ICMP6:
7852 flow_dv_translate_item_icmp6(match_mask, match_value,
7854 last_item = MLX5_FLOW_LAYER_ICMP6;
7856 case RTE_FLOW_ITEM_TYPE_TAG:
7857 flow_dv_translate_item_tag(dev, match_mask,
7858 match_value, items);
7859 last_item = MLX5_FLOW_ITEM_TAG;
7861 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7862 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7863 match_value, items);
7864 last_item = MLX5_FLOW_ITEM_TAG;
7866 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7867 flow_dv_translate_item_tx_queue(dev, match_mask,
7870 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7872 case RTE_FLOW_ITEM_TYPE_GTP:
7873 flow_dv_translate_item_gtp(match_mask, match_value,
7875 matcher.priority = flow->rss.level >= 2 ?
7876 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7877 last_item = MLX5_FLOW_LAYER_GTP;
7882 item_flags |= last_item;
7885 * When E-Switch mode is enabled, we have two cases where we need to
7886 * set the source port manually.
7887 * The first one, is in case of Nic steering rule, and the second is
7888 * E-Switch rule where no port_id item was found. In both cases
7889 * the source port is set according the current port in use.
7891 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7892 (priv->representor || priv->master)) {
7893 if (flow_dv_translate_item_port_id(dev, match_mask,
7897 #ifdef RTE_LIBRTE_MLX5_DEBUG
7898 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7899 dev_flow->dv.value.buf));
7902 * Layers may be already initialized from prefix flow if this dev_flow
7903 * is the suffix flow.
7905 dev_flow->layers |= item_flags;
7906 if (action_flags & MLX5_FLOW_ACTION_RSS)
7907 flow_dv_hashfields_set(dev_flow);
7908 /* Register matcher. */
7909 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7911 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7913 /* reserved field no needs to be set to 0 here. */
7914 tbl_key.domain = attr->transfer;
7915 tbl_key.direction = attr->egress;
7916 tbl_key.table_id = dev_flow->group;
7917 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7923 * Apply the flow to the NIC, lock free,
7924 * (mutex should be acquired by caller).
7927 * Pointer to the Ethernet device structure.
7928 * @param[in, out] flow
7929 * Pointer to flow structure.
7931 * Pointer to error structure.
7934 * 0 on success, a negative errno value otherwise and rte_errno is set.
7937 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7938 struct rte_flow_error *error)
7940 struct mlx5_flow_dv *dv;
7941 struct mlx5_flow *dev_flow;
7942 struct mlx5_priv *priv = dev->data->dev_private;
7946 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7949 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7950 if (dev_flow->transfer) {
7951 dv->actions[n++] = priv->sh->esw_drop_action;
7953 dv->hrxq = mlx5_hrxq_drop_new(dev);
7957 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7959 "cannot get drop hash queue");
7962 dv->actions[n++] = dv->hrxq->action;
7964 } else if (dev_flow->actions &
7965 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7966 struct mlx5_hrxq *hrxq;
7968 MLX5_ASSERT(flow->rss.queue);
7969 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7970 MLX5_RSS_HASH_KEY_LEN,
7971 dev_flow->hash_fields,
7973 flow->rss.queue_num);
7975 hrxq = mlx5_hrxq_new
7976 (dev, flow->rss.key,
7977 MLX5_RSS_HASH_KEY_LEN,
7978 dev_flow->hash_fields,
7980 flow->rss.queue_num,
7981 !!(dev_flow->layers &
7982 MLX5_FLOW_LAYER_TUNNEL));
7987 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7988 "cannot get hash queue");
7992 dv->actions[n++] = dv->hrxq->action;
7995 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7996 (void *)&dv->value, n,
7999 rte_flow_error_set(error, errno,
8000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8002 "hardware refuses to create flow");
8005 if (priv->vmwa_context &&
8006 dev_flow->dv.vf_vlan.tag &&
8007 !dev_flow->dv.vf_vlan.created) {
8009 * The rule contains the VLAN pattern.
8010 * For VF we are going to create VLAN
8011 * interface to make hypervisor set correct
8012 * e-Switch vport context.
8014 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
8019 err = rte_errno; /* Save rte_errno before cleanup. */
8020 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8021 struct mlx5_flow_dv *dv = &dev_flow->dv;
8023 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8024 mlx5_hrxq_drop_release(dev);
8026 mlx5_hrxq_release(dev, dv->hrxq);
8029 if (dev_flow->dv.vf_vlan.tag &&
8030 dev_flow->dv.vf_vlan.created)
8031 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8033 rte_errno = err; /* Restore rte_errno. */
8038 * Release the flow matcher.
8041 * Pointer to Ethernet device.
8043 * Pointer to mlx5_flow.
8046 * 1 while a reference on it exists, 0 when freed.
8049 flow_dv_matcher_release(struct rte_eth_dev *dev,
8050 struct mlx5_flow *flow)
8052 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
8054 MLX5_ASSERT(matcher->matcher_object);
8055 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8056 dev->data->port_id, (void *)matcher,
8057 rte_atomic32_read(&matcher->refcnt));
8058 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8059 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8060 (matcher->matcher_object));
8061 LIST_REMOVE(matcher, next);
8062 /* table ref-- in release interface. */
8063 flow_dv_tbl_resource_release(dev, matcher->tbl);
8065 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8066 dev->data->port_id, (void *)matcher);
8073 * Release an encap/decap resource.
8076 * Pointer to mlx5_flow.
8079 * 1 while a reference on it exists, 0 when freed.
8082 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
8084 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8085 flow->dv.encap_decap;
8087 MLX5_ASSERT(cache_resource->verbs_action);
8088 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8089 (void *)cache_resource,
8090 rte_atomic32_read(&cache_resource->refcnt));
8091 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8092 claim_zero(mlx5_glue->destroy_flow_action
8093 (cache_resource->verbs_action));
8094 LIST_REMOVE(cache_resource, next);
8095 rte_free(cache_resource);
8096 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8097 (void *)cache_resource);
8104 * Release an jump to table action resource.
8107 * Pointer to Ethernet device.
8109 * Pointer to mlx5_flow.
8112 * 1 while a reference on it exists, 0 when freed.
8115 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8116 struct mlx5_flow *flow)
8118 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
8119 struct mlx5_flow_tbl_data_entry *tbl_data =
8120 container_of(cache_resource,
8121 struct mlx5_flow_tbl_data_entry, jump);
8123 MLX5_ASSERT(cache_resource->action);
8124 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8125 (void *)cache_resource,
8126 rte_atomic32_read(&cache_resource->refcnt));
8127 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8128 claim_zero(mlx5_glue->destroy_flow_action
8129 (cache_resource->action));
8130 /* jump action memory free is inside the table release. */
8131 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8132 DRV_LOG(DEBUG, "jump table resource %p: removed",
8133 (void *)cache_resource);
8140 * Release a modify-header resource.
8143 * Pointer to mlx5_flow.
8146 * 1 while a reference on it exists, 0 when freed.
8149 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8151 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8152 flow->dv.modify_hdr;
8154 MLX5_ASSERT(cache_resource->verbs_action);
8155 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8156 (void *)cache_resource,
8157 rte_atomic32_read(&cache_resource->refcnt));
8158 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8159 claim_zero(mlx5_glue->destroy_flow_action
8160 (cache_resource->verbs_action));
8161 LIST_REMOVE(cache_resource, next);
8162 rte_free(cache_resource);
8163 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8164 (void *)cache_resource);
8171 * Release port ID action resource.
8174 * Pointer to mlx5_flow.
8177 * 1 while a reference on it exists, 0 when freed.
8180 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8182 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8183 flow->dv.port_id_action;
8185 MLX5_ASSERT(cache_resource->action);
8186 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8187 (void *)cache_resource,
8188 rte_atomic32_read(&cache_resource->refcnt));
8189 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8190 claim_zero(mlx5_glue->destroy_flow_action
8191 (cache_resource->action));
8192 LIST_REMOVE(cache_resource, next);
8193 rte_free(cache_resource);
8194 DRV_LOG(DEBUG, "port id action resource %p: removed",
8195 (void *)cache_resource);
8202 * Release push vlan action resource.
8205 * Pointer to mlx5_flow.
8208 * 1 while a reference on it exists, 0 when freed.
8211 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8213 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8214 flow->dv.push_vlan_res;
8216 MLX5_ASSERT(cache_resource->action);
8217 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8218 (void *)cache_resource,
8219 rte_atomic32_read(&cache_resource->refcnt));
8220 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8221 claim_zero(mlx5_glue->destroy_flow_action
8222 (cache_resource->action));
8223 LIST_REMOVE(cache_resource, next);
8224 rte_free(cache_resource);
8225 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8226 (void *)cache_resource);
8233 * Remove the flow from the NIC but keeps it in memory.
8234 * Lock free, (mutex should be acquired by caller).
8237 * Pointer to Ethernet device.
8238 * @param[in, out] flow
8239 * Pointer to flow structure.
8242 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8244 struct mlx5_flow_dv *dv;
8245 struct mlx5_flow *dev_flow;
8249 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8252 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8256 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8257 mlx5_hrxq_drop_release(dev);
8259 mlx5_hrxq_release(dev, dv->hrxq);
8262 if (dev_flow->dv.vf_vlan.tag &&
8263 dev_flow->dv.vf_vlan.created)
8264 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8269 * Remove the flow from the NIC and the memory.
8270 * Lock free, (mutex should be acquired by caller).
8273 * Pointer to the Ethernet device structure.
8274 * @param[in, out] flow
8275 * Pointer to flow structure.
8278 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8280 struct mlx5_flow *dev_flow;
8284 __flow_dv_remove(dev, flow);
8285 if (flow->counter) {
8286 flow_dv_counter_release(dev, flow->counter);
8287 flow->counter = NULL;
8290 mlx5_flow_meter_detach(flow->meter);
8293 while (!LIST_EMPTY(&flow->dev_flows)) {
8294 dev_flow = LIST_FIRST(&flow->dev_flows);
8295 LIST_REMOVE(dev_flow, next);
8296 if (dev_flow->dv.matcher)
8297 flow_dv_matcher_release(dev, dev_flow);
8298 if (dev_flow->dv.encap_decap)
8299 flow_dv_encap_decap_resource_release(dev_flow);
8300 if (dev_flow->dv.modify_hdr)
8301 flow_dv_modify_hdr_resource_release(dev_flow);
8302 if (dev_flow->dv.jump)
8303 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8304 if (dev_flow->dv.port_id_action)
8305 flow_dv_port_id_action_resource_release(dev_flow);
8306 if (dev_flow->dv.push_vlan_res)
8307 flow_dv_push_vlan_action_resource_release(dev_flow);
8308 if (dev_flow->dv.tag_resource)
8309 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8315 * Query a dv flow rule for its statistics via devx.
8318 * Pointer to Ethernet device.
8320 * Pointer to the sub flow.
8322 * data retrieved by the query.
8324 * Perform verbose error reporting if not NULL.
8327 * 0 on success, a negative errno value otherwise and rte_errno is set.
8330 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8331 void *data, struct rte_flow_error *error)
8333 struct mlx5_priv *priv = dev->data->dev_private;
8334 struct rte_flow_query_count *qc = data;
8336 if (!priv->config.devx)
8337 return rte_flow_error_set(error, ENOTSUP,
8338 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8340 "counters are not supported");
8341 if (flow->counter) {
8342 uint64_t pkts, bytes;
8343 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8347 return rte_flow_error_set(error, -err,
8348 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8349 NULL, "cannot read counters");
8352 qc->hits = pkts - flow->counter->hits;
8353 qc->bytes = bytes - flow->counter->bytes;
8355 flow->counter->hits = pkts;
8356 flow->counter->bytes = bytes;
8360 return rte_flow_error_set(error, EINVAL,
8361 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8363 "counters are not available");
8369 * @see rte_flow_query()
8373 flow_dv_query(struct rte_eth_dev *dev,
8374 struct rte_flow *flow __rte_unused,
8375 const struct rte_flow_action *actions __rte_unused,
8376 void *data __rte_unused,
8377 struct rte_flow_error *error __rte_unused)
8381 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8382 switch (actions->type) {
8383 case RTE_FLOW_ACTION_TYPE_VOID:
8385 case RTE_FLOW_ACTION_TYPE_COUNT:
8386 ret = flow_dv_query_count(dev, flow, data, error);
8389 return rte_flow_error_set(error, ENOTSUP,
8390 RTE_FLOW_ERROR_TYPE_ACTION,
8392 "action not supported");
8399 * Destroy the meter table set.
8400 * Lock free, (mutex should be acquired by caller).
8403 * Pointer to Ethernet device.
8405 * Pointer to the meter table set.
8411 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8412 struct mlx5_meter_domains_infos *tbl)
8414 struct mlx5_priv *priv = dev->data->dev_private;
8415 struct mlx5_meter_domains_infos *mtd =
8416 (struct mlx5_meter_domains_infos *)tbl;
8418 if (!mtd || !priv->config.dv_flow_en)
8420 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8421 claim_zero(mlx5_glue->dv_destroy_flow
8422 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8423 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8424 claim_zero(mlx5_glue->dv_destroy_flow
8425 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8426 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8427 claim_zero(mlx5_glue->dv_destroy_flow
8428 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8429 if (mtd->egress.color_matcher)
8430 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8431 (mtd->egress.color_matcher));
8432 if (mtd->egress.any_matcher)
8433 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8434 (mtd->egress.any_matcher));
8435 if (mtd->egress.tbl)
8436 claim_zero(flow_dv_tbl_resource_release(dev,
8438 if (mtd->ingress.color_matcher)
8439 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8440 (mtd->ingress.color_matcher));
8441 if (mtd->ingress.any_matcher)
8442 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8443 (mtd->ingress.any_matcher));
8444 if (mtd->ingress.tbl)
8445 claim_zero(flow_dv_tbl_resource_release(dev,
8447 if (mtd->transfer.color_matcher)
8448 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8449 (mtd->transfer.color_matcher));
8450 if (mtd->transfer.any_matcher)
8451 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8452 (mtd->transfer.any_matcher));
8453 if (mtd->transfer.tbl)
8454 claim_zero(flow_dv_tbl_resource_release(dev,
8455 mtd->transfer.tbl));
8457 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8462 /* Number of meter flow actions, count and jump or count and drop. */
8463 #define METER_ACTIONS 2
8466 * Create specify domain meter table and suffix table.
8469 * Pointer to Ethernet device.
8470 * @param[in,out] mtb
8471 * Pointer to DV meter table set.
8474 * @param[in] transfer
8476 * @param[in] color_reg_c_idx
8477 * Reg C index for color match.
8480 * 0 on success, -1 otherwise and rte_errno is set.
8483 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8484 struct mlx5_meter_domains_infos *mtb,
8485 uint8_t egress, uint8_t transfer,
8486 uint32_t color_reg_c_idx)
8488 struct mlx5_priv *priv = dev->data->dev_private;
8489 struct mlx5_ibv_shared *sh = priv->sh;
8490 struct mlx5_flow_dv_match_params mask = {
8491 .size = sizeof(mask.buf),
8493 struct mlx5_flow_dv_match_params value = {
8494 .size = sizeof(value.buf),
8496 struct mlx5dv_flow_matcher_attr dv_attr = {
8497 .type = IBV_FLOW_ATTR_NORMAL,
8499 .match_criteria_enable = 0,
8500 .match_mask = (void *)&mask,
8502 void *actions[METER_ACTIONS];
8503 struct mlx5_flow_tbl_resource **sfx_tbl;
8504 struct mlx5_meter_domain_info *dtb;
8505 struct rte_flow_error error;
8509 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8510 dtb = &mtb->transfer;
8511 } else if (egress) {
8512 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8515 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8516 dtb = &mtb->ingress;
8518 /* If the suffix table in missing, create it. */
8520 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8521 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8522 egress, transfer, &error);
8524 DRV_LOG(ERR, "Failed to create meter suffix table.");
8528 /* Create the meter table with METER level. */
8529 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8530 egress, transfer, &error);
8532 DRV_LOG(ERR, "Failed to create meter policer table.");
8535 /* Create matchers, Any and Color. */
8536 dv_attr.priority = 3;
8537 dv_attr.match_criteria_enable = 0;
8538 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8541 if (!dtb->any_matcher) {
8542 DRV_LOG(ERR, "Failed to create meter"
8543 " policer default matcher.");
8546 dv_attr.priority = 0;
8547 dv_attr.match_criteria_enable =
8548 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8549 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8550 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8551 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8554 if (!dtb->color_matcher) {
8555 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8558 if (mtb->count_actns[RTE_MTR_DROPPED])
8559 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8560 actions[i++] = mtb->drop_actn;
8561 /* Default rule: lowest priority, match any, actions: drop. */
8562 dtb->policer_rules[RTE_MTR_DROPPED] =
8563 mlx5_glue->dv_create_flow(dtb->any_matcher,
8564 (void *)&value, i, actions);
8565 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8566 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8575 * Create the needed meter and suffix tables.
8576 * Lock free, (mutex should be acquired by caller).
8579 * Pointer to Ethernet device.
8581 * Pointer to the flow meter.
8584 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8586 static struct mlx5_meter_domains_infos *
8587 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8588 const struct mlx5_flow_meter *fm)
8590 struct mlx5_priv *priv = dev->data->dev_private;
8591 struct mlx5_meter_domains_infos *mtb;
8595 if (!priv->mtr_en) {
8596 rte_errno = ENOTSUP;
8599 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8601 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8604 /* Create meter count actions */
8605 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8606 if (!fm->policer_stats.cnt[i])
8608 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8610 /* Create drop action. */
8611 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8612 if (!mtb->drop_actn) {
8613 DRV_LOG(ERR, "Failed to create drop action.");
8616 /* Egress meter table. */
8617 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8619 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8622 /* Ingress meter table. */
8623 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8625 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8628 /* FDB meter table. */
8629 if (priv->config.dv_esw_en) {
8630 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8631 priv->mtr_color_reg);
8633 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8639 flow_dv_destroy_mtr_tbl(dev, mtb);
8644 * Destroy domain policer rule.
8647 * Pointer to domain table.
8650 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8654 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8655 if (dt->policer_rules[i]) {
8656 claim_zero(mlx5_glue->dv_destroy_flow
8657 (dt->policer_rules[i]));
8658 dt->policer_rules[i] = NULL;
8661 if (dt->jump_actn) {
8662 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8663 dt->jump_actn = NULL;
8668 * Destroy policer rules.
8671 * Pointer to Ethernet device.
8673 * Pointer to flow meter structure.
8675 * Pointer to flow attributes.
8681 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8682 const struct mlx5_flow_meter *fm,
8683 const struct rte_flow_attr *attr)
8685 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8690 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8692 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8694 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8699 * Create specify domain meter policer rule.
8702 * Pointer to flow meter structure.
8704 * Pointer to DV meter table set.
8706 * Pointer to suffix table.
8707 * @param[in] mtr_reg_c
8708 * Color match REG_C.
8711 * 0 on success, -1 otherwise.
8714 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8715 struct mlx5_meter_domain_info *dtb,
8716 struct mlx5_flow_tbl_resource *sfx_tb,
8719 struct mlx5_flow_dv_match_params matcher = {
8720 .size = sizeof(matcher.buf),
8722 struct mlx5_flow_dv_match_params value = {
8723 .size = sizeof(value.buf),
8725 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8726 void *actions[METER_ACTIONS];
8729 /* Create jump action. */
8732 if (!dtb->jump_actn)
8734 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8736 if (!dtb->jump_actn) {
8737 DRV_LOG(ERR, "Failed to create policer jump action.");
8740 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8743 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8744 rte_col_2_mlx5_col(i), UINT8_MAX);
8745 if (mtb->count_actns[i])
8746 actions[j++] = mtb->count_actns[i];
8747 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8748 actions[j++] = mtb->drop_actn;
8750 actions[j++] = dtb->jump_actn;
8751 dtb->policer_rules[i] =
8752 mlx5_glue->dv_create_flow(dtb->color_matcher,
8755 if (!dtb->policer_rules[i]) {
8756 DRV_LOG(ERR, "Failed to create policer rule.");
8767 * Create policer rules.
8770 * Pointer to Ethernet device.
8772 * Pointer to flow meter structure.
8774 * Pointer to flow attributes.
8777 * 0 on success, -1 otherwise.
8780 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8781 struct mlx5_flow_meter *fm,
8782 const struct rte_flow_attr *attr)
8784 struct mlx5_priv *priv = dev->data->dev_private;
8785 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8789 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8790 priv->sh->tx_mtr_sfx_tbl,
8791 priv->mtr_color_reg);
8793 DRV_LOG(ERR, "Failed to create egress policer.");
8797 if (attr->ingress) {
8798 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8799 priv->sh->rx_mtr_sfx_tbl,
8800 priv->mtr_color_reg);
8802 DRV_LOG(ERR, "Failed to create ingress policer.");
8806 if (attr->transfer) {
8807 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8808 priv->sh->fdb_mtr_sfx_tbl,
8809 priv->mtr_color_reg);
8811 DRV_LOG(ERR, "Failed to create transfer policer.");
8817 flow_dv_destroy_policer_rules(dev, fm, attr);
8822 * Query a devx counter.
8825 * Pointer to the Ethernet device structure.
8827 * Pointer to the flow counter.
8829 * Set to clear the counter statistics.
8831 * The statistics value of packets.
8833 * The statistics value of bytes.
8836 * 0 on success, otherwise return -1.
8839 flow_dv_counter_query(struct rte_eth_dev *dev,
8840 struct mlx5_flow_counter *cnt, bool clear,
8841 uint64_t *pkts, uint64_t *bytes)
8843 struct mlx5_priv *priv = dev->data->dev_private;
8844 uint64_t inn_pkts, inn_bytes;
8847 if (!priv->config.devx)
8849 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8852 *pkts = inn_pkts - cnt->hits;
8853 *bytes = inn_bytes - cnt->bytes;
8855 cnt->hits = inn_pkts;
8856 cnt->bytes = inn_bytes;
8862 * Mutex-protected thunk to lock-free __flow_dv_translate().
8865 flow_dv_translate(struct rte_eth_dev *dev,
8866 struct mlx5_flow *dev_flow,
8867 const struct rte_flow_attr *attr,
8868 const struct rte_flow_item items[],
8869 const struct rte_flow_action actions[],
8870 struct rte_flow_error *error)
8874 flow_dv_shared_lock(dev);
8875 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8876 flow_dv_shared_unlock(dev);
8881 * Mutex-protected thunk to lock-free __flow_dv_apply().
8884 flow_dv_apply(struct rte_eth_dev *dev,
8885 struct rte_flow *flow,
8886 struct rte_flow_error *error)
8890 flow_dv_shared_lock(dev);
8891 ret = __flow_dv_apply(dev, flow, error);
8892 flow_dv_shared_unlock(dev);
8897 * Mutex-protected thunk to lock-free __flow_dv_remove().
8900 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8902 flow_dv_shared_lock(dev);
8903 __flow_dv_remove(dev, flow);
8904 flow_dv_shared_unlock(dev);
8908 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8911 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8913 flow_dv_shared_lock(dev);
8914 __flow_dv_destroy(dev, flow);
8915 flow_dv_shared_unlock(dev);
8919 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8921 static struct mlx5_flow_counter *
8922 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8924 struct mlx5_flow_counter *cnt;
8926 flow_dv_shared_lock(dev);
8927 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8928 flow_dv_shared_unlock(dev);
8933 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8936 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8938 flow_dv_shared_lock(dev);
8939 flow_dv_counter_release(dev, cnt);
8940 flow_dv_shared_unlock(dev);
8943 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8944 .validate = flow_dv_validate,
8945 .prepare = flow_dv_prepare,
8946 .translate = flow_dv_translate,
8947 .apply = flow_dv_apply,
8948 .remove = flow_dv_remove,
8949 .destroy = flow_dv_destroy,
8950 .query = flow_dv_query,
8951 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8952 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8953 .create_policer_rules = flow_dv_create_policer_rules,
8954 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8955 .counter_alloc = flow_dv_counter_allocate,
8956 .counter_free = flow_dv_counter_free,
8957 .counter_query = flow_dv_counter_query,
8960 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */