1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
78 struct mlx5_flow_tbl_resource *tbl);
81 * Initialize flow attributes structure according to flow items' types.
83 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
84 * mode. For tunnel mode, the items to be modified are the outermost ones.
87 * Pointer to item specification.
89 * Pointer to flow attributes structure.
91 * Pointer to the sub flow.
92 * @param[in] tunnel_decap
93 * Whether action is after tunnel decapsulation.
96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
97 struct mlx5_flow *dev_flow, bool tunnel_decap)
99 uint64_t layers = dev_flow->handle->layers;
102 * If layers is already initialized, it means this dev_flow is the
103 * suffix flow, the layers flags is set by the prefix flow. Need to
104 * use the layer flags from prefix flow as the suffix flow may not
105 * have the user defined items as the flow is split.
108 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
112 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
114 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
119 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
120 uint8_t next_protocol = 0xff;
121 switch (item->type) {
122 case RTE_FLOW_ITEM_TYPE_GRE:
123 case RTE_FLOW_ITEM_TYPE_NVGRE:
124 case RTE_FLOW_ITEM_TYPE_VXLAN:
125 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
126 case RTE_FLOW_ITEM_TYPE_GENEVE:
127 case RTE_FLOW_ITEM_TYPE_MPLS:
131 case RTE_FLOW_ITEM_TYPE_IPV4:
134 if (item->mask != NULL &&
135 ((const struct rte_flow_item_ipv4 *)
136 item->mask)->hdr.next_proto_id)
138 ((const struct rte_flow_item_ipv4 *)
139 (item->spec))->hdr.next_proto_id &
140 ((const struct rte_flow_item_ipv4 *)
141 (item->mask))->hdr.next_proto_id;
142 if ((next_protocol == IPPROTO_IPIP ||
143 next_protocol == IPPROTO_IPV6) && tunnel_decap)
146 case RTE_FLOW_ITEM_TYPE_IPV6:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv6 *)
151 item->mask)->hdr.proto)
153 ((const struct rte_flow_item_ipv6 *)
154 (item->spec))->hdr.proto &
155 ((const struct rte_flow_item_ipv6 *)
156 (item->mask))->hdr.proto;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_UDP:
165 case RTE_FLOW_ITEM_TYPE_TCP:
177 * Convert rte_mtr_color to mlx5 color.
186 rte_col_2_mlx5_col(enum rte_color rcol)
189 case RTE_COLOR_GREEN:
190 return MLX5_FLOW_COLOR_GREEN;
191 case RTE_COLOR_YELLOW:
192 return MLX5_FLOW_COLOR_YELLOW;
194 return MLX5_FLOW_COLOR_RED;
198 return MLX5_FLOW_COLOR_UNDEFINED;
201 struct field_modify_info {
202 uint32_t size; /* Size of field in protocol header, in bytes. */
203 uint32_t offset; /* Offset of field in protocol header, in bytes. */
204 enum mlx5_modification_field id;
207 struct field_modify_info modify_eth[] = {
208 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
209 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
210 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
211 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
215 struct field_modify_info modify_vlan_out_first_vid[] = {
216 /* Size in bits !!! */
217 {12, 0, MLX5_MODI_OUT_FIRST_VID},
221 struct field_modify_info modify_ipv4[] = {
222 {1, 1, MLX5_MODI_OUT_IP_DSCP},
223 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
224 {4, 12, MLX5_MODI_OUT_SIPV4},
225 {4, 16, MLX5_MODI_OUT_DIPV4},
229 struct field_modify_info modify_ipv6[] = {
230 {1, 0, MLX5_MODI_OUT_IP_DSCP},
231 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
232 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
233 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
234 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
235 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
236 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
237 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
238 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
239 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
243 struct field_modify_info modify_udp[] = {
244 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
245 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
249 struct field_modify_info modify_tcp[] = {
250 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
251 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
252 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
253 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
259 uint8_t next_protocol, uint64_t *item_flags,
262 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
263 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
264 if (next_protocol == IPPROTO_IPIP) {
265 *item_flags |= MLX5_FLOW_LAYER_IPIP;
268 if (next_protocol == IPPROTO_IPV6) {
269 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
275 * Acquire the synchronizing object to protect multithreaded access
276 * to shared dv context. Lock occurs only if context is actually
277 * shared, i.e. we have multiport IB device and representors are
281 * Pointer to the rte_eth_dev structure.
284 flow_dv_shared_lock(struct rte_eth_dev *dev)
286 struct mlx5_priv *priv = dev->data->dev_private;
287 struct mlx5_ibv_shared *sh = priv->sh;
289 if (sh->dv_refcnt > 1) {
292 ret = pthread_mutex_lock(&sh->dv_mutex);
299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
301 struct mlx5_priv *priv = dev->data->dev_private;
302 struct mlx5_ibv_shared *sh = priv->sh;
304 if (sh->dv_refcnt > 1) {
307 ret = pthread_mutex_unlock(&sh->dv_mutex);
313 /* Update VLAN's VID/PCP based on input rte_flow_action.
316 * Pointer to struct rte_flow_action.
318 * Pointer to struct rte_vlan_hdr.
321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
322 struct rte_vlan_hdr *vlan)
325 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
327 ((const struct rte_flow_action_of_set_vlan_pcp *)
328 action->conf)->vlan_pcp;
329 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
330 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
331 vlan->vlan_tci |= vlan_tci;
332 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
333 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
334 vlan->vlan_tci |= rte_be_to_cpu_16
335 (((const struct rte_flow_action_of_set_vlan_vid *)
336 action->conf)->vlan_vid);
341 * Fetch 1, 2, 3 or 4 byte field from the byte array
342 * and return as unsigned integer in host-endian format.
345 * Pointer to data array.
347 * Size of field to extract.
350 * converted field in host endian format.
352 static inline uint32_t
353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
362 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = (ret << 8) | *(data + sizeof(uint16_t));
369 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
380 * Convert modify-header action to DV specification.
382 * Data length of each action is determined by provided field description
383 * and the item mask. Data bit offset and width of each action is determined
384 * by provided item mask.
387 * Pointer to item specification.
389 * Pointer to field modification information.
390 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
394 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
395 * Negative offset value sets the same offset as source offset.
396 * size field is ignored, value is taken from source field.
397 * @param[in,out] resource
398 * Pointer to the modify-header resource.
400 * Type of modification.
402 * Pointer to the error structure.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 flow_dv_convert_modify_action(struct rte_flow_item *item,
409 struct field_modify_info *field,
410 struct field_modify_info *dcopy,
411 struct mlx5_flow_dv_modify_hdr_resource *resource,
412 uint32_t type, struct rte_flow_error *error)
414 uint32_t i = resource->actions_num;
415 struct mlx5_modification_cmd *actions = resource->actions;
418 * The item and mask are provided in big-endian format.
419 * The fields should be presented as in big-endian format either.
420 * Mask must be always present, it defines the actual field width.
422 MLX5_ASSERT(item->mask);
423 MLX5_ASSERT(field->size);
430 if (i >= MLX5_MAX_MODIFY_NUM)
431 return rte_flow_error_set(error, EINVAL,
432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
433 "too many items to modify");
434 /* Fetch variable byte size mask from the array. */
435 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
436 field->offset, field->size);
441 /* Deduce actual data width in bits from mask value. */
442 off_b = rte_bsf32(mask);
443 size_b = sizeof(uint32_t) * CHAR_BIT -
444 off_b - __builtin_clz(mask);
446 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
447 actions[i] = (struct mlx5_modification_cmd) {
453 /* Convert entire record to expected big-endian format. */
454 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
455 if (type == MLX5_MODIFICATION_TYPE_COPY) {
457 actions[i].dst_field = dcopy->id;
458 actions[i].dst_offset =
459 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
460 /* Convert entire record to big-endian format. */
461 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
463 MLX5_ASSERT(item->spec);
464 data = flow_dv_fetch_field((const uint8_t *)item->spec +
465 field->offset, field->size);
466 /* Shift out the trailing masked bits from data. */
467 data = (data & mask) >> off_b;
468 actions[i].data1 = rte_cpu_to_be_32(data);
472 } while (field->size);
473 if (resource->actions_num == i)
474 return rte_flow_error_set(error, EINVAL,
475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
476 "invalid modification flow item");
477 resource->actions_num = i;
482 * Convert modify-header set IPv4 address action to DV specification.
484 * @param[in,out] resource
485 * Pointer to the modify-header resource.
487 * Pointer to action specification.
489 * Pointer to the error structure.
492 * 0 on success, a negative errno value otherwise and rte_errno is set.
495 flow_dv_convert_action_modify_ipv4
496 (struct mlx5_flow_dv_modify_hdr_resource *resource,
497 const struct rte_flow_action *action,
498 struct rte_flow_error *error)
500 const struct rte_flow_action_set_ipv4 *conf =
501 (const struct rte_flow_action_set_ipv4 *)(action->conf);
502 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
503 struct rte_flow_item_ipv4 ipv4;
504 struct rte_flow_item_ipv4 ipv4_mask;
506 memset(&ipv4, 0, sizeof(ipv4));
507 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
508 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
509 ipv4.hdr.src_addr = conf->ipv4_addr;
510 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
512 ipv4.hdr.dst_addr = conf->ipv4_addr;
513 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
516 item.mask = &ipv4_mask;
517 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
518 MLX5_MODIFICATION_TYPE_SET, error);
522 * Convert modify-header set IPv6 address action to DV specification.
524 * @param[in,out] resource
525 * Pointer to the modify-header resource.
527 * Pointer to action specification.
529 * Pointer to the error structure.
532 * 0 on success, a negative errno value otherwise and rte_errno is set.
535 flow_dv_convert_action_modify_ipv6
536 (struct mlx5_flow_dv_modify_hdr_resource *resource,
537 const struct rte_flow_action *action,
538 struct rte_flow_error *error)
540 const struct rte_flow_action_set_ipv6 *conf =
541 (const struct rte_flow_action_set_ipv6 *)(action->conf);
542 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
543 struct rte_flow_item_ipv6 ipv6;
544 struct rte_flow_item_ipv6 ipv6_mask;
546 memset(&ipv6, 0, sizeof(ipv6));
547 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
548 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
549 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6_mask.hdr.src_addr,
552 &rte_flow_item_ipv6_mask.hdr.src_addr,
553 sizeof(ipv6.hdr.src_addr));
555 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
556 sizeof(ipv6.hdr.dst_addr));
557 memcpy(&ipv6_mask.hdr.dst_addr,
558 &rte_flow_item_ipv6_mask.hdr.dst_addr,
559 sizeof(ipv6.hdr.dst_addr));
562 item.mask = &ipv6_mask;
563 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
564 MLX5_MODIFICATION_TYPE_SET, error);
568 * Convert modify-header set MAC address action to DV specification.
570 * @param[in,out] resource
571 * Pointer to the modify-header resource.
573 * Pointer to action specification.
575 * Pointer to the error structure.
578 * 0 on success, a negative errno value otherwise and rte_errno is set.
581 flow_dv_convert_action_modify_mac
582 (struct mlx5_flow_dv_modify_hdr_resource *resource,
583 const struct rte_flow_action *action,
584 struct rte_flow_error *error)
586 const struct rte_flow_action_set_mac *conf =
587 (const struct rte_flow_action_set_mac *)(action->conf);
588 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
589 struct rte_flow_item_eth eth;
590 struct rte_flow_item_eth eth_mask;
592 memset(ð, 0, sizeof(eth));
593 memset(ð_mask, 0, sizeof(eth_mask));
594 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
595 memcpy(ð.src.addr_bytes, &conf->mac_addr,
596 sizeof(eth.src.addr_bytes));
597 memcpy(ð_mask.src.addr_bytes,
598 &rte_flow_item_eth_mask.src.addr_bytes,
599 sizeof(eth_mask.src.addr_bytes));
601 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
602 sizeof(eth.dst.addr_bytes));
603 memcpy(ð_mask.dst.addr_bytes,
604 &rte_flow_item_eth_mask.dst.addr_bytes,
605 sizeof(eth_mask.dst.addr_bytes));
608 item.mask = ð_mask;
609 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
610 MLX5_MODIFICATION_TYPE_SET, error);
614 * Convert modify-header set VLAN VID action to DV specification.
616 * @param[in,out] resource
617 * Pointer to the modify-header resource.
619 * Pointer to action specification.
621 * Pointer to the error structure.
624 * 0 on success, a negative errno value otherwise and rte_errno is set.
627 flow_dv_convert_action_modify_vlan_vid
628 (struct mlx5_flow_dv_modify_hdr_resource *resource,
629 const struct rte_flow_action *action,
630 struct rte_flow_error *error)
632 const struct rte_flow_action_of_set_vlan_vid *conf =
633 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
634 int i = resource->actions_num;
635 struct mlx5_modification_cmd *actions = resource->actions;
636 struct field_modify_info *field = modify_vlan_out_first_vid;
638 if (i >= MLX5_MAX_MODIFY_NUM)
639 return rte_flow_error_set(error, EINVAL,
640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
641 "too many items to modify");
642 actions[i] = (struct mlx5_modification_cmd) {
643 .action_type = MLX5_MODIFICATION_TYPE_SET,
645 .length = field->size,
646 .offset = field->offset,
648 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
649 actions[i].data1 = conf->vlan_vid;
650 actions[i].data1 = actions[i].data1 << 16;
651 resource->actions_num = ++i;
656 * Convert modify-header set TP action to DV specification.
658 * @param[in,out] resource
659 * Pointer to the modify-header resource.
661 * Pointer to action specification.
663 * Pointer to rte_flow_item objects list.
665 * Pointer to flow attributes structure.
666 * @param[in] dev_flow
667 * Pointer to the sub flow.
668 * @param[in] tunnel_decap
669 * Whether action is after tunnel decapsulation.
671 * Pointer to the error structure.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 flow_dv_convert_action_modify_tp
678 (struct mlx5_flow_dv_modify_hdr_resource *resource,
679 const struct rte_flow_action *action,
680 const struct rte_flow_item *items,
681 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
682 bool tunnel_decap, struct rte_flow_error *error)
684 const struct rte_flow_action_set_tp *conf =
685 (const struct rte_flow_action_set_tp *)(action->conf);
686 struct rte_flow_item item;
687 struct rte_flow_item_udp udp;
688 struct rte_flow_item_udp udp_mask;
689 struct rte_flow_item_tcp tcp;
690 struct rte_flow_item_tcp tcp_mask;
691 struct field_modify_info *field;
694 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
696 memset(&udp, 0, sizeof(udp));
697 memset(&udp_mask, 0, sizeof(udp_mask));
698 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
699 udp.hdr.src_port = conf->port;
700 udp_mask.hdr.src_port =
701 rte_flow_item_udp_mask.hdr.src_port;
703 udp.hdr.dst_port = conf->port;
704 udp_mask.hdr.dst_port =
705 rte_flow_item_udp_mask.hdr.dst_port;
707 item.type = RTE_FLOW_ITEM_TYPE_UDP;
709 item.mask = &udp_mask;
712 MLX5_ASSERT(attr->tcp);
713 memset(&tcp, 0, sizeof(tcp));
714 memset(&tcp_mask, 0, sizeof(tcp_mask));
715 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
716 tcp.hdr.src_port = conf->port;
717 tcp_mask.hdr.src_port =
718 rte_flow_item_tcp_mask.hdr.src_port;
720 tcp.hdr.dst_port = conf->port;
721 tcp_mask.hdr.dst_port =
722 rte_flow_item_tcp_mask.hdr.dst_port;
724 item.type = RTE_FLOW_ITEM_TYPE_TCP;
726 item.mask = &tcp_mask;
729 return flow_dv_convert_modify_action(&item, field, NULL, resource,
730 MLX5_MODIFICATION_TYPE_SET, error);
734 * Convert modify-header set TTL action to DV specification.
736 * @param[in,out] resource
737 * Pointer to the modify-header resource.
739 * Pointer to action specification.
741 * Pointer to rte_flow_item objects list.
743 * Pointer to flow attributes structure.
744 * @param[in] dev_flow
745 * Pointer to the sub flow.
746 * @param[in] tunnel_decap
747 * Whether action is after tunnel decapsulation.
749 * Pointer to the error structure.
752 * 0 on success, a negative errno value otherwise and rte_errno is set.
755 flow_dv_convert_action_modify_ttl
756 (struct mlx5_flow_dv_modify_hdr_resource *resource,
757 const struct rte_flow_action *action,
758 const struct rte_flow_item *items,
759 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
760 bool tunnel_decap, struct rte_flow_error *error)
762 const struct rte_flow_action_set_ttl *conf =
763 (const struct rte_flow_action_set_ttl *)(action->conf);
764 struct rte_flow_item item;
765 struct rte_flow_item_ipv4 ipv4;
766 struct rte_flow_item_ipv4 ipv4_mask;
767 struct rte_flow_item_ipv6 ipv6;
768 struct rte_flow_item_ipv6 ipv6_mask;
769 struct field_modify_info *field;
772 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
774 memset(&ipv4, 0, sizeof(ipv4));
775 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
776 ipv4.hdr.time_to_live = conf->ttl_value;
777 ipv4_mask.hdr.time_to_live = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
780 item.mask = &ipv4_mask;
783 MLX5_ASSERT(attr->ipv6);
784 memset(&ipv6, 0, sizeof(ipv6));
785 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
786 ipv6.hdr.hop_limits = conf->ttl_value;
787 ipv6_mask.hdr.hop_limits = 0xFF;
788 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
790 item.mask = &ipv6_mask;
793 return flow_dv_convert_modify_action(&item, field, NULL, resource,
794 MLX5_MODIFICATION_TYPE_SET, error);
798 * Convert modify-header decrement TTL action to DV specification.
800 * @param[in,out] resource
801 * Pointer to the modify-header resource.
803 * Pointer to action specification.
805 * Pointer to rte_flow_item objects list.
807 * Pointer to flow attributes structure.
808 * @param[in] dev_flow
809 * Pointer to the sub flow.
810 * @param[in] tunnel_decap
811 * Whether action is after tunnel decapsulation.
813 * Pointer to the error structure.
816 * 0 on success, a negative errno value otherwise and rte_errno is set.
819 flow_dv_convert_action_modify_dec_ttl
820 (struct mlx5_flow_dv_modify_hdr_resource *resource,
821 const struct rte_flow_item *items,
822 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
823 bool tunnel_decap, struct rte_flow_error *error)
825 struct rte_flow_item item;
826 struct rte_flow_item_ipv4 ipv4;
827 struct rte_flow_item_ipv4 ipv4_mask;
828 struct rte_flow_item_ipv6 ipv6;
829 struct rte_flow_item_ipv6 ipv6_mask;
830 struct field_modify_info *field;
833 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
835 memset(&ipv4, 0, sizeof(ipv4));
836 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
837 ipv4.hdr.time_to_live = 0xFF;
838 ipv4_mask.hdr.time_to_live = 0xFF;
839 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
841 item.mask = &ipv4_mask;
844 MLX5_ASSERT(attr->ipv6);
845 memset(&ipv6, 0, sizeof(ipv6));
846 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
847 ipv6.hdr.hop_limits = 0xFF;
848 ipv6_mask.hdr.hop_limits = 0xFF;
849 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
851 item.mask = &ipv6_mask;
854 return flow_dv_convert_modify_action(&item, field, NULL, resource,
855 MLX5_MODIFICATION_TYPE_ADD, error);
859 * Convert modify-header increment/decrement TCP Sequence number
860 * to DV specification.
862 * @param[in,out] resource
863 * Pointer to the modify-header resource.
865 * Pointer to action specification.
867 * Pointer to the error structure.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 flow_dv_convert_action_modify_tcp_seq
874 (struct mlx5_flow_dv_modify_hdr_resource *resource,
875 const struct rte_flow_action *action,
876 struct rte_flow_error *error)
878 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
879 uint64_t value = rte_be_to_cpu_32(*conf);
880 struct rte_flow_item item;
881 struct rte_flow_item_tcp tcp;
882 struct rte_flow_item_tcp tcp_mask;
884 memset(&tcp, 0, sizeof(tcp));
885 memset(&tcp_mask, 0, sizeof(tcp_mask));
886 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
888 * The HW has no decrement operation, only increment operation.
889 * To simulate decrement X from Y using increment operation
890 * we need to add UINT32_MAX X times to Y.
891 * Each adding of UINT32_MAX decrements Y by 1.
894 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
895 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
896 item.type = RTE_FLOW_ITEM_TYPE_TCP;
898 item.mask = &tcp_mask;
899 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
900 MLX5_MODIFICATION_TYPE_ADD, error);
904 * Convert modify-header increment/decrement TCP Acknowledgment number
905 * to DV specification.
907 * @param[in,out] resource
908 * Pointer to the modify-header resource.
910 * Pointer to action specification.
912 * Pointer to the error structure.
915 * 0 on success, a negative errno value otherwise and rte_errno is set.
918 flow_dv_convert_action_modify_tcp_ack
919 (struct mlx5_flow_dv_modify_hdr_resource *resource,
920 const struct rte_flow_action *action,
921 struct rte_flow_error *error)
923 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
924 uint64_t value = rte_be_to_cpu_32(*conf);
925 struct rte_flow_item item;
926 struct rte_flow_item_tcp tcp;
927 struct rte_flow_item_tcp tcp_mask;
929 memset(&tcp, 0, sizeof(tcp));
930 memset(&tcp_mask, 0, sizeof(tcp_mask));
931 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
933 * The HW has no decrement operation, only increment operation.
934 * To simulate decrement X from Y using increment operation
935 * we need to add UINT32_MAX X times to Y.
936 * Each adding of UINT32_MAX decrements Y by 1.
939 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
940 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
941 item.type = RTE_FLOW_ITEM_TYPE_TCP;
943 item.mask = &tcp_mask;
944 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
945 MLX5_MODIFICATION_TYPE_ADD, error);
948 static enum mlx5_modification_field reg_to_field[] = {
949 [REG_NONE] = MLX5_MODI_OUT_NONE,
950 [REG_A] = MLX5_MODI_META_DATA_REG_A,
951 [REG_B] = MLX5_MODI_META_DATA_REG_B,
952 [REG_C_0] = MLX5_MODI_META_REG_C_0,
953 [REG_C_1] = MLX5_MODI_META_REG_C_1,
954 [REG_C_2] = MLX5_MODI_META_REG_C_2,
955 [REG_C_3] = MLX5_MODI_META_REG_C_3,
956 [REG_C_4] = MLX5_MODI_META_REG_C_4,
957 [REG_C_5] = MLX5_MODI_META_REG_C_5,
958 [REG_C_6] = MLX5_MODI_META_REG_C_6,
959 [REG_C_7] = MLX5_MODI_META_REG_C_7,
963 * Convert register set to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_set_reg
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
982 struct mlx5_modification_cmd *actions = resource->actions;
983 uint32_t i = resource->actions_num;
985 if (i >= MLX5_MAX_MODIFY_NUM)
986 return rte_flow_error_set(error, EINVAL,
987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
988 "too many items to modify");
989 MLX5_ASSERT(conf->id != REG_NONE);
990 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
991 actions[i] = (struct mlx5_modification_cmd) {
992 .action_type = MLX5_MODIFICATION_TYPE_SET,
993 .field = reg_to_field[conf->id],
995 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
996 actions[i].data1 = rte_cpu_to_be_32(conf->data);
998 resource->actions_num = i;
1003 * Convert SET_TAG action to DV specification.
1006 * Pointer to the rte_eth_dev structure.
1007 * @param[in,out] resource
1008 * Pointer to the modify-header resource.
1010 * Pointer to action specification.
1012 * Pointer to the error structure.
1015 * 0 on success, a negative errno value otherwise and rte_errno is set.
1018 flow_dv_convert_action_set_tag
1019 (struct rte_eth_dev *dev,
1020 struct mlx5_flow_dv_modify_hdr_resource *resource,
1021 const struct rte_flow_action_set_tag *conf,
1022 struct rte_flow_error *error)
1024 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026 struct rte_flow_item item = {
1030 struct field_modify_info reg_c_x[] = {
1033 enum mlx5_modification_field reg_type;
1036 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1039 MLX5_ASSERT(ret != REG_NONE);
1040 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041 reg_type = reg_to_field[ret];
1042 MLX5_ASSERT(reg_type > 0);
1043 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045 MLX5_MODIFICATION_TYPE_SET, error);
1049 * Convert internal COPY_REG action to DV specification.
1052 * Pointer to the rte_eth_dev structure.
1053 * @param[in,out] res
1054 * Pointer to the modify-header resource.
1056 * Pointer to action specification.
1058 * Pointer to the error structure.
1061 * 0 on success, a negative errno value otherwise and rte_errno is set.
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065 struct mlx5_flow_dv_modify_hdr_resource *res,
1066 const struct rte_flow_action *action,
1067 struct rte_flow_error *error)
1069 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071 struct rte_flow_item item = {
1075 struct field_modify_info reg_src[] = {
1076 {4, 0, reg_to_field[conf->src]},
1079 struct field_modify_info reg_dst = {
1081 .id = reg_to_field[conf->dst],
1083 /* Adjust reg_c[0] usage according to reported mask. */
1084 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085 struct mlx5_priv *priv = dev->data->dev_private;
1086 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088 MLX5_ASSERT(reg_c0);
1089 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090 if (conf->dst == REG_C_0) {
1091 /* Copy to reg_c[0], within mask only. */
1092 reg_dst.offset = rte_bsf32(reg_c0);
1094 * Mask is ignoring the enianness, because
1095 * there is no conversion in datapath.
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098 /* Copy from destination lower bits to reg_c[0]. */
1099 mask = reg_c0 >> reg_dst.offset;
1101 /* Copy from destination upper bits to reg_c[0]. */
1102 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103 rte_fls_u32(reg_c0));
1106 mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108 /* Copy from reg_c[0] to destination lower bits. */
1111 /* Copy from reg_c[0] to destination upper bits. */
1112 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113 (rte_fls_u32(reg_c0) -
1118 return flow_dv_convert_modify_action(&item,
1119 reg_src, ®_dst, res,
1120 MLX5_MODIFICATION_TYPE_COPY,
1125 * Convert MARK action to DV specification. This routine is used
1126 * in extensive metadata only and requires metadata register to be
1127 * handled. In legacy mode hardware tag resource is engaged.
1130 * Pointer to the rte_eth_dev structure.
1132 * Pointer to MARK action specification.
1133 * @param[in,out] resource
1134 * Pointer to the modify-header resource.
1136 * Pointer to the error structure.
1139 * 0 on success, a negative errno value otherwise and rte_errno is set.
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143 const struct rte_flow_action_mark *conf,
1144 struct mlx5_flow_dv_modify_hdr_resource *resource,
1145 struct rte_flow_error *error)
1147 struct mlx5_priv *priv = dev->data->dev_private;
1148 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149 priv->sh->dv_mark_mask);
1150 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151 struct rte_flow_item item = {
1155 struct field_modify_info reg_c_x[] = {
1156 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1162 return rte_flow_error_set(error, EINVAL,
1163 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164 NULL, "zero mark action mask");
1165 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1168 MLX5_ASSERT(reg > 0);
1169 if (reg == REG_C_0) {
1170 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175 mask = rte_cpu_to_be_32(mask << shl_c0);
1177 reg_c_x[0].id = reg_to_field[reg];
1178 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179 MLX5_MODIFICATION_TYPE_SET, error);
1183 * Get metadata register index for specified steering domain.
1186 * Pointer to the rte_eth_dev structure.
1188 * Attributes of flow to determine steering domain.
1190 * Pointer to the error structure.
1193 * positive index on success, a negative errno value otherwise
1194 * and rte_errno is set.
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198 const struct rte_flow_attr *attr,
1199 struct rte_flow_error *error)
1202 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206 MLX5_METADATA_RX, 0, error);
1208 return rte_flow_error_set(error,
1209 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210 NULL, "unavailable "
1211 "metadata register");
1216 * Convert SET_META action to DV specification.
1219 * Pointer to the rte_eth_dev structure.
1220 * @param[in,out] resource
1221 * Pointer to the modify-header resource.
1223 * Attributes of flow that includes this item.
1225 * Pointer to action specification.
1227 * Pointer to the error structure.
1230 * 0 on success, a negative errno value otherwise and rte_errno is set.
1233 flow_dv_convert_action_set_meta
1234 (struct rte_eth_dev *dev,
1235 struct mlx5_flow_dv_modify_hdr_resource *resource,
1236 const struct rte_flow_attr *attr,
1237 const struct rte_flow_action_set_meta *conf,
1238 struct rte_flow_error *error)
1240 uint32_t data = conf->data;
1241 uint32_t mask = conf->mask;
1242 struct rte_flow_item item = {
1246 struct field_modify_info reg_c_x[] = {
1249 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254 * In datapath code there is no endianness
1255 * coversions for perfromance reasons, all
1256 * pattern conversions are done in rte_flow.
1258 if (reg == REG_C_0) {
1259 struct mlx5_priv *priv = dev->data->dev_private;
1260 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1263 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265 shl_c0 = rte_bsf32(msk_c0);
1267 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274 /* The routine expects parameters in memory as big-endian ones. */
1275 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276 MLX5_MODIFICATION_TYPE_SET, error);
1280 * Convert modify-header set IPv4 DSCP action to DV specification.
1282 * @param[in,out] resource
1283 * Pointer to the modify-header resource.
1285 * Pointer to action specification.
1287 * Pointer to the error structure.
1290 * 0 on success, a negative errno value otherwise and rte_errno is set.
1293 flow_dv_convert_action_modify_ipv4_dscp
1294 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295 const struct rte_flow_action *action,
1296 struct rte_flow_error *error)
1298 const struct rte_flow_action_set_dscp *conf =
1299 (const struct rte_flow_action_set_dscp *)(action->conf);
1300 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301 struct rte_flow_item_ipv4 ipv4;
1302 struct rte_flow_item_ipv4 ipv4_mask;
1304 memset(&ipv4, 0, sizeof(ipv4));
1305 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306 ipv4.hdr.type_of_service = conf->dscp;
1307 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309 item.mask = &ipv4_mask;
1310 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311 MLX5_MODIFICATION_TYPE_SET, error);
1315 * Convert modify-header set IPv6 DSCP action to DV specification.
1317 * @param[in,out] resource
1318 * Pointer to the modify-header resource.
1320 * Pointer to action specification.
1322 * Pointer to the error structure.
1325 * 0 on success, a negative errno value otherwise and rte_errno is set.
1328 flow_dv_convert_action_modify_ipv6_dscp
1329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330 const struct rte_flow_action *action,
1331 struct rte_flow_error *error)
1333 const struct rte_flow_action_set_dscp *conf =
1334 (const struct rte_flow_action_set_dscp *)(action->conf);
1335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336 struct rte_flow_item_ipv6 ipv6;
1337 struct rte_flow_item_ipv6 ipv6_mask;
1339 memset(&ipv6, 0, sizeof(ipv6));
1340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343 * rdma-core only accept the DSCP bits byte aligned start from
1344 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345 * bits in IPv6 case as rdma-core requires byte aligned value.
1347 ipv6.hdr.vtc_flow = conf->dscp;
1348 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350 item.mask = &ipv6_mask;
1351 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352 MLX5_MODIFICATION_TYPE_SET, error);
1356 * Validate MARK item.
1359 * Pointer to the rte_eth_dev structure.
1361 * Item specification.
1363 * Attributes of flow that includes this item.
1365 * Pointer to error structure.
1368 * 0 on success, a negative errno value otherwise and rte_errno is set.
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372 const struct rte_flow_item *item,
1373 const struct rte_flow_attr *attr __rte_unused,
1374 struct rte_flow_error *error)
1376 struct mlx5_priv *priv = dev->data->dev_private;
1377 struct mlx5_dev_config *config = &priv->config;
1378 const struct rte_flow_item_mark *spec = item->spec;
1379 const struct rte_flow_item_mark *mask = item->mask;
1380 const struct rte_flow_item_mark nic_mask = {
1381 .id = priv->sh->dv_mark_mask,
1385 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386 return rte_flow_error_set(error, ENOTSUP,
1387 RTE_FLOW_ERROR_TYPE_ITEM, item,
1388 "extended metadata feature"
1390 if (!mlx5_flow_ext_mreg_supported(dev))
1391 return rte_flow_error_set(error, ENOTSUP,
1392 RTE_FLOW_ERROR_TYPE_ITEM, item,
1393 "extended metadata register"
1394 " isn't supported");
1396 return rte_flow_error_set(error, ENOTSUP,
1397 RTE_FLOW_ERROR_TYPE_ITEM, item,
1398 "extended metadata register"
1399 " isn't available");
1400 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404 return rte_flow_error_set(error, EINVAL,
1405 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407 "data cannot be empty");
1408 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409 return rte_flow_error_set(error, EINVAL,
1410 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412 "mark id exceeds the limit");
1416 return rte_flow_error_set(error, EINVAL,
1417 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418 "mask cannot be zero");
1420 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421 (const uint8_t *)&nic_mask,
1422 sizeof(struct rte_flow_item_mark),
1430 * Validate META item.
1433 * Pointer to the rte_eth_dev structure.
1435 * Item specification.
1437 * Attributes of flow that includes this item.
1439 * Pointer to error structure.
1442 * 0 on success, a negative errno value otherwise and rte_errno is set.
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446 const struct rte_flow_item *item,
1447 const struct rte_flow_attr *attr,
1448 struct rte_flow_error *error)
1450 struct mlx5_priv *priv = dev->data->dev_private;
1451 struct mlx5_dev_config *config = &priv->config;
1452 const struct rte_flow_item_meta *spec = item->spec;
1453 const struct rte_flow_item_meta *mask = item->mask;
1454 struct rte_flow_item_meta nic_mask = {
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464 "data cannot be empty");
1465 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466 if (!mlx5_flow_ext_mreg_supported(dev))
1467 return rte_flow_error_set(error, ENOTSUP,
1468 RTE_FLOW_ERROR_TYPE_ITEM, item,
1469 "extended metadata register"
1470 " isn't supported");
1471 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475 return rte_flow_error_set(error, ENOTSUP,
1476 RTE_FLOW_ERROR_TYPE_ITEM, item,
1480 nic_mask.data = priv->sh->dv_meta_mask;
1483 mask = &rte_flow_item_meta_mask;
1485 return rte_flow_error_set(error, EINVAL,
1486 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487 "mask cannot be zero");
1489 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490 (const uint8_t *)&nic_mask,
1491 sizeof(struct rte_flow_item_meta),
1497 * Validate TAG item.
1500 * Pointer to the rte_eth_dev structure.
1502 * Item specification.
1504 * Attributes of flow that includes this item.
1506 * Pointer to error structure.
1509 * 0 on success, a negative errno value otherwise and rte_errno is set.
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513 const struct rte_flow_item *item,
1514 const struct rte_flow_attr *attr __rte_unused,
1515 struct rte_flow_error *error)
1517 const struct rte_flow_item_tag *spec = item->spec;
1518 const struct rte_flow_item_tag *mask = item->mask;
1519 const struct rte_flow_item_tag nic_mask = {
1520 .data = RTE_BE32(UINT32_MAX),
1525 if (!mlx5_flow_ext_mreg_supported(dev))
1526 return rte_flow_error_set(error, ENOTSUP,
1527 RTE_FLOW_ERROR_TYPE_ITEM, item,
1528 "extensive metadata register"
1529 " isn't supported");
1531 return rte_flow_error_set(error, EINVAL,
1532 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534 "data cannot be empty");
1536 mask = &rte_flow_item_tag_mask;
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540 "mask cannot be zero");
1542 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543 (const uint8_t *)&nic_mask,
1544 sizeof(struct rte_flow_item_tag),
1548 if (mask->index != 0xff)
1549 return rte_flow_error_set(error, EINVAL,
1550 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551 "partial mask for tag index"
1552 " is not supported");
1553 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1556 MLX5_ASSERT(ret != REG_NONE);
1561 * Validate vport item.
1564 * Pointer to the rte_eth_dev structure.
1566 * Item specification.
1568 * Attributes of flow that includes this item.
1569 * @param[in] item_flags
1570 * Bit-fields that holds the items detected until now.
1572 * Pointer to error structure.
1575 * 0 on success, a negative errno value otherwise and rte_errno is set.
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579 const struct rte_flow_item *item,
1580 const struct rte_flow_attr *attr,
1581 uint64_t item_flags,
1582 struct rte_flow_error *error)
1584 const struct rte_flow_item_port_id *spec = item->spec;
1585 const struct rte_flow_item_port_id *mask = item->mask;
1586 const struct rte_flow_item_port_id switch_mask = {
1589 struct mlx5_priv *esw_priv;
1590 struct mlx5_priv *dev_priv;
1593 if (!attr->transfer)
1594 return rte_flow_error_set(error, EINVAL,
1595 RTE_FLOW_ERROR_TYPE_ITEM,
1597 "match on port id is valid only"
1598 " when transfer flag is enabled");
1599 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600 return rte_flow_error_set(error, ENOTSUP,
1601 RTE_FLOW_ERROR_TYPE_ITEM, item,
1602 "multiple source ports are not"
1605 mask = &switch_mask;
1606 if (mask->id != 0xffffffff)
1607 return rte_flow_error_set(error, ENOTSUP,
1608 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610 "no support for partial mask on"
1612 ret = mlx5_flow_item_acceptable
1613 (item, (const uint8_t *)mask,
1614 (const uint8_t *)&rte_flow_item_port_id_mask,
1615 sizeof(struct rte_flow_item_port_id),
1621 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623 return rte_flow_error_set(error, rte_errno,
1624 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625 "failed to obtain E-Switch info for"
1627 dev_priv = mlx5_dev_to_eswitch_info(dev);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632 "failed to obtain E-Switch info");
1633 if (esw_priv->domain_id != dev_priv->domain_id)
1634 return rte_flow_error_set(error, EINVAL,
1635 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636 "cannot match on a port from a"
1637 " different E-Switch");
1642 * Validate GTP item.
1645 * Pointer to the rte_eth_dev structure.
1647 * Item specification.
1648 * @param[in] item_flags
1649 * Bit-fields that holds the items detected until now.
1651 * Pointer to error structure.
1654 * 0 on success, a negative errno value otherwise and rte_errno is set.
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658 const struct rte_flow_item *item,
1659 uint64_t item_flags,
1660 struct rte_flow_error *error)
1662 struct mlx5_priv *priv = dev->data->dev_private;
1663 const struct rte_flow_item_gtp *mask = item->mask;
1664 const struct rte_flow_item_gtp nic_mask = {
1666 .teid = RTE_BE32(0xffffffff),
1669 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "GTP support is not enabled");
1673 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674 return rte_flow_error_set(error, ENOTSUP,
1675 RTE_FLOW_ERROR_TYPE_ITEM, item,
1676 "multiple tunnel layers not"
1678 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679 return rte_flow_error_set(error, EINVAL,
1680 RTE_FLOW_ERROR_TYPE_ITEM, item,
1681 "no outer UDP layer found");
1683 mask = &rte_flow_item_gtp_mask;
1684 return mlx5_flow_item_acceptable
1685 (item, (const uint8_t *)mask,
1686 (const uint8_t *)&nic_mask,
1687 sizeof(struct rte_flow_item_gtp),
1692 * Validate the pop VLAN action.
1695 * Pointer to the rte_eth_dev structure.
1696 * @param[in] action_flags
1697 * Holds the actions detected until now.
1699 * Pointer to the pop vlan action.
1700 * @param[in] item_flags
1701 * The items found in this flow rule.
1703 * Pointer to flow attributes.
1705 * Pointer to error structure.
1708 * 0 on success, a negative errno value otherwise and rte_errno is set.
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712 uint64_t action_flags,
1713 const struct rte_flow_action *action,
1714 uint64_t item_flags,
1715 const struct rte_flow_attr *attr,
1716 struct rte_flow_error *error)
1718 const struct mlx5_priv *priv = dev->data->dev_private;
1722 if (!priv->sh->pop_vlan_action)
1723 return rte_flow_error_set(error, ENOTSUP,
1724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726 "pop vlan action is not supported");
1728 return rte_flow_error_set(error, ENOTSUP,
1729 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731 "pop vlan action not supported for "
1733 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734 return rte_flow_error_set(error, ENOTSUP,
1735 RTE_FLOW_ERROR_TYPE_ACTION, action,
1736 "no support for multiple VLAN "
1738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739 return rte_flow_error_set(error, ENOTSUP,
1740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742 "cannot pop vlan without a "
1743 "match on (outer) vlan in the flow");
1744 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745 return rte_flow_error_set(error, EINVAL,
1746 RTE_FLOW_ERROR_TYPE_ACTION, action,
1747 "wrong action order, port_id should "
1748 "be after pop VLAN action");
1749 if (!attr->transfer && priv->representor)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752 "pop vlan action for VF representor "
1753 "not supported on NIC table");
1758 * Get VLAN default info from vlan match info.
1761 * the list of item specifications.
1763 * pointer VLAN info to fill to.
1766 * 0 on success, a negative errno value otherwise and rte_errno is set.
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770 struct rte_vlan_hdr *vlan)
1772 const struct rte_flow_item_vlan nic_mask = {
1773 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774 MLX5DV_FLOW_VLAN_VID_MASK),
1775 .inner_type = RTE_BE16(0xffff),
1780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781 int type = items->type;
1783 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1787 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793 /* Only full match values are accepted */
1794 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798 rte_be_to_cpu_16(vlan_v->tci &
1799 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805 rte_be_to_cpu_16(vlan_v->tci &
1806 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808 if (vlan_m->inner_type == nic_mask.inner_type)
1809 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810 vlan_m->inner_type);
1815 * Validate the push VLAN action.
1818 * Pointer to the rte_eth_dev structure.
1819 * @param[in] action_flags
1820 * Holds the actions detected until now.
1821 * @param[in] item_flags
1822 * The items found in this flow rule.
1824 * Pointer to the action structure.
1826 * Pointer to flow attributes
1828 * Pointer to error structure.
1831 * 0 on success, a negative errno value otherwise and rte_errno is set.
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835 uint64_t action_flags,
1836 uint64_t item_flags __rte_unused,
1837 const struct rte_flow_action *action,
1838 const struct rte_flow_attr *attr,
1839 struct rte_flow_error *error)
1841 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842 const struct mlx5_priv *priv = dev->data->dev_private;
1844 if (!attr->transfer && attr->ingress)
1845 return rte_flow_error_set(error, ENOTSUP,
1846 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848 "push VLAN action not supported for "
1850 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "invalid vlan ethertype");
1855 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856 return rte_flow_error_set(error, ENOTSUP,
1857 RTE_FLOW_ERROR_TYPE_ACTION, action,
1858 "no support for multiple VLAN "
1860 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861 return rte_flow_error_set(error, EINVAL,
1862 RTE_FLOW_ERROR_TYPE_ACTION, action,
1863 "wrong action order, port_id should "
1864 "be after push VLAN");
1865 if (!attr->transfer && priv->representor)
1866 return rte_flow_error_set(error, ENOTSUP,
1867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868 "push vlan action for VF representor "
1869 "not supported on NIC table");
1875 * Validate the set VLAN PCP.
1877 * @param[in] action_flags
1878 * Holds the actions detected until now.
1879 * @param[in] actions
1880 * Pointer to the list of actions remaining in the flow rule.
1882 * Pointer to error structure.
1885 * 0 on success, a negative errno value otherwise and rte_errno is set.
1888 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1889 const struct rte_flow_action actions[],
1890 struct rte_flow_error *error)
1892 const struct rte_flow_action *action = actions;
1893 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1895 if (conf->vlan_pcp > 7)
1896 return rte_flow_error_set(error, EINVAL,
1897 RTE_FLOW_ERROR_TYPE_ACTION, action,
1898 "VLAN PCP value is too big");
1899 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1900 return rte_flow_error_set(error, ENOTSUP,
1901 RTE_FLOW_ERROR_TYPE_ACTION, action,
1902 "set VLAN PCP action must follow "
1903 "the push VLAN action");
1904 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1905 return rte_flow_error_set(error, ENOTSUP,
1906 RTE_FLOW_ERROR_TYPE_ACTION, action,
1907 "Multiple VLAN PCP modification are "
1909 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1910 return rte_flow_error_set(error, EINVAL,
1911 RTE_FLOW_ERROR_TYPE_ACTION, action,
1912 "wrong action order, port_id should "
1913 "be after set VLAN PCP");
1918 * Validate the set VLAN VID.
1920 * @param[in] item_flags
1921 * Holds the items detected in this rule.
1922 * @param[in] action_flags
1923 * Holds the actions detected until now.
1924 * @param[in] actions
1925 * Pointer to the list of actions remaining in the flow rule.
1927 * Pointer to error structure.
1930 * 0 on success, a negative errno value otherwise and rte_errno is set.
1933 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1934 uint64_t action_flags,
1935 const struct rte_flow_action actions[],
1936 struct rte_flow_error *error)
1938 const struct rte_flow_action *action = actions;
1939 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1941 if (conf->vlan_vid > RTE_BE16(0xFFE))
1942 return rte_flow_error_set(error, EINVAL,
1943 RTE_FLOW_ERROR_TYPE_ACTION, action,
1944 "VLAN VID value is too big");
1945 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1946 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1947 return rte_flow_error_set(error, ENOTSUP,
1948 RTE_FLOW_ERROR_TYPE_ACTION, action,
1949 "set VLAN VID action must follow push"
1950 " VLAN action or match on VLAN item");
1951 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1952 return rte_flow_error_set(error, ENOTSUP,
1953 RTE_FLOW_ERROR_TYPE_ACTION, action,
1954 "Multiple VLAN VID modifications are "
1956 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION, action,
1959 "wrong action order, port_id should "
1960 "be after set VLAN VID");
1965 * Validate the FLAG action.
1968 * Pointer to the rte_eth_dev structure.
1969 * @param[in] action_flags
1970 * Holds the actions detected until now.
1972 * Pointer to flow attributes
1974 * Pointer to error structure.
1977 * 0 on success, a negative errno value otherwise and rte_errno is set.
1980 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1981 uint64_t action_flags,
1982 const struct rte_flow_attr *attr,
1983 struct rte_flow_error *error)
1985 struct mlx5_priv *priv = dev->data->dev_private;
1986 struct mlx5_dev_config *config = &priv->config;
1989 /* Fall back if no extended metadata register support. */
1990 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1991 return mlx5_flow_validate_action_flag(action_flags, attr,
1993 /* Extensive metadata mode requires registers. */
1994 if (!mlx5_flow_ext_mreg_supported(dev))
1995 return rte_flow_error_set(error, ENOTSUP,
1996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1997 "no metadata registers "
1998 "to support flag action");
1999 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2000 return rte_flow_error_set(error, ENOTSUP,
2001 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2002 "extended metadata register"
2003 " isn't available");
2004 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2007 MLX5_ASSERT(ret > 0);
2008 if (action_flags & MLX5_FLOW_ACTION_MARK)
2009 return rte_flow_error_set(error, EINVAL,
2010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2011 "can't mark and flag in same flow");
2012 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2013 return rte_flow_error_set(error, EINVAL,
2014 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2016 " actions in same flow");
2021 * Validate MARK action.
2024 * Pointer to the rte_eth_dev structure.
2026 * Pointer to action.
2027 * @param[in] action_flags
2028 * Holds the actions detected until now.
2030 * Pointer to flow attributes
2032 * Pointer to error structure.
2035 * 0 on success, a negative errno value otherwise and rte_errno is set.
2038 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2039 const struct rte_flow_action *action,
2040 uint64_t action_flags,
2041 const struct rte_flow_attr *attr,
2042 struct rte_flow_error *error)
2044 struct mlx5_priv *priv = dev->data->dev_private;
2045 struct mlx5_dev_config *config = &priv->config;
2046 const struct rte_flow_action_mark *mark = action->conf;
2049 /* Fall back if no extended metadata register support. */
2050 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2051 return mlx5_flow_validate_action_mark(action, action_flags,
2053 /* Extensive metadata mode requires registers. */
2054 if (!mlx5_flow_ext_mreg_supported(dev))
2055 return rte_flow_error_set(error, ENOTSUP,
2056 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2057 "no metadata registers "
2058 "to support mark action");
2059 if (!priv->sh->dv_mark_mask)
2060 return rte_flow_error_set(error, ENOTSUP,
2061 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2062 "extended metadata register"
2063 " isn't available");
2064 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2067 MLX5_ASSERT(ret > 0);
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ACTION, action,
2071 "configuration cannot be null");
2072 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2073 return rte_flow_error_set(error, EINVAL,
2074 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2076 "mark id exceeds the limit");
2077 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2080 "can't flag and mark in same flow");
2081 if (action_flags & MLX5_FLOW_ACTION_MARK)
2082 return rte_flow_error_set(error, EINVAL,
2083 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2084 "can't have 2 mark actions in same"
2090 * Validate SET_META action.
2093 * Pointer to the rte_eth_dev structure.
2095 * Pointer to the action structure.
2096 * @param[in] action_flags
2097 * Holds the actions detected until now.
2099 * Pointer to flow attributes
2101 * Pointer to error structure.
2104 * 0 on success, a negative errno value otherwise and rte_errno is set.
2107 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2108 const struct rte_flow_action *action,
2109 uint64_t action_flags __rte_unused,
2110 const struct rte_flow_attr *attr,
2111 struct rte_flow_error *error)
2113 const struct rte_flow_action_set_meta *conf;
2114 uint32_t nic_mask = UINT32_MAX;
2117 if (!mlx5_flow_ext_mreg_supported(dev))
2118 return rte_flow_error_set(error, ENOTSUP,
2119 RTE_FLOW_ERROR_TYPE_ACTION, action,
2120 "extended metadata register"
2121 " isn't supported");
2122 reg = flow_dv_get_metadata_reg(dev, attr, error);
2125 if (reg != REG_A && reg != REG_B) {
2126 struct mlx5_priv *priv = dev->data->dev_private;
2128 nic_mask = priv->sh->dv_meta_mask;
2130 if (!(action->conf))
2131 return rte_flow_error_set(error, EINVAL,
2132 RTE_FLOW_ERROR_TYPE_ACTION, action,
2133 "configuration cannot be null");
2134 conf = (const struct rte_flow_action_set_meta *)action->conf;
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION, action,
2138 "zero mask doesn't have any effect");
2139 if (conf->mask & ~nic_mask)
2140 return rte_flow_error_set(error, EINVAL,
2141 RTE_FLOW_ERROR_TYPE_ACTION, action,
2142 "meta data must be within reg C0");
2147 * Validate SET_TAG action.
2150 * Pointer to the rte_eth_dev structure.
2152 * Pointer to the action structure.
2153 * @param[in] action_flags
2154 * Holds the actions detected until now.
2156 * Pointer to flow attributes
2158 * Pointer to error structure.
2161 * 0 on success, a negative errno value otherwise and rte_errno is set.
2164 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2165 const struct rte_flow_action *action,
2166 uint64_t action_flags,
2167 const struct rte_flow_attr *attr,
2168 struct rte_flow_error *error)
2170 const struct rte_flow_action_set_tag *conf;
2171 const uint64_t terminal_action_flags =
2172 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2173 MLX5_FLOW_ACTION_RSS;
2176 if (!mlx5_flow_ext_mreg_supported(dev))
2177 return rte_flow_error_set(error, ENOTSUP,
2178 RTE_FLOW_ERROR_TYPE_ACTION, action,
2179 "extensive metadata register"
2180 " isn't supported");
2181 if (!(action->conf))
2182 return rte_flow_error_set(error, EINVAL,
2183 RTE_FLOW_ERROR_TYPE_ACTION, action,
2184 "configuration cannot be null");
2185 conf = (const struct rte_flow_action_set_tag *)action->conf;
2187 return rte_flow_error_set(error, EINVAL,
2188 RTE_FLOW_ERROR_TYPE_ACTION, action,
2189 "zero mask doesn't have any effect");
2190 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2193 if (!attr->transfer && attr->ingress &&
2194 (action_flags & terminal_action_flags))
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "set_tag has no effect"
2198 " with terminal actions");
2203 * Validate count action.
2206 * Pointer to rte_eth_dev structure.
2208 * Pointer to error structure.
2211 * 0 on success, a negative errno value otherwise and rte_errno is set.
2214 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2215 struct rte_flow_error *error)
2217 struct mlx5_priv *priv = dev->data->dev_private;
2219 if (!priv->config.devx)
2221 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2225 return rte_flow_error_set
2227 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2229 "count action not supported");
2233 * Validate the L2 encap action.
2236 * Pointer to the rte_eth_dev structure.
2237 * @param[in] action_flags
2238 * Holds the actions detected until now.
2240 * Pointer to the action structure.
2242 * Pointer to flow attributes.
2244 * Pointer to error structure.
2247 * 0 on success, a negative errno value otherwise and rte_errno is set.
2250 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2251 uint64_t action_flags,
2252 const struct rte_flow_action *action,
2253 const struct rte_flow_attr *attr,
2254 struct rte_flow_error *error)
2256 const struct mlx5_priv *priv = dev->data->dev_private;
2258 if (!(action->conf))
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, action,
2261 "configuration cannot be null");
2262 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2263 return rte_flow_error_set(error, EINVAL,
2264 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2265 "can only have a single encap action "
2267 if (!attr->transfer && priv->representor)
2268 return rte_flow_error_set(error, ENOTSUP,
2269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2270 "encap action for VF representor "
2271 "not supported on NIC table");
2276 * Validate a decap action.
2279 * Pointer to the rte_eth_dev structure.
2280 * @param[in] action_flags
2281 * Holds the actions detected until now.
2283 * Pointer to flow attributes
2285 * Pointer to error structure.
2288 * 0 on success, a negative errno value otherwise and rte_errno is set.
2291 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2292 uint64_t action_flags,
2293 const struct rte_flow_attr *attr,
2294 struct rte_flow_error *error)
2296 const struct mlx5_priv *priv = dev->data->dev_private;
2298 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2299 return rte_flow_error_set(error, ENOTSUP,
2300 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2302 MLX5_FLOW_ACTION_DECAP ? "can only "
2303 "have a single decap action" : "decap "
2304 "after encap is not supported");
2305 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2306 return rte_flow_error_set(error, EINVAL,
2307 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2308 "can't have decap action after"
2311 return rte_flow_error_set(error, ENOTSUP,
2312 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2314 "decap action not supported for "
2316 if (!attr->transfer && priv->representor)
2317 return rte_flow_error_set(error, ENOTSUP,
2318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2319 "decap action for VF representor "
2320 "not supported on NIC table");
2324 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2327 * Validate the raw encap and decap actions.
2330 * Pointer to the rte_eth_dev structure.
2332 * Pointer to the decap action.
2334 * Pointer to the encap action.
2336 * Pointer to flow attributes
2337 * @param[in/out] action_flags
2338 * Holds the actions detected until now.
2339 * @param[out] actions_n
2340 * pointer to the number of actions counter.
2342 * Pointer to error structure.
2345 * 0 on success, a negative errno value otherwise and rte_errno is set.
2348 flow_dv_validate_action_raw_encap_decap
2349 (struct rte_eth_dev *dev,
2350 const struct rte_flow_action_raw_decap *decap,
2351 const struct rte_flow_action_raw_encap *encap,
2352 const struct rte_flow_attr *attr, uint64_t *action_flags,
2353 int *actions_n, struct rte_flow_error *error)
2355 const struct mlx5_priv *priv = dev->data->dev_private;
2358 if (encap && (!encap->size || !encap->data))
2359 return rte_flow_error_set(error, EINVAL,
2360 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2361 "raw encap data cannot be empty");
2362 if (decap && encap) {
2363 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2364 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2367 else if (encap->size <=
2368 MLX5_ENCAPSULATION_DECISION_SIZE &&
2370 MLX5_ENCAPSULATION_DECISION_SIZE)
2373 else if (encap->size >
2374 MLX5_ENCAPSULATION_DECISION_SIZE &&
2376 MLX5_ENCAPSULATION_DECISION_SIZE)
2377 /* 2 L2 actions: encap and decap. */
2380 return rte_flow_error_set(error,
2382 RTE_FLOW_ERROR_TYPE_ACTION,
2383 NULL, "unsupported too small "
2384 "raw decap and too small raw "
2385 "encap combination");
2388 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2392 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2396 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2397 return rte_flow_error_set(error, ENOTSUP,
2398 RTE_FLOW_ERROR_TYPE_ACTION,
2400 "small raw encap size");
2401 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2402 return rte_flow_error_set(error, EINVAL,
2403 RTE_FLOW_ERROR_TYPE_ACTION,
2405 "more than one encap action");
2406 if (!attr->transfer && priv->representor)
2407 return rte_flow_error_set
2409 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "encap action for VF representor "
2411 "not supported on NIC table");
2412 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2419 * Find existing encap/decap resource or create and register a new one.
2421 * @param[in, out] dev
2422 * Pointer to rte_eth_dev structure.
2423 * @param[in, out] resource
2424 * Pointer to encap/decap resource.
2425 * @parm[in, out] dev_flow
2426 * Pointer to the dev_flow.
2428 * pointer to error structure.
2431 * 0 on success otherwise -errno and errno is set.
2434 flow_dv_encap_decap_resource_register
2435 (struct rte_eth_dev *dev,
2436 struct mlx5_flow_dv_encap_decap_resource *resource,
2437 struct mlx5_flow *dev_flow,
2438 struct rte_flow_error *error)
2440 struct mlx5_priv *priv = dev->data->dev_private;
2441 struct mlx5_ibv_shared *sh = priv->sh;
2442 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2443 struct mlx5dv_dr_domain *domain;
2445 resource->flags = dev_flow->dv.group ? 0 : 1;
2446 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2447 domain = sh->fdb_domain;
2448 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2449 domain = sh->rx_domain;
2451 domain = sh->tx_domain;
2452 /* Lookup a matching resource from cache. */
2453 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2454 if (resource->reformat_type == cache_resource->reformat_type &&
2455 resource->ft_type == cache_resource->ft_type &&
2456 resource->flags == cache_resource->flags &&
2457 resource->size == cache_resource->size &&
2458 !memcmp((const void *)resource->buf,
2459 (const void *)cache_resource->buf,
2461 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2462 (void *)cache_resource,
2463 rte_atomic32_read(&cache_resource->refcnt));
2464 rte_atomic32_inc(&cache_resource->refcnt);
2465 dev_flow->handle->dvh.encap_decap = cache_resource;
2469 /* Register new encap/decap resource. */
2470 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2471 if (!cache_resource)
2472 return rte_flow_error_set(error, ENOMEM,
2473 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2474 "cannot allocate resource memory");
2475 *cache_resource = *resource;
2476 cache_resource->verbs_action =
2477 mlx5_glue->dv_create_flow_action_packet_reformat
2478 (sh->ctx, cache_resource->reformat_type,
2479 cache_resource->ft_type, domain, cache_resource->flags,
2480 cache_resource->size,
2481 (cache_resource->size ? cache_resource->buf : NULL));
2482 if (!cache_resource->verbs_action) {
2483 rte_free(cache_resource);
2484 return rte_flow_error_set(error, ENOMEM,
2485 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2486 NULL, "cannot create action");
2488 rte_atomic32_init(&cache_resource->refcnt);
2489 rte_atomic32_inc(&cache_resource->refcnt);
2490 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2491 dev_flow->handle->dvh.encap_decap = cache_resource;
2492 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2493 (void *)cache_resource,
2494 rte_atomic32_read(&cache_resource->refcnt));
2499 * Find existing table jump resource or create and register a new one.
2501 * @param[in, out] dev
2502 * Pointer to rte_eth_dev structure.
2503 * @param[in, out] tbl
2504 * Pointer to flow table resource.
2505 * @parm[in, out] dev_flow
2506 * Pointer to the dev_flow.
2508 * pointer to error structure.
2511 * 0 on success otherwise -errno and errno is set.
2514 flow_dv_jump_tbl_resource_register
2515 (struct rte_eth_dev *dev __rte_unused,
2516 struct mlx5_flow_tbl_resource *tbl,
2517 struct mlx5_flow *dev_flow,
2518 struct rte_flow_error *error)
2520 struct mlx5_flow_tbl_data_entry *tbl_data =
2521 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2525 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2527 tbl_data->jump.action =
2528 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2530 if (!tbl_data->jump.action)
2531 return rte_flow_error_set(error, ENOMEM,
2532 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2533 NULL, "cannot create jump action");
2534 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2535 (void *)&tbl_data->jump, cnt);
2537 /* old jump should not make the table ref++. */
2538 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2539 MLX5_ASSERT(tbl_data->jump.action);
2540 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2541 (void *)&tbl_data->jump, cnt);
2543 rte_atomic32_inc(&tbl_data->jump.refcnt);
2544 dev_flow->handle->dvh.jump = &tbl_data->jump;
2549 * Find existing table port ID resource or create and register a new one.
2551 * @param[in, out] dev
2552 * Pointer to rte_eth_dev structure.
2553 * @param[in, out] resource
2554 * Pointer to port ID action resource.
2555 * @parm[in, out] dev_flow
2556 * Pointer to the dev_flow.
2558 * pointer to error structure.
2561 * 0 on success otherwise -errno and errno is set.
2564 flow_dv_port_id_action_resource_register
2565 (struct rte_eth_dev *dev,
2566 struct mlx5_flow_dv_port_id_action_resource *resource,
2567 struct mlx5_flow *dev_flow,
2568 struct rte_flow_error *error)
2570 struct mlx5_priv *priv = dev->data->dev_private;
2571 struct mlx5_ibv_shared *sh = priv->sh;
2572 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2574 /* Lookup a matching resource from cache. */
2575 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2576 if (resource->port_id == cache_resource->port_id) {
2577 DRV_LOG(DEBUG, "port id action resource resource %p: "
2579 (void *)cache_resource,
2580 rte_atomic32_read(&cache_resource->refcnt));
2581 rte_atomic32_inc(&cache_resource->refcnt);
2582 dev_flow->handle->dvh.port_id_action = cache_resource;
2586 /* Register new port id action resource. */
2587 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2588 if (!cache_resource)
2589 return rte_flow_error_set(error, ENOMEM,
2590 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2591 "cannot allocate resource memory");
2592 *cache_resource = *resource;
2594 * Depending on rdma_core version the glue routine calls
2595 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2596 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2598 cache_resource->action =
2599 mlx5_glue->dr_create_flow_action_dest_port
2600 (priv->sh->fdb_domain, resource->port_id);
2601 if (!cache_resource->action) {
2602 rte_free(cache_resource);
2603 return rte_flow_error_set(error, ENOMEM,
2604 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2605 NULL, "cannot create action");
2607 rte_atomic32_init(&cache_resource->refcnt);
2608 rte_atomic32_inc(&cache_resource->refcnt);
2609 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2610 dev_flow->handle->dvh.port_id_action = cache_resource;
2611 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2612 (void *)cache_resource,
2613 rte_atomic32_read(&cache_resource->refcnt));
2618 * Find existing push vlan resource or create and register a new one.
2620 * @param [in, out] dev
2621 * Pointer to rte_eth_dev structure.
2622 * @param[in, out] resource
2623 * Pointer to port ID action resource.
2624 * @parm[in, out] dev_flow
2625 * Pointer to the dev_flow.
2627 * pointer to error structure.
2630 * 0 on success otherwise -errno and errno is set.
2633 flow_dv_push_vlan_action_resource_register
2634 (struct rte_eth_dev *dev,
2635 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2636 struct mlx5_flow *dev_flow,
2637 struct rte_flow_error *error)
2639 struct mlx5_priv *priv = dev->data->dev_private;
2640 struct mlx5_ibv_shared *sh = priv->sh;
2641 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2642 struct mlx5dv_dr_domain *domain;
2644 /* Lookup a matching resource from cache. */
2645 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2646 if (resource->vlan_tag == cache_resource->vlan_tag &&
2647 resource->ft_type == cache_resource->ft_type) {
2648 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2650 (void *)cache_resource,
2651 rte_atomic32_read(&cache_resource->refcnt));
2652 rte_atomic32_inc(&cache_resource->refcnt);
2653 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2657 /* Register new push_vlan action resource. */
2658 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2659 if (!cache_resource)
2660 return rte_flow_error_set(error, ENOMEM,
2661 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2662 "cannot allocate resource memory");
2663 *cache_resource = *resource;
2664 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2665 domain = sh->fdb_domain;
2666 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2667 domain = sh->rx_domain;
2669 domain = sh->tx_domain;
2670 cache_resource->action =
2671 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2672 resource->vlan_tag);
2673 if (!cache_resource->action) {
2674 rte_free(cache_resource);
2675 return rte_flow_error_set(error, ENOMEM,
2676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2677 NULL, "cannot create action");
2679 rte_atomic32_init(&cache_resource->refcnt);
2680 rte_atomic32_inc(&cache_resource->refcnt);
2681 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2682 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2683 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2684 (void *)cache_resource,
2685 rte_atomic32_read(&cache_resource->refcnt));
2689 * Get the size of specific rte_flow_item_type
2691 * @param[in] item_type
2692 * Tested rte_flow_item_type.
2695 * sizeof struct item_type, 0 if void or irrelevant.
2698 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2702 switch (item_type) {
2703 case RTE_FLOW_ITEM_TYPE_ETH:
2704 retval = sizeof(struct rte_flow_item_eth);
2706 case RTE_FLOW_ITEM_TYPE_VLAN:
2707 retval = sizeof(struct rte_flow_item_vlan);
2709 case RTE_FLOW_ITEM_TYPE_IPV4:
2710 retval = sizeof(struct rte_flow_item_ipv4);
2712 case RTE_FLOW_ITEM_TYPE_IPV6:
2713 retval = sizeof(struct rte_flow_item_ipv6);
2715 case RTE_FLOW_ITEM_TYPE_UDP:
2716 retval = sizeof(struct rte_flow_item_udp);
2718 case RTE_FLOW_ITEM_TYPE_TCP:
2719 retval = sizeof(struct rte_flow_item_tcp);
2721 case RTE_FLOW_ITEM_TYPE_VXLAN:
2722 retval = sizeof(struct rte_flow_item_vxlan);
2724 case RTE_FLOW_ITEM_TYPE_GRE:
2725 retval = sizeof(struct rte_flow_item_gre);
2727 case RTE_FLOW_ITEM_TYPE_NVGRE:
2728 retval = sizeof(struct rte_flow_item_nvgre);
2730 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2731 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2733 case RTE_FLOW_ITEM_TYPE_MPLS:
2734 retval = sizeof(struct rte_flow_item_mpls);
2736 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2744 #define MLX5_ENCAP_IPV4_VERSION 0x40
2745 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2746 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2747 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2748 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2749 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2750 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2753 * Convert the encap action data from list of rte_flow_item to raw buffer
2756 * Pointer to rte_flow_item objects list.
2758 * Pointer to the output buffer.
2760 * Pointer to the output buffer size.
2762 * Pointer to the error structure.
2765 * 0 on success, a negative errno value otherwise and rte_errno is set.
2768 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2769 size_t *size, struct rte_flow_error *error)
2771 struct rte_ether_hdr *eth = NULL;
2772 struct rte_vlan_hdr *vlan = NULL;
2773 struct rte_ipv4_hdr *ipv4 = NULL;
2774 struct rte_ipv6_hdr *ipv6 = NULL;
2775 struct rte_udp_hdr *udp = NULL;
2776 struct rte_vxlan_hdr *vxlan = NULL;
2777 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2778 struct rte_gre_hdr *gre = NULL;
2780 size_t temp_size = 0;
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION,
2785 NULL, "invalid empty data");
2786 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2787 len = flow_dv_get_item_len(items->type);
2788 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2789 return rte_flow_error_set(error, EINVAL,
2790 RTE_FLOW_ERROR_TYPE_ACTION,
2791 (void *)items->type,
2792 "items total size is too big"
2793 " for encap action");
2794 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2795 switch (items->type) {
2796 case RTE_FLOW_ITEM_TYPE_ETH:
2797 eth = (struct rte_ether_hdr *)&buf[temp_size];
2799 case RTE_FLOW_ITEM_TYPE_VLAN:
2800 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2802 return rte_flow_error_set(error, EINVAL,
2803 RTE_FLOW_ERROR_TYPE_ACTION,
2804 (void *)items->type,
2805 "eth header not found");
2806 if (!eth->ether_type)
2807 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2809 case RTE_FLOW_ITEM_TYPE_IPV4:
2810 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2812 return rte_flow_error_set(error, EINVAL,
2813 RTE_FLOW_ERROR_TYPE_ACTION,
2814 (void *)items->type,
2815 "neither eth nor vlan"
2817 if (vlan && !vlan->eth_proto)
2818 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2819 else if (eth && !eth->ether_type)
2820 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2821 if (!ipv4->version_ihl)
2822 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2823 MLX5_ENCAP_IPV4_IHL_MIN;
2824 if (!ipv4->time_to_live)
2825 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2827 case RTE_FLOW_ITEM_TYPE_IPV6:
2828 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2830 return rte_flow_error_set(error, EINVAL,
2831 RTE_FLOW_ERROR_TYPE_ACTION,
2832 (void *)items->type,
2833 "neither eth nor vlan"
2835 if (vlan && !vlan->eth_proto)
2836 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2837 else if (eth && !eth->ether_type)
2838 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2839 if (!ipv6->vtc_flow)
2841 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2842 if (!ipv6->hop_limits)
2843 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2845 case RTE_FLOW_ITEM_TYPE_UDP:
2846 udp = (struct rte_udp_hdr *)&buf[temp_size];
2848 return rte_flow_error_set(error, EINVAL,
2849 RTE_FLOW_ERROR_TYPE_ACTION,
2850 (void *)items->type,
2851 "ip header not found");
2852 if (ipv4 && !ipv4->next_proto_id)
2853 ipv4->next_proto_id = IPPROTO_UDP;
2854 else if (ipv6 && !ipv6->proto)
2855 ipv6->proto = IPPROTO_UDP;
2857 case RTE_FLOW_ITEM_TYPE_VXLAN:
2858 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2860 return rte_flow_error_set(error, EINVAL,
2861 RTE_FLOW_ERROR_TYPE_ACTION,
2862 (void *)items->type,
2863 "udp header not found");
2865 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2866 if (!vxlan->vx_flags)
2868 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2870 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2871 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2873 return rte_flow_error_set(error, EINVAL,
2874 RTE_FLOW_ERROR_TYPE_ACTION,
2875 (void *)items->type,
2876 "udp header not found");
2877 if (!vxlan_gpe->proto)
2878 return rte_flow_error_set(error, EINVAL,
2879 RTE_FLOW_ERROR_TYPE_ACTION,
2880 (void *)items->type,
2881 "next protocol not found");
2884 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2885 if (!vxlan_gpe->vx_flags)
2886 vxlan_gpe->vx_flags =
2887 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2889 case RTE_FLOW_ITEM_TYPE_GRE:
2890 case RTE_FLOW_ITEM_TYPE_NVGRE:
2891 gre = (struct rte_gre_hdr *)&buf[temp_size];
2893 return rte_flow_error_set(error, EINVAL,
2894 RTE_FLOW_ERROR_TYPE_ACTION,
2895 (void *)items->type,
2896 "next protocol not found");
2898 return rte_flow_error_set(error, EINVAL,
2899 RTE_FLOW_ERROR_TYPE_ACTION,
2900 (void *)items->type,
2901 "ip header not found");
2902 if (ipv4 && !ipv4->next_proto_id)
2903 ipv4->next_proto_id = IPPROTO_GRE;
2904 else if (ipv6 && !ipv6->proto)
2905 ipv6->proto = IPPROTO_GRE;
2907 case RTE_FLOW_ITEM_TYPE_VOID:
2910 return rte_flow_error_set(error, EINVAL,
2911 RTE_FLOW_ERROR_TYPE_ACTION,
2912 (void *)items->type,
2913 "unsupported item type");
2923 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2925 struct rte_ether_hdr *eth = NULL;
2926 struct rte_vlan_hdr *vlan = NULL;
2927 struct rte_ipv6_hdr *ipv6 = NULL;
2928 struct rte_udp_hdr *udp = NULL;
2932 eth = (struct rte_ether_hdr *)data;
2933 next_hdr = (char *)(eth + 1);
2934 proto = RTE_BE16(eth->ether_type);
2937 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2938 vlan = (struct rte_vlan_hdr *)next_hdr;
2939 proto = RTE_BE16(vlan->eth_proto);
2940 next_hdr += sizeof(struct rte_vlan_hdr);
2943 /* HW calculates IPv4 csum. no need to proceed */
2944 if (proto == RTE_ETHER_TYPE_IPV4)
2947 /* non IPv4/IPv6 header. not supported */
2948 if (proto != RTE_ETHER_TYPE_IPV6) {
2949 return rte_flow_error_set(error, ENOTSUP,
2950 RTE_FLOW_ERROR_TYPE_ACTION,
2951 NULL, "Cannot offload non IPv4/IPv6");
2954 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2956 /* ignore non UDP */
2957 if (ipv6->proto != IPPROTO_UDP)
2960 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2961 udp->dgram_cksum = 0;
2967 * Convert L2 encap action to DV specification.
2970 * Pointer to rte_eth_dev structure.
2972 * Pointer to action structure.
2973 * @param[in, out] dev_flow
2974 * Pointer to the mlx5_flow.
2975 * @param[in] transfer
2976 * Mark if the flow is E-Switch flow.
2978 * Pointer to the error structure.
2981 * 0 on success, a negative errno value otherwise and rte_errno is set.
2984 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2985 const struct rte_flow_action *action,
2986 struct mlx5_flow *dev_flow,
2988 struct rte_flow_error *error)
2990 const struct rte_flow_item *encap_data;
2991 const struct rte_flow_action_raw_encap *raw_encap_data;
2992 struct mlx5_flow_dv_encap_decap_resource res = {
2994 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2995 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2996 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2999 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3001 (const struct rte_flow_action_raw_encap *)action->conf;
3002 res.size = raw_encap_data->size;
3003 memcpy(res.buf, raw_encap_data->data, res.size);
3005 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3007 ((const struct rte_flow_action_vxlan_encap *)
3008 action->conf)->definition;
3011 ((const struct rte_flow_action_nvgre_encap *)
3012 action->conf)->definition;
3013 if (flow_dv_convert_encap_data(encap_data, res.buf,
3017 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3019 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3020 return rte_flow_error_set(error, EINVAL,
3021 RTE_FLOW_ERROR_TYPE_ACTION,
3022 NULL, "can't create L2 encap action");
3027 * Convert L2 decap action to DV specification.
3030 * Pointer to rte_eth_dev structure.
3031 * @param[in, out] dev_flow
3032 * Pointer to the mlx5_flow.
3033 * @param[in] transfer
3034 * Mark if the flow is E-Switch flow.
3036 * Pointer to the error structure.
3039 * 0 on success, a negative errno value otherwise and rte_errno is set.
3042 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3043 struct mlx5_flow *dev_flow,
3045 struct rte_flow_error *error)
3047 struct mlx5_flow_dv_encap_decap_resource res = {
3050 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3051 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3052 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3055 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3056 return rte_flow_error_set(error, EINVAL,
3057 RTE_FLOW_ERROR_TYPE_ACTION,
3058 NULL, "can't create L2 decap action");
3063 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3066 * Pointer to rte_eth_dev structure.
3068 * Pointer to action structure.
3069 * @param[in, out] dev_flow
3070 * Pointer to the mlx5_flow.
3072 * Pointer to the flow attributes.
3074 * Pointer to the error structure.
3077 * 0 on success, a negative errno value otherwise and rte_errno is set.
3080 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3081 const struct rte_flow_action *action,
3082 struct mlx5_flow *dev_flow,
3083 const struct rte_flow_attr *attr,
3084 struct rte_flow_error *error)
3086 const struct rte_flow_action_raw_encap *encap_data;
3087 struct mlx5_flow_dv_encap_decap_resource res;
3089 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3090 res.size = encap_data->size;
3091 memcpy(res.buf, encap_data->data, res.size);
3092 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3093 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3094 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3096 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3098 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3099 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3100 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3101 return rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION,
3103 NULL, "can't create encap action");
3108 * Create action push VLAN.
3111 * Pointer to rte_eth_dev structure.
3113 * Pointer to the flow attributes.
3115 * Pointer to the vlan to push to the Ethernet header.
3116 * @param[in, out] dev_flow
3117 * Pointer to the mlx5_flow.
3119 * Pointer to the error structure.
3122 * 0 on success, a negative errno value otherwise and rte_errno is set.
3125 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3126 const struct rte_flow_attr *attr,
3127 const struct rte_vlan_hdr *vlan,
3128 struct mlx5_flow *dev_flow,
3129 struct rte_flow_error *error)
3131 struct mlx5_flow_dv_push_vlan_action_resource res;
3134 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3137 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3139 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3140 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3141 return flow_dv_push_vlan_action_resource_register
3142 (dev, &res, dev_flow, error);
3146 * Validate the modify-header actions.
3148 * @param[in] action_flags
3149 * Holds the actions detected until now.
3151 * Pointer to the modify action.
3153 * Pointer to error structure.
3156 * 0 on success, a negative errno value otherwise and rte_errno is set.
3159 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3160 const struct rte_flow_action *action,
3161 struct rte_flow_error *error)
3163 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3164 return rte_flow_error_set(error, EINVAL,
3165 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3166 NULL, "action configuration not set");
3167 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3168 return rte_flow_error_set(error, EINVAL,
3169 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3170 "can't have encap action before"
3176 * Validate the modify-header MAC address actions.
3178 * @param[in] action_flags
3179 * Holds the actions detected until now.
3181 * Pointer to the modify action.
3182 * @param[in] item_flags
3183 * Holds the items detected.
3185 * Pointer to error structure.
3188 * 0 on success, a negative errno value otherwise and rte_errno is set.
3191 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3192 const struct rte_flow_action *action,
3193 const uint64_t item_flags,
3194 struct rte_flow_error *error)
3198 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3200 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3201 return rte_flow_error_set(error, EINVAL,
3202 RTE_FLOW_ERROR_TYPE_ACTION,
3204 "no L2 item in pattern");
3210 * Validate the modify-header IPv4 address actions.
3212 * @param[in] action_flags
3213 * Holds the actions detected until now.
3215 * Pointer to the modify action.
3216 * @param[in] item_flags
3217 * Holds the items detected.
3219 * Pointer to error structure.
3222 * 0 on success, a negative errno value otherwise and rte_errno is set.
3225 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3226 const struct rte_flow_action *action,
3227 const uint64_t item_flags,
3228 struct rte_flow_error *error)
3233 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3235 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3236 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3237 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3238 if (!(item_flags & layer))
3239 return rte_flow_error_set(error, EINVAL,
3240 RTE_FLOW_ERROR_TYPE_ACTION,
3242 "no ipv4 item in pattern");
3248 * Validate the modify-header IPv6 address actions.
3250 * @param[in] action_flags
3251 * Holds the actions detected until now.
3253 * Pointer to the modify action.
3254 * @param[in] item_flags
3255 * Holds the items detected.
3257 * Pointer to error structure.
3260 * 0 on success, a negative errno value otherwise and rte_errno is set.
3263 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3264 const struct rte_flow_action *action,
3265 const uint64_t item_flags,
3266 struct rte_flow_error *error)
3271 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3273 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3274 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3275 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3276 if (!(item_flags & layer))
3277 return rte_flow_error_set(error, EINVAL,
3278 RTE_FLOW_ERROR_TYPE_ACTION,
3280 "no ipv6 item in pattern");
3286 * Validate the modify-header TP actions.
3288 * @param[in] action_flags
3289 * Holds the actions detected until now.
3291 * Pointer to the modify action.
3292 * @param[in] item_flags
3293 * Holds the items detected.
3295 * Pointer to error structure.
3298 * 0 on success, a negative errno value otherwise and rte_errno is set.
3301 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3302 const struct rte_flow_action *action,
3303 const uint64_t item_flags,
3304 struct rte_flow_error *error)
3309 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3311 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3312 MLX5_FLOW_LAYER_INNER_L4 :
3313 MLX5_FLOW_LAYER_OUTER_L4;
3314 if (!(item_flags & layer))
3315 return rte_flow_error_set(error, EINVAL,
3316 RTE_FLOW_ERROR_TYPE_ACTION,
3317 NULL, "no transport layer "
3324 * Validate the modify-header actions of increment/decrement
3325 * TCP Sequence-number.
3327 * @param[in] action_flags
3328 * Holds the actions detected until now.
3330 * Pointer to the modify action.
3331 * @param[in] item_flags
3332 * Holds the items detected.
3334 * Pointer to error structure.
3337 * 0 on success, a negative errno value otherwise and rte_errno is set.
3340 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3341 const struct rte_flow_action *action,
3342 const uint64_t item_flags,
3343 struct rte_flow_error *error)
3348 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3350 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3351 MLX5_FLOW_LAYER_INNER_L4_TCP :
3352 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3353 if (!(item_flags & layer))
3354 return rte_flow_error_set(error, EINVAL,
3355 RTE_FLOW_ERROR_TYPE_ACTION,
3356 NULL, "no TCP item in"
3358 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3359 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3360 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3361 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3362 return rte_flow_error_set(error, EINVAL,
3363 RTE_FLOW_ERROR_TYPE_ACTION,
3365 "cannot decrease and increase"
3366 " TCP sequence number"
3367 " at the same time");
3373 * Validate the modify-header actions of increment/decrement
3374 * TCP Acknowledgment number.
3376 * @param[in] action_flags
3377 * Holds the actions detected until now.
3379 * Pointer to the modify action.
3380 * @param[in] item_flags
3381 * Holds the items detected.
3383 * Pointer to error structure.
3386 * 0 on success, a negative errno value otherwise and rte_errno is set.
3389 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3390 const struct rte_flow_action *action,
3391 const uint64_t item_flags,
3392 struct rte_flow_error *error)
3397 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3399 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3400 MLX5_FLOW_LAYER_INNER_L4_TCP :
3401 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3402 if (!(item_flags & layer))
3403 return rte_flow_error_set(error, EINVAL,
3404 RTE_FLOW_ERROR_TYPE_ACTION,
3405 NULL, "no TCP item in"
3407 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3408 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3409 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3410 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3411 return rte_flow_error_set(error, EINVAL,
3412 RTE_FLOW_ERROR_TYPE_ACTION,
3414 "cannot decrease and increase"
3415 " TCP acknowledgment number"
3416 " at the same time");
3422 * Validate the modify-header TTL actions.
3424 * @param[in] action_flags
3425 * Holds the actions detected until now.
3427 * Pointer to the modify action.
3428 * @param[in] item_flags
3429 * Holds the items detected.
3431 * Pointer to error structure.
3434 * 0 on success, a negative errno value otherwise and rte_errno is set.
3437 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3438 const struct rte_flow_action *action,
3439 const uint64_t item_flags,
3440 struct rte_flow_error *error)
3445 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3448 MLX5_FLOW_LAYER_INNER_L3 :
3449 MLX5_FLOW_LAYER_OUTER_L3;
3450 if (!(item_flags & layer))
3451 return rte_flow_error_set(error, EINVAL,
3452 RTE_FLOW_ERROR_TYPE_ACTION,
3454 "no IP protocol in pattern");
3460 * Validate jump action.
3463 * Pointer to the jump action.
3464 * @param[in] action_flags
3465 * Holds the actions detected until now.
3466 * @param[in] attributes
3467 * Pointer to flow attributes
3468 * @param[in] external
3469 * Action belongs to flow rule created by request external to PMD.
3471 * Pointer to error structure.
3474 * 0 on success, a negative errno value otherwise and rte_errno is set.
3477 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3478 uint64_t action_flags,
3479 const struct rte_flow_attr *attributes,
3480 bool external, struct rte_flow_error *error)
3482 uint32_t target_group, table;
3485 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3486 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3487 return rte_flow_error_set(error, EINVAL,
3488 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3489 "can't have 2 fate actions in"
3491 if (action_flags & MLX5_FLOW_ACTION_METER)
3492 return rte_flow_error_set(error, ENOTSUP,
3493 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3494 "jump with meter not support");
3496 return rte_flow_error_set(error, EINVAL,
3497 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3498 NULL, "action configuration not set");
3500 ((const struct rte_flow_action_jump *)action->conf)->group;
3501 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3502 true, &table, error);
3505 if (attributes->group == target_group)
3506 return rte_flow_error_set(error, EINVAL,
3507 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3508 "target group must be other than"
3509 " the current flow group");
3514 * Validate the port_id action.
3517 * Pointer to rte_eth_dev structure.
3518 * @param[in] action_flags
3519 * Bit-fields that holds the actions detected until now.
3521 * Port_id RTE action structure.
3523 * Attributes of flow that includes this action.
3525 * Pointer to error structure.
3528 * 0 on success, a negative errno value otherwise and rte_errno is set.
3531 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3532 uint64_t action_flags,
3533 const struct rte_flow_action *action,
3534 const struct rte_flow_attr *attr,
3535 struct rte_flow_error *error)
3537 const struct rte_flow_action_port_id *port_id;
3538 struct mlx5_priv *act_priv;
3539 struct mlx5_priv *dev_priv;
3542 if (!attr->transfer)
3543 return rte_flow_error_set(error, ENOTSUP,
3544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3546 "port id action is valid in transfer"
3548 if (!action || !action->conf)
3549 return rte_flow_error_set(error, ENOTSUP,
3550 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3552 "port id action parameters must be"
3554 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3555 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3556 return rte_flow_error_set(error, EINVAL,
3557 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3558 "can have only one fate actions in"
3560 dev_priv = mlx5_dev_to_eswitch_info(dev);
3562 return rte_flow_error_set(error, rte_errno,
3563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3565 "failed to obtain E-Switch info");
3566 port_id = action->conf;
3567 port = port_id->original ? dev->data->port_id : port_id->id;
3568 act_priv = mlx5_port_to_eswitch_info(port, false);
3570 return rte_flow_error_set
3572 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3573 "failed to obtain E-Switch port id for port");
3574 if (act_priv->domain_id != dev_priv->domain_id)
3575 return rte_flow_error_set
3577 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3578 "port does not belong to"
3579 " E-Switch being configured");
3584 * Get the maximum number of modify header actions.
3587 * Pointer to rte_eth_dev structure.
3589 * Flags bits to check if root level.
3592 * Max number of modify header actions device can support.
3595 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3598 * There's no way to directly query the max cap. Although it has to be
3599 * acquried by iterative trial, it is a safe assumption that more
3600 * actions are supported by FW if extensive metadata register is
3601 * supported. (Only in the root table)
3603 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3604 return MLX5_MAX_MODIFY_NUM;
3606 return mlx5_flow_ext_mreg_supported(dev) ?
3607 MLX5_ROOT_TBL_MODIFY_NUM :
3608 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3612 * Validate the meter action.
3615 * Pointer to rte_eth_dev structure.
3616 * @param[in] action_flags
3617 * Bit-fields that holds the actions detected until now.
3619 * Pointer to the meter action.
3621 * Attributes of flow that includes this action.
3623 * Pointer to error structure.
3626 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3629 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3630 uint64_t action_flags,
3631 const struct rte_flow_action *action,
3632 const struct rte_flow_attr *attr,
3633 struct rte_flow_error *error)
3635 struct mlx5_priv *priv = dev->data->dev_private;
3636 const struct rte_flow_action_meter *am = action->conf;
3637 struct mlx5_flow_meter *fm;
3640 return rte_flow_error_set(error, EINVAL,
3641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3642 "meter action conf is NULL");
3644 if (action_flags & MLX5_FLOW_ACTION_METER)
3645 return rte_flow_error_set(error, ENOTSUP,
3646 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3647 "meter chaining not support");
3648 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3649 return rte_flow_error_set(error, ENOTSUP,
3650 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3651 "meter with jump not support");
3653 return rte_flow_error_set(error, ENOTSUP,
3654 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3656 "meter action not supported");
3657 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3659 return rte_flow_error_set(error, EINVAL,
3660 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3662 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3663 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3664 (!fm->attr.egress && !attr->egress && attr->ingress))))
3665 return rte_flow_error_set(error, EINVAL,
3666 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3667 "Flow attributes are either invalid "
3668 "or have a conflict with current "
3669 "meter attributes");
3674 * Validate the modify-header IPv4 DSCP actions.
3676 * @param[in] action_flags
3677 * Holds the actions detected until now.
3679 * Pointer to the modify action.
3680 * @param[in] item_flags
3681 * Holds the items detected.
3683 * Pointer to error structure.
3686 * 0 on success, a negative errno value otherwise and rte_errno is set.
3689 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3690 const struct rte_flow_action *action,
3691 const uint64_t item_flags,
3692 struct rte_flow_error *error)
3696 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3698 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3699 return rte_flow_error_set(error, EINVAL,
3700 RTE_FLOW_ERROR_TYPE_ACTION,
3702 "no ipv4 item in pattern");
3708 * Validate the modify-header IPv6 DSCP actions.
3710 * @param[in] action_flags
3711 * Holds the actions detected until now.
3713 * Pointer to the modify action.
3714 * @param[in] item_flags
3715 * Holds the items detected.
3717 * Pointer to error structure.
3720 * 0 on success, a negative errno value otherwise and rte_errno is set.
3723 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3724 const struct rte_flow_action *action,
3725 const uint64_t item_flags,
3726 struct rte_flow_error *error)
3730 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3732 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3733 return rte_flow_error_set(error, EINVAL,
3734 RTE_FLOW_ERROR_TYPE_ACTION,
3736 "no ipv6 item in pattern");
3742 * Find existing modify-header resource or create and register a new one.
3744 * @param dev[in, out]
3745 * Pointer to rte_eth_dev structure.
3746 * @param[in, out] resource
3747 * Pointer to modify-header resource.
3748 * @parm[in, out] dev_flow
3749 * Pointer to the dev_flow.
3751 * pointer to error structure.
3754 * 0 on success otherwise -errno and errno is set.
3757 flow_dv_modify_hdr_resource_register
3758 (struct rte_eth_dev *dev,
3759 struct mlx5_flow_dv_modify_hdr_resource *resource,
3760 struct mlx5_flow *dev_flow,
3761 struct rte_flow_error *error)
3763 struct mlx5_priv *priv = dev->data->dev_private;
3764 struct mlx5_ibv_shared *sh = priv->sh;
3765 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3766 struct mlx5dv_dr_domain *ns;
3767 uint32_t actions_len;
3769 resource->flags = dev_flow->dv.group ? 0 :
3770 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3771 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3773 return rte_flow_error_set(error, EOVERFLOW,
3774 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3775 "too many modify header items");
3776 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3777 ns = sh->fdb_domain;
3778 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3782 /* Lookup a matching resource from cache. */
3783 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3784 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3785 if (resource->ft_type == cache_resource->ft_type &&
3786 resource->actions_num == cache_resource->actions_num &&
3787 resource->flags == cache_resource->flags &&
3788 !memcmp((const void *)resource->actions,
3789 (const void *)cache_resource->actions,
3791 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3792 (void *)cache_resource,
3793 rte_atomic32_read(&cache_resource->refcnt));
3794 rte_atomic32_inc(&cache_resource->refcnt);
3795 dev_flow->handle->dvh.modify_hdr = cache_resource;
3799 /* Register new modify-header resource. */
3800 cache_resource = rte_calloc(__func__, 1,
3801 sizeof(*cache_resource) + actions_len, 0);
3802 if (!cache_resource)
3803 return rte_flow_error_set(error, ENOMEM,
3804 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3805 "cannot allocate resource memory");
3806 *cache_resource = *resource;
3807 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3808 cache_resource->verbs_action =
3809 mlx5_glue->dv_create_flow_action_modify_header
3810 (sh->ctx, cache_resource->ft_type, ns,
3811 cache_resource->flags, actions_len,
3812 (uint64_t *)cache_resource->actions);
3813 if (!cache_resource->verbs_action) {
3814 rte_free(cache_resource);
3815 return rte_flow_error_set(error, ENOMEM,
3816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3817 NULL, "cannot create action");
3819 rte_atomic32_init(&cache_resource->refcnt);
3820 rte_atomic32_inc(&cache_resource->refcnt);
3821 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3822 dev_flow->handle->dvh.modify_hdr = cache_resource;
3823 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3824 (void *)cache_resource,
3825 rte_atomic32_read(&cache_resource->refcnt));
3830 * Get DV flow counter by index.
3833 * Pointer to the Ethernet device structure.
3835 * mlx5 flow counter index in the container.
3837 * mlx5 flow counter pool in the container,
3840 * Pointer to the counter, NULL otherwise.
3842 static struct mlx5_flow_counter *
3843 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3845 struct mlx5_flow_counter_pool **ppool)
3847 struct mlx5_priv *priv = dev->data->dev_private;
3848 struct mlx5_pools_container *cont;
3849 struct mlx5_flow_counter_pool *pool;
3853 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3854 idx -= MLX5_CNT_BATCH_OFFSET;
3857 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3858 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3859 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3863 return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3867 * Get a pool by devx counter ID.
3870 * Pointer to the counter container.
3872 * The counter devx ID.
3875 * The counter pool pointer if exists, NULL otherwise,
3877 static struct mlx5_flow_counter_pool *
3878 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3881 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3883 for (i = 0; i < n_valid; i++) {
3884 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3885 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3886 MLX5_COUNTERS_PER_POOL;
3888 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3890 * Move the pool to the head, as counter allocate
3891 * always gets the first pool in the container.
3893 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3894 TAILQ_REMOVE(&cont->pool_list, pool, next);
3895 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3904 * Allocate a new memory for the counter values wrapped by all the needed
3908 * Pointer to the Ethernet device structure.
3910 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3913 * The new memory management pointer on success, otherwise NULL and rte_errno
3916 static struct mlx5_counter_stats_mem_mng *
3917 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3919 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3920 (dev->data->dev_private))->sh;
3921 struct mlx5_devx_mkey_attr mkey_attr;
3922 struct mlx5_counter_stats_mem_mng *mem_mng;
3923 volatile struct flow_counter_stats *raw_data;
3924 int size = (sizeof(struct flow_counter_stats) *
3925 MLX5_COUNTERS_PER_POOL +
3926 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3927 sizeof(struct mlx5_counter_stats_mem_mng);
3928 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3935 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3936 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3937 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3938 IBV_ACCESS_LOCAL_WRITE);
3939 if (!mem_mng->umem) {
3944 mkey_attr.addr = (uintptr_t)mem;
3945 mkey_attr.size = size;
3946 mkey_attr.umem_id = mem_mng->umem->umem_id;
3947 mkey_attr.pd = sh->pdn;
3948 mkey_attr.log_entity_size = 0;
3949 mkey_attr.pg_access = 0;
3950 mkey_attr.klm_array = NULL;
3951 mkey_attr.klm_num = 0;
3952 mkey_attr.relaxed_ordering = 1;
3953 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3955 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3960 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3961 raw_data = (volatile struct flow_counter_stats *)mem;
3962 for (i = 0; i < raws_n; ++i) {
3963 mem_mng->raws[i].mem_mng = mem_mng;
3964 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3966 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3971 * Resize a counter container.
3974 * Pointer to the Ethernet device structure.
3976 * Whether the pool is for counter that was allocated by batch command.
3979 * The new container pointer on success, otherwise NULL and rte_errno is set.
3981 static struct mlx5_pools_container *
3982 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3984 struct mlx5_priv *priv = dev->data->dev_private;
3985 struct mlx5_pools_container *cont =
3986 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3987 struct mlx5_pools_container *new_cont =
3988 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3989 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
3990 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3991 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3994 /* Fallback mode has no background thread. Skip the check. */
3995 if (!priv->counter_fallback &&
3996 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3997 /* The last resize still hasn't detected by the host thread. */
4001 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4002 if (!new_cont->pools) {
4007 memcpy(new_cont->pools, cont->pools, cont->n *
4008 sizeof(struct mlx5_flow_counter_pool *));
4010 * Fallback mode query the counter directly, no background query
4011 * resources are needed.
4013 if (!priv->counter_fallback) {
4014 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4015 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4017 rte_free(new_cont->pools);
4020 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4021 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4023 MLX5_CNT_CONTAINER_RESIZE +
4027 * Release the old container pools directly as no background
4028 * thread helps that.
4030 rte_free(cont->pools);
4032 new_cont->n = resize;
4033 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4034 TAILQ_INIT(&new_cont->pool_list);
4035 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4036 new_cont->init_mem_mng = mem_mng;
4038 /* Flip the master container. */
4039 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4044 * Query a devx flow counter.
4047 * Pointer to the Ethernet device structure.
4049 * Index to the flow counter.
4051 * The statistics value of packets.
4053 * The statistics value of bytes.
4056 * 0 on success, otherwise a negative errno value and rte_errno is set.
4059 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4062 struct mlx5_priv *priv = dev->data->dev_private;
4063 struct mlx5_flow_counter_pool *pool = NULL;
4064 struct mlx5_flow_counter *cnt;
4065 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4068 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4070 if (counter < MLX5_CNT_BATCH_OFFSET) {
4071 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4072 if (priv->counter_fallback)
4073 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4074 0, pkts, bytes, 0, NULL, NULL, 0);
4077 rte_spinlock_lock(&pool->sl);
4079 * The single counters allocation may allocate smaller ID than the
4080 * current allocated in parallel to the host reading.
4081 * In this case the new counter values must be reported as 0.
4083 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4087 offset = cnt - &pool->counters_raw[0];
4088 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4089 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4091 rte_spinlock_unlock(&pool->sl);
4096 * Create and initialize a new counter pool.
4099 * Pointer to the Ethernet device structure.
4101 * The devX counter handle.
4103 * Whether the pool is for counter that was allocated by batch command.
4104 * @param[in/out] cont_cur
4105 * Pointer to the container pointer, it will be update in pool resize.
4108 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4110 static struct mlx5_pools_container *
4111 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4114 struct mlx5_priv *priv = dev->data->dev_private;
4115 struct mlx5_flow_counter_pool *pool;
4116 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4118 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4121 if (cont->n == n_valid) {
4122 cont = flow_dv_container_resize(dev, batch);
4126 size = sizeof(*pool);
4128 size += MLX5_COUNTERS_PER_POOL *
4129 sizeof(struct mlx5_flow_counter_ext);
4130 pool = rte_calloc(__func__, 1, size, 0);
4135 pool->min_dcs = dcs;
4136 if (!priv->counter_fallback)
4137 pool->raw = cont->init_mem_mng->raws + n_valid %
4138 MLX5_CNT_CONTAINER_RESIZE;
4139 pool->raw_hw = NULL;
4140 rte_spinlock_init(&pool->sl);
4142 * The generation of the new allocated counters in this pool is 0, 2 in
4143 * the pool generation makes all the counters valid for allocation.
4144 * The start and end query generation protect the counters be released
4145 * between the query and update gap period will not be reallocated
4146 * without the last query finished and stats updated to the memory.
4148 rte_atomic64_set(&pool->start_query_gen, 0x2);
4150 * There's no background query thread for fallback mode, set the
4151 * end_query_gen to the maximum value since no need to wait for
4152 * statistics update.
4154 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4156 TAILQ_INIT(&pool->counters);
4157 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4158 pool->index = n_valid;
4159 cont->pools[n_valid] = pool;
4160 /* Pool initialization must be updated before host thread access. */
4162 rte_atomic16_add(&cont->n_valid, 1);
4167 * Prepare a new counter and/or a new counter pool.
4170 * Pointer to the Ethernet device structure.
4171 * @param[out] cnt_free
4172 * Where to put the pointer of a new counter.
4174 * Whether the pool is for counter that was allocated by batch command.
4177 * The counter container pointer and @p cnt_free is set on success,
4178 * NULL otherwise and rte_errno is set.
4180 static struct mlx5_pools_container *
4181 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4182 struct mlx5_flow_counter **cnt_free,
4185 struct mlx5_priv *priv = dev->data->dev_private;
4186 struct mlx5_pools_container *cont;
4187 struct mlx5_flow_counter_pool *pool;
4188 struct mlx5_devx_obj *dcs = NULL;
4189 struct mlx5_flow_counter *cnt;
4192 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4194 /* bulk_bitmap must be 0 for single counter allocation. */
4195 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4198 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4200 cont = flow_dv_pool_create(dev, dcs, batch);
4202 mlx5_devx_cmd_destroy(dcs);
4205 pool = TAILQ_FIRST(&cont->pool_list);
4206 } else if (dcs->id < pool->min_dcs->id) {
4207 rte_atomic64_set(&pool->a64_dcs,
4208 (int64_t)(uintptr_t)dcs);
4210 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4211 cnt = &pool->counters_raw[i];
4212 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4213 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4217 /* bulk_bitmap is in 128 counters units. */
4218 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4219 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4221 rte_errno = ENODATA;
4224 cont = flow_dv_pool_create(dev, dcs, batch);
4226 mlx5_devx_cmd_destroy(dcs);
4229 pool = TAILQ_FIRST(&cont->pool_list);
4230 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4231 cnt = &pool->counters_raw[i];
4232 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4234 *cnt_free = &pool->counters_raw[0];
4239 * Search for existed shared counter.
4242 * Pointer to the relevant counter pool container.
4244 * The shared counter ID to search.
4246 * mlx5 flow counter pool in the container,
4249 * NULL if not existed, otherwise pointer to the shared extend counter.
4251 static struct mlx5_flow_counter_ext *
4252 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4253 struct mlx5_flow_counter_pool **ppool)
4255 static struct mlx5_flow_counter_ext *cnt;
4256 struct mlx5_flow_counter_pool *pool;
4258 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4260 for (i = 0; i < n_valid; i++) {
4261 pool = cont->pools[i];
4262 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4263 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4264 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4266 *ppool = cont->pools[i];
4275 * Allocate a flow counter.
4278 * Pointer to the Ethernet device structure.
4280 * Indicate if this counter is shared with other flows.
4282 * Counter identifier.
4284 * Counter flow group.
4287 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4290 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4293 struct mlx5_priv *priv = dev->data->dev_private;
4294 struct mlx5_flow_counter_pool *pool = NULL;
4295 struct mlx5_flow_counter *cnt_free = NULL;
4296 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4298 * Currently group 0 flow counter cannot be assigned to a flow if it is
4299 * not the first one in the batch counter allocation, so it is better
4300 * to allocate counters one by one for these flows in a separate
4302 * A counter can be shared between different groups so need to take
4303 * shared counters from the single container.
4305 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4306 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4310 if (!priv->config.devx) {
4311 rte_errno = ENOTSUP;
4315 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4317 if (cnt_ext->ref_cnt + 1 == 0) {
4322 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4323 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4328 /* Pools which has a free counters are in the start. */
4329 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4331 * The free counter reset values must be updated between the
4332 * counter release to the counter allocation, so, at least one
4333 * query must be done in this time. ensure it by saving the
4334 * query generation in the release time.
4335 * The free list is sorted according to the generation - so if
4336 * the first one is not updated, all the others are not
4339 cnt_free = TAILQ_FIRST(&pool->counters);
4340 if (cnt_free && cnt_free->query_gen <
4341 rte_atomic64_read(&pool->end_query_gen))
4346 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4349 pool = TAILQ_FIRST(&cont->pool_list);
4352 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4353 /* Create a DV counter action only in the first time usage. */
4354 if (!cnt_free->action) {
4356 struct mlx5_devx_obj *dcs;
4359 offset = cnt_free - &pool->counters_raw[0];
4360 dcs = pool->min_dcs;
4365 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4367 if (!cnt_free->action) {
4372 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4373 (cnt_free - pool->counters_raw));
4374 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4375 /* Update the counter reset values. */
4376 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4380 cnt_ext->shared = shared;
4381 cnt_ext->ref_cnt = 1;
4384 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4385 /* Start the asynchronous batch query by the host thread. */
4386 mlx5_set_query_alarm(priv->sh);
4387 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4388 if (TAILQ_EMPTY(&pool->counters)) {
4389 /* Move the pool to the end of the container pool list. */
4390 TAILQ_REMOVE(&cont->pool_list, pool, next);
4391 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4397 * Release a flow counter.
4400 * Pointer to the Ethernet device structure.
4401 * @param[in] counter
4402 * Index to the counter handler.
4405 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4407 struct mlx5_flow_counter_pool *pool = NULL;
4408 struct mlx5_flow_counter *cnt;
4409 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4413 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4415 if (counter < MLX5_CNT_BATCH_OFFSET) {
4416 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4417 if (cnt_ext && --cnt_ext->ref_cnt)
4420 /* Put the counter in the end - the last updated one. */
4421 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4423 * Counters released between query trigger and handler need
4424 * to wait the next round of query. Since the packets arrive
4425 * in the gap period will not be taken into account to the
4428 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4432 * Verify the @p attributes will be correctly understood by the NIC and store
4433 * them in the @p flow if everything is correct.
4436 * Pointer to dev struct.
4437 * @param[in] attributes
4438 * Pointer to flow attributes
4439 * @param[in] external
4440 * This flow rule is created by request external to PMD.
4442 * Pointer to error structure.
4445 * 0 on success, a negative errno value otherwise and rte_errno is set.
4448 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4449 const struct rte_flow_attr *attributes,
4450 bool external __rte_unused,
4451 struct rte_flow_error *error)
4453 struct mlx5_priv *priv = dev->data->dev_private;
4454 uint32_t priority_max = priv->config.flow_prio - 1;
4456 #ifndef HAVE_MLX5DV_DR
4457 if (attributes->group)
4458 return rte_flow_error_set(error, ENOTSUP,
4459 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4461 "groups are not supported");
4466 ret = mlx5_flow_group_to_table(attributes, external,
4467 attributes->group, !!priv->fdb_def_rule,
4472 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4473 attributes->priority >= priority_max)
4474 return rte_flow_error_set(error, ENOTSUP,
4475 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4477 "priority out of range");
4478 if (attributes->transfer) {
4479 if (!priv->config.dv_esw_en)
4480 return rte_flow_error_set
4482 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4483 "E-Switch dr is not supported");
4484 if (!(priv->representor || priv->master))
4485 return rte_flow_error_set
4486 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4487 NULL, "E-Switch configuration can only be"
4488 " done by a master or a representor device");
4489 if (attributes->egress)
4490 return rte_flow_error_set
4492 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4493 "egress is not supported");
4495 if (!(attributes->egress ^ attributes->ingress))
4496 return rte_flow_error_set(error, ENOTSUP,
4497 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4498 "must specify exactly one of "
4499 "ingress or egress");
4504 * Internal validation function. For validating both actions and items.
4507 * Pointer to the rte_eth_dev structure.
4509 * Pointer to the flow attributes.
4511 * Pointer to the list of items.
4512 * @param[in] actions
4513 * Pointer to the list of actions.
4514 * @param[in] external
4515 * This flow rule is created by request external to PMD.
4517 * Pointer to the error structure.
4520 * 0 on success, a negative errno value otherwise and rte_errno is set.
4523 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4524 const struct rte_flow_item items[],
4525 const struct rte_flow_action actions[],
4526 bool external, struct rte_flow_error *error)
4529 uint64_t action_flags = 0;
4530 uint64_t item_flags = 0;
4531 uint64_t last_item = 0;
4532 uint8_t next_protocol = 0xff;
4533 uint16_t ether_type = 0;
4535 uint8_t item_ipv6_proto = 0;
4536 const struct rte_flow_item *gre_item = NULL;
4537 const struct rte_flow_action_raw_decap *decap;
4538 const struct rte_flow_action_raw_encap *encap;
4539 const struct rte_flow_action_rss *rss;
4540 const struct rte_flow_item_tcp nic_tcp_mask = {
4543 .src_port = RTE_BE16(UINT16_MAX),
4544 .dst_port = RTE_BE16(UINT16_MAX),
4547 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4549 .src_addr = RTE_BE32(0xffffffff),
4550 .dst_addr = RTE_BE32(0xffffffff),
4551 .type_of_service = 0xff,
4552 .next_proto_id = 0xff,
4553 .time_to_live = 0xff,
4556 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4559 "\xff\xff\xff\xff\xff\xff\xff\xff"
4560 "\xff\xff\xff\xff\xff\xff\xff\xff",
4562 "\xff\xff\xff\xff\xff\xff\xff\xff"
4563 "\xff\xff\xff\xff\xff\xff\xff\xff",
4564 .vtc_flow = RTE_BE32(0xffffffff),
4569 struct mlx5_priv *priv = dev->data->dev_private;
4570 struct mlx5_dev_config *dev_conf = &priv->config;
4571 uint16_t queue_index = 0xFFFF;
4575 ret = flow_dv_validate_attributes(dev, attr, external, error);
4578 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4579 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4580 int type = items->type;
4583 case RTE_FLOW_ITEM_TYPE_VOID:
4585 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4586 ret = flow_dv_validate_item_port_id
4587 (dev, items, attr, item_flags, error);
4590 last_item = MLX5_FLOW_ITEM_PORT_ID;
4592 case RTE_FLOW_ITEM_TYPE_ETH:
4593 ret = mlx5_flow_validate_item_eth(items, item_flags,
4597 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4598 MLX5_FLOW_LAYER_OUTER_L2;
4599 if (items->mask != NULL && items->spec != NULL) {
4601 ((const struct rte_flow_item_eth *)
4604 ((const struct rte_flow_item_eth *)
4606 ether_type = rte_be_to_cpu_16(ether_type);
4611 case RTE_FLOW_ITEM_TYPE_VLAN:
4612 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4616 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4617 MLX5_FLOW_LAYER_OUTER_VLAN;
4618 if (items->mask != NULL && items->spec != NULL) {
4620 ((const struct rte_flow_item_vlan *)
4621 items->spec)->inner_type;
4623 ((const struct rte_flow_item_vlan *)
4624 items->mask)->inner_type;
4625 ether_type = rte_be_to_cpu_16(ether_type);
4630 case RTE_FLOW_ITEM_TYPE_IPV4:
4631 mlx5_flow_tunnel_ip_check(items, next_protocol,
4632 &item_flags, &tunnel);
4633 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4640 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4641 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4642 if (items->mask != NULL &&
4643 ((const struct rte_flow_item_ipv4 *)
4644 items->mask)->hdr.next_proto_id) {
4646 ((const struct rte_flow_item_ipv4 *)
4647 (items->spec))->hdr.next_proto_id;
4649 ((const struct rte_flow_item_ipv4 *)
4650 (items->mask))->hdr.next_proto_id;
4652 /* Reset for inner layer. */
4653 next_protocol = 0xff;
4656 case RTE_FLOW_ITEM_TYPE_IPV6:
4657 mlx5_flow_tunnel_ip_check(items, next_protocol,
4658 &item_flags, &tunnel);
4659 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4666 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4667 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4668 if (items->mask != NULL &&
4669 ((const struct rte_flow_item_ipv6 *)
4670 items->mask)->hdr.proto) {
4672 ((const struct rte_flow_item_ipv6 *)
4673 items->spec)->hdr.proto;
4675 ((const struct rte_flow_item_ipv6 *)
4676 items->spec)->hdr.proto;
4678 ((const struct rte_flow_item_ipv6 *)
4679 items->mask)->hdr.proto;
4681 /* Reset for inner layer. */
4682 next_protocol = 0xff;
4685 case RTE_FLOW_ITEM_TYPE_TCP:
4686 ret = mlx5_flow_validate_item_tcp
4693 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4694 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 case RTE_FLOW_ITEM_TYPE_UDP:
4697 ret = mlx5_flow_validate_item_udp(items, item_flags,
4702 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4703 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4705 case RTE_FLOW_ITEM_TYPE_GRE:
4706 ret = mlx5_flow_validate_item_gre(items, item_flags,
4707 next_protocol, error);
4711 last_item = MLX5_FLOW_LAYER_GRE;
4713 case RTE_FLOW_ITEM_TYPE_NVGRE:
4714 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4719 last_item = MLX5_FLOW_LAYER_NVGRE;
4721 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4722 ret = mlx5_flow_validate_item_gre_key
4723 (items, item_flags, gre_item, error);
4726 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4728 case RTE_FLOW_ITEM_TYPE_VXLAN:
4729 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4733 last_item = MLX5_FLOW_LAYER_VXLAN;
4735 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4736 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4741 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4743 case RTE_FLOW_ITEM_TYPE_GENEVE:
4744 ret = mlx5_flow_validate_item_geneve(items,
4749 last_item = MLX5_FLOW_LAYER_GENEVE;
4751 case RTE_FLOW_ITEM_TYPE_MPLS:
4752 ret = mlx5_flow_validate_item_mpls(dev, items,
4757 last_item = MLX5_FLOW_LAYER_MPLS;
4760 case RTE_FLOW_ITEM_TYPE_MARK:
4761 ret = flow_dv_validate_item_mark(dev, items, attr,
4765 last_item = MLX5_FLOW_ITEM_MARK;
4767 case RTE_FLOW_ITEM_TYPE_META:
4768 ret = flow_dv_validate_item_meta(dev, items, attr,
4772 last_item = MLX5_FLOW_ITEM_METADATA;
4774 case RTE_FLOW_ITEM_TYPE_ICMP:
4775 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4780 last_item = MLX5_FLOW_LAYER_ICMP;
4782 case RTE_FLOW_ITEM_TYPE_ICMP6:
4783 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4788 item_ipv6_proto = IPPROTO_ICMPV6;
4789 last_item = MLX5_FLOW_LAYER_ICMP6;
4791 case RTE_FLOW_ITEM_TYPE_TAG:
4792 ret = flow_dv_validate_item_tag(dev, items,
4796 last_item = MLX5_FLOW_ITEM_TAG;
4798 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4799 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4801 case RTE_FLOW_ITEM_TYPE_GTP:
4802 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4806 last_item = MLX5_FLOW_LAYER_GTP;
4809 return rte_flow_error_set(error, ENOTSUP,
4810 RTE_FLOW_ERROR_TYPE_ITEM,
4811 NULL, "item not supported");
4813 item_flags |= last_item;
4815 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4816 int type = actions->type;
4817 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4818 return rte_flow_error_set(error, ENOTSUP,
4819 RTE_FLOW_ERROR_TYPE_ACTION,
4820 actions, "too many actions");
4822 case RTE_FLOW_ACTION_TYPE_VOID:
4824 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4825 ret = flow_dv_validate_action_port_id(dev,
4832 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4835 case RTE_FLOW_ACTION_TYPE_FLAG:
4836 ret = flow_dv_validate_action_flag(dev, action_flags,
4840 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4841 /* Count all modify-header actions as one. */
4842 if (!(action_flags &
4843 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4845 action_flags |= MLX5_FLOW_ACTION_FLAG |
4846 MLX5_FLOW_ACTION_MARK_EXT;
4848 action_flags |= MLX5_FLOW_ACTION_FLAG;
4852 case RTE_FLOW_ACTION_TYPE_MARK:
4853 ret = flow_dv_validate_action_mark(dev, actions,
4858 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4859 /* Count all modify-header actions as one. */
4860 if (!(action_flags &
4861 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4863 action_flags |= MLX5_FLOW_ACTION_MARK |
4864 MLX5_FLOW_ACTION_MARK_EXT;
4866 action_flags |= MLX5_FLOW_ACTION_MARK;
4870 case RTE_FLOW_ACTION_TYPE_SET_META:
4871 ret = flow_dv_validate_action_set_meta(dev, actions,
4876 /* Count all modify-header actions as one action. */
4877 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4879 action_flags |= MLX5_FLOW_ACTION_SET_META;
4881 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4882 ret = flow_dv_validate_action_set_tag(dev, actions,
4887 /* Count all modify-header actions as one action. */
4888 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4890 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4892 case RTE_FLOW_ACTION_TYPE_DROP:
4893 ret = mlx5_flow_validate_action_drop(action_flags,
4897 action_flags |= MLX5_FLOW_ACTION_DROP;
4900 case RTE_FLOW_ACTION_TYPE_QUEUE:
4901 ret = mlx5_flow_validate_action_queue(actions,
4906 queue_index = ((const struct rte_flow_action_queue *)
4907 (actions->conf))->index;
4908 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4911 case RTE_FLOW_ACTION_TYPE_RSS:
4912 rss = actions->conf;
4913 ret = mlx5_flow_validate_action_rss(actions,
4919 if (rss != NULL && rss->queue_num)
4920 queue_index = rss->queue[0];
4921 action_flags |= MLX5_FLOW_ACTION_RSS;
4924 case RTE_FLOW_ACTION_TYPE_COUNT:
4925 ret = flow_dv_validate_action_count(dev, error);
4928 action_flags |= MLX5_FLOW_ACTION_COUNT;
4931 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4932 if (flow_dv_validate_action_pop_vlan(dev,
4938 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4941 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4942 ret = flow_dv_validate_action_push_vlan(dev,
4949 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4952 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4953 ret = flow_dv_validate_action_set_vlan_pcp
4954 (action_flags, actions, error);
4957 /* Count PCP with push_vlan command. */
4958 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4960 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4961 ret = flow_dv_validate_action_set_vlan_vid
4962 (item_flags, action_flags,
4966 /* Count VID with push_vlan command. */
4967 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4969 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4970 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4971 ret = flow_dv_validate_action_l2_encap(dev,
4977 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4980 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4981 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4982 ret = flow_dv_validate_action_decap(dev, action_flags,
4986 action_flags |= MLX5_FLOW_ACTION_DECAP;
4989 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4990 ret = flow_dv_validate_action_raw_encap_decap
4991 (dev, NULL, actions->conf, attr, &action_flags,
4996 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4997 decap = actions->conf;
4998 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5000 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5004 encap = actions->conf;
5006 ret = flow_dv_validate_action_raw_encap_decap
5008 decap ? decap : &empty_decap, encap,
5009 attr, &action_flags, &actions_n,
5014 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5015 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5016 ret = flow_dv_validate_action_modify_mac(action_flags,
5022 /* Count all modify-header actions as one action. */
5023 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5025 action_flags |= actions->type ==
5026 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5027 MLX5_FLOW_ACTION_SET_MAC_SRC :
5028 MLX5_FLOW_ACTION_SET_MAC_DST;
5031 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5032 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5033 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5039 /* Count all modify-header actions as one action. */
5040 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5042 action_flags |= actions->type ==
5043 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5044 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5045 MLX5_FLOW_ACTION_SET_IPV4_DST;
5047 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5048 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5049 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5055 if (item_ipv6_proto == IPPROTO_ICMPV6)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION,
5059 "Can't change header "
5060 "with ICMPv6 proto");
5061 /* Count all modify-header actions as one action. */
5062 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5064 action_flags |= actions->type ==
5065 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5066 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5067 MLX5_FLOW_ACTION_SET_IPV6_DST;
5069 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5070 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5071 ret = flow_dv_validate_action_modify_tp(action_flags,
5077 /* Count all modify-header actions as one action. */
5078 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5080 action_flags |= actions->type ==
5081 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5082 MLX5_FLOW_ACTION_SET_TP_SRC :
5083 MLX5_FLOW_ACTION_SET_TP_DST;
5085 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5086 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5087 ret = flow_dv_validate_action_modify_ttl(action_flags,
5093 /* Count all modify-header actions as one action. */
5094 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5096 action_flags |= actions->type ==
5097 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5098 MLX5_FLOW_ACTION_SET_TTL :
5099 MLX5_FLOW_ACTION_DEC_TTL;
5101 case RTE_FLOW_ACTION_TYPE_JUMP:
5102 ret = flow_dv_validate_action_jump(actions,
5109 action_flags |= MLX5_FLOW_ACTION_JUMP;
5111 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5112 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5113 ret = flow_dv_validate_action_modify_tcp_seq
5120 /* Count all modify-header actions as one action. */
5121 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5123 action_flags |= actions->type ==
5124 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5125 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5126 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5128 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5129 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5130 ret = flow_dv_validate_action_modify_tcp_ack
5137 /* Count all modify-header actions as one action. */
5138 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5140 action_flags |= actions->type ==
5141 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5142 MLX5_FLOW_ACTION_INC_TCP_ACK :
5143 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5145 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5146 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5147 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5149 case RTE_FLOW_ACTION_TYPE_METER:
5150 ret = mlx5_flow_validate_action_meter(dev,
5156 action_flags |= MLX5_FLOW_ACTION_METER;
5159 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5160 ret = flow_dv_validate_action_modify_ipv4_dscp
5167 /* Count all modify-header actions as one action. */
5168 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5170 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5172 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5173 ret = flow_dv_validate_action_modify_ipv6_dscp
5180 /* Count all modify-header actions as one action. */
5181 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5183 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5186 return rte_flow_error_set(error, ENOTSUP,
5187 RTE_FLOW_ERROR_TYPE_ACTION,
5189 "action not supported");
5193 * Validate the drop action mutual exclusion with other actions.
5194 * Drop action is mutually-exclusive with any other action, except for
5197 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5198 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5199 return rte_flow_error_set(error, EINVAL,
5200 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5201 "Drop action is mutually-exclusive "
5202 "with any other action, except for "
5204 /* Eswitch has few restrictions on using items and actions */
5205 if (attr->transfer) {
5206 if (!mlx5_flow_ext_mreg_supported(dev) &&
5207 action_flags & MLX5_FLOW_ACTION_FLAG)
5208 return rte_flow_error_set(error, ENOTSUP,
5209 RTE_FLOW_ERROR_TYPE_ACTION,
5211 "unsupported action FLAG");
5212 if (!mlx5_flow_ext_mreg_supported(dev) &&
5213 action_flags & MLX5_FLOW_ACTION_MARK)
5214 return rte_flow_error_set(error, ENOTSUP,
5215 RTE_FLOW_ERROR_TYPE_ACTION,
5217 "unsupported action MARK");
5218 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5219 return rte_flow_error_set(error, ENOTSUP,
5220 RTE_FLOW_ERROR_TYPE_ACTION,
5222 "unsupported action QUEUE");
5223 if (action_flags & MLX5_FLOW_ACTION_RSS)
5224 return rte_flow_error_set(error, ENOTSUP,
5225 RTE_FLOW_ERROR_TYPE_ACTION,
5227 "unsupported action RSS");
5228 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5229 return rte_flow_error_set(error, EINVAL,
5230 RTE_FLOW_ERROR_TYPE_ACTION,
5232 "no fate action is found");
5234 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5235 return rte_flow_error_set(error, EINVAL,
5236 RTE_FLOW_ERROR_TYPE_ACTION,
5238 "no fate action is found");
5240 /* Continue validation for Xcap actions.*/
5241 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5242 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5243 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5244 MLX5_FLOW_XCAP_ACTIONS)
5245 return rte_flow_error_set(error, ENOTSUP,
5246 RTE_FLOW_ERROR_TYPE_ACTION,
5247 NULL, "encap and decap "
5248 "combination aren't supported");
5249 if (!attr->transfer && attr->ingress && (action_flags &
5250 MLX5_FLOW_ACTION_ENCAP))
5251 return rte_flow_error_set(error, ENOTSUP,
5252 RTE_FLOW_ERROR_TYPE_ACTION,
5253 NULL, "encap is not supported"
5254 " for ingress traffic");
5260 * Internal preparation function. Allocates the DV flow size,
5261 * this size is constant.
5264 * Pointer to the rte_eth_dev structure.
5266 * Pointer to the flow attributes.
5268 * Pointer to the list of items.
5269 * @param[in] actions
5270 * Pointer to the list of actions.
5272 * Pointer to the error structure.
5275 * Pointer to mlx5_flow object on success,
5276 * otherwise NULL and rte_errno is set.
5278 static struct mlx5_flow *
5279 flow_dv_prepare(struct rte_eth_dev *dev,
5280 const struct rte_flow_attr *attr __rte_unused,
5281 const struct rte_flow_item items[] __rte_unused,
5282 const struct rte_flow_action actions[] __rte_unused,
5283 struct rte_flow_error *error)
5285 size_t size = sizeof(struct mlx5_flow_handle);
5286 struct mlx5_flow *dev_flow;
5287 struct mlx5_flow_handle *dev_handle;
5288 struct mlx5_priv *priv = dev->data->dev_private;
5290 /* In case of corrupting the memory. */
5291 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5292 rte_flow_error_set(error, ENOSPC,
5293 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5294 "not free temporary device flow");
5297 dev_handle = rte_calloc(__func__, 1, size, 0);
5299 rte_flow_error_set(error, ENOMEM,
5300 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5301 "not enough memory to create flow handle");
5304 /* No multi-thread supporting. */
5305 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5306 dev_flow->handle = dev_handle;
5307 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5309 * The matching value needs to be cleared to 0 before using. In the
5310 * past, it will be automatically cleared when using rte_*alloc
5311 * API. The time consumption will be almost the same as before.
5313 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5314 dev_flow->ingress = attr->ingress;
5315 dev_flow->dv.transfer = attr->transfer;
5319 #ifdef RTE_LIBRTE_MLX5_DEBUG
5321 * Sanity check for match mask and value. Similar to check_valid_spec() in
5322 * kernel driver. If unmasked bit is present in value, it returns failure.
5325 * pointer to match mask buffer.
5326 * @param match_value
5327 * pointer to match value buffer.
5330 * 0 if valid, -EINVAL otherwise.
5333 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5335 uint8_t *m = match_mask;
5336 uint8_t *v = match_value;
5339 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5342 "match_value differs from match_criteria"
5343 " %p[%u] != %p[%u]",
5344 match_value, i, match_mask, i);
5353 * Add Ethernet item to matcher and to the value.
5355 * @param[in, out] matcher
5357 * @param[in, out] key
5358 * Flow matcher value.
5360 * Flow pattern to translate.
5362 * Item is inner pattern.
5365 flow_dv_translate_item_eth(void *matcher, void *key,
5366 const struct rte_flow_item *item, int inner)
5368 const struct rte_flow_item_eth *eth_m = item->mask;
5369 const struct rte_flow_item_eth *eth_v = item->spec;
5370 const struct rte_flow_item_eth nic_mask = {
5371 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5372 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5373 .type = RTE_BE16(0xffff),
5385 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5387 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5389 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5391 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5393 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5394 ð_m->dst, sizeof(eth_m->dst));
5395 /* The value must be in the range of the mask. */
5396 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5397 for (i = 0; i < sizeof(eth_m->dst); ++i)
5398 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5399 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5400 ð_m->src, sizeof(eth_m->src));
5401 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5402 /* The value must be in the range of the mask. */
5403 for (i = 0; i < sizeof(eth_m->dst); ++i)
5404 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5406 /* When ethertype is present set mask for tagged VLAN. */
5407 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5408 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5409 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5410 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5413 /* Return here to avoid setting match on ethertype. */
5418 * HW supports match on one Ethertype, the Ethertype following the last
5419 * VLAN tag of the packet (see PRM).
5420 * Set match on ethertype only if ETH header is not followed by VLAN.
5422 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5423 rte_be_to_cpu_16(eth_m->type));
5424 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5425 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5429 * Add VLAN item to matcher and to the value.
5431 * @param[in, out] dev_flow
5433 * @param[in, out] matcher
5435 * @param[in, out] key
5436 * Flow matcher value.
5438 * Flow pattern to translate.
5440 * Item is inner pattern.
5443 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5444 void *matcher, void *key,
5445 const struct rte_flow_item *item,
5448 const struct rte_flow_item_vlan *vlan_m = item->mask;
5449 const struct rte_flow_item_vlan *vlan_v = item->spec;
5458 vlan_m = &rte_flow_item_vlan_mask;
5460 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5462 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5464 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5466 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5468 * This is workaround, masks are not supported,
5469 * and pre-validated.
5471 dev_flow->handle->vf_vlan.tag =
5472 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5474 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5475 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5476 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5477 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5478 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5480 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5481 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5482 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5483 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5484 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5485 rte_be_to_cpu_16(vlan_m->inner_type));
5486 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5487 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5491 * Add IPV4 item to matcher and to the value.
5493 * @param[in, out] matcher
5495 * @param[in, out] key
5496 * Flow matcher value.
5498 * Flow pattern to translate.
5499 * @param[in] item_flags
5500 * Bit-fields that holds the items detected until now.
5502 * Item is inner pattern.
5504 * The group to insert the rule.
5507 flow_dv_translate_item_ipv4(void *matcher, void *key,
5508 const struct rte_flow_item *item,
5509 const uint64_t item_flags,
5510 int inner, uint32_t group)
5512 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5513 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5514 const struct rte_flow_item_ipv4 nic_mask = {
5516 .src_addr = RTE_BE32(0xffffffff),
5517 .dst_addr = RTE_BE32(0xffffffff),
5518 .type_of_service = 0xff,
5519 .next_proto_id = 0xff,
5520 .time_to_live = 0xff,
5530 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5532 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5534 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5536 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5539 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5544 * On outer header (which must contains L2), or inner header with L2,
5545 * set cvlan_tag mask bit to mark this packet as untagged.
5546 * This should be done even if item->spec is empty.
5548 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5549 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5554 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5555 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5556 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5557 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5558 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5559 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5560 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5561 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5562 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5563 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5564 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5565 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5566 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5568 ipv4_m->hdr.type_of_service);
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5570 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5571 ipv4_m->hdr.type_of_service >> 2);
5572 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5573 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5574 ipv4_m->hdr.next_proto_id);
5575 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5576 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5577 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5578 ipv4_m->hdr.time_to_live);
5579 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5580 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5584 * Add IPV6 item to matcher and to the value.
5586 * @param[in, out] matcher
5588 * @param[in, out] key
5589 * Flow matcher value.
5591 * Flow pattern to translate.
5592 * @param[in] item_flags
5593 * Bit-fields that holds the items detected until now.
5595 * Item is inner pattern.
5597 * The group to insert the rule.
5600 flow_dv_translate_item_ipv6(void *matcher, void *key,
5601 const struct rte_flow_item *item,
5602 const uint64_t item_flags,
5603 int inner, uint32_t group)
5605 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5606 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5607 const struct rte_flow_item_ipv6 nic_mask = {
5610 "\xff\xff\xff\xff\xff\xff\xff\xff"
5611 "\xff\xff\xff\xff\xff\xff\xff\xff",
5613 "\xff\xff\xff\xff\xff\xff\xff\xff"
5614 "\xff\xff\xff\xff\xff\xff\xff\xff",
5615 .vtc_flow = RTE_BE32(0xffffffff),
5622 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5623 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5632 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5634 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5636 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5638 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5643 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5644 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5646 * On outer header (which must contains L2), or inner header with L2,
5647 * set cvlan_tag mask bit to mark this packet as untagged.
5648 * This should be done even if item->spec is empty.
5650 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5651 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5656 size = sizeof(ipv6_m->hdr.dst_addr);
5657 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5658 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5659 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5660 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5661 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5662 for (i = 0; i < size; ++i)
5663 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5664 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5665 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5666 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5667 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5668 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5669 for (i = 0; i < size; ++i)
5670 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5672 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5673 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5674 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5675 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5676 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5677 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5680 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5682 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5685 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5687 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5691 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5693 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5694 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5696 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5697 ipv6_m->hdr.hop_limits);
5698 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5699 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5703 * Add TCP item to matcher and to the value.
5705 * @param[in, out] matcher
5707 * @param[in, out] key
5708 * Flow matcher value.
5710 * Flow pattern to translate.
5712 * Item is inner pattern.
5715 flow_dv_translate_item_tcp(void *matcher, void *key,
5716 const struct rte_flow_item *item,
5719 const struct rte_flow_item_tcp *tcp_m = item->mask;
5720 const struct rte_flow_item_tcp *tcp_v = item->spec;
5725 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5727 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5729 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5731 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5734 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5738 tcp_m = &rte_flow_item_tcp_mask;
5739 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5740 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5742 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5743 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5744 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5745 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5746 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5747 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5748 tcp_m->hdr.tcp_flags);
5749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5750 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5754 * Add UDP item to matcher and to the value.
5756 * @param[in, out] matcher
5758 * @param[in, out] key
5759 * Flow matcher value.
5761 * Flow pattern to translate.
5763 * Item is inner pattern.
5766 flow_dv_translate_item_udp(void *matcher, void *key,
5767 const struct rte_flow_item *item,
5770 const struct rte_flow_item_udp *udp_m = item->mask;
5771 const struct rte_flow_item_udp *udp_v = item->spec;
5776 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5778 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5780 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5782 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5785 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5789 udp_m = &rte_flow_item_udp_mask;
5790 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5791 rte_be_to_cpu_16(udp_m->hdr.src_port));
5792 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5793 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5794 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5795 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5796 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5797 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5801 * Add GRE optional Key item to matcher and to the value.
5803 * @param[in, out] matcher
5805 * @param[in, out] key
5806 * Flow matcher value.
5808 * Flow pattern to translate.
5810 * Item is inner pattern.
5813 flow_dv_translate_item_gre_key(void *matcher, void *key,
5814 const struct rte_flow_item *item)
5816 const rte_be32_t *key_m = item->mask;
5817 const rte_be32_t *key_v = item->spec;
5818 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5819 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5820 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5822 /* GRE K bit must be on and should already be validated */
5823 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5824 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5828 key_m = &gre_key_default_mask;
5829 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5830 rte_be_to_cpu_32(*key_m) >> 8);
5831 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5832 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5833 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5834 rte_be_to_cpu_32(*key_m) & 0xFF);
5835 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5836 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5840 * Add GRE item to matcher and to the value.
5842 * @param[in, out] matcher
5844 * @param[in, out] key
5845 * Flow matcher value.
5847 * Flow pattern to translate.
5849 * Item is inner pattern.
5852 flow_dv_translate_item_gre(void *matcher, void *key,
5853 const struct rte_flow_item *item,
5856 const struct rte_flow_item_gre *gre_m = item->mask;
5857 const struct rte_flow_item_gre *gre_v = item->spec;
5860 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5861 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5868 uint16_t s_present:1;
5869 uint16_t k_present:1;
5870 uint16_t rsvd_bit1:1;
5871 uint16_t c_present:1;
5875 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5878 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5880 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5882 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5884 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5886 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5887 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5891 gre_m = &rte_flow_item_gre_mask;
5892 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5893 rte_be_to_cpu_16(gre_m->protocol));
5894 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5895 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5896 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5897 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5898 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5899 gre_crks_rsvd0_ver_m.c_present);
5900 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5901 gre_crks_rsvd0_ver_v.c_present &
5902 gre_crks_rsvd0_ver_m.c_present);
5903 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5904 gre_crks_rsvd0_ver_m.k_present);
5905 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5906 gre_crks_rsvd0_ver_v.k_present &
5907 gre_crks_rsvd0_ver_m.k_present);
5908 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5909 gre_crks_rsvd0_ver_m.s_present);
5910 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5911 gre_crks_rsvd0_ver_v.s_present &
5912 gre_crks_rsvd0_ver_m.s_present);
5916 * Add NVGRE item to matcher and to the value.
5918 * @param[in, out] matcher
5920 * @param[in, out] key
5921 * Flow matcher value.
5923 * Flow pattern to translate.
5925 * Item is inner pattern.
5928 flow_dv_translate_item_nvgre(void *matcher, void *key,
5929 const struct rte_flow_item *item,
5932 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5933 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5934 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5935 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5936 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5937 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5943 /* For NVGRE, GRE header fields must be set with defined values. */
5944 const struct rte_flow_item_gre gre_spec = {
5945 .c_rsvd0_ver = RTE_BE16(0x2000),
5946 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5948 const struct rte_flow_item_gre gre_mask = {
5949 .c_rsvd0_ver = RTE_BE16(0xB000),
5950 .protocol = RTE_BE16(UINT16_MAX),
5952 const struct rte_flow_item gre_item = {
5957 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5961 nvgre_m = &rte_flow_item_nvgre_mask;
5962 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5963 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5964 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5965 memcpy(gre_key_m, tni_flow_id_m, size);
5966 for (i = 0; i < size; ++i)
5967 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5971 * Add VXLAN item to matcher and to the value.
5973 * @param[in, out] matcher
5975 * @param[in, out] key
5976 * Flow matcher value.
5978 * Flow pattern to translate.
5980 * Item is inner pattern.
5983 flow_dv_translate_item_vxlan(void *matcher, void *key,
5984 const struct rte_flow_item *item,
5987 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5988 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5991 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5992 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6000 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6002 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6004 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6006 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6008 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6009 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6010 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6011 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6012 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6017 vxlan_m = &rte_flow_item_vxlan_mask;
6018 size = sizeof(vxlan_m->vni);
6019 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6020 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6021 memcpy(vni_m, vxlan_m->vni, size);
6022 for (i = 0; i < size; ++i)
6023 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6027 * Add VXLAN-GPE item to matcher and to the value.
6029 * @param[in, out] matcher
6031 * @param[in, out] key
6032 * Flow matcher value.
6034 * Flow pattern to translate.
6036 * Item is inner pattern.
6040 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6041 const struct rte_flow_item *item, int inner)
6043 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6044 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6048 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6050 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6056 uint8_t flags_m = 0xff;
6057 uint8_t flags_v = 0xc;
6060 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6062 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6064 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6066 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6068 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6069 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6070 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6071 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6072 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6077 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6078 size = sizeof(vxlan_m->vni);
6079 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6080 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6081 memcpy(vni_m, vxlan_m->vni, size);
6082 for (i = 0; i < size; ++i)
6083 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6084 if (vxlan_m->flags) {
6085 flags_m = vxlan_m->flags;
6086 flags_v = vxlan_v->flags;
6088 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6089 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6090 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6092 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6097 * Add Geneve item to matcher and to the value.
6099 * @param[in, out] matcher
6101 * @param[in, out] key
6102 * Flow matcher value.
6104 * Flow pattern to translate.
6106 * Item is inner pattern.
6110 flow_dv_translate_item_geneve(void *matcher, void *key,
6111 const struct rte_flow_item *item, int inner)
6113 const struct rte_flow_item_geneve *geneve_m = item->mask;
6114 const struct rte_flow_item_geneve *geneve_v = item->spec;
6117 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6118 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6127 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6129 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6131 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6133 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6135 dport = MLX5_UDP_PORT_GENEVE;
6136 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6137 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6143 geneve_m = &rte_flow_item_geneve_mask;
6144 size = sizeof(geneve_m->vni);
6145 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6146 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6147 memcpy(vni_m, geneve_m->vni, size);
6148 for (i = 0; i < size; ++i)
6149 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6150 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6151 rte_be_to_cpu_16(geneve_m->protocol));
6152 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6153 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6154 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6155 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6156 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6157 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6158 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6159 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6160 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6161 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6162 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6163 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6164 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6168 * Add MPLS item to matcher and to the value.
6170 * @param[in, out] matcher
6172 * @param[in, out] key
6173 * Flow matcher value.
6175 * Flow pattern to translate.
6176 * @param[in] prev_layer
6177 * The protocol layer indicated in previous item.
6179 * Item is inner pattern.
6182 flow_dv_translate_item_mpls(void *matcher, void *key,
6183 const struct rte_flow_item *item,
6184 uint64_t prev_layer,
6187 const uint32_t *in_mpls_m = item->mask;
6188 const uint32_t *in_mpls_v = item->spec;
6189 uint32_t *out_mpls_m = 0;
6190 uint32_t *out_mpls_v = 0;
6191 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6192 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6193 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6195 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6196 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6197 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6199 switch (prev_layer) {
6200 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6201 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6202 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6203 MLX5_UDP_PORT_MPLS);
6205 case MLX5_FLOW_LAYER_GRE:
6206 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6207 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6208 RTE_ETHER_TYPE_MPLS);
6211 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6212 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6219 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6220 switch (prev_layer) {
6221 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6223 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6224 outer_first_mpls_over_udp);
6226 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6227 outer_first_mpls_over_udp);
6229 case MLX5_FLOW_LAYER_GRE:
6231 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6232 outer_first_mpls_over_gre);
6234 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6235 outer_first_mpls_over_gre);
6238 /* Inner MPLS not over GRE is not supported. */
6241 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6245 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6251 if (out_mpls_m && out_mpls_v) {
6252 *out_mpls_m = *in_mpls_m;
6253 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6258 * Add metadata register item to matcher
6260 * @param[in, out] matcher
6262 * @param[in, out] key
6263 * Flow matcher value.
6264 * @param[in] reg_type
6265 * Type of device metadata register
6272 flow_dv_match_meta_reg(void *matcher, void *key,
6273 enum modify_reg reg_type,
6274 uint32_t data, uint32_t mask)
6277 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6279 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6285 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6286 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6289 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6290 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6294 * The metadata register C0 field might be divided into
6295 * source vport index and META item value, we should set
6296 * this field according to specified mask, not as whole one.
6298 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6300 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6301 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6304 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6307 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6308 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6311 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6312 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6315 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6316 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6319 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6320 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6323 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6324 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6327 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6328 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6331 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6332 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6341 * Add MARK item to matcher
6344 * The device to configure through.
6345 * @param[in, out] matcher
6347 * @param[in, out] key
6348 * Flow matcher value.
6350 * Flow pattern to translate.
6353 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6354 void *matcher, void *key,
6355 const struct rte_flow_item *item)
6357 struct mlx5_priv *priv = dev->data->dev_private;
6358 const struct rte_flow_item_mark *mark;
6362 mark = item->mask ? (const void *)item->mask :
6363 &rte_flow_item_mark_mask;
6364 mask = mark->id & priv->sh->dv_mark_mask;
6365 mark = (const void *)item->spec;
6367 value = mark->id & priv->sh->dv_mark_mask & mask;
6369 enum modify_reg reg;
6371 /* Get the metadata register index for the mark. */
6372 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6373 MLX5_ASSERT(reg > 0);
6374 if (reg == REG_C_0) {
6375 struct mlx5_priv *priv = dev->data->dev_private;
6376 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6377 uint32_t shl_c0 = rte_bsf32(msk_c0);
6383 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6388 * Add META item to matcher
6391 * The devich to configure through.
6392 * @param[in, out] matcher
6394 * @param[in, out] key
6395 * Flow matcher value.
6397 * Attributes of flow that includes this item.
6399 * Flow pattern to translate.
6402 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6403 void *matcher, void *key,
6404 const struct rte_flow_attr *attr,
6405 const struct rte_flow_item *item)
6407 const struct rte_flow_item_meta *meta_m;
6408 const struct rte_flow_item_meta *meta_v;
6410 meta_m = (const void *)item->mask;
6412 meta_m = &rte_flow_item_meta_mask;
6413 meta_v = (const void *)item->spec;
6416 uint32_t value = meta_v->data;
6417 uint32_t mask = meta_m->data;
6419 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6423 * In datapath code there is no endianness
6424 * coversions for perfromance reasons, all
6425 * pattern conversions are done in rte_flow.
6427 value = rte_cpu_to_be_32(value);
6428 mask = rte_cpu_to_be_32(mask);
6429 if (reg == REG_C_0) {
6430 struct mlx5_priv *priv = dev->data->dev_private;
6431 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6432 uint32_t shl_c0 = rte_bsf32(msk_c0);
6433 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6434 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6441 MLX5_ASSERT(msk_c0);
6442 MLX5_ASSERT(!(~msk_c0 & mask));
6444 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6449 * Add vport metadata Reg C0 item to matcher
6451 * @param[in, out] matcher
6453 * @param[in, out] key
6454 * Flow matcher value.
6456 * Flow pattern to translate.
6459 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6460 uint32_t value, uint32_t mask)
6462 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6466 * Add tag item to matcher
6469 * The devich to configure through.
6470 * @param[in, out] matcher
6472 * @param[in, out] key
6473 * Flow matcher value.
6475 * Flow pattern to translate.
6478 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6479 void *matcher, void *key,
6480 const struct rte_flow_item *item)
6482 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6483 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6484 uint32_t mask, value;
6487 value = tag_v->data;
6488 mask = tag_m ? tag_m->data : UINT32_MAX;
6489 if (tag_v->id == REG_C_0) {
6490 struct mlx5_priv *priv = dev->data->dev_private;
6491 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6492 uint32_t shl_c0 = rte_bsf32(msk_c0);
6498 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6502 * Add TAG item to matcher
6505 * The devich to configure through.
6506 * @param[in, out] matcher
6508 * @param[in, out] key
6509 * Flow matcher value.
6511 * Flow pattern to translate.
6514 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6515 void *matcher, void *key,
6516 const struct rte_flow_item *item)
6518 const struct rte_flow_item_tag *tag_v = item->spec;
6519 const struct rte_flow_item_tag *tag_m = item->mask;
6520 enum modify_reg reg;
6523 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6524 /* Get the metadata register index for the tag. */
6525 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6526 MLX5_ASSERT(reg > 0);
6527 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6531 * Add source vport match to the specified matcher.
6533 * @param[in, out] matcher
6535 * @param[in, out] key
6536 * Flow matcher value.
6538 * Source vport value to match
6543 flow_dv_translate_item_source_vport(void *matcher, void *key,
6544 int16_t port, uint16_t mask)
6546 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6547 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6549 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6550 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6554 * Translate port-id item to eswitch match on port-id.
6557 * The devich to configure through.
6558 * @param[in, out] matcher
6560 * @param[in, out] key
6561 * Flow matcher value.
6563 * Flow pattern to translate.
6566 * 0 on success, a negative errno value otherwise.
6569 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6570 void *key, const struct rte_flow_item *item)
6572 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6573 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6574 struct mlx5_priv *priv;
6577 mask = pid_m ? pid_m->id : 0xffff;
6578 id = pid_v ? pid_v->id : dev->data->port_id;
6579 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6582 /* Translate to vport field or to metadata, depending on mode. */
6583 if (priv->vport_meta_mask)
6584 flow_dv_translate_item_meta_vport(matcher, key,
6585 priv->vport_meta_tag,
6586 priv->vport_meta_mask);
6588 flow_dv_translate_item_source_vport(matcher, key,
6589 priv->vport_id, mask);
6594 * Add ICMP6 item to matcher and to the value.
6596 * @param[in, out] matcher
6598 * @param[in, out] key
6599 * Flow matcher value.
6601 * Flow pattern to translate.
6603 * Item is inner pattern.
6606 flow_dv_translate_item_icmp6(void *matcher, void *key,
6607 const struct rte_flow_item *item,
6610 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6611 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6614 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6616 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6618 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6620 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6622 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6624 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6626 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6627 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6631 icmp6_m = &rte_flow_item_icmp6_mask;
6633 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6634 * If only the protocol is specified, no need to match the frag.
6636 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6637 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6638 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6639 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6640 icmp6_v->type & icmp6_m->type);
6641 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6642 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6643 icmp6_v->code & icmp6_m->code);
6647 * Add ICMP item to matcher and to the value.
6649 * @param[in, out] matcher
6651 * @param[in, out] key
6652 * Flow matcher value.
6654 * Flow pattern to translate.
6656 * Item is inner pattern.
6659 flow_dv_translate_item_icmp(void *matcher, void *key,
6660 const struct rte_flow_item *item,
6663 const struct rte_flow_item_icmp *icmp_m = item->mask;
6664 const struct rte_flow_item_icmp *icmp_v = item->spec;
6667 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6669 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6671 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6673 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6675 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6677 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6684 icmp_m = &rte_flow_item_icmp_mask;
6686 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6687 * If only the protocol is specified, no need to match the frag.
6689 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6691 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6692 icmp_m->hdr.icmp_type);
6693 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6694 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6695 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6696 icmp_m->hdr.icmp_code);
6697 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6698 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6702 * Add GTP item to matcher and to the value.
6704 * @param[in, out] matcher
6706 * @param[in, out] key
6707 * Flow matcher value.
6709 * Flow pattern to translate.
6711 * Item is inner pattern.
6714 flow_dv_translate_item_gtp(void *matcher, void *key,
6715 const struct rte_flow_item *item, int inner)
6717 const struct rte_flow_item_gtp *gtp_m = item->mask;
6718 const struct rte_flow_item_gtp *gtp_v = item->spec;
6721 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6723 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6724 uint16_t dport = RTE_GTPU_UDP_PORT;
6727 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6729 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6731 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6733 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6735 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6736 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6742 gtp_m = &rte_flow_item_gtp_mask;
6743 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6744 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6745 gtp_v->msg_type & gtp_m->msg_type);
6746 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6747 rte_be_to_cpu_32(gtp_m->teid));
6748 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6749 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6752 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6754 #define HEADER_IS_ZERO(match_criteria, headers) \
6755 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6756 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6759 * Calculate flow matcher enable bitmap.
6761 * @param match_criteria
6762 * Pointer to flow matcher criteria.
6765 * Bitmap of enabled fields.
6768 flow_dv_matcher_enable(uint32_t *match_criteria)
6770 uint8_t match_criteria_enable;
6772 match_criteria_enable =
6773 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6774 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6775 match_criteria_enable |=
6776 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6777 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6778 match_criteria_enable |=
6779 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6780 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6781 match_criteria_enable |=
6782 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6783 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6784 match_criteria_enable |=
6785 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6786 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6787 return match_criteria_enable;
6794 * @param[in, out] dev
6795 * Pointer to rte_eth_dev structure.
6796 * @param[in] table_id
6799 * Direction of the table.
6800 * @param[in] transfer
6801 * E-Switch or NIC flow.
6803 * pointer to error structure.
6806 * Returns tables resource based on the index, NULL in case of failed.
6808 static struct mlx5_flow_tbl_resource *
6809 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6810 uint32_t table_id, uint8_t egress,
6812 struct rte_flow_error *error)
6814 struct mlx5_priv *priv = dev->data->dev_private;
6815 struct mlx5_ibv_shared *sh = priv->sh;
6816 struct mlx5_flow_tbl_resource *tbl;
6817 union mlx5_flow_tbl_key table_key = {
6819 .table_id = table_id,
6821 .domain = !!transfer,
6822 .direction = !!egress,
6825 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6827 struct mlx5_flow_tbl_data_entry *tbl_data;
6832 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6834 tbl = &tbl_data->tbl;
6835 rte_atomic32_inc(&tbl->refcnt);
6838 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6840 rte_flow_error_set(error, ENOMEM,
6841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6843 "cannot allocate flow table data entry");
6846 tbl = &tbl_data->tbl;
6847 pos = &tbl_data->entry;
6849 domain = sh->fdb_domain;
6851 domain = sh->tx_domain;
6853 domain = sh->rx_domain;
6854 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6856 rte_flow_error_set(error, ENOMEM,
6857 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6858 NULL, "cannot create flow table object");
6863 * No multi-threads now, but still better to initialize the reference
6864 * count before insert it into the hash list.
6866 rte_atomic32_init(&tbl->refcnt);
6867 /* Jump action reference count is initialized here. */
6868 rte_atomic32_init(&tbl_data->jump.refcnt);
6869 pos->key = table_key.v64;
6870 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6872 rte_flow_error_set(error, -ret,
6873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6874 "cannot insert flow table data entry");
6875 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6878 rte_atomic32_inc(&tbl->refcnt);
6883 * Release a flow table.
6886 * Pointer to rte_eth_dev structure.
6888 * Table resource to be released.
6891 * Returns 0 if table was released, else return 1;
6894 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6895 struct mlx5_flow_tbl_resource *tbl)
6897 struct mlx5_priv *priv = dev->data->dev_private;
6898 struct mlx5_ibv_shared *sh = priv->sh;
6899 struct mlx5_flow_tbl_data_entry *tbl_data =
6900 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6904 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6905 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6907 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6909 /* remove the entry from the hash list and free memory. */
6910 mlx5_hlist_remove(sh->flow_tbls, pos);
6918 * Register the flow matcher.
6920 * @param[in, out] dev
6921 * Pointer to rte_eth_dev structure.
6922 * @param[in, out] matcher
6923 * Pointer to flow matcher.
6924 * @param[in, out] key
6925 * Pointer to flow table key.
6926 * @parm[in, out] dev_flow
6927 * Pointer to the dev_flow.
6929 * pointer to error structure.
6932 * 0 on success otherwise -errno and errno is set.
6935 flow_dv_matcher_register(struct rte_eth_dev *dev,
6936 struct mlx5_flow_dv_matcher *matcher,
6937 union mlx5_flow_tbl_key *key,
6938 struct mlx5_flow *dev_flow,
6939 struct rte_flow_error *error)
6941 struct mlx5_priv *priv = dev->data->dev_private;
6942 struct mlx5_ibv_shared *sh = priv->sh;
6943 struct mlx5_flow_dv_matcher *cache_matcher;
6944 struct mlx5dv_flow_matcher_attr dv_attr = {
6945 .type = IBV_FLOW_ATTR_NORMAL,
6946 .match_mask = (void *)&matcher->mask,
6948 struct mlx5_flow_tbl_resource *tbl;
6949 struct mlx5_flow_tbl_data_entry *tbl_data;
6951 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6952 key->domain, error);
6954 return -rte_errno; /* No need to refill the error info */
6955 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6956 /* Lookup from cache. */
6957 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6958 if (matcher->crc == cache_matcher->crc &&
6959 matcher->priority == cache_matcher->priority &&
6960 !memcmp((const void *)matcher->mask.buf,
6961 (const void *)cache_matcher->mask.buf,
6962 cache_matcher->mask.size)) {
6964 "%s group %u priority %hd use %s "
6965 "matcher %p: refcnt %d++",
6966 key->domain ? "FDB" : "NIC", key->table_id,
6967 cache_matcher->priority,
6968 key->direction ? "tx" : "rx",
6969 (void *)cache_matcher,
6970 rte_atomic32_read(&cache_matcher->refcnt));
6971 rte_atomic32_inc(&cache_matcher->refcnt);
6972 dev_flow->handle->dvh.matcher = cache_matcher;
6973 /* old matcher should not make the table ref++. */
6974 flow_dv_tbl_resource_release(dev, tbl);
6978 /* Register new matcher. */
6979 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6980 if (!cache_matcher) {
6981 flow_dv_tbl_resource_release(dev, tbl);
6982 return rte_flow_error_set(error, ENOMEM,
6983 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6984 "cannot allocate matcher memory");
6986 *cache_matcher = *matcher;
6987 dv_attr.match_criteria_enable =
6988 flow_dv_matcher_enable(cache_matcher->mask.buf);
6989 dv_attr.priority = matcher->priority;
6991 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6992 cache_matcher->matcher_object =
6993 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6994 if (!cache_matcher->matcher_object) {
6995 rte_free(cache_matcher);
6996 #ifdef HAVE_MLX5DV_DR
6997 flow_dv_tbl_resource_release(dev, tbl);
6999 return rte_flow_error_set(error, ENOMEM,
7000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7001 NULL, "cannot create matcher");
7003 /* Save the table information */
7004 cache_matcher->tbl = tbl;
7005 rte_atomic32_init(&cache_matcher->refcnt);
7006 /* only matcher ref++, table ref++ already done above in get API. */
7007 rte_atomic32_inc(&cache_matcher->refcnt);
7008 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7009 dev_flow->handle->dvh.matcher = cache_matcher;
7010 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7011 key->domain ? "FDB" : "NIC", key->table_id,
7012 cache_matcher->priority,
7013 key->direction ? "tx" : "rx", (void *)cache_matcher,
7014 rte_atomic32_read(&cache_matcher->refcnt));
7019 * Find existing tag resource or create and register a new one.
7021 * @param dev[in, out]
7022 * Pointer to rte_eth_dev structure.
7023 * @param[in, out] tag_be24
7024 * Tag value in big endian then R-shift 8.
7025 * @parm[in, out] dev_flow
7026 * Pointer to the dev_flow.
7028 * pointer to error structure.
7031 * 0 on success otherwise -errno and errno is set.
7034 flow_dv_tag_resource_register
7035 (struct rte_eth_dev *dev,
7037 struct mlx5_flow *dev_flow,
7038 struct rte_flow_error *error)
7040 struct mlx5_priv *priv = dev->data->dev_private;
7041 struct mlx5_ibv_shared *sh = priv->sh;
7042 struct mlx5_flow_dv_tag_resource *cache_resource;
7043 struct mlx5_hlist_entry *entry;
7045 /* Lookup a matching resource from cache. */
7046 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7048 cache_resource = container_of
7049 (entry, struct mlx5_flow_dv_tag_resource, entry);
7050 rte_atomic32_inc(&cache_resource->refcnt);
7051 dev_flow->handle->dvh.tag_resource = cache_resource;
7052 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7053 (void *)cache_resource,
7054 rte_atomic32_read(&cache_resource->refcnt));
7057 /* Register new resource. */
7058 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7059 if (!cache_resource)
7060 return rte_flow_error_set(error, ENOMEM,
7061 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7062 "cannot allocate resource memory");
7063 cache_resource->entry.key = (uint64_t)tag_be24;
7064 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7065 if (!cache_resource->action) {
7066 rte_free(cache_resource);
7067 return rte_flow_error_set(error, ENOMEM,
7068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7069 NULL, "cannot create action");
7071 rte_atomic32_init(&cache_resource->refcnt);
7072 rte_atomic32_inc(&cache_resource->refcnt);
7073 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7074 mlx5_glue->destroy_flow_action(cache_resource->action);
7075 rte_free(cache_resource);
7076 return rte_flow_error_set(error, EEXIST,
7077 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7078 NULL, "cannot insert tag");
7080 dev_flow->handle->dvh.tag_resource = cache_resource;
7081 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7082 (void *)cache_resource,
7083 rte_atomic32_read(&cache_resource->refcnt));
7091 * Pointer to Ethernet device.
7093 * Pointer to mlx5_flow.
7096 * 1 while a reference on it exists, 0 when freed.
7099 flow_dv_tag_release(struct rte_eth_dev *dev,
7100 struct mlx5_flow_dv_tag_resource *tag)
7102 struct mlx5_priv *priv = dev->data->dev_private;
7103 struct mlx5_ibv_shared *sh = priv->sh;
7106 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7107 dev->data->port_id, (void *)tag,
7108 rte_atomic32_read(&tag->refcnt));
7109 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7110 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7111 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7112 DRV_LOG(DEBUG, "port %u tag %p: removed",
7113 dev->data->port_id, (void *)tag);
7121 * Translate port ID action to vport.
7124 * Pointer to rte_eth_dev structure.
7126 * Pointer to the port ID action.
7127 * @param[out] dst_port_id
7128 * The target port ID.
7130 * Pointer to the error structure.
7133 * 0 on success, a negative errno value otherwise and rte_errno is set.
7136 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7137 const struct rte_flow_action *action,
7138 uint32_t *dst_port_id,
7139 struct rte_flow_error *error)
7142 struct mlx5_priv *priv;
7143 const struct rte_flow_action_port_id *conf =
7144 (const struct rte_flow_action_port_id *)action->conf;
7146 port = conf->original ? dev->data->port_id : conf->id;
7147 priv = mlx5_port_to_eswitch_info(port, false);
7149 return rte_flow_error_set(error, -rte_errno,
7150 RTE_FLOW_ERROR_TYPE_ACTION,
7152 "No eswitch info was found for port");
7153 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7155 * This parameter is transferred to
7156 * mlx5dv_dr_action_create_dest_ib_port().
7158 *dst_port_id = priv->ibv_port;
7161 * Legacy mode, no LAG configurations is supported.
7162 * This parameter is transferred to
7163 * mlx5dv_dr_action_create_dest_vport().
7165 *dst_port_id = priv->vport_id;
7171 * Add Tx queue matcher
7174 * Pointer to the dev struct.
7175 * @param[in, out] matcher
7177 * @param[in, out] key
7178 * Flow matcher value.
7180 * Flow pattern to translate.
7182 * Item is inner pattern.
7185 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7186 void *matcher, void *key,
7187 const struct rte_flow_item *item)
7189 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7190 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7192 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7194 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7195 struct mlx5_txq_ctrl *txq;
7199 queue_m = (const void *)item->mask;
7202 queue_v = (const void *)item->spec;
7205 txq = mlx5_txq_get(dev, queue_v->queue);
7208 queue = txq->obj->sq->id;
7209 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7210 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7211 queue & queue_m->queue);
7212 mlx5_txq_release(dev, queue_v->queue);
7216 * Set the hash fields according to the @p flow information.
7218 * @param[in] dev_flow
7219 * Pointer to the mlx5_flow.
7222 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7224 struct rte_flow *flow = dev_flow->flow;
7225 uint64_t items = dev_flow->handle->layers;
7227 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7229 dev_flow->hash_fields = 0;
7230 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7231 if (flow->rss.level >= 2) {
7232 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7236 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7237 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7238 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7239 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7240 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7241 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7242 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7244 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7246 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7247 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7248 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7249 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7250 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7251 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7252 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7254 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7257 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7258 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7259 if (rss_types & ETH_RSS_UDP) {
7260 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7261 dev_flow->hash_fields |=
7262 IBV_RX_HASH_SRC_PORT_UDP;
7263 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7264 dev_flow->hash_fields |=
7265 IBV_RX_HASH_DST_PORT_UDP;
7267 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7269 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7270 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7271 if (rss_types & ETH_RSS_TCP) {
7272 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7273 dev_flow->hash_fields |=
7274 IBV_RX_HASH_SRC_PORT_TCP;
7275 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7276 dev_flow->hash_fields |=
7277 IBV_RX_HASH_DST_PORT_TCP;
7279 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7285 * Fill the flow with DV spec, lock free
7286 * (mutex should be acquired by caller).
7289 * Pointer to rte_eth_dev structure.
7290 * @param[in, out] dev_flow
7291 * Pointer to the sub flow.
7293 * Pointer to the flow attributes.
7295 * Pointer to the list of items.
7296 * @param[in] actions
7297 * Pointer to the list of actions.
7299 * Pointer to the error structure.
7302 * 0 on success, a negative errno value otherwise and rte_errno is set.
7305 __flow_dv_translate(struct rte_eth_dev *dev,
7306 struct mlx5_flow *dev_flow,
7307 const struct rte_flow_attr *attr,
7308 const struct rte_flow_item items[],
7309 const struct rte_flow_action actions[],
7310 struct rte_flow_error *error)
7312 struct mlx5_priv *priv = dev->data->dev_private;
7313 struct mlx5_dev_config *dev_conf = &priv->config;
7314 struct rte_flow *flow = dev_flow->flow;
7315 struct mlx5_flow_handle *handle = dev_flow->handle;
7316 uint64_t item_flags = 0;
7317 uint64_t last_item = 0;
7318 uint64_t action_flags = 0;
7319 uint64_t priority = attr->priority;
7320 struct mlx5_flow_dv_matcher matcher = {
7322 .size = sizeof(matcher.mask.buf),
7326 bool actions_end = false;
7328 struct mlx5_flow_dv_modify_hdr_resource res;
7329 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7330 sizeof(struct mlx5_modification_cmd) *
7331 (MLX5_MAX_MODIFY_NUM + 1)];
7333 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7334 union flow_dv_attr flow_attr = { .attr = 0 };
7336 union mlx5_flow_tbl_key tbl_key;
7337 uint32_t modify_action_position = UINT32_MAX;
7338 void *match_mask = matcher.mask.buf;
7339 void *match_value = dev_flow->dv.value.buf;
7340 uint8_t next_protocol = 0xff;
7341 struct rte_vlan_hdr vlan = { 0 };
7345 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7346 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7347 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7348 !!priv->fdb_def_rule, &table, error);
7351 dev_flow->dv.group = table;
7353 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7354 if (priority == MLX5_FLOW_PRIO_RSVD)
7355 priority = dev_conf->flow_prio - 1;
7356 /* number of actions must be set to 0 in case of dirty stack. */
7357 mhdr_res->actions_num = 0;
7358 for (; !actions_end ; actions++) {
7359 const struct rte_flow_action_queue *queue;
7360 const struct rte_flow_action_rss *rss;
7361 const struct rte_flow_action *action = actions;
7362 const struct rte_flow_action_count *count = action->conf;
7363 const uint8_t *rss_key;
7364 const struct rte_flow_action_jump *jump_data;
7365 const struct rte_flow_action_meter *mtr;
7366 struct mlx5_flow_tbl_resource *tbl;
7367 uint32_t port_id = 0;
7368 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7369 int action_type = actions->type;
7370 const struct rte_flow_action *found_action = NULL;
7372 switch (action_type) {
7373 case RTE_FLOW_ACTION_TYPE_VOID:
7375 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7376 if (flow_dv_translate_action_port_id(dev, action,
7379 port_id_resource.port_id = port_id;
7380 if (flow_dv_port_id_action_resource_register
7381 (dev, &port_id_resource, dev_flow, error))
7383 dev_flow->dv.actions[actions_n++] =
7384 handle->dvh.port_id_action->action;
7385 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7387 case RTE_FLOW_ACTION_TYPE_FLAG:
7388 action_flags |= MLX5_FLOW_ACTION_FLAG;
7389 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7390 struct rte_flow_action_mark mark = {
7391 .id = MLX5_FLOW_MARK_DEFAULT,
7394 if (flow_dv_convert_action_mark(dev, &mark,
7398 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7401 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7403 * Only one FLAG or MARK is supported per device flow
7404 * right now. So the pointer to the tag resource must be
7405 * zero before the register process.
7407 MLX5_ASSERT(!handle->dvh.tag_resource);
7408 if (flow_dv_tag_resource_register(dev, tag_be,
7411 dev_flow->dv.actions[actions_n++] =
7412 handle->dvh.tag_resource->action;
7414 case RTE_FLOW_ACTION_TYPE_MARK:
7415 action_flags |= MLX5_FLOW_ACTION_MARK;
7416 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7417 const struct rte_flow_action_mark *mark =
7418 (const struct rte_flow_action_mark *)
7421 if (flow_dv_convert_action_mark(dev, mark,
7425 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7429 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7430 /* Legacy (non-extensive) MARK action. */
7431 tag_be = mlx5_flow_mark_set
7432 (((const struct rte_flow_action_mark *)
7433 (actions->conf))->id);
7434 MLX5_ASSERT(!handle->dvh.tag_resource);
7435 if (flow_dv_tag_resource_register(dev, tag_be,
7438 dev_flow->dv.actions[actions_n++] =
7439 handle->dvh.tag_resource->action;
7441 case RTE_FLOW_ACTION_TYPE_SET_META:
7442 if (flow_dv_convert_action_set_meta
7443 (dev, mhdr_res, attr,
7444 (const struct rte_flow_action_set_meta *)
7445 actions->conf, error))
7447 action_flags |= MLX5_FLOW_ACTION_SET_META;
7449 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7450 if (flow_dv_convert_action_set_tag
7452 (const struct rte_flow_action_set_tag *)
7453 actions->conf, error))
7455 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7457 case RTE_FLOW_ACTION_TYPE_DROP:
7458 action_flags |= MLX5_FLOW_ACTION_DROP;
7460 case RTE_FLOW_ACTION_TYPE_QUEUE:
7461 MLX5_ASSERT(flow->rss.queue);
7462 queue = actions->conf;
7463 flow->rss.queue_num = 1;
7464 (*flow->rss.queue)[0] = queue->index;
7465 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7467 case RTE_FLOW_ACTION_TYPE_RSS:
7468 MLX5_ASSERT(flow->rss.queue);
7469 rss = actions->conf;
7470 if (flow->rss.queue)
7471 memcpy((*flow->rss.queue), rss->queue,
7472 rss->queue_num * sizeof(uint16_t));
7473 flow->rss.queue_num = rss->queue_num;
7474 /* NULL RSS key indicates default RSS key. */
7475 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7476 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7478 * rss->level and rss.types should be set in advance
7479 * when expanding items for RSS.
7481 action_flags |= MLX5_FLOW_ACTION_RSS;
7483 case RTE_FLOW_ACTION_TYPE_COUNT:
7484 if (!dev_conf->devx) {
7485 rte_errno = ENOTSUP;
7488 flow->counter = flow_dv_counter_alloc(dev,
7491 dev_flow->dv.group);
7494 dev_flow->dv.actions[actions_n++] =
7495 (flow_dv_counter_get_by_idx(dev,
7496 flow->counter, NULL))->action;
7497 action_flags |= MLX5_FLOW_ACTION_COUNT;
7500 if (rte_errno == ENOTSUP)
7501 return rte_flow_error_set
7503 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7505 "count action not supported");
7507 return rte_flow_error_set
7509 RTE_FLOW_ERROR_TYPE_ACTION,
7511 "cannot create counter"
7514 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7515 dev_flow->dv.actions[actions_n++] =
7516 priv->sh->pop_vlan_action;
7517 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7519 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7520 flow_dev_get_vlan_info_from_items(items, &vlan);
7521 vlan.eth_proto = rte_be_to_cpu_16
7522 ((((const struct rte_flow_action_of_push_vlan *)
7523 actions->conf)->ethertype));
7524 found_action = mlx5_flow_find_action
7526 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7528 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7529 found_action = mlx5_flow_find_action
7531 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7533 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7534 if (flow_dv_create_action_push_vlan
7535 (dev, attr, &vlan, dev_flow, error))
7537 dev_flow->dv.actions[actions_n++] =
7538 handle->dvh.push_vlan_res->action;
7539 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7541 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7542 /* of_vlan_push action handled this action */
7543 MLX5_ASSERT(action_flags &
7544 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7546 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7547 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7549 flow_dev_get_vlan_info_from_items(items, &vlan);
7550 mlx5_update_vlan_vid_pcp(actions, &vlan);
7551 /* If no VLAN push - this is a modify header action */
7552 if (flow_dv_convert_action_modify_vlan_vid
7553 (mhdr_res, actions, error))
7555 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7557 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7558 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7559 if (flow_dv_create_action_l2_encap(dev, actions,
7564 dev_flow->dv.actions[actions_n++] =
7565 handle->dvh.encap_decap->verbs_action;
7566 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7568 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7569 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7570 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7574 dev_flow->dv.actions[actions_n++] =
7575 handle->dvh.encap_decap->verbs_action;
7576 action_flags |= MLX5_FLOW_ACTION_DECAP;
7578 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7579 /* Handle encap with preceding decap. */
7580 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7581 if (flow_dv_create_action_raw_encap
7582 (dev, actions, dev_flow, attr, error))
7584 dev_flow->dv.actions[actions_n++] =
7585 handle->dvh.encap_decap->verbs_action;
7587 /* Handle encap without preceding decap. */
7588 if (flow_dv_create_action_l2_encap
7589 (dev, actions, dev_flow, attr->transfer,
7592 dev_flow->dv.actions[actions_n++] =
7593 handle->dvh.encap_decap->verbs_action;
7595 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7597 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7598 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7600 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7601 if (flow_dv_create_action_l2_decap
7602 (dev, dev_flow, attr->transfer, error))
7604 dev_flow->dv.actions[actions_n++] =
7605 handle->dvh.encap_decap->verbs_action;
7607 /* If decap is followed by encap, handle it at encap. */
7608 action_flags |= MLX5_FLOW_ACTION_DECAP;
7610 case RTE_FLOW_ACTION_TYPE_JUMP:
7611 jump_data = action->conf;
7612 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7614 !!priv->fdb_def_rule,
7618 tbl = flow_dv_tbl_resource_get(dev, table,
7620 attr->transfer, error);
7622 return rte_flow_error_set
7624 RTE_FLOW_ERROR_TYPE_ACTION,
7626 "cannot create jump action.");
7627 if (flow_dv_jump_tbl_resource_register
7628 (dev, tbl, dev_flow, error)) {
7629 flow_dv_tbl_resource_release(dev, tbl);
7630 return rte_flow_error_set
7632 RTE_FLOW_ERROR_TYPE_ACTION,
7634 "cannot create jump action.");
7636 dev_flow->dv.actions[actions_n++] =
7637 handle->dvh.jump->action;
7638 action_flags |= MLX5_FLOW_ACTION_JUMP;
7640 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7641 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7642 if (flow_dv_convert_action_modify_mac
7643 (mhdr_res, actions, error))
7645 action_flags |= actions->type ==
7646 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7647 MLX5_FLOW_ACTION_SET_MAC_SRC :
7648 MLX5_FLOW_ACTION_SET_MAC_DST;
7650 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7651 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7652 if (flow_dv_convert_action_modify_ipv4
7653 (mhdr_res, actions, error))
7655 action_flags |= actions->type ==
7656 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7657 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7658 MLX5_FLOW_ACTION_SET_IPV4_DST;
7660 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7661 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7662 if (flow_dv_convert_action_modify_ipv6
7663 (mhdr_res, actions, error))
7665 action_flags |= actions->type ==
7666 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7667 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7668 MLX5_FLOW_ACTION_SET_IPV6_DST;
7670 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7671 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7672 if (flow_dv_convert_action_modify_tp
7673 (mhdr_res, actions, items,
7674 &flow_attr, dev_flow, !!(action_flags &
7675 MLX5_FLOW_ACTION_DECAP), error))
7677 action_flags |= actions->type ==
7678 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7679 MLX5_FLOW_ACTION_SET_TP_SRC :
7680 MLX5_FLOW_ACTION_SET_TP_DST;
7682 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7683 if (flow_dv_convert_action_modify_dec_ttl
7684 (mhdr_res, items, &flow_attr, dev_flow,
7686 MLX5_FLOW_ACTION_DECAP), error))
7688 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7690 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7691 if (flow_dv_convert_action_modify_ttl
7692 (mhdr_res, actions, items, &flow_attr,
7693 dev_flow, !!(action_flags &
7694 MLX5_FLOW_ACTION_DECAP), error))
7696 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7698 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7699 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7700 if (flow_dv_convert_action_modify_tcp_seq
7701 (mhdr_res, actions, error))
7703 action_flags |= actions->type ==
7704 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7705 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7706 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7709 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7710 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7711 if (flow_dv_convert_action_modify_tcp_ack
7712 (mhdr_res, actions, error))
7714 action_flags |= actions->type ==
7715 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7716 MLX5_FLOW_ACTION_INC_TCP_ACK :
7717 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7719 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7720 if (flow_dv_convert_action_set_reg
7721 (mhdr_res, actions, error))
7723 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7725 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7726 if (flow_dv_convert_action_copy_mreg
7727 (dev, mhdr_res, actions, error))
7729 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7731 case RTE_FLOW_ACTION_TYPE_METER:
7732 mtr = actions->conf;
7734 flow->meter = mlx5_flow_meter_attach(priv,
7738 return rte_flow_error_set(error,
7740 RTE_FLOW_ERROR_TYPE_ACTION,
7743 "or invalid parameters");
7745 /* Set the meter action. */
7746 dev_flow->dv.actions[actions_n++] =
7747 flow->meter->mfts->meter_action;
7748 action_flags |= MLX5_FLOW_ACTION_METER;
7750 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7751 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7754 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7756 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7757 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7760 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7762 case RTE_FLOW_ACTION_TYPE_END:
7764 if (mhdr_res->actions_num) {
7765 /* create modify action if needed. */
7766 if (flow_dv_modify_hdr_resource_register
7767 (dev, mhdr_res, dev_flow, error))
7769 dev_flow->dv.actions[modify_action_position] =
7770 handle->dvh.modify_hdr->verbs_action;
7776 if (mhdr_res->actions_num &&
7777 modify_action_position == UINT32_MAX)
7778 modify_action_position = actions_n++;
7780 dev_flow->dv.actions_n = actions_n;
7781 handle->act_flags = action_flags;
7782 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7783 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7784 int item_type = items->type;
7786 switch (item_type) {
7787 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7788 flow_dv_translate_item_port_id(dev, match_mask,
7789 match_value, items);
7790 last_item = MLX5_FLOW_ITEM_PORT_ID;
7792 case RTE_FLOW_ITEM_TYPE_ETH:
7793 flow_dv_translate_item_eth(match_mask, match_value,
7795 matcher.priority = MLX5_PRIORITY_MAP_L2;
7796 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7797 MLX5_FLOW_LAYER_OUTER_L2;
7799 case RTE_FLOW_ITEM_TYPE_VLAN:
7800 flow_dv_translate_item_vlan(dev_flow,
7801 match_mask, match_value,
7803 matcher.priority = MLX5_PRIORITY_MAP_L2;
7804 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7805 MLX5_FLOW_LAYER_INNER_VLAN) :
7806 (MLX5_FLOW_LAYER_OUTER_L2 |
7807 MLX5_FLOW_LAYER_OUTER_VLAN);
7809 case RTE_FLOW_ITEM_TYPE_IPV4:
7810 mlx5_flow_tunnel_ip_check(items, next_protocol,
7811 &item_flags, &tunnel);
7812 flow_dv_translate_item_ipv4(match_mask, match_value,
7813 items, item_flags, tunnel,
7814 dev_flow->dv.group);
7815 matcher.priority = MLX5_PRIORITY_MAP_L3;
7816 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7817 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7818 if (items->mask != NULL &&
7819 ((const struct rte_flow_item_ipv4 *)
7820 items->mask)->hdr.next_proto_id) {
7822 ((const struct rte_flow_item_ipv4 *)
7823 (items->spec))->hdr.next_proto_id;
7825 ((const struct rte_flow_item_ipv4 *)
7826 (items->mask))->hdr.next_proto_id;
7828 /* Reset for inner layer. */
7829 next_protocol = 0xff;
7832 case RTE_FLOW_ITEM_TYPE_IPV6:
7833 mlx5_flow_tunnel_ip_check(items, next_protocol,
7834 &item_flags, &tunnel);
7835 flow_dv_translate_item_ipv6(match_mask, match_value,
7836 items, item_flags, tunnel,
7837 dev_flow->dv.group);
7838 matcher.priority = MLX5_PRIORITY_MAP_L3;
7839 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7840 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7841 if (items->mask != NULL &&
7842 ((const struct rte_flow_item_ipv6 *)
7843 items->mask)->hdr.proto) {
7845 ((const struct rte_flow_item_ipv6 *)
7846 items->spec)->hdr.proto;
7848 ((const struct rte_flow_item_ipv6 *)
7849 items->mask)->hdr.proto;
7851 /* Reset for inner layer. */
7852 next_protocol = 0xff;
7855 case RTE_FLOW_ITEM_TYPE_TCP:
7856 flow_dv_translate_item_tcp(match_mask, match_value,
7858 matcher.priority = MLX5_PRIORITY_MAP_L4;
7859 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7860 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7862 case RTE_FLOW_ITEM_TYPE_UDP:
7863 flow_dv_translate_item_udp(match_mask, match_value,
7865 matcher.priority = MLX5_PRIORITY_MAP_L4;
7866 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7867 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7869 case RTE_FLOW_ITEM_TYPE_GRE:
7870 flow_dv_translate_item_gre(match_mask, match_value,
7872 matcher.priority = flow->rss.level >= 2 ?
7873 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7874 last_item = MLX5_FLOW_LAYER_GRE;
7876 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7877 flow_dv_translate_item_gre_key(match_mask,
7878 match_value, items);
7879 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7881 case RTE_FLOW_ITEM_TYPE_NVGRE:
7882 flow_dv_translate_item_nvgre(match_mask, match_value,
7884 matcher.priority = flow->rss.level >= 2 ?
7885 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7886 last_item = MLX5_FLOW_LAYER_GRE;
7888 case RTE_FLOW_ITEM_TYPE_VXLAN:
7889 flow_dv_translate_item_vxlan(match_mask, match_value,
7891 matcher.priority = flow->rss.level >= 2 ?
7892 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7893 last_item = MLX5_FLOW_LAYER_VXLAN;
7895 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7896 flow_dv_translate_item_vxlan_gpe(match_mask,
7899 matcher.priority = flow->rss.level >= 2 ?
7900 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7901 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7903 case RTE_FLOW_ITEM_TYPE_GENEVE:
7904 flow_dv_translate_item_geneve(match_mask, match_value,
7906 matcher.priority = flow->rss.level >= 2 ?
7907 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7908 last_item = MLX5_FLOW_LAYER_GENEVE;
7910 case RTE_FLOW_ITEM_TYPE_MPLS:
7911 flow_dv_translate_item_mpls(match_mask, match_value,
7912 items, last_item, tunnel);
7913 matcher.priority = flow->rss.level >= 2 ?
7914 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7915 last_item = MLX5_FLOW_LAYER_MPLS;
7917 case RTE_FLOW_ITEM_TYPE_MARK:
7918 flow_dv_translate_item_mark(dev, match_mask,
7919 match_value, items);
7920 last_item = MLX5_FLOW_ITEM_MARK;
7922 case RTE_FLOW_ITEM_TYPE_META:
7923 flow_dv_translate_item_meta(dev, match_mask,
7924 match_value, attr, items);
7925 last_item = MLX5_FLOW_ITEM_METADATA;
7927 case RTE_FLOW_ITEM_TYPE_ICMP:
7928 flow_dv_translate_item_icmp(match_mask, match_value,
7930 last_item = MLX5_FLOW_LAYER_ICMP;
7932 case RTE_FLOW_ITEM_TYPE_ICMP6:
7933 flow_dv_translate_item_icmp6(match_mask, match_value,
7935 last_item = MLX5_FLOW_LAYER_ICMP6;
7937 case RTE_FLOW_ITEM_TYPE_TAG:
7938 flow_dv_translate_item_tag(dev, match_mask,
7939 match_value, items);
7940 last_item = MLX5_FLOW_ITEM_TAG;
7942 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7943 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7944 match_value, items);
7945 last_item = MLX5_FLOW_ITEM_TAG;
7947 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7948 flow_dv_translate_item_tx_queue(dev, match_mask,
7951 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7953 case RTE_FLOW_ITEM_TYPE_GTP:
7954 flow_dv_translate_item_gtp(match_mask, match_value,
7956 matcher.priority = flow->rss.level >= 2 ?
7957 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7958 last_item = MLX5_FLOW_LAYER_GTP;
7963 item_flags |= last_item;
7966 * When E-Switch mode is enabled, we have two cases where we need to
7967 * set the source port manually.
7968 * The first one, is in case of Nic steering rule, and the second is
7969 * E-Switch rule where no port_id item was found. In both cases
7970 * the source port is set according the current port in use.
7972 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7973 (priv->representor || priv->master)) {
7974 if (flow_dv_translate_item_port_id(dev, match_mask,
7978 #ifdef RTE_LIBRTE_MLX5_DEBUG
7979 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7980 dev_flow->dv.value.buf));
7983 * Layers may be already initialized from prefix flow if this dev_flow
7984 * is the suffix flow.
7986 handle->layers |= item_flags;
7987 if (action_flags & MLX5_FLOW_ACTION_RSS)
7988 flow_dv_hashfields_set(dev_flow);
7989 /* Register matcher. */
7990 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7992 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7994 /* reserved field no needs to be set to 0 here. */
7995 tbl_key.domain = attr->transfer;
7996 tbl_key.direction = attr->egress;
7997 tbl_key.table_id = dev_flow->dv.group;
7998 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8004 * Apply the flow to the NIC, lock free,
8005 * (mutex should be acquired by caller).
8008 * Pointer to the Ethernet device structure.
8009 * @param[in, out] flow
8010 * Pointer to flow structure.
8012 * Pointer to error structure.
8015 * 0 on success, a negative errno value otherwise and rte_errno is set.
8018 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8019 struct rte_flow_error *error)
8021 struct mlx5_flow_dv_workspace *dv;
8022 struct mlx5_flow_handle *dh;
8023 struct mlx5_flow_handle_dv *dv_h;
8024 struct mlx5_flow *dev_flow;
8025 struct mlx5_priv *priv = dev->data->dev_private;
8030 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8031 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8033 dh = dev_flow->handle;
8036 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8038 dv->actions[n++] = priv->sh->esw_drop_action;
8040 dh->hrxq = mlx5_hrxq_drop_new(dev);
8044 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8046 "cannot get drop hash queue");
8049 dv->actions[n++] = dh->hrxq->action;
8051 } else if (dh->act_flags &
8052 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8053 struct mlx5_hrxq *hrxq;
8055 MLX5_ASSERT(flow->rss.queue);
8056 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8057 MLX5_RSS_HASH_KEY_LEN,
8058 dev_flow->hash_fields,
8060 flow->rss.queue_num);
8062 hrxq = mlx5_hrxq_new
8063 (dev, flow->rss.key,
8064 MLX5_RSS_HASH_KEY_LEN,
8065 dev_flow->hash_fields,
8067 flow->rss.queue_num,
8069 MLX5_FLOW_LAYER_TUNNEL));
8074 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8075 "cannot get hash queue");
8079 dv->actions[n++] = dh->hrxq->action;
8082 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8083 (void *)&dv->value, n,
8086 rte_flow_error_set(error, errno,
8087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8089 "hardware refuses to create flow");
8092 if (priv->vmwa_context &&
8093 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8095 * The rule contains the VLAN pattern.
8096 * For VF we are going to create VLAN
8097 * interface to make hypervisor set correct
8098 * e-Switch vport context.
8100 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8105 err = rte_errno; /* Save rte_errno before cleanup. */
8106 LIST_FOREACH(dh, &flow->dev_handles, next) {
8108 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8109 mlx5_hrxq_drop_release(dev);
8111 mlx5_hrxq_release(dev, dh->hrxq);
8114 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8115 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8117 rte_errno = err; /* Restore rte_errno. */
8122 * Release the flow matcher.
8125 * Pointer to Ethernet device.
8127 * Pointer to mlx5_flow_handle.
8130 * 1 while a reference on it exists, 0 when freed.
8133 flow_dv_matcher_release(struct rte_eth_dev *dev,
8134 struct mlx5_flow_handle *handle)
8136 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8138 MLX5_ASSERT(matcher->matcher_object);
8139 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8140 dev->data->port_id, (void *)matcher,
8141 rte_atomic32_read(&matcher->refcnt));
8142 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8143 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8144 (matcher->matcher_object));
8145 LIST_REMOVE(matcher, next);
8146 /* table ref-- in release interface. */
8147 flow_dv_tbl_resource_release(dev, matcher->tbl);
8149 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8150 dev->data->port_id, (void *)matcher);
8157 * Release an encap/decap resource.
8160 * Pointer to mlx5_flow_handle.
8163 * 1 while a reference on it exists, 0 when freed.
8166 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8168 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8169 handle->dvh.encap_decap;
8171 MLX5_ASSERT(cache_resource->verbs_action);
8172 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8173 (void *)cache_resource,
8174 rte_atomic32_read(&cache_resource->refcnt));
8175 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8176 claim_zero(mlx5_glue->destroy_flow_action
8177 (cache_resource->verbs_action));
8178 LIST_REMOVE(cache_resource, next);
8179 rte_free(cache_resource);
8180 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8181 (void *)cache_resource);
8188 * Release an jump to table action resource.
8191 * Pointer to Ethernet device.
8193 * Pointer to mlx5_flow_handle.
8196 * 1 while a reference on it exists, 0 when freed.
8199 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8200 struct mlx5_flow_handle *handle)
8202 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8204 struct mlx5_flow_tbl_data_entry *tbl_data =
8205 container_of(cache_resource,
8206 struct mlx5_flow_tbl_data_entry, jump);
8208 MLX5_ASSERT(cache_resource->action);
8209 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8210 (void *)cache_resource,
8211 rte_atomic32_read(&cache_resource->refcnt));
8212 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8213 claim_zero(mlx5_glue->destroy_flow_action
8214 (cache_resource->action));
8215 /* jump action memory free is inside the table release. */
8216 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8217 DRV_LOG(DEBUG, "jump table resource %p: removed",
8218 (void *)cache_resource);
8225 * Release a modify-header resource.
8228 * Pointer to mlx5_flow_handle.
8231 * 1 while a reference on it exists, 0 when freed.
8234 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8236 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8237 handle->dvh.modify_hdr;
8239 MLX5_ASSERT(cache_resource->verbs_action);
8240 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8241 (void *)cache_resource,
8242 rte_atomic32_read(&cache_resource->refcnt));
8243 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8244 claim_zero(mlx5_glue->destroy_flow_action
8245 (cache_resource->verbs_action));
8246 LIST_REMOVE(cache_resource, next);
8247 rte_free(cache_resource);
8248 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8249 (void *)cache_resource);
8256 * Release port ID action resource.
8259 * Pointer to mlx5_flow_handle.
8262 * 1 while a reference on it exists, 0 when freed.
8265 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8267 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8268 handle->dvh.port_id_action;
8270 MLX5_ASSERT(cache_resource->action);
8271 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8272 (void *)cache_resource,
8273 rte_atomic32_read(&cache_resource->refcnt));
8274 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8275 claim_zero(mlx5_glue->destroy_flow_action
8276 (cache_resource->action));
8277 LIST_REMOVE(cache_resource, next);
8278 rte_free(cache_resource);
8279 DRV_LOG(DEBUG, "port id action resource %p: removed",
8280 (void *)cache_resource);
8287 * Release push vlan action resource.
8290 * Pointer to mlx5_flow_handle.
8293 * 1 while a reference on it exists, 0 when freed.
8296 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8298 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8299 handle->dvh.push_vlan_res;
8301 MLX5_ASSERT(cache_resource->action);
8302 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8303 (void *)cache_resource,
8304 rte_atomic32_read(&cache_resource->refcnt));
8305 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8306 claim_zero(mlx5_glue->destroy_flow_action
8307 (cache_resource->action));
8308 LIST_REMOVE(cache_resource, next);
8309 rte_free(cache_resource);
8310 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8311 (void *)cache_resource);
8318 * Remove the flow from the NIC but keeps it in memory.
8319 * Lock free, (mutex should be acquired by caller).
8322 * Pointer to Ethernet device.
8323 * @param[in, out] flow
8324 * Pointer to flow structure.
8327 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8329 struct mlx5_flow_handle *dh;
8333 LIST_FOREACH(dh, &flow->dev_handles, next) {
8335 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8339 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8340 mlx5_hrxq_drop_release(dev);
8342 mlx5_hrxq_release(dev, dh->hrxq);
8345 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8346 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8351 * Remove the flow from the NIC and the memory.
8352 * Lock free, (mutex should be acquired by caller).
8355 * Pointer to the Ethernet device structure.
8356 * @param[in, out] flow
8357 * Pointer to flow structure.
8360 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8362 struct mlx5_flow_handle *dev_handle;
8366 __flow_dv_remove(dev, flow);
8367 if (flow->counter) {
8368 flow_dv_counter_release(dev, flow->counter);
8372 mlx5_flow_meter_detach(flow->meter);
8375 while (!LIST_EMPTY(&flow->dev_handles)) {
8376 dev_handle = LIST_FIRST(&flow->dev_handles);
8377 LIST_REMOVE(dev_handle, next);
8378 if (dev_handle->dvh.matcher)
8379 flow_dv_matcher_release(dev, dev_handle);
8380 if (dev_handle->dvh.encap_decap)
8381 flow_dv_encap_decap_resource_release(dev_handle);
8382 if (dev_handle->dvh.modify_hdr)
8383 flow_dv_modify_hdr_resource_release(dev_handle);
8384 if (dev_handle->dvh.jump)
8385 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8386 if (dev_handle->dvh.port_id_action)
8387 flow_dv_port_id_action_resource_release(dev_handle);
8388 if (dev_handle->dvh.push_vlan_res)
8389 flow_dv_push_vlan_action_resource_release(dev_handle);
8390 if (dev_handle->dvh.tag_resource)
8391 flow_dv_tag_release(dev,
8392 dev_handle->dvh.tag_resource);
8393 rte_free(dev_handle);
8398 * Query a dv flow rule for its statistics via devx.
8401 * Pointer to Ethernet device.
8403 * Pointer to the sub flow.
8405 * data retrieved by the query.
8407 * Perform verbose error reporting if not NULL.
8410 * 0 on success, a negative errno value otherwise and rte_errno is set.
8413 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8414 void *data, struct rte_flow_error *error)
8416 struct mlx5_priv *priv = dev->data->dev_private;
8417 struct rte_flow_query_count *qc = data;
8419 if (!priv->config.devx)
8420 return rte_flow_error_set(error, ENOTSUP,
8421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8423 "counters are not supported");
8424 if (flow->counter) {
8425 uint64_t pkts, bytes;
8426 struct mlx5_flow_counter *cnt;
8428 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8430 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8434 return rte_flow_error_set(error, -err,
8435 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8436 NULL, "cannot read counters");
8439 qc->hits = pkts - cnt->hits;
8440 qc->bytes = bytes - cnt->bytes;
8447 return rte_flow_error_set(error, EINVAL,
8448 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8450 "counters are not available");
8456 * @see rte_flow_query()
8460 flow_dv_query(struct rte_eth_dev *dev,
8461 struct rte_flow *flow __rte_unused,
8462 const struct rte_flow_action *actions __rte_unused,
8463 void *data __rte_unused,
8464 struct rte_flow_error *error __rte_unused)
8468 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8469 switch (actions->type) {
8470 case RTE_FLOW_ACTION_TYPE_VOID:
8472 case RTE_FLOW_ACTION_TYPE_COUNT:
8473 ret = flow_dv_query_count(dev, flow, data, error);
8476 return rte_flow_error_set(error, ENOTSUP,
8477 RTE_FLOW_ERROR_TYPE_ACTION,
8479 "action not supported");
8486 * Destroy the meter table set.
8487 * Lock free, (mutex should be acquired by caller).
8490 * Pointer to Ethernet device.
8492 * Pointer to the meter table set.
8498 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8499 struct mlx5_meter_domains_infos *tbl)
8501 struct mlx5_priv *priv = dev->data->dev_private;
8502 struct mlx5_meter_domains_infos *mtd =
8503 (struct mlx5_meter_domains_infos *)tbl;
8505 if (!mtd || !priv->config.dv_flow_en)
8507 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8508 claim_zero(mlx5_glue->dv_destroy_flow
8509 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8510 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8511 claim_zero(mlx5_glue->dv_destroy_flow
8512 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8513 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8514 claim_zero(mlx5_glue->dv_destroy_flow
8515 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8516 if (mtd->egress.color_matcher)
8517 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8518 (mtd->egress.color_matcher));
8519 if (mtd->egress.any_matcher)
8520 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8521 (mtd->egress.any_matcher));
8522 if (mtd->egress.tbl)
8523 claim_zero(flow_dv_tbl_resource_release(dev,
8525 if (mtd->egress.sfx_tbl)
8526 claim_zero(flow_dv_tbl_resource_release(dev,
8527 mtd->egress.sfx_tbl));
8528 if (mtd->ingress.color_matcher)
8529 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8530 (mtd->ingress.color_matcher));
8531 if (mtd->ingress.any_matcher)
8532 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8533 (mtd->ingress.any_matcher));
8534 if (mtd->ingress.tbl)
8535 claim_zero(flow_dv_tbl_resource_release(dev,
8537 if (mtd->ingress.sfx_tbl)
8538 claim_zero(flow_dv_tbl_resource_release(dev,
8539 mtd->ingress.sfx_tbl));
8540 if (mtd->transfer.color_matcher)
8541 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8542 (mtd->transfer.color_matcher));
8543 if (mtd->transfer.any_matcher)
8544 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8545 (mtd->transfer.any_matcher));
8546 if (mtd->transfer.tbl)
8547 claim_zero(flow_dv_tbl_resource_release(dev,
8548 mtd->transfer.tbl));
8549 if (mtd->transfer.sfx_tbl)
8550 claim_zero(flow_dv_tbl_resource_release(dev,
8551 mtd->transfer.sfx_tbl));
8553 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8558 /* Number of meter flow actions, count and jump or count and drop. */
8559 #define METER_ACTIONS 2
8562 * Create specify domain meter table and suffix table.
8565 * Pointer to Ethernet device.
8566 * @param[in,out] mtb
8567 * Pointer to DV meter table set.
8570 * @param[in] transfer
8572 * @param[in] color_reg_c_idx
8573 * Reg C index for color match.
8576 * 0 on success, -1 otherwise and rte_errno is set.
8579 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8580 struct mlx5_meter_domains_infos *mtb,
8581 uint8_t egress, uint8_t transfer,
8582 uint32_t color_reg_c_idx)
8584 struct mlx5_priv *priv = dev->data->dev_private;
8585 struct mlx5_ibv_shared *sh = priv->sh;
8586 struct mlx5_flow_dv_match_params mask = {
8587 .size = sizeof(mask.buf),
8589 struct mlx5_flow_dv_match_params value = {
8590 .size = sizeof(value.buf),
8592 struct mlx5dv_flow_matcher_attr dv_attr = {
8593 .type = IBV_FLOW_ATTR_NORMAL,
8595 .match_criteria_enable = 0,
8596 .match_mask = (void *)&mask,
8598 void *actions[METER_ACTIONS];
8599 struct mlx5_meter_domain_info *dtb;
8600 struct rte_flow_error error;
8604 dtb = &mtb->transfer;
8608 dtb = &mtb->ingress;
8609 /* Create the meter table with METER level. */
8610 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8611 egress, transfer, &error);
8613 DRV_LOG(ERR, "Failed to create meter policer table.");
8616 /* Create the meter suffix table with SUFFIX level. */
8617 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8618 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8619 egress, transfer, &error);
8620 if (!dtb->sfx_tbl) {
8621 DRV_LOG(ERR, "Failed to create meter suffix table.");
8624 /* Create matchers, Any and Color. */
8625 dv_attr.priority = 3;
8626 dv_attr.match_criteria_enable = 0;
8627 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8630 if (!dtb->any_matcher) {
8631 DRV_LOG(ERR, "Failed to create meter"
8632 " policer default matcher.");
8635 dv_attr.priority = 0;
8636 dv_attr.match_criteria_enable =
8637 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8638 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8639 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8640 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8643 if (!dtb->color_matcher) {
8644 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8647 if (mtb->count_actns[RTE_MTR_DROPPED])
8648 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8649 actions[i++] = mtb->drop_actn;
8650 /* Default rule: lowest priority, match any, actions: drop. */
8651 dtb->policer_rules[RTE_MTR_DROPPED] =
8652 mlx5_glue->dv_create_flow(dtb->any_matcher,
8653 (void *)&value, i, actions);
8654 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8655 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8664 * Create the needed meter and suffix tables.
8665 * Lock free, (mutex should be acquired by caller).
8668 * Pointer to Ethernet device.
8670 * Pointer to the flow meter.
8673 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8675 static struct mlx5_meter_domains_infos *
8676 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8677 const struct mlx5_flow_meter *fm)
8679 struct mlx5_priv *priv = dev->data->dev_private;
8680 struct mlx5_meter_domains_infos *mtb;
8684 if (!priv->mtr_en) {
8685 rte_errno = ENOTSUP;
8688 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8690 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8693 /* Create meter count actions */
8694 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8695 struct mlx5_flow_counter *cnt;
8696 if (!fm->policer_stats.cnt[i])
8698 cnt = flow_dv_counter_get_by_idx(dev,
8699 fm->policer_stats.cnt[i], NULL);
8700 mtb->count_actns[i] = cnt->action;
8702 /* Create drop action. */
8703 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8704 if (!mtb->drop_actn) {
8705 DRV_LOG(ERR, "Failed to create drop action.");
8708 /* Egress meter table. */
8709 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8711 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8714 /* Ingress meter table. */
8715 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8717 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8720 /* FDB meter table. */
8721 if (priv->config.dv_esw_en) {
8722 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8723 priv->mtr_color_reg);
8725 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8731 flow_dv_destroy_mtr_tbl(dev, mtb);
8736 * Destroy domain policer rule.
8739 * Pointer to domain table.
8742 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8746 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8747 if (dt->policer_rules[i]) {
8748 claim_zero(mlx5_glue->dv_destroy_flow
8749 (dt->policer_rules[i]));
8750 dt->policer_rules[i] = NULL;
8753 if (dt->jump_actn) {
8754 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8755 dt->jump_actn = NULL;
8760 * Destroy policer rules.
8763 * Pointer to Ethernet device.
8765 * Pointer to flow meter structure.
8767 * Pointer to flow attributes.
8773 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8774 const struct mlx5_flow_meter *fm,
8775 const struct rte_flow_attr *attr)
8777 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8782 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8784 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8786 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8791 * Create specify domain meter policer rule.
8794 * Pointer to flow meter structure.
8796 * Pointer to DV meter table set.
8797 * @param[in] mtr_reg_c
8798 * Color match REG_C.
8801 * 0 on success, -1 otherwise.
8804 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8805 struct mlx5_meter_domain_info *dtb,
8808 struct mlx5_flow_dv_match_params matcher = {
8809 .size = sizeof(matcher.buf),
8811 struct mlx5_flow_dv_match_params value = {
8812 .size = sizeof(value.buf),
8814 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8815 void *actions[METER_ACTIONS];
8818 /* Create jump action. */
8819 if (!dtb->jump_actn)
8821 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8822 (dtb->sfx_tbl->obj);
8823 if (!dtb->jump_actn) {
8824 DRV_LOG(ERR, "Failed to create policer jump action.");
8827 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8830 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8831 rte_col_2_mlx5_col(i), UINT8_MAX);
8832 if (mtb->count_actns[i])
8833 actions[j++] = mtb->count_actns[i];
8834 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8835 actions[j++] = mtb->drop_actn;
8837 actions[j++] = dtb->jump_actn;
8838 dtb->policer_rules[i] =
8839 mlx5_glue->dv_create_flow(dtb->color_matcher,
8842 if (!dtb->policer_rules[i]) {
8843 DRV_LOG(ERR, "Failed to create policer rule.");
8854 * Create policer rules.
8857 * Pointer to Ethernet device.
8859 * Pointer to flow meter structure.
8861 * Pointer to flow attributes.
8864 * 0 on success, -1 otherwise.
8867 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8868 struct mlx5_flow_meter *fm,
8869 const struct rte_flow_attr *attr)
8871 struct mlx5_priv *priv = dev->data->dev_private;
8872 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8876 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8877 priv->mtr_color_reg);
8879 DRV_LOG(ERR, "Failed to create egress policer.");
8883 if (attr->ingress) {
8884 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8885 priv->mtr_color_reg);
8887 DRV_LOG(ERR, "Failed to create ingress policer.");
8891 if (attr->transfer) {
8892 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8893 priv->mtr_color_reg);
8895 DRV_LOG(ERR, "Failed to create transfer policer.");
8901 flow_dv_destroy_policer_rules(dev, fm, attr);
8906 * Query a devx counter.
8909 * Pointer to the Ethernet device structure.
8911 * Index to the flow counter.
8913 * Set to clear the counter statistics.
8915 * The statistics value of packets.
8917 * The statistics value of bytes.
8920 * 0 on success, otherwise return -1.
8923 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
8924 uint64_t *pkts, uint64_t *bytes)
8926 struct mlx5_priv *priv = dev->data->dev_private;
8927 struct mlx5_flow_counter *cnt;
8928 uint64_t inn_pkts, inn_bytes;
8931 if (!priv->config.devx)
8934 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
8937 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
8938 *pkts = inn_pkts - cnt->hits;
8939 *bytes = inn_bytes - cnt->bytes;
8941 cnt->hits = inn_pkts;
8942 cnt->bytes = inn_bytes;
8948 * Mutex-protected thunk to lock-free __flow_dv_translate().
8951 flow_dv_translate(struct rte_eth_dev *dev,
8952 struct mlx5_flow *dev_flow,
8953 const struct rte_flow_attr *attr,
8954 const struct rte_flow_item items[],
8955 const struct rte_flow_action actions[],
8956 struct rte_flow_error *error)
8960 flow_dv_shared_lock(dev);
8961 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8962 flow_dv_shared_unlock(dev);
8967 * Mutex-protected thunk to lock-free __flow_dv_apply().
8970 flow_dv_apply(struct rte_eth_dev *dev,
8971 struct rte_flow *flow,
8972 struct rte_flow_error *error)
8976 flow_dv_shared_lock(dev);
8977 ret = __flow_dv_apply(dev, flow, error);
8978 flow_dv_shared_unlock(dev);
8983 * Mutex-protected thunk to lock-free __flow_dv_remove().
8986 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8988 flow_dv_shared_lock(dev);
8989 __flow_dv_remove(dev, flow);
8990 flow_dv_shared_unlock(dev);
8994 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8997 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8999 flow_dv_shared_lock(dev);
9000 __flow_dv_destroy(dev, flow);
9001 flow_dv_shared_unlock(dev);
9005 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9008 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9012 flow_dv_shared_lock(dev);
9013 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9014 flow_dv_shared_unlock(dev);
9019 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9022 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9024 flow_dv_shared_lock(dev);
9025 flow_dv_counter_release(dev, cnt);
9026 flow_dv_shared_unlock(dev);
9029 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9030 .validate = flow_dv_validate,
9031 .prepare = flow_dv_prepare,
9032 .translate = flow_dv_translate,
9033 .apply = flow_dv_apply,
9034 .remove = flow_dv_remove,
9035 .destroy = flow_dv_destroy,
9036 .query = flow_dv_query,
9037 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9038 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9039 .create_policer_rules = flow_dv_create_policer_rules,
9040 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9041 .counter_alloc = flow_dv_counter_allocate,
9042 .counter_free = flow_dv_counter_free,
9043 .counter_query = flow_dv_counter_query,
9046 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */