1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
100 struct mlx5_common_device *cdev = priv->sh->cdev;
102 if (cdev->config.hca_attr.esw_mgr_vport_id_valid)
103 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id;
105 if (priv->pci_dev == NULL)
107 switch (priv->pci_dev->id.device_id) {
108 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
109 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
110 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
111 return (int16_t)0xfffe;
118 * Initialize flow attributes structure according to flow items' types.
120 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
121 * mode. For tunnel mode, the items to be modified are the outermost ones.
124 * Pointer to item specification.
126 * Pointer to flow attributes structure.
127 * @param[in] dev_flow
128 * Pointer to the sub flow.
129 * @param[in] tunnel_decap
130 * Whether action is after tunnel decapsulation.
133 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
134 struct mlx5_flow *dev_flow, bool tunnel_decap)
136 uint64_t layers = dev_flow->handle->layers;
139 * If layers is already initialized, it means this dev_flow is the
140 * suffix flow, the layers flags is set by the prefix flow. Need to
141 * use the layer flags from prefix flow as the suffix flow may not
142 * have the user defined items as the flow is split.
145 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
149 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
151 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
156 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
157 uint8_t next_protocol = 0xff;
158 switch (item->type) {
159 case RTE_FLOW_ITEM_TYPE_GRE:
160 case RTE_FLOW_ITEM_TYPE_NVGRE:
161 case RTE_FLOW_ITEM_TYPE_VXLAN:
162 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
163 case RTE_FLOW_ITEM_TYPE_GENEVE:
164 case RTE_FLOW_ITEM_TYPE_MPLS:
168 case RTE_FLOW_ITEM_TYPE_IPV4:
171 if (item->mask != NULL &&
172 ((const struct rte_flow_item_ipv4 *)
173 item->mask)->hdr.next_proto_id)
175 ((const struct rte_flow_item_ipv4 *)
176 (item->spec))->hdr.next_proto_id &
177 ((const struct rte_flow_item_ipv4 *)
178 (item->mask))->hdr.next_proto_id;
179 if ((next_protocol == IPPROTO_IPIP ||
180 next_protocol == IPPROTO_IPV6) && tunnel_decap)
183 case RTE_FLOW_ITEM_TYPE_IPV6:
186 if (item->mask != NULL &&
187 ((const struct rte_flow_item_ipv6 *)
188 item->mask)->hdr.proto)
190 ((const struct rte_flow_item_ipv6 *)
191 (item->spec))->hdr.proto &
192 ((const struct rte_flow_item_ipv6 *)
193 (item->mask))->hdr.proto;
194 if ((next_protocol == IPPROTO_IPIP ||
195 next_protocol == IPPROTO_IPV6) && tunnel_decap)
198 case RTE_FLOW_ITEM_TYPE_UDP:
202 case RTE_FLOW_ITEM_TYPE_TCP:
214 * Convert rte_mtr_color to mlx5 color.
223 rte_col_2_mlx5_col(enum rte_color rcol)
226 case RTE_COLOR_GREEN:
227 return MLX5_FLOW_COLOR_GREEN;
228 case RTE_COLOR_YELLOW:
229 return MLX5_FLOW_COLOR_YELLOW;
231 return MLX5_FLOW_COLOR_RED;
235 return MLX5_FLOW_COLOR_UNDEFINED;
238 struct field_modify_info {
239 uint32_t size; /* Size of field in protocol header, in bytes. */
240 uint32_t offset; /* Offset of field in protocol header, in bytes. */
241 enum mlx5_modification_field id;
244 struct field_modify_info modify_eth[] = {
245 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
246 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
247 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
248 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
252 struct field_modify_info modify_vlan_out_first_vid[] = {
253 /* Size in bits !!! */
254 {12, 0, MLX5_MODI_OUT_FIRST_VID},
258 struct field_modify_info modify_ipv4[] = {
259 {1, 1, MLX5_MODI_OUT_IP_DSCP},
260 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
261 {4, 12, MLX5_MODI_OUT_SIPV4},
262 {4, 16, MLX5_MODI_OUT_DIPV4},
266 struct field_modify_info modify_ipv6[] = {
267 {1, 0, MLX5_MODI_OUT_IP_DSCP},
268 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
269 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
270 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
271 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
272 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
273 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
274 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
275 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
276 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
280 struct field_modify_info modify_udp[] = {
281 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
282 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
286 struct field_modify_info modify_tcp[] = {
287 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
288 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
289 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
290 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
295 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
296 uint8_t next_protocol, uint64_t *item_flags,
299 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
300 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
301 if (next_protocol == IPPROTO_IPIP) {
302 *item_flags |= MLX5_FLOW_LAYER_IPIP;
305 if (next_protocol == IPPROTO_IPV6) {
306 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
311 static inline struct mlx5_hlist *
312 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
313 const char *name, uint32_t size, bool direct_key,
314 bool lcores_share, void *ctx,
315 mlx5_list_create_cb cb_create,
316 mlx5_list_match_cb cb_match,
317 mlx5_list_remove_cb cb_remove,
318 mlx5_list_clone_cb cb_clone,
319 mlx5_list_clone_free_cb cb_clone_free,
320 struct rte_flow_error *error)
322 struct mlx5_hlist *hl;
323 struct mlx5_hlist *expected = NULL;
324 char s[MLX5_NAME_SIZE];
326 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
329 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
330 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
331 ctx, cb_create, cb_match, cb_remove, cb_clone,
334 DRV_LOG(ERR, "%s hash creation failed", name);
335 rte_flow_error_set(error, ENOMEM,
336 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
337 "cannot allocate resource memory");
340 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
343 mlx5_hlist_destroy(hl);
344 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
349 /* Update VLAN's VID/PCP based on input rte_flow_action.
352 * Pointer to struct rte_flow_action.
354 * Pointer to struct rte_vlan_hdr.
357 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
358 struct rte_vlan_hdr *vlan)
361 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
363 ((const struct rte_flow_action_of_set_vlan_pcp *)
364 action->conf)->vlan_pcp;
365 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
366 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
367 vlan->vlan_tci |= vlan_tci;
368 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
369 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
370 vlan->vlan_tci |= rte_be_to_cpu_16
371 (((const struct rte_flow_action_of_set_vlan_vid *)
372 action->conf)->vlan_vid);
377 * Fetch 1, 2, 3 or 4 byte field from the byte array
378 * and return as unsigned integer in host-endian format.
381 * Pointer to data array.
383 * Size of field to extract.
386 * converted field in host endian format.
388 static inline uint32_t
389 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
398 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
401 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
402 ret = (ret << 8) | *(data + sizeof(uint16_t));
405 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
416 * Convert modify-header action to DV specification.
418 * Data length of each action is determined by provided field description
419 * and the item mask. Data bit offset and width of each action is determined
420 * by provided item mask.
423 * Pointer to item specification.
425 * Pointer to field modification information.
426 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
427 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
428 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
430 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
431 * Negative offset value sets the same offset as source offset.
432 * size field is ignored, value is taken from source field.
433 * @param[in,out] resource
434 * Pointer to the modify-header resource.
436 * Type of modification.
438 * Pointer to the error structure.
441 * 0 on success, a negative errno value otherwise and rte_errno is set.
444 flow_dv_convert_modify_action(struct rte_flow_item *item,
445 struct field_modify_info *field,
446 struct field_modify_info *dcopy,
447 struct mlx5_flow_dv_modify_hdr_resource *resource,
448 uint32_t type, struct rte_flow_error *error)
450 uint32_t i = resource->actions_num;
451 struct mlx5_modification_cmd *actions = resource->actions;
452 uint32_t carry_b = 0;
455 * The item and mask are provided in big-endian format.
456 * The fields should be presented as in big-endian format either.
457 * Mask must be always present, it defines the actual field width.
459 MLX5_ASSERT(item->mask);
460 MLX5_ASSERT(field->size);
466 bool next_field = true;
467 bool next_dcopy = true;
469 if (i >= MLX5_MAX_MODIFY_NUM)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "too many items to modify");
473 /* Fetch variable byte size mask from the array. */
474 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
475 field->offset, field->size);
480 /* Deduce actual data width in bits from mask value. */
481 off_b = rte_bsf32(mask) + carry_b;
482 size_b = sizeof(uint32_t) * CHAR_BIT -
483 off_b - __builtin_clz(mask);
485 actions[i] = (struct mlx5_modification_cmd) {
489 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
492 if (type == MLX5_MODIFICATION_TYPE_COPY) {
494 actions[i].dst_field = dcopy->id;
495 actions[i].dst_offset =
496 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
497 /* Convert entire record to big-endian format. */
498 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
500 * Destination field overflow. Copy leftovers of
501 * a source field to the next destination field.
504 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
507 dcopy->size * CHAR_BIT - dcopy->offset;
508 carry_b = actions[i].length;
512 * Not enough bits in a source filed to fill a
513 * destination field. Switch to the next source.
515 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
516 (size_b == field->size * CHAR_BIT - off_b)) {
518 field->size * CHAR_BIT - off_b;
519 dcopy->offset += actions[i].length;
525 MLX5_ASSERT(item->spec);
526 data = flow_dv_fetch_field((const uint8_t *)item->spec +
527 field->offset, field->size);
528 /* Shift out the trailing masked bits from data. */
529 data = (data & mask) >> off_b;
530 actions[i].data1 = rte_cpu_to_be_32(data);
532 /* Convert entire record to expected big-endian format. */
533 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
537 } while (field->size);
538 if (resource->actions_num == i)
539 return rte_flow_error_set(error, EINVAL,
540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
541 "invalid modification flow item");
542 resource->actions_num = i;
547 * Convert modify-header set IPv4 address action to DV specification.
549 * @param[in,out] resource
550 * Pointer to the modify-header resource.
552 * Pointer to action specification.
554 * Pointer to the error structure.
557 * 0 on success, a negative errno value otherwise and rte_errno is set.
560 flow_dv_convert_action_modify_ipv4
561 (struct mlx5_flow_dv_modify_hdr_resource *resource,
562 const struct rte_flow_action *action,
563 struct rte_flow_error *error)
565 const struct rte_flow_action_set_ipv4 *conf =
566 (const struct rte_flow_action_set_ipv4 *)(action->conf);
567 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
568 struct rte_flow_item_ipv4 ipv4;
569 struct rte_flow_item_ipv4 ipv4_mask;
571 memset(&ipv4, 0, sizeof(ipv4));
572 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
573 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
574 ipv4.hdr.src_addr = conf->ipv4_addr;
575 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
577 ipv4.hdr.dst_addr = conf->ipv4_addr;
578 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
581 item.mask = &ipv4_mask;
582 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set IPv6 address action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_ipv6
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_set_ipv6 *conf =
606 (const struct rte_flow_action_set_ipv6 *)(action->conf);
607 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
608 struct rte_flow_item_ipv6 ipv6;
609 struct rte_flow_item_ipv6 ipv6_mask;
611 memset(&ipv6, 0, sizeof(ipv6));
612 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
613 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
614 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
615 sizeof(ipv6.hdr.src_addr));
616 memcpy(&ipv6_mask.hdr.src_addr,
617 &rte_flow_item_ipv6_mask.hdr.src_addr,
618 sizeof(ipv6.hdr.src_addr));
620 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
621 sizeof(ipv6.hdr.dst_addr));
622 memcpy(&ipv6_mask.hdr.dst_addr,
623 &rte_flow_item_ipv6_mask.hdr.dst_addr,
624 sizeof(ipv6.hdr.dst_addr));
627 item.mask = &ipv6_mask;
628 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
629 MLX5_MODIFICATION_TYPE_SET, error);
633 * Convert modify-header set MAC address action to DV specification.
635 * @param[in,out] resource
636 * Pointer to the modify-header resource.
638 * Pointer to action specification.
640 * Pointer to the error structure.
643 * 0 on success, a negative errno value otherwise and rte_errno is set.
646 flow_dv_convert_action_modify_mac
647 (struct mlx5_flow_dv_modify_hdr_resource *resource,
648 const struct rte_flow_action *action,
649 struct rte_flow_error *error)
651 const struct rte_flow_action_set_mac *conf =
652 (const struct rte_flow_action_set_mac *)(action->conf);
653 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
654 struct rte_flow_item_eth eth;
655 struct rte_flow_item_eth eth_mask;
657 memset(ð, 0, sizeof(eth));
658 memset(ð_mask, 0, sizeof(eth_mask));
659 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
660 memcpy(ð.src.addr_bytes, &conf->mac_addr,
661 sizeof(eth.src.addr_bytes));
662 memcpy(ð_mask.src.addr_bytes,
663 &rte_flow_item_eth_mask.src.addr_bytes,
664 sizeof(eth_mask.src.addr_bytes));
666 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
667 sizeof(eth.dst.addr_bytes));
668 memcpy(ð_mask.dst.addr_bytes,
669 &rte_flow_item_eth_mask.dst.addr_bytes,
670 sizeof(eth_mask.dst.addr_bytes));
673 item.mask = ð_mask;
674 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
675 MLX5_MODIFICATION_TYPE_SET, error);
679 * Convert modify-header set VLAN VID action to DV specification.
681 * @param[in,out] resource
682 * Pointer to the modify-header resource.
684 * Pointer to action specification.
686 * Pointer to the error structure.
689 * 0 on success, a negative errno value otherwise and rte_errno is set.
692 flow_dv_convert_action_modify_vlan_vid
693 (struct mlx5_flow_dv_modify_hdr_resource *resource,
694 const struct rte_flow_action *action,
695 struct rte_flow_error *error)
697 const struct rte_flow_action_of_set_vlan_vid *conf =
698 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
699 int i = resource->actions_num;
700 struct mlx5_modification_cmd *actions = resource->actions;
701 struct field_modify_info *field = modify_vlan_out_first_vid;
703 if (i >= MLX5_MAX_MODIFY_NUM)
704 return rte_flow_error_set(error, EINVAL,
705 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
706 "too many items to modify");
707 actions[i] = (struct mlx5_modification_cmd) {
708 .action_type = MLX5_MODIFICATION_TYPE_SET,
710 .length = field->size,
711 .offset = field->offset,
713 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
714 actions[i].data1 = conf->vlan_vid;
715 actions[i].data1 = actions[i].data1 << 16;
716 resource->actions_num = ++i;
721 * Convert modify-header set TP action to DV specification.
723 * @param[in,out] resource
724 * Pointer to the modify-header resource.
726 * Pointer to action specification.
728 * Pointer to rte_flow_item objects list.
730 * Pointer to flow attributes structure.
731 * @param[in] dev_flow
732 * Pointer to the sub flow.
733 * @param[in] tunnel_decap
734 * Whether action is after tunnel decapsulation.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_tp
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_action *action,
745 const struct rte_flow_item *items,
746 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
747 bool tunnel_decap, struct rte_flow_error *error)
749 const struct rte_flow_action_set_tp *conf =
750 (const struct rte_flow_action_set_tp *)(action->conf);
751 struct rte_flow_item item;
752 struct rte_flow_item_udp udp;
753 struct rte_flow_item_udp udp_mask;
754 struct rte_flow_item_tcp tcp;
755 struct rte_flow_item_tcp tcp_mask;
756 struct field_modify_info *field;
759 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
761 memset(&udp, 0, sizeof(udp));
762 memset(&udp_mask, 0, sizeof(udp_mask));
763 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
764 udp.hdr.src_port = conf->port;
765 udp_mask.hdr.src_port =
766 rte_flow_item_udp_mask.hdr.src_port;
768 udp.hdr.dst_port = conf->port;
769 udp_mask.hdr.dst_port =
770 rte_flow_item_udp_mask.hdr.dst_port;
772 item.type = RTE_FLOW_ITEM_TYPE_UDP;
774 item.mask = &udp_mask;
777 MLX5_ASSERT(attr->tcp);
778 memset(&tcp, 0, sizeof(tcp));
779 memset(&tcp_mask, 0, sizeof(tcp_mask));
780 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
781 tcp.hdr.src_port = conf->port;
782 tcp_mask.hdr.src_port =
783 rte_flow_item_tcp_mask.hdr.src_port;
785 tcp.hdr.dst_port = conf->port;
786 tcp_mask.hdr.dst_port =
787 rte_flow_item_tcp_mask.hdr.dst_port;
789 item.type = RTE_FLOW_ITEM_TYPE_TCP;
791 item.mask = &tcp_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header set TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_action *action,
823 const struct rte_flow_item *items,
824 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
825 bool tunnel_decap, struct rte_flow_error *error)
827 const struct rte_flow_action_set_ttl *conf =
828 (const struct rte_flow_action_set_ttl *)(action->conf);
829 struct rte_flow_item item;
830 struct rte_flow_item_ipv4 ipv4;
831 struct rte_flow_item_ipv4 ipv4_mask;
832 struct rte_flow_item_ipv6 ipv6;
833 struct rte_flow_item_ipv6 ipv6_mask;
834 struct field_modify_info *field;
837 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
839 memset(&ipv4, 0, sizeof(ipv4));
840 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
841 ipv4.hdr.time_to_live = conf->ttl_value;
842 ipv4_mask.hdr.time_to_live = 0xFF;
843 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
845 item.mask = &ipv4_mask;
848 MLX5_ASSERT(attr->ipv6);
849 memset(&ipv6, 0, sizeof(ipv6));
850 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
851 ipv6.hdr.hop_limits = conf->ttl_value;
852 ipv6_mask.hdr.hop_limits = 0xFF;
853 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
855 item.mask = &ipv6_mask;
858 return flow_dv_convert_modify_action(&item, field, NULL, resource,
859 MLX5_MODIFICATION_TYPE_SET, error);
863 * Convert modify-header decrement TTL action to DV specification.
865 * @param[in,out] resource
866 * Pointer to the modify-header resource.
868 * Pointer to action specification.
870 * Pointer to rte_flow_item objects list.
872 * Pointer to flow attributes structure.
873 * @param[in] dev_flow
874 * Pointer to the sub flow.
875 * @param[in] tunnel_decap
876 * Whether action is after tunnel decapsulation.
878 * Pointer to the error structure.
881 * 0 on success, a negative errno value otherwise and rte_errno is set.
884 flow_dv_convert_action_modify_dec_ttl
885 (struct mlx5_flow_dv_modify_hdr_resource *resource,
886 const struct rte_flow_item *items,
887 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
888 bool tunnel_decap, struct rte_flow_error *error)
890 struct rte_flow_item item;
891 struct rte_flow_item_ipv4 ipv4;
892 struct rte_flow_item_ipv4 ipv4_mask;
893 struct rte_flow_item_ipv6 ipv6;
894 struct rte_flow_item_ipv6 ipv6_mask;
895 struct field_modify_info *field;
898 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
900 memset(&ipv4, 0, sizeof(ipv4));
901 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
902 ipv4.hdr.time_to_live = 0xFF;
903 ipv4_mask.hdr.time_to_live = 0xFF;
904 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
906 item.mask = &ipv4_mask;
909 MLX5_ASSERT(attr->ipv6);
910 memset(&ipv6, 0, sizeof(ipv6));
911 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
912 ipv6.hdr.hop_limits = 0xFF;
913 ipv6_mask.hdr.hop_limits = 0xFF;
914 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
916 item.mask = &ipv6_mask;
919 return flow_dv_convert_modify_action(&item, field, NULL, resource,
920 MLX5_MODIFICATION_TYPE_ADD, error);
924 * Convert modify-header increment/decrement TCP Sequence number
925 * to DV specification.
927 * @param[in,out] resource
928 * Pointer to the modify-header resource.
930 * Pointer to action specification.
932 * Pointer to the error structure.
935 * 0 on success, a negative errno value otherwise and rte_errno is set.
938 flow_dv_convert_action_modify_tcp_seq
939 (struct mlx5_flow_dv_modify_hdr_resource *resource,
940 const struct rte_flow_action *action,
941 struct rte_flow_error *error)
943 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
944 uint64_t value = rte_be_to_cpu_32(*conf);
945 struct rte_flow_item item;
946 struct rte_flow_item_tcp tcp;
947 struct rte_flow_item_tcp tcp_mask;
949 memset(&tcp, 0, sizeof(tcp));
950 memset(&tcp_mask, 0, sizeof(tcp_mask));
951 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
953 * The HW has no decrement operation, only increment operation.
954 * To simulate decrement X from Y using increment operation
955 * we need to add UINT32_MAX X times to Y.
956 * Each adding of UINT32_MAX decrements Y by 1.
959 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
960 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
961 item.type = RTE_FLOW_ITEM_TYPE_TCP;
963 item.mask = &tcp_mask;
964 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
965 MLX5_MODIFICATION_TYPE_ADD, error);
969 * Convert modify-header increment/decrement TCP Acknowledgment number
970 * to DV specification.
972 * @param[in,out] resource
973 * Pointer to the modify-header resource.
975 * Pointer to action specification.
977 * Pointer to the error structure.
980 * 0 on success, a negative errno value otherwise and rte_errno is set.
983 flow_dv_convert_action_modify_tcp_ack
984 (struct mlx5_flow_dv_modify_hdr_resource *resource,
985 const struct rte_flow_action *action,
986 struct rte_flow_error *error)
988 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
989 uint64_t value = rte_be_to_cpu_32(*conf);
990 struct rte_flow_item item;
991 struct rte_flow_item_tcp tcp;
992 struct rte_flow_item_tcp tcp_mask;
994 memset(&tcp, 0, sizeof(tcp));
995 memset(&tcp_mask, 0, sizeof(tcp_mask));
996 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
998 * The HW has no decrement operation, only increment operation.
999 * To simulate decrement X from Y using increment operation
1000 * we need to add UINT32_MAX X times to Y.
1001 * Each adding of UINT32_MAX decrements Y by 1.
1003 value *= UINT32_MAX;
1004 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1005 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1006 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1008 item.mask = &tcp_mask;
1009 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1010 MLX5_MODIFICATION_TYPE_ADD, error);
1013 static enum mlx5_modification_field reg_to_field[] = {
1014 [REG_NON] = MLX5_MODI_OUT_NONE,
1015 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1016 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1017 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1018 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1019 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1020 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1021 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1022 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1023 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1024 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1028 * Convert register set to DV specification.
1030 * @param[in,out] resource
1031 * Pointer to the modify-header resource.
1033 * Pointer to action specification.
1035 * Pointer to the error structure.
1038 * 0 on success, a negative errno value otherwise and rte_errno is set.
1041 flow_dv_convert_action_set_reg
1042 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1043 const struct rte_flow_action *action,
1044 struct rte_flow_error *error)
1046 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1047 struct mlx5_modification_cmd *actions = resource->actions;
1048 uint32_t i = resource->actions_num;
1050 if (i >= MLX5_MAX_MODIFY_NUM)
1051 return rte_flow_error_set(error, EINVAL,
1052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1053 "too many items to modify");
1054 MLX5_ASSERT(conf->id != REG_NON);
1055 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1056 actions[i] = (struct mlx5_modification_cmd) {
1057 .action_type = MLX5_MODIFICATION_TYPE_SET,
1058 .field = reg_to_field[conf->id],
1059 .offset = conf->offset,
1060 .length = conf->length,
1062 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1063 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1065 resource->actions_num = i;
1070 * Convert SET_TAG action to DV specification.
1073 * Pointer to the rte_eth_dev structure.
1074 * @param[in,out] resource
1075 * Pointer to the modify-header resource.
1077 * Pointer to action specification.
1079 * Pointer to the error structure.
1082 * 0 on success, a negative errno value otherwise and rte_errno is set.
1085 flow_dv_convert_action_set_tag
1086 (struct rte_eth_dev *dev,
1087 struct mlx5_flow_dv_modify_hdr_resource *resource,
1088 const struct rte_flow_action_set_tag *conf,
1089 struct rte_flow_error *error)
1091 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1092 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1093 struct rte_flow_item item = {
1097 struct field_modify_info reg_c_x[] = {
1100 enum mlx5_modification_field reg_type;
1103 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1106 MLX5_ASSERT(ret != REG_NON);
1107 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1108 reg_type = reg_to_field[ret];
1109 MLX5_ASSERT(reg_type > 0);
1110 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1111 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1112 MLX5_MODIFICATION_TYPE_SET, error);
1116 * Convert internal COPY_REG action to DV specification.
1119 * Pointer to the rte_eth_dev structure.
1120 * @param[in,out] res
1121 * Pointer to the modify-header resource.
1123 * Pointer to action specification.
1125 * Pointer to the error structure.
1128 * 0 on success, a negative errno value otherwise and rte_errno is set.
1131 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1132 struct mlx5_flow_dv_modify_hdr_resource *res,
1133 const struct rte_flow_action *action,
1134 struct rte_flow_error *error)
1136 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1137 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1138 struct rte_flow_item item = {
1142 struct field_modify_info reg_src[] = {
1143 {4, 0, reg_to_field[conf->src]},
1146 struct field_modify_info reg_dst = {
1148 .id = reg_to_field[conf->dst],
1150 /* Adjust reg_c[0] usage according to reported mask. */
1151 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1152 struct mlx5_priv *priv = dev->data->dev_private;
1153 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1155 MLX5_ASSERT(reg_c0);
1156 MLX5_ASSERT(priv->sh->config.dv_xmeta_en !=
1157 MLX5_XMETA_MODE_LEGACY);
1158 if (conf->dst == REG_C_0) {
1159 /* Copy to reg_c[0], within mask only. */
1160 reg_dst.offset = rte_bsf32(reg_c0);
1161 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1164 mask = rte_cpu_to_be_32(reg_c0);
1167 return flow_dv_convert_modify_action(&item,
1168 reg_src, ®_dst, res,
1169 MLX5_MODIFICATION_TYPE_COPY,
1174 * Convert MARK action to DV specification. This routine is used
1175 * in extensive metadata only and requires metadata register to be
1176 * handled. In legacy mode hardware tag resource is engaged.
1179 * Pointer to the rte_eth_dev structure.
1181 * Pointer to MARK action specification.
1182 * @param[in,out] resource
1183 * Pointer to the modify-header resource.
1185 * Pointer to the error structure.
1188 * 0 on success, a negative errno value otherwise and rte_errno is set.
1191 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1192 const struct rte_flow_action_mark *conf,
1193 struct mlx5_flow_dv_modify_hdr_resource *resource,
1194 struct rte_flow_error *error)
1196 struct mlx5_priv *priv = dev->data->dev_private;
1197 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1198 priv->sh->dv_mark_mask);
1199 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1200 struct rte_flow_item item = {
1204 struct field_modify_info reg_c_x[] = {
1210 return rte_flow_error_set(error, EINVAL,
1211 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1212 NULL, "zero mark action mask");
1213 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1216 MLX5_ASSERT(reg > 0);
1217 if (reg == REG_C_0) {
1218 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1219 uint32_t shl_c0 = rte_bsf32(msk_c0);
1221 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1222 mask = rte_cpu_to_be_32(mask) & msk_c0;
1223 mask = rte_cpu_to_be_32(mask << shl_c0);
1225 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1226 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1227 MLX5_MODIFICATION_TYPE_SET, error);
1231 * Get metadata register index for specified steering domain.
1234 * Pointer to the rte_eth_dev structure.
1236 * Attributes of flow to determine steering domain.
1238 * Pointer to the error structure.
1241 * positive index on success, a negative errno value otherwise
1242 * and rte_errno is set.
1244 static enum modify_reg
1245 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1246 const struct rte_flow_attr *attr,
1247 struct rte_flow_error *error)
1250 mlx5_flow_get_reg_id(dev, attr->transfer ?
1254 MLX5_METADATA_RX, 0, error);
1256 return rte_flow_error_set(error,
1257 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1258 NULL, "unavailable "
1259 "metadata register");
1264 * Convert SET_META action to DV specification.
1267 * Pointer to the rte_eth_dev structure.
1268 * @param[in,out] resource
1269 * Pointer to the modify-header resource.
1271 * Attributes of flow that includes this item.
1273 * Pointer to action specification.
1275 * Pointer to the error structure.
1278 * 0 on success, a negative errno value otherwise and rte_errno is set.
1281 flow_dv_convert_action_set_meta
1282 (struct rte_eth_dev *dev,
1283 struct mlx5_flow_dv_modify_hdr_resource *resource,
1284 const struct rte_flow_attr *attr,
1285 const struct rte_flow_action_set_meta *conf,
1286 struct rte_flow_error *error)
1288 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1289 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1290 struct rte_flow_item item = {
1294 struct field_modify_info reg_c_x[] = {
1297 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1301 MLX5_ASSERT(reg != REG_NON);
1302 if (reg == REG_C_0) {
1303 struct mlx5_priv *priv = dev->data->dev_private;
1304 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1305 uint32_t shl_c0 = rte_bsf32(msk_c0);
1307 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1308 mask = rte_cpu_to_be_32(mask) & msk_c0;
1309 mask = rte_cpu_to_be_32(mask << shl_c0);
1311 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1312 /* The routine expects parameters in memory as big-endian ones. */
1313 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1314 MLX5_MODIFICATION_TYPE_SET, error);
1318 * Convert modify-header set IPv4 DSCP action to DV specification.
1320 * @param[in,out] resource
1321 * Pointer to the modify-header resource.
1323 * Pointer to action specification.
1325 * Pointer to the error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_convert_action_modify_ipv4_dscp
1332 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333 const struct rte_flow_action *action,
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action_set_dscp *conf =
1337 (const struct rte_flow_action_set_dscp *)(action->conf);
1338 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1339 struct rte_flow_item_ipv4 ipv4;
1340 struct rte_flow_item_ipv4 ipv4_mask;
1342 memset(&ipv4, 0, sizeof(ipv4));
1343 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1344 ipv4.hdr.type_of_service = conf->dscp;
1345 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1347 item.mask = &ipv4_mask;
1348 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1349 MLX5_MODIFICATION_TYPE_SET, error);
1353 * Convert modify-header set IPv6 DSCP action to DV specification.
1355 * @param[in,out] resource
1356 * Pointer to the modify-header resource.
1358 * Pointer to action specification.
1360 * Pointer to the error structure.
1363 * 0 on success, a negative errno value otherwise and rte_errno is set.
1366 flow_dv_convert_action_modify_ipv6_dscp
1367 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1368 const struct rte_flow_action *action,
1369 struct rte_flow_error *error)
1371 const struct rte_flow_action_set_dscp *conf =
1372 (const struct rte_flow_action_set_dscp *)(action->conf);
1373 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1374 struct rte_flow_item_ipv6 ipv6;
1375 struct rte_flow_item_ipv6 ipv6_mask;
1377 memset(&ipv6, 0, sizeof(ipv6));
1378 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1380 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1381 * rdma-core only accept the DSCP bits byte aligned start from
1382 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1383 * bits in IPv6 case as rdma-core requires byte aligned value.
1385 ipv6.hdr.vtc_flow = conf->dscp;
1386 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1388 item.mask = &ipv6_mask;
1389 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1390 MLX5_MODIFICATION_TYPE_SET, error);
1394 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1395 enum rte_flow_field_id field, int inherit,
1396 const struct rte_flow_attr *attr,
1397 struct rte_flow_error *error)
1399 struct mlx5_priv *priv = dev->data->dev_private;
1402 case RTE_FLOW_FIELD_START:
1404 case RTE_FLOW_FIELD_MAC_DST:
1405 case RTE_FLOW_FIELD_MAC_SRC:
1407 case RTE_FLOW_FIELD_VLAN_TYPE:
1409 case RTE_FLOW_FIELD_VLAN_ID:
1411 case RTE_FLOW_FIELD_MAC_TYPE:
1413 case RTE_FLOW_FIELD_IPV4_DSCP:
1415 case RTE_FLOW_FIELD_IPV4_TTL:
1417 case RTE_FLOW_FIELD_IPV4_SRC:
1418 case RTE_FLOW_FIELD_IPV4_DST:
1420 case RTE_FLOW_FIELD_IPV6_DSCP:
1422 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1424 case RTE_FLOW_FIELD_IPV6_SRC:
1425 case RTE_FLOW_FIELD_IPV6_DST:
1427 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1428 case RTE_FLOW_FIELD_TCP_PORT_DST:
1430 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1431 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1433 case RTE_FLOW_FIELD_TCP_FLAGS:
1435 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1436 case RTE_FLOW_FIELD_UDP_PORT_DST:
1438 case RTE_FLOW_FIELD_VXLAN_VNI:
1439 case RTE_FLOW_FIELD_GENEVE_VNI:
1441 case RTE_FLOW_FIELD_GTP_TEID:
1442 case RTE_FLOW_FIELD_TAG:
1444 case RTE_FLOW_FIELD_MARK:
1445 return __builtin_popcount(priv->sh->dv_mark_mask);
1446 case RTE_FLOW_FIELD_META:
1447 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1448 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1449 case RTE_FLOW_FIELD_POINTER:
1450 case RTE_FLOW_FIELD_VALUE:
1451 return inherit < 0 ? 0 : inherit;
1459 mlx5_flow_field_id_to_modify_info
1460 (const struct rte_flow_action_modify_data *data,
1461 struct field_modify_info *info, uint32_t *mask,
1462 uint32_t width, struct rte_eth_dev *dev,
1463 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1465 struct mlx5_priv *priv = dev->data->dev_private;
1469 switch (data->field) {
1470 case RTE_FLOW_FIELD_START:
1471 /* not supported yet */
1474 case RTE_FLOW_FIELD_MAC_DST:
1475 off = data->offset > 16 ? data->offset - 16 : 0;
1477 if (data->offset < 16) {
1478 info[idx] = (struct field_modify_info){2, 4,
1479 MLX5_MODI_OUT_DMAC_15_0};
1481 mask[1] = rte_cpu_to_be_16(0xffff >>
1485 mask[1] = RTE_BE16(0xffff);
1492 info[idx] = (struct field_modify_info){4, 0,
1493 MLX5_MODI_OUT_DMAC_47_16};
1494 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1495 (32 - width)) << off);
1497 if (data->offset < 16)
1498 info[idx++] = (struct field_modify_info){2, 0,
1499 MLX5_MODI_OUT_DMAC_15_0};
1500 info[idx] = (struct field_modify_info){4, off,
1501 MLX5_MODI_OUT_DMAC_47_16};
1504 case RTE_FLOW_FIELD_MAC_SRC:
1505 off = data->offset > 16 ? data->offset - 16 : 0;
1507 if (data->offset < 16) {
1508 info[idx] = (struct field_modify_info){2, 4,
1509 MLX5_MODI_OUT_SMAC_15_0};
1511 mask[1] = rte_cpu_to_be_16(0xffff >>
1515 mask[1] = RTE_BE16(0xffff);
1522 info[idx] = (struct field_modify_info){4, 0,
1523 MLX5_MODI_OUT_SMAC_47_16};
1524 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1525 (32 - width)) << off);
1527 if (data->offset < 16)
1528 info[idx++] = (struct field_modify_info){2, 0,
1529 MLX5_MODI_OUT_SMAC_15_0};
1530 info[idx] = (struct field_modify_info){4, off,
1531 MLX5_MODI_OUT_SMAC_47_16};
1534 case RTE_FLOW_FIELD_VLAN_TYPE:
1535 /* not supported yet */
1537 case RTE_FLOW_FIELD_VLAN_ID:
1538 info[idx] = (struct field_modify_info){2, 0,
1539 MLX5_MODI_OUT_FIRST_VID};
1541 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1543 case RTE_FLOW_FIELD_MAC_TYPE:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_ETHERTYPE};
1547 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1549 case RTE_FLOW_FIELD_IPV4_DSCP:
1550 info[idx] = (struct field_modify_info){1, 0,
1551 MLX5_MODI_OUT_IP_DSCP};
1553 mask[idx] = 0x3f >> (6 - width);
1555 case RTE_FLOW_FIELD_IPV4_TTL:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IPV4_TTL};
1559 mask[idx] = 0xff >> (8 - width);
1561 case RTE_FLOW_FIELD_IPV4_SRC:
1562 info[idx] = (struct field_modify_info){4, 0,
1563 MLX5_MODI_OUT_SIPV4};
1565 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1568 case RTE_FLOW_FIELD_IPV4_DST:
1569 info[idx] = (struct field_modify_info){4, 0,
1570 MLX5_MODI_OUT_DIPV4};
1572 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1575 case RTE_FLOW_FIELD_IPV6_DSCP:
1576 info[idx] = (struct field_modify_info){1, 0,
1577 MLX5_MODI_OUT_IP_DSCP};
1579 mask[idx] = 0x3f >> (6 - width);
1581 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1585 mask[idx] = 0xff >> (8 - width);
1587 case RTE_FLOW_FIELD_IPV6_SRC:
1589 if (data->offset < 32) {
1590 info[idx] = (struct field_modify_info){4, 12,
1591 MLX5_MODI_OUT_SIPV6_31_0};
1594 rte_cpu_to_be_32(0xffffffff >>
1598 mask[3] = RTE_BE32(0xffffffff);
1605 if (data->offset < 64) {
1606 info[idx] = (struct field_modify_info){4, 8,
1607 MLX5_MODI_OUT_SIPV6_63_32};
1610 rte_cpu_to_be_32(0xffffffff >>
1614 mask[2] = RTE_BE32(0xffffffff);
1621 if (data->offset < 96) {
1622 info[idx] = (struct field_modify_info){4, 4,
1623 MLX5_MODI_OUT_SIPV6_95_64};
1626 rte_cpu_to_be_32(0xffffffff >>
1630 mask[1] = RTE_BE32(0xffffffff);
1637 info[idx] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_SIPV6_127_96};
1639 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1641 if (data->offset < 32)
1642 info[idx++] = (struct field_modify_info){4, 0,
1643 MLX5_MODI_OUT_SIPV6_31_0};
1644 if (data->offset < 64)
1645 info[idx++] = (struct field_modify_info){4, 0,
1646 MLX5_MODI_OUT_SIPV6_63_32};
1647 if (data->offset < 96)
1648 info[idx++] = (struct field_modify_info){4, 0,
1649 MLX5_MODI_OUT_SIPV6_95_64};
1650 if (data->offset < 128)
1651 info[idx++] = (struct field_modify_info){4, 0,
1652 MLX5_MODI_OUT_SIPV6_127_96};
1655 case RTE_FLOW_FIELD_IPV6_DST:
1657 if (data->offset < 32) {
1658 info[idx] = (struct field_modify_info){4, 12,
1659 MLX5_MODI_OUT_DIPV6_31_0};
1662 rte_cpu_to_be_32(0xffffffff >>
1666 mask[3] = RTE_BE32(0xffffffff);
1673 if (data->offset < 64) {
1674 info[idx] = (struct field_modify_info){4, 8,
1675 MLX5_MODI_OUT_DIPV6_63_32};
1678 rte_cpu_to_be_32(0xffffffff >>
1682 mask[2] = RTE_BE32(0xffffffff);
1689 if (data->offset < 96) {
1690 info[idx] = (struct field_modify_info){4, 4,
1691 MLX5_MODI_OUT_DIPV6_95_64};
1694 rte_cpu_to_be_32(0xffffffff >>
1698 mask[1] = RTE_BE32(0xffffffff);
1705 info[idx] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_127_96};
1707 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1709 if (data->offset < 32)
1710 info[idx++] = (struct field_modify_info){4, 0,
1711 MLX5_MODI_OUT_DIPV6_31_0};
1712 if (data->offset < 64)
1713 info[idx++] = (struct field_modify_info){4, 0,
1714 MLX5_MODI_OUT_DIPV6_63_32};
1715 if (data->offset < 96)
1716 info[idx++] = (struct field_modify_info){4, 0,
1717 MLX5_MODI_OUT_DIPV6_95_64};
1718 if (data->offset < 128)
1719 info[idx++] = (struct field_modify_info){4, 0,
1720 MLX5_MODI_OUT_DIPV6_127_96};
1723 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1724 info[idx] = (struct field_modify_info){2, 0,
1725 MLX5_MODI_OUT_TCP_SPORT};
1727 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1729 case RTE_FLOW_FIELD_TCP_PORT_DST:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_DPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1736 info[idx] = (struct field_modify_info){4, 0,
1737 MLX5_MODI_OUT_TCP_SEQ_NUM};
1739 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1742 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1743 info[idx] = (struct field_modify_info){4, 0,
1744 MLX5_MODI_OUT_TCP_ACK_NUM};
1746 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1749 case RTE_FLOW_FIELD_TCP_FLAGS:
1750 info[idx] = (struct field_modify_info){2, 0,
1751 MLX5_MODI_OUT_TCP_FLAGS};
1753 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1755 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_UDP_SPORT};
1759 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_DST:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_DPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_VXLAN_VNI:
1768 /* not supported yet */
1770 case RTE_FLOW_FIELD_GENEVE_VNI:
1771 /* not supported yet*/
1773 case RTE_FLOW_FIELD_GTP_TEID:
1774 info[idx] = (struct field_modify_info){4, 0,
1775 MLX5_MODI_GTP_TEID};
1777 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1780 case RTE_FLOW_FIELD_TAG:
1782 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1783 data->level, error);
1786 MLX5_ASSERT(reg != REG_NON);
1787 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1788 info[idx] = (struct field_modify_info){4, 0,
1792 rte_cpu_to_be_32(0xffffffff >>
1796 case RTE_FLOW_FIELD_MARK:
1798 uint32_t mark_mask = priv->sh->dv_mark_mask;
1799 uint32_t mark_count = __builtin_popcount(mark_mask);
1800 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1804 MLX5_ASSERT(reg != REG_NON);
1805 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1806 info[idx] = (struct field_modify_info){4, 0,
1809 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1810 (mark_count - width)) & mark_mask);
1813 case RTE_FLOW_FIELD_META:
1815 uint32_t meta_mask = priv->sh->dv_meta_mask;
1816 uint32_t meta_count = __builtin_popcount(meta_mask);
1817 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1820 MLX5_ASSERT(reg != REG_NON);
1821 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1822 info[idx] = (struct field_modify_info){4, 0,
1825 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1826 (meta_count - width)) & meta_mask);
1829 case RTE_FLOW_FIELD_POINTER:
1830 case RTE_FLOW_FIELD_VALUE:
1838 * Convert modify_field action to DV specification.
1841 * Pointer to the rte_eth_dev structure.
1842 * @param[in,out] resource
1843 * Pointer to the modify-header resource.
1845 * Pointer to action specification.
1847 * Attributes of flow that includes this item.
1849 * Pointer to the error structure.
1852 * 0 on success, a negative errno value otherwise and rte_errno is set.
1855 flow_dv_convert_action_modify_field
1856 (struct rte_eth_dev *dev,
1857 struct mlx5_flow_dv_modify_hdr_resource *resource,
1858 const struct rte_flow_action *action,
1859 const struct rte_flow_attr *attr,
1860 struct rte_flow_error *error)
1862 const struct rte_flow_action_modify_field *conf =
1863 (const struct rte_flow_action_modify_field *)(action->conf);
1864 struct rte_flow_item item = {
1868 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1870 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1872 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1873 uint32_t type, meta = 0;
1875 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1876 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1877 type = MLX5_MODIFICATION_TYPE_SET;
1878 /** For SET fill the destination field (field) first. */
1879 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1882 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1883 (void *)(uintptr_t)conf->src.pvalue :
1884 (void *)(uintptr_t)&conf->src.value;
1885 if (conf->dst.field == RTE_FLOW_FIELD_META) {
1886 meta = *(const unaligned_uint32_t *)item.spec;
1887 meta = rte_cpu_to_be_32(meta);
1891 type = MLX5_MODIFICATION_TYPE_COPY;
1892 /** For COPY fill the destination field (dcopy) without mask. */
1893 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1896 /** Then construct the source field (field) with mask. */
1897 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1902 return flow_dv_convert_modify_action(&item,
1903 field, dcopy, resource, type, error);
1907 * Validate MARK item.
1910 * Pointer to the rte_eth_dev structure.
1912 * Item specification.
1914 * Attributes of flow that includes this item.
1916 * Pointer to error structure.
1919 * 0 on success, a negative errno value otherwise and rte_errno is set.
1922 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1923 const struct rte_flow_item *item,
1924 const struct rte_flow_attr *attr __rte_unused,
1925 struct rte_flow_error *error)
1927 struct mlx5_priv *priv = dev->data->dev_private;
1928 struct mlx5_sh_config *config = &priv->sh->config;
1929 const struct rte_flow_item_mark *spec = item->spec;
1930 const struct rte_flow_item_mark *mask = item->mask;
1931 const struct rte_flow_item_mark nic_mask = {
1932 .id = priv->sh->dv_mark_mask,
1936 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "extended metadata feature"
1941 if (!mlx5_flow_ext_mreg_supported(dev))
1942 return rte_flow_error_set(error, ENOTSUP,
1943 RTE_FLOW_ERROR_TYPE_ITEM, item,
1944 "extended metadata register"
1945 " isn't supported");
1947 return rte_flow_error_set(error, ENOTSUP,
1948 RTE_FLOW_ERROR_TYPE_ITEM, item,
1949 "extended metadata register"
1950 " isn't available");
1951 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1955 return rte_flow_error_set(error, EINVAL,
1956 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1958 "data cannot be empty");
1959 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1960 return rte_flow_error_set(error, EINVAL,
1961 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1963 "mark id exceeds the limit");
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1969 "mask cannot be zero");
1971 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1972 (const uint8_t *)&nic_mask,
1973 sizeof(struct rte_flow_item_mark),
1974 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1981 * Validate META item.
1984 * Pointer to the rte_eth_dev structure.
1986 * Item specification.
1988 * Attributes of flow that includes this item.
1990 * Pointer to error structure.
1993 * 0 on success, a negative errno value otherwise and rte_errno is set.
1996 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1997 const struct rte_flow_item *item,
1998 const struct rte_flow_attr *attr,
1999 struct rte_flow_error *error)
2001 struct mlx5_priv *priv = dev->data->dev_private;
2002 struct mlx5_sh_config *config = &priv->sh->config;
2003 const struct rte_flow_item_meta *spec = item->spec;
2004 const struct rte_flow_item_meta *mask = item->mask;
2005 struct rte_flow_item_meta nic_mask = {
2012 return rte_flow_error_set(error, EINVAL,
2013 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2015 "data cannot be empty");
2016 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2017 if (!mlx5_flow_ext_mreg_supported(dev))
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ITEM, item,
2020 "extended metadata register"
2021 " isn't supported");
2022 reg = flow_dv_get_metadata_reg(dev, attr, error);
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ITEM, item,
2028 "unavailable extended metadata register");
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 nic_mask.data = priv->sh->dv_meta_mask;
2038 return rte_flow_error_set(error, ENOTSUP,
2039 RTE_FLOW_ERROR_TYPE_ITEM, item,
2040 "extended metadata feature "
2041 "should be enabled when "
2042 "meta item is requested "
2043 "with e-switch mode ");
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "match on metadata for ingress "
2048 "is not supported in legacy "
2052 mask = &rte_flow_item_meta_mask;
2054 return rte_flow_error_set(error, EINVAL,
2055 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2056 "mask cannot be zero");
2058 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2059 (const uint8_t *)&nic_mask,
2060 sizeof(struct rte_flow_item_meta),
2061 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066 * Validate TAG item.
2069 * Pointer to the rte_eth_dev structure.
2071 * Item specification.
2073 * Attributes of flow that includes this item.
2075 * Pointer to error structure.
2078 * 0 on success, a negative errno value otherwise and rte_errno is set.
2081 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2082 const struct rte_flow_item *item,
2083 const struct rte_flow_attr *attr __rte_unused,
2084 struct rte_flow_error *error)
2086 const struct rte_flow_item_tag *spec = item->spec;
2087 const struct rte_flow_item_tag *mask = item->mask;
2088 const struct rte_flow_item_tag nic_mask = {
2089 .data = RTE_BE32(UINT32_MAX),
2094 if (!mlx5_flow_ext_mreg_supported(dev))
2095 return rte_flow_error_set(error, ENOTSUP,
2096 RTE_FLOW_ERROR_TYPE_ITEM, item,
2097 "extensive metadata register"
2098 " isn't supported");
2100 return rte_flow_error_set(error, EINVAL,
2101 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2103 "data cannot be empty");
2105 mask = &rte_flow_item_tag_mask;
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2109 "mask cannot be zero");
2111 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2112 (const uint8_t *)&nic_mask,
2113 sizeof(struct rte_flow_item_tag),
2114 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2117 if (mask->index != 0xff)
2118 return rte_flow_error_set(error, EINVAL,
2119 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2120 "partial mask for tag index"
2121 " is not supported");
2122 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2125 MLX5_ASSERT(ret != REG_NON);
2130 * Validate vport item.
2133 * Pointer to the rte_eth_dev structure.
2135 * Item specification.
2137 * Attributes of flow that includes this item.
2138 * @param[in] item_flags
2139 * Bit-fields that holds the items detected until now.
2141 * Pointer to error structure.
2144 * 0 on success, a negative errno value otherwise and rte_errno is set.
2147 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2148 const struct rte_flow_item *item,
2149 const struct rte_flow_attr *attr,
2150 uint64_t item_flags,
2151 struct rte_flow_error *error)
2153 const struct rte_flow_item_port_id *spec = item->spec;
2154 const struct rte_flow_item_port_id *mask = item->mask;
2155 const struct rte_flow_item_port_id switch_mask = {
2158 struct mlx5_priv *esw_priv;
2159 struct mlx5_priv *dev_priv;
2162 if (!attr->transfer)
2163 return rte_flow_error_set(error, EINVAL,
2164 RTE_FLOW_ERROR_TYPE_ITEM,
2166 "match on port id is valid only"
2167 " when transfer flag is enabled");
2168 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2169 return rte_flow_error_set(error, ENOTSUP,
2170 RTE_FLOW_ERROR_TYPE_ITEM, item,
2171 "multiple source ports are not"
2174 mask = &switch_mask;
2175 if (mask->id != 0xffffffff)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2179 "no support for partial mask on"
2181 ret = mlx5_flow_item_acceptable
2182 (item, (const uint8_t *)mask,
2183 (const uint8_t *)&rte_flow_item_port_id_mask,
2184 sizeof(struct rte_flow_item_port_id),
2185 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2190 if (spec->id == MLX5_PORT_ESW_MGR)
2192 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2194 return rte_flow_error_set(error, rte_errno,
2195 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2196 "failed to obtain E-Switch info for"
2198 dev_priv = mlx5_dev_to_eswitch_info(dev);
2200 return rte_flow_error_set(error, rte_errno,
2201 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2203 "failed to obtain E-Switch info");
2204 if (esw_priv->domain_id != dev_priv->domain_id)
2205 return rte_flow_error_set(error, EINVAL,
2206 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2207 "cannot match on a port from a"
2208 " different E-Switch");
2213 * Validate VLAN item.
2216 * Item specification.
2217 * @param[in] item_flags
2218 * Bit-fields that holds the items detected until now.
2220 * Ethernet device flow is being created on.
2222 * Pointer to error structure.
2225 * 0 on success, a negative errno value otherwise and rte_errno is set.
2228 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2229 uint64_t item_flags,
2230 struct rte_eth_dev *dev,
2231 struct rte_flow_error *error)
2233 const struct rte_flow_item_vlan *mask = item->mask;
2234 const struct rte_flow_item_vlan nic_mask = {
2235 .tci = RTE_BE16(UINT16_MAX),
2236 .inner_type = RTE_BE16(UINT16_MAX),
2239 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2241 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2242 MLX5_FLOW_LAYER_INNER_L4) :
2243 (MLX5_FLOW_LAYER_OUTER_L3 |
2244 MLX5_FLOW_LAYER_OUTER_L4);
2245 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2246 MLX5_FLOW_LAYER_OUTER_VLAN;
2248 if (item_flags & vlanm)
2249 return rte_flow_error_set(error, EINVAL,
2250 RTE_FLOW_ERROR_TYPE_ITEM, item,
2251 "multiple VLAN layers not supported");
2252 else if ((item_flags & l34m) != 0)
2253 return rte_flow_error_set(error, EINVAL,
2254 RTE_FLOW_ERROR_TYPE_ITEM, item,
2255 "VLAN cannot follow L3/L4 layer");
2257 mask = &rte_flow_item_vlan_mask;
2258 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2259 (const uint8_t *)&nic_mask,
2260 sizeof(struct rte_flow_item_vlan),
2261 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2264 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2265 struct mlx5_priv *priv = dev->data->dev_private;
2267 if (priv->vmwa_context) {
2269 * Non-NULL context means we have a virtual machine
2270 * and SR-IOV enabled, we have to create VLAN interface
2271 * to make hypervisor to setup E-Switch vport
2272 * context correctly. We avoid creating the multiple
2273 * VLAN interfaces, so we cannot support VLAN tag mask.
2275 return rte_flow_error_set(error, EINVAL,
2276 RTE_FLOW_ERROR_TYPE_ITEM,
2278 "VLAN tag mask is not"
2279 " supported in virtual"
2287 * GTP flags are contained in 1 byte of the format:
2288 * -------------------------------------------
2289 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2290 * |-----------------------------------------|
2291 * | value | Version | PT | Res | E | S | PN |
2292 * -------------------------------------------
2294 * Matching is supported only for GTP flags E, S, PN.
2296 #define MLX5_GTP_FLAGS_MASK 0x07
2299 * Validate GTP item.
2302 * Pointer to the rte_eth_dev structure.
2304 * Item specification.
2305 * @param[in] item_flags
2306 * Bit-fields that holds the items detected until now.
2308 * Pointer to error structure.
2311 * 0 on success, a negative errno value otherwise and rte_errno is set.
2314 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2315 const struct rte_flow_item *item,
2316 uint64_t item_flags,
2317 struct rte_flow_error *error)
2319 struct mlx5_priv *priv = dev->data->dev_private;
2320 const struct rte_flow_item_gtp *spec = item->spec;
2321 const struct rte_flow_item_gtp *mask = item->mask;
2322 const struct rte_flow_item_gtp nic_mask = {
2323 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2325 .teid = RTE_BE32(0xffffffff),
2328 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_gtp)
2329 return rte_flow_error_set(error, ENOTSUP,
2330 RTE_FLOW_ERROR_TYPE_ITEM, item,
2331 "GTP support is not enabled");
2332 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2333 return rte_flow_error_set(error, ENOTSUP,
2334 RTE_FLOW_ERROR_TYPE_ITEM, item,
2335 "multiple tunnel layers not"
2337 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2338 return rte_flow_error_set(error, EINVAL,
2339 RTE_FLOW_ERROR_TYPE_ITEM, item,
2340 "no outer UDP layer found");
2342 mask = &rte_flow_item_gtp_mask;
2343 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2344 return rte_flow_error_set(error, ENOTSUP,
2345 RTE_FLOW_ERROR_TYPE_ITEM, item,
2346 "Match is supported for GTP"
2348 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2349 (const uint8_t *)&nic_mask,
2350 sizeof(struct rte_flow_item_gtp),
2351 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2355 * Validate GTP PSC item.
2358 * Item specification.
2359 * @param[in] last_item
2360 * Previous validated item in the pattern items.
2361 * @param[in] gtp_item
2362 * Previous GTP item specification.
2364 * Pointer to flow attributes.
2366 * Pointer to error structure.
2369 * 0 on success, a negative errno value otherwise and rte_errno is set.
2372 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2374 const struct rte_flow_item *gtp_item,
2375 const struct rte_flow_attr *attr,
2376 struct rte_flow_error *error)
2378 const struct rte_flow_item_gtp *gtp_spec;
2379 const struct rte_flow_item_gtp *gtp_mask;
2380 const struct rte_flow_item_gtp_psc *mask;
2381 const struct rte_flow_item_gtp_psc nic_mask = {
2386 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2387 return rte_flow_error_set
2388 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2389 "GTP PSC item must be preceded with GTP item");
2390 gtp_spec = gtp_item->spec;
2391 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2392 /* GTP spec and E flag is requested to match zero. */
2394 (gtp_mask->v_pt_rsv_flags &
2395 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2396 return rte_flow_error_set
2397 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2398 "GTP E flag must be 1 to match GTP PSC");
2399 /* Check the flow is not created in group zero. */
2400 if (!attr->transfer && !attr->group)
2401 return rte_flow_error_set
2402 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2403 "GTP PSC is not supported for group 0");
2404 /* GTP spec is here and E flag is requested to match zero. */
2407 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2408 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2409 (const uint8_t *)&nic_mask,
2410 sizeof(struct rte_flow_item_gtp_psc),
2411 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2415 * Validate IPV4 item.
2416 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2417 * add specific validation of fragment_offset field,
2420 * Item specification.
2421 * @param[in] item_flags
2422 * Bit-fields that holds the items detected until now.
2424 * Pointer to error structure.
2427 * 0 on success, a negative errno value otherwise and rte_errno is set.
2430 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2431 const struct rte_flow_item *item,
2432 uint64_t item_flags, uint64_t last_item,
2433 uint16_t ether_type, struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_hca_attr *attr = &priv->sh->cdev->config.hca_attr;
2438 const struct rte_flow_item_ipv4 *spec = item->spec;
2439 const struct rte_flow_item_ipv4 *last = item->last;
2440 const struct rte_flow_item_ipv4 *mask = item->mask;
2441 rte_be16_t fragment_offset_spec = 0;
2442 rte_be16_t fragment_offset_last = 0;
2443 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2445 .src_addr = RTE_BE32(0xffffffff),
2446 .dst_addr = RTE_BE32(0xffffffff),
2447 .type_of_service = 0xff,
2448 .fragment_offset = RTE_BE16(0xffff),
2449 .next_proto_id = 0xff,
2450 .time_to_live = 0xff,
2454 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2455 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2456 bool ihl_cap = !tunnel ?
2457 attr->outer_ipv4_ihl : attr->inner_ipv4_ihl;
2459 return rte_flow_error_set(error, ENOTSUP,
2460 RTE_FLOW_ERROR_TYPE_ITEM,
2462 "IPV4 ihl offload not supported");
2463 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2465 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2466 ether_type, &nic_ipv4_mask,
2467 MLX5_ITEM_RANGE_ACCEPTED, error);
2471 fragment_offset_spec = spec->hdr.fragment_offset &
2472 mask->hdr.fragment_offset;
2473 if (!fragment_offset_spec)
2476 * spec and mask are valid, enforce using full mask to make sure the
2477 * complete value is used correctly.
2479 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2480 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2481 return rte_flow_error_set(error, EINVAL,
2482 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483 item, "must use full mask for"
2484 " fragment_offset");
2486 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2487 * indicating this is 1st fragment of fragmented packet.
2488 * This is not yet supported in MLX5, return appropriate error message.
2490 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2491 return rte_flow_error_set(error, ENOTSUP,
2492 RTE_FLOW_ERROR_TYPE_ITEM, item,
2493 "match on first fragment not "
2495 if (fragment_offset_spec && !last)
2496 return rte_flow_error_set(error, ENOTSUP,
2497 RTE_FLOW_ERROR_TYPE_ITEM, item,
2498 "specified value not supported");
2499 /* spec and last are valid, validate the specified range. */
2500 fragment_offset_last = last->hdr.fragment_offset &
2501 mask->hdr.fragment_offset;
2503 * Match on fragment_offset spec 0x2001 and last 0x3fff
2504 * means MF is 1 and frag-offset is > 0.
2505 * This packet is fragment 2nd and onward, excluding last.
2506 * This is not yet supported in MLX5, return appropriate
2509 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2510 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2511 return rte_flow_error_set(error, ENOTSUP,
2512 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2513 last, "match on following "
2514 "fragments not supported");
2516 * Match on fragment_offset spec 0x0001 and last 0x1fff
2517 * means MF is 0 and frag-offset is > 0.
2518 * This packet is last fragment of fragmented packet.
2519 * This is not yet supported in MLX5, return appropriate
2522 if (fragment_offset_spec == RTE_BE16(1) &&
2523 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2524 return rte_flow_error_set(error, ENOTSUP,
2525 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2526 last, "match on last "
2527 "fragment not supported");
2529 * Match on fragment_offset spec 0x0001 and last 0x3fff
2530 * means MF and/or frag-offset is not 0.
2531 * This is a fragmented packet.
2532 * Other range values are invalid and rejected.
2534 if (!(fragment_offset_spec == RTE_BE16(1) &&
2535 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2536 return rte_flow_error_set(error, ENOTSUP,
2537 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2538 "specified range not supported");
2543 * Validate IPV6 fragment extension item.
2546 * Item specification.
2547 * @param[in] item_flags
2548 * Bit-fields that holds the items detected until now.
2550 * Pointer to error structure.
2553 * 0 on success, a negative errno value otherwise and rte_errno is set.
2556 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2557 uint64_t item_flags,
2558 struct rte_flow_error *error)
2560 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2561 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2562 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2563 rte_be16_t frag_data_spec = 0;
2564 rte_be16_t frag_data_last = 0;
2565 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2566 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2567 MLX5_FLOW_LAYER_OUTER_L4;
2569 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2571 .next_header = 0xff,
2572 .frag_data = RTE_BE16(0xffff),
2576 if (item_flags & l4m)
2577 return rte_flow_error_set(error, EINVAL,
2578 RTE_FLOW_ERROR_TYPE_ITEM, item,
2579 "ipv6 fragment extension item cannot "
2581 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2582 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item must "
2586 "follow ipv6 item");
2588 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2589 if (!frag_data_spec)
2592 * spec and mask are valid, enforce using full mask to make sure the
2593 * complete value is used correctly.
2595 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2596 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2597 return rte_flow_error_set(error, EINVAL,
2598 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2599 item, "must use full mask for"
2602 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2603 * This is 1st fragment of fragmented packet.
2605 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2606 return rte_flow_error_set(error, ENOTSUP,
2607 RTE_FLOW_ERROR_TYPE_ITEM, item,
2608 "match on first fragment not "
2610 if (frag_data_spec && !last)
2611 return rte_flow_error_set(error, EINVAL,
2612 RTE_FLOW_ERROR_TYPE_ITEM, item,
2613 "specified value not supported");
2614 ret = mlx5_flow_item_acceptable
2615 (item, (const uint8_t *)mask,
2616 (const uint8_t *)&nic_mask,
2617 sizeof(struct rte_flow_item_ipv6_frag_ext),
2618 MLX5_ITEM_RANGE_ACCEPTED, error);
2621 /* spec and last are valid, validate the specified range. */
2622 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2624 * Match on frag_data spec 0x0009 and last 0xfff9
2625 * means M is 1 and frag-offset is > 0.
2626 * This packet is fragment 2nd and onward, excluding last.
2627 * This is not yet supported in MLX5, return appropriate
2630 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2631 RTE_IPV6_EHDR_MF_MASK) &&
2632 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2633 return rte_flow_error_set(error, ENOTSUP,
2634 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2635 last, "match on following "
2636 "fragments not supported");
2638 * Match on frag_data spec 0x0008 and last 0xfff8
2639 * means M is 0 and frag-offset is > 0.
2640 * This packet is last fragment of fragmented packet.
2641 * This is not yet supported in MLX5, return appropriate
2644 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2645 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2646 return rte_flow_error_set(error, ENOTSUP,
2647 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2648 last, "match on last "
2649 "fragment not supported");
2650 /* Other range values are invalid and rejected. */
2651 return rte_flow_error_set(error, EINVAL,
2652 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2653 "specified range not supported");
2657 * Validate ASO CT item.
2660 * Pointer to the rte_eth_dev structure.
2662 * Item specification.
2663 * @param[in] item_flags
2664 * Pointer to bit-fields that holds the items detected until now.
2666 * Pointer to error structure.
2669 * 0 on success, a negative errno value otherwise and rte_errno is set.
2672 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2673 const struct rte_flow_item *item,
2674 uint64_t *item_flags,
2675 struct rte_flow_error *error)
2677 const struct rte_flow_item_conntrack *spec = item->spec;
2678 const struct rte_flow_item_conntrack *mask = item->mask;
2682 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2683 return rte_flow_error_set(error, EINVAL,
2684 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2685 "Only one CT is supported");
2687 mask = &rte_flow_item_conntrack_mask;
2688 flags = spec->flags & mask->flags;
2689 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2690 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2691 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2692 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2693 return rte_flow_error_set(error, EINVAL,
2694 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2695 "Conflict status bits");
2696 /* State change also needs to be considered. */
2697 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2702 * Validate the pop VLAN action.
2705 * Pointer to the rte_eth_dev structure.
2706 * @param[in] action_flags
2707 * Holds the actions detected until now.
2709 * Pointer to the pop vlan action.
2710 * @param[in] item_flags
2711 * The items found in this flow rule.
2713 * Pointer to flow attributes.
2715 * Pointer to error structure.
2718 * 0 on success, a negative errno value otherwise and rte_errno is set.
2721 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2722 uint64_t action_flags,
2723 const struct rte_flow_action *action,
2724 uint64_t item_flags,
2725 const struct rte_flow_attr *attr,
2726 struct rte_flow_error *error)
2728 const struct mlx5_priv *priv = dev->data->dev_private;
2729 struct mlx5_dev_ctx_shared *sh = priv->sh;
2730 bool direction_error = false;
2732 if (!priv->sh->pop_vlan_action)
2733 return rte_flow_error_set(error, ENOTSUP,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2736 "pop vlan action is not supported");
2737 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2738 if (attr->transfer) {
2739 bool fdb_tx = priv->representor_id != UINT16_MAX;
2740 bool is_cx5 = sh->steering_format_version ==
2741 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2743 if (fdb_tx && is_cx5)
2744 direction_error = true;
2745 } else if (attr->egress) {
2746 direction_error = true;
2748 if (direction_error)
2749 return rte_flow_error_set(error, ENOTSUP,
2750 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2752 "pop vlan action not supported for egress");
2753 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2754 return rte_flow_error_set(error, ENOTSUP,
2755 RTE_FLOW_ERROR_TYPE_ACTION, action,
2756 "no support for multiple VLAN "
2758 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2759 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2760 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2761 return rte_flow_error_set(error, ENOTSUP,
2762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2764 "cannot pop vlan after decap without "
2765 "match on inner vlan in the flow");
2766 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2767 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2768 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2769 return rte_flow_error_set(error, ENOTSUP,
2770 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2772 "cannot pop vlan without a "
2773 "match on (outer) vlan in the flow");
2774 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION, action,
2777 "wrong action order, port_id should "
2778 "be after pop VLAN action");
2779 if (!attr->transfer && priv->representor)
2780 return rte_flow_error_set(error, ENOTSUP,
2781 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2782 "pop vlan action for VF representor "
2783 "not supported on NIC table");
2788 * Get VLAN default info from vlan match info.
2791 * the list of item specifications.
2793 * pointer VLAN info to fill to.
2796 * 0 on success, a negative errno value otherwise and rte_errno is set.
2799 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2800 struct rte_vlan_hdr *vlan)
2802 const struct rte_flow_item_vlan nic_mask = {
2803 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2804 MLX5DV_FLOW_VLAN_VID_MASK),
2805 .inner_type = RTE_BE16(0xffff),
2810 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2811 int type = items->type;
2813 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2814 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2817 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2818 const struct rte_flow_item_vlan *vlan_m = items->mask;
2819 const struct rte_flow_item_vlan *vlan_v = items->spec;
2821 /* If VLAN item in pattern doesn't contain data, return here. */
2826 /* Only full match values are accepted */
2827 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2828 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2829 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2831 rte_be_to_cpu_16(vlan_v->tci &
2832 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2834 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2835 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2836 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2838 rte_be_to_cpu_16(vlan_v->tci &
2839 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2841 if (vlan_m->inner_type == nic_mask.inner_type)
2842 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2843 vlan_m->inner_type);
2848 * Validate the push VLAN action.
2851 * Pointer to the rte_eth_dev structure.
2852 * @param[in] action_flags
2853 * Holds the actions detected until now.
2854 * @param[in] item_flags
2855 * The items found in this flow rule.
2857 * Pointer to the action structure.
2859 * Pointer to flow attributes
2861 * Pointer to error structure.
2864 * 0 on success, a negative errno value otherwise and rte_errno is set.
2867 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2868 uint64_t action_flags,
2869 const struct rte_flow_item_vlan *vlan_m,
2870 const struct rte_flow_action *action,
2871 const struct rte_flow_attr *attr,
2872 struct rte_flow_error *error)
2874 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2875 const struct mlx5_priv *priv = dev->data->dev_private;
2876 struct mlx5_dev_ctx_shared *sh = priv->sh;
2877 bool direction_error = false;
2879 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2880 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2881 return rte_flow_error_set(error, EINVAL,
2882 RTE_FLOW_ERROR_TYPE_ACTION, action,
2883 "invalid vlan ethertype");
2884 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2885 return rte_flow_error_set(error, EINVAL,
2886 RTE_FLOW_ERROR_TYPE_ACTION, action,
2887 "wrong action order, port_id should "
2888 "be after push VLAN");
2889 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2890 if (attr->transfer) {
2891 bool fdb_tx = priv->representor_id != UINT16_MAX;
2892 bool is_cx5 = sh->steering_format_version ==
2893 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2895 if (!fdb_tx && is_cx5)
2896 direction_error = true;
2897 } else if (attr->ingress) {
2898 direction_error = true;
2900 if (direction_error)
2901 return rte_flow_error_set(error, ENOTSUP,
2902 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2904 "push vlan action not supported for ingress");
2905 if (!attr->transfer && priv->representor)
2906 return rte_flow_error_set(error, ENOTSUP,
2907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2908 "push vlan action for VF representor "
2909 "not supported on NIC table");
2911 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2912 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2913 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2914 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2915 !(mlx5_flow_find_action
2916 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2917 return rte_flow_error_set(error, EINVAL,
2918 RTE_FLOW_ERROR_TYPE_ACTION, action,
2919 "not full match mask on VLAN PCP and "
2920 "there is no of_set_vlan_pcp action, "
2921 "push VLAN action cannot figure out "
2924 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2925 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2926 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2927 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2928 !(mlx5_flow_find_action
2929 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2930 return rte_flow_error_set(error, EINVAL,
2931 RTE_FLOW_ERROR_TYPE_ACTION, action,
2932 "not full match mask on VLAN VID and "
2933 "there is no of_set_vlan_vid action, "
2934 "push VLAN action cannot figure out "
2941 * Validate the set VLAN PCP.
2943 * @param[in] action_flags
2944 * Holds the actions detected until now.
2945 * @param[in] actions
2946 * Pointer to the list of actions remaining in the flow rule.
2948 * Pointer to error structure.
2951 * 0 on success, a negative errno value otherwise and rte_errno is set.
2954 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2955 const struct rte_flow_action actions[],
2956 struct rte_flow_error *error)
2958 const struct rte_flow_action *action = actions;
2959 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2961 if (conf->vlan_pcp > 7)
2962 return rte_flow_error_set(error, EINVAL,
2963 RTE_FLOW_ERROR_TYPE_ACTION, action,
2964 "VLAN PCP value is too big");
2965 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2966 return rte_flow_error_set(error, ENOTSUP,
2967 RTE_FLOW_ERROR_TYPE_ACTION, action,
2968 "set VLAN PCP action must follow "
2969 "the push VLAN action");
2970 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2971 return rte_flow_error_set(error, ENOTSUP,
2972 RTE_FLOW_ERROR_TYPE_ACTION, action,
2973 "Multiple VLAN PCP modification are "
2975 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2976 return rte_flow_error_set(error, EINVAL,
2977 RTE_FLOW_ERROR_TYPE_ACTION, action,
2978 "wrong action order, port_id should "
2979 "be after set VLAN PCP");
2984 * Validate the set VLAN VID.
2986 * @param[in] item_flags
2987 * Holds the items detected in this rule.
2988 * @param[in] action_flags
2989 * Holds the actions detected until now.
2990 * @param[in] actions
2991 * Pointer to the list of actions remaining in the flow rule.
2993 * Pointer to error structure.
2996 * 0 on success, a negative errno value otherwise and rte_errno is set.
2999 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3000 uint64_t action_flags,
3001 const struct rte_flow_action actions[],
3002 struct rte_flow_error *error)
3004 const struct rte_flow_action *action = actions;
3005 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3007 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3008 return rte_flow_error_set(error, EINVAL,
3009 RTE_FLOW_ERROR_TYPE_ACTION, action,
3010 "VLAN VID value is too big");
3011 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3012 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3013 return rte_flow_error_set(error, ENOTSUP,
3014 RTE_FLOW_ERROR_TYPE_ACTION, action,
3015 "set VLAN VID action must follow push"
3016 " VLAN action or match on VLAN item");
3017 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3018 return rte_flow_error_set(error, ENOTSUP,
3019 RTE_FLOW_ERROR_TYPE_ACTION, action,
3020 "Multiple VLAN VID modifications are "
3022 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3023 return rte_flow_error_set(error, EINVAL,
3024 RTE_FLOW_ERROR_TYPE_ACTION, action,
3025 "wrong action order, port_id should "
3026 "be after set VLAN VID");
3031 * Validate the FLAG action.
3034 * Pointer to the rte_eth_dev structure.
3035 * @param[in] action_flags
3036 * Holds the actions detected until now.
3038 * Pointer to flow attributes
3040 * Pointer to error structure.
3043 * 0 on success, a negative errno value otherwise and rte_errno is set.
3046 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3047 uint64_t action_flags,
3048 const struct rte_flow_attr *attr,
3049 struct rte_flow_error *error)
3051 struct mlx5_priv *priv = dev->data->dev_private;
3052 struct mlx5_sh_config *config = &priv->sh->config;
3055 /* Fall back if no extended metadata register support. */
3056 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3057 return mlx5_flow_validate_action_flag(action_flags, attr,
3059 /* Extensive metadata mode requires registers. */
3060 if (!mlx5_flow_ext_mreg_supported(dev))
3061 return rte_flow_error_set(error, ENOTSUP,
3062 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3063 "no metadata registers "
3064 "to support flag action");
3065 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3066 return rte_flow_error_set(error, ENOTSUP,
3067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3068 "extended metadata register"
3069 " isn't available");
3070 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3073 MLX5_ASSERT(ret > 0);
3074 if (action_flags & MLX5_FLOW_ACTION_MARK)
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3077 "can't mark and flag in same flow");
3078 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3079 return rte_flow_error_set(error, EINVAL,
3080 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3082 " actions in same flow");
3087 * Validate MARK action.
3090 * Pointer to the rte_eth_dev structure.
3092 * Pointer to action.
3093 * @param[in] action_flags
3094 * Holds the actions detected until now.
3096 * Pointer to flow attributes
3098 * Pointer to error structure.
3101 * 0 on success, a negative errno value otherwise and rte_errno is set.
3104 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3105 const struct rte_flow_action *action,
3106 uint64_t action_flags,
3107 const struct rte_flow_attr *attr,
3108 struct rte_flow_error *error)
3110 struct mlx5_priv *priv = dev->data->dev_private;
3111 struct mlx5_sh_config *config = &priv->sh->config;
3112 const struct rte_flow_action_mark *mark = action->conf;
3115 if (is_tunnel_offload_active(dev))
3116 return rte_flow_error_set(error, ENOTSUP,
3117 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3119 "if tunnel offload active");
3120 /* Fall back if no extended metadata register support. */
3121 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3122 return mlx5_flow_validate_action_mark(action, action_flags,
3124 /* Extensive metadata mode requires registers. */
3125 if (!mlx5_flow_ext_mreg_supported(dev))
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3128 "no metadata registers "
3129 "to support mark action");
3130 if (!priv->sh->dv_mark_mask)
3131 return rte_flow_error_set(error, ENOTSUP,
3132 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3133 "extended metadata register"
3134 " isn't available");
3135 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3138 MLX5_ASSERT(ret > 0);
3140 return rte_flow_error_set(error, EINVAL,
3141 RTE_FLOW_ERROR_TYPE_ACTION, action,
3142 "configuration cannot be null");
3143 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3144 return rte_flow_error_set(error, EINVAL,
3145 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3147 "mark id exceeds the limit");
3148 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3149 return rte_flow_error_set(error, EINVAL,
3150 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3151 "can't flag and mark in same flow");
3152 if (action_flags & MLX5_FLOW_ACTION_MARK)
3153 return rte_flow_error_set(error, EINVAL,
3154 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3155 "can't have 2 mark actions in same"
3161 * Validate SET_META action.
3164 * Pointer to the rte_eth_dev structure.
3166 * Pointer to the action structure.
3167 * @param[in] action_flags
3168 * Holds the actions detected until now.
3170 * Pointer to flow attributes
3172 * Pointer to error structure.
3175 * 0 on success, a negative errno value otherwise and rte_errno is set.
3178 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3179 const struct rte_flow_action *action,
3180 uint64_t action_flags __rte_unused,
3181 const struct rte_flow_attr *attr,
3182 struct rte_flow_error *error)
3184 struct mlx5_priv *priv = dev->data->dev_private;
3185 struct mlx5_sh_config *config = &priv->sh->config;
3186 const struct rte_flow_action_set_meta *conf;
3187 uint32_t nic_mask = UINT32_MAX;
3190 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3191 !mlx5_flow_ext_mreg_supported(dev))
3192 return rte_flow_error_set(error, ENOTSUP,
3193 RTE_FLOW_ERROR_TYPE_ACTION, action,
3194 "extended metadata register"
3195 " isn't supported");
3196 reg = flow_dv_get_metadata_reg(dev, attr, error);
3200 return rte_flow_error_set(error, ENOTSUP,
3201 RTE_FLOW_ERROR_TYPE_ACTION, action,
3202 "unavailable extended metadata register");
3203 if (reg != REG_A && reg != REG_B) {
3204 struct mlx5_priv *priv = dev->data->dev_private;
3206 nic_mask = priv->sh->dv_meta_mask;
3208 if (!(action->conf))
3209 return rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, action,
3211 "configuration cannot be null");
3212 conf = (const struct rte_flow_action_set_meta *)action->conf;
3214 return rte_flow_error_set(error, EINVAL,
3215 RTE_FLOW_ERROR_TYPE_ACTION, action,
3216 "zero mask doesn't have any effect");
3217 if (conf->mask & ~nic_mask)
3218 return rte_flow_error_set(error, EINVAL,
3219 RTE_FLOW_ERROR_TYPE_ACTION, action,
3220 "meta data must be within reg C0");
3225 * Validate SET_TAG action.
3228 * Pointer to the rte_eth_dev structure.
3230 * Pointer to the action structure.
3231 * @param[in] action_flags
3232 * Holds the actions detected until now.
3234 * Pointer to flow attributes
3236 * Pointer to error structure.
3239 * 0 on success, a negative errno value otherwise and rte_errno is set.
3242 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3243 const struct rte_flow_action *action,
3244 uint64_t action_flags,
3245 const struct rte_flow_attr *attr,
3246 struct rte_flow_error *error)
3248 const struct rte_flow_action_set_tag *conf;
3249 const uint64_t terminal_action_flags =
3250 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3251 MLX5_FLOW_ACTION_RSS;
3254 if (!mlx5_flow_ext_mreg_supported(dev))
3255 return rte_flow_error_set(error, ENOTSUP,
3256 RTE_FLOW_ERROR_TYPE_ACTION, action,
3257 "extensive metadata register"
3258 " isn't supported");
3259 if (!(action->conf))
3260 return rte_flow_error_set(error, EINVAL,
3261 RTE_FLOW_ERROR_TYPE_ACTION, action,
3262 "configuration cannot be null");
3263 conf = (const struct rte_flow_action_set_tag *)action->conf;
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION, action,
3267 "zero mask doesn't have any effect");
3268 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3271 if (!attr->transfer && attr->ingress &&
3272 (action_flags & terminal_action_flags))
3273 return rte_flow_error_set(error, EINVAL,
3274 RTE_FLOW_ERROR_TYPE_ACTION, action,
3275 "set_tag has no effect"
3276 " with terminal actions");
3281 * Indicates whether ASO aging is supported.
3284 * Pointer to shared device context structure.
3286 * Attributes of flow that includes AGE action.
3289 * True when ASO aging is supported, false otherwise.
3292 flow_hit_aso_supported(const struct mlx5_dev_ctx_shared *sh,
3293 const struct rte_flow_attr *attr)
3295 MLX5_ASSERT(sh && attr);
3296 return (sh->flow_hit_aso_en && (attr->transfer || attr->group));
3300 * Validate count action.
3303 * Pointer to rte_eth_dev structure.
3305 * Indicator if action is shared.
3306 * @param[in] action_flags
3307 * Holds the actions detected until now.
3309 * Attributes of flow that includes this action.
3311 * Pointer to error structure.
3314 * 0 on success, a negative errno value otherwise and rte_errno is set.
3317 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3318 uint64_t action_flags,
3319 const struct rte_flow_attr *attr,
3320 struct rte_flow_error *error)
3322 struct mlx5_priv *priv = dev->data->dev_private;
3324 if (!priv->sh->cdev->config.devx)
3326 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3327 return rte_flow_error_set(error, EINVAL,
3328 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3329 "duplicate count actions set");
3330 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3331 !flow_hit_aso_supported(priv->sh, attr))
3332 return rte_flow_error_set(error, EINVAL,
3333 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3334 "old age and indirect count combination is not supported");
3335 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3339 return rte_flow_error_set
3341 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3343 "count action not supported");
3347 * Validate the L2 encap action.
3350 * Pointer to the rte_eth_dev structure.
3351 * @param[in] action_flags
3352 * Holds the actions detected until now.
3354 * Pointer to the action structure.
3356 * Pointer to flow attributes.
3358 * Pointer to error structure.
3361 * 0 on success, a negative errno value otherwise and rte_errno is set.
3364 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3365 uint64_t action_flags,
3366 const struct rte_flow_action *action,
3367 const struct rte_flow_attr *attr,
3368 struct rte_flow_error *error)
3370 const struct mlx5_priv *priv = dev->data->dev_private;
3372 if (!(action->conf))
3373 return rte_flow_error_set(error, EINVAL,
3374 RTE_FLOW_ERROR_TYPE_ACTION, action,
3375 "configuration cannot be null");
3376 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3377 return rte_flow_error_set(error, EINVAL,
3378 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3379 "can only have a single encap action "
3381 if (!attr->transfer && priv->representor)
3382 return rte_flow_error_set(error, ENOTSUP,
3383 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3384 "encap action for VF representor "
3385 "not supported on NIC table");
3390 * Validate a decap action.
3393 * Pointer to the rte_eth_dev structure.
3394 * @param[in] action_flags
3395 * Holds the actions detected until now.
3397 * Pointer to the action structure.
3398 * @param[in] item_flags
3399 * Holds the items detected.
3401 * Pointer to flow attributes
3403 * Pointer to error structure.
3406 * 0 on success, a negative errno value otherwise and rte_errno is set.
3409 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3410 uint64_t action_flags,
3411 const struct rte_flow_action *action,
3412 const uint64_t item_flags,
3413 const struct rte_flow_attr *attr,
3414 struct rte_flow_error *error)
3416 const struct mlx5_priv *priv = dev->data->dev_private;
3418 if (priv->sh->cdev->config.hca_attr.scatter_fcs_w_decap_disable &&
3419 !priv->sh->config.decap_en)
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3422 "decap is not enabled");
3423 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3424 return rte_flow_error_set(error, ENOTSUP,
3425 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3427 MLX5_FLOW_ACTION_DECAP ? "can only "
3428 "have a single decap action" : "decap "
3429 "after encap is not supported");
3430 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3431 return rte_flow_error_set(error, EINVAL,
3432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3433 "can't have decap action after"
3436 return rte_flow_error_set(error, ENOTSUP,
3437 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3439 "decap action not supported for "
3441 if (!attr->transfer && priv->representor)
3442 return rte_flow_error_set(error, ENOTSUP,
3443 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3444 "decap action for VF representor "
3445 "not supported on NIC table");
3446 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3447 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3448 return rte_flow_error_set(error, ENOTSUP,
3449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3450 "VXLAN item should be present for VXLAN decap");
3454 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3457 * Validate the raw encap and decap actions.
3460 * Pointer to the rte_eth_dev structure.
3462 * Pointer to the decap action.
3464 * Pointer to the encap action.
3466 * Pointer to flow attributes
3467 * @param[in/out] action_flags
3468 * Holds the actions detected until now.
3469 * @param[out] actions_n
3470 * pointer to the number of actions counter.
3472 * Pointer to the action structure.
3473 * @param[in] item_flags
3474 * Holds the items detected.
3476 * Pointer to error structure.
3479 * 0 on success, a negative errno value otherwise and rte_errno is set.
3482 flow_dv_validate_action_raw_encap_decap
3483 (struct rte_eth_dev *dev,
3484 const struct rte_flow_action_raw_decap *decap,
3485 const struct rte_flow_action_raw_encap *encap,
3486 const struct rte_flow_attr *attr, uint64_t *action_flags,
3487 int *actions_n, const struct rte_flow_action *action,
3488 uint64_t item_flags, struct rte_flow_error *error)
3490 const struct mlx5_priv *priv = dev->data->dev_private;
3493 if (encap && (!encap->size || !encap->data))
3494 return rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3496 "raw encap data cannot be empty");
3497 if (decap && encap) {
3498 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3499 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3502 else if (encap->size <=
3503 MLX5_ENCAPSULATION_DECISION_SIZE &&
3505 MLX5_ENCAPSULATION_DECISION_SIZE)
3508 else if (encap->size >
3509 MLX5_ENCAPSULATION_DECISION_SIZE &&
3511 MLX5_ENCAPSULATION_DECISION_SIZE)
3512 /* 2 L2 actions: encap and decap. */
3515 return rte_flow_error_set(error,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3518 NULL, "unsupported too small "
3519 "raw decap and too small raw "
3520 "encap combination");
3523 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3524 item_flags, attr, error);
3527 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3531 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3532 return rte_flow_error_set(error, ENOTSUP,
3533 RTE_FLOW_ERROR_TYPE_ACTION,
3535 "small raw encap size");
3536 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3537 return rte_flow_error_set(error, EINVAL,
3538 RTE_FLOW_ERROR_TYPE_ACTION,
3540 "more than one encap action");
3541 if (!attr->transfer && priv->representor)
3542 return rte_flow_error_set
3544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3545 "encap action for VF representor "
3546 "not supported on NIC table");
3547 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3554 * Validate the ASO CT action.
3557 * Pointer to the rte_eth_dev structure.
3558 * @param[in] action_flags
3559 * Holds the actions detected until now.
3560 * @param[in] item_flags
3561 * The items found in this flow rule.
3563 * Pointer to flow attributes.
3565 * Pointer to error structure.
3568 * 0 on success, a negative errno value otherwise and rte_errno is set.
3571 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3572 uint64_t action_flags,
3573 uint64_t item_flags,
3574 const struct rte_flow_attr *attr,
3575 struct rte_flow_error *error)
3579 if (attr->group == 0 && !attr->transfer)
3580 return rte_flow_error_set(error, ENOTSUP,
3581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3583 "Only support non-root table");
3584 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3585 return rte_flow_error_set(error, ENOTSUP,
3586 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3587 "CT cannot follow a fate action");
3588 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3589 (action_flags & MLX5_FLOW_ACTION_AGE))
3590 return rte_flow_error_set(error, EINVAL,
3591 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3592 "Only one ASO action is supported");
3593 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3594 return rte_flow_error_set(error, EINVAL,
3595 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3596 "Encap cannot exist before CT");
3597 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3598 return rte_flow_error_set(error, EINVAL,
3599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3600 "Not a outer TCP packet");
3605 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3606 struct mlx5_list_entry *entry, void *cb_ctx)
3608 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3609 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3610 struct mlx5_flow_dv_encap_decap_resource *resource;
3612 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3614 if (resource->reformat_type == ctx_resource->reformat_type &&
3615 resource->ft_type == ctx_resource->ft_type &&
3616 resource->flags == ctx_resource->flags &&
3617 resource->size == ctx_resource->size &&
3618 !memcmp((const void *)resource->buf,
3619 (const void *)ctx_resource->buf,
3625 struct mlx5_list_entry *
3626 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3628 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3629 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3630 struct mlx5dv_dr_domain *domain;
3631 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3632 struct mlx5_flow_dv_encap_decap_resource *resource;
3636 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3637 domain = sh->fdb_domain;
3638 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3639 domain = sh->rx_domain;
3641 domain = sh->tx_domain;
3642 /* Register new encap/decap resource. */
3643 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3645 rte_flow_error_set(ctx->error, ENOMEM,
3646 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3647 "cannot allocate resource memory");
3650 *resource = *ctx_resource;
3651 resource->idx = idx;
3652 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3656 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3657 rte_flow_error_set(ctx->error, ENOMEM,
3658 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3659 NULL, "cannot create action");
3663 return &resource->entry;
3666 struct mlx5_list_entry *
3667 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3670 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3671 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3672 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3675 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3677 if (!cache_resource) {
3678 rte_flow_error_set(ctx->error, ENOMEM,
3679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3680 "cannot allocate resource memory");
3683 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3684 cache_resource->idx = idx;
3685 return &cache_resource->entry;
3689 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3691 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3692 struct mlx5_flow_dv_encap_decap_resource *res =
3693 container_of(entry, typeof(*res), entry);
3695 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3699 * Find existing encap/decap resource or create and register a new one.
3701 * @param[in, out] dev
3702 * Pointer to rte_eth_dev structure.
3703 * @param[in, out] resource
3704 * Pointer to encap/decap resource.
3705 * @parm[in, out] dev_flow
3706 * Pointer to the dev_flow.
3708 * pointer to error structure.
3711 * 0 on success otherwise -errno and errno is set.
3714 flow_dv_encap_decap_resource_register
3715 (struct rte_eth_dev *dev,
3716 struct mlx5_flow_dv_encap_decap_resource *resource,
3717 struct mlx5_flow *dev_flow,
3718 struct rte_flow_error *error)
3720 struct mlx5_priv *priv = dev->data->dev_private;
3721 struct mlx5_dev_ctx_shared *sh = priv->sh;
3722 struct mlx5_list_entry *entry;
3726 uint32_t refmt_type:8;
3728 * Header reformat actions can be shared between
3729 * non-root tables. One bit to indicate non-root
3733 uint32_t reserve:15;
3736 } encap_decap_key = {
3738 .ft_type = resource->ft_type,
3739 .refmt_type = resource->reformat_type,
3740 .is_root = !!dev_flow->dv.group,
3744 struct mlx5_flow_cb_ctx ctx = {
3748 struct mlx5_hlist *encaps_decaps;
3751 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3753 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3755 flow_dv_encap_decap_create_cb,
3756 flow_dv_encap_decap_match_cb,
3757 flow_dv_encap_decap_remove_cb,
3758 flow_dv_encap_decap_clone_cb,
3759 flow_dv_encap_decap_clone_free_cb,
3761 if (unlikely(!encaps_decaps))
3763 resource->flags = dev_flow->dv.group ? 0 : 1;
3764 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3765 sizeof(encap_decap_key.v32), 0);
3766 if (resource->reformat_type !=
3767 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3769 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3770 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3773 resource = container_of(entry, typeof(*resource), entry);
3774 dev_flow->dv.encap_decap = resource;
3775 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3780 * Find existing table jump resource or create and register a new one.
3782 * @param[in, out] dev
3783 * Pointer to rte_eth_dev structure.
3784 * @param[in, out] tbl
3785 * Pointer to flow table resource.
3786 * @parm[in, out] dev_flow
3787 * Pointer to the dev_flow.
3789 * pointer to error structure.
3792 * 0 on success otherwise -errno and errno is set.
3795 flow_dv_jump_tbl_resource_register
3796 (struct rte_eth_dev *dev __rte_unused,
3797 struct mlx5_flow_tbl_resource *tbl,
3798 struct mlx5_flow *dev_flow,
3799 struct rte_flow_error *error __rte_unused)
3801 struct mlx5_flow_tbl_data_entry *tbl_data =
3802 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3805 MLX5_ASSERT(tbl_data->jump.action);
3806 dev_flow->handle->rix_jump = tbl_data->idx;
3807 dev_flow->dv.jump = &tbl_data->jump;
3812 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3813 struct mlx5_list_entry *entry, void *cb_ctx)
3815 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3816 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3817 struct mlx5_flow_dv_port_id_action_resource *res =
3818 container_of(entry, typeof(*res), entry);
3820 return ref->port_id != res->port_id;
3823 struct mlx5_list_entry *
3824 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3826 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3827 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3828 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3829 struct mlx5_flow_dv_port_id_action_resource *resource;
3833 /* Register new port id action resource. */
3834 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3836 rte_flow_error_set(ctx->error, ENOMEM,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3838 "cannot allocate port_id action memory");
3842 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3846 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3847 rte_flow_error_set(ctx->error, ENOMEM,
3848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3849 "cannot create action");
3852 resource->idx = idx;
3853 return &resource->entry;
3856 struct mlx5_list_entry *
3857 flow_dv_port_id_clone_cb(void *tool_ctx,
3858 struct mlx5_list_entry *entry __rte_unused,
3861 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3862 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3863 struct mlx5_flow_dv_port_id_action_resource *resource;
3866 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3868 rte_flow_error_set(ctx->error, ENOMEM,
3869 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3870 "cannot allocate port_id action memory");
3873 memcpy(resource, entry, sizeof(*resource));
3874 resource->idx = idx;
3875 return &resource->entry;
3879 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3881 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3882 struct mlx5_flow_dv_port_id_action_resource *resource =
3883 container_of(entry, typeof(*resource), entry);
3885 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3889 * Find existing table port ID resource or create and register a new one.
3891 * @param[in, out] dev
3892 * Pointer to rte_eth_dev structure.
3893 * @param[in, out] ref
3894 * Pointer to port ID action resource reference.
3895 * @parm[in, out] dev_flow
3896 * Pointer to the dev_flow.
3898 * pointer to error structure.
3901 * 0 on success otherwise -errno and errno is set.
3904 flow_dv_port_id_action_resource_register
3905 (struct rte_eth_dev *dev,
3906 struct mlx5_flow_dv_port_id_action_resource *ref,
3907 struct mlx5_flow *dev_flow,
3908 struct rte_flow_error *error)
3910 struct mlx5_priv *priv = dev->data->dev_private;
3911 struct mlx5_list_entry *entry;
3912 struct mlx5_flow_dv_port_id_action_resource *resource;
3913 struct mlx5_flow_cb_ctx ctx = {
3918 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3921 resource = container_of(entry, typeof(*resource), entry);
3922 dev_flow->dv.port_id_action = resource;
3923 dev_flow->handle->rix_port_id_action = resource->idx;
3928 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3929 struct mlx5_list_entry *entry, void *cb_ctx)
3931 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3932 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3933 struct mlx5_flow_dv_push_vlan_action_resource *res =
3934 container_of(entry, typeof(*res), entry);
3936 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3939 struct mlx5_list_entry *
3940 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3942 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3943 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3944 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3945 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3946 struct mlx5dv_dr_domain *domain;
3950 /* Register new port id action resource. */
3951 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3953 rte_flow_error_set(ctx->error, ENOMEM,
3954 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3955 "cannot allocate push_vlan action memory");
3959 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3960 domain = sh->fdb_domain;
3961 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3962 domain = sh->rx_domain;
3964 domain = sh->tx_domain;
3965 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3968 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3969 rte_flow_error_set(ctx->error, ENOMEM,
3970 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3971 "cannot create push vlan action");
3974 resource->idx = idx;
3975 return &resource->entry;
3978 struct mlx5_list_entry *
3979 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3980 struct mlx5_list_entry *entry __rte_unused,
3983 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3984 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3985 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3988 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3990 rte_flow_error_set(ctx->error, ENOMEM,
3991 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3992 "cannot allocate push_vlan action memory");
3995 memcpy(resource, entry, sizeof(*resource));
3996 resource->idx = idx;
3997 return &resource->entry;
4001 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
4003 struct mlx5_dev_ctx_shared *sh = tool_ctx;
4004 struct mlx5_flow_dv_push_vlan_action_resource *resource =
4005 container_of(entry, typeof(*resource), entry);
4007 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
4011 * Find existing push vlan resource or create and register a new one.
4013 * @param [in, out] dev
4014 * Pointer to rte_eth_dev structure.
4015 * @param[in, out] ref
4016 * Pointer to port ID action resource reference.
4017 * @parm[in, out] dev_flow
4018 * Pointer to the dev_flow.
4020 * pointer to error structure.
4023 * 0 on success otherwise -errno and errno is set.
4026 flow_dv_push_vlan_action_resource_register
4027 (struct rte_eth_dev *dev,
4028 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4029 struct mlx5_flow *dev_flow,
4030 struct rte_flow_error *error)
4032 struct mlx5_priv *priv = dev->data->dev_private;
4033 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4034 struct mlx5_list_entry *entry;
4035 struct mlx5_flow_cb_ctx ctx = {
4040 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4043 resource = container_of(entry, typeof(*resource), entry);
4045 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4046 dev_flow->dv.push_vlan_res = resource;
4051 * Get the size of specific rte_flow_item_type hdr size
4053 * @param[in] item_type
4054 * Tested rte_flow_item_type.
4057 * sizeof struct item_type, 0 if void or irrelevant.
4060 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4064 switch (item_type) {
4065 case RTE_FLOW_ITEM_TYPE_ETH:
4066 retval = sizeof(struct rte_ether_hdr);
4068 case RTE_FLOW_ITEM_TYPE_VLAN:
4069 retval = sizeof(struct rte_vlan_hdr);
4071 case RTE_FLOW_ITEM_TYPE_IPV4:
4072 retval = sizeof(struct rte_ipv4_hdr);
4074 case RTE_FLOW_ITEM_TYPE_IPV6:
4075 retval = sizeof(struct rte_ipv6_hdr);
4077 case RTE_FLOW_ITEM_TYPE_UDP:
4078 retval = sizeof(struct rte_udp_hdr);
4080 case RTE_FLOW_ITEM_TYPE_TCP:
4081 retval = sizeof(struct rte_tcp_hdr);
4083 case RTE_FLOW_ITEM_TYPE_VXLAN:
4084 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4085 retval = sizeof(struct rte_vxlan_hdr);
4087 case RTE_FLOW_ITEM_TYPE_GRE:
4088 case RTE_FLOW_ITEM_TYPE_NVGRE:
4089 retval = sizeof(struct rte_gre_hdr);
4091 case RTE_FLOW_ITEM_TYPE_MPLS:
4092 retval = sizeof(struct rte_mpls_hdr);
4094 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4102 #define MLX5_ENCAP_IPV4_VERSION 0x40
4103 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4104 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4105 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4106 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4107 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4108 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4111 * Convert the encap action data from list of rte_flow_item to raw buffer
4114 * Pointer to rte_flow_item objects list.
4116 * Pointer to the output buffer.
4118 * Pointer to the output buffer size.
4120 * Pointer to the error structure.
4123 * 0 on success, a negative errno value otherwise and rte_errno is set.
4126 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4127 size_t *size, struct rte_flow_error *error)
4129 struct rte_ether_hdr *eth = NULL;
4130 struct rte_vlan_hdr *vlan = NULL;
4131 struct rte_ipv4_hdr *ipv4 = NULL;
4132 struct rte_ipv6_hdr *ipv6 = NULL;
4133 struct rte_udp_hdr *udp = NULL;
4134 struct rte_vxlan_hdr *vxlan = NULL;
4135 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4136 struct rte_gre_hdr *gre = NULL;
4138 size_t temp_size = 0;
4141 return rte_flow_error_set(error, EINVAL,
4142 RTE_FLOW_ERROR_TYPE_ACTION,
4143 NULL, "invalid empty data");
4144 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4145 len = flow_dv_get_item_hdr_len(items->type);
4146 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4147 return rte_flow_error_set(error, EINVAL,
4148 RTE_FLOW_ERROR_TYPE_ACTION,
4149 (void *)items->type,
4150 "items total size is too big"
4151 " for encap action");
4152 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4153 switch (items->type) {
4154 case RTE_FLOW_ITEM_TYPE_ETH:
4155 eth = (struct rte_ether_hdr *)&buf[temp_size];
4157 case RTE_FLOW_ITEM_TYPE_VLAN:
4158 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4160 return rte_flow_error_set(error, EINVAL,
4161 RTE_FLOW_ERROR_TYPE_ACTION,
4162 (void *)items->type,
4163 "eth header not found");
4164 if (!eth->ether_type)
4165 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4167 case RTE_FLOW_ITEM_TYPE_IPV4:
4168 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4170 return rte_flow_error_set(error, EINVAL,
4171 RTE_FLOW_ERROR_TYPE_ACTION,
4172 (void *)items->type,
4173 "neither eth nor vlan"
4175 if (vlan && !vlan->eth_proto)
4176 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4177 else if (eth && !eth->ether_type)
4178 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4179 if (!ipv4->version_ihl)
4180 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4181 MLX5_ENCAP_IPV4_IHL_MIN;
4182 if (!ipv4->time_to_live)
4183 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4185 case RTE_FLOW_ITEM_TYPE_IPV6:
4186 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4188 return rte_flow_error_set(error, EINVAL,
4189 RTE_FLOW_ERROR_TYPE_ACTION,
4190 (void *)items->type,
4191 "neither eth nor vlan"
4193 if (vlan && !vlan->eth_proto)
4194 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4195 else if (eth && !eth->ether_type)
4196 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4197 if (!ipv6->vtc_flow)
4199 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4200 if (!ipv6->hop_limits)
4201 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4203 case RTE_FLOW_ITEM_TYPE_UDP:
4204 udp = (struct rte_udp_hdr *)&buf[temp_size];
4206 return rte_flow_error_set(error, EINVAL,
4207 RTE_FLOW_ERROR_TYPE_ACTION,
4208 (void *)items->type,
4209 "ip header not found");
4210 if (ipv4 && !ipv4->next_proto_id)
4211 ipv4->next_proto_id = IPPROTO_UDP;
4212 else if (ipv6 && !ipv6->proto)
4213 ipv6->proto = IPPROTO_UDP;
4215 case RTE_FLOW_ITEM_TYPE_VXLAN:
4216 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4218 return rte_flow_error_set(error, EINVAL,
4219 RTE_FLOW_ERROR_TYPE_ACTION,
4220 (void *)items->type,
4221 "udp header not found");
4223 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4224 if (!vxlan->vx_flags)
4226 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4228 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4229 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4231 return rte_flow_error_set(error, EINVAL,
4232 RTE_FLOW_ERROR_TYPE_ACTION,
4233 (void *)items->type,
4234 "udp header not found");
4235 if (!vxlan_gpe->proto)
4236 return rte_flow_error_set(error, EINVAL,
4237 RTE_FLOW_ERROR_TYPE_ACTION,
4238 (void *)items->type,
4239 "next protocol not found");
4242 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4243 if (!vxlan_gpe->vx_flags)
4244 vxlan_gpe->vx_flags =
4245 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4247 case RTE_FLOW_ITEM_TYPE_GRE:
4248 case RTE_FLOW_ITEM_TYPE_NVGRE:
4249 gre = (struct rte_gre_hdr *)&buf[temp_size];
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "next protocol not found");
4256 return rte_flow_error_set(error, EINVAL,
4257 RTE_FLOW_ERROR_TYPE_ACTION,
4258 (void *)items->type,
4259 "ip header not found");
4260 if (ipv4 && !ipv4->next_proto_id)
4261 ipv4->next_proto_id = IPPROTO_GRE;
4262 else if (ipv6 && !ipv6->proto)
4263 ipv6->proto = IPPROTO_GRE;
4265 case RTE_FLOW_ITEM_TYPE_VOID:
4268 return rte_flow_error_set(error, EINVAL,
4269 RTE_FLOW_ERROR_TYPE_ACTION,
4270 (void *)items->type,
4271 "unsupported item type");
4281 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4283 struct rte_ether_hdr *eth = NULL;
4284 struct rte_vlan_hdr *vlan = NULL;
4285 struct rte_ipv6_hdr *ipv6 = NULL;
4286 struct rte_udp_hdr *udp = NULL;
4290 eth = (struct rte_ether_hdr *)data;
4291 next_hdr = (char *)(eth + 1);
4292 proto = RTE_BE16(eth->ether_type);
4295 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4296 vlan = (struct rte_vlan_hdr *)next_hdr;
4297 proto = RTE_BE16(vlan->eth_proto);
4298 next_hdr += sizeof(struct rte_vlan_hdr);
4301 /* HW calculates IPv4 csum. no need to proceed */
4302 if (proto == RTE_ETHER_TYPE_IPV4)
4305 /* non IPv4/IPv6 header. not supported */
4306 if (proto != RTE_ETHER_TYPE_IPV6) {
4307 return rte_flow_error_set(error, ENOTSUP,
4308 RTE_FLOW_ERROR_TYPE_ACTION,
4309 NULL, "Cannot offload non IPv4/IPv6");
4312 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4314 /* ignore non UDP */
4315 if (ipv6->proto != IPPROTO_UDP)
4318 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4319 udp->dgram_cksum = 0;
4325 * Convert L2 encap action to DV specification.
4328 * Pointer to rte_eth_dev structure.
4330 * Pointer to action structure.
4331 * @param[in, out] dev_flow
4332 * Pointer to the mlx5_flow.
4333 * @param[in] transfer
4334 * Mark if the flow is E-Switch flow.
4336 * Pointer to the error structure.
4339 * 0 on success, a negative errno value otherwise and rte_errno is set.
4342 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4343 const struct rte_flow_action *action,
4344 struct mlx5_flow *dev_flow,
4346 struct rte_flow_error *error)
4348 const struct rte_flow_item *encap_data;
4349 const struct rte_flow_action_raw_encap *raw_encap_data;
4350 struct mlx5_flow_dv_encap_decap_resource res = {
4352 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4353 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4354 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4357 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4359 (const struct rte_flow_action_raw_encap *)action->conf;
4360 res.size = raw_encap_data->size;
4361 memcpy(res.buf, raw_encap_data->data, res.size);
4363 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4365 ((const struct rte_flow_action_vxlan_encap *)
4366 action->conf)->definition;
4369 ((const struct rte_flow_action_nvgre_encap *)
4370 action->conf)->definition;
4371 if (flow_dv_convert_encap_data(encap_data, res.buf,
4375 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4377 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4378 return rte_flow_error_set(error, EINVAL,
4379 RTE_FLOW_ERROR_TYPE_ACTION,
4380 NULL, "can't create L2 encap action");
4385 * Convert L2 decap action to DV specification.
4388 * Pointer to rte_eth_dev structure.
4389 * @param[in, out] dev_flow
4390 * Pointer to the mlx5_flow.
4391 * @param[in] transfer
4392 * Mark if the flow is E-Switch flow.
4394 * Pointer to the error structure.
4397 * 0 on success, a negative errno value otherwise and rte_errno is set.
4400 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4401 struct mlx5_flow *dev_flow,
4403 struct rte_flow_error *error)
4405 struct mlx5_flow_dv_encap_decap_resource res = {
4408 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4409 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4410 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4413 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4414 return rte_flow_error_set(error, EINVAL,
4415 RTE_FLOW_ERROR_TYPE_ACTION,
4416 NULL, "can't create L2 decap action");
4421 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4424 * Pointer to rte_eth_dev structure.
4426 * Pointer to action structure.
4427 * @param[in, out] dev_flow
4428 * Pointer to the mlx5_flow.
4430 * Pointer to the flow attributes.
4432 * Pointer to the error structure.
4435 * 0 on success, a negative errno value otherwise and rte_errno is set.
4438 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4439 const struct rte_flow_action *action,
4440 struct mlx5_flow *dev_flow,
4441 const struct rte_flow_attr *attr,
4442 struct rte_flow_error *error)
4444 const struct rte_flow_action_raw_encap *encap_data;
4445 struct mlx5_flow_dv_encap_decap_resource res;
4447 memset(&res, 0, sizeof(res));
4448 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4449 res.size = encap_data->size;
4450 memcpy(res.buf, encap_data->data, res.size);
4451 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4452 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4453 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4455 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4457 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4458 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4459 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4460 return rte_flow_error_set(error, EINVAL,
4461 RTE_FLOW_ERROR_TYPE_ACTION,
4462 NULL, "can't create encap action");
4467 * Create action push VLAN.
4470 * Pointer to rte_eth_dev structure.
4472 * Pointer to the flow attributes.
4474 * Pointer to the vlan to push to the Ethernet header.
4475 * @param[in, out] dev_flow
4476 * Pointer to the mlx5_flow.
4478 * Pointer to the error structure.
4481 * 0 on success, a negative errno value otherwise and rte_errno is set.
4484 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4485 const struct rte_flow_attr *attr,
4486 const struct rte_vlan_hdr *vlan,
4487 struct mlx5_flow *dev_flow,
4488 struct rte_flow_error *error)
4490 struct mlx5_flow_dv_push_vlan_action_resource res;
4492 memset(&res, 0, sizeof(res));
4494 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4497 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4499 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4500 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4501 return flow_dv_push_vlan_action_resource_register
4502 (dev, &res, dev_flow, error);
4506 * Validate the modify-header actions.
4508 * @param[in] action_flags
4509 * Holds the actions detected until now.
4511 * Pointer to the modify action.
4513 * Pointer to error structure.
4516 * 0 on success, a negative errno value otherwise and rte_errno is set.
4519 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4520 const struct rte_flow_action *action,
4521 struct rte_flow_error *error)
4523 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4524 return rte_flow_error_set(error, EINVAL,
4525 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4526 NULL, "action configuration not set");
4527 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4528 return rte_flow_error_set(error, EINVAL,
4529 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4530 "can't have encap action before"
4536 * Validate the modify-header MAC address actions.
4538 * @param[in] action_flags
4539 * Holds the actions detected until now.
4541 * Pointer to the modify action.
4542 * @param[in] item_flags
4543 * Holds the items detected.
4545 * Pointer to error structure.
4548 * 0 on success, a negative errno value otherwise and rte_errno is set.
4551 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4552 const struct rte_flow_action *action,
4553 const uint64_t item_flags,
4554 struct rte_flow_error *error)
4558 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4560 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4561 return rte_flow_error_set(error, EINVAL,
4562 RTE_FLOW_ERROR_TYPE_ACTION,
4564 "no L2 item in pattern");
4570 * Validate the modify-header IPv4 address actions.
4572 * @param[in] action_flags
4573 * Holds the actions detected until now.
4575 * Pointer to the modify action.
4576 * @param[in] item_flags
4577 * Holds the items detected.
4579 * Pointer to error structure.
4582 * 0 on success, a negative errno value otherwise and rte_errno is set.
4585 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4586 const struct rte_flow_action *action,
4587 const uint64_t item_flags,
4588 struct rte_flow_error *error)
4593 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4595 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4596 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4597 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4598 if (!(item_flags & layer))
4599 return rte_flow_error_set(error, EINVAL,
4600 RTE_FLOW_ERROR_TYPE_ACTION,
4602 "no ipv4 item in pattern");
4608 * Validate the modify-header IPv6 address actions.
4610 * @param[in] action_flags
4611 * Holds the actions detected until now.
4613 * Pointer to the modify action.
4614 * @param[in] item_flags
4615 * Holds the items detected.
4617 * Pointer to error structure.
4620 * 0 on success, a negative errno value otherwise and rte_errno is set.
4623 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4624 const struct rte_flow_action *action,
4625 const uint64_t item_flags,
4626 struct rte_flow_error *error)
4631 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4633 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4634 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4635 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4636 if (!(item_flags & layer))
4637 return rte_flow_error_set(error, EINVAL,
4638 RTE_FLOW_ERROR_TYPE_ACTION,
4640 "no ipv6 item in pattern");
4646 * Validate the modify-header TP actions.
4648 * @param[in] action_flags
4649 * Holds the actions detected until now.
4651 * Pointer to the modify action.
4652 * @param[in] item_flags
4653 * Holds the items detected.
4655 * Pointer to error structure.
4658 * 0 on success, a negative errno value otherwise and rte_errno is set.
4661 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4662 const struct rte_flow_action *action,
4663 const uint64_t item_flags,
4664 struct rte_flow_error *error)
4669 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4671 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4672 MLX5_FLOW_LAYER_INNER_L4 :
4673 MLX5_FLOW_LAYER_OUTER_L4;
4674 if (!(item_flags & layer))
4675 return rte_flow_error_set(error, EINVAL,
4676 RTE_FLOW_ERROR_TYPE_ACTION,
4677 NULL, "no transport layer "
4684 * Validate the modify-header actions of increment/decrement
4685 * TCP Sequence-number.
4687 * @param[in] action_flags
4688 * Holds the actions detected until now.
4690 * Pointer to the modify action.
4691 * @param[in] item_flags
4692 * Holds the items detected.
4694 * Pointer to error structure.
4697 * 0 on success, a negative errno value otherwise and rte_errno is set.
4700 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4701 const struct rte_flow_action *action,
4702 const uint64_t item_flags,
4703 struct rte_flow_error *error)
4708 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4710 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4711 MLX5_FLOW_LAYER_INNER_L4_TCP :
4712 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4713 if (!(item_flags & layer))
4714 return rte_flow_error_set(error, EINVAL,
4715 RTE_FLOW_ERROR_TYPE_ACTION,
4716 NULL, "no TCP item in"
4718 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4719 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4720 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4721 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4722 return rte_flow_error_set(error, EINVAL,
4723 RTE_FLOW_ERROR_TYPE_ACTION,
4725 "cannot decrease and increase"
4726 " TCP sequence number"
4727 " at the same time");
4733 * Validate the modify-header actions of increment/decrement
4734 * TCP Acknowledgment number.
4736 * @param[in] action_flags
4737 * Holds the actions detected until now.
4739 * Pointer to the modify action.
4740 * @param[in] item_flags
4741 * Holds the items detected.
4743 * Pointer to error structure.
4746 * 0 on success, a negative errno value otherwise and rte_errno is set.
4749 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4750 const struct rte_flow_action *action,
4751 const uint64_t item_flags,
4752 struct rte_flow_error *error)
4757 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4759 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4760 MLX5_FLOW_LAYER_INNER_L4_TCP :
4761 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4762 if (!(item_flags & layer))
4763 return rte_flow_error_set(error, EINVAL,
4764 RTE_FLOW_ERROR_TYPE_ACTION,
4765 NULL, "no TCP item in"
4767 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4768 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4769 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4770 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4771 return rte_flow_error_set(error, EINVAL,
4772 RTE_FLOW_ERROR_TYPE_ACTION,
4774 "cannot decrease and increase"
4775 " TCP acknowledgment number"
4776 " at the same time");
4782 * Validate the modify-header TTL actions.
4784 * @param[in] action_flags
4785 * Holds the actions detected until now.
4787 * Pointer to the modify action.
4788 * @param[in] item_flags
4789 * Holds the items detected.
4791 * Pointer to error structure.
4794 * 0 on success, a negative errno value otherwise and rte_errno is set.
4797 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4798 const struct rte_flow_action *action,
4799 const uint64_t item_flags,
4800 struct rte_flow_error *error)
4805 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4807 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4808 MLX5_FLOW_LAYER_INNER_L3 :
4809 MLX5_FLOW_LAYER_OUTER_L3;
4810 if (!(item_flags & layer))
4811 return rte_flow_error_set(error, EINVAL,
4812 RTE_FLOW_ERROR_TYPE_ACTION,
4814 "no IP protocol in pattern");
4820 * Validate the generic modify field actions.
4822 * Pointer to the rte_eth_dev structure.
4823 * @param[in] action_flags
4824 * Holds the actions detected until now.
4826 * Pointer to the modify action.
4828 * Pointer to the flow attributes.
4830 * Pointer to error structure.
4833 * Number of header fields to modify (0 or more) on success,
4834 * a negative errno value otherwise and rte_errno is set.
4837 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4838 const uint64_t action_flags,
4839 const struct rte_flow_action *action,
4840 const struct rte_flow_attr *attr,
4841 struct rte_flow_error *error)
4844 struct mlx5_priv *priv = dev->data->dev_private;
4845 struct mlx5_sh_config *config = &priv->sh->config;
4846 const struct rte_flow_action_modify_field *action_modify_field =
4848 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4849 action_modify_field->dst.field,
4851 uint32_t src_width = mlx5_flow_item_field_width(dev,
4852 action_modify_field->src.field,
4853 dst_width, attr, error);
4855 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4859 if (action_modify_field->width == 0)
4860 return rte_flow_error_set(error, EINVAL,
4861 RTE_FLOW_ERROR_TYPE_ACTION, action,
4862 "no bits are requested to be modified");
4863 else if (action_modify_field->width > dst_width ||
4864 action_modify_field->width > src_width)
4865 return rte_flow_error_set(error, EINVAL,
4866 RTE_FLOW_ERROR_TYPE_ACTION, action,
4867 "cannot modify more bits than"
4868 " the width of a field");
4869 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4870 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4871 if ((action_modify_field->dst.offset +
4872 action_modify_field->width > dst_width) ||
4873 (action_modify_field->dst.offset % 32))
4874 return rte_flow_error_set(error, EINVAL,
4875 RTE_FLOW_ERROR_TYPE_ACTION, action,
4876 "destination offset is too big"
4877 " or not aligned to 4 bytes");
4878 if (action_modify_field->dst.level &&
4879 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4880 return rte_flow_error_set(error, ENOTSUP,
4881 RTE_FLOW_ERROR_TYPE_ACTION, action,
4882 "inner header fields modification"
4883 " is not supported");
4885 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4886 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4887 if (!attr->transfer && !attr->group)
4888 return rte_flow_error_set(error, ENOTSUP,
4889 RTE_FLOW_ERROR_TYPE_ACTION, action,
4890 "modify field action is not"
4891 " supported for group 0");
4892 if ((action_modify_field->src.offset +
4893 action_modify_field->width > src_width) ||
4894 (action_modify_field->src.offset % 32))
4895 return rte_flow_error_set(error, EINVAL,
4896 RTE_FLOW_ERROR_TYPE_ACTION, action,
4897 "source offset is too big"
4898 " or not aligned to 4 bytes");
4899 if (action_modify_field->src.level &&
4900 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4901 return rte_flow_error_set(error, ENOTSUP,
4902 RTE_FLOW_ERROR_TYPE_ACTION, action,
4903 "inner header fields modification"
4904 " is not supported");
4906 if ((action_modify_field->dst.field ==
4907 action_modify_field->src.field) &&
4908 (action_modify_field->dst.level ==
4909 action_modify_field->src.level))
4910 return rte_flow_error_set(error, EINVAL,
4911 RTE_FLOW_ERROR_TYPE_ACTION, action,
4912 "source and destination fields"
4913 " cannot be the same");
4914 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4915 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4916 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4917 return rte_flow_error_set(error, EINVAL,
4918 RTE_FLOW_ERROR_TYPE_ACTION, action,
4919 "mark, immediate value or a pointer to it"
4920 " cannot be used as a destination");
4921 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4922 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4923 return rte_flow_error_set(error, ENOTSUP,
4924 RTE_FLOW_ERROR_TYPE_ACTION, action,
4925 "modifications of an arbitrary"
4926 " place in a packet is not supported");
4927 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4928 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4929 return rte_flow_error_set(error, ENOTSUP,
4930 RTE_FLOW_ERROR_TYPE_ACTION, action,
4931 "modifications of the 802.1Q Tag"
4932 " Identifier is not supported");
4933 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4934 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4935 return rte_flow_error_set(error, ENOTSUP,
4936 RTE_FLOW_ERROR_TYPE_ACTION, action,
4937 "modifications of the VXLAN Network"
4938 " Identifier is not supported");
4939 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4940 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4941 return rte_flow_error_set(error, ENOTSUP,
4942 RTE_FLOW_ERROR_TYPE_ACTION, action,
4943 "modifications of the GENEVE Network"
4944 " Identifier is not supported");
4945 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4946 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4947 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4948 !mlx5_flow_ext_mreg_supported(dev))
4949 return rte_flow_error_set(error, ENOTSUP,
4950 RTE_FLOW_ERROR_TYPE_ACTION, action,
4951 "cannot modify mark in legacy mode"
4952 " or without extensive registers");
4953 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4954 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4955 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4956 !mlx5_flow_ext_mreg_supported(dev))
4957 return rte_flow_error_set(error, ENOTSUP,
4958 RTE_FLOW_ERROR_TYPE_ACTION, action,
4959 "cannot modify meta without"
4960 " extensive registers support");
4961 ret = flow_dv_get_metadata_reg(dev, attr, error);
4962 if (ret < 0 || ret == REG_NON)
4963 return rte_flow_error_set(error, ENOTSUP,
4964 RTE_FLOW_ERROR_TYPE_ACTION, action,
4965 "cannot modify meta without"
4966 " extensive registers available");
4968 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4969 return rte_flow_error_set(error, ENOTSUP,
4970 RTE_FLOW_ERROR_TYPE_ACTION, action,
4971 "add and sub operations"
4972 " are not supported");
4973 return (action_modify_field->width / 32) +
4974 !!(action_modify_field->width % 32);
4978 * Validate jump action.
4981 * Pointer to the jump action.
4982 * @param[in] action_flags
4983 * Holds the actions detected until now.
4984 * @param[in] attributes
4985 * Pointer to flow attributes
4986 * @param[in] external
4987 * Action belongs to flow rule created by request external to PMD.
4989 * Pointer to error structure.
4992 * 0 on success, a negative errno value otherwise and rte_errno is set.
4995 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4996 const struct mlx5_flow_tunnel *tunnel,
4997 const struct rte_flow_action *action,
4998 uint64_t action_flags,
4999 const struct rte_flow_attr *attributes,
5000 bool external, struct rte_flow_error *error)
5002 uint32_t target_group, table = 0;
5004 struct flow_grp_info grp_info = {
5005 .external = !!external,
5006 .transfer = !!attributes->transfer,
5010 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5011 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "can't have 2 fate actions in"
5017 return rte_flow_error_set(error, EINVAL,
5018 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5019 NULL, "action configuration not set");
5021 ((const struct rte_flow_action_jump *)action->conf)->group;
5022 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5026 if (attributes->group == target_group &&
5027 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5028 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5029 return rte_flow_error_set(error, EINVAL,
5030 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5031 "target group must be other than"
5032 " the current flow group");
5034 return rte_flow_error_set(error, EINVAL,
5035 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5036 NULL, "root table shouldn't be destination");
5041 * Validate action PORT_ID / REPRESENTED_PORT.
5044 * Pointer to rte_eth_dev structure.
5045 * @param[in] action_flags
5046 * Bit-fields that holds the actions detected until now.
5048 * PORT_ID / REPRESENTED_PORT action structure.
5050 * Attributes of flow that includes this action.
5052 * Pointer to error structure.
5055 * 0 on success, a negative errno value otherwise and rte_errno is set.
5058 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5059 uint64_t action_flags,
5060 const struct rte_flow_action *action,
5061 const struct rte_flow_attr *attr,
5062 struct rte_flow_error *error)
5064 const struct rte_flow_action_port_id *port_id;
5065 const struct rte_flow_action_ethdev *ethdev;
5066 struct mlx5_priv *act_priv;
5067 struct mlx5_priv *dev_priv;
5070 if (!attr->transfer)
5071 return rte_flow_error_set(error, ENOTSUP,
5072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5074 "port action is valid in transfer"
5076 if (!action || !action->conf)
5077 return rte_flow_error_set(error, ENOTSUP,
5078 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5080 "port action parameters must be"
5082 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5083 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5084 return rte_flow_error_set(error, EINVAL,
5085 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5086 "can have only one fate actions in"
5088 dev_priv = mlx5_dev_to_eswitch_info(dev);
5090 return rte_flow_error_set(error, rte_errno,
5091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5093 "failed to obtain E-Switch info");
5094 switch (action->type) {
5095 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5096 port_id = action->conf;
5097 port = port_id->original ? dev->data->port_id : port_id->id;
5099 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5100 ethdev = action->conf;
5101 port = ethdev->port_id;
5105 return rte_flow_error_set
5107 RTE_FLOW_ERROR_TYPE_ACTION, action,
5108 "unknown E-Switch action");
5110 act_priv = mlx5_port_to_eswitch_info(port, false);
5112 return rte_flow_error_set
5114 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5115 "failed to obtain E-Switch port id for port");
5116 if (act_priv->domain_id != dev_priv->domain_id)
5117 return rte_flow_error_set
5119 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5120 "port does not belong to"
5121 " E-Switch being configured");
5126 * Get the maximum number of modify header actions.
5129 * Pointer to rte_eth_dev structure.
5131 * Whether action is on root table.
5134 * Max number of modify header actions device can support.
5136 static inline unsigned int
5137 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5141 * There's no way to directly query the max capacity from FW.
5142 * The maximal value on root table should be assumed to be supported.
5145 return MLX5_MAX_MODIFY_NUM;
5147 return MLX5_ROOT_TBL_MODIFY_NUM;
5151 * Validate the meter action.
5154 * Pointer to rte_eth_dev structure.
5155 * @param[in] action_flags
5156 * Bit-fields that holds the actions detected until now.
5157 * @param[in] item_flags
5158 * Holds the items detected.
5160 * Pointer to the meter action.
5162 * Attributes of flow that includes this action.
5163 * @param[in] port_id_item
5164 * Pointer to item indicating port id.
5166 * Pointer to error structure.
5169 * 0 on success, a negative errno value otherwise and rte_errno is set.
5172 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5173 uint64_t action_flags, uint64_t item_flags,
5174 const struct rte_flow_action *action,
5175 const struct rte_flow_attr *attr,
5176 const struct rte_flow_item *port_id_item,
5178 struct rte_flow_error *error)
5180 struct mlx5_priv *priv = dev->data->dev_private;
5181 const struct rte_flow_action_meter *am = action->conf;
5182 struct mlx5_flow_meter_info *fm;
5183 struct mlx5_flow_meter_policy *mtr_policy;
5184 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5187 return rte_flow_error_set(error, EINVAL,
5188 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5189 "meter action conf is NULL");
5191 if (action_flags & MLX5_FLOW_ACTION_METER)
5192 return rte_flow_error_set(error, ENOTSUP,
5193 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5194 "meter chaining not support");
5195 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5196 return rte_flow_error_set(error, ENOTSUP,
5197 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5198 "meter with jump not support");
5200 return rte_flow_error_set(error, ENOTSUP,
5201 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5203 "meter action not supported");
5204 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5206 return rte_flow_error_set(error, EINVAL,
5207 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5209 /* aso meter can always be shared by different domains */
5210 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5211 !(fm->transfer == attr->transfer ||
5212 (!fm->ingress && !attr->ingress && attr->egress) ||
5213 (!fm->egress && !attr->egress && attr->ingress)))
5214 return rte_flow_error_set(error, EINVAL,
5215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5216 "Flow attributes domain are either invalid "
5217 "or have a domain conflict with current "
5218 "meter attributes");
5219 if (fm->def_policy) {
5220 if (!((attr->transfer &&
5221 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5223 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5225 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5226 return rte_flow_error_set(error, EINVAL,
5227 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5228 "Flow attributes domain "
5229 "have a conflict with current "
5230 "meter domain attributes");
5233 mtr_policy = mlx5_flow_meter_policy_find(dev,
5234 fm->policy_id, NULL);
5236 return rte_flow_error_set(error, EINVAL,
5237 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5238 "Invalid policy id for meter ");
5239 if (!((attr->transfer && mtr_policy->transfer) ||
5240 (attr->egress && mtr_policy->egress) ||
5241 (attr->ingress && mtr_policy->ingress)))
5242 return rte_flow_error_set(error, EINVAL,
5243 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5244 "Flow attributes domain "
5245 "have a conflict with current "
5246 "meter domain attributes");
5247 if (attr->transfer && mtr_policy->dev) {
5249 * When policy has fate action of port_id,
5250 * the flow should have the same src port as policy.
5252 struct mlx5_priv *policy_port_priv =
5253 mtr_policy->dev->data->dev_private;
5254 int32_t flow_src_port = priv->representor_id;
5257 const struct rte_flow_item_port_id *spec =
5259 struct mlx5_priv *port_priv =
5260 mlx5_port_to_eswitch_info(spec->id,
5263 return rte_flow_error_set(error,
5265 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5267 "Failed to get port info.");
5268 flow_src_port = port_priv->representor_id;
5270 if (flow_src_port != policy_port_priv->representor_id)
5271 return rte_flow_error_set(error,
5273 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5275 "Flow and meter policy "
5276 "have different src port.");
5277 } else if (mtr_policy->is_rss) {
5278 struct mlx5_flow_meter_policy *fp;
5279 struct mlx5_meter_policy_action_container *acg;
5280 struct mlx5_meter_policy_action_container *acy;
5281 const struct rte_flow_action *rss_act;
5284 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5287 return rte_flow_error_set(error, EINVAL,
5288 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5289 "Unable to get the final "
5290 "policy in the hierarchy");
5291 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5292 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5293 MLX5_ASSERT(acg->fate_action ==
5294 MLX5_FLOW_FATE_SHARED_RSS ||
5296 MLX5_FLOW_FATE_SHARED_RSS);
5297 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5301 ret = mlx5_flow_validate_action_rss(rss_act,
5302 action_flags, dev, attr,
5307 *def_policy = false;
5313 * Validate the age action.
5315 * @param[in] action_flags
5316 * Holds the actions detected until now.
5318 * Pointer to the age action.
5320 * Pointer to the Ethernet device structure.
5322 * Pointer to error structure.
5325 * 0 on success, a negative errno value otherwise and rte_errno is set.
5328 flow_dv_validate_action_age(uint64_t action_flags,
5329 const struct rte_flow_action *action,
5330 struct rte_eth_dev *dev,
5331 struct rte_flow_error *error)
5333 struct mlx5_priv *priv = dev->data->dev_private;
5334 const struct rte_flow_action_age *age = action->conf;
5336 if (!priv->sh->cdev->config.devx ||
5337 (priv->sh->cmng.counter_fallback && !priv->sh->aso_age_mng))
5338 return rte_flow_error_set(error, ENOTSUP,
5339 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5341 "age action not supported");
5342 if (!(action->conf))
5343 return rte_flow_error_set(error, EINVAL,
5344 RTE_FLOW_ERROR_TYPE_ACTION, action,
5345 "configuration cannot be null");
5346 if (!(age->timeout))
5347 return rte_flow_error_set(error, EINVAL,
5348 RTE_FLOW_ERROR_TYPE_ACTION, action,
5349 "invalid timeout value 0");
5350 if (action_flags & MLX5_FLOW_ACTION_AGE)
5351 return rte_flow_error_set(error, EINVAL,
5352 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5353 "duplicate age actions set");
5358 * Validate the modify-header IPv4 DSCP actions.
5360 * @param[in] action_flags
5361 * Holds the actions detected until now.
5363 * Pointer to the modify action.
5364 * @param[in] item_flags
5365 * Holds the items detected.
5367 * Pointer to error structure.
5370 * 0 on success, a negative errno value otherwise and rte_errno is set.
5373 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5374 const struct rte_flow_action *action,
5375 const uint64_t item_flags,
5376 struct rte_flow_error *error)
5380 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5382 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5383 return rte_flow_error_set(error, EINVAL,
5384 RTE_FLOW_ERROR_TYPE_ACTION,
5386 "no ipv4 item in pattern");
5392 * Validate the modify-header IPv6 DSCP actions.
5394 * @param[in] action_flags
5395 * Holds the actions detected until now.
5397 * Pointer to the modify action.
5398 * @param[in] item_flags
5399 * Holds the items detected.
5401 * Pointer to error structure.
5404 * 0 on success, a negative errno value otherwise and rte_errno is set.
5407 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5408 const struct rte_flow_action *action,
5409 const uint64_t item_flags,
5410 struct rte_flow_error *error)
5414 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5416 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5417 return rte_flow_error_set(error, EINVAL,
5418 RTE_FLOW_ERROR_TYPE_ACTION,
5420 "no ipv6 item in pattern");
5426 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5427 struct mlx5_list_entry *entry, void *cb_ctx)
5429 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5430 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5431 struct mlx5_flow_dv_modify_hdr_resource *resource =
5432 container_of(entry, typeof(*resource), entry);
5433 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5435 key_len += ref->actions_num * sizeof(ref->actions[0]);
5436 return ref->actions_num != resource->actions_num ||
5437 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5440 static struct mlx5_indexed_pool *
5441 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5443 struct mlx5_indexed_pool *ipool = __atomic_load_n
5444 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5447 struct mlx5_indexed_pool *expected = NULL;
5448 struct mlx5_indexed_pool_config cfg =
5449 (struct mlx5_indexed_pool_config) {
5450 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5452 sizeof(struct mlx5_modification_cmd),
5457 .release_mem_en = !!sh->config.reclaim_mode,
5459 sh->config.reclaim_mode ? 0 : (1 << 16),
5460 .malloc = mlx5_malloc,
5462 .type = "mlx5_modify_action_resource",
5465 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5466 ipool = mlx5_ipool_create(&cfg);
5469 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5470 &expected, ipool, false,
5472 __ATOMIC_SEQ_CST)) {
5473 mlx5_ipool_destroy(ipool);
5474 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5481 struct mlx5_list_entry *
5482 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5484 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5485 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5486 struct mlx5dv_dr_domain *ns;
5487 struct mlx5_flow_dv_modify_hdr_resource *entry;
5488 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5489 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5490 ref->actions_num - 1);
5492 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5493 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5496 if (unlikely(!ipool)) {
5497 rte_flow_error_set(ctx->error, ENOMEM,
5498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5499 NULL, "cannot allocate modify ipool");
5502 entry = mlx5_ipool_zmalloc(ipool, &idx);
5504 rte_flow_error_set(ctx->error, ENOMEM,
5505 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5506 "cannot allocate resource memory");
5509 rte_memcpy(&entry->ft_type,
5510 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5511 key_len + data_len);
5512 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5513 ns = sh->fdb_domain;
5514 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5518 ret = mlx5_flow_os_create_flow_action_modify_header
5519 (sh->cdev->ctx, ns, entry,
5520 data_len, &entry->action);
5522 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5523 rte_flow_error_set(ctx->error, ENOMEM,
5524 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5525 NULL, "cannot create modification action");
5529 return &entry->entry;
5532 struct mlx5_list_entry *
5533 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5536 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5537 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5538 struct mlx5_flow_dv_modify_hdr_resource *entry;
5539 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5540 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5543 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5546 rte_flow_error_set(ctx->error, ENOMEM,
5547 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5548 "cannot allocate resource memory");
5551 memcpy(entry, oentry, sizeof(*entry) + data_len);
5553 return &entry->entry;
5557 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5559 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5560 struct mlx5_flow_dv_modify_hdr_resource *res =
5561 container_of(entry, typeof(*res), entry);
5563 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5567 * Validate the sample action.
5569 * @param[in, out] action_flags
5570 * Holds the actions detected until now.
5572 * Pointer to the sample action.
5574 * Pointer to the Ethernet device structure.
5576 * Attributes of flow that includes this action.
5577 * @param[in] item_flags
5578 * Holds the items detected.
5580 * Pointer to the RSS action.
5581 * @param[out] sample_rss
5582 * Pointer to the RSS action in sample action list.
5584 * Pointer to the COUNT action in sample action list.
5585 * @param[out] fdb_mirror_limit
5586 * Pointer to the FDB mirror limitation flag.
5588 * Pointer to error structure.
5591 * 0 on success, a negative errno value otherwise and rte_errno is set.
5594 flow_dv_validate_action_sample(uint64_t *action_flags,
5595 const struct rte_flow_action *action,
5596 struct rte_eth_dev *dev,
5597 const struct rte_flow_attr *attr,
5598 uint64_t item_flags,
5599 const struct rte_flow_action_rss *rss,
5600 const struct rte_flow_action_rss **sample_rss,
5601 const struct rte_flow_action_count **count,
5602 int *fdb_mirror_limit,
5603 struct rte_flow_error *error)
5605 struct mlx5_priv *priv = dev->data->dev_private;
5606 struct mlx5_sh_config *dev_conf = &priv->sh->config;
5607 const struct rte_flow_action_sample *sample = action->conf;
5608 const struct rte_flow_action *act;
5609 uint64_t sub_action_flags = 0;
5610 uint16_t queue_index = 0xFFFF;
5615 return rte_flow_error_set(error, EINVAL,
5616 RTE_FLOW_ERROR_TYPE_ACTION, action,
5617 "configuration cannot be NULL");
5618 if (sample->ratio == 0)
5619 return rte_flow_error_set(error, EINVAL,
5620 RTE_FLOW_ERROR_TYPE_ACTION, action,
5621 "ratio value starts from 1");
5622 if (!priv->sh->cdev->config.devx ||
5623 (sample->ratio > 0 && !priv->sampler_en))
5624 return rte_flow_error_set(error, ENOTSUP,
5625 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5627 "sample action not supported");
5628 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5629 return rte_flow_error_set(error, EINVAL,
5630 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5631 "Multiple sample actions not "
5633 if (*action_flags & MLX5_FLOW_ACTION_METER)
5634 return rte_flow_error_set(error, EINVAL,
5635 RTE_FLOW_ERROR_TYPE_ACTION, action,
5636 "wrong action order, meter should "
5637 "be after sample action");
5638 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5639 return rte_flow_error_set(error, EINVAL,
5640 RTE_FLOW_ERROR_TYPE_ACTION, action,
5641 "wrong action order, jump should "
5642 "be after sample action");
5643 if (*action_flags & MLX5_FLOW_ACTION_CT)
5644 return rte_flow_error_set(error, EINVAL,
5645 RTE_FLOW_ERROR_TYPE_ACTION, action,
5646 "Sample after CT not supported");
5647 act = sample->actions;
5648 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5649 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5650 return rte_flow_error_set(error, ENOTSUP,
5651 RTE_FLOW_ERROR_TYPE_ACTION,
5652 act, "too many actions");
5653 switch (act->type) {
5654 case RTE_FLOW_ACTION_TYPE_QUEUE:
5655 ret = mlx5_flow_validate_action_queue(act,
5661 queue_index = ((const struct rte_flow_action_queue *)
5662 (act->conf))->index;
5663 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5666 case RTE_FLOW_ACTION_TYPE_RSS:
5667 *sample_rss = act->conf;
5668 ret = mlx5_flow_validate_action_rss(act,
5675 if (rss && *sample_rss &&
5676 ((*sample_rss)->level != rss->level ||
5677 (*sample_rss)->types != rss->types))
5678 return rte_flow_error_set(error, ENOTSUP,
5679 RTE_FLOW_ERROR_TYPE_ACTION,
5681 "Can't use the different RSS types "
5682 "or level in the same flow");
5683 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5684 queue_index = (*sample_rss)->queue[0];
5685 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5688 case RTE_FLOW_ACTION_TYPE_MARK:
5689 ret = flow_dv_validate_action_mark(dev, act,
5694 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5695 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5696 MLX5_FLOW_ACTION_MARK_EXT;
5698 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5701 case RTE_FLOW_ACTION_TYPE_COUNT:
5702 ret = flow_dv_validate_action_count
5703 (dev, false, *action_flags | sub_action_flags,
5708 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5709 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5712 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5713 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5714 ret = flow_dv_validate_action_port_id(dev,
5721 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5724 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5725 ret = flow_dv_validate_action_raw_encap_decap
5726 (dev, NULL, act->conf, attr, &sub_action_flags,
5727 &actions_n, action, item_flags, error);
5732 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5733 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5734 ret = flow_dv_validate_action_l2_encap(dev,
5740 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5744 return rte_flow_error_set(error, ENOTSUP,
5745 RTE_FLOW_ERROR_TYPE_ACTION,
5747 "Doesn't support optional "
5751 if (attr->ingress && !attr->transfer) {
5752 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5753 MLX5_FLOW_ACTION_RSS)))
5754 return rte_flow_error_set(error, EINVAL,
5755 RTE_FLOW_ERROR_TYPE_ACTION,
5757 "Ingress must has a dest "
5758 "QUEUE for Sample");
5759 } else if (attr->egress && !attr->transfer) {
5760 return rte_flow_error_set(error, ENOTSUP,
5761 RTE_FLOW_ERROR_TYPE_ACTION,
5763 "Sample Only support Ingress "
5765 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5766 MLX5_ASSERT(attr->transfer);
5767 if (sample->ratio > 1)
5768 return rte_flow_error_set(error, ENOTSUP,
5769 RTE_FLOW_ERROR_TYPE_ACTION,
5771 "E-Switch doesn't support "
5772 "any optional action "
5774 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5775 return rte_flow_error_set(error, ENOTSUP,
5776 RTE_FLOW_ERROR_TYPE_ACTION,
5778 "unsupported action QUEUE");
5779 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5780 return rte_flow_error_set(error, ENOTSUP,
5781 RTE_FLOW_ERROR_TYPE_ACTION,
5783 "unsupported action QUEUE");
5784 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5785 return rte_flow_error_set(error, EINVAL,
5786 RTE_FLOW_ERROR_TYPE_ACTION,
5788 "E-Switch must has a dest "
5789 "port for mirroring");
5790 if (!priv->sh->cdev->config.hca_attr.reg_c_preserve &&
5791 priv->representor_id != UINT16_MAX)
5792 *fdb_mirror_limit = 1;
5794 /* Continue validation for Xcap actions.*/
5795 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5796 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index))) {
5797 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5798 MLX5_FLOW_XCAP_ACTIONS)
5799 return rte_flow_error_set(error, ENOTSUP,
5800 RTE_FLOW_ERROR_TYPE_ACTION,
5801 NULL, "encap and decap "
5802 "combination aren't "
5804 if (!attr->transfer && attr->ingress && (sub_action_flags &
5805 MLX5_FLOW_ACTION_ENCAP))
5806 return rte_flow_error_set(error, ENOTSUP,
5807 RTE_FLOW_ERROR_TYPE_ACTION,
5808 NULL, "encap is not supported"
5809 " for ingress traffic");
5815 * Find existing modify-header resource or create and register a new one.
5817 * @param dev[in, out]
5818 * Pointer to rte_eth_dev structure.
5819 * @param[in, out] resource
5820 * Pointer to modify-header resource.
5821 * @parm[in, out] dev_flow
5822 * Pointer to the dev_flow.
5824 * pointer to error structure.
5827 * 0 on success otherwise -errno and errno is set.
5830 flow_dv_modify_hdr_resource_register
5831 (struct rte_eth_dev *dev,
5832 struct mlx5_flow_dv_modify_hdr_resource *resource,
5833 struct mlx5_flow *dev_flow,
5834 struct rte_flow_error *error)
5836 struct mlx5_priv *priv = dev->data->dev_private;
5837 struct mlx5_dev_ctx_shared *sh = priv->sh;
5838 uint32_t key_len = sizeof(*resource) -
5839 offsetof(typeof(*resource), ft_type) +
5840 resource->actions_num * sizeof(resource->actions[0]);
5841 struct mlx5_list_entry *entry;
5842 struct mlx5_flow_cb_ctx ctx = {
5846 struct mlx5_hlist *modify_cmds;
5849 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5851 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5853 flow_dv_modify_create_cb,
5854 flow_dv_modify_match_cb,
5855 flow_dv_modify_remove_cb,
5856 flow_dv_modify_clone_cb,
5857 flow_dv_modify_clone_free_cb,
5859 if (unlikely(!modify_cmds))
5861 resource->root = !dev_flow->dv.group;
5862 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5864 return rte_flow_error_set(error, EOVERFLOW,
5865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5866 "too many modify header items");
5867 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5868 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5871 resource = container_of(entry, typeof(*resource), entry);
5872 dev_flow->handle->dvh.modify_hdr = resource;
5877 * Get DV flow counter by index.
5880 * Pointer to the Ethernet device structure.
5882 * mlx5 flow counter index in the container.
5884 * mlx5 flow counter pool in the container.
5887 * Pointer to the counter, NULL otherwise.
5889 static struct mlx5_flow_counter *
5890 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5892 struct mlx5_flow_counter_pool **ppool)
5894 struct mlx5_priv *priv = dev->data->dev_private;
5895 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5896 struct mlx5_flow_counter_pool *pool;
5898 /* Decrease to original index and clear shared bit. */
5899 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5900 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5901 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5905 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5909 * Check the devx counter belongs to the pool.
5912 * Pointer to the counter pool.
5914 * The counter devx ID.
5917 * True if counter belongs to the pool, false otherwise.
5920 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5922 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5923 MLX5_COUNTERS_PER_POOL;
5925 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5931 * Get a pool by devx counter ID.
5934 * Pointer to the counter management.
5936 * The counter devx ID.
5939 * The counter pool pointer if exists, NULL otherwise,
5941 static struct mlx5_flow_counter_pool *
5942 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5945 struct mlx5_flow_counter_pool *pool = NULL;
5947 rte_spinlock_lock(&cmng->pool_update_sl);
5948 /* Check last used pool. */
5949 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5950 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5951 pool = cmng->pools[cmng->last_pool_idx];
5954 /* ID out of range means no suitable pool in the container. */
5955 if (id > cmng->max_id || id < cmng->min_id)
5958 * Find the pool from the end of the container, since mostly counter
5959 * ID is sequence increasing, and the last pool should be the needed
5964 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5966 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5972 rte_spinlock_unlock(&cmng->pool_update_sl);
5977 * Resize a counter container.
5980 * Pointer to the Ethernet device structure.
5983 * 0 on success, otherwise negative errno value and rte_errno is set.
5986 flow_dv_container_resize(struct rte_eth_dev *dev)
5988 struct mlx5_priv *priv = dev->data->dev_private;
5989 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5990 void *old_pools = cmng->pools;
5991 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5992 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5993 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6000 memcpy(pools, old_pools, cmng->n *
6001 sizeof(struct mlx5_flow_counter_pool *));
6003 cmng->pools = pools;
6005 mlx5_free(old_pools);
6010 * Query a devx flow counter.
6013 * Pointer to the Ethernet device structure.
6014 * @param[in] counter
6015 * Index to the flow counter.
6017 * The statistics value of packets.
6019 * The statistics value of bytes.
6022 * 0 on success, otherwise a negative errno value and rte_errno is set.
6025 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
6028 struct mlx5_priv *priv = dev->data->dev_private;
6029 struct mlx5_flow_counter_pool *pool = NULL;
6030 struct mlx5_flow_counter *cnt;
6033 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6035 if (priv->sh->cmng.counter_fallback)
6036 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6037 0, pkts, bytes, 0, NULL, NULL, 0);
6038 rte_spinlock_lock(&pool->sl);
6043 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6044 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6045 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6047 rte_spinlock_unlock(&pool->sl);
6052 * Create and initialize a new counter pool.
6055 * Pointer to the Ethernet device structure.
6057 * The devX counter handle.
6059 * Whether the pool is for counter that was allocated for aging.
6060 * @param[in/out] cont_cur
6061 * Pointer to the container pointer, it will be update in pool resize.
6064 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6066 static struct mlx5_flow_counter_pool *
6067 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6070 struct mlx5_priv *priv = dev->data->dev_private;
6071 struct mlx5_flow_counter_pool *pool;
6072 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6073 bool fallback = priv->sh->cmng.counter_fallback;
6074 uint32_t size = sizeof(*pool);
6076 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6077 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6078 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6084 pool->is_aged = !!age;
6085 pool->query_gen = 0;
6086 pool->min_dcs = dcs;
6087 rte_spinlock_init(&pool->sl);
6088 rte_spinlock_init(&pool->csl);
6089 TAILQ_INIT(&pool->counters[0]);
6090 TAILQ_INIT(&pool->counters[1]);
6091 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6092 rte_spinlock_lock(&cmng->pool_update_sl);
6093 pool->index = cmng->n_valid;
6094 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6096 rte_spinlock_unlock(&cmng->pool_update_sl);
6099 cmng->pools[pool->index] = pool;
6101 if (unlikely(fallback)) {
6102 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6104 if (base < cmng->min_id)
6105 cmng->min_id = base;
6106 if (base > cmng->max_id)
6107 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6108 cmng->last_pool_idx = pool->index;
6110 rte_spinlock_unlock(&cmng->pool_update_sl);
6115 * Prepare a new counter and/or a new counter pool.
6118 * Pointer to the Ethernet device structure.
6119 * @param[out] cnt_free
6120 * Where to put the pointer of a new counter.
6122 * Whether the pool is for counter that was allocated for aging.
6125 * The counter pool pointer and @p cnt_free is set on success,
6126 * NULL otherwise and rte_errno is set.
6128 static struct mlx5_flow_counter_pool *
6129 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6130 struct mlx5_flow_counter **cnt_free,
6133 struct mlx5_priv *priv = dev->data->dev_private;
6134 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6135 struct mlx5_flow_counter_pool *pool;
6136 struct mlx5_counters tmp_tq;
6137 struct mlx5_devx_obj *dcs = NULL;
6138 struct mlx5_flow_counter *cnt;
6139 enum mlx5_counter_type cnt_type =
6140 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6141 bool fallback = priv->sh->cmng.counter_fallback;
6145 /* bulk_bitmap must be 0 for single counter allocation. */
6146 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6149 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6151 pool = flow_dv_pool_create(dev, dcs, age);
6153 mlx5_devx_cmd_destroy(dcs);
6157 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6158 cnt = MLX5_POOL_GET_CNT(pool, i);
6160 cnt->dcs_when_free = dcs;
6164 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6166 rte_errno = ENODATA;
6169 pool = flow_dv_pool_create(dev, dcs, age);
6171 mlx5_devx_cmd_destroy(dcs);
6174 TAILQ_INIT(&tmp_tq);
6175 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6176 cnt = MLX5_POOL_GET_CNT(pool, i);
6178 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6180 rte_spinlock_lock(&cmng->csl[cnt_type]);
6181 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6182 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6183 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6184 (*cnt_free)->pool = pool;
6189 * Allocate a flow counter.
6192 * Pointer to the Ethernet device structure.
6194 * Whether the counter was allocated for aging.
6197 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6200 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6202 struct mlx5_priv *priv = dev->data->dev_private;
6203 struct mlx5_flow_counter_pool *pool = NULL;
6204 struct mlx5_flow_counter *cnt_free = NULL;
6205 bool fallback = priv->sh->cmng.counter_fallback;
6206 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6207 enum mlx5_counter_type cnt_type =
6208 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6211 if (!priv->sh->cdev->config.devx) {
6212 rte_errno = ENOTSUP;
6215 /* Get free counters from container. */
6216 rte_spinlock_lock(&cmng->csl[cnt_type]);
6217 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6219 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6220 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6221 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6223 pool = cnt_free->pool;
6225 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6226 /* Create a DV counter action only in the first time usage. */
6227 if (!cnt_free->action) {
6229 struct mlx5_devx_obj *dcs;
6233 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6234 dcs = pool->min_dcs;
6237 dcs = cnt_free->dcs_when_free;
6239 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6246 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6247 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6248 /* Update the counter reset values. */
6249 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6252 if (!fallback && !priv->sh->cmng.query_thread_on)
6253 /* Start the asynchronous batch query by the host thread. */
6254 mlx5_set_query_alarm(priv->sh);
6256 * When the count action isn't shared (by ID), shared_info field is
6257 * used for indirect action API's refcnt.
6258 * When the counter action is not shared neither by ID nor by indirect
6259 * action API, shared info must be 1.
6261 cnt_free->shared_info.refcnt = 1;
6265 cnt_free->pool = pool;
6267 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6268 rte_spinlock_lock(&cmng->csl[cnt_type]);
6269 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6270 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6276 * Get age param from counter index.
6279 * Pointer to the Ethernet device structure.
6280 * @param[in] counter
6281 * Index to the counter handler.
6284 * The aging parameter specified for the counter index.
6286 static struct mlx5_age_param*
6287 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6290 struct mlx5_flow_counter *cnt;
6291 struct mlx5_flow_counter_pool *pool = NULL;
6293 flow_dv_counter_get_by_idx(dev, counter, &pool);
6294 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6295 cnt = MLX5_POOL_GET_CNT(pool, counter);
6296 return MLX5_CNT_TO_AGE(cnt);
6300 * Remove a flow counter from aged counter list.
6303 * Pointer to the Ethernet device structure.
6304 * @param[in] counter
6305 * Index to the counter handler.
6307 * Pointer to the counter handler.
6310 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6311 uint32_t counter, struct mlx5_flow_counter *cnt)
6313 struct mlx5_age_info *age_info;
6314 struct mlx5_age_param *age_param;
6315 struct mlx5_priv *priv = dev->data->dev_private;
6316 uint16_t expected = AGE_CANDIDATE;
6318 age_info = GET_PORT_AGE_INFO(priv);
6319 age_param = flow_dv_counter_idx_get_age(dev, counter);
6320 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6321 AGE_FREE, false, __ATOMIC_RELAXED,
6322 __ATOMIC_RELAXED)) {
6324 * We need the lock even it is age timeout,
6325 * since counter may still in process.
6327 rte_spinlock_lock(&age_info->aged_sl);
6328 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6329 rte_spinlock_unlock(&age_info->aged_sl);
6330 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6335 * Release a flow counter.
6338 * Pointer to the Ethernet device structure.
6339 * @param[in] counter
6340 * Index to the counter handler.
6343 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6345 struct mlx5_priv *priv = dev->data->dev_private;
6346 struct mlx5_flow_counter_pool *pool = NULL;
6347 struct mlx5_flow_counter *cnt;
6348 enum mlx5_counter_type cnt_type;
6352 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6354 if (pool->is_aged) {
6355 flow_dv_counter_remove_from_age(dev, counter, cnt);
6358 * If the counter action is shared by indirect action API,
6359 * the atomic function reduces its references counter.
6360 * If after the reduction the action is still referenced, the
6361 * function returns here and does not release it.
6362 * When the counter action is not shared by
6363 * indirect action API, shared info is 1 before the reduction,
6364 * so this condition is failed and function doesn't return here.
6366 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6372 * Put the counter back to list to be updated in none fallback mode.
6373 * Currently, we are using two list alternately, while one is in query,
6374 * add the freed counter to the other list based on the pool query_gen
6375 * value. After query finishes, add counter the list to the global
6376 * container counter list. The list changes while query starts. In
6377 * this case, lock will not be needed as query callback and release
6378 * function both operate with the different list.
6380 if (!priv->sh->cmng.counter_fallback) {
6381 rte_spinlock_lock(&pool->csl);
6382 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6383 rte_spinlock_unlock(&pool->csl);
6385 cnt->dcs_when_free = cnt->dcs_when_active;
6386 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6387 MLX5_COUNTER_TYPE_ORIGIN;
6388 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6389 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6391 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6396 * Resize a meter id container.
6399 * Pointer to the Ethernet device structure.
6402 * 0 on success, otherwise negative errno value and rte_errno is set.
6405 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6407 struct mlx5_priv *priv = dev->data->dev_private;
6408 struct mlx5_aso_mtr_pools_mng *pools_mng =
6409 &priv->sh->mtrmng->pools_mng;
6410 void *old_pools = pools_mng->pools;
6411 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6412 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6413 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6420 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6425 memcpy(pools, old_pools, pools_mng->n *
6426 sizeof(struct mlx5_aso_mtr_pool *));
6427 pools_mng->n = resize;
6428 pools_mng->pools = pools;
6430 mlx5_free(old_pools);
6435 * Prepare a new meter and/or a new meter pool.
6438 * Pointer to the Ethernet device structure.
6439 * @param[out] mtr_free
6440 * Where to put the pointer of a new meter.g.
6443 * The meter pool pointer and @mtr_free is set on success,
6444 * NULL otherwise and rte_errno is set.
6446 static struct mlx5_aso_mtr_pool *
6447 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6449 struct mlx5_priv *priv = dev->data->dev_private;
6450 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6451 struct mlx5_aso_mtr_pool *pool = NULL;
6452 struct mlx5_devx_obj *dcs = NULL;
6454 uint32_t log_obj_size;
6456 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6457 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6458 priv->sh->cdev->pdn,
6461 rte_errno = ENODATA;
6464 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6467 claim_zero(mlx5_devx_cmd_destroy(dcs));
6470 pool->devx_obj = dcs;
6471 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6472 pool->index = pools_mng->n_valid;
6473 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6475 claim_zero(mlx5_devx_cmd_destroy(dcs));
6476 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6479 pools_mng->pools[pool->index] = pool;
6480 pools_mng->n_valid++;
6481 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6482 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6483 pool->mtrs[i].offset = i;
6484 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6486 pool->mtrs[0].offset = 0;
6487 *mtr_free = &pool->mtrs[0];
6492 * Release a flow meter into pool.
6495 * Pointer to the Ethernet device structure.
6496 * @param[in] mtr_idx
6497 * Index to aso flow meter.
6500 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6502 struct mlx5_priv *priv = dev->data->dev_private;
6503 struct mlx5_aso_mtr_pools_mng *pools_mng =
6504 &priv->sh->mtrmng->pools_mng;
6505 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6507 MLX5_ASSERT(aso_mtr);
6508 rte_spinlock_lock(&pools_mng->mtrsl);
6509 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6510 aso_mtr->state = ASO_METER_FREE;
6511 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6512 rte_spinlock_unlock(&pools_mng->mtrsl);
6516 * Allocate a aso flow meter.
6519 * Pointer to the Ethernet device structure.
6522 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6525 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6527 struct mlx5_priv *priv = dev->data->dev_private;
6528 struct mlx5_aso_mtr *mtr_free = NULL;
6529 struct mlx5_aso_mtr_pools_mng *pools_mng =
6530 &priv->sh->mtrmng->pools_mng;
6531 struct mlx5_aso_mtr_pool *pool;
6532 uint32_t mtr_idx = 0;
6534 if (!priv->sh->cdev->config.devx) {
6535 rte_errno = ENOTSUP;
6538 /* Allocate the flow meter memory. */
6539 /* Get free meters from management. */
6540 rte_spinlock_lock(&pools_mng->mtrsl);
6541 mtr_free = LIST_FIRST(&pools_mng->meters);
6543 LIST_REMOVE(mtr_free, next);
6544 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6545 rte_spinlock_unlock(&pools_mng->mtrsl);
6548 mtr_free->state = ASO_METER_WAIT;
6549 rte_spinlock_unlock(&pools_mng->mtrsl);
6550 pool = container_of(mtr_free,
6551 struct mlx5_aso_mtr_pool,
6552 mtrs[mtr_free->offset]);
6553 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6554 if (!mtr_free->fm.meter_action) {
6555 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6556 struct rte_flow_error error;
6559 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6560 mtr_free->fm.meter_action =
6561 mlx5_glue->dv_create_flow_action_aso
6562 (priv->sh->rx_domain,
6563 pool->devx_obj->obj,
6565 (1 << MLX5_FLOW_COLOR_GREEN),
6567 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6568 if (!mtr_free->fm.meter_action) {
6569 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6577 * Verify the @p attributes will be correctly understood by the NIC and store
6578 * them in the @p flow if everything is correct.
6581 * Pointer to dev struct.
6582 * @param[in] attributes
6583 * Pointer to flow attributes
6584 * @param[in] external
6585 * This flow rule is created by request external to PMD.
6587 * Pointer to error structure.
6590 * - 0 on success and non root table.
6591 * - 1 on success and root table.
6592 * - a negative errno value otherwise and rte_errno is set.
6595 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6596 const struct mlx5_flow_tunnel *tunnel,
6597 const struct rte_flow_attr *attributes,
6598 const struct flow_grp_info *grp_info,
6599 struct rte_flow_error *error)
6601 struct mlx5_priv *priv = dev->data->dev_private;
6602 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6605 #ifndef HAVE_MLX5DV_DR
6606 RTE_SET_USED(tunnel);
6607 RTE_SET_USED(grp_info);
6608 if (attributes->group)
6609 return rte_flow_error_set(error, ENOTSUP,
6610 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6612 "groups are not supported");
6616 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6621 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6623 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6624 attributes->priority > lowest_priority)
6625 return rte_flow_error_set(error, ENOTSUP,
6626 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6628 "priority out of range");
6629 if (attributes->transfer) {
6630 if (!priv->sh->config.dv_esw_en)
6631 return rte_flow_error_set
6633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6634 "E-Switch dr is not supported");
6635 if (attributes->egress)
6636 return rte_flow_error_set
6638 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6639 "egress is not supported");
6641 if (!(attributes->egress ^ attributes->ingress))
6642 return rte_flow_error_set(error, ENOTSUP,
6643 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6644 "must specify exactly one of "
6645 "ingress or egress");
6650 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6651 int64_t pattern_flags, uint64_t l3_flags,
6652 uint64_t l4_flags, uint64_t ip4_flag,
6653 struct rte_flow_error *error)
6655 if (mask->l3_ok && !(pattern_flags & l3_flags))
6656 return rte_flow_error_set(error, EINVAL,
6657 RTE_FLOW_ERROR_TYPE_ITEM,
6658 NULL, "missing L3 protocol");
6660 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6661 return rte_flow_error_set(error, EINVAL,
6662 RTE_FLOW_ERROR_TYPE_ITEM,
6663 NULL, "missing IPv4 protocol");
6665 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6666 return rte_flow_error_set(error, EINVAL,
6667 RTE_FLOW_ERROR_TYPE_ITEM,
6668 NULL, "missing L4 protocol");
6674 flow_dv_validate_item_integrity_post(const struct
6675 rte_flow_item *integrity_items[2],
6676 int64_t pattern_flags,
6677 struct rte_flow_error *error)
6679 const struct rte_flow_item_integrity *mask;
6682 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6683 mask = (typeof(mask))integrity_items[0]->mask;
6684 ret = validate_integrity_bits(mask, pattern_flags,
6685 MLX5_FLOW_LAYER_OUTER_L3,
6686 MLX5_FLOW_LAYER_OUTER_L4,
6687 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6692 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6693 mask = (typeof(mask))integrity_items[1]->mask;
6694 ret = validate_integrity_bits(mask, pattern_flags,
6695 MLX5_FLOW_LAYER_INNER_L3,
6696 MLX5_FLOW_LAYER_INNER_L4,
6697 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6706 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6707 const struct rte_flow_item *integrity_item,
6708 uint64_t pattern_flags, uint64_t *last_item,
6709 const struct rte_flow_item *integrity_items[2],
6710 struct rte_flow_error *error)
6712 struct mlx5_priv *priv = dev->data->dev_private;
6713 const struct rte_flow_item_integrity *mask = (typeof(mask))
6714 integrity_item->mask;
6715 const struct rte_flow_item_integrity *spec = (typeof(spec))
6716 integrity_item->spec;
6718 if (!priv->sh->cdev->config.hca_attr.pkt_integrity_match)
6719 return rte_flow_error_set(error, ENOTSUP,
6720 RTE_FLOW_ERROR_TYPE_ITEM,
6722 "packet integrity integrity_item not supported");
6724 return rte_flow_error_set(error, ENOTSUP,
6725 RTE_FLOW_ERROR_TYPE_ITEM,
6727 "no spec for integrity item");
6729 mask = &rte_flow_item_integrity_mask;
6730 if (!mlx5_validate_integrity_item(mask))
6731 return rte_flow_error_set(error, ENOTSUP,
6732 RTE_FLOW_ERROR_TYPE_ITEM,
6734 "unsupported integrity filter");
6735 if (spec->level > 1) {
6736 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6737 return rte_flow_error_set
6739 RTE_FLOW_ERROR_TYPE_ITEM,
6740 NULL, "multiple inner integrity items not supported");
6741 integrity_items[1] = integrity_item;
6742 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6744 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6745 return rte_flow_error_set
6747 RTE_FLOW_ERROR_TYPE_ITEM,
6748 NULL, "multiple outer integrity items not supported");
6749 integrity_items[0] = integrity_item;
6750 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6756 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6757 const struct rte_flow_item *item,
6758 uint64_t item_flags,
6759 uint64_t *last_item,
6761 struct rte_flow_error *error)
6763 const struct rte_flow_item_flex *flow_spec = item->spec;
6764 const struct rte_flow_item_flex *flow_mask = item->mask;
6765 struct mlx5_flex_item *flex;
6768 return rte_flow_error_set(error, EINVAL,
6769 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6770 "flex flow item spec cannot be NULL");
6772 return rte_flow_error_set(error, EINVAL,
6773 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6774 "flex flow item mask cannot be NULL");
6776 return rte_flow_error_set(error, ENOTSUP,
6777 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6778 "flex flow item last not supported");
6779 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6780 return rte_flow_error_set(error, EINVAL,
6781 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6782 "invalid flex flow item handle");
6783 flex = (struct mlx5_flex_item *)flow_spec->handle;
6784 switch (flex->tunnel_mode) {
6785 case FLEX_TUNNEL_MODE_SINGLE:
6787 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6788 rte_flow_error_set(error, EINVAL,
6789 RTE_FLOW_ERROR_TYPE_ITEM,
6790 NULL, "multiple flex items not supported");
6792 case FLEX_TUNNEL_MODE_OUTER:
6794 rte_flow_error_set(error, EINVAL,
6795 RTE_FLOW_ERROR_TYPE_ITEM,
6796 NULL, "inner flex item was not configured");
6797 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6798 rte_flow_error_set(error, ENOTSUP,
6799 RTE_FLOW_ERROR_TYPE_ITEM,
6800 NULL, "multiple flex items not supported");
6802 case FLEX_TUNNEL_MODE_INNER:
6804 rte_flow_error_set(error, EINVAL,
6805 RTE_FLOW_ERROR_TYPE_ITEM,
6806 NULL, "outer flex item was not configured");
6807 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6808 rte_flow_error_set(error, EINVAL,
6809 RTE_FLOW_ERROR_TYPE_ITEM,
6810 NULL, "multiple flex items not supported");
6812 case FLEX_TUNNEL_MODE_MULTI:
6813 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6814 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6815 rte_flow_error_set(error, EINVAL,
6816 RTE_FLOW_ERROR_TYPE_ITEM,
6817 NULL, "multiple flex items not supported");
6820 case FLEX_TUNNEL_MODE_TUNNEL:
6821 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6822 rte_flow_error_set(error, EINVAL,
6823 RTE_FLOW_ERROR_TYPE_ITEM,
6824 NULL, "multiple flex tunnel items not supported");
6827 rte_flow_error_set(error, EINVAL,
6828 RTE_FLOW_ERROR_TYPE_ITEM,
6829 NULL, "invalid flex item configuration");
6831 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6832 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6833 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6838 * Internal validation function. For validating both actions and items.
6841 * Pointer to the rte_eth_dev structure.
6843 * Pointer to the flow attributes.
6845 * Pointer to the list of items.
6846 * @param[in] actions
6847 * Pointer to the list of actions.
6848 * @param[in] external
6849 * This flow rule is created by request external to PMD.
6850 * @param[in] hairpin
6851 * Number of hairpin TX actions, 0 means classic flow.
6853 * Pointer to the error structure.
6856 * 0 on success, a negative errno value otherwise and rte_errno is set.
6859 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6860 const struct rte_flow_item items[],
6861 const struct rte_flow_action actions[],
6862 bool external, int hairpin, struct rte_flow_error *error)
6865 uint64_t action_flags = 0;
6866 uint64_t item_flags = 0;
6867 uint64_t last_item = 0;
6868 uint8_t next_protocol = 0xff;
6869 uint16_t ether_type = 0;
6871 uint8_t item_ipv6_proto = 0;
6872 int fdb_mirror_limit = 0;
6873 int modify_after_mirror = 0;
6874 const struct rte_flow_item *geneve_item = NULL;
6875 const struct rte_flow_item *gre_item = NULL;
6876 const struct rte_flow_item *gtp_item = NULL;
6877 const struct rte_flow_action_raw_decap *decap;
6878 const struct rte_flow_action_raw_encap *encap;
6879 const struct rte_flow_action_rss *rss = NULL;
6880 const struct rte_flow_action_rss *sample_rss = NULL;
6881 const struct rte_flow_action_count *sample_count = NULL;
6882 const struct rte_flow_item_tcp nic_tcp_mask = {
6885 .src_port = RTE_BE16(UINT16_MAX),
6886 .dst_port = RTE_BE16(UINT16_MAX),
6889 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6892 "\xff\xff\xff\xff\xff\xff\xff\xff"
6893 "\xff\xff\xff\xff\xff\xff\xff\xff",
6895 "\xff\xff\xff\xff\xff\xff\xff\xff"
6896 "\xff\xff\xff\xff\xff\xff\xff\xff",
6897 .vtc_flow = RTE_BE32(0xffffffff),
6903 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6907 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6911 .dummy[0] = 0xffffffff,
6914 struct mlx5_priv *priv = dev->data->dev_private;
6915 struct mlx5_sh_config *dev_conf = &priv->sh->config;
6916 uint16_t queue_index = 0xFFFF;
6917 const struct rte_flow_item_vlan *vlan_m = NULL;
6918 uint32_t rw_act_num = 0;
6920 const struct mlx5_flow_tunnel *tunnel;
6921 enum mlx5_tof_rule_type tof_rule_type;
6922 struct flow_grp_info grp_info = {
6923 .external = !!external,
6924 .transfer = !!attr->transfer,
6925 .fdb_def_rule = !!priv->fdb_def_rule,
6926 .std_tbl_fix = true,
6928 const struct rte_eth_hairpin_conf *conf;
6929 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6930 const struct rte_flow_item *port_id_item = NULL;
6931 bool def_policy = false;
6932 bool shared_count = false;
6933 uint16_t udp_dport = 0;
6937 tunnel = is_tunnel_offload_active(dev) ?
6938 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6940 if (!dev_conf->dv_flow_en)
6941 return rte_flow_error_set
6943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6944 NULL, "tunnel offload requires DV flow interface");
6945 if (priv->representor)
6946 return rte_flow_error_set
6948 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6949 NULL, "decap not supported for VF representor");
6950 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6951 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6952 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6953 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6954 MLX5_FLOW_ACTION_DECAP;
6955 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6956 (dev, attr, tunnel, tof_rule_type);
6958 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6961 is_root = (uint64_t)ret;
6962 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6963 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6964 int type = items->type;
6966 if (!mlx5_flow_os_item_supported(type))
6967 return rte_flow_error_set(error, ENOTSUP,
6968 RTE_FLOW_ERROR_TYPE_ITEM,
6969 NULL, "item not supported");
6971 case RTE_FLOW_ITEM_TYPE_VOID:
6973 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6974 ret = flow_dv_validate_item_port_id
6975 (dev, items, attr, item_flags, error);
6978 last_item = MLX5_FLOW_ITEM_PORT_ID;
6979 port_id_item = items;
6981 case RTE_FLOW_ITEM_TYPE_ETH:
6982 ret = mlx5_flow_validate_item_eth(items, item_flags,
6986 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6987 MLX5_FLOW_LAYER_OUTER_L2;
6988 if (items->mask != NULL && items->spec != NULL) {
6990 ((const struct rte_flow_item_eth *)
6993 ((const struct rte_flow_item_eth *)
6995 ether_type = rte_be_to_cpu_16(ether_type);
7000 case RTE_FLOW_ITEM_TYPE_VLAN:
7001 ret = flow_dv_validate_item_vlan(items, item_flags,
7005 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
7006 MLX5_FLOW_LAYER_OUTER_VLAN;
7007 if (items->mask != NULL && items->spec != NULL) {
7009 ((const struct rte_flow_item_vlan *)
7010 items->spec)->inner_type;
7012 ((const struct rte_flow_item_vlan *)
7013 items->mask)->inner_type;
7014 ether_type = rte_be_to_cpu_16(ether_type);
7018 /* Store outer VLAN mask for of_push_vlan action. */
7020 vlan_m = items->mask;
7022 case RTE_FLOW_ITEM_TYPE_IPV4:
7023 mlx5_flow_tunnel_ip_check(items, next_protocol,
7024 &item_flags, &tunnel);
7025 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7026 last_item, ether_type,
7030 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7031 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7032 if (items->mask != NULL &&
7033 ((const struct rte_flow_item_ipv4 *)
7034 items->mask)->hdr.next_proto_id) {
7036 ((const struct rte_flow_item_ipv4 *)
7037 (items->spec))->hdr.next_proto_id;
7039 ((const struct rte_flow_item_ipv4 *)
7040 (items->mask))->hdr.next_proto_id;
7042 /* Reset for inner layer. */
7043 next_protocol = 0xff;
7046 case RTE_FLOW_ITEM_TYPE_IPV6:
7047 mlx5_flow_tunnel_ip_check(items, next_protocol,
7048 &item_flags, &tunnel);
7049 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7056 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7057 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7058 if (items->mask != NULL &&
7059 ((const struct rte_flow_item_ipv6 *)
7060 items->mask)->hdr.proto) {
7062 ((const struct rte_flow_item_ipv6 *)
7063 items->spec)->hdr.proto;
7065 ((const struct rte_flow_item_ipv6 *)
7066 items->spec)->hdr.proto;
7068 ((const struct rte_flow_item_ipv6 *)
7069 items->mask)->hdr.proto;
7071 /* Reset for inner layer. */
7072 next_protocol = 0xff;
7075 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7076 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7081 last_item = tunnel ?
7082 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7083 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7084 if (items->mask != NULL &&
7085 ((const struct rte_flow_item_ipv6_frag_ext *)
7086 items->mask)->hdr.next_header) {
7088 ((const struct rte_flow_item_ipv6_frag_ext *)
7089 items->spec)->hdr.next_header;
7091 ((const struct rte_flow_item_ipv6_frag_ext *)
7092 items->mask)->hdr.next_header;
7094 /* Reset for inner layer. */
7095 next_protocol = 0xff;
7098 case RTE_FLOW_ITEM_TYPE_TCP:
7099 ret = mlx5_flow_validate_item_tcp
7106 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7107 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7109 case RTE_FLOW_ITEM_TYPE_UDP:
7110 ret = mlx5_flow_validate_item_udp(items, item_flags,
7113 const struct rte_flow_item_udp *spec = items->spec;
7114 const struct rte_flow_item_udp *mask = items->mask;
7116 mask = &rte_flow_item_udp_mask;
7118 udp_dport = rte_be_to_cpu_16
7119 (spec->hdr.dst_port &
7120 mask->hdr.dst_port);
7123 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7124 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7126 case RTE_FLOW_ITEM_TYPE_GRE:
7127 ret = mlx5_flow_validate_item_gre(items, item_flags,
7128 next_protocol, error);
7132 last_item = MLX5_FLOW_LAYER_GRE;
7134 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
7135 ret = mlx5_flow_validate_item_gre_option(dev, items, item_flags,
7136 attr, gre_item, error);
7139 last_item = MLX5_FLOW_LAYER_GRE;
7141 case RTE_FLOW_ITEM_TYPE_NVGRE:
7142 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7147 last_item = MLX5_FLOW_LAYER_NVGRE;
7149 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7150 ret = mlx5_flow_validate_item_gre_key
7151 (items, item_flags, gre_item, error);
7154 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7156 case RTE_FLOW_ITEM_TYPE_VXLAN:
7157 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7162 last_item = MLX5_FLOW_LAYER_VXLAN;
7164 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7165 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7170 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7172 case RTE_FLOW_ITEM_TYPE_GENEVE:
7173 ret = mlx5_flow_validate_item_geneve(items,
7178 geneve_item = items;
7179 last_item = MLX5_FLOW_LAYER_GENEVE;
7181 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7182 ret = mlx5_flow_validate_item_geneve_opt(items,
7189 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7191 case RTE_FLOW_ITEM_TYPE_MPLS:
7192 ret = mlx5_flow_validate_item_mpls(dev, items,
7197 last_item = MLX5_FLOW_LAYER_MPLS;
7200 case RTE_FLOW_ITEM_TYPE_MARK:
7201 ret = flow_dv_validate_item_mark(dev, items, attr,
7205 last_item = MLX5_FLOW_ITEM_MARK;
7207 case RTE_FLOW_ITEM_TYPE_META:
7208 ret = flow_dv_validate_item_meta(dev, items, attr,
7212 last_item = MLX5_FLOW_ITEM_METADATA;
7214 case RTE_FLOW_ITEM_TYPE_ICMP:
7215 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7220 last_item = MLX5_FLOW_LAYER_ICMP;
7222 case RTE_FLOW_ITEM_TYPE_ICMP6:
7223 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7228 item_ipv6_proto = IPPROTO_ICMPV6;
7229 last_item = MLX5_FLOW_LAYER_ICMP6;
7231 case RTE_FLOW_ITEM_TYPE_TAG:
7232 ret = flow_dv_validate_item_tag(dev, items,
7236 last_item = MLX5_FLOW_ITEM_TAG;
7238 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7239 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7241 case RTE_FLOW_ITEM_TYPE_GTP:
7242 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7247 last_item = MLX5_FLOW_LAYER_GTP;
7249 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7250 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7255 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7257 case RTE_FLOW_ITEM_TYPE_ECPRI:
7258 /* Capacity will be checked in the translate stage. */
7259 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7266 last_item = MLX5_FLOW_LAYER_ECPRI;
7268 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7269 ret = flow_dv_validate_item_integrity(dev, items,
7277 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7278 ret = flow_dv_validate_item_aso_ct(dev, items,
7279 &item_flags, error);
7283 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7284 /* tunnel offload item was processed before
7285 * list it here as a supported type
7288 case RTE_FLOW_ITEM_TYPE_FLEX:
7289 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7291 tunnel != 0, error);
7296 return rte_flow_error_set(error, ENOTSUP,
7297 RTE_FLOW_ERROR_TYPE_ITEM,
7298 NULL, "item not supported");
7300 item_flags |= last_item;
7302 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7303 ret = flow_dv_validate_item_integrity_post(integrity_items,
7308 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7309 int type = actions->type;
7311 if (!mlx5_flow_os_action_supported(type))
7312 return rte_flow_error_set(error, ENOTSUP,
7313 RTE_FLOW_ERROR_TYPE_ACTION,
7315 "action not supported");
7316 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7317 return rte_flow_error_set(error, ENOTSUP,
7318 RTE_FLOW_ERROR_TYPE_ACTION,
7319 actions, "too many actions");
7321 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7322 return rte_flow_error_set(error, ENOTSUP,
7323 RTE_FLOW_ERROR_TYPE_ACTION,
7324 NULL, "meter action with policy "
7325 "must be the last action");
7327 case RTE_FLOW_ACTION_TYPE_VOID:
7329 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7330 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7331 ret = flow_dv_validate_action_port_id(dev,
7338 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7341 case RTE_FLOW_ACTION_TYPE_FLAG:
7342 ret = flow_dv_validate_action_flag(dev, action_flags,
7346 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7347 /* Count all modify-header actions as one. */
7348 if (!(action_flags &
7349 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7351 action_flags |= MLX5_FLOW_ACTION_FLAG |
7352 MLX5_FLOW_ACTION_MARK_EXT;
7353 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7354 modify_after_mirror = 1;
7357 action_flags |= MLX5_FLOW_ACTION_FLAG;
7360 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7362 case RTE_FLOW_ACTION_TYPE_MARK:
7363 ret = flow_dv_validate_action_mark(dev, actions,
7368 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7369 /* Count all modify-header actions as one. */
7370 if (!(action_flags &
7371 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7373 action_flags |= MLX5_FLOW_ACTION_MARK |
7374 MLX5_FLOW_ACTION_MARK_EXT;
7375 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7376 modify_after_mirror = 1;
7378 action_flags |= MLX5_FLOW_ACTION_MARK;
7381 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7383 case RTE_FLOW_ACTION_TYPE_SET_META:
7384 ret = flow_dv_validate_action_set_meta(dev, actions,
7389 /* Count all modify-header actions as one action. */
7390 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7392 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7393 modify_after_mirror = 1;
7394 action_flags |= MLX5_FLOW_ACTION_SET_META;
7395 rw_act_num += MLX5_ACT_NUM_SET_META;
7397 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7398 ret = flow_dv_validate_action_set_tag(dev, actions,
7403 /* Count all modify-header actions as one action. */
7404 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7406 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7407 modify_after_mirror = 1;
7408 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7409 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7411 case RTE_FLOW_ACTION_TYPE_DROP:
7412 ret = mlx5_flow_validate_action_drop(action_flags,
7416 action_flags |= MLX5_FLOW_ACTION_DROP;
7419 case RTE_FLOW_ACTION_TYPE_QUEUE:
7420 ret = mlx5_flow_validate_action_queue(actions,
7425 queue_index = ((const struct rte_flow_action_queue *)
7426 (actions->conf))->index;
7427 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7430 case RTE_FLOW_ACTION_TYPE_RSS:
7431 rss = actions->conf;
7432 ret = mlx5_flow_validate_action_rss(actions,
7438 if (rss && sample_rss &&
7439 (sample_rss->level != rss->level ||
7440 sample_rss->types != rss->types))
7441 return rte_flow_error_set(error, ENOTSUP,
7442 RTE_FLOW_ERROR_TYPE_ACTION,
7444 "Can't use the different RSS types "
7445 "or level in the same flow");
7446 if (rss != NULL && rss->queue_num)
7447 queue_index = rss->queue[0];
7448 action_flags |= MLX5_FLOW_ACTION_RSS;
7451 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7453 mlx5_flow_validate_action_default_miss(action_flags,
7457 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7460 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7461 shared_count = true;
7463 case RTE_FLOW_ACTION_TYPE_COUNT:
7464 ret = flow_dv_validate_action_count(dev, shared_count,
7469 action_flags |= MLX5_FLOW_ACTION_COUNT;
7472 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7473 if (flow_dv_validate_action_pop_vlan(dev,
7479 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7480 modify_after_mirror = 1;
7481 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7484 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7485 ret = flow_dv_validate_action_push_vlan(dev,
7492 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7493 modify_after_mirror = 1;
7494 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7497 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7498 ret = flow_dv_validate_action_set_vlan_pcp
7499 (action_flags, actions, error);
7502 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7503 modify_after_mirror = 1;
7504 /* Count PCP with push_vlan command. */
7505 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7507 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7508 ret = flow_dv_validate_action_set_vlan_vid
7509 (item_flags, action_flags,
7513 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7514 modify_after_mirror = 1;
7515 /* Count VID with push_vlan command. */
7516 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7517 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7519 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7520 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7521 ret = flow_dv_validate_action_l2_encap(dev,
7527 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7530 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7531 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7532 ret = flow_dv_validate_action_decap(dev, action_flags,
7533 actions, item_flags,
7537 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7538 modify_after_mirror = 1;
7539 action_flags |= MLX5_FLOW_ACTION_DECAP;
7542 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7543 ret = flow_dv_validate_action_raw_encap_decap
7544 (dev, NULL, actions->conf, attr, &action_flags,
7545 &actions_n, actions, item_flags, error);
7549 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7550 decap = actions->conf;
7551 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7553 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7557 encap = actions->conf;
7559 ret = flow_dv_validate_action_raw_encap_decap
7561 decap ? decap : &empty_decap, encap,
7562 attr, &action_flags, &actions_n,
7563 actions, item_flags, error);
7566 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7567 (action_flags & MLX5_FLOW_ACTION_DECAP))
7568 modify_after_mirror = 1;
7570 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7571 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7572 ret = flow_dv_validate_action_modify_mac(action_flags,
7578 /* Count all modify-header actions as one action. */
7579 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7581 action_flags |= actions->type ==
7582 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7583 MLX5_FLOW_ACTION_SET_MAC_SRC :
7584 MLX5_FLOW_ACTION_SET_MAC_DST;
7585 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7586 modify_after_mirror = 1;
7588 * Even if the source and destination MAC addresses have
7589 * overlap in the header with 4B alignment, the convert
7590 * function will handle them separately and 4 SW actions
7591 * will be created. And 2 actions will be added each
7592 * time no matter how many bytes of address will be set.
7594 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7596 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7597 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7598 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7604 /* Count all modify-header actions as one action. */
7605 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7607 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7608 modify_after_mirror = 1;
7609 action_flags |= actions->type ==
7610 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7611 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7612 MLX5_FLOW_ACTION_SET_IPV4_DST;
7613 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7615 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7616 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7617 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7623 if (item_ipv6_proto == IPPROTO_ICMPV6)
7624 return rte_flow_error_set(error, ENOTSUP,
7625 RTE_FLOW_ERROR_TYPE_ACTION,
7627 "Can't change header "
7628 "with ICMPv6 proto");
7629 /* Count all modify-header actions as one action. */
7630 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7632 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7633 modify_after_mirror = 1;
7634 action_flags |= actions->type ==
7635 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7636 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7637 MLX5_FLOW_ACTION_SET_IPV6_DST;
7638 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7640 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7641 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7642 ret = flow_dv_validate_action_modify_tp(action_flags,
7648 /* Count all modify-header actions as one action. */
7649 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7651 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7652 modify_after_mirror = 1;
7653 action_flags |= actions->type ==
7654 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7655 MLX5_FLOW_ACTION_SET_TP_SRC :
7656 MLX5_FLOW_ACTION_SET_TP_DST;
7657 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7659 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7660 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7661 ret = flow_dv_validate_action_modify_ttl(action_flags,
7667 /* Count all modify-header actions as one action. */
7668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7670 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7671 modify_after_mirror = 1;
7672 action_flags |= actions->type ==
7673 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7674 MLX5_FLOW_ACTION_SET_TTL :
7675 MLX5_FLOW_ACTION_DEC_TTL;
7676 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7678 case RTE_FLOW_ACTION_TYPE_JUMP:
7679 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7685 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7687 return rte_flow_error_set(error, EINVAL,
7688 RTE_FLOW_ERROR_TYPE_ACTION,
7690 "sample and jump action combination is not supported");
7692 action_flags |= MLX5_FLOW_ACTION_JUMP;
7694 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7695 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7696 ret = flow_dv_validate_action_modify_tcp_seq
7703 /* Count all modify-header actions as one action. */
7704 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7706 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7707 modify_after_mirror = 1;
7708 action_flags |= actions->type ==
7709 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7710 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7711 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7712 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7714 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7715 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7716 ret = flow_dv_validate_action_modify_tcp_ack
7723 /* Count all modify-header actions as one action. */
7724 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7726 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7727 modify_after_mirror = 1;
7728 action_flags |= actions->type ==
7729 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7730 MLX5_FLOW_ACTION_INC_TCP_ACK :
7731 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7732 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7734 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7736 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7737 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7738 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7740 case RTE_FLOW_ACTION_TYPE_METER:
7741 ret = mlx5_flow_validate_action_meter(dev,
7750 action_flags |= MLX5_FLOW_ACTION_METER;
7753 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7755 /* Meter action will add one more TAG action. */
7756 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7758 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7759 if (!attr->transfer && !attr->group)
7760 return rte_flow_error_set(error, ENOTSUP,
7761 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7763 "Shared ASO age action is not supported for group 0");
7764 if (action_flags & MLX5_FLOW_ACTION_AGE)
7765 return rte_flow_error_set
7767 RTE_FLOW_ERROR_TYPE_ACTION,
7769 "duplicate age actions set");
7770 action_flags |= MLX5_FLOW_ACTION_AGE;
7773 case RTE_FLOW_ACTION_TYPE_AGE:
7774 ret = flow_dv_validate_action_age(action_flags,
7780 * Validate the regular AGE action (using counter)
7781 * mutual exclusion with indirect counter actions.
7783 if (!flow_hit_aso_supported(priv->sh, attr)) {
7785 return rte_flow_error_set
7787 RTE_FLOW_ERROR_TYPE_ACTION,
7789 "old age and indirect count combination is not supported");
7791 return rte_flow_error_set
7793 RTE_FLOW_ERROR_TYPE_ACTION,
7795 "old age action and count must be in the same sub flow");
7797 action_flags |= MLX5_FLOW_ACTION_AGE;
7800 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7801 ret = flow_dv_validate_action_modify_ipv4_dscp
7808 /* Count all modify-header actions as one action. */
7809 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7811 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7812 modify_after_mirror = 1;
7813 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7814 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7816 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7817 ret = flow_dv_validate_action_modify_ipv6_dscp
7824 /* Count all modify-header actions as one action. */
7825 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7827 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7828 modify_after_mirror = 1;
7829 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7830 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7832 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7833 ret = flow_dv_validate_action_sample(&action_flags,
7842 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7845 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7846 ret = flow_dv_validate_action_modify_field(dev,
7853 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7854 modify_after_mirror = 1;
7855 /* Count all modify-header actions as one action. */
7856 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7858 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7861 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7862 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7867 action_flags |= MLX5_FLOW_ACTION_CT;
7869 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7870 /* tunnel offload action was processed before
7871 * list it here as a supported type
7875 return rte_flow_error_set(error, ENOTSUP,
7876 RTE_FLOW_ERROR_TYPE_ACTION,
7878 "action not supported");
7882 * Validate actions in flow rules
7883 * - Explicit decap action is prohibited by the tunnel offload API.
7884 * - Drop action in tunnel steer rule is prohibited by the API.
7885 * - Application cannot use MARK action because it's value can mask
7886 * tunnel default miss notification.
7887 * - JUMP in tunnel match rule has no support in current PMD
7889 * - TAG & META are reserved for future uses.
7891 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7892 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7893 MLX5_FLOW_ACTION_MARK |
7894 MLX5_FLOW_ACTION_SET_TAG |
7895 MLX5_FLOW_ACTION_SET_META |
7896 MLX5_FLOW_ACTION_DROP;
7898 if (action_flags & bad_actions_mask)
7899 return rte_flow_error_set
7901 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7902 "Invalid RTE action in tunnel "
7904 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7905 return rte_flow_error_set
7907 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7908 "tunnel set decap rule must terminate "
7911 return rte_flow_error_set
7913 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7914 "tunnel flows for ingress traffic only");
7916 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7917 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7918 MLX5_FLOW_ACTION_MARK |
7919 MLX5_FLOW_ACTION_SET_TAG |
7920 MLX5_FLOW_ACTION_SET_META;
7922 if (action_flags & bad_actions_mask)
7923 return rte_flow_error_set
7925 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7926 "Invalid RTE action in tunnel "
7930 * Validate the drop action mutual exclusion with other actions.
7931 * Drop action is mutually-exclusive with any other action, except for
7933 * Drop action compatibility with tunnel offload was already validated.
7935 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7936 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7937 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7938 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7939 return rte_flow_error_set(error, EINVAL,
7940 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7941 "Drop action is mutually-exclusive "
7942 "with any other action, except for "
7944 /* Eswitch has few restrictions on using items and actions */
7945 if (attr->transfer) {
7946 if (!mlx5_flow_ext_mreg_supported(dev) &&
7947 action_flags & MLX5_FLOW_ACTION_FLAG)
7948 return rte_flow_error_set(error, ENOTSUP,
7949 RTE_FLOW_ERROR_TYPE_ACTION,
7951 "unsupported action FLAG");
7952 if (!mlx5_flow_ext_mreg_supported(dev) &&
7953 action_flags & MLX5_FLOW_ACTION_MARK)
7954 return rte_flow_error_set(error, ENOTSUP,
7955 RTE_FLOW_ERROR_TYPE_ACTION,
7957 "unsupported action MARK");
7958 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7959 return rte_flow_error_set(error, ENOTSUP,
7960 RTE_FLOW_ERROR_TYPE_ACTION,
7962 "unsupported action QUEUE");
7963 if (action_flags & MLX5_FLOW_ACTION_RSS)
7964 return rte_flow_error_set(error, ENOTSUP,
7965 RTE_FLOW_ERROR_TYPE_ACTION,
7967 "unsupported action RSS");
7968 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7969 return rte_flow_error_set(error, EINVAL,
7970 RTE_FLOW_ERROR_TYPE_ACTION,
7972 "no fate action is found");
7974 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7975 return rte_flow_error_set(error, EINVAL,
7976 RTE_FLOW_ERROR_TYPE_ACTION,
7978 "no fate action is found");
7981 * Continue validation for Xcap and VLAN actions.
7982 * If hairpin is working in explicit TX rule mode, there is no actions
7983 * splitting and the validation of hairpin ingress flow should be the
7984 * same as other standard flows.
7986 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7987 MLX5_FLOW_VLAN_ACTIONS)) &&
7988 (queue_index == 0xFFFF || !mlx5_rxq_is_hairpin(dev, queue_index) ||
7989 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7990 conf->tx_explicit != 0))) {
7991 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7992 MLX5_FLOW_XCAP_ACTIONS)
7993 return rte_flow_error_set(error, ENOTSUP,
7994 RTE_FLOW_ERROR_TYPE_ACTION,
7995 NULL, "encap and decap "
7996 "combination aren't supported");
7997 if (!attr->transfer && attr->ingress) {
7998 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7999 return rte_flow_error_set
8001 RTE_FLOW_ERROR_TYPE_ACTION,
8002 NULL, "encap is not supported"
8003 " for ingress traffic");
8004 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8005 return rte_flow_error_set
8007 RTE_FLOW_ERROR_TYPE_ACTION,
8008 NULL, "push VLAN action not "
8009 "supported for ingress");
8010 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
8011 MLX5_FLOW_VLAN_ACTIONS)
8012 return rte_flow_error_set
8014 RTE_FLOW_ERROR_TYPE_ACTION,
8015 NULL, "no support for "
8016 "multiple VLAN actions");
8019 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
8020 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
8021 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
8023 return rte_flow_error_set
8025 RTE_FLOW_ERROR_TYPE_ACTION,
8026 NULL, "fate action not supported for "
8027 "meter with policy");
8029 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
8030 return rte_flow_error_set
8032 RTE_FLOW_ERROR_TYPE_ACTION,
8033 NULL, "modify header action in egress "
8034 "cannot be done before meter action");
8035 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8036 return rte_flow_error_set
8038 RTE_FLOW_ERROR_TYPE_ACTION,
8039 NULL, "encap action in egress "
8040 "cannot be done before meter action");
8041 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8042 return rte_flow_error_set
8044 RTE_FLOW_ERROR_TYPE_ACTION,
8045 NULL, "push vlan action in egress "
8046 "cannot be done before meter action");
8050 * Hairpin flow will add one more TAG action in TX implicit mode.
8051 * In TX explicit mode, there will be no hairpin flow ID.
8054 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8055 /* extra metadata enabled: one more TAG action will be add. */
8056 if (dev_conf->dv_flow_en &&
8057 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8058 mlx5_flow_ext_mreg_supported(dev))
8059 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8061 flow_dv_modify_hdr_action_max(dev, is_root)) {
8062 return rte_flow_error_set(error, ENOTSUP,
8063 RTE_FLOW_ERROR_TYPE_ACTION,
8064 NULL, "too many header modify"
8065 " actions to support");
8067 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8068 if (fdb_mirror_limit && modify_after_mirror)
8069 return rte_flow_error_set(error, EINVAL,
8070 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8071 "sample before modify action is not supported");
8076 * Internal preparation function. Allocates the DV flow size,
8077 * this size is constant.
8080 * Pointer to the rte_eth_dev structure.
8082 * Pointer to the flow attributes.
8084 * Pointer to the list of items.
8085 * @param[in] actions
8086 * Pointer to the list of actions.
8088 * Pointer to the error structure.
8091 * Pointer to mlx5_flow object on success,
8092 * otherwise NULL and rte_errno is set.
8094 static struct mlx5_flow *
8095 flow_dv_prepare(struct rte_eth_dev *dev,
8096 const struct rte_flow_attr *attr __rte_unused,
8097 const struct rte_flow_item items[] __rte_unused,
8098 const struct rte_flow_action actions[] __rte_unused,
8099 struct rte_flow_error *error)
8101 uint32_t handle_idx = 0;
8102 struct mlx5_flow *dev_flow;
8103 struct mlx5_flow_handle *dev_handle;
8104 struct mlx5_priv *priv = dev->data->dev_private;
8105 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8108 wks->skip_matcher_reg = 0;
8110 wks->final_policy = NULL;
8111 /* In case of corrupting the memory. */
8112 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8113 rte_flow_error_set(error, ENOSPC,
8114 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8115 "not free temporary device flow");
8118 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8121 rte_flow_error_set(error, ENOMEM,
8122 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8123 "not enough memory to create flow handle");
8126 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8127 dev_flow = &wks->flows[wks->flow_idx++];
8128 memset(dev_flow, 0, sizeof(*dev_flow));
8129 dev_flow->handle = dev_handle;
8130 dev_flow->handle_idx = handle_idx;
8131 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8132 dev_flow->ingress = attr->ingress;
8133 dev_flow->dv.transfer = attr->transfer;
8137 #ifdef RTE_LIBRTE_MLX5_DEBUG
8139 * Sanity check for match mask and value. Similar to check_valid_spec() in
8140 * kernel driver. If unmasked bit is present in value, it returns failure.
8143 * pointer to match mask buffer.
8144 * @param match_value
8145 * pointer to match value buffer.
8148 * 0 if valid, -EINVAL otherwise.
8151 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8153 uint8_t *m = match_mask;
8154 uint8_t *v = match_value;
8157 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8160 "match_value differs from match_criteria"
8161 " %p[%u] != %p[%u]",
8162 match_value, i, match_mask, i);
8171 * Add match of ip_version.
8175 * @param[in] headers_v
8176 * Values header pointer.
8177 * @param[in] headers_m
8178 * Masks header pointer.
8179 * @param[in] ip_version
8180 * The IP version to set.
8183 flow_dv_set_match_ip_version(uint32_t group,
8189 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8191 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8193 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8194 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8195 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8199 * Add Ethernet item to matcher and to the value.
8201 * @param[in, out] matcher
8203 * @param[in, out] key
8204 * Flow matcher value.
8206 * Flow pattern to translate.
8208 * Item is inner pattern.
8211 flow_dv_translate_item_eth(void *matcher, void *key,
8212 const struct rte_flow_item *item, int inner,
8215 const struct rte_flow_item_eth *eth_m = item->mask;
8216 const struct rte_flow_item_eth *eth_v = item->spec;
8217 const struct rte_flow_item_eth nic_mask = {
8218 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8219 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8220 .type = RTE_BE16(0xffff),
8233 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8235 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8237 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8239 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8241 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8242 ð_m->dst, sizeof(eth_m->dst));
8243 /* The value must be in the range of the mask. */
8244 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8245 for (i = 0; i < sizeof(eth_m->dst); ++i)
8246 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8247 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8248 ð_m->src, sizeof(eth_m->src));
8249 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8250 /* The value must be in the range of the mask. */
8251 for (i = 0; i < sizeof(eth_m->dst); ++i)
8252 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8254 * HW supports match on one Ethertype, the Ethertype following the last
8255 * VLAN tag of the packet (see PRM).
8256 * Set match on ethertype only if ETH header is not followed by VLAN.
8257 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8258 * ethertype, and use ip_version field instead.
8259 * eCPRI over Ether layer will use type value 0xAEFE.
8261 if (eth_m->type == 0xFFFF) {
8262 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8263 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8264 switch (eth_v->type) {
8265 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8266 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8268 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8269 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8270 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8272 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8273 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8275 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8276 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8282 if (eth_m->has_vlan) {
8283 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8284 if (eth_v->has_vlan) {
8286 * Here, when also has_more_vlan field in VLAN item is
8287 * not set, only single-tagged packets will be matched.
8289 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8293 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8294 rte_be_to_cpu_16(eth_m->type));
8295 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8296 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8300 * Add VLAN item to matcher and to the value.
8302 * @param[in, out] dev_flow
8304 * @param[in, out] matcher
8306 * @param[in, out] key
8307 * Flow matcher value.
8309 * Flow pattern to translate.
8311 * Item is inner pattern.
8314 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8315 void *matcher, void *key,
8316 const struct rte_flow_item *item,
8317 int inner, uint32_t group)
8319 const struct rte_flow_item_vlan *vlan_m = item->mask;
8320 const struct rte_flow_item_vlan *vlan_v = item->spec;
8327 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8329 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8331 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8333 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8335 * This is workaround, masks are not supported,
8336 * and pre-validated.
8339 dev_flow->handle->vf_vlan.tag =
8340 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8343 * When VLAN item exists in flow, mark packet as tagged,
8344 * even if TCI is not specified.
8346 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8347 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8348 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8353 vlan_m = &rte_flow_item_vlan_mask;
8354 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8355 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8356 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8357 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8358 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8359 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8360 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8361 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8363 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8364 * ethertype, and use ip_version field instead.
8366 if (vlan_m->inner_type == 0xFFFF) {
8367 switch (vlan_v->inner_type) {
8368 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8369 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8370 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8371 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8373 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8374 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8376 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8377 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8383 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8384 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8385 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8386 /* Only one vlan_tag bit can be set. */
8387 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8390 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8391 rte_be_to_cpu_16(vlan_m->inner_type));
8392 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8393 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8397 * Add IPV4 item to matcher and to the value.
8399 * @param[in, out] matcher
8401 * @param[in, out] key
8402 * Flow matcher value.
8404 * Flow pattern to translate.
8406 * Item is inner pattern.
8408 * The group to insert the rule.
8411 flow_dv_translate_item_ipv4(void *matcher, void *key,
8412 const struct rte_flow_item *item,
8413 int inner, uint32_t group)
8415 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8416 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8417 const struct rte_flow_item_ipv4 nic_mask = {
8419 .src_addr = RTE_BE32(0xffffffff),
8420 .dst_addr = RTE_BE32(0xffffffff),
8421 .type_of_service = 0xff,
8422 .next_proto_id = 0xff,
8423 .time_to_live = 0xff,
8430 uint8_t tos, ihl_m, ihl_v;
8433 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8435 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8437 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8439 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8441 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8446 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8447 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8448 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8449 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8450 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8451 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8452 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8453 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8454 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8455 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8456 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8457 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8458 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8459 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8460 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8461 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8462 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8463 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8464 ipv4_m->hdr.type_of_service);
8465 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8466 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8467 ipv4_m->hdr.type_of_service >> 2);
8468 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8469 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8470 ipv4_m->hdr.next_proto_id);
8471 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8472 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8473 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8474 ipv4_m->hdr.time_to_live);
8475 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8476 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8477 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8478 !!(ipv4_m->hdr.fragment_offset));
8479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8480 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8484 * Add IPV6 item to matcher and to the value.
8486 * @param[in, out] matcher
8488 * @param[in, out] key
8489 * Flow matcher value.
8491 * Flow pattern to translate.
8493 * Item is inner pattern.
8495 * The group to insert the rule.
8498 flow_dv_translate_item_ipv6(void *matcher, void *key,
8499 const struct rte_flow_item *item,
8500 int inner, uint32_t group)
8502 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8503 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8504 const struct rte_flow_item_ipv6 nic_mask = {
8507 "\xff\xff\xff\xff\xff\xff\xff\xff"
8508 "\xff\xff\xff\xff\xff\xff\xff\xff",
8510 "\xff\xff\xff\xff\xff\xff\xff\xff"
8511 "\xff\xff\xff\xff\xff\xff\xff\xff",
8512 .vtc_flow = RTE_BE32(0xffffffff),
8519 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8520 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8529 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8531 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8533 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8535 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8537 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8542 size = sizeof(ipv6_m->hdr.dst_addr);
8543 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8544 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8545 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8546 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8547 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8548 for (i = 0; i < size; ++i)
8549 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8550 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8551 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8552 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8553 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8554 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8555 for (i = 0; i < size; ++i)
8556 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8558 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8559 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8560 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8561 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8562 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8566 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8568 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8571 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8573 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8577 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8579 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8580 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8582 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8583 ipv6_m->hdr.hop_limits);
8584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8585 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8586 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8587 !!(ipv6_m->has_frag_ext));
8588 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8589 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8593 * Add IPV6 fragment extension item to matcher and to the value.
8595 * @param[in, out] matcher
8597 * @param[in, out] key
8598 * Flow matcher value.
8600 * Flow pattern to translate.
8602 * Item is inner pattern.
8605 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8606 const struct rte_flow_item *item,
8609 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8610 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8611 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8613 .next_header = 0xff,
8614 .frag_data = RTE_BE16(0xffff),
8621 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8623 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8625 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8627 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8629 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8630 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8632 if (!ipv6_frag_ext_v)
8634 if (!ipv6_frag_ext_m)
8635 ipv6_frag_ext_m = &nic_mask;
8636 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8637 ipv6_frag_ext_m->hdr.next_header);
8638 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8639 ipv6_frag_ext_v->hdr.next_header &
8640 ipv6_frag_ext_m->hdr.next_header);
8644 * Add TCP item to matcher and to the value.
8646 * @param[in, out] matcher
8648 * @param[in, out] key
8649 * Flow matcher value.
8651 * Flow pattern to translate.
8653 * Item is inner pattern.
8656 flow_dv_translate_item_tcp(void *matcher, void *key,
8657 const struct rte_flow_item *item,
8660 const struct rte_flow_item_tcp *tcp_m = item->mask;
8661 const struct rte_flow_item_tcp *tcp_v = item->spec;
8666 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8668 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8670 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8672 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8674 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8675 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8679 tcp_m = &rte_flow_item_tcp_mask;
8680 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8681 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8682 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8683 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8684 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8685 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8687 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8688 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8689 tcp_m->hdr.tcp_flags);
8690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8691 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8695 * Add UDP item to matcher and to the value.
8697 * @param[in, out] matcher
8699 * @param[in, out] key
8700 * Flow matcher value.
8702 * Flow pattern to translate.
8704 * Item is inner pattern.
8707 flow_dv_translate_item_udp(void *matcher, void *key,
8708 const struct rte_flow_item *item,
8711 const struct rte_flow_item_udp *udp_m = item->mask;
8712 const struct rte_flow_item_udp *udp_v = item->spec;
8717 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8719 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8721 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8723 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8726 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8730 udp_m = &rte_flow_item_udp_mask;
8731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8732 rte_be_to_cpu_16(udp_m->hdr.src_port));
8733 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8734 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8735 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8736 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8738 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8742 * Add GRE optional Key item to matcher and to the value.
8744 * @param[in, out] matcher
8746 * @param[in, out] key
8747 * Flow matcher value.
8749 * Flow pattern to translate.
8751 * Item is inner pattern.
8754 flow_dv_translate_item_gre_key(void *matcher, void *key,
8755 const struct rte_flow_item *item)
8757 const rte_be32_t *key_m = item->mask;
8758 const rte_be32_t *key_v = item->spec;
8759 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8760 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8761 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8763 /* GRE K bit must be on and should already be validated */
8764 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8765 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8769 key_m = &gre_key_default_mask;
8770 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8771 rte_be_to_cpu_32(*key_m) >> 8);
8772 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8773 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8774 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8775 rte_be_to_cpu_32(*key_m) & 0xFF);
8776 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8777 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8781 * Add GRE item to matcher and to the value.
8783 * @param[in, out] matcher
8785 * @param[in, out] key
8786 * Flow matcher value.
8788 * Flow pattern to translate.
8789 * @param[in] pattern_flags
8790 * Accumulated pattern flags.
8793 flow_dv_translate_item_gre(void *matcher, void *key,
8794 const struct rte_flow_item *item,
8795 uint64_t pattern_flags)
8797 static const struct rte_flow_item_gre empty_gre = {0,};
8798 const struct rte_flow_item_gre *gre_m = item->mask;
8799 const struct rte_flow_item_gre *gre_v = item->spec;
8800 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8801 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8802 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8803 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8810 uint16_t s_present:1;
8811 uint16_t k_present:1;
8812 uint16_t rsvd_bit1:1;
8813 uint16_t c_present:1;
8817 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8818 uint16_t protocol_m, protocol_v;
8820 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8821 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8827 gre_m = &rte_flow_item_gre_mask;
8829 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8830 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8831 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8832 gre_crks_rsvd0_ver_m.c_present);
8833 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8834 gre_crks_rsvd0_ver_v.c_present &
8835 gre_crks_rsvd0_ver_m.c_present);
8836 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8837 gre_crks_rsvd0_ver_m.k_present);
8838 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8839 gre_crks_rsvd0_ver_v.k_present &
8840 gre_crks_rsvd0_ver_m.k_present);
8841 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8842 gre_crks_rsvd0_ver_m.s_present);
8843 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8844 gre_crks_rsvd0_ver_v.s_present &
8845 gre_crks_rsvd0_ver_m.s_present);
8846 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8847 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8849 /* Force next protocol to prevent matchers duplication */
8850 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8852 protocol_m = 0xFFFF;
8854 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8855 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8856 protocol_m & protocol_v);
8860 * Add GRE optional items to matcher and to the value.
8862 * @param[in, out] matcher
8864 * @param[in, out] key
8865 * Flow matcher value.
8867 * Flow pattern to translate.
8868 * @param[in] gre_item
8869 * Pointer to gre_item.
8870 * @param[in] pattern_flags
8871 * Accumulated pattern flags.
8874 flow_dv_translate_item_gre_option(void *matcher, void *key,
8875 const struct rte_flow_item *item,
8876 const struct rte_flow_item *gre_item,
8877 uint64_t pattern_flags)
8879 const struct rte_flow_item_gre_opt *option_m = item->mask;
8880 const struct rte_flow_item_gre_opt *option_v = item->spec;
8881 const struct rte_flow_item_gre *gre_m = gre_item->mask;
8882 const struct rte_flow_item_gre *gre_v = gre_item->spec;
8883 static const struct rte_flow_item_gre empty_gre = {0};
8884 struct rte_flow_item gre_key_item;
8885 uint16_t c_rsvd0_ver_m, c_rsvd0_ver_v;
8886 uint16_t protocol_m, protocol_v;
8891 * If only match key field, keep using misc for matching.
8892 * If need to match checksum or sequence, using misc5 and do
8893 * not need using misc.
8895 if (!(option_m->sequence.sequence ||
8896 option_m->checksum_rsvd.checksum)) {
8897 flow_dv_translate_item_gre(matcher, key, gre_item,
8899 gre_key_item.spec = &option_v->key.key;
8900 gre_key_item.mask = &option_m->key.key;
8901 flow_dv_translate_item_gre_key(matcher, key, &gre_key_item);
8909 gre_m = &rte_flow_item_gre_mask;
8911 protocol_v = gre_v->protocol;
8912 protocol_m = gre_m->protocol;
8914 /* Force next protocol to prevent matchers duplication */
8915 uint16_t ether_type =
8916 mlx5_translate_tunnel_etypes(pattern_flags);
8918 protocol_v = rte_be_to_cpu_16(ether_type);
8919 protocol_m = UINT16_MAX;
8922 c_rsvd0_ver_v = gre_v->c_rsvd0_ver;
8923 c_rsvd0_ver_m = gre_m->c_rsvd0_ver;
8924 if (option_m->sequence.sequence) {
8925 c_rsvd0_ver_v |= RTE_BE16(0x1000);
8926 c_rsvd0_ver_m |= RTE_BE16(0x1000);
8928 if (option_m->key.key) {
8929 c_rsvd0_ver_v |= RTE_BE16(0x2000);
8930 c_rsvd0_ver_m |= RTE_BE16(0x2000);
8932 if (option_m->checksum_rsvd.checksum) {
8933 c_rsvd0_ver_v |= RTE_BE16(0x8000);
8934 c_rsvd0_ver_m |= RTE_BE16(0x8000);
8937 * Hardware parses GRE optional field into the fixed location,
8938 * do not need to adjust the tunnel dword indices.
8940 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8941 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8942 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_0,
8943 rte_be_to_cpu_32((c_rsvd0_ver_v | protocol_v << 16) &
8944 (c_rsvd0_ver_m | protocol_m << 16)));
8945 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_0,
8946 rte_be_to_cpu_32(c_rsvd0_ver_m | protocol_m << 16));
8947 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1,
8948 rte_be_to_cpu_32(option_v->checksum_rsvd.checksum &
8949 option_m->checksum_rsvd.checksum));
8950 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_1,
8951 rte_be_to_cpu_32(option_m->checksum_rsvd.checksum));
8952 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_2,
8953 rte_be_to_cpu_32(option_v->key.key & option_m->key.key));
8954 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_2,
8955 rte_be_to_cpu_32(option_m->key.key));
8956 MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_3,
8957 rte_be_to_cpu_32(option_v->sequence.sequence &
8958 option_m->sequence.sequence));
8959 MLX5_SET(fte_match_set_misc5, misc5_m, tunnel_header_3,
8960 rte_be_to_cpu_32(option_m->sequence.sequence));
8964 * Add NVGRE item to matcher and to the value.
8966 * @param[in, out] matcher
8968 * @param[in, out] key
8969 * Flow matcher value.
8971 * Flow pattern to translate.
8972 * @param[in] pattern_flags
8973 * Accumulated pattern flags.
8976 flow_dv_translate_item_nvgre(void *matcher, void *key,
8977 const struct rte_flow_item *item,
8978 unsigned long pattern_flags)
8980 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8981 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8982 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8983 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8984 const char *tni_flow_id_m;
8985 const char *tni_flow_id_v;
8991 /* For NVGRE, GRE header fields must be set with defined values. */
8992 const struct rte_flow_item_gre gre_spec = {
8993 .c_rsvd0_ver = RTE_BE16(0x2000),
8994 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8996 const struct rte_flow_item_gre gre_mask = {
8997 .c_rsvd0_ver = RTE_BE16(0xB000),
8998 .protocol = RTE_BE16(UINT16_MAX),
9000 const struct rte_flow_item gre_item = {
9005 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
9009 nvgre_m = &rte_flow_item_nvgre_mask;
9010 tni_flow_id_m = (const char *)nvgre_m->tni;
9011 tni_flow_id_v = (const char *)nvgre_v->tni;
9012 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
9013 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
9014 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
9015 memcpy(gre_key_m, tni_flow_id_m, size);
9016 for (i = 0; i < size; ++i)
9017 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
9021 * Add VXLAN item to matcher and to the value.
9024 * Pointer to the Ethernet device structure.
9026 * Flow rule attributes.
9027 * @param[in, out] matcher
9029 * @param[in, out] key
9030 * Flow matcher value.
9032 * Flow pattern to translate.
9034 * Item is inner pattern.
9037 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
9038 const struct rte_flow_attr *attr,
9039 void *matcher, void *key,
9040 const struct rte_flow_item *item,
9043 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
9044 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
9049 uint32_t *tunnel_header_v;
9050 uint32_t *tunnel_header_m;
9052 struct mlx5_priv *priv = dev->data->dev_private;
9053 const struct rte_flow_item_vxlan nic_mask = {
9054 .vni = "\xff\xff\xff",
9059 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9061 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9063 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9065 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9067 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
9068 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
9069 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9070 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9071 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9073 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
9077 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
9078 (attr->group && !priv->sh->misc5_cap))
9079 vxlan_m = &rte_flow_item_vxlan_mask;
9081 vxlan_m = &nic_mask;
9083 if ((priv->sh->steering_format_version ==
9084 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
9085 dport != MLX5_UDP_PORT_VXLAN) ||
9086 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
9087 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
9094 misc_m = MLX5_ADDR_OF(fte_match_param,
9095 matcher, misc_parameters);
9096 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9097 size = sizeof(vxlan_m->vni);
9098 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
9099 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
9100 memcpy(vni_m, vxlan_m->vni, size);
9101 for (i = 0; i < size; ++i)
9102 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9105 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
9106 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
9107 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9110 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
9113 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
9114 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
9115 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
9116 if (*tunnel_header_v)
9117 *tunnel_header_m = vxlan_m->vni[0] |
9118 vxlan_m->vni[1] << 8 |
9119 vxlan_m->vni[2] << 16;
9121 *tunnel_header_m = 0x0;
9122 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
9123 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
9124 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
9128 * Add VXLAN-GPE item to matcher and to the value.
9130 * @param[in, out] matcher
9132 * @param[in, out] key
9133 * Flow matcher value.
9135 * Flow pattern to translate.
9137 * Item is inner pattern.
9141 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9142 const struct rte_flow_item *item,
9143 const uint64_t pattern_flags)
9145 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9146 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9147 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9148 /* The item was validated to be on the outer side */
9149 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9150 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9152 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9154 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9156 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9158 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9159 int i, size = sizeof(vxlan_m->vni);
9160 uint8_t flags_m = 0xff;
9161 uint8_t flags_v = 0xc;
9162 uint8_t m_protocol, v_protocol;
9164 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9165 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9166 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9167 MLX5_UDP_PORT_VXLAN_GPE);
9170 vxlan_v = &dummy_vxlan_gpe_hdr;
9171 vxlan_m = &dummy_vxlan_gpe_hdr;
9174 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9176 memcpy(vni_m, vxlan_m->vni, size);
9177 for (i = 0; i < size; ++i)
9178 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9179 if (vxlan_m->flags) {
9180 flags_m = vxlan_m->flags;
9181 flags_v = vxlan_v->flags;
9183 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9184 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9185 m_protocol = vxlan_m->protocol;
9186 v_protocol = vxlan_v->protocol;
9188 /* Force next protocol to ensure next headers parsing. */
9189 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9190 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9191 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9192 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9193 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9194 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9198 MLX5_SET(fte_match_set_misc3, misc_m,
9199 outer_vxlan_gpe_next_protocol, m_protocol);
9200 MLX5_SET(fte_match_set_misc3, misc_v,
9201 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9205 * Add Geneve item to matcher and to the value.
9207 * @param[in, out] matcher
9209 * @param[in, out] key
9210 * Flow matcher value.
9212 * Flow pattern to translate.
9214 * Item is inner pattern.
9218 flow_dv_translate_item_geneve(void *matcher, void *key,
9219 const struct rte_flow_item *item,
9220 uint64_t pattern_flags)
9222 static const struct rte_flow_item_geneve empty_geneve = {0,};
9223 const struct rte_flow_item_geneve *geneve_m = item->mask;
9224 const struct rte_flow_item_geneve *geneve_v = item->spec;
9225 /* GENEVE flow item validation allows single tunnel item */
9226 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9227 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9228 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9229 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9232 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9233 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9234 size_t size = sizeof(geneve_m->vni), i;
9235 uint16_t protocol_m, protocol_v;
9237 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9238 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9239 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9240 MLX5_UDP_PORT_GENEVE);
9243 geneve_v = &empty_geneve;
9244 geneve_m = &empty_geneve;
9247 geneve_m = &rte_flow_item_geneve_mask;
9249 memcpy(vni_m, geneve_m->vni, size);
9250 for (i = 0; i < size; ++i)
9251 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9252 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9253 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9254 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9255 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9256 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9257 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9258 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9259 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9260 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9261 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9262 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9263 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9264 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9266 /* Force next protocol to prevent matchers duplication */
9267 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9269 protocol_m = 0xFFFF;
9271 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9272 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9273 protocol_m & protocol_v);
9277 * Create Geneve TLV option resource.
9279 * @param dev[in, out]
9280 * Pointer to rte_eth_dev structure.
9281 * @param[in, out] tag_be24
9282 * Tag value in big endian then R-shift 8.
9283 * @parm[in, out] dev_flow
9284 * Pointer to the dev_flow.
9286 * pointer to error structure.
9289 * 0 on success otherwise -errno and errno is set.
9293 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9294 const struct rte_flow_item *item,
9295 struct rte_flow_error *error)
9297 struct mlx5_priv *priv = dev->data->dev_private;
9298 struct mlx5_dev_ctx_shared *sh = priv->sh;
9299 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9300 sh->geneve_tlv_option_resource;
9301 struct mlx5_devx_obj *obj;
9302 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9307 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9308 if (geneve_opt_resource != NULL) {
9309 if (geneve_opt_resource->option_class ==
9310 geneve_opt_v->option_class &&
9311 geneve_opt_resource->option_type ==
9312 geneve_opt_v->option_type &&
9313 geneve_opt_resource->length ==
9314 geneve_opt_v->option_len) {
9315 /* We already have GENEVE TLV option obj allocated. */
9316 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9319 ret = rte_flow_error_set(error, ENOMEM,
9320 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9321 "Only one GENEVE TLV option supported");
9325 /* Create a GENEVE TLV object and resource. */
9326 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9327 geneve_opt_v->option_class,
9328 geneve_opt_v->option_type,
9329 geneve_opt_v->option_len);
9331 ret = rte_flow_error_set(error, ENODATA,
9332 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9333 "Failed to create GENEVE TLV Devx object");
9336 sh->geneve_tlv_option_resource =
9337 mlx5_malloc(MLX5_MEM_ZERO,
9338 sizeof(*geneve_opt_resource),
9340 if (!sh->geneve_tlv_option_resource) {
9341 claim_zero(mlx5_devx_cmd_destroy(obj));
9342 ret = rte_flow_error_set(error, ENOMEM,
9343 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9344 "GENEVE TLV object memory allocation failed");
9347 geneve_opt_resource = sh->geneve_tlv_option_resource;
9348 geneve_opt_resource->obj = obj;
9349 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9350 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9351 geneve_opt_resource->length = geneve_opt_v->option_len;
9352 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9356 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9361 * Add Geneve TLV option item to matcher.
9363 * @param[in, out] dev
9364 * Pointer to rte_eth_dev structure.
9365 * @param[in, out] matcher
9367 * @param[in, out] key
9368 * Flow matcher value.
9370 * Flow pattern to translate.
9372 * Pointer to error structure.
9375 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9376 void *key, const struct rte_flow_item *item,
9377 struct rte_flow_error *error)
9379 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9380 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9381 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9382 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9383 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9385 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9386 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9392 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9393 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9396 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9400 * Set the option length in GENEVE header if not requested.
9401 * The GENEVE TLV option length is expressed by the option length field
9402 * in the GENEVE header.
9403 * If the option length was not requested but the GENEVE TLV option item
9404 * is present we set the option length field implicitly.
9406 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9407 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9408 MLX5_GENEVE_OPTLEN_MASK);
9409 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9410 geneve_opt_v->option_len + 1);
9412 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9413 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9415 if (geneve_opt_v->data) {
9416 memcpy(&opt_data_key, geneve_opt_v->data,
9417 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9418 sizeof(opt_data_key)));
9419 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9420 sizeof(opt_data_key));
9421 memcpy(&opt_data_mask, geneve_opt_m->data,
9422 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9423 sizeof(opt_data_mask)));
9424 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9425 sizeof(opt_data_mask));
9426 MLX5_SET(fte_match_set_misc3, misc3_m,
9427 geneve_tlv_option_0_data,
9428 rte_be_to_cpu_32(opt_data_mask));
9429 MLX5_SET(fte_match_set_misc3, misc3_v,
9430 geneve_tlv_option_0_data,
9431 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9437 * Add MPLS item to matcher and to the value.
9439 * @param[in, out] matcher
9441 * @param[in, out] key
9442 * Flow matcher value.
9444 * Flow pattern to translate.
9445 * @param[in] prev_layer
9446 * The protocol layer indicated in previous item.
9448 * Item is inner pattern.
9451 flow_dv_translate_item_mpls(void *matcher, void *key,
9452 const struct rte_flow_item *item,
9453 uint64_t prev_layer,
9456 const uint32_t *in_mpls_m = item->mask;
9457 const uint32_t *in_mpls_v = item->spec;
9458 uint32_t *out_mpls_m = 0;
9459 uint32_t *out_mpls_v = 0;
9460 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9461 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9462 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9464 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9465 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9466 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9468 switch (prev_layer) {
9469 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9470 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9471 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9473 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9474 MLX5_UDP_PORT_MPLS);
9477 case MLX5_FLOW_LAYER_GRE:
9479 case MLX5_FLOW_LAYER_GRE_KEY:
9480 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9481 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9483 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9484 RTE_ETHER_TYPE_MPLS);
9493 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9494 switch (prev_layer) {
9495 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9497 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9498 outer_first_mpls_over_udp);
9500 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9501 outer_first_mpls_over_udp);
9503 case MLX5_FLOW_LAYER_GRE:
9505 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9506 outer_first_mpls_over_gre);
9508 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9509 outer_first_mpls_over_gre);
9512 /* Inner MPLS not over GRE is not supported. */
9515 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9519 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9525 if (out_mpls_m && out_mpls_v) {
9526 *out_mpls_m = *in_mpls_m;
9527 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9532 * Add metadata register item to matcher
9534 * @param[in, out] matcher
9536 * @param[in, out] key
9537 * Flow matcher value.
9538 * @param[in] reg_type
9539 * Type of device metadata register
9546 flow_dv_match_meta_reg(void *matcher, void *key,
9547 enum modify_reg reg_type,
9548 uint32_t data, uint32_t mask)
9551 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9553 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9559 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9560 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9563 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9564 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9568 * The metadata register C0 field might be divided into
9569 * source vport index and META item value, we should set
9570 * this field according to specified mask, not as whole one.
9572 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9574 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9575 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9578 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9581 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9582 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9585 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9586 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9589 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9590 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9593 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9594 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9597 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9598 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9601 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9602 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9605 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9606 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9615 * Add MARK item to matcher
9618 * The device to configure through.
9619 * @param[in, out] matcher
9621 * @param[in, out] key
9622 * Flow matcher value.
9624 * Flow pattern to translate.
9627 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9628 void *matcher, void *key,
9629 const struct rte_flow_item *item)
9631 struct mlx5_priv *priv = dev->data->dev_private;
9632 const struct rte_flow_item_mark *mark;
9636 mark = item->mask ? (const void *)item->mask :
9637 &rte_flow_item_mark_mask;
9638 mask = mark->id & priv->sh->dv_mark_mask;
9639 mark = (const void *)item->spec;
9641 value = mark->id & priv->sh->dv_mark_mask & mask;
9643 enum modify_reg reg;
9645 /* Get the metadata register index for the mark. */
9646 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9647 MLX5_ASSERT(reg > 0);
9648 if (reg == REG_C_0) {
9649 struct mlx5_priv *priv = dev->data->dev_private;
9650 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9651 uint32_t shl_c0 = rte_bsf32(msk_c0);
9657 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9662 * Add META item to matcher
9665 * The devich to configure through.
9666 * @param[in, out] matcher
9668 * @param[in, out] key
9669 * Flow matcher value.
9671 * Attributes of flow that includes this item.
9673 * Flow pattern to translate.
9676 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9677 void *matcher, void *key,
9678 const struct rte_flow_attr *attr,
9679 const struct rte_flow_item *item)
9681 const struct rte_flow_item_meta *meta_m;
9682 const struct rte_flow_item_meta *meta_v;
9684 meta_m = (const void *)item->mask;
9686 meta_m = &rte_flow_item_meta_mask;
9687 meta_v = (const void *)item->spec;
9690 uint32_t value = meta_v->data;
9691 uint32_t mask = meta_m->data;
9693 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9696 MLX5_ASSERT(reg != REG_NON);
9697 if (reg == REG_C_0) {
9698 struct mlx5_priv *priv = dev->data->dev_private;
9699 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9700 uint32_t shl_c0 = rte_bsf32(msk_c0);
9706 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9711 * Add vport metadata Reg C0 item to matcher
9713 * @param[in, out] matcher
9715 * @param[in, out] key
9716 * Flow matcher value.
9718 * Flow pattern to translate.
9721 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9722 uint32_t value, uint32_t mask)
9724 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9728 * Add tag item to matcher
9731 * The devich to configure through.
9732 * @param[in, out] matcher
9734 * @param[in, out] key
9735 * Flow matcher value.
9737 * Flow pattern to translate.
9740 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9741 void *matcher, void *key,
9742 const struct rte_flow_item *item)
9744 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9745 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9746 uint32_t mask, value;
9749 value = tag_v->data;
9750 mask = tag_m ? tag_m->data : UINT32_MAX;
9751 if (tag_v->id == REG_C_0) {
9752 struct mlx5_priv *priv = dev->data->dev_private;
9753 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9754 uint32_t shl_c0 = rte_bsf32(msk_c0);
9760 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9764 * Add TAG item to matcher
9767 * The devich to configure through.
9768 * @param[in, out] matcher
9770 * @param[in, out] key
9771 * Flow matcher value.
9773 * Flow pattern to translate.
9776 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9777 void *matcher, void *key,
9778 const struct rte_flow_item *item)
9780 const struct rte_flow_item_tag *tag_v = item->spec;
9781 const struct rte_flow_item_tag *tag_m = item->mask;
9782 enum modify_reg reg;
9785 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9786 /* Get the metadata register index for the tag. */
9787 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9788 MLX5_ASSERT(reg > 0);
9789 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9793 * Add source vport match to the specified matcher.
9795 * @param[in, out] matcher
9797 * @param[in, out] key
9798 * Flow matcher value.
9800 * Source vport value to match
9805 flow_dv_translate_item_source_vport(void *matcher, void *key,
9806 int16_t port, uint16_t mask)
9808 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9809 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9811 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9812 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9816 * Translate port-id item to eswitch match on port-id.
9819 * The devich to configure through.
9820 * @param[in, out] matcher
9822 * @param[in, out] key
9823 * Flow matcher value.
9825 * Flow pattern to translate.
9830 * 0 on success, a negative errno value otherwise.
9833 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9834 void *key, const struct rte_flow_item *item,
9835 const struct rte_flow_attr *attr)
9837 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9838 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9839 struct mlx5_priv *priv;
9842 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9843 flow_dv_translate_item_source_vport(matcher, key,
9844 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9847 mask = pid_m ? pid_m->id : 0xffff;
9848 id = pid_v ? pid_v->id : dev->data->port_id;
9849 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9853 * Translate to vport field or to metadata, depending on mode.
9854 * Kernel can use either misc.source_port or half of C0 metadata
9857 if (priv->vport_meta_mask) {
9859 * Provide the hint for SW steering library
9860 * to insert the flow into ingress domain and
9861 * save the extra vport match.
9863 if (mask == 0xffff && priv->vport_id == 0xffff &&
9864 priv->pf_bond < 0 && attr->transfer)
9865 flow_dv_translate_item_source_vport
9866 (matcher, key, priv->vport_id, mask);
9868 * We should always set the vport metadata register,
9869 * otherwise the SW steering library can drop
9870 * the rule if wire vport metadata value is not zero,
9871 * it depends on kernel configuration.
9873 flow_dv_translate_item_meta_vport(matcher, key,
9874 priv->vport_meta_tag,
9875 priv->vport_meta_mask);
9877 flow_dv_translate_item_source_vport(matcher, key,
9878 priv->vport_id, mask);
9884 * Add ICMP6 item to matcher and to the value.
9886 * @param[in, out] matcher
9888 * @param[in, out] key
9889 * Flow matcher value.
9891 * Flow pattern to translate.
9893 * Item is inner pattern.
9896 flow_dv_translate_item_icmp6(void *matcher, void *key,
9897 const struct rte_flow_item *item,
9900 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9901 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9904 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9906 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9908 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9910 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9912 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9914 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9916 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9917 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9921 icmp6_m = &rte_flow_item_icmp6_mask;
9922 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9923 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9924 icmp6_v->type & icmp6_m->type);
9925 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9926 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9927 icmp6_v->code & icmp6_m->code);
9931 * Add ICMP item to matcher and to the value.
9933 * @param[in, out] matcher
9935 * @param[in, out] key
9936 * Flow matcher value.
9938 * Flow pattern to translate.
9940 * Item is inner pattern.
9943 flow_dv_translate_item_icmp(void *matcher, void *key,
9944 const struct rte_flow_item *item,
9947 const struct rte_flow_item_icmp *icmp_m = item->mask;
9948 const struct rte_flow_item_icmp *icmp_v = item->spec;
9949 uint32_t icmp_header_data_m = 0;
9950 uint32_t icmp_header_data_v = 0;
9953 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9955 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9957 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9959 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9961 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9963 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9965 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9966 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9970 icmp_m = &rte_flow_item_icmp_mask;
9971 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9972 icmp_m->hdr.icmp_type);
9973 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9974 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9975 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9976 icmp_m->hdr.icmp_code);
9977 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9978 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9979 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9980 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9981 if (icmp_header_data_m) {
9982 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9983 icmp_header_data_v |=
9984 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9985 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9986 icmp_header_data_m);
9987 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9988 icmp_header_data_v & icmp_header_data_m);
9993 * Add GTP item to matcher and to the value.
9995 * @param[in, out] matcher
9997 * @param[in, out] key
9998 * Flow matcher value.
10000 * Flow pattern to translate.
10002 * Item is inner pattern.
10005 flow_dv_translate_item_gtp(void *matcher, void *key,
10006 const struct rte_flow_item *item, int inner)
10008 const struct rte_flow_item_gtp *gtp_m = item->mask;
10009 const struct rte_flow_item_gtp *gtp_v = item->spec;
10012 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10013 misc_parameters_3);
10014 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10015 uint16_t dport = RTE_GTPU_UDP_PORT;
10018 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10020 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
10022 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
10024 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10026 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
10027 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
10028 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
10033 gtp_m = &rte_flow_item_gtp_mask;
10034 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
10035 gtp_m->v_pt_rsv_flags);
10036 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
10037 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
10038 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
10039 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
10040 gtp_v->msg_type & gtp_m->msg_type);
10041 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
10042 rte_be_to_cpu_32(gtp_m->teid));
10043 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
10044 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
10048 * Add GTP PSC item to matcher.
10050 * @param[in, out] matcher
10052 * @param[in, out] key
10053 * Flow matcher value.
10055 * Flow pattern to translate.
10058 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
10059 const struct rte_flow_item *item)
10061 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
10062 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
10063 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
10064 misc_parameters_3);
10065 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
10071 uint8_t next_ext_header_type;
10076 /* Always set E-flag match on one, regardless of GTP item settings. */
10077 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
10078 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10079 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
10080 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
10081 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
10082 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
10083 /*Set next extension header type. */
10086 dw_2.next_ext_header_type = 0xff;
10087 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
10088 rte_cpu_to_be_32(dw_2.w32));
10091 dw_2.next_ext_header_type = 0x85;
10092 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
10093 rte_cpu_to_be_32(dw_2.w32));
10099 uint8_t type_flags;
10105 /*Set extension header PDU type and Qos. */
10107 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
10109 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
10110 dw_0.qfi = gtp_psc_m->hdr.qfi;
10111 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
10112 rte_cpu_to_be_32(dw_0.w32));
10114 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
10115 gtp_psc_m->hdr.type);
10116 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
10117 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
10118 rte_cpu_to_be_32(dw_0.w32));
10124 * Add eCPRI item to matcher and to the value.
10127 * The devich to configure through.
10128 * @param[in, out] matcher
10130 * @param[in, out] key
10131 * Flow matcher value.
10133 * Flow pattern to translate.
10134 * @param[in] last_item
10138 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10139 void *key, const struct rte_flow_item *item,
10140 uint64_t last_item)
10142 struct mlx5_priv *priv = dev->data->dev_private;
10143 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10144 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10145 struct rte_ecpri_common_hdr common;
10146 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10147 misc_parameters_4);
10148 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10154 * In case of eCPRI over Ethernet, if EtherType is not specified,
10155 * match on eCPRI EtherType implicitly.
10157 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10158 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10160 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10161 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10162 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10163 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10164 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10165 *(uint16_t *)l2m = UINT16_MAX;
10166 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10172 ecpri_m = &rte_flow_item_ecpri_mask;
10174 * Maximal four DW samples are supported in a single matching now.
10175 * Two are used now for a eCPRI matching:
10176 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10177 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10180 if (!ecpri_m->hdr.common.u32)
10182 samples = priv->sh->ecpri_parser.ids;
10183 /* Need to take the whole DW as the mask to fill the entry. */
10184 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10185 prog_sample_field_value_0);
10186 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10187 prog_sample_field_value_0);
10188 /* Already big endian (network order) in the header. */
10189 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10190 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10191 /* Sample#0, used for matching type, offset 0. */
10192 MLX5_SET(fte_match_set_misc4, misc4_m,
10193 prog_sample_field_id_0, samples[0]);
10194 /* It makes no sense to set the sample ID in the mask field. */
10195 MLX5_SET(fte_match_set_misc4, misc4_v,
10196 prog_sample_field_id_0, samples[0]);
10198 * Checking if message body part needs to be matched.
10199 * Some wildcard rules only matching type field should be supported.
10201 if (ecpri_m->hdr.dummy[0]) {
10202 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10203 switch (common.type) {
10204 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10205 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10206 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10207 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10208 prog_sample_field_value_1);
10209 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10210 prog_sample_field_value_1);
10211 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10212 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10213 ecpri_m->hdr.dummy[0];
10214 /* Sample#1, to match message body, offset 4. */
10215 MLX5_SET(fte_match_set_misc4, misc4_m,
10216 prog_sample_field_id_1, samples[1]);
10217 MLX5_SET(fte_match_set_misc4, misc4_v,
10218 prog_sample_field_id_1, samples[1]);
10221 /* Others, do not match any sample ID. */
10228 * Add connection tracking status item to matcher
10231 * The devich to configure through.
10232 * @param[in, out] matcher
10234 * @param[in, out] key
10235 * Flow matcher value.
10237 * Flow pattern to translate.
10240 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10241 void *matcher, void *key,
10242 const struct rte_flow_item *item)
10244 uint32_t reg_value = 0;
10246 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10247 uint32_t reg_mask = 0;
10248 const struct rte_flow_item_conntrack *spec = item->spec;
10249 const struct rte_flow_item_conntrack *mask = item->mask;
10251 struct rte_flow_error error;
10254 mask = &rte_flow_item_conntrack_mask;
10255 if (!spec || !mask->flags)
10257 flags = spec->flags & mask->flags;
10258 /* The conflict should be checked in the validation. */
10259 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10260 reg_value |= MLX5_CT_SYNDROME_VALID;
10261 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10262 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10263 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10264 reg_value |= MLX5_CT_SYNDROME_INVALID;
10265 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10266 reg_value |= MLX5_CT_SYNDROME_TRAP;
10267 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10268 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10269 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10270 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10271 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10273 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10274 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10275 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10276 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10277 /* The REG_C_x value could be saved during startup. */
10278 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10279 if (reg_id == REG_NON)
10281 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10282 reg_value, reg_mask);
10286 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10287 const struct rte_flow_item *item,
10288 struct mlx5_flow *dev_flow, bool is_inner)
10290 const struct rte_flow_item_flex *spec =
10291 (const struct rte_flow_item_flex *)item->spec;
10292 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10294 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10297 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10298 /* Don't count both inner and outer flex items in one rule. */
10299 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10300 MLX5_ASSERT(false);
10301 dev_flow->handle->flex_item |= (uint8_t)RTE_BIT32(index);
10303 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10306 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10308 #define HEADER_IS_ZERO(match_criteria, headers) \
10309 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10310 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10313 * Calculate flow matcher enable bitmap.
10315 * @param match_criteria
10316 * Pointer to flow matcher criteria.
10319 * Bitmap of enabled fields.
10322 flow_dv_matcher_enable(uint32_t *match_criteria)
10324 uint8_t match_criteria_enable;
10326 match_criteria_enable =
10327 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10328 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10329 match_criteria_enable |=
10330 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10331 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10332 match_criteria_enable |=
10333 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10334 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10335 match_criteria_enable |=
10336 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10337 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10338 match_criteria_enable |=
10339 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10340 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10341 match_criteria_enable |=
10342 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10343 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10344 match_criteria_enable |=
10345 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10346 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10347 return match_criteria_enable;
10351 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10354 * Check flow matching criteria first, subtract misc5/4 length if flow
10355 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10356 * misc5/4 are not supported, and matcher creation failure is expected
10357 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10358 * misc5 is right after misc4.
10360 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10361 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10362 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10363 if (!(match_criteria & (1 <<
10364 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10365 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10370 static struct mlx5_list_entry *
10371 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10372 struct mlx5_list_entry *entry, void *cb_ctx)
10374 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10375 struct mlx5_flow_dv_matcher *ref = ctx->data;
10376 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10377 typeof(*tbl), tbl);
10378 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10383 rte_flow_error_set(ctx->error, ENOMEM,
10384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10385 "cannot create matcher");
10388 memcpy(resource, entry, sizeof(*resource));
10389 resource->tbl = &tbl->tbl;
10390 return &resource->entry;
10394 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10395 struct mlx5_list_entry *entry)
10400 struct mlx5_list_entry *
10401 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10403 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10404 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10405 struct rte_eth_dev *dev = ctx->dev;
10406 struct mlx5_flow_tbl_data_entry *tbl_data;
10407 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10408 struct rte_flow_error *error = ctx->error;
10409 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10410 struct mlx5_flow_tbl_resource *tbl;
10415 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10417 rte_flow_error_set(error, ENOMEM,
10418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10420 "cannot allocate flow table data entry");
10423 tbl_data->idx = idx;
10424 tbl_data->tunnel = tt_prm->tunnel;
10425 tbl_data->group_id = tt_prm->group_id;
10426 tbl_data->external = !!tt_prm->external;
10427 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10428 tbl_data->is_egress = !!key.is_egress;
10429 tbl_data->is_transfer = !!key.is_fdb;
10430 tbl_data->dummy = !!key.dummy;
10431 tbl_data->level = key.level;
10432 tbl_data->id = key.id;
10433 tbl = &tbl_data->tbl;
10435 return &tbl_data->entry;
10437 domain = sh->fdb_domain;
10438 else if (key.is_egress)
10439 domain = sh->tx_domain;
10441 domain = sh->rx_domain;
10442 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10444 rte_flow_error_set(error, ENOMEM,
10445 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10446 NULL, "cannot create flow table object");
10447 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10450 if (key.level != 0) {
10451 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10452 (tbl->obj, &tbl_data->jump.action);
10454 rte_flow_error_set(error, ENOMEM,
10455 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10457 "cannot create flow jump action");
10458 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10459 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10463 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10464 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10465 key.level, key.id);
10466 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10467 flow_dv_matcher_create_cb,
10468 flow_dv_matcher_match_cb,
10469 flow_dv_matcher_remove_cb,
10470 flow_dv_matcher_clone_cb,
10471 flow_dv_matcher_clone_free_cb);
10472 if (!tbl_data->matchers) {
10473 rte_flow_error_set(error, ENOMEM,
10474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10476 "cannot create tbl matcher list");
10477 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10478 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10479 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10482 return &tbl_data->entry;
10486 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10489 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10490 struct mlx5_flow_tbl_data_entry *tbl_data =
10491 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10492 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10494 return tbl_data->level != key.level ||
10495 tbl_data->id != key.id ||
10496 tbl_data->dummy != key.dummy ||
10497 tbl_data->is_transfer != !!key.is_fdb ||
10498 tbl_data->is_egress != !!key.is_egress;
10501 struct mlx5_list_entry *
10502 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10505 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10506 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10507 struct mlx5_flow_tbl_data_entry *tbl_data;
10508 struct rte_flow_error *error = ctx->error;
10511 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10513 rte_flow_error_set(error, ENOMEM,
10514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10516 "cannot allocate flow table data entry");
10519 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10520 tbl_data->idx = idx;
10521 return &tbl_data->entry;
10525 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10527 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10528 struct mlx5_flow_tbl_data_entry *tbl_data =
10529 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10531 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10535 * Get a flow table.
10537 * @param[in, out] dev
10538 * Pointer to rte_eth_dev structure.
10539 * @param[in] table_level
10540 * Table level to use.
10541 * @param[in] egress
10542 * Direction of the table.
10543 * @param[in] transfer
10544 * E-Switch or NIC flow.
10546 * Dummy entry for dv API.
10547 * @param[in] table_id
10549 * @param[out] error
10550 * pointer to error structure.
10553 * Returns tables resource based on the index, NULL in case of failed.
10555 struct mlx5_flow_tbl_resource *
10556 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10557 uint32_t table_level, uint8_t egress,
10560 const struct mlx5_flow_tunnel *tunnel,
10561 uint32_t group_id, uint8_t dummy,
10563 struct rte_flow_error *error)
10565 struct mlx5_priv *priv = dev->data->dev_private;
10566 union mlx5_flow_tbl_key table_key = {
10568 .level = table_level,
10572 .is_fdb = !!transfer,
10573 .is_egress = !!egress,
10576 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10578 .group_id = group_id,
10579 .external = external,
10581 struct mlx5_flow_cb_ctx ctx = {
10584 .data = &table_key.v64,
10587 struct mlx5_list_entry *entry;
10588 struct mlx5_flow_tbl_data_entry *tbl_data;
10590 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10592 rte_flow_error_set(error, ENOMEM,
10593 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10594 "cannot get table");
10597 DRV_LOG(DEBUG, "table_level %u table_id %u "
10598 "tunnel %u group %u registered.",
10599 table_level, table_id,
10600 tunnel ? tunnel->tunnel_id : 0, group_id);
10601 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10602 return &tbl_data->tbl;
10606 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10608 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10609 struct mlx5_flow_tbl_data_entry *tbl_data =
10610 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10612 MLX5_ASSERT(entry && sh);
10613 if (tbl_data->jump.action)
10614 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10615 if (tbl_data->tbl.obj)
10616 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10617 if (tbl_data->tunnel_offload && tbl_data->external) {
10618 struct mlx5_list_entry *he;
10619 struct mlx5_hlist *tunnel_grp_hash;
10620 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10621 union tunnel_tbl_key tunnel_key = {
10622 .tunnel_id = tbl_data->tunnel ?
10623 tbl_data->tunnel->tunnel_id : 0,
10624 .group = tbl_data->group_id
10626 uint32_t table_level = tbl_data->level;
10627 struct mlx5_flow_cb_ctx ctx = {
10628 .data = (void *)&tunnel_key.val,
10631 tunnel_grp_hash = tbl_data->tunnel ?
10632 tbl_data->tunnel->groups :
10634 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10636 mlx5_hlist_unregister(tunnel_grp_hash, he);
10638 "table_level %u id %u tunnel %u group %u released.",
10642 tbl_data->tunnel->tunnel_id : 0,
10643 tbl_data->group_id);
10645 if (tbl_data->matchers)
10646 mlx5_list_destroy(tbl_data->matchers);
10647 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10651 * Release a flow table.
10654 * Pointer to device shared structure.
10656 * Table resource to be released.
10659 * Returns 0 if table was released, else return 1;
10662 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10663 struct mlx5_flow_tbl_resource *tbl)
10665 struct mlx5_flow_tbl_data_entry *tbl_data =
10666 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10670 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10674 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10675 struct mlx5_list_entry *entry, void *cb_ctx)
10677 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10678 struct mlx5_flow_dv_matcher *ref = ctx->data;
10679 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10682 return cur->crc != ref->crc ||
10683 cur->priority != ref->priority ||
10684 memcmp((const void *)cur->mask.buf,
10685 (const void *)ref->mask.buf, ref->mask.size);
10688 struct mlx5_list_entry *
10689 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10691 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10692 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10693 struct mlx5_flow_dv_matcher *ref = ctx->data;
10694 struct mlx5_flow_dv_matcher *resource;
10695 struct mlx5dv_flow_matcher_attr dv_attr = {
10696 .type = IBV_FLOW_ATTR_NORMAL,
10697 .match_mask = (void *)&ref->mask,
10699 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10700 typeof(*tbl), tbl);
10703 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10706 rte_flow_error_set(ctx->error, ENOMEM,
10707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10708 "cannot create matcher");
10712 dv_attr.match_criteria_enable =
10713 flow_dv_matcher_enable(resource->mask.buf);
10714 __flow_dv_adjust_buf_size(&ref->mask.size,
10715 dv_attr.match_criteria_enable);
10716 dv_attr.priority = ref->priority;
10717 if (tbl->is_egress)
10718 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10719 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10721 &resource->matcher_object);
10723 mlx5_free(resource);
10724 rte_flow_error_set(ctx->error, ENOMEM,
10725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10726 "cannot create matcher");
10729 return &resource->entry;
10733 * Register the flow matcher.
10735 * @param[in, out] dev
10736 * Pointer to rte_eth_dev structure.
10737 * @param[in, out] matcher
10738 * Pointer to flow matcher.
10739 * @param[in, out] key
10740 * Pointer to flow table key.
10741 * @parm[in, out] dev_flow
10742 * Pointer to the dev_flow.
10743 * @param[out] error
10744 * pointer to error structure.
10747 * 0 on success otherwise -errno and errno is set.
10750 flow_dv_matcher_register(struct rte_eth_dev *dev,
10751 struct mlx5_flow_dv_matcher *ref,
10752 union mlx5_flow_tbl_key *key,
10753 struct mlx5_flow *dev_flow,
10754 const struct mlx5_flow_tunnel *tunnel,
10756 struct rte_flow_error *error)
10758 struct mlx5_list_entry *entry;
10759 struct mlx5_flow_dv_matcher *resource;
10760 struct mlx5_flow_tbl_resource *tbl;
10761 struct mlx5_flow_tbl_data_entry *tbl_data;
10762 struct mlx5_flow_cb_ctx ctx = {
10767 * tunnel offload API requires this registration for cases when
10768 * tunnel match rule was inserted before tunnel set rule.
10770 tbl = flow_dv_tbl_resource_get(dev, key->level,
10771 key->is_egress, key->is_fdb,
10772 dev_flow->external, tunnel,
10773 group_id, 0, key->id, error);
10775 return -rte_errno; /* No need to refill the error info */
10776 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10778 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10780 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10781 return rte_flow_error_set(error, ENOMEM,
10782 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10783 "cannot allocate ref memory");
10785 resource = container_of(entry, typeof(*resource), entry);
10786 dev_flow->handle->dvh.matcher = resource;
10790 struct mlx5_list_entry *
10791 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10793 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10794 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10795 struct mlx5_flow_dv_tag_resource *entry;
10799 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10801 rte_flow_error_set(ctx->error, ENOMEM,
10802 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10803 "cannot allocate resource memory");
10807 entry->tag_id = *(uint32_t *)(ctx->data);
10808 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10811 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10812 rte_flow_error_set(ctx->error, ENOMEM,
10813 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10814 NULL, "cannot create action");
10817 return &entry->entry;
10821 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10824 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10825 struct mlx5_flow_dv_tag_resource *tag =
10826 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10828 return *(uint32_t *)(ctx->data) != tag->tag_id;
10831 struct mlx5_list_entry *
10832 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10835 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10836 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10837 struct mlx5_flow_dv_tag_resource *entry;
10840 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10842 rte_flow_error_set(ctx->error, ENOMEM,
10843 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10844 "cannot allocate tag resource memory");
10847 memcpy(entry, oentry, sizeof(*entry));
10849 return &entry->entry;
10853 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10855 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10856 struct mlx5_flow_dv_tag_resource *tag =
10857 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10859 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10863 * Find existing tag resource or create and register a new one.
10865 * @param dev[in, out]
10866 * Pointer to rte_eth_dev structure.
10867 * @param[in, out] tag_be24
10868 * Tag value in big endian then R-shift 8.
10869 * @parm[in, out] dev_flow
10870 * Pointer to the dev_flow.
10871 * @param[out] error
10872 * pointer to error structure.
10875 * 0 on success otherwise -errno and errno is set.
10878 flow_dv_tag_resource_register
10879 (struct rte_eth_dev *dev,
10881 struct mlx5_flow *dev_flow,
10882 struct rte_flow_error *error)
10884 struct mlx5_priv *priv = dev->data->dev_private;
10885 struct mlx5_flow_dv_tag_resource *resource;
10886 struct mlx5_list_entry *entry;
10887 struct mlx5_flow_cb_ctx ctx = {
10891 struct mlx5_hlist *tag_table;
10893 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10895 MLX5_TAGS_HLIST_ARRAY_SIZE,
10896 false, false, priv->sh,
10897 flow_dv_tag_create_cb,
10898 flow_dv_tag_match_cb,
10899 flow_dv_tag_remove_cb,
10900 flow_dv_tag_clone_cb,
10901 flow_dv_tag_clone_free_cb,
10903 if (unlikely(!tag_table))
10905 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10907 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10909 dev_flow->handle->dvh.rix_tag = resource->idx;
10910 dev_flow->dv.tag_resource = resource;
10917 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10919 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10920 struct mlx5_flow_dv_tag_resource *tag =
10921 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10923 MLX5_ASSERT(tag && sh && tag->action);
10924 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10925 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10926 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10933 * Pointer to Ethernet device.
10938 * 1 while a reference on it exists, 0 when freed.
10941 flow_dv_tag_release(struct rte_eth_dev *dev,
10944 struct mlx5_priv *priv = dev->data->dev_private;
10945 struct mlx5_flow_dv_tag_resource *tag;
10947 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10950 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10951 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10952 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10956 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10959 * Pointer to rte_eth_dev structure.
10960 * @param[in] action
10961 * Pointer to action PORT_ID / REPRESENTED_PORT.
10962 * @param[out] dst_port_id
10963 * The target port ID.
10964 * @param[out] error
10965 * Pointer to the error structure.
10968 * 0 on success, a negative errno value otherwise and rte_errno is set.
10971 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10972 const struct rte_flow_action *action,
10973 uint32_t *dst_port_id,
10974 struct rte_flow_error *error)
10977 struct mlx5_priv *priv;
10979 switch (action->type) {
10980 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10981 const struct rte_flow_action_port_id *conf;
10983 conf = (const struct rte_flow_action_port_id *)action->conf;
10984 port = conf->original ? dev->data->port_id : conf->id;
10987 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10988 const struct rte_flow_action_ethdev *ethdev;
10990 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10991 port = ethdev->port_id;
10995 MLX5_ASSERT(false);
10996 return rte_flow_error_set(error, EINVAL,
10997 RTE_FLOW_ERROR_TYPE_ACTION, action,
10998 "unknown E-Switch action");
11001 priv = mlx5_port_to_eswitch_info(port, false);
11003 return rte_flow_error_set(error, -rte_errno,
11004 RTE_FLOW_ERROR_TYPE_ACTION,
11006 "No eswitch info was found for port");
11007 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
11009 * This parameter is transferred to
11010 * mlx5dv_dr_action_create_dest_ib_port().
11012 *dst_port_id = priv->dev_port;
11015 * Legacy mode, no LAG configurations is supported.
11016 * This parameter is transferred to
11017 * mlx5dv_dr_action_create_dest_vport().
11019 *dst_port_id = priv->vport_id;
11025 * Create a counter with aging configuration.
11028 * Pointer to rte_eth_dev structure.
11029 * @param[in] dev_flow
11030 * Pointer to the mlx5_flow.
11031 * @param[out] count
11032 * Pointer to the counter action configuration.
11034 * Pointer to the aging action configuration.
11037 * Index to flow counter on success, 0 otherwise.
11040 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
11041 struct mlx5_flow *dev_flow,
11042 const struct rte_flow_action_count *count
11044 const struct rte_flow_action_age *age)
11047 struct mlx5_age_param *age_param;
11049 counter = flow_dv_counter_alloc(dev, !!age);
11050 if (!counter || age == NULL)
11052 age_param = flow_dv_counter_idx_get_age(dev, counter);
11053 age_param->context = age->context ? age->context :
11054 (void *)(uintptr_t)(dev_flow->flow_idx);
11055 age_param->timeout = age->timeout;
11056 age_param->port_id = dev->data->port_id;
11057 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
11058 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
11063 * Add Tx queue matcher
11066 * Pointer to the dev struct.
11067 * @param[in, out] matcher
11069 * @param[in, out] key
11070 * Flow matcher value.
11072 * Flow pattern to translate.
11074 * Item is inner pattern.
11077 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
11078 void *matcher, void *key,
11079 const struct rte_flow_item *item)
11081 const struct mlx5_rte_flow_item_tx_queue *queue_m;
11082 const struct mlx5_rte_flow_item_tx_queue *queue_v;
11083 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
11084 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
11085 struct mlx5_txq_ctrl *txq;
11086 uint32_t queue, mask;
11088 queue_m = (const void *)item->mask;
11089 queue_v = (const void *)item->spec;
11092 txq = mlx5_txq_get(dev, queue_v->queue);
11095 if (txq->is_hairpin)
11096 queue = txq->obj->sq->id;
11098 queue = txq->obj->sq_obj.sq->id;
11099 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
11100 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
11101 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
11102 mlx5_txq_release(dev, queue_v->queue);
11106 * Set the hash fields according to the @p flow information.
11108 * @param[in] item_flags
11109 * The match pattern item flags.
11110 * @param[in] rss_desc
11111 * Pointer to the mlx5_flow_rss_desc.
11112 * @param[out] hash_fields
11113 * Pointer to the RSS hash fields.
11116 flow_dv_hashfields_set(uint64_t item_flags,
11117 struct mlx5_flow_rss_desc *rss_desc,
11118 uint64_t *hash_fields)
11120 uint64_t items = item_flags;
11121 uint64_t fields = 0;
11123 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
11126 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
11127 if (rss_desc->level >= 2)
11130 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
11131 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||
11133 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
11134 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11135 fields |= IBV_RX_HASH_SRC_IPV4;
11136 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11137 fields |= IBV_RX_HASH_DST_IPV4;
11139 fields |= MLX5_IPV4_IBV_RX_HASH;
11141 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
11142 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||
11144 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11145 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11146 fields |= IBV_RX_HASH_SRC_IPV6;
11147 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11148 fields |= IBV_RX_HASH_DST_IPV6;
11150 fields |= MLX5_IPV6_IBV_RX_HASH;
11155 * There is no match between the RSS types and the
11156 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11159 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11160 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||
11162 if (rss_types & RTE_ETH_RSS_UDP) {
11163 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11164 fields |= IBV_RX_HASH_SRC_PORT_UDP;
11165 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11166 fields |= IBV_RX_HASH_DST_PORT_UDP;
11168 fields |= MLX5_UDP_IBV_RX_HASH;
11170 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11171 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||
11173 if (rss_types & RTE_ETH_RSS_TCP) {
11174 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11175 fields |= IBV_RX_HASH_SRC_PORT_TCP;
11176 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11177 fields |= IBV_RX_HASH_DST_PORT_TCP;
11179 fields |= MLX5_TCP_IBV_RX_HASH;
11183 fields |= IBV_RX_HASH_INNER;
11184 *hash_fields = fields;
11188 * Prepare an Rx Hash queue.
11191 * Pointer to Ethernet device.
11192 * @param[in] dev_flow
11193 * Pointer to the mlx5_flow.
11194 * @param[in] rss_desc
11195 * Pointer to the mlx5_flow_rss_desc.
11196 * @param[out] hrxq_idx
11197 * Hash Rx queue index.
11200 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11202 static struct mlx5_hrxq *
11203 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11204 struct mlx5_flow *dev_flow,
11205 struct mlx5_flow_rss_desc *rss_desc,
11206 uint32_t *hrxq_idx)
11208 struct mlx5_flow_handle *dh = dev_flow->handle;
11209 uint32_t shared_rss = rss_desc->shared_rss;
11210 struct mlx5_hrxq *hrxq;
11212 MLX5_ASSERT(rss_desc->queue_num);
11213 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11214 rss_desc->hash_fields = dev_flow->hash_fields;
11215 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11216 rss_desc->shared_rss = 0;
11217 if (rss_desc->hash_fields == 0)
11218 rss_desc->queue_num = 1;
11219 hrxq = mlx5_hrxq_get(dev, rss_desc);
11220 *hrxq_idx = hrxq ? hrxq->idx : 0;
11221 rss_desc->shared_rss = shared_rss;
11226 * Release sample sub action resource.
11228 * @param[in, out] dev
11229 * Pointer to rte_eth_dev structure.
11230 * @param[in] act_res
11231 * Pointer to sample sub action resource.
11234 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11235 struct mlx5_flow_sub_actions_idx *act_res)
11237 if (act_res->rix_hrxq) {
11238 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11239 act_res->rix_hrxq = 0;
11241 if (act_res->rix_encap_decap) {
11242 flow_dv_encap_decap_resource_release(dev,
11243 act_res->rix_encap_decap);
11244 act_res->rix_encap_decap = 0;
11246 if (act_res->rix_port_id_action) {
11247 flow_dv_port_id_action_resource_release(dev,
11248 act_res->rix_port_id_action);
11249 act_res->rix_port_id_action = 0;
11251 if (act_res->rix_tag) {
11252 flow_dv_tag_release(dev, act_res->rix_tag);
11253 act_res->rix_tag = 0;
11255 if (act_res->rix_jump) {
11256 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11257 act_res->rix_jump = 0;
11262 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11263 struct mlx5_list_entry *entry, void *cb_ctx)
11265 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11266 struct rte_eth_dev *dev = ctx->dev;
11267 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11268 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11272 if (ctx_resource->ratio == resource->ratio &&
11273 ctx_resource->ft_type == resource->ft_type &&
11274 ctx_resource->ft_id == resource->ft_id &&
11275 ctx_resource->set_action == resource->set_action &&
11276 !memcmp((void *)&ctx_resource->sample_act,
11277 (void *)&resource->sample_act,
11278 sizeof(struct mlx5_flow_sub_actions_list))) {
11280 * Existing sample action should release the prepared
11281 * sub-actions reference counter.
11283 flow_dv_sample_sub_actions_release(dev,
11284 &ctx_resource->sample_idx);
11290 struct mlx5_list_entry *
11291 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11293 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11294 struct rte_eth_dev *dev = ctx->dev;
11295 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11296 void **sample_dv_actions = ctx_resource->sub_actions;
11297 struct mlx5_flow_dv_sample_resource *resource;
11298 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11299 struct mlx5_priv *priv = dev->data->dev_private;
11300 struct mlx5_dev_ctx_shared *sh = priv->sh;
11301 struct mlx5_flow_tbl_resource *tbl;
11303 const uint32_t next_ft_step = 1;
11304 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11305 uint8_t is_egress = 0;
11306 uint8_t is_transfer = 0;
11307 struct rte_flow_error *error = ctx->error;
11309 /* Register new sample resource. */
11310 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11312 rte_flow_error_set(error, ENOMEM,
11313 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11315 "cannot allocate resource memory");
11318 *resource = *ctx_resource;
11319 /* Create normal path table level */
11320 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11322 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11324 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11325 is_egress, is_transfer,
11326 true, NULL, 0, 0, 0, error);
11328 rte_flow_error_set(error, ENOMEM,
11329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11331 "fail to create normal path table "
11335 resource->normal_path_tbl = tbl;
11336 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11337 if (!sh->default_miss_action) {
11338 rte_flow_error_set(error, ENOMEM,
11339 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11341 "default miss action was not "
11345 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11346 sh->default_miss_action;
11348 /* Create a DR sample action */
11349 sampler_attr.sample_ratio = resource->ratio;
11350 sampler_attr.default_next_table = tbl->obj;
11351 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11352 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11353 &sample_dv_actions[0];
11354 sampler_attr.action = resource->set_action;
11355 if (mlx5_os_flow_dr_create_flow_action_sampler
11356 (&sampler_attr, &resource->verbs_action)) {
11357 rte_flow_error_set(error, ENOMEM,
11358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11359 NULL, "cannot create sample action");
11362 resource->idx = idx;
11363 resource->dev = dev;
11364 return &resource->entry;
11366 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11367 flow_dv_sample_sub_actions_release(dev,
11368 &resource->sample_idx);
11369 if (resource->normal_path_tbl)
11370 flow_dv_tbl_resource_release(MLX5_SH(dev),
11371 resource->normal_path_tbl);
11372 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11377 struct mlx5_list_entry *
11378 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11379 struct mlx5_list_entry *entry __rte_unused,
11382 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11383 struct rte_eth_dev *dev = ctx->dev;
11384 struct mlx5_flow_dv_sample_resource *resource;
11385 struct mlx5_priv *priv = dev->data->dev_private;
11386 struct mlx5_dev_ctx_shared *sh = priv->sh;
11389 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11391 rte_flow_error_set(ctx->error, ENOMEM,
11392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11394 "cannot allocate resource memory");
11397 memcpy(resource, entry, sizeof(*resource));
11398 resource->idx = idx;
11399 resource->dev = dev;
11400 return &resource->entry;
11404 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11405 struct mlx5_list_entry *entry)
11407 struct mlx5_flow_dv_sample_resource *resource =
11408 container_of(entry, typeof(*resource), entry);
11409 struct rte_eth_dev *dev = resource->dev;
11410 struct mlx5_priv *priv = dev->data->dev_private;
11412 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11416 * Find existing sample resource or create and register a new one.
11418 * @param[in, out] dev
11419 * Pointer to rte_eth_dev structure.
11421 * Pointer to sample resource reference.
11422 * @parm[in, out] dev_flow
11423 * Pointer to the dev_flow.
11424 * @param[out] error
11425 * pointer to error structure.
11428 * 0 on success otherwise -errno and errno is set.
11431 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11432 struct mlx5_flow_dv_sample_resource *ref,
11433 struct mlx5_flow *dev_flow,
11434 struct rte_flow_error *error)
11436 struct mlx5_flow_dv_sample_resource *resource;
11437 struct mlx5_list_entry *entry;
11438 struct mlx5_priv *priv = dev->data->dev_private;
11439 struct mlx5_flow_cb_ctx ctx = {
11445 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11448 resource = container_of(entry, typeof(*resource), entry);
11449 dev_flow->handle->dvh.rix_sample = resource->idx;
11450 dev_flow->dv.sample_res = resource;
11455 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11456 struct mlx5_list_entry *entry, void *cb_ctx)
11458 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11459 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11460 struct rte_eth_dev *dev = ctx->dev;
11461 struct mlx5_flow_dv_dest_array_resource *resource =
11462 container_of(entry, typeof(*resource), entry);
11465 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11466 ctx_resource->ft_type == resource->ft_type &&
11467 !memcmp((void *)resource->sample_act,
11468 (void *)ctx_resource->sample_act,
11469 (ctx_resource->num_of_dest *
11470 sizeof(struct mlx5_flow_sub_actions_list)))) {
11472 * Existing sample action should release the prepared
11473 * sub-actions reference counter.
11475 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11476 flow_dv_sample_sub_actions_release(dev,
11477 &ctx_resource->sample_idx[idx]);
11483 struct mlx5_list_entry *
11484 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11486 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11487 struct rte_eth_dev *dev = ctx->dev;
11488 struct mlx5_flow_dv_dest_array_resource *resource;
11489 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11490 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11491 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11492 struct mlx5_priv *priv = dev->data->dev_private;
11493 struct mlx5_dev_ctx_shared *sh = priv->sh;
11494 struct mlx5_flow_sub_actions_list *sample_act;
11495 struct mlx5dv_dr_domain *domain;
11496 uint32_t idx = 0, res_idx = 0;
11497 struct rte_flow_error *error = ctx->error;
11498 uint64_t action_flags;
11501 /* Register new destination array resource. */
11502 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11505 rte_flow_error_set(error, ENOMEM,
11506 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11508 "cannot allocate resource memory");
11511 *resource = *ctx_resource;
11512 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11513 domain = sh->fdb_domain;
11514 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11515 domain = sh->rx_domain;
11517 domain = sh->tx_domain;
11518 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11519 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11520 mlx5_malloc(MLX5_MEM_ZERO,
11521 sizeof(struct mlx5dv_dr_action_dest_attr),
11523 if (!dest_attr[idx]) {
11524 rte_flow_error_set(error, ENOMEM,
11525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11527 "cannot allocate resource memory");
11530 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11531 sample_act = &ctx_resource->sample_act[idx];
11532 action_flags = sample_act->action_flags;
11533 switch (action_flags) {
11534 case MLX5_FLOW_ACTION_QUEUE:
11535 dest_attr[idx]->dest = sample_act->dr_queue_action;
11537 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11538 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11539 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11540 dest_attr[idx]->dest_reformat->reformat =
11541 sample_act->dr_encap_action;
11542 dest_attr[idx]->dest_reformat->dest =
11543 sample_act->dr_port_id_action;
11545 case MLX5_FLOW_ACTION_PORT_ID:
11546 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11548 case MLX5_FLOW_ACTION_JUMP:
11549 dest_attr[idx]->dest = sample_act->dr_jump_action;
11552 rte_flow_error_set(error, EINVAL,
11553 RTE_FLOW_ERROR_TYPE_ACTION,
11555 "unsupported actions type");
11559 /* create a dest array action */
11560 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11562 resource->num_of_dest,
11564 &resource->action);
11566 rte_flow_error_set(error, ENOMEM,
11567 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11569 "cannot create destination array action");
11572 resource->idx = res_idx;
11573 resource->dev = dev;
11574 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11575 mlx5_free(dest_attr[idx]);
11576 return &resource->entry;
11578 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11579 flow_dv_sample_sub_actions_release(dev,
11580 &resource->sample_idx[idx]);
11581 if (dest_attr[idx])
11582 mlx5_free(dest_attr[idx]);
11584 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11588 struct mlx5_list_entry *
11589 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11590 struct mlx5_list_entry *entry __rte_unused,
11593 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11594 struct rte_eth_dev *dev = ctx->dev;
11595 struct mlx5_flow_dv_dest_array_resource *resource;
11596 struct mlx5_priv *priv = dev->data->dev_private;
11597 struct mlx5_dev_ctx_shared *sh = priv->sh;
11598 uint32_t res_idx = 0;
11599 struct rte_flow_error *error = ctx->error;
11601 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11604 rte_flow_error_set(error, ENOMEM,
11605 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11607 "cannot allocate dest-array memory");
11610 memcpy(resource, entry, sizeof(*resource));
11611 resource->idx = res_idx;
11612 resource->dev = dev;
11613 return &resource->entry;
11617 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11618 struct mlx5_list_entry *entry)
11620 struct mlx5_flow_dv_dest_array_resource *resource =
11621 container_of(entry, typeof(*resource), entry);
11622 struct rte_eth_dev *dev = resource->dev;
11623 struct mlx5_priv *priv = dev->data->dev_private;
11625 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11629 * Find existing destination array resource or create and register a new one.
11631 * @param[in, out] dev
11632 * Pointer to rte_eth_dev structure.
11634 * Pointer to destination array resource reference.
11635 * @parm[in, out] dev_flow
11636 * Pointer to the dev_flow.
11637 * @param[out] error
11638 * pointer to error structure.
11641 * 0 on success otherwise -errno and errno is set.
11644 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11645 struct mlx5_flow_dv_dest_array_resource *ref,
11646 struct mlx5_flow *dev_flow,
11647 struct rte_flow_error *error)
11649 struct mlx5_flow_dv_dest_array_resource *resource;
11650 struct mlx5_priv *priv = dev->data->dev_private;
11651 struct mlx5_list_entry *entry;
11652 struct mlx5_flow_cb_ctx ctx = {
11658 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11661 resource = container_of(entry, typeof(*resource), entry);
11662 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11663 dev_flow->dv.dest_array_res = resource;
11668 * Convert Sample action to DV specification.
11671 * Pointer to rte_eth_dev structure.
11672 * @param[in] action
11673 * Pointer to sample action structure.
11674 * @param[in, out] dev_flow
11675 * Pointer to the mlx5_flow.
11677 * Pointer to the flow attributes.
11678 * @param[in, out] num_of_dest
11679 * Pointer to the num of destination.
11680 * @param[in, out] sample_actions
11681 * Pointer to sample actions list.
11682 * @param[in, out] res
11683 * Pointer to sample resource.
11684 * @param[out] error
11685 * Pointer to the error structure.
11688 * 0 on success, a negative errno value otherwise and rte_errno is set.
11691 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11692 const struct rte_flow_action_sample *action,
11693 struct mlx5_flow *dev_flow,
11694 const struct rte_flow_attr *attr,
11695 uint32_t *num_of_dest,
11696 void **sample_actions,
11697 struct mlx5_flow_dv_sample_resource *res,
11698 struct rte_flow_error *error)
11700 struct mlx5_priv *priv = dev->data->dev_private;
11701 const struct rte_flow_action *sub_actions;
11702 struct mlx5_flow_sub_actions_list *sample_act;
11703 struct mlx5_flow_sub_actions_idx *sample_idx;
11704 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11705 struct rte_flow *flow = dev_flow->flow;
11706 struct mlx5_flow_rss_desc *rss_desc;
11707 uint64_t action_flags = 0;
11710 rss_desc = &wks->rss_desc;
11711 sample_act = &res->sample_act;
11712 sample_idx = &res->sample_idx;
11713 res->ratio = action->ratio;
11714 sub_actions = action->actions;
11715 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11716 int type = sub_actions->type;
11717 uint32_t pre_rix = 0;
11720 case RTE_FLOW_ACTION_TYPE_QUEUE:
11722 const struct rte_flow_action_queue *queue;
11723 struct mlx5_hrxq *hrxq;
11726 queue = sub_actions->conf;
11727 rss_desc->queue_num = 1;
11728 rss_desc->queue[0] = queue->index;
11729 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11730 rss_desc, &hrxq_idx);
11732 return rte_flow_error_set
11734 RTE_FLOW_ERROR_TYPE_ACTION,
11736 "cannot create fate queue");
11737 sample_act->dr_queue_action = hrxq->action;
11738 sample_idx->rix_hrxq = hrxq_idx;
11739 sample_actions[sample_act->actions_num++] =
11742 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11743 if (action_flags & MLX5_FLOW_ACTION_MARK)
11744 dev_flow->handle->rix_hrxq = hrxq_idx;
11745 dev_flow->handle->fate_action =
11746 MLX5_FLOW_FATE_QUEUE;
11749 case RTE_FLOW_ACTION_TYPE_RSS:
11751 struct mlx5_hrxq *hrxq;
11753 const struct rte_flow_action_rss *rss;
11754 const uint8_t *rss_key;
11756 rss = sub_actions->conf;
11757 memcpy(rss_desc->queue, rss->queue,
11758 rss->queue_num * sizeof(uint16_t));
11759 rss_desc->queue_num = rss->queue_num;
11760 /* NULL RSS key indicates default RSS key. */
11761 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11762 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11764 * rss->level and rss.types should be set in advance
11765 * when expanding items for RSS.
11767 flow_dv_hashfields_set(dev_flow->handle->layers,
11769 &dev_flow->hash_fields);
11770 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11771 rss_desc, &hrxq_idx);
11773 return rte_flow_error_set
11775 RTE_FLOW_ERROR_TYPE_ACTION,
11777 "cannot create fate queue");
11778 sample_act->dr_queue_action = hrxq->action;
11779 sample_idx->rix_hrxq = hrxq_idx;
11780 sample_actions[sample_act->actions_num++] =
11783 action_flags |= MLX5_FLOW_ACTION_RSS;
11784 if (action_flags & MLX5_FLOW_ACTION_MARK)
11785 dev_flow->handle->rix_hrxq = hrxq_idx;
11786 dev_flow->handle->fate_action =
11787 MLX5_FLOW_FATE_QUEUE;
11790 case RTE_FLOW_ACTION_TYPE_MARK:
11792 uint32_t tag_be = mlx5_flow_mark_set
11793 (((const struct rte_flow_action_mark *)
11794 (sub_actions->conf))->id);
11797 pre_rix = dev_flow->handle->dvh.rix_tag;
11798 /* Save the mark resource before sample */
11799 pre_r = dev_flow->dv.tag_resource;
11800 if (flow_dv_tag_resource_register(dev, tag_be,
11803 MLX5_ASSERT(dev_flow->dv.tag_resource);
11804 sample_act->dr_tag_action =
11805 dev_flow->dv.tag_resource->action;
11806 sample_idx->rix_tag =
11807 dev_flow->handle->dvh.rix_tag;
11808 sample_actions[sample_act->actions_num++] =
11809 sample_act->dr_tag_action;
11810 /* Recover the mark resource after sample */
11811 dev_flow->dv.tag_resource = pre_r;
11812 dev_flow->handle->dvh.rix_tag = pre_rix;
11813 action_flags |= MLX5_FLOW_ACTION_MARK;
11816 case RTE_FLOW_ACTION_TYPE_COUNT:
11818 if (!flow->counter) {
11820 flow_dv_translate_create_counter(dev,
11821 dev_flow, sub_actions->conf,
11823 if (!flow->counter)
11824 return rte_flow_error_set
11826 RTE_FLOW_ERROR_TYPE_ACTION,
11828 "cannot create counter"
11831 sample_act->dr_cnt_action =
11832 (flow_dv_counter_get_by_idx(dev,
11833 flow->counter, NULL))->action;
11834 sample_actions[sample_act->actions_num++] =
11835 sample_act->dr_cnt_action;
11836 action_flags |= MLX5_FLOW_ACTION_COUNT;
11839 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11840 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11842 struct mlx5_flow_dv_port_id_action_resource
11844 uint32_t port_id = 0;
11846 memset(&port_id_resource, 0, sizeof(port_id_resource));
11847 /* Save the port id resource before sample */
11848 pre_rix = dev_flow->handle->rix_port_id_action;
11849 pre_r = dev_flow->dv.port_id_action;
11850 if (flow_dv_translate_action_port_id(dev, sub_actions,
11853 port_id_resource.port_id = port_id;
11854 if (flow_dv_port_id_action_resource_register
11855 (dev, &port_id_resource, dev_flow, error))
11857 sample_act->dr_port_id_action =
11858 dev_flow->dv.port_id_action->action;
11859 sample_idx->rix_port_id_action =
11860 dev_flow->handle->rix_port_id_action;
11861 sample_actions[sample_act->actions_num++] =
11862 sample_act->dr_port_id_action;
11863 /* Recover the port id resource after sample */
11864 dev_flow->dv.port_id_action = pre_r;
11865 dev_flow->handle->rix_port_id_action = pre_rix;
11867 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11870 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11871 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11872 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11873 /* Save the encap resource before sample */
11874 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11875 pre_r = dev_flow->dv.encap_decap;
11876 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11881 sample_act->dr_encap_action =
11882 dev_flow->dv.encap_decap->action;
11883 sample_idx->rix_encap_decap =
11884 dev_flow->handle->dvh.rix_encap_decap;
11885 sample_actions[sample_act->actions_num++] =
11886 sample_act->dr_encap_action;
11887 /* Recover the encap resource after sample */
11888 dev_flow->dv.encap_decap = pre_r;
11889 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11890 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11893 return rte_flow_error_set(error, EINVAL,
11894 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11896 "Not support for sampler action");
11899 sample_act->action_flags = action_flags;
11900 res->ft_id = dev_flow->dv.group;
11901 if (attr->transfer) {
11903 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11904 uint64_t set_action;
11905 } action_ctx = { .set_action = 0 };
11907 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11908 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11909 MLX5_MODIFICATION_TYPE_SET);
11910 MLX5_SET(set_action_in, action_ctx.action_in, field,
11911 MLX5_MODI_META_REG_C_0);
11912 MLX5_SET(set_action_in, action_ctx.action_in, data,
11913 priv->vport_meta_tag);
11914 res->set_action = action_ctx.set_action;
11915 } else if (attr->ingress) {
11916 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11918 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11924 * Convert Sample action to DV specification.
11927 * Pointer to rte_eth_dev structure.
11928 * @param[in, out] dev_flow
11929 * Pointer to the mlx5_flow.
11930 * @param[in] num_of_dest
11931 * The num of destination.
11932 * @param[in, out] res
11933 * Pointer to sample resource.
11934 * @param[in, out] mdest_res
11935 * Pointer to destination array resource.
11936 * @param[in] sample_actions
11937 * Pointer to sample path actions list.
11938 * @param[in] action_flags
11939 * Holds the actions detected until now.
11940 * @param[out] error
11941 * Pointer to the error structure.
11944 * 0 on success, a negative errno value otherwise and rte_errno is set.
11947 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11948 struct mlx5_flow *dev_flow,
11949 uint32_t num_of_dest,
11950 struct mlx5_flow_dv_sample_resource *res,
11951 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11952 void **sample_actions,
11953 uint64_t action_flags,
11954 struct rte_flow_error *error)
11956 /* update normal path action resource into last index of array */
11957 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11958 struct mlx5_flow_sub_actions_list *sample_act =
11959 &mdest_res->sample_act[dest_index];
11960 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11961 struct mlx5_flow_rss_desc *rss_desc;
11962 uint32_t normal_idx = 0;
11963 struct mlx5_hrxq *hrxq;
11967 rss_desc = &wks->rss_desc;
11968 if (num_of_dest > 1) {
11969 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11970 /* Handle QP action for mirroring */
11971 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11972 rss_desc, &hrxq_idx);
11974 return rte_flow_error_set
11976 RTE_FLOW_ERROR_TYPE_ACTION,
11978 "cannot create rx queue");
11980 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11981 sample_act->dr_queue_action = hrxq->action;
11982 if (action_flags & MLX5_FLOW_ACTION_MARK)
11983 dev_flow->handle->rix_hrxq = hrxq_idx;
11984 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11986 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11988 mdest_res->sample_idx[dest_index].rix_encap_decap =
11989 dev_flow->handle->dvh.rix_encap_decap;
11990 sample_act->dr_encap_action =
11991 dev_flow->dv.encap_decap->action;
11992 dev_flow->handle->dvh.rix_encap_decap = 0;
11994 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11996 mdest_res->sample_idx[dest_index].rix_port_id_action =
11997 dev_flow->handle->rix_port_id_action;
11998 sample_act->dr_port_id_action =
11999 dev_flow->dv.port_id_action->action;
12000 dev_flow->handle->rix_port_id_action = 0;
12002 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
12004 mdest_res->sample_idx[dest_index].rix_jump =
12005 dev_flow->handle->rix_jump;
12006 sample_act->dr_jump_action =
12007 dev_flow->dv.jump->action;
12008 dev_flow->handle->rix_jump = 0;
12010 sample_act->actions_num = normal_idx;
12011 /* update sample action resource into first index of array */
12012 mdest_res->ft_type = res->ft_type;
12013 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
12014 sizeof(struct mlx5_flow_sub_actions_idx));
12015 memcpy(&mdest_res->sample_act[0], &res->sample_act,
12016 sizeof(struct mlx5_flow_sub_actions_list));
12017 mdest_res->num_of_dest = num_of_dest;
12018 if (flow_dv_dest_array_resource_register(dev, mdest_res,
12020 return rte_flow_error_set(error, EINVAL,
12021 RTE_FLOW_ERROR_TYPE_ACTION,
12022 NULL, "can't create sample "
12025 res->sub_actions = sample_actions;
12026 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
12027 return rte_flow_error_set(error, EINVAL,
12028 RTE_FLOW_ERROR_TYPE_ACTION,
12030 "can't create sample action");
12036 * Remove an ASO age action from age actions list.
12039 * Pointer to the Ethernet device structure.
12041 * Pointer to the aso age action handler.
12044 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
12045 struct mlx5_aso_age_action *age)
12047 struct mlx5_age_info *age_info;
12048 struct mlx5_age_param *age_param = &age->age_params;
12049 struct mlx5_priv *priv = dev->data->dev_private;
12050 uint16_t expected = AGE_CANDIDATE;
12052 age_info = GET_PORT_AGE_INFO(priv);
12053 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
12054 AGE_FREE, false, __ATOMIC_RELAXED,
12055 __ATOMIC_RELAXED)) {
12057 * We need the lock even it is age timeout,
12058 * since age action may still in process.
12060 rte_spinlock_lock(&age_info->aged_sl);
12061 LIST_REMOVE(age, next);
12062 rte_spinlock_unlock(&age_info->aged_sl);
12063 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
12068 * Release an ASO age action.
12071 * Pointer to the Ethernet device structure.
12072 * @param[in] age_idx
12073 * Index of ASO age action to release.
12075 * True if the release operation is during flow destroy operation.
12076 * False if the release operation is during action destroy operation.
12079 * 0 when age action was removed, otherwise the number of references.
12082 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
12084 struct mlx5_priv *priv = dev->data->dev_private;
12085 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12086 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
12087 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
12090 flow_dv_aso_age_remove_from_age(dev, age);
12091 rte_spinlock_lock(&mng->free_sl);
12092 LIST_INSERT_HEAD(&mng->free, age, next);
12093 rte_spinlock_unlock(&mng->free_sl);
12099 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
12102 * Pointer to the Ethernet device structure.
12105 * 0 on success, otherwise negative errno value and rte_errno is set.
12108 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
12110 struct mlx5_priv *priv = dev->data->dev_private;
12111 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12112 void *old_pools = mng->pools;
12113 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
12114 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
12115 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12118 rte_errno = ENOMEM;
12122 memcpy(pools, old_pools,
12123 mng->n * sizeof(struct mlx5_flow_counter_pool *));
12124 mlx5_free(old_pools);
12126 /* First ASO flow hit allocation - starting ASO data-path. */
12127 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
12135 mng->pools = pools;
12140 * Create and initialize a new ASO aging pool.
12143 * Pointer to the Ethernet device structure.
12144 * @param[out] age_free
12145 * Where to put the pointer of a new age action.
12148 * The age actions pool pointer and @p age_free is set on success,
12149 * NULL otherwise and rte_errno is set.
12151 static struct mlx5_aso_age_pool *
12152 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12153 struct mlx5_aso_age_action **age_free)
12155 struct mlx5_priv *priv = dev->data->dev_private;
12156 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12157 struct mlx5_aso_age_pool *pool = NULL;
12158 struct mlx5_devx_obj *obj = NULL;
12161 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12162 priv->sh->cdev->pdn);
12164 rte_errno = ENODATA;
12165 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12168 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12170 claim_zero(mlx5_devx_cmd_destroy(obj));
12171 rte_errno = ENOMEM;
12174 pool->flow_hit_aso_obj = obj;
12175 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12176 rte_rwlock_write_lock(&mng->resize_rwl);
12177 pool->index = mng->next;
12178 /* Resize pools array if there is no room for the new pool in it. */
12179 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12180 claim_zero(mlx5_devx_cmd_destroy(obj));
12182 rte_rwlock_write_unlock(&mng->resize_rwl);
12185 mng->pools[pool->index] = pool;
12187 rte_rwlock_write_unlock(&mng->resize_rwl);
12188 /* Assign the first action in the new pool, the rest go to free list. */
12189 *age_free = &pool->actions[0];
12190 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12191 pool->actions[i].offset = i;
12192 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12198 * Allocate a ASO aging bit.
12201 * Pointer to the Ethernet device structure.
12202 * @param[out] error
12203 * Pointer to the error structure.
12206 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12209 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12211 struct mlx5_priv *priv = dev->data->dev_private;
12212 const struct mlx5_aso_age_pool *pool;
12213 struct mlx5_aso_age_action *age_free = NULL;
12214 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12217 /* Try to get the next free age action bit. */
12218 rte_spinlock_lock(&mng->free_sl);
12219 age_free = LIST_FIRST(&mng->free);
12221 LIST_REMOVE(age_free, next);
12222 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12223 rte_spinlock_unlock(&mng->free_sl);
12224 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12225 NULL, "failed to create ASO age pool");
12226 return 0; /* 0 is an error. */
12228 rte_spinlock_unlock(&mng->free_sl);
12229 pool = container_of
12230 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12231 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12233 if (!age_free->dr_action) {
12234 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12238 rte_flow_error_set(error, rte_errno,
12239 RTE_FLOW_ERROR_TYPE_ACTION,
12240 NULL, "failed to get reg_c "
12241 "for ASO flow hit");
12242 return 0; /* 0 is an error. */
12244 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12245 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12246 (priv->sh->rx_domain,
12247 pool->flow_hit_aso_obj->obj, age_free->offset,
12248 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12249 (reg_c - REG_C_0));
12250 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12251 if (!age_free->dr_action) {
12253 rte_spinlock_lock(&mng->free_sl);
12254 LIST_INSERT_HEAD(&mng->free, age_free, next);
12255 rte_spinlock_unlock(&mng->free_sl);
12256 rte_flow_error_set(error, rte_errno,
12257 RTE_FLOW_ERROR_TYPE_ACTION,
12258 NULL, "failed to create ASO "
12259 "flow hit action");
12260 return 0; /* 0 is an error. */
12263 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12264 return pool->index | ((age_free->offset + 1) << 16);
12268 * Initialize flow ASO age parameters.
12271 * Pointer to rte_eth_dev structure.
12272 * @param[in] age_idx
12273 * Index of ASO age action.
12274 * @param[in] context
12275 * Pointer to flow counter age context.
12276 * @param[in] timeout
12277 * Aging timeout in seconds.
12281 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12286 struct mlx5_aso_age_action *aso_age;
12288 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12289 MLX5_ASSERT(aso_age);
12290 aso_age->age_params.context = context;
12291 aso_age->age_params.timeout = timeout;
12292 aso_age->age_params.port_id = dev->data->port_id;
12293 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12295 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12300 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12301 const struct rte_flow_item_integrity *value,
12302 void *headers_m, void *headers_v)
12305 /* RTE l4_ok filter aggregates hardware l4_ok and
12306 * l4_checksum_ok filters.
12307 * Positive RTE l4_ok match requires hardware match on both L4
12308 * hardware integrity bits.
12309 * For negative match, check hardware l4_checksum_ok bit only,
12310 * because hardware sets that bit to 0 for all packets
12313 if (value->l4_ok) {
12314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12315 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12317 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12318 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12321 if (mask->l4_csum_ok) {
12322 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12323 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12324 value->l4_csum_ok);
12329 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12330 const struct rte_flow_item_integrity *value,
12331 void *headers_m, void *headers_v, bool is_ipv4)
12334 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12335 * ipv4_csum_ok filters.
12336 * Positive RTE l3_ok match requires hardware match on both L3
12337 * hardware integrity bits.
12338 * For negative match, check hardware l3_csum_ok bit only,
12339 * because hardware sets that bit to 0 for all packets
12343 if (value->l3_ok) {
12344 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12346 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12349 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12350 ipv4_checksum_ok, 1);
12351 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12352 ipv4_checksum_ok, !!value->l3_ok);
12354 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12359 if (mask->ipv4_csum_ok) {
12360 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12361 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12362 value->ipv4_csum_ok);
12367 set_integrity_bits(void *headers_m, void *headers_v,
12368 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12370 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12371 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12373 /* Integrity bits validation cleared spec pointer */
12374 MLX5_ASSERT(spec != NULL);
12376 mask = &rte_flow_item_integrity_mask;
12377 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12379 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12383 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12385 struct rte_flow_item *integrity_items[2],
12386 uint64_t pattern_flags)
12388 void *headers_m, *headers_v;
12391 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12392 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12394 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12395 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12397 set_integrity_bits(headers_m, headers_v,
12398 integrity_items[1], is_l3_ip4);
12400 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12401 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12403 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12404 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12406 set_integrity_bits(headers_m, headers_v,
12407 integrity_items[0], is_l3_ip4);
12412 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12413 const struct rte_flow_item *integrity_items[2],
12414 uint64_t *last_item)
12416 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12418 /* integrity bits validation cleared spec pointer */
12419 MLX5_ASSERT(spec != NULL);
12420 if (spec->level > 1) {
12421 integrity_items[1] = item;
12422 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12424 integrity_items[0] = item;
12425 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12430 * Prepares DV flow counter with aging configuration.
12431 * Gets it by index when exists, creates a new one when doesn't.
12434 * Pointer to rte_eth_dev structure.
12435 * @param[in] dev_flow
12436 * Pointer to the mlx5_flow.
12437 * @param[in, out] flow
12438 * Pointer to the sub flow.
12440 * Pointer to the counter action configuration.
12442 * Pointer to the aging action configuration.
12443 * @param[out] error
12444 * Pointer to the error structure.
12447 * Pointer to the counter, NULL otherwise.
12449 static struct mlx5_flow_counter *
12450 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12451 struct mlx5_flow *dev_flow,
12452 struct rte_flow *flow,
12453 const struct rte_flow_action_count *count,
12454 const struct rte_flow_action_age *age,
12455 struct rte_flow_error *error)
12457 if (!flow->counter) {
12458 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12460 if (!flow->counter) {
12461 rte_flow_error_set(error, rte_errno,
12462 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12463 "cannot create counter object.");
12467 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12471 * Release an ASO CT action by its own device.
12474 * Pointer to the Ethernet device structure.
12476 * Index of ASO CT action to release.
12479 * 0 when CT action was removed, otherwise the number of references.
12482 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12484 struct mlx5_priv *priv = dev->data->dev_private;
12485 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12487 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12488 enum mlx5_aso_ct_state state =
12489 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12491 /* Cannot release when CT is in the ASO SQ. */
12492 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12494 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12496 if (ct->dr_action_orig) {
12497 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12498 claim_zero(mlx5_glue->destroy_flow_action
12499 (ct->dr_action_orig));
12501 ct->dr_action_orig = NULL;
12503 if (ct->dr_action_rply) {
12504 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12505 claim_zero(mlx5_glue->destroy_flow_action
12506 (ct->dr_action_rply));
12508 ct->dr_action_rply = NULL;
12510 /* Clear the state to free, no need in 1st allocation. */
12511 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12512 rte_spinlock_lock(&mng->ct_sl);
12513 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12514 rte_spinlock_unlock(&mng->ct_sl);
12520 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12521 struct rte_flow_error *error)
12523 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12524 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12525 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12528 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12529 if (dev->data->dev_started != 1)
12530 return rte_flow_error_set(error, EAGAIN,
12531 RTE_FLOW_ERROR_TYPE_ACTION,
12533 "Indirect CT action cannot be destroyed when the port is stopped");
12534 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12536 return rte_flow_error_set(error, EAGAIN,
12537 RTE_FLOW_ERROR_TYPE_ACTION,
12539 "Current state prevents indirect CT action from being destroyed");
12544 * Resize the ASO CT pools array by 64 pools.
12547 * Pointer to the Ethernet device structure.
12550 * 0 on success, otherwise negative errno value and rte_errno is set.
12553 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12555 struct mlx5_priv *priv = dev->data->dev_private;
12556 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12557 void *old_pools = mng->pools;
12558 /* Magic number now, need a macro. */
12559 uint32_t resize = mng->n + 64;
12560 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12561 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12564 rte_errno = ENOMEM;
12567 rte_rwlock_write_lock(&mng->resize_rwl);
12568 /* ASO SQ/QP was already initialized in the startup. */
12570 /* Realloc could be an alternative choice. */
12571 rte_memcpy(pools, old_pools,
12572 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12573 mlx5_free(old_pools);
12576 mng->pools = pools;
12577 rte_rwlock_write_unlock(&mng->resize_rwl);
12582 * Create and initialize a new ASO CT pool.
12585 * Pointer to the Ethernet device structure.
12586 * @param[out] ct_free
12587 * Where to put the pointer of a new CT action.
12590 * The CT actions pool pointer and @p ct_free is set on success,
12591 * NULL otherwise and rte_errno is set.
12593 static struct mlx5_aso_ct_pool *
12594 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12595 struct mlx5_aso_ct_action **ct_free)
12597 struct mlx5_priv *priv = dev->data->dev_private;
12598 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12599 struct mlx5_aso_ct_pool *pool = NULL;
12600 struct mlx5_devx_obj *obj = NULL;
12602 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12604 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12605 priv->sh->cdev->pdn,
12608 rte_errno = ENODATA;
12609 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12612 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12614 rte_errno = ENOMEM;
12615 claim_zero(mlx5_devx_cmd_destroy(obj));
12618 pool->devx_obj = obj;
12619 pool->index = mng->next;
12620 /* Resize pools array if there is no room for the new pool in it. */
12621 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12622 claim_zero(mlx5_devx_cmd_destroy(obj));
12626 mng->pools[pool->index] = pool;
12628 /* Assign the first action in the new pool, the rest go to free list. */
12629 *ct_free = &pool->actions[0];
12630 /* Lock outside, the list operation is safe here. */
12631 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12632 /* refcnt is 0 when allocating the memory. */
12633 pool->actions[i].offset = i;
12634 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12640 * Allocate a ASO CT action from free list.
12643 * Pointer to the Ethernet device structure.
12644 * @param[out] error
12645 * Pointer to the error structure.
12648 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12651 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12653 struct mlx5_priv *priv = dev->data->dev_private;
12654 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12655 struct mlx5_aso_ct_action *ct = NULL;
12656 struct mlx5_aso_ct_pool *pool;
12661 if (!priv->sh->cdev->config.devx) {
12662 rte_errno = ENOTSUP;
12665 /* Get a free CT action, if no, a new pool will be created. */
12666 rte_spinlock_lock(&mng->ct_sl);
12667 ct = LIST_FIRST(&mng->free_cts);
12669 LIST_REMOVE(ct, next);
12670 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12671 rte_spinlock_unlock(&mng->ct_sl);
12672 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12673 NULL, "failed to create ASO CT pool");
12676 rte_spinlock_unlock(&mng->ct_sl);
12677 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12678 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12679 /* 0: inactive, 1: created, 2+: used by flows. */
12680 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12681 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12682 if (!ct->dr_action_orig) {
12683 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12684 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12685 (priv->sh->rx_domain, pool->devx_obj->obj,
12687 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12690 RTE_SET_USED(reg_c);
12692 if (!ct->dr_action_orig) {
12693 flow_dv_aso_ct_dev_release(dev, ct_idx);
12694 rte_flow_error_set(error, rte_errno,
12695 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12696 "failed to create ASO CT action");
12700 if (!ct->dr_action_rply) {
12701 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12702 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12703 (priv->sh->rx_domain, pool->devx_obj->obj,
12705 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12708 if (!ct->dr_action_rply) {
12709 flow_dv_aso_ct_dev_release(dev, ct_idx);
12710 rte_flow_error_set(error, rte_errno,
12711 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12712 "failed to create ASO CT action");
12720 * Create a conntrack object with context and actions by using ASO mechanism.
12723 * Pointer to rte_eth_dev structure.
12725 * Pointer to conntrack information profile.
12726 * @param[out] error
12727 * Pointer to the error structure.
12730 * Index to conntrack object on success, 0 otherwise.
12733 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12734 const struct rte_flow_action_conntrack *pro,
12735 struct rte_flow_error *error)
12737 struct mlx5_priv *priv = dev->data->dev_private;
12738 struct mlx5_dev_ctx_shared *sh = priv->sh;
12739 struct mlx5_aso_ct_action *ct;
12742 if (!sh->ct_aso_en)
12743 return rte_flow_error_set(error, ENOTSUP,
12744 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12745 "Connection is not supported");
12746 idx = flow_dv_aso_ct_alloc(dev, error);
12748 return rte_flow_error_set(error, rte_errno,
12749 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12750 "Failed to allocate CT object");
12751 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12752 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12753 return rte_flow_error_set(error, EBUSY,
12754 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12755 "Failed to update CT");
12756 ct->is_original = !!pro->is_original_dir;
12757 ct->peer = pro->peer_port;
12762 * Fill the flow with DV spec, lock free
12763 * (mutex should be acquired by caller).
12766 * Pointer to rte_eth_dev structure.
12767 * @param[in, out] dev_flow
12768 * Pointer to the sub flow.
12770 * Pointer to the flow attributes.
12772 * Pointer to the list of items.
12773 * @param[in] actions
12774 * Pointer to the list of actions.
12775 * @param[out] error
12776 * Pointer to the error structure.
12779 * 0 on success, a negative errno value otherwise and rte_errno is set.
12782 flow_dv_translate(struct rte_eth_dev *dev,
12783 struct mlx5_flow *dev_flow,
12784 const struct rte_flow_attr *attr,
12785 const struct rte_flow_item items[],
12786 const struct rte_flow_action actions[],
12787 struct rte_flow_error *error)
12789 struct mlx5_priv *priv = dev->data->dev_private;
12790 struct mlx5_sh_config *dev_conf = &priv->sh->config;
12791 struct rte_flow *flow = dev_flow->flow;
12792 struct mlx5_flow_handle *handle = dev_flow->handle;
12793 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12794 struct mlx5_flow_rss_desc *rss_desc;
12795 uint64_t item_flags = 0;
12796 uint64_t last_item = 0;
12797 uint64_t action_flags = 0;
12798 struct mlx5_flow_dv_matcher matcher = {
12800 .size = sizeof(matcher.mask.buf),
12804 bool actions_end = false;
12806 struct mlx5_flow_dv_modify_hdr_resource res;
12807 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12808 sizeof(struct mlx5_modification_cmd) *
12809 (MLX5_MAX_MODIFY_NUM + 1)];
12811 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12812 const struct rte_flow_action_count *count = NULL;
12813 const struct rte_flow_action_age *non_shared_age = NULL;
12814 union flow_dv_attr flow_attr = { .attr = 0 };
12816 union mlx5_flow_tbl_key tbl_key;
12817 uint32_t modify_action_position = UINT32_MAX;
12818 void *match_mask = matcher.mask.buf;
12819 void *match_value = dev_flow->dv.value.buf;
12820 uint8_t next_protocol = 0xff;
12821 struct rte_vlan_hdr vlan = { 0 };
12822 struct mlx5_flow_dv_dest_array_resource mdest_res;
12823 struct mlx5_flow_dv_sample_resource sample_res;
12824 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12825 const struct rte_flow_action_sample *sample = NULL;
12826 struct mlx5_flow_sub_actions_list *sample_act;
12827 uint32_t sample_act_pos = UINT32_MAX;
12828 uint32_t age_act_pos = UINT32_MAX;
12829 uint32_t num_of_dest = 0;
12830 int tmp_actions_n = 0;
12833 const struct mlx5_flow_tunnel *tunnel = NULL;
12834 struct flow_grp_info grp_info = {
12835 .external = !!dev_flow->external,
12836 .transfer = !!attr->transfer,
12837 .fdb_def_rule = !!priv->fdb_def_rule,
12838 .skip_scale = dev_flow->skip_scale &
12839 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12840 .std_tbl_fix = true,
12842 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12843 const struct rte_flow_item *tunnel_item = NULL;
12844 const struct rte_flow_item *gre_item = NULL;
12847 return rte_flow_error_set(error, ENOMEM,
12848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12850 "failed to push flow workspace");
12851 rss_desc = &wks->rss_desc;
12852 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12853 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12854 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12855 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12856 /* update normal path action resource into last index of array */
12857 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12858 if (is_tunnel_offload_active(dev)) {
12859 if (dev_flow->tunnel) {
12860 RTE_VERIFY(dev_flow->tof_type ==
12861 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12862 tunnel = dev_flow->tunnel;
12864 tunnel = mlx5_get_tof(items, actions,
12865 &dev_flow->tof_type);
12866 dev_flow->tunnel = tunnel;
12868 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12869 (dev, attr, tunnel, dev_flow->tof_type);
12871 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12872 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12873 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12877 dev_flow->dv.group = table;
12878 if (attr->transfer)
12879 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12880 /* number of actions must be set to 0 in case of dirty stack. */
12881 mhdr_res->actions_num = 0;
12882 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12884 * do not add decap action if match rule drops packet
12885 * HW rejects rules with decap & drop
12887 * if tunnel match rule was inserted before matching tunnel set
12888 * rule flow table used in the match rule must be registered.
12889 * current implementation handles that in the
12890 * flow_dv_match_register() at the function end.
12892 bool add_decap = true;
12893 const struct rte_flow_action *ptr = actions;
12895 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12896 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12902 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12906 dev_flow->dv.actions[actions_n++] =
12907 dev_flow->dv.encap_decap->action;
12908 action_flags |= MLX5_FLOW_ACTION_DECAP;
12911 for (; !actions_end ; actions++) {
12912 const struct rte_flow_action_queue *queue;
12913 const struct rte_flow_action_rss *rss;
12914 const struct rte_flow_action *action = actions;
12915 const uint8_t *rss_key;
12916 struct mlx5_flow_tbl_resource *tbl;
12917 struct mlx5_aso_age_action *age_act;
12918 struct mlx5_flow_counter *cnt_act;
12919 uint32_t port_id = 0;
12920 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12921 int action_type = actions->type;
12922 const struct rte_flow_action *found_action = NULL;
12923 uint32_t jump_group = 0;
12924 uint32_t owner_idx;
12925 struct mlx5_aso_ct_action *ct;
12927 if (!mlx5_flow_os_action_supported(action_type))
12928 return rte_flow_error_set(error, ENOTSUP,
12929 RTE_FLOW_ERROR_TYPE_ACTION,
12931 "action not supported");
12932 switch (action_type) {
12933 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12934 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12936 case RTE_FLOW_ACTION_TYPE_VOID:
12938 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12939 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12940 if (flow_dv_translate_action_port_id(dev, action,
12943 port_id_resource.port_id = port_id;
12944 MLX5_ASSERT(!handle->rix_port_id_action);
12945 if (flow_dv_port_id_action_resource_register
12946 (dev, &port_id_resource, dev_flow, error))
12948 dev_flow->dv.actions[actions_n++] =
12949 dev_flow->dv.port_id_action->action;
12950 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12951 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12952 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12955 case RTE_FLOW_ACTION_TYPE_FLAG:
12956 action_flags |= MLX5_FLOW_ACTION_FLAG;
12958 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12959 struct rte_flow_action_mark mark = {
12960 .id = MLX5_FLOW_MARK_DEFAULT,
12963 if (flow_dv_convert_action_mark(dev, &mark,
12967 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12970 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12972 * Only one FLAG or MARK is supported per device flow
12973 * right now. So the pointer to the tag resource must be
12974 * zero before the register process.
12976 MLX5_ASSERT(!handle->dvh.rix_tag);
12977 if (flow_dv_tag_resource_register(dev, tag_be,
12980 MLX5_ASSERT(dev_flow->dv.tag_resource);
12981 dev_flow->dv.actions[actions_n++] =
12982 dev_flow->dv.tag_resource->action;
12984 case RTE_FLOW_ACTION_TYPE_MARK:
12985 action_flags |= MLX5_FLOW_ACTION_MARK;
12987 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12988 const struct rte_flow_action_mark *mark =
12989 (const struct rte_flow_action_mark *)
12992 if (flow_dv_convert_action_mark(dev, mark,
12996 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
13000 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
13001 /* Legacy (non-extensive) MARK action. */
13002 tag_be = mlx5_flow_mark_set
13003 (((const struct rte_flow_action_mark *)
13004 (actions->conf))->id);
13005 MLX5_ASSERT(!handle->dvh.rix_tag);
13006 if (flow_dv_tag_resource_register(dev, tag_be,
13009 MLX5_ASSERT(dev_flow->dv.tag_resource);
13010 dev_flow->dv.actions[actions_n++] =
13011 dev_flow->dv.tag_resource->action;
13013 case RTE_FLOW_ACTION_TYPE_SET_META:
13014 if (flow_dv_convert_action_set_meta
13015 (dev, mhdr_res, attr,
13016 (const struct rte_flow_action_set_meta *)
13017 actions->conf, error))
13019 action_flags |= MLX5_FLOW_ACTION_SET_META;
13021 case RTE_FLOW_ACTION_TYPE_SET_TAG:
13022 if (flow_dv_convert_action_set_tag
13024 (const struct rte_flow_action_set_tag *)
13025 actions->conf, error))
13027 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13029 case RTE_FLOW_ACTION_TYPE_DROP:
13030 action_flags |= MLX5_FLOW_ACTION_DROP;
13031 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
13033 case RTE_FLOW_ACTION_TYPE_QUEUE:
13034 queue = actions->conf;
13035 rss_desc->queue_num = 1;
13036 rss_desc->queue[0] = queue->index;
13037 action_flags |= MLX5_FLOW_ACTION_QUEUE;
13038 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
13039 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
13042 case RTE_FLOW_ACTION_TYPE_RSS:
13043 rss = actions->conf;
13044 memcpy(rss_desc->queue, rss->queue,
13045 rss->queue_num * sizeof(uint16_t));
13046 rss_desc->queue_num = rss->queue_num;
13047 /* NULL RSS key indicates default RSS key. */
13048 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13049 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13051 * rss->level and rss.types should be set in advance
13052 * when expanding items for RSS.
13054 action_flags |= MLX5_FLOW_ACTION_RSS;
13055 dev_flow->handle->fate_action = rss_desc->shared_rss ?
13056 MLX5_FLOW_FATE_SHARED_RSS :
13057 MLX5_FLOW_FATE_QUEUE;
13059 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
13060 owner_idx = (uint32_t)(uintptr_t)action->conf;
13061 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
13062 if (flow->age == 0) {
13063 flow->age = owner_idx;
13064 __atomic_fetch_add(&age_act->refcnt, 1,
13067 age_act_pos = actions_n++;
13068 action_flags |= MLX5_FLOW_ACTION_AGE;
13070 case RTE_FLOW_ACTION_TYPE_AGE:
13071 non_shared_age = action->conf;
13072 age_act_pos = actions_n++;
13073 action_flags |= MLX5_FLOW_ACTION_AGE;
13075 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
13076 owner_idx = (uint32_t)(uintptr_t)action->conf;
13077 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
13079 MLX5_ASSERT(cnt_act != NULL);
13081 * When creating meter drop flow in drop table, the
13082 * counter should not overwrite the rte flow counter.
13084 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13085 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
13086 dev_flow->dv.actions[actions_n++] =
13089 if (flow->counter == 0) {
13090 flow->counter = owner_idx;
13092 (&cnt_act->shared_info.refcnt,
13093 1, __ATOMIC_RELAXED);
13095 /* Save information first, will apply later. */
13096 action_flags |= MLX5_FLOW_ACTION_COUNT;
13099 case RTE_FLOW_ACTION_TYPE_COUNT:
13100 if (!priv->sh->cdev->config.devx) {
13101 return rte_flow_error_set
13103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13105 "count action not supported");
13107 /* Save information first, will apply later. */
13108 count = action->conf;
13109 action_flags |= MLX5_FLOW_ACTION_COUNT;
13111 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
13112 dev_flow->dv.actions[actions_n++] =
13113 priv->sh->pop_vlan_action;
13114 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
13116 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
13117 if (!(action_flags &
13118 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
13119 flow_dev_get_vlan_info_from_items(items, &vlan);
13120 vlan.eth_proto = rte_be_to_cpu_16
13121 ((((const struct rte_flow_action_of_push_vlan *)
13122 actions->conf)->ethertype));
13123 found_action = mlx5_flow_find_action
13125 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
13127 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13128 found_action = mlx5_flow_find_action
13130 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
13132 mlx5_update_vlan_vid_pcp(found_action, &vlan);
13133 if (flow_dv_create_action_push_vlan
13134 (dev, attr, &vlan, dev_flow, error))
13136 dev_flow->dv.actions[actions_n++] =
13137 dev_flow->dv.push_vlan_res->action;
13138 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
13140 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
13141 /* of_vlan_push action handled this action */
13142 MLX5_ASSERT(action_flags &
13143 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13145 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13146 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13148 flow_dev_get_vlan_info_from_items(items, &vlan);
13149 mlx5_update_vlan_vid_pcp(actions, &vlan);
13150 /* If no VLAN push - this is a modify header action */
13151 if (flow_dv_convert_action_modify_vlan_vid
13152 (mhdr_res, actions, error))
13154 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13156 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13157 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13158 if (flow_dv_create_action_l2_encap(dev, actions,
13163 dev_flow->dv.actions[actions_n++] =
13164 dev_flow->dv.encap_decap->action;
13165 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13166 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13167 sample_act->action_flags |=
13168 MLX5_FLOW_ACTION_ENCAP;
13170 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13171 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13172 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13176 dev_flow->dv.actions[actions_n++] =
13177 dev_flow->dv.encap_decap->action;
13178 action_flags |= MLX5_FLOW_ACTION_DECAP;
13180 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13181 /* Handle encap with preceding decap. */
13182 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13183 if (flow_dv_create_action_raw_encap
13184 (dev, actions, dev_flow, attr, error))
13186 dev_flow->dv.actions[actions_n++] =
13187 dev_flow->dv.encap_decap->action;
13189 /* Handle encap without preceding decap. */
13190 if (flow_dv_create_action_l2_encap
13191 (dev, actions, dev_flow, attr->transfer,
13194 dev_flow->dv.actions[actions_n++] =
13195 dev_flow->dv.encap_decap->action;
13197 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13198 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13199 sample_act->action_flags |=
13200 MLX5_FLOW_ACTION_ENCAP;
13202 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13203 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13205 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13206 if (flow_dv_create_action_l2_decap
13207 (dev, dev_flow, attr->transfer, error))
13209 dev_flow->dv.actions[actions_n++] =
13210 dev_flow->dv.encap_decap->action;
13212 /* If decap is followed by encap, handle it at encap. */
13213 action_flags |= MLX5_FLOW_ACTION_DECAP;
13215 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13216 dev_flow->dv.actions[actions_n++] =
13217 (void *)(uintptr_t)action->conf;
13218 action_flags |= MLX5_FLOW_ACTION_JUMP;
13220 case RTE_FLOW_ACTION_TYPE_JUMP:
13221 jump_group = ((const struct rte_flow_action_jump *)
13222 action->conf)->group;
13223 grp_info.std_tbl_fix = 0;
13224 if (dev_flow->skip_scale &
13225 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13226 grp_info.skip_scale = 1;
13228 grp_info.skip_scale = 0;
13229 ret = mlx5_flow_group_to_table(dev, tunnel,
13235 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13237 !!dev_flow->external,
13238 tunnel, jump_group, 0,
13241 return rte_flow_error_set
13243 RTE_FLOW_ERROR_TYPE_ACTION,
13245 "cannot create jump action.");
13246 if (flow_dv_jump_tbl_resource_register
13247 (dev, tbl, dev_flow, error)) {
13248 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13249 return rte_flow_error_set
13251 RTE_FLOW_ERROR_TYPE_ACTION,
13253 "cannot create jump action.");
13255 dev_flow->dv.actions[actions_n++] =
13256 dev_flow->dv.jump->action;
13257 action_flags |= MLX5_FLOW_ACTION_JUMP;
13258 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13259 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13262 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13263 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13264 if (flow_dv_convert_action_modify_mac
13265 (mhdr_res, actions, error))
13267 action_flags |= actions->type ==
13268 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13269 MLX5_FLOW_ACTION_SET_MAC_SRC :
13270 MLX5_FLOW_ACTION_SET_MAC_DST;
13272 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13273 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13274 if (flow_dv_convert_action_modify_ipv4
13275 (mhdr_res, actions, error))
13277 action_flags |= actions->type ==
13278 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13279 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13280 MLX5_FLOW_ACTION_SET_IPV4_DST;
13282 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13283 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13284 if (flow_dv_convert_action_modify_ipv6
13285 (mhdr_res, actions, error))
13287 action_flags |= actions->type ==
13288 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13289 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13290 MLX5_FLOW_ACTION_SET_IPV6_DST;
13292 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13293 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13294 if (flow_dv_convert_action_modify_tp
13295 (mhdr_res, actions, items,
13296 &flow_attr, dev_flow, !!(action_flags &
13297 MLX5_FLOW_ACTION_DECAP), error))
13299 action_flags |= actions->type ==
13300 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13301 MLX5_FLOW_ACTION_SET_TP_SRC :
13302 MLX5_FLOW_ACTION_SET_TP_DST;
13304 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13305 if (flow_dv_convert_action_modify_dec_ttl
13306 (mhdr_res, items, &flow_attr, dev_flow,
13308 MLX5_FLOW_ACTION_DECAP), error))
13310 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13312 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13313 if (flow_dv_convert_action_modify_ttl
13314 (mhdr_res, actions, items, &flow_attr,
13315 dev_flow, !!(action_flags &
13316 MLX5_FLOW_ACTION_DECAP), error))
13318 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13320 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13321 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13322 if (flow_dv_convert_action_modify_tcp_seq
13323 (mhdr_res, actions, error))
13325 action_flags |= actions->type ==
13326 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13327 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13328 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13331 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13332 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13333 if (flow_dv_convert_action_modify_tcp_ack
13334 (mhdr_res, actions, error))
13336 action_flags |= actions->type ==
13337 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13338 MLX5_FLOW_ACTION_INC_TCP_ACK :
13339 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13341 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13342 if (flow_dv_convert_action_set_reg
13343 (mhdr_res, actions, error))
13345 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13347 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13348 if (flow_dv_convert_action_copy_mreg
13349 (dev, mhdr_res, actions, error))
13351 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13353 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13354 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13355 dev_flow->handle->fate_action =
13356 MLX5_FLOW_FATE_DEFAULT_MISS;
13358 case RTE_FLOW_ACTION_TYPE_METER:
13360 return rte_flow_error_set(error, rte_errno,
13361 RTE_FLOW_ERROR_TYPE_ACTION,
13362 NULL, "Failed to get meter in flow.");
13363 /* Set the meter action. */
13364 dev_flow->dv.actions[actions_n++] =
13365 wks->fm->meter_action;
13366 action_flags |= MLX5_FLOW_ACTION_METER;
13368 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13369 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13372 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13374 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13375 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13378 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13380 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13381 sample_act_pos = actions_n;
13382 sample = (const struct rte_flow_action_sample *)
13385 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13386 /* put encap action into group if work with port id */
13387 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13388 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13389 sample_act->action_flags |=
13390 MLX5_FLOW_ACTION_ENCAP;
13392 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13393 if (flow_dv_convert_action_modify_field
13394 (dev, mhdr_res, actions, attr, error))
13396 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13398 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13399 owner_idx = (uint32_t)(uintptr_t)action->conf;
13400 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13402 return rte_flow_error_set(error, EINVAL,
13403 RTE_FLOW_ERROR_TYPE_ACTION,
13405 "Failed to get CT object.");
13406 if (mlx5_aso_ct_available(priv->sh, ct))
13407 return rte_flow_error_set(error, rte_errno,
13408 RTE_FLOW_ERROR_TYPE_ACTION,
13410 "CT is unavailable.");
13411 if (ct->is_original)
13412 dev_flow->dv.actions[actions_n] =
13413 ct->dr_action_orig;
13415 dev_flow->dv.actions[actions_n] =
13416 ct->dr_action_rply;
13417 if (flow->ct == 0) {
13418 flow->indirect_type =
13419 MLX5_INDIRECT_ACTION_TYPE_CT;
13420 flow->ct = owner_idx;
13421 __atomic_fetch_add(&ct->refcnt, 1,
13425 action_flags |= MLX5_FLOW_ACTION_CT;
13427 case RTE_FLOW_ACTION_TYPE_END:
13428 actions_end = true;
13429 if (mhdr_res->actions_num) {
13430 /* create modify action if needed. */
13431 if (flow_dv_modify_hdr_resource_register
13432 (dev, mhdr_res, dev_flow, error))
13434 dev_flow->dv.actions[modify_action_position] =
13435 handle->dvh.modify_hdr->action;
13438 * Handle AGE and COUNT action by single HW counter
13439 * when they are not shared.
13441 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13442 if ((non_shared_age && count) ||
13443 !flow_hit_aso_supported(priv->sh, attr)) {
13444 /* Creates age by counters. */
13445 cnt_act = flow_dv_prepare_counter
13452 dev_flow->dv.actions[age_act_pos] =
13456 if (!flow->age && non_shared_age) {
13457 flow->age = flow_dv_aso_age_alloc
13461 flow_dv_aso_age_params_init
13463 non_shared_age->context ?
13464 non_shared_age->context :
13465 (void *)(uintptr_t)
13466 (dev_flow->flow_idx),
13467 non_shared_age->timeout);
13469 age_act = flow_aso_age_get_by_idx(dev,
13471 dev_flow->dv.actions[age_act_pos] =
13472 age_act->dr_action;
13474 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13476 * Create one count action, to be used
13477 * by all sub-flows.
13479 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13484 dev_flow->dv.actions[actions_n++] =
13490 if (mhdr_res->actions_num &&
13491 modify_action_position == UINT32_MAX)
13492 modify_action_position = actions_n++;
13494 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13495 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13496 int item_type = items->type;
13498 if (!mlx5_flow_os_item_supported(item_type))
13499 return rte_flow_error_set(error, ENOTSUP,
13500 RTE_FLOW_ERROR_TYPE_ITEM,
13501 NULL, "item not supported");
13502 switch (item_type) {
13503 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13504 flow_dv_translate_item_port_id
13505 (dev, match_mask, match_value, items, attr);
13506 last_item = MLX5_FLOW_ITEM_PORT_ID;
13508 case RTE_FLOW_ITEM_TYPE_ETH:
13509 flow_dv_translate_item_eth(match_mask, match_value,
13511 dev_flow->dv.group);
13512 matcher.priority = action_flags &
13513 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13514 !dev_flow->external ?
13515 MLX5_PRIORITY_MAP_L3 :
13516 MLX5_PRIORITY_MAP_L2;
13517 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13518 MLX5_FLOW_LAYER_OUTER_L2;
13520 case RTE_FLOW_ITEM_TYPE_VLAN:
13521 flow_dv_translate_item_vlan(dev_flow,
13522 match_mask, match_value,
13524 dev_flow->dv.group);
13525 matcher.priority = MLX5_PRIORITY_MAP_L2;
13526 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13527 MLX5_FLOW_LAYER_INNER_VLAN) :
13528 (MLX5_FLOW_LAYER_OUTER_L2 |
13529 MLX5_FLOW_LAYER_OUTER_VLAN);
13531 case RTE_FLOW_ITEM_TYPE_IPV4:
13532 mlx5_flow_tunnel_ip_check(items, next_protocol,
13533 &item_flags, &tunnel);
13534 flow_dv_translate_item_ipv4(match_mask, match_value,
13536 dev_flow->dv.group);
13537 matcher.priority = MLX5_PRIORITY_MAP_L3;
13538 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13539 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13540 if (items->mask != NULL &&
13541 ((const struct rte_flow_item_ipv4 *)
13542 items->mask)->hdr.next_proto_id) {
13544 ((const struct rte_flow_item_ipv4 *)
13545 (items->spec))->hdr.next_proto_id;
13547 ((const struct rte_flow_item_ipv4 *)
13548 (items->mask))->hdr.next_proto_id;
13550 /* Reset for inner layer. */
13551 next_protocol = 0xff;
13554 case RTE_FLOW_ITEM_TYPE_IPV6:
13555 mlx5_flow_tunnel_ip_check(items, next_protocol,
13556 &item_flags, &tunnel);
13557 flow_dv_translate_item_ipv6(match_mask, match_value,
13559 dev_flow->dv.group);
13560 matcher.priority = MLX5_PRIORITY_MAP_L3;
13561 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13562 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13563 if (items->mask != NULL &&
13564 ((const struct rte_flow_item_ipv6 *)
13565 items->mask)->hdr.proto) {
13567 ((const struct rte_flow_item_ipv6 *)
13568 items->spec)->hdr.proto;
13570 ((const struct rte_flow_item_ipv6 *)
13571 items->mask)->hdr.proto;
13573 /* Reset for inner layer. */
13574 next_protocol = 0xff;
13577 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13578 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13581 last_item = tunnel ?
13582 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13583 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13584 if (items->mask != NULL &&
13585 ((const struct rte_flow_item_ipv6_frag_ext *)
13586 items->mask)->hdr.next_header) {
13588 ((const struct rte_flow_item_ipv6_frag_ext *)
13589 items->spec)->hdr.next_header;
13591 ((const struct rte_flow_item_ipv6_frag_ext *)
13592 items->mask)->hdr.next_header;
13594 /* Reset for inner layer. */
13595 next_protocol = 0xff;
13598 case RTE_FLOW_ITEM_TYPE_TCP:
13599 flow_dv_translate_item_tcp(match_mask, match_value,
13601 matcher.priority = MLX5_PRIORITY_MAP_L4;
13602 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13603 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13605 case RTE_FLOW_ITEM_TYPE_UDP:
13606 flow_dv_translate_item_udp(match_mask, match_value,
13608 matcher.priority = MLX5_PRIORITY_MAP_L4;
13609 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13610 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13612 case RTE_FLOW_ITEM_TYPE_GRE:
13613 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13614 last_item = MLX5_FLOW_LAYER_GRE;
13615 tunnel_item = items;
13618 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13619 flow_dv_translate_item_gre_key(match_mask,
13620 match_value, items);
13621 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13623 case RTE_FLOW_ITEM_TYPE_GRE_OPTION:
13624 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13625 last_item = MLX5_FLOW_LAYER_GRE;
13626 tunnel_item = items;
13628 case RTE_FLOW_ITEM_TYPE_NVGRE:
13629 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13630 last_item = MLX5_FLOW_LAYER_GRE;
13631 tunnel_item = items;
13633 case RTE_FLOW_ITEM_TYPE_VXLAN:
13634 flow_dv_translate_item_vxlan(dev, attr,
13635 match_mask, match_value,
13637 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13638 last_item = MLX5_FLOW_LAYER_VXLAN;
13640 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13641 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13642 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13643 tunnel_item = items;
13645 case RTE_FLOW_ITEM_TYPE_GENEVE:
13646 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13647 last_item = MLX5_FLOW_LAYER_GENEVE;
13648 tunnel_item = items;
13650 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13651 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13655 return rte_flow_error_set(error, -ret,
13656 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13657 "cannot create GENEVE TLV option");
13658 flow->geneve_tlv_option = 1;
13659 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13661 case RTE_FLOW_ITEM_TYPE_MPLS:
13662 flow_dv_translate_item_mpls(match_mask, match_value,
13663 items, last_item, tunnel);
13664 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13665 last_item = MLX5_FLOW_LAYER_MPLS;
13667 case RTE_FLOW_ITEM_TYPE_MARK:
13668 flow_dv_translate_item_mark(dev, match_mask,
13669 match_value, items);
13670 last_item = MLX5_FLOW_ITEM_MARK;
13672 case RTE_FLOW_ITEM_TYPE_META:
13673 flow_dv_translate_item_meta(dev, match_mask,
13674 match_value, attr, items);
13675 last_item = MLX5_FLOW_ITEM_METADATA;
13677 case RTE_FLOW_ITEM_TYPE_ICMP:
13678 flow_dv_translate_item_icmp(match_mask, match_value,
13680 matcher.priority = MLX5_PRIORITY_MAP_L4;
13681 last_item = MLX5_FLOW_LAYER_ICMP;
13683 case RTE_FLOW_ITEM_TYPE_ICMP6:
13684 flow_dv_translate_item_icmp6(match_mask, match_value,
13686 matcher.priority = MLX5_PRIORITY_MAP_L4;
13687 last_item = MLX5_FLOW_LAYER_ICMP6;
13689 case RTE_FLOW_ITEM_TYPE_TAG:
13690 flow_dv_translate_item_tag(dev, match_mask,
13691 match_value, items);
13692 last_item = MLX5_FLOW_ITEM_TAG;
13694 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13695 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13696 match_value, items);
13697 last_item = MLX5_FLOW_ITEM_TAG;
13699 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13700 flow_dv_translate_item_tx_queue(dev, match_mask,
13703 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13705 case RTE_FLOW_ITEM_TYPE_GTP:
13706 flow_dv_translate_item_gtp(match_mask, match_value,
13708 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13709 last_item = MLX5_FLOW_LAYER_GTP;
13711 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13712 ret = flow_dv_translate_item_gtp_psc(match_mask,
13716 return rte_flow_error_set(error, -ret,
13717 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13718 "cannot create GTP PSC item");
13719 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13721 case RTE_FLOW_ITEM_TYPE_ECPRI:
13722 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13723 /* Create it only the first time to be used. */
13724 ret = mlx5_flex_parser_ecpri_alloc(dev);
13726 return rte_flow_error_set
13728 RTE_FLOW_ERROR_TYPE_ITEM,
13730 "cannot create eCPRI parser");
13732 flow_dv_translate_item_ecpri(dev, match_mask,
13733 match_value, items,
13735 /* No other protocol should follow eCPRI layer. */
13736 last_item = MLX5_FLOW_LAYER_ECPRI;
13738 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13739 flow_dv_translate_item_integrity(items, integrity_items,
13742 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13743 flow_dv_translate_item_aso_ct(dev, match_mask,
13744 match_value, items);
13746 case RTE_FLOW_ITEM_TYPE_FLEX:
13747 flow_dv_translate_item_flex(dev, match_mask,
13748 match_value, items,
13749 dev_flow, tunnel != 0);
13750 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13751 MLX5_FLOW_ITEM_OUTER_FLEX;
13756 item_flags |= last_item;
13759 * When E-Switch mode is enabled, we have two cases where we need to
13760 * set the source port manually.
13761 * The first one, is in case of Nic steering rule, and the second is
13762 * E-Switch rule where no port_id item was found. In both cases
13763 * the source port is set according the current port in use.
13765 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode) {
13766 if (flow_dv_translate_item_port_id(dev, match_mask,
13767 match_value, NULL, attr))
13770 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13771 flow_dv_translate_item_integrity_post(match_mask, match_value,
13775 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13776 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13777 tunnel_item, item_flags);
13778 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13779 flow_dv_translate_item_geneve(match_mask, match_value,
13780 tunnel_item, item_flags);
13781 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13782 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13783 flow_dv_translate_item_gre(match_mask, match_value,
13784 tunnel_item, item_flags);
13785 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13786 flow_dv_translate_item_nvgre(match_mask, match_value,
13787 tunnel_item, item_flags);
13788 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION)
13789 flow_dv_translate_item_gre_option(match_mask, match_value,
13790 tunnel_item, gre_item, item_flags);
13792 MLX5_ASSERT(false);
13794 #ifdef RTE_LIBRTE_MLX5_DEBUG
13795 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13796 dev_flow->dv.value.buf));
13799 * Layers may be already initialized from prefix flow if this dev_flow
13800 * is the suffix flow.
13802 handle->layers |= item_flags;
13803 if (action_flags & MLX5_FLOW_ACTION_RSS)
13804 flow_dv_hashfields_set(dev_flow->handle->layers,
13806 &dev_flow->hash_fields);
13807 /* If has RSS action in the sample action, the Sample/Mirror resource
13808 * should be registered after the hash filed be update.
13810 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13811 ret = flow_dv_translate_action_sample(dev,
13820 ret = flow_dv_create_action_sample(dev,
13829 return rte_flow_error_set
13831 RTE_FLOW_ERROR_TYPE_ACTION,
13833 "cannot create sample action");
13834 if (num_of_dest > 1) {
13835 dev_flow->dv.actions[sample_act_pos] =
13836 dev_flow->dv.dest_array_res->action;
13838 dev_flow->dv.actions[sample_act_pos] =
13839 dev_flow->dv.sample_res->verbs_action;
13843 * For multiple destination (sample action with ratio=1), the encap
13844 * action and port id action will be combined into group action.
13845 * So need remove the original these actions in the flow and only
13846 * use the sample action instead of.
13848 if (num_of_dest > 1 &&
13849 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13851 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13853 for (i = 0; i < actions_n; i++) {
13854 if ((sample_act->dr_encap_action &&
13855 sample_act->dr_encap_action ==
13856 dev_flow->dv.actions[i]) ||
13857 (sample_act->dr_port_id_action &&
13858 sample_act->dr_port_id_action ==
13859 dev_flow->dv.actions[i]) ||
13860 (sample_act->dr_jump_action &&
13861 sample_act->dr_jump_action ==
13862 dev_flow->dv.actions[i]))
13864 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13866 memcpy((void *)dev_flow->dv.actions,
13867 (void *)temp_actions,
13868 tmp_actions_n * sizeof(void *));
13869 actions_n = tmp_actions_n;
13871 dev_flow->dv.actions_n = actions_n;
13872 dev_flow->act_flags = action_flags;
13873 if (wks->skip_matcher_reg)
13875 /* Register matcher. */
13876 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13877 matcher.mask.size);
13878 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13880 dev_flow->external);
13882 * When creating meter drop flow in drop table, using original
13883 * 5-tuple match, the matcher priority should be lower than
13886 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13887 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13888 matcher.priority <= MLX5_REG_BITS)
13889 matcher.priority += MLX5_REG_BITS;
13890 /* reserved field no needs to be set to 0 here. */
13891 tbl_key.is_fdb = attr->transfer;
13892 tbl_key.is_egress = attr->egress;
13893 tbl_key.level = dev_flow->dv.group;
13894 tbl_key.id = dev_flow->dv.table_id;
13895 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13896 tunnel, attr->group, error))
13902 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13905 * @param[in, out] action
13906 * Shred RSS action holding hash RX queue objects.
13907 * @param[in] hash_fields
13908 * Defines combination of packet fields to participate in RX hash.
13909 * @param[in] tunnel
13911 * @param[in] hrxq_idx
13912 * Hash RX queue index to set.
13915 * 0 on success, otherwise negative errno value.
13918 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13919 const uint64_t hash_fields,
13922 uint32_t *hrxqs = action->hrxq;
13924 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13925 case MLX5_RSS_HASH_IPV4:
13926 /* fall-through. */
13927 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13928 /* fall-through. */
13929 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13930 hrxqs[0] = hrxq_idx;
13932 case MLX5_RSS_HASH_IPV4_TCP:
13933 /* fall-through. */
13934 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13935 /* fall-through. */
13936 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13937 hrxqs[1] = hrxq_idx;
13939 case MLX5_RSS_HASH_IPV4_UDP:
13940 /* fall-through. */
13941 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13942 /* fall-through. */
13943 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13944 hrxqs[2] = hrxq_idx;
13946 case MLX5_RSS_HASH_IPV6:
13947 /* fall-through. */
13948 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13949 /* fall-through. */
13950 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13951 hrxqs[3] = hrxq_idx;
13953 case MLX5_RSS_HASH_IPV6_TCP:
13954 /* fall-through. */
13955 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13956 /* fall-through. */
13957 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13958 hrxqs[4] = hrxq_idx;
13960 case MLX5_RSS_HASH_IPV6_UDP:
13961 /* fall-through. */
13962 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13963 /* fall-through. */
13964 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13965 hrxqs[5] = hrxq_idx;
13967 case MLX5_RSS_HASH_NONE:
13968 hrxqs[6] = hrxq_idx;
13976 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13980 * Pointer to the Ethernet device structure.
13982 * Shared RSS action ID holding hash RX queue objects.
13983 * @param[in] hash_fields
13984 * Defines combination of packet fields to participate in RX hash.
13985 * @param[in] tunnel
13989 * Valid hash RX queue index, otherwise 0.
13992 flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13993 const uint64_t hash_fields)
13995 struct mlx5_priv *priv = dev->data->dev_private;
13996 struct mlx5_shared_action_rss *shared_rss =
13997 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13998 const uint32_t *hrxqs = shared_rss->hrxq;
14000 switch (hash_fields & ~IBV_RX_HASH_INNER) {
14001 case MLX5_RSS_HASH_IPV4:
14002 /* fall-through. */
14003 case MLX5_RSS_HASH_IPV4_DST_ONLY:
14004 /* fall-through. */
14005 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
14007 case MLX5_RSS_HASH_IPV4_TCP:
14008 /* fall-through. */
14009 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
14010 /* fall-through. */
14011 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
14013 case MLX5_RSS_HASH_IPV4_UDP:
14014 /* fall-through. */
14015 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
14016 /* fall-through. */
14017 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
14019 case MLX5_RSS_HASH_IPV6:
14020 /* fall-through. */
14021 case MLX5_RSS_HASH_IPV6_DST_ONLY:
14022 /* fall-through. */
14023 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
14025 case MLX5_RSS_HASH_IPV6_TCP:
14026 /* fall-through. */
14027 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
14028 /* fall-through. */
14029 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
14031 case MLX5_RSS_HASH_IPV6_UDP:
14032 /* fall-through. */
14033 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
14034 /* fall-through. */
14035 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
14037 case MLX5_RSS_HASH_NONE:
14046 * Apply the flow to the NIC, lock free,
14047 * (mutex should be acquired by caller).
14050 * Pointer to the Ethernet device structure.
14051 * @param[in, out] flow
14052 * Pointer to flow structure.
14053 * @param[out] error
14054 * Pointer to error structure.
14057 * 0 on success, a negative errno value otherwise and rte_errno is set.
14060 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
14061 struct rte_flow_error *error)
14063 struct mlx5_flow_dv_workspace *dv;
14064 struct mlx5_flow_handle *dh;
14065 struct mlx5_flow_handle_dv *dv_h;
14066 struct mlx5_flow *dev_flow;
14067 struct mlx5_priv *priv = dev->data->dev_private;
14068 uint32_t handle_idx;
14072 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
14073 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
14077 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
14078 dev_flow = &wks->flows[idx];
14079 dv = &dev_flow->dv;
14080 dh = dev_flow->handle;
14083 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
14084 if (dv->transfer) {
14085 MLX5_ASSERT(priv->sh->dr_drop_action);
14086 dv->actions[n++] = priv->sh->dr_drop_action;
14088 #ifdef HAVE_MLX5DV_DR
14089 /* DR supports drop action placeholder. */
14090 MLX5_ASSERT(priv->sh->dr_drop_action);
14091 dv->actions[n++] = dv->group ?
14092 priv->sh->dr_drop_action :
14093 priv->root_drop_action;
14095 /* For DV we use the explicit drop queue. */
14096 MLX5_ASSERT(priv->drop_queue.hrxq);
14098 priv->drop_queue.hrxq->action;
14101 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
14102 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
14103 struct mlx5_hrxq *hrxq;
14106 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
14111 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14112 "cannot get hash queue");
14115 dh->rix_hrxq = hrxq_idx;
14116 dv->actions[n++] = hrxq->action;
14117 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14118 struct mlx5_hrxq *hrxq = NULL;
14121 hrxq_idx = flow_dv_action_rss_hrxq_lookup(dev,
14122 rss_desc->shared_rss,
14123 dev_flow->hash_fields);
14125 hrxq = mlx5_ipool_get
14126 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
14131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14132 "cannot get hash queue");
14135 dh->rix_srss = rss_desc->shared_rss;
14136 dv->actions[n++] = hrxq->action;
14137 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
14138 if (!priv->sh->default_miss_action) {
14141 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14142 "default miss action not be created.");
14145 dv->actions[n++] = priv->sh->default_miss_action;
14147 misc_mask = flow_dv_matcher_enable(dv->value.buf);
14148 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
14149 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
14150 (void *)&dv->value, n,
14151 dv->actions, &dh->drv_flow);
14155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14157 (!priv->sh->config.allow_duplicate_pattern &&
14159 "duplicating pattern is not allowed" :
14160 "hardware refuses to create flow");
14163 if (priv->vmwa_context &&
14164 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14166 * The rule contains the VLAN pattern.
14167 * For VF we are going to create VLAN
14168 * interface to make hypervisor set correct
14169 * e-Switch vport context.
14171 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14176 err = rte_errno; /* Save rte_errno before cleanup. */
14177 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14178 handle_idx, dh, next) {
14179 /* hrxq is union, don't clear it if the flag is not set. */
14180 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14181 mlx5_hrxq_release(dev, dh->rix_hrxq);
14183 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14186 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14187 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14189 rte_errno = err; /* Restore rte_errno. */
14194 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14195 struct mlx5_list_entry *entry)
14197 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14201 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14202 mlx5_free(resource);
14206 * Release the flow matcher.
14209 * Pointer to Ethernet device.
14211 * Index to port ID action resource.
14214 * 1 while a reference on it exists, 0 when freed.
14217 flow_dv_matcher_release(struct rte_eth_dev *dev,
14218 struct mlx5_flow_handle *handle)
14220 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14221 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14222 typeof(*tbl), tbl);
14225 MLX5_ASSERT(matcher->matcher_object);
14226 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14227 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14232 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14234 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14235 struct mlx5_flow_dv_encap_decap_resource *res =
14236 container_of(entry, typeof(*res), entry);
14238 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14239 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14243 * Release an encap/decap resource.
14246 * Pointer to Ethernet device.
14247 * @param encap_decap_idx
14248 * Index of encap decap resource.
14251 * 1 while a reference on it exists, 0 when freed.
14254 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14255 uint32_t encap_decap_idx)
14257 struct mlx5_priv *priv = dev->data->dev_private;
14258 struct mlx5_flow_dv_encap_decap_resource *resource;
14260 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14264 MLX5_ASSERT(resource->action);
14265 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14269 * Release an jump to table action resource.
14272 * Pointer to Ethernet device.
14274 * Index to the jump action resource.
14277 * 1 while a reference on it exists, 0 when freed.
14280 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14283 struct mlx5_priv *priv = dev->data->dev_private;
14284 struct mlx5_flow_tbl_data_entry *tbl_data;
14286 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14290 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14294 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14296 struct mlx5_flow_dv_modify_hdr_resource *res =
14297 container_of(entry, typeof(*res), entry);
14298 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14300 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14301 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14305 * Release a modify-header resource.
14308 * Pointer to Ethernet device.
14310 * Pointer to mlx5_flow_handle.
14313 * 1 while a reference on it exists, 0 when freed.
14316 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14317 struct mlx5_flow_handle *handle)
14319 struct mlx5_priv *priv = dev->data->dev_private;
14320 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14322 MLX5_ASSERT(entry->action);
14323 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14327 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14329 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14330 struct mlx5_flow_dv_port_id_action_resource *resource =
14331 container_of(entry, typeof(*resource), entry);
14333 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14334 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14338 * Release port ID action resource.
14341 * Pointer to Ethernet device.
14343 * Pointer to mlx5_flow_handle.
14346 * 1 while a reference on it exists, 0 when freed.
14349 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14352 struct mlx5_priv *priv = dev->data->dev_private;
14353 struct mlx5_flow_dv_port_id_action_resource *resource;
14355 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14358 MLX5_ASSERT(resource->action);
14359 return mlx5_list_unregister(priv->sh->port_id_action_list,
14364 * Release shared RSS action resource.
14367 * Pointer to Ethernet device.
14369 * Shared RSS action index.
14372 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14374 struct mlx5_priv *priv = dev->data->dev_private;
14375 struct mlx5_shared_action_rss *shared_rss;
14377 shared_rss = mlx5_ipool_get
14378 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14379 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14383 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14385 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14386 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14387 container_of(entry, typeof(*resource), entry);
14389 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14390 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14394 * Release push vlan action resource.
14397 * Pointer to Ethernet device.
14399 * Pointer to mlx5_flow_handle.
14402 * 1 while a reference on it exists, 0 when freed.
14405 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14406 struct mlx5_flow_handle *handle)
14408 struct mlx5_priv *priv = dev->data->dev_private;
14409 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14410 uint32_t idx = handle->dvh.rix_push_vlan;
14412 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14415 MLX5_ASSERT(resource->action);
14416 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14421 * Release the fate resource.
14424 * Pointer to Ethernet device.
14426 * Pointer to mlx5_flow_handle.
14429 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14430 struct mlx5_flow_handle *handle)
14432 if (!handle->rix_fate)
14434 switch (handle->fate_action) {
14435 case MLX5_FLOW_FATE_QUEUE:
14436 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14437 mlx5_hrxq_release(dev, handle->rix_hrxq);
14439 case MLX5_FLOW_FATE_JUMP:
14440 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14442 case MLX5_FLOW_FATE_PORT_ID:
14443 flow_dv_port_id_action_resource_release(dev,
14444 handle->rix_port_id_action);
14447 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14450 handle->rix_fate = 0;
14454 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14455 struct mlx5_list_entry *entry)
14457 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14460 struct rte_eth_dev *dev = resource->dev;
14461 struct mlx5_priv *priv = dev->data->dev_private;
14463 if (resource->verbs_action)
14464 claim_zero(mlx5_flow_os_destroy_flow_action
14465 (resource->verbs_action));
14466 if (resource->normal_path_tbl)
14467 flow_dv_tbl_resource_release(MLX5_SH(dev),
14468 resource->normal_path_tbl);
14469 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14470 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14471 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14475 * Release an sample resource.
14478 * Pointer to Ethernet device.
14480 * Pointer to mlx5_flow_handle.
14483 * 1 while a reference on it exists, 0 when freed.
14486 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14487 struct mlx5_flow_handle *handle)
14489 struct mlx5_priv *priv = dev->data->dev_private;
14490 struct mlx5_flow_dv_sample_resource *resource;
14492 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14493 handle->dvh.rix_sample);
14496 MLX5_ASSERT(resource->verbs_action);
14497 return mlx5_list_unregister(priv->sh->sample_action_list,
14502 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14503 struct mlx5_list_entry *entry)
14505 struct mlx5_flow_dv_dest_array_resource *resource =
14506 container_of(entry, typeof(*resource), entry);
14507 struct rte_eth_dev *dev = resource->dev;
14508 struct mlx5_priv *priv = dev->data->dev_private;
14511 MLX5_ASSERT(resource->action);
14512 if (resource->action)
14513 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14514 for (; i < resource->num_of_dest; i++)
14515 flow_dv_sample_sub_actions_release(dev,
14516 &resource->sample_idx[i]);
14517 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14518 DRV_LOG(DEBUG, "destination array resource %p: removed",
14523 * Release an destination array resource.
14526 * Pointer to Ethernet device.
14528 * Pointer to mlx5_flow_handle.
14531 * 1 while a reference on it exists, 0 when freed.
14534 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14535 struct mlx5_flow_handle *handle)
14537 struct mlx5_priv *priv = dev->data->dev_private;
14538 struct mlx5_flow_dv_dest_array_resource *resource;
14540 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14541 handle->dvh.rix_dest_array);
14544 MLX5_ASSERT(resource->action);
14545 return mlx5_list_unregister(priv->sh->dest_array_list,
14550 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14552 struct mlx5_priv *priv = dev->data->dev_private;
14553 struct mlx5_dev_ctx_shared *sh = priv->sh;
14554 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14555 sh->geneve_tlv_option_resource;
14556 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14557 if (geneve_opt_resource) {
14558 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14559 __ATOMIC_RELAXED))) {
14560 claim_zero(mlx5_devx_cmd_destroy
14561 (geneve_opt_resource->obj));
14562 mlx5_free(sh->geneve_tlv_option_resource);
14563 sh->geneve_tlv_option_resource = NULL;
14566 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14570 * Remove the flow from the NIC but keeps it in memory.
14571 * Lock free, (mutex should be acquired by caller).
14574 * Pointer to Ethernet device.
14575 * @param[in, out] flow
14576 * Pointer to flow structure.
14579 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14581 struct mlx5_flow_handle *dh;
14582 uint32_t handle_idx;
14583 struct mlx5_priv *priv = dev->data->dev_private;
14587 handle_idx = flow->dev_handles;
14588 while (handle_idx) {
14589 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14593 if (dh->drv_flow) {
14594 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14595 dh->drv_flow = NULL;
14597 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14598 flow_dv_fate_resource_release(dev, dh);
14599 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14600 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14601 handle_idx = dh->next.next;
14606 * Remove the flow from the NIC and the memory.
14607 * Lock free, (mutex should be acquired by caller).
14610 * Pointer to the Ethernet device structure.
14611 * @param[in, out] flow
14612 * Pointer to flow structure.
14615 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14617 struct mlx5_flow_handle *dev_handle;
14618 struct mlx5_priv *priv = dev->data->dev_private;
14619 struct mlx5_flow_meter_info *fm = NULL;
14624 flow_dv_remove(dev, flow);
14625 if (flow->counter) {
14626 flow_dv_counter_free(dev, flow->counter);
14630 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14632 mlx5_flow_meter_detach(priv, fm);
14635 /* Keep the current age handling by default. */
14636 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14637 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14638 else if (flow->age)
14639 flow_dv_aso_age_release(dev, flow->age);
14640 if (flow->geneve_tlv_option) {
14641 flow_dv_geneve_tlv_option_resource_release(dev);
14642 flow->geneve_tlv_option = 0;
14644 while (flow->dev_handles) {
14645 uint32_t tmp_idx = flow->dev_handles;
14647 dev_handle = mlx5_ipool_get(priv->sh->ipool
14648 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14651 flow->dev_handles = dev_handle->next.next;
14652 while (dev_handle->flex_item) {
14653 int index = rte_bsf32(dev_handle->flex_item);
14655 mlx5_flex_release_index(dev, index);
14656 dev_handle->flex_item &= ~(uint8_t)RTE_BIT32(index);
14658 if (dev_handle->dvh.matcher)
14659 flow_dv_matcher_release(dev, dev_handle);
14660 if (dev_handle->dvh.rix_sample)
14661 flow_dv_sample_resource_release(dev, dev_handle);
14662 if (dev_handle->dvh.rix_dest_array)
14663 flow_dv_dest_array_resource_release(dev, dev_handle);
14664 if (dev_handle->dvh.rix_encap_decap)
14665 flow_dv_encap_decap_resource_release(dev,
14666 dev_handle->dvh.rix_encap_decap);
14667 if (dev_handle->dvh.modify_hdr)
14668 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14669 if (dev_handle->dvh.rix_push_vlan)
14670 flow_dv_push_vlan_action_resource_release(dev,
14672 if (dev_handle->dvh.rix_tag)
14673 flow_dv_tag_release(dev,
14674 dev_handle->dvh.rix_tag);
14675 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14676 flow_dv_fate_resource_release(dev, dev_handle);
14678 srss = dev_handle->rix_srss;
14679 if (fm && dev_handle->is_meter_flow_id &&
14680 dev_handle->split_flow_id)
14681 mlx5_ipool_free(fm->flow_ipool,
14682 dev_handle->split_flow_id);
14683 else if (dev_handle->split_flow_id &&
14684 !dev_handle->is_meter_flow_id)
14685 mlx5_ipool_free(priv->sh->ipool
14686 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14687 dev_handle->split_flow_id);
14688 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14692 flow_dv_shared_rss_action_release(dev, srss);
14696 * Release array of hash RX queue objects.
14700 * Pointer to the Ethernet device structure.
14701 * @param[in, out] hrxqs
14702 * Array of hash RX queue objects.
14705 * Total number of references to hash RX queue objects in *hrxqs* array
14706 * after this operation.
14709 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14710 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14715 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14716 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14726 * Release all hash RX queue objects representing shared RSS action.
14729 * Pointer to the Ethernet device structure.
14730 * @param[in, out] action
14731 * Shared RSS action to remove hash RX queue objects from.
14734 * Total number of references to hash RX queue objects stored in *action*
14735 * after this operation.
14736 * Expected to be 0 if no external references held.
14739 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14740 struct mlx5_shared_action_rss *shared_rss)
14742 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14746 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14749 * Only one hash value is available for one L3+L4 combination:
14751 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14752 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14753 * same slot in mlx5_rss_hash_fields.
14755 * @param[in] rss_types
14757 * @param[in, out] hash_field
14758 * hash_field variable needed to be adjusted.
14764 flow_dv_action_rss_l34_hash_adjust(uint64_t rss_types,
14765 uint64_t *hash_field)
14767 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14768 case MLX5_RSS_HASH_IPV4:
14769 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14770 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14771 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14772 *hash_field |= IBV_RX_HASH_DST_IPV4;
14773 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14774 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14776 *hash_field |= MLX5_RSS_HASH_IPV4;
14779 case MLX5_RSS_HASH_IPV6:
14780 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14781 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14782 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14783 *hash_field |= IBV_RX_HASH_DST_IPV6;
14784 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14785 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14787 *hash_field |= MLX5_RSS_HASH_IPV6;
14790 case MLX5_RSS_HASH_IPV4_UDP:
14791 /* fall-through. */
14792 case MLX5_RSS_HASH_IPV6_UDP:
14793 if (rss_types & RTE_ETH_RSS_UDP) {
14794 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14795 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14796 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14797 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14798 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14800 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14803 case MLX5_RSS_HASH_IPV4_TCP:
14804 /* fall-through. */
14805 case MLX5_RSS_HASH_IPV6_TCP:
14806 if (rss_types & RTE_ETH_RSS_TCP) {
14807 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14808 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14809 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14810 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14811 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14813 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14822 * Setup shared RSS action.
14823 * Prepare set of hash RX queue objects sufficient to handle all valid
14824 * hash_fields combinations (see enum ibv_rx_hash_fields).
14827 * Pointer to the Ethernet device structure.
14828 * @param[in] action_idx
14829 * Shared RSS action ipool index.
14830 * @param[in, out] action
14831 * Partially initialized shared RSS action.
14832 * @param[out] error
14833 * Perform verbose error reporting if not NULL. Initialized in case of
14837 * 0 on success, otherwise negative errno value.
14840 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14841 uint32_t action_idx,
14842 struct mlx5_shared_action_rss *shared_rss,
14843 struct rte_flow_error *error)
14845 struct mlx5_priv *priv = dev->data->dev_private;
14846 struct mlx5_flow_rss_desc rss_desc = { 0 };
14850 shared_rss->ind_tbl = mlx5_ind_table_obj_new
14851 (dev, shared_rss->origin.queue,
14852 shared_rss->origin.queue_num,
14854 !!dev->data->dev_started);
14855 if (!shared_rss->ind_tbl)
14856 return rte_flow_error_set(error, rte_errno,
14857 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14858 "cannot setup indirection table");
14859 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14860 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14861 rss_desc.const_q = shared_rss->origin.queue;
14862 rss_desc.queue_num = shared_rss->origin.queue_num;
14863 /* Set non-zero value to indicate a shared RSS. */
14864 rss_desc.shared_rss = action_idx;
14865 rss_desc.ind_tbl = shared_rss->ind_tbl;
14866 if (priv->sh->config.dv_flow_en == 2)
14867 rss_desc.hws_flags = MLX5DR_ACTION_FLAG_HWS_RX;
14868 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14869 struct mlx5_hrxq *hrxq;
14870 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14873 flow_dv_action_rss_l34_hash_adjust(shared_rss->origin.types,
14875 if (shared_rss->origin.level > 1) {
14876 hash_fields |= IBV_RX_HASH_INNER;
14879 rss_desc.tunnel = tunnel;
14880 rss_desc.hash_fields = hash_fields;
14881 hrxq = mlx5_hrxq_get(dev, &rss_desc);
14885 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14886 "cannot get hash queue");
14887 goto error_hrxq_new;
14889 err = __flow_dv_action_rss_hrxq_set
14890 (shared_rss, hash_fields, hrxq->idx);
14896 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14897 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
14898 shared_rss->ind_tbl = NULL;
14904 * Create shared RSS action.
14907 * Pointer to the Ethernet device structure.
14909 * Shared action configuration.
14911 * RSS action specification used to create shared action.
14912 * @param[out] error
14913 * Perform verbose error reporting if not NULL. Initialized in case of
14917 * A valid shared action ID in case of success, 0 otherwise and
14918 * rte_errno is set.
14921 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14922 const struct rte_flow_indir_action_conf *conf,
14923 const struct rte_flow_action_rss *rss,
14924 struct rte_flow_error *error)
14926 struct mlx5_priv *priv = dev->data->dev_private;
14927 struct mlx5_shared_action_rss *shared_rss = NULL;
14928 struct rte_flow_action_rss *origin;
14929 const uint8_t *rss_key;
14932 RTE_SET_USED(conf);
14933 shared_rss = mlx5_ipool_zmalloc
14934 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14936 rte_flow_error_set(error, ENOMEM,
14937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14938 "cannot allocate resource memory");
14939 goto error_rss_init;
14941 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14942 rte_flow_error_set(error, E2BIG,
14943 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14944 "rss action number out of range");
14945 goto error_rss_init;
14947 origin = &shared_rss->origin;
14948 origin->func = rss->func;
14949 origin->level = rss->level;
14950 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14951 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14952 /* NULL RSS key indicates default RSS key. */
14953 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14954 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14955 origin->key = &shared_rss->key[0];
14956 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14957 origin->queue = rss->queue;
14958 origin->queue_num = rss->queue_num;
14959 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14960 goto error_rss_init;
14961 /* Update queue with indirect table queue memoyr. */
14962 origin->queue = shared_rss->ind_tbl->queues;
14963 rte_spinlock_init(&shared_rss->action_rss_sl);
14964 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14965 rte_spinlock_lock(&priv->shared_act_sl);
14966 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14967 &priv->rss_shared_actions, idx, shared_rss, next);
14968 rte_spinlock_unlock(&priv->shared_act_sl);
14972 if (shared_rss->ind_tbl)
14973 mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
14974 !!dev->data->dev_started);
14975 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14982 * Destroy the shared RSS action.
14983 * Release related hash RX queue objects.
14986 * Pointer to the Ethernet device structure.
14988 * The shared RSS action object ID to be removed.
14989 * @param[out] error
14990 * Perform verbose error reporting if not NULL. Initialized in case of
14994 * 0 on success, otherwise negative errno value.
14997 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14998 struct rte_flow_error *error)
15000 struct mlx5_priv *priv = dev->data->dev_private;
15001 struct mlx5_shared_action_rss *shared_rss =
15002 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15003 uint32_t old_refcnt = 1;
15007 return rte_flow_error_set(error, EINVAL,
15008 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15009 "invalid shared action");
15010 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
15011 0, 0, __ATOMIC_ACQUIRE,
15013 return rte_flow_error_set(error, EBUSY,
15014 RTE_FLOW_ERROR_TYPE_ACTION,
15016 "shared rss has references");
15017 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
15019 return rte_flow_error_set(error, EBUSY,
15020 RTE_FLOW_ERROR_TYPE_ACTION,
15022 "shared rss hrxq has references");
15023 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl,
15024 !!dev->data->dev_started);
15026 return rte_flow_error_set(error, EBUSY,
15027 RTE_FLOW_ERROR_TYPE_ACTION,
15029 "shared rss indirection table has"
15031 rte_spinlock_lock(&priv->shared_act_sl);
15032 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15033 &priv->rss_shared_actions, idx, shared_rss, next);
15034 rte_spinlock_unlock(&priv->shared_act_sl);
15035 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
15041 * Create indirect action, lock free,
15042 * (mutex should be acquired by caller).
15043 * Dispatcher for action type specific call.
15046 * Pointer to the Ethernet device structure.
15048 * Shared action configuration.
15049 * @param[in] action
15050 * Action specification used to create indirect action.
15051 * @param[out] error
15052 * Perform verbose error reporting if not NULL. Initialized in case of
15056 * A valid shared action handle in case of success, NULL otherwise and
15057 * rte_errno is set.
15059 struct rte_flow_action_handle *
15060 flow_dv_action_create(struct rte_eth_dev *dev,
15061 const struct rte_flow_indir_action_conf *conf,
15062 const struct rte_flow_action *action,
15063 struct rte_flow_error *err)
15065 struct mlx5_priv *priv = dev->data->dev_private;
15066 uint32_t age_idx = 0;
15070 switch (action->type) {
15071 case RTE_FLOW_ACTION_TYPE_RSS:
15072 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
15073 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
15074 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15076 case RTE_FLOW_ACTION_TYPE_AGE:
15077 age_idx = flow_dv_aso_age_alloc(dev, err);
15082 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
15083 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
15084 flow_dv_aso_age_params_init(dev, age_idx,
15085 ((const struct rte_flow_action_age *)
15086 action->conf)->context ?
15087 ((const struct rte_flow_action_age *)
15088 action->conf)->context :
15089 (void *)(uintptr_t)idx,
15090 ((const struct rte_flow_action_age *)
15091 action->conf)->timeout);
15094 case RTE_FLOW_ACTION_TYPE_COUNT:
15095 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
15096 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
15097 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
15099 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
15100 ret = flow_dv_translate_create_conntrack(dev, action->conf,
15102 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
15105 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
15106 NULL, "action type not supported");
15109 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
15113 * Destroy the indirect action.
15114 * Release action related resources on the NIC and the memory.
15115 * Lock free, (mutex should be acquired by caller).
15116 * Dispatcher for action type specific call.
15119 * Pointer to the Ethernet device structure.
15120 * @param[in] handle
15121 * The indirect action object handle to be removed.
15122 * @param[out] error
15123 * Perform verbose error reporting if not NULL. Initialized in case of
15127 * 0 on success, otherwise negative errno value.
15130 flow_dv_action_destroy(struct rte_eth_dev *dev,
15131 struct rte_flow_action_handle *handle,
15132 struct rte_flow_error *error)
15134 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15135 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15136 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15137 struct mlx5_flow_counter *cnt;
15138 uint32_t no_flow_refcnt = 1;
15142 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15143 return __flow_dv_action_rss_release(dev, idx, error);
15144 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15145 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15146 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15147 &no_flow_refcnt, 1, false,
15150 return rte_flow_error_set(error, EBUSY,
15151 RTE_FLOW_ERROR_TYPE_ACTION,
15153 "Indirect count action has references");
15154 flow_dv_counter_free(dev, idx);
15156 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15157 ret = flow_dv_aso_age_release(dev, idx);
15160 * In this case, the last flow has a reference will
15161 * actually release the age action.
15163 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15164 " released with references %d.", idx, ret);
15166 case MLX5_INDIRECT_ACTION_TYPE_CT:
15167 ret = flow_dv_aso_ct_release(dev, idx, error);
15171 DRV_LOG(DEBUG, "Connection tracking object %u still "
15172 "has references %d.", idx, ret);
15175 return rte_flow_error_set(error, ENOTSUP,
15176 RTE_FLOW_ERROR_TYPE_ACTION,
15178 "action type not supported");
15183 * Updates in place shared RSS action configuration.
15186 * Pointer to the Ethernet device structure.
15188 * The shared RSS action object ID to be updated.
15189 * @param[in] action_conf
15190 * RSS action specification used to modify *shared_rss*.
15191 * @param[out] error
15192 * Perform verbose error reporting if not NULL. Initialized in case of
15196 * 0 on success, otherwise negative errno value.
15197 * @note: currently only support update of RSS queues.
15200 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15201 const struct rte_flow_action_rss *action_conf,
15202 struct rte_flow_error *error)
15204 struct mlx5_priv *priv = dev->data->dev_private;
15205 struct mlx5_shared_action_rss *shared_rss =
15206 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15208 void *queue = NULL;
15209 void *queue_i = NULL;
15210 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15211 bool dev_started = !!dev->data->dev_started;
15214 return rte_flow_error_set(error, EINVAL,
15215 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15216 "invalid shared action to update");
15217 if (priv->obj_ops.ind_table_modify == NULL)
15218 return rte_flow_error_set(error, ENOTSUP,
15219 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15220 "cannot modify indirection table");
15221 queue = mlx5_malloc(MLX5_MEM_ZERO,
15222 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15225 return rte_flow_error_set(error, ENOMEM,
15226 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15228 "cannot allocate resource memory");
15229 memcpy(queue, action_conf->queue, queue_size);
15230 MLX5_ASSERT(shared_rss->ind_tbl);
15231 rte_spinlock_lock(&shared_rss->action_rss_sl);
15232 queue_i = shared_rss->ind_tbl->queues;
15233 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15234 queue, action_conf->queue_num,
15235 true /* standalone */,
15236 dev_started /* ref_new_qs */,
15237 dev_started /* deref_old_qs */);
15239 ret = rte_flow_error_set(error, rte_errno,
15240 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15241 "cannot update indirection table");
15243 /* Restore the queue to indirect table internal queue. */
15244 memcpy(queue_i, queue, queue_size);
15245 shared_rss->ind_tbl->queues = queue_i;
15246 shared_rss->origin.queue_num = action_conf->queue_num;
15249 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15254 * Updates in place conntrack context or direction.
15255 * Context update should be synchronized.
15258 * Pointer to the Ethernet device structure.
15260 * The conntrack object ID to be updated.
15261 * @param[in] update
15262 * Pointer to the structure of information to update.
15263 * @param[out] error
15264 * Perform verbose error reporting if not NULL. Initialized in case of
15268 * 0 on success, otherwise negative errno value.
15271 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15272 const struct rte_flow_modify_conntrack *update,
15273 struct rte_flow_error *error)
15275 struct mlx5_priv *priv = dev->data->dev_private;
15276 struct mlx5_aso_ct_action *ct;
15277 const struct rte_flow_action_conntrack *new_prf;
15279 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15282 if (PORT_ID(priv) != owner)
15283 return rte_flow_error_set(error, EACCES,
15284 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15286 "CT object owned by another port");
15287 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15288 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15290 return rte_flow_error_set(error, ENOMEM,
15291 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15293 "CT object is inactive");
15294 new_prf = &update->new_ct;
15295 if (update->direction)
15296 ct->is_original = !!new_prf->is_original_dir;
15297 if (update->state) {
15298 /* Only validate the profile when it needs to be updated. */
15299 ret = mlx5_validate_action_ct(dev, new_prf, error);
15302 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15304 return rte_flow_error_set(error, EIO,
15305 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15307 "Failed to send CT context update WQE");
15308 /* Block until ready or a failure. */
15309 ret = mlx5_aso_ct_available(priv->sh, ct);
15311 rte_flow_error_set(error, rte_errno,
15312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15314 "Timeout to get the CT update");
15320 * Updates in place shared action configuration, lock free,
15321 * (mutex should be acquired by caller).
15324 * Pointer to the Ethernet device structure.
15325 * @param[in] handle
15326 * The indirect action object handle to be updated.
15327 * @param[in] update
15328 * Action specification used to modify the action pointed by *handle*.
15329 * *update* could be of same type with the action pointed by the *handle*
15330 * handle argument, or some other structures like a wrapper, depending on
15331 * the indirect action type.
15332 * @param[out] error
15333 * Perform verbose error reporting if not NULL. Initialized in case of
15337 * 0 on success, otherwise negative errno value.
15340 flow_dv_action_update(struct rte_eth_dev *dev,
15341 struct rte_flow_action_handle *handle,
15342 const void *update,
15343 struct rte_flow_error *err)
15345 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15346 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15347 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15348 const void *action_conf;
15351 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15352 action_conf = ((const struct rte_flow_action *)update)->conf;
15353 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15354 case MLX5_INDIRECT_ACTION_TYPE_CT:
15355 return __flow_dv_action_ct_update(dev, idx, update, err);
15357 return rte_flow_error_set(err, ENOTSUP,
15358 RTE_FLOW_ERROR_TYPE_ACTION,
15360 "action type update not supported");
15365 * Destroy the meter sub policy table rules.
15366 * Lock free, (mutex should be acquired by caller).
15369 * Pointer to Ethernet device.
15370 * @param[in] sub_policy
15371 * Pointer to meter sub policy table.
15374 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15375 struct mlx5_flow_meter_sub_policy *sub_policy)
15377 struct mlx5_priv *priv = dev->data->dev_private;
15378 struct mlx5_flow_tbl_data_entry *tbl;
15379 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15380 struct mlx5_flow_meter_info *next_fm;
15381 struct mlx5_sub_policy_color_rule *color_rule;
15385 for (i = 0; i < RTE_COLORS; i++) {
15387 if (i == RTE_COLOR_GREEN && policy &&
15388 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15389 next_fm = mlx5_flow_meter_find(priv,
15390 policy->act_cnt[i].next_mtr_id, NULL);
15391 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15393 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15394 tbl = container_of(color_rule->matcher->tbl,
15395 typeof(*tbl), tbl);
15396 mlx5_list_unregister(tbl->matchers,
15397 &color_rule->matcher->entry);
15398 TAILQ_REMOVE(&sub_policy->color_rules[i],
15399 color_rule, next_port);
15400 mlx5_free(color_rule);
15402 mlx5_flow_meter_detach(priv, next_fm);
15405 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15406 if (sub_policy->rix_hrxq[i]) {
15407 if (policy && !policy->is_hierarchy)
15408 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15409 sub_policy->rix_hrxq[i] = 0;
15411 if (sub_policy->jump_tbl[i]) {
15412 flow_dv_tbl_resource_release(MLX5_SH(dev),
15413 sub_policy->jump_tbl[i]);
15414 sub_policy->jump_tbl[i] = NULL;
15417 if (sub_policy->tbl_rsc) {
15418 flow_dv_tbl_resource_release(MLX5_SH(dev),
15419 sub_policy->tbl_rsc);
15420 sub_policy->tbl_rsc = NULL;
15425 * Destroy policy rules, lock free,
15426 * (mutex should be acquired by caller).
15427 * Dispatcher for action type specific call.
15430 * Pointer to the Ethernet device structure.
15431 * @param[in] mtr_policy
15432 * Meter policy struct.
15435 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15436 struct mlx5_flow_meter_policy *mtr_policy)
15439 struct mlx5_flow_meter_sub_policy *sub_policy;
15440 uint16_t sub_policy_num;
15442 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15443 sub_policy_num = (mtr_policy->sub_policy_num >>
15444 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15445 MLX5_MTR_SUB_POLICY_NUM_MASK;
15446 for (j = 0; j < sub_policy_num; j++) {
15447 sub_policy = mtr_policy->sub_policys[i][j];
15449 __flow_dv_destroy_sub_policy_rules(dev,
15456 * Destroy policy action, lock free,
15457 * (mutex should be acquired by caller).
15458 * Dispatcher for action type specific call.
15461 * Pointer to the Ethernet device structure.
15462 * @param[in] mtr_policy
15463 * Meter policy struct.
15466 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15467 struct mlx5_flow_meter_policy *mtr_policy)
15469 struct rte_flow_action *rss_action;
15470 struct mlx5_flow_handle dev_handle;
15473 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15474 if (mtr_policy->act_cnt[i].rix_mark) {
15475 flow_dv_tag_release(dev,
15476 mtr_policy->act_cnt[i].rix_mark);
15477 mtr_policy->act_cnt[i].rix_mark = 0;
15479 if (mtr_policy->act_cnt[i].modify_hdr) {
15480 dev_handle.dvh.modify_hdr =
15481 mtr_policy->act_cnt[i].modify_hdr;
15482 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15484 switch (mtr_policy->act_cnt[i].fate_action) {
15485 case MLX5_FLOW_FATE_SHARED_RSS:
15486 rss_action = mtr_policy->act_cnt[i].rss;
15487 mlx5_free(rss_action);
15489 case MLX5_FLOW_FATE_PORT_ID:
15490 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15491 flow_dv_port_id_action_resource_release(dev,
15492 mtr_policy->act_cnt[i].rix_port_id_action);
15493 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15496 case MLX5_FLOW_FATE_DROP:
15497 case MLX5_FLOW_FATE_JUMP:
15498 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15499 mtr_policy->act_cnt[i].dr_jump_action[j] =
15503 /*Queue action do nothing*/
15507 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15508 mtr_policy->dr_drop_action[j] = NULL;
15512 * Create policy action per domain, lock free,
15513 * (mutex should be acquired by caller).
15514 * Dispatcher for action type specific call.
15517 * Pointer to the Ethernet device structure.
15518 * @param[in] mtr_policy
15519 * Meter policy struct.
15520 * @param[in] action
15521 * Action specification used to create meter actions.
15522 * @param[out] error
15523 * Perform verbose error reporting if not NULL. Initialized in case of
15527 * 0 on success, otherwise negative errno value.
15530 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15531 struct mlx5_flow_meter_policy *mtr_policy,
15532 const struct rte_flow_action *actions[RTE_COLORS],
15533 enum mlx5_meter_domain domain,
15534 struct rte_mtr_error *error)
15536 struct mlx5_priv *priv = dev->data->dev_private;
15537 struct rte_flow_error flow_err;
15538 const struct rte_flow_action *act;
15539 uint64_t action_flags;
15540 struct mlx5_flow_handle dh;
15541 struct mlx5_flow dev_flow;
15542 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15544 uint8_t egress, transfer;
15545 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15547 struct mlx5_flow_dv_modify_hdr_resource res;
15548 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15549 sizeof(struct mlx5_modification_cmd) *
15550 (MLX5_MAX_MODIFY_NUM + 1)];
15552 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15553 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
15556 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15557 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15558 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15559 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15560 memset(&port_id_action, 0,
15561 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15562 memset(mhdr_res, 0, sizeof(*mhdr_res));
15563 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15564 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15565 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15566 dev_flow.handle = &dh;
15567 dev_flow.dv.port_id_action = &port_id_action;
15568 dev_flow.external = true;
15569 for (i = 0; i < RTE_COLORS; i++) {
15570 if (i < MLX5_MTR_RTE_COLORS)
15571 act_cnt = &mtr_policy->act_cnt[i];
15572 /* Skip the color policy actions creation. */
15573 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15574 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15577 for (act = actions[i];
15578 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15579 switch (act->type) {
15580 case RTE_FLOW_ACTION_TYPE_MARK:
15582 uint32_t tag_be = mlx5_flow_mark_set
15583 (((const struct rte_flow_action_mark *)
15586 if (i >= MLX5_MTR_RTE_COLORS)
15587 return -rte_mtr_error_set(error,
15589 RTE_MTR_ERROR_TYPE_METER_POLICY,
15591 "cannot create policy "
15592 "mark action for this color");
15594 if (flow_dv_tag_resource_register(dev, tag_be,
15595 &dev_flow, &flow_err))
15596 return -rte_mtr_error_set(error,
15598 RTE_MTR_ERROR_TYPE_METER_POLICY,
15600 "cannot setup policy mark action");
15601 MLX5_ASSERT(dev_flow.dv.tag_resource);
15602 act_cnt->rix_mark =
15603 dev_flow.handle->dvh.rix_tag;
15604 action_flags |= MLX5_FLOW_ACTION_MARK;
15607 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15608 if (i >= MLX5_MTR_RTE_COLORS)
15609 return -rte_mtr_error_set(error,
15611 RTE_MTR_ERROR_TYPE_METER_POLICY,
15613 "cannot create policy "
15614 "set tag action for this color");
15615 if (flow_dv_convert_action_set_tag
15617 (const struct rte_flow_action_set_tag *)
15618 act->conf, &flow_err))
15619 return -rte_mtr_error_set(error,
15621 RTE_MTR_ERROR_TYPE_METER_POLICY,
15622 NULL, "cannot convert policy "
15624 if (!mhdr_res->actions_num)
15625 return -rte_mtr_error_set(error,
15627 RTE_MTR_ERROR_TYPE_METER_POLICY,
15628 NULL, "cannot find policy "
15630 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15632 case RTE_FLOW_ACTION_TYPE_DROP:
15634 struct mlx5_flow_mtr_mng *mtrmng =
15636 struct mlx5_flow_tbl_data_entry *tbl_data;
15639 * Create the drop table with
15640 * METER DROP level.
15642 if (!mtrmng->drop_tbl[domain]) {
15643 mtrmng->drop_tbl[domain] =
15644 flow_dv_tbl_resource_get(dev,
15645 MLX5_FLOW_TABLE_LEVEL_METER,
15646 egress, transfer, false, NULL, 0,
15647 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15648 if (!mtrmng->drop_tbl[domain])
15649 return -rte_mtr_error_set
15651 RTE_MTR_ERROR_TYPE_METER_POLICY,
15653 "Failed to create meter drop table");
15655 tbl_data = container_of
15656 (mtrmng->drop_tbl[domain],
15657 struct mlx5_flow_tbl_data_entry, tbl);
15658 if (i < MLX5_MTR_RTE_COLORS) {
15659 act_cnt->dr_jump_action[domain] =
15660 tbl_data->jump.action;
15661 act_cnt->fate_action =
15662 MLX5_FLOW_FATE_DROP;
15664 if (i == RTE_COLOR_RED)
15665 mtr_policy->dr_drop_action[domain] =
15666 tbl_data->jump.action;
15667 action_flags |= MLX5_FLOW_ACTION_DROP;
15670 case RTE_FLOW_ACTION_TYPE_QUEUE:
15672 if (i >= MLX5_MTR_RTE_COLORS)
15673 return -rte_mtr_error_set(error,
15675 RTE_MTR_ERROR_TYPE_METER_POLICY,
15676 NULL, "cannot create policy "
15677 "fate queue for this color");
15679 ((const struct rte_flow_action_queue *)
15680 (act->conf))->index;
15681 act_cnt->fate_action =
15682 MLX5_FLOW_FATE_QUEUE;
15683 dev_flow.handle->fate_action =
15684 MLX5_FLOW_FATE_QUEUE;
15685 mtr_policy->is_queue = 1;
15686 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15689 case RTE_FLOW_ACTION_TYPE_RSS:
15693 if (i >= MLX5_MTR_RTE_COLORS)
15694 return -rte_mtr_error_set(error,
15696 RTE_MTR_ERROR_TYPE_METER_POLICY,
15698 "cannot create policy "
15699 "rss action for this color");
15701 * Save RSS conf into policy struct
15702 * for translate stage.
15704 rss_size = (int)rte_flow_conv
15705 (RTE_FLOW_CONV_OP_ACTION,
15706 NULL, 0, act, &flow_err);
15708 return -rte_mtr_error_set(error,
15710 RTE_MTR_ERROR_TYPE_METER_POLICY,
15711 NULL, "Get the wrong "
15712 "rss action struct size");
15713 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15714 rss_size, 0, SOCKET_ID_ANY);
15716 return -rte_mtr_error_set(error,
15718 RTE_MTR_ERROR_TYPE_METER_POLICY,
15720 "Fail to malloc rss action memory");
15721 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15722 act_cnt->rss, rss_size,
15725 return -rte_mtr_error_set(error,
15727 RTE_MTR_ERROR_TYPE_METER_POLICY,
15728 NULL, "Fail to save "
15729 "rss action into policy struct");
15730 act_cnt->fate_action =
15731 MLX5_FLOW_FATE_SHARED_RSS;
15732 action_flags |= MLX5_FLOW_ACTION_RSS;
15735 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15736 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15738 struct mlx5_flow_dv_port_id_action_resource
15740 uint32_t port_id = 0;
15742 if (i >= MLX5_MTR_RTE_COLORS)
15743 return -rte_mtr_error_set(error,
15745 RTE_MTR_ERROR_TYPE_METER_POLICY,
15746 NULL, "cannot create policy "
15747 "port action for this color");
15748 memset(&port_id_resource, 0,
15749 sizeof(port_id_resource));
15750 if (flow_dv_translate_action_port_id(dev, act,
15751 &port_id, &flow_err))
15752 return -rte_mtr_error_set(error,
15754 RTE_MTR_ERROR_TYPE_METER_POLICY,
15755 NULL, "cannot translate "
15756 "policy port action");
15757 port_id_resource.port_id = port_id;
15758 if (flow_dv_port_id_action_resource_register
15759 (dev, &port_id_resource,
15760 &dev_flow, &flow_err))
15761 return -rte_mtr_error_set(error,
15763 RTE_MTR_ERROR_TYPE_METER_POLICY,
15764 NULL, "cannot setup "
15765 "policy port action");
15766 act_cnt->rix_port_id_action =
15767 dev_flow.handle->rix_port_id_action;
15768 act_cnt->fate_action =
15769 MLX5_FLOW_FATE_PORT_ID;
15770 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15773 case RTE_FLOW_ACTION_TYPE_JUMP:
15775 uint32_t jump_group = 0;
15776 uint32_t table = 0;
15777 struct mlx5_flow_tbl_data_entry *tbl_data;
15778 struct flow_grp_info grp_info = {
15779 .external = !!dev_flow.external,
15780 .transfer = !!transfer,
15781 .fdb_def_rule = !!priv->fdb_def_rule,
15783 .skip_scale = dev_flow.skip_scale &
15784 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15786 struct mlx5_flow_meter_sub_policy *sub_policy =
15787 mtr_policy->sub_policys[domain][0];
15789 if (i >= MLX5_MTR_RTE_COLORS)
15790 return -rte_mtr_error_set(error,
15792 RTE_MTR_ERROR_TYPE_METER_POLICY,
15794 "cannot create policy "
15795 "jump action for this color");
15797 ((const struct rte_flow_action_jump *)
15799 if (mlx5_flow_group_to_table(dev, NULL,
15802 &grp_info, &flow_err))
15803 return -rte_mtr_error_set(error,
15805 RTE_MTR_ERROR_TYPE_METER_POLICY,
15806 NULL, "cannot setup "
15807 "policy jump action");
15808 sub_policy->jump_tbl[i] =
15809 flow_dv_tbl_resource_get(dev,
15812 !!dev_flow.external,
15813 NULL, jump_group, 0,
15816 (!sub_policy->jump_tbl[i])
15817 return -rte_mtr_error_set(error,
15819 RTE_MTR_ERROR_TYPE_METER_POLICY,
15820 NULL, "cannot create jump action.");
15821 tbl_data = container_of
15822 (sub_policy->jump_tbl[i],
15823 struct mlx5_flow_tbl_data_entry, tbl);
15824 act_cnt->dr_jump_action[domain] =
15825 tbl_data->jump.action;
15826 act_cnt->fate_action =
15827 MLX5_FLOW_FATE_JUMP;
15828 action_flags |= MLX5_FLOW_ACTION_JUMP;
15832 * No need to check meter hierarchy for Y or R colors
15833 * here since it is done in the validation stage.
15835 case RTE_FLOW_ACTION_TYPE_METER:
15837 const struct rte_flow_action_meter *mtr;
15838 struct mlx5_flow_meter_info *next_fm;
15839 struct mlx5_flow_meter_policy *next_policy;
15840 struct rte_flow_action tag_action;
15841 struct mlx5_rte_flow_action_set_tag set_tag;
15842 uint32_t next_mtr_idx = 0;
15845 next_fm = mlx5_flow_meter_find(priv,
15849 return -rte_mtr_error_set(error, EINVAL,
15850 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15851 "Fail to find next meter.");
15852 if (next_fm->def_policy)
15853 return -rte_mtr_error_set(error, EINVAL,
15854 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15855 "Hierarchy only supports termination meter.");
15856 next_policy = mlx5_flow_meter_policy_find(dev,
15857 next_fm->policy_id, NULL);
15858 MLX5_ASSERT(next_policy);
15859 if (next_fm->drop_cnt) {
15862 mlx5_flow_get_reg_id(dev,
15865 (struct rte_flow_error *)error);
15866 set_tag.offset = (priv->mtr_reg_share ?
15867 MLX5_MTR_COLOR_BITS : 0);
15868 set_tag.length = (priv->mtr_reg_share ?
15869 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15871 set_tag.data = next_mtr_idx;
15873 (enum rte_flow_action_type)
15874 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15875 tag_action.conf = &set_tag;
15876 if (flow_dv_convert_action_set_reg
15877 (mhdr_res, &tag_action,
15878 (struct rte_flow_error *)error))
15881 MLX5_FLOW_ACTION_SET_TAG;
15883 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15884 act_cnt->next_mtr_id = next_fm->meter_id;
15885 act_cnt->next_sub_policy = NULL;
15886 mtr_policy->is_hierarchy = 1;
15887 mtr_policy->dev = next_policy->dev;
15889 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15893 return -rte_mtr_error_set(error, ENOTSUP,
15894 RTE_MTR_ERROR_TYPE_METER_POLICY,
15895 NULL, "action type not supported");
15897 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15898 /* create modify action if needed. */
15899 dev_flow.dv.group = 1;
15900 if (flow_dv_modify_hdr_resource_register
15901 (dev, mhdr_res, &dev_flow, &flow_err))
15902 return -rte_mtr_error_set(error,
15904 RTE_MTR_ERROR_TYPE_METER_POLICY,
15905 NULL, "cannot register policy "
15907 act_cnt->modify_hdr =
15908 dev_flow.handle->dvh.modify_hdr;
15916 * Create policy action per domain, lock free,
15917 * (mutex should be acquired by caller).
15918 * Dispatcher for action type specific call.
15921 * Pointer to the Ethernet device structure.
15922 * @param[in] mtr_policy
15923 * Meter policy struct.
15924 * @param[in] action
15925 * Action specification used to create meter actions.
15926 * @param[out] error
15927 * Perform verbose error reporting if not NULL. Initialized in case of
15931 * 0 on success, otherwise negative errno value.
15934 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15935 struct mlx5_flow_meter_policy *mtr_policy,
15936 const struct rte_flow_action *actions[RTE_COLORS],
15937 struct rte_mtr_error *error)
15940 uint16_t sub_policy_num;
15942 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15943 sub_policy_num = (mtr_policy->sub_policy_num >>
15944 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15945 MLX5_MTR_SUB_POLICY_NUM_MASK;
15946 if (sub_policy_num) {
15947 ret = __flow_dv_create_domain_policy_acts(dev,
15948 mtr_policy, actions,
15949 (enum mlx5_meter_domain)i, error);
15950 /* Cleaning resource is done in the caller level. */
15959 * Query a DV flow rule for its statistics via DevX.
15962 * Pointer to Ethernet device.
15963 * @param[in] cnt_idx
15964 * Index to the flow counter.
15966 * Data retrieved by the query.
15967 * @param[out] error
15968 * Perform verbose error reporting if not NULL.
15971 * 0 on success, a negative errno value otherwise and rte_errno is set.
15974 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15975 struct rte_flow_error *error)
15977 struct mlx5_priv *priv = dev->data->dev_private;
15978 struct rte_flow_query_count *qc = data;
15980 if (!priv->sh->cdev->config.devx)
15981 return rte_flow_error_set(error, ENOTSUP,
15982 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15984 "counters are not supported");
15986 uint64_t pkts, bytes;
15987 struct mlx5_flow_counter *cnt;
15988 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15991 return rte_flow_error_set(error, -err,
15992 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15993 NULL, "cannot read counters");
15994 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15997 qc->hits = pkts - cnt->hits;
15998 qc->bytes = bytes - cnt->bytes;
16001 cnt->bytes = bytes;
16005 return rte_flow_error_set(error, EINVAL,
16006 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16008 "counters are not available");
16012 flow_dv_action_query(struct rte_eth_dev *dev,
16013 const struct rte_flow_action_handle *handle, void *data,
16014 struct rte_flow_error *error)
16016 struct mlx5_age_param *age_param;
16017 struct rte_flow_query_age *resp;
16018 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
16019 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
16020 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
16021 struct mlx5_priv *priv = dev->data->dev_private;
16022 struct mlx5_aso_ct_action *ct;
16027 case MLX5_INDIRECT_ACTION_TYPE_AGE:
16028 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
16030 resp->aged = __atomic_load_n(&age_param->state,
16031 __ATOMIC_RELAXED) == AGE_TMOUT ?
16033 resp->sec_since_last_hit_valid = !resp->aged;
16034 if (resp->sec_since_last_hit_valid)
16035 resp->sec_since_last_hit = __atomic_load_n
16036 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16038 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
16039 return flow_dv_query_count(dev, idx, data, error);
16040 case MLX5_INDIRECT_ACTION_TYPE_CT:
16041 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
16042 if (owner != PORT_ID(priv))
16043 return rte_flow_error_set(error, EACCES,
16044 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16046 "CT object owned by another port");
16047 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
16048 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
16051 return rte_flow_error_set(error, EFAULT,
16052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16054 "CT object is inactive");
16055 ((struct rte_flow_action_conntrack *)data)->peer_port =
16057 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
16059 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
16060 return rte_flow_error_set(error, EIO,
16061 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16063 "Failed to query CT context");
16066 return rte_flow_error_set(error, ENOTSUP,
16067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
16068 "action type query not supported");
16073 * Query a flow rule AGE action for aging information.
16076 * Pointer to Ethernet device.
16078 * Pointer to the sub flow.
16080 * data retrieved by the query.
16081 * @param[out] error
16082 * Perform verbose error reporting if not NULL.
16085 * 0 on success, a negative errno value otherwise and rte_errno is set.
16088 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
16089 void *data, struct rte_flow_error *error)
16091 struct rte_flow_query_age *resp = data;
16092 struct mlx5_age_param *age_param;
16095 struct mlx5_aso_age_action *act =
16096 flow_aso_age_get_by_idx(dev, flow->age);
16098 age_param = &act->age_params;
16099 } else if (flow->counter) {
16100 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16102 if (!age_param || !age_param->timeout)
16103 return rte_flow_error_set
16105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16106 NULL, "cannot read age data");
16108 return rte_flow_error_set(error, EINVAL,
16109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16110 NULL, "age data not available");
16112 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16114 resp->sec_since_last_hit_valid = !resp->aged;
16115 if (resp->sec_since_last_hit_valid)
16116 resp->sec_since_last_hit = __atomic_load_n
16117 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16124 * @see rte_flow_query()
16125 * @see rte_flow_ops
16128 flow_dv_query(struct rte_eth_dev *dev,
16129 struct rte_flow *flow __rte_unused,
16130 const struct rte_flow_action *actions __rte_unused,
16131 void *data __rte_unused,
16132 struct rte_flow_error *error __rte_unused)
16136 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16137 switch (actions->type) {
16138 case RTE_FLOW_ACTION_TYPE_VOID:
16140 case RTE_FLOW_ACTION_TYPE_COUNT:
16141 ret = flow_dv_query_count(dev, flow->counter, data,
16144 case RTE_FLOW_ACTION_TYPE_AGE:
16145 ret = flow_dv_query_age(dev, flow, data, error);
16148 return rte_flow_error_set(error, ENOTSUP,
16149 RTE_FLOW_ERROR_TYPE_ACTION,
16151 "action not supported");
16158 * Destroy the meter table set.
16159 * Lock free, (mutex should be acquired by caller).
16162 * Pointer to Ethernet device.
16164 * Meter information table.
16167 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16168 struct mlx5_flow_meter_info *fm)
16170 struct mlx5_priv *priv = dev->data->dev_private;
16173 if (!fm || !priv->sh->config.dv_flow_en)
16175 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16176 if (fm->drop_rule[i]) {
16177 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16178 fm->drop_rule[i] = NULL;
16184 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16186 struct mlx5_priv *priv = dev->data->dev_private;
16187 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16188 struct mlx5_flow_tbl_data_entry *tbl;
16191 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16192 if (mtrmng->def_rule[i]) {
16193 claim_zero(mlx5_flow_os_destroy_flow
16194 (mtrmng->def_rule[i]));
16195 mtrmng->def_rule[i] = NULL;
16197 if (mtrmng->def_matcher[i]) {
16198 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16199 struct mlx5_flow_tbl_data_entry, tbl);
16200 mlx5_list_unregister(tbl->matchers,
16201 &mtrmng->def_matcher[i]->entry);
16202 mtrmng->def_matcher[i] = NULL;
16204 for (j = 0; j < MLX5_REG_BITS; j++) {
16205 if (mtrmng->drop_matcher[i][j]) {
16207 container_of(mtrmng->drop_matcher[i][j]->tbl,
16208 struct mlx5_flow_tbl_data_entry,
16210 mlx5_list_unregister(tbl->matchers,
16211 &mtrmng->drop_matcher[i][j]->entry);
16212 mtrmng->drop_matcher[i][j] = NULL;
16215 if (mtrmng->drop_tbl[i]) {
16216 flow_dv_tbl_resource_release(MLX5_SH(dev),
16217 mtrmng->drop_tbl[i]);
16218 mtrmng->drop_tbl[i] = NULL;
16223 /* Number of meter flow actions, count and jump or count and drop. */
16224 #define METER_ACTIONS 2
16227 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16228 enum mlx5_meter_domain domain)
16230 struct mlx5_priv *priv = dev->data->dev_private;
16231 struct mlx5_flow_meter_def_policy *def_policy =
16232 priv->sh->mtrmng->def_policy[domain];
16234 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16235 mlx5_free(def_policy);
16236 priv->sh->mtrmng->def_policy[domain] = NULL;
16240 * Destroy the default policy table set.
16243 * Pointer to Ethernet device.
16246 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16248 struct mlx5_priv *priv = dev->data->dev_private;
16251 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16252 if (priv->sh->mtrmng->def_policy[i])
16253 __flow_dv_destroy_domain_def_policy(dev,
16254 (enum mlx5_meter_domain)i);
16255 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16259 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16260 uint32_t color_reg_c_idx,
16261 enum rte_color color, void *matcher_object,
16262 int actions_n, void *actions,
16263 bool match_src_port, const struct rte_flow_item *item,
16264 void **rule, const struct rte_flow_attr *attr)
16267 struct mlx5_flow_dv_match_params value = {
16268 .size = sizeof(value.buf),
16270 struct mlx5_flow_dv_match_params matcher = {
16271 .size = sizeof(matcher.buf),
16273 struct mlx5_priv *priv = dev->data->dev_private;
16276 if (match_src_port && priv->sh->esw_mode) {
16277 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16278 value.buf, item, attr)) {
16279 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16280 " value with port.", color);
16284 flow_dv_match_meta_reg(matcher.buf, value.buf,
16285 (enum modify_reg)color_reg_c_idx,
16286 rte_col_2_mlx5_col(color), UINT32_MAX);
16287 misc_mask = flow_dv_matcher_enable(value.buf);
16288 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16289 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16290 actions_n, actions, rule);
16292 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16299 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16300 uint32_t color_reg_c_idx,
16302 struct mlx5_flow_meter_sub_policy *sub_policy,
16303 const struct rte_flow_attr *attr,
16304 bool match_src_port,
16305 const struct rte_flow_item *item,
16306 struct mlx5_flow_dv_matcher **policy_matcher,
16307 struct rte_flow_error *error)
16309 struct mlx5_list_entry *entry;
16310 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16311 struct mlx5_flow_dv_matcher matcher = {
16313 .size = sizeof(matcher.mask.buf),
16317 struct mlx5_flow_dv_match_params value = {
16318 .size = sizeof(value.buf),
16320 struct mlx5_flow_cb_ctx ctx = {
16324 struct mlx5_flow_tbl_data_entry *tbl_data;
16325 struct mlx5_priv *priv = dev->data->dev_private;
16326 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16328 if (match_src_port && priv->sh->esw_mode) {
16329 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16330 value.buf, item, attr)) {
16331 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16332 " with port.", priority);
16336 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16337 if (priority < RTE_COLOR_RED)
16338 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16339 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16340 matcher.priority = priority;
16341 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16342 matcher.mask.size);
16343 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16345 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16349 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16354 * Create the policy rules per domain.
16357 * Pointer to Ethernet device.
16358 * @param[in] sub_policy
16359 * Pointer to sub policy table..
16360 * @param[in] egress
16361 * Direction of the table.
16362 * @param[in] transfer
16363 * E-Switch or NIC flow.
16365 * Pointer to policy action list per color.
16368 * 0 on success, -1 otherwise.
16371 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16372 struct mlx5_flow_meter_sub_policy *sub_policy,
16373 uint8_t egress, uint8_t transfer, bool match_src_port,
16374 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16376 struct mlx5_priv *priv = dev->data->dev_private;
16377 struct rte_flow_error flow_err;
16378 uint32_t color_reg_c_idx;
16379 struct rte_flow_attr attr = {
16380 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16383 .egress = !!egress,
16384 .transfer = !!transfer,
16388 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16389 struct mlx5_sub_policy_color_rule *color_rule;
16391 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16395 /* Create policy table with POLICY level. */
16396 if (!sub_policy->tbl_rsc)
16397 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16398 MLX5_FLOW_TABLE_LEVEL_POLICY,
16399 egress, transfer, false, NULL, 0, 0,
16400 sub_policy->idx, &flow_err);
16401 if (!sub_policy->tbl_rsc) {
16403 "Failed to create meter sub policy table.");
16406 /* Prepare matchers. */
16407 color_reg_c_idx = ret;
16408 for (i = 0; i < RTE_COLORS; i++) {
16409 TAILQ_INIT(&sub_policy->color_rules[i]);
16410 if (!acts[i].actions_n)
16412 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16413 sizeof(struct mlx5_sub_policy_color_rule),
16416 DRV_LOG(ERR, "No memory to create color rule.");
16419 tmp_rules[i] = color_rule;
16420 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16421 color_rule, next_port);
16422 color_rule->src_port = priv->representor_id;
16425 /* Create matchers for colors. */
16426 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16427 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16428 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16429 &attr, svport_match, NULL,
16430 &color_rule->matcher, &flow_err)) {
16431 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16434 /* Create flow, matching color. */
16435 if (__flow_dv_create_policy_flow(dev,
16436 color_reg_c_idx, (enum rte_color)i,
16437 color_rule->matcher->matcher_object,
16438 acts[i].actions_n, acts[i].dv_actions,
16439 svport_match, NULL, &color_rule->rule,
16441 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16447 /* All the policy rules will be cleared. */
16449 color_rule = tmp_rules[i];
16451 if (color_rule->rule)
16452 mlx5_flow_os_destroy_flow(color_rule->rule);
16453 if (color_rule->matcher) {
16454 struct mlx5_flow_tbl_data_entry *tbl =
16455 container_of(color_rule->matcher->tbl,
16456 typeof(*tbl), tbl);
16457 mlx5_list_unregister(tbl->matchers,
16458 &color_rule->matcher->entry);
16460 TAILQ_REMOVE(&sub_policy->color_rules[i],
16461 color_rule, next_port);
16462 mlx5_free(color_rule);
16469 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16470 struct mlx5_flow_meter_policy *mtr_policy,
16471 struct mlx5_flow_meter_sub_policy *sub_policy,
16474 struct mlx5_priv *priv = dev->data->dev_private;
16475 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16476 struct mlx5_flow_dv_tag_resource *tag;
16477 struct mlx5_flow_dv_port_id_action_resource *port_action;
16478 struct mlx5_hrxq *hrxq;
16479 struct mlx5_flow_meter_info *next_fm = NULL;
16480 struct mlx5_flow_meter_policy *next_policy;
16481 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16482 struct mlx5_flow_tbl_data_entry *tbl_data;
16483 struct rte_flow_error error;
16484 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16485 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16486 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16487 bool match_src_port = false;
16490 /* If RSS or Queue, no previous actions / rules is created. */
16491 for (i = 0; i < RTE_COLORS; i++) {
16492 acts[i].actions_n = 0;
16493 if (i == RTE_COLOR_RED) {
16494 /* Only support drop on red. */
16495 acts[i].dv_actions[0] =
16496 mtr_policy->dr_drop_action[domain];
16497 acts[i].actions_n = 1;
16500 if (i == RTE_COLOR_GREEN &&
16501 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16502 struct rte_flow_attr attr = {
16503 .transfer = transfer
16506 next_fm = mlx5_flow_meter_find(priv,
16507 mtr_policy->act_cnt[i].next_mtr_id,
16511 "Failed to get next hierarchy meter.");
16514 if (mlx5_flow_meter_attach(priv, next_fm,
16516 DRV_LOG(ERR, "%s", error.message);
16520 /* Meter action must be the first for TX. */
16522 acts[i].dv_actions[acts[i].actions_n] =
16523 next_fm->meter_action;
16524 acts[i].actions_n++;
16527 if (mtr_policy->act_cnt[i].rix_mark) {
16528 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16529 mtr_policy->act_cnt[i].rix_mark);
16531 DRV_LOG(ERR, "Failed to find "
16532 "mark action for policy.");
16535 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16536 acts[i].actions_n++;
16538 if (mtr_policy->act_cnt[i].modify_hdr) {
16539 acts[i].dv_actions[acts[i].actions_n] =
16540 mtr_policy->act_cnt[i].modify_hdr->action;
16541 acts[i].actions_n++;
16543 if (mtr_policy->act_cnt[i].fate_action) {
16544 switch (mtr_policy->act_cnt[i].fate_action) {
16545 case MLX5_FLOW_FATE_PORT_ID:
16546 port_action = mlx5_ipool_get
16547 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16548 mtr_policy->act_cnt[i].rix_port_id_action);
16549 if (!port_action) {
16550 DRV_LOG(ERR, "Failed to find "
16551 "port action for policy.");
16554 acts[i].dv_actions[acts[i].actions_n] =
16555 port_action->action;
16556 acts[i].actions_n++;
16557 mtr_policy->dev = dev;
16558 match_src_port = true;
16560 case MLX5_FLOW_FATE_DROP:
16561 case MLX5_FLOW_FATE_JUMP:
16562 acts[i].dv_actions[acts[i].actions_n] =
16563 mtr_policy->act_cnt[i].dr_jump_action[domain];
16564 acts[i].actions_n++;
16566 case MLX5_FLOW_FATE_SHARED_RSS:
16567 case MLX5_FLOW_FATE_QUEUE:
16568 hrxq = mlx5_ipool_get
16569 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16570 sub_policy->rix_hrxq[i]);
16572 DRV_LOG(ERR, "Failed to find "
16573 "queue action for policy.");
16576 acts[i].dv_actions[acts[i].actions_n] =
16578 acts[i].actions_n++;
16580 case MLX5_FLOW_FATE_MTR:
16583 "No next hierarchy meter.");
16587 acts[i].dv_actions[acts[i].actions_n] =
16588 next_fm->meter_action;
16589 acts[i].actions_n++;
16591 if (mtr_policy->act_cnt[i].next_sub_policy) {
16593 mtr_policy->act_cnt[i].next_sub_policy;
16596 mlx5_flow_meter_policy_find(dev,
16597 next_fm->policy_id, NULL);
16598 MLX5_ASSERT(next_policy);
16600 next_policy->sub_policys[domain][0];
16603 container_of(next_sub_policy->tbl_rsc,
16604 struct mlx5_flow_tbl_data_entry, tbl);
16605 acts[i].dv_actions[acts[i].actions_n++] =
16606 tbl_data->jump.action;
16607 if (mtr_policy->act_cnt[i].modify_hdr)
16608 match_src_port = !!transfer;
16611 /*Queue action do nothing*/
16616 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16617 egress, transfer, match_src_port, acts)) {
16619 "Failed to create policy rules per domain.");
16625 mlx5_flow_meter_detach(priv, next_fm);
16630 * Create the policy rules.
16633 * Pointer to Ethernet device.
16634 * @param[in,out] mtr_policy
16635 * Pointer to meter policy table.
16638 * 0 on success, -1 otherwise.
16641 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16642 struct mlx5_flow_meter_policy *mtr_policy)
16645 uint16_t sub_policy_num;
16647 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16648 sub_policy_num = (mtr_policy->sub_policy_num >>
16649 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16650 MLX5_MTR_SUB_POLICY_NUM_MASK;
16651 if (!sub_policy_num)
16653 /* Prepare actions list and create policy rules. */
16654 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16655 mtr_policy->sub_policys[i][0], i)) {
16656 DRV_LOG(ERR, "Failed to create policy action "
16657 "list per domain.");
16665 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16667 struct mlx5_priv *priv = dev->data->dev_private;
16668 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16669 struct mlx5_flow_meter_def_policy *def_policy;
16670 struct mlx5_flow_tbl_resource *jump_tbl;
16671 struct mlx5_flow_tbl_data_entry *tbl_data;
16672 uint8_t egress, transfer;
16673 struct rte_flow_error error;
16674 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16677 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16678 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16679 def_policy = mtrmng->def_policy[domain];
16681 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16682 sizeof(struct mlx5_flow_meter_def_policy),
16683 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16685 DRV_LOG(ERR, "Failed to alloc default policy table.");
16686 goto def_policy_error;
16688 mtrmng->def_policy[domain] = def_policy;
16689 /* Create the meter suffix table with SUFFIX level. */
16690 jump_tbl = flow_dv_tbl_resource_get(dev,
16691 MLX5_FLOW_TABLE_LEVEL_METER,
16692 egress, transfer, false, NULL, 0,
16693 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16696 "Failed to create meter suffix table.");
16697 goto def_policy_error;
16699 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16700 tbl_data = container_of(jump_tbl,
16701 struct mlx5_flow_tbl_data_entry, tbl);
16702 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16703 tbl_data->jump.action;
16704 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16705 acts[RTE_COLOR_GREEN].actions_n = 1;
16707 * YELLOW has the same default policy as GREEN does.
16708 * G & Y share the same table and action. The 2nd time of table
16709 * resource getting is just to update the reference count for
16710 * the releasing stage.
16712 jump_tbl = flow_dv_tbl_resource_get(dev,
16713 MLX5_FLOW_TABLE_LEVEL_METER,
16714 egress, transfer, false, NULL, 0,
16715 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16718 "Failed to get meter suffix table.");
16719 goto def_policy_error;
16721 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16722 tbl_data = container_of(jump_tbl,
16723 struct mlx5_flow_tbl_data_entry, tbl);
16724 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16725 tbl_data->jump.action;
16726 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16727 acts[RTE_COLOR_YELLOW].actions_n = 1;
16728 /* Create jump action to the drop table. */
16729 if (!mtrmng->drop_tbl[domain]) {
16730 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16731 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16732 egress, transfer, false, NULL, 0,
16733 0, MLX5_MTR_TABLE_ID_DROP, &error);
16734 if (!mtrmng->drop_tbl[domain]) {
16735 DRV_LOG(ERR, "Failed to create meter "
16736 "drop table for default policy.");
16737 goto def_policy_error;
16740 /* all RED: unique Drop table for jump action. */
16741 tbl_data = container_of(mtrmng->drop_tbl[domain],
16742 struct mlx5_flow_tbl_data_entry, tbl);
16743 def_policy->dr_jump_action[RTE_COLOR_RED] =
16744 tbl_data->jump.action;
16745 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16746 acts[RTE_COLOR_RED].actions_n = 1;
16747 /* Create default policy rules. */
16748 ret = __flow_dv_create_domain_policy_rules(dev,
16749 &def_policy->sub_policy,
16750 egress, transfer, false, acts);
16752 DRV_LOG(ERR, "Failed to create default policy rules.");
16753 goto def_policy_error;
16758 __flow_dv_destroy_domain_def_policy(dev,
16759 (enum mlx5_meter_domain)domain);
16764 * Create the default policy table set.
16767 * Pointer to Ethernet device.
16769 * 0 on success, -1 otherwise.
16772 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16774 struct mlx5_priv *priv = dev->data->dev_private;
16777 /* Non-termination policy table. */
16778 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16779 if (!priv->sh->config.dv_esw_en &&
16780 i == MLX5_MTR_DOMAIN_TRANSFER)
16782 if (__flow_dv_create_domain_def_policy(dev, i)) {
16783 DRV_LOG(ERR, "Failed to create default policy");
16784 /* Rollback the created default policies for others. */
16785 flow_dv_destroy_def_policy(dev);
16793 * Create the needed meter tables.
16794 * Lock free, (mutex should be acquired by caller).
16797 * Pointer to Ethernet device.
16799 * Meter information table.
16800 * @param[in] mtr_idx
16802 * @param[in] domain_bitmap
16805 * 0 on success, -1 otherwise.
16808 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16809 struct mlx5_flow_meter_info *fm,
16811 uint8_t domain_bitmap)
16813 struct mlx5_priv *priv = dev->data->dev_private;
16814 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16815 struct rte_flow_error error;
16816 struct mlx5_flow_tbl_data_entry *tbl_data;
16817 uint8_t egress, transfer;
16818 void *actions[METER_ACTIONS];
16819 int domain, ret, i;
16820 struct mlx5_flow_counter *cnt;
16821 struct mlx5_flow_dv_match_params value = {
16822 .size = sizeof(value.buf),
16824 struct mlx5_flow_dv_match_params matcher_para = {
16825 .size = sizeof(matcher_para.buf),
16827 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16829 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16830 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16831 struct mlx5_list_entry *entry;
16832 struct mlx5_flow_dv_matcher matcher = {
16834 .size = sizeof(matcher.mask.buf),
16837 struct mlx5_flow_dv_matcher *drop_matcher;
16838 struct mlx5_flow_cb_ctx ctx = {
16844 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16845 rte_errno = ENOTSUP;
16848 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16849 if (!(domain_bitmap & (1 << domain)) ||
16850 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16852 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16853 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16854 /* Create the drop table with METER DROP level. */
16855 if (!mtrmng->drop_tbl[domain]) {
16856 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16857 MLX5_FLOW_TABLE_LEVEL_METER,
16858 egress, transfer, false, NULL, 0,
16859 0, MLX5_MTR_TABLE_ID_DROP, &error);
16860 if (!mtrmng->drop_tbl[domain]) {
16861 DRV_LOG(ERR, "Failed to create meter drop table.");
16865 /* Create default matcher in drop table. */
16866 matcher.tbl = mtrmng->drop_tbl[domain],
16867 tbl_data = container_of(mtrmng->drop_tbl[domain],
16868 struct mlx5_flow_tbl_data_entry, tbl);
16869 if (!mtrmng->def_matcher[domain]) {
16870 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16871 (enum modify_reg)mtr_id_reg_c,
16873 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16874 matcher.crc = rte_raw_cksum
16875 ((const void *)matcher.mask.buf,
16876 matcher.mask.size);
16877 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16879 DRV_LOG(ERR, "Failed to register meter "
16880 "drop default matcher.");
16883 mtrmng->def_matcher[domain] = container_of(entry,
16884 struct mlx5_flow_dv_matcher, entry);
16886 /* Create default rule in drop table. */
16887 if (!mtrmng->def_rule[domain]) {
16889 actions[i++] = priv->sh->dr_drop_action;
16890 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16891 (enum modify_reg)mtr_id_reg_c, 0, 0);
16892 misc_mask = flow_dv_matcher_enable(value.buf);
16893 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16894 ret = mlx5_flow_os_create_flow
16895 (mtrmng->def_matcher[domain]->matcher_object,
16896 (void *)&value, i, actions,
16897 &mtrmng->def_rule[domain]);
16899 DRV_LOG(ERR, "Failed to create meter "
16900 "default drop rule for drop table.");
16906 MLX5_ASSERT(mtrmng->max_mtr_bits);
16907 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16908 /* Create matchers for Drop. */
16909 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16910 (enum modify_reg)mtr_id_reg_c, 0,
16911 (mtr_id_mask << mtr_id_offset));
16912 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16913 matcher.crc = rte_raw_cksum
16914 ((const void *)matcher.mask.buf,
16915 matcher.mask.size);
16916 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16919 "Failed to register meter drop matcher.");
16922 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16923 container_of(entry, struct mlx5_flow_dv_matcher,
16927 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16928 /* Create drop rule, matching meter_id only. */
16929 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16930 (enum modify_reg)mtr_id_reg_c,
16931 (mtr_idx << mtr_id_offset), UINT32_MAX);
16933 cnt = flow_dv_counter_get_by_idx(dev,
16934 fm->drop_cnt, NULL);
16935 actions[i++] = cnt->action;
16936 actions[i++] = priv->sh->dr_drop_action;
16937 misc_mask = flow_dv_matcher_enable(value.buf);
16938 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16939 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16940 (void *)&value, i, actions,
16941 &fm->drop_rule[domain]);
16943 DRV_LOG(ERR, "Failed to create meter "
16944 "drop rule for drop table.");
16950 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16951 if (fm->drop_rule[i]) {
16952 claim_zero(mlx5_flow_os_destroy_flow
16953 (fm->drop_rule[i]));
16954 fm->drop_rule[i] = NULL;
16960 static struct mlx5_flow_meter_sub_policy *
16961 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16962 struct mlx5_flow_meter_policy *mtr_policy,
16963 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16964 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16967 struct mlx5_priv *priv = dev->data->dev_private;
16968 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16969 uint32_t sub_policy_idx = 0;
16970 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16972 struct mlx5_hrxq *hrxq;
16973 struct mlx5_flow_handle dh;
16974 struct mlx5_meter_policy_action_container *act_cnt;
16975 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16976 uint16_t sub_policy_num;
16977 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
16980 rte_spinlock_lock(&mtr_policy->sl);
16981 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16984 hrxq = mlx5_hrxq_get(dev, rss_desc[i]);
16986 rte_spinlock_unlock(&mtr_policy->sl);
16989 hrxq_idx[i] = hrxq->idx;
16991 sub_policy_num = (mtr_policy->sub_policy_num >>
16992 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16993 MLX5_MTR_SUB_POLICY_NUM_MASK;
16994 for (j = 0; j < sub_policy_num; j++) {
16995 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16998 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
17001 if (i >= MLX5_MTR_RTE_COLORS) {
17003 * Found the sub policy table with
17004 * the same queue per color.
17006 rte_spinlock_unlock(&mtr_policy->sl);
17007 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17008 mlx5_hrxq_release(dev, hrxq_idx[i]);
17010 return mtr_policy->sub_policys[domain][j];
17013 /* Create sub policy. */
17014 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
17015 /* Reuse the first pre-allocated sub_policy. */
17016 sub_policy = mtr_policy->sub_policys[domain][0];
17017 sub_policy_idx = sub_policy->idx;
17019 sub_policy = mlx5_ipool_zmalloc
17020 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17023 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
17024 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
17025 mlx5_hrxq_release(dev, hrxq_idx[i]);
17026 goto rss_sub_policy_error;
17028 sub_policy->idx = sub_policy_idx;
17029 sub_policy->main_policy = mtr_policy;
17031 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17034 sub_policy->rix_hrxq[i] = hrxq_idx[i];
17035 if (mtr_policy->is_hierarchy) {
17036 act_cnt = &mtr_policy->act_cnt[i];
17037 act_cnt->next_sub_policy = next_sub_policy;
17038 mlx5_hrxq_release(dev, hrxq_idx[i]);
17041 * Overwrite the last action from
17042 * RSS action to Queue action.
17044 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
17047 DRV_LOG(ERR, "Failed to get policy hrxq");
17048 goto rss_sub_policy_error;
17050 act_cnt = &mtr_policy->act_cnt[i];
17051 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
17052 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
17053 if (act_cnt->rix_mark)
17055 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
17056 dh.rix_hrxq = hrxq_idx[i];
17057 flow_drv_rxq_flags_set(dev, &dh);
17061 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
17062 sub_policy, domain)) {
17063 DRV_LOG(ERR, "Failed to create policy "
17064 "rules for ingress domain.");
17065 goto rss_sub_policy_error;
17067 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17068 i = (mtr_policy->sub_policy_num >>
17069 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17070 MLX5_MTR_SUB_POLICY_NUM_MASK;
17071 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
17072 DRV_LOG(ERR, "No free sub-policy slot.");
17073 goto rss_sub_policy_error;
17075 mtr_policy->sub_policys[domain][i] = sub_policy;
17077 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17078 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17079 mtr_policy->sub_policy_num |=
17080 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17081 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17083 rte_spinlock_unlock(&mtr_policy->sl);
17086 rss_sub_policy_error:
17088 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17089 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17090 i = (mtr_policy->sub_policy_num >>
17091 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17092 MLX5_MTR_SUB_POLICY_NUM_MASK;
17093 mtr_policy->sub_policys[domain][i] = NULL;
17094 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17098 rte_spinlock_unlock(&mtr_policy->sl);
17103 * Find the policy table for prefix table with RSS.
17106 * Pointer to Ethernet device.
17107 * @param[in] mtr_policy
17108 * Pointer to meter policy table.
17109 * @param[in] rss_desc
17110 * Pointer to rss_desc
17112 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17114 static struct mlx5_flow_meter_sub_policy *
17115 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17116 struct mlx5_flow_meter_policy *mtr_policy,
17117 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17119 struct mlx5_priv *priv = dev->data->dev_private;
17120 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17121 struct mlx5_flow_meter_info *next_fm;
17122 struct mlx5_flow_meter_policy *next_policy;
17123 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17124 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17125 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17126 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17127 bool reuse_sub_policy;
17132 /* Iterate hierarchy to get all policies in this hierarchy. */
17133 policies[i++] = mtr_policy;
17134 if (!mtr_policy->is_hierarchy)
17136 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17137 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17140 next_fm = mlx5_flow_meter_find(priv,
17141 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17143 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17147 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17149 MLX5_ASSERT(next_policy);
17150 mtr_policy = next_policy;
17154 * From last policy to the first one in hierarchy,
17155 * create / get the sub policy for each of them.
17157 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17161 &reuse_sub_policy);
17163 DRV_LOG(ERR, "Failed to get the sub policy.");
17166 if (!reuse_sub_policy)
17167 sub_policies[j++] = sub_policy;
17168 next_sub_policy = sub_policy;
17173 uint16_t sub_policy_num;
17175 sub_policy = sub_policies[--j];
17176 mtr_policy = sub_policy->main_policy;
17177 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17178 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17179 sub_policy_num = (mtr_policy->sub_policy_num >>
17180 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17181 MLX5_MTR_SUB_POLICY_NUM_MASK;
17182 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17185 mtr_policy->sub_policy_num &=
17186 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17187 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17188 mtr_policy->sub_policy_num |=
17189 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17190 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17191 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17199 * Create the sub policy tag rule for all meters in hierarchy.
17202 * Pointer to Ethernet device.
17204 * Meter information table.
17205 * @param[in] src_port
17206 * The src port this extra rule should use.
17208 * The src port match item.
17209 * @param[out] error
17210 * Perform verbose error reporting if not NULL.
17212 * 0 on success, a negative errno value otherwise and rte_errno is set.
17215 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17216 struct mlx5_flow_meter_info *fm,
17218 const struct rte_flow_item *item,
17219 struct rte_flow_error *error)
17221 struct mlx5_priv *priv = dev->data->dev_private;
17222 struct mlx5_flow_meter_policy *mtr_policy;
17223 struct mlx5_flow_meter_sub_policy *sub_policy;
17224 struct mlx5_flow_meter_info *next_fm = NULL;
17225 struct mlx5_flow_meter_policy *next_policy;
17226 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17227 struct mlx5_flow_tbl_data_entry *tbl_data;
17228 struct mlx5_sub_policy_color_rule *color_rule;
17229 struct mlx5_meter_policy_acts acts;
17230 uint32_t color_reg_c_idx;
17231 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17232 struct rte_flow_attr attr = {
17233 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17240 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17243 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17244 MLX5_ASSERT(mtr_policy);
17245 if (!mtr_policy->is_hierarchy)
17247 next_fm = mlx5_flow_meter_find(priv,
17248 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17250 return rte_flow_error_set(error, EINVAL,
17251 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17252 "Failed to find next meter in hierarchy.");
17254 if (!next_fm->drop_cnt)
17256 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17257 sub_policy = mtr_policy->sub_policys[domain][0];
17258 for (i = 0; i < RTE_COLORS; i++) {
17259 bool rule_exist = false;
17260 struct mlx5_meter_policy_action_container *act_cnt;
17262 if (i >= RTE_COLOR_YELLOW)
17264 TAILQ_FOREACH(color_rule,
17265 &sub_policy->color_rules[i], next_port)
17266 if (color_rule->src_port == src_port) {
17272 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17273 sizeof(struct mlx5_sub_policy_color_rule),
17276 return rte_flow_error_set(error, ENOMEM,
17277 RTE_FLOW_ERROR_TYPE_ACTION,
17278 NULL, "No memory to create tag color rule.");
17279 color_rule->src_port = src_port;
17281 next_policy = mlx5_flow_meter_policy_find(dev,
17282 next_fm->policy_id, NULL);
17283 MLX5_ASSERT(next_policy);
17284 next_sub_policy = next_policy->sub_policys[domain][0];
17285 tbl_data = container_of(next_sub_policy->tbl_rsc,
17286 struct mlx5_flow_tbl_data_entry, tbl);
17287 act_cnt = &mtr_policy->act_cnt[i];
17289 acts.dv_actions[0] = next_fm->meter_action;
17290 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17292 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17293 acts.dv_actions[1] = next_fm->meter_action;
17295 acts.dv_actions[2] = tbl_data->jump.action;
17296 acts.actions_n = 3;
17297 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17301 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17302 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17304 &color_rule->matcher, error)) {
17305 rte_flow_error_set(error, errno,
17306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17307 "Failed to create hierarchy meter matcher.");
17310 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17312 color_rule->matcher->matcher_object,
17313 acts.actions_n, acts.dv_actions,
17315 &color_rule->rule, &attr)) {
17316 rte_flow_error_set(error, errno,
17317 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17318 "Failed to create hierarchy meter rule.");
17321 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17322 color_rule, next_port);
17326 * Recursive call to iterate all meters in hierarchy and
17327 * create needed rules.
17329 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17330 src_port, item, error);
17333 if (color_rule->rule)
17334 mlx5_flow_os_destroy_flow(color_rule->rule);
17335 if (color_rule->matcher) {
17336 struct mlx5_flow_tbl_data_entry *tbl =
17337 container_of(color_rule->matcher->tbl,
17338 typeof(*tbl), tbl);
17339 mlx5_list_unregister(tbl->matchers,
17340 &color_rule->matcher->entry);
17342 mlx5_free(color_rule);
17345 mlx5_flow_meter_detach(priv, next_fm);
17350 * Destroy the sub policy table with RX queue.
17353 * Pointer to Ethernet device.
17354 * @param[in] mtr_policy
17355 * Pointer to meter policy table.
17358 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17359 struct mlx5_flow_meter_policy *mtr_policy)
17361 struct mlx5_priv *priv = dev->data->dev_private;
17362 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17363 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17365 uint16_t sub_policy_num, new_policy_num;
17367 rte_spinlock_lock(&mtr_policy->sl);
17368 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17369 switch (mtr_policy->act_cnt[i].fate_action) {
17370 case MLX5_FLOW_FATE_SHARED_RSS:
17371 sub_policy_num = (mtr_policy->sub_policy_num >>
17372 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17373 MLX5_MTR_SUB_POLICY_NUM_MASK;
17374 new_policy_num = sub_policy_num;
17375 for (j = 0; j < sub_policy_num; j++) {
17377 mtr_policy->sub_policys[domain][j];
17379 __flow_dv_destroy_sub_policy_rules(dev,
17382 mtr_policy->sub_policys[domain][0]) {
17383 mtr_policy->sub_policys[domain][j] =
17386 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17392 if (new_policy_num != sub_policy_num) {
17393 mtr_policy->sub_policy_num &=
17394 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17395 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17396 mtr_policy->sub_policy_num |=
17398 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17399 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17402 case MLX5_FLOW_FATE_QUEUE:
17403 sub_policy = mtr_policy->sub_policys[domain][0];
17404 __flow_dv_destroy_sub_policy_rules(dev,
17408 /*Other actions without queue and do nothing*/
17412 rte_spinlock_unlock(&mtr_policy->sl);
17415 * Check whether the DR drop action is supported on the root table or not.
17417 * Create a simple flow with DR drop action on root table to validate
17418 * if DR drop action on root table is supported or not.
17421 * Pointer to rte_eth_dev structure.
17424 * 0 on success, a negative errno value otherwise and rte_errno is set.
17427 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17429 struct mlx5_priv *priv = dev->data->dev_private;
17430 struct mlx5_dev_ctx_shared *sh = priv->sh;
17431 struct mlx5_flow_dv_match_params mask = {
17432 .size = sizeof(mask.buf),
17434 struct mlx5_flow_dv_match_params value = {
17435 .size = sizeof(value.buf),
17437 struct mlx5dv_flow_matcher_attr dv_attr = {
17438 .type = IBV_FLOW_ATTR_NORMAL,
17440 .match_criteria_enable = 0,
17441 .match_mask = (void *)&mask,
17443 struct mlx5_flow_tbl_resource *tbl = NULL;
17444 void *matcher = NULL;
17448 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17452 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17453 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17454 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17455 tbl->obj, &matcher);
17458 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17459 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17460 &sh->dr_drop_action, &flow);
17463 * If DR drop action is not supported on root table, flow create will
17464 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17468 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17469 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17471 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17474 claim_zero(mlx5_flow_os_destroy_flow(flow));
17477 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17479 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17484 * Validate the batch counter support in root table.
17486 * Create a simple flow with invalid counter and drop action on root table to
17487 * validate if batch counter with offset on root table is supported or not.
17490 * Pointer to rte_eth_dev structure.
17493 * 0 on success, a negative errno value otherwise and rte_errno is set.
17496 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17498 struct mlx5_priv *priv = dev->data->dev_private;
17499 struct mlx5_dev_ctx_shared *sh = priv->sh;
17500 struct mlx5_flow_dv_match_params mask = {
17501 .size = sizeof(mask.buf),
17503 struct mlx5_flow_dv_match_params value = {
17504 .size = sizeof(value.buf),
17506 struct mlx5dv_flow_matcher_attr dv_attr = {
17507 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17509 .match_criteria_enable = 0,
17510 .match_mask = (void *)&mask,
17512 void *actions[2] = { 0 };
17513 struct mlx5_flow_tbl_resource *tbl = NULL;
17514 struct mlx5_devx_obj *dcs = NULL;
17515 void *matcher = NULL;
17519 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17523 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17526 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17530 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17531 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17532 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17533 tbl->obj, &matcher);
17536 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17537 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17541 * If batch counter with offset is not supported, the driver will not
17542 * validate the invalid offset value, flow create should success.
17543 * In this case, it means batch counter is not supported in root table.
17545 * Otherwise, if flow create is failed, counter offset is supported.
17548 DRV_LOG(INFO, "Batch counter is not supported in root "
17549 "table. Switch to fallback mode.");
17550 rte_errno = ENOTSUP;
17552 claim_zero(mlx5_flow_os_destroy_flow(flow));
17554 /* Check matcher to make sure validate fail at flow create. */
17555 if (!matcher || (matcher && errno != EINVAL))
17556 DRV_LOG(ERR, "Unexpected error in counter offset "
17557 "support detection");
17561 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17563 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17565 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17567 claim_zero(mlx5_devx_cmd_destroy(dcs));
17572 * Query a devx counter.
17575 * Pointer to the Ethernet device structure.
17577 * Index to the flow counter.
17579 * Set to clear the counter statistics.
17581 * The statistics value of packets.
17582 * @param[out] bytes
17583 * The statistics value of bytes.
17586 * 0 on success, otherwise return -1.
17589 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17590 uint64_t *pkts, uint64_t *bytes, void **action)
17592 struct mlx5_priv *priv = dev->data->dev_private;
17593 struct mlx5_flow_counter *cnt;
17594 uint64_t inn_pkts, inn_bytes;
17597 if (!priv->sh->cdev->config.devx)
17600 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17603 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17605 *action = cnt->action;
17607 *pkts = inn_pkts - cnt->hits;
17608 *bytes = inn_bytes - cnt->bytes;
17610 cnt->hits = inn_pkts;
17611 cnt->bytes = inn_bytes;
17617 * Get aged-out flows.
17620 * Pointer to the Ethernet device structure.
17621 * @param[in] context
17622 * The address of an array of pointers to the aged-out flows contexts.
17623 * @param[in] nb_contexts
17624 * The length of context array pointers.
17625 * @param[out] error
17626 * Perform verbose error reporting if not NULL. Initialized in case of
17630 * how many contexts get in success, otherwise negative errno value.
17631 * if nb_contexts is 0, return the amount of all aged contexts.
17632 * if nb_contexts is not 0 , return the amount of aged flows reported
17633 * in the context array.
17634 * @note: only stub for now
17637 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17639 uint32_t nb_contexts,
17640 struct rte_flow_error *error)
17642 struct mlx5_priv *priv = dev->data->dev_private;
17643 struct mlx5_age_info *age_info;
17644 struct mlx5_age_param *age_param;
17645 struct mlx5_flow_counter *counter;
17646 struct mlx5_aso_age_action *act;
17649 if (nb_contexts && !context)
17650 return rte_flow_error_set(error, EINVAL,
17651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17652 NULL, "empty context");
17653 age_info = GET_PORT_AGE_INFO(priv);
17654 rte_spinlock_lock(&age_info->aged_sl);
17655 LIST_FOREACH(act, &age_info->aged_aso, next) {
17658 context[nb_flows - 1] =
17659 act->age_params.context;
17660 if (!(--nb_contexts))
17664 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17667 age_param = MLX5_CNT_TO_AGE(counter);
17668 context[nb_flows - 1] = age_param->context;
17669 if (!(--nb_contexts))
17673 rte_spinlock_unlock(&age_info->aged_sl);
17674 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17679 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17682 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17684 return flow_dv_counter_alloc(dev, 0);
17688 * Validate indirect action.
17689 * Dispatcher for action type specific validation.
17692 * Pointer to the Ethernet device structure.
17694 * Indirect action configuration.
17695 * @param[in] action
17696 * The indirect action object to validate.
17697 * @param[out] error
17698 * Perform verbose error reporting if not NULL. Initialized in case of
17702 * 0 on success, otherwise negative errno value.
17705 flow_dv_action_validate(struct rte_eth_dev *dev,
17706 const struct rte_flow_indir_action_conf *conf,
17707 const struct rte_flow_action *action,
17708 struct rte_flow_error *err)
17710 struct mlx5_priv *priv = dev->data->dev_private;
17712 RTE_SET_USED(conf);
17713 switch (action->type) {
17714 case RTE_FLOW_ACTION_TYPE_RSS:
17716 * priv->obj_ops is set according to driver capabilities.
17717 * When DevX capabilities are
17718 * sufficient, it is set to devx_obj_ops.
17719 * Otherwise, it is set to ibv_obj_ops.
17720 * ibv_obj_ops doesn't support ind_table_modify operation.
17721 * In this case the indirect RSS action can't be used.
17723 if (priv->obj_ops.ind_table_modify == NULL)
17724 return rte_flow_error_set
17726 RTE_FLOW_ERROR_TYPE_ACTION,
17728 "Indirect RSS action not supported");
17729 return mlx5_validate_action_rss(dev, action, err);
17730 case RTE_FLOW_ACTION_TYPE_AGE:
17731 if (!priv->sh->aso_age_mng)
17732 return rte_flow_error_set(err, ENOTSUP,
17733 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17735 "Indirect age action not supported");
17736 return flow_dv_validate_action_age(0, action, dev, err);
17737 case RTE_FLOW_ACTION_TYPE_COUNT:
17738 return flow_dv_validate_action_count(dev, true, 0, NULL, err);
17739 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17740 if (!priv->sh->ct_aso_en)
17741 return rte_flow_error_set(err, ENOTSUP,
17742 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17743 "ASO CT is not supported");
17744 return mlx5_validate_action_ct(dev, action->conf, err);
17746 return rte_flow_error_set(err, ENOTSUP,
17747 RTE_FLOW_ERROR_TYPE_ACTION,
17749 "action type not supported");
17754 * Check if the RSS configurations for colors of a meter policy match
17755 * each other, except the queues.
17758 * Pointer to the first RSS flow action.
17760 * Pointer to the second RSS flow action.
17763 * 0 on match, 1 on conflict.
17766 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17767 const struct rte_flow_action_rss *r2)
17769 if (r1 == NULL || r2 == NULL)
17771 if (!(r1->level <= 1 && r2->level <= 1) &&
17772 !(r1->level > 1 && r2->level > 1))
17774 if (r1->types != r2->types &&
17775 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17776 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17778 if (r1->key || r2->key) {
17779 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17780 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17782 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17789 * Validate the meter hierarchy chain for meter policy.
17792 * Pointer to the Ethernet device structure.
17793 * @param[in] meter_id
17795 * @param[in] action_flags
17796 * Holds the actions detected until now.
17797 * @param[out] is_rss
17799 * @param[out] hierarchy_domain
17800 * The domain bitmap for hierarchy policy.
17801 * @param[out] error
17802 * Perform verbose error reporting if not NULL. Initialized in case of
17806 * 0 on success, otherwise negative errno value with error set.
17809 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17811 uint64_t action_flags,
17813 uint8_t *hierarchy_domain,
17814 struct rte_mtr_error *error)
17816 struct mlx5_priv *priv = dev->data->dev_private;
17817 struct mlx5_flow_meter_info *fm;
17818 struct mlx5_flow_meter_policy *policy;
17821 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17822 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17823 return -rte_mtr_error_set(error, EINVAL,
17824 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17826 "Multiple fate actions not supported.");
17827 *hierarchy_domain = 0;
17829 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17831 return -rte_mtr_error_set(error, EINVAL,
17832 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17833 "Meter not found in meter hierarchy.");
17834 if (fm->def_policy)
17835 return -rte_mtr_error_set(error, EINVAL,
17836 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17837 "Non termination meter not supported in hierarchy.");
17838 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17839 MLX5_ASSERT(policy);
17841 * Only inherit the supported domains of the first meter in
17843 * One meter supports at least one domain.
17845 if (!*hierarchy_domain) {
17846 if (policy->transfer)
17847 *hierarchy_domain |=
17848 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17849 if (policy->ingress)
17850 *hierarchy_domain |=
17851 MLX5_MTR_DOMAIN_INGRESS_BIT;
17852 if (policy->egress)
17853 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17855 if (!policy->is_hierarchy) {
17856 *is_rss = policy->is_rss;
17859 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17860 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17861 return -rte_mtr_error_set(error, EINVAL,
17862 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17863 "Exceed max hierarchy meter number.");
17869 * Validate meter policy actions.
17870 * Dispatcher for action type specific validation.
17873 * Pointer to the Ethernet device structure.
17874 * @param[in] action
17875 * The meter policy action object to validate.
17877 * Attributes of flow to determine steering domain.
17878 * @param[out] error
17879 * Perform verbose error reporting if not NULL. Initialized in case of
17883 * 0 on success, otherwise negative errno value.
17886 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17887 const struct rte_flow_action *actions[RTE_COLORS],
17888 struct rte_flow_attr *attr,
17890 uint8_t *domain_bitmap,
17891 uint8_t *policy_mode,
17892 struct rte_mtr_error *error)
17894 struct mlx5_priv *priv = dev->data->dev_private;
17895 struct mlx5_sh_config *dev_conf = &priv->sh->config;
17896 const struct rte_flow_action *act;
17897 uint64_t action_flags[RTE_COLORS] = {0};
17900 struct rte_flow_error flow_err;
17901 uint8_t domain_color[RTE_COLORS] = {0};
17902 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17903 uint8_t hierarchy_domain = 0;
17904 const struct rte_flow_action_meter *mtr;
17905 bool def_green = false;
17906 bool def_yellow = false;
17907 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17909 if (!dev_conf->dv_esw_en)
17910 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17911 *domain_bitmap = def_domain;
17912 /* Red color could only support DROP action. */
17913 if (!actions[RTE_COLOR_RED] ||
17914 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17915 return -rte_mtr_error_set(error, ENOTSUP,
17916 RTE_MTR_ERROR_TYPE_METER_POLICY,
17917 NULL, "Red color only supports drop action.");
17919 * Check default policy actions:
17920 * Green / Yellow: no action, Red: drop action
17921 * Either G or Y will trigger default policy actions to be created.
17923 if (!actions[RTE_COLOR_GREEN] ||
17924 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17926 if (!actions[RTE_COLOR_YELLOW] ||
17927 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17929 if (def_green && def_yellow) {
17930 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17932 } else if (!def_green && def_yellow) {
17933 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17934 } else if (def_green && !def_yellow) {
17935 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17937 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17939 /* Set to empty string in case of NULL pointer access by user. */
17940 flow_err.message = "";
17941 for (i = 0; i < RTE_COLORS; i++) {
17943 for (action_flags[i] = 0, actions_n = 0;
17944 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17946 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17947 return -rte_mtr_error_set(error, ENOTSUP,
17948 RTE_MTR_ERROR_TYPE_METER_POLICY,
17949 NULL, "too many actions");
17950 switch (act->type) {
17951 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17952 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17953 if (!dev_conf->dv_esw_en)
17954 return -rte_mtr_error_set(error,
17956 RTE_MTR_ERROR_TYPE_METER_POLICY,
17957 NULL, "PORT action validate check"
17958 " fail for ESW disable");
17959 ret = flow_dv_validate_action_port_id(dev,
17961 act, attr, &flow_err);
17963 return -rte_mtr_error_set(error,
17965 RTE_MTR_ERROR_TYPE_METER_POLICY,
17966 NULL, flow_err.message ?
17968 "PORT action validate check fail");
17970 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17972 case RTE_FLOW_ACTION_TYPE_MARK:
17973 ret = flow_dv_validate_action_mark(dev, act,
17977 return -rte_mtr_error_set(error,
17979 RTE_MTR_ERROR_TYPE_METER_POLICY,
17980 NULL, flow_err.message ?
17982 "Mark action validate check fail");
17983 if (dev_conf->dv_xmeta_en !=
17984 MLX5_XMETA_MODE_LEGACY)
17985 return -rte_mtr_error_set(error,
17987 RTE_MTR_ERROR_TYPE_METER_POLICY,
17988 NULL, "Extend MARK action is "
17989 "not supported. Please try use "
17990 "default policy for meter.");
17991 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17994 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17995 ret = flow_dv_validate_action_set_tag(dev,
17996 act, action_flags[i],
17999 return -rte_mtr_error_set(error,
18001 RTE_MTR_ERROR_TYPE_METER_POLICY,
18002 NULL, flow_err.message ?
18004 "Set tag action validate check fail");
18005 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
18008 case RTE_FLOW_ACTION_TYPE_DROP:
18009 ret = mlx5_flow_validate_action_drop
18010 (action_flags[i], attr, &flow_err);
18012 return -rte_mtr_error_set(error,
18014 RTE_MTR_ERROR_TYPE_METER_POLICY,
18015 NULL, flow_err.message ?
18017 "Drop action validate check fail");
18018 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
18021 case RTE_FLOW_ACTION_TYPE_QUEUE:
18023 * Check whether extensive
18024 * metadata feature is engaged.
18026 if (dev_conf->dv_flow_en &&
18027 (dev_conf->dv_xmeta_en !=
18028 MLX5_XMETA_MODE_LEGACY) &&
18029 mlx5_flow_ext_mreg_supported(dev))
18030 return -rte_mtr_error_set(error,
18032 RTE_MTR_ERROR_TYPE_METER_POLICY,
18033 NULL, "Queue action with meta "
18034 "is not supported. Please try use "
18035 "default policy for meter.");
18036 ret = mlx5_flow_validate_action_queue(act,
18037 action_flags[i], dev,
18040 return -rte_mtr_error_set(error,
18042 RTE_MTR_ERROR_TYPE_METER_POLICY,
18043 NULL, flow_err.message ?
18045 "Queue action validate check fail");
18046 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
18049 case RTE_FLOW_ACTION_TYPE_RSS:
18050 if (dev_conf->dv_flow_en &&
18051 (dev_conf->dv_xmeta_en !=
18052 MLX5_XMETA_MODE_LEGACY) &&
18053 mlx5_flow_ext_mreg_supported(dev))
18054 return -rte_mtr_error_set(error,
18056 RTE_MTR_ERROR_TYPE_METER_POLICY,
18057 NULL, "RSS action with meta "
18058 "is not supported. Please try use "
18059 "default policy for meter.");
18060 ret = mlx5_validate_action_rss(dev, act,
18063 return -rte_mtr_error_set(error,
18065 RTE_MTR_ERROR_TYPE_METER_POLICY,
18066 NULL, flow_err.message ?
18068 "RSS action validate check fail");
18069 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
18071 /* Either G or Y will set the RSS. */
18072 rss_color[i] = act->conf;
18074 case RTE_FLOW_ACTION_TYPE_JUMP:
18075 ret = flow_dv_validate_action_jump(dev,
18076 NULL, act, action_flags[i],
18077 attr, true, &flow_err);
18079 return -rte_mtr_error_set(error,
18081 RTE_MTR_ERROR_TYPE_METER_POLICY,
18082 NULL, flow_err.message ?
18084 "Jump action validate check fail");
18086 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
18089 * Only the last meter in the hierarchy will support
18090 * the YELLOW color steering. Then in the meter policy
18091 * actions list, there should be no other meter inside.
18093 case RTE_FLOW_ACTION_TYPE_METER:
18094 if (i != RTE_COLOR_GREEN)
18095 return -rte_mtr_error_set(error,
18097 RTE_MTR_ERROR_TYPE_METER_POLICY,
18099 "Meter hierarchy only supports GREEN color.");
18100 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
18101 return -rte_mtr_error_set(error,
18103 RTE_MTR_ERROR_TYPE_METER_POLICY,
18105 "No yellow policy should be provided in meter hierarchy.");
18107 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18117 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18120 return -rte_mtr_error_set(error, ENOTSUP,
18121 RTE_MTR_ERROR_TYPE_METER_POLICY,
18123 "Doesn't support optional action");
18126 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18127 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18128 } else if ((action_flags[i] &
18129 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18130 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18132 * Only support MLX5_XMETA_MODE_LEGACY
18133 * so MARK action is only in ingress domain.
18135 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18137 domain_color[i] = def_domain;
18138 if (action_flags[i] &&
18139 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18141 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18143 if (action_flags[i] &
18144 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18145 domain_color[i] &= hierarchy_domain;
18147 * Non-termination actions only support NIC Tx domain.
18148 * The adjustion should be skipped when there is no
18149 * action or only END is provided. The default domains
18150 * bit-mask is set to find the MIN intersection.
18151 * The action flags checking should also be skipped.
18153 if ((def_green && i == RTE_COLOR_GREEN) ||
18154 (def_yellow && i == RTE_COLOR_YELLOW))
18157 * Validate the drop action mutual exclusion
18158 * with other actions. Drop action is mutually-exclusive
18159 * with any other action, except for Count action.
18161 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18162 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18163 return -rte_mtr_error_set(error, ENOTSUP,
18164 RTE_MTR_ERROR_TYPE_METER_POLICY,
18165 NULL, "Drop action is mutually-exclusive "
18166 "with any other action");
18168 /* Eswitch has few restrictions on using items and actions */
18169 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18170 if (!mlx5_flow_ext_mreg_supported(dev) &&
18171 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18172 return -rte_mtr_error_set(error, ENOTSUP,
18173 RTE_MTR_ERROR_TYPE_METER_POLICY,
18174 NULL, "unsupported action MARK");
18175 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18176 return -rte_mtr_error_set(error, ENOTSUP,
18177 RTE_MTR_ERROR_TYPE_METER_POLICY,
18178 NULL, "unsupported action QUEUE");
18179 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18180 return -rte_mtr_error_set(error, ENOTSUP,
18181 RTE_MTR_ERROR_TYPE_METER_POLICY,
18182 NULL, "unsupported action RSS");
18183 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18184 return -rte_mtr_error_set(error, ENOTSUP,
18185 RTE_MTR_ERROR_TYPE_METER_POLICY,
18186 NULL, "no fate action is found");
18188 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18189 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18190 if ((domain_color[i] &
18191 MLX5_MTR_DOMAIN_EGRESS_BIT))
18193 MLX5_MTR_DOMAIN_EGRESS_BIT;
18195 return -rte_mtr_error_set(error,
18197 RTE_MTR_ERROR_TYPE_METER_POLICY,
18199 "no fate action is found");
18203 /* If both colors have RSS, the attributes should be the same. */
18204 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18205 rss_color[RTE_COLOR_YELLOW]))
18206 return -rte_mtr_error_set(error, EINVAL,
18207 RTE_MTR_ERROR_TYPE_METER_POLICY,
18208 NULL, "policy RSS attr conflict");
18209 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18211 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18212 if (!def_green && !def_yellow &&
18213 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18214 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18215 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18216 return -rte_mtr_error_set(error, EINVAL,
18217 RTE_MTR_ERROR_TYPE_METER_POLICY,
18218 NULL, "policy domains conflict");
18220 * At least one color policy is listed in the actions, the domains
18221 * to be supported should be the intersection.
18223 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18224 domain_color[RTE_COLOR_YELLOW];
18229 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18231 struct mlx5_priv *priv = dev->data->dev_private;
18234 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18235 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18240 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18241 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18245 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18246 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18254 * Discover the number of available flow priorities
18255 * by trying to create a flow with the highest priority value
18256 * for each possible number.
18261 * List of possible number of available priorities.
18262 * @param[in] vprio_n
18263 * Size of @p vprio array.
18265 * On success, number of available flow priorities.
18266 * On failure, a negative errno-style code and rte_errno is set.
18269 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18270 const uint16_t *vprio, int vprio_n)
18272 struct mlx5_priv *priv = dev->data->dev_private;
18273 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18274 struct rte_flow_item_eth eth;
18275 struct rte_flow_item item = {
18276 .type = RTE_FLOW_ITEM_TYPE_ETH,
18280 struct mlx5_flow_dv_matcher matcher = {
18282 .size = sizeof(matcher.mask.buf),
18285 union mlx5_flow_tbl_key tbl_key;
18286 struct mlx5_flow flow;
18288 struct rte_flow_error error;
18290 int i, err, ret = -ENOTSUP;
18293 * Prepare a flow with a catch-all pattern and a drop action.
18294 * Use drop queue, because shared drop action may be unavailable.
18296 action = priv->drop_queue.hrxq->action;
18297 if (action == NULL) {
18298 DRV_LOG(ERR, "Priority discovery requires a drop action");
18299 rte_errno = ENOTSUP;
18302 memset(&flow, 0, sizeof(flow));
18303 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18304 if (flow.handle == NULL) {
18305 DRV_LOG(ERR, "Cannot create flow handle");
18306 rte_errno = ENOMEM;
18309 flow.ingress = true;
18310 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18311 flow.dv.actions[0] = action;
18312 flow.dv.actions_n = 1;
18313 memset(ð, 0, sizeof(eth));
18314 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18315 &item, /* inner */ false, /* group */ 0);
18316 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18317 for (i = 0; i < vprio_n; i++) {
18318 /* Configure the next proposed maximum priority. */
18319 matcher.priority = vprio[i] - 1;
18320 memset(&tbl_key, 0, sizeof(tbl_key));
18321 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18326 /* This action is pure SW and must always succeed. */
18327 DRV_LOG(ERR, "Cannot register matcher");
18331 /* Try to apply the flow to HW. */
18332 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18333 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18334 err = mlx5_flow_os_create_flow
18335 (flow.handle->dvh.matcher->matcher_object,
18336 (void *)&flow.dv.value, flow.dv.actions_n,
18337 flow.dv.actions, &flow.handle->drv_flow);
18339 claim_zero(mlx5_flow_os_destroy_flow
18340 (flow.handle->drv_flow));
18341 flow.handle->drv_flow = NULL;
18343 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18348 mlx5_ipool_free(pool, flow.handle_idx);
18349 /* Set rte_errno if no expected priority value matched. */
18355 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18356 .validate = flow_dv_validate,
18357 .prepare = flow_dv_prepare,
18358 .translate = flow_dv_translate,
18359 .apply = flow_dv_apply,
18360 .remove = flow_dv_remove,
18361 .destroy = flow_dv_destroy,
18362 .query = flow_dv_query,
18363 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18364 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18365 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18366 .create_meter = flow_dv_mtr_alloc,
18367 .free_meter = flow_dv_aso_mtr_release_to_pool,
18368 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18369 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18370 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18371 .create_policy_rules = flow_dv_create_policy_rules,
18372 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18373 .create_def_policy = flow_dv_create_def_policy,
18374 .destroy_def_policy = flow_dv_destroy_def_policy,
18375 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18376 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18377 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18378 .counter_alloc = flow_dv_counter_allocate,
18379 .counter_free = flow_dv_counter_free,
18380 .counter_query = flow_dv_counter_query,
18381 .get_aged_flows = flow_dv_get_aged_flows,
18382 .action_validate = flow_dv_action_validate,
18383 .action_create = flow_dv_action_create,
18384 .action_destroy = flow_dv_action_destroy,
18385 .action_update = flow_dv_action_update,
18386 .action_query = flow_dv_action_query,
18387 .sync_domain = flow_dv_sync_domain,
18388 .discover_priorities = flow_dv_discover_priorities,
18389 .item_create = flow_dv_item_create,
18390 .item_release = flow_dv_item_release,
18393 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */