1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36 #include "rte_pmd_mlx5.h"
38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
44 #ifndef HAVE_MLX5DV_DR_ESWITCH
45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
50 #ifndef HAVE_MLX5DV_DR
51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
54 /* VLAN header definitions */
55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
75 struct mlx5_flow_tbl_resource *tbl);
78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
79 uint32_t encap_decap_idx);
82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
92 * Initialize flow attributes structure according to flow items' types.
94 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
95 * mode. For tunnel mode, the items to be modified are the outermost ones.
98 * Pointer to item specification.
100 * Pointer to flow attributes structure.
101 * @param[in] dev_flow
102 * Pointer to the sub flow.
103 * @param[in] tunnel_decap
104 * Whether action is after tunnel decapsulation.
107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
108 struct mlx5_flow *dev_flow, bool tunnel_decap)
110 uint64_t layers = dev_flow->handle->layers;
113 * If layers is already initialized, it means this dev_flow is the
114 * suffix flow, the layers flags is set by the prefix flow. Need to
115 * use the layer flags from prefix flow as the suffix flow may not
116 * have the user defined items as the flow is split.
119 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
121 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
123 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
125 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
130 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
131 uint8_t next_protocol = 0xff;
132 switch (item->type) {
133 case RTE_FLOW_ITEM_TYPE_GRE:
134 case RTE_FLOW_ITEM_TYPE_NVGRE:
135 case RTE_FLOW_ITEM_TYPE_VXLAN:
136 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
137 case RTE_FLOW_ITEM_TYPE_GENEVE:
138 case RTE_FLOW_ITEM_TYPE_MPLS:
142 case RTE_FLOW_ITEM_TYPE_IPV4:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv4 *)
147 item->mask)->hdr.next_proto_id)
149 ((const struct rte_flow_item_ipv4 *)
150 (item->spec))->hdr.next_proto_id &
151 ((const struct rte_flow_item_ipv4 *)
152 (item->mask))->hdr.next_proto_id;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_IPV6:
160 if (item->mask != NULL &&
161 ((const struct rte_flow_item_ipv6 *)
162 item->mask)->hdr.proto)
164 ((const struct rte_flow_item_ipv6 *)
165 (item->spec))->hdr.proto &
166 ((const struct rte_flow_item_ipv6 *)
167 (item->mask))->hdr.proto;
168 if ((next_protocol == IPPROTO_IPIP ||
169 next_protocol == IPPROTO_IPV6) && tunnel_decap)
172 case RTE_FLOW_ITEM_TYPE_UDP:
176 case RTE_FLOW_ITEM_TYPE_TCP:
188 * Convert rte_mtr_color to mlx5 color.
197 rte_col_2_mlx5_col(enum rte_color rcol)
200 case RTE_COLOR_GREEN:
201 return MLX5_FLOW_COLOR_GREEN;
202 case RTE_COLOR_YELLOW:
203 return MLX5_FLOW_COLOR_YELLOW;
205 return MLX5_FLOW_COLOR_RED;
209 return MLX5_FLOW_COLOR_UNDEFINED;
212 struct field_modify_info {
213 uint32_t size; /* Size of field in protocol header, in bytes. */
214 uint32_t offset; /* Offset of field in protocol header, in bytes. */
215 enum mlx5_modification_field id;
218 struct field_modify_info modify_eth[] = {
219 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
220 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
221 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
222 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
226 struct field_modify_info modify_vlan_out_first_vid[] = {
227 /* Size in bits !!! */
228 {12, 0, MLX5_MODI_OUT_FIRST_VID},
232 struct field_modify_info modify_ipv4[] = {
233 {1, 1, MLX5_MODI_OUT_IP_DSCP},
234 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
235 {4, 12, MLX5_MODI_OUT_SIPV4},
236 {4, 16, MLX5_MODI_OUT_DIPV4},
240 struct field_modify_info modify_ipv6[] = {
241 {1, 0, MLX5_MODI_OUT_IP_DSCP},
242 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
243 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
244 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
245 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
246 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
247 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
248 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
249 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
250 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
254 struct field_modify_info modify_udp[] = {
255 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
256 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
260 struct field_modify_info modify_tcp[] = {
261 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
262 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
263 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
264 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
270 uint8_t next_protocol, uint64_t *item_flags,
273 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
274 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
275 if (next_protocol == IPPROTO_IPIP) {
276 *item_flags |= MLX5_FLOW_LAYER_IPIP;
279 if (next_protocol == IPPROTO_IPV6) {
280 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
285 /* Update VLAN's VID/PCP based on input rte_flow_action.
288 * Pointer to struct rte_flow_action.
290 * Pointer to struct rte_vlan_hdr.
293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
294 struct rte_vlan_hdr *vlan)
297 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
299 ((const struct rte_flow_action_of_set_vlan_pcp *)
300 action->conf)->vlan_pcp;
301 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
302 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
303 vlan->vlan_tci |= vlan_tci;
304 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
305 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
306 vlan->vlan_tci |= rte_be_to_cpu_16
307 (((const struct rte_flow_action_of_set_vlan_vid *)
308 action->conf)->vlan_vid);
313 * Fetch 1, 2, 3 or 4 byte field from the byte array
314 * and return as unsigned integer in host-endian format.
317 * Pointer to data array.
319 * Size of field to extract.
322 * converted field in host endian format.
324 static inline uint32_t
325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
334 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
337 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
338 ret = (ret << 8) | *(data + sizeof(uint16_t));
341 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
352 * Convert modify-header action to DV specification.
354 * Data length of each action is determined by provided field description
355 * and the item mask. Data bit offset and width of each action is determined
356 * by provided item mask.
359 * Pointer to item specification.
361 * Pointer to field modification information.
362 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
363 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
364 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
366 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
367 * Negative offset value sets the same offset as source offset.
368 * size field is ignored, value is taken from source field.
369 * @param[in,out] resource
370 * Pointer to the modify-header resource.
372 * Type of modification.
374 * Pointer to the error structure.
377 * 0 on success, a negative errno value otherwise and rte_errno is set.
380 flow_dv_convert_modify_action(struct rte_flow_item *item,
381 struct field_modify_info *field,
382 struct field_modify_info *dcopy,
383 struct mlx5_flow_dv_modify_hdr_resource *resource,
384 uint32_t type, struct rte_flow_error *error)
386 uint32_t i = resource->actions_num;
387 struct mlx5_modification_cmd *actions = resource->actions;
390 * The item and mask are provided in big-endian format.
391 * The fields should be presented as in big-endian format either.
392 * Mask must be always present, it defines the actual field width.
394 MLX5_ASSERT(item->mask);
395 MLX5_ASSERT(field->size);
402 if (i >= MLX5_MAX_MODIFY_NUM)
403 return rte_flow_error_set(error, EINVAL,
404 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
405 "too many items to modify");
406 /* Fetch variable byte size mask from the array. */
407 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
408 field->offset, field->size);
413 /* Deduce actual data width in bits from mask value. */
414 off_b = rte_bsf32(mask);
415 size_b = sizeof(uint32_t) * CHAR_BIT -
416 off_b - __builtin_clz(mask);
418 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
419 actions[i] = (struct mlx5_modification_cmd) {
425 /* Convert entire record to expected big-endian format. */
426 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
427 if (type == MLX5_MODIFICATION_TYPE_COPY) {
429 actions[i].dst_field = dcopy->id;
430 actions[i].dst_offset =
431 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
432 /* Convert entire record to big-endian format. */
433 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
436 MLX5_ASSERT(item->spec);
437 data = flow_dv_fetch_field((const uint8_t *)item->spec +
438 field->offset, field->size);
439 /* Shift out the trailing masked bits from data. */
440 data = (data & mask) >> off_b;
441 actions[i].data1 = rte_cpu_to_be_32(data);
445 } while (field->size);
446 if (resource->actions_num == i)
447 return rte_flow_error_set(error, EINVAL,
448 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
449 "invalid modification flow item");
450 resource->actions_num = i;
455 * Convert modify-header set IPv4 address action to DV specification.
457 * @param[in,out] resource
458 * Pointer to the modify-header resource.
460 * Pointer to action specification.
462 * Pointer to the error structure.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 flow_dv_convert_action_modify_ipv4
469 (struct mlx5_flow_dv_modify_hdr_resource *resource,
470 const struct rte_flow_action *action,
471 struct rte_flow_error *error)
473 const struct rte_flow_action_set_ipv4 *conf =
474 (const struct rte_flow_action_set_ipv4 *)(action->conf);
475 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
476 struct rte_flow_item_ipv4 ipv4;
477 struct rte_flow_item_ipv4 ipv4_mask;
479 memset(&ipv4, 0, sizeof(ipv4));
480 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
481 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
482 ipv4.hdr.src_addr = conf->ipv4_addr;
483 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
485 ipv4.hdr.dst_addr = conf->ipv4_addr;
486 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
489 item.mask = &ipv4_mask;
490 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
491 MLX5_MODIFICATION_TYPE_SET, error);
495 * Convert modify-header set IPv6 address action to DV specification.
497 * @param[in,out] resource
498 * Pointer to the modify-header resource.
500 * Pointer to action specification.
502 * Pointer to the error structure.
505 * 0 on success, a negative errno value otherwise and rte_errno is set.
508 flow_dv_convert_action_modify_ipv6
509 (struct mlx5_flow_dv_modify_hdr_resource *resource,
510 const struct rte_flow_action *action,
511 struct rte_flow_error *error)
513 const struct rte_flow_action_set_ipv6 *conf =
514 (const struct rte_flow_action_set_ipv6 *)(action->conf);
515 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
516 struct rte_flow_item_ipv6 ipv6;
517 struct rte_flow_item_ipv6 ipv6_mask;
519 memset(&ipv6, 0, sizeof(ipv6));
520 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
521 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
522 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
523 sizeof(ipv6.hdr.src_addr));
524 memcpy(&ipv6_mask.hdr.src_addr,
525 &rte_flow_item_ipv6_mask.hdr.src_addr,
526 sizeof(ipv6.hdr.src_addr));
528 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
529 sizeof(ipv6.hdr.dst_addr));
530 memcpy(&ipv6_mask.hdr.dst_addr,
531 &rte_flow_item_ipv6_mask.hdr.dst_addr,
532 sizeof(ipv6.hdr.dst_addr));
535 item.mask = &ipv6_mask;
536 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
537 MLX5_MODIFICATION_TYPE_SET, error);
541 * Convert modify-header set MAC address action to DV specification.
543 * @param[in,out] resource
544 * Pointer to the modify-header resource.
546 * Pointer to action specification.
548 * Pointer to the error structure.
551 * 0 on success, a negative errno value otherwise and rte_errno is set.
554 flow_dv_convert_action_modify_mac
555 (struct mlx5_flow_dv_modify_hdr_resource *resource,
556 const struct rte_flow_action *action,
557 struct rte_flow_error *error)
559 const struct rte_flow_action_set_mac *conf =
560 (const struct rte_flow_action_set_mac *)(action->conf);
561 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
562 struct rte_flow_item_eth eth;
563 struct rte_flow_item_eth eth_mask;
565 memset(ð, 0, sizeof(eth));
566 memset(ð_mask, 0, sizeof(eth_mask));
567 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
568 memcpy(ð.src.addr_bytes, &conf->mac_addr,
569 sizeof(eth.src.addr_bytes));
570 memcpy(ð_mask.src.addr_bytes,
571 &rte_flow_item_eth_mask.src.addr_bytes,
572 sizeof(eth_mask.src.addr_bytes));
574 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
575 sizeof(eth.dst.addr_bytes));
576 memcpy(ð_mask.dst.addr_bytes,
577 &rte_flow_item_eth_mask.dst.addr_bytes,
578 sizeof(eth_mask.dst.addr_bytes));
581 item.mask = ð_mask;
582 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
583 MLX5_MODIFICATION_TYPE_SET, error);
587 * Convert modify-header set VLAN VID action to DV specification.
589 * @param[in,out] resource
590 * Pointer to the modify-header resource.
592 * Pointer to action specification.
594 * Pointer to the error structure.
597 * 0 on success, a negative errno value otherwise and rte_errno is set.
600 flow_dv_convert_action_modify_vlan_vid
601 (struct mlx5_flow_dv_modify_hdr_resource *resource,
602 const struct rte_flow_action *action,
603 struct rte_flow_error *error)
605 const struct rte_flow_action_of_set_vlan_vid *conf =
606 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
607 int i = resource->actions_num;
608 struct mlx5_modification_cmd *actions = resource->actions;
609 struct field_modify_info *field = modify_vlan_out_first_vid;
611 if (i >= MLX5_MAX_MODIFY_NUM)
612 return rte_flow_error_set(error, EINVAL,
613 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
614 "too many items to modify");
615 actions[i] = (struct mlx5_modification_cmd) {
616 .action_type = MLX5_MODIFICATION_TYPE_SET,
618 .length = field->size,
619 .offset = field->offset,
621 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
622 actions[i].data1 = conf->vlan_vid;
623 actions[i].data1 = actions[i].data1 << 16;
624 resource->actions_num = ++i;
629 * Convert modify-header set TP action to DV specification.
631 * @param[in,out] resource
632 * Pointer to the modify-header resource.
634 * Pointer to action specification.
636 * Pointer to rte_flow_item objects list.
638 * Pointer to flow attributes structure.
639 * @param[in] dev_flow
640 * Pointer to the sub flow.
641 * @param[in] tunnel_decap
642 * Whether action is after tunnel decapsulation.
644 * Pointer to the error structure.
647 * 0 on success, a negative errno value otherwise and rte_errno is set.
650 flow_dv_convert_action_modify_tp
651 (struct mlx5_flow_dv_modify_hdr_resource *resource,
652 const struct rte_flow_action *action,
653 const struct rte_flow_item *items,
654 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
655 bool tunnel_decap, struct rte_flow_error *error)
657 const struct rte_flow_action_set_tp *conf =
658 (const struct rte_flow_action_set_tp *)(action->conf);
659 struct rte_flow_item item;
660 struct rte_flow_item_udp udp;
661 struct rte_flow_item_udp udp_mask;
662 struct rte_flow_item_tcp tcp;
663 struct rte_flow_item_tcp tcp_mask;
664 struct field_modify_info *field;
667 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
669 memset(&udp, 0, sizeof(udp));
670 memset(&udp_mask, 0, sizeof(udp_mask));
671 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
672 udp.hdr.src_port = conf->port;
673 udp_mask.hdr.src_port =
674 rte_flow_item_udp_mask.hdr.src_port;
676 udp.hdr.dst_port = conf->port;
677 udp_mask.hdr.dst_port =
678 rte_flow_item_udp_mask.hdr.dst_port;
680 item.type = RTE_FLOW_ITEM_TYPE_UDP;
682 item.mask = &udp_mask;
685 MLX5_ASSERT(attr->tcp);
686 memset(&tcp, 0, sizeof(tcp));
687 memset(&tcp_mask, 0, sizeof(tcp_mask));
688 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
689 tcp.hdr.src_port = conf->port;
690 tcp_mask.hdr.src_port =
691 rte_flow_item_tcp_mask.hdr.src_port;
693 tcp.hdr.dst_port = conf->port;
694 tcp_mask.hdr.dst_port =
695 rte_flow_item_tcp_mask.hdr.dst_port;
697 item.type = RTE_FLOW_ITEM_TYPE_TCP;
699 item.mask = &tcp_mask;
702 return flow_dv_convert_modify_action(&item, field, NULL, resource,
703 MLX5_MODIFICATION_TYPE_SET, error);
707 * Convert modify-header set TTL action to DV specification.
709 * @param[in,out] resource
710 * Pointer to the modify-header resource.
712 * Pointer to action specification.
714 * Pointer to rte_flow_item objects list.
716 * Pointer to flow attributes structure.
717 * @param[in] dev_flow
718 * Pointer to the sub flow.
719 * @param[in] tunnel_decap
720 * Whether action is after tunnel decapsulation.
722 * Pointer to the error structure.
725 * 0 on success, a negative errno value otherwise and rte_errno is set.
728 flow_dv_convert_action_modify_ttl
729 (struct mlx5_flow_dv_modify_hdr_resource *resource,
730 const struct rte_flow_action *action,
731 const struct rte_flow_item *items,
732 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
733 bool tunnel_decap, struct rte_flow_error *error)
735 const struct rte_flow_action_set_ttl *conf =
736 (const struct rte_flow_action_set_ttl *)(action->conf);
737 struct rte_flow_item item;
738 struct rte_flow_item_ipv4 ipv4;
739 struct rte_flow_item_ipv4 ipv4_mask;
740 struct rte_flow_item_ipv6 ipv6;
741 struct rte_flow_item_ipv6 ipv6_mask;
742 struct field_modify_info *field;
745 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
747 memset(&ipv4, 0, sizeof(ipv4));
748 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
749 ipv4.hdr.time_to_live = conf->ttl_value;
750 ipv4_mask.hdr.time_to_live = 0xFF;
751 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
753 item.mask = &ipv4_mask;
756 MLX5_ASSERT(attr->ipv6);
757 memset(&ipv6, 0, sizeof(ipv6));
758 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
759 ipv6.hdr.hop_limits = conf->ttl_value;
760 ipv6_mask.hdr.hop_limits = 0xFF;
761 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
763 item.mask = &ipv6_mask;
766 return flow_dv_convert_modify_action(&item, field, NULL, resource,
767 MLX5_MODIFICATION_TYPE_SET, error);
771 * Convert modify-header decrement TTL action to DV specification.
773 * @param[in,out] resource
774 * Pointer to the modify-header resource.
776 * Pointer to action specification.
778 * Pointer to rte_flow_item objects list.
780 * Pointer to flow attributes structure.
781 * @param[in] dev_flow
782 * Pointer to the sub flow.
783 * @param[in] tunnel_decap
784 * Whether action is after tunnel decapsulation.
786 * Pointer to the error structure.
789 * 0 on success, a negative errno value otherwise and rte_errno is set.
792 flow_dv_convert_action_modify_dec_ttl
793 (struct mlx5_flow_dv_modify_hdr_resource *resource,
794 const struct rte_flow_item *items,
795 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
796 bool tunnel_decap, struct rte_flow_error *error)
798 struct rte_flow_item item;
799 struct rte_flow_item_ipv4 ipv4;
800 struct rte_flow_item_ipv4 ipv4_mask;
801 struct rte_flow_item_ipv6 ipv6;
802 struct rte_flow_item_ipv6 ipv6_mask;
803 struct field_modify_info *field;
806 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
808 memset(&ipv4, 0, sizeof(ipv4));
809 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
810 ipv4.hdr.time_to_live = 0xFF;
811 ipv4_mask.hdr.time_to_live = 0xFF;
812 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
814 item.mask = &ipv4_mask;
817 MLX5_ASSERT(attr->ipv6);
818 memset(&ipv6, 0, sizeof(ipv6));
819 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
820 ipv6.hdr.hop_limits = 0xFF;
821 ipv6_mask.hdr.hop_limits = 0xFF;
822 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
824 item.mask = &ipv6_mask;
827 return flow_dv_convert_modify_action(&item, field, NULL, resource,
828 MLX5_MODIFICATION_TYPE_ADD, error);
832 * Convert modify-header increment/decrement TCP Sequence number
833 * to DV specification.
835 * @param[in,out] resource
836 * Pointer to the modify-header resource.
838 * Pointer to action specification.
840 * Pointer to the error structure.
843 * 0 on success, a negative errno value otherwise and rte_errno is set.
846 flow_dv_convert_action_modify_tcp_seq
847 (struct mlx5_flow_dv_modify_hdr_resource *resource,
848 const struct rte_flow_action *action,
849 struct rte_flow_error *error)
851 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
852 uint64_t value = rte_be_to_cpu_32(*conf);
853 struct rte_flow_item item;
854 struct rte_flow_item_tcp tcp;
855 struct rte_flow_item_tcp tcp_mask;
857 memset(&tcp, 0, sizeof(tcp));
858 memset(&tcp_mask, 0, sizeof(tcp_mask));
859 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
861 * The HW has no decrement operation, only increment operation.
862 * To simulate decrement X from Y using increment operation
863 * we need to add UINT32_MAX X times to Y.
864 * Each adding of UINT32_MAX decrements Y by 1.
867 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
868 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
869 item.type = RTE_FLOW_ITEM_TYPE_TCP;
871 item.mask = &tcp_mask;
872 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
873 MLX5_MODIFICATION_TYPE_ADD, error);
877 * Convert modify-header increment/decrement TCP Acknowledgment number
878 * to DV specification.
880 * @param[in,out] resource
881 * Pointer to the modify-header resource.
883 * Pointer to action specification.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_tcp_ack
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_action *action,
894 struct rte_flow_error *error)
896 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
897 uint64_t value = rte_be_to_cpu_32(*conf);
898 struct rte_flow_item item;
899 struct rte_flow_item_tcp tcp;
900 struct rte_flow_item_tcp tcp_mask;
902 memset(&tcp, 0, sizeof(tcp));
903 memset(&tcp_mask, 0, sizeof(tcp_mask));
904 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
906 * The HW has no decrement operation, only increment operation.
907 * To simulate decrement X from Y using increment operation
908 * we need to add UINT32_MAX X times to Y.
909 * Each adding of UINT32_MAX decrements Y by 1.
912 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
913 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
914 item.type = RTE_FLOW_ITEM_TYPE_TCP;
916 item.mask = &tcp_mask;
917 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
918 MLX5_MODIFICATION_TYPE_ADD, error);
921 static enum mlx5_modification_field reg_to_field[] = {
922 [REG_NON] = MLX5_MODI_OUT_NONE,
923 [REG_A] = MLX5_MODI_META_DATA_REG_A,
924 [REG_B] = MLX5_MODI_META_DATA_REG_B,
925 [REG_C_0] = MLX5_MODI_META_REG_C_0,
926 [REG_C_1] = MLX5_MODI_META_REG_C_1,
927 [REG_C_2] = MLX5_MODI_META_REG_C_2,
928 [REG_C_3] = MLX5_MODI_META_REG_C_3,
929 [REG_C_4] = MLX5_MODI_META_REG_C_4,
930 [REG_C_5] = MLX5_MODI_META_REG_C_5,
931 [REG_C_6] = MLX5_MODI_META_REG_C_6,
932 [REG_C_7] = MLX5_MODI_META_REG_C_7,
936 * Convert register set to DV specification.
938 * @param[in,out] resource
939 * Pointer to the modify-header resource.
941 * Pointer to action specification.
943 * Pointer to the error structure.
946 * 0 on success, a negative errno value otherwise and rte_errno is set.
949 flow_dv_convert_action_set_reg
950 (struct mlx5_flow_dv_modify_hdr_resource *resource,
951 const struct rte_flow_action *action,
952 struct rte_flow_error *error)
954 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
955 struct mlx5_modification_cmd *actions = resource->actions;
956 uint32_t i = resource->actions_num;
958 if (i >= MLX5_MAX_MODIFY_NUM)
959 return rte_flow_error_set(error, EINVAL,
960 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
961 "too many items to modify");
962 MLX5_ASSERT(conf->id != REG_NON);
963 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
964 actions[i] = (struct mlx5_modification_cmd) {
965 .action_type = MLX5_MODIFICATION_TYPE_SET,
966 .field = reg_to_field[conf->id],
968 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
969 actions[i].data1 = rte_cpu_to_be_32(conf->data);
971 resource->actions_num = i;
976 * Convert SET_TAG action to DV specification.
979 * Pointer to the rte_eth_dev structure.
980 * @param[in,out] resource
981 * Pointer to the modify-header resource.
983 * Pointer to action specification.
985 * Pointer to the error structure.
988 * 0 on success, a negative errno value otherwise and rte_errno is set.
991 flow_dv_convert_action_set_tag
992 (struct rte_eth_dev *dev,
993 struct mlx5_flow_dv_modify_hdr_resource *resource,
994 const struct rte_flow_action_set_tag *conf,
995 struct rte_flow_error *error)
997 rte_be32_t data = rte_cpu_to_be_32(conf->data);
998 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
999 struct rte_flow_item item = {
1003 struct field_modify_info reg_c_x[] = {
1006 enum mlx5_modification_field reg_type;
1009 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1012 MLX5_ASSERT(ret != REG_NON);
1013 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014 reg_type = reg_to_field[ret];
1015 MLX5_ASSERT(reg_type > 0);
1016 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018 MLX5_MODIFICATION_TYPE_SET, error);
1022 * Convert internal COPY_REG action to DV specification.
1025 * Pointer to the rte_eth_dev structure.
1026 * @param[in,out] res
1027 * Pointer to the modify-header resource.
1029 * Pointer to action specification.
1031 * Pointer to the error structure.
1034 * 0 on success, a negative errno value otherwise and rte_errno is set.
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038 struct mlx5_flow_dv_modify_hdr_resource *res,
1039 const struct rte_flow_action *action,
1040 struct rte_flow_error *error)
1042 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044 struct rte_flow_item item = {
1048 struct field_modify_info reg_src[] = {
1049 {4, 0, reg_to_field[conf->src]},
1052 struct field_modify_info reg_dst = {
1054 .id = reg_to_field[conf->dst],
1056 /* Adjust reg_c[0] usage according to reported mask. */
1057 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058 struct mlx5_priv *priv = dev->data->dev_private;
1059 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1061 MLX5_ASSERT(reg_c0);
1062 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063 if (conf->dst == REG_C_0) {
1064 /* Copy to reg_c[0], within mask only. */
1065 reg_dst.offset = rte_bsf32(reg_c0);
1067 * Mask is ignoring the enianness, because
1068 * there is no conversion in datapath.
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071 /* Copy from destination lower bits to reg_c[0]. */
1072 mask = reg_c0 >> reg_dst.offset;
1074 /* Copy from destination upper bits to reg_c[0]. */
1075 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076 rte_fls_u32(reg_c0));
1079 mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081 /* Copy from reg_c[0] to destination lower bits. */
1084 /* Copy from reg_c[0] to destination upper bits. */
1085 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086 (rte_fls_u32(reg_c0) -
1091 return flow_dv_convert_modify_action(&item,
1092 reg_src, ®_dst, res,
1093 MLX5_MODIFICATION_TYPE_COPY,
1098 * Convert MARK action to DV specification. This routine is used
1099 * in extensive metadata only and requires metadata register to be
1100 * handled. In legacy mode hardware tag resource is engaged.
1103 * Pointer to the rte_eth_dev structure.
1105 * Pointer to MARK action specification.
1106 * @param[in,out] resource
1107 * Pointer to the modify-header resource.
1109 * Pointer to the error structure.
1112 * 0 on success, a negative errno value otherwise and rte_errno is set.
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116 const struct rte_flow_action_mark *conf,
1117 struct mlx5_flow_dv_modify_hdr_resource *resource,
1118 struct rte_flow_error *error)
1120 struct mlx5_priv *priv = dev->data->dev_private;
1121 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122 priv->sh->dv_mark_mask);
1123 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124 struct rte_flow_item item = {
1128 struct field_modify_info reg_c_x[] = {
1134 return rte_flow_error_set(error, EINVAL,
1135 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136 NULL, "zero mark action mask");
1137 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1140 MLX5_ASSERT(reg > 0);
1141 if (reg == REG_C_0) {
1142 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143 uint32_t shl_c0 = rte_bsf32(msk_c0);
1145 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147 mask = rte_cpu_to_be_32(mask << shl_c0);
1149 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151 MLX5_MODIFICATION_TYPE_SET, error);
1155 * Get metadata register index for specified steering domain.
1158 * Pointer to the rte_eth_dev structure.
1160 * Attributes of flow to determine steering domain.
1162 * Pointer to the error structure.
1165 * positive index on success, a negative errno value otherwise
1166 * and rte_errno is set.
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170 const struct rte_flow_attr *attr,
1171 struct rte_flow_error *error)
1174 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178 MLX5_METADATA_RX, 0, error);
1180 return rte_flow_error_set(error,
1181 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182 NULL, "unavailable "
1183 "metadata register");
1188 * Convert SET_META action to DV specification.
1191 * Pointer to the rte_eth_dev structure.
1192 * @param[in,out] resource
1193 * Pointer to the modify-header resource.
1195 * Attributes of flow that includes this item.
1197 * Pointer to action specification.
1199 * Pointer to the error structure.
1202 * 0 on success, a negative errno value otherwise and rte_errno is set.
1205 flow_dv_convert_action_set_meta
1206 (struct rte_eth_dev *dev,
1207 struct mlx5_flow_dv_modify_hdr_resource *resource,
1208 const struct rte_flow_attr *attr,
1209 const struct rte_flow_action_set_meta *conf,
1210 struct rte_flow_error *error)
1212 uint32_t data = conf->data;
1213 uint32_t mask = conf->mask;
1214 struct rte_flow_item item = {
1218 struct field_modify_info reg_c_x[] = {
1221 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225 MLX5_ASSERT(reg != REG_NON);
1227 * In datapath code there is no endianness
1228 * coversions for perfromance reasons, all
1229 * pattern conversions are done in rte_flow.
1231 if (reg == REG_C_0) {
1232 struct mlx5_priv *priv = dev->data->dev_private;
1233 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1236 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238 shl_c0 = rte_bsf32(msk_c0);
1240 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1246 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247 /* The routine expects parameters in memory as big-endian ones. */
1248 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249 MLX5_MODIFICATION_TYPE_SET, error);
1253 * Convert modify-header set IPv4 DSCP action to DV specification.
1255 * @param[in,out] resource
1256 * Pointer to the modify-header resource.
1258 * Pointer to action specification.
1260 * Pointer to the error structure.
1263 * 0 on success, a negative errno value otherwise and rte_errno is set.
1266 flow_dv_convert_action_modify_ipv4_dscp
1267 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268 const struct rte_flow_action *action,
1269 struct rte_flow_error *error)
1271 const struct rte_flow_action_set_dscp *conf =
1272 (const struct rte_flow_action_set_dscp *)(action->conf);
1273 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274 struct rte_flow_item_ipv4 ipv4;
1275 struct rte_flow_item_ipv4 ipv4_mask;
1277 memset(&ipv4, 0, sizeof(ipv4));
1278 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279 ipv4.hdr.type_of_service = conf->dscp;
1280 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1282 item.mask = &ipv4_mask;
1283 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284 MLX5_MODIFICATION_TYPE_SET, error);
1288 * Convert modify-header set IPv6 DSCP action to DV specification.
1290 * @param[in,out] resource
1291 * Pointer to the modify-header resource.
1293 * Pointer to action specification.
1295 * Pointer to the error structure.
1298 * 0 on success, a negative errno value otherwise and rte_errno is set.
1301 flow_dv_convert_action_modify_ipv6_dscp
1302 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303 const struct rte_flow_action *action,
1304 struct rte_flow_error *error)
1306 const struct rte_flow_action_set_dscp *conf =
1307 (const struct rte_flow_action_set_dscp *)(action->conf);
1308 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309 struct rte_flow_item_ipv6 ipv6;
1310 struct rte_flow_item_ipv6 ipv6_mask;
1312 memset(&ipv6, 0, sizeof(ipv6));
1313 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1315 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316 * rdma-core only accept the DSCP bits byte aligned start from
1317 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318 * bits in IPv6 case as rdma-core requires byte aligned value.
1320 ipv6.hdr.vtc_flow = conf->dscp;
1321 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1323 item.mask = &ipv6_mask;
1324 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325 MLX5_MODIFICATION_TYPE_SET, error);
1329 mlx5_flow_field_id_to_modify_info
1330 (const struct rte_flow_action_modify_data *data,
1331 struct field_modify_info *info,
1332 uint32_t *mask, uint32_t *value, uint32_t width,
1333 struct rte_eth_dev *dev,
1334 const struct rte_flow_attr *attr,
1335 struct rte_flow_error *error)
1338 switch (data->field) {
1339 case RTE_FLOW_FIELD_START:
1340 /* not supported yet */
1343 case RTE_FLOW_FIELD_MAC_DST:
1345 if (data->offset < 32) {
1346 info[idx] = (struct field_modify_info){4, 0,
1347 MLX5_MODI_OUT_DMAC_47_16};
1350 rte_cpu_to_be_32(0xffffffff >>
1354 mask[idx] = RTE_BE32(0xffffffff);
1361 info[idx] = (struct field_modify_info){2, 4 * idx,
1362 MLX5_MODI_OUT_DMAC_15_0};
1363 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1366 if (data->offset < 32)
1367 info[idx++] = (struct field_modify_info){4, 0,
1368 MLX5_MODI_OUT_DMAC_47_16};
1369 info[idx] = (struct field_modify_info){2, 0,
1370 MLX5_MODI_OUT_DMAC_15_0};
1373 case RTE_FLOW_FIELD_MAC_SRC:
1375 if (data->offset < 32) {
1376 info[idx] = (struct field_modify_info){4, 0,
1377 MLX5_MODI_OUT_SMAC_47_16};
1380 rte_cpu_to_be_32(0xffffffff >>
1384 mask[idx] = RTE_BE32(0xffffffff);
1391 info[idx] = (struct field_modify_info){2, 4 * idx,
1392 MLX5_MODI_OUT_SMAC_15_0};
1393 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1396 if (data->offset < 32)
1397 info[idx++] = (struct field_modify_info){4, 0,
1398 MLX5_MODI_OUT_SMAC_47_16};
1399 info[idx] = (struct field_modify_info){2, 0,
1400 MLX5_MODI_OUT_SMAC_15_0};
1403 case RTE_FLOW_FIELD_VLAN_TYPE:
1404 /* not supported yet */
1406 case RTE_FLOW_FIELD_VLAN_ID:
1407 info[idx] = (struct field_modify_info){2, 0,
1408 MLX5_MODI_OUT_FIRST_VID};
1410 mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1413 case RTE_FLOW_FIELD_MAC_TYPE:
1414 info[idx] = (struct field_modify_info){2, 0,
1415 MLX5_MODI_OUT_ETHERTYPE};
1417 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1420 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 info[idx] = (struct field_modify_info){1, 0,
1422 MLX5_MODI_OUT_IP_DSCP};
1424 mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1427 case RTE_FLOW_FIELD_IPV4_TTL:
1428 info[idx] = (struct field_modify_info){1, 0,
1429 MLX5_MODI_OUT_IPV4_TTL};
1431 mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1434 case RTE_FLOW_FIELD_IPV4_SRC:
1435 info[idx] = (struct field_modify_info){4, 0,
1436 MLX5_MODI_OUT_SIPV4};
1438 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1441 case RTE_FLOW_FIELD_IPV4_DST:
1442 info[idx] = (struct field_modify_info){4, 0,
1443 MLX5_MODI_OUT_DIPV4};
1445 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1448 case RTE_FLOW_FIELD_IPV6_DSCP:
1449 info[idx] = (struct field_modify_info){1, 0,
1450 MLX5_MODI_OUT_IP_DSCP};
1452 mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1455 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456 info[idx] = (struct field_modify_info){1, 0,
1457 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1459 mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1462 case RTE_FLOW_FIELD_IPV6_SRC:
1464 if (data->offset < 32) {
1465 info[idx] = (struct field_modify_info){4, 0,
1466 MLX5_MODI_OUT_SIPV6_127_96};
1469 rte_cpu_to_be_32(0xffffffff >>
1473 mask[idx] = RTE_BE32(0xffffffff);
1480 if (data->offset < 64) {
1481 info[idx] = (struct field_modify_info){4,
1483 MLX5_MODI_OUT_SIPV6_95_64};
1486 rte_cpu_to_be_32(0xffffffff >>
1490 mask[idx] = RTE_BE32(0xffffffff);
1497 if (data->offset < 96) {
1498 info[idx] = (struct field_modify_info){4,
1500 MLX5_MODI_OUT_SIPV6_63_32};
1503 rte_cpu_to_be_32(0xffffffff >>
1507 mask[idx] = RTE_BE32(0xffffffff);
1514 info[idx] = (struct field_modify_info){4, 12 * idx,
1515 MLX5_MODI_OUT_SIPV6_31_0};
1516 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1519 if (data->offset < 32)
1520 info[idx++] = (struct field_modify_info){4, 0,
1521 MLX5_MODI_OUT_SIPV6_127_96};
1522 if (data->offset < 64)
1523 info[idx++] = (struct field_modify_info){4, 0,
1524 MLX5_MODI_OUT_SIPV6_95_64};
1525 if (data->offset < 96)
1526 info[idx++] = (struct field_modify_info){4, 0,
1527 MLX5_MODI_OUT_SIPV6_63_32};
1528 if (data->offset < 128)
1529 info[idx++] = (struct field_modify_info){4, 0,
1530 MLX5_MODI_OUT_SIPV6_31_0};
1533 case RTE_FLOW_FIELD_IPV6_DST:
1535 if (data->offset < 32) {
1536 info[idx] = (struct field_modify_info){4, 0,
1537 MLX5_MODI_OUT_DIPV6_127_96};
1540 rte_cpu_to_be_32(0xffffffff >>
1544 mask[idx] = RTE_BE32(0xffffffff);
1551 if (data->offset < 64) {
1552 info[idx] = (struct field_modify_info){4,
1554 MLX5_MODI_OUT_DIPV6_95_64};
1557 rte_cpu_to_be_32(0xffffffff >>
1561 mask[idx] = RTE_BE32(0xffffffff);
1568 if (data->offset < 96) {
1569 info[idx] = (struct field_modify_info){4,
1571 MLX5_MODI_OUT_DIPV6_63_32};
1574 rte_cpu_to_be_32(0xffffffff >>
1578 mask[idx] = RTE_BE32(0xffffffff);
1585 info[idx] = (struct field_modify_info){4, 12 * idx,
1586 MLX5_MODI_OUT_DIPV6_31_0};
1587 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1590 if (data->offset < 32)
1591 info[idx++] = (struct field_modify_info){4, 0,
1592 MLX5_MODI_OUT_DIPV6_127_96};
1593 if (data->offset < 64)
1594 info[idx++] = (struct field_modify_info){4, 0,
1595 MLX5_MODI_OUT_DIPV6_95_64};
1596 if (data->offset < 96)
1597 info[idx++] = (struct field_modify_info){4, 0,
1598 MLX5_MODI_OUT_DIPV6_63_32};
1599 if (data->offset < 128)
1600 info[idx++] = (struct field_modify_info){4, 0,
1601 MLX5_MODI_OUT_DIPV6_31_0};
1604 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1605 info[idx] = (struct field_modify_info){2, 0,
1606 MLX5_MODI_OUT_TCP_SPORT};
1608 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1611 case RTE_FLOW_FIELD_TCP_PORT_DST:
1612 info[idx] = (struct field_modify_info){2, 0,
1613 MLX5_MODI_OUT_TCP_DPORT};
1615 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1618 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1619 info[idx] = (struct field_modify_info){4, 0,
1620 MLX5_MODI_OUT_TCP_SEQ_NUM};
1622 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1625 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1626 info[idx] = (struct field_modify_info){4, 0,
1627 MLX5_MODI_OUT_TCP_ACK_NUM};
1629 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1632 case RTE_FLOW_FIELD_TCP_FLAGS:
1633 info[idx] = (struct field_modify_info){1, 0,
1634 MLX5_MODI_OUT_TCP_FLAGS};
1636 mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1639 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1640 info[idx] = (struct field_modify_info){2, 0,
1641 MLX5_MODI_OUT_UDP_SPORT};
1643 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1646 case RTE_FLOW_FIELD_UDP_PORT_DST:
1647 info[idx] = (struct field_modify_info){2, 0,
1648 MLX5_MODI_OUT_UDP_DPORT};
1650 mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1653 case RTE_FLOW_FIELD_VXLAN_VNI:
1654 /* not supported yet */
1656 case RTE_FLOW_FIELD_GENEVE_VNI:
1657 /* not supported yet*/
1659 case RTE_FLOW_FIELD_GTP_TEID:
1660 info[idx] = (struct field_modify_info){4, 0,
1661 MLX5_MODI_GTP_TEID};
1663 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1666 case RTE_FLOW_FIELD_TAG:
1668 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1669 data->level, error);
1672 MLX5_ASSERT(reg != REG_NON);
1673 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1674 info[idx] = (struct field_modify_info){4, 0,
1678 rte_cpu_to_be_32(0xffffffff >>
1682 case RTE_FLOW_FIELD_MARK:
1684 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1688 MLX5_ASSERT(reg != REG_NON);
1689 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1690 info[idx] = (struct field_modify_info){4, 0,
1694 rte_cpu_to_be_32(0xffffffff >>
1698 case RTE_FLOW_FIELD_META:
1700 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1703 MLX5_ASSERT(reg != REG_NON);
1704 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1705 info[idx] = (struct field_modify_info){4, 0,
1709 rte_cpu_to_be_32(0xffffffff >>
1713 case RTE_FLOW_FIELD_POINTER:
1714 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1717 (void *)(uintptr_t)data->value, 32);
1718 value[idx] = rte_cpu_to_be_32(value[idx]);
1723 case RTE_FLOW_FIELD_VALUE:
1724 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1727 rte_cpu_to_be_32((uint32_t)data->value);
1739 * Convert modify_field action to DV specification.
1742 * Pointer to the rte_eth_dev structure.
1743 * @param[in,out] resource
1744 * Pointer to the modify-header resource.
1746 * Pointer to action specification.
1748 * Attributes of flow that includes this item.
1750 * Pointer to the error structure.
1753 * 0 on success, a negative errno value otherwise and rte_errno is set.
1756 flow_dv_convert_action_modify_field
1757 (struct rte_eth_dev *dev,
1758 struct mlx5_flow_dv_modify_hdr_resource *resource,
1759 const struct rte_flow_action *action,
1760 const struct rte_flow_attr *attr,
1761 struct rte_flow_error *error)
1763 const struct rte_flow_action_modify_field *conf =
1764 (const struct rte_flow_action_modify_field *)(action->conf);
1765 struct rte_flow_item item;
1766 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1768 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1770 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1771 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1774 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1775 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1776 type = MLX5_MODIFICATION_TYPE_SET;
1777 /** For SET fill the destination field (field) first. */
1778 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1779 value, conf->width, dev, attr, error);
1780 /** Then copy immediate value from source as per mask. */
1781 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1782 value, conf->width, dev, attr, error);
1785 type = MLX5_MODIFICATION_TYPE_COPY;
1786 /** For COPY fill the destination field (dcopy) without mask. */
1787 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1788 value, conf->width, dev, attr, error);
1789 /** Then construct the source field (field) with mask. */
1790 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1791 value, conf->width, dev, attr, error);
1794 return flow_dv_convert_modify_action(&item,
1795 field, dcopy, resource, type, error);
1799 * Validate MARK item.
1802 * Pointer to the rte_eth_dev structure.
1804 * Item specification.
1806 * Attributes of flow that includes this item.
1808 * Pointer to error structure.
1811 * 0 on success, a negative errno value otherwise and rte_errno is set.
1814 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1815 const struct rte_flow_item *item,
1816 const struct rte_flow_attr *attr __rte_unused,
1817 struct rte_flow_error *error)
1819 struct mlx5_priv *priv = dev->data->dev_private;
1820 struct mlx5_dev_config *config = &priv->config;
1821 const struct rte_flow_item_mark *spec = item->spec;
1822 const struct rte_flow_item_mark *mask = item->mask;
1823 const struct rte_flow_item_mark nic_mask = {
1824 .id = priv->sh->dv_mark_mask,
1828 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1829 return rte_flow_error_set(error, ENOTSUP,
1830 RTE_FLOW_ERROR_TYPE_ITEM, item,
1831 "extended metadata feature"
1833 if (!mlx5_flow_ext_mreg_supported(dev))
1834 return rte_flow_error_set(error, ENOTSUP,
1835 RTE_FLOW_ERROR_TYPE_ITEM, item,
1836 "extended metadata register"
1837 " isn't supported");
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_ITEM, item,
1841 "extended metadata register"
1842 " isn't available");
1843 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1847 return rte_flow_error_set(error, EINVAL,
1848 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1850 "data cannot be empty");
1851 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1855 "mark id exceeds the limit");
1859 return rte_flow_error_set(error, EINVAL,
1860 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1861 "mask cannot be zero");
1863 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1864 (const uint8_t *)&nic_mask,
1865 sizeof(struct rte_flow_item_mark),
1866 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1873 * Validate META item.
1876 * Pointer to the rte_eth_dev structure.
1878 * Item specification.
1880 * Attributes of flow that includes this item.
1882 * Pointer to error structure.
1885 * 0 on success, a negative errno value otherwise and rte_errno is set.
1888 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1889 const struct rte_flow_item *item,
1890 const struct rte_flow_attr *attr,
1891 struct rte_flow_error *error)
1893 struct mlx5_priv *priv = dev->data->dev_private;
1894 struct mlx5_dev_config *config = &priv->config;
1895 const struct rte_flow_item_meta *spec = item->spec;
1896 const struct rte_flow_item_meta *mask = item->mask;
1897 struct rte_flow_item_meta nic_mask = {
1904 return rte_flow_error_set(error, EINVAL,
1905 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1907 "data cannot be empty");
1908 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1909 if (!mlx5_flow_ext_mreg_supported(dev))
1910 return rte_flow_error_set(error, ENOTSUP,
1911 RTE_FLOW_ERROR_TYPE_ITEM, item,
1912 "extended metadata register"
1913 " isn't supported");
1914 reg = flow_dv_get_metadata_reg(dev, attr, error);
1918 return rte_flow_error_set(error, ENOTSUP,
1919 RTE_FLOW_ERROR_TYPE_ITEM, item,
1920 "unavalable extended metadata register");
1922 return rte_flow_error_set(error, ENOTSUP,
1923 RTE_FLOW_ERROR_TYPE_ITEM, item,
1927 nic_mask.data = priv->sh->dv_meta_mask;
1930 return rte_flow_error_set(error, ENOTSUP,
1931 RTE_FLOW_ERROR_TYPE_ITEM, item,
1932 "extended metadata feature "
1933 "should be enabled when "
1934 "meta item is requested "
1935 "with e-switch mode ");
1937 return rte_flow_error_set(error, ENOTSUP,
1938 RTE_FLOW_ERROR_TYPE_ITEM, item,
1939 "match on metadata for ingress "
1940 "is not supported in legacy "
1944 mask = &rte_flow_item_meta_mask;
1946 return rte_flow_error_set(error, EINVAL,
1947 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1948 "mask cannot be zero");
1950 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1951 (const uint8_t *)&nic_mask,
1952 sizeof(struct rte_flow_item_meta),
1953 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1958 * Validate TAG item.
1961 * Pointer to the rte_eth_dev structure.
1963 * Item specification.
1965 * Attributes of flow that includes this item.
1967 * Pointer to error structure.
1970 * 0 on success, a negative errno value otherwise and rte_errno is set.
1973 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1974 const struct rte_flow_item *item,
1975 const struct rte_flow_attr *attr __rte_unused,
1976 struct rte_flow_error *error)
1978 const struct rte_flow_item_tag *spec = item->spec;
1979 const struct rte_flow_item_tag *mask = item->mask;
1980 const struct rte_flow_item_tag nic_mask = {
1981 .data = RTE_BE32(UINT32_MAX),
1986 if (!mlx5_flow_ext_mreg_supported(dev))
1987 return rte_flow_error_set(error, ENOTSUP,
1988 RTE_FLOW_ERROR_TYPE_ITEM, item,
1989 "extensive metadata register"
1990 " isn't supported");
1992 return rte_flow_error_set(error, EINVAL,
1993 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1995 "data cannot be empty");
1997 mask = &rte_flow_item_tag_mask;
1999 return rte_flow_error_set(error, EINVAL,
2000 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001 "mask cannot be zero");
2003 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2004 (const uint8_t *)&nic_mask,
2005 sizeof(struct rte_flow_item_tag),
2006 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2009 if (mask->index != 0xff)
2010 return rte_flow_error_set(error, EINVAL,
2011 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2012 "partial mask for tag index"
2013 " is not supported");
2014 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2017 MLX5_ASSERT(ret != REG_NON);
2022 * Validate vport item.
2025 * Pointer to the rte_eth_dev structure.
2027 * Item specification.
2029 * Attributes of flow that includes this item.
2030 * @param[in] item_flags
2031 * Bit-fields that holds the items detected until now.
2033 * Pointer to error structure.
2036 * 0 on success, a negative errno value otherwise and rte_errno is set.
2039 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2040 const struct rte_flow_item *item,
2041 const struct rte_flow_attr *attr,
2042 uint64_t item_flags,
2043 struct rte_flow_error *error)
2045 const struct rte_flow_item_port_id *spec = item->spec;
2046 const struct rte_flow_item_port_id *mask = item->mask;
2047 const struct rte_flow_item_port_id switch_mask = {
2050 struct mlx5_priv *esw_priv;
2051 struct mlx5_priv *dev_priv;
2054 if (!attr->transfer)
2055 return rte_flow_error_set(error, EINVAL,
2056 RTE_FLOW_ERROR_TYPE_ITEM,
2058 "match on port id is valid only"
2059 " when transfer flag is enabled");
2060 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2061 return rte_flow_error_set(error, ENOTSUP,
2062 RTE_FLOW_ERROR_TYPE_ITEM, item,
2063 "multiple source ports are not"
2066 mask = &switch_mask;
2067 if (mask->id != 0xffffffff)
2068 return rte_flow_error_set(error, ENOTSUP,
2069 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2071 "no support for partial mask on"
2073 ret = mlx5_flow_item_acceptable
2074 (item, (const uint8_t *)mask,
2075 (const uint8_t *)&rte_flow_item_port_id_mask,
2076 sizeof(struct rte_flow_item_port_id),
2077 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2082 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2084 return rte_flow_error_set(error, rte_errno,
2085 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086 "failed to obtain E-Switch info for"
2088 dev_priv = mlx5_dev_to_eswitch_info(dev);
2090 return rte_flow_error_set(error, rte_errno,
2091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2093 "failed to obtain E-Switch info");
2094 if (esw_priv->domain_id != dev_priv->domain_id)
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2097 "cannot match on a port from a"
2098 " different E-Switch");
2103 * Validate VLAN item.
2106 * Item specification.
2107 * @param[in] item_flags
2108 * Bit-fields that holds the items detected until now.
2110 * Ethernet device flow is being created on.
2112 * Pointer to error structure.
2115 * 0 on success, a negative errno value otherwise and rte_errno is set.
2118 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2119 uint64_t item_flags,
2120 struct rte_eth_dev *dev,
2121 struct rte_flow_error *error)
2123 const struct rte_flow_item_vlan *mask = item->mask;
2124 const struct rte_flow_item_vlan nic_mask = {
2125 .tci = RTE_BE16(UINT16_MAX),
2126 .inner_type = RTE_BE16(UINT16_MAX),
2129 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2131 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2132 MLX5_FLOW_LAYER_INNER_L4) :
2133 (MLX5_FLOW_LAYER_OUTER_L3 |
2134 MLX5_FLOW_LAYER_OUTER_L4);
2135 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2136 MLX5_FLOW_LAYER_OUTER_VLAN;
2138 if (item_flags & vlanm)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ITEM, item,
2141 "multiple VLAN layers not supported");
2142 else if ((item_flags & l34m) != 0)
2143 return rte_flow_error_set(error, EINVAL,
2144 RTE_FLOW_ERROR_TYPE_ITEM, item,
2145 "VLAN cannot follow L3/L4 layer");
2147 mask = &rte_flow_item_vlan_mask;
2148 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2149 (const uint8_t *)&nic_mask,
2150 sizeof(struct rte_flow_item_vlan),
2151 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2154 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2155 struct mlx5_priv *priv = dev->data->dev_private;
2157 if (priv->vmwa_context) {
2159 * Non-NULL context means we have a virtual machine
2160 * and SR-IOV enabled, we have to create VLAN interface
2161 * to make hypervisor to setup E-Switch vport
2162 * context correctly. We avoid creating the multiple
2163 * VLAN interfaces, so we cannot support VLAN tag mask.
2165 return rte_flow_error_set(error, EINVAL,
2166 RTE_FLOW_ERROR_TYPE_ITEM,
2168 "VLAN tag mask is not"
2169 " supported in virtual"
2177 * GTP flags are contained in 1 byte of the format:
2178 * -------------------------------------------
2179 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2180 * |-----------------------------------------|
2181 * | value | Version | PT | Res | E | S | PN |
2182 * -------------------------------------------
2184 * Matching is supported only for GTP flags E, S, PN.
2186 #define MLX5_GTP_FLAGS_MASK 0x07
2189 * Validate GTP item.
2192 * Pointer to the rte_eth_dev structure.
2194 * Item specification.
2195 * @param[in] item_flags
2196 * Bit-fields that holds the items detected until now.
2198 * Pointer to error structure.
2201 * 0 on success, a negative errno value otherwise and rte_errno is set.
2204 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2205 const struct rte_flow_item *item,
2206 uint64_t item_flags,
2207 struct rte_flow_error *error)
2209 struct mlx5_priv *priv = dev->data->dev_private;
2210 const struct rte_flow_item_gtp *spec = item->spec;
2211 const struct rte_flow_item_gtp *mask = item->mask;
2212 const struct rte_flow_item_gtp nic_mask = {
2213 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2215 .teid = RTE_BE32(0xffffffff),
2218 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2219 return rte_flow_error_set(error, ENOTSUP,
2220 RTE_FLOW_ERROR_TYPE_ITEM, item,
2221 "GTP support is not enabled");
2222 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2223 return rte_flow_error_set(error, ENOTSUP,
2224 RTE_FLOW_ERROR_TYPE_ITEM, item,
2225 "multiple tunnel layers not"
2227 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2228 return rte_flow_error_set(error, EINVAL,
2229 RTE_FLOW_ERROR_TYPE_ITEM, item,
2230 "no outer UDP layer found");
2232 mask = &rte_flow_item_gtp_mask;
2233 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2234 return rte_flow_error_set(error, ENOTSUP,
2235 RTE_FLOW_ERROR_TYPE_ITEM, item,
2236 "Match is supported for GTP"
2238 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2239 (const uint8_t *)&nic_mask,
2240 sizeof(struct rte_flow_item_gtp),
2241 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2245 * Validate GTP PSC item.
2248 * Item specification.
2249 * @param[in] last_item
2250 * Previous validated item in the pattern items.
2251 * @param[in] gtp_item
2252 * Previous GTP item specification.
2254 * Pointer to flow attributes.
2256 * Pointer to error structure.
2259 * 0 on success, a negative errno value otherwise and rte_errno is set.
2262 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2264 const struct rte_flow_item *gtp_item,
2265 const struct rte_flow_attr *attr,
2266 struct rte_flow_error *error)
2268 const struct rte_flow_item_gtp *gtp_spec;
2269 const struct rte_flow_item_gtp *gtp_mask;
2270 const struct rte_flow_item_gtp_psc *spec;
2271 const struct rte_flow_item_gtp_psc *mask;
2272 const struct rte_flow_item_gtp_psc nic_mask = {
2277 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2278 return rte_flow_error_set
2279 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2280 "GTP PSC item must be preceded with GTP item");
2281 gtp_spec = gtp_item->spec;
2282 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2283 /* GTP spec and E flag is requested to match zero. */
2285 (gtp_mask->v_pt_rsv_flags &
2286 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2287 return rte_flow_error_set
2288 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2289 "GTP E flag must be 1 to match GTP PSC");
2290 /* Check the flow is not created in group zero. */
2291 if (!attr->transfer && !attr->group)
2292 return rte_flow_error_set
2293 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2294 "GTP PSC is not supported for group 0");
2295 /* GTP spec is here and E flag is requested to match zero. */
2299 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2300 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2301 return rte_flow_error_set
2302 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2303 "PDU type should be smaller than 16");
2304 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2305 (const uint8_t *)&nic_mask,
2306 sizeof(struct rte_flow_item_gtp_psc),
2307 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2311 * Validate IPV4 item.
2312 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2313 * add specific validation of fragment_offset field,
2316 * Item specification.
2317 * @param[in] item_flags
2318 * Bit-fields that holds the items detected until now.
2320 * Pointer to error structure.
2323 * 0 on success, a negative errno value otherwise and rte_errno is set.
2326 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2327 uint64_t item_flags,
2329 uint16_t ether_type,
2330 struct rte_flow_error *error)
2333 const struct rte_flow_item_ipv4 *spec = item->spec;
2334 const struct rte_flow_item_ipv4 *last = item->last;
2335 const struct rte_flow_item_ipv4 *mask = item->mask;
2336 rte_be16_t fragment_offset_spec = 0;
2337 rte_be16_t fragment_offset_last = 0;
2338 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2340 .src_addr = RTE_BE32(0xffffffff),
2341 .dst_addr = RTE_BE32(0xffffffff),
2342 .type_of_service = 0xff,
2343 .fragment_offset = RTE_BE16(0xffff),
2344 .next_proto_id = 0xff,
2345 .time_to_live = 0xff,
2349 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2350 ether_type, &nic_ipv4_mask,
2351 MLX5_ITEM_RANGE_ACCEPTED, error);
2355 fragment_offset_spec = spec->hdr.fragment_offset &
2356 mask->hdr.fragment_offset;
2357 if (!fragment_offset_spec)
2360 * spec and mask are valid, enforce using full mask to make sure the
2361 * complete value is used correctly.
2363 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2364 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2365 return rte_flow_error_set(error, EINVAL,
2366 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2367 item, "must use full mask for"
2368 " fragment_offset");
2370 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2371 * indicating this is 1st fragment of fragmented packet.
2372 * This is not yet supported in MLX5, return appropriate error message.
2374 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2375 return rte_flow_error_set(error, ENOTSUP,
2376 RTE_FLOW_ERROR_TYPE_ITEM, item,
2377 "match on first fragment not "
2379 if (fragment_offset_spec && !last)
2380 return rte_flow_error_set(error, ENOTSUP,
2381 RTE_FLOW_ERROR_TYPE_ITEM, item,
2382 "specified value not supported");
2383 /* spec and last are valid, validate the specified range. */
2384 fragment_offset_last = last->hdr.fragment_offset &
2385 mask->hdr.fragment_offset;
2387 * Match on fragment_offset spec 0x2001 and last 0x3fff
2388 * means MF is 1 and frag-offset is > 0.
2389 * This packet is fragment 2nd and onward, excluding last.
2390 * This is not yet supported in MLX5, return appropriate
2393 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2394 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2395 return rte_flow_error_set(error, ENOTSUP,
2396 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2397 last, "match on following "
2398 "fragments not supported");
2400 * Match on fragment_offset spec 0x0001 and last 0x1fff
2401 * means MF is 0 and frag-offset is > 0.
2402 * This packet is last fragment of fragmented packet.
2403 * This is not yet supported in MLX5, return appropriate
2406 if (fragment_offset_spec == RTE_BE16(1) &&
2407 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2408 return rte_flow_error_set(error, ENOTSUP,
2409 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2410 last, "match on last "
2411 "fragment not supported");
2413 * Match on fragment_offset spec 0x0001 and last 0x3fff
2414 * means MF and/or frag-offset is not 0.
2415 * This is a fragmented packet.
2416 * Other range values are invalid and rejected.
2418 if (!(fragment_offset_spec == RTE_BE16(1) &&
2419 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2420 return rte_flow_error_set(error, ENOTSUP,
2421 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2422 "specified range not supported");
2427 * Validate IPV6 fragment extension item.
2430 * Item specification.
2431 * @param[in] item_flags
2432 * Bit-fields that holds the items detected until now.
2434 * Pointer to error structure.
2437 * 0 on success, a negative errno value otherwise and rte_errno is set.
2440 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2441 uint64_t item_flags,
2442 struct rte_flow_error *error)
2444 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2445 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2446 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2447 rte_be16_t frag_data_spec = 0;
2448 rte_be16_t frag_data_last = 0;
2449 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2451 MLX5_FLOW_LAYER_OUTER_L4;
2453 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2455 .next_header = 0xff,
2456 .frag_data = RTE_BE16(0xffff),
2460 if (item_flags & l4m)
2461 return rte_flow_error_set(error, EINVAL,
2462 RTE_FLOW_ERROR_TYPE_ITEM, item,
2463 "ipv6 fragment extension item cannot "
2465 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2466 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2467 return rte_flow_error_set(error, EINVAL,
2468 RTE_FLOW_ERROR_TYPE_ITEM, item,
2469 "ipv6 fragment extension item must "
2470 "follow ipv6 item");
2472 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2473 if (!frag_data_spec)
2476 * spec and mask are valid, enforce using full mask to make sure the
2477 * complete value is used correctly.
2479 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2480 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2481 return rte_flow_error_set(error, EINVAL,
2482 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483 item, "must use full mask for"
2486 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2487 * This is 1st fragment of fragmented packet.
2489 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2490 return rte_flow_error_set(error, ENOTSUP,
2491 RTE_FLOW_ERROR_TYPE_ITEM, item,
2492 "match on first fragment not "
2494 if (frag_data_spec && !last)
2495 return rte_flow_error_set(error, EINVAL,
2496 RTE_FLOW_ERROR_TYPE_ITEM, item,
2497 "specified value not supported");
2498 ret = mlx5_flow_item_acceptable
2499 (item, (const uint8_t *)mask,
2500 (const uint8_t *)&nic_mask,
2501 sizeof(struct rte_flow_item_ipv6_frag_ext),
2502 MLX5_ITEM_RANGE_ACCEPTED, error);
2505 /* spec and last are valid, validate the specified range. */
2506 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2508 * Match on frag_data spec 0x0009 and last 0xfff9
2509 * means M is 1 and frag-offset is > 0.
2510 * This packet is fragment 2nd and onward, excluding last.
2511 * This is not yet supported in MLX5, return appropriate
2514 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2515 RTE_IPV6_EHDR_MF_MASK) &&
2516 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on frag_data spec 0x0008 and last 0xfff8
2523 * means M is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2529 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2534 /* Other range values are invalid and rejected. */
2535 return rte_flow_error_set(error, EINVAL,
2536 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2537 "specified range not supported");
2541 * Validate the pop VLAN action.
2544 * Pointer to the rte_eth_dev structure.
2545 * @param[in] action_flags
2546 * Holds the actions detected until now.
2548 * Pointer to the pop vlan action.
2549 * @param[in] item_flags
2550 * The items found in this flow rule.
2552 * Pointer to flow attributes.
2554 * Pointer to error structure.
2557 * 0 on success, a negative errno value otherwise and rte_errno is set.
2560 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2561 uint64_t action_flags,
2562 const struct rte_flow_action *action,
2563 uint64_t item_flags,
2564 const struct rte_flow_attr *attr,
2565 struct rte_flow_error *error)
2567 const struct mlx5_priv *priv = dev->data->dev_private;
2571 if (!priv->sh->pop_vlan_action)
2572 return rte_flow_error_set(error, ENOTSUP,
2573 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2575 "pop vlan action is not supported");
2577 return rte_flow_error_set(error, ENOTSUP,
2578 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2580 "pop vlan action not supported for "
2582 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2583 return rte_flow_error_set(error, ENOTSUP,
2584 RTE_FLOW_ERROR_TYPE_ACTION, action,
2585 "no support for multiple VLAN "
2587 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2588 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2589 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2590 return rte_flow_error_set(error, ENOTSUP,
2591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2593 "cannot pop vlan after decap without "
2594 "match on inner vlan in the flow");
2595 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2596 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2597 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2598 return rte_flow_error_set(error, ENOTSUP,
2599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2601 "cannot pop vlan without a "
2602 "match on (outer) vlan in the flow");
2603 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2604 return rte_flow_error_set(error, EINVAL,
2605 RTE_FLOW_ERROR_TYPE_ACTION, action,
2606 "wrong action order, port_id should "
2607 "be after pop VLAN action");
2608 if (!attr->transfer && priv->representor)
2609 return rte_flow_error_set(error, ENOTSUP,
2610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2611 "pop vlan action for VF representor "
2612 "not supported on NIC table");
2617 * Get VLAN default info from vlan match info.
2620 * the list of item specifications.
2622 * pointer VLAN info to fill to.
2625 * 0 on success, a negative errno value otherwise and rte_errno is set.
2628 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2629 struct rte_vlan_hdr *vlan)
2631 const struct rte_flow_item_vlan nic_mask = {
2632 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2633 MLX5DV_FLOW_VLAN_VID_MASK),
2634 .inner_type = RTE_BE16(0xffff),
2639 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2640 int type = items->type;
2642 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2643 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2646 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2647 const struct rte_flow_item_vlan *vlan_m = items->mask;
2648 const struct rte_flow_item_vlan *vlan_v = items->spec;
2650 /* If VLAN item in pattern doesn't contain data, return here. */
2655 /* Only full match values are accepted */
2656 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2657 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2658 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2660 rte_be_to_cpu_16(vlan_v->tci &
2661 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2663 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2664 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2665 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2667 rte_be_to_cpu_16(vlan_v->tci &
2668 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2670 if (vlan_m->inner_type == nic_mask.inner_type)
2671 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2672 vlan_m->inner_type);
2677 * Validate the push VLAN action.
2680 * Pointer to the rte_eth_dev structure.
2681 * @param[in] action_flags
2682 * Holds the actions detected until now.
2683 * @param[in] item_flags
2684 * The items found in this flow rule.
2686 * Pointer to the action structure.
2688 * Pointer to flow attributes
2690 * Pointer to error structure.
2693 * 0 on success, a negative errno value otherwise and rte_errno is set.
2696 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2697 uint64_t action_flags,
2698 const struct rte_flow_item_vlan *vlan_m,
2699 const struct rte_flow_action *action,
2700 const struct rte_flow_attr *attr,
2701 struct rte_flow_error *error)
2703 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2704 const struct mlx5_priv *priv = dev->data->dev_private;
2706 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2707 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2708 return rte_flow_error_set(error, EINVAL,
2709 RTE_FLOW_ERROR_TYPE_ACTION, action,
2710 "invalid vlan ethertype");
2711 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2712 return rte_flow_error_set(error, EINVAL,
2713 RTE_FLOW_ERROR_TYPE_ACTION, action,
2714 "wrong action order, port_id should "
2715 "be after push VLAN");
2716 if (!attr->transfer && priv->representor)
2717 return rte_flow_error_set(error, ENOTSUP,
2718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2719 "push vlan action for VF representor "
2720 "not supported on NIC table");
2722 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2723 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2724 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2725 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2726 !(mlx5_flow_find_action
2727 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2728 return rte_flow_error_set(error, EINVAL,
2729 RTE_FLOW_ERROR_TYPE_ACTION, action,
2730 "not full match mask on VLAN PCP and "
2731 "there is no of_set_vlan_pcp action, "
2732 "push VLAN action cannot figure out "
2735 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2736 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2737 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2738 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2739 !(mlx5_flow_find_action
2740 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2741 return rte_flow_error_set(error, EINVAL,
2742 RTE_FLOW_ERROR_TYPE_ACTION, action,
2743 "not full match mask on VLAN VID and "
2744 "there is no of_set_vlan_vid action, "
2745 "push VLAN action cannot figure out "
2752 * Validate the set VLAN PCP.
2754 * @param[in] action_flags
2755 * Holds the actions detected until now.
2756 * @param[in] actions
2757 * Pointer to the list of actions remaining in the flow rule.
2759 * Pointer to error structure.
2762 * 0 on success, a negative errno value otherwise and rte_errno is set.
2765 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2766 const struct rte_flow_action actions[],
2767 struct rte_flow_error *error)
2769 const struct rte_flow_action *action = actions;
2770 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2772 if (conf->vlan_pcp > 7)
2773 return rte_flow_error_set(error, EINVAL,
2774 RTE_FLOW_ERROR_TYPE_ACTION, action,
2775 "VLAN PCP value is too big");
2776 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2777 return rte_flow_error_set(error, ENOTSUP,
2778 RTE_FLOW_ERROR_TYPE_ACTION, action,
2779 "set VLAN PCP action must follow "
2780 "the push VLAN action");
2781 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2782 return rte_flow_error_set(error, ENOTSUP,
2783 RTE_FLOW_ERROR_TYPE_ACTION, action,
2784 "Multiple VLAN PCP modification are "
2786 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2787 return rte_flow_error_set(error, EINVAL,
2788 RTE_FLOW_ERROR_TYPE_ACTION, action,
2789 "wrong action order, port_id should "
2790 "be after set VLAN PCP");
2795 * Validate the set VLAN VID.
2797 * @param[in] item_flags
2798 * Holds the items detected in this rule.
2799 * @param[in] action_flags
2800 * Holds the actions detected until now.
2801 * @param[in] actions
2802 * Pointer to the list of actions remaining in the flow rule.
2804 * Pointer to error structure.
2807 * 0 on success, a negative errno value otherwise and rte_errno is set.
2810 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2811 uint64_t action_flags,
2812 const struct rte_flow_action actions[],
2813 struct rte_flow_error *error)
2815 const struct rte_flow_action *action = actions;
2816 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2818 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2819 return rte_flow_error_set(error, EINVAL,
2820 RTE_FLOW_ERROR_TYPE_ACTION, action,
2821 "VLAN VID value is too big");
2822 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2823 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2824 return rte_flow_error_set(error, ENOTSUP,
2825 RTE_FLOW_ERROR_TYPE_ACTION, action,
2826 "set VLAN VID action must follow push"
2827 " VLAN action or match on VLAN item");
2828 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2829 return rte_flow_error_set(error, ENOTSUP,
2830 RTE_FLOW_ERROR_TYPE_ACTION, action,
2831 "Multiple VLAN VID modifications are "
2833 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2834 return rte_flow_error_set(error, EINVAL,
2835 RTE_FLOW_ERROR_TYPE_ACTION, action,
2836 "wrong action order, port_id should "
2837 "be after set VLAN VID");
2842 * Validate the FLAG action.
2845 * Pointer to the rte_eth_dev structure.
2846 * @param[in] action_flags
2847 * Holds the actions detected until now.
2849 * Pointer to flow attributes
2851 * Pointer to error structure.
2854 * 0 on success, a negative errno value otherwise and rte_errno is set.
2857 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2858 uint64_t action_flags,
2859 const struct rte_flow_attr *attr,
2860 struct rte_flow_error *error)
2862 struct mlx5_priv *priv = dev->data->dev_private;
2863 struct mlx5_dev_config *config = &priv->config;
2866 /* Fall back if no extended metadata register support. */
2867 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2868 return mlx5_flow_validate_action_flag(action_flags, attr,
2870 /* Extensive metadata mode requires registers. */
2871 if (!mlx5_flow_ext_mreg_supported(dev))
2872 return rte_flow_error_set(error, ENOTSUP,
2873 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2874 "no metadata registers "
2875 "to support flag action");
2876 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2877 return rte_flow_error_set(error, ENOTSUP,
2878 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2879 "extended metadata register"
2880 " isn't available");
2881 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2884 MLX5_ASSERT(ret > 0);
2885 if (action_flags & MLX5_FLOW_ACTION_MARK)
2886 return rte_flow_error_set(error, EINVAL,
2887 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2888 "can't mark and flag in same flow");
2889 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2890 return rte_flow_error_set(error, EINVAL,
2891 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2893 " actions in same flow");
2898 * Validate MARK action.
2901 * Pointer to the rte_eth_dev structure.
2903 * Pointer to action.
2904 * @param[in] action_flags
2905 * Holds the actions detected until now.
2907 * Pointer to flow attributes
2909 * Pointer to error structure.
2912 * 0 on success, a negative errno value otherwise and rte_errno is set.
2915 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2916 const struct rte_flow_action *action,
2917 uint64_t action_flags,
2918 const struct rte_flow_attr *attr,
2919 struct rte_flow_error *error)
2921 struct mlx5_priv *priv = dev->data->dev_private;
2922 struct mlx5_dev_config *config = &priv->config;
2923 const struct rte_flow_action_mark *mark = action->conf;
2926 if (is_tunnel_offload_active(dev))
2927 return rte_flow_error_set(error, ENOTSUP,
2928 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2930 "if tunnel offload active");
2931 /* Fall back if no extended metadata register support. */
2932 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2933 return mlx5_flow_validate_action_mark(action, action_flags,
2935 /* Extensive metadata mode requires registers. */
2936 if (!mlx5_flow_ext_mreg_supported(dev))
2937 return rte_flow_error_set(error, ENOTSUP,
2938 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2939 "no metadata registers "
2940 "to support mark action");
2941 if (!priv->sh->dv_mark_mask)
2942 return rte_flow_error_set(error, ENOTSUP,
2943 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944 "extended metadata register"
2945 " isn't available");
2946 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2949 MLX5_ASSERT(ret > 0);
2951 return rte_flow_error_set(error, EINVAL,
2952 RTE_FLOW_ERROR_TYPE_ACTION, action,
2953 "configuration cannot be null");
2954 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2955 return rte_flow_error_set(error, EINVAL,
2956 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2958 "mark id exceeds the limit");
2959 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2960 return rte_flow_error_set(error, EINVAL,
2961 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2962 "can't flag and mark in same flow");
2963 if (action_flags & MLX5_FLOW_ACTION_MARK)
2964 return rte_flow_error_set(error, EINVAL,
2965 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2966 "can't have 2 mark actions in same"
2972 * Validate SET_META action.
2975 * Pointer to the rte_eth_dev structure.
2977 * Pointer to the action structure.
2978 * @param[in] action_flags
2979 * Holds the actions detected until now.
2981 * Pointer to flow attributes
2983 * Pointer to error structure.
2986 * 0 on success, a negative errno value otherwise and rte_errno is set.
2989 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2990 const struct rte_flow_action *action,
2991 uint64_t action_flags __rte_unused,
2992 const struct rte_flow_attr *attr,
2993 struct rte_flow_error *error)
2995 const struct rte_flow_action_set_meta *conf;
2996 uint32_t nic_mask = UINT32_MAX;
2999 if (!mlx5_flow_ext_mreg_supported(dev))
3000 return rte_flow_error_set(error, ENOTSUP,
3001 RTE_FLOW_ERROR_TYPE_ACTION, action,
3002 "extended metadata register"
3003 " isn't supported");
3004 reg = flow_dv_get_metadata_reg(dev, attr, error);
3008 return rte_flow_error_set(error, ENOTSUP,
3009 RTE_FLOW_ERROR_TYPE_ACTION, action,
3010 "unavalable extended metadata register");
3011 if (reg != REG_A && reg != REG_B) {
3012 struct mlx5_priv *priv = dev->data->dev_private;
3014 nic_mask = priv->sh->dv_meta_mask;
3016 if (!(action->conf))
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION, action,
3019 "configuration cannot be null");
3020 conf = (const struct rte_flow_action_set_meta *)action->conf;
3022 return rte_flow_error_set(error, EINVAL,
3023 RTE_FLOW_ERROR_TYPE_ACTION, action,
3024 "zero mask doesn't have any effect");
3025 if (conf->mask & ~nic_mask)
3026 return rte_flow_error_set(error, EINVAL,
3027 RTE_FLOW_ERROR_TYPE_ACTION, action,
3028 "meta data must be within reg C0");
3033 * Validate SET_TAG action.
3036 * Pointer to the rte_eth_dev structure.
3038 * Pointer to the action structure.
3039 * @param[in] action_flags
3040 * Holds the actions detected until now.
3042 * Pointer to flow attributes
3044 * Pointer to error structure.
3047 * 0 on success, a negative errno value otherwise and rte_errno is set.
3050 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3051 const struct rte_flow_action *action,
3052 uint64_t action_flags,
3053 const struct rte_flow_attr *attr,
3054 struct rte_flow_error *error)
3056 const struct rte_flow_action_set_tag *conf;
3057 const uint64_t terminal_action_flags =
3058 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3059 MLX5_FLOW_ACTION_RSS;
3062 if (!mlx5_flow_ext_mreg_supported(dev))
3063 return rte_flow_error_set(error, ENOTSUP,
3064 RTE_FLOW_ERROR_TYPE_ACTION, action,
3065 "extensive metadata register"
3066 " isn't supported");
3067 if (!(action->conf))
3068 return rte_flow_error_set(error, EINVAL,
3069 RTE_FLOW_ERROR_TYPE_ACTION, action,
3070 "configuration cannot be null");
3071 conf = (const struct rte_flow_action_set_tag *)action->conf;
3073 return rte_flow_error_set(error, EINVAL,
3074 RTE_FLOW_ERROR_TYPE_ACTION, action,
3075 "zero mask doesn't have any effect");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3079 if (!attr->transfer && attr->ingress &&
3080 (action_flags & terminal_action_flags))
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, action,
3083 "set_tag has no effect"
3084 " with terminal actions");
3089 * Validate count action.
3092 * Pointer to rte_eth_dev structure.
3094 * Pointer to the action structure.
3095 * @param[in] action_flags
3096 * Holds the actions detected until now.
3098 * Pointer to error structure.
3101 * 0 on success, a negative errno value otherwise and rte_errno is set.
3104 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3105 const struct rte_flow_action *action,
3106 uint64_t action_flags,
3107 struct rte_flow_error *error)
3109 struct mlx5_priv *priv = dev->data->dev_private;
3110 const struct rte_flow_action_count *count;
3112 if (!priv->config.devx)
3114 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3115 return rte_flow_error_set(error, EINVAL,
3116 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3117 "duplicate count actions set");
3118 count = (const struct rte_flow_action_count *)action->conf;
3119 if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3120 !priv->sh->flow_hit_aso_en)
3121 return rte_flow_error_set(error, EINVAL,
3122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123 "old age and shared count combination is not supported");
3124 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3128 return rte_flow_error_set
3130 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3132 "count action not supported");
3136 * Validate the L2 encap action.
3139 * Pointer to the rte_eth_dev structure.
3140 * @param[in] action_flags
3141 * Holds the actions detected until now.
3143 * Pointer to the action structure.
3145 * Pointer to flow attributes.
3147 * Pointer to error structure.
3150 * 0 on success, a negative errno value otherwise and rte_errno is set.
3153 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3154 uint64_t action_flags,
3155 const struct rte_flow_action *action,
3156 const struct rte_flow_attr *attr,
3157 struct rte_flow_error *error)
3159 const struct mlx5_priv *priv = dev->data->dev_private;
3161 if (!(action->conf))
3162 return rte_flow_error_set(error, EINVAL,
3163 RTE_FLOW_ERROR_TYPE_ACTION, action,
3164 "configuration cannot be null");
3165 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3166 return rte_flow_error_set(error, EINVAL,
3167 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3168 "can only have a single encap action "
3170 if (!attr->transfer && priv->representor)
3171 return rte_flow_error_set(error, ENOTSUP,
3172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173 "encap action for VF representor "
3174 "not supported on NIC table");
3179 * Validate a decap action.
3182 * Pointer to the rte_eth_dev structure.
3183 * @param[in] action_flags
3184 * Holds the actions detected until now.
3186 * Pointer to the action structure.
3187 * @param[in] item_flags
3188 * Holds the items detected.
3190 * Pointer to flow attributes
3192 * Pointer to error structure.
3195 * 0 on success, a negative errno value otherwise and rte_errno is set.
3198 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3199 uint64_t action_flags,
3200 const struct rte_flow_action *action,
3201 const uint64_t item_flags,
3202 const struct rte_flow_attr *attr,
3203 struct rte_flow_error *error)
3205 const struct mlx5_priv *priv = dev->data->dev_private;
3207 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3208 !priv->config.decap_en)
3209 return rte_flow_error_set(error, ENOTSUP,
3210 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211 "decap is not enabled");
3212 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3213 return rte_flow_error_set(error, ENOTSUP,
3214 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3216 MLX5_FLOW_ACTION_DECAP ? "can only "
3217 "have a single decap action" : "decap "
3218 "after encap is not supported");
3219 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3222 "can't have decap action after"
3225 return rte_flow_error_set(error, ENOTSUP,
3226 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3228 "decap action not supported for "
3230 if (!attr->transfer && priv->representor)
3231 return rte_flow_error_set(error, ENOTSUP,
3232 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3233 "decap action for VF representor "
3234 "not supported on NIC table");
3235 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3236 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3237 return rte_flow_error_set(error, ENOTSUP,
3238 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239 "VXLAN item should be present for VXLAN decap");
3243 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3246 * Validate the raw encap and decap actions.
3249 * Pointer to the rte_eth_dev structure.
3251 * Pointer to the decap action.
3253 * Pointer to the encap action.
3255 * Pointer to flow attributes
3256 * @param[in/out] action_flags
3257 * Holds the actions detected until now.
3258 * @param[out] actions_n
3259 * pointer to the number of actions counter.
3261 * Pointer to the action structure.
3262 * @param[in] item_flags
3263 * Holds the items detected.
3265 * Pointer to error structure.
3268 * 0 on success, a negative errno value otherwise and rte_errno is set.
3271 flow_dv_validate_action_raw_encap_decap
3272 (struct rte_eth_dev *dev,
3273 const struct rte_flow_action_raw_decap *decap,
3274 const struct rte_flow_action_raw_encap *encap,
3275 const struct rte_flow_attr *attr, uint64_t *action_flags,
3276 int *actions_n, const struct rte_flow_action *action,
3277 uint64_t item_flags, struct rte_flow_error *error)
3279 const struct mlx5_priv *priv = dev->data->dev_private;
3282 if (encap && (!encap->size || !encap->data))
3283 return rte_flow_error_set(error, EINVAL,
3284 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3285 "raw encap data cannot be empty");
3286 if (decap && encap) {
3287 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3288 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3291 else if (encap->size <=
3292 MLX5_ENCAPSULATION_DECISION_SIZE &&
3294 MLX5_ENCAPSULATION_DECISION_SIZE)
3297 else if (encap->size >
3298 MLX5_ENCAPSULATION_DECISION_SIZE &&
3300 MLX5_ENCAPSULATION_DECISION_SIZE)
3301 /* 2 L2 actions: encap and decap. */
3304 return rte_flow_error_set(error,
3306 RTE_FLOW_ERROR_TYPE_ACTION,
3307 NULL, "unsupported too small "
3308 "raw decap and too small raw "
3309 "encap combination");
3312 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3313 item_flags, attr, error);
3316 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3320 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3321 return rte_flow_error_set(error, ENOTSUP,
3322 RTE_FLOW_ERROR_TYPE_ACTION,
3324 "small raw encap size");
3325 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3326 return rte_flow_error_set(error, EINVAL,
3327 RTE_FLOW_ERROR_TYPE_ACTION,
3329 "more than one encap action");
3330 if (!attr->transfer && priv->representor)
3331 return rte_flow_error_set
3333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3334 "encap action for VF representor "
3335 "not supported on NIC table");
3336 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3343 * Match encap_decap resource.
3346 * Pointer to the hash list.
3348 * Pointer to exist resource entry object.
3350 * Key of the new entry.
3352 * Pointer to new encap_decap resource.
3355 * 0 on matching, none-zero otherwise.
3358 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3359 struct mlx5_hlist_entry *entry,
3360 uint64_t key __rte_unused, void *cb_ctx)
3362 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3363 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3364 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3366 cache_resource = container_of(entry,
3367 struct mlx5_flow_dv_encap_decap_resource,
3369 if (resource->reformat_type == cache_resource->reformat_type &&
3370 resource->ft_type == cache_resource->ft_type &&
3371 resource->flags == cache_resource->flags &&
3372 resource->size == cache_resource->size &&
3373 !memcmp((const void *)resource->buf,
3374 (const void *)cache_resource->buf,
3381 * Allocate encap_decap resource.
3384 * Pointer to the hash list.
3386 * Pointer to exist resource entry object.
3388 * Pointer to new encap_decap resource.
3391 * 0 on matching, none-zero otherwise.
3393 struct mlx5_hlist_entry *
3394 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3395 uint64_t key __rte_unused,
3398 struct mlx5_dev_ctx_shared *sh = list->ctx;
3399 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3400 struct mlx5dv_dr_domain *domain;
3401 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3402 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3406 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3407 domain = sh->fdb_domain;
3408 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3409 domain = sh->rx_domain;
3411 domain = sh->tx_domain;
3412 /* Register new encap/decap resource. */
3413 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3415 if (!cache_resource) {
3416 rte_flow_error_set(ctx->error, ENOMEM,
3417 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418 "cannot allocate resource memory");
3421 *cache_resource = *resource;
3422 cache_resource->idx = idx;
3423 ret = mlx5_flow_os_create_flow_action_packet_reformat
3424 (sh->ctx, domain, cache_resource,
3425 &cache_resource->action);
3427 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3428 rte_flow_error_set(ctx->error, ENOMEM,
3429 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3430 NULL, "cannot create action");
3434 return &cache_resource->entry;
3438 * Find existing encap/decap resource or create and register a new one.
3440 * @param[in, out] dev
3441 * Pointer to rte_eth_dev structure.
3442 * @param[in, out] resource
3443 * Pointer to encap/decap resource.
3444 * @parm[in, out] dev_flow
3445 * Pointer to the dev_flow.
3447 * pointer to error structure.
3450 * 0 on success otherwise -errno and errno is set.
3453 flow_dv_encap_decap_resource_register
3454 (struct rte_eth_dev *dev,
3455 struct mlx5_flow_dv_encap_decap_resource *resource,
3456 struct mlx5_flow *dev_flow,
3457 struct rte_flow_error *error)
3459 struct mlx5_priv *priv = dev->data->dev_private;
3460 struct mlx5_dev_ctx_shared *sh = priv->sh;
3461 struct mlx5_hlist_entry *entry;
3465 uint32_t refmt_type:8;
3467 * Header reformat actions can be shared between
3468 * non-root tables. One bit to indicate non-root
3472 uint32_t reserve:15;
3475 } encap_decap_key = {
3477 .ft_type = resource->ft_type,
3478 .refmt_type = resource->reformat_type,
3479 .is_root = !!dev_flow->dv.group,
3483 struct mlx5_flow_cb_ctx ctx = {
3489 resource->flags = dev_flow->dv.group ? 0 : 1;
3490 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3491 sizeof(encap_decap_key.v32), 0);
3492 if (resource->reformat_type !=
3493 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3495 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3496 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3499 resource = container_of(entry, typeof(*resource), entry);
3500 dev_flow->dv.encap_decap = resource;
3501 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3506 * Find existing table jump resource or create and register a new one.
3508 * @param[in, out] dev
3509 * Pointer to rte_eth_dev structure.
3510 * @param[in, out] tbl
3511 * Pointer to flow table resource.
3512 * @parm[in, out] dev_flow
3513 * Pointer to the dev_flow.
3515 * pointer to error structure.
3518 * 0 on success otherwise -errno and errno is set.
3521 flow_dv_jump_tbl_resource_register
3522 (struct rte_eth_dev *dev __rte_unused,
3523 struct mlx5_flow_tbl_resource *tbl,
3524 struct mlx5_flow *dev_flow,
3525 struct rte_flow_error *error __rte_unused)
3527 struct mlx5_flow_tbl_data_entry *tbl_data =
3528 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3531 MLX5_ASSERT(tbl_data->jump.action);
3532 dev_flow->handle->rix_jump = tbl_data->idx;
3533 dev_flow->dv.jump = &tbl_data->jump;
3538 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3539 struct mlx5_cache_entry *entry, void *cb_ctx)
3541 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3542 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3543 struct mlx5_flow_dv_port_id_action_resource *res =
3544 container_of(entry, typeof(*res), entry);
3546 return ref->port_id != res->port_id;
3549 struct mlx5_cache_entry *
3550 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3551 struct mlx5_cache_entry *entry __rte_unused,
3554 struct mlx5_dev_ctx_shared *sh = list->ctx;
3555 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3556 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3557 struct mlx5_flow_dv_port_id_action_resource *cache;
3561 /* Register new port id action resource. */
3562 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3564 rte_flow_error_set(ctx->error, ENOMEM,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566 "cannot allocate port_id action cache memory");
3570 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3574 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3575 rte_flow_error_set(ctx->error, ENOMEM,
3576 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3577 "cannot create action");
3581 return &cache->entry;
3585 * Find existing table port ID resource or create and register a new one.
3587 * @param[in, out] dev
3588 * Pointer to rte_eth_dev structure.
3589 * @param[in, out] resource
3590 * Pointer to port ID action resource.
3591 * @parm[in, out] dev_flow
3592 * Pointer to the dev_flow.
3594 * pointer to error structure.
3597 * 0 on success otherwise -errno and errno is set.
3600 flow_dv_port_id_action_resource_register
3601 (struct rte_eth_dev *dev,
3602 struct mlx5_flow_dv_port_id_action_resource *resource,
3603 struct mlx5_flow *dev_flow,
3604 struct rte_flow_error *error)
3606 struct mlx5_priv *priv = dev->data->dev_private;
3607 struct mlx5_cache_entry *entry;
3608 struct mlx5_flow_dv_port_id_action_resource *cache;
3609 struct mlx5_flow_cb_ctx ctx = {
3614 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3617 cache = container_of(entry, typeof(*cache), entry);
3618 dev_flow->dv.port_id_action = cache;
3619 dev_flow->handle->rix_port_id_action = cache->idx;
3624 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3625 struct mlx5_cache_entry *entry, void *cb_ctx)
3627 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3628 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3629 struct mlx5_flow_dv_push_vlan_action_resource *res =
3630 container_of(entry, typeof(*res), entry);
3632 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3635 struct mlx5_cache_entry *
3636 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3637 struct mlx5_cache_entry *entry __rte_unused,
3640 struct mlx5_dev_ctx_shared *sh = list->ctx;
3641 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3643 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3644 struct mlx5dv_dr_domain *domain;
3648 /* Register new port id action resource. */
3649 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3651 rte_flow_error_set(ctx->error, ENOMEM,
3652 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3653 "cannot allocate push_vlan action cache memory");
3657 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3658 domain = sh->fdb_domain;
3659 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3660 domain = sh->rx_domain;
3662 domain = sh->tx_domain;
3663 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3666 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3667 rte_flow_error_set(ctx->error, ENOMEM,
3668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669 "cannot create push vlan action");
3673 return &cache->entry;
3677 * Find existing push vlan resource or create and register a new one.
3679 * @param [in, out] dev
3680 * Pointer to rte_eth_dev structure.
3681 * @param[in, out] resource
3682 * Pointer to port ID action resource.
3683 * @parm[in, out] dev_flow
3684 * Pointer to the dev_flow.
3686 * pointer to error structure.
3689 * 0 on success otherwise -errno and errno is set.
3692 flow_dv_push_vlan_action_resource_register
3693 (struct rte_eth_dev *dev,
3694 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3695 struct mlx5_flow *dev_flow,
3696 struct rte_flow_error *error)
3698 struct mlx5_priv *priv = dev->data->dev_private;
3699 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700 struct mlx5_cache_entry *entry;
3701 struct mlx5_flow_cb_ctx ctx = {
3706 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3709 cache = container_of(entry, typeof(*cache), entry);
3711 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3712 dev_flow->dv.push_vlan_res = cache;
3717 * Get the size of specific rte_flow_item_type hdr size
3719 * @param[in] item_type
3720 * Tested rte_flow_item_type.
3723 * sizeof struct item_type, 0 if void or irrelevant.
3726 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3730 switch (item_type) {
3731 case RTE_FLOW_ITEM_TYPE_ETH:
3732 retval = sizeof(struct rte_ether_hdr);
3734 case RTE_FLOW_ITEM_TYPE_VLAN:
3735 retval = sizeof(struct rte_vlan_hdr);
3737 case RTE_FLOW_ITEM_TYPE_IPV4:
3738 retval = sizeof(struct rte_ipv4_hdr);
3740 case RTE_FLOW_ITEM_TYPE_IPV6:
3741 retval = sizeof(struct rte_ipv6_hdr);
3743 case RTE_FLOW_ITEM_TYPE_UDP:
3744 retval = sizeof(struct rte_udp_hdr);
3746 case RTE_FLOW_ITEM_TYPE_TCP:
3747 retval = sizeof(struct rte_tcp_hdr);
3749 case RTE_FLOW_ITEM_TYPE_VXLAN:
3750 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3751 retval = sizeof(struct rte_vxlan_hdr);
3753 case RTE_FLOW_ITEM_TYPE_GRE:
3754 case RTE_FLOW_ITEM_TYPE_NVGRE:
3755 retval = sizeof(struct rte_gre_hdr);
3757 case RTE_FLOW_ITEM_TYPE_MPLS:
3758 retval = sizeof(struct rte_mpls_hdr);
3760 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3768 #define MLX5_ENCAP_IPV4_VERSION 0x40
3769 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3770 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3771 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3772 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3773 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3774 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3777 * Convert the encap action data from list of rte_flow_item to raw buffer
3780 * Pointer to rte_flow_item objects list.
3782 * Pointer to the output buffer.
3784 * Pointer to the output buffer size.
3786 * Pointer to the error structure.
3789 * 0 on success, a negative errno value otherwise and rte_errno is set.
3792 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3793 size_t *size, struct rte_flow_error *error)
3795 struct rte_ether_hdr *eth = NULL;
3796 struct rte_vlan_hdr *vlan = NULL;
3797 struct rte_ipv4_hdr *ipv4 = NULL;
3798 struct rte_ipv6_hdr *ipv6 = NULL;
3799 struct rte_udp_hdr *udp = NULL;
3800 struct rte_vxlan_hdr *vxlan = NULL;
3801 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3802 struct rte_gre_hdr *gre = NULL;
3804 size_t temp_size = 0;
3807 return rte_flow_error_set(error, EINVAL,
3808 RTE_FLOW_ERROR_TYPE_ACTION,
3809 NULL, "invalid empty data");
3810 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3811 len = flow_dv_get_item_hdr_len(items->type);
3812 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3813 return rte_flow_error_set(error, EINVAL,
3814 RTE_FLOW_ERROR_TYPE_ACTION,
3815 (void *)items->type,
3816 "items total size is too big"
3817 " for encap action");
3818 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3819 switch (items->type) {
3820 case RTE_FLOW_ITEM_TYPE_ETH:
3821 eth = (struct rte_ether_hdr *)&buf[temp_size];
3823 case RTE_FLOW_ITEM_TYPE_VLAN:
3824 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3826 return rte_flow_error_set(error, EINVAL,
3827 RTE_FLOW_ERROR_TYPE_ACTION,
3828 (void *)items->type,
3829 "eth header not found");
3830 if (!eth->ether_type)
3831 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3833 case RTE_FLOW_ITEM_TYPE_IPV4:
3834 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3836 return rte_flow_error_set(error, EINVAL,
3837 RTE_FLOW_ERROR_TYPE_ACTION,
3838 (void *)items->type,
3839 "neither eth nor vlan"
3841 if (vlan && !vlan->eth_proto)
3842 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3843 else if (eth && !eth->ether_type)
3844 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845 if (!ipv4->version_ihl)
3846 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3847 MLX5_ENCAP_IPV4_IHL_MIN;
3848 if (!ipv4->time_to_live)
3849 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3851 case RTE_FLOW_ITEM_TYPE_IPV6:
3852 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3854 return rte_flow_error_set(error, EINVAL,
3855 RTE_FLOW_ERROR_TYPE_ACTION,
3856 (void *)items->type,
3857 "neither eth nor vlan"
3859 if (vlan && !vlan->eth_proto)
3860 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3861 else if (eth && !eth->ether_type)
3862 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863 if (!ipv6->vtc_flow)
3865 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3866 if (!ipv6->hop_limits)
3867 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3869 case RTE_FLOW_ITEM_TYPE_UDP:
3870 udp = (struct rte_udp_hdr *)&buf[temp_size];
3872 return rte_flow_error_set(error, EINVAL,
3873 RTE_FLOW_ERROR_TYPE_ACTION,
3874 (void *)items->type,
3875 "ip header not found");
3876 if (ipv4 && !ipv4->next_proto_id)
3877 ipv4->next_proto_id = IPPROTO_UDP;
3878 else if (ipv6 && !ipv6->proto)
3879 ipv6->proto = IPPROTO_UDP;
3881 case RTE_FLOW_ITEM_TYPE_VXLAN:
3882 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3884 return rte_flow_error_set(error, EINVAL,
3885 RTE_FLOW_ERROR_TYPE_ACTION,
3886 (void *)items->type,
3887 "udp header not found");
3889 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3890 if (!vxlan->vx_flags)
3892 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3894 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3895 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3897 return rte_flow_error_set(error, EINVAL,
3898 RTE_FLOW_ERROR_TYPE_ACTION,
3899 (void *)items->type,
3900 "udp header not found");
3901 if (!vxlan_gpe->proto)
3902 return rte_flow_error_set(error, EINVAL,
3903 RTE_FLOW_ERROR_TYPE_ACTION,
3904 (void *)items->type,
3905 "next protocol not found");
3908 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3909 if (!vxlan_gpe->vx_flags)
3910 vxlan_gpe->vx_flags =
3911 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3913 case RTE_FLOW_ITEM_TYPE_GRE:
3914 case RTE_FLOW_ITEM_TYPE_NVGRE:
3915 gre = (struct rte_gre_hdr *)&buf[temp_size];
3917 return rte_flow_error_set(error, EINVAL,
3918 RTE_FLOW_ERROR_TYPE_ACTION,
3919 (void *)items->type,
3920 "next protocol not found");
3922 return rte_flow_error_set(error, EINVAL,
3923 RTE_FLOW_ERROR_TYPE_ACTION,
3924 (void *)items->type,
3925 "ip header not found");
3926 if (ipv4 && !ipv4->next_proto_id)
3927 ipv4->next_proto_id = IPPROTO_GRE;
3928 else if (ipv6 && !ipv6->proto)
3929 ipv6->proto = IPPROTO_GRE;
3931 case RTE_FLOW_ITEM_TYPE_VOID:
3934 return rte_flow_error_set(error, EINVAL,
3935 RTE_FLOW_ERROR_TYPE_ACTION,
3936 (void *)items->type,
3937 "unsupported item type");
3947 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3949 struct rte_ether_hdr *eth = NULL;
3950 struct rte_vlan_hdr *vlan = NULL;
3951 struct rte_ipv6_hdr *ipv6 = NULL;
3952 struct rte_udp_hdr *udp = NULL;
3956 eth = (struct rte_ether_hdr *)data;
3957 next_hdr = (char *)(eth + 1);
3958 proto = RTE_BE16(eth->ether_type);
3961 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3962 vlan = (struct rte_vlan_hdr *)next_hdr;
3963 proto = RTE_BE16(vlan->eth_proto);
3964 next_hdr += sizeof(struct rte_vlan_hdr);
3967 /* HW calculates IPv4 csum. no need to proceed */
3968 if (proto == RTE_ETHER_TYPE_IPV4)
3971 /* non IPv4/IPv6 header. not supported */
3972 if (proto != RTE_ETHER_TYPE_IPV6) {
3973 return rte_flow_error_set(error, ENOTSUP,
3974 RTE_FLOW_ERROR_TYPE_ACTION,
3975 NULL, "Cannot offload non IPv4/IPv6");
3978 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3980 /* ignore non UDP */
3981 if (ipv6->proto != IPPROTO_UDP)
3984 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3985 udp->dgram_cksum = 0;
3991 * Convert L2 encap action to DV specification.
3994 * Pointer to rte_eth_dev structure.
3996 * Pointer to action structure.
3997 * @param[in, out] dev_flow
3998 * Pointer to the mlx5_flow.
3999 * @param[in] transfer
4000 * Mark if the flow is E-Switch flow.
4002 * Pointer to the error structure.
4005 * 0 on success, a negative errno value otherwise and rte_errno is set.
4008 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4009 const struct rte_flow_action *action,
4010 struct mlx5_flow *dev_flow,
4012 struct rte_flow_error *error)
4014 const struct rte_flow_item *encap_data;
4015 const struct rte_flow_action_raw_encap *raw_encap_data;
4016 struct mlx5_flow_dv_encap_decap_resource res = {
4018 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4019 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4020 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4023 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4025 (const struct rte_flow_action_raw_encap *)action->conf;
4026 res.size = raw_encap_data->size;
4027 memcpy(res.buf, raw_encap_data->data, res.size);
4029 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4031 ((const struct rte_flow_action_vxlan_encap *)
4032 action->conf)->definition;
4035 ((const struct rte_flow_action_nvgre_encap *)
4036 action->conf)->definition;
4037 if (flow_dv_convert_encap_data(encap_data, res.buf,
4041 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4043 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4044 return rte_flow_error_set(error, EINVAL,
4045 RTE_FLOW_ERROR_TYPE_ACTION,
4046 NULL, "can't create L2 encap action");
4051 * Convert L2 decap action to DV specification.
4054 * Pointer to rte_eth_dev structure.
4055 * @param[in, out] dev_flow
4056 * Pointer to the mlx5_flow.
4057 * @param[in] transfer
4058 * Mark if the flow is E-Switch flow.
4060 * Pointer to the error structure.
4063 * 0 on success, a negative errno value otherwise and rte_errno is set.
4066 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4067 struct mlx5_flow *dev_flow,
4069 struct rte_flow_error *error)
4071 struct mlx5_flow_dv_encap_decap_resource res = {
4074 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4075 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4079 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4080 return rte_flow_error_set(error, EINVAL,
4081 RTE_FLOW_ERROR_TYPE_ACTION,
4082 NULL, "can't create L2 decap action");
4087 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4090 * Pointer to rte_eth_dev structure.
4092 * Pointer to action structure.
4093 * @param[in, out] dev_flow
4094 * Pointer to the mlx5_flow.
4096 * Pointer to the flow attributes.
4098 * Pointer to the error structure.
4101 * 0 on success, a negative errno value otherwise and rte_errno is set.
4104 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4105 const struct rte_flow_action *action,
4106 struct mlx5_flow *dev_flow,
4107 const struct rte_flow_attr *attr,
4108 struct rte_flow_error *error)
4110 const struct rte_flow_action_raw_encap *encap_data;
4111 struct mlx5_flow_dv_encap_decap_resource res;
4113 memset(&res, 0, sizeof(res));
4114 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4115 res.size = encap_data->size;
4116 memcpy(res.buf, encap_data->data, res.size);
4117 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4118 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4119 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4121 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4123 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4124 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4125 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4126 return rte_flow_error_set(error, EINVAL,
4127 RTE_FLOW_ERROR_TYPE_ACTION,
4128 NULL, "can't create encap action");
4133 * Create action push VLAN.
4136 * Pointer to rte_eth_dev structure.
4138 * Pointer to the flow attributes.
4140 * Pointer to the vlan to push to the Ethernet header.
4141 * @param[in, out] dev_flow
4142 * Pointer to the mlx5_flow.
4144 * Pointer to the error structure.
4147 * 0 on success, a negative errno value otherwise and rte_errno is set.
4150 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4151 const struct rte_flow_attr *attr,
4152 const struct rte_vlan_hdr *vlan,
4153 struct mlx5_flow *dev_flow,
4154 struct rte_flow_error *error)
4156 struct mlx5_flow_dv_push_vlan_action_resource res;
4158 memset(&res, 0, sizeof(res));
4160 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4163 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4165 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4166 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4167 return flow_dv_push_vlan_action_resource_register
4168 (dev, &res, dev_flow, error);
4172 * Validate the modify-header actions.
4174 * @param[in] action_flags
4175 * Holds the actions detected until now.
4177 * Pointer to the modify action.
4179 * Pointer to error structure.
4182 * 0 on success, a negative errno value otherwise and rte_errno is set.
4185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4186 const struct rte_flow_action *action,
4187 struct rte_flow_error *error)
4189 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4190 return rte_flow_error_set(error, EINVAL,
4191 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4192 NULL, "action configuration not set");
4193 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4194 return rte_flow_error_set(error, EINVAL,
4195 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196 "can't have encap action before"
4202 * Validate the modify-header MAC address actions.
4204 * @param[in] action_flags
4205 * Holds the actions detected until now.
4207 * Pointer to the modify action.
4208 * @param[in] item_flags
4209 * Holds the items detected.
4211 * Pointer to error structure.
4214 * 0 on success, a negative errno value otherwise and rte_errno is set.
4217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4218 const struct rte_flow_action *action,
4219 const uint64_t item_flags,
4220 struct rte_flow_error *error)
4224 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4226 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4227 return rte_flow_error_set(error, EINVAL,
4228 RTE_FLOW_ERROR_TYPE_ACTION,
4230 "no L2 item in pattern");
4236 * Validate the modify-header IPv4 address actions.
4238 * @param[in] action_flags
4239 * Holds the actions detected until now.
4241 * Pointer to the modify action.
4242 * @param[in] item_flags
4243 * Holds the items detected.
4245 * Pointer to error structure.
4248 * 0 on success, a negative errno value otherwise and rte_errno is set.
4251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4252 const struct rte_flow_action *action,
4253 const uint64_t item_flags,
4254 struct rte_flow_error *error)
4259 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4261 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4262 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4263 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4264 if (!(item_flags & layer))
4265 return rte_flow_error_set(error, EINVAL,
4266 RTE_FLOW_ERROR_TYPE_ACTION,
4268 "no ipv4 item in pattern");
4274 * Validate the modify-header IPv6 address actions.
4276 * @param[in] action_flags
4277 * Holds the actions detected until now.
4279 * Pointer to the modify action.
4280 * @param[in] item_flags
4281 * Holds the items detected.
4283 * Pointer to error structure.
4286 * 0 on success, a negative errno value otherwise and rte_errno is set.
4289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4290 const struct rte_flow_action *action,
4291 const uint64_t item_flags,
4292 struct rte_flow_error *error)
4297 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4299 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4300 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4301 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4302 if (!(item_flags & layer))
4303 return rte_flow_error_set(error, EINVAL,
4304 RTE_FLOW_ERROR_TYPE_ACTION,
4306 "no ipv6 item in pattern");
4312 * Validate the modify-header TP actions.
4314 * @param[in] action_flags
4315 * Holds the actions detected until now.
4317 * Pointer to the modify action.
4318 * @param[in] item_flags
4319 * Holds the items detected.
4321 * Pointer to error structure.
4324 * 0 on success, a negative errno value otherwise and rte_errno is set.
4327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4328 const struct rte_flow_action *action,
4329 const uint64_t item_flags,
4330 struct rte_flow_error *error)
4335 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4337 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4338 MLX5_FLOW_LAYER_INNER_L4 :
4339 MLX5_FLOW_LAYER_OUTER_L4;
4340 if (!(item_flags & layer))
4341 return rte_flow_error_set(error, EINVAL,
4342 RTE_FLOW_ERROR_TYPE_ACTION,
4343 NULL, "no transport layer "
4350 * Validate the modify-header actions of increment/decrement
4351 * TCP Sequence-number.
4353 * @param[in] action_flags
4354 * Holds the actions detected until now.
4356 * Pointer to the modify action.
4357 * @param[in] item_flags
4358 * Holds the items detected.
4360 * Pointer to error structure.
4363 * 0 on success, a negative errno value otherwise and rte_errno is set.
4366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4367 const struct rte_flow_action *action,
4368 const uint64_t item_flags,
4369 struct rte_flow_error *error)
4374 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4376 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4377 MLX5_FLOW_LAYER_INNER_L4_TCP :
4378 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4379 if (!(item_flags & layer))
4380 return rte_flow_error_set(error, EINVAL,
4381 RTE_FLOW_ERROR_TYPE_ACTION,
4382 NULL, "no TCP item in"
4384 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4385 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4386 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4387 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4388 return rte_flow_error_set(error, EINVAL,
4389 RTE_FLOW_ERROR_TYPE_ACTION,
4391 "cannot decrease and increase"
4392 " TCP sequence number"
4393 " at the same time");
4399 * Validate the modify-header actions of increment/decrement
4400 * TCP Acknowledgment number.
4402 * @param[in] action_flags
4403 * Holds the actions detected until now.
4405 * Pointer to the modify action.
4406 * @param[in] item_flags
4407 * Holds the items detected.
4409 * Pointer to error structure.
4412 * 0 on success, a negative errno value otherwise and rte_errno is set.
4415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4416 const struct rte_flow_action *action,
4417 const uint64_t item_flags,
4418 struct rte_flow_error *error)
4423 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4425 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4426 MLX5_FLOW_LAYER_INNER_L4_TCP :
4427 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4428 if (!(item_flags & layer))
4429 return rte_flow_error_set(error, EINVAL,
4430 RTE_FLOW_ERROR_TYPE_ACTION,
4431 NULL, "no TCP item in"
4433 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4434 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4435 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4436 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4437 return rte_flow_error_set(error, EINVAL,
4438 RTE_FLOW_ERROR_TYPE_ACTION,
4440 "cannot decrease and increase"
4441 " TCP acknowledgment number"
4442 " at the same time");
4448 * Validate the modify-header TTL actions.
4450 * @param[in] action_flags
4451 * Holds the actions detected until now.
4453 * Pointer to the modify action.
4454 * @param[in] item_flags
4455 * Holds the items detected.
4457 * Pointer to error structure.
4460 * 0 on success, a negative errno value otherwise and rte_errno is set.
4463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4464 const struct rte_flow_action *action,
4465 const uint64_t item_flags,
4466 struct rte_flow_error *error)
4471 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4473 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4474 MLX5_FLOW_LAYER_INNER_L3 :
4475 MLX5_FLOW_LAYER_OUTER_L3;
4476 if (!(item_flags & layer))
4477 return rte_flow_error_set(error, EINVAL,
4478 RTE_FLOW_ERROR_TYPE_ACTION,
4480 "no IP protocol in pattern");
4486 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4489 case RTE_FLOW_FIELD_START:
4491 case RTE_FLOW_FIELD_MAC_DST:
4492 case RTE_FLOW_FIELD_MAC_SRC:
4494 case RTE_FLOW_FIELD_VLAN_TYPE:
4496 case RTE_FLOW_FIELD_VLAN_ID:
4498 case RTE_FLOW_FIELD_MAC_TYPE:
4500 case RTE_FLOW_FIELD_IPV4_DSCP:
4502 case RTE_FLOW_FIELD_IPV4_TTL:
4504 case RTE_FLOW_FIELD_IPV4_SRC:
4505 case RTE_FLOW_FIELD_IPV4_DST:
4507 case RTE_FLOW_FIELD_IPV6_DSCP:
4509 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4511 case RTE_FLOW_FIELD_IPV6_SRC:
4512 case RTE_FLOW_FIELD_IPV6_DST:
4514 case RTE_FLOW_FIELD_TCP_PORT_SRC:
4515 case RTE_FLOW_FIELD_TCP_PORT_DST:
4517 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4518 case RTE_FLOW_FIELD_TCP_ACK_NUM:
4520 case RTE_FLOW_FIELD_TCP_FLAGS:
4522 case RTE_FLOW_FIELD_UDP_PORT_SRC:
4523 case RTE_FLOW_FIELD_UDP_PORT_DST:
4525 case RTE_FLOW_FIELD_VXLAN_VNI:
4526 case RTE_FLOW_FIELD_GENEVE_VNI:
4528 case RTE_FLOW_FIELD_GTP_TEID:
4529 case RTE_FLOW_FIELD_TAG:
4531 case RTE_FLOW_FIELD_MARK:
4533 case RTE_FLOW_FIELD_META:
4534 case RTE_FLOW_FIELD_POINTER:
4535 case RTE_FLOW_FIELD_VALUE:
4544 * Validate the generic modify field actions.
4546 * Pointer to the rte_eth_dev structure.
4547 * @param[in] action_flags
4548 * Holds the actions detected until now.
4550 * Pointer to the modify action.
4552 * Pointer to the flow attributes.
4554 * Pointer to error structure.
4557 * Number of header fields to modify (0 or more) on success,
4558 * a negative errno value otherwise and rte_errno is set.
4561 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4562 const uint64_t action_flags,
4563 const struct rte_flow_action *action,
4564 const struct rte_flow_attr *attr,
4565 struct rte_flow_error *error)
4568 struct mlx5_priv *priv = dev->data->dev_private;
4569 struct mlx5_dev_config *config = &priv->config;
4570 const struct rte_flow_action_modify_field *action_modify_field =
4572 uint32_t dst_width =
4573 mlx5_flow_item_field_width(action_modify_field->dst.field);
4574 uint32_t src_width =
4575 mlx5_flow_item_field_width(action_modify_field->src.field);
4577 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4581 if (action_modify_field->width == 0)
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no bits are requested to be modified");
4586 else if (action_modify_field->width > dst_width ||
4587 action_modify_field->width > src_width)
4588 return rte_flow_error_set(error, EINVAL,
4589 RTE_FLOW_ERROR_TYPE_ACTION,
4591 "cannot modify more bits than"
4592 " the width of a field");
4593 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4594 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4595 if ((action_modify_field->dst.offset +
4596 action_modify_field->width > dst_width) ||
4597 (action_modify_field->dst.offset % 32))
4598 return rte_flow_error_set(error, EINVAL,
4599 RTE_FLOW_ERROR_TYPE_ACTION,
4601 "destination offset is too big"
4602 " or not aligned to 4 bytes");
4603 if (action_modify_field->dst.level &&
4604 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4605 return rte_flow_error_set(error, EINVAL,
4606 RTE_FLOW_ERROR_TYPE_ACTION,
4608 "cannot modify inner headers");
4610 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4611 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4612 if (!attr->transfer && !attr->group)
4613 return rte_flow_error_set(error, ENOTSUP,
4614 RTE_FLOW_ERROR_TYPE_ACTION,
4615 NULL, "modify field action "
4616 "is not supported for group 0");
4617 if ((action_modify_field->src.offset +
4618 action_modify_field->width > src_width) ||
4619 (action_modify_field->src.offset % 32))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "source offset is too big"
4624 " or not aligned to 4 bytes");
4625 if (action_modify_field->src.level &&
4626 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4627 return rte_flow_error_set(error, EINVAL,
4628 RTE_FLOW_ERROR_TYPE_ACTION,
4630 "cannot copy from inner headers");
4632 if (action_modify_field->dst.field ==
4633 action_modify_field->src.field)
4634 return rte_flow_error_set(error, EINVAL,
4635 RTE_FLOW_ERROR_TYPE_ACTION,
4637 "source and destination fields"
4638 " cannot be the same");
4639 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4640 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4641 return rte_flow_error_set(error, EINVAL,
4642 RTE_FLOW_ERROR_TYPE_ACTION,
4644 "immediate value or a pointer to it"
4645 " cannot be used as a destination");
4646 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4647 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4648 return rte_flow_error_set(error, EINVAL,
4649 RTE_FLOW_ERROR_TYPE_ACTION,
4651 "modifications of an arbitrary"
4652 " place in a packet is not supported");
4653 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4654 action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
4655 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4656 !mlx5_flow_ext_mreg_supported(dev))
4657 return rte_flow_error_set(error, ENOTSUP,
4658 RTE_FLOW_ERROR_TYPE_ACTION, action,
4659 "cannot modify mark without extended"
4660 " metadata register support");
4662 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4663 return rte_flow_error_set(error, EINVAL,
4664 RTE_FLOW_ERROR_TYPE_ACTION,
4666 "add and sub operations"
4667 " are not supported");
4668 return (action_modify_field->width / 32) +
4669 !!(action_modify_field->width % 32);
4673 * Validate jump action.
4676 * Pointer to the jump action.
4677 * @param[in] action_flags
4678 * Holds the actions detected until now.
4679 * @param[in] attributes
4680 * Pointer to flow attributes
4681 * @param[in] external
4682 * Action belongs to flow rule created by request external to PMD.
4684 * Pointer to error structure.
4687 * 0 on success, a negative errno value otherwise and rte_errno is set.
4690 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4691 const struct mlx5_flow_tunnel *tunnel,
4692 const struct rte_flow_action *action,
4693 uint64_t action_flags,
4694 const struct rte_flow_attr *attributes,
4695 bool external, struct rte_flow_error *error)
4697 uint32_t target_group, table;
4699 struct flow_grp_info grp_info = {
4700 .external = !!external,
4701 .transfer = !!attributes->transfer,
4705 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4706 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4707 return rte_flow_error_set(error, EINVAL,
4708 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4709 "can't have 2 fate actions in"
4711 if (action_flags & MLX5_FLOW_ACTION_METER)
4712 return rte_flow_error_set(error, ENOTSUP,
4713 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4714 "jump with meter not support");
4716 return rte_flow_error_set(error, EINVAL,
4717 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4718 NULL, "action configuration not set");
4720 ((const struct rte_flow_action_jump *)action->conf)->group;
4721 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4725 if (attributes->group == target_group &&
4726 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4727 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4728 return rte_flow_error_set(error, EINVAL,
4729 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4730 "target group must be other than"
4731 " the current flow group");
4736 * Validate the port_id action.
4739 * Pointer to rte_eth_dev structure.
4740 * @param[in] action_flags
4741 * Bit-fields that holds the actions detected until now.
4743 * Port_id RTE action structure.
4745 * Attributes of flow that includes this action.
4747 * Pointer to error structure.
4750 * 0 on success, a negative errno value otherwise and rte_errno is set.
4753 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4754 uint64_t action_flags,
4755 const struct rte_flow_action *action,
4756 const struct rte_flow_attr *attr,
4757 struct rte_flow_error *error)
4759 const struct rte_flow_action_port_id *port_id;
4760 struct mlx5_priv *act_priv;
4761 struct mlx5_priv *dev_priv;
4764 if (!attr->transfer)
4765 return rte_flow_error_set(error, ENOTSUP,
4766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4768 "port id action is valid in transfer"
4770 if (!action || !action->conf)
4771 return rte_flow_error_set(error, ENOTSUP,
4772 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4774 "port id action parameters must be"
4776 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4777 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4778 return rte_flow_error_set(error, EINVAL,
4779 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4780 "can have only one fate actions in"
4782 dev_priv = mlx5_dev_to_eswitch_info(dev);
4784 return rte_flow_error_set(error, rte_errno,
4785 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4787 "failed to obtain E-Switch info");
4788 port_id = action->conf;
4789 port = port_id->original ? dev->data->port_id : port_id->id;
4790 act_priv = mlx5_port_to_eswitch_info(port, false);
4792 return rte_flow_error_set
4794 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4795 "failed to obtain E-Switch port id for port");
4796 if (act_priv->domain_id != dev_priv->domain_id)
4797 return rte_flow_error_set
4799 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4800 "port does not belong to"
4801 " E-Switch being configured");
4806 * Get the maximum number of modify header actions.
4809 * Pointer to rte_eth_dev structure.
4811 * Flags bits to check if root level.
4814 * Max number of modify header actions device can support.
4816 static inline unsigned int
4817 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4821 * There's no way to directly query the max capacity from FW.
4822 * The maximal value on root table should be assumed to be supported.
4824 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4825 return MLX5_MAX_MODIFY_NUM;
4827 return MLX5_ROOT_TBL_MODIFY_NUM;
4831 * Validate the meter action.
4834 * Pointer to rte_eth_dev structure.
4835 * @param[in] action_flags
4836 * Bit-fields that holds the actions detected until now.
4838 * Pointer to the meter action.
4840 * Attributes of flow that includes this action.
4842 * Pointer to error structure.
4845 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4848 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4849 uint64_t action_flags,
4850 const struct rte_flow_action *action,
4851 const struct rte_flow_attr *attr,
4852 struct rte_flow_error *error)
4854 struct mlx5_priv *priv = dev->data->dev_private;
4855 const struct rte_flow_action_meter *am = action->conf;
4856 struct mlx5_flow_meter *fm;
4859 return rte_flow_error_set(error, EINVAL,
4860 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4861 "meter action conf is NULL");
4863 if (action_flags & MLX5_FLOW_ACTION_METER)
4864 return rte_flow_error_set(error, ENOTSUP,
4865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4866 "meter chaining not support");
4867 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4868 return rte_flow_error_set(error, ENOTSUP,
4869 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4870 "meter with jump not support");
4872 return rte_flow_error_set(error, ENOTSUP,
4873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4875 "meter action not supported");
4876 fm = mlx5_flow_meter_find(priv, am->mtr_id);
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4881 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4882 (!fm->ingress && !attr->ingress && attr->egress) ||
4883 (!fm->egress && !attr->egress && attr->ingress))))
4884 return rte_flow_error_set(error, EINVAL,
4885 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4886 "Flow attributes are either invalid "
4887 "or have a conflict with current "
4888 "meter attributes");
4893 * Validate the age action.
4895 * @param[in] action_flags
4896 * Holds the actions detected until now.
4898 * Pointer to the age action.
4900 * Pointer to the Ethernet device structure.
4902 * Pointer to error structure.
4905 * 0 on success, a negative errno value otherwise and rte_errno is set.
4908 flow_dv_validate_action_age(uint64_t action_flags,
4909 const struct rte_flow_action *action,
4910 struct rte_eth_dev *dev,
4911 struct rte_flow_error *error)
4913 struct mlx5_priv *priv = dev->data->dev_private;
4914 const struct rte_flow_action_age *age = action->conf;
4916 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4917 !priv->sh->aso_age_mng))
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4921 "age action not supported");
4922 if (!(action->conf))
4923 return rte_flow_error_set(error, EINVAL,
4924 RTE_FLOW_ERROR_TYPE_ACTION, action,
4925 "configuration cannot be null");
4926 if (!(age->timeout))
4927 return rte_flow_error_set(error, EINVAL,
4928 RTE_FLOW_ERROR_TYPE_ACTION, action,
4929 "invalid timeout value 0");
4930 if (action_flags & MLX5_FLOW_ACTION_AGE)
4931 return rte_flow_error_set(error, EINVAL,
4932 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4933 "duplicate age actions set");
4938 * Validate the modify-header IPv4 DSCP actions.
4940 * @param[in] action_flags
4941 * Holds the actions detected until now.
4943 * Pointer to the modify action.
4944 * @param[in] item_flags
4945 * Holds the items detected.
4947 * Pointer to error structure.
4950 * 0 on success, a negative errno value otherwise and rte_errno is set.
4953 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4954 const struct rte_flow_action *action,
4955 const uint64_t item_flags,
4956 struct rte_flow_error *error)
4960 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4962 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4963 return rte_flow_error_set(error, EINVAL,
4964 RTE_FLOW_ERROR_TYPE_ACTION,
4966 "no ipv4 item in pattern");
4972 * Validate the modify-header IPv6 DSCP actions.
4974 * @param[in] action_flags
4975 * Holds the actions detected until now.
4977 * Pointer to the modify action.
4978 * @param[in] item_flags
4979 * Holds the items detected.
4981 * Pointer to error structure.
4984 * 0 on success, a negative errno value otherwise and rte_errno is set.
4987 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4988 const struct rte_flow_action *action,
4989 const uint64_t item_flags,
4990 struct rte_flow_error *error)
4994 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4996 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4997 return rte_flow_error_set(error, EINVAL,
4998 RTE_FLOW_ERROR_TYPE_ACTION,
5000 "no ipv6 item in pattern");
5006 * Match modify-header resource.
5009 * Pointer to the hash list.
5011 * Pointer to exist resource entry object.
5013 * Key of the new entry.
5015 * Pointer to new modify-header resource.
5018 * 0 on matching, non-zero otherwise.
5021 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5022 struct mlx5_hlist_entry *entry,
5023 uint64_t key __rte_unused, void *cb_ctx)
5025 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5026 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5027 struct mlx5_flow_dv_modify_hdr_resource *resource =
5028 container_of(entry, typeof(*resource), entry);
5029 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5031 key_len += ref->actions_num * sizeof(ref->actions[0]);
5032 return ref->actions_num != resource->actions_num ||
5033 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5036 struct mlx5_hlist_entry *
5037 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5040 struct mlx5_dev_ctx_shared *sh = list->ctx;
5041 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5042 struct mlx5dv_dr_domain *ns;
5043 struct mlx5_flow_dv_modify_hdr_resource *entry;
5044 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5046 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5047 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5049 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5052 rte_flow_error_set(ctx->error, ENOMEM,
5053 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5054 "cannot allocate resource memory");
5057 rte_memcpy(&entry->ft_type,
5058 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5059 key_len + data_len);
5060 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5061 ns = sh->fdb_domain;
5062 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5066 ret = mlx5_flow_os_create_flow_action_modify_header
5067 (sh->ctx, ns, entry,
5068 data_len, &entry->action);
5071 rte_flow_error_set(ctx->error, ENOMEM,
5072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5073 NULL, "cannot create modification action");
5076 return &entry->entry;
5080 * Validate the sample action.
5082 * @param[in, out] action_flags
5083 * Holds the actions detected until now.
5085 * Pointer to the sample action.
5087 * Pointer to the Ethernet device structure.
5089 * Attributes of flow that includes this action.
5090 * @param[in] item_flags
5091 * Holds the items detected.
5093 * Pointer to the RSS action.
5094 * @param[out] sample_rss
5095 * Pointer to the RSS action in sample action list.
5097 * Pointer to the COUNT action in sample action list.
5098 * @param[out] fdb_mirror_limit
5099 * Pointer to the FDB mirror limitation flag.
5101 * Pointer to error structure.
5104 * 0 on success, a negative errno value otherwise and rte_errno is set.
5107 flow_dv_validate_action_sample(uint64_t *action_flags,
5108 const struct rte_flow_action *action,
5109 struct rte_eth_dev *dev,
5110 const struct rte_flow_attr *attr,
5111 uint64_t item_flags,
5112 const struct rte_flow_action_rss *rss,
5113 const struct rte_flow_action_rss **sample_rss,
5114 const struct rte_flow_action_count **count,
5115 int *fdb_mirror_limit,
5116 struct rte_flow_error *error)
5118 struct mlx5_priv *priv = dev->data->dev_private;
5119 struct mlx5_dev_config *dev_conf = &priv->config;
5120 const struct rte_flow_action_sample *sample = action->conf;
5121 const struct rte_flow_action *act;
5122 uint64_t sub_action_flags = 0;
5123 uint16_t queue_index = 0xFFFF;
5128 return rte_flow_error_set(error, EINVAL,
5129 RTE_FLOW_ERROR_TYPE_ACTION, action,
5130 "configuration cannot be NULL");
5131 if (sample->ratio == 0)
5132 return rte_flow_error_set(error, EINVAL,
5133 RTE_FLOW_ERROR_TYPE_ACTION, action,
5134 "ratio value starts from 1");
5135 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5136 return rte_flow_error_set(error, ENOTSUP,
5137 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5139 "sample action not supported");
5140 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5141 return rte_flow_error_set(error, EINVAL,
5142 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5143 "Multiple sample actions not "
5145 if (*action_flags & MLX5_FLOW_ACTION_METER)
5146 return rte_flow_error_set(error, EINVAL,
5147 RTE_FLOW_ERROR_TYPE_ACTION, action,
5148 "wrong action order, meter should "
5149 "be after sample action");
5150 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5151 return rte_flow_error_set(error, EINVAL,
5152 RTE_FLOW_ERROR_TYPE_ACTION, action,
5153 "wrong action order, jump should "
5154 "be after sample action");
5155 act = sample->actions;
5156 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5157 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5158 return rte_flow_error_set(error, ENOTSUP,
5159 RTE_FLOW_ERROR_TYPE_ACTION,
5160 act, "too many actions");
5161 switch (act->type) {
5162 case RTE_FLOW_ACTION_TYPE_QUEUE:
5163 ret = mlx5_flow_validate_action_queue(act,
5169 queue_index = ((const struct rte_flow_action_queue *)
5170 (act->conf))->index;
5171 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5174 case RTE_FLOW_ACTION_TYPE_RSS:
5175 *sample_rss = act->conf;
5176 ret = mlx5_flow_validate_action_rss(act,
5183 if (rss && *sample_rss &&
5184 ((*sample_rss)->level != rss->level ||
5185 (*sample_rss)->types != rss->types))
5186 return rte_flow_error_set(error, ENOTSUP,
5187 RTE_FLOW_ERROR_TYPE_ACTION,
5189 "Can't use the different RSS types "
5190 "or level in the same flow");
5191 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5192 queue_index = (*sample_rss)->queue[0];
5193 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5196 case RTE_FLOW_ACTION_TYPE_MARK:
5197 ret = flow_dv_validate_action_mark(dev, act,
5202 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5203 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5204 MLX5_FLOW_ACTION_MARK_EXT;
5206 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5209 case RTE_FLOW_ACTION_TYPE_COUNT:
5210 ret = flow_dv_validate_action_count
5212 *action_flags | sub_action_flags,
5217 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5218 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5221 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5222 ret = flow_dv_validate_action_port_id(dev,
5229 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5232 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5233 ret = flow_dv_validate_action_raw_encap_decap
5234 (dev, NULL, act->conf, attr, &sub_action_flags,
5235 &actions_n, action, item_flags, error);
5241 return rte_flow_error_set(error, ENOTSUP,
5242 RTE_FLOW_ERROR_TYPE_ACTION,
5244 "Doesn't support optional "
5248 if (attr->ingress && !attr->transfer) {
5249 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5250 MLX5_FLOW_ACTION_RSS)))
5251 return rte_flow_error_set(error, EINVAL,
5252 RTE_FLOW_ERROR_TYPE_ACTION,
5254 "Ingress must has a dest "
5255 "QUEUE for Sample");
5256 } else if (attr->egress && !attr->transfer) {
5257 return rte_flow_error_set(error, ENOTSUP,
5258 RTE_FLOW_ERROR_TYPE_ACTION,
5260 "Sample Only support Ingress "
5262 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5263 MLX5_ASSERT(attr->transfer);
5264 if (sample->ratio > 1)
5265 return rte_flow_error_set(error, ENOTSUP,
5266 RTE_FLOW_ERROR_TYPE_ACTION,
5268 "E-Switch doesn't support "
5269 "any optional action "
5271 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5272 return rte_flow_error_set(error, ENOTSUP,
5273 RTE_FLOW_ERROR_TYPE_ACTION,
5275 "unsupported action QUEUE");
5276 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5277 return rte_flow_error_set(error, ENOTSUP,
5278 RTE_FLOW_ERROR_TYPE_ACTION,
5280 "unsupported action QUEUE");
5281 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5282 return rte_flow_error_set(error, EINVAL,
5283 RTE_FLOW_ERROR_TYPE_ACTION,
5285 "E-Switch must has a dest "
5286 "port for mirroring");
5287 if (!priv->config.hca_attr.reg_c_preserve &&
5288 priv->representor_id != -1)
5289 *fdb_mirror_limit = 1;
5291 /* Continue validation for Xcap actions.*/
5292 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5293 (queue_index == 0xFFFF ||
5294 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5295 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5296 MLX5_FLOW_XCAP_ACTIONS)
5297 return rte_flow_error_set(error, ENOTSUP,
5298 RTE_FLOW_ERROR_TYPE_ACTION,
5299 NULL, "encap and decap "
5300 "combination aren't "
5302 if (!attr->transfer && attr->ingress && (sub_action_flags &
5303 MLX5_FLOW_ACTION_ENCAP))
5304 return rte_flow_error_set(error, ENOTSUP,
5305 RTE_FLOW_ERROR_TYPE_ACTION,
5306 NULL, "encap is not supported"
5307 " for ingress traffic");
5313 * Find existing modify-header resource or create and register a new one.
5315 * @param dev[in, out]
5316 * Pointer to rte_eth_dev structure.
5317 * @param[in, out] resource
5318 * Pointer to modify-header resource.
5319 * @parm[in, out] dev_flow
5320 * Pointer to the dev_flow.
5322 * pointer to error structure.
5325 * 0 on success otherwise -errno and errno is set.
5328 flow_dv_modify_hdr_resource_register
5329 (struct rte_eth_dev *dev,
5330 struct mlx5_flow_dv_modify_hdr_resource *resource,
5331 struct mlx5_flow *dev_flow,
5332 struct rte_flow_error *error)
5334 struct mlx5_priv *priv = dev->data->dev_private;
5335 struct mlx5_dev_ctx_shared *sh = priv->sh;
5336 uint32_t key_len = sizeof(*resource) -
5337 offsetof(typeof(*resource), ft_type) +
5338 resource->actions_num * sizeof(resource->actions[0]);
5339 struct mlx5_hlist_entry *entry;
5340 struct mlx5_flow_cb_ctx ctx = {
5346 resource->flags = dev_flow->dv.group ? 0 :
5347 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5348 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5350 return rte_flow_error_set(error, EOVERFLOW,
5351 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5352 "too many modify header items");
5353 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5354 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5357 resource = container_of(entry, typeof(*resource), entry);
5358 dev_flow->handle->dvh.modify_hdr = resource;
5363 * Get DV flow counter by index.
5366 * Pointer to the Ethernet device structure.
5368 * mlx5 flow counter index in the container.
5370 * mlx5 flow counter pool in the container,
5373 * Pointer to the counter, NULL otherwise.
5375 static struct mlx5_flow_counter *
5376 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5378 struct mlx5_flow_counter_pool **ppool)
5380 struct mlx5_priv *priv = dev->data->dev_private;
5381 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5382 struct mlx5_flow_counter_pool *pool;
5384 /* Decrease to original index and clear shared bit. */
5385 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5386 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5387 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5391 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5395 * Check the devx counter belongs to the pool.
5398 * Pointer to the counter pool.
5400 * The counter devx ID.
5403 * True if counter belongs to the pool, false otherwise.
5406 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5408 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5409 MLX5_COUNTERS_PER_POOL;
5411 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5417 * Get a pool by devx counter ID.
5420 * Pointer to the counter management.
5422 * The counter devx ID.
5425 * The counter pool pointer if exists, NULL otherwise,
5427 static struct mlx5_flow_counter_pool *
5428 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5431 struct mlx5_flow_counter_pool *pool = NULL;
5433 rte_spinlock_lock(&cmng->pool_update_sl);
5434 /* Check last used pool. */
5435 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5436 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5437 pool = cmng->pools[cmng->last_pool_idx];
5440 /* ID out of range means no suitable pool in the container. */
5441 if (id > cmng->max_id || id < cmng->min_id)
5444 * Find the pool from the end of the container, since mostly counter
5445 * ID is sequence increasing, and the last pool should be the needed
5450 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5452 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5458 rte_spinlock_unlock(&cmng->pool_update_sl);
5463 * Resize a counter container.
5466 * Pointer to the Ethernet device structure.
5469 * 0 on success, otherwise negative errno value and rte_errno is set.
5472 flow_dv_container_resize(struct rte_eth_dev *dev)
5474 struct mlx5_priv *priv = dev->data->dev_private;
5475 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5476 void *old_pools = cmng->pools;
5477 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5478 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5479 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5486 memcpy(pools, old_pools, cmng->n *
5487 sizeof(struct mlx5_flow_counter_pool *));
5489 cmng->pools = pools;
5491 mlx5_free(old_pools);
5496 * Query a devx flow counter.
5499 * Pointer to the Ethernet device structure.
5501 * Index to the flow counter.
5503 * The statistics value of packets.
5505 * The statistics value of bytes.
5508 * 0 on success, otherwise a negative errno value and rte_errno is set.
5511 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5514 struct mlx5_priv *priv = dev->data->dev_private;
5515 struct mlx5_flow_counter_pool *pool = NULL;
5516 struct mlx5_flow_counter *cnt;
5519 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5521 if (priv->sh->cmng.counter_fallback)
5522 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5523 0, pkts, bytes, 0, NULL, NULL, 0);
5524 rte_spinlock_lock(&pool->sl);
5529 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5530 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5531 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5533 rte_spinlock_unlock(&pool->sl);
5538 * Create and initialize a new counter pool.
5541 * Pointer to the Ethernet device structure.
5543 * The devX counter handle.
5545 * Whether the pool is for counter that was allocated for aging.
5546 * @param[in/out] cont_cur
5547 * Pointer to the container pointer, it will be update in pool resize.
5550 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5552 static struct mlx5_flow_counter_pool *
5553 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5556 struct mlx5_priv *priv = dev->data->dev_private;
5557 struct mlx5_flow_counter_pool *pool;
5558 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5559 bool fallback = priv->sh->cmng.counter_fallback;
5560 uint32_t size = sizeof(*pool);
5562 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5563 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5564 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5570 pool->is_aged = !!age;
5571 pool->query_gen = 0;
5572 pool->min_dcs = dcs;
5573 rte_spinlock_init(&pool->sl);
5574 rte_spinlock_init(&pool->csl);
5575 TAILQ_INIT(&pool->counters[0]);
5576 TAILQ_INIT(&pool->counters[1]);
5577 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5578 rte_spinlock_lock(&cmng->pool_update_sl);
5579 pool->index = cmng->n_valid;
5580 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5582 rte_spinlock_unlock(&cmng->pool_update_sl);
5585 cmng->pools[pool->index] = pool;
5587 if (unlikely(fallback)) {
5588 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5590 if (base < cmng->min_id)
5591 cmng->min_id = base;
5592 if (base > cmng->max_id)
5593 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5594 cmng->last_pool_idx = pool->index;
5596 rte_spinlock_unlock(&cmng->pool_update_sl);
5601 * Prepare a new counter and/or a new counter pool.
5604 * Pointer to the Ethernet device structure.
5605 * @param[out] cnt_free
5606 * Where to put the pointer of a new counter.
5608 * Whether the pool is for counter that was allocated for aging.
5611 * The counter pool pointer and @p cnt_free is set on success,
5612 * NULL otherwise and rte_errno is set.
5614 static struct mlx5_flow_counter_pool *
5615 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5616 struct mlx5_flow_counter **cnt_free,
5619 struct mlx5_priv *priv = dev->data->dev_private;
5620 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5621 struct mlx5_flow_counter_pool *pool;
5622 struct mlx5_counters tmp_tq;
5623 struct mlx5_devx_obj *dcs = NULL;
5624 struct mlx5_flow_counter *cnt;
5625 enum mlx5_counter_type cnt_type =
5626 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5627 bool fallback = priv->sh->cmng.counter_fallback;
5631 /* bulk_bitmap must be 0 for single counter allocation. */
5632 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5635 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5637 pool = flow_dv_pool_create(dev, dcs, age);
5639 mlx5_devx_cmd_destroy(dcs);
5643 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5644 cnt = MLX5_POOL_GET_CNT(pool, i);
5646 cnt->dcs_when_free = dcs;
5650 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5652 rte_errno = ENODATA;
5655 pool = flow_dv_pool_create(dev, dcs, age);
5657 mlx5_devx_cmd_destroy(dcs);
5660 TAILQ_INIT(&tmp_tq);
5661 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5662 cnt = MLX5_POOL_GET_CNT(pool, i);
5664 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5666 rte_spinlock_lock(&cmng->csl[cnt_type]);
5667 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5668 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5669 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5670 (*cnt_free)->pool = pool;
5675 * Allocate a flow counter.
5678 * Pointer to the Ethernet device structure.
5680 * Whether the counter was allocated for aging.
5683 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5686 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5688 struct mlx5_priv *priv = dev->data->dev_private;
5689 struct mlx5_flow_counter_pool *pool = NULL;
5690 struct mlx5_flow_counter *cnt_free = NULL;
5691 bool fallback = priv->sh->cmng.counter_fallback;
5692 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5693 enum mlx5_counter_type cnt_type =
5694 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5697 if (!priv->config.devx) {
5698 rte_errno = ENOTSUP;
5701 /* Get free counters from container. */
5702 rte_spinlock_lock(&cmng->csl[cnt_type]);
5703 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5705 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5706 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5707 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5709 pool = cnt_free->pool;
5711 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5712 /* Create a DV counter action only in the first time usage. */
5713 if (!cnt_free->action) {
5715 struct mlx5_devx_obj *dcs;
5719 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5720 dcs = pool->min_dcs;
5723 dcs = cnt_free->dcs_when_free;
5725 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5732 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5733 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5734 /* Update the counter reset values. */
5735 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5738 if (!fallback && !priv->sh->cmng.query_thread_on)
5739 /* Start the asynchronous batch query by the host thread. */
5740 mlx5_set_query_alarm(priv->sh);
5744 cnt_free->pool = pool;
5746 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5747 rte_spinlock_lock(&cmng->csl[cnt_type]);
5748 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5749 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5755 * Allocate a shared flow counter.
5758 * Pointer to the shared counter configuration.
5760 * Pointer to save the allocated counter index.
5763 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5767 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5769 struct mlx5_shared_counter_conf *conf = ctx;
5770 struct rte_eth_dev *dev = conf->dev;
5771 struct mlx5_flow_counter *cnt;
5773 data->dword = flow_dv_counter_alloc(dev, 0);
5774 data->dword |= MLX5_CNT_SHARED_OFFSET;
5775 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5776 cnt->shared_info.id = conf->id;
5781 * Get a shared flow counter.
5784 * Pointer to the Ethernet device structure.
5786 * Counter identifier.
5789 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5792 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5794 struct mlx5_priv *priv = dev->data->dev_private;
5795 struct mlx5_shared_counter_conf conf = {
5799 union mlx5_l3t_data data = {
5803 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5804 flow_dv_counter_alloc_shared_cb, &conf);
5809 * Get age param from counter index.
5812 * Pointer to the Ethernet device structure.
5813 * @param[in] counter
5814 * Index to the counter handler.
5817 * The aging parameter specified for the counter index.
5819 static struct mlx5_age_param*
5820 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5823 struct mlx5_flow_counter *cnt;
5824 struct mlx5_flow_counter_pool *pool = NULL;
5826 flow_dv_counter_get_by_idx(dev, counter, &pool);
5827 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5828 cnt = MLX5_POOL_GET_CNT(pool, counter);
5829 return MLX5_CNT_TO_AGE(cnt);
5833 * Remove a flow counter from aged counter list.
5836 * Pointer to the Ethernet device structure.
5837 * @param[in] counter
5838 * Index to the counter handler.
5840 * Pointer to the counter handler.
5843 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5844 uint32_t counter, struct mlx5_flow_counter *cnt)
5846 struct mlx5_age_info *age_info;
5847 struct mlx5_age_param *age_param;
5848 struct mlx5_priv *priv = dev->data->dev_private;
5849 uint16_t expected = AGE_CANDIDATE;
5851 age_info = GET_PORT_AGE_INFO(priv);
5852 age_param = flow_dv_counter_idx_get_age(dev, counter);
5853 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5854 AGE_FREE, false, __ATOMIC_RELAXED,
5855 __ATOMIC_RELAXED)) {
5857 * We need the lock even it is age timeout,
5858 * since counter may still in process.
5860 rte_spinlock_lock(&age_info->aged_sl);
5861 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5862 rte_spinlock_unlock(&age_info->aged_sl);
5863 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5868 * Release a flow counter.
5871 * Pointer to the Ethernet device structure.
5872 * @param[in] counter
5873 * Index to the counter handler.
5876 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5878 struct mlx5_priv *priv = dev->data->dev_private;
5879 struct mlx5_flow_counter_pool *pool = NULL;
5880 struct mlx5_flow_counter *cnt;
5881 enum mlx5_counter_type cnt_type;
5885 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5887 if (IS_SHARED_CNT(counter) &&
5888 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5891 flow_dv_counter_remove_from_age(dev, counter, cnt);
5894 * Put the counter back to list to be updated in none fallback mode.
5895 * Currently, we are using two list alternately, while one is in query,
5896 * add the freed counter to the other list based on the pool query_gen
5897 * value. After query finishes, add counter the list to the global
5898 * container counter list. The list changes while query starts. In
5899 * this case, lock will not be needed as query callback and release
5900 * function both operate with the different list.
5903 if (!priv->sh->cmng.counter_fallback) {
5904 rte_spinlock_lock(&pool->csl);
5905 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5906 rte_spinlock_unlock(&pool->csl);
5908 cnt->dcs_when_free = cnt->dcs_when_active;
5909 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5910 MLX5_COUNTER_TYPE_ORIGIN;
5911 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5912 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5914 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5919 * Verify the @p attributes will be correctly understood by the NIC and store
5920 * them in the @p flow if everything is correct.
5923 * Pointer to dev struct.
5924 * @param[in] attributes
5925 * Pointer to flow attributes
5926 * @param[in] external
5927 * This flow rule is created by request external to PMD.
5929 * Pointer to error structure.
5932 * - 0 on success and non root table.
5933 * - 1 on success and root table.
5934 * - a negative errno value otherwise and rte_errno is set.
5937 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5938 const struct mlx5_flow_tunnel *tunnel,
5939 const struct rte_flow_attr *attributes,
5940 const struct flow_grp_info *grp_info,
5941 struct rte_flow_error *error)
5943 struct mlx5_priv *priv = dev->data->dev_private;
5944 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5947 #ifndef HAVE_MLX5DV_DR
5948 RTE_SET_USED(tunnel);
5949 RTE_SET_USED(grp_info);
5950 if (attributes->group)
5951 return rte_flow_error_set(error, ENOTSUP,
5952 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5954 "groups are not supported");
5958 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5963 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5965 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5966 attributes->priority > lowest_priority)
5967 return rte_flow_error_set(error, ENOTSUP,
5968 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5970 "priority out of range");
5971 if (attributes->transfer) {
5972 if (!priv->config.dv_esw_en)
5973 return rte_flow_error_set
5975 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5976 "E-Switch dr is not supported");
5977 if (!(priv->representor || priv->master))
5978 return rte_flow_error_set
5979 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5980 NULL, "E-Switch configuration can only be"
5981 " done by a master or a representor device");
5982 if (attributes->egress)
5983 return rte_flow_error_set
5985 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5986 "egress is not supported");
5988 if (!(attributes->egress ^ attributes->ingress))
5989 return rte_flow_error_set(error, ENOTSUP,
5990 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5991 "must specify exactly one of "
5992 "ingress or egress");
5997 * Internal validation function. For validating both actions and items.
6000 * Pointer to the rte_eth_dev structure.
6002 * Pointer to the flow attributes.
6004 * Pointer to the list of items.
6005 * @param[in] actions
6006 * Pointer to the list of actions.
6007 * @param[in] external
6008 * This flow rule is created by request external to PMD.
6009 * @param[in] hairpin
6010 * Number of hairpin TX actions, 0 means classic flow.
6012 * Pointer to the error structure.
6015 * 0 on success, a negative errno value otherwise and rte_errno is set.
6018 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6019 const struct rte_flow_item items[],
6020 const struct rte_flow_action actions[],
6021 bool external, int hairpin, struct rte_flow_error *error)
6024 uint64_t action_flags = 0;
6025 uint64_t item_flags = 0;
6026 uint64_t last_item = 0;
6027 uint8_t next_protocol = 0xff;
6028 uint16_t ether_type = 0;
6030 uint8_t item_ipv6_proto = 0;
6031 int fdb_mirror_limit = 0;
6032 int modify_after_mirror = 0;
6033 const struct rte_flow_item *geneve_item = NULL;
6034 const struct rte_flow_item *gre_item = NULL;
6035 const struct rte_flow_item *gtp_item = NULL;
6036 const struct rte_flow_action_raw_decap *decap;
6037 const struct rte_flow_action_raw_encap *encap;
6038 const struct rte_flow_action_rss *rss = NULL;
6039 const struct rte_flow_action_rss *sample_rss = NULL;
6040 const struct rte_flow_action_count *count = NULL;
6041 const struct rte_flow_action_count *sample_count = NULL;
6042 const struct rte_flow_item_tcp nic_tcp_mask = {
6045 .src_port = RTE_BE16(UINT16_MAX),
6046 .dst_port = RTE_BE16(UINT16_MAX),
6049 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6052 "\xff\xff\xff\xff\xff\xff\xff\xff"
6053 "\xff\xff\xff\xff\xff\xff\xff\xff",
6055 "\xff\xff\xff\xff\xff\xff\xff\xff"
6056 "\xff\xff\xff\xff\xff\xff\xff\xff",
6057 .vtc_flow = RTE_BE32(0xffffffff),
6063 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6067 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6071 .dummy[0] = 0xffffffff,
6074 struct mlx5_priv *priv = dev->data->dev_private;
6075 struct mlx5_dev_config *dev_conf = &priv->config;
6076 uint16_t queue_index = 0xFFFF;
6077 const struct rte_flow_item_vlan *vlan_m = NULL;
6078 uint32_t rw_act_num = 0;
6080 const struct mlx5_flow_tunnel *tunnel;
6081 struct flow_grp_info grp_info = {
6082 .external = !!external,
6083 .transfer = !!attr->transfer,
6084 .fdb_def_rule = !!priv->fdb_def_rule,
6086 const struct rte_eth_hairpin_conf *conf;
6090 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6091 tunnel = flow_items_to_tunnel(items);
6092 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6093 MLX5_FLOW_ACTION_DECAP;
6094 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6095 tunnel = flow_actions_to_tunnel(actions);
6096 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6100 if (tunnel && priv->representor)
6101 return rte_flow_error_set(error, ENOTSUP,
6102 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6103 "decap not supported "
6104 "for VF representor");
6105 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6106 (dev, tunnel, attr, items, actions);
6107 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6110 is_root = (uint64_t)ret;
6111 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6112 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6113 int type = items->type;
6115 if (!mlx5_flow_os_item_supported(type))
6116 return rte_flow_error_set(error, ENOTSUP,
6117 RTE_FLOW_ERROR_TYPE_ITEM,
6118 NULL, "item not supported");
6120 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6121 if (items[0].type != (typeof(items[0].type))
6122 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6123 return rte_flow_error_set
6125 RTE_FLOW_ERROR_TYPE_ITEM,
6126 NULL, "MLX5 private items "
6127 "must be the first");
6129 case RTE_FLOW_ITEM_TYPE_VOID:
6131 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6132 ret = flow_dv_validate_item_port_id
6133 (dev, items, attr, item_flags, error);
6136 last_item = MLX5_FLOW_ITEM_PORT_ID;
6138 case RTE_FLOW_ITEM_TYPE_ETH:
6139 ret = mlx5_flow_validate_item_eth(items, item_flags,
6143 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6144 MLX5_FLOW_LAYER_OUTER_L2;
6145 if (items->mask != NULL && items->spec != NULL) {
6147 ((const struct rte_flow_item_eth *)
6150 ((const struct rte_flow_item_eth *)
6152 ether_type = rte_be_to_cpu_16(ether_type);
6157 case RTE_FLOW_ITEM_TYPE_VLAN:
6158 ret = flow_dv_validate_item_vlan(items, item_flags,
6162 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6163 MLX5_FLOW_LAYER_OUTER_VLAN;
6164 if (items->mask != NULL && items->spec != NULL) {
6166 ((const struct rte_flow_item_vlan *)
6167 items->spec)->inner_type;
6169 ((const struct rte_flow_item_vlan *)
6170 items->mask)->inner_type;
6171 ether_type = rte_be_to_cpu_16(ether_type);
6175 /* Store outer VLAN mask for of_push_vlan action. */
6177 vlan_m = items->mask;
6179 case RTE_FLOW_ITEM_TYPE_IPV4:
6180 mlx5_flow_tunnel_ip_check(items, next_protocol,
6181 &item_flags, &tunnel);
6182 ret = flow_dv_validate_item_ipv4(items, item_flags,
6183 last_item, ether_type,
6187 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6188 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6189 if (items->mask != NULL &&
6190 ((const struct rte_flow_item_ipv4 *)
6191 items->mask)->hdr.next_proto_id) {
6193 ((const struct rte_flow_item_ipv4 *)
6194 (items->spec))->hdr.next_proto_id;
6196 ((const struct rte_flow_item_ipv4 *)
6197 (items->mask))->hdr.next_proto_id;
6199 /* Reset for inner layer. */
6200 next_protocol = 0xff;
6203 case RTE_FLOW_ITEM_TYPE_IPV6:
6204 mlx5_flow_tunnel_ip_check(items, next_protocol,
6205 &item_flags, &tunnel);
6206 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6213 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6214 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6215 if (items->mask != NULL &&
6216 ((const struct rte_flow_item_ipv6 *)
6217 items->mask)->hdr.proto) {
6219 ((const struct rte_flow_item_ipv6 *)
6220 items->spec)->hdr.proto;
6222 ((const struct rte_flow_item_ipv6 *)
6223 items->spec)->hdr.proto;
6225 ((const struct rte_flow_item_ipv6 *)
6226 items->mask)->hdr.proto;
6228 /* Reset for inner layer. */
6229 next_protocol = 0xff;
6232 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6233 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6238 last_item = tunnel ?
6239 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6240 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6241 if (items->mask != NULL &&
6242 ((const struct rte_flow_item_ipv6_frag_ext *)
6243 items->mask)->hdr.next_header) {
6245 ((const struct rte_flow_item_ipv6_frag_ext *)
6246 items->spec)->hdr.next_header;
6248 ((const struct rte_flow_item_ipv6_frag_ext *)
6249 items->mask)->hdr.next_header;
6251 /* Reset for inner layer. */
6252 next_protocol = 0xff;
6255 case RTE_FLOW_ITEM_TYPE_TCP:
6256 ret = mlx5_flow_validate_item_tcp
6263 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6264 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6266 case RTE_FLOW_ITEM_TYPE_UDP:
6267 ret = mlx5_flow_validate_item_udp(items, item_flags,
6272 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6273 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6275 case RTE_FLOW_ITEM_TYPE_GRE:
6276 ret = mlx5_flow_validate_item_gre(items, item_flags,
6277 next_protocol, error);
6281 last_item = MLX5_FLOW_LAYER_GRE;
6283 case RTE_FLOW_ITEM_TYPE_NVGRE:
6284 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6289 last_item = MLX5_FLOW_LAYER_NVGRE;
6291 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6292 ret = mlx5_flow_validate_item_gre_key
6293 (items, item_flags, gre_item, error);
6296 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6298 case RTE_FLOW_ITEM_TYPE_VXLAN:
6299 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6303 last_item = MLX5_FLOW_LAYER_VXLAN;
6305 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6306 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6311 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6313 case RTE_FLOW_ITEM_TYPE_GENEVE:
6314 ret = mlx5_flow_validate_item_geneve(items,
6319 geneve_item = items;
6320 last_item = MLX5_FLOW_LAYER_GENEVE;
6322 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6323 ret = mlx5_flow_validate_item_geneve_opt(items,
6330 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6332 case RTE_FLOW_ITEM_TYPE_MPLS:
6333 ret = mlx5_flow_validate_item_mpls(dev, items,
6338 last_item = MLX5_FLOW_LAYER_MPLS;
6341 case RTE_FLOW_ITEM_TYPE_MARK:
6342 ret = flow_dv_validate_item_mark(dev, items, attr,
6346 last_item = MLX5_FLOW_ITEM_MARK;
6348 case RTE_FLOW_ITEM_TYPE_META:
6349 ret = flow_dv_validate_item_meta(dev, items, attr,
6353 last_item = MLX5_FLOW_ITEM_METADATA;
6355 case RTE_FLOW_ITEM_TYPE_ICMP:
6356 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6361 last_item = MLX5_FLOW_LAYER_ICMP;
6363 case RTE_FLOW_ITEM_TYPE_ICMP6:
6364 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6369 item_ipv6_proto = IPPROTO_ICMPV6;
6370 last_item = MLX5_FLOW_LAYER_ICMP6;
6372 case RTE_FLOW_ITEM_TYPE_TAG:
6373 ret = flow_dv_validate_item_tag(dev, items,
6377 last_item = MLX5_FLOW_ITEM_TAG;
6379 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6380 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6382 case RTE_FLOW_ITEM_TYPE_GTP:
6383 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6388 last_item = MLX5_FLOW_LAYER_GTP;
6390 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6391 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6396 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6398 case RTE_FLOW_ITEM_TYPE_ECPRI:
6399 /* Capacity will be checked in the translate stage. */
6400 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6407 last_item = MLX5_FLOW_LAYER_ECPRI;
6410 return rte_flow_error_set(error, ENOTSUP,
6411 RTE_FLOW_ERROR_TYPE_ITEM,
6412 NULL, "item not supported");
6414 item_flags |= last_item;
6416 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6417 int type = actions->type;
6419 if (!mlx5_flow_os_action_supported(type))
6420 return rte_flow_error_set(error, ENOTSUP,
6421 RTE_FLOW_ERROR_TYPE_ACTION,
6423 "action not supported");
6424 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6425 return rte_flow_error_set(error, ENOTSUP,
6426 RTE_FLOW_ERROR_TYPE_ACTION,
6427 actions, "too many actions");
6429 case RTE_FLOW_ACTION_TYPE_VOID:
6431 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6432 ret = flow_dv_validate_action_port_id(dev,
6439 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6442 case RTE_FLOW_ACTION_TYPE_FLAG:
6443 ret = flow_dv_validate_action_flag(dev, action_flags,
6447 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6448 /* Count all modify-header actions as one. */
6449 if (!(action_flags &
6450 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6452 action_flags |= MLX5_FLOW_ACTION_FLAG |
6453 MLX5_FLOW_ACTION_MARK_EXT;
6454 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6455 modify_after_mirror = 1;
6458 action_flags |= MLX5_FLOW_ACTION_FLAG;
6461 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6463 case RTE_FLOW_ACTION_TYPE_MARK:
6464 ret = flow_dv_validate_action_mark(dev, actions,
6469 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6470 /* Count all modify-header actions as one. */
6471 if (!(action_flags &
6472 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6474 action_flags |= MLX5_FLOW_ACTION_MARK |
6475 MLX5_FLOW_ACTION_MARK_EXT;
6476 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6477 modify_after_mirror = 1;
6479 action_flags |= MLX5_FLOW_ACTION_MARK;
6482 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6484 case RTE_FLOW_ACTION_TYPE_SET_META:
6485 ret = flow_dv_validate_action_set_meta(dev, actions,
6490 /* Count all modify-header actions as one action. */
6491 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6493 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6494 modify_after_mirror = 1;
6495 action_flags |= MLX5_FLOW_ACTION_SET_META;
6496 rw_act_num += MLX5_ACT_NUM_SET_META;
6498 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6499 ret = flow_dv_validate_action_set_tag(dev, actions,
6504 /* Count all modify-header actions as one action. */
6505 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6507 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6508 modify_after_mirror = 1;
6509 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6510 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6512 case RTE_FLOW_ACTION_TYPE_DROP:
6513 ret = mlx5_flow_validate_action_drop(action_flags,
6517 action_flags |= MLX5_FLOW_ACTION_DROP;
6520 case RTE_FLOW_ACTION_TYPE_QUEUE:
6521 ret = mlx5_flow_validate_action_queue(actions,
6526 queue_index = ((const struct rte_flow_action_queue *)
6527 (actions->conf))->index;
6528 action_flags |= MLX5_FLOW_ACTION_QUEUE;
6531 case RTE_FLOW_ACTION_TYPE_RSS:
6532 rss = actions->conf;
6533 ret = mlx5_flow_validate_action_rss(actions,
6539 if (rss && sample_rss &&
6540 (sample_rss->level != rss->level ||
6541 sample_rss->types != rss->types))
6542 return rte_flow_error_set(error, ENOTSUP,
6543 RTE_FLOW_ERROR_TYPE_ACTION,
6545 "Can't use the different RSS types "
6546 "or level in the same flow");
6547 if (rss != NULL && rss->queue_num)
6548 queue_index = rss->queue[0];
6549 action_flags |= MLX5_FLOW_ACTION_RSS;
6552 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6554 mlx5_flow_validate_action_default_miss(action_flags,
6558 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6561 case RTE_FLOW_ACTION_TYPE_COUNT:
6562 ret = flow_dv_validate_action_count(dev, actions,
6567 count = actions->conf;
6568 action_flags |= MLX5_FLOW_ACTION_COUNT;
6571 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6572 if (flow_dv_validate_action_pop_vlan(dev,
6578 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6581 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6582 ret = flow_dv_validate_action_push_vlan(dev,
6589 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6592 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6593 ret = flow_dv_validate_action_set_vlan_pcp
6594 (action_flags, actions, error);
6597 /* Count PCP with push_vlan command. */
6598 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6600 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6601 ret = flow_dv_validate_action_set_vlan_vid
6602 (item_flags, action_flags,
6606 /* Count VID with push_vlan command. */
6607 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6608 rw_act_num += MLX5_ACT_NUM_MDF_VID;
6610 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6611 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6612 ret = flow_dv_validate_action_l2_encap(dev,
6618 action_flags |= MLX5_FLOW_ACTION_ENCAP;
6621 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6622 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6623 ret = flow_dv_validate_action_decap(dev, action_flags,
6624 actions, item_flags,
6628 action_flags |= MLX5_FLOW_ACTION_DECAP;
6631 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6632 ret = flow_dv_validate_action_raw_encap_decap
6633 (dev, NULL, actions->conf, attr, &action_flags,
6634 &actions_n, actions, item_flags, error);
6638 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6639 decap = actions->conf;
6640 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6642 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6646 encap = actions->conf;
6648 ret = flow_dv_validate_action_raw_encap_decap
6650 decap ? decap : &empty_decap, encap,
6651 attr, &action_flags, &actions_n,
6652 actions, item_flags, error);
6656 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6657 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6658 ret = flow_dv_validate_action_modify_mac(action_flags,
6664 /* Count all modify-header actions as one action. */
6665 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6667 action_flags |= actions->type ==
6668 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6669 MLX5_FLOW_ACTION_SET_MAC_SRC :
6670 MLX5_FLOW_ACTION_SET_MAC_DST;
6671 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6672 modify_after_mirror = 1;
6674 * Even if the source and destination MAC addresses have
6675 * overlap in the header with 4B alignment, the convert
6676 * function will handle them separately and 4 SW actions
6677 * will be created. And 2 actions will be added each
6678 * time no matter how many bytes of address will be set.
6680 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6682 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6683 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6684 ret = flow_dv_validate_action_modify_ipv4(action_flags,
6690 /* Count all modify-header actions as one action. */
6691 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6693 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6694 modify_after_mirror = 1;
6695 action_flags |= actions->type ==
6696 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6697 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6698 MLX5_FLOW_ACTION_SET_IPV4_DST;
6699 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6701 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6702 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6703 ret = flow_dv_validate_action_modify_ipv6(action_flags,
6709 if (item_ipv6_proto == IPPROTO_ICMPV6)
6710 return rte_flow_error_set(error, ENOTSUP,
6711 RTE_FLOW_ERROR_TYPE_ACTION,
6713 "Can't change header "
6714 "with ICMPv6 proto");
6715 /* Count all modify-header actions as one action. */
6716 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6718 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6719 modify_after_mirror = 1;
6720 action_flags |= actions->type ==
6721 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6722 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6723 MLX5_FLOW_ACTION_SET_IPV6_DST;
6724 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6726 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6727 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6728 ret = flow_dv_validate_action_modify_tp(action_flags,
6734 /* Count all modify-header actions as one action. */
6735 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6737 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6738 modify_after_mirror = 1;
6739 action_flags |= actions->type ==
6740 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6741 MLX5_FLOW_ACTION_SET_TP_SRC :
6742 MLX5_FLOW_ACTION_SET_TP_DST;
6743 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6745 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6746 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6747 ret = flow_dv_validate_action_modify_ttl(action_flags,
6753 /* Count all modify-header actions as one action. */
6754 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6756 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6757 modify_after_mirror = 1;
6758 action_flags |= actions->type ==
6759 RTE_FLOW_ACTION_TYPE_SET_TTL ?
6760 MLX5_FLOW_ACTION_SET_TTL :
6761 MLX5_FLOW_ACTION_DEC_TTL;
6762 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6764 case RTE_FLOW_ACTION_TYPE_JUMP:
6765 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6771 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6773 return rte_flow_error_set(error, EINVAL,
6774 RTE_FLOW_ERROR_TYPE_ACTION,
6776 "sample and jump action combination is not supported");
6778 action_flags |= MLX5_FLOW_ACTION_JUMP;
6780 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6781 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6782 ret = flow_dv_validate_action_modify_tcp_seq
6789 /* Count all modify-header actions as one action. */
6790 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6792 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6793 modify_after_mirror = 1;
6794 action_flags |= actions->type ==
6795 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6796 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6797 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6798 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6800 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6801 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6802 ret = flow_dv_validate_action_modify_tcp_ack
6809 /* Count all modify-header actions as one action. */
6810 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6812 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6813 modify_after_mirror = 1;
6814 action_flags |= actions->type ==
6815 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6816 MLX5_FLOW_ACTION_INC_TCP_ACK :
6817 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6818 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6820 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6822 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6823 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6824 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6826 case RTE_FLOW_ACTION_TYPE_METER:
6827 ret = mlx5_flow_validate_action_meter(dev,
6833 action_flags |= MLX5_FLOW_ACTION_METER;
6835 /* Meter action will add one more TAG action. */
6836 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6838 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6839 if (!attr->transfer && !attr->group)
6840 return rte_flow_error_set(error, ENOTSUP,
6841 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6843 "Shared ASO age action is not supported for group 0");
6844 action_flags |= MLX5_FLOW_ACTION_AGE;
6847 case RTE_FLOW_ACTION_TYPE_AGE:
6848 ret = flow_dv_validate_action_age(action_flags,
6854 * Validate the regular AGE action (using counter)
6855 * mutual exclusion with share counter actions.
6857 if (!priv->sh->flow_hit_aso_en) {
6858 if (count && count->shared)
6859 return rte_flow_error_set
6861 RTE_FLOW_ERROR_TYPE_ACTION,
6863 "old age and shared count combination is not supported");
6865 return rte_flow_error_set
6867 RTE_FLOW_ERROR_TYPE_ACTION,
6869 "old age action and count must be in the same sub flow");
6871 action_flags |= MLX5_FLOW_ACTION_AGE;
6874 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6875 ret = flow_dv_validate_action_modify_ipv4_dscp
6882 /* Count all modify-header actions as one action. */
6883 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6885 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6886 modify_after_mirror = 1;
6887 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6888 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6890 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6891 ret = flow_dv_validate_action_modify_ipv6_dscp
6898 /* Count all modify-header actions as one action. */
6899 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6901 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6902 modify_after_mirror = 1;
6903 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6904 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6906 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6907 ret = flow_dv_validate_action_sample(&action_flags,
6916 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6919 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6920 if (actions[0].type != (typeof(actions[0].type))
6921 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6922 return rte_flow_error_set
6924 RTE_FLOW_ERROR_TYPE_ACTION,
6925 NULL, "MLX5 private action "
6926 "must be the first");
6928 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6930 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6931 ret = flow_dv_validate_action_modify_field(dev,
6938 /* Count all modify-header actions as one action. */
6939 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6941 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6945 return rte_flow_error_set(error, ENOTSUP,
6946 RTE_FLOW_ERROR_TYPE_ACTION,
6948 "action not supported");
6952 * Validate actions in flow rules
6953 * - Explicit decap action is prohibited by the tunnel offload API.
6954 * - Drop action in tunnel steer rule is prohibited by the API.
6955 * - Application cannot use MARK action because it's value can mask
6956 * tunnel default miss nitification.
6957 * - JUMP in tunnel match rule has no support in current PMD
6959 * - TAG & META are reserved for future uses.
6961 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6962 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
6963 MLX5_FLOW_ACTION_MARK |
6964 MLX5_FLOW_ACTION_SET_TAG |
6965 MLX5_FLOW_ACTION_SET_META |
6966 MLX5_FLOW_ACTION_DROP;
6968 if (action_flags & bad_actions_mask)
6969 return rte_flow_error_set
6971 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6972 "Invalid RTE action in tunnel "
6974 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6975 return rte_flow_error_set
6977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6978 "tunnel set decap rule must terminate "
6981 return rte_flow_error_set
6983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6984 "tunnel flows for ingress traffic only");
6986 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6987 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
6988 MLX5_FLOW_ACTION_MARK |
6989 MLX5_FLOW_ACTION_SET_TAG |
6990 MLX5_FLOW_ACTION_SET_META;
6992 if (action_flags & bad_actions_mask)
6993 return rte_flow_error_set
6995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6996 "Invalid RTE action in tunnel "
7000 * Validate the drop action mutual exclusion with other actions.
7001 * Drop action is mutually-exclusive with any other action, except for
7003 * Drop action compatibility with tunnel offload was already validated.
7005 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7006 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7007 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7008 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7009 return rte_flow_error_set(error, EINVAL,
7010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7011 "Drop action is mutually-exclusive "
7012 "with any other action, except for "
7014 /* Eswitch has few restrictions on using items and actions */
7015 if (attr->transfer) {
7016 if (!mlx5_flow_ext_mreg_supported(dev) &&
7017 action_flags & MLX5_FLOW_ACTION_FLAG)
7018 return rte_flow_error_set(error, ENOTSUP,
7019 RTE_FLOW_ERROR_TYPE_ACTION,
7021 "unsupported action FLAG");
7022 if (!mlx5_flow_ext_mreg_supported(dev) &&
7023 action_flags & MLX5_FLOW_ACTION_MARK)
7024 return rte_flow_error_set(error, ENOTSUP,
7025 RTE_FLOW_ERROR_TYPE_ACTION,
7027 "unsupported action MARK");
7028 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7029 return rte_flow_error_set(error, ENOTSUP,
7030 RTE_FLOW_ERROR_TYPE_ACTION,
7032 "unsupported action QUEUE");
7033 if (action_flags & MLX5_FLOW_ACTION_RSS)
7034 return rte_flow_error_set(error, ENOTSUP,
7035 RTE_FLOW_ERROR_TYPE_ACTION,
7037 "unsupported action RSS");
7038 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7039 return rte_flow_error_set(error, EINVAL,
7040 RTE_FLOW_ERROR_TYPE_ACTION,
7042 "no fate action is found");
7044 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7045 return rte_flow_error_set(error, EINVAL,
7046 RTE_FLOW_ERROR_TYPE_ACTION,
7048 "no fate action is found");
7051 * Continue validation for Xcap and VLAN actions.
7052 * If hairpin is working in explicit TX rule mode, there is no actions
7053 * splitting and the validation of hairpin ingress flow should be the
7054 * same as other standard flows.
7056 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7057 MLX5_FLOW_VLAN_ACTIONS)) &&
7058 (queue_index == 0xFFFF ||
7059 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7060 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7061 conf->tx_explicit != 0))) {
7062 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7063 MLX5_FLOW_XCAP_ACTIONS)
7064 return rte_flow_error_set(error, ENOTSUP,
7065 RTE_FLOW_ERROR_TYPE_ACTION,
7066 NULL, "encap and decap "
7067 "combination aren't supported");
7068 if (!attr->transfer && attr->ingress) {
7069 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7070 return rte_flow_error_set
7072 RTE_FLOW_ERROR_TYPE_ACTION,
7073 NULL, "encap is not supported"
7074 " for ingress traffic");
7075 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7076 return rte_flow_error_set
7078 RTE_FLOW_ERROR_TYPE_ACTION,
7079 NULL, "push VLAN action not "
7080 "supported for ingress");
7081 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7082 MLX5_FLOW_VLAN_ACTIONS)
7083 return rte_flow_error_set
7085 RTE_FLOW_ERROR_TYPE_ACTION,
7086 NULL, "no support for "
7087 "multiple VLAN actions");
7091 * Hairpin flow will add one more TAG action in TX implicit mode.
7092 * In TX explicit mode, there will be no hairpin flow ID.
7095 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7096 /* extra metadata enabled: one more TAG action will be add. */
7097 if (dev_conf->dv_flow_en &&
7098 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7099 mlx5_flow_ext_mreg_supported(dev))
7100 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7102 flow_dv_modify_hdr_action_max(dev, is_root)) {
7103 return rte_flow_error_set(error, ENOTSUP,
7104 RTE_FLOW_ERROR_TYPE_ACTION,
7105 NULL, "too many header modify"
7106 " actions to support");
7108 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7109 if (fdb_mirror_limit && modify_after_mirror)
7110 return rte_flow_error_set(error, EINVAL,
7111 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7112 "sample before modify action is not supported");
7117 * Internal preparation function. Allocates the DV flow size,
7118 * this size is constant.
7121 * Pointer to the rte_eth_dev structure.
7123 * Pointer to the flow attributes.
7125 * Pointer to the list of items.
7126 * @param[in] actions
7127 * Pointer to the list of actions.
7129 * Pointer to the error structure.
7132 * Pointer to mlx5_flow object on success,
7133 * otherwise NULL and rte_errno is set.
7135 static struct mlx5_flow *
7136 flow_dv_prepare(struct rte_eth_dev *dev,
7137 const struct rte_flow_attr *attr __rte_unused,
7138 const struct rte_flow_item items[] __rte_unused,
7139 const struct rte_flow_action actions[] __rte_unused,
7140 struct rte_flow_error *error)
7142 uint32_t handle_idx = 0;
7143 struct mlx5_flow *dev_flow;
7144 struct mlx5_flow_handle *dev_handle;
7145 struct mlx5_priv *priv = dev->data->dev_private;
7146 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7149 /* In case of corrupting the memory. */
7150 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7151 rte_flow_error_set(error, ENOSPC,
7152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7153 "not free temporary device flow");
7156 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7159 rte_flow_error_set(error, ENOMEM,
7160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7161 "not enough memory to create flow handle");
7164 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7165 dev_flow = &wks->flows[wks->flow_idx++];
7166 memset(dev_flow, 0, sizeof(*dev_flow));
7167 dev_flow->handle = dev_handle;
7168 dev_flow->handle_idx = handle_idx;
7170 * In some old rdma-core releases, before continuing, a check of the
7171 * length of matching parameter will be done at first. It needs to use
7172 * the length without misc4 param. If the flow has misc4 support, then
7173 * the length needs to be adjusted accordingly. Each param member is
7174 * aligned with a 64B boundary naturally.
7176 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7177 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7178 dev_flow->ingress = attr->ingress;
7179 dev_flow->dv.transfer = attr->transfer;
7183 #ifdef RTE_LIBRTE_MLX5_DEBUG
7185 * Sanity check for match mask and value. Similar to check_valid_spec() in
7186 * kernel driver. If unmasked bit is present in value, it returns failure.
7189 * pointer to match mask buffer.
7190 * @param match_value
7191 * pointer to match value buffer.
7194 * 0 if valid, -EINVAL otherwise.
7197 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7199 uint8_t *m = match_mask;
7200 uint8_t *v = match_value;
7203 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7206 "match_value differs from match_criteria"
7207 " %p[%u] != %p[%u]",
7208 match_value, i, match_mask, i);
7217 * Add match of ip_version.
7221 * @param[in] headers_v
7222 * Values header pointer.
7223 * @param[in] headers_m
7224 * Masks header pointer.
7225 * @param[in] ip_version
7226 * The IP version to set.
7229 flow_dv_set_match_ip_version(uint32_t group,
7235 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7237 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7239 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7240 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7241 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7245 * Add Ethernet item to matcher and to the value.
7247 * @param[in, out] matcher
7249 * @param[in, out] key
7250 * Flow matcher value.
7252 * Flow pattern to translate.
7254 * Item is inner pattern.
7257 flow_dv_translate_item_eth(void *matcher, void *key,
7258 const struct rte_flow_item *item, int inner,
7261 const struct rte_flow_item_eth *eth_m = item->mask;
7262 const struct rte_flow_item_eth *eth_v = item->spec;
7263 const struct rte_flow_item_eth nic_mask = {
7264 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7265 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7266 .type = RTE_BE16(0xffff),
7279 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7281 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7283 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7285 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7287 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7288 ð_m->dst, sizeof(eth_m->dst));
7289 /* The value must be in the range of the mask. */
7290 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7291 for (i = 0; i < sizeof(eth_m->dst); ++i)
7292 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7293 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7294 ð_m->src, sizeof(eth_m->src));
7295 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7296 /* The value must be in the range of the mask. */
7297 for (i = 0; i < sizeof(eth_m->dst); ++i)
7298 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7300 * HW supports match on one Ethertype, the Ethertype following the last
7301 * VLAN tag of the packet (see PRM).
7302 * Set match on ethertype only if ETH header is not followed by VLAN.
7303 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7304 * ethertype, and use ip_version field instead.
7305 * eCPRI over Ether layer will use type value 0xAEFE.
7307 if (eth_m->type == 0xFFFF) {
7308 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7309 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7310 switch (eth_v->type) {
7311 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7312 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7314 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7315 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7316 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7318 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7319 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7321 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7322 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7328 if (eth_m->has_vlan) {
7329 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7330 if (eth_v->has_vlan) {
7332 * Here, when also has_more_vlan field in VLAN item is
7333 * not set, only single-tagged packets will be matched.
7335 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7339 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7340 rte_be_to_cpu_16(eth_m->type));
7341 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7342 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7346 * Add VLAN item to matcher and to the value.
7348 * @param[in, out] dev_flow
7350 * @param[in, out] matcher
7352 * @param[in, out] key
7353 * Flow matcher value.
7355 * Flow pattern to translate.
7357 * Item is inner pattern.
7360 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7361 void *matcher, void *key,
7362 const struct rte_flow_item *item,
7363 int inner, uint32_t group)
7365 const struct rte_flow_item_vlan *vlan_m = item->mask;
7366 const struct rte_flow_item_vlan *vlan_v = item->spec;
7373 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7375 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7377 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7379 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7381 * This is workaround, masks are not supported,
7382 * and pre-validated.
7385 dev_flow->handle->vf_vlan.tag =
7386 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7389 * When VLAN item exists in flow, mark packet as tagged,
7390 * even if TCI is not specified.
7392 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7393 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7394 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7399 vlan_m = &rte_flow_item_vlan_mask;
7400 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7401 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7402 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7403 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7404 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7405 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7406 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7407 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7409 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7410 * ethertype, and use ip_version field instead.
7412 if (vlan_m->inner_type == 0xFFFF) {
7413 switch (vlan_v->inner_type) {
7414 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7415 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7416 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7417 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7419 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7420 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7422 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7423 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7429 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7430 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7431 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7432 /* Only one vlan_tag bit can be set. */
7433 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7436 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7437 rte_be_to_cpu_16(vlan_m->inner_type));
7438 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7439 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7443 * Add IPV4 item to matcher and to the value.
7445 * @param[in, out] matcher
7447 * @param[in, out] key
7448 * Flow matcher value.
7450 * Flow pattern to translate.
7452 * Item is inner pattern.
7454 * The group to insert the rule.
7457 flow_dv_translate_item_ipv4(void *matcher, void *key,
7458 const struct rte_flow_item *item,
7459 int inner, uint32_t group)
7461 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7462 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7463 const struct rte_flow_item_ipv4 nic_mask = {
7465 .src_addr = RTE_BE32(0xffffffff),
7466 .dst_addr = RTE_BE32(0xffffffff),
7467 .type_of_service = 0xff,
7468 .next_proto_id = 0xff,
7469 .time_to_live = 0xff,
7479 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7481 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7483 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7485 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7487 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7492 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7493 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7494 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7495 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7496 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7497 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7498 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7499 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7500 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7501 src_ipv4_src_ipv6.ipv4_layout.ipv4);
7502 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7503 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7504 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7505 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7506 ipv4_m->hdr.type_of_service);
7507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7508 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7509 ipv4_m->hdr.type_of_service >> 2);
7510 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7511 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7512 ipv4_m->hdr.next_proto_id);
7513 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7514 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7515 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7516 ipv4_m->hdr.time_to_live);
7517 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7518 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7519 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7520 !!(ipv4_m->hdr.fragment_offset));
7521 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7522 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7526 * Add IPV6 item to matcher and to the value.
7528 * @param[in, out] matcher
7530 * @param[in, out] key
7531 * Flow matcher value.
7533 * Flow pattern to translate.
7535 * Item is inner pattern.
7537 * The group to insert the rule.
7540 flow_dv_translate_item_ipv6(void *matcher, void *key,
7541 const struct rte_flow_item *item,
7542 int inner, uint32_t group)
7544 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7545 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7546 const struct rte_flow_item_ipv6 nic_mask = {
7549 "\xff\xff\xff\xff\xff\xff\xff\xff"
7550 "\xff\xff\xff\xff\xff\xff\xff\xff",
7552 "\xff\xff\xff\xff\xff\xff\xff\xff"
7553 "\xff\xff\xff\xff\xff\xff\xff\xff",
7554 .vtc_flow = RTE_BE32(0xffffffff),
7561 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7562 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7571 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7573 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7575 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7577 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7579 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7584 size = sizeof(ipv6_m->hdr.dst_addr);
7585 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7586 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7587 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7588 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7589 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7590 for (i = 0; i < size; ++i)
7591 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7592 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7593 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7594 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7595 src_ipv4_src_ipv6.ipv6_layout.ipv6);
7596 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7597 for (i = 0; i < size; ++i)
7598 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7600 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7601 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7602 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7603 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7604 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7608 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7610 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7613 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7615 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7619 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7621 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7622 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7625 ipv6_m->hdr.hop_limits);
7626 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7627 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7628 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7629 !!(ipv6_m->has_frag_ext));
7630 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7631 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7635 * Add IPV6 fragment extension item to matcher and to the value.
7637 * @param[in, out] matcher
7639 * @param[in, out] key
7640 * Flow matcher value.
7642 * Flow pattern to translate.
7644 * Item is inner pattern.
7647 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7648 const struct rte_flow_item *item,
7651 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7652 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7653 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7655 .next_header = 0xff,
7656 .frag_data = RTE_BE16(0xffff),
7663 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7665 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7667 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7669 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7671 /* IPv6 fragment extension item exists, so packet is IP fragment. */
7672 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7673 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7674 if (!ipv6_frag_ext_v)
7676 if (!ipv6_frag_ext_m)
7677 ipv6_frag_ext_m = &nic_mask;
7678 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7679 ipv6_frag_ext_m->hdr.next_header);
7680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7681 ipv6_frag_ext_v->hdr.next_header &
7682 ipv6_frag_ext_m->hdr.next_header);
7686 * Add TCP item to matcher and to the value.
7688 * @param[in, out] matcher
7690 * @param[in, out] key
7691 * Flow matcher value.
7693 * Flow pattern to translate.
7695 * Item is inner pattern.
7698 flow_dv_translate_item_tcp(void *matcher, void *key,
7699 const struct rte_flow_item *item,
7702 const struct rte_flow_item_tcp *tcp_m = item->mask;
7703 const struct rte_flow_item_tcp *tcp_v = item->spec;
7708 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7710 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7712 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7714 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7716 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7717 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7721 tcp_m = &rte_flow_item_tcp_mask;
7722 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7723 rte_be_to_cpu_16(tcp_m->hdr.src_port));
7724 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7725 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7727 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7729 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7731 tcp_m->hdr.tcp_flags);
7732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7733 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7737 * Add UDP item to matcher and to the value.
7739 * @param[in, out] matcher
7741 * @param[in, out] key
7742 * Flow matcher value.
7744 * Flow pattern to translate.
7746 * Item is inner pattern.
7749 flow_dv_translate_item_udp(void *matcher, void *key,
7750 const struct rte_flow_item *item,
7753 const struct rte_flow_item_udp *udp_m = item->mask;
7754 const struct rte_flow_item_udp *udp_v = item->spec;
7759 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7761 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7763 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7765 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7767 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7768 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7772 udp_m = &rte_flow_item_udp_mask;
7773 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7774 rte_be_to_cpu_16(udp_m->hdr.src_port));
7775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7776 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7778 rte_be_to_cpu_16(udp_m->hdr.dst_port));
7779 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7780 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7784 * Add GRE optional Key item to matcher and to the value.
7786 * @param[in, out] matcher
7788 * @param[in, out] key
7789 * Flow matcher value.
7791 * Flow pattern to translate.
7793 * Item is inner pattern.
7796 flow_dv_translate_item_gre_key(void *matcher, void *key,
7797 const struct rte_flow_item *item)
7799 const rte_be32_t *key_m = item->mask;
7800 const rte_be32_t *key_v = item->spec;
7801 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7802 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7803 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7805 /* GRE K bit must be on and should already be validated */
7806 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7807 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7811 key_m = &gre_key_default_mask;
7812 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7813 rte_be_to_cpu_32(*key_m) >> 8);
7814 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7815 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7816 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7817 rte_be_to_cpu_32(*key_m) & 0xFF);
7818 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7819 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7823 * Add GRE item to matcher and to the value.
7825 * @param[in, out] matcher
7827 * @param[in, out] key
7828 * Flow matcher value.
7830 * Flow pattern to translate.
7832 * Item is inner pattern.
7835 flow_dv_translate_item_gre(void *matcher, void *key,
7836 const struct rte_flow_item *item,
7839 const struct rte_flow_item_gre *gre_m = item->mask;
7840 const struct rte_flow_item_gre *gre_v = item->spec;
7843 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7844 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7851 uint16_t s_present:1;
7852 uint16_t k_present:1;
7853 uint16_t rsvd_bit1:1;
7854 uint16_t c_present:1;
7858 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7861 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7863 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7865 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7867 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7869 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7874 gre_m = &rte_flow_item_gre_mask;
7875 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7876 rte_be_to_cpu_16(gre_m->protocol));
7877 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7878 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7879 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7880 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7881 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7882 gre_crks_rsvd0_ver_m.c_present);
7883 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7884 gre_crks_rsvd0_ver_v.c_present &
7885 gre_crks_rsvd0_ver_m.c_present);
7886 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7887 gre_crks_rsvd0_ver_m.k_present);
7888 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7889 gre_crks_rsvd0_ver_v.k_present &
7890 gre_crks_rsvd0_ver_m.k_present);
7891 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7892 gre_crks_rsvd0_ver_m.s_present);
7893 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7894 gre_crks_rsvd0_ver_v.s_present &
7895 gre_crks_rsvd0_ver_m.s_present);
7899 * Add NVGRE item to matcher and to the value.
7901 * @param[in, out] matcher
7903 * @param[in, out] key
7904 * Flow matcher value.
7906 * Flow pattern to translate.
7908 * Item is inner pattern.
7911 flow_dv_translate_item_nvgre(void *matcher, void *key,
7912 const struct rte_flow_item *item,
7915 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7916 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7917 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7918 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7919 const char *tni_flow_id_m;
7920 const char *tni_flow_id_v;
7926 /* For NVGRE, GRE header fields must be set with defined values. */
7927 const struct rte_flow_item_gre gre_spec = {
7928 .c_rsvd0_ver = RTE_BE16(0x2000),
7929 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7931 const struct rte_flow_item_gre gre_mask = {
7932 .c_rsvd0_ver = RTE_BE16(0xB000),
7933 .protocol = RTE_BE16(UINT16_MAX),
7935 const struct rte_flow_item gre_item = {
7940 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7944 nvgre_m = &rte_flow_item_nvgre_mask;
7945 tni_flow_id_m = (const char *)nvgre_m->tni;
7946 tni_flow_id_v = (const char *)nvgre_v->tni;
7947 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7948 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7949 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7950 memcpy(gre_key_m, tni_flow_id_m, size);
7951 for (i = 0; i < size; ++i)
7952 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7956 * Add VXLAN item to matcher and to the value.
7958 * @param[in, out] matcher
7960 * @param[in, out] key
7961 * Flow matcher value.
7963 * Flow pattern to translate.
7965 * Item is inner pattern.
7968 flow_dv_translate_item_vxlan(void *matcher, void *key,
7969 const struct rte_flow_item *item,
7972 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7973 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7976 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7977 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7985 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7987 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7989 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7991 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7993 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7994 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7995 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7996 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7997 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8002 vxlan_m = &rte_flow_item_vxlan_mask;
8003 size = sizeof(vxlan_m->vni);
8004 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8005 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8006 memcpy(vni_m, vxlan_m->vni, size);
8007 for (i = 0; i < size; ++i)
8008 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8012 * Add VXLAN-GPE item to matcher and to the value.
8014 * @param[in, out] matcher
8016 * @param[in, out] key
8017 * Flow matcher value.
8019 * Flow pattern to translate.
8021 * Item is inner pattern.
8025 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8026 const struct rte_flow_item *item, int inner)
8028 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8029 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8033 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8035 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8041 uint8_t flags_m = 0xff;
8042 uint8_t flags_v = 0xc;
8045 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8047 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8049 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8051 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8053 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8054 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8055 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8056 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8057 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8062 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8063 size = sizeof(vxlan_m->vni);
8064 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8065 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8066 memcpy(vni_m, vxlan_m->vni, size);
8067 for (i = 0; i < size; ++i)
8068 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8069 if (vxlan_m->flags) {
8070 flags_m = vxlan_m->flags;
8071 flags_v = vxlan_v->flags;
8073 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8074 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8075 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8077 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8082 * Add Geneve item to matcher and to the value.
8084 * @param[in, out] matcher
8086 * @param[in, out] key
8087 * Flow matcher value.
8089 * Flow pattern to translate.
8091 * Item is inner pattern.
8095 flow_dv_translate_item_geneve(void *matcher, void *key,
8096 const struct rte_flow_item *item, int inner)
8098 const struct rte_flow_item_geneve *geneve_m = item->mask;
8099 const struct rte_flow_item_geneve *geneve_v = item->spec;
8102 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8103 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8112 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8114 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8116 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8118 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8120 dport = MLX5_UDP_PORT_GENEVE;
8121 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8122 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8123 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8128 geneve_m = &rte_flow_item_geneve_mask;
8129 size = sizeof(geneve_m->vni);
8130 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8131 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8132 memcpy(vni_m, geneve_m->vni, size);
8133 for (i = 0; i < size; ++i)
8134 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8135 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8136 rte_be_to_cpu_16(geneve_m->protocol));
8137 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8138 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8139 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8140 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8141 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8142 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8143 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8144 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8145 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8146 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8147 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8148 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8149 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8153 * Create Geneve TLV option resource.
8155 * @param dev[in, out]
8156 * Pointer to rte_eth_dev structure.
8157 * @param[in, out] tag_be24
8158 * Tag value in big endian then R-shift 8.
8159 * @parm[in, out] dev_flow
8160 * Pointer to the dev_flow.
8162 * pointer to error structure.
8165 * 0 on success otherwise -errno and errno is set.
8169 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8170 const struct rte_flow_item *item,
8171 struct rte_flow_error *error)
8173 struct mlx5_priv *priv = dev->data->dev_private;
8174 struct mlx5_dev_ctx_shared *sh = priv->sh;
8175 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8176 sh->geneve_tlv_option_resource;
8177 struct mlx5_devx_obj *obj;
8178 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8183 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8184 if (geneve_opt_resource != NULL) {
8185 if (geneve_opt_resource->option_class ==
8186 geneve_opt_v->option_class &&
8187 geneve_opt_resource->option_type ==
8188 geneve_opt_v->option_type &&
8189 geneve_opt_resource->length ==
8190 geneve_opt_v->option_len) {
8191 /* We already have GENVE TLV option obj allocated. */
8192 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8195 ret = rte_flow_error_set(error, ENOMEM,
8196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8197 "Only one GENEVE TLV option supported");
8201 /* Create a GENEVE TLV object and resource. */
8202 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8203 geneve_opt_v->option_class,
8204 geneve_opt_v->option_type,
8205 geneve_opt_v->option_len);
8207 ret = rte_flow_error_set(error, ENODATA,
8208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8209 "Failed to create GENEVE TLV Devx object");
8212 sh->geneve_tlv_option_resource =
8213 mlx5_malloc(MLX5_MEM_ZERO,
8214 sizeof(*geneve_opt_resource),
8216 if (!sh->geneve_tlv_option_resource) {
8217 claim_zero(mlx5_devx_cmd_destroy(obj));
8218 ret = rte_flow_error_set(error, ENOMEM,
8219 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8220 "GENEVE TLV object memory allocation failed");
8223 geneve_opt_resource = sh->geneve_tlv_option_resource;
8224 geneve_opt_resource->obj = obj;
8225 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8226 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8227 geneve_opt_resource->length = geneve_opt_v->option_len;
8228 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8232 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8237 * Add Geneve TLV option item to matcher.
8239 * @param[in, out] dev
8240 * Pointer to rte_eth_dev structure.
8241 * @param[in, out] matcher
8243 * @param[in, out] key
8244 * Flow matcher value.
8246 * Flow pattern to translate.
8248 * Pointer to error structure.
8251 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8252 void *key, const struct rte_flow_item *item,
8253 struct rte_flow_error *error)
8255 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8256 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8257 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8258 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8259 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8261 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8262 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8268 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8269 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8272 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8276 * Set the option length in GENEVE header if not requested.
8277 * The GENEVE TLV option length is expressed by the option length field
8278 * in the GENEVE header.
8279 * If the option length was not requested but the GENEVE TLV option item
8280 * is present we set the option length field implicitly.
8282 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8283 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8284 MLX5_GENEVE_OPTLEN_MASK);
8285 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8286 geneve_opt_v->option_len + 1);
8289 if (geneve_opt_v->data) {
8290 memcpy(&opt_data_key, geneve_opt_v->data,
8291 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8292 sizeof(opt_data_key)));
8293 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8294 sizeof(opt_data_key));
8295 memcpy(&opt_data_mask, geneve_opt_m->data,
8296 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8297 sizeof(opt_data_mask)));
8298 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8299 sizeof(opt_data_mask));
8300 MLX5_SET(fte_match_set_misc3, misc3_m,
8301 geneve_tlv_option_0_data,
8302 rte_be_to_cpu_32(opt_data_mask));
8303 MLX5_SET(fte_match_set_misc3, misc3_v,
8304 geneve_tlv_option_0_data,
8305 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8311 * Add MPLS item to matcher and to the value.
8313 * @param[in, out] matcher
8315 * @param[in, out] key
8316 * Flow matcher value.
8318 * Flow pattern to translate.
8319 * @param[in] prev_layer
8320 * The protocol layer indicated in previous item.
8322 * Item is inner pattern.
8325 flow_dv_translate_item_mpls(void *matcher, void *key,
8326 const struct rte_flow_item *item,
8327 uint64_t prev_layer,
8330 const uint32_t *in_mpls_m = item->mask;
8331 const uint32_t *in_mpls_v = item->spec;
8332 uint32_t *out_mpls_m = 0;
8333 uint32_t *out_mpls_v = 0;
8334 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8335 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8336 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8338 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8339 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8340 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8342 switch (prev_layer) {
8343 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8344 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8346 MLX5_UDP_PORT_MPLS);
8348 case MLX5_FLOW_LAYER_GRE:
8349 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8350 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8351 RTE_ETHER_TYPE_MPLS);
8354 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8362 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8363 switch (prev_layer) {
8364 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8366 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8367 outer_first_mpls_over_udp);
8369 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8370 outer_first_mpls_over_udp);
8372 case MLX5_FLOW_LAYER_GRE:
8374 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8375 outer_first_mpls_over_gre);
8377 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8378 outer_first_mpls_over_gre);
8381 /* Inner MPLS not over GRE is not supported. */
8384 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8388 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8394 if (out_mpls_m && out_mpls_v) {
8395 *out_mpls_m = *in_mpls_m;
8396 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8401 * Add metadata register item to matcher
8403 * @param[in, out] matcher
8405 * @param[in, out] key
8406 * Flow matcher value.
8407 * @param[in] reg_type
8408 * Type of device metadata register
8415 flow_dv_match_meta_reg(void *matcher, void *key,
8416 enum modify_reg reg_type,
8417 uint32_t data, uint32_t mask)
8420 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8422 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8428 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8429 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8432 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8433 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8437 * The metadata register C0 field might be divided into
8438 * source vport index and META item value, we should set
8439 * this field according to specified mask, not as whole one.
8441 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8443 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8444 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8447 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8450 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8451 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8454 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8455 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8458 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8459 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8462 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8463 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8466 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8467 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8470 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8471 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8474 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8475 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8484 * Add MARK item to matcher
8487 * The device to configure through.
8488 * @param[in, out] matcher
8490 * @param[in, out] key
8491 * Flow matcher value.
8493 * Flow pattern to translate.
8496 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8497 void *matcher, void *key,
8498 const struct rte_flow_item *item)
8500 struct mlx5_priv *priv = dev->data->dev_private;
8501 const struct rte_flow_item_mark *mark;
8505 mark = item->mask ? (const void *)item->mask :
8506 &rte_flow_item_mark_mask;
8507 mask = mark->id & priv->sh->dv_mark_mask;
8508 mark = (const void *)item->spec;
8510 value = mark->id & priv->sh->dv_mark_mask & mask;
8512 enum modify_reg reg;
8514 /* Get the metadata register index for the mark. */
8515 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8516 MLX5_ASSERT(reg > 0);
8517 if (reg == REG_C_0) {
8518 struct mlx5_priv *priv = dev->data->dev_private;
8519 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8520 uint32_t shl_c0 = rte_bsf32(msk_c0);
8526 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8531 * Add META item to matcher
8534 * The devich to configure through.
8535 * @param[in, out] matcher
8537 * @param[in, out] key
8538 * Flow matcher value.
8540 * Attributes of flow that includes this item.
8542 * Flow pattern to translate.
8545 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8546 void *matcher, void *key,
8547 const struct rte_flow_attr *attr,
8548 const struct rte_flow_item *item)
8550 const struct rte_flow_item_meta *meta_m;
8551 const struct rte_flow_item_meta *meta_v;
8553 meta_m = (const void *)item->mask;
8555 meta_m = &rte_flow_item_meta_mask;
8556 meta_v = (const void *)item->spec;
8559 uint32_t value = meta_v->data;
8560 uint32_t mask = meta_m->data;
8562 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8565 MLX5_ASSERT(reg != REG_NON);
8567 * In datapath code there is no endianness
8568 * coversions for perfromance reasons, all
8569 * pattern conversions are done in rte_flow.
8571 value = rte_cpu_to_be_32(value);
8572 mask = rte_cpu_to_be_32(mask);
8573 if (reg == REG_C_0) {
8574 struct mlx5_priv *priv = dev->data->dev_private;
8575 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8576 uint32_t shl_c0 = rte_bsf32(msk_c0);
8577 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8578 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8585 MLX5_ASSERT(msk_c0);
8586 MLX5_ASSERT(!(~msk_c0 & mask));
8588 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8593 * Add vport metadata Reg C0 item to matcher
8595 * @param[in, out] matcher
8597 * @param[in, out] key
8598 * Flow matcher value.
8600 * Flow pattern to translate.
8603 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8604 uint32_t value, uint32_t mask)
8606 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8610 * Add tag item to matcher
8613 * The devich to configure through.
8614 * @param[in, out] matcher
8616 * @param[in, out] key
8617 * Flow matcher value.
8619 * Flow pattern to translate.
8622 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8623 void *matcher, void *key,
8624 const struct rte_flow_item *item)
8626 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8627 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8628 uint32_t mask, value;
8631 value = tag_v->data;
8632 mask = tag_m ? tag_m->data : UINT32_MAX;
8633 if (tag_v->id == REG_C_0) {
8634 struct mlx5_priv *priv = dev->data->dev_private;
8635 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8636 uint32_t shl_c0 = rte_bsf32(msk_c0);
8642 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8646 * Add TAG item to matcher
8649 * The devich to configure through.
8650 * @param[in, out] matcher
8652 * @param[in, out] key
8653 * Flow matcher value.
8655 * Flow pattern to translate.
8658 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8659 void *matcher, void *key,
8660 const struct rte_flow_item *item)
8662 const struct rte_flow_item_tag *tag_v = item->spec;
8663 const struct rte_flow_item_tag *tag_m = item->mask;
8664 enum modify_reg reg;
8667 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8668 /* Get the metadata register index for the tag. */
8669 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8670 MLX5_ASSERT(reg > 0);
8671 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8675 * Add source vport match to the specified matcher.
8677 * @param[in, out] matcher
8679 * @param[in, out] key
8680 * Flow matcher value.
8682 * Source vport value to match
8687 flow_dv_translate_item_source_vport(void *matcher, void *key,
8688 int16_t port, uint16_t mask)
8690 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8691 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8693 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8694 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8698 * Translate port-id item to eswitch match on port-id.
8701 * The devich to configure through.
8702 * @param[in, out] matcher
8704 * @param[in, out] key
8705 * Flow matcher value.
8707 * Flow pattern to translate.
8712 * 0 on success, a negative errno value otherwise.
8715 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8716 void *key, const struct rte_flow_item *item,
8717 const struct rte_flow_attr *attr)
8719 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8720 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8721 struct mlx5_priv *priv;
8724 mask = pid_m ? pid_m->id : 0xffff;
8725 id = pid_v ? pid_v->id : dev->data->port_id;
8726 priv = mlx5_port_to_eswitch_info(id, item == NULL);
8730 * Translate to vport field or to metadata, depending on mode.
8731 * Kernel can use either misc.source_port or half of C0 metadata
8734 if (priv->vport_meta_mask) {
8736 * Provide the hint for SW steering library
8737 * to insert the flow into ingress domain and
8738 * save the extra vport match.
8740 if (mask == 0xffff && priv->vport_id == 0xffff &&
8741 priv->pf_bond < 0 && attr->transfer)
8742 flow_dv_translate_item_source_vport
8743 (matcher, key, priv->vport_id, mask);
8745 * We should always set the vport metadata register,
8746 * otherwise the SW steering library can drop
8747 * the rule if wire vport metadata value is not zero,
8748 * it depends on kernel configuration.
8750 flow_dv_translate_item_meta_vport(matcher, key,
8751 priv->vport_meta_tag,
8752 priv->vport_meta_mask);
8754 flow_dv_translate_item_source_vport(matcher, key,
8755 priv->vport_id, mask);
8761 * Add ICMP6 item to matcher and to the value.
8763 * @param[in, out] matcher
8765 * @param[in, out] key
8766 * Flow matcher value.
8768 * Flow pattern to translate.
8770 * Item is inner pattern.
8773 flow_dv_translate_item_icmp6(void *matcher, void *key,
8774 const struct rte_flow_item *item,
8777 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8778 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8781 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8783 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8785 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8787 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8789 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8791 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8793 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8794 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8798 icmp6_m = &rte_flow_item_icmp6_mask;
8799 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8800 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8801 icmp6_v->type & icmp6_m->type);
8802 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8803 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8804 icmp6_v->code & icmp6_m->code);
8808 * Add ICMP item to matcher and to the value.
8810 * @param[in, out] matcher
8812 * @param[in, out] key
8813 * Flow matcher value.
8815 * Flow pattern to translate.
8817 * Item is inner pattern.
8820 flow_dv_translate_item_icmp(void *matcher, void *key,
8821 const struct rte_flow_item *item,
8824 const struct rte_flow_item_icmp *icmp_m = item->mask;
8825 const struct rte_flow_item_icmp *icmp_v = item->spec;
8826 uint32_t icmp_header_data_m = 0;
8827 uint32_t icmp_header_data_v = 0;
8830 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8832 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8834 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8836 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8838 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8840 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8842 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8843 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8847 icmp_m = &rte_flow_item_icmp_mask;
8848 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8849 icmp_m->hdr.icmp_type);
8850 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8851 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8852 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8853 icmp_m->hdr.icmp_code);
8854 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8855 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8856 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8857 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8858 if (icmp_header_data_m) {
8859 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8860 icmp_header_data_v |=
8861 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8862 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8863 icmp_header_data_m);
8864 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8865 icmp_header_data_v & icmp_header_data_m);
8870 * Add GTP item to matcher and to the value.
8872 * @param[in, out] matcher
8874 * @param[in, out] key
8875 * Flow matcher value.
8877 * Flow pattern to translate.
8879 * Item is inner pattern.
8882 flow_dv_translate_item_gtp(void *matcher, void *key,
8883 const struct rte_flow_item *item, int inner)
8885 const struct rte_flow_item_gtp *gtp_m = item->mask;
8886 const struct rte_flow_item_gtp *gtp_v = item->spec;
8889 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8891 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8892 uint16_t dport = RTE_GTPU_UDP_PORT;
8895 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8897 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8899 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8901 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8903 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8904 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8905 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8910 gtp_m = &rte_flow_item_gtp_mask;
8911 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8912 gtp_m->v_pt_rsv_flags);
8913 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8914 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8915 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8916 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8917 gtp_v->msg_type & gtp_m->msg_type);
8918 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8919 rte_be_to_cpu_32(gtp_m->teid));
8920 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8921 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8925 * Add GTP PSC item to matcher.
8927 * @param[in, out] matcher
8929 * @param[in, out] key
8930 * Flow matcher value.
8932 * Flow pattern to translate.
8935 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8936 const struct rte_flow_item *item)
8938 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8939 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8940 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8942 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8948 uint8_t next_ext_header_type;
8953 /* Always set E-flag match on one, regardless of GTP item settings. */
8954 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8955 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8956 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8957 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8958 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8959 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8960 /*Set next extension header type. */
8963 dw_2.next_ext_header_type = 0xff;
8964 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8965 rte_cpu_to_be_32(dw_2.w32));
8968 dw_2.next_ext_header_type = 0x85;
8969 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8970 rte_cpu_to_be_32(dw_2.w32));
8982 /*Set extension header PDU type and Qos. */
8984 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8986 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8987 dw_0.qfi = gtp_psc_m->qfi;
8988 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8989 rte_cpu_to_be_32(dw_0.w32));
8991 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8992 gtp_psc_m->pdu_type);
8993 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8994 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8995 rte_cpu_to_be_32(dw_0.w32));
9001 * Add eCPRI item to matcher and to the value.
9004 * The devich to configure through.
9005 * @param[in, out] matcher
9007 * @param[in, out] key
9008 * Flow matcher value.
9010 * Flow pattern to translate.
9011 * @param[in] samples
9012 * Sample IDs to be used in the matching.
9015 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9016 void *key, const struct rte_flow_item *item)
9018 struct mlx5_priv *priv = dev->data->dev_private;
9019 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9020 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9021 struct rte_ecpri_common_hdr common;
9022 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9024 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9032 ecpri_m = &rte_flow_item_ecpri_mask;
9034 * Maximal four DW samples are supported in a single matching now.
9035 * Two are used now for a eCPRI matching:
9036 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9037 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9040 if (!ecpri_m->hdr.common.u32)
9042 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9043 /* Need to take the whole DW as the mask to fill the entry. */
9044 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9045 prog_sample_field_value_0);
9046 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9047 prog_sample_field_value_0);
9048 /* Already big endian (network order) in the header. */
9049 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9050 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9051 /* Sample#0, used for matching type, offset 0. */
9052 MLX5_SET(fte_match_set_misc4, misc4_m,
9053 prog_sample_field_id_0, samples[0]);
9054 /* It makes no sense to set the sample ID in the mask field. */
9055 MLX5_SET(fte_match_set_misc4, misc4_v,
9056 prog_sample_field_id_0, samples[0]);
9058 * Checking if message body part needs to be matched.
9059 * Some wildcard rules only matching type field should be supported.
9061 if (ecpri_m->hdr.dummy[0]) {
9062 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9063 switch (common.type) {
9064 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9065 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9066 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9067 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9068 prog_sample_field_value_1);
9069 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9070 prog_sample_field_value_1);
9071 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9072 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9073 ecpri_m->hdr.dummy[0];
9074 /* Sample#1, to match message body, offset 4. */
9075 MLX5_SET(fte_match_set_misc4, misc4_m,
9076 prog_sample_field_id_1, samples[1]);
9077 MLX5_SET(fte_match_set_misc4, misc4_v,
9078 prog_sample_field_id_1, samples[1]);
9081 /* Others, do not match any sample ID. */
9087 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9089 #define HEADER_IS_ZERO(match_criteria, headers) \
9090 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9091 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9094 * Calculate flow matcher enable bitmap.
9096 * @param match_criteria
9097 * Pointer to flow matcher criteria.
9100 * Bitmap of enabled fields.
9103 flow_dv_matcher_enable(uint32_t *match_criteria)
9105 uint8_t match_criteria_enable;
9107 match_criteria_enable =
9108 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9109 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9110 match_criteria_enable |=
9111 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9112 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9113 match_criteria_enable |=
9114 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9115 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9116 match_criteria_enable |=
9117 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9118 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9119 match_criteria_enable |=
9120 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9121 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9122 match_criteria_enable |=
9123 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9124 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9125 return match_criteria_enable;
9128 struct mlx5_hlist_entry *
9129 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9131 struct mlx5_dev_ctx_shared *sh = list->ctx;
9132 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9133 struct rte_eth_dev *dev = ctx->dev;
9134 struct mlx5_flow_tbl_data_entry *tbl_data;
9135 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9136 struct rte_flow_error *error = ctx->error;
9137 union mlx5_flow_tbl_key key = { .v64 = key64 };
9138 struct mlx5_flow_tbl_resource *tbl;
9143 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9145 rte_flow_error_set(error, ENOMEM,
9146 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9148 "cannot allocate flow table data entry");
9151 tbl_data->idx = idx;
9152 tbl_data->tunnel = tt_prm->tunnel;
9153 tbl_data->group_id = tt_prm->group_id;
9154 tbl_data->external = !!tt_prm->external;
9155 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9156 tbl_data->is_egress = !!key.direction;
9157 tbl_data->is_transfer = !!key.domain;
9158 tbl_data->dummy = !!key.dummy;
9159 tbl_data->table_id = key.table_id;
9160 tbl = &tbl_data->tbl;
9162 return &tbl_data->entry;
9164 domain = sh->fdb_domain;
9165 else if (key.direction)
9166 domain = sh->tx_domain;
9168 domain = sh->rx_domain;
9169 ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9171 rte_flow_error_set(error, ENOMEM,
9172 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9173 NULL, "cannot create flow table object");
9174 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9178 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9179 (tbl->obj, &tbl_data->jump.action);
9181 rte_flow_error_set(error, ENOMEM,
9182 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9184 "cannot create flow jump action");
9185 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9186 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9190 MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9191 key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9193 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9194 flow_dv_matcher_create_cb,
9195 flow_dv_matcher_match_cb,
9196 flow_dv_matcher_remove_cb);
9197 return &tbl_data->entry;
9201 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9202 struct mlx5_hlist_entry *entry, uint64_t key64,
9203 void *cb_ctx __rte_unused)
9205 struct mlx5_flow_tbl_data_entry *tbl_data =
9206 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9207 union mlx5_flow_tbl_key key = { .v64 = key64 };
9209 return tbl_data->table_id != key.table_id ||
9210 tbl_data->dummy != key.dummy ||
9211 tbl_data->is_transfer != key.domain ||
9212 tbl_data->is_egress != key.direction;
9218 * @param[in, out] dev
9219 * Pointer to rte_eth_dev structure.
9220 * @param[in] table_id
9223 * Direction of the table.
9224 * @param[in] transfer
9225 * E-Switch or NIC flow.
9227 * Dummy entry for dv API.
9229 * pointer to error structure.
9232 * Returns tables resource based on the index, NULL in case of failed.
9234 struct mlx5_flow_tbl_resource *
9235 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9236 uint32_t table_id, uint8_t egress,
9239 const struct mlx5_flow_tunnel *tunnel,
9240 uint32_t group_id, uint8_t dummy,
9241 struct rte_flow_error *error)
9243 struct mlx5_priv *priv = dev->data->dev_private;
9244 union mlx5_flow_tbl_key table_key = {
9246 .table_id = table_id,
9248 .domain = !!transfer,
9249 .direction = !!egress,
9252 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9254 .group_id = group_id,
9255 .external = external,
9257 struct mlx5_flow_cb_ctx ctx = {
9262 struct mlx5_hlist_entry *entry;
9263 struct mlx5_flow_tbl_data_entry *tbl_data;
9265 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9267 rte_flow_error_set(error, ENOMEM,
9268 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9269 "cannot get table");
9272 DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9273 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9274 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9275 return &tbl_data->tbl;
9279 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9280 struct mlx5_hlist_entry *entry)
9282 struct mlx5_dev_ctx_shared *sh = list->ctx;
9283 struct mlx5_flow_tbl_data_entry *tbl_data =
9284 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9286 MLX5_ASSERT(entry && sh);
9287 if (tbl_data->jump.action)
9288 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9289 if (tbl_data->tbl.obj)
9290 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9291 if (tbl_data->tunnel_offload && tbl_data->external) {
9292 struct mlx5_hlist_entry *he;
9293 struct mlx5_hlist *tunnel_grp_hash;
9294 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9295 union tunnel_tbl_key tunnel_key = {
9296 .tunnel_id = tbl_data->tunnel ?
9297 tbl_data->tunnel->tunnel_id : 0,
9298 .group = tbl_data->group_id
9300 uint32_t table_id = tbl_data->table_id;
9302 tunnel_grp_hash = tbl_data->tunnel ?
9303 tbl_data->tunnel->groups :
9305 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9307 mlx5_hlist_unregister(tunnel_grp_hash, he);
9309 "Table_id %u tunnel %u group %u released.",
9312 tbl_data->tunnel->tunnel_id : 0,
9313 tbl_data->group_id);
9315 mlx5_cache_list_destroy(&tbl_data->matchers);
9316 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9320 * Release a flow table.
9323 * Pointer to device shared structure.
9325 * Table resource to be released.
9328 * Returns 0 if table was released, else return 1;
9331 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9332 struct mlx5_flow_tbl_resource *tbl)
9334 struct mlx5_flow_tbl_data_entry *tbl_data =
9335 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9339 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9343 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9344 struct mlx5_cache_entry *entry, void *cb_ctx)
9346 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9347 struct mlx5_flow_dv_matcher *ref = ctx->data;
9348 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9351 return cur->crc != ref->crc ||
9352 cur->priority != ref->priority ||
9353 memcmp((const void *)cur->mask.buf,
9354 (const void *)ref->mask.buf, ref->mask.size);
9357 struct mlx5_cache_entry *
9358 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9359 struct mlx5_cache_entry *entry __rte_unused,
9362 struct mlx5_dev_ctx_shared *sh = list->ctx;
9363 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9364 struct mlx5_flow_dv_matcher *ref = ctx->data;
9365 struct mlx5_flow_dv_matcher *cache;
9366 struct mlx5dv_flow_matcher_attr dv_attr = {
9367 .type = IBV_FLOW_ATTR_NORMAL,
9368 .match_mask = (void *)&ref->mask,
9370 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9374 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9376 rte_flow_error_set(ctx->error, ENOMEM,
9377 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9378 "cannot create matcher");
9382 dv_attr.match_criteria_enable =
9383 flow_dv_matcher_enable(cache->mask.buf);
9384 dv_attr.priority = ref->priority;
9386 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9387 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9388 &cache->matcher_object);
9391 rte_flow_error_set(ctx->error, ENOMEM,
9392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9393 "cannot create matcher");
9396 return &cache->entry;
9400 * Register the flow matcher.
9402 * @param[in, out] dev
9403 * Pointer to rte_eth_dev structure.
9404 * @param[in, out] matcher
9405 * Pointer to flow matcher.
9406 * @param[in, out] key
9407 * Pointer to flow table key.
9408 * @parm[in, out] dev_flow
9409 * Pointer to the dev_flow.
9411 * pointer to error structure.
9414 * 0 on success otherwise -errno and errno is set.
9417 flow_dv_matcher_register(struct rte_eth_dev *dev,
9418 struct mlx5_flow_dv_matcher *ref,
9419 union mlx5_flow_tbl_key *key,
9420 struct mlx5_flow *dev_flow,
9421 const struct mlx5_flow_tunnel *tunnel,
9423 struct rte_flow_error *error)
9425 struct mlx5_cache_entry *entry;
9426 struct mlx5_flow_dv_matcher *cache;
9427 struct mlx5_flow_tbl_resource *tbl;
9428 struct mlx5_flow_tbl_data_entry *tbl_data;
9429 struct mlx5_flow_cb_ctx ctx = {
9435 * tunnel offload API requires this registration for cases when
9436 * tunnel match rule was inserted before tunnel set rule.
9438 tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9439 key->direction, key->domain,
9440 dev_flow->external, tunnel,
9441 group_id, 0, error);
9443 return -rte_errno; /* No need to refill the error info */
9444 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9446 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9448 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9449 return rte_flow_error_set(error, ENOMEM,
9450 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9451 "cannot allocate ref memory");
9453 cache = container_of(entry, typeof(*cache), entry);
9454 dev_flow->handle->dvh.matcher = cache;
9458 struct mlx5_hlist_entry *
9459 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9461 struct mlx5_dev_ctx_shared *sh = list->ctx;
9462 struct rte_flow_error *error = ctx;
9463 struct mlx5_flow_dv_tag_resource *entry;
9467 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9469 rte_flow_error_set(error, ENOMEM,
9470 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9471 "cannot allocate resource memory");
9475 entry->tag_id = key;
9476 ret = mlx5_flow_os_create_flow_action_tag(key,
9479 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9480 rte_flow_error_set(error, ENOMEM,
9481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9482 NULL, "cannot create action");
9485 return &entry->entry;
9489 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9490 struct mlx5_hlist_entry *entry, uint64_t key,
9491 void *cb_ctx __rte_unused)
9493 struct mlx5_flow_dv_tag_resource *tag =
9494 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9496 return key != tag->tag_id;
9500 * Find existing tag resource or create and register a new one.
9502 * @param dev[in, out]
9503 * Pointer to rte_eth_dev structure.
9504 * @param[in, out] tag_be24
9505 * Tag value in big endian then R-shift 8.
9506 * @parm[in, out] dev_flow
9507 * Pointer to the dev_flow.
9509 * pointer to error structure.
9512 * 0 on success otherwise -errno and errno is set.
9515 flow_dv_tag_resource_register
9516 (struct rte_eth_dev *dev,
9518 struct mlx5_flow *dev_flow,
9519 struct rte_flow_error *error)
9521 struct mlx5_priv *priv = dev->data->dev_private;
9522 struct mlx5_flow_dv_tag_resource *cache_resource;
9523 struct mlx5_hlist_entry *entry;
9525 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9527 cache_resource = container_of
9528 (entry, struct mlx5_flow_dv_tag_resource, entry);
9529 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9530 dev_flow->dv.tag_resource = cache_resource;
9537 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9538 struct mlx5_hlist_entry *entry)
9540 struct mlx5_dev_ctx_shared *sh = list->ctx;
9541 struct mlx5_flow_dv_tag_resource *tag =
9542 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9544 MLX5_ASSERT(tag && sh && tag->action);
9545 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9546 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9547 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9554 * Pointer to Ethernet device.
9559 * 1 while a reference on it exists, 0 when freed.
9562 flow_dv_tag_release(struct rte_eth_dev *dev,
9565 struct mlx5_priv *priv = dev->data->dev_private;
9566 struct mlx5_flow_dv_tag_resource *tag;
9568 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9571 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9572 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9573 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9577 * Translate port ID action to vport.
9580 * Pointer to rte_eth_dev structure.
9582 * Pointer to the port ID action.
9583 * @param[out] dst_port_id
9584 * The target port ID.
9586 * Pointer to the error structure.
9589 * 0 on success, a negative errno value otherwise and rte_errno is set.
9592 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9593 const struct rte_flow_action *action,
9594 uint32_t *dst_port_id,
9595 struct rte_flow_error *error)
9598 struct mlx5_priv *priv;
9599 const struct rte_flow_action_port_id *conf =
9600 (const struct rte_flow_action_port_id *)action->conf;
9602 port = conf->original ? dev->data->port_id : conf->id;
9603 priv = mlx5_port_to_eswitch_info(port, false);
9605 return rte_flow_error_set(error, -rte_errno,
9606 RTE_FLOW_ERROR_TYPE_ACTION,
9608 "No eswitch info was found for port");
9609 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9611 * This parameter is transferred to
9612 * mlx5dv_dr_action_create_dest_ib_port().
9614 *dst_port_id = priv->dev_port;
9617 * Legacy mode, no LAG configurations is supported.
9618 * This parameter is transferred to
9619 * mlx5dv_dr_action_create_dest_vport().
9621 *dst_port_id = priv->vport_id;
9627 * Create a counter with aging configuration.
9630 * Pointer to rte_eth_dev structure.
9632 * Pointer to the counter action configuration.
9634 * Pointer to the aging action configuration.
9637 * Index to flow counter on success, 0 otherwise.
9640 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9641 struct mlx5_flow *dev_flow,
9642 const struct rte_flow_action_count *count,
9643 const struct rte_flow_action_age *age)
9646 struct mlx5_age_param *age_param;
9648 if (count && count->shared)
9649 counter = flow_dv_counter_get_shared(dev, count->id);
9651 counter = flow_dv_counter_alloc(dev, !!age);
9652 if (!counter || age == NULL)
9654 age_param = flow_dv_counter_idx_get_age(dev, counter);
9655 age_param->context = age->context ? age->context :
9656 (void *)(uintptr_t)(dev_flow->flow_idx);
9657 age_param->timeout = age->timeout;
9658 age_param->port_id = dev->data->port_id;
9659 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9660 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9665 * Add Tx queue matcher
9668 * Pointer to the dev struct.
9669 * @param[in, out] matcher
9671 * @param[in, out] key
9672 * Flow matcher value.
9674 * Flow pattern to translate.
9676 * Item is inner pattern.
9679 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9680 void *matcher, void *key,
9681 const struct rte_flow_item *item)
9683 const struct mlx5_rte_flow_item_tx_queue *queue_m;
9684 const struct mlx5_rte_flow_item_tx_queue *queue_v;
9686 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9688 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9689 struct mlx5_txq_ctrl *txq;
9693 queue_m = (const void *)item->mask;
9696 queue_v = (const void *)item->spec;
9699 txq = mlx5_txq_get(dev, queue_v->queue);
9702 queue = txq->obj->sq->id;
9703 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9704 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9705 queue & queue_m->queue);
9706 mlx5_txq_release(dev, queue_v->queue);
9710 * Set the hash fields according to the @p flow information.
9712 * @param[in] dev_flow
9713 * Pointer to the mlx5_flow.
9714 * @param[in] rss_desc
9715 * Pointer to the mlx5_flow_rss_desc.
9718 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9719 struct mlx5_flow_rss_desc *rss_desc)
9721 uint64_t items = dev_flow->handle->layers;
9723 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9725 dev_flow->hash_fields = 0;
9726 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9727 if (rss_desc->level >= 2) {
9728 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9732 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9733 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9734 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9735 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9736 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9737 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9738 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9740 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9742 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9743 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9744 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9745 if (rss_types & ETH_RSS_L3_SRC_ONLY)
9746 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9747 else if (rss_types & ETH_RSS_L3_DST_ONLY)
9748 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9750 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9753 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9754 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9755 if (rss_types & ETH_RSS_UDP) {
9756 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9757 dev_flow->hash_fields |=
9758 IBV_RX_HASH_SRC_PORT_UDP;
9759 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9760 dev_flow->hash_fields |=
9761 IBV_RX_HASH_DST_PORT_UDP;
9763 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9765 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9766 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9767 if (rss_types & ETH_RSS_TCP) {
9768 if (rss_types & ETH_RSS_L4_SRC_ONLY)
9769 dev_flow->hash_fields |=
9770 IBV_RX_HASH_SRC_PORT_TCP;
9771 else if (rss_types & ETH_RSS_L4_DST_ONLY)
9772 dev_flow->hash_fields |=
9773 IBV_RX_HASH_DST_PORT_TCP;
9775 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9781 * Prepare an Rx Hash queue.
9784 * Pointer to Ethernet device.
9785 * @param[in] dev_flow
9786 * Pointer to the mlx5_flow.
9787 * @param[in] rss_desc
9788 * Pointer to the mlx5_flow_rss_desc.
9789 * @param[out] hrxq_idx
9790 * Hash Rx queue index.
9793 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9795 static struct mlx5_hrxq *
9796 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9797 struct mlx5_flow *dev_flow,
9798 struct mlx5_flow_rss_desc *rss_desc,
9801 struct mlx5_priv *priv = dev->data->dev_private;
9802 struct mlx5_flow_handle *dh = dev_flow->handle;
9803 struct mlx5_hrxq *hrxq;
9805 MLX5_ASSERT(rss_desc->queue_num);
9806 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9807 rss_desc->hash_fields = dev_flow->hash_fields;
9808 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9809 rss_desc->shared_rss = 0;
9810 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9813 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9819 * Release sample sub action resource.
9821 * @param[in, out] dev
9822 * Pointer to rte_eth_dev structure.
9823 * @param[in] act_res
9824 * Pointer to sample sub action resource.
9827 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9828 struct mlx5_flow_sub_actions_idx *act_res)
9830 if (act_res->rix_hrxq) {
9831 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9832 act_res->rix_hrxq = 0;
9834 if (act_res->rix_encap_decap) {
9835 flow_dv_encap_decap_resource_release(dev,
9836 act_res->rix_encap_decap);
9837 act_res->rix_encap_decap = 0;
9839 if (act_res->rix_port_id_action) {
9840 flow_dv_port_id_action_resource_release(dev,
9841 act_res->rix_port_id_action);
9842 act_res->rix_port_id_action = 0;
9844 if (act_res->rix_tag) {
9845 flow_dv_tag_release(dev, act_res->rix_tag);
9846 act_res->rix_tag = 0;
9848 if (act_res->rix_jump) {
9849 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9850 act_res->rix_jump = 0;
9855 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9856 struct mlx5_cache_entry *entry, void *cb_ctx)
9858 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9859 struct rte_eth_dev *dev = ctx->dev;
9860 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9861 struct mlx5_flow_dv_sample_resource *cache_resource =
9862 container_of(entry, typeof(*cache_resource), entry);
9864 if (resource->ratio == cache_resource->ratio &&
9865 resource->ft_type == cache_resource->ft_type &&
9866 resource->ft_id == cache_resource->ft_id &&
9867 resource->set_action == cache_resource->set_action &&
9868 !memcmp((void *)&resource->sample_act,
9869 (void *)&cache_resource->sample_act,
9870 sizeof(struct mlx5_flow_sub_actions_list))) {
9872 * Existing sample action should release the prepared
9873 * sub-actions reference counter.
9875 flow_dv_sample_sub_actions_release(dev,
9876 &resource->sample_idx);
9882 struct mlx5_cache_entry *
9883 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9884 struct mlx5_cache_entry *entry __rte_unused,
9887 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9888 struct rte_eth_dev *dev = ctx->dev;
9889 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9890 void **sample_dv_actions = resource->sub_actions;
9891 struct mlx5_flow_dv_sample_resource *cache_resource;
9892 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9893 struct mlx5_priv *priv = dev->data->dev_private;
9894 struct mlx5_dev_ctx_shared *sh = priv->sh;
9895 struct mlx5_flow_tbl_resource *tbl;
9897 const uint32_t next_ft_step = 1;
9898 uint32_t next_ft_id = resource->ft_id + next_ft_step;
9899 uint8_t is_egress = 0;
9900 uint8_t is_transfer = 0;
9901 struct rte_flow_error *error = ctx->error;
9903 /* Register new sample resource. */
9904 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9905 if (!cache_resource) {
9906 rte_flow_error_set(error, ENOMEM,
9907 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9909 "cannot allocate resource memory");
9912 *cache_resource = *resource;
9913 /* Create normal path table level */
9914 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9916 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9918 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9919 is_egress, is_transfer,
9920 true, NULL, 0, 0, error);
9922 rte_flow_error_set(error, ENOMEM,
9923 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9925 "fail to create normal path table "
9929 cache_resource->normal_path_tbl = tbl;
9930 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9931 if (!sh->default_miss_action) {
9932 rte_flow_error_set(error, ENOMEM,
9933 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9935 "default miss action was not "
9939 sample_dv_actions[resource->sample_act.actions_num++] =
9940 sh->default_miss_action;
9942 /* Create a DR sample action */
9943 sampler_attr.sample_ratio = cache_resource->ratio;
9944 sampler_attr.default_next_table = tbl->obj;
9945 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9946 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9947 &sample_dv_actions[0];
9948 sampler_attr.action = cache_resource->set_action;
9949 if (mlx5_os_flow_dr_create_flow_action_sampler
9950 (&sampler_attr, &cache_resource->verbs_action)) {
9951 rte_flow_error_set(error, ENOMEM,
9952 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9953 NULL, "cannot create sample action");
9956 cache_resource->idx = idx;
9957 cache_resource->dev = dev;
9958 return &cache_resource->entry;
9960 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9961 flow_dv_sample_sub_actions_release(dev,
9962 &cache_resource->sample_idx);
9963 if (cache_resource->normal_path_tbl)
9964 flow_dv_tbl_resource_release(MLX5_SH(dev),
9965 cache_resource->normal_path_tbl);
9966 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9972 * Find existing sample resource or create and register a new one.
9974 * @param[in, out] dev
9975 * Pointer to rte_eth_dev structure.
9976 * @param[in] resource
9977 * Pointer to sample resource.
9978 * @parm[in, out] dev_flow
9979 * Pointer to the dev_flow.
9981 * pointer to error structure.
9984 * 0 on success otherwise -errno and errno is set.
9987 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9988 struct mlx5_flow_dv_sample_resource *resource,
9989 struct mlx5_flow *dev_flow,
9990 struct rte_flow_error *error)
9992 struct mlx5_flow_dv_sample_resource *cache_resource;
9993 struct mlx5_cache_entry *entry;
9994 struct mlx5_priv *priv = dev->data->dev_private;
9995 struct mlx5_flow_cb_ctx ctx = {
10001 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10004 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10005 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10006 dev_flow->dv.sample_res = cache_resource;
10011 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10012 struct mlx5_cache_entry *entry, void *cb_ctx)
10014 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10015 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10016 struct rte_eth_dev *dev = ctx->dev;
10017 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10018 container_of(entry, typeof(*cache_resource), entry);
10021 if (resource->num_of_dest == cache_resource->num_of_dest &&
10022 resource->ft_type == cache_resource->ft_type &&
10023 !memcmp((void *)cache_resource->sample_act,
10024 (void *)resource->sample_act,
10025 (resource->num_of_dest *
10026 sizeof(struct mlx5_flow_sub_actions_list)))) {
10028 * Existing sample action should release the prepared
10029 * sub-actions reference counter.
10031 for (idx = 0; idx < resource->num_of_dest; idx++)
10032 flow_dv_sample_sub_actions_release(dev,
10033 &resource->sample_idx[idx]);
10039 struct mlx5_cache_entry *
10040 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10041 struct mlx5_cache_entry *entry __rte_unused,
10044 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10045 struct rte_eth_dev *dev = ctx->dev;
10046 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10047 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10048 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10049 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10050 struct mlx5_priv *priv = dev->data->dev_private;
10051 struct mlx5_dev_ctx_shared *sh = priv->sh;
10052 struct mlx5_flow_sub_actions_list *sample_act;
10053 struct mlx5dv_dr_domain *domain;
10054 uint32_t idx = 0, res_idx = 0;
10055 struct rte_flow_error *error = ctx->error;
10056 uint64_t action_flags;
10059 /* Register new destination array resource. */
10060 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10062 if (!cache_resource) {
10063 rte_flow_error_set(error, ENOMEM,
10064 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10066 "cannot allocate resource memory");
10069 *cache_resource = *resource;
10070 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10071 domain = sh->fdb_domain;
10072 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10073 domain = sh->rx_domain;
10075 domain = sh->tx_domain;
10076 for (idx = 0; idx < resource->num_of_dest; idx++) {
10077 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10078 mlx5_malloc(MLX5_MEM_ZERO,
10079 sizeof(struct mlx5dv_dr_action_dest_attr),
10081 if (!dest_attr[idx]) {
10082 rte_flow_error_set(error, ENOMEM,
10083 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10085 "cannot allocate resource memory");
10088 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10089 sample_act = &resource->sample_act[idx];
10090 action_flags = sample_act->action_flags;
10091 switch (action_flags) {
10092 case MLX5_FLOW_ACTION_QUEUE:
10093 dest_attr[idx]->dest = sample_act->dr_queue_action;
10095 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10096 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10097 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10098 dest_attr[idx]->dest_reformat->reformat =
10099 sample_act->dr_encap_action;
10100 dest_attr[idx]->dest_reformat->dest =
10101 sample_act->dr_port_id_action;
10103 case MLX5_FLOW_ACTION_PORT_ID:
10104 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10106 case MLX5_FLOW_ACTION_JUMP:
10107 dest_attr[idx]->dest = sample_act->dr_jump_action;
10110 rte_flow_error_set(error, EINVAL,
10111 RTE_FLOW_ERROR_TYPE_ACTION,
10113 "unsupported actions type");
10117 /* create a dest array actioin */
10118 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10120 cache_resource->num_of_dest,
10122 &cache_resource->action);
10124 rte_flow_error_set(error, ENOMEM,
10125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10127 "cannot create destination array action");
10130 cache_resource->idx = res_idx;
10131 cache_resource->dev = dev;
10132 for (idx = 0; idx < resource->num_of_dest; idx++)
10133 mlx5_free(dest_attr[idx]);
10134 return &cache_resource->entry;
10136 for (idx = 0; idx < resource->num_of_dest; idx++) {
10137 struct mlx5_flow_sub_actions_idx *act_res =
10138 &cache_resource->sample_idx[idx];
10139 if (act_res->rix_hrxq &&
10140 !mlx5_hrxq_release(dev,
10141 act_res->rix_hrxq))
10142 act_res->rix_hrxq = 0;
10143 if (act_res->rix_encap_decap &&
10144 !flow_dv_encap_decap_resource_release(dev,
10145 act_res->rix_encap_decap))
10146 act_res->rix_encap_decap = 0;
10147 if (act_res->rix_port_id_action &&
10148 !flow_dv_port_id_action_resource_release(dev,
10149 act_res->rix_port_id_action))
10150 act_res->rix_port_id_action = 0;
10151 if (act_res->rix_jump &&
10152 !flow_dv_jump_tbl_resource_release(dev,
10153 act_res->rix_jump))
10154 act_res->rix_jump = 0;
10155 if (dest_attr[idx])
10156 mlx5_free(dest_attr[idx]);
10159 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10164 * Find existing destination array resource or create and register a new one.
10166 * @param[in, out] dev
10167 * Pointer to rte_eth_dev structure.
10168 * @param[in] resource
10169 * Pointer to destination array resource.
10170 * @parm[in, out] dev_flow
10171 * Pointer to the dev_flow.
10172 * @param[out] error
10173 * pointer to error structure.
10176 * 0 on success otherwise -errno and errno is set.
10179 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10180 struct mlx5_flow_dv_dest_array_resource *resource,
10181 struct mlx5_flow *dev_flow,
10182 struct rte_flow_error *error)
10184 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10185 struct mlx5_priv *priv = dev->data->dev_private;
10186 struct mlx5_cache_entry *entry;
10187 struct mlx5_flow_cb_ctx ctx = {
10193 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10196 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10197 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10198 dev_flow->dv.dest_array_res = cache_resource;
10203 * Convert Sample action to DV specification.
10206 * Pointer to rte_eth_dev structure.
10207 * @param[in] action
10208 * Pointer to sample action structure.
10209 * @param[in, out] dev_flow
10210 * Pointer to the mlx5_flow.
10212 * Pointer to the flow attributes.
10213 * @param[in, out] num_of_dest
10214 * Pointer to the num of destination.
10215 * @param[in, out] sample_actions
10216 * Pointer to sample actions list.
10217 * @param[in, out] res
10218 * Pointer to sample resource.
10219 * @param[out] error
10220 * Pointer to the error structure.
10223 * 0 on success, a negative errno value otherwise and rte_errno is set.
10226 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10227 const struct rte_flow_action_sample *action,
10228 struct mlx5_flow *dev_flow,
10229 const struct rte_flow_attr *attr,
10230 uint32_t *num_of_dest,
10231 void **sample_actions,
10232 struct mlx5_flow_dv_sample_resource *res,
10233 struct rte_flow_error *error)
10235 struct mlx5_priv *priv = dev->data->dev_private;
10236 const struct rte_flow_action *sub_actions;
10237 struct mlx5_flow_sub_actions_list *sample_act;
10238 struct mlx5_flow_sub_actions_idx *sample_idx;
10239 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10240 struct rte_flow *flow = dev_flow->flow;
10241 struct mlx5_flow_rss_desc *rss_desc;
10242 uint64_t action_flags = 0;
10245 rss_desc = &wks->rss_desc;
10246 sample_act = &res->sample_act;
10247 sample_idx = &res->sample_idx;
10248 res->ratio = action->ratio;
10249 sub_actions = action->actions;
10250 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10251 int type = sub_actions->type;
10252 uint32_t pre_rix = 0;
10255 case RTE_FLOW_ACTION_TYPE_QUEUE:
10257 const struct rte_flow_action_queue *queue;
10258 struct mlx5_hrxq *hrxq;
10261 queue = sub_actions->conf;
10262 rss_desc->queue_num = 1;
10263 rss_desc->queue[0] = queue->index;
10264 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10265 rss_desc, &hrxq_idx);
10267 return rte_flow_error_set
10269 RTE_FLOW_ERROR_TYPE_ACTION,
10271 "cannot create fate queue");
10272 sample_act->dr_queue_action = hrxq->action;
10273 sample_idx->rix_hrxq = hrxq_idx;
10274 sample_actions[sample_act->actions_num++] =
10277 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10278 if (action_flags & MLX5_FLOW_ACTION_MARK)
10279 dev_flow->handle->rix_hrxq = hrxq_idx;
10280 dev_flow->handle->fate_action =
10281 MLX5_FLOW_FATE_QUEUE;
10284 case RTE_FLOW_ACTION_TYPE_RSS:
10286 struct mlx5_hrxq *hrxq;
10288 const struct rte_flow_action_rss *rss;
10289 const uint8_t *rss_key;
10291 rss = sub_actions->conf;
10292 memcpy(rss_desc->queue, rss->queue,
10293 rss->queue_num * sizeof(uint16_t));
10294 rss_desc->queue_num = rss->queue_num;
10295 /* NULL RSS key indicates default RSS key. */
10296 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10297 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10299 * rss->level and rss.types should be set in advance
10300 * when expanding items for RSS.
10302 flow_dv_hashfields_set(dev_flow, rss_desc);
10303 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10304 rss_desc, &hrxq_idx);
10306 return rte_flow_error_set
10308 RTE_FLOW_ERROR_TYPE_ACTION,
10310 "cannot create fate queue");
10311 sample_act->dr_queue_action = hrxq->action;
10312 sample_idx->rix_hrxq = hrxq_idx;
10313 sample_actions[sample_act->actions_num++] =
10316 action_flags |= MLX5_FLOW_ACTION_RSS;
10317 if (action_flags & MLX5_FLOW_ACTION_MARK)
10318 dev_flow->handle->rix_hrxq = hrxq_idx;
10319 dev_flow->handle->fate_action =
10320 MLX5_FLOW_FATE_QUEUE;
10323 case RTE_FLOW_ACTION_TYPE_MARK:
10325 uint32_t tag_be = mlx5_flow_mark_set
10326 (((const struct rte_flow_action_mark *)
10327 (sub_actions->conf))->id);
10329 dev_flow->handle->mark = 1;
10330 pre_rix = dev_flow->handle->dvh.rix_tag;
10331 /* Save the mark resource before sample */
10332 pre_r = dev_flow->dv.tag_resource;
10333 if (flow_dv_tag_resource_register(dev, tag_be,
10336 MLX5_ASSERT(dev_flow->dv.tag_resource);
10337 sample_act->dr_tag_action =
10338 dev_flow->dv.tag_resource->action;
10339 sample_idx->rix_tag =
10340 dev_flow->handle->dvh.rix_tag;
10341 sample_actions[sample_act->actions_num++] =
10342 sample_act->dr_tag_action;
10343 /* Recover the mark resource after sample */
10344 dev_flow->dv.tag_resource = pre_r;
10345 dev_flow->handle->dvh.rix_tag = pre_rix;
10346 action_flags |= MLX5_FLOW_ACTION_MARK;
10349 case RTE_FLOW_ACTION_TYPE_COUNT:
10351 if (!flow->counter) {
10353 flow_dv_translate_create_counter(dev,
10354 dev_flow, sub_actions->conf,
10356 if (!flow->counter)
10357 return rte_flow_error_set
10359 RTE_FLOW_ERROR_TYPE_ACTION,
10361 "cannot create counter"
10364 sample_act->dr_cnt_action =
10365 (flow_dv_counter_get_by_idx(dev,
10366 flow->counter, NULL))->action;
10367 sample_actions[sample_act->actions_num++] =
10368 sample_act->dr_cnt_action;
10369 action_flags |= MLX5_FLOW_ACTION_COUNT;
10372 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10374 struct mlx5_flow_dv_port_id_action_resource
10376 uint32_t port_id = 0;
10378 memset(&port_id_resource, 0, sizeof(port_id_resource));
10379 /* Save the port id resource before sample */
10380 pre_rix = dev_flow->handle->rix_port_id_action;
10381 pre_r = dev_flow->dv.port_id_action;
10382 if (flow_dv_translate_action_port_id(dev, sub_actions,
10385 port_id_resource.port_id = port_id;
10386 if (flow_dv_port_id_action_resource_register
10387 (dev, &port_id_resource, dev_flow, error))
10389 sample_act->dr_port_id_action =
10390 dev_flow->dv.port_id_action->action;
10391 sample_idx->rix_port_id_action =
10392 dev_flow->handle->rix_port_id_action;
10393 sample_actions[sample_act->actions_num++] =
10394 sample_act->dr_port_id_action;
10395 /* Recover the port id resource after sample */
10396 dev_flow->dv.port_id_action = pre_r;
10397 dev_flow->handle->rix_port_id_action = pre_rix;
10399 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10402 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10403 /* Save the encap resource before sample */
10404 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10405 pre_r = dev_flow->dv.encap_decap;
10406 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10411 sample_act->dr_encap_action =
10412 dev_flow->dv.encap_decap->action;
10413 sample_idx->rix_encap_decap =
10414 dev_flow->handle->dvh.rix_encap_decap;
10415 sample_actions[sample_act->actions_num++] =
10416 sample_act->dr_encap_action;
10417 /* Recover the encap resource after sample */
10418 dev_flow->dv.encap_decap = pre_r;
10419 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10420 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10423 return rte_flow_error_set(error, EINVAL,
10424 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10426 "Not support for sampler action");
10429 sample_act->action_flags = action_flags;
10430 res->ft_id = dev_flow->dv.group;
10431 if (attr->transfer) {
10433 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10434 uint64_t set_action;
10435 } action_ctx = { .set_action = 0 };
10437 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10438 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10439 MLX5_MODIFICATION_TYPE_SET);
10440 MLX5_SET(set_action_in, action_ctx.action_in, field,
10441 MLX5_MODI_META_REG_C_0);
10442 MLX5_SET(set_action_in, action_ctx.action_in, data,
10443 priv->vport_meta_tag);
10444 res->set_action = action_ctx.set_action;
10445 } else if (attr->ingress) {
10446 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10448 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10454 * Convert Sample action to DV specification.
10457 * Pointer to rte_eth_dev structure.
10458 * @param[in, out] dev_flow
10459 * Pointer to the mlx5_flow.
10460 * @param[in] num_of_dest
10461 * The num of destination.
10462 * @param[in, out] res
10463 * Pointer to sample resource.
10464 * @param[in, out] mdest_res
10465 * Pointer to destination array resource.
10466 * @param[in] sample_actions
10467 * Pointer to sample path actions list.
10468 * @param[in] action_flags
10469 * Holds the actions detected until now.
10470 * @param[out] error
10471 * Pointer to the error structure.
10474 * 0 on success, a negative errno value otherwise and rte_errno is set.
10477 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10478 struct mlx5_flow *dev_flow,
10479 uint32_t num_of_dest,
10480 struct mlx5_flow_dv_sample_resource *res,
10481 struct mlx5_flow_dv_dest_array_resource *mdest_res,
10482 void **sample_actions,
10483 uint64_t action_flags,
10484 struct rte_flow_error *error)
10486 /* update normal path action resource into last index of array */
10487 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10488 struct mlx5_flow_sub_actions_list *sample_act =
10489 &mdest_res->sample_act[dest_index];
10490 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10491 struct mlx5_flow_rss_desc *rss_desc;
10492 uint32_t normal_idx = 0;
10493 struct mlx5_hrxq *hrxq;
10497 rss_desc = &wks->rss_desc;
10498 if (num_of_dest > 1) {
10499 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10500 /* Handle QP action for mirroring */
10501 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10502 rss_desc, &hrxq_idx);
10504 return rte_flow_error_set
10506 RTE_FLOW_ERROR_TYPE_ACTION,
10508 "cannot create rx queue");
10510 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10511 sample_act->dr_queue_action = hrxq->action;
10512 if (action_flags & MLX5_FLOW_ACTION_MARK)
10513 dev_flow->handle->rix_hrxq = hrxq_idx;
10514 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10516 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10518 mdest_res->sample_idx[dest_index].rix_encap_decap =
10519 dev_flow->handle->dvh.rix_encap_decap;
10520 sample_act->dr_encap_action =
10521 dev_flow->dv.encap_decap->action;
10523 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10525 mdest_res->sample_idx[dest_index].rix_port_id_action =
10526 dev_flow->handle->rix_port_id_action;
10527 sample_act->dr_port_id_action =
10528 dev_flow->dv.port_id_action->action;
10530 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10532 mdest_res->sample_idx[dest_index].rix_jump =
10533 dev_flow->handle->rix_jump;
10534 sample_act->dr_jump_action =
10535 dev_flow->dv.jump->action;
10536 dev_flow->handle->rix_jump = 0;
10538 sample_act->actions_num = normal_idx;
10539 /* update sample action resource into first index of array */
10540 mdest_res->ft_type = res->ft_type;
10541 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10542 sizeof(struct mlx5_flow_sub_actions_idx));
10543 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10544 sizeof(struct mlx5_flow_sub_actions_list));
10545 mdest_res->num_of_dest = num_of_dest;
10546 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10548 return rte_flow_error_set(error, EINVAL,
10549 RTE_FLOW_ERROR_TYPE_ACTION,
10550 NULL, "can't create sample "
10553 res->sub_actions = sample_actions;
10554 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10555 return rte_flow_error_set(error, EINVAL,
10556 RTE_FLOW_ERROR_TYPE_ACTION,
10558 "can't create sample action");
10564 * Remove an ASO age action from age actions list.
10567 * Pointer to the Ethernet device structure.
10569 * Pointer to the aso age action handler.
10572 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10573 struct mlx5_aso_age_action *age)
10575 struct mlx5_age_info *age_info;
10576 struct mlx5_age_param *age_param = &age->age_params;
10577 struct mlx5_priv *priv = dev->data->dev_private;
10578 uint16_t expected = AGE_CANDIDATE;
10580 age_info = GET_PORT_AGE_INFO(priv);
10581 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10582 AGE_FREE, false, __ATOMIC_RELAXED,
10583 __ATOMIC_RELAXED)) {
10585 * We need the lock even it is age timeout,
10586 * since age action may still in process.
10588 rte_spinlock_lock(&age_info->aged_sl);
10589 LIST_REMOVE(age, next);
10590 rte_spinlock_unlock(&age_info->aged_sl);
10591 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10596 * Release an ASO age action.
10599 * Pointer to the Ethernet device structure.
10600 * @param[in] age_idx
10601 * Index of ASO age action to release.
10603 * True if the release operation is during flow destroy operation.
10604 * False if the release operation is during action destroy operation.
10607 * 0 when age action was removed, otherwise the number of references.
10610 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10612 struct mlx5_priv *priv = dev->data->dev_private;
10613 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10614 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10615 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10618 flow_dv_aso_age_remove_from_age(dev, age);
10619 rte_spinlock_lock(&mng->free_sl);
10620 LIST_INSERT_HEAD(&mng->free, age, next);
10621 rte_spinlock_unlock(&mng->free_sl);
10627 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10630 * Pointer to the Ethernet device structure.
10633 * 0 on success, otherwise negative errno value and rte_errno is set.
10636 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10638 struct mlx5_priv *priv = dev->data->dev_private;
10639 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10640 void *old_pools = mng->pools;
10641 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10642 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10643 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10646 rte_errno = ENOMEM;
10650 memcpy(pools, old_pools,
10651 mng->n * sizeof(struct mlx5_flow_counter_pool *));
10652 mlx5_free(old_pools);
10654 /* First ASO flow hit allocation - starting ASO data-path. */
10655 int ret = mlx5_aso_queue_start(priv->sh);
10663 mng->pools = pools;
10668 * Create and initialize a new ASO aging pool.
10671 * Pointer to the Ethernet device structure.
10672 * @param[out] age_free
10673 * Where to put the pointer of a new age action.
10676 * The age actions pool pointer and @p age_free is set on success,
10677 * NULL otherwise and rte_errno is set.
10679 static struct mlx5_aso_age_pool *
10680 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10681 struct mlx5_aso_age_action **age_free)
10683 struct mlx5_priv *priv = dev->data->dev_private;
10684 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10685 struct mlx5_aso_age_pool *pool = NULL;
10686 struct mlx5_devx_obj *obj = NULL;
10689 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10692 rte_errno = ENODATA;
10693 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10696 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10698 claim_zero(mlx5_devx_cmd_destroy(obj));
10699 rte_errno = ENOMEM;
10702 pool->flow_hit_aso_obj = obj;
10703 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10704 rte_spinlock_lock(&mng->resize_sl);
10705 pool->index = mng->next;
10706 /* Resize pools array if there is no room for the new pool in it. */
10707 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10708 claim_zero(mlx5_devx_cmd_destroy(obj));
10710 rte_spinlock_unlock(&mng->resize_sl);
10713 mng->pools[pool->index] = pool;
10715 rte_spinlock_unlock(&mng->resize_sl);
10716 /* Assign the first action in the new pool, the rest go to free list. */
10717 *age_free = &pool->actions[0];
10718 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10719 pool->actions[i].offset = i;
10720 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10726 * Allocate a ASO aging bit.
10729 * Pointer to the Ethernet device structure.
10730 * @param[out] error
10731 * Pointer to the error structure.
10734 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
10737 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10739 struct mlx5_priv *priv = dev->data->dev_private;
10740 const struct mlx5_aso_age_pool *pool;
10741 struct mlx5_aso_age_action *age_free = NULL;
10742 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10745 /* Try to get the next free age action bit. */
10746 rte_spinlock_lock(&mng->free_sl);
10747 age_free = LIST_FIRST(&mng->free);
10749 LIST_REMOVE(age_free, next);
10750 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10751 rte_spinlock_unlock(&mng->free_sl);
10752 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10753 NULL, "failed to create ASO age pool");
10754 return 0; /* 0 is an error. */
10756 rte_spinlock_unlock(&mng->free_sl);
10757 pool = container_of
10758 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10759 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10761 if (!age_free->dr_action) {
10762 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10766 rte_flow_error_set(error, rte_errno,
10767 RTE_FLOW_ERROR_TYPE_ACTION,
10768 NULL, "failed to get reg_c "
10769 "for ASO flow hit");
10770 return 0; /* 0 is an error. */
10772 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10773 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10774 (priv->sh->rx_domain,
10775 pool->flow_hit_aso_obj->obj, age_free->offset,
10776 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10777 (reg_c - REG_C_0));
10778 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10779 if (!age_free->dr_action) {
10781 rte_spinlock_lock(&mng->free_sl);
10782 LIST_INSERT_HEAD(&mng->free, age_free, next);
10783 rte_spinlock_unlock(&mng->free_sl);
10784 rte_flow_error_set(error, rte_errno,
10785 RTE_FLOW_ERROR_TYPE_ACTION,
10786 NULL, "failed to create ASO "
10787 "flow hit action");
10788 return 0; /* 0 is an error. */
10791 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10792 return pool->index | ((age_free->offset + 1) << 16);
10796 * Create a age action using ASO mechanism.
10799 * Pointer to rte_eth_dev structure.
10801 * Pointer to the aging action configuration.
10802 * @param[out] error
10803 * Pointer to the error structure.
10806 * Index to flow counter on success, 0 otherwise.
10809 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10810 const struct rte_flow_action_age *age,
10811 struct rte_flow_error *error)
10813 uint32_t age_idx = 0;
10814 struct mlx5_aso_age_action *aso_age;
10816 age_idx = flow_dv_aso_age_alloc(dev, error);
10819 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10820 aso_age->age_params.context = age->context;
10821 aso_age->age_params.timeout = age->timeout;
10822 aso_age->age_params.port_id = dev->data->port_id;
10823 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10825 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10831 * Fill the flow with DV spec, lock free
10832 * (mutex should be acquired by caller).
10835 * Pointer to rte_eth_dev structure.
10836 * @param[in, out] dev_flow
10837 * Pointer to the sub flow.
10839 * Pointer to the flow attributes.
10841 * Pointer to the list of items.
10842 * @param[in] actions
10843 * Pointer to the list of actions.
10844 * @param[out] error
10845 * Pointer to the error structure.
10848 * 0 on success, a negative errno value otherwise and rte_errno is set.
10851 flow_dv_translate(struct rte_eth_dev *dev,
10852 struct mlx5_flow *dev_flow,
10853 const struct rte_flow_attr *attr,
10854 const struct rte_flow_item items[],
10855 const struct rte_flow_action actions[],
10856 struct rte_flow_error *error)
10858 struct mlx5_priv *priv = dev->data->dev_private;
10859 struct mlx5_dev_config *dev_conf = &priv->config;
10860 struct rte_flow *flow = dev_flow->flow;
10861 struct mlx5_flow_handle *handle = dev_flow->handle;
10862 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10863 struct mlx5_flow_rss_desc *rss_desc;
10864 uint64_t item_flags = 0;
10865 uint64_t last_item = 0;
10866 uint64_t action_flags = 0;
10867 struct mlx5_flow_dv_matcher matcher = {
10869 .size = sizeof(matcher.mask.buf) -
10870 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10874 bool actions_end = false;
10876 struct mlx5_flow_dv_modify_hdr_resource res;
10877 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10878 sizeof(struct mlx5_modification_cmd) *
10879 (MLX5_MAX_MODIFY_NUM + 1)];
10881 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10882 const struct rte_flow_action_count *count = NULL;
10883 const struct rte_flow_action_age *age = NULL;
10884 union flow_dv_attr flow_attr = { .attr = 0 };
10886 union mlx5_flow_tbl_key tbl_key;
10887 uint32_t modify_action_position = UINT32_MAX;
10888 void *match_mask = matcher.mask.buf;
10889 void *match_value = dev_flow->dv.value.buf;
10890 uint8_t next_protocol = 0xff;
10891 struct rte_vlan_hdr vlan = { 0 };
10892 struct mlx5_flow_dv_dest_array_resource mdest_res;
10893 struct mlx5_flow_dv_sample_resource sample_res;
10894 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10895 const struct rte_flow_action_sample *sample = NULL;
10896 struct mlx5_flow_sub_actions_list *sample_act;
10897 uint32_t sample_act_pos = UINT32_MAX;
10898 uint32_t num_of_dest = 0;
10899 int tmp_actions_n = 0;
10902 const struct mlx5_flow_tunnel *tunnel;
10903 struct flow_grp_info grp_info = {
10904 .external = !!dev_flow->external,
10905 .transfer = !!attr->transfer,
10906 .fdb_def_rule = !!priv->fdb_def_rule,
10907 .skip_scale = dev_flow->skip_scale &
10908 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10912 return rte_flow_error_set(error, ENOMEM,
10913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10915 "failed to push flow workspace");
10916 rss_desc = &wks->rss_desc;
10917 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10918 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10919 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10920 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10921 /* update normal path action resource into last index of array */
10922 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10923 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10924 flow_items_to_tunnel(items) :
10925 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10926 flow_actions_to_tunnel(actions) :
10927 dev_flow->tunnel ? dev_flow->tunnel : NULL;
10928 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10929 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10930 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10931 (dev, tunnel, attr, items, actions);
10932 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10936 dev_flow->dv.group = table;
10937 if (attr->transfer)
10938 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10939 /* number of actions must be set to 0 in case of dirty stack. */
10940 mhdr_res->actions_num = 0;
10941 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10943 * do not add decap action if match rule drops packet
10944 * HW rejects rules with decap & drop
10946 * if tunnel match rule was inserted before matching tunnel set
10947 * rule flow table used in the match rule must be registered.
10948 * current implementation handles that in the
10949 * flow_dv_match_register() at the function end.
10951 bool add_decap = true;
10952 const struct rte_flow_action *ptr = actions;
10954 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10955 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10961 if (flow_dv_create_action_l2_decap(dev, dev_flow,
10965 dev_flow->dv.actions[actions_n++] =
10966 dev_flow->dv.encap_decap->action;
10967 action_flags |= MLX5_FLOW_ACTION_DECAP;
10970 for (; !actions_end ; actions++) {
10971 const struct rte_flow_action_queue *queue;
10972 const struct rte_flow_action_rss *rss;
10973 const struct rte_flow_action *action = actions;
10974 const uint8_t *rss_key;
10975 const struct rte_flow_action_meter *mtr;
10976 struct mlx5_flow_tbl_resource *tbl;
10977 struct mlx5_aso_age_action *age_act;
10978 uint32_t port_id = 0;
10979 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10980 int action_type = actions->type;
10981 const struct rte_flow_action *found_action = NULL;
10982 struct mlx5_flow_meter *fm = NULL;
10983 uint32_t jump_group = 0;
10985 if (!mlx5_flow_os_action_supported(action_type))
10986 return rte_flow_error_set(error, ENOTSUP,
10987 RTE_FLOW_ERROR_TYPE_ACTION,
10989 "action not supported");
10990 switch (action_type) {
10991 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10992 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10994 case RTE_FLOW_ACTION_TYPE_VOID:
10996 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10997 if (flow_dv_translate_action_port_id(dev, action,
11000 port_id_resource.port_id = port_id;
11001 MLX5_ASSERT(!handle->rix_port_id_action);
11002 if (flow_dv_port_id_action_resource_register
11003 (dev, &port_id_resource, dev_flow, error))
11005 dev_flow->dv.actions[actions_n++] =
11006 dev_flow->dv.port_id_action->action;
11007 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11008 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11009 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11012 case RTE_FLOW_ACTION_TYPE_FLAG:
11013 action_flags |= MLX5_FLOW_ACTION_FLAG;
11014 dev_flow->handle->mark = 1;
11015 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11016 struct rte_flow_action_mark mark = {
11017 .id = MLX5_FLOW_MARK_DEFAULT,
11020 if (flow_dv_convert_action_mark(dev, &mark,
11024 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11027 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11029 * Only one FLAG or MARK is supported per device flow
11030 * right now. So the pointer to the tag resource must be
11031 * zero before the register process.
11033 MLX5_ASSERT(!handle->dvh.rix_tag);
11034 if (flow_dv_tag_resource_register(dev, tag_be,
11037 MLX5_ASSERT(dev_flow->dv.tag_resource);
11038 dev_flow->dv.actions[actions_n++] =
11039 dev_flow->dv.tag_resource->action;
11041 case RTE_FLOW_ACTION_TYPE_MARK:
11042 action_flags |= MLX5_FLOW_ACTION_MARK;
11043 dev_flow->handle->mark = 1;
11044 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11045 const struct rte_flow_action_mark *mark =
11046 (const struct rte_flow_action_mark *)
11049 if (flow_dv_convert_action_mark(dev, mark,
11053 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11057 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11058 /* Legacy (non-extensive) MARK action. */
11059 tag_be = mlx5_flow_mark_set
11060 (((const struct rte_flow_action_mark *)
11061 (actions->conf))->id);
11062 MLX5_ASSERT(!handle->dvh.rix_tag);
11063 if (flow_dv_tag_resource_register(dev, tag_be,
11066 MLX5_ASSERT(dev_flow->dv.tag_resource);
11067 dev_flow->dv.actions[actions_n++] =
11068 dev_flow->dv.tag_resource->action;
11070 case RTE_FLOW_ACTION_TYPE_SET_META:
11071 if (flow_dv_convert_action_set_meta
11072 (dev, mhdr_res, attr,
11073 (const struct rte_flow_action_set_meta *)
11074 actions->conf, error))
11076 action_flags |= MLX5_FLOW_ACTION_SET_META;
11078 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11079 if (flow_dv_convert_action_set_tag
11081 (const struct rte_flow_action_set_tag *)
11082 actions->conf, error))
11084 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11086 case RTE_FLOW_ACTION_TYPE_DROP:
11087 action_flags |= MLX5_FLOW_ACTION_DROP;
11088 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11090 case RTE_FLOW_ACTION_TYPE_QUEUE:
11091 queue = actions->conf;
11092 rss_desc->queue_num = 1;
11093 rss_desc->queue[0] = queue->index;
11094 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11095 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11096 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11099 case RTE_FLOW_ACTION_TYPE_RSS:
11100 rss = actions->conf;
11101 memcpy(rss_desc->queue, rss->queue,
11102 rss->queue_num * sizeof(uint16_t));
11103 rss_desc->queue_num = rss->queue_num;
11104 /* NULL RSS key indicates default RSS key. */
11105 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11106 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11108 * rss->level and rss.types should be set in advance
11109 * when expanding items for RSS.
11111 action_flags |= MLX5_FLOW_ACTION_RSS;
11112 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11113 MLX5_FLOW_FATE_SHARED_RSS :
11114 MLX5_FLOW_FATE_QUEUE;
11116 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11117 flow->age = (uint32_t)(uintptr_t)(action->conf);
11118 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11119 __atomic_fetch_add(&age_act->refcnt, 1,
11121 dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11122 action_flags |= MLX5_FLOW_ACTION_AGE;
11124 case RTE_FLOW_ACTION_TYPE_AGE:
11125 if (priv->sh->flow_hit_aso_en && attr->group) {
11127 * Create one shared age action, to be used
11128 * by all sub-flows.
11132 flow_dv_translate_create_aso_age
11133 (dev, action->conf,
11136 return rte_flow_error_set
11138 RTE_FLOW_ERROR_TYPE_ACTION,
11140 "can't create ASO age action");
11142 dev_flow->dv.actions[actions_n++] =
11143 (flow_aso_age_get_by_idx
11144 (dev, flow->age))->dr_action;
11145 action_flags |= MLX5_FLOW_ACTION_AGE;
11149 case RTE_FLOW_ACTION_TYPE_COUNT:
11150 if (!dev_conf->devx) {
11151 return rte_flow_error_set
11153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11155 "count action not supported");
11157 /* Save information first, will apply later. */
11158 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11159 count = action->conf;
11161 age = action->conf;
11162 action_flags |= MLX5_FLOW_ACTION_COUNT;
11164 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11165 dev_flow->dv.actions[actions_n++] =
11166 priv->sh->pop_vlan_action;
11167 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11169 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11170 if (!(action_flags &
11171 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11172 flow_dev_get_vlan_info_from_items(items, &vlan);
11173 vlan.eth_proto = rte_be_to_cpu_16
11174 ((((const struct rte_flow_action_of_push_vlan *)
11175 actions->conf)->ethertype));
11176 found_action = mlx5_flow_find_action
11178 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11180 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11181 found_action = mlx5_flow_find_action
11183 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11185 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11186 if (flow_dv_create_action_push_vlan
11187 (dev, attr, &vlan, dev_flow, error))
11189 dev_flow->dv.actions[actions_n++] =
11190 dev_flow->dv.push_vlan_res->action;
11191 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11193 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11194 /* of_vlan_push action handled this action */
11195 MLX5_ASSERT(action_flags &
11196 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11198 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11199 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11201 flow_dev_get_vlan_info_from_items(items, &vlan);
11202 mlx5_update_vlan_vid_pcp(actions, &vlan);
11203 /* If no VLAN push - this is a modify header action */
11204 if (flow_dv_convert_action_modify_vlan_vid
11205 (mhdr_res, actions, error))
11207 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11209 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11210 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11211 if (flow_dv_create_action_l2_encap(dev, actions,
11216 dev_flow->dv.actions[actions_n++] =
11217 dev_flow->dv.encap_decap->action;
11218 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11219 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11220 sample_act->action_flags |=
11221 MLX5_FLOW_ACTION_ENCAP;
11223 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11224 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11225 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11229 dev_flow->dv.actions[actions_n++] =
11230 dev_flow->dv.encap_decap->action;
11231 action_flags |= MLX5_FLOW_ACTION_DECAP;
11233 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11234 /* Handle encap with preceding decap. */
11235 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11236 if (flow_dv_create_action_raw_encap
11237 (dev, actions, dev_flow, attr, error))
11239 dev_flow->dv.actions[actions_n++] =
11240 dev_flow->dv.encap_decap->action;
11242 /* Handle encap without preceding decap. */
11243 if (flow_dv_create_action_l2_encap
11244 (dev, actions, dev_flow, attr->transfer,
11247 dev_flow->dv.actions[actions_n++] =
11248 dev_flow->dv.encap_decap->action;
11250 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11251 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11252 sample_act->action_flags |=
11253 MLX5_FLOW_ACTION_ENCAP;
11255 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11256 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11258 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11259 if (flow_dv_create_action_l2_decap
11260 (dev, dev_flow, attr->transfer, error))
11262 dev_flow->dv.actions[actions_n++] =
11263 dev_flow->dv.encap_decap->action;
11265 /* If decap is followed by encap, handle it at encap. */
11266 action_flags |= MLX5_FLOW_ACTION_DECAP;
11268 case RTE_FLOW_ACTION_TYPE_JUMP:
11269 jump_group = ((const struct rte_flow_action_jump *)
11270 action->conf)->group;
11271 grp_info.std_tbl_fix = 0;
11272 if (dev_flow->skip_scale &
11273 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11274 grp_info.skip_scale = 1;
11276 grp_info.skip_scale = 0;
11277 ret = mlx5_flow_group_to_table(dev, tunnel,
11283 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11285 !!dev_flow->external,
11286 tunnel, jump_group, 0,
11289 return rte_flow_error_set
11291 RTE_FLOW_ERROR_TYPE_ACTION,
11293 "cannot create jump action.");
11294 if (flow_dv_jump_tbl_resource_register
11295 (dev, tbl, dev_flow, error)) {
11296 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11297 return rte_flow_error_set
11299 RTE_FLOW_ERROR_TYPE_ACTION,
11301 "cannot create jump action.");
11303 dev_flow->dv.actions[actions_n++] =
11304 dev_flow->dv.jump->action;
11305 action_flags |= MLX5_FLOW_ACTION_JUMP;
11306 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11307 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11310 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11311 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11312 if (flow_dv_convert_action_modify_mac
11313 (mhdr_res, actions, error))
11315 action_flags |= actions->type ==
11316 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11317 MLX5_FLOW_ACTION_SET_MAC_SRC :
11318 MLX5_FLOW_ACTION_SET_MAC_DST;
11320 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11321 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11322 if (flow_dv_convert_action_modify_ipv4
11323 (mhdr_res, actions, error))
11325 action_flags |= actions->type ==
11326 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11327 MLX5_FLOW_ACTION_SET_IPV4_SRC :
11328 MLX5_FLOW_ACTION_SET_IPV4_DST;
11330 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11331 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11332 if (flow_dv_convert_action_modify_ipv6
11333 (mhdr_res, actions, error))
11335 action_flags |= actions->type ==
11336 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11337 MLX5_FLOW_ACTION_SET_IPV6_SRC :
11338 MLX5_FLOW_ACTION_SET_IPV6_DST;
11340 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11341 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11342 if (flow_dv_convert_action_modify_tp
11343 (mhdr_res, actions, items,
11344 &flow_attr, dev_flow, !!(action_flags &
11345 MLX5_FLOW_ACTION_DECAP), error))
11347 action_flags |= actions->type ==
11348 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11349 MLX5_FLOW_ACTION_SET_TP_SRC :
11350 MLX5_FLOW_ACTION_SET_TP_DST;
11352 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11353 if (flow_dv_convert_action_modify_dec_ttl
11354 (mhdr_res, items, &flow_attr, dev_flow,
11356 MLX5_FLOW_ACTION_DECAP), error))
11358 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11360 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11361 if (flow_dv_convert_action_modify_ttl
11362 (mhdr_res, actions, items, &flow_attr,
11363 dev_flow, !!(action_flags &
11364 MLX5_FLOW_ACTION_DECAP), error))
11366 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11368 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11369 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11370 if (flow_dv_convert_action_modify_tcp_seq
11371 (mhdr_res, actions, error))
11373 action_flags |= actions->type ==
11374 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11375 MLX5_FLOW_ACTION_INC_TCP_SEQ :
11376 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11379 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11380 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11381 if (flow_dv_convert_action_modify_tcp_ack
11382 (mhdr_res, actions, error))
11384 action_flags |= actions->type ==
11385 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11386 MLX5_FLOW_ACTION_INC_TCP_ACK :
11387 MLX5_FLOW_ACTION_DEC_TCP_ACK;
11389 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11390 if (flow_dv_convert_action_set_reg
11391 (mhdr_res, actions, error))
11393 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11395 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11396 if (flow_dv_convert_action_copy_mreg
11397 (dev, mhdr_res, actions, error))
11399 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11401 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11402 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11403 dev_flow->handle->fate_action =
11404 MLX5_FLOW_FATE_DEFAULT_MISS;
11406 case RTE_FLOW_ACTION_TYPE_METER:
11407 mtr = actions->conf;
11408 if (!flow->meter) {
11409 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11412 return rte_flow_error_set(error,
11414 RTE_FLOW_ERROR_TYPE_ACTION,
11417 "or invalid parameters");
11418 flow->meter = fm->idx;
11420 /* Set the meter action. */
11422 fm = mlx5_ipool_get(priv->sh->ipool
11423 [MLX5_IPOOL_MTR], flow->meter);
11425 return rte_flow_error_set(error,
11427 RTE_FLOW_ERROR_TYPE_ACTION,
11430 "or invalid parameters");
11432 dev_flow->dv.actions[actions_n++] =
11433 fm->mfts->meter_action;
11434 action_flags |= MLX5_FLOW_ACTION_METER;
11436 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11437 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11440 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11442 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11443 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11446 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11448 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11449 sample_act_pos = actions_n;
11450 sample = (const struct rte_flow_action_sample *)
11453 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11454 /* put encap action into group if work with port id */
11455 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11456 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11457 sample_act->action_flags |=
11458 MLX5_FLOW_ACTION_ENCAP;
11460 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11461 if (flow_dv_convert_action_modify_field
11462 (dev, mhdr_res, actions, attr, error))
11464 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11466 case RTE_FLOW_ACTION_TYPE_END:
11467 actions_end = true;
11468 if (mhdr_res->actions_num) {
11469 /* create modify action if needed. */
11470 if (flow_dv_modify_hdr_resource_register
11471 (dev, mhdr_res, dev_flow, error))
11473 dev_flow->dv.actions[modify_action_position] =
11474 handle->dvh.modify_hdr->action;
11476 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11478 * Create one count action, to be used
11479 * by all sub-flows.
11481 if (!flow->counter) {
11483 flow_dv_translate_create_counter
11484 (dev, dev_flow, count,
11486 if (!flow->counter)
11487 return rte_flow_error_set
11489 RTE_FLOW_ERROR_TYPE_ACTION,
11490 NULL, "cannot create counter"
11493 dev_flow->dv.actions[actions_n] =
11494 (flow_dv_counter_get_by_idx(dev,
11495 flow->counter, NULL))->action;
11501 if (mhdr_res->actions_num &&
11502 modify_action_position == UINT32_MAX)
11503 modify_action_position = actions_n++;
11505 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11506 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11507 int item_type = items->type;
11509 if (!mlx5_flow_os_item_supported(item_type))
11510 return rte_flow_error_set(error, ENOTSUP,
11511 RTE_FLOW_ERROR_TYPE_ITEM,
11512 NULL, "item not supported");
11513 switch (item_type) {
11514 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11515 flow_dv_translate_item_port_id
11516 (dev, match_mask, match_value, items, attr);
11517 last_item = MLX5_FLOW_ITEM_PORT_ID;
11519 case RTE_FLOW_ITEM_TYPE_ETH:
11520 flow_dv_translate_item_eth(match_mask, match_value,
11522 dev_flow->dv.group);
11523 matcher.priority = action_flags &
11524 MLX5_FLOW_ACTION_DEFAULT_MISS &&
11525 !dev_flow->external ?
11526 MLX5_PRIORITY_MAP_L3 :
11527 MLX5_PRIORITY_MAP_L2;
11528 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11529 MLX5_FLOW_LAYER_OUTER_L2;
11531 case RTE_FLOW_ITEM_TYPE_VLAN:
11532 flow_dv_translate_item_vlan(dev_flow,
11533 match_mask, match_value,
11535 dev_flow->dv.group);
11536 matcher.priority = MLX5_PRIORITY_MAP_L2;
11537 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11538 MLX5_FLOW_LAYER_INNER_VLAN) :
11539 (MLX5_FLOW_LAYER_OUTER_L2 |
11540 MLX5_FLOW_LAYER_OUTER_VLAN);
11542 case RTE_FLOW_ITEM_TYPE_IPV4:
11543 mlx5_flow_tunnel_ip_check(items, next_protocol,
11544 &item_flags, &tunnel);
11545 flow_dv_translate_item_ipv4(match_mask, match_value,
11547 dev_flow->dv.group);
11548 matcher.priority = MLX5_PRIORITY_MAP_L3;
11549 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11550 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11551 if (items->mask != NULL &&
11552 ((const struct rte_flow_item_ipv4 *)
11553 items->mask)->hdr.next_proto_id) {
11555 ((const struct rte_flow_item_ipv4 *)
11556 (items->spec))->hdr.next_proto_id;
11558 ((const struct rte_flow_item_ipv4 *)
11559 (items->mask))->hdr.next_proto_id;
11561 /* Reset for inner layer. */
11562 next_protocol = 0xff;
11565 case RTE_FLOW_ITEM_TYPE_IPV6:
11566 mlx5_flow_tunnel_ip_check(items, next_protocol,
11567 &item_flags, &tunnel);
11568 flow_dv_translate_item_ipv6(match_mask, match_value,
11570 dev_flow->dv.group);
11571 matcher.priority = MLX5_PRIORITY_MAP_L3;
11572 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11573 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11574 if (items->mask != NULL &&
11575 ((const struct rte_flow_item_ipv6 *)
11576 items->mask)->hdr.proto) {
11578 ((const struct rte_flow_item_ipv6 *)
11579 items->spec)->hdr.proto;
11581 ((const struct rte_flow_item_ipv6 *)
11582 items->mask)->hdr.proto;
11584 /* Reset for inner layer. */
11585 next_protocol = 0xff;
11588 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11589 flow_dv_translate_item_ipv6_frag_ext(match_mask,
11592 last_item = tunnel ?
11593 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11594 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11595 if (items->mask != NULL &&
11596 ((const struct rte_flow_item_ipv6_frag_ext *)
11597 items->mask)->hdr.next_header) {
11599 ((const struct rte_flow_item_ipv6_frag_ext *)
11600 items->spec)->hdr.next_header;
11602 ((const struct rte_flow_item_ipv6_frag_ext *)
11603 items->mask)->hdr.next_header;
11605 /* Reset for inner layer. */
11606 next_protocol = 0xff;
11609 case RTE_FLOW_ITEM_TYPE_TCP:
11610 flow_dv_translate_item_tcp(match_mask, match_value,
11612 matcher.priority = MLX5_PRIORITY_MAP_L4;
11613 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11614 MLX5_FLOW_LAYER_OUTER_L4_TCP;
11616 case RTE_FLOW_ITEM_TYPE_UDP:
11617 flow_dv_translate_item_udp(match_mask, match_value,
11619 matcher.priority = MLX5_PRIORITY_MAP_L4;
11620 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11621 MLX5_FLOW_LAYER_OUTER_L4_UDP;
11623 case RTE_FLOW_ITEM_TYPE_GRE:
11624 flow_dv_translate_item_gre(match_mask, match_value,
11626 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11627 last_item = MLX5_FLOW_LAYER_GRE;
11629 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11630 flow_dv_translate_item_gre_key(match_mask,
11631 match_value, items);
11632 last_item = MLX5_FLOW_LAYER_GRE_KEY;
11634 case RTE_FLOW_ITEM_TYPE_NVGRE:
11635 flow_dv_translate_item_nvgre(match_mask, match_value,
11637 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11638 last_item = MLX5_FLOW_LAYER_GRE;
11640 case RTE_FLOW_ITEM_TYPE_VXLAN:
11641 flow_dv_translate_item_vxlan(match_mask, match_value,
11643 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11644 last_item = MLX5_FLOW_LAYER_VXLAN;
11646 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11647 flow_dv_translate_item_vxlan_gpe(match_mask,
11648 match_value, items,
11650 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11651 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11653 case RTE_FLOW_ITEM_TYPE_GENEVE:
11654 flow_dv_translate_item_geneve(match_mask, match_value,
11656 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11657 last_item = MLX5_FLOW_LAYER_GENEVE;
11659 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11660 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11664 return rte_flow_error_set(error, -ret,
11665 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11666 "cannot create GENEVE TLV option");
11667 flow->geneve_tlv_option = 1;
11668 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11670 case RTE_FLOW_ITEM_TYPE_MPLS:
11671 flow_dv_translate_item_mpls(match_mask, match_value,
11672 items, last_item, tunnel);
11673 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11674 last_item = MLX5_FLOW_LAYER_MPLS;
11676 case RTE_FLOW_ITEM_TYPE_MARK:
11677 flow_dv_translate_item_mark(dev, match_mask,
11678 match_value, items);
11679 last_item = MLX5_FLOW_ITEM_MARK;
11681 case RTE_FLOW_ITEM_TYPE_META:
11682 flow_dv_translate_item_meta(dev, match_mask,
11683 match_value, attr, items);
11684 last_item = MLX5_FLOW_ITEM_METADATA;
11686 case RTE_FLOW_ITEM_TYPE_ICMP:
11687 flow_dv_translate_item_icmp(match_mask, match_value,
11689 last_item = MLX5_FLOW_LAYER_ICMP;
11691 case RTE_FLOW_ITEM_TYPE_ICMP6:
11692 flow_dv_translate_item_icmp6(match_mask, match_value,
11694 last_item = MLX5_FLOW_LAYER_ICMP6;
11696 case RTE_FLOW_ITEM_TYPE_TAG:
11697 flow_dv_translate_item_tag(dev, match_mask,
11698 match_value, items);
11699 last_item = MLX5_FLOW_ITEM_TAG;
11701 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11702 flow_dv_translate_mlx5_item_tag(dev, match_mask,
11703 match_value, items);
11704 last_item = MLX5_FLOW_ITEM_TAG;
11706 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11707 flow_dv_translate_item_tx_queue(dev, match_mask,
11710 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11712 case RTE_FLOW_ITEM_TYPE_GTP:
11713 flow_dv_translate_item_gtp(match_mask, match_value,
11715 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11716 last_item = MLX5_FLOW_LAYER_GTP;
11718 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11719 ret = flow_dv_translate_item_gtp_psc(match_mask,
11723 return rte_flow_error_set(error, -ret,
11724 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11725 "cannot create GTP PSC item");
11726 last_item = MLX5_FLOW_LAYER_GTP_PSC;
11728 case RTE_FLOW_ITEM_TYPE_ECPRI:
11729 if (!mlx5_flex_parser_ecpri_exist(dev)) {
11730 /* Create it only the first time to be used. */
11731 ret = mlx5_flex_parser_ecpri_alloc(dev);
11733 return rte_flow_error_set
11735 RTE_FLOW_ERROR_TYPE_ITEM,
11737 "cannot create eCPRI parser");
11739 /* Adjust the length matcher and device flow value. */
11740 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11741 dev_flow->dv.value.size =
11742 MLX5_ST_SZ_BYTES(fte_match_param);
11743 flow_dv_translate_item_ecpri(dev, match_mask,
11744 match_value, items);
11745 /* No other protocol should follow eCPRI layer. */
11746 last_item = MLX5_FLOW_LAYER_ECPRI;
11751 item_flags |= last_item;
11754 * When E-Switch mode is enabled, we have two cases where we need to
11755 * set the source port manually.
11756 * The first one, is in case of Nic steering rule, and the second is
11757 * E-Switch rule where no port_id item was found. In both cases
11758 * the source port is set according the current port in use.
11760 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11761 (priv->representor || priv->master)) {
11762 if (flow_dv_translate_item_port_id(dev, match_mask,
11763 match_value, NULL, attr))
11766 #ifdef RTE_LIBRTE_MLX5_DEBUG
11767 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11768 dev_flow->dv.value.buf));
11771 * Layers may be already initialized from prefix flow if this dev_flow
11772 * is the suffix flow.
11774 handle->layers |= item_flags;
11775 if (action_flags & MLX5_FLOW_ACTION_RSS)
11776 flow_dv_hashfields_set(dev_flow, rss_desc);
11777 /* If has RSS action in the sample action, the Sample/Mirror resource
11778 * should be registered after the hash filed be update.
11780 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11781 ret = flow_dv_translate_action_sample(dev,
11790 ret = flow_dv_create_action_sample(dev,
11799 return rte_flow_error_set
11801 RTE_FLOW_ERROR_TYPE_ACTION,
11803 "cannot create sample action");
11804 if (num_of_dest > 1) {
11805 dev_flow->dv.actions[sample_act_pos] =
11806 dev_flow->dv.dest_array_res->action;
11808 dev_flow->dv.actions[sample_act_pos] =
11809 dev_flow->dv.sample_res->verbs_action;
11813 * For multiple destination (sample action with ratio=1), the encap
11814 * action and port id action will be combined into group action.
11815 * So need remove the original these actions in the flow and only
11816 * use the sample action instead of.
11818 if (num_of_dest > 1 &&
11819 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11821 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11823 for (i = 0; i < actions_n; i++) {
11824 if ((sample_act->dr_encap_action &&
11825 sample_act->dr_encap_action ==
11826 dev_flow->dv.actions[i]) ||
11827 (sample_act->dr_port_id_action &&
11828 sample_act->dr_port_id_action ==
11829 dev_flow->dv.actions[i]) ||
11830 (sample_act->dr_jump_action &&
11831 sample_act->dr_jump_action ==
11832 dev_flow->dv.actions[i]))
11834 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11836 memcpy((void *)dev_flow->dv.actions,
11837 (void *)temp_actions,
11838 tmp_actions_n * sizeof(void *));
11839 actions_n = tmp_actions_n;
11841 dev_flow->dv.actions_n = actions_n;
11842 dev_flow->act_flags = action_flags;
11843 /* Register matcher. */
11844 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11845 matcher.mask.size);
11846 matcher.priority = mlx5_get_matcher_priority(dev, attr,
11848 /* reserved field no needs to be set to 0 here. */
11849 tbl_key.domain = attr->transfer;
11850 tbl_key.direction = attr->egress;
11851 tbl_key.table_id = dev_flow->dv.group;
11852 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11853 tunnel, attr->group, error))
11859 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11862 * @param[in, out] action
11863 * Shred RSS action holding hash RX queue objects.
11864 * @param[in] hash_fields
11865 * Defines combination of packet fields to participate in RX hash.
11866 * @param[in] tunnel
11868 * @param[in] hrxq_idx
11869 * Hash RX queue index to set.
11872 * 0 on success, otherwise negative errno value.
11875 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11876 const uint64_t hash_fields,
11880 uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11882 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11883 case MLX5_RSS_HASH_IPV4:
11884 hrxqs[0] = hrxq_idx;
11886 case MLX5_RSS_HASH_IPV4_TCP:
11887 hrxqs[1] = hrxq_idx;
11889 case MLX5_RSS_HASH_IPV4_UDP:
11890 hrxqs[2] = hrxq_idx;
11892 case MLX5_RSS_HASH_IPV6:
11893 hrxqs[3] = hrxq_idx;
11895 case MLX5_RSS_HASH_IPV6_TCP:
11896 hrxqs[4] = hrxq_idx;
11898 case MLX5_RSS_HASH_IPV6_UDP:
11899 hrxqs[5] = hrxq_idx;
11901 case MLX5_RSS_HASH_NONE:
11902 hrxqs[6] = hrxq_idx;
11910 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11914 * Pointer to the Ethernet device structure.
11916 * Shared RSS action ID holding hash RX queue objects.
11917 * @param[in] hash_fields
11918 * Defines combination of packet fields to participate in RX hash.
11919 * @param[in] tunnel
11923 * Valid hash RX queue index, otherwise 0.
11926 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11927 const uint64_t hash_fields,
11930 struct mlx5_priv *priv = dev->data->dev_private;
11931 struct mlx5_shared_action_rss *shared_rss =
11932 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11933 const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11934 shared_rss->hrxq_tunnel;
11936 switch (hash_fields & ~IBV_RX_HASH_INNER) {
11937 case MLX5_RSS_HASH_IPV4:
11939 case MLX5_RSS_HASH_IPV4_TCP:
11941 case MLX5_RSS_HASH_IPV4_UDP:
11943 case MLX5_RSS_HASH_IPV6:
11945 case MLX5_RSS_HASH_IPV6_TCP:
11947 case MLX5_RSS_HASH_IPV6_UDP:
11949 case MLX5_RSS_HASH_NONE:
11957 * Apply the flow to the NIC, lock free,
11958 * (mutex should be acquired by caller).
11961 * Pointer to the Ethernet device structure.
11962 * @param[in, out] flow
11963 * Pointer to flow structure.
11964 * @param[out] error
11965 * Pointer to error structure.
11968 * 0 on success, a negative errno value otherwise and rte_errno is set.
11971 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11972 struct rte_flow_error *error)
11974 struct mlx5_flow_dv_workspace *dv;
11975 struct mlx5_flow_handle *dh;
11976 struct mlx5_flow_handle_dv *dv_h;
11977 struct mlx5_flow *dev_flow;
11978 struct mlx5_priv *priv = dev->data->dev_private;
11979 uint32_t handle_idx;
11983 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11984 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11987 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11988 dev_flow = &wks->flows[idx];
11989 dv = &dev_flow->dv;
11990 dh = dev_flow->handle;
11993 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11994 if (dv->transfer) {
11995 dv->actions[n++] = priv->sh->esw_drop_action;
11997 MLX5_ASSERT(priv->drop_queue.hrxq);
11999 priv->drop_queue.hrxq->action;
12001 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12002 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12003 struct mlx5_hrxq *hrxq;
12006 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12011 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12012 "cannot get hash queue");
12015 dh->rix_hrxq = hrxq_idx;
12016 dv->actions[n++] = hrxq->action;
12017 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12018 struct mlx5_hrxq *hrxq = NULL;
12021 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12022 rss_desc->shared_rss,
12023 dev_flow->hash_fields,
12025 MLX5_FLOW_LAYER_TUNNEL));
12027 hrxq = mlx5_ipool_get
12028 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12033 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12034 "cannot get hash queue");
12037 dh->rix_srss = rss_desc->shared_rss;
12038 dv->actions[n++] = hrxq->action;
12039 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12040 if (!priv->sh->default_miss_action) {
12043 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12044 "default miss action not be created.");
12047 dv->actions[n++] = priv->sh->default_miss_action;
12049 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12050 (void *)&dv->value, n,
12051 dv->actions, &dh->drv_flow);
12053 rte_flow_error_set(error, errno,
12054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12056 "hardware refuses to create flow");
12059 if (priv->vmwa_context &&
12060 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12062 * The rule contains the VLAN pattern.
12063 * For VF we are going to create VLAN
12064 * interface to make hypervisor set correct
12065 * e-Switch vport context.
12067 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12072 err = rte_errno; /* Save rte_errno before cleanup. */
12073 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12074 handle_idx, dh, next) {
12075 /* hrxq is union, don't clear it if the flag is not set. */
12076 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12077 mlx5_hrxq_release(dev, dh->rix_hrxq);
12079 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12082 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12083 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12085 rte_errno = err; /* Restore rte_errno. */
12090 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12091 struct mlx5_cache_entry *entry)
12093 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12096 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12101 * Release the flow matcher.
12104 * Pointer to Ethernet device.
12106 * Index to port ID action resource.
12109 * 1 while a reference on it exists, 0 when freed.
12112 flow_dv_matcher_release(struct rte_eth_dev *dev,
12113 struct mlx5_flow_handle *handle)
12115 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12116 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12117 typeof(*tbl), tbl);
12120 MLX5_ASSERT(matcher->matcher_object);
12121 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12122 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12127 * Release encap_decap resource.
12130 * Pointer to the hash list.
12132 * Pointer to exist resource entry object.
12135 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12136 struct mlx5_hlist_entry *entry)
12138 struct mlx5_dev_ctx_shared *sh = list->ctx;
12139 struct mlx5_flow_dv_encap_decap_resource *res =
12140 container_of(entry, typeof(*res), entry);
12142 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12143 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12147 * Release an encap/decap resource.
12150 * Pointer to Ethernet device.
12151 * @param encap_decap_idx
12152 * Index of encap decap resource.
12155 * 1 while a reference on it exists, 0 when freed.
12158 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12159 uint32_t encap_decap_idx)
12161 struct mlx5_priv *priv = dev->data->dev_private;
12162 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12164 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12166 if (!cache_resource)
12168 MLX5_ASSERT(cache_resource->action);
12169 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12170 &cache_resource->entry);
12174 * Release an jump to table action resource.
12177 * Pointer to Ethernet device.
12179 * Index to the jump action resource.
12182 * 1 while a reference on it exists, 0 when freed.
12185 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12188 struct mlx5_priv *priv = dev->data->dev_private;
12189 struct mlx5_flow_tbl_data_entry *tbl_data;
12191 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12195 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12199 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12200 struct mlx5_hlist_entry *entry)
12202 struct mlx5_flow_dv_modify_hdr_resource *res =
12203 container_of(entry, typeof(*res), entry);
12205 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12210 * Release a modify-header resource.
12213 * Pointer to Ethernet device.
12215 * Pointer to mlx5_flow_handle.
12218 * 1 while a reference on it exists, 0 when freed.
12221 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12222 struct mlx5_flow_handle *handle)
12224 struct mlx5_priv *priv = dev->data->dev_private;
12225 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12227 MLX5_ASSERT(entry->action);
12228 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12232 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12233 struct mlx5_cache_entry *entry)
12235 struct mlx5_dev_ctx_shared *sh = list->ctx;
12236 struct mlx5_flow_dv_port_id_action_resource *cache =
12237 container_of(entry, typeof(*cache), entry);
12239 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12240 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12244 * Release port ID action resource.
12247 * Pointer to Ethernet device.
12249 * Pointer to mlx5_flow_handle.
12252 * 1 while a reference on it exists, 0 when freed.
12255 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12258 struct mlx5_priv *priv = dev->data->dev_private;
12259 struct mlx5_flow_dv_port_id_action_resource *cache;
12261 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12264 MLX5_ASSERT(cache->action);
12265 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12270 * Release shared RSS action resource.
12273 * Pointer to Ethernet device.
12275 * Shared RSS action index.
12278 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12280 struct mlx5_priv *priv = dev->data->dev_private;
12281 struct mlx5_shared_action_rss *shared_rss;
12283 shared_rss = mlx5_ipool_get
12284 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12285 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12289 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12290 struct mlx5_cache_entry *entry)
12292 struct mlx5_dev_ctx_shared *sh = list->ctx;
12293 struct mlx5_flow_dv_push_vlan_action_resource *cache =
12294 container_of(entry, typeof(*cache), entry);
12296 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12297 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12301 * Release push vlan action resource.
12304 * Pointer to Ethernet device.
12306 * Pointer to mlx5_flow_handle.
12309 * 1 while a reference on it exists, 0 when freed.
12312 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12313 struct mlx5_flow_handle *handle)
12315 struct mlx5_priv *priv = dev->data->dev_private;
12316 struct mlx5_flow_dv_push_vlan_action_resource *cache;
12317 uint32_t idx = handle->dvh.rix_push_vlan;
12319 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12322 MLX5_ASSERT(cache->action);
12323 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12328 * Release the fate resource.
12331 * Pointer to Ethernet device.
12333 * Pointer to mlx5_flow_handle.
12336 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12337 struct mlx5_flow_handle *handle)
12339 if (!handle->rix_fate)
12341 switch (handle->fate_action) {
12342 case MLX5_FLOW_FATE_QUEUE:
12343 mlx5_hrxq_release(dev, handle->rix_hrxq);
12345 case MLX5_FLOW_FATE_JUMP:
12346 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12348 case MLX5_FLOW_FATE_PORT_ID:
12349 flow_dv_port_id_action_resource_release(dev,
12350 handle->rix_port_id_action);
12353 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12356 handle->rix_fate = 0;
12360 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12361 struct mlx5_cache_entry *entry)
12363 struct mlx5_flow_dv_sample_resource *cache_resource =
12364 container_of(entry, typeof(*cache_resource), entry);
12365 struct rte_eth_dev *dev = cache_resource->dev;
12366 struct mlx5_priv *priv = dev->data->dev_private;
12368 if (cache_resource->verbs_action)
12369 claim_zero(mlx5_flow_os_destroy_flow_action
12370 (cache_resource->verbs_action));
12371 if (cache_resource->normal_path_tbl)
12372 flow_dv_tbl_resource_release(MLX5_SH(dev),
12373 cache_resource->normal_path_tbl);
12374 flow_dv_sample_sub_actions_release(dev,
12375 &cache_resource->sample_idx);
12376 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12377 cache_resource->idx);
12378 DRV_LOG(DEBUG, "sample resource %p: removed",
12379 (void *)cache_resource);
12383 * Release an sample resource.
12386 * Pointer to Ethernet device.
12388 * Pointer to mlx5_flow_handle.
12391 * 1 while a reference on it exists, 0 when freed.
12394 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12395 struct mlx5_flow_handle *handle)
12397 struct mlx5_priv *priv = dev->data->dev_private;
12398 struct mlx5_flow_dv_sample_resource *cache_resource;
12400 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12401 handle->dvh.rix_sample);
12402 if (!cache_resource)
12404 MLX5_ASSERT(cache_resource->verbs_action);
12405 return mlx5_cache_unregister(&priv->sh->sample_action_list,
12406 &cache_resource->entry);
12410 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12411 struct mlx5_cache_entry *entry)
12413 struct mlx5_flow_dv_dest_array_resource *cache_resource =
12414 container_of(entry, typeof(*cache_resource), entry);
12415 struct rte_eth_dev *dev = cache_resource->dev;
12416 struct mlx5_priv *priv = dev->data->dev_private;
12419 MLX5_ASSERT(cache_resource->action);
12420 if (cache_resource->action)
12421 claim_zero(mlx5_flow_os_destroy_flow_action
12422 (cache_resource->action));
12423 for (; i < cache_resource->num_of_dest; i++)
12424 flow_dv_sample_sub_actions_release(dev,
12425 &cache_resource->sample_idx[i]);
12426 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12427 cache_resource->idx);
12428 DRV_LOG(DEBUG, "destination array resource %p: removed",
12429 (void *)cache_resource);
12433 * Release an destination array resource.
12436 * Pointer to Ethernet device.
12438 * Pointer to mlx5_flow_handle.
12441 * 1 while a reference on it exists, 0 when freed.
12444 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12445 struct mlx5_flow_handle *handle)
12447 struct mlx5_priv *priv = dev->data->dev_private;
12448 struct mlx5_flow_dv_dest_array_resource *cache;
12450 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12451 handle->dvh.rix_dest_array);
12454 MLX5_ASSERT(cache->action);
12455 return mlx5_cache_unregister(&priv->sh->dest_array_list,
12460 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12462 struct mlx5_priv *priv = dev->data->dev_private;
12463 struct mlx5_dev_ctx_shared *sh = priv->sh;
12464 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12465 sh->geneve_tlv_option_resource;
12466 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12467 if (geneve_opt_resource) {
12468 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12469 __ATOMIC_RELAXED))) {
12470 claim_zero(mlx5_devx_cmd_destroy
12471 (geneve_opt_resource->obj));
12472 mlx5_free(sh->geneve_tlv_option_resource);
12473 sh->geneve_tlv_option_resource = NULL;
12476 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12480 * Remove the flow from the NIC but keeps it in memory.
12481 * Lock free, (mutex should be acquired by caller).
12484 * Pointer to Ethernet device.
12485 * @param[in, out] flow
12486 * Pointer to flow structure.
12489 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12491 struct mlx5_flow_handle *dh;
12492 uint32_t handle_idx;
12493 struct mlx5_priv *priv = dev->data->dev_private;
12497 handle_idx = flow->dev_handles;
12498 while (handle_idx) {
12499 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12503 if (dh->drv_flow) {
12504 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12505 dh->drv_flow = NULL;
12507 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12508 flow_dv_fate_resource_release(dev, dh);
12509 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12510 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12511 handle_idx = dh->next.next;
12516 * Remove the flow from the NIC and the memory.
12517 * Lock free, (mutex should be acquired by caller).
12520 * Pointer to the Ethernet device structure.
12521 * @param[in, out] flow
12522 * Pointer to flow structure.
12525 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12527 struct mlx5_flow_handle *dev_handle;
12528 struct mlx5_priv *priv = dev->data->dev_private;
12533 flow_dv_remove(dev, flow);
12534 if (flow->counter) {
12535 flow_dv_counter_free(dev, flow->counter);
12539 struct mlx5_flow_meter *fm;
12541 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12544 mlx5_flow_meter_detach(fm);
12548 flow_dv_aso_age_release(dev, flow->age);
12549 if (flow->geneve_tlv_option) {
12550 flow_dv_geneve_tlv_option_resource_release(dev);
12551 flow->geneve_tlv_option = 0;
12553 while (flow->dev_handles) {
12554 uint32_t tmp_idx = flow->dev_handles;
12556 dev_handle = mlx5_ipool_get(priv->sh->ipool
12557 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12560 flow->dev_handles = dev_handle->next.next;
12561 if (dev_handle->dvh.matcher)
12562 flow_dv_matcher_release(dev, dev_handle);
12563 if (dev_handle->dvh.rix_sample)
12564 flow_dv_sample_resource_release(dev, dev_handle);
12565 if (dev_handle->dvh.rix_dest_array)
12566 flow_dv_dest_array_resource_release(dev, dev_handle);
12567 if (dev_handle->dvh.rix_encap_decap)
12568 flow_dv_encap_decap_resource_release(dev,
12569 dev_handle->dvh.rix_encap_decap);
12570 if (dev_handle->dvh.modify_hdr)
12571 flow_dv_modify_hdr_resource_release(dev, dev_handle);
12572 if (dev_handle->dvh.rix_push_vlan)
12573 flow_dv_push_vlan_action_resource_release(dev,
12575 if (dev_handle->dvh.rix_tag)
12576 flow_dv_tag_release(dev,
12577 dev_handle->dvh.rix_tag);
12578 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12579 flow_dv_fate_resource_release(dev, dev_handle);
12581 srss = dev_handle->rix_srss;
12582 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12586 flow_dv_shared_rss_action_release(dev, srss);
12590 * Release array of hash RX queue objects.
12594 * Pointer to the Ethernet device structure.
12595 * @param[in, out] hrxqs
12596 * Array of hash RX queue objects.
12599 * Total number of references to hash RX queue objects in *hrxqs* array
12600 * after this operation.
12603 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12604 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12609 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12610 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12620 * Release all hash RX queue objects representing shared RSS action.
12623 * Pointer to the Ethernet device structure.
12624 * @param[in, out] action
12625 * Shared RSS action to remove hash RX queue objects from.
12628 * Total number of references to hash RX queue objects stored in *action*
12629 * after this operation.
12630 * Expected to be 0 if no external references held.
12633 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12634 struct mlx5_shared_action_rss *shared_rss)
12636 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12637 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12641 * Setup shared RSS action.
12642 * Prepare set of hash RX queue objects sufficient to handle all valid
12643 * hash_fields combinations (see enum ibv_rx_hash_fields).
12646 * Pointer to the Ethernet device structure.
12647 * @param[in] action_idx
12648 * Shared RSS action ipool index.
12649 * @param[in, out] action
12650 * Partially initialized shared RSS action.
12651 * @param[out] error
12652 * Perform verbose error reporting if not NULL. Initialized in case of
12656 * 0 on success, otherwise negative errno value.
12659 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12660 uint32_t action_idx,
12661 struct mlx5_shared_action_rss *shared_rss,
12662 struct rte_flow_error *error)
12664 struct mlx5_flow_rss_desc rss_desc = { 0 };
12668 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12669 return rte_flow_error_set(error, rte_errno,
12670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12671 "cannot setup indirection table");
12673 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12674 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12675 rss_desc.const_q = shared_rss->origin.queue;
12676 rss_desc.queue_num = shared_rss->origin.queue_num;
12677 /* Set non-zero value to indicate a shared RSS. */
12678 rss_desc.shared_rss = action_idx;
12679 rss_desc.ind_tbl = shared_rss->ind_tbl;
12680 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12682 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12685 for (tunnel = 0; tunnel < 2; tunnel++) {
12686 rss_desc.tunnel = tunnel;
12687 rss_desc.hash_fields = hash_fields;
12688 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12692 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12693 "cannot get hash queue");
12694 goto error_hrxq_new;
12696 err = __flow_dv_action_rss_hrxq_set
12697 (shared_rss, hash_fields, tunnel, hrxq_idx);
12704 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12705 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12706 shared_rss->ind_tbl = NULL;
12712 * Create shared RSS action.
12715 * Pointer to the Ethernet device structure.
12717 * Shared action configuration.
12719 * RSS action specification used to create shared action.
12720 * @param[out] error
12721 * Perform verbose error reporting if not NULL. Initialized in case of
12725 * A valid shared action ID in case of success, 0 otherwise and
12726 * rte_errno is set.
12729 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12730 const struct rte_flow_shared_action_conf *conf,
12731 const struct rte_flow_action_rss *rss,
12732 struct rte_flow_error *error)
12734 struct mlx5_priv *priv = dev->data->dev_private;
12735 struct mlx5_shared_action_rss *shared_rss = NULL;
12736 void *queue = NULL;
12737 struct rte_flow_action_rss *origin;
12738 const uint8_t *rss_key;
12739 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12742 RTE_SET_USED(conf);
12743 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12745 shared_rss = mlx5_ipool_zmalloc
12746 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12747 if (!shared_rss || !queue) {
12748 rte_flow_error_set(error, ENOMEM,
12749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12750 "cannot allocate resource memory");
12751 goto error_rss_init;
12753 if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12754 rte_flow_error_set(error, E2BIG,
12755 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12756 "rss action number out of range");
12757 goto error_rss_init;
12759 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12760 sizeof(*shared_rss->ind_tbl),
12762 if (!shared_rss->ind_tbl) {
12763 rte_flow_error_set(error, ENOMEM,
12764 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12765 "cannot allocate resource memory");
12766 goto error_rss_init;
12768 memcpy(queue, rss->queue, queue_size);
12769 shared_rss->ind_tbl->queues = queue;
12770 shared_rss->ind_tbl->queues_n = rss->queue_num;
12771 origin = &shared_rss->origin;
12772 origin->func = rss->func;
12773 origin->level = rss->level;
12774 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12775 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12776 /* NULL RSS key indicates default RSS key. */
12777 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12778 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12779 origin->key = &shared_rss->key[0];
12780 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12781 origin->queue = queue;
12782 origin->queue_num = rss->queue_num;
12783 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12784 goto error_rss_init;
12785 rte_spinlock_init(&shared_rss->action_rss_sl);
12786 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12787 rte_spinlock_lock(&priv->shared_act_sl);
12788 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12789 &priv->rss_shared_actions, idx, shared_rss, next);
12790 rte_spinlock_unlock(&priv->shared_act_sl);
12794 if (shared_rss->ind_tbl)
12795 mlx5_free(shared_rss->ind_tbl);
12796 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12805 * Destroy the shared RSS action.
12806 * Release related hash RX queue objects.
12809 * Pointer to the Ethernet device structure.
12811 * The shared RSS action object ID to be removed.
12812 * @param[out] error
12813 * Perform verbose error reporting if not NULL. Initialized in case of
12817 * 0 on success, otherwise negative errno value.
12820 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12821 struct rte_flow_error *error)
12823 struct mlx5_priv *priv = dev->data->dev_private;
12824 struct mlx5_shared_action_rss *shared_rss =
12825 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12826 uint32_t old_refcnt = 1;
12828 uint16_t *queue = NULL;
12831 return rte_flow_error_set(error, EINVAL,
12832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12833 "invalid shared action");
12834 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12836 return rte_flow_error_set(error, EBUSY,
12837 RTE_FLOW_ERROR_TYPE_ACTION,
12839 "shared rss hrxq has references");
12840 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12841 0, 0, __ATOMIC_ACQUIRE,
12843 return rte_flow_error_set(error, EBUSY,
12844 RTE_FLOW_ERROR_TYPE_ACTION,
12846 "shared rss has references");
12847 queue = shared_rss->ind_tbl->queues;
12848 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12850 return rte_flow_error_set(error, EBUSY,
12851 RTE_FLOW_ERROR_TYPE_ACTION,
12853 "shared rss indirection table has"
12856 rte_spinlock_lock(&priv->shared_act_sl);
12857 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12858 &priv->rss_shared_actions, idx, shared_rss, next);
12859 rte_spinlock_unlock(&priv->shared_act_sl);
12860 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12866 * Create shared action, lock free,
12867 * (mutex should be acquired by caller).
12868 * Dispatcher for action type specific call.
12871 * Pointer to the Ethernet device structure.
12873 * Shared action configuration.
12874 * @param[in] action
12875 * Action specification used to create shared action.
12876 * @param[out] error
12877 * Perform verbose error reporting if not NULL. Initialized in case of
12881 * A valid shared action handle in case of success, NULL otherwise and
12882 * rte_errno is set.
12884 static struct rte_flow_shared_action *
12885 flow_dv_action_create(struct rte_eth_dev *dev,
12886 const struct rte_flow_shared_action_conf *conf,
12887 const struct rte_flow_action *action,
12888 struct rte_flow_error *err)
12893 switch (action->type) {
12894 case RTE_FLOW_ACTION_TYPE_RSS:
12895 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12896 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12897 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12899 case RTE_FLOW_ACTION_TYPE_AGE:
12900 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12901 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12902 MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12904 struct mlx5_aso_age_action *aso_age =
12905 flow_aso_age_get_by_idx(dev, ret);
12907 if (!aso_age->age_params.context)
12908 aso_age->age_params.context =
12909 (void *)(uintptr_t)idx;
12913 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12914 NULL, "action type not supported");
12917 return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12921 * Destroy the shared action.
12922 * Release action related resources on the NIC and the memory.
12923 * Lock free, (mutex should be acquired by caller).
12924 * Dispatcher for action type specific call.
12927 * Pointer to the Ethernet device structure.
12928 * @param[in] action
12929 * The shared action object to be removed.
12930 * @param[out] error
12931 * Perform verbose error reporting if not NULL. Initialized in case of
12935 * 0 on success, otherwise negative errno value.
12938 flow_dv_action_destroy(struct rte_eth_dev *dev,
12939 struct rte_flow_shared_action *action,
12940 struct rte_flow_error *error)
12942 uint32_t act_idx = (uint32_t)(uintptr_t)action;
12943 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12944 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12948 case MLX5_SHARED_ACTION_TYPE_RSS:
12949 return __flow_dv_action_rss_release(dev, idx, error);
12950 case MLX5_SHARED_ACTION_TYPE_AGE:
12951 ret = flow_dv_aso_age_release(dev, idx);
12954 * In this case, the last flow has a reference will
12955 * actually release the age action.
12957 DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12958 " released with references %d.", idx, ret);
12961 return rte_flow_error_set(error, ENOTSUP,
12962 RTE_FLOW_ERROR_TYPE_ACTION,
12964 "action type not supported");
12969 * Updates in place shared RSS action configuration.
12972 * Pointer to the Ethernet device structure.
12974 * The shared RSS action object ID to be updated.
12975 * @param[in] action_conf
12976 * RSS action specification used to modify *shared_rss*.
12977 * @param[out] error
12978 * Perform verbose error reporting if not NULL. Initialized in case of
12982 * 0 on success, otherwise negative errno value.
12983 * @note: currently only support update of RSS queues.
12986 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12987 const struct rte_flow_action_rss *action_conf,
12988 struct rte_flow_error *error)
12990 struct mlx5_priv *priv = dev->data->dev_private;
12991 struct mlx5_shared_action_rss *shared_rss =
12992 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12994 void *queue = NULL;
12995 uint16_t *queue_old = NULL;
12996 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12999 return rte_flow_error_set(error, EINVAL,
13000 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13001 "invalid shared action to update");
13002 if (priv->obj_ops.ind_table_modify == NULL)
13003 return rte_flow_error_set(error, ENOTSUP,
13004 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13005 "cannot modify indirection table");
13006 queue = mlx5_malloc(MLX5_MEM_ZERO,
13007 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13010 return rte_flow_error_set(error, ENOMEM,
13011 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13013 "cannot allocate resource memory");
13014 memcpy(queue, action_conf->queue, queue_size);
13015 MLX5_ASSERT(shared_rss->ind_tbl);
13016 rte_spinlock_lock(&shared_rss->action_rss_sl);
13017 queue_old = shared_rss->ind_tbl->queues;
13018 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13019 queue, action_conf->queue_num, true);
13022 ret = rte_flow_error_set(error, rte_errno,
13023 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13024 "cannot update indirection table");
13026 mlx5_free(queue_old);
13027 shared_rss->origin.queue = queue;
13028 shared_rss->origin.queue_num = action_conf->queue_num;
13030 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13035 * Updates in place shared action configuration, lock free,
13036 * (mutex should be acquired by caller).
13039 * Pointer to the Ethernet device structure.
13040 * @param[in] action
13041 * The shared action object to be updated.
13042 * @param[in] action_conf
13043 * Action specification used to modify *action*.
13044 * *action_conf* should be of type correlating with type of the *action*,
13045 * otherwise considered as invalid.
13046 * @param[out] error
13047 * Perform verbose error reporting if not NULL. Initialized in case of
13051 * 0 on success, otherwise negative errno value.
13054 flow_dv_action_update(struct rte_eth_dev *dev,
13055 struct rte_flow_shared_action *action,
13056 const void *action_conf,
13057 struct rte_flow_error *err)
13059 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13060 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13061 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13064 case MLX5_SHARED_ACTION_TYPE_RSS:
13065 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13067 return rte_flow_error_set(err, ENOTSUP,
13068 RTE_FLOW_ERROR_TYPE_ACTION,
13070 "action type update not supported");
13075 flow_dv_action_query(struct rte_eth_dev *dev,
13076 const struct rte_flow_shared_action *action, void *data,
13077 struct rte_flow_error *error)
13079 struct mlx5_age_param *age_param;
13080 struct rte_flow_query_age *resp;
13081 uint32_t act_idx = (uint32_t)(uintptr_t)action;
13082 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13083 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13086 case MLX5_SHARED_ACTION_TYPE_AGE:
13087 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13089 resp->aged = __atomic_load_n(&age_param->state,
13090 __ATOMIC_RELAXED) == AGE_TMOUT ?
13092 resp->sec_since_last_hit_valid = !resp->aged;
13093 if (resp->sec_since_last_hit_valid)
13094 resp->sec_since_last_hit = __atomic_load_n
13095 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13098 return rte_flow_error_set(error, ENOTSUP,
13099 RTE_FLOW_ERROR_TYPE_ACTION,
13101 "action type query not supported");
13106 * Query a dv flow rule for its statistics via devx.
13109 * Pointer to Ethernet device.
13111 * Pointer to the sub flow.
13113 * data retrieved by the query.
13114 * @param[out] error
13115 * Perform verbose error reporting if not NULL.
13118 * 0 on success, a negative errno value otherwise and rte_errno is set.
13121 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13122 void *data, struct rte_flow_error *error)
13124 struct mlx5_priv *priv = dev->data->dev_private;
13125 struct rte_flow_query_count *qc = data;
13127 if (!priv->config.devx)
13128 return rte_flow_error_set(error, ENOTSUP,
13129 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13131 "counters are not supported");
13132 if (flow->counter) {
13133 uint64_t pkts, bytes;
13134 struct mlx5_flow_counter *cnt;
13136 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13138 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13142 return rte_flow_error_set(error, -err,
13143 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13144 NULL, "cannot read counters");
13147 qc->hits = pkts - cnt->hits;
13148 qc->bytes = bytes - cnt->bytes;
13151 cnt->bytes = bytes;
13155 return rte_flow_error_set(error, EINVAL,
13156 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13158 "counters are not available");
13162 * Query a flow rule AGE action for aging information.
13165 * Pointer to Ethernet device.
13167 * Pointer to the sub flow.
13169 * data retrieved by the query.
13170 * @param[out] error
13171 * Perform verbose error reporting if not NULL.
13174 * 0 on success, a negative errno value otherwise and rte_errno is set.
13177 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13178 void *data, struct rte_flow_error *error)
13180 struct rte_flow_query_age *resp = data;
13181 struct mlx5_age_param *age_param;
13184 struct mlx5_aso_age_action *act =
13185 flow_aso_age_get_by_idx(dev, flow->age);
13187 age_param = &act->age_params;
13188 } else if (flow->counter) {
13189 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13191 if (!age_param || !age_param->timeout)
13192 return rte_flow_error_set
13194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13195 NULL, "cannot read age data");
13197 return rte_flow_error_set(error, EINVAL,
13198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13199 NULL, "age data not available");
13201 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13203 resp->sec_since_last_hit_valid = !resp->aged;
13204 if (resp->sec_since_last_hit_valid)
13205 resp->sec_since_last_hit = __atomic_load_n
13206 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13213 * @see rte_flow_query()
13214 * @see rte_flow_ops
13217 flow_dv_query(struct rte_eth_dev *dev,
13218 struct rte_flow *flow __rte_unused,
13219 const struct rte_flow_action *actions __rte_unused,
13220 void *data __rte_unused,
13221 struct rte_flow_error *error __rte_unused)
13225 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13226 switch (actions->type) {
13227 case RTE_FLOW_ACTION_TYPE_VOID:
13229 case RTE_FLOW_ACTION_TYPE_COUNT:
13230 ret = flow_dv_query_count(dev, flow, data, error);
13232 case RTE_FLOW_ACTION_TYPE_AGE:
13233 ret = flow_dv_query_age(dev, flow, data, error);
13236 return rte_flow_error_set(error, ENOTSUP,
13237 RTE_FLOW_ERROR_TYPE_ACTION,
13239 "action not supported");
13246 * Destroy the meter table set.
13247 * Lock free, (mutex should be acquired by caller).
13250 * Pointer to Ethernet device.
13252 * Pointer to the meter table set.
13258 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13259 struct mlx5_meter_domains_infos *tbl)
13261 struct mlx5_priv *priv = dev->data->dev_private;
13262 struct mlx5_meter_domains_infos *mtd =
13263 (struct mlx5_meter_domains_infos *)tbl;
13265 if (!mtd || !priv->config.dv_flow_en)
13267 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13268 claim_zero(mlx5_flow_os_destroy_flow
13269 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13270 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13271 claim_zero(mlx5_flow_os_destroy_flow
13272 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13273 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13274 claim_zero(mlx5_flow_os_destroy_flow
13275 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13276 if (mtd->egress.color_matcher)
13277 claim_zero(mlx5_flow_os_destroy_flow_matcher
13278 (mtd->egress.color_matcher));
13279 if (mtd->egress.any_matcher)
13280 claim_zero(mlx5_flow_os_destroy_flow_matcher
13281 (mtd->egress.any_matcher));
13282 if (mtd->egress.tbl)
13283 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13284 if (mtd->egress.sfx_tbl)
13285 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13286 if (mtd->ingress.color_matcher)
13287 claim_zero(mlx5_flow_os_destroy_flow_matcher
13288 (mtd->ingress.color_matcher));
13289 if (mtd->ingress.any_matcher)
13290 claim_zero(mlx5_flow_os_destroy_flow_matcher
13291 (mtd->ingress.any_matcher));
13292 if (mtd->ingress.tbl)
13293 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13294 if (mtd->ingress.sfx_tbl)
13295 flow_dv_tbl_resource_release(MLX5_SH(dev),
13296 mtd->ingress.sfx_tbl);
13297 if (mtd->transfer.color_matcher)
13298 claim_zero(mlx5_flow_os_destroy_flow_matcher
13299 (mtd->transfer.color_matcher));
13300 if (mtd->transfer.any_matcher)
13301 claim_zero(mlx5_flow_os_destroy_flow_matcher
13302 (mtd->transfer.any_matcher));
13303 if (mtd->transfer.tbl)
13304 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13305 if (mtd->transfer.sfx_tbl)
13306 flow_dv_tbl_resource_release(MLX5_SH(dev),
13307 mtd->transfer.sfx_tbl);
13308 if (mtd->drop_actn)
13309 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13314 /* Number of meter flow actions, count and jump or count and drop. */
13315 #define METER_ACTIONS 2
13318 * Create specify domain meter table and suffix table.
13321 * Pointer to Ethernet device.
13322 * @param[in,out] mtb
13323 * Pointer to DV meter table set.
13324 * @param[in] egress
13326 * @param[in] transfer
13328 * @param[in] color_reg_c_idx
13329 * Reg C index for color match.
13332 * 0 on success, -1 otherwise and rte_errno is set.
13335 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13336 struct mlx5_meter_domains_infos *mtb,
13337 uint8_t egress, uint8_t transfer,
13338 uint32_t color_reg_c_idx)
13340 struct mlx5_priv *priv = dev->data->dev_private;
13341 struct mlx5_dev_ctx_shared *sh = priv->sh;
13342 struct mlx5_flow_dv_match_params mask = {
13343 .size = sizeof(mask.buf),
13345 struct mlx5_flow_dv_match_params value = {
13346 .size = sizeof(value.buf),
13348 struct mlx5dv_flow_matcher_attr dv_attr = {
13349 .type = IBV_FLOW_ATTR_NORMAL,
13351 .match_criteria_enable = 0,
13352 .match_mask = (void *)&mask,
13354 void *actions[METER_ACTIONS];
13355 struct mlx5_meter_domain_info *dtb;
13356 struct rte_flow_error error;
13361 dtb = &mtb->transfer;
13363 dtb = &mtb->egress;
13365 dtb = &mtb->ingress;
13366 /* Create the meter table with METER level. */
13367 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13368 egress, transfer, false, NULL, 0,
13371 DRV_LOG(ERR, "Failed to create meter policer table.");
13374 /* Create the meter suffix table with SUFFIX level. */
13375 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13376 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13377 egress, transfer, false, NULL, 0,
13379 if (!dtb->sfx_tbl) {
13380 DRV_LOG(ERR, "Failed to create meter suffix table.");
13383 /* Create matchers, Any and Color. */
13384 dv_attr.priority = 3;
13385 dv_attr.match_criteria_enable = 0;
13386 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13387 &dtb->any_matcher);
13389 DRV_LOG(ERR, "Failed to create meter"
13390 " policer default matcher.");
13393 dv_attr.priority = 0;
13394 dv_attr.match_criteria_enable =
13395 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13396 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13397 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13398 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13399 &dtb->color_matcher);
13401 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13404 if (mtb->count_actns[RTE_MTR_DROPPED])
13405 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13406 actions[i++] = mtb->drop_actn;
13407 /* Default rule: lowest priority, match any, actions: drop. */
13408 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13410 &dtb->policer_rules[RTE_MTR_DROPPED]);
13412 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13421 * Create the needed meter and suffix tables.
13422 * Lock free, (mutex should be acquired by caller).
13425 * Pointer to Ethernet device.
13427 * Pointer to the flow meter.
13430 * Pointer to table set on success, NULL otherwise and rte_errno is set.
13432 static struct mlx5_meter_domains_infos *
13433 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13434 const struct mlx5_flow_meter *fm)
13436 struct mlx5_priv *priv = dev->data->dev_private;
13437 struct mlx5_meter_domains_infos *mtb;
13441 if (!priv->mtr_en) {
13442 rte_errno = ENOTSUP;
13445 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13447 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13450 /* Create meter count actions */
13451 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13452 struct mlx5_flow_counter *cnt;
13453 if (!fm->policer_stats.cnt[i])
13455 cnt = flow_dv_counter_get_by_idx(dev,
13456 fm->policer_stats.cnt[i], NULL);
13457 mtb->count_actns[i] = cnt->action;
13459 /* Create drop action. */
13460 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13462 DRV_LOG(ERR, "Failed to create drop action.");
13465 /* Egress meter table. */
13466 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13468 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13471 /* Ingress meter table. */
13472 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13474 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13477 /* FDB meter table. */
13478 if (priv->config.dv_esw_en) {
13479 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13480 priv->mtr_color_reg);
13482 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13488 flow_dv_destroy_mtr_tbl(dev, mtb);
13493 * Destroy domain policer rule.
13496 * Pointer to domain table.
13499 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13503 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13504 if (dt->policer_rules[i]) {
13505 claim_zero(mlx5_flow_os_destroy_flow
13506 (dt->policer_rules[i]));
13507 dt->policer_rules[i] = NULL;
13510 if (dt->jump_actn) {
13511 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13512 dt->jump_actn = NULL;
13517 * Destroy policer rules.
13520 * Pointer to Ethernet device.
13522 * Pointer to flow meter structure.
13524 * Pointer to flow attributes.
13530 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13531 const struct mlx5_flow_meter *fm,
13532 const struct rte_flow_attr *attr)
13534 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13539 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13541 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13542 if (attr->transfer)
13543 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13548 * Create specify domain meter policer rule.
13551 * Pointer to flow meter structure.
13553 * Pointer to DV meter table set.
13554 * @param[in] mtr_reg_c
13555 * Color match REG_C.
13558 * 0 on success, -1 otherwise.
13561 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13562 struct mlx5_meter_domain_info *dtb,
13565 struct mlx5_flow_dv_match_params matcher = {
13566 .size = sizeof(matcher.buf),
13568 struct mlx5_flow_dv_match_params value = {
13569 .size = sizeof(value.buf),
13571 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13572 void *actions[METER_ACTIONS];
13576 /* Create jump action. */
13577 if (!dtb->jump_actn)
13578 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13579 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13581 DRV_LOG(ERR, "Failed to create policer jump action.");
13584 for (i = 0; i < RTE_MTR_DROPPED; i++) {
13587 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13588 rte_col_2_mlx5_col(i), UINT8_MAX);
13589 if (mtb->count_actns[i])
13590 actions[j++] = mtb->count_actns[i];
13591 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13592 actions[j++] = mtb->drop_actn;
13594 actions[j++] = dtb->jump_actn;
13595 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13596 (void *)&value, j, actions,
13597 &dtb->policer_rules[i]);
13599 DRV_LOG(ERR, "Failed to create policer rule.");
13610 * Create policer rules.
13613 * Pointer to Ethernet device.
13615 * Pointer to flow meter structure.
13617 * Pointer to flow attributes.
13620 * 0 on success, -1 otherwise.
13623 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13624 struct mlx5_flow_meter *fm,
13625 const struct rte_flow_attr *attr)
13627 struct mlx5_priv *priv = dev->data->dev_private;
13628 struct mlx5_meter_domains_infos *mtb = fm->mfts;
13631 if (attr->egress) {
13632 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13633 priv->mtr_color_reg);
13635 DRV_LOG(ERR, "Failed to create egress policer.");
13639 if (attr->ingress) {
13640 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13641 priv->mtr_color_reg);
13643 DRV_LOG(ERR, "Failed to create ingress policer.");
13647 if (attr->transfer) {
13648 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13649 priv->mtr_color_reg);
13651 DRV_LOG(ERR, "Failed to create transfer policer.");
13657 flow_dv_destroy_policer_rules(dev, fm, attr);
13662 * Validate the batch counter support in root table.
13664 * Create a simple flow with invalid counter and drop action on root table to
13665 * validate if batch counter with offset on root table is supported or not.
13668 * Pointer to rte_eth_dev structure.
13671 * 0 on success, a negative errno value otherwise and rte_errno is set.
13674 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13676 struct mlx5_priv *priv = dev->data->dev_private;
13677 struct mlx5_dev_ctx_shared *sh = priv->sh;
13678 struct mlx5_flow_dv_match_params mask = {
13679 .size = sizeof(mask.buf),
13681 struct mlx5_flow_dv_match_params value = {
13682 .size = sizeof(value.buf),
13684 struct mlx5dv_flow_matcher_attr dv_attr = {
13685 .type = IBV_FLOW_ATTR_NORMAL,
13687 .match_criteria_enable = 0,
13688 .match_mask = (void *)&mask,
13690 void *actions[2] = { 0 };
13691 struct mlx5_flow_tbl_resource *tbl = NULL;
13692 struct mlx5_devx_obj *dcs = NULL;
13693 void *matcher = NULL;
13697 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13700 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13703 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13707 actions[1] = priv->drop_queue.hrxq->action;
13708 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13709 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13713 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13717 * If batch counter with offset is not supported, the driver will not
13718 * validate the invalid offset value, flow create should success.
13719 * In this case, it means batch counter is not supported in root table.
13721 * Otherwise, if flow create is failed, counter offset is supported.
13724 DRV_LOG(INFO, "Batch counter is not supported in root "
13725 "table. Switch to fallback mode.");
13726 rte_errno = ENOTSUP;
13728 claim_zero(mlx5_flow_os_destroy_flow(flow));
13730 /* Check matcher to make sure validate fail at flow create. */
13731 if (!matcher || (matcher && errno != EINVAL))
13732 DRV_LOG(ERR, "Unexpected error in counter offset "
13733 "support detection");
13737 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13739 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13741 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13743 claim_zero(mlx5_devx_cmd_destroy(dcs));
13748 * Query a devx counter.
13751 * Pointer to the Ethernet device structure.
13753 * Index to the flow counter.
13755 * Set to clear the counter statistics.
13757 * The statistics value of packets.
13758 * @param[out] bytes
13759 * The statistics value of bytes.
13762 * 0 on success, otherwise return -1.
13765 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13766 uint64_t *pkts, uint64_t *bytes)
13768 struct mlx5_priv *priv = dev->data->dev_private;
13769 struct mlx5_flow_counter *cnt;
13770 uint64_t inn_pkts, inn_bytes;
13773 if (!priv->config.devx)
13776 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13779 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13780 *pkts = inn_pkts - cnt->hits;
13781 *bytes = inn_bytes - cnt->bytes;
13783 cnt->hits = inn_pkts;
13784 cnt->bytes = inn_bytes;
13790 * Get aged-out flows.
13793 * Pointer to the Ethernet device structure.
13794 * @param[in] context
13795 * The address of an array of pointers to the aged-out flows contexts.
13796 * @param[in] nb_contexts
13797 * The length of context array pointers.
13798 * @param[out] error
13799 * Perform verbose error reporting if not NULL. Initialized in case of
13803 * how many contexts get in success, otherwise negative errno value.
13804 * if nb_contexts is 0, return the amount of all aged contexts.
13805 * if nb_contexts is not 0 , return the amount of aged flows reported
13806 * in the context array.
13807 * @note: only stub for now
13810 flow_get_aged_flows(struct rte_eth_dev *dev,
13812 uint32_t nb_contexts,
13813 struct rte_flow_error *error)
13815 struct mlx5_priv *priv = dev->data->dev_private;
13816 struct mlx5_age_info *age_info;
13817 struct mlx5_age_param *age_param;
13818 struct mlx5_flow_counter *counter;
13819 struct mlx5_aso_age_action *act;
13822 if (nb_contexts && !context)
13823 return rte_flow_error_set(error, EINVAL,
13824 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13825 NULL, "empty context");
13826 age_info = GET_PORT_AGE_INFO(priv);
13827 rte_spinlock_lock(&age_info->aged_sl);
13828 LIST_FOREACH(act, &age_info->aged_aso, next) {
13831 context[nb_flows - 1] =
13832 act->age_params.context;
13833 if (!(--nb_contexts))
13837 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13840 age_param = MLX5_CNT_TO_AGE(counter);
13841 context[nb_flows - 1] = age_param->context;
13842 if (!(--nb_contexts))
13846 rte_spinlock_unlock(&age_info->aged_sl);
13847 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13852 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13855 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13857 return flow_dv_counter_alloc(dev, 0);
13861 * Validate shared action.
13862 * Dispatcher for action type specific validation.
13865 * Pointer to the Ethernet device structure.
13867 * Shared action configuration.
13868 * @param[in] action
13869 * The shared action object to validate.
13870 * @param[out] error
13871 * Perform verbose error reporting if not NULL. Initialized in case of
13875 * 0 on success, otherwise negative errno value.
13878 flow_dv_action_validate(struct rte_eth_dev *dev,
13879 const struct rte_flow_shared_action_conf *conf,
13880 const struct rte_flow_action *action,
13881 struct rte_flow_error *err)
13883 struct mlx5_priv *priv = dev->data->dev_private;
13885 RTE_SET_USED(conf);
13886 switch (action->type) {
13887 case RTE_FLOW_ACTION_TYPE_RSS:
13889 * priv->obj_ops is set according to driver capabilities.
13890 * When DevX capabilities are
13891 * sufficient, it is set to devx_obj_ops.
13892 * Otherwise, it is set to ibv_obj_ops.
13893 * ibv_obj_ops doesn't support ind_table_modify operation.
13894 * In this case the shared RSS action can't be used.
13896 if (priv->obj_ops.ind_table_modify == NULL)
13897 return rte_flow_error_set
13899 RTE_FLOW_ERROR_TYPE_ACTION,
13901 "shared RSS action not supported");
13902 return mlx5_validate_action_rss(dev, action, err);
13903 case RTE_FLOW_ACTION_TYPE_AGE:
13904 if (!priv->sh->aso_age_mng)
13905 return rte_flow_error_set(err, ENOTSUP,
13906 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13908 "shared age action not supported");
13909 return flow_dv_validate_action_age(0, action, dev, err);
13911 return rte_flow_error_set(err, ENOTSUP,
13912 RTE_FLOW_ERROR_TYPE_ACTION,
13914 "action type not supported");
13919 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13921 struct mlx5_priv *priv = dev->data->dev_private;
13924 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13925 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13930 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13931 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13935 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13936 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13943 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13944 .validate = flow_dv_validate,
13945 .prepare = flow_dv_prepare,
13946 .translate = flow_dv_translate,
13947 .apply = flow_dv_apply,
13948 .remove = flow_dv_remove,
13949 .destroy = flow_dv_destroy,
13950 .query = flow_dv_query,
13951 .create_mtr_tbls = flow_dv_create_mtr_tbl,
13952 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13953 .create_policer_rules = flow_dv_create_policer_rules,
13954 .destroy_policer_rules = flow_dv_destroy_policer_rules,
13955 .counter_alloc = flow_dv_counter_allocate,
13956 .counter_free = flow_dv_counter_free,
13957 .counter_query = flow_dv_counter_query,
13958 .get_aged_flows = flow_get_aged_flows,
13959 .action_validate = flow_dv_action_validate,
13960 .action_create = flow_dv_action_create,
13961 .action_destroy = flow_dv_action_destroy,
13962 .action_update = flow_dv_action_update,
13963 .action_query = flow_dv_action_query,
13964 .sync_domain = flow_dv_sync_domain,
13967 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */