1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
97 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
99 struct mlx5_priv *priv = dev->data->dev_private;
101 if (priv->pci_dev == NULL)
103 switch (priv->pci_dev->id.device_id) {
104 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
105 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
106 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
107 return (int16_t)0xfffe;
114 * Initialize flow attributes structure according to flow items' types.
116 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
117 * mode. For tunnel mode, the items to be modified are the outermost ones.
120 * Pointer to item specification.
122 * Pointer to flow attributes structure.
123 * @param[in] dev_flow
124 * Pointer to the sub flow.
125 * @param[in] tunnel_decap
126 * Whether action is after tunnel decapsulation.
129 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
130 struct mlx5_flow *dev_flow, bool tunnel_decap)
132 uint64_t layers = dev_flow->handle->layers;
135 * If layers is already initialized, it means this dev_flow is the
136 * suffix flow, the layers flags is set by the prefix flow. Need to
137 * use the layer flags from prefix flow as the suffix flow may not
138 * have the user defined items as the flow is split.
141 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
143 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
145 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
147 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
153 uint8_t next_protocol = 0xff;
154 switch (item->type) {
155 case RTE_FLOW_ITEM_TYPE_GRE:
156 case RTE_FLOW_ITEM_TYPE_NVGRE:
157 case RTE_FLOW_ITEM_TYPE_VXLAN:
158 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
159 case RTE_FLOW_ITEM_TYPE_GENEVE:
160 case RTE_FLOW_ITEM_TYPE_MPLS:
164 case RTE_FLOW_ITEM_TYPE_IPV4:
167 if (item->mask != NULL &&
168 ((const struct rte_flow_item_ipv4 *)
169 item->mask)->hdr.next_proto_id)
171 ((const struct rte_flow_item_ipv4 *)
172 (item->spec))->hdr.next_proto_id &
173 ((const struct rte_flow_item_ipv4 *)
174 (item->mask))->hdr.next_proto_id;
175 if ((next_protocol == IPPROTO_IPIP ||
176 next_protocol == IPPROTO_IPV6) && tunnel_decap)
179 case RTE_FLOW_ITEM_TYPE_IPV6:
182 if (item->mask != NULL &&
183 ((const struct rte_flow_item_ipv6 *)
184 item->mask)->hdr.proto)
186 ((const struct rte_flow_item_ipv6 *)
187 (item->spec))->hdr.proto &
188 ((const struct rte_flow_item_ipv6 *)
189 (item->mask))->hdr.proto;
190 if ((next_protocol == IPPROTO_IPIP ||
191 next_protocol == IPPROTO_IPV6) && tunnel_decap)
194 case RTE_FLOW_ITEM_TYPE_UDP:
198 case RTE_FLOW_ITEM_TYPE_TCP:
210 * Convert rte_mtr_color to mlx5 color.
219 rte_col_2_mlx5_col(enum rte_color rcol)
222 case RTE_COLOR_GREEN:
223 return MLX5_FLOW_COLOR_GREEN;
224 case RTE_COLOR_YELLOW:
225 return MLX5_FLOW_COLOR_YELLOW;
227 return MLX5_FLOW_COLOR_RED;
231 return MLX5_FLOW_COLOR_UNDEFINED;
234 struct field_modify_info {
235 uint32_t size; /* Size of field in protocol header, in bytes. */
236 uint32_t offset; /* Offset of field in protocol header, in bytes. */
237 enum mlx5_modification_field id;
240 struct field_modify_info modify_eth[] = {
241 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
242 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
243 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
244 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
248 struct field_modify_info modify_vlan_out_first_vid[] = {
249 /* Size in bits !!! */
250 {12, 0, MLX5_MODI_OUT_FIRST_VID},
254 struct field_modify_info modify_ipv4[] = {
255 {1, 1, MLX5_MODI_OUT_IP_DSCP},
256 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
257 {4, 12, MLX5_MODI_OUT_SIPV4},
258 {4, 16, MLX5_MODI_OUT_DIPV4},
262 struct field_modify_info modify_ipv6[] = {
263 {1, 0, MLX5_MODI_OUT_IP_DSCP},
264 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
265 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
266 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
267 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
268 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
269 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
270 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
271 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
272 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
276 struct field_modify_info modify_udp[] = {
277 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
278 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
282 struct field_modify_info modify_tcp[] = {
283 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
284 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
285 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
286 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
291 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
292 uint8_t next_protocol, uint64_t *item_flags,
295 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
296 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
297 if (next_protocol == IPPROTO_IPIP) {
298 *item_flags |= MLX5_FLOW_LAYER_IPIP;
301 if (next_protocol == IPPROTO_IPV6) {
302 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
307 static inline struct mlx5_hlist *
308 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
309 const char *name, uint32_t size, bool direct_key,
310 bool lcores_share, void *ctx,
311 mlx5_list_create_cb cb_create,
312 mlx5_list_match_cb cb_match,
313 mlx5_list_remove_cb cb_remove,
314 mlx5_list_clone_cb cb_clone,
315 mlx5_list_clone_free_cb cb_clone_free)
317 struct mlx5_hlist *hl;
318 struct mlx5_hlist *expected = NULL;
319 char s[MLX5_NAME_SIZE];
321 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
324 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
325 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
326 ctx, cb_create, cb_match, cb_remove, cb_clone,
329 DRV_LOG(ERR, "%s hash creation failed", name);
333 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
336 mlx5_hlist_destroy(hl);
337 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
342 /* Update VLAN's VID/PCP based on input rte_flow_action.
345 * Pointer to struct rte_flow_action.
347 * Pointer to struct rte_vlan_hdr.
350 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
351 struct rte_vlan_hdr *vlan)
354 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
356 ((const struct rte_flow_action_of_set_vlan_pcp *)
357 action->conf)->vlan_pcp;
358 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
359 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
360 vlan->vlan_tci |= vlan_tci;
361 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
362 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
363 vlan->vlan_tci |= rte_be_to_cpu_16
364 (((const struct rte_flow_action_of_set_vlan_vid *)
365 action->conf)->vlan_vid);
370 * Fetch 1, 2, 3 or 4 byte field from the byte array
371 * and return as unsigned integer in host-endian format.
374 * Pointer to data array.
376 * Size of field to extract.
379 * converted field in host endian format.
381 static inline uint32_t
382 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
391 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
394 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
395 ret = (ret << 8) | *(data + sizeof(uint16_t));
398 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
409 * Convert modify-header action to DV specification.
411 * Data length of each action is determined by provided field description
412 * and the item mask. Data bit offset and width of each action is determined
413 * by provided item mask.
416 * Pointer to item specification.
418 * Pointer to field modification information.
419 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
420 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
421 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
423 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
424 * Negative offset value sets the same offset as source offset.
425 * size field is ignored, value is taken from source field.
426 * @param[in,out] resource
427 * Pointer to the modify-header resource.
429 * Type of modification.
431 * Pointer to the error structure.
434 * 0 on success, a negative errno value otherwise and rte_errno is set.
437 flow_dv_convert_modify_action(struct rte_flow_item *item,
438 struct field_modify_info *field,
439 struct field_modify_info *dcopy,
440 struct mlx5_flow_dv_modify_hdr_resource *resource,
441 uint32_t type, struct rte_flow_error *error)
443 uint32_t i = resource->actions_num;
444 struct mlx5_modification_cmd *actions = resource->actions;
445 uint32_t carry_b = 0;
448 * The item and mask are provided in big-endian format.
449 * The fields should be presented as in big-endian format either.
450 * Mask must be always present, it defines the actual field width.
452 MLX5_ASSERT(item->mask);
453 MLX5_ASSERT(field->size);
459 bool next_field = true;
460 bool next_dcopy = true;
462 if (i >= MLX5_MAX_MODIFY_NUM)
463 return rte_flow_error_set(error, EINVAL,
464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
465 "too many items to modify");
466 /* Fetch variable byte size mask from the array. */
467 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
468 field->offset, field->size);
473 /* Deduce actual data width in bits from mask value. */
474 off_b = rte_bsf32(mask) + carry_b;
475 size_b = sizeof(uint32_t) * CHAR_BIT -
476 off_b - __builtin_clz(mask);
478 actions[i] = (struct mlx5_modification_cmd) {
482 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
485 if (type == MLX5_MODIFICATION_TYPE_COPY) {
487 actions[i].dst_field = dcopy->id;
488 actions[i].dst_offset =
489 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
490 /* Convert entire record to big-endian format. */
491 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
493 * Destination field overflow. Copy leftovers of
494 * a source field to the next destination field.
497 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
500 dcopy->size * CHAR_BIT - dcopy->offset;
501 carry_b = actions[i].length;
505 * Not enough bits in a source filed to fill a
506 * destination field. Switch to the next source.
508 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
509 (size_b == field->size * CHAR_BIT - off_b)) {
511 field->size * CHAR_BIT - off_b;
512 dcopy->offset += actions[i].length;
518 MLX5_ASSERT(item->spec);
519 data = flow_dv_fetch_field((const uint8_t *)item->spec +
520 field->offset, field->size);
521 /* Shift out the trailing masked bits from data. */
522 data = (data & mask) >> off_b;
523 actions[i].data1 = rte_cpu_to_be_32(data);
525 /* Convert entire record to expected big-endian format. */
526 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
530 } while (field->size);
531 if (resource->actions_num == i)
532 return rte_flow_error_set(error, EINVAL,
533 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
534 "invalid modification flow item");
535 resource->actions_num = i;
540 * Convert modify-header set IPv4 address action to DV specification.
542 * @param[in,out] resource
543 * Pointer to the modify-header resource.
545 * Pointer to action specification.
547 * Pointer to the error structure.
550 * 0 on success, a negative errno value otherwise and rte_errno is set.
553 flow_dv_convert_action_modify_ipv4
554 (struct mlx5_flow_dv_modify_hdr_resource *resource,
555 const struct rte_flow_action *action,
556 struct rte_flow_error *error)
558 const struct rte_flow_action_set_ipv4 *conf =
559 (const struct rte_flow_action_set_ipv4 *)(action->conf);
560 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
561 struct rte_flow_item_ipv4 ipv4;
562 struct rte_flow_item_ipv4 ipv4_mask;
564 memset(&ipv4, 0, sizeof(ipv4));
565 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
566 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
567 ipv4.hdr.src_addr = conf->ipv4_addr;
568 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
570 ipv4.hdr.dst_addr = conf->ipv4_addr;
571 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
574 item.mask = &ipv4_mask;
575 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
576 MLX5_MODIFICATION_TYPE_SET, error);
580 * Convert modify-header set IPv6 address action to DV specification.
582 * @param[in,out] resource
583 * Pointer to the modify-header resource.
585 * Pointer to action specification.
587 * Pointer to the error structure.
590 * 0 on success, a negative errno value otherwise and rte_errno is set.
593 flow_dv_convert_action_modify_ipv6
594 (struct mlx5_flow_dv_modify_hdr_resource *resource,
595 const struct rte_flow_action *action,
596 struct rte_flow_error *error)
598 const struct rte_flow_action_set_ipv6 *conf =
599 (const struct rte_flow_action_set_ipv6 *)(action->conf);
600 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
601 struct rte_flow_item_ipv6 ipv6;
602 struct rte_flow_item_ipv6 ipv6_mask;
604 memset(&ipv6, 0, sizeof(ipv6));
605 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
606 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
607 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
608 sizeof(ipv6.hdr.src_addr));
609 memcpy(&ipv6_mask.hdr.src_addr,
610 &rte_flow_item_ipv6_mask.hdr.src_addr,
611 sizeof(ipv6.hdr.src_addr));
613 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
614 sizeof(ipv6.hdr.dst_addr));
615 memcpy(&ipv6_mask.hdr.dst_addr,
616 &rte_flow_item_ipv6_mask.hdr.dst_addr,
617 sizeof(ipv6.hdr.dst_addr));
620 item.mask = &ipv6_mask;
621 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
622 MLX5_MODIFICATION_TYPE_SET, error);
626 * Convert modify-header set MAC address action to DV specification.
628 * @param[in,out] resource
629 * Pointer to the modify-header resource.
631 * Pointer to action specification.
633 * Pointer to the error structure.
636 * 0 on success, a negative errno value otherwise and rte_errno is set.
639 flow_dv_convert_action_modify_mac
640 (struct mlx5_flow_dv_modify_hdr_resource *resource,
641 const struct rte_flow_action *action,
642 struct rte_flow_error *error)
644 const struct rte_flow_action_set_mac *conf =
645 (const struct rte_flow_action_set_mac *)(action->conf);
646 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
647 struct rte_flow_item_eth eth;
648 struct rte_flow_item_eth eth_mask;
650 memset(ð, 0, sizeof(eth));
651 memset(ð_mask, 0, sizeof(eth_mask));
652 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
653 memcpy(ð.src.addr_bytes, &conf->mac_addr,
654 sizeof(eth.src.addr_bytes));
655 memcpy(ð_mask.src.addr_bytes,
656 &rte_flow_item_eth_mask.src.addr_bytes,
657 sizeof(eth_mask.src.addr_bytes));
659 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
660 sizeof(eth.dst.addr_bytes));
661 memcpy(ð_mask.dst.addr_bytes,
662 &rte_flow_item_eth_mask.dst.addr_bytes,
663 sizeof(eth_mask.dst.addr_bytes));
666 item.mask = ð_mask;
667 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
668 MLX5_MODIFICATION_TYPE_SET, error);
672 * Convert modify-header set VLAN VID action to DV specification.
674 * @param[in,out] resource
675 * Pointer to the modify-header resource.
677 * Pointer to action specification.
679 * Pointer to the error structure.
682 * 0 on success, a negative errno value otherwise and rte_errno is set.
685 flow_dv_convert_action_modify_vlan_vid
686 (struct mlx5_flow_dv_modify_hdr_resource *resource,
687 const struct rte_flow_action *action,
688 struct rte_flow_error *error)
690 const struct rte_flow_action_of_set_vlan_vid *conf =
691 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
692 int i = resource->actions_num;
693 struct mlx5_modification_cmd *actions = resource->actions;
694 struct field_modify_info *field = modify_vlan_out_first_vid;
696 if (i >= MLX5_MAX_MODIFY_NUM)
697 return rte_flow_error_set(error, EINVAL,
698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
699 "too many items to modify");
700 actions[i] = (struct mlx5_modification_cmd) {
701 .action_type = MLX5_MODIFICATION_TYPE_SET,
703 .length = field->size,
704 .offset = field->offset,
706 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
707 actions[i].data1 = conf->vlan_vid;
708 actions[i].data1 = actions[i].data1 << 16;
709 resource->actions_num = ++i;
714 * Convert modify-header set TP action to DV specification.
716 * @param[in,out] resource
717 * Pointer to the modify-header resource.
719 * Pointer to action specification.
721 * Pointer to rte_flow_item objects list.
723 * Pointer to flow attributes structure.
724 * @param[in] dev_flow
725 * Pointer to the sub flow.
726 * @param[in] tunnel_decap
727 * Whether action is after tunnel decapsulation.
729 * Pointer to the error structure.
732 * 0 on success, a negative errno value otherwise and rte_errno is set.
735 flow_dv_convert_action_modify_tp
736 (struct mlx5_flow_dv_modify_hdr_resource *resource,
737 const struct rte_flow_action *action,
738 const struct rte_flow_item *items,
739 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
740 bool tunnel_decap, struct rte_flow_error *error)
742 const struct rte_flow_action_set_tp *conf =
743 (const struct rte_flow_action_set_tp *)(action->conf);
744 struct rte_flow_item item;
745 struct rte_flow_item_udp udp;
746 struct rte_flow_item_udp udp_mask;
747 struct rte_flow_item_tcp tcp;
748 struct rte_flow_item_tcp tcp_mask;
749 struct field_modify_info *field;
752 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
754 memset(&udp, 0, sizeof(udp));
755 memset(&udp_mask, 0, sizeof(udp_mask));
756 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
757 udp.hdr.src_port = conf->port;
758 udp_mask.hdr.src_port =
759 rte_flow_item_udp_mask.hdr.src_port;
761 udp.hdr.dst_port = conf->port;
762 udp_mask.hdr.dst_port =
763 rte_flow_item_udp_mask.hdr.dst_port;
765 item.type = RTE_FLOW_ITEM_TYPE_UDP;
767 item.mask = &udp_mask;
770 MLX5_ASSERT(attr->tcp);
771 memset(&tcp, 0, sizeof(tcp));
772 memset(&tcp_mask, 0, sizeof(tcp_mask));
773 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
774 tcp.hdr.src_port = conf->port;
775 tcp_mask.hdr.src_port =
776 rte_flow_item_tcp_mask.hdr.src_port;
778 tcp.hdr.dst_port = conf->port;
779 tcp_mask.hdr.dst_port =
780 rte_flow_item_tcp_mask.hdr.dst_port;
782 item.type = RTE_FLOW_ITEM_TYPE_TCP;
784 item.mask = &tcp_mask;
787 return flow_dv_convert_modify_action(&item, field, NULL, resource,
788 MLX5_MODIFICATION_TYPE_SET, error);
792 * Convert modify-header set TTL action to DV specification.
794 * @param[in,out] resource
795 * Pointer to the modify-header resource.
797 * Pointer to action specification.
799 * Pointer to rte_flow_item objects list.
801 * Pointer to flow attributes structure.
802 * @param[in] dev_flow
803 * Pointer to the sub flow.
804 * @param[in] tunnel_decap
805 * Whether action is after tunnel decapsulation.
807 * Pointer to the error structure.
810 * 0 on success, a negative errno value otherwise and rte_errno is set.
813 flow_dv_convert_action_modify_ttl
814 (struct mlx5_flow_dv_modify_hdr_resource *resource,
815 const struct rte_flow_action *action,
816 const struct rte_flow_item *items,
817 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
818 bool tunnel_decap, struct rte_flow_error *error)
820 const struct rte_flow_action_set_ttl *conf =
821 (const struct rte_flow_action_set_ttl *)(action->conf);
822 struct rte_flow_item item;
823 struct rte_flow_item_ipv4 ipv4;
824 struct rte_flow_item_ipv4 ipv4_mask;
825 struct rte_flow_item_ipv6 ipv6;
826 struct rte_flow_item_ipv6 ipv6_mask;
827 struct field_modify_info *field;
830 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
832 memset(&ipv4, 0, sizeof(ipv4));
833 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
834 ipv4.hdr.time_to_live = conf->ttl_value;
835 ipv4_mask.hdr.time_to_live = 0xFF;
836 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
838 item.mask = &ipv4_mask;
841 MLX5_ASSERT(attr->ipv6);
842 memset(&ipv6, 0, sizeof(ipv6));
843 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
844 ipv6.hdr.hop_limits = conf->ttl_value;
845 ipv6_mask.hdr.hop_limits = 0xFF;
846 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
848 item.mask = &ipv6_mask;
851 return flow_dv_convert_modify_action(&item, field, NULL, resource,
852 MLX5_MODIFICATION_TYPE_SET, error);
856 * Convert modify-header decrement TTL action to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to rte_flow_item objects list.
865 * Pointer to flow attributes structure.
866 * @param[in] dev_flow
867 * Pointer to the sub flow.
868 * @param[in] tunnel_decap
869 * Whether action is after tunnel decapsulation.
871 * Pointer to the error structure.
874 * 0 on success, a negative errno value otherwise and rte_errno is set.
877 flow_dv_convert_action_modify_dec_ttl
878 (struct mlx5_flow_dv_modify_hdr_resource *resource,
879 const struct rte_flow_item *items,
880 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
881 bool tunnel_decap, struct rte_flow_error *error)
883 struct rte_flow_item item;
884 struct rte_flow_item_ipv4 ipv4;
885 struct rte_flow_item_ipv4 ipv4_mask;
886 struct rte_flow_item_ipv6 ipv6;
887 struct rte_flow_item_ipv6 ipv6_mask;
888 struct field_modify_info *field;
891 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
893 memset(&ipv4, 0, sizeof(ipv4));
894 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
895 ipv4.hdr.time_to_live = 0xFF;
896 ipv4_mask.hdr.time_to_live = 0xFF;
897 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
899 item.mask = &ipv4_mask;
902 MLX5_ASSERT(attr->ipv6);
903 memset(&ipv6, 0, sizeof(ipv6));
904 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
905 ipv6.hdr.hop_limits = 0xFF;
906 ipv6_mask.hdr.hop_limits = 0xFF;
907 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
909 item.mask = &ipv6_mask;
912 return flow_dv_convert_modify_action(&item, field, NULL, resource,
913 MLX5_MODIFICATION_TYPE_ADD, error);
917 * Convert modify-header increment/decrement TCP Sequence number
918 * to DV specification.
920 * @param[in,out] resource
921 * Pointer to the modify-header resource.
923 * Pointer to action specification.
925 * Pointer to the error structure.
928 * 0 on success, a negative errno value otherwise and rte_errno is set.
931 flow_dv_convert_action_modify_tcp_seq
932 (struct mlx5_flow_dv_modify_hdr_resource *resource,
933 const struct rte_flow_action *action,
934 struct rte_flow_error *error)
936 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
937 uint64_t value = rte_be_to_cpu_32(*conf);
938 struct rte_flow_item item;
939 struct rte_flow_item_tcp tcp;
940 struct rte_flow_item_tcp tcp_mask;
942 memset(&tcp, 0, sizeof(tcp));
943 memset(&tcp_mask, 0, sizeof(tcp_mask));
944 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
946 * The HW has no decrement operation, only increment operation.
947 * To simulate decrement X from Y using increment operation
948 * we need to add UINT32_MAX X times to Y.
949 * Each adding of UINT32_MAX decrements Y by 1.
952 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
953 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
954 item.type = RTE_FLOW_ITEM_TYPE_TCP;
956 item.mask = &tcp_mask;
957 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
958 MLX5_MODIFICATION_TYPE_ADD, error);
962 * Convert modify-header increment/decrement TCP Acknowledgment number
963 * to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_modify_tcp_ack
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
982 uint64_t value = rte_be_to_cpu_32(*conf);
983 struct rte_flow_item item;
984 struct rte_flow_item_tcp tcp;
985 struct rte_flow_item_tcp tcp_mask;
987 memset(&tcp, 0, sizeof(tcp));
988 memset(&tcp_mask, 0, sizeof(tcp_mask));
989 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
991 * The HW has no decrement operation, only increment operation.
992 * To simulate decrement X from Y using increment operation
993 * we need to add UINT32_MAX X times to Y.
994 * Each adding of UINT32_MAX decrements Y by 1.
997 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
998 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
999 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1001 item.mask = &tcp_mask;
1002 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1003 MLX5_MODIFICATION_TYPE_ADD, error);
1006 static enum mlx5_modification_field reg_to_field[] = {
1007 [REG_NON] = MLX5_MODI_OUT_NONE,
1008 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1009 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1010 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1011 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1012 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1013 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1014 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1015 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1016 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1017 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1021 * Convert register set to DV specification.
1023 * @param[in,out] resource
1024 * Pointer to the modify-header resource.
1026 * Pointer to action specification.
1028 * Pointer to the error structure.
1031 * 0 on success, a negative errno value otherwise and rte_errno is set.
1034 flow_dv_convert_action_set_reg
1035 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1036 const struct rte_flow_action *action,
1037 struct rte_flow_error *error)
1039 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1040 struct mlx5_modification_cmd *actions = resource->actions;
1041 uint32_t i = resource->actions_num;
1043 if (i >= MLX5_MAX_MODIFY_NUM)
1044 return rte_flow_error_set(error, EINVAL,
1045 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1046 "too many items to modify");
1047 MLX5_ASSERT(conf->id != REG_NON);
1048 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1049 actions[i] = (struct mlx5_modification_cmd) {
1050 .action_type = MLX5_MODIFICATION_TYPE_SET,
1051 .field = reg_to_field[conf->id],
1052 .offset = conf->offset,
1053 .length = conf->length,
1055 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1056 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1058 resource->actions_num = i;
1063 * Convert SET_TAG action to DV specification.
1066 * Pointer to the rte_eth_dev structure.
1067 * @param[in,out] resource
1068 * Pointer to the modify-header resource.
1070 * Pointer to action specification.
1072 * Pointer to the error structure.
1075 * 0 on success, a negative errno value otherwise and rte_errno is set.
1078 flow_dv_convert_action_set_tag
1079 (struct rte_eth_dev *dev,
1080 struct mlx5_flow_dv_modify_hdr_resource *resource,
1081 const struct rte_flow_action_set_tag *conf,
1082 struct rte_flow_error *error)
1084 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1085 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1086 struct rte_flow_item item = {
1090 struct field_modify_info reg_c_x[] = {
1093 enum mlx5_modification_field reg_type;
1096 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1099 MLX5_ASSERT(ret != REG_NON);
1100 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1101 reg_type = reg_to_field[ret];
1102 MLX5_ASSERT(reg_type > 0);
1103 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1104 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1105 MLX5_MODIFICATION_TYPE_SET, error);
1109 * Convert internal COPY_REG action to DV specification.
1112 * Pointer to the rte_eth_dev structure.
1113 * @param[in,out] res
1114 * Pointer to the modify-header resource.
1116 * Pointer to action specification.
1118 * Pointer to the error structure.
1121 * 0 on success, a negative errno value otherwise and rte_errno is set.
1124 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1125 struct mlx5_flow_dv_modify_hdr_resource *res,
1126 const struct rte_flow_action *action,
1127 struct rte_flow_error *error)
1129 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1130 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1131 struct rte_flow_item item = {
1135 struct field_modify_info reg_src[] = {
1136 {4, 0, reg_to_field[conf->src]},
1139 struct field_modify_info reg_dst = {
1141 .id = reg_to_field[conf->dst],
1143 /* Adjust reg_c[0] usage according to reported mask. */
1144 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1145 struct mlx5_priv *priv = dev->data->dev_private;
1146 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1148 MLX5_ASSERT(reg_c0);
1149 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1150 if (conf->dst == REG_C_0) {
1151 /* Copy to reg_c[0], within mask only. */
1152 reg_dst.offset = rte_bsf32(reg_c0);
1153 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1156 mask = rte_cpu_to_be_32(reg_c0);
1159 return flow_dv_convert_modify_action(&item,
1160 reg_src, ®_dst, res,
1161 MLX5_MODIFICATION_TYPE_COPY,
1166 * Convert MARK action to DV specification. This routine is used
1167 * in extensive metadata only and requires metadata register to be
1168 * handled. In legacy mode hardware tag resource is engaged.
1171 * Pointer to the rte_eth_dev structure.
1173 * Pointer to MARK action specification.
1174 * @param[in,out] resource
1175 * Pointer to the modify-header resource.
1177 * Pointer to the error structure.
1180 * 0 on success, a negative errno value otherwise and rte_errno is set.
1183 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1184 const struct rte_flow_action_mark *conf,
1185 struct mlx5_flow_dv_modify_hdr_resource *resource,
1186 struct rte_flow_error *error)
1188 struct mlx5_priv *priv = dev->data->dev_private;
1189 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1190 priv->sh->dv_mark_mask);
1191 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1192 struct rte_flow_item item = {
1196 struct field_modify_info reg_c_x[] = {
1202 return rte_flow_error_set(error, EINVAL,
1203 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1204 NULL, "zero mark action mask");
1205 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1208 MLX5_ASSERT(reg > 0);
1209 if (reg == REG_C_0) {
1210 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1211 uint32_t shl_c0 = rte_bsf32(msk_c0);
1213 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1214 mask = rte_cpu_to_be_32(mask) & msk_c0;
1215 mask = rte_cpu_to_be_32(mask << shl_c0);
1217 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1218 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1219 MLX5_MODIFICATION_TYPE_SET, error);
1223 * Get metadata register index for specified steering domain.
1226 * Pointer to the rte_eth_dev structure.
1228 * Attributes of flow to determine steering domain.
1230 * Pointer to the error structure.
1233 * positive index on success, a negative errno value otherwise
1234 * and rte_errno is set.
1236 static enum modify_reg
1237 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1238 const struct rte_flow_attr *attr,
1239 struct rte_flow_error *error)
1242 mlx5_flow_get_reg_id(dev, attr->transfer ?
1246 MLX5_METADATA_RX, 0, error);
1248 return rte_flow_error_set(error,
1249 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1250 NULL, "unavailable "
1251 "metadata register");
1256 * Convert SET_META action to DV specification.
1259 * Pointer to the rte_eth_dev structure.
1260 * @param[in,out] resource
1261 * Pointer to the modify-header resource.
1263 * Attributes of flow that includes this item.
1265 * Pointer to action specification.
1267 * Pointer to the error structure.
1270 * 0 on success, a negative errno value otherwise and rte_errno is set.
1273 flow_dv_convert_action_set_meta
1274 (struct rte_eth_dev *dev,
1275 struct mlx5_flow_dv_modify_hdr_resource *resource,
1276 const struct rte_flow_attr *attr,
1277 const struct rte_flow_action_set_meta *conf,
1278 struct rte_flow_error *error)
1280 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1281 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1282 struct rte_flow_item item = {
1286 struct field_modify_info reg_c_x[] = {
1289 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1293 MLX5_ASSERT(reg != REG_NON);
1294 if (reg == REG_C_0) {
1295 struct mlx5_priv *priv = dev->data->dev_private;
1296 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1297 uint32_t shl_c0 = rte_bsf32(msk_c0);
1299 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1300 mask = rte_cpu_to_be_32(mask) & msk_c0;
1301 mask = rte_cpu_to_be_32(mask << shl_c0);
1303 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1304 /* The routine expects parameters in memory as big-endian ones. */
1305 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1306 MLX5_MODIFICATION_TYPE_SET, error);
1310 * Convert modify-header set IPv4 DSCP action to DV specification.
1312 * @param[in,out] resource
1313 * Pointer to the modify-header resource.
1315 * Pointer to action specification.
1317 * Pointer to the error structure.
1320 * 0 on success, a negative errno value otherwise and rte_errno is set.
1323 flow_dv_convert_action_modify_ipv4_dscp
1324 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1325 const struct rte_flow_action *action,
1326 struct rte_flow_error *error)
1328 const struct rte_flow_action_set_dscp *conf =
1329 (const struct rte_flow_action_set_dscp *)(action->conf);
1330 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1331 struct rte_flow_item_ipv4 ipv4;
1332 struct rte_flow_item_ipv4 ipv4_mask;
1334 memset(&ipv4, 0, sizeof(ipv4));
1335 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1336 ipv4.hdr.type_of_service = conf->dscp;
1337 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1339 item.mask = &ipv4_mask;
1340 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1341 MLX5_MODIFICATION_TYPE_SET, error);
1345 * Convert modify-header set IPv6 DSCP action to DV specification.
1347 * @param[in,out] resource
1348 * Pointer to the modify-header resource.
1350 * Pointer to action specification.
1352 * Pointer to the error structure.
1355 * 0 on success, a negative errno value otherwise and rte_errno is set.
1358 flow_dv_convert_action_modify_ipv6_dscp
1359 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1360 const struct rte_flow_action *action,
1361 struct rte_flow_error *error)
1363 const struct rte_flow_action_set_dscp *conf =
1364 (const struct rte_flow_action_set_dscp *)(action->conf);
1365 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1366 struct rte_flow_item_ipv6 ipv6;
1367 struct rte_flow_item_ipv6 ipv6_mask;
1369 memset(&ipv6, 0, sizeof(ipv6));
1370 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1372 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1373 * rdma-core only accept the DSCP bits byte aligned start from
1374 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1375 * bits in IPv6 case as rdma-core requires byte aligned value.
1377 ipv6.hdr.vtc_flow = conf->dscp;
1378 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1380 item.mask = &ipv6_mask;
1381 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1382 MLX5_MODIFICATION_TYPE_SET, error);
1386 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1387 enum rte_flow_field_id field, int inherit,
1388 const struct rte_flow_attr *attr,
1389 struct rte_flow_error *error)
1391 struct mlx5_priv *priv = dev->data->dev_private;
1394 case RTE_FLOW_FIELD_START:
1396 case RTE_FLOW_FIELD_MAC_DST:
1397 case RTE_FLOW_FIELD_MAC_SRC:
1399 case RTE_FLOW_FIELD_VLAN_TYPE:
1401 case RTE_FLOW_FIELD_VLAN_ID:
1403 case RTE_FLOW_FIELD_MAC_TYPE:
1405 case RTE_FLOW_FIELD_IPV4_DSCP:
1407 case RTE_FLOW_FIELD_IPV4_TTL:
1409 case RTE_FLOW_FIELD_IPV4_SRC:
1410 case RTE_FLOW_FIELD_IPV4_DST:
1412 case RTE_FLOW_FIELD_IPV6_DSCP:
1414 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1416 case RTE_FLOW_FIELD_IPV6_SRC:
1417 case RTE_FLOW_FIELD_IPV6_DST:
1419 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1420 case RTE_FLOW_FIELD_TCP_PORT_DST:
1422 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1423 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1425 case RTE_FLOW_FIELD_TCP_FLAGS:
1427 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1428 case RTE_FLOW_FIELD_UDP_PORT_DST:
1430 case RTE_FLOW_FIELD_VXLAN_VNI:
1431 case RTE_FLOW_FIELD_GENEVE_VNI:
1433 case RTE_FLOW_FIELD_GTP_TEID:
1434 case RTE_FLOW_FIELD_TAG:
1436 case RTE_FLOW_FIELD_MARK:
1437 return __builtin_popcount(priv->sh->dv_mark_mask);
1438 case RTE_FLOW_FIELD_META:
1439 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1440 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1441 case RTE_FLOW_FIELD_POINTER:
1442 case RTE_FLOW_FIELD_VALUE:
1443 return inherit < 0 ? 0 : inherit;
1451 mlx5_flow_field_id_to_modify_info
1452 (const struct rte_flow_action_modify_data *data,
1453 struct field_modify_info *info, uint32_t *mask,
1454 uint32_t width, struct rte_eth_dev *dev,
1455 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1457 struct mlx5_priv *priv = dev->data->dev_private;
1461 switch (data->field) {
1462 case RTE_FLOW_FIELD_START:
1463 /* not supported yet */
1466 case RTE_FLOW_FIELD_MAC_DST:
1467 off = data->offset > 16 ? data->offset - 16 : 0;
1469 if (data->offset < 16) {
1470 info[idx] = (struct field_modify_info){2, 4,
1471 MLX5_MODI_OUT_DMAC_15_0};
1473 mask[1] = rte_cpu_to_be_16(0xffff >>
1477 mask[1] = RTE_BE16(0xffff);
1484 info[idx] = (struct field_modify_info){4, 0,
1485 MLX5_MODI_OUT_DMAC_47_16};
1486 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1487 (32 - width)) << off);
1489 if (data->offset < 16)
1490 info[idx++] = (struct field_modify_info){2, 0,
1491 MLX5_MODI_OUT_DMAC_15_0};
1492 info[idx] = (struct field_modify_info){4, off,
1493 MLX5_MODI_OUT_DMAC_47_16};
1496 case RTE_FLOW_FIELD_MAC_SRC:
1497 off = data->offset > 16 ? data->offset - 16 : 0;
1499 if (data->offset < 16) {
1500 info[idx] = (struct field_modify_info){2, 4,
1501 MLX5_MODI_OUT_SMAC_15_0};
1503 mask[1] = rte_cpu_to_be_16(0xffff >>
1507 mask[1] = RTE_BE16(0xffff);
1514 info[idx] = (struct field_modify_info){4, 0,
1515 MLX5_MODI_OUT_SMAC_47_16};
1516 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1517 (32 - width)) << off);
1519 if (data->offset < 16)
1520 info[idx++] = (struct field_modify_info){2, 0,
1521 MLX5_MODI_OUT_SMAC_15_0};
1522 info[idx] = (struct field_modify_info){4, off,
1523 MLX5_MODI_OUT_SMAC_47_16};
1526 case RTE_FLOW_FIELD_VLAN_TYPE:
1527 /* not supported yet */
1529 case RTE_FLOW_FIELD_VLAN_ID:
1530 info[idx] = (struct field_modify_info){2, 0,
1531 MLX5_MODI_OUT_FIRST_VID};
1533 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1535 case RTE_FLOW_FIELD_MAC_TYPE:
1536 info[idx] = (struct field_modify_info){2, 0,
1537 MLX5_MODI_OUT_ETHERTYPE};
1539 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1541 case RTE_FLOW_FIELD_IPV4_DSCP:
1542 info[idx] = (struct field_modify_info){1, 0,
1543 MLX5_MODI_OUT_IP_DSCP};
1545 mask[idx] = 0x3f >> (6 - width);
1547 case RTE_FLOW_FIELD_IPV4_TTL:
1548 info[idx] = (struct field_modify_info){1, 0,
1549 MLX5_MODI_OUT_IPV4_TTL};
1551 mask[idx] = 0xff >> (8 - width);
1553 case RTE_FLOW_FIELD_IPV4_SRC:
1554 info[idx] = (struct field_modify_info){4, 0,
1555 MLX5_MODI_OUT_SIPV4};
1557 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1560 case RTE_FLOW_FIELD_IPV4_DST:
1561 info[idx] = (struct field_modify_info){4, 0,
1562 MLX5_MODI_OUT_DIPV4};
1564 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1567 case RTE_FLOW_FIELD_IPV6_DSCP:
1568 info[idx] = (struct field_modify_info){1, 0,
1569 MLX5_MODI_OUT_IP_DSCP};
1571 mask[idx] = 0x3f >> (6 - width);
1573 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1574 info[idx] = (struct field_modify_info){1, 0,
1575 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1577 mask[idx] = 0xff >> (8 - width);
1579 case RTE_FLOW_FIELD_IPV6_SRC:
1581 if (data->offset < 32) {
1582 info[idx] = (struct field_modify_info){4, 12,
1583 MLX5_MODI_OUT_SIPV6_31_0};
1586 rte_cpu_to_be_32(0xffffffff >>
1590 mask[3] = RTE_BE32(0xffffffff);
1597 if (data->offset < 64) {
1598 info[idx] = (struct field_modify_info){4, 8,
1599 MLX5_MODI_OUT_SIPV6_63_32};
1602 rte_cpu_to_be_32(0xffffffff >>
1606 mask[2] = RTE_BE32(0xffffffff);
1613 if (data->offset < 96) {
1614 info[idx] = (struct field_modify_info){4, 4,
1615 MLX5_MODI_OUT_SIPV6_95_64};
1618 rte_cpu_to_be_32(0xffffffff >>
1622 mask[1] = RTE_BE32(0xffffffff);
1629 info[idx] = (struct field_modify_info){4, 0,
1630 MLX5_MODI_OUT_SIPV6_127_96};
1631 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1633 if (data->offset < 32)
1634 info[idx++] = (struct field_modify_info){4, 0,
1635 MLX5_MODI_OUT_SIPV6_31_0};
1636 if (data->offset < 64)
1637 info[idx++] = (struct field_modify_info){4, 0,
1638 MLX5_MODI_OUT_SIPV6_63_32};
1639 if (data->offset < 96)
1640 info[idx++] = (struct field_modify_info){4, 0,
1641 MLX5_MODI_OUT_SIPV6_95_64};
1642 if (data->offset < 128)
1643 info[idx++] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1647 case RTE_FLOW_FIELD_IPV6_DST:
1649 if (data->offset < 32) {
1650 info[idx] = (struct field_modify_info){4, 12,
1651 MLX5_MODI_OUT_DIPV6_31_0};
1654 rte_cpu_to_be_32(0xffffffff >>
1658 mask[3] = RTE_BE32(0xffffffff);
1665 if (data->offset < 64) {
1666 info[idx] = (struct field_modify_info){4, 8,
1667 MLX5_MODI_OUT_DIPV6_63_32};
1670 rte_cpu_to_be_32(0xffffffff >>
1674 mask[2] = RTE_BE32(0xffffffff);
1681 if (data->offset < 96) {
1682 info[idx] = (struct field_modify_info){4, 4,
1683 MLX5_MODI_OUT_DIPV6_95_64};
1686 rte_cpu_to_be_32(0xffffffff >>
1690 mask[1] = RTE_BE32(0xffffffff);
1697 info[idx] = (struct field_modify_info){4, 0,
1698 MLX5_MODI_OUT_DIPV6_127_96};
1699 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1701 if (data->offset < 32)
1702 info[idx++] = (struct field_modify_info){4, 0,
1703 MLX5_MODI_OUT_DIPV6_31_0};
1704 if (data->offset < 64)
1705 info[idx++] = (struct field_modify_info){4, 0,
1706 MLX5_MODI_OUT_DIPV6_63_32};
1707 if (data->offset < 96)
1708 info[idx++] = (struct field_modify_info){4, 0,
1709 MLX5_MODI_OUT_DIPV6_95_64};
1710 if (data->offset < 128)
1711 info[idx++] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1715 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1716 info[idx] = (struct field_modify_info){2, 0,
1717 MLX5_MODI_OUT_TCP_SPORT};
1719 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1721 case RTE_FLOW_FIELD_TCP_PORT_DST:
1722 info[idx] = (struct field_modify_info){2, 0,
1723 MLX5_MODI_OUT_TCP_DPORT};
1725 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1727 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1728 info[idx] = (struct field_modify_info){4, 0,
1729 MLX5_MODI_OUT_TCP_SEQ_NUM};
1731 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1734 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1735 info[idx] = (struct field_modify_info){4, 0,
1736 MLX5_MODI_OUT_TCP_ACK_NUM};
1738 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1741 case RTE_FLOW_FIELD_TCP_FLAGS:
1742 info[idx] = (struct field_modify_info){2, 0,
1743 MLX5_MODI_OUT_TCP_FLAGS};
1745 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1747 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1748 info[idx] = (struct field_modify_info){2, 0,
1749 MLX5_MODI_OUT_UDP_SPORT};
1751 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1753 case RTE_FLOW_FIELD_UDP_PORT_DST:
1754 info[idx] = (struct field_modify_info){2, 0,
1755 MLX5_MODI_OUT_UDP_DPORT};
1757 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1759 case RTE_FLOW_FIELD_VXLAN_VNI:
1760 /* not supported yet */
1762 case RTE_FLOW_FIELD_GENEVE_VNI:
1763 /* not supported yet*/
1765 case RTE_FLOW_FIELD_GTP_TEID:
1766 info[idx] = (struct field_modify_info){4, 0,
1767 MLX5_MODI_GTP_TEID};
1769 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1772 case RTE_FLOW_FIELD_TAG:
1774 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1775 data->level, error);
1778 MLX5_ASSERT(reg != REG_NON);
1779 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1780 info[idx] = (struct field_modify_info){4, 0,
1784 rte_cpu_to_be_32(0xffffffff >>
1788 case RTE_FLOW_FIELD_MARK:
1790 uint32_t mark_mask = priv->sh->dv_mark_mask;
1791 uint32_t mark_count = __builtin_popcount(mark_mask);
1792 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1796 MLX5_ASSERT(reg != REG_NON);
1797 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1798 info[idx] = (struct field_modify_info){4, 0,
1801 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1802 (mark_count - width)) & mark_mask);
1805 case RTE_FLOW_FIELD_META:
1807 uint32_t meta_mask = priv->sh->dv_meta_mask;
1808 uint32_t meta_count = __builtin_popcount(meta_mask);
1809 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1812 MLX5_ASSERT(reg != REG_NON);
1813 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1814 info[idx] = (struct field_modify_info){4, 0,
1817 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1818 (meta_count - width)) & meta_mask);
1821 case RTE_FLOW_FIELD_POINTER:
1822 case RTE_FLOW_FIELD_VALUE:
1830 * Convert modify_field action to DV specification.
1833 * Pointer to the rte_eth_dev structure.
1834 * @param[in,out] resource
1835 * Pointer to the modify-header resource.
1837 * Pointer to action specification.
1839 * Attributes of flow that includes this item.
1841 * Pointer to the error structure.
1844 * 0 on success, a negative errno value otherwise and rte_errno is set.
1847 flow_dv_convert_action_modify_field
1848 (struct rte_eth_dev *dev,
1849 struct mlx5_flow_dv_modify_hdr_resource *resource,
1850 const struct rte_flow_action *action,
1851 const struct rte_flow_attr *attr,
1852 struct rte_flow_error *error)
1854 const struct rte_flow_action_modify_field *conf =
1855 (const struct rte_flow_action_modify_field *)(action->conf);
1856 struct rte_flow_item item = {
1860 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1862 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1864 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1865 uint32_t type, meta = 0;
1867 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1868 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1869 type = MLX5_MODIFICATION_TYPE_SET;
1870 /** For SET fill the destination field (field) first. */
1871 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1874 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1875 (void *)(uintptr_t)conf->src.pvalue :
1876 (void *)(uintptr_t)&conf->src.value;
1877 if (conf->dst.field == RTE_FLOW_FIELD_META) {
1878 meta = *(const unaligned_uint32_t *)item.spec;
1879 meta = rte_cpu_to_be_32(meta);
1883 type = MLX5_MODIFICATION_TYPE_COPY;
1884 /** For COPY fill the destination field (dcopy) without mask. */
1885 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1888 /** Then construct the source field (field) with mask. */
1889 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1894 return flow_dv_convert_modify_action(&item,
1895 field, dcopy, resource, type, error);
1899 * Validate MARK item.
1902 * Pointer to the rte_eth_dev structure.
1904 * Item specification.
1906 * Attributes of flow that includes this item.
1908 * Pointer to error structure.
1911 * 0 on success, a negative errno value otherwise and rte_errno is set.
1914 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1915 const struct rte_flow_item *item,
1916 const struct rte_flow_attr *attr __rte_unused,
1917 struct rte_flow_error *error)
1919 struct mlx5_priv *priv = dev->data->dev_private;
1920 struct mlx5_dev_config *config = &priv->config;
1921 const struct rte_flow_item_mark *spec = item->spec;
1922 const struct rte_flow_item_mark *mask = item->mask;
1923 const struct rte_flow_item_mark nic_mask = {
1924 .id = priv->sh->dv_mark_mask,
1928 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1929 return rte_flow_error_set(error, ENOTSUP,
1930 RTE_FLOW_ERROR_TYPE_ITEM, item,
1931 "extended metadata feature"
1933 if (!mlx5_flow_ext_mreg_supported(dev))
1934 return rte_flow_error_set(error, ENOTSUP,
1935 RTE_FLOW_ERROR_TYPE_ITEM, item,
1936 "extended metadata register"
1937 " isn't supported");
1939 return rte_flow_error_set(error, ENOTSUP,
1940 RTE_FLOW_ERROR_TYPE_ITEM, item,
1941 "extended metadata register"
1942 " isn't available");
1943 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1947 return rte_flow_error_set(error, EINVAL,
1948 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1950 "data cannot be empty");
1951 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1952 return rte_flow_error_set(error, EINVAL,
1953 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1955 "mark id exceeds the limit");
1959 return rte_flow_error_set(error, EINVAL,
1960 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1961 "mask cannot be zero");
1963 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1964 (const uint8_t *)&nic_mask,
1965 sizeof(struct rte_flow_item_mark),
1966 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1973 * Validate META item.
1976 * Pointer to the rte_eth_dev structure.
1978 * Item specification.
1980 * Attributes of flow that includes this item.
1982 * Pointer to error structure.
1985 * 0 on success, a negative errno value otherwise and rte_errno is set.
1988 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1989 const struct rte_flow_item *item,
1990 const struct rte_flow_attr *attr,
1991 struct rte_flow_error *error)
1993 struct mlx5_priv *priv = dev->data->dev_private;
1994 struct mlx5_dev_config *config = &priv->config;
1995 const struct rte_flow_item_meta *spec = item->spec;
1996 const struct rte_flow_item_meta *mask = item->mask;
1997 struct rte_flow_item_meta nic_mask = {
2004 return rte_flow_error_set(error, EINVAL,
2005 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2007 "data cannot be empty");
2008 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2009 if (!mlx5_flow_ext_mreg_supported(dev))
2010 return rte_flow_error_set(error, ENOTSUP,
2011 RTE_FLOW_ERROR_TYPE_ITEM, item,
2012 "extended metadata register"
2013 " isn't supported");
2014 reg = flow_dv_get_metadata_reg(dev, attr, error);
2018 return rte_flow_error_set(error, ENOTSUP,
2019 RTE_FLOW_ERROR_TYPE_ITEM, item,
2020 "unavailable extended metadata register");
2022 return rte_flow_error_set(error, ENOTSUP,
2023 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 nic_mask.data = priv->sh->dv_meta_mask;
2030 return rte_flow_error_set(error, ENOTSUP,
2031 RTE_FLOW_ERROR_TYPE_ITEM, item,
2032 "extended metadata feature "
2033 "should be enabled when "
2034 "meta item is requested "
2035 "with e-switch mode ");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2039 "match on metadata for ingress "
2040 "is not supported in legacy "
2044 mask = &rte_flow_item_meta_mask;
2046 return rte_flow_error_set(error, EINVAL,
2047 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2048 "mask cannot be zero");
2050 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2051 (const uint8_t *)&nic_mask,
2052 sizeof(struct rte_flow_item_meta),
2053 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2058 * Validate TAG item.
2061 * Pointer to the rte_eth_dev structure.
2063 * Item specification.
2065 * Attributes of flow that includes this item.
2067 * Pointer to error structure.
2070 * 0 on success, a negative errno value otherwise and rte_errno is set.
2073 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2074 const struct rte_flow_item *item,
2075 const struct rte_flow_attr *attr __rte_unused,
2076 struct rte_flow_error *error)
2078 const struct rte_flow_item_tag *spec = item->spec;
2079 const struct rte_flow_item_tag *mask = item->mask;
2080 const struct rte_flow_item_tag nic_mask = {
2081 .data = RTE_BE32(UINT32_MAX),
2086 if (!mlx5_flow_ext_mreg_supported(dev))
2087 return rte_flow_error_set(error, ENOTSUP,
2088 RTE_FLOW_ERROR_TYPE_ITEM, item,
2089 "extensive metadata register"
2090 " isn't supported");
2092 return rte_flow_error_set(error, EINVAL,
2093 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2095 "data cannot be empty");
2097 mask = &rte_flow_item_tag_mask;
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2101 "mask cannot be zero");
2103 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2104 (const uint8_t *)&nic_mask,
2105 sizeof(struct rte_flow_item_tag),
2106 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2109 if (mask->index != 0xff)
2110 return rte_flow_error_set(error, EINVAL,
2111 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2112 "partial mask for tag index"
2113 " is not supported");
2114 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2117 MLX5_ASSERT(ret != REG_NON);
2122 * Validate vport item.
2125 * Pointer to the rte_eth_dev structure.
2127 * Item specification.
2129 * Attributes of flow that includes this item.
2130 * @param[in] item_flags
2131 * Bit-fields that holds the items detected until now.
2133 * Pointer to error structure.
2136 * 0 on success, a negative errno value otherwise and rte_errno is set.
2139 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2140 const struct rte_flow_item *item,
2141 const struct rte_flow_attr *attr,
2142 uint64_t item_flags,
2143 struct rte_flow_error *error)
2145 const struct rte_flow_item_port_id *spec = item->spec;
2146 const struct rte_flow_item_port_id *mask = item->mask;
2147 const struct rte_flow_item_port_id switch_mask = {
2150 struct mlx5_priv *esw_priv;
2151 struct mlx5_priv *dev_priv;
2154 if (!attr->transfer)
2155 return rte_flow_error_set(error, EINVAL,
2156 RTE_FLOW_ERROR_TYPE_ITEM,
2158 "match on port id is valid only"
2159 " when transfer flag is enabled");
2160 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2161 return rte_flow_error_set(error, ENOTSUP,
2162 RTE_FLOW_ERROR_TYPE_ITEM, item,
2163 "multiple source ports are not"
2166 mask = &switch_mask;
2167 if (mask->id != 0xffffffff)
2168 return rte_flow_error_set(error, ENOTSUP,
2169 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2171 "no support for partial mask on"
2173 ret = mlx5_flow_item_acceptable
2174 (item, (const uint8_t *)mask,
2175 (const uint8_t *)&rte_flow_item_port_id_mask,
2176 sizeof(struct rte_flow_item_port_id),
2177 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2182 if (spec->id == MLX5_PORT_ESW_MGR)
2184 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2186 return rte_flow_error_set(error, rte_errno,
2187 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2188 "failed to obtain E-Switch info for"
2190 dev_priv = mlx5_dev_to_eswitch_info(dev);
2192 return rte_flow_error_set(error, rte_errno,
2193 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2195 "failed to obtain E-Switch info");
2196 if (esw_priv->domain_id != dev_priv->domain_id)
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2199 "cannot match on a port from a"
2200 " different E-Switch");
2205 * Validate VLAN item.
2208 * Item specification.
2209 * @param[in] item_flags
2210 * Bit-fields that holds the items detected until now.
2212 * Ethernet device flow is being created on.
2214 * Pointer to error structure.
2217 * 0 on success, a negative errno value otherwise and rte_errno is set.
2220 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2221 uint64_t item_flags,
2222 struct rte_eth_dev *dev,
2223 struct rte_flow_error *error)
2225 const struct rte_flow_item_vlan *mask = item->mask;
2226 const struct rte_flow_item_vlan nic_mask = {
2227 .tci = RTE_BE16(UINT16_MAX),
2228 .inner_type = RTE_BE16(UINT16_MAX),
2231 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2233 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2234 MLX5_FLOW_LAYER_INNER_L4) :
2235 (MLX5_FLOW_LAYER_OUTER_L3 |
2236 MLX5_FLOW_LAYER_OUTER_L4);
2237 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2238 MLX5_FLOW_LAYER_OUTER_VLAN;
2240 if (item_flags & vlanm)
2241 return rte_flow_error_set(error, EINVAL,
2242 RTE_FLOW_ERROR_TYPE_ITEM, item,
2243 "multiple VLAN layers not supported");
2244 else if ((item_flags & l34m) != 0)
2245 return rte_flow_error_set(error, EINVAL,
2246 RTE_FLOW_ERROR_TYPE_ITEM, item,
2247 "VLAN cannot follow L3/L4 layer");
2249 mask = &rte_flow_item_vlan_mask;
2250 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2251 (const uint8_t *)&nic_mask,
2252 sizeof(struct rte_flow_item_vlan),
2253 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2256 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2257 struct mlx5_priv *priv = dev->data->dev_private;
2259 if (priv->vmwa_context) {
2261 * Non-NULL context means we have a virtual machine
2262 * and SR-IOV enabled, we have to create VLAN interface
2263 * to make hypervisor to setup E-Switch vport
2264 * context correctly. We avoid creating the multiple
2265 * VLAN interfaces, so we cannot support VLAN tag mask.
2267 return rte_flow_error_set(error, EINVAL,
2268 RTE_FLOW_ERROR_TYPE_ITEM,
2270 "VLAN tag mask is not"
2271 " supported in virtual"
2279 * GTP flags are contained in 1 byte of the format:
2280 * -------------------------------------------
2281 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2282 * |-----------------------------------------|
2283 * | value | Version | PT | Res | E | S | PN |
2284 * -------------------------------------------
2286 * Matching is supported only for GTP flags E, S, PN.
2288 #define MLX5_GTP_FLAGS_MASK 0x07
2291 * Validate GTP item.
2294 * Pointer to the rte_eth_dev structure.
2296 * Item specification.
2297 * @param[in] item_flags
2298 * Bit-fields that holds the items detected until now.
2300 * Pointer to error structure.
2303 * 0 on success, a negative errno value otherwise and rte_errno is set.
2306 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2307 const struct rte_flow_item *item,
2308 uint64_t item_flags,
2309 struct rte_flow_error *error)
2311 struct mlx5_priv *priv = dev->data->dev_private;
2312 const struct rte_flow_item_gtp *spec = item->spec;
2313 const struct rte_flow_item_gtp *mask = item->mask;
2314 const struct rte_flow_item_gtp nic_mask = {
2315 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2317 .teid = RTE_BE32(0xffffffff),
2320 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2321 return rte_flow_error_set(error, ENOTSUP,
2322 RTE_FLOW_ERROR_TYPE_ITEM, item,
2323 "GTP support is not enabled");
2324 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2325 return rte_flow_error_set(error, ENOTSUP,
2326 RTE_FLOW_ERROR_TYPE_ITEM, item,
2327 "multiple tunnel layers not"
2329 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2330 return rte_flow_error_set(error, EINVAL,
2331 RTE_FLOW_ERROR_TYPE_ITEM, item,
2332 "no outer UDP layer found");
2334 mask = &rte_flow_item_gtp_mask;
2335 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "Match is supported for GTP"
2340 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2341 (const uint8_t *)&nic_mask,
2342 sizeof(struct rte_flow_item_gtp),
2343 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2347 * Validate GTP PSC item.
2350 * Item specification.
2351 * @param[in] last_item
2352 * Previous validated item in the pattern items.
2353 * @param[in] gtp_item
2354 * Previous GTP item specification.
2356 * Pointer to flow attributes.
2358 * Pointer to error structure.
2361 * 0 on success, a negative errno value otherwise and rte_errno is set.
2364 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2366 const struct rte_flow_item *gtp_item,
2367 const struct rte_flow_attr *attr,
2368 struct rte_flow_error *error)
2370 const struct rte_flow_item_gtp *gtp_spec;
2371 const struct rte_flow_item_gtp *gtp_mask;
2372 const struct rte_flow_item_gtp_psc *mask;
2373 const struct rte_flow_item_gtp_psc nic_mask = {
2378 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2379 return rte_flow_error_set
2380 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2381 "GTP PSC item must be preceded with GTP item");
2382 gtp_spec = gtp_item->spec;
2383 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2384 /* GTP spec and E flag is requested to match zero. */
2386 (gtp_mask->v_pt_rsv_flags &
2387 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2388 return rte_flow_error_set
2389 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2390 "GTP E flag must be 1 to match GTP PSC");
2391 /* Check the flow is not created in group zero. */
2392 if (!attr->transfer && !attr->group)
2393 return rte_flow_error_set
2394 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2395 "GTP PSC is not supported for group 0");
2396 /* GTP spec is here and E flag is requested to match zero. */
2399 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2400 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2401 (const uint8_t *)&nic_mask,
2402 sizeof(struct rte_flow_item_gtp_psc),
2403 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2407 * Validate IPV4 item.
2408 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2409 * add specific validation of fragment_offset field,
2412 * Item specification.
2413 * @param[in] item_flags
2414 * Bit-fields that holds the items detected until now.
2416 * Pointer to error structure.
2419 * 0 on success, a negative errno value otherwise and rte_errno is set.
2422 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2423 const struct rte_flow_item *item,
2424 uint64_t item_flags, uint64_t last_item,
2425 uint16_t ether_type, struct rte_flow_error *error)
2428 struct mlx5_priv *priv = dev->data->dev_private;
2429 const struct rte_flow_item_ipv4 *spec = item->spec;
2430 const struct rte_flow_item_ipv4 *last = item->last;
2431 const struct rte_flow_item_ipv4 *mask = item->mask;
2432 rte_be16_t fragment_offset_spec = 0;
2433 rte_be16_t fragment_offset_last = 0;
2434 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2436 .src_addr = RTE_BE32(0xffffffff),
2437 .dst_addr = RTE_BE32(0xffffffff),
2438 .type_of_service = 0xff,
2439 .fragment_offset = RTE_BE16(0xffff),
2440 .next_proto_id = 0xff,
2441 .time_to_live = 0xff,
2445 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2446 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2447 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2448 priv->config.hca_attr.inner_ipv4_ihl;
2450 return rte_flow_error_set(error, ENOTSUP,
2451 RTE_FLOW_ERROR_TYPE_ITEM,
2453 "IPV4 ihl offload not supported");
2454 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2456 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2457 ether_type, &nic_ipv4_mask,
2458 MLX5_ITEM_RANGE_ACCEPTED, error);
2462 fragment_offset_spec = spec->hdr.fragment_offset &
2463 mask->hdr.fragment_offset;
2464 if (!fragment_offset_spec)
2467 * spec and mask are valid, enforce using full mask to make sure the
2468 * complete value is used correctly.
2470 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2471 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2472 return rte_flow_error_set(error, EINVAL,
2473 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2474 item, "must use full mask for"
2475 " fragment_offset");
2477 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2478 * indicating this is 1st fragment of fragmented packet.
2479 * This is not yet supported in MLX5, return appropriate error message.
2481 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2482 return rte_flow_error_set(error, ENOTSUP,
2483 RTE_FLOW_ERROR_TYPE_ITEM, item,
2484 "match on first fragment not "
2486 if (fragment_offset_spec && !last)
2487 return rte_flow_error_set(error, ENOTSUP,
2488 RTE_FLOW_ERROR_TYPE_ITEM, item,
2489 "specified value not supported");
2490 /* spec and last are valid, validate the specified range. */
2491 fragment_offset_last = last->hdr.fragment_offset &
2492 mask->hdr.fragment_offset;
2494 * Match on fragment_offset spec 0x2001 and last 0x3fff
2495 * means MF is 1 and frag-offset is > 0.
2496 * This packet is fragment 2nd and onward, excluding last.
2497 * This is not yet supported in MLX5, return appropriate
2500 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2501 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2504 last, "match on following "
2505 "fragments not supported");
2507 * Match on fragment_offset spec 0x0001 and last 0x1fff
2508 * means MF is 0 and frag-offset is > 0.
2509 * This packet is last fragment of fragmented packet.
2510 * This is not yet supported in MLX5, return appropriate
2513 if (fragment_offset_spec == RTE_BE16(1) &&
2514 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2515 return rte_flow_error_set(error, ENOTSUP,
2516 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2517 last, "match on last "
2518 "fragment not supported");
2520 * Match on fragment_offset spec 0x0001 and last 0x3fff
2521 * means MF and/or frag-offset is not 0.
2522 * This is a fragmented packet.
2523 * Other range values are invalid and rejected.
2525 if (!(fragment_offset_spec == RTE_BE16(1) &&
2526 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2527 return rte_flow_error_set(error, ENOTSUP,
2528 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2529 "specified range not supported");
2534 * Validate IPV6 fragment extension item.
2537 * Item specification.
2538 * @param[in] item_flags
2539 * Bit-fields that holds the items detected until now.
2541 * Pointer to error structure.
2544 * 0 on success, a negative errno value otherwise and rte_errno is set.
2547 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2548 uint64_t item_flags,
2549 struct rte_flow_error *error)
2551 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2552 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2553 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2554 rte_be16_t frag_data_spec = 0;
2555 rte_be16_t frag_data_last = 0;
2556 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2557 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2558 MLX5_FLOW_LAYER_OUTER_L4;
2560 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2562 .next_header = 0xff,
2563 .frag_data = RTE_BE16(0xffff),
2567 if (item_flags & l4m)
2568 return rte_flow_error_set(error, EINVAL,
2569 RTE_FLOW_ERROR_TYPE_ITEM, item,
2570 "ipv6 fragment extension item cannot "
2572 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2573 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2574 return rte_flow_error_set(error, EINVAL,
2575 RTE_FLOW_ERROR_TYPE_ITEM, item,
2576 "ipv6 fragment extension item must "
2577 "follow ipv6 item");
2579 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2580 if (!frag_data_spec)
2583 * spec and mask are valid, enforce using full mask to make sure the
2584 * complete value is used correctly.
2586 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2587 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2588 return rte_flow_error_set(error, EINVAL,
2589 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2590 item, "must use full mask for"
2593 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2594 * This is 1st fragment of fragmented packet.
2596 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2597 return rte_flow_error_set(error, ENOTSUP,
2598 RTE_FLOW_ERROR_TYPE_ITEM, item,
2599 "match on first fragment not "
2601 if (frag_data_spec && !last)
2602 return rte_flow_error_set(error, EINVAL,
2603 RTE_FLOW_ERROR_TYPE_ITEM, item,
2604 "specified value not supported");
2605 ret = mlx5_flow_item_acceptable
2606 (item, (const uint8_t *)mask,
2607 (const uint8_t *)&nic_mask,
2608 sizeof(struct rte_flow_item_ipv6_frag_ext),
2609 MLX5_ITEM_RANGE_ACCEPTED, error);
2612 /* spec and last are valid, validate the specified range. */
2613 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2615 * Match on frag_data spec 0x0009 and last 0xfff9
2616 * means M is 1 and frag-offset is > 0.
2617 * This packet is fragment 2nd and onward, excluding last.
2618 * This is not yet supported in MLX5, return appropriate
2621 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2622 RTE_IPV6_EHDR_MF_MASK) &&
2623 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2624 return rte_flow_error_set(error, ENOTSUP,
2625 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2626 last, "match on following "
2627 "fragments not supported");
2629 * Match on frag_data spec 0x0008 and last 0xfff8
2630 * means M is 0 and frag-offset is > 0.
2631 * This packet is last fragment of fragmented packet.
2632 * This is not yet supported in MLX5, return appropriate
2635 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2636 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2637 return rte_flow_error_set(error, ENOTSUP,
2638 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2639 last, "match on last "
2640 "fragment not supported");
2641 /* Other range values are invalid and rejected. */
2642 return rte_flow_error_set(error, EINVAL,
2643 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2644 "specified range not supported");
2648 * Validate ASO CT item.
2651 * Pointer to the rte_eth_dev structure.
2653 * Item specification.
2654 * @param[in] item_flags
2655 * Pointer to bit-fields that holds the items detected until now.
2657 * Pointer to error structure.
2660 * 0 on success, a negative errno value otherwise and rte_errno is set.
2663 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2664 const struct rte_flow_item *item,
2665 uint64_t *item_flags,
2666 struct rte_flow_error *error)
2668 const struct rte_flow_item_conntrack *spec = item->spec;
2669 const struct rte_flow_item_conntrack *mask = item->mask;
2673 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2674 return rte_flow_error_set(error, EINVAL,
2675 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2676 "Only one CT is supported");
2678 mask = &rte_flow_item_conntrack_mask;
2679 flags = spec->flags & mask->flags;
2680 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2681 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2682 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2683 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2684 return rte_flow_error_set(error, EINVAL,
2685 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2686 "Conflict status bits");
2687 /* State change also needs to be considered. */
2688 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2693 * Validate the pop VLAN action.
2696 * Pointer to the rte_eth_dev structure.
2697 * @param[in] action_flags
2698 * Holds the actions detected until now.
2700 * Pointer to the pop vlan action.
2701 * @param[in] item_flags
2702 * The items found in this flow rule.
2704 * Pointer to flow attributes.
2706 * Pointer to error structure.
2709 * 0 on success, a negative errno value otherwise and rte_errno is set.
2712 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2713 uint64_t action_flags,
2714 const struct rte_flow_action *action,
2715 uint64_t item_flags,
2716 const struct rte_flow_attr *attr,
2717 struct rte_flow_error *error)
2719 const struct mlx5_priv *priv = dev->data->dev_private;
2720 struct mlx5_dev_ctx_shared *sh = priv->sh;
2721 bool direction_error = false;
2723 if (!priv->sh->pop_vlan_action)
2724 return rte_flow_error_set(error, ENOTSUP,
2725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2727 "pop vlan action is not supported");
2728 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2729 if (attr->transfer) {
2730 bool fdb_tx = priv->representor_id != UINT16_MAX;
2731 bool is_cx5 = sh->steering_format_version ==
2732 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2734 if (fdb_tx && is_cx5)
2735 direction_error = true;
2736 } else if (attr->egress) {
2737 direction_error = true;
2739 if (direction_error)
2740 return rte_flow_error_set(error, ENOTSUP,
2741 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2743 "pop vlan action not supported for egress");
2744 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2745 return rte_flow_error_set(error, ENOTSUP,
2746 RTE_FLOW_ERROR_TYPE_ACTION, action,
2747 "no support for multiple VLAN "
2749 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2750 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2751 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2752 return rte_flow_error_set(error, ENOTSUP,
2753 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2755 "cannot pop vlan after decap without "
2756 "match on inner vlan in the flow");
2757 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2758 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2759 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2763 "cannot pop vlan without a "
2764 "match on (outer) vlan in the flow");
2765 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2766 return rte_flow_error_set(error, EINVAL,
2767 RTE_FLOW_ERROR_TYPE_ACTION, action,
2768 "wrong action order, port_id should "
2769 "be after pop VLAN action");
2770 if (!attr->transfer && priv->representor)
2771 return rte_flow_error_set(error, ENOTSUP,
2772 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2773 "pop vlan action for VF representor "
2774 "not supported on NIC table");
2779 * Get VLAN default info from vlan match info.
2782 * the list of item specifications.
2784 * pointer VLAN info to fill to.
2787 * 0 on success, a negative errno value otherwise and rte_errno is set.
2790 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2791 struct rte_vlan_hdr *vlan)
2793 const struct rte_flow_item_vlan nic_mask = {
2794 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2795 MLX5DV_FLOW_VLAN_VID_MASK),
2796 .inner_type = RTE_BE16(0xffff),
2801 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2802 int type = items->type;
2804 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2805 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2808 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2809 const struct rte_flow_item_vlan *vlan_m = items->mask;
2810 const struct rte_flow_item_vlan *vlan_v = items->spec;
2812 /* If VLAN item in pattern doesn't contain data, return here. */
2817 /* Only full match values are accepted */
2818 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2819 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2820 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2822 rte_be_to_cpu_16(vlan_v->tci &
2823 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2825 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2826 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2827 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2829 rte_be_to_cpu_16(vlan_v->tci &
2830 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2832 if (vlan_m->inner_type == nic_mask.inner_type)
2833 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2834 vlan_m->inner_type);
2839 * Validate the push VLAN action.
2842 * Pointer to the rte_eth_dev structure.
2843 * @param[in] action_flags
2844 * Holds the actions detected until now.
2845 * @param[in] item_flags
2846 * The items found in this flow rule.
2848 * Pointer to the action structure.
2850 * Pointer to flow attributes
2852 * Pointer to error structure.
2855 * 0 on success, a negative errno value otherwise and rte_errno is set.
2858 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2859 uint64_t action_flags,
2860 const struct rte_flow_item_vlan *vlan_m,
2861 const struct rte_flow_action *action,
2862 const struct rte_flow_attr *attr,
2863 struct rte_flow_error *error)
2865 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2866 const struct mlx5_priv *priv = dev->data->dev_private;
2867 struct mlx5_dev_ctx_shared *sh = priv->sh;
2868 bool direction_error = false;
2870 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2871 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2872 return rte_flow_error_set(error, EINVAL,
2873 RTE_FLOW_ERROR_TYPE_ACTION, action,
2874 "invalid vlan ethertype");
2875 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2876 return rte_flow_error_set(error, EINVAL,
2877 RTE_FLOW_ERROR_TYPE_ACTION, action,
2878 "wrong action order, port_id should "
2879 "be after push VLAN");
2880 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2881 if (attr->transfer) {
2882 bool fdb_tx = priv->representor_id != UINT16_MAX;
2883 bool is_cx5 = sh->steering_format_version ==
2884 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2886 if (!fdb_tx && is_cx5)
2887 direction_error = true;
2888 } else if (attr->ingress) {
2889 direction_error = true;
2891 if (direction_error)
2892 return rte_flow_error_set(error, ENOTSUP,
2893 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2895 "push vlan action not supported for ingress");
2896 if (!attr->transfer && priv->representor)
2897 return rte_flow_error_set(error, ENOTSUP,
2898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2899 "push vlan action for VF representor "
2900 "not supported on NIC table");
2902 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2903 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2904 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2905 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2906 !(mlx5_flow_find_action
2907 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2908 return rte_flow_error_set(error, EINVAL,
2909 RTE_FLOW_ERROR_TYPE_ACTION, action,
2910 "not full match mask on VLAN PCP and "
2911 "there is no of_set_vlan_pcp action, "
2912 "push VLAN action cannot figure out "
2915 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2916 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2917 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2918 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2919 !(mlx5_flow_find_action
2920 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2921 return rte_flow_error_set(error, EINVAL,
2922 RTE_FLOW_ERROR_TYPE_ACTION, action,
2923 "not full match mask on VLAN VID and "
2924 "there is no of_set_vlan_vid action, "
2925 "push VLAN action cannot figure out "
2932 * Validate the set VLAN PCP.
2934 * @param[in] action_flags
2935 * Holds the actions detected until now.
2936 * @param[in] actions
2937 * Pointer to the list of actions remaining in the flow rule.
2939 * Pointer to error structure.
2942 * 0 on success, a negative errno value otherwise and rte_errno is set.
2945 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2946 const struct rte_flow_action actions[],
2947 struct rte_flow_error *error)
2949 const struct rte_flow_action *action = actions;
2950 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2952 if (conf->vlan_pcp > 7)
2953 return rte_flow_error_set(error, EINVAL,
2954 RTE_FLOW_ERROR_TYPE_ACTION, action,
2955 "VLAN PCP value is too big");
2956 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2957 return rte_flow_error_set(error, ENOTSUP,
2958 RTE_FLOW_ERROR_TYPE_ACTION, action,
2959 "set VLAN PCP action must follow "
2960 "the push VLAN action");
2961 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2962 return rte_flow_error_set(error, ENOTSUP,
2963 RTE_FLOW_ERROR_TYPE_ACTION, action,
2964 "Multiple VLAN PCP modification are "
2966 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2967 return rte_flow_error_set(error, EINVAL,
2968 RTE_FLOW_ERROR_TYPE_ACTION, action,
2969 "wrong action order, port_id should "
2970 "be after set VLAN PCP");
2975 * Validate the set VLAN VID.
2977 * @param[in] item_flags
2978 * Holds the items detected in this rule.
2979 * @param[in] action_flags
2980 * Holds the actions detected until now.
2981 * @param[in] actions
2982 * Pointer to the list of actions remaining in the flow rule.
2984 * Pointer to error structure.
2987 * 0 on success, a negative errno value otherwise and rte_errno is set.
2990 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2991 uint64_t action_flags,
2992 const struct rte_flow_action actions[],
2993 struct rte_flow_error *error)
2995 const struct rte_flow_action *action = actions;
2996 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2998 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2999 return rte_flow_error_set(error, EINVAL,
3000 RTE_FLOW_ERROR_TYPE_ACTION, action,
3001 "VLAN VID value is too big");
3002 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3003 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3004 return rte_flow_error_set(error, ENOTSUP,
3005 RTE_FLOW_ERROR_TYPE_ACTION, action,
3006 "set VLAN VID action must follow push"
3007 " VLAN action or match on VLAN item");
3008 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3009 return rte_flow_error_set(error, ENOTSUP,
3010 RTE_FLOW_ERROR_TYPE_ACTION, action,
3011 "Multiple VLAN VID modifications are "
3013 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "wrong action order, port_id should "
3017 "be after set VLAN VID");
3022 * Validate the FLAG action.
3025 * Pointer to the rte_eth_dev structure.
3026 * @param[in] action_flags
3027 * Holds the actions detected until now.
3029 * Pointer to flow attributes
3031 * Pointer to error structure.
3034 * 0 on success, a negative errno value otherwise and rte_errno is set.
3037 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3038 uint64_t action_flags,
3039 const struct rte_flow_attr *attr,
3040 struct rte_flow_error *error)
3042 struct mlx5_priv *priv = dev->data->dev_private;
3043 struct mlx5_dev_config *config = &priv->config;
3046 /* Fall back if no extended metadata register support. */
3047 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3048 return mlx5_flow_validate_action_flag(action_flags, attr,
3050 /* Extensive metadata mode requires registers. */
3051 if (!mlx5_flow_ext_mreg_supported(dev))
3052 return rte_flow_error_set(error, ENOTSUP,
3053 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3054 "no metadata registers "
3055 "to support flag action");
3056 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3057 return rte_flow_error_set(error, ENOTSUP,
3058 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3059 "extended metadata register"
3060 " isn't available");
3061 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3064 MLX5_ASSERT(ret > 0);
3065 if (action_flags & MLX5_FLOW_ACTION_MARK)
3066 return rte_flow_error_set(error, EINVAL,
3067 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3068 "can't mark and flag in same flow");
3069 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3073 " actions in same flow");
3078 * Validate MARK action.
3081 * Pointer to the rte_eth_dev structure.
3083 * Pointer to action.
3084 * @param[in] action_flags
3085 * Holds the actions detected until now.
3087 * Pointer to flow attributes
3089 * Pointer to error structure.
3092 * 0 on success, a negative errno value otherwise and rte_errno is set.
3095 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3096 const struct rte_flow_action *action,
3097 uint64_t action_flags,
3098 const struct rte_flow_attr *attr,
3099 struct rte_flow_error *error)
3101 struct mlx5_priv *priv = dev->data->dev_private;
3102 struct mlx5_dev_config *config = &priv->config;
3103 const struct rte_flow_action_mark *mark = action->conf;
3106 if (is_tunnel_offload_active(dev))
3107 return rte_flow_error_set(error, ENOTSUP,
3108 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3110 "if tunnel offload active");
3111 /* Fall back if no extended metadata register support. */
3112 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3113 return mlx5_flow_validate_action_mark(action, action_flags,
3115 /* Extensive metadata mode requires registers. */
3116 if (!mlx5_flow_ext_mreg_supported(dev))
3117 return rte_flow_error_set(error, ENOTSUP,
3118 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3119 "no metadata registers "
3120 "to support mark action");
3121 if (!priv->sh->dv_mark_mask)
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3124 "extended metadata register"
3125 " isn't available");
3126 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3129 MLX5_ASSERT(ret > 0);
3131 return rte_flow_error_set(error, EINVAL,
3132 RTE_FLOW_ERROR_TYPE_ACTION, action,
3133 "configuration cannot be null");
3134 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3135 return rte_flow_error_set(error, EINVAL,
3136 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3138 "mark id exceeds the limit");
3139 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3140 return rte_flow_error_set(error, EINVAL,
3141 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3142 "can't flag and mark in same flow");
3143 if (action_flags & MLX5_FLOW_ACTION_MARK)
3144 return rte_flow_error_set(error, EINVAL,
3145 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3146 "can't have 2 mark actions in same"
3152 * Validate SET_META action.
3155 * Pointer to the rte_eth_dev structure.
3157 * Pointer to the action structure.
3158 * @param[in] action_flags
3159 * Holds the actions detected until now.
3161 * Pointer to flow attributes
3163 * Pointer to error structure.
3166 * 0 on success, a negative errno value otherwise and rte_errno is set.
3169 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3170 const struct rte_flow_action *action,
3171 uint64_t action_flags __rte_unused,
3172 const struct rte_flow_attr *attr,
3173 struct rte_flow_error *error)
3175 struct mlx5_priv *priv = dev->data->dev_private;
3176 struct mlx5_dev_config *config = &priv->config;
3177 const struct rte_flow_action_set_meta *conf;
3178 uint32_t nic_mask = UINT32_MAX;
3181 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3182 !mlx5_flow_ext_mreg_supported(dev))
3183 return rte_flow_error_set(error, ENOTSUP,
3184 RTE_FLOW_ERROR_TYPE_ACTION, action,
3185 "extended metadata register"
3186 " isn't supported");
3187 reg = flow_dv_get_metadata_reg(dev, attr, error);
3191 return rte_flow_error_set(error, ENOTSUP,
3192 RTE_FLOW_ERROR_TYPE_ACTION, action,
3193 "unavailable extended metadata register");
3194 if (reg != REG_A && reg != REG_B) {
3195 struct mlx5_priv *priv = dev->data->dev_private;
3197 nic_mask = priv->sh->dv_meta_mask;
3199 if (!(action->conf))
3200 return rte_flow_error_set(error, EINVAL,
3201 RTE_FLOW_ERROR_TYPE_ACTION, action,
3202 "configuration cannot be null");
3203 conf = (const struct rte_flow_action_set_meta *)action->conf;
3205 return rte_flow_error_set(error, EINVAL,
3206 RTE_FLOW_ERROR_TYPE_ACTION, action,
3207 "zero mask doesn't have any effect");
3208 if (conf->mask & ~nic_mask)
3209 return rte_flow_error_set(error, EINVAL,
3210 RTE_FLOW_ERROR_TYPE_ACTION, action,
3211 "meta data must be within reg C0");
3216 * Validate SET_TAG action.
3219 * Pointer to the rte_eth_dev structure.
3221 * Pointer to the action structure.
3222 * @param[in] action_flags
3223 * Holds the actions detected until now.
3225 * Pointer to flow attributes
3227 * Pointer to error structure.
3230 * 0 on success, a negative errno value otherwise and rte_errno is set.
3233 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3234 const struct rte_flow_action *action,
3235 uint64_t action_flags,
3236 const struct rte_flow_attr *attr,
3237 struct rte_flow_error *error)
3239 const struct rte_flow_action_set_tag *conf;
3240 const uint64_t terminal_action_flags =
3241 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3242 MLX5_FLOW_ACTION_RSS;
3245 if (!mlx5_flow_ext_mreg_supported(dev))
3246 return rte_flow_error_set(error, ENOTSUP,
3247 RTE_FLOW_ERROR_TYPE_ACTION, action,
3248 "extensive metadata register"
3249 " isn't supported");
3250 if (!(action->conf))
3251 return rte_flow_error_set(error, EINVAL,
3252 RTE_FLOW_ERROR_TYPE_ACTION, action,
3253 "configuration cannot be null");
3254 conf = (const struct rte_flow_action_set_tag *)action->conf;
3256 return rte_flow_error_set(error, EINVAL,
3257 RTE_FLOW_ERROR_TYPE_ACTION, action,
3258 "zero mask doesn't have any effect");
3259 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3262 if (!attr->transfer && attr->ingress &&
3263 (action_flags & terminal_action_flags))
3264 return rte_flow_error_set(error, EINVAL,
3265 RTE_FLOW_ERROR_TYPE_ACTION, action,
3266 "set_tag has no effect"
3267 " with terminal actions");
3272 * Validate count action.
3275 * Pointer to rte_eth_dev structure.
3277 * Indicator if action is shared.
3278 * @param[in] action_flags
3279 * Holds the actions detected until now.
3281 * Pointer to error structure.
3284 * 0 on success, a negative errno value otherwise and rte_errno is set.
3287 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3288 uint64_t action_flags,
3289 struct rte_flow_error *error)
3291 struct mlx5_priv *priv = dev->data->dev_private;
3293 if (!priv->sh->devx)
3295 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3296 return rte_flow_error_set(error, EINVAL,
3297 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3298 "duplicate count actions set");
3299 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3300 !priv->sh->flow_hit_aso_en)
3301 return rte_flow_error_set(error, EINVAL,
3302 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3303 "old age and shared count combination is not supported");
3304 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3308 return rte_flow_error_set
3310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3312 "count action not supported");
3316 * Validate the L2 encap action.
3319 * Pointer to the rte_eth_dev structure.
3320 * @param[in] action_flags
3321 * Holds the actions detected until now.
3323 * Pointer to the action structure.
3325 * Pointer to flow attributes.
3327 * Pointer to error structure.
3330 * 0 on success, a negative errno value otherwise and rte_errno is set.
3333 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3334 uint64_t action_flags,
3335 const struct rte_flow_action *action,
3336 const struct rte_flow_attr *attr,
3337 struct rte_flow_error *error)
3339 const struct mlx5_priv *priv = dev->data->dev_private;
3341 if (!(action->conf))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION, action,
3344 "configuration cannot be null");
3345 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3346 return rte_flow_error_set(error, EINVAL,
3347 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3348 "can only have a single encap action "
3350 if (!attr->transfer && priv->representor)
3351 return rte_flow_error_set(error, ENOTSUP,
3352 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3353 "encap action for VF representor "
3354 "not supported on NIC table");
3359 * Validate a decap action.
3362 * Pointer to the rte_eth_dev structure.
3363 * @param[in] action_flags
3364 * Holds the actions detected until now.
3366 * Pointer to the action structure.
3367 * @param[in] item_flags
3368 * Holds the items detected.
3370 * Pointer to flow attributes
3372 * Pointer to error structure.
3375 * 0 on success, a negative errno value otherwise and rte_errno is set.
3378 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3379 uint64_t action_flags,
3380 const struct rte_flow_action *action,
3381 const uint64_t item_flags,
3382 const struct rte_flow_attr *attr,
3383 struct rte_flow_error *error)
3385 const struct mlx5_priv *priv = dev->data->dev_private;
3387 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3388 !priv->config.decap_en)
3389 return rte_flow_error_set(error, ENOTSUP,
3390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3391 "decap is not enabled");
3392 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3393 return rte_flow_error_set(error, ENOTSUP,
3394 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3396 MLX5_FLOW_ACTION_DECAP ? "can only "
3397 "have a single decap action" : "decap "
3398 "after encap is not supported");
3399 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3400 return rte_flow_error_set(error, EINVAL,
3401 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3402 "can't have decap action after"
3405 return rte_flow_error_set(error, ENOTSUP,
3406 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3408 "decap action not supported for "
3410 if (!attr->transfer && priv->representor)
3411 return rte_flow_error_set(error, ENOTSUP,
3412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3413 "decap action for VF representor "
3414 "not supported on NIC table");
3415 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3416 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3417 return rte_flow_error_set(error, ENOTSUP,
3418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3419 "VXLAN item should be present for VXLAN decap");
3423 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3426 * Validate the raw encap and decap actions.
3429 * Pointer to the rte_eth_dev structure.
3431 * Pointer to the decap action.
3433 * Pointer to the encap action.
3435 * Pointer to flow attributes
3436 * @param[in/out] action_flags
3437 * Holds the actions detected until now.
3438 * @param[out] actions_n
3439 * pointer to the number of actions counter.
3441 * Pointer to the action structure.
3442 * @param[in] item_flags
3443 * Holds the items detected.
3445 * Pointer to error structure.
3448 * 0 on success, a negative errno value otherwise and rte_errno is set.
3451 flow_dv_validate_action_raw_encap_decap
3452 (struct rte_eth_dev *dev,
3453 const struct rte_flow_action_raw_decap *decap,
3454 const struct rte_flow_action_raw_encap *encap,
3455 const struct rte_flow_attr *attr, uint64_t *action_flags,
3456 int *actions_n, const struct rte_flow_action *action,
3457 uint64_t item_flags, struct rte_flow_error *error)
3459 const struct mlx5_priv *priv = dev->data->dev_private;
3462 if (encap && (!encap->size || !encap->data))
3463 return rte_flow_error_set(error, EINVAL,
3464 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3465 "raw encap data cannot be empty");
3466 if (decap && encap) {
3467 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3468 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3471 else if (encap->size <=
3472 MLX5_ENCAPSULATION_DECISION_SIZE &&
3474 MLX5_ENCAPSULATION_DECISION_SIZE)
3477 else if (encap->size >
3478 MLX5_ENCAPSULATION_DECISION_SIZE &&
3480 MLX5_ENCAPSULATION_DECISION_SIZE)
3481 /* 2 L2 actions: encap and decap. */
3484 return rte_flow_error_set(error,
3486 RTE_FLOW_ERROR_TYPE_ACTION,
3487 NULL, "unsupported too small "
3488 "raw decap and too small raw "
3489 "encap combination");
3492 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3493 item_flags, attr, error);
3496 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3500 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3501 return rte_flow_error_set(error, ENOTSUP,
3502 RTE_FLOW_ERROR_TYPE_ACTION,
3504 "small raw encap size");
3505 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3506 return rte_flow_error_set(error, EINVAL,
3507 RTE_FLOW_ERROR_TYPE_ACTION,
3509 "more than one encap action");
3510 if (!attr->transfer && priv->representor)
3511 return rte_flow_error_set
3513 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3514 "encap action for VF representor "
3515 "not supported on NIC table");
3516 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3523 * Validate the ASO CT action.
3526 * Pointer to the rte_eth_dev structure.
3527 * @param[in] action_flags
3528 * Holds the actions detected until now.
3529 * @param[in] item_flags
3530 * The items found in this flow rule.
3532 * Pointer to flow attributes.
3534 * Pointer to error structure.
3537 * 0 on success, a negative errno value otherwise and rte_errno is set.
3540 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3541 uint64_t action_flags,
3542 uint64_t item_flags,
3543 const struct rte_flow_attr *attr,
3544 struct rte_flow_error *error)
3548 if (attr->group == 0 && !attr->transfer)
3549 return rte_flow_error_set(error, ENOTSUP,
3550 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3552 "Only support non-root table");
3553 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3554 return rte_flow_error_set(error, ENOTSUP,
3555 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3556 "CT cannot follow a fate action");
3557 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3558 (action_flags & MLX5_FLOW_ACTION_AGE))
3559 return rte_flow_error_set(error, EINVAL,
3560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3561 "Only one ASO action is supported");
3562 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3563 return rte_flow_error_set(error, EINVAL,
3564 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3565 "Encap cannot exist before CT");
3566 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3567 return rte_flow_error_set(error, EINVAL,
3568 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3569 "Not a outer TCP packet");
3574 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3575 struct mlx5_list_entry *entry, void *cb_ctx)
3577 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3578 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3579 struct mlx5_flow_dv_encap_decap_resource *resource;
3581 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3583 if (resource->reformat_type == ctx_resource->reformat_type &&
3584 resource->ft_type == ctx_resource->ft_type &&
3585 resource->flags == ctx_resource->flags &&
3586 resource->size == ctx_resource->size &&
3587 !memcmp((const void *)resource->buf,
3588 (const void *)ctx_resource->buf,
3594 struct mlx5_list_entry *
3595 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3597 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3598 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3599 struct mlx5dv_dr_domain *domain;
3600 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3601 struct mlx5_flow_dv_encap_decap_resource *resource;
3605 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3606 domain = sh->fdb_domain;
3607 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3608 domain = sh->rx_domain;
3610 domain = sh->tx_domain;
3611 /* Register new encap/decap resource. */
3612 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3614 rte_flow_error_set(ctx->error, ENOMEM,
3615 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3616 "cannot allocate resource memory");
3619 *resource = *ctx_resource;
3620 resource->idx = idx;
3621 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3625 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3626 rte_flow_error_set(ctx->error, ENOMEM,
3627 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3628 NULL, "cannot create action");
3632 return &resource->entry;
3635 struct mlx5_list_entry *
3636 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3639 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3640 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3641 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3644 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3646 if (!cache_resource) {
3647 rte_flow_error_set(ctx->error, ENOMEM,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3649 "cannot allocate resource memory");
3652 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3653 cache_resource->idx = idx;
3654 return &cache_resource->entry;
3658 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3660 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3661 struct mlx5_flow_dv_encap_decap_resource *res =
3662 container_of(entry, typeof(*res), entry);
3664 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3668 * Find existing encap/decap resource or create and register a new one.
3670 * @param[in, out] dev
3671 * Pointer to rte_eth_dev structure.
3672 * @param[in, out] resource
3673 * Pointer to encap/decap resource.
3674 * @parm[in, out] dev_flow
3675 * Pointer to the dev_flow.
3677 * pointer to error structure.
3680 * 0 on success otherwise -errno and errno is set.
3683 flow_dv_encap_decap_resource_register
3684 (struct rte_eth_dev *dev,
3685 struct mlx5_flow_dv_encap_decap_resource *resource,
3686 struct mlx5_flow *dev_flow,
3687 struct rte_flow_error *error)
3689 struct mlx5_priv *priv = dev->data->dev_private;
3690 struct mlx5_dev_ctx_shared *sh = priv->sh;
3691 struct mlx5_list_entry *entry;
3695 uint32_t refmt_type:8;
3697 * Header reformat actions can be shared between
3698 * non-root tables. One bit to indicate non-root
3702 uint32_t reserve:15;
3705 } encap_decap_key = {
3707 .ft_type = resource->ft_type,
3708 .refmt_type = resource->reformat_type,
3709 .is_root = !!dev_flow->dv.group,
3713 struct mlx5_flow_cb_ctx ctx = {
3717 struct mlx5_hlist *encaps_decaps;
3720 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3722 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3724 flow_dv_encap_decap_create_cb,
3725 flow_dv_encap_decap_match_cb,
3726 flow_dv_encap_decap_remove_cb,
3727 flow_dv_encap_decap_clone_cb,
3728 flow_dv_encap_decap_clone_free_cb);
3729 if (unlikely(!encaps_decaps))
3731 resource->flags = dev_flow->dv.group ? 0 : 1;
3732 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3733 sizeof(encap_decap_key.v32), 0);
3734 if (resource->reformat_type !=
3735 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3737 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3738 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3741 resource = container_of(entry, typeof(*resource), entry);
3742 dev_flow->dv.encap_decap = resource;
3743 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3748 * Find existing table jump resource or create and register a new one.
3750 * @param[in, out] dev
3751 * Pointer to rte_eth_dev structure.
3752 * @param[in, out] tbl
3753 * Pointer to flow table resource.
3754 * @parm[in, out] dev_flow
3755 * Pointer to the dev_flow.
3757 * pointer to error structure.
3760 * 0 on success otherwise -errno and errno is set.
3763 flow_dv_jump_tbl_resource_register
3764 (struct rte_eth_dev *dev __rte_unused,
3765 struct mlx5_flow_tbl_resource *tbl,
3766 struct mlx5_flow *dev_flow,
3767 struct rte_flow_error *error __rte_unused)
3769 struct mlx5_flow_tbl_data_entry *tbl_data =
3770 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3773 MLX5_ASSERT(tbl_data->jump.action);
3774 dev_flow->handle->rix_jump = tbl_data->idx;
3775 dev_flow->dv.jump = &tbl_data->jump;
3780 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3781 struct mlx5_list_entry *entry, void *cb_ctx)
3783 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3784 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3785 struct mlx5_flow_dv_port_id_action_resource *res =
3786 container_of(entry, typeof(*res), entry);
3788 return ref->port_id != res->port_id;
3791 struct mlx5_list_entry *
3792 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3794 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3795 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3796 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3797 struct mlx5_flow_dv_port_id_action_resource *resource;
3801 /* Register new port id action resource. */
3802 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3804 rte_flow_error_set(ctx->error, ENOMEM,
3805 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3806 "cannot allocate port_id action memory");
3810 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3814 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3815 rte_flow_error_set(ctx->error, ENOMEM,
3816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3817 "cannot create action");
3820 resource->idx = idx;
3821 return &resource->entry;
3824 struct mlx5_list_entry *
3825 flow_dv_port_id_clone_cb(void *tool_ctx,
3826 struct mlx5_list_entry *entry __rte_unused,
3829 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3830 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3831 struct mlx5_flow_dv_port_id_action_resource *resource;
3834 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3836 rte_flow_error_set(ctx->error, ENOMEM,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3838 "cannot allocate port_id action memory");
3841 memcpy(resource, entry, sizeof(*resource));
3842 resource->idx = idx;
3843 return &resource->entry;
3847 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3849 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3850 struct mlx5_flow_dv_port_id_action_resource *resource =
3851 container_of(entry, typeof(*resource), entry);
3853 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3857 * Find existing table port ID resource or create and register a new one.
3859 * @param[in, out] dev
3860 * Pointer to rte_eth_dev structure.
3861 * @param[in, out] ref
3862 * Pointer to port ID action resource reference.
3863 * @parm[in, out] dev_flow
3864 * Pointer to the dev_flow.
3866 * pointer to error structure.
3869 * 0 on success otherwise -errno and errno is set.
3872 flow_dv_port_id_action_resource_register
3873 (struct rte_eth_dev *dev,
3874 struct mlx5_flow_dv_port_id_action_resource *ref,
3875 struct mlx5_flow *dev_flow,
3876 struct rte_flow_error *error)
3878 struct mlx5_priv *priv = dev->data->dev_private;
3879 struct mlx5_list_entry *entry;
3880 struct mlx5_flow_dv_port_id_action_resource *resource;
3881 struct mlx5_flow_cb_ctx ctx = {
3886 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3889 resource = container_of(entry, typeof(*resource), entry);
3890 dev_flow->dv.port_id_action = resource;
3891 dev_flow->handle->rix_port_id_action = resource->idx;
3896 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3897 struct mlx5_list_entry *entry, void *cb_ctx)
3899 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3900 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3901 struct mlx5_flow_dv_push_vlan_action_resource *res =
3902 container_of(entry, typeof(*res), entry);
3904 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3907 struct mlx5_list_entry *
3908 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3910 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3911 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3912 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3913 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3914 struct mlx5dv_dr_domain *domain;
3918 /* Register new port id action resource. */
3919 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3921 rte_flow_error_set(ctx->error, ENOMEM,
3922 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3923 "cannot allocate push_vlan action memory");
3927 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3928 domain = sh->fdb_domain;
3929 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3930 domain = sh->rx_domain;
3932 domain = sh->tx_domain;
3933 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3936 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3937 rte_flow_error_set(ctx->error, ENOMEM,
3938 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3939 "cannot create push vlan action");
3942 resource->idx = idx;
3943 return &resource->entry;
3946 struct mlx5_list_entry *
3947 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3948 struct mlx5_list_entry *entry __rte_unused,
3951 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3952 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3953 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3956 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3958 rte_flow_error_set(ctx->error, ENOMEM,
3959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3960 "cannot allocate push_vlan action memory");
3963 memcpy(resource, entry, sizeof(*resource));
3964 resource->idx = idx;
3965 return &resource->entry;
3969 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3971 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3972 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3973 container_of(entry, typeof(*resource), entry);
3975 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3979 * Find existing push vlan resource or create and register a new one.
3981 * @param [in, out] dev
3982 * Pointer to rte_eth_dev structure.
3983 * @param[in, out] ref
3984 * Pointer to port ID action resource reference.
3985 * @parm[in, out] dev_flow
3986 * Pointer to the dev_flow.
3988 * pointer to error structure.
3991 * 0 on success otherwise -errno and errno is set.
3994 flow_dv_push_vlan_action_resource_register
3995 (struct rte_eth_dev *dev,
3996 struct mlx5_flow_dv_push_vlan_action_resource *ref,
3997 struct mlx5_flow *dev_flow,
3998 struct rte_flow_error *error)
4000 struct mlx5_priv *priv = dev->data->dev_private;
4001 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4002 struct mlx5_list_entry *entry;
4003 struct mlx5_flow_cb_ctx ctx = {
4008 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4011 resource = container_of(entry, typeof(*resource), entry);
4013 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4014 dev_flow->dv.push_vlan_res = resource;
4019 * Get the size of specific rte_flow_item_type hdr size
4021 * @param[in] item_type
4022 * Tested rte_flow_item_type.
4025 * sizeof struct item_type, 0 if void or irrelevant.
4028 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4032 switch (item_type) {
4033 case RTE_FLOW_ITEM_TYPE_ETH:
4034 retval = sizeof(struct rte_ether_hdr);
4036 case RTE_FLOW_ITEM_TYPE_VLAN:
4037 retval = sizeof(struct rte_vlan_hdr);
4039 case RTE_FLOW_ITEM_TYPE_IPV4:
4040 retval = sizeof(struct rte_ipv4_hdr);
4042 case RTE_FLOW_ITEM_TYPE_IPV6:
4043 retval = sizeof(struct rte_ipv6_hdr);
4045 case RTE_FLOW_ITEM_TYPE_UDP:
4046 retval = sizeof(struct rte_udp_hdr);
4048 case RTE_FLOW_ITEM_TYPE_TCP:
4049 retval = sizeof(struct rte_tcp_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VXLAN:
4052 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4053 retval = sizeof(struct rte_vxlan_hdr);
4055 case RTE_FLOW_ITEM_TYPE_GRE:
4056 case RTE_FLOW_ITEM_TYPE_NVGRE:
4057 retval = sizeof(struct rte_gre_hdr);
4059 case RTE_FLOW_ITEM_TYPE_MPLS:
4060 retval = sizeof(struct rte_mpls_hdr);
4062 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4070 #define MLX5_ENCAP_IPV4_VERSION 0x40
4071 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4072 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4073 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4074 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4075 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4076 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4079 * Convert the encap action data from list of rte_flow_item to raw buffer
4082 * Pointer to rte_flow_item objects list.
4084 * Pointer to the output buffer.
4086 * Pointer to the output buffer size.
4088 * Pointer to the error structure.
4091 * 0 on success, a negative errno value otherwise and rte_errno is set.
4094 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4095 size_t *size, struct rte_flow_error *error)
4097 struct rte_ether_hdr *eth = NULL;
4098 struct rte_vlan_hdr *vlan = NULL;
4099 struct rte_ipv4_hdr *ipv4 = NULL;
4100 struct rte_ipv6_hdr *ipv6 = NULL;
4101 struct rte_udp_hdr *udp = NULL;
4102 struct rte_vxlan_hdr *vxlan = NULL;
4103 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4104 struct rte_gre_hdr *gre = NULL;
4106 size_t temp_size = 0;
4109 return rte_flow_error_set(error, EINVAL,
4110 RTE_FLOW_ERROR_TYPE_ACTION,
4111 NULL, "invalid empty data");
4112 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4113 len = flow_dv_get_item_hdr_len(items->type);
4114 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4115 return rte_flow_error_set(error, EINVAL,
4116 RTE_FLOW_ERROR_TYPE_ACTION,
4117 (void *)items->type,
4118 "items total size is too big"
4119 " for encap action");
4120 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4121 switch (items->type) {
4122 case RTE_FLOW_ITEM_TYPE_ETH:
4123 eth = (struct rte_ether_hdr *)&buf[temp_size];
4125 case RTE_FLOW_ITEM_TYPE_VLAN:
4126 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4128 return rte_flow_error_set(error, EINVAL,
4129 RTE_FLOW_ERROR_TYPE_ACTION,
4130 (void *)items->type,
4131 "eth header not found");
4132 if (!eth->ether_type)
4133 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4135 case RTE_FLOW_ITEM_TYPE_IPV4:
4136 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4138 return rte_flow_error_set(error, EINVAL,
4139 RTE_FLOW_ERROR_TYPE_ACTION,
4140 (void *)items->type,
4141 "neither eth nor vlan"
4143 if (vlan && !vlan->eth_proto)
4144 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4145 else if (eth && !eth->ether_type)
4146 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4147 if (!ipv4->version_ihl)
4148 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4149 MLX5_ENCAP_IPV4_IHL_MIN;
4150 if (!ipv4->time_to_live)
4151 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4153 case RTE_FLOW_ITEM_TYPE_IPV6:
4154 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4156 return rte_flow_error_set(error, EINVAL,
4157 RTE_FLOW_ERROR_TYPE_ACTION,
4158 (void *)items->type,
4159 "neither eth nor vlan"
4161 if (vlan && !vlan->eth_proto)
4162 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4163 else if (eth && !eth->ether_type)
4164 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4165 if (!ipv6->vtc_flow)
4167 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4168 if (!ipv6->hop_limits)
4169 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4171 case RTE_FLOW_ITEM_TYPE_UDP:
4172 udp = (struct rte_udp_hdr *)&buf[temp_size];
4174 return rte_flow_error_set(error, EINVAL,
4175 RTE_FLOW_ERROR_TYPE_ACTION,
4176 (void *)items->type,
4177 "ip header not found");
4178 if (ipv4 && !ipv4->next_proto_id)
4179 ipv4->next_proto_id = IPPROTO_UDP;
4180 else if (ipv6 && !ipv6->proto)
4181 ipv6->proto = IPPROTO_UDP;
4183 case RTE_FLOW_ITEM_TYPE_VXLAN:
4184 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4186 return rte_flow_error_set(error, EINVAL,
4187 RTE_FLOW_ERROR_TYPE_ACTION,
4188 (void *)items->type,
4189 "udp header not found");
4191 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4192 if (!vxlan->vx_flags)
4194 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4196 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4197 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4199 return rte_flow_error_set(error, EINVAL,
4200 RTE_FLOW_ERROR_TYPE_ACTION,
4201 (void *)items->type,
4202 "udp header not found");
4203 if (!vxlan_gpe->proto)
4204 return rte_flow_error_set(error, EINVAL,
4205 RTE_FLOW_ERROR_TYPE_ACTION,
4206 (void *)items->type,
4207 "next protocol not found");
4210 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4211 if (!vxlan_gpe->vx_flags)
4212 vxlan_gpe->vx_flags =
4213 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4215 case RTE_FLOW_ITEM_TYPE_GRE:
4216 case RTE_FLOW_ITEM_TYPE_NVGRE:
4217 gre = (struct rte_gre_hdr *)&buf[temp_size];
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4224 return rte_flow_error_set(error, EINVAL,
4225 RTE_FLOW_ERROR_TYPE_ACTION,
4226 (void *)items->type,
4227 "ip header not found");
4228 if (ipv4 && !ipv4->next_proto_id)
4229 ipv4->next_proto_id = IPPROTO_GRE;
4230 else if (ipv6 && !ipv6->proto)
4231 ipv6->proto = IPPROTO_GRE;
4233 case RTE_FLOW_ITEM_TYPE_VOID:
4236 return rte_flow_error_set(error, EINVAL,
4237 RTE_FLOW_ERROR_TYPE_ACTION,
4238 (void *)items->type,
4239 "unsupported item type");
4249 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4251 struct rte_ether_hdr *eth = NULL;
4252 struct rte_vlan_hdr *vlan = NULL;
4253 struct rte_ipv6_hdr *ipv6 = NULL;
4254 struct rte_udp_hdr *udp = NULL;
4258 eth = (struct rte_ether_hdr *)data;
4259 next_hdr = (char *)(eth + 1);
4260 proto = RTE_BE16(eth->ether_type);
4263 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4264 vlan = (struct rte_vlan_hdr *)next_hdr;
4265 proto = RTE_BE16(vlan->eth_proto);
4266 next_hdr += sizeof(struct rte_vlan_hdr);
4269 /* HW calculates IPv4 csum. no need to proceed */
4270 if (proto == RTE_ETHER_TYPE_IPV4)
4273 /* non IPv4/IPv6 header. not supported */
4274 if (proto != RTE_ETHER_TYPE_IPV6) {
4275 return rte_flow_error_set(error, ENOTSUP,
4276 RTE_FLOW_ERROR_TYPE_ACTION,
4277 NULL, "Cannot offload non IPv4/IPv6");
4280 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4282 /* ignore non UDP */
4283 if (ipv6->proto != IPPROTO_UDP)
4286 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4287 udp->dgram_cksum = 0;
4293 * Convert L2 encap action to DV specification.
4296 * Pointer to rte_eth_dev structure.
4298 * Pointer to action structure.
4299 * @param[in, out] dev_flow
4300 * Pointer to the mlx5_flow.
4301 * @param[in] transfer
4302 * Mark if the flow is E-Switch flow.
4304 * Pointer to the error structure.
4307 * 0 on success, a negative errno value otherwise and rte_errno is set.
4310 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4311 const struct rte_flow_action *action,
4312 struct mlx5_flow *dev_flow,
4314 struct rte_flow_error *error)
4316 const struct rte_flow_item *encap_data;
4317 const struct rte_flow_action_raw_encap *raw_encap_data;
4318 struct mlx5_flow_dv_encap_decap_resource res = {
4320 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4321 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4322 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4325 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4327 (const struct rte_flow_action_raw_encap *)action->conf;
4328 res.size = raw_encap_data->size;
4329 memcpy(res.buf, raw_encap_data->data, res.size);
4331 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4333 ((const struct rte_flow_action_vxlan_encap *)
4334 action->conf)->definition;
4337 ((const struct rte_flow_action_nvgre_encap *)
4338 action->conf)->definition;
4339 if (flow_dv_convert_encap_data(encap_data, res.buf,
4343 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4345 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4346 return rte_flow_error_set(error, EINVAL,
4347 RTE_FLOW_ERROR_TYPE_ACTION,
4348 NULL, "can't create L2 encap action");
4353 * Convert L2 decap action to DV specification.
4356 * Pointer to rte_eth_dev structure.
4357 * @param[in, out] dev_flow
4358 * Pointer to the mlx5_flow.
4359 * @param[in] transfer
4360 * Mark if the flow is E-Switch flow.
4362 * Pointer to the error structure.
4365 * 0 on success, a negative errno value otherwise and rte_errno is set.
4368 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4369 struct mlx5_flow *dev_flow,
4371 struct rte_flow_error *error)
4373 struct mlx5_flow_dv_encap_decap_resource res = {
4376 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4377 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4378 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4381 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4382 return rte_flow_error_set(error, EINVAL,
4383 RTE_FLOW_ERROR_TYPE_ACTION,
4384 NULL, "can't create L2 decap action");
4389 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4392 * Pointer to rte_eth_dev structure.
4394 * Pointer to action structure.
4395 * @param[in, out] dev_flow
4396 * Pointer to the mlx5_flow.
4398 * Pointer to the flow attributes.
4400 * Pointer to the error structure.
4403 * 0 on success, a negative errno value otherwise and rte_errno is set.
4406 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4407 const struct rte_flow_action *action,
4408 struct mlx5_flow *dev_flow,
4409 const struct rte_flow_attr *attr,
4410 struct rte_flow_error *error)
4412 const struct rte_flow_action_raw_encap *encap_data;
4413 struct mlx5_flow_dv_encap_decap_resource res;
4415 memset(&res, 0, sizeof(res));
4416 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4417 res.size = encap_data->size;
4418 memcpy(res.buf, encap_data->data, res.size);
4419 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4420 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4421 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4423 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4425 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4426 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4427 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4428 return rte_flow_error_set(error, EINVAL,
4429 RTE_FLOW_ERROR_TYPE_ACTION,
4430 NULL, "can't create encap action");
4435 * Create action push VLAN.
4438 * Pointer to rte_eth_dev structure.
4440 * Pointer to the flow attributes.
4442 * Pointer to the vlan to push to the Ethernet header.
4443 * @param[in, out] dev_flow
4444 * Pointer to the mlx5_flow.
4446 * Pointer to the error structure.
4449 * 0 on success, a negative errno value otherwise and rte_errno is set.
4452 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4453 const struct rte_flow_attr *attr,
4454 const struct rte_vlan_hdr *vlan,
4455 struct mlx5_flow *dev_flow,
4456 struct rte_flow_error *error)
4458 struct mlx5_flow_dv_push_vlan_action_resource res;
4460 memset(&res, 0, sizeof(res));
4462 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4465 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4467 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4468 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4469 return flow_dv_push_vlan_action_resource_register
4470 (dev, &res, dev_flow, error);
4474 * Validate the modify-header actions.
4476 * @param[in] action_flags
4477 * Holds the actions detected until now.
4479 * Pointer to the modify action.
4481 * Pointer to error structure.
4484 * 0 on success, a negative errno value otherwise and rte_errno is set.
4487 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4488 const struct rte_flow_action *action,
4489 struct rte_flow_error *error)
4491 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4492 return rte_flow_error_set(error, EINVAL,
4493 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4494 NULL, "action configuration not set");
4495 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4496 return rte_flow_error_set(error, EINVAL,
4497 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4498 "can't have encap action before"
4504 * Validate the modify-header MAC address actions.
4506 * @param[in] action_flags
4507 * Holds the actions detected until now.
4509 * Pointer to the modify action.
4510 * @param[in] item_flags
4511 * Holds the items detected.
4513 * Pointer to error structure.
4516 * 0 on success, a negative errno value otherwise and rte_errno is set.
4519 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4520 const struct rte_flow_action *action,
4521 const uint64_t item_flags,
4522 struct rte_flow_error *error)
4526 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4528 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4529 return rte_flow_error_set(error, EINVAL,
4530 RTE_FLOW_ERROR_TYPE_ACTION,
4532 "no L2 item in pattern");
4538 * Validate the modify-header IPv4 address actions.
4540 * @param[in] action_flags
4541 * Holds the actions detected until now.
4543 * Pointer to the modify action.
4544 * @param[in] item_flags
4545 * Holds the items detected.
4547 * Pointer to error structure.
4550 * 0 on success, a negative errno value otherwise and rte_errno is set.
4553 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4554 const struct rte_flow_action *action,
4555 const uint64_t item_flags,
4556 struct rte_flow_error *error)
4561 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4563 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4564 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4565 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4566 if (!(item_flags & layer))
4567 return rte_flow_error_set(error, EINVAL,
4568 RTE_FLOW_ERROR_TYPE_ACTION,
4570 "no ipv4 item in pattern");
4576 * Validate the modify-header IPv6 address actions.
4578 * @param[in] action_flags
4579 * Holds the actions detected until now.
4581 * Pointer to the modify action.
4582 * @param[in] item_flags
4583 * Holds the items detected.
4585 * Pointer to error structure.
4588 * 0 on success, a negative errno value otherwise and rte_errno is set.
4591 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4592 const struct rte_flow_action *action,
4593 const uint64_t item_flags,
4594 struct rte_flow_error *error)
4599 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4601 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4602 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4603 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4604 if (!(item_flags & layer))
4605 return rte_flow_error_set(error, EINVAL,
4606 RTE_FLOW_ERROR_TYPE_ACTION,
4608 "no ipv6 item in pattern");
4614 * Validate the modify-header TP actions.
4616 * @param[in] action_flags
4617 * Holds the actions detected until now.
4619 * Pointer to the modify action.
4620 * @param[in] item_flags
4621 * Holds the items detected.
4623 * Pointer to error structure.
4626 * 0 on success, a negative errno value otherwise and rte_errno is set.
4629 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4630 const struct rte_flow_action *action,
4631 const uint64_t item_flags,
4632 struct rte_flow_error *error)
4637 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4639 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4640 MLX5_FLOW_LAYER_INNER_L4 :
4641 MLX5_FLOW_LAYER_OUTER_L4;
4642 if (!(item_flags & layer))
4643 return rte_flow_error_set(error, EINVAL,
4644 RTE_FLOW_ERROR_TYPE_ACTION,
4645 NULL, "no transport layer "
4652 * Validate the modify-header actions of increment/decrement
4653 * TCP Sequence-number.
4655 * @param[in] action_flags
4656 * Holds the actions detected until now.
4658 * Pointer to the modify action.
4659 * @param[in] item_flags
4660 * Holds the items detected.
4662 * Pointer to error structure.
4665 * 0 on success, a negative errno value otherwise and rte_errno is set.
4668 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4669 const struct rte_flow_action *action,
4670 const uint64_t item_flags,
4671 struct rte_flow_error *error)
4676 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4678 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4679 MLX5_FLOW_LAYER_INNER_L4_TCP :
4680 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4681 if (!(item_flags & layer))
4682 return rte_flow_error_set(error, EINVAL,
4683 RTE_FLOW_ERROR_TYPE_ACTION,
4684 NULL, "no TCP item in"
4686 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4687 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4688 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4689 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4690 return rte_flow_error_set(error, EINVAL,
4691 RTE_FLOW_ERROR_TYPE_ACTION,
4693 "cannot decrease and increase"
4694 " TCP sequence number"
4695 " at the same time");
4701 * Validate the modify-header actions of increment/decrement
4702 * TCP Acknowledgment number.
4704 * @param[in] action_flags
4705 * Holds the actions detected until now.
4707 * Pointer to the modify action.
4708 * @param[in] item_flags
4709 * Holds the items detected.
4711 * Pointer to error structure.
4714 * 0 on success, a negative errno value otherwise and rte_errno is set.
4717 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4718 const struct rte_flow_action *action,
4719 const uint64_t item_flags,
4720 struct rte_flow_error *error)
4725 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4727 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4728 MLX5_FLOW_LAYER_INNER_L4_TCP :
4729 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4730 if (!(item_flags & layer))
4731 return rte_flow_error_set(error, EINVAL,
4732 RTE_FLOW_ERROR_TYPE_ACTION,
4733 NULL, "no TCP item in"
4735 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4736 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4737 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4738 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4739 return rte_flow_error_set(error, EINVAL,
4740 RTE_FLOW_ERROR_TYPE_ACTION,
4742 "cannot decrease and increase"
4743 " TCP acknowledgment number"
4744 " at the same time");
4750 * Validate the modify-header TTL actions.
4752 * @param[in] action_flags
4753 * Holds the actions detected until now.
4755 * Pointer to the modify action.
4756 * @param[in] item_flags
4757 * Holds the items detected.
4759 * Pointer to error structure.
4762 * 0 on success, a negative errno value otherwise and rte_errno is set.
4765 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4766 const struct rte_flow_action *action,
4767 const uint64_t item_flags,
4768 struct rte_flow_error *error)
4773 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4775 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4776 MLX5_FLOW_LAYER_INNER_L3 :
4777 MLX5_FLOW_LAYER_OUTER_L3;
4778 if (!(item_flags & layer))
4779 return rte_flow_error_set(error, EINVAL,
4780 RTE_FLOW_ERROR_TYPE_ACTION,
4782 "no IP protocol in pattern");
4788 * Validate the generic modify field actions.
4790 * Pointer to the rte_eth_dev structure.
4791 * @param[in] action_flags
4792 * Holds the actions detected until now.
4794 * Pointer to the modify action.
4796 * Pointer to the flow attributes.
4798 * Pointer to error structure.
4801 * Number of header fields to modify (0 or more) on success,
4802 * a negative errno value otherwise and rte_errno is set.
4805 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4806 const uint64_t action_flags,
4807 const struct rte_flow_action *action,
4808 const struct rte_flow_attr *attr,
4809 struct rte_flow_error *error)
4812 struct mlx5_priv *priv = dev->data->dev_private;
4813 struct mlx5_dev_config *config = &priv->config;
4814 const struct rte_flow_action_modify_field *action_modify_field =
4816 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4817 action_modify_field->dst.field,
4819 uint32_t src_width = mlx5_flow_item_field_width(dev,
4820 action_modify_field->src.field,
4821 dst_width, attr, error);
4823 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4827 if (action_modify_field->width == 0)
4828 return rte_flow_error_set(error, EINVAL,
4829 RTE_FLOW_ERROR_TYPE_ACTION, action,
4830 "no bits are requested to be modified");
4831 else if (action_modify_field->width > dst_width ||
4832 action_modify_field->width > src_width)
4833 return rte_flow_error_set(error, EINVAL,
4834 RTE_FLOW_ERROR_TYPE_ACTION, action,
4835 "cannot modify more bits than"
4836 " the width of a field");
4837 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4838 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4839 if ((action_modify_field->dst.offset +
4840 action_modify_field->width > dst_width) ||
4841 (action_modify_field->dst.offset % 32))
4842 return rte_flow_error_set(error, EINVAL,
4843 RTE_FLOW_ERROR_TYPE_ACTION, action,
4844 "destination offset is too big"
4845 " or not aligned to 4 bytes");
4846 if (action_modify_field->dst.level &&
4847 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4848 return rte_flow_error_set(error, ENOTSUP,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "inner header fields modification"
4851 " is not supported");
4853 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4854 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4855 if (!attr->transfer && !attr->group)
4856 return rte_flow_error_set(error, ENOTSUP,
4857 RTE_FLOW_ERROR_TYPE_ACTION, action,
4858 "modify field action is not"
4859 " supported for group 0");
4860 if ((action_modify_field->src.offset +
4861 action_modify_field->width > src_width) ||
4862 (action_modify_field->src.offset % 32))
4863 return rte_flow_error_set(error, EINVAL,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "source offset is too big"
4866 " or not aligned to 4 bytes");
4867 if (action_modify_field->src.level &&
4868 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4869 return rte_flow_error_set(error, ENOTSUP,
4870 RTE_FLOW_ERROR_TYPE_ACTION, action,
4871 "inner header fields modification"
4872 " is not supported");
4874 if ((action_modify_field->dst.field ==
4875 action_modify_field->src.field) &&
4876 (action_modify_field->dst.level ==
4877 action_modify_field->src.level))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source and destination fields"
4881 " cannot be the same");
4882 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4883 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4884 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4885 return rte_flow_error_set(error, EINVAL,
4886 RTE_FLOW_ERROR_TYPE_ACTION, action,
4887 "mark, immediate value or a pointer to it"
4888 " cannot be used as a destination");
4889 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4890 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4891 return rte_flow_error_set(error, ENOTSUP,
4892 RTE_FLOW_ERROR_TYPE_ACTION, action,
4893 "modifications of an arbitrary"
4894 " place in a packet is not supported");
4895 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4896 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4897 return rte_flow_error_set(error, ENOTSUP,
4898 RTE_FLOW_ERROR_TYPE_ACTION, action,
4899 "modifications of the 802.1Q Tag"
4900 " Identifier is not supported");
4901 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4902 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4903 return rte_flow_error_set(error, ENOTSUP,
4904 RTE_FLOW_ERROR_TYPE_ACTION, action,
4905 "modifications of the VXLAN Network"
4906 " Identifier is not supported");
4907 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4908 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4909 return rte_flow_error_set(error, ENOTSUP,
4910 RTE_FLOW_ERROR_TYPE_ACTION, action,
4911 "modifications of the GENEVE Network"
4912 " Identifier is not supported");
4913 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4914 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4915 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4916 !mlx5_flow_ext_mreg_supported(dev))
4917 return rte_flow_error_set(error, ENOTSUP,
4918 RTE_FLOW_ERROR_TYPE_ACTION, action,
4919 "cannot modify mark in legacy mode"
4920 " or without extensive registers");
4921 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4922 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4923 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4924 !mlx5_flow_ext_mreg_supported(dev))
4925 return rte_flow_error_set(error, ENOTSUP,
4926 RTE_FLOW_ERROR_TYPE_ACTION, action,
4927 "cannot modify meta without"
4928 " extensive registers support");
4929 ret = flow_dv_get_metadata_reg(dev, attr, error);
4930 if (ret < 0 || ret == REG_NON)
4931 return rte_flow_error_set(error, ENOTSUP,
4932 RTE_FLOW_ERROR_TYPE_ACTION, action,
4933 "cannot modify meta without"
4934 " extensive registers available");
4936 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4937 return rte_flow_error_set(error, ENOTSUP,
4938 RTE_FLOW_ERROR_TYPE_ACTION, action,
4939 "add and sub operations"
4940 " are not supported");
4941 return (action_modify_field->width / 32) +
4942 !!(action_modify_field->width % 32);
4946 * Validate jump action.
4949 * Pointer to the jump action.
4950 * @param[in] action_flags
4951 * Holds the actions detected until now.
4952 * @param[in] attributes
4953 * Pointer to flow attributes
4954 * @param[in] external
4955 * Action belongs to flow rule created by request external to PMD.
4957 * Pointer to error structure.
4960 * 0 on success, a negative errno value otherwise and rte_errno is set.
4963 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4964 const struct mlx5_flow_tunnel *tunnel,
4965 const struct rte_flow_action *action,
4966 uint64_t action_flags,
4967 const struct rte_flow_attr *attributes,
4968 bool external, struct rte_flow_error *error)
4970 uint32_t target_group, table = 0;
4972 struct flow_grp_info grp_info = {
4973 .external = !!external,
4974 .transfer = !!attributes->transfer,
4978 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4979 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4980 return rte_flow_error_set(error, EINVAL,
4981 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4982 "can't have 2 fate actions in"
4985 return rte_flow_error_set(error, EINVAL,
4986 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4987 NULL, "action configuration not set");
4989 ((const struct rte_flow_action_jump *)action->conf)->group;
4990 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4994 if (attributes->group == target_group &&
4995 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4996 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4997 return rte_flow_error_set(error, EINVAL,
4998 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4999 "target group must be other than"
5000 " the current flow group");
5002 return rte_flow_error_set(error, EINVAL,
5003 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5004 NULL, "root table shouldn't be destination");
5009 * Validate action PORT_ID / REPRESENTED_PORT.
5012 * Pointer to rte_eth_dev structure.
5013 * @param[in] action_flags
5014 * Bit-fields that holds the actions detected until now.
5016 * PORT_ID / REPRESENTED_PORT action structure.
5018 * Attributes of flow that includes this action.
5020 * Pointer to error structure.
5023 * 0 on success, a negative errno value otherwise and rte_errno is set.
5026 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5027 uint64_t action_flags,
5028 const struct rte_flow_action *action,
5029 const struct rte_flow_attr *attr,
5030 struct rte_flow_error *error)
5032 const struct rte_flow_action_port_id *port_id;
5033 const struct rte_flow_action_ethdev *ethdev;
5034 struct mlx5_priv *act_priv;
5035 struct mlx5_priv *dev_priv;
5038 if (!attr->transfer)
5039 return rte_flow_error_set(error, ENOTSUP,
5040 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5042 "port action is valid in transfer"
5044 if (!action || !action->conf)
5045 return rte_flow_error_set(error, ENOTSUP,
5046 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5048 "port action parameters must be"
5050 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5051 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5052 return rte_flow_error_set(error, EINVAL,
5053 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5054 "can have only one fate actions in"
5056 dev_priv = mlx5_dev_to_eswitch_info(dev);
5058 return rte_flow_error_set(error, rte_errno,
5059 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5061 "failed to obtain E-Switch info");
5062 switch (action->type) {
5063 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5064 port_id = action->conf;
5065 port = port_id->original ? dev->data->port_id : port_id->id;
5067 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5068 ethdev = action->conf;
5069 port = ethdev->port_id;
5073 return rte_flow_error_set
5075 RTE_FLOW_ERROR_TYPE_ACTION, action,
5076 "unknown E-Switch action");
5078 act_priv = mlx5_port_to_eswitch_info(port, false);
5080 return rte_flow_error_set
5082 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5083 "failed to obtain E-Switch port id for port");
5084 if (act_priv->domain_id != dev_priv->domain_id)
5085 return rte_flow_error_set
5087 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5088 "port does not belong to"
5089 " E-Switch being configured");
5094 * Get the maximum number of modify header actions.
5097 * Pointer to rte_eth_dev structure.
5099 * Whether action is on root table.
5102 * Max number of modify header actions device can support.
5104 static inline unsigned int
5105 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5109 * There's no way to directly query the max capacity from FW.
5110 * The maximal value on root table should be assumed to be supported.
5113 return MLX5_MAX_MODIFY_NUM;
5115 return MLX5_ROOT_TBL_MODIFY_NUM;
5119 * Validate the meter action.
5122 * Pointer to rte_eth_dev structure.
5123 * @param[in] action_flags
5124 * Bit-fields that holds the actions detected until now.
5125 * @param[in] item_flags
5126 * Holds the items detected.
5128 * Pointer to the meter action.
5130 * Attributes of flow that includes this action.
5131 * @param[in] port_id_item
5132 * Pointer to item indicating port id.
5134 * Pointer to error structure.
5137 * 0 on success, a negative errno value otherwise and rte_errno is set.
5140 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5141 uint64_t action_flags, uint64_t item_flags,
5142 const struct rte_flow_action *action,
5143 const struct rte_flow_attr *attr,
5144 const struct rte_flow_item *port_id_item,
5146 struct rte_flow_error *error)
5148 struct mlx5_priv *priv = dev->data->dev_private;
5149 const struct rte_flow_action_meter *am = action->conf;
5150 struct mlx5_flow_meter_info *fm;
5151 struct mlx5_flow_meter_policy *mtr_policy;
5152 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5155 return rte_flow_error_set(error, EINVAL,
5156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5157 "meter action conf is NULL");
5159 if (action_flags & MLX5_FLOW_ACTION_METER)
5160 return rte_flow_error_set(error, ENOTSUP,
5161 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5162 "meter chaining not support");
5163 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5164 return rte_flow_error_set(error, ENOTSUP,
5165 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5166 "meter with jump not support");
5168 return rte_flow_error_set(error, ENOTSUP,
5169 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5171 "meter action not supported");
5172 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5174 return rte_flow_error_set(error, EINVAL,
5175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5177 /* aso meter can always be shared by different domains */
5178 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5179 !(fm->transfer == attr->transfer ||
5180 (!fm->ingress && !attr->ingress && attr->egress) ||
5181 (!fm->egress && !attr->egress && attr->ingress)))
5182 return rte_flow_error_set(error, EINVAL,
5183 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5184 "Flow attributes domain are either invalid "
5185 "or have a domain conflict with current "
5186 "meter attributes");
5187 if (fm->def_policy) {
5188 if (!((attr->transfer &&
5189 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5191 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5193 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5194 return rte_flow_error_set(error, EINVAL,
5195 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5196 "Flow attributes domain "
5197 "have a conflict with current "
5198 "meter domain attributes");
5201 mtr_policy = mlx5_flow_meter_policy_find(dev,
5202 fm->policy_id, NULL);
5204 return rte_flow_error_set(error, EINVAL,
5205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5206 "Invalid policy id for meter ");
5207 if (!((attr->transfer && mtr_policy->transfer) ||
5208 (attr->egress && mtr_policy->egress) ||
5209 (attr->ingress && mtr_policy->ingress)))
5210 return rte_flow_error_set(error, EINVAL,
5211 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5212 "Flow attributes domain "
5213 "have a conflict with current "
5214 "meter domain attributes");
5215 if (attr->transfer && mtr_policy->dev) {
5217 * When policy has fate action of port_id,
5218 * the flow should have the same src port as policy.
5220 struct mlx5_priv *policy_port_priv =
5221 mtr_policy->dev->data->dev_private;
5222 int32_t flow_src_port = priv->representor_id;
5225 const struct rte_flow_item_port_id *spec =
5227 struct mlx5_priv *port_priv =
5228 mlx5_port_to_eswitch_info(spec->id,
5231 return rte_flow_error_set(error,
5233 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5235 "Failed to get port info.");
5236 flow_src_port = port_priv->representor_id;
5238 if (flow_src_port != policy_port_priv->representor_id)
5239 return rte_flow_error_set(error,
5241 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5243 "Flow and meter policy "
5244 "have different src port.");
5245 } else if (mtr_policy->is_rss) {
5246 struct mlx5_flow_meter_policy *fp;
5247 struct mlx5_meter_policy_action_container *acg;
5248 struct mlx5_meter_policy_action_container *acy;
5249 const struct rte_flow_action *rss_act;
5252 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5255 return rte_flow_error_set(error, EINVAL,
5256 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5257 "Unable to get the final "
5258 "policy in the hierarchy");
5259 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5260 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5261 MLX5_ASSERT(acg->fate_action ==
5262 MLX5_FLOW_FATE_SHARED_RSS ||
5264 MLX5_FLOW_FATE_SHARED_RSS);
5265 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5269 ret = mlx5_flow_validate_action_rss(rss_act,
5270 action_flags, dev, attr,
5275 *def_policy = false;
5281 * Validate the age action.
5283 * @param[in] action_flags
5284 * Holds the actions detected until now.
5286 * Pointer to the age action.
5288 * Pointer to the Ethernet device structure.
5290 * Pointer to error structure.
5293 * 0 on success, a negative errno value otherwise and rte_errno is set.
5296 flow_dv_validate_action_age(uint64_t action_flags,
5297 const struct rte_flow_action *action,
5298 struct rte_eth_dev *dev,
5299 struct rte_flow_error *error)
5301 struct mlx5_priv *priv = dev->data->dev_private;
5302 const struct rte_flow_action_age *age = action->conf;
5304 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5305 !priv->sh->aso_age_mng))
5306 return rte_flow_error_set(error, ENOTSUP,
5307 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5309 "age action not supported");
5310 if (!(action->conf))
5311 return rte_flow_error_set(error, EINVAL,
5312 RTE_FLOW_ERROR_TYPE_ACTION, action,
5313 "configuration cannot be null");
5314 if (!(age->timeout))
5315 return rte_flow_error_set(error, EINVAL,
5316 RTE_FLOW_ERROR_TYPE_ACTION, action,
5317 "invalid timeout value 0");
5318 if (action_flags & MLX5_FLOW_ACTION_AGE)
5319 return rte_flow_error_set(error, EINVAL,
5320 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5321 "duplicate age actions set");
5326 * Validate the modify-header IPv4 DSCP actions.
5328 * @param[in] action_flags
5329 * Holds the actions detected until now.
5331 * Pointer to the modify action.
5332 * @param[in] item_flags
5333 * Holds the items detected.
5335 * Pointer to error structure.
5338 * 0 on success, a negative errno value otherwise and rte_errno is set.
5341 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5342 const struct rte_flow_action *action,
5343 const uint64_t item_flags,
5344 struct rte_flow_error *error)
5348 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5350 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5351 return rte_flow_error_set(error, EINVAL,
5352 RTE_FLOW_ERROR_TYPE_ACTION,
5354 "no ipv4 item in pattern");
5360 * Validate the modify-header IPv6 DSCP actions.
5362 * @param[in] action_flags
5363 * Holds the actions detected until now.
5365 * Pointer to the modify action.
5366 * @param[in] item_flags
5367 * Holds the items detected.
5369 * Pointer to error structure.
5372 * 0 on success, a negative errno value otherwise and rte_errno is set.
5375 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5376 const struct rte_flow_action *action,
5377 const uint64_t item_flags,
5378 struct rte_flow_error *error)
5382 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5384 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5385 return rte_flow_error_set(error, EINVAL,
5386 RTE_FLOW_ERROR_TYPE_ACTION,
5388 "no ipv6 item in pattern");
5394 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5395 struct mlx5_list_entry *entry, void *cb_ctx)
5397 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5398 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5399 struct mlx5_flow_dv_modify_hdr_resource *resource =
5400 container_of(entry, typeof(*resource), entry);
5401 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5403 key_len += ref->actions_num * sizeof(ref->actions[0]);
5404 return ref->actions_num != resource->actions_num ||
5405 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5408 static struct mlx5_indexed_pool *
5409 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5411 struct mlx5_indexed_pool *ipool = __atomic_load_n
5412 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5415 struct mlx5_indexed_pool *expected = NULL;
5416 struct mlx5_indexed_pool_config cfg =
5417 (struct mlx5_indexed_pool_config) {
5418 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5420 sizeof(struct mlx5_modification_cmd),
5425 .release_mem_en = !!sh->reclaim_mode,
5426 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5427 .malloc = mlx5_malloc,
5429 .type = "mlx5_modify_action_resource",
5432 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5433 ipool = mlx5_ipool_create(&cfg);
5436 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5437 &expected, ipool, false,
5439 __ATOMIC_SEQ_CST)) {
5440 mlx5_ipool_destroy(ipool);
5441 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5448 struct mlx5_list_entry *
5449 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5451 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5452 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5453 struct mlx5dv_dr_domain *ns;
5454 struct mlx5_flow_dv_modify_hdr_resource *entry;
5455 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5456 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5457 ref->actions_num - 1);
5459 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5460 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5463 if (unlikely(!ipool)) {
5464 rte_flow_error_set(ctx->error, ENOMEM,
5465 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5466 NULL, "cannot allocate modify ipool");
5469 entry = mlx5_ipool_zmalloc(ipool, &idx);
5471 rte_flow_error_set(ctx->error, ENOMEM,
5472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5473 "cannot allocate resource memory");
5476 rte_memcpy(&entry->ft_type,
5477 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5478 key_len + data_len);
5479 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5480 ns = sh->fdb_domain;
5481 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5485 ret = mlx5_flow_os_create_flow_action_modify_header
5486 (sh->cdev->ctx, ns, entry,
5487 data_len, &entry->action);
5489 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5490 rte_flow_error_set(ctx->error, ENOMEM,
5491 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5492 NULL, "cannot create modification action");
5496 return &entry->entry;
5499 struct mlx5_list_entry *
5500 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5503 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5504 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5505 struct mlx5_flow_dv_modify_hdr_resource *entry;
5506 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5507 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5510 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5513 rte_flow_error_set(ctx->error, ENOMEM,
5514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5515 "cannot allocate resource memory");
5518 memcpy(entry, oentry, sizeof(*entry) + data_len);
5520 return &entry->entry;
5524 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5526 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5527 struct mlx5_flow_dv_modify_hdr_resource *res =
5528 container_of(entry, typeof(*res), entry);
5530 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5534 * Validate the sample action.
5536 * @param[in, out] action_flags
5537 * Holds the actions detected until now.
5539 * Pointer to the sample action.
5541 * Pointer to the Ethernet device structure.
5543 * Attributes of flow that includes this action.
5544 * @param[in] item_flags
5545 * Holds the items detected.
5547 * Pointer to the RSS action.
5548 * @param[out] sample_rss
5549 * Pointer to the RSS action in sample action list.
5551 * Pointer to the COUNT action in sample action list.
5552 * @param[out] fdb_mirror_limit
5553 * Pointer to the FDB mirror limitation flag.
5555 * Pointer to error structure.
5558 * 0 on success, a negative errno value otherwise and rte_errno is set.
5561 flow_dv_validate_action_sample(uint64_t *action_flags,
5562 const struct rte_flow_action *action,
5563 struct rte_eth_dev *dev,
5564 const struct rte_flow_attr *attr,
5565 uint64_t item_flags,
5566 const struct rte_flow_action_rss *rss,
5567 const struct rte_flow_action_rss **sample_rss,
5568 const struct rte_flow_action_count **count,
5569 int *fdb_mirror_limit,
5570 struct rte_flow_error *error)
5572 struct mlx5_priv *priv = dev->data->dev_private;
5573 struct mlx5_dev_config *dev_conf = &priv->config;
5574 const struct rte_flow_action_sample *sample = action->conf;
5575 const struct rte_flow_action *act;
5576 uint64_t sub_action_flags = 0;
5577 uint16_t queue_index = 0xFFFF;
5582 return rte_flow_error_set(error, EINVAL,
5583 RTE_FLOW_ERROR_TYPE_ACTION, action,
5584 "configuration cannot be NULL");
5585 if (sample->ratio == 0)
5586 return rte_flow_error_set(error, EINVAL,
5587 RTE_FLOW_ERROR_TYPE_ACTION, action,
5588 "ratio value starts from 1");
5589 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5590 return rte_flow_error_set(error, ENOTSUP,
5591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5593 "sample action not supported");
5594 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5595 return rte_flow_error_set(error, EINVAL,
5596 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5597 "Multiple sample actions not "
5599 if (*action_flags & MLX5_FLOW_ACTION_METER)
5600 return rte_flow_error_set(error, EINVAL,
5601 RTE_FLOW_ERROR_TYPE_ACTION, action,
5602 "wrong action order, meter should "
5603 "be after sample action");
5604 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5605 return rte_flow_error_set(error, EINVAL,
5606 RTE_FLOW_ERROR_TYPE_ACTION, action,
5607 "wrong action order, jump should "
5608 "be after sample action");
5609 if (*action_flags & MLX5_FLOW_ACTION_CT)
5610 return rte_flow_error_set(error, EINVAL,
5611 RTE_FLOW_ERROR_TYPE_ACTION, action,
5612 "Sample after CT not supported");
5613 act = sample->actions;
5614 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5615 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5616 return rte_flow_error_set(error, ENOTSUP,
5617 RTE_FLOW_ERROR_TYPE_ACTION,
5618 act, "too many actions");
5619 switch (act->type) {
5620 case RTE_FLOW_ACTION_TYPE_QUEUE:
5621 ret = mlx5_flow_validate_action_queue(act,
5627 queue_index = ((const struct rte_flow_action_queue *)
5628 (act->conf))->index;
5629 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5632 case RTE_FLOW_ACTION_TYPE_RSS:
5633 *sample_rss = act->conf;
5634 ret = mlx5_flow_validate_action_rss(act,
5641 if (rss && *sample_rss &&
5642 ((*sample_rss)->level != rss->level ||
5643 (*sample_rss)->types != rss->types))
5644 return rte_flow_error_set(error, ENOTSUP,
5645 RTE_FLOW_ERROR_TYPE_ACTION,
5647 "Can't use the different RSS types "
5648 "or level in the same flow");
5649 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5650 queue_index = (*sample_rss)->queue[0];
5651 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5654 case RTE_FLOW_ACTION_TYPE_MARK:
5655 ret = flow_dv_validate_action_mark(dev, act,
5660 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5661 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5662 MLX5_FLOW_ACTION_MARK_EXT;
5664 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5667 case RTE_FLOW_ACTION_TYPE_COUNT:
5668 ret = flow_dv_validate_action_count
5669 (dev, false, *action_flags | sub_action_flags,
5674 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5675 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5678 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5679 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5680 ret = flow_dv_validate_action_port_id(dev,
5687 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5690 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5691 ret = flow_dv_validate_action_raw_encap_decap
5692 (dev, NULL, act->conf, attr, &sub_action_flags,
5693 &actions_n, action, item_flags, error);
5698 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5699 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5700 ret = flow_dv_validate_action_l2_encap(dev,
5706 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5710 return rte_flow_error_set(error, ENOTSUP,
5711 RTE_FLOW_ERROR_TYPE_ACTION,
5713 "Doesn't support optional "
5717 if (attr->ingress && !attr->transfer) {
5718 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5719 MLX5_FLOW_ACTION_RSS)))
5720 return rte_flow_error_set(error, EINVAL,
5721 RTE_FLOW_ERROR_TYPE_ACTION,
5723 "Ingress must has a dest "
5724 "QUEUE for Sample");
5725 } else if (attr->egress && !attr->transfer) {
5726 return rte_flow_error_set(error, ENOTSUP,
5727 RTE_FLOW_ERROR_TYPE_ACTION,
5729 "Sample Only support Ingress "
5731 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5732 MLX5_ASSERT(attr->transfer);
5733 if (sample->ratio > 1)
5734 return rte_flow_error_set(error, ENOTSUP,
5735 RTE_FLOW_ERROR_TYPE_ACTION,
5737 "E-Switch doesn't support "
5738 "any optional action "
5740 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5741 return rte_flow_error_set(error, ENOTSUP,
5742 RTE_FLOW_ERROR_TYPE_ACTION,
5744 "unsupported action QUEUE");
5745 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5746 return rte_flow_error_set(error, ENOTSUP,
5747 RTE_FLOW_ERROR_TYPE_ACTION,
5749 "unsupported action QUEUE");
5750 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5751 return rte_flow_error_set(error, EINVAL,
5752 RTE_FLOW_ERROR_TYPE_ACTION,
5754 "E-Switch must has a dest "
5755 "port for mirroring");
5756 if (!priv->config.hca_attr.reg_c_preserve &&
5757 priv->representor_id != UINT16_MAX)
5758 *fdb_mirror_limit = 1;
5760 /* Continue validation for Xcap actions.*/
5761 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5762 (queue_index == 0xFFFF ||
5763 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5764 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5765 MLX5_FLOW_XCAP_ACTIONS)
5766 return rte_flow_error_set(error, ENOTSUP,
5767 RTE_FLOW_ERROR_TYPE_ACTION,
5768 NULL, "encap and decap "
5769 "combination aren't "
5771 if (!attr->transfer && attr->ingress && (sub_action_flags &
5772 MLX5_FLOW_ACTION_ENCAP))
5773 return rte_flow_error_set(error, ENOTSUP,
5774 RTE_FLOW_ERROR_TYPE_ACTION,
5775 NULL, "encap is not supported"
5776 " for ingress traffic");
5782 * Find existing modify-header resource or create and register a new one.
5784 * @param dev[in, out]
5785 * Pointer to rte_eth_dev structure.
5786 * @param[in, out] resource
5787 * Pointer to modify-header resource.
5788 * @parm[in, out] dev_flow
5789 * Pointer to the dev_flow.
5791 * pointer to error structure.
5794 * 0 on success otherwise -errno and errno is set.
5797 flow_dv_modify_hdr_resource_register
5798 (struct rte_eth_dev *dev,
5799 struct mlx5_flow_dv_modify_hdr_resource *resource,
5800 struct mlx5_flow *dev_flow,
5801 struct rte_flow_error *error)
5803 struct mlx5_priv *priv = dev->data->dev_private;
5804 struct mlx5_dev_ctx_shared *sh = priv->sh;
5805 uint32_t key_len = sizeof(*resource) -
5806 offsetof(typeof(*resource), ft_type) +
5807 resource->actions_num * sizeof(resource->actions[0]);
5808 struct mlx5_list_entry *entry;
5809 struct mlx5_flow_cb_ctx ctx = {
5813 struct mlx5_hlist *modify_cmds;
5816 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5818 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5820 flow_dv_modify_create_cb,
5821 flow_dv_modify_match_cb,
5822 flow_dv_modify_remove_cb,
5823 flow_dv_modify_clone_cb,
5824 flow_dv_modify_clone_free_cb);
5825 if (unlikely(!modify_cmds))
5827 resource->root = !dev_flow->dv.group;
5828 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5830 return rte_flow_error_set(error, EOVERFLOW,
5831 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5832 "too many modify header items");
5833 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5834 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5837 resource = container_of(entry, typeof(*resource), entry);
5838 dev_flow->handle->dvh.modify_hdr = resource;
5843 * Get DV flow counter by index.
5846 * Pointer to the Ethernet device structure.
5848 * mlx5 flow counter index in the container.
5850 * mlx5 flow counter pool in the container.
5853 * Pointer to the counter, NULL otherwise.
5855 static struct mlx5_flow_counter *
5856 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5858 struct mlx5_flow_counter_pool **ppool)
5860 struct mlx5_priv *priv = dev->data->dev_private;
5861 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5862 struct mlx5_flow_counter_pool *pool;
5864 /* Decrease to original index and clear shared bit. */
5865 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5866 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5867 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5871 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5875 * Check the devx counter belongs to the pool.
5878 * Pointer to the counter pool.
5880 * The counter devx ID.
5883 * True if counter belongs to the pool, false otherwise.
5886 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5888 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5889 MLX5_COUNTERS_PER_POOL;
5891 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5897 * Get a pool by devx counter ID.
5900 * Pointer to the counter management.
5902 * The counter devx ID.
5905 * The counter pool pointer if exists, NULL otherwise,
5907 static struct mlx5_flow_counter_pool *
5908 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5911 struct mlx5_flow_counter_pool *pool = NULL;
5913 rte_spinlock_lock(&cmng->pool_update_sl);
5914 /* Check last used pool. */
5915 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5916 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5917 pool = cmng->pools[cmng->last_pool_idx];
5920 /* ID out of range means no suitable pool in the container. */
5921 if (id > cmng->max_id || id < cmng->min_id)
5924 * Find the pool from the end of the container, since mostly counter
5925 * ID is sequence increasing, and the last pool should be the needed
5930 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5932 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5938 rte_spinlock_unlock(&cmng->pool_update_sl);
5943 * Resize a counter container.
5946 * Pointer to the Ethernet device structure.
5949 * 0 on success, otherwise negative errno value and rte_errno is set.
5952 flow_dv_container_resize(struct rte_eth_dev *dev)
5954 struct mlx5_priv *priv = dev->data->dev_private;
5955 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5956 void *old_pools = cmng->pools;
5957 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5958 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5959 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5966 memcpy(pools, old_pools, cmng->n *
5967 sizeof(struct mlx5_flow_counter_pool *));
5969 cmng->pools = pools;
5971 mlx5_free(old_pools);
5976 * Query a devx flow counter.
5979 * Pointer to the Ethernet device structure.
5980 * @param[in] counter
5981 * Index to the flow counter.
5983 * The statistics value of packets.
5985 * The statistics value of bytes.
5988 * 0 on success, otherwise a negative errno value and rte_errno is set.
5991 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5994 struct mlx5_priv *priv = dev->data->dev_private;
5995 struct mlx5_flow_counter_pool *pool = NULL;
5996 struct mlx5_flow_counter *cnt;
5999 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6001 if (priv->sh->cmng.counter_fallback)
6002 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6003 0, pkts, bytes, 0, NULL, NULL, 0);
6004 rte_spinlock_lock(&pool->sl);
6009 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6010 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6011 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6013 rte_spinlock_unlock(&pool->sl);
6018 * Create and initialize a new counter pool.
6021 * Pointer to the Ethernet device structure.
6023 * The devX counter handle.
6025 * Whether the pool is for counter that was allocated for aging.
6026 * @param[in/out] cont_cur
6027 * Pointer to the container pointer, it will be update in pool resize.
6030 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6032 static struct mlx5_flow_counter_pool *
6033 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6036 struct mlx5_priv *priv = dev->data->dev_private;
6037 struct mlx5_flow_counter_pool *pool;
6038 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6039 bool fallback = priv->sh->cmng.counter_fallback;
6040 uint32_t size = sizeof(*pool);
6042 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6043 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6044 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6050 pool->is_aged = !!age;
6051 pool->query_gen = 0;
6052 pool->min_dcs = dcs;
6053 rte_spinlock_init(&pool->sl);
6054 rte_spinlock_init(&pool->csl);
6055 TAILQ_INIT(&pool->counters[0]);
6056 TAILQ_INIT(&pool->counters[1]);
6057 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6058 rte_spinlock_lock(&cmng->pool_update_sl);
6059 pool->index = cmng->n_valid;
6060 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6062 rte_spinlock_unlock(&cmng->pool_update_sl);
6065 cmng->pools[pool->index] = pool;
6067 if (unlikely(fallback)) {
6068 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6070 if (base < cmng->min_id)
6071 cmng->min_id = base;
6072 if (base > cmng->max_id)
6073 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6074 cmng->last_pool_idx = pool->index;
6076 rte_spinlock_unlock(&cmng->pool_update_sl);
6081 * Prepare a new counter and/or a new counter pool.
6084 * Pointer to the Ethernet device structure.
6085 * @param[out] cnt_free
6086 * Where to put the pointer of a new counter.
6088 * Whether the pool is for counter that was allocated for aging.
6091 * The counter pool pointer and @p cnt_free is set on success,
6092 * NULL otherwise and rte_errno is set.
6094 static struct mlx5_flow_counter_pool *
6095 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6096 struct mlx5_flow_counter **cnt_free,
6099 struct mlx5_priv *priv = dev->data->dev_private;
6100 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6101 struct mlx5_flow_counter_pool *pool;
6102 struct mlx5_counters tmp_tq;
6103 struct mlx5_devx_obj *dcs = NULL;
6104 struct mlx5_flow_counter *cnt;
6105 enum mlx5_counter_type cnt_type =
6106 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6107 bool fallback = priv->sh->cmng.counter_fallback;
6111 /* bulk_bitmap must be 0 for single counter allocation. */
6112 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6115 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6117 pool = flow_dv_pool_create(dev, dcs, age);
6119 mlx5_devx_cmd_destroy(dcs);
6123 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6124 cnt = MLX5_POOL_GET_CNT(pool, i);
6126 cnt->dcs_when_free = dcs;
6130 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6132 rte_errno = ENODATA;
6135 pool = flow_dv_pool_create(dev, dcs, age);
6137 mlx5_devx_cmd_destroy(dcs);
6140 TAILQ_INIT(&tmp_tq);
6141 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6142 cnt = MLX5_POOL_GET_CNT(pool, i);
6144 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6146 rte_spinlock_lock(&cmng->csl[cnt_type]);
6147 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6148 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6149 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6150 (*cnt_free)->pool = pool;
6155 * Allocate a flow counter.
6158 * Pointer to the Ethernet device structure.
6160 * Whether the counter was allocated for aging.
6163 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6166 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6168 struct mlx5_priv *priv = dev->data->dev_private;
6169 struct mlx5_flow_counter_pool *pool = NULL;
6170 struct mlx5_flow_counter *cnt_free = NULL;
6171 bool fallback = priv->sh->cmng.counter_fallback;
6172 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6173 enum mlx5_counter_type cnt_type =
6174 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6177 if (!priv->sh->devx) {
6178 rte_errno = ENOTSUP;
6181 /* Get free counters from container. */
6182 rte_spinlock_lock(&cmng->csl[cnt_type]);
6183 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6185 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6186 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6187 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6189 pool = cnt_free->pool;
6191 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6192 /* Create a DV counter action only in the first time usage. */
6193 if (!cnt_free->action) {
6195 struct mlx5_devx_obj *dcs;
6199 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6200 dcs = pool->min_dcs;
6203 dcs = cnt_free->dcs_when_free;
6205 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6212 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6213 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6214 /* Update the counter reset values. */
6215 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6218 if (!fallback && !priv->sh->cmng.query_thread_on)
6219 /* Start the asynchronous batch query by the host thread. */
6220 mlx5_set_query_alarm(priv->sh);
6222 * When the count action isn't shared (by ID), shared_info field is
6223 * used for indirect action API's refcnt.
6224 * When the counter action is not shared neither by ID nor by indirect
6225 * action API, shared info must be 1.
6227 cnt_free->shared_info.refcnt = 1;
6231 cnt_free->pool = pool;
6233 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6234 rte_spinlock_lock(&cmng->csl[cnt_type]);
6235 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6236 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6242 * Get age param from counter index.
6245 * Pointer to the Ethernet device structure.
6246 * @param[in] counter
6247 * Index to the counter handler.
6250 * The aging parameter specified for the counter index.
6252 static struct mlx5_age_param*
6253 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6256 struct mlx5_flow_counter *cnt;
6257 struct mlx5_flow_counter_pool *pool = NULL;
6259 flow_dv_counter_get_by_idx(dev, counter, &pool);
6260 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6261 cnt = MLX5_POOL_GET_CNT(pool, counter);
6262 return MLX5_CNT_TO_AGE(cnt);
6266 * Remove a flow counter from aged counter list.
6269 * Pointer to the Ethernet device structure.
6270 * @param[in] counter
6271 * Index to the counter handler.
6273 * Pointer to the counter handler.
6276 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6277 uint32_t counter, struct mlx5_flow_counter *cnt)
6279 struct mlx5_age_info *age_info;
6280 struct mlx5_age_param *age_param;
6281 struct mlx5_priv *priv = dev->data->dev_private;
6282 uint16_t expected = AGE_CANDIDATE;
6284 age_info = GET_PORT_AGE_INFO(priv);
6285 age_param = flow_dv_counter_idx_get_age(dev, counter);
6286 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6287 AGE_FREE, false, __ATOMIC_RELAXED,
6288 __ATOMIC_RELAXED)) {
6290 * We need the lock even it is age timeout,
6291 * since counter may still in process.
6293 rte_spinlock_lock(&age_info->aged_sl);
6294 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6295 rte_spinlock_unlock(&age_info->aged_sl);
6296 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6301 * Release a flow counter.
6304 * Pointer to the Ethernet device structure.
6305 * @param[in] counter
6306 * Index to the counter handler.
6309 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6311 struct mlx5_priv *priv = dev->data->dev_private;
6312 struct mlx5_flow_counter_pool *pool = NULL;
6313 struct mlx5_flow_counter *cnt;
6314 enum mlx5_counter_type cnt_type;
6318 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6320 if (pool->is_aged) {
6321 flow_dv_counter_remove_from_age(dev, counter, cnt);
6324 * If the counter action is shared by indirect action API,
6325 * the atomic function reduces its references counter.
6326 * If after the reduction the action is still referenced, the
6327 * function returns here and does not release it.
6328 * When the counter action is not shared by
6329 * indirect action API, shared info is 1 before the reduction,
6330 * so this condition is failed and function doesn't return here.
6332 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6338 * Put the counter back to list to be updated in none fallback mode.
6339 * Currently, we are using two list alternately, while one is in query,
6340 * add the freed counter to the other list based on the pool query_gen
6341 * value. After query finishes, add counter the list to the global
6342 * container counter list. The list changes while query starts. In
6343 * this case, lock will not be needed as query callback and release
6344 * function both operate with the different list.
6346 if (!priv->sh->cmng.counter_fallback) {
6347 rte_spinlock_lock(&pool->csl);
6348 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6349 rte_spinlock_unlock(&pool->csl);
6351 cnt->dcs_when_free = cnt->dcs_when_active;
6352 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6353 MLX5_COUNTER_TYPE_ORIGIN;
6354 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6355 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6357 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6362 * Resize a meter id container.
6365 * Pointer to the Ethernet device structure.
6368 * 0 on success, otherwise negative errno value and rte_errno is set.
6371 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6373 struct mlx5_priv *priv = dev->data->dev_private;
6374 struct mlx5_aso_mtr_pools_mng *pools_mng =
6375 &priv->sh->mtrmng->pools_mng;
6376 void *old_pools = pools_mng->pools;
6377 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6378 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6379 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6386 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6391 memcpy(pools, old_pools, pools_mng->n *
6392 sizeof(struct mlx5_aso_mtr_pool *));
6393 pools_mng->n = resize;
6394 pools_mng->pools = pools;
6396 mlx5_free(old_pools);
6401 * Prepare a new meter and/or a new meter pool.
6404 * Pointer to the Ethernet device structure.
6405 * @param[out] mtr_free
6406 * Where to put the pointer of a new meter.g.
6409 * The meter pool pointer and @mtr_free is set on success,
6410 * NULL otherwise and rte_errno is set.
6412 static struct mlx5_aso_mtr_pool *
6413 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6415 struct mlx5_priv *priv = dev->data->dev_private;
6416 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6417 struct mlx5_aso_mtr_pool *pool = NULL;
6418 struct mlx5_devx_obj *dcs = NULL;
6420 uint32_t log_obj_size;
6422 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6423 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6424 priv->sh->cdev->pdn,
6427 rte_errno = ENODATA;
6430 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6433 claim_zero(mlx5_devx_cmd_destroy(dcs));
6436 pool->devx_obj = dcs;
6437 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6438 pool->index = pools_mng->n_valid;
6439 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6441 claim_zero(mlx5_devx_cmd_destroy(dcs));
6442 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6445 pools_mng->pools[pool->index] = pool;
6446 pools_mng->n_valid++;
6447 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6448 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6449 pool->mtrs[i].offset = i;
6450 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6452 pool->mtrs[0].offset = 0;
6453 *mtr_free = &pool->mtrs[0];
6458 * Release a flow meter into pool.
6461 * Pointer to the Ethernet device structure.
6462 * @param[in] mtr_idx
6463 * Index to aso flow meter.
6466 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6468 struct mlx5_priv *priv = dev->data->dev_private;
6469 struct mlx5_aso_mtr_pools_mng *pools_mng =
6470 &priv->sh->mtrmng->pools_mng;
6471 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6473 MLX5_ASSERT(aso_mtr);
6474 rte_spinlock_lock(&pools_mng->mtrsl);
6475 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6476 aso_mtr->state = ASO_METER_FREE;
6477 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6478 rte_spinlock_unlock(&pools_mng->mtrsl);
6482 * Allocate a aso flow meter.
6485 * Pointer to the Ethernet device structure.
6488 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6491 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6493 struct mlx5_priv *priv = dev->data->dev_private;
6494 struct mlx5_aso_mtr *mtr_free = NULL;
6495 struct mlx5_aso_mtr_pools_mng *pools_mng =
6496 &priv->sh->mtrmng->pools_mng;
6497 struct mlx5_aso_mtr_pool *pool;
6498 uint32_t mtr_idx = 0;
6500 if (!priv->sh->devx) {
6501 rte_errno = ENOTSUP;
6504 /* Allocate the flow meter memory. */
6505 /* Get free meters from management. */
6506 rte_spinlock_lock(&pools_mng->mtrsl);
6507 mtr_free = LIST_FIRST(&pools_mng->meters);
6509 LIST_REMOVE(mtr_free, next);
6510 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6511 rte_spinlock_unlock(&pools_mng->mtrsl);
6514 mtr_free->state = ASO_METER_WAIT;
6515 rte_spinlock_unlock(&pools_mng->mtrsl);
6516 pool = container_of(mtr_free,
6517 struct mlx5_aso_mtr_pool,
6518 mtrs[mtr_free->offset]);
6519 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6520 if (!mtr_free->fm.meter_action) {
6521 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6522 struct rte_flow_error error;
6525 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6526 mtr_free->fm.meter_action =
6527 mlx5_glue->dv_create_flow_action_aso
6528 (priv->sh->rx_domain,
6529 pool->devx_obj->obj,
6531 (1 << MLX5_FLOW_COLOR_GREEN),
6533 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6534 if (!mtr_free->fm.meter_action) {
6535 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6543 * Verify the @p attributes will be correctly understood by the NIC and store
6544 * them in the @p flow if everything is correct.
6547 * Pointer to dev struct.
6548 * @param[in] attributes
6549 * Pointer to flow attributes
6550 * @param[in] external
6551 * This flow rule is created by request external to PMD.
6553 * Pointer to error structure.
6556 * - 0 on success and non root table.
6557 * - 1 on success and root table.
6558 * - a negative errno value otherwise and rte_errno is set.
6561 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6562 const struct mlx5_flow_tunnel *tunnel,
6563 const struct rte_flow_attr *attributes,
6564 const struct flow_grp_info *grp_info,
6565 struct rte_flow_error *error)
6567 struct mlx5_priv *priv = dev->data->dev_private;
6568 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6571 #ifndef HAVE_MLX5DV_DR
6572 RTE_SET_USED(tunnel);
6573 RTE_SET_USED(grp_info);
6574 if (attributes->group)
6575 return rte_flow_error_set(error, ENOTSUP,
6576 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6578 "groups are not supported");
6582 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6587 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6589 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6590 attributes->priority > lowest_priority)
6591 return rte_flow_error_set(error, ENOTSUP,
6592 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6594 "priority out of range");
6595 if (attributes->transfer) {
6596 if (!priv->config.dv_esw_en)
6597 return rte_flow_error_set
6599 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6600 "E-Switch dr is not supported");
6601 if (!(priv->representor || priv->master))
6602 return rte_flow_error_set
6603 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6604 NULL, "E-Switch configuration can only be"
6605 " done by a master or a representor device");
6606 if (attributes->egress)
6607 return rte_flow_error_set
6609 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6610 "egress is not supported");
6612 if (!(attributes->egress ^ attributes->ingress))
6613 return rte_flow_error_set(error, ENOTSUP,
6614 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6615 "must specify exactly one of "
6616 "ingress or egress");
6621 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6622 int64_t pattern_flags, uint64_t l3_flags,
6623 uint64_t l4_flags, uint64_t ip4_flag,
6624 struct rte_flow_error *error)
6626 if (mask->l3_ok && !(pattern_flags & l3_flags))
6627 return rte_flow_error_set(error, EINVAL,
6628 RTE_FLOW_ERROR_TYPE_ITEM,
6629 NULL, "missing L3 protocol");
6631 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6632 return rte_flow_error_set(error, EINVAL,
6633 RTE_FLOW_ERROR_TYPE_ITEM,
6634 NULL, "missing IPv4 protocol");
6636 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6637 return rte_flow_error_set(error, EINVAL,
6638 RTE_FLOW_ERROR_TYPE_ITEM,
6639 NULL, "missing L4 protocol");
6645 flow_dv_validate_item_integrity_post(const struct
6646 rte_flow_item *integrity_items[2],
6647 int64_t pattern_flags,
6648 struct rte_flow_error *error)
6650 const struct rte_flow_item_integrity *mask;
6653 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6654 mask = (typeof(mask))integrity_items[0]->mask;
6655 ret = validate_integrity_bits(mask, pattern_flags,
6656 MLX5_FLOW_LAYER_OUTER_L3,
6657 MLX5_FLOW_LAYER_OUTER_L4,
6658 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6663 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6664 mask = (typeof(mask))integrity_items[1]->mask;
6665 ret = validate_integrity_bits(mask, pattern_flags,
6666 MLX5_FLOW_LAYER_INNER_L3,
6667 MLX5_FLOW_LAYER_INNER_L4,
6668 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6677 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6678 const struct rte_flow_item *integrity_item,
6679 uint64_t pattern_flags, uint64_t *last_item,
6680 const struct rte_flow_item *integrity_items[2],
6681 struct rte_flow_error *error)
6683 struct mlx5_priv *priv = dev->data->dev_private;
6684 const struct rte_flow_item_integrity *mask = (typeof(mask))
6685 integrity_item->mask;
6686 const struct rte_flow_item_integrity *spec = (typeof(spec))
6687 integrity_item->spec;
6689 if (!priv->config.hca_attr.pkt_integrity_match)
6690 return rte_flow_error_set(error, ENOTSUP,
6691 RTE_FLOW_ERROR_TYPE_ITEM,
6693 "packet integrity integrity_item not supported");
6695 return rte_flow_error_set(error, ENOTSUP,
6696 RTE_FLOW_ERROR_TYPE_ITEM,
6698 "no spec for integrity item");
6700 mask = &rte_flow_item_integrity_mask;
6701 if (!mlx5_validate_integrity_item(mask))
6702 return rte_flow_error_set(error, ENOTSUP,
6703 RTE_FLOW_ERROR_TYPE_ITEM,
6705 "unsupported integrity filter");
6706 if (spec->level > 1) {
6707 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6708 return rte_flow_error_set
6710 RTE_FLOW_ERROR_TYPE_ITEM,
6711 NULL, "multiple inner integrity items not supported");
6712 integrity_items[1] = integrity_item;
6713 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6715 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6716 return rte_flow_error_set
6718 RTE_FLOW_ERROR_TYPE_ITEM,
6719 NULL, "multiple outer integrity items not supported");
6720 integrity_items[0] = integrity_item;
6721 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6727 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6728 const struct rte_flow_item *item,
6729 uint64_t item_flags,
6730 uint64_t *last_item,
6732 struct rte_flow_error *error)
6734 const struct rte_flow_item_flex *flow_spec = item->spec;
6735 const struct rte_flow_item_flex *flow_mask = item->mask;
6736 struct mlx5_flex_item *flex;
6739 return rte_flow_error_set(error, EINVAL,
6740 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6741 "flex flow item spec cannot be NULL");
6743 return rte_flow_error_set(error, EINVAL,
6744 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6745 "flex flow item mask cannot be NULL");
6747 return rte_flow_error_set(error, ENOTSUP,
6748 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6749 "flex flow item last not supported");
6750 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6751 return rte_flow_error_set(error, EINVAL,
6752 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6753 "invalid flex flow item handle");
6754 flex = (struct mlx5_flex_item *)flow_spec->handle;
6755 switch (flex->tunnel_mode) {
6756 case FLEX_TUNNEL_MODE_SINGLE:
6758 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6759 rte_flow_error_set(error, EINVAL,
6760 RTE_FLOW_ERROR_TYPE_ITEM,
6761 NULL, "multiple flex items not supported");
6763 case FLEX_TUNNEL_MODE_OUTER:
6765 rte_flow_error_set(error, EINVAL,
6766 RTE_FLOW_ERROR_TYPE_ITEM,
6767 NULL, "inner flex item was not configured");
6768 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6769 rte_flow_error_set(error, ENOTSUP,
6770 RTE_FLOW_ERROR_TYPE_ITEM,
6771 NULL, "multiple flex items not supported");
6773 case FLEX_TUNNEL_MODE_INNER:
6775 rte_flow_error_set(error, EINVAL,
6776 RTE_FLOW_ERROR_TYPE_ITEM,
6777 NULL, "outer flex item was not configured");
6778 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6779 rte_flow_error_set(error, EINVAL,
6780 RTE_FLOW_ERROR_TYPE_ITEM,
6781 NULL, "multiple flex items not supported");
6783 case FLEX_TUNNEL_MODE_MULTI:
6784 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6785 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6786 rte_flow_error_set(error, EINVAL,
6787 RTE_FLOW_ERROR_TYPE_ITEM,
6788 NULL, "multiple flex items not supported");
6791 case FLEX_TUNNEL_MODE_TUNNEL:
6792 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6793 rte_flow_error_set(error, EINVAL,
6794 RTE_FLOW_ERROR_TYPE_ITEM,
6795 NULL, "multiple flex tunnel items not supported");
6798 rte_flow_error_set(error, EINVAL,
6799 RTE_FLOW_ERROR_TYPE_ITEM,
6800 NULL, "invalid flex item configuration");
6802 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6803 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6804 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6809 * Internal validation function. For validating both actions and items.
6812 * Pointer to the rte_eth_dev structure.
6814 * Pointer to the flow attributes.
6816 * Pointer to the list of items.
6817 * @param[in] actions
6818 * Pointer to the list of actions.
6819 * @param[in] external
6820 * This flow rule is created by request external to PMD.
6821 * @param[in] hairpin
6822 * Number of hairpin TX actions, 0 means classic flow.
6824 * Pointer to the error structure.
6827 * 0 on success, a negative errno value otherwise and rte_errno is set.
6830 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6831 const struct rte_flow_item items[],
6832 const struct rte_flow_action actions[],
6833 bool external, int hairpin, struct rte_flow_error *error)
6836 uint64_t action_flags = 0;
6837 uint64_t item_flags = 0;
6838 uint64_t last_item = 0;
6839 uint8_t next_protocol = 0xff;
6840 uint16_t ether_type = 0;
6842 uint8_t item_ipv6_proto = 0;
6843 int fdb_mirror_limit = 0;
6844 int modify_after_mirror = 0;
6845 const struct rte_flow_item *geneve_item = NULL;
6846 const struct rte_flow_item *gre_item = NULL;
6847 const struct rte_flow_item *gtp_item = NULL;
6848 const struct rte_flow_action_raw_decap *decap;
6849 const struct rte_flow_action_raw_encap *encap;
6850 const struct rte_flow_action_rss *rss = NULL;
6851 const struct rte_flow_action_rss *sample_rss = NULL;
6852 const struct rte_flow_action_count *sample_count = NULL;
6853 const struct rte_flow_item_tcp nic_tcp_mask = {
6856 .src_port = RTE_BE16(UINT16_MAX),
6857 .dst_port = RTE_BE16(UINT16_MAX),
6860 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6863 "\xff\xff\xff\xff\xff\xff\xff\xff"
6864 "\xff\xff\xff\xff\xff\xff\xff\xff",
6866 "\xff\xff\xff\xff\xff\xff\xff\xff"
6867 "\xff\xff\xff\xff\xff\xff\xff\xff",
6868 .vtc_flow = RTE_BE32(0xffffffff),
6874 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6878 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6882 .dummy[0] = 0xffffffff,
6885 struct mlx5_priv *priv = dev->data->dev_private;
6886 struct mlx5_dev_config *dev_conf = &priv->config;
6887 uint16_t queue_index = 0xFFFF;
6888 const struct rte_flow_item_vlan *vlan_m = NULL;
6889 uint32_t rw_act_num = 0;
6891 const struct mlx5_flow_tunnel *tunnel;
6892 enum mlx5_tof_rule_type tof_rule_type;
6893 struct flow_grp_info grp_info = {
6894 .external = !!external,
6895 .transfer = !!attr->transfer,
6896 .fdb_def_rule = !!priv->fdb_def_rule,
6897 .std_tbl_fix = true,
6899 const struct rte_eth_hairpin_conf *conf;
6900 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6901 const struct rte_flow_item *port_id_item = NULL;
6902 bool def_policy = false;
6903 uint16_t udp_dport = 0;
6907 tunnel = is_tunnel_offload_active(dev) ?
6908 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6910 if (!priv->config.dv_flow_en)
6911 return rte_flow_error_set
6913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6914 NULL, "tunnel offload requires DV flow interface");
6915 if (priv->representor)
6916 return rte_flow_error_set
6918 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6919 NULL, "decap not supported for VF representor");
6920 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6921 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6922 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6923 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6924 MLX5_FLOW_ACTION_DECAP;
6925 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6926 (dev, attr, tunnel, tof_rule_type);
6928 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6931 is_root = (uint64_t)ret;
6932 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6933 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6934 int type = items->type;
6936 if (!mlx5_flow_os_item_supported(type))
6937 return rte_flow_error_set(error, ENOTSUP,
6938 RTE_FLOW_ERROR_TYPE_ITEM,
6939 NULL, "item not supported");
6941 case RTE_FLOW_ITEM_TYPE_VOID:
6943 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6944 ret = flow_dv_validate_item_port_id
6945 (dev, items, attr, item_flags, error);
6948 last_item = MLX5_FLOW_ITEM_PORT_ID;
6949 port_id_item = items;
6951 case RTE_FLOW_ITEM_TYPE_ETH:
6952 ret = mlx5_flow_validate_item_eth(items, item_flags,
6956 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6957 MLX5_FLOW_LAYER_OUTER_L2;
6958 if (items->mask != NULL && items->spec != NULL) {
6960 ((const struct rte_flow_item_eth *)
6963 ((const struct rte_flow_item_eth *)
6965 ether_type = rte_be_to_cpu_16(ether_type);
6970 case RTE_FLOW_ITEM_TYPE_VLAN:
6971 ret = flow_dv_validate_item_vlan(items, item_flags,
6975 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6976 MLX5_FLOW_LAYER_OUTER_VLAN;
6977 if (items->mask != NULL && items->spec != NULL) {
6979 ((const struct rte_flow_item_vlan *)
6980 items->spec)->inner_type;
6982 ((const struct rte_flow_item_vlan *)
6983 items->mask)->inner_type;
6984 ether_type = rte_be_to_cpu_16(ether_type);
6988 /* Store outer VLAN mask for of_push_vlan action. */
6990 vlan_m = items->mask;
6992 case RTE_FLOW_ITEM_TYPE_IPV4:
6993 mlx5_flow_tunnel_ip_check(items, next_protocol,
6994 &item_flags, &tunnel);
6995 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
6996 last_item, ether_type,
7000 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7001 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7002 if (items->mask != NULL &&
7003 ((const struct rte_flow_item_ipv4 *)
7004 items->mask)->hdr.next_proto_id) {
7006 ((const struct rte_flow_item_ipv4 *)
7007 (items->spec))->hdr.next_proto_id;
7009 ((const struct rte_flow_item_ipv4 *)
7010 (items->mask))->hdr.next_proto_id;
7012 /* Reset for inner layer. */
7013 next_protocol = 0xff;
7016 case RTE_FLOW_ITEM_TYPE_IPV6:
7017 mlx5_flow_tunnel_ip_check(items, next_protocol,
7018 &item_flags, &tunnel);
7019 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7026 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7027 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7028 if (items->mask != NULL &&
7029 ((const struct rte_flow_item_ipv6 *)
7030 items->mask)->hdr.proto) {
7032 ((const struct rte_flow_item_ipv6 *)
7033 items->spec)->hdr.proto;
7035 ((const struct rte_flow_item_ipv6 *)
7036 items->spec)->hdr.proto;
7038 ((const struct rte_flow_item_ipv6 *)
7039 items->mask)->hdr.proto;
7041 /* Reset for inner layer. */
7042 next_protocol = 0xff;
7045 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7046 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7051 last_item = tunnel ?
7052 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7053 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7054 if (items->mask != NULL &&
7055 ((const struct rte_flow_item_ipv6_frag_ext *)
7056 items->mask)->hdr.next_header) {
7058 ((const struct rte_flow_item_ipv6_frag_ext *)
7059 items->spec)->hdr.next_header;
7061 ((const struct rte_flow_item_ipv6_frag_ext *)
7062 items->mask)->hdr.next_header;
7064 /* Reset for inner layer. */
7065 next_protocol = 0xff;
7068 case RTE_FLOW_ITEM_TYPE_TCP:
7069 ret = mlx5_flow_validate_item_tcp
7076 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7077 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7079 case RTE_FLOW_ITEM_TYPE_UDP:
7080 ret = mlx5_flow_validate_item_udp(items, item_flags,
7083 const struct rte_flow_item_udp *spec = items->spec;
7084 const struct rte_flow_item_udp *mask = items->mask;
7086 mask = &rte_flow_item_udp_mask;
7088 udp_dport = rte_be_to_cpu_16
7089 (spec->hdr.dst_port &
7090 mask->hdr.dst_port);
7093 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7094 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7096 case RTE_FLOW_ITEM_TYPE_GRE:
7097 ret = mlx5_flow_validate_item_gre(items, item_flags,
7098 next_protocol, error);
7102 last_item = MLX5_FLOW_LAYER_GRE;
7104 case RTE_FLOW_ITEM_TYPE_NVGRE:
7105 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7110 last_item = MLX5_FLOW_LAYER_NVGRE;
7112 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7113 ret = mlx5_flow_validate_item_gre_key
7114 (items, item_flags, gre_item, error);
7117 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7119 case RTE_FLOW_ITEM_TYPE_VXLAN:
7120 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7125 last_item = MLX5_FLOW_LAYER_VXLAN;
7127 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7128 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7133 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7135 case RTE_FLOW_ITEM_TYPE_GENEVE:
7136 ret = mlx5_flow_validate_item_geneve(items,
7141 geneve_item = items;
7142 last_item = MLX5_FLOW_LAYER_GENEVE;
7144 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7145 ret = mlx5_flow_validate_item_geneve_opt(items,
7152 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7154 case RTE_FLOW_ITEM_TYPE_MPLS:
7155 ret = mlx5_flow_validate_item_mpls(dev, items,
7160 last_item = MLX5_FLOW_LAYER_MPLS;
7163 case RTE_FLOW_ITEM_TYPE_MARK:
7164 ret = flow_dv_validate_item_mark(dev, items, attr,
7168 last_item = MLX5_FLOW_ITEM_MARK;
7170 case RTE_FLOW_ITEM_TYPE_META:
7171 ret = flow_dv_validate_item_meta(dev, items, attr,
7175 last_item = MLX5_FLOW_ITEM_METADATA;
7177 case RTE_FLOW_ITEM_TYPE_ICMP:
7178 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7183 last_item = MLX5_FLOW_LAYER_ICMP;
7185 case RTE_FLOW_ITEM_TYPE_ICMP6:
7186 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7191 item_ipv6_proto = IPPROTO_ICMPV6;
7192 last_item = MLX5_FLOW_LAYER_ICMP6;
7194 case RTE_FLOW_ITEM_TYPE_TAG:
7195 ret = flow_dv_validate_item_tag(dev, items,
7199 last_item = MLX5_FLOW_ITEM_TAG;
7201 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7202 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7204 case RTE_FLOW_ITEM_TYPE_GTP:
7205 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7210 last_item = MLX5_FLOW_LAYER_GTP;
7212 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7213 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7218 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7220 case RTE_FLOW_ITEM_TYPE_ECPRI:
7221 /* Capacity will be checked in the translate stage. */
7222 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7229 last_item = MLX5_FLOW_LAYER_ECPRI;
7231 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7232 ret = flow_dv_validate_item_integrity(dev, items,
7240 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7241 ret = flow_dv_validate_item_aso_ct(dev, items,
7242 &item_flags, error);
7246 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7247 /* tunnel offload item was processed before
7248 * list it here as a supported type
7251 case RTE_FLOW_ITEM_TYPE_FLEX:
7252 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7254 tunnel != 0, error);
7259 return rte_flow_error_set(error, ENOTSUP,
7260 RTE_FLOW_ERROR_TYPE_ITEM,
7261 NULL, "item not supported");
7263 item_flags |= last_item;
7265 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7266 ret = flow_dv_validate_item_integrity_post(integrity_items,
7271 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7272 int type = actions->type;
7273 bool shared_count = false;
7275 if (!mlx5_flow_os_action_supported(type))
7276 return rte_flow_error_set(error, ENOTSUP,
7277 RTE_FLOW_ERROR_TYPE_ACTION,
7279 "action not supported");
7280 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7281 return rte_flow_error_set(error, ENOTSUP,
7282 RTE_FLOW_ERROR_TYPE_ACTION,
7283 actions, "too many actions");
7285 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7286 return rte_flow_error_set(error, ENOTSUP,
7287 RTE_FLOW_ERROR_TYPE_ACTION,
7288 NULL, "meter action with policy "
7289 "must be the last action");
7291 case RTE_FLOW_ACTION_TYPE_VOID:
7293 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7294 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7295 ret = flow_dv_validate_action_port_id(dev,
7302 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7305 case RTE_FLOW_ACTION_TYPE_FLAG:
7306 ret = flow_dv_validate_action_flag(dev, action_flags,
7310 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7311 /* Count all modify-header actions as one. */
7312 if (!(action_flags &
7313 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7315 action_flags |= MLX5_FLOW_ACTION_FLAG |
7316 MLX5_FLOW_ACTION_MARK_EXT;
7317 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7318 modify_after_mirror = 1;
7321 action_flags |= MLX5_FLOW_ACTION_FLAG;
7324 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7326 case RTE_FLOW_ACTION_TYPE_MARK:
7327 ret = flow_dv_validate_action_mark(dev, actions,
7332 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7333 /* Count all modify-header actions as one. */
7334 if (!(action_flags &
7335 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7337 action_flags |= MLX5_FLOW_ACTION_MARK |
7338 MLX5_FLOW_ACTION_MARK_EXT;
7339 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7340 modify_after_mirror = 1;
7342 action_flags |= MLX5_FLOW_ACTION_MARK;
7345 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7347 case RTE_FLOW_ACTION_TYPE_SET_META:
7348 ret = flow_dv_validate_action_set_meta(dev, actions,
7353 /* Count all modify-header actions as one action. */
7354 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7356 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7357 modify_after_mirror = 1;
7358 action_flags |= MLX5_FLOW_ACTION_SET_META;
7359 rw_act_num += MLX5_ACT_NUM_SET_META;
7361 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7362 ret = flow_dv_validate_action_set_tag(dev, actions,
7367 /* Count all modify-header actions as one action. */
7368 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7370 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7371 modify_after_mirror = 1;
7372 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7373 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7375 case RTE_FLOW_ACTION_TYPE_DROP:
7376 ret = mlx5_flow_validate_action_drop(action_flags,
7380 action_flags |= MLX5_FLOW_ACTION_DROP;
7383 case RTE_FLOW_ACTION_TYPE_QUEUE:
7384 ret = mlx5_flow_validate_action_queue(actions,
7389 queue_index = ((const struct rte_flow_action_queue *)
7390 (actions->conf))->index;
7391 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7394 case RTE_FLOW_ACTION_TYPE_RSS:
7395 rss = actions->conf;
7396 ret = mlx5_flow_validate_action_rss(actions,
7402 if (rss && sample_rss &&
7403 (sample_rss->level != rss->level ||
7404 sample_rss->types != rss->types))
7405 return rte_flow_error_set(error, ENOTSUP,
7406 RTE_FLOW_ERROR_TYPE_ACTION,
7408 "Can't use the different RSS types "
7409 "or level in the same flow");
7410 if (rss != NULL && rss->queue_num)
7411 queue_index = rss->queue[0];
7412 action_flags |= MLX5_FLOW_ACTION_RSS;
7415 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7417 mlx5_flow_validate_action_default_miss(action_flags,
7421 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7424 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7425 shared_count = true;
7427 case RTE_FLOW_ACTION_TYPE_COUNT:
7428 ret = flow_dv_validate_action_count(dev, shared_count,
7433 action_flags |= MLX5_FLOW_ACTION_COUNT;
7436 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7437 if (flow_dv_validate_action_pop_vlan(dev,
7443 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7444 modify_after_mirror = 1;
7445 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7448 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7449 ret = flow_dv_validate_action_push_vlan(dev,
7456 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7457 modify_after_mirror = 1;
7458 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7461 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7462 ret = flow_dv_validate_action_set_vlan_pcp
7463 (action_flags, actions, error);
7466 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7467 modify_after_mirror = 1;
7468 /* Count PCP with push_vlan command. */
7469 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7471 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7472 ret = flow_dv_validate_action_set_vlan_vid
7473 (item_flags, action_flags,
7477 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7478 modify_after_mirror = 1;
7479 /* Count VID with push_vlan command. */
7480 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7481 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7483 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7484 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7485 ret = flow_dv_validate_action_l2_encap(dev,
7491 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7494 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7495 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7496 ret = flow_dv_validate_action_decap(dev, action_flags,
7497 actions, item_flags,
7501 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7502 modify_after_mirror = 1;
7503 action_flags |= MLX5_FLOW_ACTION_DECAP;
7506 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7507 ret = flow_dv_validate_action_raw_encap_decap
7508 (dev, NULL, actions->conf, attr, &action_flags,
7509 &actions_n, actions, item_flags, error);
7513 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7514 decap = actions->conf;
7515 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7517 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7521 encap = actions->conf;
7523 ret = flow_dv_validate_action_raw_encap_decap
7525 decap ? decap : &empty_decap, encap,
7526 attr, &action_flags, &actions_n,
7527 actions, item_flags, error);
7530 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7531 (action_flags & MLX5_FLOW_ACTION_DECAP))
7532 modify_after_mirror = 1;
7534 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7535 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7536 ret = flow_dv_validate_action_modify_mac(action_flags,
7542 /* Count all modify-header actions as one action. */
7543 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7545 action_flags |= actions->type ==
7546 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7547 MLX5_FLOW_ACTION_SET_MAC_SRC :
7548 MLX5_FLOW_ACTION_SET_MAC_DST;
7549 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7550 modify_after_mirror = 1;
7552 * Even if the source and destination MAC addresses have
7553 * overlap in the header with 4B alignment, the convert
7554 * function will handle them separately and 4 SW actions
7555 * will be created. And 2 actions will be added each
7556 * time no matter how many bytes of address will be set.
7558 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7560 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7561 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7562 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7568 /* Count all modify-header actions as one action. */
7569 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7571 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7572 modify_after_mirror = 1;
7573 action_flags |= actions->type ==
7574 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7575 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7576 MLX5_FLOW_ACTION_SET_IPV4_DST;
7577 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7579 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7580 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7581 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7587 if (item_ipv6_proto == IPPROTO_ICMPV6)
7588 return rte_flow_error_set(error, ENOTSUP,
7589 RTE_FLOW_ERROR_TYPE_ACTION,
7591 "Can't change header "
7592 "with ICMPv6 proto");
7593 /* Count all modify-header actions as one action. */
7594 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7596 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7597 modify_after_mirror = 1;
7598 action_flags |= actions->type ==
7599 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7600 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7601 MLX5_FLOW_ACTION_SET_IPV6_DST;
7602 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7604 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7605 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7606 ret = flow_dv_validate_action_modify_tp(action_flags,
7612 /* Count all modify-header actions as one action. */
7613 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7615 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7616 modify_after_mirror = 1;
7617 action_flags |= actions->type ==
7618 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7619 MLX5_FLOW_ACTION_SET_TP_SRC :
7620 MLX5_FLOW_ACTION_SET_TP_DST;
7621 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7623 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7624 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7625 ret = flow_dv_validate_action_modify_ttl(action_flags,
7631 /* Count all modify-header actions as one action. */
7632 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7634 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7635 modify_after_mirror = 1;
7636 action_flags |= actions->type ==
7637 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7638 MLX5_FLOW_ACTION_SET_TTL :
7639 MLX5_FLOW_ACTION_DEC_TTL;
7640 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7642 case RTE_FLOW_ACTION_TYPE_JUMP:
7643 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7649 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7651 return rte_flow_error_set(error, EINVAL,
7652 RTE_FLOW_ERROR_TYPE_ACTION,
7654 "sample and jump action combination is not supported");
7656 action_flags |= MLX5_FLOW_ACTION_JUMP;
7658 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7659 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7660 ret = flow_dv_validate_action_modify_tcp_seq
7667 /* Count all modify-header actions as one action. */
7668 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7670 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7671 modify_after_mirror = 1;
7672 action_flags |= actions->type ==
7673 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7674 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7675 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7676 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7678 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7679 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7680 ret = flow_dv_validate_action_modify_tcp_ack
7687 /* Count all modify-header actions as one action. */
7688 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7690 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7691 modify_after_mirror = 1;
7692 action_flags |= actions->type ==
7693 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7694 MLX5_FLOW_ACTION_INC_TCP_ACK :
7695 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7696 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7698 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7700 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7701 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7702 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7704 case RTE_FLOW_ACTION_TYPE_METER:
7705 ret = mlx5_flow_validate_action_meter(dev,
7714 action_flags |= MLX5_FLOW_ACTION_METER;
7717 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7719 /* Meter action will add one more TAG action. */
7720 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7722 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7723 if (!attr->transfer && !attr->group)
7724 return rte_flow_error_set(error, ENOTSUP,
7725 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7727 "Shared ASO age action is not supported for group 0");
7728 if (action_flags & MLX5_FLOW_ACTION_AGE)
7729 return rte_flow_error_set
7731 RTE_FLOW_ERROR_TYPE_ACTION,
7733 "duplicate age actions set");
7734 action_flags |= MLX5_FLOW_ACTION_AGE;
7737 case RTE_FLOW_ACTION_TYPE_AGE:
7738 ret = flow_dv_validate_action_age(action_flags,
7744 * Validate the regular AGE action (using counter)
7745 * mutual exclusion with share counter actions.
7747 if (!priv->sh->flow_hit_aso_en) {
7749 return rte_flow_error_set
7751 RTE_FLOW_ERROR_TYPE_ACTION,
7753 "old age and shared count combination is not supported");
7755 return rte_flow_error_set
7757 RTE_FLOW_ERROR_TYPE_ACTION,
7759 "old age action and count must be in the same sub flow");
7761 action_flags |= MLX5_FLOW_ACTION_AGE;
7764 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7765 ret = flow_dv_validate_action_modify_ipv4_dscp
7772 /* Count all modify-header actions as one action. */
7773 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7775 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7776 modify_after_mirror = 1;
7777 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7778 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7780 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7781 ret = flow_dv_validate_action_modify_ipv6_dscp
7788 /* Count all modify-header actions as one action. */
7789 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7791 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7792 modify_after_mirror = 1;
7793 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7794 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7796 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7797 ret = flow_dv_validate_action_sample(&action_flags,
7806 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7809 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7810 ret = flow_dv_validate_action_modify_field(dev,
7817 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7818 modify_after_mirror = 1;
7819 /* Count all modify-header actions as one action. */
7820 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7822 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7825 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7826 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7831 action_flags |= MLX5_FLOW_ACTION_CT;
7833 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7834 /* tunnel offload action was processed before
7835 * list it here as a supported type
7839 return rte_flow_error_set(error, ENOTSUP,
7840 RTE_FLOW_ERROR_TYPE_ACTION,
7842 "action not supported");
7846 * Validate actions in flow rules
7847 * - Explicit decap action is prohibited by the tunnel offload API.
7848 * - Drop action in tunnel steer rule is prohibited by the API.
7849 * - Application cannot use MARK action because it's value can mask
7850 * tunnel default miss notification.
7851 * - JUMP in tunnel match rule has no support in current PMD
7853 * - TAG & META are reserved for future uses.
7855 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7856 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7857 MLX5_FLOW_ACTION_MARK |
7858 MLX5_FLOW_ACTION_SET_TAG |
7859 MLX5_FLOW_ACTION_SET_META |
7860 MLX5_FLOW_ACTION_DROP;
7862 if (action_flags & bad_actions_mask)
7863 return rte_flow_error_set
7865 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7866 "Invalid RTE action in tunnel "
7868 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7869 return rte_flow_error_set
7871 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7872 "tunnel set decap rule must terminate "
7875 return rte_flow_error_set
7877 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7878 "tunnel flows for ingress traffic only");
7880 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7881 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7882 MLX5_FLOW_ACTION_MARK |
7883 MLX5_FLOW_ACTION_SET_TAG |
7884 MLX5_FLOW_ACTION_SET_META;
7886 if (action_flags & bad_actions_mask)
7887 return rte_flow_error_set
7889 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7890 "Invalid RTE action in tunnel "
7894 * Validate the drop action mutual exclusion with other actions.
7895 * Drop action is mutually-exclusive with any other action, except for
7897 * Drop action compatibility with tunnel offload was already validated.
7899 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7900 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7901 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7902 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7903 return rte_flow_error_set(error, EINVAL,
7904 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7905 "Drop action is mutually-exclusive "
7906 "with any other action, except for "
7908 /* Eswitch has few restrictions on using items and actions */
7909 if (attr->transfer) {
7910 if (!mlx5_flow_ext_mreg_supported(dev) &&
7911 action_flags & MLX5_FLOW_ACTION_FLAG)
7912 return rte_flow_error_set(error, ENOTSUP,
7913 RTE_FLOW_ERROR_TYPE_ACTION,
7915 "unsupported action FLAG");
7916 if (!mlx5_flow_ext_mreg_supported(dev) &&
7917 action_flags & MLX5_FLOW_ACTION_MARK)
7918 return rte_flow_error_set(error, ENOTSUP,
7919 RTE_FLOW_ERROR_TYPE_ACTION,
7921 "unsupported action MARK");
7922 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7923 return rte_flow_error_set(error, ENOTSUP,
7924 RTE_FLOW_ERROR_TYPE_ACTION,
7926 "unsupported action QUEUE");
7927 if (action_flags & MLX5_FLOW_ACTION_RSS)
7928 return rte_flow_error_set(error, ENOTSUP,
7929 RTE_FLOW_ERROR_TYPE_ACTION,
7931 "unsupported action RSS");
7932 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7933 return rte_flow_error_set(error, EINVAL,
7934 RTE_FLOW_ERROR_TYPE_ACTION,
7936 "no fate action is found");
7938 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7939 return rte_flow_error_set(error, EINVAL,
7940 RTE_FLOW_ERROR_TYPE_ACTION,
7942 "no fate action is found");
7945 * Continue validation for Xcap and VLAN actions.
7946 * If hairpin is working in explicit TX rule mode, there is no actions
7947 * splitting and the validation of hairpin ingress flow should be the
7948 * same as other standard flows.
7950 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7951 MLX5_FLOW_VLAN_ACTIONS)) &&
7952 (queue_index == 0xFFFF ||
7953 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7954 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7955 conf->tx_explicit != 0))) {
7956 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7957 MLX5_FLOW_XCAP_ACTIONS)
7958 return rte_flow_error_set(error, ENOTSUP,
7959 RTE_FLOW_ERROR_TYPE_ACTION,
7960 NULL, "encap and decap "
7961 "combination aren't supported");
7962 if (!attr->transfer && attr->ingress) {
7963 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7964 return rte_flow_error_set
7966 RTE_FLOW_ERROR_TYPE_ACTION,
7967 NULL, "encap is not supported"
7968 " for ingress traffic");
7969 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7970 return rte_flow_error_set
7972 RTE_FLOW_ERROR_TYPE_ACTION,
7973 NULL, "push VLAN action not "
7974 "supported for ingress");
7975 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7976 MLX5_FLOW_VLAN_ACTIONS)
7977 return rte_flow_error_set
7979 RTE_FLOW_ERROR_TYPE_ACTION,
7980 NULL, "no support for "
7981 "multiple VLAN actions");
7984 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7985 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7986 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7988 return rte_flow_error_set
7990 RTE_FLOW_ERROR_TYPE_ACTION,
7991 NULL, "fate action not supported for "
7992 "meter with policy");
7994 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7995 return rte_flow_error_set
7997 RTE_FLOW_ERROR_TYPE_ACTION,
7998 NULL, "modify header action in egress "
7999 "cannot be done before meter action");
8000 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8001 return rte_flow_error_set
8003 RTE_FLOW_ERROR_TYPE_ACTION,
8004 NULL, "encap action in egress "
8005 "cannot be done before meter action");
8006 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8007 return rte_flow_error_set
8009 RTE_FLOW_ERROR_TYPE_ACTION,
8010 NULL, "push vlan action in egress "
8011 "cannot be done before meter action");
8015 * Hairpin flow will add one more TAG action in TX implicit mode.
8016 * In TX explicit mode, there will be no hairpin flow ID.
8019 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8020 /* extra metadata enabled: one more TAG action will be add. */
8021 if (dev_conf->dv_flow_en &&
8022 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8023 mlx5_flow_ext_mreg_supported(dev))
8024 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8026 flow_dv_modify_hdr_action_max(dev, is_root)) {
8027 return rte_flow_error_set(error, ENOTSUP,
8028 RTE_FLOW_ERROR_TYPE_ACTION,
8029 NULL, "too many header modify"
8030 " actions to support");
8032 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8033 if (fdb_mirror_limit && modify_after_mirror)
8034 return rte_flow_error_set(error, EINVAL,
8035 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8036 "sample before modify action is not supported");
8041 * Internal preparation function. Allocates the DV flow size,
8042 * this size is constant.
8045 * Pointer to the rte_eth_dev structure.
8047 * Pointer to the flow attributes.
8049 * Pointer to the list of items.
8050 * @param[in] actions
8051 * Pointer to the list of actions.
8053 * Pointer to the error structure.
8056 * Pointer to mlx5_flow object on success,
8057 * otherwise NULL and rte_errno is set.
8059 static struct mlx5_flow *
8060 flow_dv_prepare(struct rte_eth_dev *dev,
8061 const struct rte_flow_attr *attr __rte_unused,
8062 const struct rte_flow_item items[] __rte_unused,
8063 const struct rte_flow_action actions[] __rte_unused,
8064 struct rte_flow_error *error)
8066 uint32_t handle_idx = 0;
8067 struct mlx5_flow *dev_flow;
8068 struct mlx5_flow_handle *dev_handle;
8069 struct mlx5_priv *priv = dev->data->dev_private;
8070 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8073 wks->skip_matcher_reg = 0;
8075 wks->final_policy = NULL;
8076 /* In case of corrupting the memory. */
8077 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8078 rte_flow_error_set(error, ENOSPC,
8079 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8080 "not free temporary device flow");
8083 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8086 rte_flow_error_set(error, ENOMEM,
8087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8088 "not enough memory to create flow handle");
8091 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8092 dev_flow = &wks->flows[wks->flow_idx++];
8093 memset(dev_flow, 0, sizeof(*dev_flow));
8094 dev_flow->handle = dev_handle;
8095 dev_flow->handle_idx = handle_idx;
8096 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8097 dev_flow->ingress = attr->ingress;
8098 dev_flow->dv.transfer = attr->transfer;
8102 #ifdef RTE_LIBRTE_MLX5_DEBUG
8104 * Sanity check for match mask and value. Similar to check_valid_spec() in
8105 * kernel driver. If unmasked bit is present in value, it returns failure.
8108 * pointer to match mask buffer.
8109 * @param match_value
8110 * pointer to match value buffer.
8113 * 0 if valid, -EINVAL otherwise.
8116 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8118 uint8_t *m = match_mask;
8119 uint8_t *v = match_value;
8122 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8125 "match_value differs from match_criteria"
8126 " %p[%u] != %p[%u]",
8127 match_value, i, match_mask, i);
8136 * Add match of ip_version.
8140 * @param[in] headers_v
8141 * Values header pointer.
8142 * @param[in] headers_m
8143 * Masks header pointer.
8144 * @param[in] ip_version
8145 * The IP version to set.
8148 flow_dv_set_match_ip_version(uint32_t group,
8154 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8156 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8158 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8159 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8160 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8164 * Add Ethernet item to matcher and to the value.
8166 * @param[in, out] matcher
8168 * @param[in, out] key
8169 * Flow matcher value.
8171 * Flow pattern to translate.
8173 * Item is inner pattern.
8176 flow_dv_translate_item_eth(void *matcher, void *key,
8177 const struct rte_flow_item *item, int inner,
8180 const struct rte_flow_item_eth *eth_m = item->mask;
8181 const struct rte_flow_item_eth *eth_v = item->spec;
8182 const struct rte_flow_item_eth nic_mask = {
8183 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8184 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8185 .type = RTE_BE16(0xffff),
8198 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8200 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8202 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8204 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8206 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8207 ð_m->dst, sizeof(eth_m->dst));
8208 /* The value must be in the range of the mask. */
8209 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8210 for (i = 0; i < sizeof(eth_m->dst); ++i)
8211 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8212 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8213 ð_m->src, sizeof(eth_m->src));
8214 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8215 /* The value must be in the range of the mask. */
8216 for (i = 0; i < sizeof(eth_m->dst); ++i)
8217 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8219 * HW supports match on one Ethertype, the Ethertype following the last
8220 * VLAN tag of the packet (see PRM).
8221 * Set match on ethertype only if ETH header is not followed by VLAN.
8222 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8223 * ethertype, and use ip_version field instead.
8224 * eCPRI over Ether layer will use type value 0xAEFE.
8226 if (eth_m->type == 0xFFFF) {
8227 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8228 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8229 switch (eth_v->type) {
8230 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8231 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8233 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8234 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8235 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8237 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8238 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8240 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8241 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8247 if (eth_m->has_vlan) {
8248 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8249 if (eth_v->has_vlan) {
8251 * Here, when also has_more_vlan field in VLAN item is
8252 * not set, only single-tagged packets will be matched.
8254 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8258 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8259 rte_be_to_cpu_16(eth_m->type));
8260 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8261 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8265 * Add VLAN item to matcher and to the value.
8267 * @param[in, out] dev_flow
8269 * @param[in, out] matcher
8271 * @param[in, out] key
8272 * Flow matcher value.
8274 * Flow pattern to translate.
8276 * Item is inner pattern.
8279 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8280 void *matcher, void *key,
8281 const struct rte_flow_item *item,
8282 int inner, uint32_t group)
8284 const struct rte_flow_item_vlan *vlan_m = item->mask;
8285 const struct rte_flow_item_vlan *vlan_v = item->spec;
8292 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8294 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8296 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8298 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8300 * This is workaround, masks are not supported,
8301 * and pre-validated.
8304 dev_flow->handle->vf_vlan.tag =
8305 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8308 * When VLAN item exists in flow, mark packet as tagged,
8309 * even if TCI is not specified.
8311 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8312 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8313 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8318 vlan_m = &rte_flow_item_vlan_mask;
8319 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8320 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8321 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8322 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8323 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8325 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8326 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8328 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8329 * ethertype, and use ip_version field instead.
8331 if (vlan_m->inner_type == 0xFFFF) {
8332 switch (vlan_v->inner_type) {
8333 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8335 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8338 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8339 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8341 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8342 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8348 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8349 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8350 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8351 /* Only one vlan_tag bit can be set. */
8352 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8355 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8356 rte_be_to_cpu_16(vlan_m->inner_type));
8357 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8358 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8362 * Add IPV4 item to matcher and to the value.
8364 * @param[in, out] matcher
8366 * @param[in, out] key
8367 * Flow matcher value.
8369 * Flow pattern to translate.
8371 * Item is inner pattern.
8373 * The group to insert the rule.
8376 flow_dv_translate_item_ipv4(void *matcher, void *key,
8377 const struct rte_flow_item *item,
8378 int inner, uint32_t group)
8380 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8381 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8382 const struct rte_flow_item_ipv4 nic_mask = {
8384 .src_addr = RTE_BE32(0xffffffff),
8385 .dst_addr = RTE_BE32(0xffffffff),
8386 .type_of_service = 0xff,
8387 .next_proto_id = 0xff,
8388 .time_to_live = 0xff,
8395 uint8_t tos, ihl_m, ihl_v;
8398 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8400 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8402 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8404 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8406 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8411 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8412 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8413 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8414 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8415 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8416 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8417 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8418 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8419 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8420 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8421 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8422 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8423 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8424 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8425 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8426 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8429 ipv4_m->hdr.type_of_service);
8430 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8431 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8432 ipv4_m->hdr.type_of_service >> 2);
8433 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8434 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8435 ipv4_m->hdr.next_proto_id);
8436 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8437 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8438 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8439 ipv4_m->hdr.time_to_live);
8440 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8441 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8442 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8443 !!(ipv4_m->hdr.fragment_offset));
8444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8445 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8449 * Add IPV6 item to matcher and to the value.
8451 * @param[in, out] matcher
8453 * @param[in, out] key
8454 * Flow matcher value.
8456 * Flow pattern to translate.
8458 * Item is inner pattern.
8460 * The group to insert the rule.
8463 flow_dv_translate_item_ipv6(void *matcher, void *key,
8464 const struct rte_flow_item *item,
8465 int inner, uint32_t group)
8467 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8468 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8469 const struct rte_flow_item_ipv6 nic_mask = {
8472 "\xff\xff\xff\xff\xff\xff\xff\xff"
8473 "\xff\xff\xff\xff\xff\xff\xff\xff",
8475 "\xff\xff\xff\xff\xff\xff\xff\xff"
8476 "\xff\xff\xff\xff\xff\xff\xff\xff",
8477 .vtc_flow = RTE_BE32(0xffffffff),
8484 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8485 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8494 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8496 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8498 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8500 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8502 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8507 size = sizeof(ipv6_m->hdr.dst_addr);
8508 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8509 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8510 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8511 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8512 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8513 for (i = 0; i < size; ++i)
8514 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8515 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8516 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8517 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8518 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8519 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8520 for (i = 0; i < size; ++i)
8521 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8523 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8524 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8525 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8526 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8531 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8533 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8536 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8538 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8542 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8544 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8545 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8547 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8548 ipv6_m->hdr.hop_limits);
8549 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8550 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8551 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8552 !!(ipv6_m->has_frag_ext));
8553 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8554 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8558 * Add IPV6 fragment extension item to matcher and to the value.
8560 * @param[in, out] matcher
8562 * @param[in, out] key
8563 * Flow matcher value.
8565 * Flow pattern to translate.
8567 * Item is inner pattern.
8570 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8571 const struct rte_flow_item *item,
8574 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8575 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8576 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8578 .next_header = 0xff,
8579 .frag_data = RTE_BE16(0xffff),
8586 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8588 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8590 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8592 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8594 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8595 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8596 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8597 if (!ipv6_frag_ext_v)
8599 if (!ipv6_frag_ext_m)
8600 ipv6_frag_ext_m = &nic_mask;
8601 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8602 ipv6_frag_ext_m->hdr.next_header);
8603 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8604 ipv6_frag_ext_v->hdr.next_header &
8605 ipv6_frag_ext_m->hdr.next_header);
8609 * Add TCP item to matcher and to the value.
8611 * @param[in, out] matcher
8613 * @param[in, out] key
8614 * Flow matcher value.
8616 * Flow pattern to translate.
8618 * Item is inner pattern.
8621 flow_dv_translate_item_tcp(void *matcher, void *key,
8622 const struct rte_flow_item *item,
8625 const struct rte_flow_item_tcp *tcp_m = item->mask;
8626 const struct rte_flow_item_tcp *tcp_v = item->spec;
8631 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8633 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8635 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8637 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8639 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8640 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8644 tcp_m = &rte_flow_item_tcp_mask;
8645 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8646 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8647 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8648 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8649 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8650 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8652 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8653 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8654 tcp_m->hdr.tcp_flags);
8655 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8656 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8660 * Add UDP item to matcher and to the value.
8662 * @param[in, out] matcher
8664 * @param[in, out] key
8665 * Flow matcher value.
8667 * Flow pattern to translate.
8669 * Item is inner pattern.
8672 flow_dv_translate_item_udp(void *matcher, void *key,
8673 const struct rte_flow_item *item,
8676 const struct rte_flow_item_udp *udp_m = item->mask;
8677 const struct rte_flow_item_udp *udp_v = item->spec;
8682 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8684 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8686 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8688 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8690 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8691 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8695 udp_m = &rte_flow_item_udp_mask;
8696 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8697 rte_be_to_cpu_16(udp_m->hdr.src_port));
8698 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8699 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8700 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8701 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8703 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8707 * Add GRE optional Key item to matcher and to the value.
8709 * @param[in, out] matcher
8711 * @param[in, out] key
8712 * Flow matcher value.
8714 * Flow pattern to translate.
8716 * Item is inner pattern.
8719 flow_dv_translate_item_gre_key(void *matcher, void *key,
8720 const struct rte_flow_item *item)
8722 const rte_be32_t *key_m = item->mask;
8723 const rte_be32_t *key_v = item->spec;
8724 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8725 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8726 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8728 /* GRE K bit must be on and should already be validated */
8729 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8730 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8734 key_m = &gre_key_default_mask;
8735 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8736 rte_be_to_cpu_32(*key_m) >> 8);
8737 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8738 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8739 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8740 rte_be_to_cpu_32(*key_m) & 0xFF);
8741 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8742 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8746 * Add GRE item to matcher and to the value.
8748 * @param[in, out] matcher
8750 * @param[in, out] key
8751 * Flow matcher value.
8753 * Flow pattern to translate.
8754 * @param[in] pattern_flags
8755 * Accumulated pattern flags.
8758 flow_dv_translate_item_gre(void *matcher, void *key,
8759 const struct rte_flow_item *item,
8760 uint64_t pattern_flags)
8762 static const struct rte_flow_item_gre empty_gre = {0,};
8763 const struct rte_flow_item_gre *gre_m = item->mask;
8764 const struct rte_flow_item_gre *gre_v = item->spec;
8765 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8766 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8767 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8768 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8775 uint16_t s_present:1;
8776 uint16_t k_present:1;
8777 uint16_t rsvd_bit1:1;
8778 uint16_t c_present:1;
8782 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8783 uint16_t protocol_m, protocol_v;
8785 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8792 gre_m = &rte_flow_item_gre_mask;
8794 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8795 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8796 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8797 gre_crks_rsvd0_ver_m.c_present);
8798 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8799 gre_crks_rsvd0_ver_v.c_present &
8800 gre_crks_rsvd0_ver_m.c_present);
8801 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8802 gre_crks_rsvd0_ver_m.k_present);
8803 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8804 gre_crks_rsvd0_ver_v.k_present &
8805 gre_crks_rsvd0_ver_m.k_present);
8806 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8807 gre_crks_rsvd0_ver_m.s_present);
8808 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8809 gre_crks_rsvd0_ver_v.s_present &
8810 gre_crks_rsvd0_ver_m.s_present);
8811 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8812 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8814 /* Force next protocol to prevent matchers duplication */
8815 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8817 protocol_m = 0xFFFF;
8819 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8820 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8821 protocol_m & protocol_v);
8825 * Add NVGRE item to matcher and to the value.
8827 * @param[in, out] matcher
8829 * @param[in, out] key
8830 * Flow matcher value.
8832 * Flow pattern to translate.
8833 * @param[in] pattern_flags
8834 * Accumulated pattern flags.
8837 flow_dv_translate_item_nvgre(void *matcher, void *key,
8838 const struct rte_flow_item *item,
8839 unsigned long pattern_flags)
8841 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8842 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8843 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8844 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8845 const char *tni_flow_id_m;
8846 const char *tni_flow_id_v;
8852 /* For NVGRE, GRE header fields must be set with defined values. */
8853 const struct rte_flow_item_gre gre_spec = {
8854 .c_rsvd0_ver = RTE_BE16(0x2000),
8855 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8857 const struct rte_flow_item_gre gre_mask = {
8858 .c_rsvd0_ver = RTE_BE16(0xB000),
8859 .protocol = RTE_BE16(UINT16_MAX),
8861 const struct rte_flow_item gre_item = {
8866 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8870 nvgre_m = &rte_flow_item_nvgre_mask;
8871 tni_flow_id_m = (const char *)nvgre_m->tni;
8872 tni_flow_id_v = (const char *)nvgre_v->tni;
8873 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8874 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8875 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8876 memcpy(gre_key_m, tni_flow_id_m, size);
8877 for (i = 0; i < size; ++i)
8878 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8882 * Add VXLAN item to matcher and to the value.
8885 * Pointer to the Ethernet device structure.
8887 * Flow rule attributes.
8888 * @param[in, out] matcher
8890 * @param[in, out] key
8891 * Flow matcher value.
8893 * Flow pattern to translate.
8895 * Item is inner pattern.
8898 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8899 const struct rte_flow_attr *attr,
8900 void *matcher, void *key,
8901 const struct rte_flow_item *item,
8904 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8905 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8910 uint32_t *tunnel_header_v;
8911 uint32_t *tunnel_header_m;
8913 struct mlx5_priv *priv = dev->data->dev_private;
8914 const struct rte_flow_item_vxlan nic_mask = {
8915 .vni = "\xff\xff\xff",
8920 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8922 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8924 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8926 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8928 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8929 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8930 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8931 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8932 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8934 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8938 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8939 (attr->group && !priv->sh->misc5_cap))
8940 vxlan_m = &rte_flow_item_vxlan_mask;
8942 vxlan_m = &nic_mask;
8944 if ((priv->sh->steering_format_version ==
8945 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8946 dport != MLX5_UDP_PORT_VXLAN) ||
8947 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8948 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8955 misc_m = MLX5_ADDR_OF(fte_match_param,
8956 matcher, misc_parameters);
8957 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8958 size = sizeof(vxlan_m->vni);
8959 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8960 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8961 memcpy(vni_m, vxlan_m->vni, size);
8962 for (i = 0; i < size; ++i)
8963 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8966 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8967 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8968 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8971 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8974 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8975 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8976 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8977 if (*tunnel_header_v)
8978 *tunnel_header_m = vxlan_m->vni[0] |
8979 vxlan_m->vni[1] << 8 |
8980 vxlan_m->vni[2] << 16;
8982 *tunnel_header_m = 0x0;
8983 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8984 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8985 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
8989 * Add VXLAN-GPE item to matcher and to the value.
8991 * @param[in, out] matcher
8993 * @param[in, out] key
8994 * Flow matcher value.
8996 * Flow pattern to translate.
8998 * Item is inner pattern.
9002 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9003 const struct rte_flow_item *item,
9004 const uint64_t pattern_flags)
9006 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9007 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9008 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9009 /* The item was validated to be on the outer side */
9010 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9011 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9013 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9015 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9017 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9019 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9020 int i, size = sizeof(vxlan_m->vni);
9021 uint8_t flags_m = 0xff;
9022 uint8_t flags_v = 0xc;
9023 uint8_t m_protocol, v_protocol;
9025 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9026 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9027 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9028 MLX5_UDP_PORT_VXLAN_GPE);
9031 vxlan_v = &dummy_vxlan_gpe_hdr;
9032 vxlan_m = &dummy_vxlan_gpe_hdr;
9035 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9037 memcpy(vni_m, vxlan_m->vni, size);
9038 for (i = 0; i < size; ++i)
9039 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9040 if (vxlan_m->flags) {
9041 flags_m = vxlan_m->flags;
9042 flags_v = vxlan_v->flags;
9044 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9045 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9046 m_protocol = vxlan_m->protocol;
9047 v_protocol = vxlan_v->protocol;
9049 /* Force next protocol to ensure next headers parsing. */
9050 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9051 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9052 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9053 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9054 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9055 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9059 MLX5_SET(fte_match_set_misc3, misc_m,
9060 outer_vxlan_gpe_next_protocol, m_protocol);
9061 MLX5_SET(fte_match_set_misc3, misc_v,
9062 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9066 * Add Geneve item to matcher and to the value.
9068 * @param[in, out] matcher
9070 * @param[in, out] key
9071 * Flow matcher value.
9073 * Flow pattern to translate.
9075 * Item is inner pattern.
9079 flow_dv_translate_item_geneve(void *matcher, void *key,
9080 const struct rte_flow_item *item,
9081 uint64_t pattern_flags)
9083 static const struct rte_flow_item_geneve empty_geneve = {0,};
9084 const struct rte_flow_item_geneve *geneve_m = item->mask;
9085 const struct rte_flow_item_geneve *geneve_v = item->spec;
9086 /* GENEVE flow item validation allows single tunnel item */
9087 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9088 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9089 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9090 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9093 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9094 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9095 size_t size = sizeof(geneve_m->vni), i;
9096 uint16_t protocol_m, protocol_v;
9098 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9099 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9100 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9101 MLX5_UDP_PORT_GENEVE);
9104 geneve_v = &empty_geneve;
9105 geneve_m = &empty_geneve;
9108 geneve_m = &rte_flow_item_geneve_mask;
9110 memcpy(vni_m, geneve_m->vni, size);
9111 for (i = 0; i < size; ++i)
9112 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9113 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9114 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9115 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9116 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9117 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9118 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9119 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9120 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9121 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9122 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9123 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9124 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9125 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9127 /* Force next protocol to prevent matchers duplication */
9128 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9130 protocol_m = 0xFFFF;
9132 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9133 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9134 protocol_m & protocol_v);
9138 * Create Geneve TLV option resource.
9140 * @param dev[in, out]
9141 * Pointer to rte_eth_dev structure.
9142 * @param[in, out] tag_be24
9143 * Tag value in big endian then R-shift 8.
9144 * @parm[in, out] dev_flow
9145 * Pointer to the dev_flow.
9147 * pointer to error structure.
9150 * 0 on success otherwise -errno and errno is set.
9154 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9155 const struct rte_flow_item *item,
9156 struct rte_flow_error *error)
9158 struct mlx5_priv *priv = dev->data->dev_private;
9159 struct mlx5_dev_ctx_shared *sh = priv->sh;
9160 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9161 sh->geneve_tlv_option_resource;
9162 struct mlx5_devx_obj *obj;
9163 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9168 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9169 if (geneve_opt_resource != NULL) {
9170 if (geneve_opt_resource->option_class ==
9171 geneve_opt_v->option_class &&
9172 geneve_opt_resource->option_type ==
9173 geneve_opt_v->option_type &&
9174 geneve_opt_resource->length ==
9175 geneve_opt_v->option_len) {
9176 /* We already have GENEVE TLV option obj allocated. */
9177 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9180 ret = rte_flow_error_set(error, ENOMEM,
9181 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9182 "Only one GENEVE TLV option supported");
9186 /* Create a GENEVE TLV object and resource. */
9187 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9188 geneve_opt_v->option_class,
9189 geneve_opt_v->option_type,
9190 geneve_opt_v->option_len);
9192 ret = rte_flow_error_set(error, ENODATA,
9193 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9194 "Failed to create GENEVE TLV Devx object");
9197 sh->geneve_tlv_option_resource =
9198 mlx5_malloc(MLX5_MEM_ZERO,
9199 sizeof(*geneve_opt_resource),
9201 if (!sh->geneve_tlv_option_resource) {
9202 claim_zero(mlx5_devx_cmd_destroy(obj));
9203 ret = rte_flow_error_set(error, ENOMEM,
9204 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9205 "GENEVE TLV object memory allocation failed");
9208 geneve_opt_resource = sh->geneve_tlv_option_resource;
9209 geneve_opt_resource->obj = obj;
9210 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9211 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9212 geneve_opt_resource->length = geneve_opt_v->option_len;
9213 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9217 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9222 * Add Geneve TLV option item to matcher.
9224 * @param[in, out] dev
9225 * Pointer to rte_eth_dev structure.
9226 * @param[in, out] matcher
9228 * @param[in, out] key
9229 * Flow matcher value.
9231 * Flow pattern to translate.
9233 * Pointer to error structure.
9236 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9237 void *key, const struct rte_flow_item *item,
9238 struct rte_flow_error *error)
9240 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9241 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9242 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9243 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9244 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9246 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9247 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9253 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9254 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9257 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9261 * Set the option length in GENEVE header if not requested.
9262 * The GENEVE TLV option length is expressed by the option length field
9263 * in the GENEVE header.
9264 * If the option length was not requested but the GENEVE TLV option item
9265 * is present we set the option length field implicitly.
9267 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9268 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9269 MLX5_GENEVE_OPTLEN_MASK);
9270 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9271 geneve_opt_v->option_len + 1);
9273 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9274 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9276 if (geneve_opt_v->data) {
9277 memcpy(&opt_data_key, geneve_opt_v->data,
9278 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9279 sizeof(opt_data_key)));
9280 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9281 sizeof(opt_data_key));
9282 memcpy(&opt_data_mask, geneve_opt_m->data,
9283 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9284 sizeof(opt_data_mask)));
9285 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9286 sizeof(opt_data_mask));
9287 MLX5_SET(fte_match_set_misc3, misc3_m,
9288 geneve_tlv_option_0_data,
9289 rte_be_to_cpu_32(opt_data_mask));
9290 MLX5_SET(fte_match_set_misc3, misc3_v,
9291 geneve_tlv_option_0_data,
9292 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9298 * Add MPLS item to matcher and to the value.
9300 * @param[in, out] matcher
9302 * @param[in, out] key
9303 * Flow matcher value.
9305 * Flow pattern to translate.
9306 * @param[in] prev_layer
9307 * The protocol layer indicated in previous item.
9309 * Item is inner pattern.
9312 flow_dv_translate_item_mpls(void *matcher, void *key,
9313 const struct rte_flow_item *item,
9314 uint64_t prev_layer,
9317 const uint32_t *in_mpls_m = item->mask;
9318 const uint32_t *in_mpls_v = item->spec;
9319 uint32_t *out_mpls_m = 0;
9320 uint32_t *out_mpls_v = 0;
9321 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9322 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9323 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9325 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9326 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9327 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9329 switch (prev_layer) {
9330 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9331 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9332 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9334 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9335 MLX5_UDP_PORT_MPLS);
9338 case MLX5_FLOW_LAYER_GRE:
9340 case MLX5_FLOW_LAYER_GRE_KEY:
9341 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9342 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9344 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9345 RTE_ETHER_TYPE_MPLS);
9354 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9355 switch (prev_layer) {
9356 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9358 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9359 outer_first_mpls_over_udp);
9361 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9362 outer_first_mpls_over_udp);
9364 case MLX5_FLOW_LAYER_GRE:
9366 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9367 outer_first_mpls_over_gre);
9369 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9370 outer_first_mpls_over_gre);
9373 /* Inner MPLS not over GRE is not supported. */
9376 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9380 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9386 if (out_mpls_m && out_mpls_v) {
9387 *out_mpls_m = *in_mpls_m;
9388 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9393 * Add metadata register item to matcher
9395 * @param[in, out] matcher
9397 * @param[in, out] key
9398 * Flow matcher value.
9399 * @param[in] reg_type
9400 * Type of device metadata register
9407 flow_dv_match_meta_reg(void *matcher, void *key,
9408 enum modify_reg reg_type,
9409 uint32_t data, uint32_t mask)
9412 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9414 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9420 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9421 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9424 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9425 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9429 * The metadata register C0 field might be divided into
9430 * source vport index and META item value, we should set
9431 * this field according to specified mask, not as whole one.
9433 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9435 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9436 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9439 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9442 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9443 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9446 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9447 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9450 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9451 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9454 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9455 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9458 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9459 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9462 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9463 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9466 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9467 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9476 * Add MARK item to matcher
9479 * The device to configure through.
9480 * @param[in, out] matcher
9482 * @param[in, out] key
9483 * Flow matcher value.
9485 * Flow pattern to translate.
9488 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9489 void *matcher, void *key,
9490 const struct rte_flow_item *item)
9492 struct mlx5_priv *priv = dev->data->dev_private;
9493 const struct rte_flow_item_mark *mark;
9497 mark = item->mask ? (const void *)item->mask :
9498 &rte_flow_item_mark_mask;
9499 mask = mark->id & priv->sh->dv_mark_mask;
9500 mark = (const void *)item->spec;
9502 value = mark->id & priv->sh->dv_mark_mask & mask;
9504 enum modify_reg reg;
9506 /* Get the metadata register index for the mark. */
9507 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9508 MLX5_ASSERT(reg > 0);
9509 if (reg == REG_C_0) {
9510 struct mlx5_priv *priv = dev->data->dev_private;
9511 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9512 uint32_t shl_c0 = rte_bsf32(msk_c0);
9518 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9523 * Add META item to matcher
9526 * The devich to configure through.
9527 * @param[in, out] matcher
9529 * @param[in, out] key
9530 * Flow matcher value.
9532 * Attributes of flow that includes this item.
9534 * Flow pattern to translate.
9537 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9538 void *matcher, void *key,
9539 const struct rte_flow_attr *attr,
9540 const struct rte_flow_item *item)
9542 const struct rte_flow_item_meta *meta_m;
9543 const struct rte_flow_item_meta *meta_v;
9545 meta_m = (const void *)item->mask;
9547 meta_m = &rte_flow_item_meta_mask;
9548 meta_v = (const void *)item->spec;
9551 uint32_t value = meta_v->data;
9552 uint32_t mask = meta_m->data;
9554 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9557 MLX5_ASSERT(reg != REG_NON);
9558 if (reg == REG_C_0) {
9559 struct mlx5_priv *priv = dev->data->dev_private;
9560 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9561 uint32_t shl_c0 = rte_bsf32(msk_c0);
9567 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9572 * Add vport metadata Reg C0 item to matcher
9574 * @param[in, out] matcher
9576 * @param[in, out] key
9577 * Flow matcher value.
9579 * Flow pattern to translate.
9582 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9583 uint32_t value, uint32_t mask)
9585 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9589 * Add tag item to matcher
9592 * The devich to configure through.
9593 * @param[in, out] matcher
9595 * @param[in, out] key
9596 * Flow matcher value.
9598 * Flow pattern to translate.
9601 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9602 void *matcher, void *key,
9603 const struct rte_flow_item *item)
9605 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9606 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9607 uint32_t mask, value;
9610 value = tag_v->data;
9611 mask = tag_m ? tag_m->data : UINT32_MAX;
9612 if (tag_v->id == REG_C_0) {
9613 struct mlx5_priv *priv = dev->data->dev_private;
9614 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9615 uint32_t shl_c0 = rte_bsf32(msk_c0);
9621 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9625 * Add TAG item to matcher
9628 * The devich to configure through.
9629 * @param[in, out] matcher
9631 * @param[in, out] key
9632 * Flow matcher value.
9634 * Flow pattern to translate.
9637 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9638 void *matcher, void *key,
9639 const struct rte_flow_item *item)
9641 const struct rte_flow_item_tag *tag_v = item->spec;
9642 const struct rte_flow_item_tag *tag_m = item->mask;
9643 enum modify_reg reg;
9646 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9647 /* Get the metadata register index for the tag. */
9648 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9649 MLX5_ASSERT(reg > 0);
9650 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9654 * Add source vport match to the specified matcher.
9656 * @param[in, out] matcher
9658 * @param[in, out] key
9659 * Flow matcher value.
9661 * Source vport value to match
9666 flow_dv_translate_item_source_vport(void *matcher, void *key,
9667 int16_t port, uint16_t mask)
9669 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9670 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9672 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9673 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9677 * Translate port-id item to eswitch match on port-id.
9680 * The devich to configure through.
9681 * @param[in, out] matcher
9683 * @param[in, out] key
9684 * Flow matcher value.
9686 * Flow pattern to translate.
9691 * 0 on success, a negative errno value otherwise.
9694 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9695 void *key, const struct rte_flow_item *item,
9696 const struct rte_flow_attr *attr)
9698 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9699 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9700 struct mlx5_priv *priv;
9703 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9704 flow_dv_translate_item_source_vport(matcher, key,
9705 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9708 mask = pid_m ? pid_m->id : 0xffff;
9709 id = pid_v ? pid_v->id : dev->data->port_id;
9710 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9714 * Translate to vport field or to metadata, depending on mode.
9715 * Kernel can use either misc.source_port or half of C0 metadata
9718 if (priv->vport_meta_mask) {
9720 * Provide the hint for SW steering library
9721 * to insert the flow into ingress domain and
9722 * save the extra vport match.
9724 if (mask == 0xffff && priv->vport_id == 0xffff &&
9725 priv->pf_bond < 0 && attr->transfer)
9726 flow_dv_translate_item_source_vport
9727 (matcher, key, priv->vport_id, mask);
9729 * We should always set the vport metadata register,
9730 * otherwise the SW steering library can drop
9731 * the rule if wire vport metadata value is not zero,
9732 * it depends on kernel configuration.
9734 flow_dv_translate_item_meta_vport(matcher, key,
9735 priv->vport_meta_tag,
9736 priv->vport_meta_mask);
9738 flow_dv_translate_item_source_vport(matcher, key,
9739 priv->vport_id, mask);
9745 * Add ICMP6 item to matcher and to the value.
9747 * @param[in, out] matcher
9749 * @param[in, out] key
9750 * Flow matcher value.
9752 * Flow pattern to translate.
9754 * Item is inner pattern.
9757 flow_dv_translate_item_icmp6(void *matcher, void *key,
9758 const struct rte_flow_item *item,
9761 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9762 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9765 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9767 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9769 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9771 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9773 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9775 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9777 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9778 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9782 icmp6_m = &rte_flow_item_icmp6_mask;
9783 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9784 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9785 icmp6_v->type & icmp6_m->type);
9786 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9787 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9788 icmp6_v->code & icmp6_m->code);
9792 * Add ICMP item to matcher and to the value.
9794 * @param[in, out] matcher
9796 * @param[in, out] key
9797 * Flow matcher value.
9799 * Flow pattern to translate.
9801 * Item is inner pattern.
9804 flow_dv_translate_item_icmp(void *matcher, void *key,
9805 const struct rte_flow_item *item,
9808 const struct rte_flow_item_icmp *icmp_m = item->mask;
9809 const struct rte_flow_item_icmp *icmp_v = item->spec;
9810 uint32_t icmp_header_data_m = 0;
9811 uint32_t icmp_header_data_v = 0;
9814 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9816 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9818 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9820 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9822 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9824 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9826 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9827 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9831 icmp_m = &rte_flow_item_icmp_mask;
9832 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9833 icmp_m->hdr.icmp_type);
9834 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9835 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9836 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9837 icmp_m->hdr.icmp_code);
9838 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9839 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9840 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9841 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9842 if (icmp_header_data_m) {
9843 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9844 icmp_header_data_v |=
9845 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9846 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9847 icmp_header_data_m);
9848 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9849 icmp_header_data_v & icmp_header_data_m);
9854 * Add GTP item to matcher and to the value.
9856 * @param[in, out] matcher
9858 * @param[in, out] key
9859 * Flow matcher value.
9861 * Flow pattern to translate.
9863 * Item is inner pattern.
9866 flow_dv_translate_item_gtp(void *matcher, void *key,
9867 const struct rte_flow_item *item, int inner)
9869 const struct rte_flow_item_gtp *gtp_m = item->mask;
9870 const struct rte_flow_item_gtp *gtp_v = item->spec;
9873 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9875 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9876 uint16_t dport = RTE_GTPU_UDP_PORT;
9879 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9881 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9883 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9885 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9887 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9888 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9889 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9894 gtp_m = &rte_flow_item_gtp_mask;
9895 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9896 gtp_m->v_pt_rsv_flags);
9897 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9898 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9899 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9900 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9901 gtp_v->msg_type & gtp_m->msg_type);
9902 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9903 rte_be_to_cpu_32(gtp_m->teid));
9904 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9905 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9909 * Add GTP PSC item to matcher.
9911 * @param[in, out] matcher
9913 * @param[in, out] key
9914 * Flow matcher value.
9916 * Flow pattern to translate.
9919 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9920 const struct rte_flow_item *item)
9922 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9923 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9924 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9926 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9932 uint8_t next_ext_header_type;
9937 /* Always set E-flag match on one, regardless of GTP item settings. */
9938 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9939 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9940 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9941 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9942 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9943 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9944 /*Set next extension header type. */
9947 dw_2.next_ext_header_type = 0xff;
9948 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9949 rte_cpu_to_be_32(dw_2.w32));
9952 dw_2.next_ext_header_type = 0x85;
9953 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9954 rte_cpu_to_be_32(dw_2.w32));
9966 /*Set extension header PDU type and Qos. */
9968 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9970 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9971 dw_0.qfi = gtp_psc_m->hdr.qfi;
9972 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9973 rte_cpu_to_be_32(dw_0.w32));
9975 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9976 gtp_psc_m->hdr.type);
9977 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9978 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9979 rte_cpu_to_be_32(dw_0.w32));
9985 * Add eCPRI item to matcher and to the value.
9988 * The devich to configure through.
9989 * @param[in, out] matcher
9991 * @param[in, out] key
9992 * Flow matcher value.
9994 * Flow pattern to translate.
9995 * @param[in] last_item
9999 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10000 void *key, const struct rte_flow_item *item,
10001 uint64_t last_item)
10003 struct mlx5_priv *priv = dev->data->dev_private;
10004 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10005 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10006 struct rte_ecpri_common_hdr common;
10007 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10008 misc_parameters_4);
10009 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10015 * In case of eCPRI over Ethernet, if EtherType is not specified,
10016 * match on eCPRI EtherType implicitly.
10018 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10019 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10021 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10022 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10023 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10024 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10025 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10026 *(uint16_t *)l2m = UINT16_MAX;
10027 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10033 ecpri_m = &rte_flow_item_ecpri_mask;
10035 * Maximal four DW samples are supported in a single matching now.
10036 * Two are used now for a eCPRI matching:
10037 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10038 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10041 if (!ecpri_m->hdr.common.u32)
10043 samples = priv->sh->ecpri_parser.ids;
10044 /* Need to take the whole DW as the mask to fill the entry. */
10045 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10046 prog_sample_field_value_0);
10047 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10048 prog_sample_field_value_0);
10049 /* Already big endian (network order) in the header. */
10050 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10051 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10052 /* Sample#0, used for matching type, offset 0. */
10053 MLX5_SET(fte_match_set_misc4, misc4_m,
10054 prog_sample_field_id_0, samples[0]);
10055 /* It makes no sense to set the sample ID in the mask field. */
10056 MLX5_SET(fte_match_set_misc4, misc4_v,
10057 prog_sample_field_id_0, samples[0]);
10059 * Checking if message body part needs to be matched.
10060 * Some wildcard rules only matching type field should be supported.
10062 if (ecpri_m->hdr.dummy[0]) {
10063 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10064 switch (common.type) {
10065 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10066 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10067 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10068 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10069 prog_sample_field_value_1);
10070 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10071 prog_sample_field_value_1);
10072 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10073 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10074 ecpri_m->hdr.dummy[0];
10075 /* Sample#1, to match message body, offset 4. */
10076 MLX5_SET(fte_match_set_misc4, misc4_m,
10077 prog_sample_field_id_1, samples[1]);
10078 MLX5_SET(fte_match_set_misc4, misc4_v,
10079 prog_sample_field_id_1, samples[1]);
10082 /* Others, do not match any sample ID. */
10089 * Add connection tracking status item to matcher
10092 * The devich to configure through.
10093 * @param[in, out] matcher
10095 * @param[in, out] key
10096 * Flow matcher value.
10098 * Flow pattern to translate.
10101 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10102 void *matcher, void *key,
10103 const struct rte_flow_item *item)
10105 uint32_t reg_value = 0;
10107 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10108 uint32_t reg_mask = 0;
10109 const struct rte_flow_item_conntrack *spec = item->spec;
10110 const struct rte_flow_item_conntrack *mask = item->mask;
10112 struct rte_flow_error error;
10115 mask = &rte_flow_item_conntrack_mask;
10116 if (!spec || !mask->flags)
10118 flags = spec->flags & mask->flags;
10119 /* The conflict should be checked in the validation. */
10120 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10121 reg_value |= MLX5_CT_SYNDROME_VALID;
10122 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10123 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10124 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10125 reg_value |= MLX5_CT_SYNDROME_INVALID;
10126 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10127 reg_value |= MLX5_CT_SYNDROME_TRAP;
10128 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10129 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10130 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10131 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10132 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10134 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10135 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10136 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10137 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10138 /* The REG_C_x value could be saved during startup. */
10139 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10140 if (reg_id == REG_NON)
10142 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10143 reg_value, reg_mask);
10147 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10148 const struct rte_flow_item *item,
10149 struct mlx5_flow *dev_flow, bool is_inner)
10151 const struct rte_flow_item_flex *spec =
10152 (const struct rte_flow_item_flex *)item->spec;
10153 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10155 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10158 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10159 /* Don't count both inner and outer flex items in one rule. */
10160 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10161 MLX5_ASSERT(false);
10162 dev_flow->handle->flex_item |= RTE_BIT32(index);
10164 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10167 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10169 #define HEADER_IS_ZERO(match_criteria, headers) \
10170 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10171 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10174 * Calculate flow matcher enable bitmap.
10176 * @param match_criteria
10177 * Pointer to flow matcher criteria.
10180 * Bitmap of enabled fields.
10183 flow_dv_matcher_enable(uint32_t *match_criteria)
10185 uint8_t match_criteria_enable;
10187 match_criteria_enable =
10188 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10189 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10190 match_criteria_enable |=
10191 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10192 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10193 match_criteria_enable |=
10194 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10195 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10196 match_criteria_enable |=
10197 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10198 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10199 match_criteria_enable |=
10200 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10201 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10202 match_criteria_enable |=
10203 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10204 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10205 match_criteria_enable |=
10206 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10207 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10208 return match_criteria_enable;
10212 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10215 * Check flow matching criteria first, subtract misc5/4 length if flow
10216 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10217 * misc5/4 are not supported, and matcher creation failure is expected
10218 * w/o subtraction. If misc5 is provided, misc4 must be counted in since
10219 * misc5 is right after misc4.
10221 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10222 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10223 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10224 if (!(match_criteria & (1 <<
10225 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10226 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10231 static struct mlx5_list_entry *
10232 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10233 struct mlx5_list_entry *entry, void *cb_ctx)
10235 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10236 struct mlx5_flow_dv_matcher *ref = ctx->data;
10237 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10238 typeof(*tbl), tbl);
10239 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10244 rte_flow_error_set(ctx->error, ENOMEM,
10245 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10246 "cannot create matcher");
10249 memcpy(resource, entry, sizeof(*resource));
10250 resource->tbl = &tbl->tbl;
10251 return &resource->entry;
10255 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10256 struct mlx5_list_entry *entry)
10261 struct mlx5_list_entry *
10262 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10264 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10265 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10266 struct rte_eth_dev *dev = ctx->dev;
10267 struct mlx5_flow_tbl_data_entry *tbl_data;
10268 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10269 struct rte_flow_error *error = ctx->error;
10270 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10271 struct mlx5_flow_tbl_resource *tbl;
10276 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10278 rte_flow_error_set(error, ENOMEM,
10279 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10281 "cannot allocate flow table data entry");
10284 tbl_data->idx = idx;
10285 tbl_data->tunnel = tt_prm->tunnel;
10286 tbl_data->group_id = tt_prm->group_id;
10287 tbl_data->external = !!tt_prm->external;
10288 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10289 tbl_data->is_egress = !!key.is_egress;
10290 tbl_data->is_transfer = !!key.is_fdb;
10291 tbl_data->dummy = !!key.dummy;
10292 tbl_data->level = key.level;
10293 tbl_data->id = key.id;
10294 tbl = &tbl_data->tbl;
10296 return &tbl_data->entry;
10298 domain = sh->fdb_domain;
10299 else if (key.is_egress)
10300 domain = sh->tx_domain;
10302 domain = sh->rx_domain;
10303 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10305 rte_flow_error_set(error, ENOMEM,
10306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10307 NULL, "cannot create flow table object");
10308 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10311 if (key.level != 0) {
10312 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10313 (tbl->obj, &tbl_data->jump.action);
10315 rte_flow_error_set(error, ENOMEM,
10316 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10318 "cannot create flow jump action");
10319 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10320 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10324 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10325 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10326 key.level, key.id);
10327 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10328 flow_dv_matcher_create_cb,
10329 flow_dv_matcher_match_cb,
10330 flow_dv_matcher_remove_cb,
10331 flow_dv_matcher_clone_cb,
10332 flow_dv_matcher_clone_free_cb);
10333 if (!tbl_data->matchers) {
10334 rte_flow_error_set(error, ENOMEM,
10335 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10337 "cannot create tbl matcher list");
10338 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10339 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10340 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10343 return &tbl_data->entry;
10347 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10350 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10351 struct mlx5_flow_tbl_data_entry *tbl_data =
10352 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10353 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10355 return tbl_data->level != key.level ||
10356 tbl_data->id != key.id ||
10357 tbl_data->dummy != key.dummy ||
10358 tbl_data->is_transfer != !!key.is_fdb ||
10359 tbl_data->is_egress != !!key.is_egress;
10362 struct mlx5_list_entry *
10363 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10366 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10367 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10368 struct mlx5_flow_tbl_data_entry *tbl_data;
10369 struct rte_flow_error *error = ctx->error;
10372 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10374 rte_flow_error_set(error, ENOMEM,
10375 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10377 "cannot allocate flow table data entry");
10380 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10381 tbl_data->idx = idx;
10382 return &tbl_data->entry;
10386 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10388 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10389 struct mlx5_flow_tbl_data_entry *tbl_data =
10390 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10392 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10396 * Get a flow table.
10398 * @param[in, out] dev
10399 * Pointer to rte_eth_dev structure.
10400 * @param[in] table_level
10401 * Table level to use.
10402 * @param[in] egress
10403 * Direction of the table.
10404 * @param[in] transfer
10405 * E-Switch or NIC flow.
10407 * Dummy entry for dv API.
10408 * @param[in] table_id
10410 * @param[out] error
10411 * pointer to error structure.
10414 * Returns tables resource based on the index, NULL in case of failed.
10416 struct mlx5_flow_tbl_resource *
10417 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10418 uint32_t table_level, uint8_t egress,
10421 const struct mlx5_flow_tunnel *tunnel,
10422 uint32_t group_id, uint8_t dummy,
10424 struct rte_flow_error *error)
10426 struct mlx5_priv *priv = dev->data->dev_private;
10427 union mlx5_flow_tbl_key table_key = {
10429 .level = table_level,
10433 .is_fdb = !!transfer,
10434 .is_egress = !!egress,
10437 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10439 .group_id = group_id,
10440 .external = external,
10442 struct mlx5_flow_cb_ctx ctx = {
10445 .data = &table_key.v64,
10448 struct mlx5_list_entry *entry;
10449 struct mlx5_flow_tbl_data_entry *tbl_data;
10451 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10453 rte_flow_error_set(error, ENOMEM,
10454 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10455 "cannot get table");
10458 DRV_LOG(DEBUG, "table_level %u table_id %u "
10459 "tunnel %u group %u registered.",
10460 table_level, table_id,
10461 tunnel ? tunnel->tunnel_id : 0, group_id);
10462 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10463 return &tbl_data->tbl;
10467 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10469 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10470 struct mlx5_flow_tbl_data_entry *tbl_data =
10471 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10473 MLX5_ASSERT(entry && sh);
10474 if (tbl_data->jump.action)
10475 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10476 if (tbl_data->tbl.obj)
10477 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10478 if (tbl_data->tunnel_offload && tbl_data->external) {
10479 struct mlx5_list_entry *he;
10480 struct mlx5_hlist *tunnel_grp_hash;
10481 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10482 union tunnel_tbl_key tunnel_key = {
10483 .tunnel_id = tbl_data->tunnel ?
10484 tbl_data->tunnel->tunnel_id : 0,
10485 .group = tbl_data->group_id
10487 uint32_t table_level = tbl_data->level;
10488 struct mlx5_flow_cb_ctx ctx = {
10489 .data = (void *)&tunnel_key.val,
10492 tunnel_grp_hash = tbl_data->tunnel ?
10493 tbl_data->tunnel->groups :
10495 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10497 mlx5_hlist_unregister(tunnel_grp_hash, he);
10499 "table_level %u id %u tunnel %u group %u released.",
10503 tbl_data->tunnel->tunnel_id : 0,
10504 tbl_data->group_id);
10506 mlx5_list_destroy(tbl_data->matchers);
10507 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10511 * Release a flow table.
10514 * Pointer to device shared structure.
10516 * Table resource to be released.
10519 * Returns 0 if table was released, else return 1;
10522 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10523 struct mlx5_flow_tbl_resource *tbl)
10525 struct mlx5_flow_tbl_data_entry *tbl_data =
10526 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10530 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10534 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10535 struct mlx5_list_entry *entry, void *cb_ctx)
10537 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10538 struct mlx5_flow_dv_matcher *ref = ctx->data;
10539 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10542 return cur->crc != ref->crc ||
10543 cur->priority != ref->priority ||
10544 memcmp((const void *)cur->mask.buf,
10545 (const void *)ref->mask.buf, ref->mask.size);
10548 struct mlx5_list_entry *
10549 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10551 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10552 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10553 struct mlx5_flow_dv_matcher *ref = ctx->data;
10554 struct mlx5_flow_dv_matcher *resource;
10555 struct mlx5dv_flow_matcher_attr dv_attr = {
10556 .type = IBV_FLOW_ATTR_NORMAL,
10557 .match_mask = (void *)&ref->mask,
10559 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10560 typeof(*tbl), tbl);
10563 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10566 rte_flow_error_set(ctx->error, ENOMEM,
10567 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10568 "cannot create matcher");
10572 dv_attr.match_criteria_enable =
10573 flow_dv_matcher_enable(resource->mask.buf);
10574 __flow_dv_adjust_buf_size(&ref->mask.size,
10575 dv_attr.match_criteria_enable);
10576 dv_attr.priority = ref->priority;
10577 if (tbl->is_egress)
10578 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10579 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10581 &resource->matcher_object);
10583 mlx5_free(resource);
10584 rte_flow_error_set(ctx->error, ENOMEM,
10585 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10586 "cannot create matcher");
10589 return &resource->entry;
10593 * Register the flow matcher.
10595 * @param[in, out] dev
10596 * Pointer to rte_eth_dev structure.
10597 * @param[in, out] matcher
10598 * Pointer to flow matcher.
10599 * @param[in, out] key
10600 * Pointer to flow table key.
10601 * @parm[in, out] dev_flow
10602 * Pointer to the dev_flow.
10603 * @param[out] error
10604 * pointer to error structure.
10607 * 0 on success otherwise -errno and errno is set.
10610 flow_dv_matcher_register(struct rte_eth_dev *dev,
10611 struct mlx5_flow_dv_matcher *ref,
10612 union mlx5_flow_tbl_key *key,
10613 struct mlx5_flow *dev_flow,
10614 const struct mlx5_flow_tunnel *tunnel,
10616 struct rte_flow_error *error)
10618 struct mlx5_list_entry *entry;
10619 struct mlx5_flow_dv_matcher *resource;
10620 struct mlx5_flow_tbl_resource *tbl;
10621 struct mlx5_flow_tbl_data_entry *tbl_data;
10622 struct mlx5_flow_cb_ctx ctx = {
10627 * tunnel offload API requires this registration for cases when
10628 * tunnel match rule was inserted before tunnel set rule.
10630 tbl = flow_dv_tbl_resource_get(dev, key->level,
10631 key->is_egress, key->is_fdb,
10632 dev_flow->external, tunnel,
10633 group_id, 0, key->id, error);
10635 return -rte_errno; /* No need to refill the error info */
10636 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10638 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10640 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10641 return rte_flow_error_set(error, ENOMEM,
10642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10643 "cannot allocate ref memory");
10645 resource = container_of(entry, typeof(*resource), entry);
10646 dev_flow->handle->dvh.matcher = resource;
10650 struct mlx5_list_entry *
10651 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10653 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10654 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10655 struct mlx5_flow_dv_tag_resource *entry;
10659 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10661 rte_flow_error_set(ctx->error, ENOMEM,
10662 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10663 "cannot allocate resource memory");
10667 entry->tag_id = *(uint32_t *)(ctx->data);
10668 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10671 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10672 rte_flow_error_set(ctx->error, ENOMEM,
10673 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10674 NULL, "cannot create action");
10677 return &entry->entry;
10681 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10684 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10685 struct mlx5_flow_dv_tag_resource *tag =
10686 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10688 return *(uint32_t *)(ctx->data) != tag->tag_id;
10691 struct mlx5_list_entry *
10692 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10695 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10696 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10697 struct mlx5_flow_dv_tag_resource *entry;
10700 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10702 rte_flow_error_set(ctx->error, ENOMEM,
10703 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10704 "cannot allocate tag resource memory");
10707 memcpy(entry, oentry, sizeof(*entry));
10709 return &entry->entry;
10713 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10715 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10716 struct mlx5_flow_dv_tag_resource *tag =
10717 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10719 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10723 * Find existing tag resource or create and register a new one.
10725 * @param dev[in, out]
10726 * Pointer to rte_eth_dev structure.
10727 * @param[in, out] tag_be24
10728 * Tag value in big endian then R-shift 8.
10729 * @parm[in, out] dev_flow
10730 * Pointer to the dev_flow.
10731 * @param[out] error
10732 * pointer to error structure.
10735 * 0 on success otherwise -errno and errno is set.
10738 flow_dv_tag_resource_register
10739 (struct rte_eth_dev *dev,
10741 struct mlx5_flow *dev_flow,
10742 struct rte_flow_error *error)
10744 struct mlx5_priv *priv = dev->data->dev_private;
10745 struct mlx5_flow_dv_tag_resource *resource;
10746 struct mlx5_list_entry *entry;
10747 struct mlx5_flow_cb_ctx ctx = {
10751 struct mlx5_hlist *tag_table;
10753 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10755 MLX5_TAGS_HLIST_ARRAY_SIZE,
10756 false, false, priv->sh,
10757 flow_dv_tag_create_cb,
10758 flow_dv_tag_match_cb,
10759 flow_dv_tag_remove_cb,
10760 flow_dv_tag_clone_cb,
10761 flow_dv_tag_clone_free_cb);
10762 if (unlikely(!tag_table))
10764 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10766 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10768 dev_flow->handle->dvh.rix_tag = resource->idx;
10769 dev_flow->dv.tag_resource = resource;
10776 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10778 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10779 struct mlx5_flow_dv_tag_resource *tag =
10780 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10782 MLX5_ASSERT(tag && sh && tag->action);
10783 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10784 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10785 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10792 * Pointer to Ethernet device.
10797 * 1 while a reference on it exists, 0 when freed.
10800 flow_dv_tag_release(struct rte_eth_dev *dev,
10803 struct mlx5_priv *priv = dev->data->dev_private;
10804 struct mlx5_flow_dv_tag_resource *tag;
10806 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10809 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10810 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10811 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10815 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10818 * Pointer to rte_eth_dev structure.
10819 * @param[in] action
10820 * Pointer to action PORT_ID / REPRESENTED_PORT.
10821 * @param[out] dst_port_id
10822 * The target port ID.
10823 * @param[out] error
10824 * Pointer to the error structure.
10827 * 0 on success, a negative errno value otherwise and rte_errno is set.
10830 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10831 const struct rte_flow_action *action,
10832 uint32_t *dst_port_id,
10833 struct rte_flow_error *error)
10836 struct mlx5_priv *priv;
10838 switch (action->type) {
10839 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10840 const struct rte_flow_action_port_id *conf;
10842 conf = (const struct rte_flow_action_port_id *)action->conf;
10843 port = conf->original ? dev->data->port_id : conf->id;
10846 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10847 const struct rte_flow_action_ethdev *ethdev;
10849 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10850 port = ethdev->port_id;
10854 MLX5_ASSERT(false);
10855 return rte_flow_error_set(error, EINVAL,
10856 RTE_FLOW_ERROR_TYPE_ACTION, action,
10857 "unknown E-Switch action");
10860 priv = mlx5_port_to_eswitch_info(port, false);
10862 return rte_flow_error_set(error, -rte_errno,
10863 RTE_FLOW_ERROR_TYPE_ACTION,
10865 "No eswitch info was found for port");
10866 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10868 * This parameter is transferred to
10869 * mlx5dv_dr_action_create_dest_ib_port().
10871 *dst_port_id = priv->dev_port;
10874 * Legacy mode, no LAG configurations is supported.
10875 * This parameter is transferred to
10876 * mlx5dv_dr_action_create_dest_vport().
10878 *dst_port_id = priv->vport_id;
10884 * Create a counter with aging configuration.
10887 * Pointer to rte_eth_dev structure.
10888 * @param[in] dev_flow
10889 * Pointer to the mlx5_flow.
10890 * @param[out] count
10891 * Pointer to the counter action configuration.
10893 * Pointer to the aging action configuration.
10896 * Index to flow counter on success, 0 otherwise.
10899 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10900 struct mlx5_flow *dev_flow,
10901 const struct rte_flow_action_count *count
10903 const struct rte_flow_action_age *age)
10906 struct mlx5_age_param *age_param;
10908 counter = flow_dv_counter_alloc(dev, !!age);
10909 if (!counter || age == NULL)
10911 age_param = flow_dv_counter_idx_get_age(dev, counter);
10912 age_param->context = age->context ? age->context :
10913 (void *)(uintptr_t)(dev_flow->flow_idx);
10914 age_param->timeout = age->timeout;
10915 age_param->port_id = dev->data->port_id;
10916 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10917 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10922 * Add Tx queue matcher
10925 * Pointer to the dev struct.
10926 * @param[in, out] matcher
10928 * @param[in, out] key
10929 * Flow matcher value.
10931 * Flow pattern to translate.
10933 * Item is inner pattern.
10936 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10937 void *matcher, void *key,
10938 const struct rte_flow_item *item)
10940 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10941 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10943 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10945 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10946 struct mlx5_txq_ctrl *txq;
10947 uint32_t queue, mask;
10949 queue_m = (const void *)item->mask;
10950 queue_v = (const void *)item->spec;
10953 txq = mlx5_txq_get(dev, queue_v->queue);
10956 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10957 queue = txq->obj->sq->id;
10959 queue = txq->obj->sq_obj.sq->id;
10960 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10961 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10962 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10963 mlx5_txq_release(dev, queue_v->queue);
10967 * Set the hash fields according to the @p flow information.
10969 * @param[in] dev_flow
10970 * Pointer to the mlx5_flow.
10971 * @param[in] rss_desc
10972 * Pointer to the mlx5_flow_rss_desc.
10975 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10976 struct mlx5_flow_rss_desc *rss_desc)
10978 uint64_t items = dev_flow->handle->layers;
10980 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10982 dev_flow->hash_fields = 0;
10983 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10984 if (rss_desc->level >= 2)
10987 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10988 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10989 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10990 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
10991 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10992 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
10993 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10995 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10997 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10998 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10999 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11000 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11001 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
11002 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11003 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
11005 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
11008 if (dev_flow->hash_fields == 0)
11010 * There is no match between the RSS types and the
11011 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11014 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11015 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
11016 if (rss_types & RTE_ETH_RSS_UDP) {
11017 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11018 dev_flow->hash_fields |=
11019 IBV_RX_HASH_SRC_PORT_UDP;
11020 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11021 dev_flow->hash_fields |=
11022 IBV_RX_HASH_DST_PORT_UDP;
11024 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
11026 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11027 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
11028 if (rss_types & RTE_ETH_RSS_TCP) {
11029 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11030 dev_flow->hash_fields |=
11031 IBV_RX_HASH_SRC_PORT_TCP;
11032 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11033 dev_flow->hash_fields |=
11034 IBV_RX_HASH_DST_PORT_TCP;
11036 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11040 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11044 * Prepare an Rx Hash queue.
11047 * Pointer to Ethernet device.
11048 * @param[in] dev_flow
11049 * Pointer to the mlx5_flow.
11050 * @param[in] rss_desc
11051 * Pointer to the mlx5_flow_rss_desc.
11052 * @param[out] hrxq_idx
11053 * Hash Rx queue index.
11056 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11058 static struct mlx5_hrxq *
11059 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11060 struct mlx5_flow *dev_flow,
11061 struct mlx5_flow_rss_desc *rss_desc,
11062 uint32_t *hrxq_idx)
11064 struct mlx5_priv *priv = dev->data->dev_private;
11065 struct mlx5_flow_handle *dh = dev_flow->handle;
11066 struct mlx5_hrxq *hrxq;
11068 MLX5_ASSERT(rss_desc->queue_num);
11069 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11070 rss_desc->hash_fields = dev_flow->hash_fields;
11071 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11072 rss_desc->shared_rss = 0;
11073 if (rss_desc->hash_fields == 0)
11074 rss_desc->queue_num = 1;
11075 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11078 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11084 * Release sample sub action resource.
11086 * @param[in, out] dev
11087 * Pointer to rte_eth_dev structure.
11088 * @param[in] act_res
11089 * Pointer to sample sub action resource.
11092 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11093 struct mlx5_flow_sub_actions_idx *act_res)
11095 if (act_res->rix_hrxq) {
11096 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11097 act_res->rix_hrxq = 0;
11099 if (act_res->rix_encap_decap) {
11100 flow_dv_encap_decap_resource_release(dev,
11101 act_res->rix_encap_decap);
11102 act_res->rix_encap_decap = 0;
11104 if (act_res->rix_port_id_action) {
11105 flow_dv_port_id_action_resource_release(dev,
11106 act_res->rix_port_id_action);
11107 act_res->rix_port_id_action = 0;
11109 if (act_res->rix_tag) {
11110 flow_dv_tag_release(dev, act_res->rix_tag);
11111 act_res->rix_tag = 0;
11113 if (act_res->rix_jump) {
11114 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11115 act_res->rix_jump = 0;
11120 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11121 struct mlx5_list_entry *entry, void *cb_ctx)
11123 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11124 struct rte_eth_dev *dev = ctx->dev;
11125 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11126 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11130 if (ctx_resource->ratio == resource->ratio &&
11131 ctx_resource->ft_type == resource->ft_type &&
11132 ctx_resource->ft_id == resource->ft_id &&
11133 ctx_resource->set_action == resource->set_action &&
11134 !memcmp((void *)&ctx_resource->sample_act,
11135 (void *)&resource->sample_act,
11136 sizeof(struct mlx5_flow_sub_actions_list))) {
11138 * Existing sample action should release the prepared
11139 * sub-actions reference counter.
11141 flow_dv_sample_sub_actions_release(dev,
11142 &ctx_resource->sample_idx);
11148 struct mlx5_list_entry *
11149 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11151 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11152 struct rte_eth_dev *dev = ctx->dev;
11153 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11154 void **sample_dv_actions = ctx_resource->sub_actions;
11155 struct mlx5_flow_dv_sample_resource *resource;
11156 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11157 struct mlx5_priv *priv = dev->data->dev_private;
11158 struct mlx5_dev_ctx_shared *sh = priv->sh;
11159 struct mlx5_flow_tbl_resource *tbl;
11161 const uint32_t next_ft_step = 1;
11162 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11163 uint8_t is_egress = 0;
11164 uint8_t is_transfer = 0;
11165 struct rte_flow_error *error = ctx->error;
11167 /* Register new sample resource. */
11168 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11170 rte_flow_error_set(error, ENOMEM,
11171 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11173 "cannot allocate resource memory");
11176 *resource = *ctx_resource;
11177 /* Create normal path table level */
11178 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11180 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11182 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11183 is_egress, is_transfer,
11184 true, NULL, 0, 0, 0, error);
11186 rte_flow_error_set(error, ENOMEM,
11187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11189 "fail to create normal path table "
11193 resource->normal_path_tbl = tbl;
11194 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11195 if (!sh->default_miss_action) {
11196 rte_flow_error_set(error, ENOMEM,
11197 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11199 "default miss action was not "
11203 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11204 sh->default_miss_action;
11206 /* Create a DR sample action */
11207 sampler_attr.sample_ratio = resource->ratio;
11208 sampler_attr.default_next_table = tbl->obj;
11209 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11210 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11211 &sample_dv_actions[0];
11212 sampler_attr.action = resource->set_action;
11213 if (mlx5_os_flow_dr_create_flow_action_sampler
11214 (&sampler_attr, &resource->verbs_action)) {
11215 rte_flow_error_set(error, ENOMEM,
11216 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11217 NULL, "cannot create sample action");
11220 resource->idx = idx;
11221 resource->dev = dev;
11222 return &resource->entry;
11224 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11225 flow_dv_sample_sub_actions_release(dev,
11226 &resource->sample_idx);
11227 if (resource->normal_path_tbl)
11228 flow_dv_tbl_resource_release(MLX5_SH(dev),
11229 resource->normal_path_tbl);
11230 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11235 struct mlx5_list_entry *
11236 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11237 struct mlx5_list_entry *entry __rte_unused,
11240 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11241 struct rte_eth_dev *dev = ctx->dev;
11242 struct mlx5_flow_dv_sample_resource *resource;
11243 struct mlx5_priv *priv = dev->data->dev_private;
11244 struct mlx5_dev_ctx_shared *sh = priv->sh;
11247 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11249 rte_flow_error_set(ctx->error, ENOMEM,
11250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11252 "cannot allocate resource memory");
11255 memcpy(resource, entry, sizeof(*resource));
11256 resource->idx = idx;
11257 resource->dev = dev;
11258 return &resource->entry;
11262 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11263 struct mlx5_list_entry *entry)
11265 struct mlx5_flow_dv_sample_resource *resource =
11266 container_of(entry, typeof(*resource), entry);
11267 struct rte_eth_dev *dev = resource->dev;
11268 struct mlx5_priv *priv = dev->data->dev_private;
11270 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11274 * Find existing sample resource or create and register a new one.
11276 * @param[in, out] dev
11277 * Pointer to rte_eth_dev structure.
11279 * Pointer to sample resource reference.
11280 * @parm[in, out] dev_flow
11281 * Pointer to the dev_flow.
11282 * @param[out] error
11283 * pointer to error structure.
11286 * 0 on success otherwise -errno and errno is set.
11289 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11290 struct mlx5_flow_dv_sample_resource *ref,
11291 struct mlx5_flow *dev_flow,
11292 struct rte_flow_error *error)
11294 struct mlx5_flow_dv_sample_resource *resource;
11295 struct mlx5_list_entry *entry;
11296 struct mlx5_priv *priv = dev->data->dev_private;
11297 struct mlx5_flow_cb_ctx ctx = {
11303 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11306 resource = container_of(entry, typeof(*resource), entry);
11307 dev_flow->handle->dvh.rix_sample = resource->idx;
11308 dev_flow->dv.sample_res = resource;
11313 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11314 struct mlx5_list_entry *entry, void *cb_ctx)
11316 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11317 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11318 struct rte_eth_dev *dev = ctx->dev;
11319 struct mlx5_flow_dv_dest_array_resource *resource =
11320 container_of(entry, typeof(*resource), entry);
11323 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11324 ctx_resource->ft_type == resource->ft_type &&
11325 !memcmp((void *)resource->sample_act,
11326 (void *)ctx_resource->sample_act,
11327 (ctx_resource->num_of_dest *
11328 sizeof(struct mlx5_flow_sub_actions_list)))) {
11330 * Existing sample action should release the prepared
11331 * sub-actions reference counter.
11333 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11334 flow_dv_sample_sub_actions_release(dev,
11335 &ctx_resource->sample_idx[idx]);
11341 struct mlx5_list_entry *
11342 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11344 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11345 struct rte_eth_dev *dev = ctx->dev;
11346 struct mlx5_flow_dv_dest_array_resource *resource;
11347 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11348 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11349 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11350 struct mlx5_priv *priv = dev->data->dev_private;
11351 struct mlx5_dev_ctx_shared *sh = priv->sh;
11352 struct mlx5_flow_sub_actions_list *sample_act;
11353 struct mlx5dv_dr_domain *domain;
11354 uint32_t idx = 0, res_idx = 0;
11355 struct rte_flow_error *error = ctx->error;
11356 uint64_t action_flags;
11359 /* Register new destination array resource. */
11360 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11363 rte_flow_error_set(error, ENOMEM,
11364 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11366 "cannot allocate resource memory");
11369 *resource = *ctx_resource;
11370 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11371 domain = sh->fdb_domain;
11372 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11373 domain = sh->rx_domain;
11375 domain = sh->tx_domain;
11376 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11377 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11378 mlx5_malloc(MLX5_MEM_ZERO,
11379 sizeof(struct mlx5dv_dr_action_dest_attr),
11381 if (!dest_attr[idx]) {
11382 rte_flow_error_set(error, ENOMEM,
11383 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11385 "cannot allocate resource memory");
11388 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11389 sample_act = &ctx_resource->sample_act[idx];
11390 action_flags = sample_act->action_flags;
11391 switch (action_flags) {
11392 case MLX5_FLOW_ACTION_QUEUE:
11393 dest_attr[idx]->dest = sample_act->dr_queue_action;
11395 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11396 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11397 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11398 dest_attr[idx]->dest_reformat->reformat =
11399 sample_act->dr_encap_action;
11400 dest_attr[idx]->dest_reformat->dest =
11401 sample_act->dr_port_id_action;
11403 case MLX5_FLOW_ACTION_PORT_ID:
11404 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11406 case MLX5_FLOW_ACTION_JUMP:
11407 dest_attr[idx]->dest = sample_act->dr_jump_action;
11410 rte_flow_error_set(error, EINVAL,
11411 RTE_FLOW_ERROR_TYPE_ACTION,
11413 "unsupported actions type");
11417 /* create a dest array action */
11418 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11420 resource->num_of_dest,
11422 &resource->action);
11424 rte_flow_error_set(error, ENOMEM,
11425 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11427 "cannot create destination array action");
11430 resource->idx = res_idx;
11431 resource->dev = dev;
11432 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11433 mlx5_free(dest_attr[idx]);
11434 return &resource->entry;
11436 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11437 flow_dv_sample_sub_actions_release(dev,
11438 &resource->sample_idx[idx]);
11439 if (dest_attr[idx])
11440 mlx5_free(dest_attr[idx]);
11442 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11446 struct mlx5_list_entry *
11447 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11448 struct mlx5_list_entry *entry __rte_unused,
11451 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11452 struct rte_eth_dev *dev = ctx->dev;
11453 struct mlx5_flow_dv_dest_array_resource *resource;
11454 struct mlx5_priv *priv = dev->data->dev_private;
11455 struct mlx5_dev_ctx_shared *sh = priv->sh;
11456 uint32_t res_idx = 0;
11457 struct rte_flow_error *error = ctx->error;
11459 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11462 rte_flow_error_set(error, ENOMEM,
11463 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11465 "cannot allocate dest-array memory");
11468 memcpy(resource, entry, sizeof(*resource));
11469 resource->idx = res_idx;
11470 resource->dev = dev;
11471 return &resource->entry;
11475 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11476 struct mlx5_list_entry *entry)
11478 struct mlx5_flow_dv_dest_array_resource *resource =
11479 container_of(entry, typeof(*resource), entry);
11480 struct rte_eth_dev *dev = resource->dev;
11481 struct mlx5_priv *priv = dev->data->dev_private;
11483 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11487 * Find existing destination array resource or create and register a new one.
11489 * @param[in, out] dev
11490 * Pointer to rte_eth_dev structure.
11492 * Pointer to destination array resource reference.
11493 * @parm[in, out] dev_flow
11494 * Pointer to the dev_flow.
11495 * @param[out] error
11496 * pointer to error structure.
11499 * 0 on success otherwise -errno and errno is set.
11502 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11503 struct mlx5_flow_dv_dest_array_resource *ref,
11504 struct mlx5_flow *dev_flow,
11505 struct rte_flow_error *error)
11507 struct mlx5_flow_dv_dest_array_resource *resource;
11508 struct mlx5_priv *priv = dev->data->dev_private;
11509 struct mlx5_list_entry *entry;
11510 struct mlx5_flow_cb_ctx ctx = {
11516 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11519 resource = container_of(entry, typeof(*resource), entry);
11520 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11521 dev_flow->dv.dest_array_res = resource;
11526 * Convert Sample action to DV specification.
11529 * Pointer to rte_eth_dev structure.
11530 * @param[in] action
11531 * Pointer to sample action structure.
11532 * @param[in, out] dev_flow
11533 * Pointer to the mlx5_flow.
11535 * Pointer to the flow attributes.
11536 * @param[in, out] num_of_dest
11537 * Pointer to the num of destination.
11538 * @param[in, out] sample_actions
11539 * Pointer to sample actions list.
11540 * @param[in, out] res
11541 * Pointer to sample resource.
11542 * @param[out] error
11543 * Pointer to the error structure.
11546 * 0 on success, a negative errno value otherwise and rte_errno is set.
11549 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11550 const struct rte_flow_action_sample *action,
11551 struct mlx5_flow *dev_flow,
11552 const struct rte_flow_attr *attr,
11553 uint32_t *num_of_dest,
11554 void **sample_actions,
11555 struct mlx5_flow_dv_sample_resource *res,
11556 struct rte_flow_error *error)
11558 struct mlx5_priv *priv = dev->data->dev_private;
11559 const struct rte_flow_action *sub_actions;
11560 struct mlx5_flow_sub_actions_list *sample_act;
11561 struct mlx5_flow_sub_actions_idx *sample_idx;
11562 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11563 struct rte_flow *flow = dev_flow->flow;
11564 struct mlx5_flow_rss_desc *rss_desc;
11565 uint64_t action_flags = 0;
11568 rss_desc = &wks->rss_desc;
11569 sample_act = &res->sample_act;
11570 sample_idx = &res->sample_idx;
11571 res->ratio = action->ratio;
11572 sub_actions = action->actions;
11573 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11574 int type = sub_actions->type;
11575 uint32_t pre_rix = 0;
11578 case RTE_FLOW_ACTION_TYPE_QUEUE:
11580 const struct rte_flow_action_queue *queue;
11581 struct mlx5_hrxq *hrxq;
11584 queue = sub_actions->conf;
11585 rss_desc->queue_num = 1;
11586 rss_desc->queue[0] = queue->index;
11587 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11588 rss_desc, &hrxq_idx);
11590 return rte_flow_error_set
11592 RTE_FLOW_ERROR_TYPE_ACTION,
11594 "cannot create fate queue");
11595 sample_act->dr_queue_action = hrxq->action;
11596 sample_idx->rix_hrxq = hrxq_idx;
11597 sample_actions[sample_act->actions_num++] =
11600 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11601 if (action_flags & MLX5_FLOW_ACTION_MARK)
11602 dev_flow->handle->rix_hrxq = hrxq_idx;
11603 dev_flow->handle->fate_action =
11604 MLX5_FLOW_FATE_QUEUE;
11607 case RTE_FLOW_ACTION_TYPE_RSS:
11609 struct mlx5_hrxq *hrxq;
11611 const struct rte_flow_action_rss *rss;
11612 const uint8_t *rss_key;
11614 rss = sub_actions->conf;
11615 memcpy(rss_desc->queue, rss->queue,
11616 rss->queue_num * sizeof(uint16_t));
11617 rss_desc->queue_num = rss->queue_num;
11618 /* NULL RSS key indicates default RSS key. */
11619 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11620 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11622 * rss->level and rss.types should be set in advance
11623 * when expanding items for RSS.
11625 flow_dv_hashfields_set(dev_flow, rss_desc);
11626 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11627 rss_desc, &hrxq_idx);
11629 return rte_flow_error_set
11631 RTE_FLOW_ERROR_TYPE_ACTION,
11633 "cannot create fate queue");
11634 sample_act->dr_queue_action = hrxq->action;
11635 sample_idx->rix_hrxq = hrxq_idx;
11636 sample_actions[sample_act->actions_num++] =
11639 action_flags |= MLX5_FLOW_ACTION_RSS;
11640 if (action_flags & MLX5_FLOW_ACTION_MARK)
11641 dev_flow->handle->rix_hrxq = hrxq_idx;
11642 dev_flow->handle->fate_action =
11643 MLX5_FLOW_FATE_QUEUE;
11646 case RTE_FLOW_ACTION_TYPE_MARK:
11648 uint32_t tag_be = mlx5_flow_mark_set
11649 (((const struct rte_flow_action_mark *)
11650 (sub_actions->conf))->id);
11653 pre_rix = dev_flow->handle->dvh.rix_tag;
11654 /* Save the mark resource before sample */
11655 pre_r = dev_flow->dv.tag_resource;
11656 if (flow_dv_tag_resource_register(dev, tag_be,
11659 MLX5_ASSERT(dev_flow->dv.tag_resource);
11660 sample_act->dr_tag_action =
11661 dev_flow->dv.tag_resource->action;
11662 sample_idx->rix_tag =
11663 dev_flow->handle->dvh.rix_tag;
11664 sample_actions[sample_act->actions_num++] =
11665 sample_act->dr_tag_action;
11666 /* Recover the mark resource after sample */
11667 dev_flow->dv.tag_resource = pre_r;
11668 dev_flow->handle->dvh.rix_tag = pre_rix;
11669 action_flags |= MLX5_FLOW_ACTION_MARK;
11672 case RTE_FLOW_ACTION_TYPE_COUNT:
11674 if (!flow->counter) {
11676 flow_dv_translate_create_counter(dev,
11677 dev_flow, sub_actions->conf,
11679 if (!flow->counter)
11680 return rte_flow_error_set
11682 RTE_FLOW_ERROR_TYPE_ACTION,
11684 "cannot create counter"
11687 sample_act->dr_cnt_action =
11688 (flow_dv_counter_get_by_idx(dev,
11689 flow->counter, NULL))->action;
11690 sample_actions[sample_act->actions_num++] =
11691 sample_act->dr_cnt_action;
11692 action_flags |= MLX5_FLOW_ACTION_COUNT;
11695 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11696 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11698 struct mlx5_flow_dv_port_id_action_resource
11700 uint32_t port_id = 0;
11702 memset(&port_id_resource, 0, sizeof(port_id_resource));
11703 /* Save the port id resource before sample */
11704 pre_rix = dev_flow->handle->rix_port_id_action;
11705 pre_r = dev_flow->dv.port_id_action;
11706 if (flow_dv_translate_action_port_id(dev, sub_actions,
11709 port_id_resource.port_id = port_id;
11710 if (flow_dv_port_id_action_resource_register
11711 (dev, &port_id_resource, dev_flow, error))
11713 sample_act->dr_port_id_action =
11714 dev_flow->dv.port_id_action->action;
11715 sample_idx->rix_port_id_action =
11716 dev_flow->handle->rix_port_id_action;
11717 sample_actions[sample_act->actions_num++] =
11718 sample_act->dr_port_id_action;
11719 /* Recover the port id resource after sample */
11720 dev_flow->dv.port_id_action = pre_r;
11721 dev_flow->handle->rix_port_id_action = pre_rix;
11723 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11726 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11727 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11728 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11729 /* Save the encap resource before sample */
11730 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11731 pre_r = dev_flow->dv.encap_decap;
11732 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11737 sample_act->dr_encap_action =
11738 dev_flow->dv.encap_decap->action;
11739 sample_idx->rix_encap_decap =
11740 dev_flow->handle->dvh.rix_encap_decap;
11741 sample_actions[sample_act->actions_num++] =
11742 sample_act->dr_encap_action;
11743 /* Recover the encap resource after sample */
11744 dev_flow->dv.encap_decap = pre_r;
11745 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11746 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11749 return rte_flow_error_set(error, EINVAL,
11750 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11752 "Not support for sampler action");
11755 sample_act->action_flags = action_flags;
11756 res->ft_id = dev_flow->dv.group;
11757 if (attr->transfer) {
11759 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11760 uint64_t set_action;
11761 } action_ctx = { .set_action = 0 };
11763 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11764 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11765 MLX5_MODIFICATION_TYPE_SET);
11766 MLX5_SET(set_action_in, action_ctx.action_in, field,
11767 MLX5_MODI_META_REG_C_0);
11768 MLX5_SET(set_action_in, action_ctx.action_in, data,
11769 priv->vport_meta_tag);
11770 res->set_action = action_ctx.set_action;
11771 } else if (attr->ingress) {
11772 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11774 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11780 * Convert Sample action to DV specification.
11783 * Pointer to rte_eth_dev structure.
11784 * @param[in, out] dev_flow
11785 * Pointer to the mlx5_flow.
11786 * @param[in] num_of_dest
11787 * The num of destination.
11788 * @param[in, out] res
11789 * Pointer to sample resource.
11790 * @param[in, out] mdest_res
11791 * Pointer to destination array resource.
11792 * @param[in] sample_actions
11793 * Pointer to sample path actions list.
11794 * @param[in] action_flags
11795 * Holds the actions detected until now.
11796 * @param[out] error
11797 * Pointer to the error structure.
11800 * 0 on success, a negative errno value otherwise and rte_errno is set.
11803 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11804 struct mlx5_flow *dev_flow,
11805 uint32_t num_of_dest,
11806 struct mlx5_flow_dv_sample_resource *res,
11807 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11808 void **sample_actions,
11809 uint64_t action_flags,
11810 struct rte_flow_error *error)
11812 /* update normal path action resource into last index of array */
11813 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11814 struct mlx5_flow_sub_actions_list *sample_act =
11815 &mdest_res->sample_act[dest_index];
11816 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11817 struct mlx5_flow_rss_desc *rss_desc;
11818 uint32_t normal_idx = 0;
11819 struct mlx5_hrxq *hrxq;
11823 rss_desc = &wks->rss_desc;
11824 if (num_of_dest > 1) {
11825 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11826 /* Handle QP action for mirroring */
11827 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11828 rss_desc, &hrxq_idx);
11830 return rte_flow_error_set
11832 RTE_FLOW_ERROR_TYPE_ACTION,
11834 "cannot create rx queue");
11836 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11837 sample_act->dr_queue_action = hrxq->action;
11838 if (action_flags & MLX5_FLOW_ACTION_MARK)
11839 dev_flow->handle->rix_hrxq = hrxq_idx;
11840 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11842 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11844 mdest_res->sample_idx[dest_index].rix_encap_decap =
11845 dev_flow->handle->dvh.rix_encap_decap;
11846 sample_act->dr_encap_action =
11847 dev_flow->dv.encap_decap->action;
11848 dev_flow->handle->dvh.rix_encap_decap = 0;
11850 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11852 mdest_res->sample_idx[dest_index].rix_port_id_action =
11853 dev_flow->handle->rix_port_id_action;
11854 sample_act->dr_port_id_action =
11855 dev_flow->dv.port_id_action->action;
11856 dev_flow->handle->rix_port_id_action = 0;
11858 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11860 mdest_res->sample_idx[dest_index].rix_jump =
11861 dev_flow->handle->rix_jump;
11862 sample_act->dr_jump_action =
11863 dev_flow->dv.jump->action;
11864 dev_flow->handle->rix_jump = 0;
11866 sample_act->actions_num = normal_idx;
11867 /* update sample action resource into first index of array */
11868 mdest_res->ft_type = res->ft_type;
11869 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11870 sizeof(struct mlx5_flow_sub_actions_idx));
11871 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11872 sizeof(struct mlx5_flow_sub_actions_list));
11873 mdest_res->num_of_dest = num_of_dest;
11874 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11876 return rte_flow_error_set(error, EINVAL,
11877 RTE_FLOW_ERROR_TYPE_ACTION,
11878 NULL, "can't create sample "
11881 res->sub_actions = sample_actions;
11882 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11883 return rte_flow_error_set(error, EINVAL,
11884 RTE_FLOW_ERROR_TYPE_ACTION,
11886 "can't create sample action");
11892 * Remove an ASO age action from age actions list.
11895 * Pointer to the Ethernet device structure.
11897 * Pointer to the aso age action handler.
11900 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11901 struct mlx5_aso_age_action *age)
11903 struct mlx5_age_info *age_info;
11904 struct mlx5_age_param *age_param = &age->age_params;
11905 struct mlx5_priv *priv = dev->data->dev_private;
11906 uint16_t expected = AGE_CANDIDATE;
11908 age_info = GET_PORT_AGE_INFO(priv);
11909 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11910 AGE_FREE, false, __ATOMIC_RELAXED,
11911 __ATOMIC_RELAXED)) {
11913 * We need the lock even it is age timeout,
11914 * since age action may still in process.
11916 rte_spinlock_lock(&age_info->aged_sl);
11917 LIST_REMOVE(age, next);
11918 rte_spinlock_unlock(&age_info->aged_sl);
11919 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11924 * Release an ASO age action.
11927 * Pointer to the Ethernet device structure.
11928 * @param[in] age_idx
11929 * Index of ASO age action to release.
11931 * True if the release operation is during flow destroy operation.
11932 * False if the release operation is during action destroy operation.
11935 * 0 when age action was removed, otherwise the number of references.
11938 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11940 struct mlx5_priv *priv = dev->data->dev_private;
11941 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11942 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11943 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11946 flow_dv_aso_age_remove_from_age(dev, age);
11947 rte_spinlock_lock(&mng->free_sl);
11948 LIST_INSERT_HEAD(&mng->free, age, next);
11949 rte_spinlock_unlock(&mng->free_sl);
11955 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11958 * Pointer to the Ethernet device structure.
11961 * 0 on success, otherwise negative errno value and rte_errno is set.
11964 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11966 struct mlx5_priv *priv = dev->data->dev_private;
11967 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11968 void *old_pools = mng->pools;
11969 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11970 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11971 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11974 rte_errno = ENOMEM;
11978 memcpy(pools, old_pools,
11979 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11980 mlx5_free(old_pools);
11982 /* First ASO flow hit allocation - starting ASO data-path. */
11983 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11991 mng->pools = pools;
11996 * Create and initialize a new ASO aging pool.
11999 * Pointer to the Ethernet device structure.
12000 * @param[out] age_free
12001 * Where to put the pointer of a new age action.
12004 * The age actions pool pointer and @p age_free is set on success,
12005 * NULL otherwise and rte_errno is set.
12007 static struct mlx5_aso_age_pool *
12008 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12009 struct mlx5_aso_age_action **age_free)
12011 struct mlx5_priv *priv = dev->data->dev_private;
12012 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12013 struct mlx5_aso_age_pool *pool = NULL;
12014 struct mlx5_devx_obj *obj = NULL;
12017 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12018 priv->sh->cdev->pdn);
12020 rte_errno = ENODATA;
12021 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12024 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12026 claim_zero(mlx5_devx_cmd_destroy(obj));
12027 rte_errno = ENOMEM;
12030 pool->flow_hit_aso_obj = obj;
12031 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12032 rte_rwlock_write_lock(&mng->resize_rwl);
12033 pool->index = mng->next;
12034 /* Resize pools array if there is no room for the new pool in it. */
12035 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12036 claim_zero(mlx5_devx_cmd_destroy(obj));
12038 rte_rwlock_write_unlock(&mng->resize_rwl);
12041 mng->pools[pool->index] = pool;
12043 rte_rwlock_write_unlock(&mng->resize_rwl);
12044 /* Assign the first action in the new pool, the rest go to free list. */
12045 *age_free = &pool->actions[0];
12046 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12047 pool->actions[i].offset = i;
12048 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12054 * Allocate a ASO aging bit.
12057 * Pointer to the Ethernet device structure.
12058 * @param[out] error
12059 * Pointer to the error structure.
12062 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12065 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12067 struct mlx5_priv *priv = dev->data->dev_private;
12068 const struct mlx5_aso_age_pool *pool;
12069 struct mlx5_aso_age_action *age_free = NULL;
12070 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12073 /* Try to get the next free age action bit. */
12074 rte_spinlock_lock(&mng->free_sl);
12075 age_free = LIST_FIRST(&mng->free);
12077 LIST_REMOVE(age_free, next);
12078 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12079 rte_spinlock_unlock(&mng->free_sl);
12080 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12081 NULL, "failed to create ASO age pool");
12082 return 0; /* 0 is an error. */
12084 rte_spinlock_unlock(&mng->free_sl);
12085 pool = container_of
12086 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12087 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12089 if (!age_free->dr_action) {
12090 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12094 rte_flow_error_set(error, rte_errno,
12095 RTE_FLOW_ERROR_TYPE_ACTION,
12096 NULL, "failed to get reg_c "
12097 "for ASO flow hit");
12098 return 0; /* 0 is an error. */
12100 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12101 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12102 (priv->sh->rx_domain,
12103 pool->flow_hit_aso_obj->obj, age_free->offset,
12104 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12105 (reg_c - REG_C_0));
12106 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12107 if (!age_free->dr_action) {
12109 rte_spinlock_lock(&mng->free_sl);
12110 LIST_INSERT_HEAD(&mng->free, age_free, next);
12111 rte_spinlock_unlock(&mng->free_sl);
12112 rte_flow_error_set(error, rte_errno,
12113 RTE_FLOW_ERROR_TYPE_ACTION,
12114 NULL, "failed to create ASO "
12115 "flow hit action");
12116 return 0; /* 0 is an error. */
12119 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12120 return pool->index | ((age_free->offset + 1) << 16);
12124 * Initialize flow ASO age parameters.
12127 * Pointer to rte_eth_dev structure.
12128 * @param[in] age_idx
12129 * Index of ASO age action.
12130 * @param[in] context
12131 * Pointer to flow counter age context.
12132 * @param[in] timeout
12133 * Aging timeout in seconds.
12137 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12142 struct mlx5_aso_age_action *aso_age;
12144 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12145 MLX5_ASSERT(aso_age);
12146 aso_age->age_params.context = context;
12147 aso_age->age_params.timeout = timeout;
12148 aso_age->age_params.port_id = dev->data->port_id;
12149 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12151 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12156 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12157 const struct rte_flow_item_integrity *value,
12158 void *headers_m, void *headers_v)
12161 /* RTE l4_ok filter aggregates hardware l4_ok and
12162 * l4_checksum_ok filters.
12163 * Positive RTE l4_ok match requires hardware match on both L4
12164 * hardware integrity bits.
12165 * For negative match, check hardware l4_checksum_ok bit only,
12166 * because hardware sets that bit to 0 for all packets
12169 if (value->l4_ok) {
12170 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12171 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12173 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12174 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12177 if (mask->l4_csum_ok) {
12178 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12179 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12180 value->l4_csum_ok);
12185 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12186 const struct rte_flow_item_integrity *value,
12187 void *headers_m, void *headers_v, bool is_ipv4)
12190 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12191 * ipv4_csum_ok filters.
12192 * Positive RTE l3_ok match requires hardware match on both L3
12193 * hardware integrity bits.
12194 * For negative match, check hardware l3_csum_ok bit only,
12195 * because hardware sets that bit to 0 for all packets
12199 if (value->l3_ok) {
12200 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12202 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12205 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12206 ipv4_checksum_ok, 1);
12207 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12208 ipv4_checksum_ok, !!value->l3_ok);
12210 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12215 if (mask->ipv4_csum_ok) {
12216 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12218 value->ipv4_csum_ok);
12223 set_integrity_bits(void *headers_m, void *headers_v,
12224 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12226 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12227 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12229 /* Integrity bits validation cleared spec pointer */
12230 MLX5_ASSERT(spec != NULL);
12232 mask = &rte_flow_item_integrity_mask;
12233 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12235 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12239 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12241 struct rte_flow_item *integrity_items[2],
12242 uint64_t pattern_flags)
12244 void *headers_m, *headers_v;
12247 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12248 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12250 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12251 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12253 set_integrity_bits(headers_m, headers_v,
12254 integrity_items[1], is_l3_ip4);
12256 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12257 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12259 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12260 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12262 set_integrity_bits(headers_m, headers_v,
12263 integrity_items[0], is_l3_ip4);
12268 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12269 const struct rte_flow_item *integrity_items[2],
12270 uint64_t *last_item)
12272 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12274 /* integrity bits validation cleared spec pointer */
12275 MLX5_ASSERT(spec != NULL);
12276 if (spec->level > 1) {
12277 integrity_items[1] = item;
12278 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12280 integrity_items[0] = item;
12281 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12286 * Prepares DV flow counter with aging configuration.
12287 * Gets it by index when exists, creates a new one when doesn't.
12290 * Pointer to rte_eth_dev structure.
12291 * @param[in] dev_flow
12292 * Pointer to the mlx5_flow.
12293 * @param[in, out] flow
12294 * Pointer to the sub flow.
12296 * Pointer to the counter action configuration.
12298 * Pointer to the aging action configuration.
12299 * @param[out] error
12300 * Pointer to the error structure.
12303 * Pointer to the counter, NULL otherwise.
12305 static struct mlx5_flow_counter *
12306 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12307 struct mlx5_flow *dev_flow,
12308 struct rte_flow *flow,
12309 const struct rte_flow_action_count *count,
12310 const struct rte_flow_action_age *age,
12311 struct rte_flow_error *error)
12313 if (!flow->counter) {
12314 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12316 if (!flow->counter) {
12317 rte_flow_error_set(error, rte_errno,
12318 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12319 "cannot create counter object.");
12323 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12327 * Release an ASO CT action by its own device.
12330 * Pointer to the Ethernet device structure.
12332 * Index of ASO CT action to release.
12335 * 0 when CT action was removed, otherwise the number of references.
12338 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12340 struct mlx5_priv *priv = dev->data->dev_private;
12341 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12343 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12344 enum mlx5_aso_ct_state state =
12345 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12347 /* Cannot release when CT is in the ASO SQ. */
12348 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12350 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12352 if (ct->dr_action_orig) {
12353 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12354 claim_zero(mlx5_glue->destroy_flow_action
12355 (ct->dr_action_orig));
12357 ct->dr_action_orig = NULL;
12359 if (ct->dr_action_rply) {
12360 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12361 claim_zero(mlx5_glue->destroy_flow_action
12362 (ct->dr_action_rply));
12364 ct->dr_action_rply = NULL;
12366 /* Clear the state to free, no need in 1st allocation. */
12367 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12368 rte_spinlock_lock(&mng->ct_sl);
12369 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12370 rte_spinlock_unlock(&mng->ct_sl);
12376 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12377 struct rte_flow_error *error)
12379 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12380 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12381 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12384 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12385 if (dev->data->dev_started != 1)
12386 return rte_flow_error_set(error, EAGAIN,
12387 RTE_FLOW_ERROR_TYPE_ACTION,
12389 "Indirect CT action cannot be destroyed when the port is stopped");
12390 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12392 return rte_flow_error_set(error, EAGAIN,
12393 RTE_FLOW_ERROR_TYPE_ACTION,
12395 "Current state prevents indirect CT action from being destroyed");
12400 * Resize the ASO CT pools array by 64 pools.
12403 * Pointer to the Ethernet device structure.
12406 * 0 on success, otherwise negative errno value and rte_errno is set.
12409 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12411 struct mlx5_priv *priv = dev->data->dev_private;
12412 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12413 void *old_pools = mng->pools;
12414 /* Magic number now, need a macro. */
12415 uint32_t resize = mng->n + 64;
12416 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12417 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12420 rte_errno = ENOMEM;
12423 rte_rwlock_write_lock(&mng->resize_rwl);
12424 /* ASO SQ/QP was already initialized in the startup. */
12426 /* Realloc could be an alternative choice. */
12427 rte_memcpy(pools, old_pools,
12428 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12429 mlx5_free(old_pools);
12432 mng->pools = pools;
12433 rte_rwlock_write_unlock(&mng->resize_rwl);
12438 * Create and initialize a new ASO CT pool.
12441 * Pointer to the Ethernet device structure.
12442 * @param[out] ct_free
12443 * Where to put the pointer of a new CT action.
12446 * The CT actions pool pointer and @p ct_free is set on success,
12447 * NULL otherwise and rte_errno is set.
12449 static struct mlx5_aso_ct_pool *
12450 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12451 struct mlx5_aso_ct_action **ct_free)
12453 struct mlx5_priv *priv = dev->data->dev_private;
12454 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12455 struct mlx5_aso_ct_pool *pool = NULL;
12456 struct mlx5_devx_obj *obj = NULL;
12458 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12460 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12461 priv->sh->cdev->pdn,
12464 rte_errno = ENODATA;
12465 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12468 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12470 rte_errno = ENOMEM;
12471 claim_zero(mlx5_devx_cmd_destroy(obj));
12474 pool->devx_obj = obj;
12475 pool->index = mng->next;
12476 /* Resize pools array if there is no room for the new pool in it. */
12477 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12478 claim_zero(mlx5_devx_cmd_destroy(obj));
12482 mng->pools[pool->index] = pool;
12484 /* Assign the first action in the new pool, the rest go to free list. */
12485 *ct_free = &pool->actions[0];
12486 /* Lock outside, the list operation is safe here. */
12487 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12488 /* refcnt is 0 when allocating the memory. */
12489 pool->actions[i].offset = i;
12490 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12496 * Allocate a ASO CT action from free list.
12499 * Pointer to the Ethernet device structure.
12500 * @param[out] error
12501 * Pointer to the error structure.
12504 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12507 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12509 struct mlx5_priv *priv = dev->data->dev_private;
12510 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12511 struct mlx5_aso_ct_action *ct = NULL;
12512 struct mlx5_aso_ct_pool *pool;
12517 if (!priv->sh->devx) {
12518 rte_errno = ENOTSUP;
12521 /* Get a free CT action, if no, a new pool will be created. */
12522 rte_spinlock_lock(&mng->ct_sl);
12523 ct = LIST_FIRST(&mng->free_cts);
12525 LIST_REMOVE(ct, next);
12526 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12527 rte_spinlock_unlock(&mng->ct_sl);
12528 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12529 NULL, "failed to create ASO CT pool");
12532 rte_spinlock_unlock(&mng->ct_sl);
12533 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12534 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12535 /* 0: inactive, 1: created, 2+: used by flows. */
12536 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12537 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12538 if (!ct->dr_action_orig) {
12539 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12540 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12541 (priv->sh->rx_domain, pool->devx_obj->obj,
12543 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12546 RTE_SET_USED(reg_c);
12548 if (!ct->dr_action_orig) {
12549 flow_dv_aso_ct_dev_release(dev, ct_idx);
12550 rte_flow_error_set(error, rte_errno,
12551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12552 "failed to create ASO CT action");
12556 if (!ct->dr_action_rply) {
12557 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12558 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12559 (priv->sh->rx_domain, pool->devx_obj->obj,
12561 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12564 if (!ct->dr_action_rply) {
12565 flow_dv_aso_ct_dev_release(dev, ct_idx);
12566 rte_flow_error_set(error, rte_errno,
12567 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12568 "failed to create ASO CT action");
12576 * Create a conntrack object with context and actions by using ASO mechanism.
12579 * Pointer to rte_eth_dev structure.
12581 * Pointer to conntrack information profile.
12582 * @param[out] error
12583 * Pointer to the error structure.
12586 * Index to conntrack object on success, 0 otherwise.
12589 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12590 const struct rte_flow_action_conntrack *pro,
12591 struct rte_flow_error *error)
12593 struct mlx5_priv *priv = dev->data->dev_private;
12594 struct mlx5_dev_ctx_shared *sh = priv->sh;
12595 struct mlx5_aso_ct_action *ct;
12598 if (!sh->ct_aso_en)
12599 return rte_flow_error_set(error, ENOTSUP,
12600 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12601 "Connection is not supported");
12602 idx = flow_dv_aso_ct_alloc(dev, error);
12604 return rte_flow_error_set(error, rte_errno,
12605 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12606 "Failed to allocate CT object");
12607 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12608 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12609 return rte_flow_error_set(error, EBUSY,
12610 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12611 "Failed to update CT");
12612 ct->is_original = !!pro->is_original_dir;
12613 ct->peer = pro->peer_port;
12618 * Fill the flow with DV spec, lock free
12619 * (mutex should be acquired by caller).
12622 * Pointer to rte_eth_dev structure.
12623 * @param[in, out] dev_flow
12624 * Pointer to the sub flow.
12626 * Pointer to the flow attributes.
12628 * Pointer to the list of items.
12629 * @param[in] actions
12630 * Pointer to the list of actions.
12631 * @param[out] error
12632 * Pointer to the error structure.
12635 * 0 on success, a negative errno value otherwise and rte_errno is set.
12638 flow_dv_translate(struct rte_eth_dev *dev,
12639 struct mlx5_flow *dev_flow,
12640 const struct rte_flow_attr *attr,
12641 const struct rte_flow_item items[],
12642 const struct rte_flow_action actions[],
12643 struct rte_flow_error *error)
12645 struct mlx5_priv *priv = dev->data->dev_private;
12646 struct mlx5_dev_config *dev_conf = &priv->config;
12647 struct rte_flow *flow = dev_flow->flow;
12648 struct mlx5_flow_handle *handle = dev_flow->handle;
12649 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12650 struct mlx5_flow_rss_desc *rss_desc;
12651 uint64_t item_flags = 0;
12652 uint64_t last_item = 0;
12653 uint64_t action_flags = 0;
12654 struct mlx5_flow_dv_matcher matcher = {
12656 .size = sizeof(matcher.mask.buf),
12660 bool actions_end = false;
12662 struct mlx5_flow_dv_modify_hdr_resource res;
12663 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12664 sizeof(struct mlx5_modification_cmd) *
12665 (MLX5_MAX_MODIFY_NUM + 1)];
12667 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12668 const struct rte_flow_action_count *count = NULL;
12669 const struct rte_flow_action_age *non_shared_age = NULL;
12670 union flow_dv_attr flow_attr = { .attr = 0 };
12672 union mlx5_flow_tbl_key tbl_key;
12673 uint32_t modify_action_position = UINT32_MAX;
12674 void *match_mask = matcher.mask.buf;
12675 void *match_value = dev_flow->dv.value.buf;
12676 uint8_t next_protocol = 0xff;
12677 struct rte_vlan_hdr vlan = { 0 };
12678 struct mlx5_flow_dv_dest_array_resource mdest_res;
12679 struct mlx5_flow_dv_sample_resource sample_res;
12680 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12681 const struct rte_flow_action_sample *sample = NULL;
12682 struct mlx5_flow_sub_actions_list *sample_act;
12683 uint32_t sample_act_pos = UINT32_MAX;
12684 uint32_t age_act_pos = UINT32_MAX;
12685 uint32_t num_of_dest = 0;
12686 int tmp_actions_n = 0;
12689 const struct mlx5_flow_tunnel *tunnel = NULL;
12690 struct flow_grp_info grp_info = {
12691 .external = !!dev_flow->external,
12692 .transfer = !!attr->transfer,
12693 .fdb_def_rule = !!priv->fdb_def_rule,
12694 .skip_scale = dev_flow->skip_scale &
12695 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12696 .std_tbl_fix = true,
12698 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12699 const struct rte_flow_item *tunnel_item = NULL;
12702 return rte_flow_error_set(error, ENOMEM,
12703 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12705 "failed to push flow workspace");
12706 rss_desc = &wks->rss_desc;
12707 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12708 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12709 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12710 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12711 /* update normal path action resource into last index of array */
12712 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12713 if (is_tunnel_offload_active(dev)) {
12714 if (dev_flow->tunnel) {
12715 RTE_VERIFY(dev_flow->tof_type ==
12716 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12717 tunnel = dev_flow->tunnel;
12719 tunnel = mlx5_get_tof(items, actions,
12720 &dev_flow->tof_type);
12721 dev_flow->tunnel = tunnel;
12723 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12724 (dev, attr, tunnel, dev_flow->tof_type);
12726 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12727 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12728 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12732 dev_flow->dv.group = table;
12733 if (attr->transfer)
12734 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12735 /* number of actions must be set to 0 in case of dirty stack. */
12736 mhdr_res->actions_num = 0;
12737 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12739 * do not add decap action if match rule drops packet
12740 * HW rejects rules with decap & drop
12742 * if tunnel match rule was inserted before matching tunnel set
12743 * rule flow table used in the match rule must be registered.
12744 * current implementation handles that in the
12745 * flow_dv_match_register() at the function end.
12747 bool add_decap = true;
12748 const struct rte_flow_action *ptr = actions;
12750 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12751 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12757 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12761 dev_flow->dv.actions[actions_n++] =
12762 dev_flow->dv.encap_decap->action;
12763 action_flags |= MLX5_FLOW_ACTION_DECAP;
12766 for (; !actions_end ; actions++) {
12767 const struct rte_flow_action_queue *queue;
12768 const struct rte_flow_action_rss *rss;
12769 const struct rte_flow_action *action = actions;
12770 const uint8_t *rss_key;
12771 struct mlx5_flow_tbl_resource *tbl;
12772 struct mlx5_aso_age_action *age_act;
12773 struct mlx5_flow_counter *cnt_act;
12774 uint32_t port_id = 0;
12775 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12776 int action_type = actions->type;
12777 const struct rte_flow_action *found_action = NULL;
12778 uint32_t jump_group = 0;
12779 uint32_t owner_idx;
12780 struct mlx5_aso_ct_action *ct;
12782 if (!mlx5_flow_os_action_supported(action_type))
12783 return rte_flow_error_set(error, ENOTSUP,
12784 RTE_FLOW_ERROR_TYPE_ACTION,
12786 "action not supported");
12787 switch (action_type) {
12788 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12789 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12791 case RTE_FLOW_ACTION_TYPE_VOID:
12793 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12794 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12795 if (flow_dv_translate_action_port_id(dev, action,
12798 port_id_resource.port_id = port_id;
12799 MLX5_ASSERT(!handle->rix_port_id_action);
12800 if (flow_dv_port_id_action_resource_register
12801 (dev, &port_id_resource, dev_flow, error))
12803 dev_flow->dv.actions[actions_n++] =
12804 dev_flow->dv.port_id_action->action;
12805 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12806 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12807 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12810 case RTE_FLOW_ACTION_TYPE_FLAG:
12811 action_flags |= MLX5_FLOW_ACTION_FLAG;
12813 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12814 struct rte_flow_action_mark mark = {
12815 .id = MLX5_FLOW_MARK_DEFAULT,
12818 if (flow_dv_convert_action_mark(dev, &mark,
12822 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12825 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12827 * Only one FLAG or MARK is supported per device flow
12828 * right now. So the pointer to the tag resource must be
12829 * zero before the register process.
12831 MLX5_ASSERT(!handle->dvh.rix_tag);
12832 if (flow_dv_tag_resource_register(dev, tag_be,
12835 MLX5_ASSERT(dev_flow->dv.tag_resource);
12836 dev_flow->dv.actions[actions_n++] =
12837 dev_flow->dv.tag_resource->action;
12839 case RTE_FLOW_ACTION_TYPE_MARK:
12840 action_flags |= MLX5_FLOW_ACTION_MARK;
12842 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12843 const struct rte_flow_action_mark *mark =
12844 (const struct rte_flow_action_mark *)
12847 if (flow_dv_convert_action_mark(dev, mark,
12851 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12855 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12856 /* Legacy (non-extensive) MARK action. */
12857 tag_be = mlx5_flow_mark_set
12858 (((const struct rte_flow_action_mark *)
12859 (actions->conf))->id);
12860 MLX5_ASSERT(!handle->dvh.rix_tag);
12861 if (flow_dv_tag_resource_register(dev, tag_be,
12864 MLX5_ASSERT(dev_flow->dv.tag_resource);
12865 dev_flow->dv.actions[actions_n++] =
12866 dev_flow->dv.tag_resource->action;
12868 case RTE_FLOW_ACTION_TYPE_SET_META:
12869 if (flow_dv_convert_action_set_meta
12870 (dev, mhdr_res, attr,
12871 (const struct rte_flow_action_set_meta *)
12872 actions->conf, error))
12874 action_flags |= MLX5_FLOW_ACTION_SET_META;
12876 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12877 if (flow_dv_convert_action_set_tag
12879 (const struct rte_flow_action_set_tag *)
12880 actions->conf, error))
12882 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12884 case RTE_FLOW_ACTION_TYPE_DROP:
12885 action_flags |= MLX5_FLOW_ACTION_DROP;
12886 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12888 case RTE_FLOW_ACTION_TYPE_QUEUE:
12889 queue = actions->conf;
12890 rss_desc->queue_num = 1;
12891 rss_desc->queue[0] = queue->index;
12892 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12893 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12894 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12897 case RTE_FLOW_ACTION_TYPE_RSS:
12898 rss = actions->conf;
12899 memcpy(rss_desc->queue, rss->queue,
12900 rss->queue_num * sizeof(uint16_t));
12901 rss_desc->queue_num = rss->queue_num;
12902 /* NULL RSS key indicates default RSS key. */
12903 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12904 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12906 * rss->level and rss.types should be set in advance
12907 * when expanding items for RSS.
12909 action_flags |= MLX5_FLOW_ACTION_RSS;
12910 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12911 MLX5_FLOW_FATE_SHARED_RSS :
12912 MLX5_FLOW_FATE_QUEUE;
12914 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12915 owner_idx = (uint32_t)(uintptr_t)action->conf;
12916 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12917 if (flow->age == 0) {
12918 flow->age = owner_idx;
12919 __atomic_fetch_add(&age_act->refcnt, 1,
12922 age_act_pos = actions_n++;
12923 action_flags |= MLX5_FLOW_ACTION_AGE;
12925 case RTE_FLOW_ACTION_TYPE_AGE:
12926 non_shared_age = action->conf;
12927 age_act_pos = actions_n++;
12928 action_flags |= MLX5_FLOW_ACTION_AGE;
12930 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12931 owner_idx = (uint32_t)(uintptr_t)action->conf;
12932 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12934 MLX5_ASSERT(cnt_act != NULL);
12936 * When creating meter drop flow in drop table, the
12937 * counter should not overwrite the rte flow counter.
12939 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12940 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12941 dev_flow->dv.actions[actions_n++] =
12944 if (flow->counter == 0) {
12945 flow->counter = owner_idx;
12947 (&cnt_act->shared_info.refcnt,
12948 1, __ATOMIC_RELAXED);
12950 /* Save information first, will apply later. */
12951 action_flags |= MLX5_FLOW_ACTION_COUNT;
12954 case RTE_FLOW_ACTION_TYPE_COUNT:
12955 if (!priv->sh->devx) {
12956 return rte_flow_error_set
12958 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12960 "count action not supported");
12962 /* Save information first, will apply later. */
12963 count = action->conf;
12964 action_flags |= MLX5_FLOW_ACTION_COUNT;
12966 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12967 dev_flow->dv.actions[actions_n++] =
12968 priv->sh->pop_vlan_action;
12969 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12971 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12972 if (!(action_flags &
12973 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12974 flow_dev_get_vlan_info_from_items(items, &vlan);
12975 vlan.eth_proto = rte_be_to_cpu_16
12976 ((((const struct rte_flow_action_of_push_vlan *)
12977 actions->conf)->ethertype));
12978 found_action = mlx5_flow_find_action
12980 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12982 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12983 found_action = mlx5_flow_find_action
12985 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12987 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12988 if (flow_dv_create_action_push_vlan
12989 (dev, attr, &vlan, dev_flow, error))
12991 dev_flow->dv.actions[actions_n++] =
12992 dev_flow->dv.push_vlan_res->action;
12993 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
12995 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
12996 /* of_vlan_push action handled this action */
12997 MLX5_ASSERT(action_flags &
12998 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13000 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13001 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13003 flow_dev_get_vlan_info_from_items(items, &vlan);
13004 mlx5_update_vlan_vid_pcp(actions, &vlan);
13005 /* If no VLAN push - this is a modify header action */
13006 if (flow_dv_convert_action_modify_vlan_vid
13007 (mhdr_res, actions, error))
13009 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13011 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13012 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13013 if (flow_dv_create_action_l2_encap(dev, actions,
13018 dev_flow->dv.actions[actions_n++] =
13019 dev_flow->dv.encap_decap->action;
13020 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13021 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13022 sample_act->action_flags |=
13023 MLX5_FLOW_ACTION_ENCAP;
13025 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13026 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13027 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13031 dev_flow->dv.actions[actions_n++] =
13032 dev_flow->dv.encap_decap->action;
13033 action_flags |= MLX5_FLOW_ACTION_DECAP;
13035 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13036 /* Handle encap with preceding decap. */
13037 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13038 if (flow_dv_create_action_raw_encap
13039 (dev, actions, dev_flow, attr, error))
13041 dev_flow->dv.actions[actions_n++] =
13042 dev_flow->dv.encap_decap->action;
13044 /* Handle encap without preceding decap. */
13045 if (flow_dv_create_action_l2_encap
13046 (dev, actions, dev_flow, attr->transfer,
13049 dev_flow->dv.actions[actions_n++] =
13050 dev_flow->dv.encap_decap->action;
13052 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13053 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13054 sample_act->action_flags |=
13055 MLX5_FLOW_ACTION_ENCAP;
13057 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13058 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13060 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13061 if (flow_dv_create_action_l2_decap
13062 (dev, dev_flow, attr->transfer, error))
13064 dev_flow->dv.actions[actions_n++] =
13065 dev_flow->dv.encap_decap->action;
13067 /* If decap is followed by encap, handle it at encap. */
13068 action_flags |= MLX5_FLOW_ACTION_DECAP;
13070 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13071 dev_flow->dv.actions[actions_n++] =
13072 (void *)(uintptr_t)action->conf;
13073 action_flags |= MLX5_FLOW_ACTION_JUMP;
13075 case RTE_FLOW_ACTION_TYPE_JUMP:
13076 jump_group = ((const struct rte_flow_action_jump *)
13077 action->conf)->group;
13078 grp_info.std_tbl_fix = 0;
13079 if (dev_flow->skip_scale &
13080 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13081 grp_info.skip_scale = 1;
13083 grp_info.skip_scale = 0;
13084 ret = mlx5_flow_group_to_table(dev, tunnel,
13090 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13092 !!dev_flow->external,
13093 tunnel, jump_group, 0,
13096 return rte_flow_error_set
13098 RTE_FLOW_ERROR_TYPE_ACTION,
13100 "cannot create jump action.");
13101 if (flow_dv_jump_tbl_resource_register
13102 (dev, tbl, dev_flow, error)) {
13103 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13104 return rte_flow_error_set
13106 RTE_FLOW_ERROR_TYPE_ACTION,
13108 "cannot create jump action.");
13110 dev_flow->dv.actions[actions_n++] =
13111 dev_flow->dv.jump->action;
13112 action_flags |= MLX5_FLOW_ACTION_JUMP;
13113 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13114 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13117 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13118 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13119 if (flow_dv_convert_action_modify_mac
13120 (mhdr_res, actions, error))
13122 action_flags |= actions->type ==
13123 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13124 MLX5_FLOW_ACTION_SET_MAC_SRC :
13125 MLX5_FLOW_ACTION_SET_MAC_DST;
13127 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13128 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13129 if (flow_dv_convert_action_modify_ipv4
13130 (mhdr_res, actions, error))
13132 action_flags |= actions->type ==
13133 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13134 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13135 MLX5_FLOW_ACTION_SET_IPV4_DST;
13137 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13138 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13139 if (flow_dv_convert_action_modify_ipv6
13140 (mhdr_res, actions, error))
13142 action_flags |= actions->type ==
13143 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13144 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13145 MLX5_FLOW_ACTION_SET_IPV6_DST;
13147 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13148 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13149 if (flow_dv_convert_action_modify_tp
13150 (mhdr_res, actions, items,
13151 &flow_attr, dev_flow, !!(action_flags &
13152 MLX5_FLOW_ACTION_DECAP), error))
13154 action_flags |= actions->type ==
13155 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13156 MLX5_FLOW_ACTION_SET_TP_SRC :
13157 MLX5_FLOW_ACTION_SET_TP_DST;
13159 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13160 if (flow_dv_convert_action_modify_dec_ttl
13161 (mhdr_res, items, &flow_attr, dev_flow,
13163 MLX5_FLOW_ACTION_DECAP), error))
13165 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13167 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13168 if (flow_dv_convert_action_modify_ttl
13169 (mhdr_res, actions, items, &flow_attr,
13170 dev_flow, !!(action_flags &
13171 MLX5_FLOW_ACTION_DECAP), error))
13173 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13175 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13176 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13177 if (flow_dv_convert_action_modify_tcp_seq
13178 (mhdr_res, actions, error))
13180 action_flags |= actions->type ==
13181 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13182 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13183 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13186 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13187 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13188 if (flow_dv_convert_action_modify_tcp_ack
13189 (mhdr_res, actions, error))
13191 action_flags |= actions->type ==
13192 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13193 MLX5_FLOW_ACTION_INC_TCP_ACK :
13194 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13196 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13197 if (flow_dv_convert_action_set_reg
13198 (mhdr_res, actions, error))
13200 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13202 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13203 if (flow_dv_convert_action_copy_mreg
13204 (dev, mhdr_res, actions, error))
13206 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13208 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13209 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13210 dev_flow->handle->fate_action =
13211 MLX5_FLOW_FATE_DEFAULT_MISS;
13213 case RTE_FLOW_ACTION_TYPE_METER:
13215 return rte_flow_error_set(error, rte_errno,
13216 RTE_FLOW_ERROR_TYPE_ACTION,
13217 NULL, "Failed to get meter in flow.");
13218 /* Set the meter action. */
13219 dev_flow->dv.actions[actions_n++] =
13220 wks->fm->meter_action;
13221 action_flags |= MLX5_FLOW_ACTION_METER;
13223 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13224 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13227 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13229 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13230 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13233 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13235 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13236 sample_act_pos = actions_n;
13237 sample = (const struct rte_flow_action_sample *)
13240 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13241 /* put encap action into group if work with port id */
13242 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13243 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13244 sample_act->action_flags |=
13245 MLX5_FLOW_ACTION_ENCAP;
13247 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13248 if (flow_dv_convert_action_modify_field
13249 (dev, mhdr_res, actions, attr, error))
13251 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13253 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13254 owner_idx = (uint32_t)(uintptr_t)action->conf;
13255 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13257 return rte_flow_error_set(error, EINVAL,
13258 RTE_FLOW_ERROR_TYPE_ACTION,
13260 "Failed to get CT object.");
13261 if (mlx5_aso_ct_available(priv->sh, ct))
13262 return rte_flow_error_set(error, rte_errno,
13263 RTE_FLOW_ERROR_TYPE_ACTION,
13265 "CT is unavailable.");
13266 if (ct->is_original)
13267 dev_flow->dv.actions[actions_n] =
13268 ct->dr_action_orig;
13270 dev_flow->dv.actions[actions_n] =
13271 ct->dr_action_rply;
13272 if (flow->ct == 0) {
13273 flow->indirect_type =
13274 MLX5_INDIRECT_ACTION_TYPE_CT;
13275 flow->ct = owner_idx;
13276 __atomic_fetch_add(&ct->refcnt, 1,
13280 action_flags |= MLX5_FLOW_ACTION_CT;
13282 case RTE_FLOW_ACTION_TYPE_END:
13283 actions_end = true;
13284 if (mhdr_res->actions_num) {
13285 /* create modify action if needed. */
13286 if (flow_dv_modify_hdr_resource_register
13287 (dev, mhdr_res, dev_flow, error))
13289 dev_flow->dv.actions[modify_action_position] =
13290 handle->dvh.modify_hdr->action;
13293 * Handle AGE and COUNT action by single HW counter
13294 * when they are not shared.
13296 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13297 if ((non_shared_age && count) ||
13298 !(priv->sh->flow_hit_aso_en &&
13299 (attr->group || attr->transfer))) {
13300 /* Creates age by counters. */
13301 cnt_act = flow_dv_prepare_counter
13308 dev_flow->dv.actions[age_act_pos] =
13312 if (!flow->age && non_shared_age) {
13313 flow->age = flow_dv_aso_age_alloc
13317 flow_dv_aso_age_params_init
13319 non_shared_age->context ?
13320 non_shared_age->context :
13321 (void *)(uintptr_t)
13322 (dev_flow->flow_idx),
13323 non_shared_age->timeout);
13325 age_act = flow_aso_age_get_by_idx(dev,
13327 dev_flow->dv.actions[age_act_pos] =
13328 age_act->dr_action;
13330 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13332 * Create one count action, to be used
13333 * by all sub-flows.
13335 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13340 dev_flow->dv.actions[actions_n++] =
13346 if (mhdr_res->actions_num &&
13347 modify_action_position == UINT32_MAX)
13348 modify_action_position = actions_n++;
13350 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13351 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13352 int item_type = items->type;
13354 if (!mlx5_flow_os_item_supported(item_type))
13355 return rte_flow_error_set(error, ENOTSUP,
13356 RTE_FLOW_ERROR_TYPE_ITEM,
13357 NULL, "item not supported");
13358 switch (item_type) {
13359 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13360 flow_dv_translate_item_port_id
13361 (dev, match_mask, match_value, items, attr);
13362 last_item = MLX5_FLOW_ITEM_PORT_ID;
13364 case RTE_FLOW_ITEM_TYPE_ETH:
13365 flow_dv_translate_item_eth(match_mask, match_value,
13367 dev_flow->dv.group);
13368 matcher.priority = action_flags &
13369 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13370 !dev_flow->external ?
13371 MLX5_PRIORITY_MAP_L3 :
13372 MLX5_PRIORITY_MAP_L2;
13373 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13374 MLX5_FLOW_LAYER_OUTER_L2;
13376 case RTE_FLOW_ITEM_TYPE_VLAN:
13377 flow_dv_translate_item_vlan(dev_flow,
13378 match_mask, match_value,
13380 dev_flow->dv.group);
13381 matcher.priority = MLX5_PRIORITY_MAP_L2;
13382 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13383 MLX5_FLOW_LAYER_INNER_VLAN) :
13384 (MLX5_FLOW_LAYER_OUTER_L2 |
13385 MLX5_FLOW_LAYER_OUTER_VLAN);
13387 case RTE_FLOW_ITEM_TYPE_IPV4:
13388 mlx5_flow_tunnel_ip_check(items, next_protocol,
13389 &item_flags, &tunnel);
13390 flow_dv_translate_item_ipv4(match_mask, match_value,
13392 dev_flow->dv.group);
13393 matcher.priority = MLX5_PRIORITY_MAP_L3;
13394 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13395 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13396 if (items->mask != NULL &&
13397 ((const struct rte_flow_item_ipv4 *)
13398 items->mask)->hdr.next_proto_id) {
13400 ((const struct rte_flow_item_ipv4 *)
13401 (items->spec))->hdr.next_proto_id;
13403 ((const struct rte_flow_item_ipv4 *)
13404 (items->mask))->hdr.next_proto_id;
13406 /* Reset for inner layer. */
13407 next_protocol = 0xff;
13410 case RTE_FLOW_ITEM_TYPE_IPV6:
13411 mlx5_flow_tunnel_ip_check(items, next_protocol,
13412 &item_flags, &tunnel);
13413 flow_dv_translate_item_ipv6(match_mask, match_value,
13415 dev_flow->dv.group);
13416 matcher.priority = MLX5_PRIORITY_MAP_L3;
13417 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13418 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13419 if (items->mask != NULL &&
13420 ((const struct rte_flow_item_ipv6 *)
13421 items->mask)->hdr.proto) {
13423 ((const struct rte_flow_item_ipv6 *)
13424 items->spec)->hdr.proto;
13426 ((const struct rte_flow_item_ipv6 *)
13427 items->mask)->hdr.proto;
13429 /* Reset for inner layer. */
13430 next_protocol = 0xff;
13433 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13434 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13437 last_item = tunnel ?
13438 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13439 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13440 if (items->mask != NULL &&
13441 ((const struct rte_flow_item_ipv6_frag_ext *)
13442 items->mask)->hdr.next_header) {
13444 ((const struct rte_flow_item_ipv6_frag_ext *)
13445 items->spec)->hdr.next_header;
13447 ((const struct rte_flow_item_ipv6_frag_ext *)
13448 items->mask)->hdr.next_header;
13450 /* Reset for inner layer. */
13451 next_protocol = 0xff;
13454 case RTE_FLOW_ITEM_TYPE_TCP:
13455 flow_dv_translate_item_tcp(match_mask, match_value,
13457 matcher.priority = MLX5_PRIORITY_MAP_L4;
13458 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13459 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13461 case RTE_FLOW_ITEM_TYPE_UDP:
13462 flow_dv_translate_item_udp(match_mask, match_value,
13464 matcher.priority = MLX5_PRIORITY_MAP_L4;
13465 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13466 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13468 case RTE_FLOW_ITEM_TYPE_GRE:
13469 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13470 last_item = MLX5_FLOW_LAYER_GRE;
13471 tunnel_item = items;
13473 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13474 flow_dv_translate_item_gre_key(match_mask,
13475 match_value, items);
13476 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13478 case RTE_FLOW_ITEM_TYPE_NVGRE:
13479 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13480 last_item = MLX5_FLOW_LAYER_GRE;
13481 tunnel_item = items;
13483 case RTE_FLOW_ITEM_TYPE_VXLAN:
13484 flow_dv_translate_item_vxlan(dev, attr,
13485 match_mask, match_value,
13487 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13488 last_item = MLX5_FLOW_LAYER_VXLAN;
13490 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13491 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13492 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13493 tunnel_item = items;
13495 case RTE_FLOW_ITEM_TYPE_GENEVE:
13496 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13497 last_item = MLX5_FLOW_LAYER_GENEVE;
13498 tunnel_item = items;
13500 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13501 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13505 return rte_flow_error_set(error, -ret,
13506 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13507 "cannot create GENEVE TLV option");
13508 flow->geneve_tlv_option = 1;
13509 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13511 case RTE_FLOW_ITEM_TYPE_MPLS:
13512 flow_dv_translate_item_mpls(match_mask, match_value,
13513 items, last_item, tunnel);
13514 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13515 last_item = MLX5_FLOW_LAYER_MPLS;
13517 case RTE_FLOW_ITEM_TYPE_MARK:
13518 flow_dv_translate_item_mark(dev, match_mask,
13519 match_value, items);
13520 last_item = MLX5_FLOW_ITEM_MARK;
13522 case RTE_FLOW_ITEM_TYPE_META:
13523 flow_dv_translate_item_meta(dev, match_mask,
13524 match_value, attr, items);
13525 last_item = MLX5_FLOW_ITEM_METADATA;
13527 case RTE_FLOW_ITEM_TYPE_ICMP:
13528 flow_dv_translate_item_icmp(match_mask, match_value,
13530 last_item = MLX5_FLOW_LAYER_ICMP;
13532 case RTE_FLOW_ITEM_TYPE_ICMP6:
13533 flow_dv_translate_item_icmp6(match_mask, match_value,
13535 last_item = MLX5_FLOW_LAYER_ICMP6;
13537 case RTE_FLOW_ITEM_TYPE_TAG:
13538 flow_dv_translate_item_tag(dev, match_mask,
13539 match_value, items);
13540 last_item = MLX5_FLOW_ITEM_TAG;
13542 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13543 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13544 match_value, items);
13545 last_item = MLX5_FLOW_ITEM_TAG;
13547 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13548 flow_dv_translate_item_tx_queue(dev, match_mask,
13551 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13553 case RTE_FLOW_ITEM_TYPE_GTP:
13554 flow_dv_translate_item_gtp(match_mask, match_value,
13556 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13557 last_item = MLX5_FLOW_LAYER_GTP;
13559 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13560 ret = flow_dv_translate_item_gtp_psc(match_mask,
13564 return rte_flow_error_set(error, -ret,
13565 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13566 "cannot create GTP PSC item");
13567 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13569 case RTE_FLOW_ITEM_TYPE_ECPRI:
13570 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13571 /* Create it only the first time to be used. */
13572 ret = mlx5_flex_parser_ecpri_alloc(dev);
13574 return rte_flow_error_set
13576 RTE_FLOW_ERROR_TYPE_ITEM,
13578 "cannot create eCPRI parser");
13580 flow_dv_translate_item_ecpri(dev, match_mask,
13581 match_value, items,
13583 /* No other protocol should follow eCPRI layer. */
13584 last_item = MLX5_FLOW_LAYER_ECPRI;
13586 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13587 flow_dv_translate_item_integrity(items, integrity_items,
13590 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13591 flow_dv_translate_item_aso_ct(dev, match_mask,
13592 match_value, items);
13594 case RTE_FLOW_ITEM_TYPE_FLEX:
13595 flow_dv_translate_item_flex(dev, match_mask,
13596 match_value, items,
13597 dev_flow, tunnel != 0);
13598 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13599 MLX5_FLOW_ITEM_OUTER_FLEX;
13604 item_flags |= last_item;
13607 * When E-Switch mode is enabled, we have two cases where we need to
13608 * set the source port manually.
13609 * The first one, is in case of Nic steering rule, and the second is
13610 * E-Switch rule where no port_id item was found. In both cases
13611 * the source port is set according the current port in use.
13613 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13614 (priv->representor || priv->master)) {
13615 if (flow_dv_translate_item_port_id(dev, match_mask,
13616 match_value, NULL, attr))
13619 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13620 flow_dv_translate_item_integrity_post(match_mask, match_value,
13624 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13625 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13626 tunnel_item, item_flags);
13627 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13628 flow_dv_translate_item_geneve(match_mask, match_value,
13629 tunnel_item, item_flags);
13630 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13631 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13632 flow_dv_translate_item_gre(match_mask, match_value,
13633 tunnel_item, item_flags);
13634 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13635 flow_dv_translate_item_nvgre(match_mask, match_value,
13636 tunnel_item, item_flags);
13638 MLX5_ASSERT(false);
13640 #ifdef RTE_LIBRTE_MLX5_DEBUG
13641 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13642 dev_flow->dv.value.buf));
13645 * Layers may be already initialized from prefix flow if this dev_flow
13646 * is the suffix flow.
13648 handle->layers |= item_flags;
13649 if (action_flags & MLX5_FLOW_ACTION_RSS)
13650 flow_dv_hashfields_set(dev_flow, rss_desc);
13651 /* If has RSS action in the sample action, the Sample/Mirror resource
13652 * should be registered after the hash filed be update.
13654 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13655 ret = flow_dv_translate_action_sample(dev,
13664 ret = flow_dv_create_action_sample(dev,
13673 return rte_flow_error_set
13675 RTE_FLOW_ERROR_TYPE_ACTION,
13677 "cannot create sample action");
13678 if (num_of_dest > 1) {
13679 dev_flow->dv.actions[sample_act_pos] =
13680 dev_flow->dv.dest_array_res->action;
13682 dev_flow->dv.actions[sample_act_pos] =
13683 dev_flow->dv.sample_res->verbs_action;
13687 * For multiple destination (sample action with ratio=1), the encap
13688 * action and port id action will be combined into group action.
13689 * So need remove the original these actions in the flow and only
13690 * use the sample action instead of.
13692 if (num_of_dest > 1 &&
13693 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13695 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13697 for (i = 0; i < actions_n; i++) {
13698 if ((sample_act->dr_encap_action &&
13699 sample_act->dr_encap_action ==
13700 dev_flow->dv.actions[i]) ||
13701 (sample_act->dr_port_id_action &&
13702 sample_act->dr_port_id_action ==
13703 dev_flow->dv.actions[i]) ||
13704 (sample_act->dr_jump_action &&
13705 sample_act->dr_jump_action ==
13706 dev_flow->dv.actions[i]))
13708 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13710 memcpy((void *)dev_flow->dv.actions,
13711 (void *)temp_actions,
13712 tmp_actions_n * sizeof(void *));
13713 actions_n = tmp_actions_n;
13715 dev_flow->dv.actions_n = actions_n;
13716 dev_flow->act_flags = action_flags;
13717 if (wks->skip_matcher_reg)
13719 /* Register matcher. */
13720 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13721 matcher.mask.size);
13722 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13724 dev_flow->external);
13726 * When creating meter drop flow in drop table, using original
13727 * 5-tuple match, the matcher priority should be lower than
13730 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13731 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13732 matcher.priority <= MLX5_REG_BITS)
13733 matcher.priority += MLX5_REG_BITS;
13734 /* reserved field no needs to be set to 0 here. */
13735 tbl_key.is_fdb = attr->transfer;
13736 tbl_key.is_egress = attr->egress;
13737 tbl_key.level = dev_flow->dv.group;
13738 tbl_key.id = dev_flow->dv.table_id;
13739 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13740 tunnel, attr->group, error))
13746 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13749 * @param[in, out] action
13750 * Shred RSS action holding hash RX queue objects.
13751 * @param[in] hash_fields
13752 * Defines combination of packet fields to participate in RX hash.
13753 * @param[in] tunnel
13755 * @param[in] hrxq_idx
13756 * Hash RX queue index to set.
13759 * 0 on success, otherwise negative errno value.
13762 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13763 const uint64_t hash_fields,
13766 uint32_t *hrxqs = action->hrxq;
13768 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13769 case MLX5_RSS_HASH_IPV4:
13770 /* fall-through. */
13771 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13772 /* fall-through. */
13773 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13774 hrxqs[0] = hrxq_idx;
13776 case MLX5_RSS_HASH_IPV4_TCP:
13777 /* fall-through. */
13778 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13779 /* fall-through. */
13780 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13781 hrxqs[1] = hrxq_idx;
13783 case MLX5_RSS_HASH_IPV4_UDP:
13784 /* fall-through. */
13785 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13786 /* fall-through. */
13787 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13788 hrxqs[2] = hrxq_idx;
13790 case MLX5_RSS_HASH_IPV6:
13791 /* fall-through. */
13792 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13793 /* fall-through. */
13794 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13795 hrxqs[3] = hrxq_idx;
13797 case MLX5_RSS_HASH_IPV6_TCP:
13798 /* fall-through. */
13799 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13800 /* fall-through. */
13801 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13802 hrxqs[4] = hrxq_idx;
13804 case MLX5_RSS_HASH_IPV6_UDP:
13805 /* fall-through. */
13806 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13807 /* fall-through. */
13808 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13809 hrxqs[5] = hrxq_idx;
13811 case MLX5_RSS_HASH_NONE:
13812 hrxqs[6] = hrxq_idx;
13820 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13824 * Pointer to the Ethernet device structure.
13826 * Shared RSS action ID holding hash RX queue objects.
13827 * @param[in] hash_fields
13828 * Defines combination of packet fields to participate in RX hash.
13829 * @param[in] tunnel
13833 * Valid hash RX queue index, otherwise 0.
13836 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13837 const uint64_t hash_fields)
13839 struct mlx5_priv *priv = dev->data->dev_private;
13840 struct mlx5_shared_action_rss *shared_rss =
13841 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13842 const uint32_t *hrxqs = shared_rss->hrxq;
13844 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13845 case MLX5_RSS_HASH_IPV4:
13846 /* fall-through. */
13847 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13848 /* fall-through. */
13849 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13851 case MLX5_RSS_HASH_IPV4_TCP:
13852 /* fall-through. */
13853 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13854 /* fall-through. */
13855 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13857 case MLX5_RSS_HASH_IPV4_UDP:
13858 /* fall-through. */
13859 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13860 /* fall-through. */
13861 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13863 case MLX5_RSS_HASH_IPV6:
13864 /* fall-through. */
13865 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13866 /* fall-through. */
13867 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13869 case MLX5_RSS_HASH_IPV6_TCP:
13870 /* fall-through. */
13871 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13872 /* fall-through. */
13873 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13875 case MLX5_RSS_HASH_IPV6_UDP:
13876 /* fall-through. */
13877 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13878 /* fall-through. */
13879 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13881 case MLX5_RSS_HASH_NONE:
13890 * Apply the flow to the NIC, lock free,
13891 * (mutex should be acquired by caller).
13894 * Pointer to the Ethernet device structure.
13895 * @param[in, out] flow
13896 * Pointer to flow structure.
13897 * @param[out] error
13898 * Pointer to error structure.
13901 * 0 on success, a negative errno value otherwise and rte_errno is set.
13904 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13905 struct rte_flow_error *error)
13907 struct mlx5_flow_dv_workspace *dv;
13908 struct mlx5_flow_handle *dh;
13909 struct mlx5_flow_handle_dv *dv_h;
13910 struct mlx5_flow *dev_flow;
13911 struct mlx5_priv *priv = dev->data->dev_private;
13912 uint32_t handle_idx;
13916 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13917 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13921 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13922 dev_flow = &wks->flows[idx];
13923 dv = &dev_flow->dv;
13924 dh = dev_flow->handle;
13927 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13928 if (dv->transfer) {
13929 MLX5_ASSERT(priv->sh->dr_drop_action);
13930 dv->actions[n++] = priv->sh->dr_drop_action;
13932 #ifdef HAVE_MLX5DV_DR
13933 /* DR supports drop action placeholder. */
13934 MLX5_ASSERT(priv->sh->dr_drop_action);
13935 dv->actions[n++] = dv->group ?
13936 priv->sh->dr_drop_action :
13937 priv->root_drop_action;
13939 /* For DV we use the explicit drop queue. */
13940 MLX5_ASSERT(priv->drop_queue.hrxq);
13942 priv->drop_queue.hrxq->action;
13945 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13946 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13947 struct mlx5_hrxq *hrxq;
13950 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13955 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13956 "cannot get hash queue");
13959 dh->rix_hrxq = hrxq_idx;
13960 dv->actions[n++] = hrxq->action;
13961 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13962 struct mlx5_hrxq *hrxq = NULL;
13965 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13966 rss_desc->shared_rss,
13967 dev_flow->hash_fields);
13969 hrxq = mlx5_ipool_get
13970 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13975 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13976 "cannot get hash queue");
13979 dh->rix_srss = rss_desc->shared_rss;
13980 dv->actions[n++] = hrxq->action;
13981 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13982 if (!priv->sh->default_miss_action) {
13985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13986 "default miss action not be created.");
13989 dv->actions[n++] = priv->sh->default_miss_action;
13991 misc_mask = flow_dv_matcher_enable(dv->value.buf);
13992 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
13993 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
13994 (void *)&dv->value, n,
13995 dv->actions, &dh->drv_flow);
13999 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14001 (!priv->config.allow_duplicate_pattern &&
14003 "duplicating pattern is not allowed" :
14004 "hardware refuses to create flow");
14007 if (priv->vmwa_context &&
14008 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14010 * The rule contains the VLAN pattern.
14011 * For VF we are going to create VLAN
14012 * interface to make hypervisor set correct
14013 * e-Switch vport context.
14015 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14020 err = rte_errno; /* Save rte_errno before cleanup. */
14021 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14022 handle_idx, dh, next) {
14023 /* hrxq is union, don't clear it if the flag is not set. */
14024 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14025 mlx5_hrxq_release(dev, dh->rix_hrxq);
14027 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14030 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14031 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14033 rte_errno = err; /* Restore rte_errno. */
14038 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14039 struct mlx5_list_entry *entry)
14041 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14045 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14046 mlx5_free(resource);
14050 * Release the flow matcher.
14053 * Pointer to Ethernet device.
14055 * Index to port ID action resource.
14058 * 1 while a reference on it exists, 0 when freed.
14061 flow_dv_matcher_release(struct rte_eth_dev *dev,
14062 struct mlx5_flow_handle *handle)
14064 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14065 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14066 typeof(*tbl), tbl);
14069 MLX5_ASSERT(matcher->matcher_object);
14070 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14071 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14076 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14078 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14079 struct mlx5_flow_dv_encap_decap_resource *res =
14080 container_of(entry, typeof(*res), entry);
14082 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14083 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14087 * Release an encap/decap resource.
14090 * Pointer to Ethernet device.
14091 * @param encap_decap_idx
14092 * Index of encap decap resource.
14095 * 1 while a reference on it exists, 0 when freed.
14098 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14099 uint32_t encap_decap_idx)
14101 struct mlx5_priv *priv = dev->data->dev_private;
14102 struct mlx5_flow_dv_encap_decap_resource *resource;
14104 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14108 MLX5_ASSERT(resource->action);
14109 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14113 * Release an jump to table action resource.
14116 * Pointer to Ethernet device.
14118 * Index to the jump action resource.
14121 * 1 while a reference on it exists, 0 when freed.
14124 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14127 struct mlx5_priv *priv = dev->data->dev_private;
14128 struct mlx5_flow_tbl_data_entry *tbl_data;
14130 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14134 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14138 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14140 struct mlx5_flow_dv_modify_hdr_resource *res =
14141 container_of(entry, typeof(*res), entry);
14142 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14144 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14145 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14149 * Release a modify-header resource.
14152 * Pointer to Ethernet device.
14154 * Pointer to mlx5_flow_handle.
14157 * 1 while a reference on it exists, 0 when freed.
14160 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14161 struct mlx5_flow_handle *handle)
14163 struct mlx5_priv *priv = dev->data->dev_private;
14164 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14166 MLX5_ASSERT(entry->action);
14167 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14171 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14173 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14174 struct mlx5_flow_dv_port_id_action_resource *resource =
14175 container_of(entry, typeof(*resource), entry);
14177 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14178 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14182 * Release port ID action resource.
14185 * Pointer to Ethernet device.
14187 * Pointer to mlx5_flow_handle.
14190 * 1 while a reference on it exists, 0 when freed.
14193 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14196 struct mlx5_priv *priv = dev->data->dev_private;
14197 struct mlx5_flow_dv_port_id_action_resource *resource;
14199 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14202 MLX5_ASSERT(resource->action);
14203 return mlx5_list_unregister(priv->sh->port_id_action_list,
14208 * Release shared RSS action resource.
14211 * Pointer to Ethernet device.
14213 * Shared RSS action index.
14216 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14218 struct mlx5_priv *priv = dev->data->dev_private;
14219 struct mlx5_shared_action_rss *shared_rss;
14221 shared_rss = mlx5_ipool_get
14222 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14223 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14227 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14229 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14230 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14231 container_of(entry, typeof(*resource), entry);
14233 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14234 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14238 * Release push vlan action resource.
14241 * Pointer to Ethernet device.
14243 * Pointer to mlx5_flow_handle.
14246 * 1 while a reference on it exists, 0 when freed.
14249 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14250 struct mlx5_flow_handle *handle)
14252 struct mlx5_priv *priv = dev->data->dev_private;
14253 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14254 uint32_t idx = handle->dvh.rix_push_vlan;
14256 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14259 MLX5_ASSERT(resource->action);
14260 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14265 * Release the fate resource.
14268 * Pointer to Ethernet device.
14270 * Pointer to mlx5_flow_handle.
14273 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14274 struct mlx5_flow_handle *handle)
14276 if (!handle->rix_fate)
14278 switch (handle->fate_action) {
14279 case MLX5_FLOW_FATE_QUEUE:
14280 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14281 mlx5_hrxq_release(dev, handle->rix_hrxq);
14283 case MLX5_FLOW_FATE_JUMP:
14284 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14286 case MLX5_FLOW_FATE_PORT_ID:
14287 flow_dv_port_id_action_resource_release(dev,
14288 handle->rix_port_id_action);
14291 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14294 handle->rix_fate = 0;
14298 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14299 struct mlx5_list_entry *entry)
14301 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14304 struct rte_eth_dev *dev = resource->dev;
14305 struct mlx5_priv *priv = dev->data->dev_private;
14307 if (resource->verbs_action)
14308 claim_zero(mlx5_flow_os_destroy_flow_action
14309 (resource->verbs_action));
14310 if (resource->normal_path_tbl)
14311 flow_dv_tbl_resource_release(MLX5_SH(dev),
14312 resource->normal_path_tbl);
14313 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14314 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14315 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14319 * Release an sample resource.
14322 * Pointer to Ethernet device.
14324 * Pointer to mlx5_flow_handle.
14327 * 1 while a reference on it exists, 0 when freed.
14330 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14331 struct mlx5_flow_handle *handle)
14333 struct mlx5_priv *priv = dev->data->dev_private;
14334 struct mlx5_flow_dv_sample_resource *resource;
14336 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14337 handle->dvh.rix_sample);
14340 MLX5_ASSERT(resource->verbs_action);
14341 return mlx5_list_unregister(priv->sh->sample_action_list,
14346 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14347 struct mlx5_list_entry *entry)
14349 struct mlx5_flow_dv_dest_array_resource *resource =
14350 container_of(entry, typeof(*resource), entry);
14351 struct rte_eth_dev *dev = resource->dev;
14352 struct mlx5_priv *priv = dev->data->dev_private;
14355 MLX5_ASSERT(resource->action);
14356 if (resource->action)
14357 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14358 for (; i < resource->num_of_dest; i++)
14359 flow_dv_sample_sub_actions_release(dev,
14360 &resource->sample_idx[i]);
14361 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14362 DRV_LOG(DEBUG, "destination array resource %p: removed",
14367 * Release an destination array resource.
14370 * Pointer to Ethernet device.
14372 * Pointer to mlx5_flow_handle.
14375 * 1 while a reference on it exists, 0 when freed.
14378 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14379 struct mlx5_flow_handle *handle)
14381 struct mlx5_priv *priv = dev->data->dev_private;
14382 struct mlx5_flow_dv_dest_array_resource *resource;
14384 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14385 handle->dvh.rix_dest_array);
14388 MLX5_ASSERT(resource->action);
14389 return mlx5_list_unregister(priv->sh->dest_array_list,
14394 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14396 struct mlx5_priv *priv = dev->data->dev_private;
14397 struct mlx5_dev_ctx_shared *sh = priv->sh;
14398 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14399 sh->geneve_tlv_option_resource;
14400 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14401 if (geneve_opt_resource) {
14402 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14403 __ATOMIC_RELAXED))) {
14404 claim_zero(mlx5_devx_cmd_destroy
14405 (geneve_opt_resource->obj));
14406 mlx5_free(sh->geneve_tlv_option_resource);
14407 sh->geneve_tlv_option_resource = NULL;
14410 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14414 * Remove the flow from the NIC but keeps it in memory.
14415 * Lock free, (mutex should be acquired by caller).
14418 * Pointer to Ethernet device.
14419 * @param[in, out] flow
14420 * Pointer to flow structure.
14423 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14425 struct mlx5_flow_handle *dh;
14426 uint32_t handle_idx;
14427 struct mlx5_priv *priv = dev->data->dev_private;
14431 handle_idx = flow->dev_handles;
14432 while (handle_idx) {
14433 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14437 if (dh->drv_flow) {
14438 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14439 dh->drv_flow = NULL;
14441 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14442 flow_dv_fate_resource_release(dev, dh);
14443 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14444 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14445 handle_idx = dh->next.next;
14450 * Remove the flow from the NIC and the memory.
14451 * Lock free, (mutex should be acquired by caller).
14454 * Pointer to the Ethernet device structure.
14455 * @param[in, out] flow
14456 * Pointer to flow structure.
14459 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14461 struct mlx5_flow_handle *dev_handle;
14462 struct mlx5_priv *priv = dev->data->dev_private;
14463 struct mlx5_flow_meter_info *fm = NULL;
14468 flow_dv_remove(dev, flow);
14469 if (flow->counter) {
14470 flow_dv_counter_free(dev, flow->counter);
14474 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14476 mlx5_flow_meter_detach(priv, fm);
14479 /* Keep the current age handling by default. */
14480 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14481 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14482 else if (flow->age)
14483 flow_dv_aso_age_release(dev, flow->age);
14484 if (flow->geneve_tlv_option) {
14485 flow_dv_geneve_tlv_option_resource_release(dev);
14486 flow->geneve_tlv_option = 0;
14488 while (flow->dev_handles) {
14489 uint32_t tmp_idx = flow->dev_handles;
14491 dev_handle = mlx5_ipool_get(priv->sh->ipool
14492 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14495 flow->dev_handles = dev_handle->next.next;
14496 while (dev_handle->flex_item) {
14497 int index = rte_bsf32(dev_handle->flex_item);
14499 mlx5_flex_release_index(dev, index);
14500 dev_handle->flex_item &= ~RTE_BIT32(index);
14502 if (dev_handle->dvh.matcher)
14503 flow_dv_matcher_release(dev, dev_handle);
14504 if (dev_handle->dvh.rix_sample)
14505 flow_dv_sample_resource_release(dev, dev_handle);
14506 if (dev_handle->dvh.rix_dest_array)
14507 flow_dv_dest_array_resource_release(dev, dev_handle);
14508 if (dev_handle->dvh.rix_encap_decap)
14509 flow_dv_encap_decap_resource_release(dev,
14510 dev_handle->dvh.rix_encap_decap);
14511 if (dev_handle->dvh.modify_hdr)
14512 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14513 if (dev_handle->dvh.rix_push_vlan)
14514 flow_dv_push_vlan_action_resource_release(dev,
14516 if (dev_handle->dvh.rix_tag)
14517 flow_dv_tag_release(dev,
14518 dev_handle->dvh.rix_tag);
14519 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14520 flow_dv_fate_resource_release(dev, dev_handle);
14522 srss = dev_handle->rix_srss;
14523 if (fm && dev_handle->is_meter_flow_id &&
14524 dev_handle->split_flow_id)
14525 mlx5_ipool_free(fm->flow_ipool,
14526 dev_handle->split_flow_id);
14527 else if (dev_handle->split_flow_id &&
14528 !dev_handle->is_meter_flow_id)
14529 mlx5_ipool_free(priv->sh->ipool
14530 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14531 dev_handle->split_flow_id);
14532 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14536 flow_dv_shared_rss_action_release(dev, srss);
14540 * Release array of hash RX queue objects.
14544 * Pointer to the Ethernet device structure.
14545 * @param[in, out] hrxqs
14546 * Array of hash RX queue objects.
14549 * Total number of references to hash RX queue objects in *hrxqs* array
14550 * after this operation.
14553 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14554 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14559 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14560 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14570 * Release all hash RX queue objects representing shared RSS action.
14573 * Pointer to the Ethernet device structure.
14574 * @param[in, out] action
14575 * Shared RSS action to remove hash RX queue objects from.
14578 * Total number of references to hash RX queue objects stored in *action*
14579 * after this operation.
14580 * Expected to be 0 if no external references held.
14583 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14584 struct mlx5_shared_action_rss *shared_rss)
14586 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14590 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14593 * Only one hash value is available for one L3+L4 combination:
14595 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14596 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14597 * same slot in mlx5_rss_hash_fields.
14600 * Pointer to the shared action RSS conf.
14601 * @param[in, out] hash_field
14602 * hash_field variable needed to be adjusted.
14608 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14609 uint64_t *hash_field)
14611 uint64_t rss_types = rss->origin.types;
14613 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14614 case MLX5_RSS_HASH_IPV4:
14615 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14616 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14617 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14618 *hash_field |= IBV_RX_HASH_DST_IPV4;
14619 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14620 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14622 *hash_field |= MLX5_RSS_HASH_IPV4;
14625 case MLX5_RSS_HASH_IPV6:
14626 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14627 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14628 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14629 *hash_field |= IBV_RX_HASH_DST_IPV6;
14630 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14631 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14633 *hash_field |= MLX5_RSS_HASH_IPV6;
14636 case MLX5_RSS_HASH_IPV4_UDP:
14637 /* fall-through. */
14638 case MLX5_RSS_HASH_IPV6_UDP:
14639 if (rss_types & RTE_ETH_RSS_UDP) {
14640 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14641 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14642 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14643 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14644 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14646 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14649 case MLX5_RSS_HASH_IPV4_TCP:
14650 /* fall-through. */
14651 case MLX5_RSS_HASH_IPV6_TCP:
14652 if (rss_types & RTE_ETH_RSS_TCP) {
14653 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14654 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14655 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14656 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14657 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14659 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14668 * Setup shared RSS action.
14669 * Prepare set of hash RX queue objects sufficient to handle all valid
14670 * hash_fields combinations (see enum ibv_rx_hash_fields).
14673 * Pointer to the Ethernet device structure.
14674 * @param[in] action_idx
14675 * Shared RSS action ipool index.
14676 * @param[in, out] action
14677 * Partially initialized shared RSS action.
14678 * @param[out] error
14679 * Perform verbose error reporting if not NULL. Initialized in case of
14683 * 0 on success, otherwise negative errno value.
14686 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14687 uint32_t action_idx,
14688 struct mlx5_shared_action_rss *shared_rss,
14689 struct rte_flow_error *error)
14691 struct mlx5_flow_rss_desc rss_desc = { 0 };
14695 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl,
14696 !!dev->data->dev_started)) {
14697 return rte_flow_error_set(error, rte_errno,
14698 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14699 "cannot setup indirection table");
14701 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14702 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14703 rss_desc.const_q = shared_rss->origin.queue;
14704 rss_desc.queue_num = shared_rss->origin.queue_num;
14705 /* Set non-zero value to indicate a shared RSS. */
14706 rss_desc.shared_rss = action_idx;
14707 rss_desc.ind_tbl = shared_rss->ind_tbl;
14708 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14710 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14713 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14714 if (shared_rss->origin.level > 1) {
14715 hash_fields |= IBV_RX_HASH_INNER;
14718 rss_desc.tunnel = tunnel;
14719 rss_desc.hash_fields = hash_fields;
14720 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14725 "cannot get hash queue");
14726 goto error_hrxq_new;
14728 err = __flow_dv_action_rss_hrxq_set
14729 (shared_rss, hash_fields, hrxq_idx);
14735 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14736 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true, true))
14737 shared_rss->ind_tbl = NULL;
14743 * Create shared RSS action.
14746 * Pointer to the Ethernet device structure.
14748 * Shared action configuration.
14750 * RSS action specification used to create shared action.
14751 * @param[out] error
14752 * Perform verbose error reporting if not NULL. Initialized in case of
14756 * A valid shared action ID in case of success, 0 otherwise and
14757 * rte_errno is set.
14760 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14761 const struct rte_flow_indir_action_conf *conf,
14762 const struct rte_flow_action_rss *rss,
14763 struct rte_flow_error *error)
14765 struct mlx5_priv *priv = dev->data->dev_private;
14766 struct mlx5_shared_action_rss *shared_rss = NULL;
14767 void *queue = NULL;
14768 struct rte_flow_action_rss *origin;
14769 const uint8_t *rss_key;
14770 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14773 RTE_SET_USED(conf);
14774 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14776 shared_rss = mlx5_ipool_zmalloc
14777 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14778 if (!shared_rss || !queue) {
14779 rte_flow_error_set(error, ENOMEM,
14780 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14781 "cannot allocate resource memory");
14782 goto error_rss_init;
14784 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14785 rte_flow_error_set(error, E2BIG,
14786 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14787 "rss action number out of range");
14788 goto error_rss_init;
14790 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14791 sizeof(*shared_rss->ind_tbl),
14793 if (!shared_rss->ind_tbl) {
14794 rte_flow_error_set(error, ENOMEM,
14795 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14796 "cannot allocate resource memory");
14797 goto error_rss_init;
14799 memcpy(queue, rss->queue, queue_size);
14800 shared_rss->ind_tbl->queues = queue;
14801 shared_rss->ind_tbl->queues_n = rss->queue_num;
14802 origin = &shared_rss->origin;
14803 origin->func = rss->func;
14804 origin->level = rss->level;
14805 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14806 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14807 /* NULL RSS key indicates default RSS key. */
14808 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14809 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14810 origin->key = &shared_rss->key[0];
14811 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14812 origin->queue = queue;
14813 origin->queue_num = rss->queue_num;
14814 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14815 goto error_rss_init;
14816 rte_spinlock_init(&shared_rss->action_rss_sl);
14817 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14818 rte_spinlock_lock(&priv->shared_act_sl);
14819 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14820 &priv->rss_shared_actions, idx, shared_rss, next);
14821 rte_spinlock_unlock(&priv->shared_act_sl);
14825 if (shared_rss->ind_tbl)
14826 mlx5_free(shared_rss->ind_tbl);
14827 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14836 * Destroy the shared RSS action.
14837 * Release related hash RX queue objects.
14840 * Pointer to the Ethernet device structure.
14842 * The shared RSS action object ID to be removed.
14843 * @param[out] error
14844 * Perform verbose error reporting if not NULL. Initialized in case of
14848 * 0 on success, otherwise negative errno value.
14851 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14852 struct rte_flow_error *error)
14854 struct mlx5_priv *priv = dev->data->dev_private;
14855 struct mlx5_shared_action_rss *shared_rss =
14856 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14857 uint32_t old_refcnt = 1;
14859 uint16_t *queue = NULL;
14862 return rte_flow_error_set(error, EINVAL,
14863 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14864 "invalid shared action");
14865 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14866 0, 0, __ATOMIC_ACQUIRE,
14868 return rte_flow_error_set(error, EBUSY,
14869 RTE_FLOW_ERROR_TYPE_ACTION,
14871 "shared rss has references");
14872 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14874 return rte_flow_error_set(error, EBUSY,
14875 RTE_FLOW_ERROR_TYPE_ACTION,
14877 "shared rss hrxq has references");
14878 queue = shared_rss->ind_tbl->queues;
14879 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true,
14880 !!dev->data->dev_started);
14882 return rte_flow_error_set(error, EBUSY,
14883 RTE_FLOW_ERROR_TYPE_ACTION,
14885 "shared rss indirection table has"
14888 rte_spinlock_lock(&priv->shared_act_sl);
14889 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14890 &priv->rss_shared_actions, idx, shared_rss, next);
14891 rte_spinlock_unlock(&priv->shared_act_sl);
14892 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14898 * Create indirect action, lock free,
14899 * (mutex should be acquired by caller).
14900 * Dispatcher for action type specific call.
14903 * Pointer to the Ethernet device structure.
14905 * Shared action configuration.
14906 * @param[in] action
14907 * Action specification used to create indirect action.
14908 * @param[out] error
14909 * Perform verbose error reporting if not NULL. Initialized in case of
14913 * A valid shared action handle in case of success, NULL otherwise and
14914 * rte_errno is set.
14916 static struct rte_flow_action_handle *
14917 flow_dv_action_create(struct rte_eth_dev *dev,
14918 const struct rte_flow_indir_action_conf *conf,
14919 const struct rte_flow_action *action,
14920 struct rte_flow_error *err)
14922 struct mlx5_priv *priv = dev->data->dev_private;
14923 uint32_t age_idx = 0;
14927 switch (action->type) {
14928 case RTE_FLOW_ACTION_TYPE_RSS:
14929 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14930 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14931 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14933 case RTE_FLOW_ACTION_TYPE_AGE:
14934 age_idx = flow_dv_aso_age_alloc(dev, err);
14939 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14940 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14941 flow_dv_aso_age_params_init(dev, age_idx,
14942 ((const struct rte_flow_action_age *)
14943 action->conf)->context ?
14944 ((const struct rte_flow_action_age *)
14945 action->conf)->context :
14946 (void *)(uintptr_t)idx,
14947 ((const struct rte_flow_action_age *)
14948 action->conf)->timeout);
14951 case RTE_FLOW_ACTION_TYPE_COUNT:
14952 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14953 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14954 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14956 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14957 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14959 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14962 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14963 NULL, "action type not supported");
14966 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14970 * Destroy the indirect action.
14971 * Release action related resources on the NIC and the memory.
14972 * Lock free, (mutex should be acquired by caller).
14973 * Dispatcher for action type specific call.
14976 * Pointer to the Ethernet device structure.
14977 * @param[in] handle
14978 * The indirect action object handle to be removed.
14979 * @param[out] error
14980 * Perform verbose error reporting if not NULL. Initialized in case of
14984 * 0 on success, otherwise negative errno value.
14987 flow_dv_action_destroy(struct rte_eth_dev *dev,
14988 struct rte_flow_action_handle *handle,
14989 struct rte_flow_error *error)
14991 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14992 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14993 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14994 struct mlx5_flow_counter *cnt;
14995 uint32_t no_flow_refcnt = 1;
14999 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15000 return __flow_dv_action_rss_release(dev, idx, error);
15001 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15002 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15003 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15004 &no_flow_refcnt, 1, false,
15007 return rte_flow_error_set(error, EBUSY,
15008 RTE_FLOW_ERROR_TYPE_ACTION,
15010 "Indirect count action has references");
15011 flow_dv_counter_free(dev, idx);
15013 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15014 ret = flow_dv_aso_age_release(dev, idx);
15017 * In this case, the last flow has a reference will
15018 * actually release the age action.
15020 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15021 " released with references %d.", idx, ret);
15023 case MLX5_INDIRECT_ACTION_TYPE_CT:
15024 ret = flow_dv_aso_ct_release(dev, idx, error);
15028 DRV_LOG(DEBUG, "Connection tracking object %u still "
15029 "has references %d.", idx, ret);
15032 return rte_flow_error_set(error, ENOTSUP,
15033 RTE_FLOW_ERROR_TYPE_ACTION,
15035 "action type not supported");
15040 * Updates in place shared RSS action configuration.
15043 * Pointer to the Ethernet device structure.
15045 * The shared RSS action object ID to be updated.
15046 * @param[in] action_conf
15047 * RSS action specification used to modify *shared_rss*.
15048 * @param[out] error
15049 * Perform verbose error reporting if not NULL. Initialized in case of
15053 * 0 on success, otherwise negative errno value.
15054 * @note: currently only support update of RSS queues.
15057 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15058 const struct rte_flow_action_rss *action_conf,
15059 struct rte_flow_error *error)
15061 struct mlx5_priv *priv = dev->data->dev_private;
15062 struct mlx5_shared_action_rss *shared_rss =
15063 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15065 void *queue = NULL;
15066 uint16_t *queue_old = NULL;
15067 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15068 bool dev_started = !!dev->data->dev_started;
15071 return rte_flow_error_set(error, EINVAL,
15072 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15073 "invalid shared action to update");
15074 if (priv->obj_ops.ind_table_modify == NULL)
15075 return rte_flow_error_set(error, ENOTSUP,
15076 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15077 "cannot modify indirection table");
15078 queue = mlx5_malloc(MLX5_MEM_ZERO,
15079 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15082 return rte_flow_error_set(error, ENOMEM,
15083 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15085 "cannot allocate resource memory");
15086 memcpy(queue, action_conf->queue, queue_size);
15087 MLX5_ASSERT(shared_rss->ind_tbl);
15088 rte_spinlock_lock(&shared_rss->action_rss_sl);
15089 queue_old = shared_rss->ind_tbl->queues;
15090 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15091 queue, action_conf->queue_num,
15092 true /* standalone */,
15093 dev_started /* ref_new_qs */,
15094 dev_started /* deref_old_qs */);
15097 ret = rte_flow_error_set(error, rte_errno,
15098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15099 "cannot update indirection table");
15101 mlx5_free(queue_old);
15102 shared_rss->origin.queue = queue;
15103 shared_rss->origin.queue_num = action_conf->queue_num;
15105 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15110 * Updates in place conntrack context or direction.
15111 * Context update should be synchronized.
15114 * Pointer to the Ethernet device structure.
15116 * The conntrack object ID to be updated.
15117 * @param[in] update
15118 * Pointer to the structure of information to update.
15119 * @param[out] error
15120 * Perform verbose error reporting if not NULL. Initialized in case of
15124 * 0 on success, otherwise negative errno value.
15127 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15128 const struct rte_flow_modify_conntrack *update,
15129 struct rte_flow_error *error)
15131 struct mlx5_priv *priv = dev->data->dev_private;
15132 struct mlx5_aso_ct_action *ct;
15133 const struct rte_flow_action_conntrack *new_prf;
15135 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15138 if (PORT_ID(priv) != owner)
15139 return rte_flow_error_set(error, EACCES,
15140 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15142 "CT object owned by another port");
15143 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15144 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15146 return rte_flow_error_set(error, ENOMEM,
15147 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15149 "CT object is inactive");
15150 new_prf = &update->new_ct;
15151 if (update->direction)
15152 ct->is_original = !!new_prf->is_original_dir;
15153 if (update->state) {
15154 /* Only validate the profile when it needs to be updated. */
15155 ret = mlx5_validate_action_ct(dev, new_prf, error);
15158 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15160 return rte_flow_error_set(error, EIO,
15161 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15163 "Failed to send CT context update WQE");
15164 /* Block until ready or a failure. */
15165 ret = mlx5_aso_ct_available(priv->sh, ct);
15167 rte_flow_error_set(error, rte_errno,
15168 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15170 "Timeout to get the CT update");
15176 * Updates in place shared action configuration, lock free,
15177 * (mutex should be acquired by caller).
15180 * Pointer to the Ethernet device structure.
15181 * @param[in] handle
15182 * The indirect action object handle to be updated.
15183 * @param[in] update
15184 * Action specification used to modify the action pointed by *handle*.
15185 * *update* could be of same type with the action pointed by the *handle*
15186 * handle argument, or some other structures like a wrapper, depending on
15187 * the indirect action type.
15188 * @param[out] error
15189 * Perform verbose error reporting if not NULL. Initialized in case of
15193 * 0 on success, otherwise negative errno value.
15196 flow_dv_action_update(struct rte_eth_dev *dev,
15197 struct rte_flow_action_handle *handle,
15198 const void *update,
15199 struct rte_flow_error *err)
15201 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15202 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15203 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15204 const void *action_conf;
15207 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15208 action_conf = ((const struct rte_flow_action *)update)->conf;
15209 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15210 case MLX5_INDIRECT_ACTION_TYPE_CT:
15211 return __flow_dv_action_ct_update(dev, idx, update, err);
15213 return rte_flow_error_set(err, ENOTSUP,
15214 RTE_FLOW_ERROR_TYPE_ACTION,
15216 "action type update not supported");
15221 * Destroy the meter sub policy table rules.
15222 * Lock free, (mutex should be acquired by caller).
15225 * Pointer to Ethernet device.
15226 * @param[in] sub_policy
15227 * Pointer to meter sub policy table.
15230 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15231 struct mlx5_flow_meter_sub_policy *sub_policy)
15233 struct mlx5_priv *priv = dev->data->dev_private;
15234 struct mlx5_flow_tbl_data_entry *tbl;
15235 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15236 struct mlx5_flow_meter_info *next_fm;
15237 struct mlx5_sub_policy_color_rule *color_rule;
15241 for (i = 0; i < RTE_COLORS; i++) {
15243 if (i == RTE_COLOR_GREEN && policy &&
15244 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15245 next_fm = mlx5_flow_meter_find(priv,
15246 policy->act_cnt[i].next_mtr_id, NULL);
15247 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15249 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15250 tbl = container_of(color_rule->matcher->tbl,
15251 typeof(*tbl), tbl);
15252 mlx5_list_unregister(tbl->matchers,
15253 &color_rule->matcher->entry);
15254 TAILQ_REMOVE(&sub_policy->color_rules[i],
15255 color_rule, next_port);
15256 mlx5_free(color_rule);
15258 mlx5_flow_meter_detach(priv, next_fm);
15261 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15262 if (sub_policy->rix_hrxq[i]) {
15263 if (policy && !policy->is_hierarchy)
15264 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15265 sub_policy->rix_hrxq[i] = 0;
15267 if (sub_policy->jump_tbl[i]) {
15268 flow_dv_tbl_resource_release(MLX5_SH(dev),
15269 sub_policy->jump_tbl[i]);
15270 sub_policy->jump_tbl[i] = NULL;
15273 if (sub_policy->tbl_rsc) {
15274 flow_dv_tbl_resource_release(MLX5_SH(dev),
15275 sub_policy->tbl_rsc);
15276 sub_policy->tbl_rsc = NULL;
15281 * Destroy policy rules, lock free,
15282 * (mutex should be acquired by caller).
15283 * Dispatcher for action type specific call.
15286 * Pointer to the Ethernet device structure.
15287 * @param[in] mtr_policy
15288 * Meter policy struct.
15291 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15292 struct mlx5_flow_meter_policy *mtr_policy)
15295 struct mlx5_flow_meter_sub_policy *sub_policy;
15296 uint16_t sub_policy_num;
15298 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15299 sub_policy_num = (mtr_policy->sub_policy_num >>
15300 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15301 MLX5_MTR_SUB_POLICY_NUM_MASK;
15302 for (j = 0; j < sub_policy_num; j++) {
15303 sub_policy = mtr_policy->sub_policys[i][j];
15305 __flow_dv_destroy_sub_policy_rules(dev,
15312 * Destroy policy action, lock free,
15313 * (mutex should be acquired by caller).
15314 * Dispatcher for action type specific call.
15317 * Pointer to the Ethernet device structure.
15318 * @param[in] mtr_policy
15319 * Meter policy struct.
15322 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15323 struct mlx5_flow_meter_policy *mtr_policy)
15325 struct rte_flow_action *rss_action;
15326 struct mlx5_flow_handle dev_handle;
15329 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15330 if (mtr_policy->act_cnt[i].rix_mark) {
15331 flow_dv_tag_release(dev,
15332 mtr_policy->act_cnt[i].rix_mark);
15333 mtr_policy->act_cnt[i].rix_mark = 0;
15335 if (mtr_policy->act_cnt[i].modify_hdr) {
15336 dev_handle.dvh.modify_hdr =
15337 mtr_policy->act_cnt[i].modify_hdr;
15338 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15340 switch (mtr_policy->act_cnt[i].fate_action) {
15341 case MLX5_FLOW_FATE_SHARED_RSS:
15342 rss_action = mtr_policy->act_cnt[i].rss;
15343 mlx5_free(rss_action);
15345 case MLX5_FLOW_FATE_PORT_ID:
15346 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15347 flow_dv_port_id_action_resource_release(dev,
15348 mtr_policy->act_cnt[i].rix_port_id_action);
15349 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15352 case MLX5_FLOW_FATE_DROP:
15353 case MLX5_FLOW_FATE_JUMP:
15354 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15355 mtr_policy->act_cnt[i].dr_jump_action[j] =
15359 /*Queue action do nothing*/
15363 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15364 mtr_policy->dr_drop_action[j] = NULL;
15368 * Create policy action per domain, lock free,
15369 * (mutex should be acquired by caller).
15370 * Dispatcher for action type specific call.
15373 * Pointer to the Ethernet device structure.
15374 * @param[in] mtr_policy
15375 * Meter policy struct.
15376 * @param[in] action
15377 * Action specification used to create meter actions.
15378 * @param[out] error
15379 * Perform verbose error reporting if not NULL. Initialized in case of
15383 * 0 on success, otherwise negative errno value.
15386 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15387 struct mlx5_flow_meter_policy *mtr_policy,
15388 const struct rte_flow_action *actions[RTE_COLORS],
15389 enum mlx5_meter_domain domain,
15390 struct rte_mtr_error *error)
15392 struct mlx5_priv *priv = dev->data->dev_private;
15393 struct rte_flow_error flow_err;
15394 const struct rte_flow_action *act;
15395 uint64_t action_flags;
15396 struct mlx5_flow_handle dh;
15397 struct mlx5_flow dev_flow;
15398 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15400 uint8_t egress, transfer;
15401 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15403 struct mlx5_flow_dv_modify_hdr_resource res;
15404 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15405 sizeof(struct mlx5_modification_cmd) *
15406 (MLX5_MAX_MODIFY_NUM + 1)];
15408 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15409 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
15412 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15413 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15414 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15415 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15416 memset(&port_id_action, 0,
15417 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15418 memset(mhdr_res, 0, sizeof(*mhdr_res));
15419 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15420 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15421 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15422 dev_flow.handle = &dh;
15423 dev_flow.dv.port_id_action = &port_id_action;
15424 dev_flow.external = true;
15425 for (i = 0; i < RTE_COLORS; i++) {
15426 if (i < MLX5_MTR_RTE_COLORS)
15427 act_cnt = &mtr_policy->act_cnt[i];
15428 /* Skip the color policy actions creation. */
15429 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15430 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15433 for (act = actions[i];
15434 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15435 switch (act->type) {
15436 case RTE_FLOW_ACTION_TYPE_MARK:
15438 uint32_t tag_be = mlx5_flow_mark_set
15439 (((const struct rte_flow_action_mark *)
15442 if (i >= MLX5_MTR_RTE_COLORS)
15443 return -rte_mtr_error_set(error,
15445 RTE_MTR_ERROR_TYPE_METER_POLICY,
15447 "cannot create policy "
15448 "mark action for this color");
15450 if (flow_dv_tag_resource_register(dev, tag_be,
15451 &dev_flow, &flow_err))
15452 return -rte_mtr_error_set(error,
15454 RTE_MTR_ERROR_TYPE_METER_POLICY,
15456 "cannot setup policy mark action");
15457 MLX5_ASSERT(dev_flow.dv.tag_resource);
15458 act_cnt->rix_mark =
15459 dev_flow.handle->dvh.rix_tag;
15460 action_flags |= MLX5_FLOW_ACTION_MARK;
15463 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15464 if (i >= MLX5_MTR_RTE_COLORS)
15465 return -rte_mtr_error_set(error,
15467 RTE_MTR_ERROR_TYPE_METER_POLICY,
15469 "cannot create policy "
15470 "set tag action for this color");
15471 if (flow_dv_convert_action_set_tag
15473 (const struct rte_flow_action_set_tag *)
15474 act->conf, &flow_err))
15475 return -rte_mtr_error_set(error,
15477 RTE_MTR_ERROR_TYPE_METER_POLICY,
15478 NULL, "cannot convert policy "
15480 if (!mhdr_res->actions_num)
15481 return -rte_mtr_error_set(error,
15483 RTE_MTR_ERROR_TYPE_METER_POLICY,
15484 NULL, "cannot find policy "
15486 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15488 case RTE_FLOW_ACTION_TYPE_DROP:
15490 struct mlx5_flow_mtr_mng *mtrmng =
15492 struct mlx5_flow_tbl_data_entry *tbl_data;
15495 * Create the drop table with
15496 * METER DROP level.
15498 if (!mtrmng->drop_tbl[domain]) {
15499 mtrmng->drop_tbl[domain] =
15500 flow_dv_tbl_resource_get(dev,
15501 MLX5_FLOW_TABLE_LEVEL_METER,
15502 egress, transfer, false, NULL, 0,
15503 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15504 if (!mtrmng->drop_tbl[domain])
15505 return -rte_mtr_error_set
15507 RTE_MTR_ERROR_TYPE_METER_POLICY,
15509 "Failed to create meter drop table");
15511 tbl_data = container_of
15512 (mtrmng->drop_tbl[domain],
15513 struct mlx5_flow_tbl_data_entry, tbl);
15514 if (i < MLX5_MTR_RTE_COLORS) {
15515 act_cnt->dr_jump_action[domain] =
15516 tbl_data->jump.action;
15517 act_cnt->fate_action =
15518 MLX5_FLOW_FATE_DROP;
15520 if (i == RTE_COLOR_RED)
15521 mtr_policy->dr_drop_action[domain] =
15522 tbl_data->jump.action;
15523 action_flags |= MLX5_FLOW_ACTION_DROP;
15526 case RTE_FLOW_ACTION_TYPE_QUEUE:
15528 if (i >= MLX5_MTR_RTE_COLORS)
15529 return -rte_mtr_error_set(error,
15531 RTE_MTR_ERROR_TYPE_METER_POLICY,
15532 NULL, "cannot create policy "
15533 "fate queue for this color");
15535 ((const struct rte_flow_action_queue *)
15536 (act->conf))->index;
15537 act_cnt->fate_action =
15538 MLX5_FLOW_FATE_QUEUE;
15539 dev_flow.handle->fate_action =
15540 MLX5_FLOW_FATE_QUEUE;
15541 mtr_policy->is_queue = 1;
15542 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15545 case RTE_FLOW_ACTION_TYPE_RSS:
15549 if (i >= MLX5_MTR_RTE_COLORS)
15550 return -rte_mtr_error_set(error,
15552 RTE_MTR_ERROR_TYPE_METER_POLICY,
15554 "cannot create policy "
15555 "rss action for this color");
15557 * Save RSS conf into policy struct
15558 * for translate stage.
15560 rss_size = (int)rte_flow_conv
15561 (RTE_FLOW_CONV_OP_ACTION,
15562 NULL, 0, act, &flow_err);
15564 return -rte_mtr_error_set(error,
15566 RTE_MTR_ERROR_TYPE_METER_POLICY,
15567 NULL, "Get the wrong "
15568 "rss action struct size");
15569 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15570 rss_size, 0, SOCKET_ID_ANY);
15572 return -rte_mtr_error_set(error,
15574 RTE_MTR_ERROR_TYPE_METER_POLICY,
15576 "Fail to malloc rss action memory");
15577 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15578 act_cnt->rss, rss_size,
15581 return -rte_mtr_error_set(error,
15583 RTE_MTR_ERROR_TYPE_METER_POLICY,
15584 NULL, "Fail to save "
15585 "rss action into policy struct");
15586 act_cnt->fate_action =
15587 MLX5_FLOW_FATE_SHARED_RSS;
15588 action_flags |= MLX5_FLOW_ACTION_RSS;
15591 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15592 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15594 struct mlx5_flow_dv_port_id_action_resource
15596 uint32_t port_id = 0;
15598 if (i >= MLX5_MTR_RTE_COLORS)
15599 return -rte_mtr_error_set(error,
15601 RTE_MTR_ERROR_TYPE_METER_POLICY,
15602 NULL, "cannot create policy "
15603 "port action for this color");
15604 memset(&port_id_resource, 0,
15605 sizeof(port_id_resource));
15606 if (flow_dv_translate_action_port_id(dev, act,
15607 &port_id, &flow_err))
15608 return -rte_mtr_error_set(error,
15610 RTE_MTR_ERROR_TYPE_METER_POLICY,
15611 NULL, "cannot translate "
15612 "policy port action");
15613 port_id_resource.port_id = port_id;
15614 if (flow_dv_port_id_action_resource_register
15615 (dev, &port_id_resource,
15616 &dev_flow, &flow_err))
15617 return -rte_mtr_error_set(error,
15619 RTE_MTR_ERROR_TYPE_METER_POLICY,
15620 NULL, "cannot setup "
15621 "policy port action");
15622 act_cnt->rix_port_id_action =
15623 dev_flow.handle->rix_port_id_action;
15624 act_cnt->fate_action =
15625 MLX5_FLOW_FATE_PORT_ID;
15626 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15629 case RTE_FLOW_ACTION_TYPE_JUMP:
15631 uint32_t jump_group = 0;
15632 uint32_t table = 0;
15633 struct mlx5_flow_tbl_data_entry *tbl_data;
15634 struct flow_grp_info grp_info = {
15635 .external = !!dev_flow.external,
15636 .transfer = !!transfer,
15637 .fdb_def_rule = !!priv->fdb_def_rule,
15639 .skip_scale = dev_flow.skip_scale &
15640 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15642 struct mlx5_flow_meter_sub_policy *sub_policy =
15643 mtr_policy->sub_policys[domain][0];
15645 if (i >= MLX5_MTR_RTE_COLORS)
15646 return -rte_mtr_error_set(error,
15648 RTE_MTR_ERROR_TYPE_METER_POLICY,
15650 "cannot create policy "
15651 "jump action for this color");
15653 ((const struct rte_flow_action_jump *)
15655 if (mlx5_flow_group_to_table(dev, NULL,
15658 &grp_info, &flow_err))
15659 return -rte_mtr_error_set(error,
15661 RTE_MTR_ERROR_TYPE_METER_POLICY,
15662 NULL, "cannot setup "
15663 "policy jump action");
15664 sub_policy->jump_tbl[i] =
15665 flow_dv_tbl_resource_get(dev,
15668 !!dev_flow.external,
15669 NULL, jump_group, 0,
15672 (!sub_policy->jump_tbl[i])
15673 return -rte_mtr_error_set(error,
15675 RTE_MTR_ERROR_TYPE_METER_POLICY,
15676 NULL, "cannot create jump action.");
15677 tbl_data = container_of
15678 (sub_policy->jump_tbl[i],
15679 struct mlx5_flow_tbl_data_entry, tbl);
15680 act_cnt->dr_jump_action[domain] =
15681 tbl_data->jump.action;
15682 act_cnt->fate_action =
15683 MLX5_FLOW_FATE_JUMP;
15684 action_flags |= MLX5_FLOW_ACTION_JUMP;
15688 * No need to check meter hierarchy for Y or R colors
15689 * here since it is done in the validation stage.
15691 case RTE_FLOW_ACTION_TYPE_METER:
15693 const struct rte_flow_action_meter *mtr;
15694 struct mlx5_flow_meter_info *next_fm;
15695 struct mlx5_flow_meter_policy *next_policy;
15696 struct rte_flow_action tag_action;
15697 struct mlx5_rte_flow_action_set_tag set_tag;
15698 uint32_t next_mtr_idx = 0;
15701 next_fm = mlx5_flow_meter_find(priv,
15705 return -rte_mtr_error_set(error, EINVAL,
15706 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15707 "Fail to find next meter.");
15708 if (next_fm->def_policy)
15709 return -rte_mtr_error_set(error, EINVAL,
15710 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15711 "Hierarchy only supports termination meter.");
15712 next_policy = mlx5_flow_meter_policy_find(dev,
15713 next_fm->policy_id, NULL);
15714 MLX5_ASSERT(next_policy);
15715 if (next_fm->drop_cnt) {
15718 mlx5_flow_get_reg_id(dev,
15721 (struct rte_flow_error *)error);
15722 set_tag.offset = (priv->mtr_reg_share ?
15723 MLX5_MTR_COLOR_BITS : 0);
15724 set_tag.length = (priv->mtr_reg_share ?
15725 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15727 set_tag.data = next_mtr_idx;
15729 (enum rte_flow_action_type)
15730 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15731 tag_action.conf = &set_tag;
15732 if (flow_dv_convert_action_set_reg
15733 (mhdr_res, &tag_action,
15734 (struct rte_flow_error *)error))
15737 MLX5_FLOW_ACTION_SET_TAG;
15739 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15740 act_cnt->next_mtr_id = next_fm->meter_id;
15741 act_cnt->next_sub_policy = NULL;
15742 mtr_policy->is_hierarchy = 1;
15743 mtr_policy->dev = next_policy->dev;
15745 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15749 return -rte_mtr_error_set(error, ENOTSUP,
15750 RTE_MTR_ERROR_TYPE_METER_POLICY,
15751 NULL, "action type not supported");
15753 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15754 /* create modify action if needed. */
15755 dev_flow.dv.group = 1;
15756 if (flow_dv_modify_hdr_resource_register
15757 (dev, mhdr_res, &dev_flow, &flow_err))
15758 return -rte_mtr_error_set(error,
15760 RTE_MTR_ERROR_TYPE_METER_POLICY,
15761 NULL, "cannot register policy "
15763 act_cnt->modify_hdr =
15764 dev_flow.handle->dvh.modify_hdr;
15772 * Create policy action per domain, lock free,
15773 * (mutex should be acquired by caller).
15774 * Dispatcher for action type specific call.
15777 * Pointer to the Ethernet device structure.
15778 * @param[in] mtr_policy
15779 * Meter policy struct.
15780 * @param[in] action
15781 * Action specification used to create meter actions.
15782 * @param[out] error
15783 * Perform verbose error reporting if not NULL. Initialized in case of
15787 * 0 on success, otherwise negative errno value.
15790 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15791 struct mlx5_flow_meter_policy *mtr_policy,
15792 const struct rte_flow_action *actions[RTE_COLORS],
15793 struct rte_mtr_error *error)
15796 uint16_t sub_policy_num;
15798 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15799 sub_policy_num = (mtr_policy->sub_policy_num >>
15800 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15801 MLX5_MTR_SUB_POLICY_NUM_MASK;
15802 if (sub_policy_num) {
15803 ret = __flow_dv_create_domain_policy_acts(dev,
15804 mtr_policy, actions,
15805 (enum mlx5_meter_domain)i, error);
15806 /* Cleaning resource is done in the caller level. */
15815 * Query a DV flow rule for its statistics via DevX.
15818 * Pointer to Ethernet device.
15819 * @param[in] cnt_idx
15820 * Index to the flow counter.
15822 * Data retrieved by the query.
15823 * @param[out] error
15824 * Perform verbose error reporting if not NULL.
15827 * 0 on success, a negative errno value otherwise and rte_errno is set.
15830 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15831 struct rte_flow_error *error)
15833 struct mlx5_priv *priv = dev->data->dev_private;
15834 struct rte_flow_query_count *qc = data;
15836 if (!priv->sh->devx)
15837 return rte_flow_error_set(error, ENOTSUP,
15838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15840 "counters are not supported");
15842 uint64_t pkts, bytes;
15843 struct mlx5_flow_counter *cnt;
15844 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15847 return rte_flow_error_set(error, -err,
15848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15849 NULL, "cannot read counters");
15850 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15853 qc->hits = pkts - cnt->hits;
15854 qc->bytes = bytes - cnt->bytes;
15857 cnt->bytes = bytes;
15861 return rte_flow_error_set(error, EINVAL,
15862 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15864 "counters are not available");
15869 * Query counter's action pointer for a DV flow rule via DevX.
15872 * Pointer to Ethernet device.
15873 * @param[in] cnt_idx
15874 * Index to the flow counter.
15875 * @param[out] action_ptr
15876 * Action pointer for counter.
15877 * @param[out] error
15878 * Perform verbose error reporting if not NULL.
15881 * 0 on success, a negative errno value otherwise and rte_errno is set.
15884 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15885 void **action_ptr, struct rte_flow_error *error)
15887 struct mlx5_priv *priv = dev->data->dev_private;
15889 if (!priv->sh->devx || !action_ptr)
15890 return rte_flow_error_set(error, ENOTSUP,
15891 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15893 "counters are not supported");
15896 struct mlx5_flow_counter *cnt = NULL;
15897 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15899 *action_ptr = cnt->action;
15903 return rte_flow_error_set(error, EINVAL,
15904 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15906 "counters are not available");
15910 flow_dv_action_query(struct rte_eth_dev *dev,
15911 const struct rte_flow_action_handle *handle, void *data,
15912 struct rte_flow_error *error)
15914 struct mlx5_age_param *age_param;
15915 struct rte_flow_query_age *resp;
15916 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15917 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15918 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15919 struct mlx5_priv *priv = dev->data->dev_private;
15920 struct mlx5_aso_ct_action *ct;
15925 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15926 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15928 resp->aged = __atomic_load_n(&age_param->state,
15929 __ATOMIC_RELAXED) == AGE_TMOUT ?
15931 resp->sec_since_last_hit_valid = !resp->aged;
15932 if (resp->sec_since_last_hit_valid)
15933 resp->sec_since_last_hit = __atomic_load_n
15934 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15936 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15937 return flow_dv_query_count(dev, idx, data, error);
15938 case MLX5_INDIRECT_ACTION_TYPE_CT:
15939 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15940 if (owner != PORT_ID(priv))
15941 return rte_flow_error_set(error, EACCES,
15942 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15944 "CT object owned by another port");
15945 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15946 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15949 return rte_flow_error_set(error, EFAULT,
15950 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15952 "CT object is inactive");
15953 ((struct rte_flow_action_conntrack *)data)->peer_port =
15955 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15957 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15958 return rte_flow_error_set(error, EIO,
15959 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15961 "Failed to query CT context");
15964 return rte_flow_error_set(error, ENOTSUP,
15965 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15966 "action type query not supported");
15971 * Query a flow rule AGE action for aging information.
15974 * Pointer to Ethernet device.
15976 * Pointer to the sub flow.
15978 * data retrieved by the query.
15979 * @param[out] error
15980 * Perform verbose error reporting if not NULL.
15983 * 0 on success, a negative errno value otherwise and rte_errno is set.
15986 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15987 void *data, struct rte_flow_error *error)
15989 struct rte_flow_query_age *resp = data;
15990 struct mlx5_age_param *age_param;
15993 struct mlx5_aso_age_action *act =
15994 flow_aso_age_get_by_idx(dev, flow->age);
15996 age_param = &act->age_params;
15997 } else if (flow->counter) {
15998 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16000 if (!age_param || !age_param->timeout)
16001 return rte_flow_error_set
16003 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16004 NULL, "cannot read age data");
16006 return rte_flow_error_set(error, EINVAL,
16007 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16008 NULL, "age data not available");
16010 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16012 resp->sec_since_last_hit_valid = !resp->aged;
16013 if (resp->sec_since_last_hit_valid)
16014 resp->sec_since_last_hit = __atomic_load_n
16015 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16022 * @see rte_flow_query()
16023 * @see rte_flow_ops
16026 flow_dv_query(struct rte_eth_dev *dev,
16027 struct rte_flow *flow __rte_unused,
16028 const struct rte_flow_action *actions __rte_unused,
16029 void *data __rte_unused,
16030 struct rte_flow_error *error __rte_unused)
16034 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16035 switch (actions->type) {
16036 case RTE_FLOW_ACTION_TYPE_VOID:
16038 case RTE_FLOW_ACTION_TYPE_COUNT:
16039 ret = flow_dv_query_count(dev, flow->counter, data,
16042 case RTE_FLOW_ACTION_TYPE_AGE:
16043 ret = flow_dv_query_age(dev, flow, data, error);
16046 return rte_flow_error_set(error, ENOTSUP,
16047 RTE_FLOW_ERROR_TYPE_ACTION,
16049 "action not supported");
16056 * Destroy the meter table set.
16057 * Lock free, (mutex should be acquired by caller).
16060 * Pointer to Ethernet device.
16062 * Meter information table.
16065 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16066 struct mlx5_flow_meter_info *fm)
16068 struct mlx5_priv *priv = dev->data->dev_private;
16071 if (!fm || !priv->config.dv_flow_en)
16073 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16074 if (fm->drop_rule[i]) {
16075 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16076 fm->drop_rule[i] = NULL;
16082 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16084 struct mlx5_priv *priv = dev->data->dev_private;
16085 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16086 struct mlx5_flow_tbl_data_entry *tbl;
16089 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16090 if (mtrmng->def_rule[i]) {
16091 claim_zero(mlx5_flow_os_destroy_flow
16092 (mtrmng->def_rule[i]));
16093 mtrmng->def_rule[i] = NULL;
16095 if (mtrmng->def_matcher[i]) {
16096 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16097 struct mlx5_flow_tbl_data_entry, tbl);
16098 mlx5_list_unregister(tbl->matchers,
16099 &mtrmng->def_matcher[i]->entry);
16100 mtrmng->def_matcher[i] = NULL;
16102 for (j = 0; j < MLX5_REG_BITS; j++) {
16103 if (mtrmng->drop_matcher[i][j]) {
16105 container_of(mtrmng->drop_matcher[i][j]->tbl,
16106 struct mlx5_flow_tbl_data_entry,
16108 mlx5_list_unregister(tbl->matchers,
16109 &mtrmng->drop_matcher[i][j]->entry);
16110 mtrmng->drop_matcher[i][j] = NULL;
16113 if (mtrmng->drop_tbl[i]) {
16114 flow_dv_tbl_resource_release(MLX5_SH(dev),
16115 mtrmng->drop_tbl[i]);
16116 mtrmng->drop_tbl[i] = NULL;
16121 /* Number of meter flow actions, count and jump or count and drop. */
16122 #define METER_ACTIONS 2
16125 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16126 enum mlx5_meter_domain domain)
16128 struct mlx5_priv *priv = dev->data->dev_private;
16129 struct mlx5_flow_meter_def_policy *def_policy =
16130 priv->sh->mtrmng->def_policy[domain];
16132 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16133 mlx5_free(def_policy);
16134 priv->sh->mtrmng->def_policy[domain] = NULL;
16138 * Destroy the default policy table set.
16141 * Pointer to Ethernet device.
16144 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16146 struct mlx5_priv *priv = dev->data->dev_private;
16149 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16150 if (priv->sh->mtrmng->def_policy[i])
16151 __flow_dv_destroy_domain_def_policy(dev,
16152 (enum mlx5_meter_domain)i);
16153 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16157 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16158 uint32_t color_reg_c_idx,
16159 enum rte_color color, void *matcher_object,
16160 int actions_n, void *actions,
16161 bool match_src_port, const struct rte_flow_item *item,
16162 void **rule, const struct rte_flow_attr *attr)
16165 struct mlx5_flow_dv_match_params value = {
16166 .size = sizeof(value.buf),
16168 struct mlx5_flow_dv_match_params matcher = {
16169 .size = sizeof(matcher.buf),
16171 struct mlx5_priv *priv = dev->data->dev_private;
16174 if (match_src_port && (priv->representor || priv->master)) {
16175 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16176 value.buf, item, attr)) {
16177 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16178 " value with port.", color);
16182 flow_dv_match_meta_reg(matcher.buf, value.buf,
16183 (enum modify_reg)color_reg_c_idx,
16184 rte_col_2_mlx5_col(color), UINT32_MAX);
16185 misc_mask = flow_dv_matcher_enable(value.buf);
16186 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16187 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16188 actions_n, actions, rule);
16190 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16197 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16198 uint32_t color_reg_c_idx,
16200 struct mlx5_flow_meter_sub_policy *sub_policy,
16201 const struct rte_flow_attr *attr,
16202 bool match_src_port,
16203 const struct rte_flow_item *item,
16204 struct mlx5_flow_dv_matcher **policy_matcher,
16205 struct rte_flow_error *error)
16207 struct mlx5_list_entry *entry;
16208 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16209 struct mlx5_flow_dv_matcher matcher = {
16211 .size = sizeof(matcher.mask.buf),
16215 struct mlx5_flow_dv_match_params value = {
16216 .size = sizeof(value.buf),
16218 struct mlx5_flow_cb_ctx ctx = {
16222 struct mlx5_flow_tbl_data_entry *tbl_data;
16223 struct mlx5_priv *priv = dev->data->dev_private;
16224 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16226 if (match_src_port && (priv->representor || priv->master)) {
16227 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16228 value.buf, item, attr)) {
16229 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16230 " with port.", priority);
16234 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16235 if (priority < RTE_COLOR_RED)
16236 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16237 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16238 matcher.priority = priority;
16239 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16240 matcher.mask.size);
16241 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16243 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16247 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16252 * Create the policy rules per domain.
16255 * Pointer to Ethernet device.
16256 * @param[in] sub_policy
16257 * Pointer to sub policy table..
16258 * @param[in] egress
16259 * Direction of the table.
16260 * @param[in] transfer
16261 * E-Switch or NIC flow.
16263 * Pointer to policy action list per color.
16266 * 0 on success, -1 otherwise.
16269 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16270 struct mlx5_flow_meter_sub_policy *sub_policy,
16271 uint8_t egress, uint8_t transfer, bool match_src_port,
16272 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16274 struct mlx5_priv *priv = dev->data->dev_private;
16275 struct rte_flow_error flow_err;
16276 uint32_t color_reg_c_idx;
16277 struct rte_flow_attr attr = {
16278 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16281 .egress = !!egress,
16282 .transfer = !!transfer,
16286 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16287 struct mlx5_sub_policy_color_rule *color_rule;
16289 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16293 /* Create policy table with POLICY level. */
16294 if (!sub_policy->tbl_rsc)
16295 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16296 MLX5_FLOW_TABLE_LEVEL_POLICY,
16297 egress, transfer, false, NULL, 0, 0,
16298 sub_policy->idx, &flow_err);
16299 if (!sub_policy->tbl_rsc) {
16301 "Failed to create meter sub policy table.");
16304 /* Prepare matchers. */
16305 color_reg_c_idx = ret;
16306 for (i = 0; i < RTE_COLORS; i++) {
16307 TAILQ_INIT(&sub_policy->color_rules[i]);
16308 if (!acts[i].actions_n)
16310 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16311 sizeof(struct mlx5_sub_policy_color_rule),
16314 DRV_LOG(ERR, "No memory to create color rule.");
16317 tmp_rules[i] = color_rule;
16318 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16319 color_rule, next_port);
16320 color_rule->src_port = priv->representor_id;
16323 /* Create matchers for colors. */
16324 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16325 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16326 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16327 &attr, svport_match, NULL,
16328 &color_rule->matcher, &flow_err)) {
16329 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16332 /* Create flow, matching color. */
16333 if (__flow_dv_create_policy_flow(dev,
16334 color_reg_c_idx, (enum rte_color)i,
16335 color_rule->matcher->matcher_object,
16336 acts[i].actions_n, acts[i].dv_actions,
16337 svport_match, NULL, &color_rule->rule,
16339 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16345 /* All the policy rules will be cleared. */
16347 color_rule = tmp_rules[i];
16349 if (color_rule->rule)
16350 mlx5_flow_os_destroy_flow(color_rule->rule);
16351 if (color_rule->matcher) {
16352 struct mlx5_flow_tbl_data_entry *tbl =
16353 container_of(color_rule->matcher->tbl,
16354 typeof(*tbl), tbl);
16355 mlx5_list_unregister(tbl->matchers,
16356 &color_rule->matcher->entry);
16358 TAILQ_REMOVE(&sub_policy->color_rules[i],
16359 color_rule, next_port);
16360 mlx5_free(color_rule);
16367 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16368 struct mlx5_flow_meter_policy *mtr_policy,
16369 struct mlx5_flow_meter_sub_policy *sub_policy,
16372 struct mlx5_priv *priv = dev->data->dev_private;
16373 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16374 struct mlx5_flow_dv_tag_resource *tag;
16375 struct mlx5_flow_dv_port_id_action_resource *port_action;
16376 struct mlx5_hrxq *hrxq;
16377 struct mlx5_flow_meter_info *next_fm = NULL;
16378 struct mlx5_flow_meter_policy *next_policy;
16379 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16380 struct mlx5_flow_tbl_data_entry *tbl_data;
16381 struct rte_flow_error error;
16382 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16383 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16384 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16385 bool match_src_port = false;
16388 /* If RSS or Queue, no previous actions / rules is created. */
16389 for (i = 0; i < RTE_COLORS; i++) {
16390 acts[i].actions_n = 0;
16391 if (i == RTE_COLOR_RED) {
16392 /* Only support drop on red. */
16393 acts[i].dv_actions[0] =
16394 mtr_policy->dr_drop_action[domain];
16395 acts[i].actions_n = 1;
16398 if (i == RTE_COLOR_GREEN &&
16399 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16400 struct rte_flow_attr attr = {
16401 .transfer = transfer
16404 next_fm = mlx5_flow_meter_find(priv,
16405 mtr_policy->act_cnt[i].next_mtr_id,
16409 "Failed to get next hierarchy meter.");
16412 if (mlx5_flow_meter_attach(priv, next_fm,
16414 DRV_LOG(ERR, "%s", error.message);
16418 /* Meter action must be the first for TX. */
16420 acts[i].dv_actions[acts[i].actions_n] =
16421 next_fm->meter_action;
16422 acts[i].actions_n++;
16425 if (mtr_policy->act_cnt[i].rix_mark) {
16426 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16427 mtr_policy->act_cnt[i].rix_mark);
16429 DRV_LOG(ERR, "Failed to find "
16430 "mark action for policy.");
16433 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16434 acts[i].actions_n++;
16436 if (mtr_policy->act_cnt[i].modify_hdr) {
16437 acts[i].dv_actions[acts[i].actions_n] =
16438 mtr_policy->act_cnt[i].modify_hdr->action;
16439 acts[i].actions_n++;
16441 if (mtr_policy->act_cnt[i].fate_action) {
16442 switch (mtr_policy->act_cnt[i].fate_action) {
16443 case MLX5_FLOW_FATE_PORT_ID:
16444 port_action = mlx5_ipool_get
16445 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16446 mtr_policy->act_cnt[i].rix_port_id_action);
16447 if (!port_action) {
16448 DRV_LOG(ERR, "Failed to find "
16449 "port action for policy.");
16452 acts[i].dv_actions[acts[i].actions_n] =
16453 port_action->action;
16454 acts[i].actions_n++;
16455 mtr_policy->dev = dev;
16456 match_src_port = true;
16458 case MLX5_FLOW_FATE_DROP:
16459 case MLX5_FLOW_FATE_JUMP:
16460 acts[i].dv_actions[acts[i].actions_n] =
16461 mtr_policy->act_cnt[i].dr_jump_action[domain];
16462 acts[i].actions_n++;
16464 case MLX5_FLOW_FATE_SHARED_RSS:
16465 case MLX5_FLOW_FATE_QUEUE:
16466 hrxq = mlx5_ipool_get
16467 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16468 sub_policy->rix_hrxq[i]);
16470 DRV_LOG(ERR, "Failed to find "
16471 "queue action for policy.");
16474 acts[i].dv_actions[acts[i].actions_n] =
16476 acts[i].actions_n++;
16478 case MLX5_FLOW_FATE_MTR:
16481 "No next hierarchy meter.");
16485 acts[i].dv_actions[acts[i].actions_n] =
16486 next_fm->meter_action;
16487 acts[i].actions_n++;
16489 if (mtr_policy->act_cnt[i].next_sub_policy) {
16491 mtr_policy->act_cnt[i].next_sub_policy;
16494 mlx5_flow_meter_policy_find(dev,
16495 next_fm->policy_id, NULL);
16496 MLX5_ASSERT(next_policy);
16498 next_policy->sub_policys[domain][0];
16501 container_of(next_sub_policy->tbl_rsc,
16502 struct mlx5_flow_tbl_data_entry, tbl);
16503 acts[i].dv_actions[acts[i].actions_n++] =
16504 tbl_data->jump.action;
16505 if (mtr_policy->act_cnt[i].modify_hdr)
16506 match_src_port = !!transfer;
16509 /*Queue action do nothing*/
16514 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16515 egress, transfer, match_src_port, acts)) {
16517 "Failed to create policy rules per domain.");
16523 mlx5_flow_meter_detach(priv, next_fm);
16528 * Create the policy rules.
16531 * Pointer to Ethernet device.
16532 * @param[in,out] mtr_policy
16533 * Pointer to meter policy table.
16536 * 0 on success, -1 otherwise.
16539 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16540 struct mlx5_flow_meter_policy *mtr_policy)
16543 uint16_t sub_policy_num;
16545 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16546 sub_policy_num = (mtr_policy->sub_policy_num >>
16547 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16548 MLX5_MTR_SUB_POLICY_NUM_MASK;
16549 if (!sub_policy_num)
16551 /* Prepare actions list and create policy rules. */
16552 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16553 mtr_policy->sub_policys[i][0], i)) {
16554 DRV_LOG(ERR, "Failed to create policy action "
16555 "list per domain.");
16563 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16565 struct mlx5_priv *priv = dev->data->dev_private;
16566 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16567 struct mlx5_flow_meter_def_policy *def_policy;
16568 struct mlx5_flow_tbl_resource *jump_tbl;
16569 struct mlx5_flow_tbl_data_entry *tbl_data;
16570 uint8_t egress, transfer;
16571 struct rte_flow_error error;
16572 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16575 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16576 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16577 def_policy = mtrmng->def_policy[domain];
16579 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16580 sizeof(struct mlx5_flow_meter_def_policy),
16581 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16583 DRV_LOG(ERR, "Failed to alloc default policy table.");
16584 goto def_policy_error;
16586 mtrmng->def_policy[domain] = def_policy;
16587 /* Create the meter suffix table with SUFFIX level. */
16588 jump_tbl = flow_dv_tbl_resource_get(dev,
16589 MLX5_FLOW_TABLE_LEVEL_METER,
16590 egress, transfer, false, NULL, 0,
16591 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16594 "Failed to create meter suffix table.");
16595 goto def_policy_error;
16597 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16598 tbl_data = container_of(jump_tbl,
16599 struct mlx5_flow_tbl_data_entry, tbl);
16600 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16601 tbl_data->jump.action;
16602 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16603 acts[RTE_COLOR_GREEN].actions_n = 1;
16605 * YELLOW has the same default policy as GREEN does.
16606 * G & Y share the same table and action. The 2nd time of table
16607 * resource getting is just to update the reference count for
16608 * the releasing stage.
16610 jump_tbl = flow_dv_tbl_resource_get(dev,
16611 MLX5_FLOW_TABLE_LEVEL_METER,
16612 egress, transfer, false, NULL, 0,
16613 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16616 "Failed to get meter suffix table.");
16617 goto def_policy_error;
16619 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16620 tbl_data = container_of(jump_tbl,
16621 struct mlx5_flow_tbl_data_entry, tbl);
16622 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16623 tbl_data->jump.action;
16624 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16625 acts[RTE_COLOR_YELLOW].actions_n = 1;
16626 /* Create jump action to the drop table. */
16627 if (!mtrmng->drop_tbl[domain]) {
16628 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16629 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16630 egress, transfer, false, NULL, 0,
16631 0, MLX5_MTR_TABLE_ID_DROP, &error);
16632 if (!mtrmng->drop_tbl[domain]) {
16633 DRV_LOG(ERR, "Failed to create meter "
16634 "drop table for default policy.");
16635 goto def_policy_error;
16638 /* all RED: unique Drop table for jump action. */
16639 tbl_data = container_of(mtrmng->drop_tbl[domain],
16640 struct mlx5_flow_tbl_data_entry, tbl);
16641 def_policy->dr_jump_action[RTE_COLOR_RED] =
16642 tbl_data->jump.action;
16643 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16644 acts[RTE_COLOR_RED].actions_n = 1;
16645 /* Create default policy rules. */
16646 ret = __flow_dv_create_domain_policy_rules(dev,
16647 &def_policy->sub_policy,
16648 egress, transfer, false, acts);
16650 DRV_LOG(ERR, "Failed to create default policy rules.");
16651 goto def_policy_error;
16656 __flow_dv_destroy_domain_def_policy(dev,
16657 (enum mlx5_meter_domain)domain);
16662 * Create the default policy table set.
16665 * Pointer to Ethernet device.
16667 * 0 on success, -1 otherwise.
16670 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16672 struct mlx5_priv *priv = dev->data->dev_private;
16675 /* Non-termination policy table. */
16676 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16677 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16679 if (__flow_dv_create_domain_def_policy(dev, i)) {
16680 DRV_LOG(ERR, "Failed to create default policy");
16681 /* Rollback the created default policies for others. */
16682 flow_dv_destroy_def_policy(dev);
16690 * Create the needed meter tables.
16691 * Lock free, (mutex should be acquired by caller).
16694 * Pointer to Ethernet device.
16696 * Meter information table.
16697 * @param[in] mtr_idx
16699 * @param[in] domain_bitmap
16702 * 0 on success, -1 otherwise.
16705 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16706 struct mlx5_flow_meter_info *fm,
16708 uint8_t domain_bitmap)
16710 struct mlx5_priv *priv = dev->data->dev_private;
16711 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16712 struct rte_flow_error error;
16713 struct mlx5_flow_tbl_data_entry *tbl_data;
16714 uint8_t egress, transfer;
16715 void *actions[METER_ACTIONS];
16716 int domain, ret, i;
16717 struct mlx5_flow_counter *cnt;
16718 struct mlx5_flow_dv_match_params value = {
16719 .size = sizeof(value.buf),
16721 struct mlx5_flow_dv_match_params matcher_para = {
16722 .size = sizeof(matcher_para.buf),
16724 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16726 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16727 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16728 struct mlx5_list_entry *entry;
16729 struct mlx5_flow_dv_matcher matcher = {
16731 .size = sizeof(matcher.mask.buf),
16734 struct mlx5_flow_dv_matcher *drop_matcher;
16735 struct mlx5_flow_cb_ctx ctx = {
16741 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16742 rte_errno = ENOTSUP;
16745 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16746 if (!(domain_bitmap & (1 << domain)) ||
16747 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16749 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16750 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16751 /* Create the drop table with METER DROP level. */
16752 if (!mtrmng->drop_tbl[domain]) {
16753 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16754 MLX5_FLOW_TABLE_LEVEL_METER,
16755 egress, transfer, false, NULL, 0,
16756 0, MLX5_MTR_TABLE_ID_DROP, &error);
16757 if (!mtrmng->drop_tbl[domain]) {
16758 DRV_LOG(ERR, "Failed to create meter drop table.");
16762 /* Create default matcher in drop table. */
16763 matcher.tbl = mtrmng->drop_tbl[domain],
16764 tbl_data = container_of(mtrmng->drop_tbl[domain],
16765 struct mlx5_flow_tbl_data_entry, tbl);
16766 if (!mtrmng->def_matcher[domain]) {
16767 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16768 (enum modify_reg)mtr_id_reg_c,
16770 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16771 matcher.crc = rte_raw_cksum
16772 ((const void *)matcher.mask.buf,
16773 matcher.mask.size);
16774 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16776 DRV_LOG(ERR, "Failed to register meter "
16777 "drop default matcher.");
16780 mtrmng->def_matcher[domain] = container_of(entry,
16781 struct mlx5_flow_dv_matcher, entry);
16783 /* Create default rule in drop table. */
16784 if (!mtrmng->def_rule[domain]) {
16786 actions[i++] = priv->sh->dr_drop_action;
16787 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16788 (enum modify_reg)mtr_id_reg_c, 0, 0);
16789 misc_mask = flow_dv_matcher_enable(value.buf);
16790 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16791 ret = mlx5_flow_os_create_flow
16792 (mtrmng->def_matcher[domain]->matcher_object,
16793 (void *)&value, i, actions,
16794 &mtrmng->def_rule[domain]);
16796 DRV_LOG(ERR, "Failed to create meter "
16797 "default drop rule for drop table.");
16803 MLX5_ASSERT(mtrmng->max_mtr_bits);
16804 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16805 /* Create matchers for Drop. */
16806 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16807 (enum modify_reg)mtr_id_reg_c, 0,
16808 (mtr_id_mask << mtr_id_offset));
16809 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16810 matcher.crc = rte_raw_cksum
16811 ((const void *)matcher.mask.buf,
16812 matcher.mask.size);
16813 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16816 "Failed to register meter drop matcher.");
16819 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16820 container_of(entry, struct mlx5_flow_dv_matcher,
16824 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16825 /* Create drop rule, matching meter_id only. */
16826 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16827 (enum modify_reg)mtr_id_reg_c,
16828 (mtr_idx << mtr_id_offset), UINT32_MAX);
16830 cnt = flow_dv_counter_get_by_idx(dev,
16831 fm->drop_cnt, NULL);
16832 actions[i++] = cnt->action;
16833 actions[i++] = priv->sh->dr_drop_action;
16834 misc_mask = flow_dv_matcher_enable(value.buf);
16835 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16836 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16837 (void *)&value, i, actions,
16838 &fm->drop_rule[domain]);
16840 DRV_LOG(ERR, "Failed to create meter "
16841 "drop rule for drop table.");
16847 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16848 if (fm->drop_rule[i]) {
16849 claim_zero(mlx5_flow_os_destroy_flow
16850 (fm->drop_rule[i]));
16851 fm->drop_rule[i] = NULL;
16857 static struct mlx5_flow_meter_sub_policy *
16858 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16859 struct mlx5_flow_meter_policy *mtr_policy,
16860 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16861 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16864 struct mlx5_priv *priv = dev->data->dev_private;
16865 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16866 uint32_t sub_policy_idx = 0;
16867 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16869 struct mlx5_hrxq *hrxq;
16870 struct mlx5_flow_handle dh;
16871 struct mlx5_meter_policy_action_container *act_cnt;
16872 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16873 uint16_t sub_policy_num;
16874 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
16877 rte_spinlock_lock(&mtr_policy->sl);
16878 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16881 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16882 if (!hrxq_idx[i]) {
16883 rte_spinlock_unlock(&mtr_policy->sl);
16887 sub_policy_num = (mtr_policy->sub_policy_num >>
16888 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16889 MLX5_MTR_SUB_POLICY_NUM_MASK;
16890 for (j = 0; j < sub_policy_num; j++) {
16891 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16894 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16897 if (i >= MLX5_MTR_RTE_COLORS) {
16899 * Found the sub policy table with
16900 * the same queue per color.
16902 rte_spinlock_unlock(&mtr_policy->sl);
16903 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16904 mlx5_hrxq_release(dev, hrxq_idx[i]);
16906 return mtr_policy->sub_policys[domain][j];
16909 /* Create sub policy. */
16910 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16911 /* Reuse the first pre-allocated sub_policy. */
16912 sub_policy = mtr_policy->sub_policys[domain][0];
16913 sub_policy_idx = sub_policy->idx;
16915 sub_policy = mlx5_ipool_zmalloc
16916 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16919 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16920 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16921 mlx5_hrxq_release(dev, hrxq_idx[i]);
16922 goto rss_sub_policy_error;
16924 sub_policy->idx = sub_policy_idx;
16925 sub_policy->main_policy = mtr_policy;
16927 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16930 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16931 if (mtr_policy->is_hierarchy) {
16932 act_cnt = &mtr_policy->act_cnt[i];
16933 act_cnt->next_sub_policy = next_sub_policy;
16934 mlx5_hrxq_release(dev, hrxq_idx[i]);
16937 * Overwrite the last action from
16938 * RSS action to Queue action.
16940 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16943 DRV_LOG(ERR, "Failed to get policy hrxq");
16944 goto rss_sub_policy_error;
16946 act_cnt = &mtr_policy->act_cnt[i];
16947 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16948 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16949 if (act_cnt->rix_mark)
16951 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16952 dh.rix_hrxq = hrxq_idx[i];
16953 flow_drv_rxq_flags_set(dev, &dh);
16957 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16958 sub_policy, domain)) {
16959 DRV_LOG(ERR, "Failed to create policy "
16960 "rules for ingress domain.");
16961 goto rss_sub_policy_error;
16963 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16964 i = (mtr_policy->sub_policy_num >>
16965 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16966 MLX5_MTR_SUB_POLICY_NUM_MASK;
16967 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16968 DRV_LOG(ERR, "No free sub-policy slot.");
16969 goto rss_sub_policy_error;
16971 mtr_policy->sub_policys[domain][i] = sub_policy;
16973 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16974 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16975 mtr_policy->sub_policy_num |=
16976 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16977 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16979 rte_spinlock_unlock(&mtr_policy->sl);
16982 rss_sub_policy_error:
16984 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16985 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16986 i = (mtr_policy->sub_policy_num >>
16987 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16988 MLX5_MTR_SUB_POLICY_NUM_MASK;
16989 mtr_policy->sub_policys[domain][i] = NULL;
16990 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16994 rte_spinlock_unlock(&mtr_policy->sl);
16999 * Find the policy table for prefix table with RSS.
17002 * Pointer to Ethernet device.
17003 * @param[in] mtr_policy
17004 * Pointer to meter policy table.
17005 * @param[in] rss_desc
17006 * Pointer to rss_desc
17008 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17010 static struct mlx5_flow_meter_sub_policy *
17011 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17012 struct mlx5_flow_meter_policy *mtr_policy,
17013 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17015 struct mlx5_priv *priv = dev->data->dev_private;
17016 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17017 struct mlx5_flow_meter_info *next_fm;
17018 struct mlx5_flow_meter_policy *next_policy;
17019 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17020 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17021 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17022 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17023 bool reuse_sub_policy;
17028 /* Iterate hierarchy to get all policies in this hierarchy. */
17029 policies[i++] = mtr_policy;
17030 if (!mtr_policy->is_hierarchy)
17032 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17033 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17036 next_fm = mlx5_flow_meter_find(priv,
17037 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17039 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17043 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17045 MLX5_ASSERT(next_policy);
17046 mtr_policy = next_policy;
17050 * From last policy to the first one in hierarchy,
17051 * create / get the sub policy for each of them.
17053 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17057 &reuse_sub_policy);
17059 DRV_LOG(ERR, "Failed to get the sub policy.");
17062 if (!reuse_sub_policy)
17063 sub_policies[j++] = sub_policy;
17064 next_sub_policy = sub_policy;
17069 uint16_t sub_policy_num;
17071 sub_policy = sub_policies[--j];
17072 mtr_policy = sub_policy->main_policy;
17073 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17074 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17075 sub_policy_num = (mtr_policy->sub_policy_num >>
17076 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17077 MLX5_MTR_SUB_POLICY_NUM_MASK;
17078 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17081 mtr_policy->sub_policy_num &=
17082 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17083 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17084 mtr_policy->sub_policy_num |=
17085 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17086 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17087 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17095 * Create the sub policy tag rule for all meters in hierarchy.
17098 * Pointer to Ethernet device.
17100 * Meter information table.
17101 * @param[in] src_port
17102 * The src port this extra rule should use.
17104 * The src port match item.
17105 * @param[out] error
17106 * Perform verbose error reporting if not NULL.
17108 * 0 on success, a negative errno value otherwise and rte_errno is set.
17111 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17112 struct mlx5_flow_meter_info *fm,
17114 const struct rte_flow_item *item,
17115 struct rte_flow_error *error)
17117 struct mlx5_priv *priv = dev->data->dev_private;
17118 struct mlx5_flow_meter_policy *mtr_policy;
17119 struct mlx5_flow_meter_sub_policy *sub_policy;
17120 struct mlx5_flow_meter_info *next_fm = NULL;
17121 struct mlx5_flow_meter_policy *next_policy;
17122 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17123 struct mlx5_flow_tbl_data_entry *tbl_data;
17124 struct mlx5_sub_policy_color_rule *color_rule;
17125 struct mlx5_meter_policy_acts acts;
17126 uint32_t color_reg_c_idx;
17127 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17128 struct rte_flow_attr attr = {
17129 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17136 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17139 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17140 MLX5_ASSERT(mtr_policy);
17141 if (!mtr_policy->is_hierarchy)
17143 next_fm = mlx5_flow_meter_find(priv,
17144 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17146 return rte_flow_error_set(error, EINVAL,
17147 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17148 "Failed to find next meter in hierarchy.");
17150 if (!next_fm->drop_cnt)
17152 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17153 sub_policy = mtr_policy->sub_policys[domain][0];
17154 for (i = 0; i < RTE_COLORS; i++) {
17155 bool rule_exist = false;
17156 struct mlx5_meter_policy_action_container *act_cnt;
17158 if (i >= RTE_COLOR_YELLOW)
17160 TAILQ_FOREACH(color_rule,
17161 &sub_policy->color_rules[i], next_port)
17162 if (color_rule->src_port == src_port) {
17168 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17169 sizeof(struct mlx5_sub_policy_color_rule),
17172 return rte_flow_error_set(error, ENOMEM,
17173 RTE_FLOW_ERROR_TYPE_ACTION,
17174 NULL, "No memory to create tag color rule.");
17175 color_rule->src_port = src_port;
17177 next_policy = mlx5_flow_meter_policy_find(dev,
17178 next_fm->policy_id, NULL);
17179 MLX5_ASSERT(next_policy);
17180 next_sub_policy = next_policy->sub_policys[domain][0];
17181 tbl_data = container_of(next_sub_policy->tbl_rsc,
17182 struct mlx5_flow_tbl_data_entry, tbl);
17183 act_cnt = &mtr_policy->act_cnt[i];
17185 acts.dv_actions[0] = next_fm->meter_action;
17186 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17188 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17189 acts.dv_actions[1] = next_fm->meter_action;
17191 acts.dv_actions[2] = tbl_data->jump.action;
17192 acts.actions_n = 3;
17193 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17197 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17198 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17200 &color_rule->matcher, error)) {
17201 rte_flow_error_set(error, errno,
17202 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17203 "Failed to create hierarchy meter matcher.");
17206 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17208 color_rule->matcher->matcher_object,
17209 acts.actions_n, acts.dv_actions,
17211 &color_rule->rule, &attr)) {
17212 rte_flow_error_set(error, errno,
17213 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17214 "Failed to create hierarchy meter rule.");
17217 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17218 color_rule, next_port);
17222 * Recursive call to iterate all meters in hierarchy and
17223 * create needed rules.
17225 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17226 src_port, item, error);
17229 if (color_rule->rule)
17230 mlx5_flow_os_destroy_flow(color_rule->rule);
17231 if (color_rule->matcher) {
17232 struct mlx5_flow_tbl_data_entry *tbl =
17233 container_of(color_rule->matcher->tbl,
17234 typeof(*tbl), tbl);
17235 mlx5_list_unregister(tbl->matchers,
17236 &color_rule->matcher->entry);
17238 mlx5_free(color_rule);
17241 mlx5_flow_meter_detach(priv, next_fm);
17246 * Destroy the sub policy table with RX queue.
17249 * Pointer to Ethernet device.
17250 * @param[in] mtr_policy
17251 * Pointer to meter policy table.
17254 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17255 struct mlx5_flow_meter_policy *mtr_policy)
17257 struct mlx5_priv *priv = dev->data->dev_private;
17258 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17259 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17261 uint16_t sub_policy_num, new_policy_num;
17263 rte_spinlock_lock(&mtr_policy->sl);
17264 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17265 switch (mtr_policy->act_cnt[i].fate_action) {
17266 case MLX5_FLOW_FATE_SHARED_RSS:
17267 sub_policy_num = (mtr_policy->sub_policy_num >>
17268 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17269 MLX5_MTR_SUB_POLICY_NUM_MASK;
17270 new_policy_num = sub_policy_num;
17271 for (j = 0; j < sub_policy_num; j++) {
17273 mtr_policy->sub_policys[domain][j];
17275 __flow_dv_destroy_sub_policy_rules(dev,
17278 mtr_policy->sub_policys[domain][0]) {
17279 mtr_policy->sub_policys[domain][j] =
17282 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17288 if (new_policy_num != sub_policy_num) {
17289 mtr_policy->sub_policy_num &=
17290 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17291 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17292 mtr_policy->sub_policy_num |=
17294 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17295 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17298 case MLX5_FLOW_FATE_QUEUE:
17299 sub_policy = mtr_policy->sub_policys[domain][0];
17300 __flow_dv_destroy_sub_policy_rules(dev,
17304 /*Other actions without queue and do nothing*/
17308 rte_spinlock_unlock(&mtr_policy->sl);
17311 * Check whether the DR drop action is supported on the root table or not.
17313 * Create a simple flow with DR drop action on root table to validate
17314 * if DR drop action on root table is supported or not.
17317 * Pointer to rte_eth_dev structure.
17320 * 0 on success, a negative errno value otherwise and rte_errno is set.
17323 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17325 struct mlx5_priv *priv = dev->data->dev_private;
17326 struct mlx5_dev_ctx_shared *sh = priv->sh;
17327 struct mlx5_flow_dv_match_params mask = {
17328 .size = sizeof(mask.buf),
17330 struct mlx5_flow_dv_match_params value = {
17331 .size = sizeof(value.buf),
17333 struct mlx5dv_flow_matcher_attr dv_attr = {
17334 .type = IBV_FLOW_ATTR_NORMAL,
17336 .match_criteria_enable = 0,
17337 .match_mask = (void *)&mask,
17339 struct mlx5_flow_tbl_resource *tbl = NULL;
17340 void *matcher = NULL;
17344 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17348 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17349 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17350 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17351 tbl->obj, &matcher);
17354 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17355 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17356 &sh->dr_drop_action, &flow);
17359 * If DR drop action is not supported on root table, flow create will
17360 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17364 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17365 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17367 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17370 claim_zero(mlx5_flow_os_destroy_flow(flow));
17373 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17375 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17380 * Validate the batch counter support in root table.
17382 * Create a simple flow with invalid counter and drop action on root table to
17383 * validate if batch counter with offset on root table is supported or not.
17386 * Pointer to rte_eth_dev structure.
17389 * 0 on success, a negative errno value otherwise and rte_errno is set.
17392 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17394 struct mlx5_priv *priv = dev->data->dev_private;
17395 struct mlx5_dev_ctx_shared *sh = priv->sh;
17396 struct mlx5_flow_dv_match_params mask = {
17397 .size = sizeof(mask.buf),
17399 struct mlx5_flow_dv_match_params value = {
17400 .size = sizeof(value.buf),
17402 struct mlx5dv_flow_matcher_attr dv_attr = {
17403 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17405 .match_criteria_enable = 0,
17406 .match_mask = (void *)&mask,
17408 void *actions[2] = { 0 };
17409 struct mlx5_flow_tbl_resource *tbl = NULL;
17410 struct mlx5_devx_obj *dcs = NULL;
17411 void *matcher = NULL;
17415 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17419 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17422 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17426 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17427 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17428 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17429 tbl->obj, &matcher);
17432 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17433 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17437 * If batch counter with offset is not supported, the driver will not
17438 * validate the invalid offset value, flow create should success.
17439 * In this case, it means batch counter is not supported in root table.
17441 * Otherwise, if flow create is failed, counter offset is supported.
17444 DRV_LOG(INFO, "Batch counter is not supported in root "
17445 "table. Switch to fallback mode.");
17446 rte_errno = ENOTSUP;
17448 claim_zero(mlx5_flow_os_destroy_flow(flow));
17450 /* Check matcher to make sure validate fail at flow create. */
17451 if (!matcher || (matcher && errno != EINVAL))
17452 DRV_LOG(ERR, "Unexpected error in counter offset "
17453 "support detection");
17457 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17459 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17461 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17463 claim_zero(mlx5_devx_cmd_destroy(dcs));
17468 * Query a devx counter.
17471 * Pointer to the Ethernet device structure.
17473 * Index to the flow counter.
17475 * Set to clear the counter statistics.
17477 * The statistics value of packets.
17478 * @param[out] bytes
17479 * The statistics value of bytes.
17482 * 0 on success, otherwise return -1.
17485 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17486 uint64_t *pkts, uint64_t *bytes)
17488 struct mlx5_priv *priv = dev->data->dev_private;
17489 struct mlx5_flow_counter *cnt;
17490 uint64_t inn_pkts, inn_bytes;
17493 if (!priv->sh->devx)
17496 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17499 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17500 *pkts = inn_pkts - cnt->hits;
17501 *bytes = inn_bytes - cnt->bytes;
17503 cnt->hits = inn_pkts;
17504 cnt->bytes = inn_bytes;
17510 * Get aged-out flows.
17513 * Pointer to the Ethernet device structure.
17514 * @param[in] context
17515 * The address of an array of pointers to the aged-out flows contexts.
17516 * @param[in] nb_contexts
17517 * The length of context array pointers.
17518 * @param[out] error
17519 * Perform verbose error reporting if not NULL. Initialized in case of
17523 * how many contexts get in success, otherwise negative errno value.
17524 * if nb_contexts is 0, return the amount of all aged contexts.
17525 * if nb_contexts is not 0 , return the amount of aged flows reported
17526 * in the context array.
17527 * @note: only stub for now
17530 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17532 uint32_t nb_contexts,
17533 struct rte_flow_error *error)
17535 struct mlx5_priv *priv = dev->data->dev_private;
17536 struct mlx5_age_info *age_info;
17537 struct mlx5_age_param *age_param;
17538 struct mlx5_flow_counter *counter;
17539 struct mlx5_aso_age_action *act;
17542 if (nb_contexts && !context)
17543 return rte_flow_error_set(error, EINVAL,
17544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17545 NULL, "empty context");
17546 age_info = GET_PORT_AGE_INFO(priv);
17547 rte_spinlock_lock(&age_info->aged_sl);
17548 LIST_FOREACH(act, &age_info->aged_aso, next) {
17551 context[nb_flows - 1] =
17552 act->age_params.context;
17553 if (!(--nb_contexts))
17557 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17560 age_param = MLX5_CNT_TO_AGE(counter);
17561 context[nb_flows - 1] = age_param->context;
17562 if (!(--nb_contexts))
17566 rte_spinlock_unlock(&age_info->aged_sl);
17567 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17572 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17575 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17577 return flow_dv_counter_alloc(dev, 0);
17581 * Validate indirect action.
17582 * Dispatcher for action type specific validation.
17585 * Pointer to the Ethernet device structure.
17587 * Indirect action configuration.
17588 * @param[in] action
17589 * The indirect action object to validate.
17590 * @param[out] error
17591 * Perform verbose error reporting if not NULL. Initialized in case of
17595 * 0 on success, otherwise negative errno value.
17598 flow_dv_action_validate(struct rte_eth_dev *dev,
17599 const struct rte_flow_indir_action_conf *conf,
17600 const struct rte_flow_action *action,
17601 struct rte_flow_error *err)
17603 struct mlx5_priv *priv = dev->data->dev_private;
17605 RTE_SET_USED(conf);
17606 switch (action->type) {
17607 case RTE_FLOW_ACTION_TYPE_RSS:
17609 * priv->obj_ops is set according to driver capabilities.
17610 * When DevX capabilities are
17611 * sufficient, it is set to devx_obj_ops.
17612 * Otherwise, it is set to ibv_obj_ops.
17613 * ibv_obj_ops doesn't support ind_table_modify operation.
17614 * In this case the indirect RSS action can't be used.
17616 if (priv->obj_ops.ind_table_modify == NULL)
17617 return rte_flow_error_set
17619 RTE_FLOW_ERROR_TYPE_ACTION,
17621 "Indirect RSS action not supported");
17622 return mlx5_validate_action_rss(dev, action, err);
17623 case RTE_FLOW_ACTION_TYPE_AGE:
17624 if (!priv->sh->aso_age_mng)
17625 return rte_flow_error_set(err, ENOTSUP,
17626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17628 "Indirect age action not supported");
17629 return flow_dv_validate_action_age(0, action, dev, err);
17630 case RTE_FLOW_ACTION_TYPE_COUNT:
17631 return flow_dv_validate_action_count(dev, true, 0, err);
17632 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17633 if (!priv->sh->ct_aso_en)
17634 return rte_flow_error_set(err, ENOTSUP,
17635 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17636 "ASO CT is not supported");
17637 return mlx5_validate_action_ct(dev, action->conf, err);
17639 return rte_flow_error_set(err, ENOTSUP,
17640 RTE_FLOW_ERROR_TYPE_ACTION,
17642 "action type not supported");
17647 * Check if the RSS configurations for colors of a meter policy match
17648 * each other, except the queues.
17651 * Pointer to the first RSS flow action.
17653 * Pointer to the second RSS flow action.
17656 * 0 on match, 1 on conflict.
17659 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17660 const struct rte_flow_action_rss *r2)
17662 if (r1 == NULL || r2 == NULL)
17664 if (!(r1->level <= 1 && r2->level <= 1) &&
17665 !(r1->level > 1 && r2->level > 1))
17667 if (r1->types != r2->types &&
17668 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17669 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17671 if (r1->key || r2->key) {
17672 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17673 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17675 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17682 * Validate the meter hierarchy chain for meter policy.
17685 * Pointer to the Ethernet device structure.
17686 * @param[in] meter_id
17688 * @param[in] action_flags
17689 * Holds the actions detected until now.
17690 * @param[out] is_rss
17692 * @param[out] hierarchy_domain
17693 * The domain bitmap for hierarchy policy.
17694 * @param[out] error
17695 * Perform verbose error reporting if not NULL. Initialized in case of
17699 * 0 on success, otherwise negative errno value with error set.
17702 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17704 uint64_t action_flags,
17706 uint8_t *hierarchy_domain,
17707 struct rte_mtr_error *error)
17709 struct mlx5_priv *priv = dev->data->dev_private;
17710 struct mlx5_flow_meter_info *fm;
17711 struct mlx5_flow_meter_policy *policy;
17714 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17715 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17716 return -rte_mtr_error_set(error, EINVAL,
17717 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17719 "Multiple fate actions not supported.");
17720 *hierarchy_domain = 0;
17722 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17724 return -rte_mtr_error_set(error, EINVAL,
17725 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17726 "Meter not found in meter hierarchy.");
17727 if (fm->def_policy)
17728 return -rte_mtr_error_set(error, EINVAL,
17729 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17730 "Non termination meter not supported in hierarchy.");
17731 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17732 MLX5_ASSERT(policy);
17734 * Only inherit the supported domains of the first meter in
17736 * One meter supports at least one domain.
17738 if (!*hierarchy_domain) {
17739 if (policy->transfer)
17740 *hierarchy_domain |=
17741 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17742 if (policy->ingress)
17743 *hierarchy_domain |=
17744 MLX5_MTR_DOMAIN_INGRESS_BIT;
17745 if (policy->egress)
17746 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17748 if (!policy->is_hierarchy) {
17749 *is_rss = policy->is_rss;
17752 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17753 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17754 return -rte_mtr_error_set(error, EINVAL,
17755 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17756 "Exceed max hierarchy meter number.");
17762 * Validate meter policy actions.
17763 * Dispatcher for action type specific validation.
17766 * Pointer to the Ethernet device structure.
17767 * @param[in] action
17768 * The meter policy action object to validate.
17770 * Attributes of flow to determine steering domain.
17771 * @param[out] error
17772 * Perform verbose error reporting if not NULL. Initialized in case of
17776 * 0 on success, otherwise negative errno value.
17779 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17780 const struct rte_flow_action *actions[RTE_COLORS],
17781 struct rte_flow_attr *attr,
17783 uint8_t *domain_bitmap,
17784 uint8_t *policy_mode,
17785 struct rte_mtr_error *error)
17787 struct mlx5_priv *priv = dev->data->dev_private;
17788 struct mlx5_dev_config *dev_conf = &priv->config;
17789 const struct rte_flow_action *act;
17790 uint64_t action_flags[RTE_COLORS] = {0};
17793 struct rte_flow_error flow_err;
17794 uint8_t domain_color[RTE_COLORS] = {0};
17795 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17796 uint8_t hierarchy_domain = 0;
17797 const struct rte_flow_action_meter *mtr;
17798 bool def_green = false;
17799 bool def_yellow = false;
17800 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17802 if (!priv->config.dv_esw_en)
17803 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17804 *domain_bitmap = def_domain;
17805 /* Red color could only support DROP action. */
17806 if (!actions[RTE_COLOR_RED] ||
17807 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17808 return -rte_mtr_error_set(error, ENOTSUP,
17809 RTE_MTR_ERROR_TYPE_METER_POLICY,
17810 NULL, "Red color only supports drop action.");
17812 * Check default policy actions:
17813 * Green / Yellow: no action, Red: drop action
17814 * Either G or Y will trigger default policy actions to be created.
17816 if (!actions[RTE_COLOR_GREEN] ||
17817 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17819 if (!actions[RTE_COLOR_YELLOW] ||
17820 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17822 if (def_green && def_yellow) {
17823 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17825 } else if (!def_green && def_yellow) {
17826 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17827 } else if (def_green && !def_yellow) {
17828 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17830 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17832 /* Set to empty string in case of NULL pointer access by user. */
17833 flow_err.message = "";
17834 for (i = 0; i < RTE_COLORS; i++) {
17836 for (action_flags[i] = 0, actions_n = 0;
17837 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17839 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17840 return -rte_mtr_error_set(error, ENOTSUP,
17841 RTE_MTR_ERROR_TYPE_METER_POLICY,
17842 NULL, "too many actions");
17843 switch (act->type) {
17844 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17845 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17846 if (!priv->config.dv_esw_en)
17847 return -rte_mtr_error_set(error,
17849 RTE_MTR_ERROR_TYPE_METER_POLICY,
17850 NULL, "PORT action validate check"
17851 " fail for ESW disable");
17852 ret = flow_dv_validate_action_port_id(dev,
17854 act, attr, &flow_err);
17856 return -rte_mtr_error_set(error,
17858 RTE_MTR_ERROR_TYPE_METER_POLICY,
17859 NULL, flow_err.message ?
17861 "PORT action validate check fail");
17863 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17865 case RTE_FLOW_ACTION_TYPE_MARK:
17866 ret = flow_dv_validate_action_mark(dev, act,
17870 return -rte_mtr_error_set(error,
17872 RTE_MTR_ERROR_TYPE_METER_POLICY,
17873 NULL, flow_err.message ?
17875 "Mark action validate check fail");
17876 if (dev_conf->dv_xmeta_en !=
17877 MLX5_XMETA_MODE_LEGACY)
17878 return -rte_mtr_error_set(error,
17880 RTE_MTR_ERROR_TYPE_METER_POLICY,
17881 NULL, "Extend MARK action is "
17882 "not supported. Please try use "
17883 "default policy for meter.");
17884 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17887 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17888 ret = flow_dv_validate_action_set_tag(dev,
17889 act, action_flags[i],
17892 return -rte_mtr_error_set(error,
17894 RTE_MTR_ERROR_TYPE_METER_POLICY,
17895 NULL, flow_err.message ?
17897 "Set tag action validate check fail");
17898 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17901 case RTE_FLOW_ACTION_TYPE_DROP:
17902 ret = mlx5_flow_validate_action_drop
17903 (action_flags[i], attr, &flow_err);
17905 return -rte_mtr_error_set(error,
17907 RTE_MTR_ERROR_TYPE_METER_POLICY,
17908 NULL, flow_err.message ?
17910 "Drop action validate check fail");
17911 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17914 case RTE_FLOW_ACTION_TYPE_QUEUE:
17916 * Check whether extensive
17917 * metadata feature is engaged.
17919 if (dev_conf->dv_flow_en &&
17920 (dev_conf->dv_xmeta_en !=
17921 MLX5_XMETA_MODE_LEGACY) &&
17922 mlx5_flow_ext_mreg_supported(dev))
17923 return -rte_mtr_error_set(error,
17925 RTE_MTR_ERROR_TYPE_METER_POLICY,
17926 NULL, "Queue action with meta "
17927 "is not supported. Please try use "
17928 "default policy for meter.");
17929 ret = mlx5_flow_validate_action_queue(act,
17930 action_flags[i], dev,
17933 return -rte_mtr_error_set(error,
17935 RTE_MTR_ERROR_TYPE_METER_POLICY,
17936 NULL, flow_err.message ?
17938 "Queue action validate check fail");
17939 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17942 case RTE_FLOW_ACTION_TYPE_RSS:
17943 if (dev_conf->dv_flow_en &&
17944 (dev_conf->dv_xmeta_en !=
17945 MLX5_XMETA_MODE_LEGACY) &&
17946 mlx5_flow_ext_mreg_supported(dev))
17947 return -rte_mtr_error_set(error,
17949 RTE_MTR_ERROR_TYPE_METER_POLICY,
17950 NULL, "RSS action with meta "
17951 "is not supported. Please try use "
17952 "default policy for meter.");
17953 ret = mlx5_validate_action_rss(dev, act,
17956 return -rte_mtr_error_set(error,
17958 RTE_MTR_ERROR_TYPE_METER_POLICY,
17959 NULL, flow_err.message ?
17961 "RSS action validate check fail");
17962 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17964 /* Either G or Y will set the RSS. */
17965 rss_color[i] = act->conf;
17967 case RTE_FLOW_ACTION_TYPE_JUMP:
17968 ret = flow_dv_validate_action_jump(dev,
17969 NULL, act, action_flags[i],
17970 attr, true, &flow_err);
17972 return -rte_mtr_error_set(error,
17974 RTE_MTR_ERROR_TYPE_METER_POLICY,
17975 NULL, flow_err.message ?
17977 "Jump action validate check fail");
17979 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17982 * Only the last meter in the hierarchy will support
17983 * the YELLOW color steering. Then in the meter policy
17984 * actions list, there should be no other meter inside.
17986 case RTE_FLOW_ACTION_TYPE_METER:
17987 if (i != RTE_COLOR_GREEN)
17988 return -rte_mtr_error_set(error,
17990 RTE_MTR_ERROR_TYPE_METER_POLICY,
17992 "Meter hierarchy only supports GREEN color.");
17993 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17994 return -rte_mtr_error_set(error,
17996 RTE_MTR_ERROR_TYPE_METER_POLICY,
17998 "No yellow policy should be provided in meter hierarchy.");
18000 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18010 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18013 return -rte_mtr_error_set(error, ENOTSUP,
18014 RTE_MTR_ERROR_TYPE_METER_POLICY,
18016 "Doesn't support optional action");
18019 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18020 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18021 } else if ((action_flags[i] &
18022 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18023 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18025 * Only support MLX5_XMETA_MODE_LEGACY
18026 * so MARK action is only in ingress domain.
18028 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18030 domain_color[i] = def_domain;
18031 if (action_flags[i] &&
18032 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18034 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18036 if (action_flags[i] &
18037 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18038 domain_color[i] &= hierarchy_domain;
18040 * Non-termination actions only support NIC Tx domain.
18041 * The adjustion should be skipped when there is no
18042 * action or only END is provided. The default domains
18043 * bit-mask is set to find the MIN intersection.
18044 * The action flags checking should also be skipped.
18046 if ((def_green && i == RTE_COLOR_GREEN) ||
18047 (def_yellow && i == RTE_COLOR_YELLOW))
18050 * Validate the drop action mutual exclusion
18051 * with other actions. Drop action is mutually-exclusive
18052 * with any other action, except for Count action.
18054 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18055 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18056 return -rte_mtr_error_set(error, ENOTSUP,
18057 RTE_MTR_ERROR_TYPE_METER_POLICY,
18058 NULL, "Drop action is mutually-exclusive "
18059 "with any other action");
18061 /* Eswitch has few restrictions on using items and actions */
18062 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18063 if (!mlx5_flow_ext_mreg_supported(dev) &&
18064 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18065 return -rte_mtr_error_set(error, ENOTSUP,
18066 RTE_MTR_ERROR_TYPE_METER_POLICY,
18067 NULL, "unsupported action MARK");
18068 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18069 return -rte_mtr_error_set(error, ENOTSUP,
18070 RTE_MTR_ERROR_TYPE_METER_POLICY,
18071 NULL, "unsupported action QUEUE");
18072 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18073 return -rte_mtr_error_set(error, ENOTSUP,
18074 RTE_MTR_ERROR_TYPE_METER_POLICY,
18075 NULL, "unsupported action RSS");
18076 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18077 return -rte_mtr_error_set(error, ENOTSUP,
18078 RTE_MTR_ERROR_TYPE_METER_POLICY,
18079 NULL, "no fate action is found");
18081 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18082 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18083 if ((domain_color[i] &
18084 MLX5_MTR_DOMAIN_EGRESS_BIT))
18086 MLX5_MTR_DOMAIN_EGRESS_BIT;
18088 return -rte_mtr_error_set(error,
18090 RTE_MTR_ERROR_TYPE_METER_POLICY,
18092 "no fate action is found");
18096 /* If both colors have RSS, the attributes should be the same. */
18097 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18098 rss_color[RTE_COLOR_YELLOW]))
18099 return -rte_mtr_error_set(error, EINVAL,
18100 RTE_MTR_ERROR_TYPE_METER_POLICY,
18101 NULL, "policy RSS attr conflict");
18102 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18104 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18105 if (!def_green && !def_yellow &&
18106 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18107 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18108 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18109 return -rte_mtr_error_set(error, EINVAL,
18110 RTE_MTR_ERROR_TYPE_METER_POLICY,
18111 NULL, "policy domains conflict");
18113 * At least one color policy is listed in the actions, the domains
18114 * to be supported should be the intersection.
18116 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18117 domain_color[RTE_COLOR_YELLOW];
18122 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18124 struct mlx5_priv *priv = dev->data->dev_private;
18127 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18128 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18133 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18134 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18138 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18139 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18147 * Discover the number of available flow priorities
18148 * by trying to create a flow with the highest priority value
18149 * for each possible number.
18154 * List of possible number of available priorities.
18155 * @param[in] vprio_n
18156 * Size of @p vprio array.
18158 * On success, number of available flow priorities.
18159 * On failure, a negative errno-style code and rte_errno is set.
18162 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18163 const uint16_t *vprio, int vprio_n)
18165 struct mlx5_priv *priv = dev->data->dev_private;
18166 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18167 struct rte_flow_item_eth eth;
18168 struct rte_flow_item item = {
18169 .type = RTE_FLOW_ITEM_TYPE_ETH,
18173 struct mlx5_flow_dv_matcher matcher = {
18175 .size = sizeof(matcher.mask.buf),
18178 union mlx5_flow_tbl_key tbl_key;
18179 struct mlx5_flow flow;
18181 struct rte_flow_error error;
18183 int i, err, ret = -ENOTSUP;
18186 * Prepare a flow with a catch-all pattern and a drop action.
18187 * Use drop queue, because shared drop action may be unavailable.
18189 action = priv->drop_queue.hrxq->action;
18190 if (action == NULL) {
18191 DRV_LOG(ERR, "Priority discovery requires a drop action");
18192 rte_errno = ENOTSUP;
18195 memset(&flow, 0, sizeof(flow));
18196 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18197 if (flow.handle == NULL) {
18198 DRV_LOG(ERR, "Cannot create flow handle");
18199 rte_errno = ENOMEM;
18202 flow.ingress = true;
18203 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18204 flow.dv.actions[0] = action;
18205 flow.dv.actions_n = 1;
18206 memset(ð, 0, sizeof(eth));
18207 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18208 &item, /* inner */ false, /* group */ 0);
18209 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18210 for (i = 0; i < vprio_n; i++) {
18211 /* Configure the next proposed maximum priority. */
18212 matcher.priority = vprio[i] - 1;
18213 memset(&tbl_key, 0, sizeof(tbl_key));
18214 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18219 /* This action is pure SW and must always succeed. */
18220 DRV_LOG(ERR, "Cannot register matcher");
18224 /* Try to apply the flow to HW. */
18225 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18226 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18227 err = mlx5_flow_os_create_flow
18228 (flow.handle->dvh.matcher->matcher_object,
18229 (void *)&flow.dv.value, flow.dv.actions_n,
18230 flow.dv.actions, &flow.handle->drv_flow);
18232 claim_zero(mlx5_flow_os_destroy_flow
18233 (flow.handle->drv_flow));
18234 flow.handle->drv_flow = NULL;
18236 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18241 mlx5_ipool_free(pool, flow.handle_idx);
18242 /* Set rte_errno if no expected priority value matched. */
18248 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18249 .validate = flow_dv_validate,
18250 .prepare = flow_dv_prepare,
18251 .translate = flow_dv_translate,
18252 .apply = flow_dv_apply,
18253 .remove = flow_dv_remove,
18254 .destroy = flow_dv_destroy,
18255 .query = flow_dv_query,
18256 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18257 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18258 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18259 .create_meter = flow_dv_mtr_alloc,
18260 .free_meter = flow_dv_aso_mtr_release_to_pool,
18261 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18262 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18263 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18264 .create_policy_rules = flow_dv_create_policy_rules,
18265 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18266 .create_def_policy = flow_dv_create_def_policy,
18267 .destroy_def_policy = flow_dv_destroy_def_policy,
18268 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18269 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18270 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18271 .counter_alloc = flow_dv_counter_allocate,
18272 .counter_free = flow_dv_counter_free,
18273 .counter_query = flow_dv_counter_query,
18274 .get_aged_flows = flow_dv_get_aged_flows,
18275 .action_validate = flow_dv_action_validate,
18276 .action_create = flow_dv_action_create,
18277 .action_destroy = flow_dv_action_destroy,
18278 .action_update = flow_dv_action_update,
18279 .action_query = flow_dv_action_query,
18280 .sync_domain = flow_dv_sync_domain,
18281 .discover_priorities = flow_dv_discover_priorities,
18282 .item_create = flow_dv_item_create,
18283 .item_release = flow_dv_item_release,
18286 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */