drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_ibv_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_ibv_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate GTP item.
1644  *
1645  * @param[in] dev
1646  *   Pointer to the rte_eth_dev structure.
1647  * @param[in] item
1648  *   Item specification.
1649  * @param[in] item_flags
1650  *   Bit-fields that holds the items detected until now.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1659                           const struct rte_flow_item *item,
1660                           uint64_t item_flags,
1661                           struct rte_flow_error *error)
1662 {
1663         struct mlx5_priv *priv = dev->data->dev_private;
1664         const struct rte_flow_item_gtp *mask = item->mask;
1665         const struct rte_flow_item_gtp nic_mask = {
1666                 .msg_type = 0xff,
1667                 .teid = RTE_BE32(0xffffffff),
1668         };
1669
1670         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1671                 return rte_flow_error_set(error, ENOTSUP,
1672                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1673                                           "GTP support is not enabled");
1674         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1675                 return rte_flow_error_set(error, ENOTSUP,
1676                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1677                                           "multiple tunnel layers not"
1678                                           " supported");
1679         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1680                 return rte_flow_error_set(error, EINVAL,
1681                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1682                                           "no outer UDP layer found");
1683         if (!mask)
1684                 mask = &rte_flow_item_gtp_mask;
1685         return mlx5_flow_item_acceptable
1686                 (item, (const uint8_t *)mask,
1687                  (const uint8_t *)&nic_mask,
1688                  sizeof(struct rte_flow_item_gtp),
1689                  error);
1690 }
1691
1692 /**
1693  * Validate the pop VLAN action.
1694  *
1695  * @param[in] dev
1696  *   Pointer to the rte_eth_dev structure.
1697  * @param[in] action_flags
1698  *   Holds the actions detected until now.
1699  * @param[in] action
1700  *   Pointer to the pop vlan action.
1701  * @param[in] item_flags
1702  *   The items found in this flow rule.
1703  * @param[in] attr
1704  *   Pointer to flow attributes.
1705  * @param[out] error
1706  *   Pointer to error structure.
1707  *
1708  * @return
1709  *   0 on success, a negative errno value otherwise and rte_errno is set.
1710  */
1711 static int
1712 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1713                                  uint64_t action_flags,
1714                                  const struct rte_flow_action *action,
1715                                  uint64_t item_flags,
1716                                  const struct rte_flow_attr *attr,
1717                                  struct rte_flow_error *error)
1718 {
1719         const struct mlx5_priv *priv = dev->data->dev_private;
1720
1721         (void)action;
1722         (void)attr;
1723         if (!priv->sh->pop_vlan_action)
1724                 return rte_flow_error_set(error, ENOTSUP,
1725                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726                                           NULL,
1727                                           "pop vlan action is not supported");
1728         if (attr->egress)
1729                 return rte_flow_error_set(error, ENOTSUP,
1730                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731                                           NULL,
1732                                           "pop vlan action not supported for "
1733                                           "egress");
1734         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1735                 return rte_flow_error_set(error, ENOTSUP,
1736                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1737                                           "no support for multiple VLAN "
1738                                           "actions");
1739         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1740                 return rte_flow_error_set(error, ENOTSUP,
1741                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742                                           NULL,
1743                                           "cannot pop vlan without a "
1744                                           "match on (outer) vlan in the flow");
1745         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1748                                           "wrong action order, port_id should "
1749                                           "be after pop VLAN action");
1750         if (!attr->transfer && priv->representor)
1751                 return rte_flow_error_set(error, ENOTSUP,
1752                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1753                                           "pop vlan action for VF representor "
1754                                           "not supported on NIC table");
1755         return 0;
1756 }
1757
1758 /**
1759  * Get VLAN default info from vlan match info.
1760  *
1761  * @param[in] items
1762  *   the list of item specifications.
1763  * @param[out] vlan
1764  *   pointer VLAN info to fill to.
1765  *
1766  * @return
1767  *   0 on success, a negative errno value otherwise and rte_errno is set.
1768  */
1769 static void
1770 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1771                                   struct rte_vlan_hdr *vlan)
1772 {
1773         const struct rte_flow_item_vlan nic_mask = {
1774                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1775                                 MLX5DV_FLOW_VLAN_VID_MASK),
1776                 .inner_type = RTE_BE16(0xffff),
1777         };
1778
1779         if (items == NULL)
1780                 return;
1781         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1782                 int type = items->type;
1783
1784                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1785                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1786                         break;
1787         }
1788         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1789                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1790                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1791
1792                 if (!vlan_m)
1793                         vlan_m = &nic_mask;
1794                 /* Only full match values are accepted */
1795                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1796                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1797                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798                         vlan->vlan_tci |=
1799                                 rte_be_to_cpu_16(vlan_v->tci &
1800                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801                 }
1802                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1803                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1804                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805                         vlan->vlan_tci |=
1806                                 rte_be_to_cpu_16(vlan_v->tci &
1807                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808                 }
1809                 if (vlan_m->inner_type == nic_mask.inner_type)
1810                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1811                                                            vlan_m->inner_type);
1812         }
1813 }
1814
1815 /**
1816  * Validate the push VLAN action.
1817  *
1818  * @param[in] dev
1819  *   Pointer to the rte_eth_dev structure.
1820  * @param[in] action_flags
1821  *   Holds the actions detected until now.
1822  * @param[in] item_flags
1823  *   The items found in this flow rule.
1824  * @param[in] action
1825  *   Pointer to the action structure.
1826  * @param[in] attr
1827  *   Pointer to flow attributes
1828  * @param[out] error
1829  *   Pointer to error structure.
1830  *
1831  * @return
1832  *   0 on success, a negative errno value otherwise and rte_errno is set.
1833  */
1834 static int
1835 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1836                                   uint64_t action_flags,
1837                                   const struct rte_flow_item_vlan *vlan_m,
1838                                   const struct rte_flow_action *action,
1839                                   const struct rte_flow_attr *attr,
1840                                   struct rte_flow_error *error)
1841 {
1842         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1843         const struct mlx5_priv *priv = dev->data->dev_private;
1844
1845         if (!attr->transfer && attr->ingress)
1846                 return rte_flow_error_set(error, ENOTSUP,
1847                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848                                           NULL,
1849                                           "push VLAN action not supported for "
1850                                           "ingress");
1851         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1852             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1853                 return rte_flow_error_set(error, EINVAL,
1854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1855                                           "invalid vlan ethertype");
1856         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1857                 return rte_flow_error_set(error, ENOTSUP,
1858                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1859                                           "no support for multiple VLAN "
1860                                           "actions");
1861         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1862                 return rte_flow_error_set(error, EINVAL,
1863                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1864                                           "wrong action order, port_id should "
1865                                           "be after push VLAN");
1866         if (!attr->transfer && priv->representor)
1867                 return rte_flow_error_set(error, ENOTSUP,
1868                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1869                                           "push vlan action for VF representor "
1870                                           "not supported on NIC table");
1871         if (vlan_m &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1873             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1874                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1875             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1876             !(mlx5_flow_find_action
1877                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1878                 return rte_flow_error_set(error, EINVAL,
1879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1880                                           "not full match mask on VLAN PCP and "
1881                                           "there is no of_set_vlan_pcp action, "
1882                                           "push VLAN action cannot figure out "
1883                                           "PCP value");
1884         if (vlan_m &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1886             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1887                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1888             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1889             !(mlx5_flow_find_action
1890                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1891                 return rte_flow_error_set(error, EINVAL,
1892                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1893                                           "not full match mask on VLAN VID and "
1894                                           "there is no of_set_vlan_vid action, "
1895                                           "push VLAN action cannot figure out "
1896                                           "VID value");
1897         (void)attr;
1898         return 0;
1899 }
1900
1901 /**
1902  * Validate the set VLAN PCP.
1903  *
1904  * @param[in] action_flags
1905  *   Holds the actions detected until now.
1906  * @param[in] actions
1907  *   Pointer to the list of actions remaining in the flow rule.
1908  * @param[out] error
1909  *   Pointer to error structure.
1910  *
1911  * @return
1912  *   0 on success, a negative errno value otherwise and rte_errno is set.
1913  */
1914 static int
1915 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1916                                      const struct rte_flow_action actions[],
1917                                      struct rte_flow_error *error)
1918 {
1919         const struct rte_flow_action *action = actions;
1920         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921
1922         if (conf->vlan_pcp > 7)
1923                 return rte_flow_error_set(error, EINVAL,
1924                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1925                                           "VLAN PCP value is too big");
1926         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1927                 return rte_flow_error_set(error, ENOTSUP,
1928                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1929                                           "set VLAN PCP action must follow "
1930                                           "the push VLAN action");
1931         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1932                 return rte_flow_error_set(error, ENOTSUP,
1933                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1934                                           "Multiple VLAN PCP modification are "
1935                                           "not supported");
1936         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1937                 return rte_flow_error_set(error, EINVAL,
1938                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1939                                           "wrong action order, port_id should "
1940                                           "be after set VLAN PCP");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate the set VLAN VID.
1946  *
1947  * @param[in] item_flags
1948  *   Holds the items detected in this rule.
1949  * @param[in] action_flags
1950  *   Holds the actions detected until now.
1951  * @param[in] actions
1952  *   Pointer to the list of actions remaining in the flow rule.
1953  * @param[out] error
1954  *   Pointer to error structure.
1955  *
1956  * @return
1957  *   0 on success, a negative errno value otherwise and rte_errno is set.
1958  */
1959 static int
1960 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1961                                      uint64_t action_flags,
1962                                      const struct rte_flow_action actions[],
1963                                      struct rte_flow_error *error)
1964 {
1965         const struct rte_flow_action *action = actions;
1966         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967
1968         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
1969                 return rte_flow_error_set(error, EINVAL,
1970                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1971                                           "VLAN VID value is too big");
1972         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1973             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1976                                           "set VLAN VID action must follow push"
1977                                           " VLAN action or match on VLAN item");
1978         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1979                 return rte_flow_error_set(error, ENOTSUP,
1980                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1981                                           "Multiple VLAN VID modifications are "
1982                                           "not supported");
1983         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1984                 return rte_flow_error_set(error, EINVAL,
1985                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1986                                           "wrong action order, port_id should "
1987                                           "be after set VLAN VID");
1988         return 0;
1989 }
1990
1991 /*
1992  * Validate the FLAG action.
1993  *
1994  * @param[in] dev
1995  *   Pointer to the rte_eth_dev structure.
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] attr
1999  *   Pointer to flow attributes
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2008                              uint64_t action_flags,
2009                              const struct rte_flow_attr *attr,
2010                              struct rte_flow_error *error)
2011 {
2012         struct mlx5_priv *priv = dev->data->dev_private;
2013         struct mlx5_dev_config *config = &priv->config;
2014         int ret;
2015
2016         /* Fall back if no extended metadata register support. */
2017         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2018                 return mlx5_flow_validate_action_flag(action_flags, attr,
2019                                                       error);
2020         /* Extensive metadata mode requires registers. */
2021         if (!mlx5_flow_ext_mreg_supported(dev))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2024                                           "no metadata registers "
2025                                           "to support flag action");
2026         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2029                                           "extended metadata register"
2030                                           " isn't available");
2031         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2032         if (ret < 0)
2033                 return ret;
2034         MLX5_ASSERT(ret > 0);
2035         if (action_flags & MLX5_FLOW_ACTION_MARK)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2038                                           "can't mark and flag in same flow");
2039         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2040                 return rte_flow_error_set(error, EINVAL,
2041                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042                                           "can't have 2 flag"
2043                                           " actions in same flow");
2044         return 0;
2045 }
2046
2047 /**
2048  * Validate MARK action.
2049  *
2050  * @param[in] dev
2051  *   Pointer to the rte_eth_dev structure.
2052  * @param[in] action
2053  *   Pointer to action.
2054  * @param[in] action_flags
2055  *   Holds the actions detected until now.
2056  * @param[in] attr
2057  *   Pointer to flow attributes
2058  * @param[out] error
2059  *   Pointer to error structure.
2060  *
2061  * @return
2062  *   0 on success, a negative errno value otherwise and rte_errno is set.
2063  */
2064 static int
2065 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2066                              const struct rte_flow_action *action,
2067                              uint64_t action_flags,
2068                              const struct rte_flow_attr *attr,
2069                              struct rte_flow_error *error)
2070 {
2071         struct mlx5_priv *priv = dev->data->dev_private;
2072         struct mlx5_dev_config *config = &priv->config;
2073         const struct rte_flow_action_mark *mark = action->conf;
2074         int ret;
2075
2076         /* Fall back if no extended metadata register support. */
2077         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2078                 return mlx5_flow_validate_action_mark(action, action_flags,
2079                                                       attr, error);
2080         /* Extensive metadata mode requires registers. */
2081         if (!mlx5_flow_ext_mreg_supported(dev))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2084                                           "no metadata registers "
2085                                           "to support mark action");
2086         if (!priv->sh->dv_mark_mask)
2087                 return rte_flow_error_set(error, ENOTSUP,
2088                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2089                                           "extended metadata register"
2090                                           " isn't available");
2091         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2092         if (ret < 0)
2093                 return ret;
2094         MLX5_ASSERT(ret > 0);
2095         if (!mark)
2096                 return rte_flow_error_set(error, EINVAL,
2097                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2098                                           "configuration cannot be null");
2099         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2100                 return rte_flow_error_set(error, EINVAL,
2101                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102                                           &mark->id,
2103                                           "mark id exceeds the limit");
2104         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2105                 return rte_flow_error_set(error, EINVAL,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2107                                           "can't flag and mark in same flow");
2108         if (action_flags & MLX5_FLOW_ACTION_MARK)
2109                 return rte_flow_error_set(error, EINVAL,
2110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111                                           "can't have 2 mark actions in same"
2112                                           " flow");
2113         return 0;
2114 }
2115
2116 /**
2117  * Validate SET_META action.
2118  *
2119  * @param[in] dev
2120  *   Pointer to the rte_eth_dev structure.
2121  * @param[in] action
2122  *   Pointer to the action structure.
2123  * @param[in] action_flags
2124  *   Holds the actions detected until now.
2125  * @param[in] attr
2126  *   Pointer to flow attributes
2127  * @param[out] error
2128  *   Pointer to error structure.
2129  *
2130  * @return
2131  *   0 on success, a negative errno value otherwise and rte_errno is set.
2132  */
2133 static int
2134 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2135                                  const struct rte_flow_action *action,
2136                                  uint64_t action_flags __rte_unused,
2137                                  const struct rte_flow_attr *attr,
2138                                  struct rte_flow_error *error)
2139 {
2140         const struct rte_flow_action_set_meta *conf;
2141         uint32_t nic_mask = UINT32_MAX;
2142         int reg;
2143
2144         if (!mlx5_flow_ext_mreg_supported(dev))
2145                 return rte_flow_error_set(error, ENOTSUP,
2146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2147                                           "extended metadata register"
2148                                           " isn't supported");
2149         reg = flow_dv_get_metadata_reg(dev, attr, error);
2150         if (reg < 0)
2151                 return reg;
2152         if (reg != REG_A && reg != REG_B) {
2153                 struct mlx5_priv *priv = dev->data->dev_private;
2154
2155                 nic_mask = priv->sh->dv_meta_mask;
2156         }
2157         if (!(action->conf))
2158                 return rte_flow_error_set(error, EINVAL,
2159                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2160                                           "configuration cannot be null");
2161         conf = (const struct rte_flow_action_set_meta *)action->conf;
2162         if (!conf->mask)
2163                 return rte_flow_error_set(error, EINVAL,
2164                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2165                                           "zero mask doesn't have any effect");
2166         if (conf->mask & ~nic_mask)
2167                 return rte_flow_error_set(error, EINVAL,
2168                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2169                                           "meta data must be within reg C0");
2170         return 0;
2171 }
2172
2173 /**
2174  * Validate SET_TAG action.
2175  *
2176  * @param[in] dev
2177  *   Pointer to the rte_eth_dev structure.
2178  * @param[in] action
2179  *   Pointer to the action structure.
2180  * @param[in] action_flags
2181  *   Holds the actions detected until now.
2182  * @param[in] attr
2183  *   Pointer to flow attributes
2184  * @param[out] error
2185  *   Pointer to error structure.
2186  *
2187  * @return
2188  *   0 on success, a negative errno value otherwise and rte_errno is set.
2189  */
2190 static int
2191 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2192                                 const struct rte_flow_action *action,
2193                                 uint64_t action_flags,
2194                                 const struct rte_flow_attr *attr,
2195                                 struct rte_flow_error *error)
2196 {
2197         const struct rte_flow_action_set_tag *conf;
2198         const uint64_t terminal_action_flags =
2199                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2200                 MLX5_FLOW_ACTION_RSS;
2201         int ret;
2202
2203         if (!mlx5_flow_ext_mreg_supported(dev))
2204                 return rte_flow_error_set(error, ENOTSUP,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2206                                           "extensive metadata register"
2207                                           " isn't supported");
2208         if (!(action->conf))
2209                 return rte_flow_error_set(error, EINVAL,
2210                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2211                                           "configuration cannot be null");
2212         conf = (const struct rte_flow_action_set_tag *)action->conf;
2213         if (!conf->mask)
2214                 return rte_flow_error_set(error, EINVAL,
2215                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2216                                           "zero mask doesn't have any effect");
2217         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2218         if (ret < 0)
2219                 return ret;
2220         if (!attr->transfer && attr->ingress &&
2221             (action_flags & terminal_action_flags))
2222                 return rte_flow_error_set(error, EINVAL,
2223                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2224                                           "set_tag has no effect"
2225                                           " with terminal actions");
2226         return 0;
2227 }
2228
2229 /**
2230  * Validate count action.
2231  *
2232  * @param[in] dev
2233  *   Pointer to rte_eth_dev structure.
2234  * @param[out] error
2235  *   Pointer to error structure.
2236  *
2237  * @return
2238  *   0 on success, a negative errno value otherwise and rte_errno is set.
2239  */
2240 static int
2241 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2242                               struct rte_flow_error *error)
2243 {
2244         struct mlx5_priv *priv = dev->data->dev_private;
2245
2246         if (!priv->config.devx)
2247                 goto notsup_err;
2248 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2249         return 0;
2250 #endif
2251 notsup_err:
2252         return rte_flow_error_set
2253                       (error, ENOTSUP,
2254                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255                        NULL,
2256                        "count action not supported");
2257 }
2258
2259 /**
2260  * Validate the L2 encap action.
2261  *
2262  * @param[in] dev
2263  *   Pointer to the rte_eth_dev structure.
2264  * @param[in] action_flags
2265  *   Holds the actions detected until now.
2266  * @param[in] action
2267  *   Pointer to the action structure.
2268  * @param[in] attr
2269  *   Pointer to flow attributes.
2270  * @param[out] error
2271  *   Pointer to error structure.
2272  *
2273  * @return
2274  *   0 on success, a negative errno value otherwise and rte_errno is set.
2275  */
2276 static int
2277 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2278                                  uint64_t action_flags,
2279                                  const struct rte_flow_action *action,
2280                                  const struct rte_flow_attr *attr,
2281                                  struct rte_flow_error *error)
2282 {
2283         const struct mlx5_priv *priv = dev->data->dev_private;
2284
2285         if (!(action->conf))
2286                 return rte_flow_error_set(error, EINVAL,
2287                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2288                                           "configuration cannot be null");
2289         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2290                 return rte_flow_error_set(error, EINVAL,
2291                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2292                                           "can only have a single encap action "
2293                                           "in a flow");
2294         if (!attr->transfer && priv->representor)
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2297                                           "encap action for VF representor "
2298                                           "not supported on NIC table");
2299         return 0;
2300 }
2301
2302 /**
2303  * Validate a decap action.
2304  *
2305  * @param[in] dev
2306  *   Pointer to the rte_eth_dev structure.
2307  * @param[in] action_flags
2308  *   Holds the actions detected until now.
2309  * @param[in] attr
2310  *   Pointer to flow attributes
2311  * @param[out] error
2312  *   Pointer to error structure.
2313  *
2314  * @return
2315  *   0 on success, a negative errno value otherwise and rte_errno is set.
2316  */
2317 static int
2318 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2319                               uint64_t action_flags,
2320                               const struct rte_flow_attr *attr,
2321                               struct rte_flow_error *error)
2322 {
2323         const struct mlx5_priv *priv = dev->data->dev_private;
2324
2325         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2326                 return rte_flow_error_set(error, ENOTSUP,
2327                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328                                           action_flags &
2329                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2330                                           "have a single decap action" : "decap "
2331                                           "after encap is not supported");
2332         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2333                 return rte_flow_error_set(error, EINVAL,
2334                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2335                                           "can't have decap action after"
2336                                           " modify action");
2337         if (attr->egress)
2338                 return rte_flow_error_set(error, ENOTSUP,
2339                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340                                           NULL,
2341                                           "decap action not supported for "
2342                                           "egress");
2343         if (!attr->transfer && priv->representor)
2344                 return rte_flow_error_set(error, ENOTSUP,
2345                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2346                                           "decap action for VF representor "
2347                                           "not supported on NIC table");
2348         return 0;
2349 }
2350
2351 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2352
2353 /**
2354  * Validate the raw encap and decap actions.
2355  *
2356  * @param[in] dev
2357  *   Pointer to the rte_eth_dev structure.
2358  * @param[in] decap
2359  *   Pointer to the decap action.
2360  * @param[in] encap
2361  *   Pointer to the encap action.
2362  * @param[in] attr
2363  *   Pointer to flow attributes
2364  * @param[in/out] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[out] actions_n
2367  *   pointer to the number of actions counter.
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_raw_encap_decap
2376         (struct rte_eth_dev *dev,
2377          const struct rte_flow_action_raw_decap *decap,
2378          const struct rte_flow_action_raw_encap *encap,
2379          const struct rte_flow_attr *attr, uint64_t *action_flags,
2380          int *actions_n, struct rte_flow_error *error)
2381 {
2382         const struct mlx5_priv *priv = dev->data->dev_private;
2383         int ret;
2384
2385         if (encap && (!encap->size || !encap->data))
2386                 return rte_flow_error_set(error, EINVAL,
2387                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2388                                           "raw encap data cannot be empty");
2389         if (decap && encap) {
2390                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2391                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2392                         /* L3 encap. */
2393                         decap = NULL;
2394                 else if (encap->size <=
2395                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2396                            decap->size >
2397                            MLX5_ENCAPSULATION_DECISION_SIZE)
2398                         /* L3 decap. */
2399                         encap = NULL;
2400                 else if (encap->size >
2401                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2402                            decap->size >
2403                            MLX5_ENCAPSULATION_DECISION_SIZE)
2404                         /* 2 L2 actions: encap and decap. */
2405                         ;
2406                 else
2407                         return rte_flow_error_set(error,
2408                                 ENOTSUP,
2409                                 RTE_FLOW_ERROR_TYPE_ACTION,
2410                                 NULL, "unsupported too small "
2411                                 "raw decap and too small raw "
2412                                 "encap combination");
2413         }
2414         if (decap) {
2415                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2416                                                     error);
2417                 if (ret < 0)
2418                         return ret;
2419                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2420                 ++(*actions_n);
2421         }
2422         if (encap) {
2423                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2424                         return rte_flow_error_set(error, ENOTSUP,
2425                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2426                                                   NULL,
2427                                                   "small raw encap size");
2428                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2429                         return rte_flow_error_set(error, EINVAL,
2430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2431                                                   NULL,
2432                                                   "more than one encap action");
2433                 if (!attr->transfer && priv->representor)
2434                         return rte_flow_error_set
2435                                         (error, ENOTSUP,
2436                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2437                                          "encap action for VF representor "
2438                                          "not supported on NIC table");
2439                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2440                 ++(*actions_n);
2441         }
2442         return 0;
2443 }
2444
2445 /**
2446  * Find existing encap/decap resource or create and register a new one.
2447  *
2448  * @param[in, out] dev
2449  *   Pointer to rte_eth_dev structure.
2450  * @param[in, out] resource
2451  *   Pointer to encap/decap resource.
2452  * @parm[in, out] dev_flow
2453  *   Pointer to the dev_flow.
2454  * @param[out] error
2455  *   pointer to error structure.
2456  *
2457  * @return
2458  *   0 on success otherwise -errno and errno is set.
2459  */
2460 static int
2461 flow_dv_encap_decap_resource_register
2462                         (struct rte_eth_dev *dev,
2463                          struct mlx5_flow_dv_encap_decap_resource *resource,
2464                          struct mlx5_flow *dev_flow,
2465                          struct rte_flow_error *error)
2466 {
2467         struct mlx5_priv *priv = dev->data->dev_private;
2468         struct mlx5_ibv_shared *sh = priv->sh;
2469         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2470         struct mlx5dv_dr_domain *domain;
2471         uint32_t idx = 0;
2472
2473         resource->flags = dev_flow->dv.group ? 0 : 1;
2474         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2475                 domain = sh->fdb_domain;
2476         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2477                 domain = sh->rx_domain;
2478         else
2479                 domain = sh->tx_domain;
2480         /* Lookup a matching resource from cache. */
2481         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2482                       cache_resource, next) {
2483                 if (resource->reformat_type == cache_resource->reformat_type &&
2484                     resource->ft_type == cache_resource->ft_type &&
2485                     resource->flags == cache_resource->flags &&
2486                     resource->size == cache_resource->size &&
2487                     !memcmp((const void *)resource->buf,
2488                             (const void *)cache_resource->buf,
2489                             resource->size)) {
2490                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2491                                 (void *)cache_resource,
2492                                 rte_atomic32_read(&cache_resource->refcnt));
2493                         rte_atomic32_inc(&cache_resource->refcnt);
2494                         dev_flow->handle->dvh.rix_encap_decap = idx;
2495                         dev_flow->dv.encap_decap = cache_resource;
2496                         return 0;
2497                 }
2498         }
2499         /* Register new encap/decap resource. */
2500         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2501                                        &dev_flow->handle->dvh.rix_encap_decap);
2502         if (!cache_resource)
2503                 return rte_flow_error_set(error, ENOMEM,
2504                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2505                                           "cannot allocate resource memory");
2506         *cache_resource = *resource;
2507         cache_resource->verbs_action =
2508                 mlx5_glue->dv_create_flow_action_packet_reformat
2509                         (sh->ctx, cache_resource->reformat_type,
2510                          cache_resource->ft_type, domain, cache_resource->flags,
2511                          cache_resource->size,
2512                          (cache_resource->size ? cache_resource->buf : NULL));
2513         if (!cache_resource->verbs_action) {
2514                 rte_free(cache_resource);
2515                 return rte_flow_error_set(error, ENOMEM,
2516                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2517                                           NULL, "cannot create action");
2518         }
2519         rte_atomic32_init(&cache_resource->refcnt);
2520         rte_atomic32_inc(&cache_resource->refcnt);
2521         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2522                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2523                      next);
2524         dev_flow->dv.encap_decap = cache_resource;
2525         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2526                 (void *)cache_resource,
2527                 rte_atomic32_read(&cache_resource->refcnt));
2528         return 0;
2529 }
2530
2531 /**
2532  * Find existing table jump resource or create and register a new one.
2533  *
2534  * @param[in, out] dev
2535  *   Pointer to rte_eth_dev structure.
2536  * @param[in, out] tbl
2537  *   Pointer to flow table resource.
2538  * @parm[in, out] dev_flow
2539  *   Pointer to the dev_flow.
2540  * @param[out] error
2541  *   pointer to error structure.
2542  *
2543  * @return
2544  *   0 on success otherwise -errno and errno is set.
2545  */
2546 static int
2547 flow_dv_jump_tbl_resource_register
2548                         (struct rte_eth_dev *dev __rte_unused,
2549                          struct mlx5_flow_tbl_resource *tbl,
2550                          struct mlx5_flow *dev_flow,
2551                          struct rte_flow_error *error)
2552 {
2553         struct mlx5_flow_tbl_data_entry *tbl_data =
2554                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2555         int cnt;
2556
2557         MLX5_ASSERT(tbl);
2558         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2559         if (!cnt) {
2560                 tbl_data->jump.action =
2561                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2562                         (tbl->obj);
2563                 if (!tbl_data->jump.action)
2564                         return rte_flow_error_set(error, ENOMEM,
2565                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2566                                         NULL, "cannot create jump action");
2567                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2568                         (void *)&tbl_data->jump, cnt);
2569         } else {
2570                 /* old jump should not make the table ref++. */
2571                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2572                 MLX5_ASSERT(tbl_data->jump.action);
2573                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2574                         (void *)&tbl_data->jump, cnt);
2575         }
2576         rte_atomic32_inc(&tbl_data->jump.refcnt);
2577         dev_flow->handle->rix_jump = tbl_data->idx;
2578         dev_flow->dv.jump = &tbl_data->jump;
2579         return 0;
2580 }
2581
2582 /**
2583  * Find existing table port ID resource or create and register a new one.
2584  *
2585  * @param[in, out] dev
2586  *   Pointer to rte_eth_dev structure.
2587  * @param[in, out] resource
2588  *   Pointer to port ID action resource.
2589  * @parm[in, out] dev_flow
2590  *   Pointer to the dev_flow.
2591  * @param[out] error
2592  *   pointer to error structure.
2593  *
2594  * @return
2595  *   0 on success otherwise -errno and errno is set.
2596  */
2597 static int
2598 flow_dv_port_id_action_resource_register
2599                         (struct rte_eth_dev *dev,
2600                          struct mlx5_flow_dv_port_id_action_resource *resource,
2601                          struct mlx5_flow *dev_flow,
2602                          struct rte_flow_error *error)
2603 {
2604         struct mlx5_priv *priv = dev->data->dev_private;
2605         struct mlx5_ibv_shared *sh = priv->sh;
2606         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2607         uint32_t idx = 0;
2608
2609         /* Lookup a matching resource from cache. */
2610         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2611                       idx, cache_resource, next) {
2612                 if (resource->port_id == cache_resource->port_id) {
2613                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2614                                 "refcnt %d++",
2615                                 (void *)cache_resource,
2616                                 rte_atomic32_read(&cache_resource->refcnt));
2617                         rte_atomic32_inc(&cache_resource->refcnt);
2618                         dev_flow->handle->rix_port_id_action = idx;
2619                         dev_flow->dv.port_id_action = cache_resource;
2620                         return 0;
2621                 }
2622         }
2623         /* Register new port id action resource. */
2624         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2625                                        &dev_flow->handle->rix_port_id_action);
2626         if (!cache_resource)
2627                 return rte_flow_error_set(error, ENOMEM,
2628                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2629                                           "cannot allocate resource memory");
2630         *cache_resource = *resource;
2631         /*
2632          * Depending on rdma_core version the glue routine calls
2633          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2634          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2635          */
2636         cache_resource->action =
2637                 mlx5_glue->dr_create_flow_action_dest_port
2638                         (priv->sh->fdb_domain, resource->port_id);
2639         if (!cache_resource->action) {
2640                 rte_free(cache_resource);
2641                 return rte_flow_error_set(error, ENOMEM,
2642                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2643                                           NULL, "cannot create action");
2644         }
2645         rte_atomic32_init(&cache_resource->refcnt);
2646         rte_atomic32_inc(&cache_resource->refcnt);
2647         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2648                      dev_flow->handle->rix_port_id_action, cache_resource,
2649                      next);
2650         dev_flow->dv.port_id_action = cache_resource;
2651         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2652                 (void *)cache_resource,
2653                 rte_atomic32_read(&cache_resource->refcnt));
2654         return 0;
2655 }
2656
2657 /**
2658  * Find existing push vlan resource or create and register a new one.
2659  *
2660  * @param [in, out] dev
2661  *   Pointer to rte_eth_dev structure.
2662  * @param[in, out] resource
2663  *   Pointer to port ID action resource.
2664  * @parm[in, out] dev_flow
2665  *   Pointer to the dev_flow.
2666  * @param[out] error
2667  *   pointer to error structure.
2668  *
2669  * @return
2670  *   0 on success otherwise -errno and errno is set.
2671  */
2672 static int
2673 flow_dv_push_vlan_action_resource_register
2674                        (struct rte_eth_dev *dev,
2675                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2676                         struct mlx5_flow *dev_flow,
2677                         struct rte_flow_error *error)
2678 {
2679         struct mlx5_priv *priv = dev->data->dev_private;
2680         struct mlx5_ibv_shared *sh = priv->sh;
2681         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2682         struct mlx5dv_dr_domain *domain;
2683         uint32_t idx = 0;
2684
2685         /* Lookup a matching resource from cache. */
2686         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2687                       sh->push_vlan_action_list, idx, cache_resource, next) {
2688                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2689                     resource->ft_type == cache_resource->ft_type) {
2690                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2691                                 "refcnt %d++",
2692                                 (void *)cache_resource,
2693                                 rte_atomic32_read(&cache_resource->refcnt));
2694                         rte_atomic32_inc(&cache_resource->refcnt);
2695                         dev_flow->handle->dvh.rix_push_vlan = idx;
2696                         dev_flow->dv.push_vlan_res = cache_resource;
2697                         return 0;
2698                 }
2699         }
2700         /* Register new push_vlan action resource. */
2701         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2702                                        &dev_flow->handle->dvh.rix_push_vlan);
2703         if (!cache_resource)
2704                 return rte_flow_error_set(error, ENOMEM,
2705                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2706                                           "cannot allocate resource memory");
2707         *cache_resource = *resource;
2708         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2709                 domain = sh->fdb_domain;
2710         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2711                 domain = sh->rx_domain;
2712         else
2713                 domain = sh->tx_domain;
2714         cache_resource->action =
2715                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2716                                                            resource->vlan_tag);
2717         if (!cache_resource->action) {
2718                 rte_free(cache_resource);
2719                 return rte_flow_error_set(error, ENOMEM,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2721                                           NULL, "cannot create action");
2722         }
2723         rte_atomic32_init(&cache_resource->refcnt);
2724         rte_atomic32_inc(&cache_resource->refcnt);
2725         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2726                      &sh->push_vlan_action_list,
2727                      dev_flow->handle->dvh.rix_push_vlan,
2728                      cache_resource, next);
2729         dev_flow->dv.push_vlan_res = cache_resource;
2730         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2731                 (void *)cache_resource,
2732                 rte_atomic32_read(&cache_resource->refcnt));
2733         return 0;
2734 }
2735 /**
2736  * Get the size of specific rte_flow_item_type
2737  *
2738  * @param[in] item_type
2739  *   Tested rte_flow_item_type.
2740  *
2741  * @return
2742  *   sizeof struct item_type, 0 if void or irrelevant.
2743  */
2744 static size_t
2745 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2746 {
2747         size_t retval;
2748
2749         switch (item_type) {
2750         case RTE_FLOW_ITEM_TYPE_ETH:
2751                 retval = sizeof(struct rte_flow_item_eth);
2752                 break;
2753         case RTE_FLOW_ITEM_TYPE_VLAN:
2754                 retval = sizeof(struct rte_flow_item_vlan);
2755                 break;
2756         case RTE_FLOW_ITEM_TYPE_IPV4:
2757                 retval = sizeof(struct rte_flow_item_ipv4);
2758                 break;
2759         case RTE_FLOW_ITEM_TYPE_IPV6:
2760                 retval = sizeof(struct rte_flow_item_ipv6);
2761                 break;
2762         case RTE_FLOW_ITEM_TYPE_UDP:
2763                 retval = sizeof(struct rte_flow_item_udp);
2764                 break;
2765         case RTE_FLOW_ITEM_TYPE_TCP:
2766                 retval = sizeof(struct rte_flow_item_tcp);
2767                 break;
2768         case RTE_FLOW_ITEM_TYPE_VXLAN:
2769                 retval = sizeof(struct rte_flow_item_vxlan);
2770                 break;
2771         case RTE_FLOW_ITEM_TYPE_GRE:
2772                 retval = sizeof(struct rte_flow_item_gre);
2773                 break;
2774         case RTE_FLOW_ITEM_TYPE_NVGRE:
2775                 retval = sizeof(struct rte_flow_item_nvgre);
2776                 break;
2777         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2778                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2779                 break;
2780         case RTE_FLOW_ITEM_TYPE_MPLS:
2781                 retval = sizeof(struct rte_flow_item_mpls);
2782                 break;
2783         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2784         default:
2785                 retval = 0;
2786                 break;
2787         }
2788         return retval;
2789 }
2790
2791 #define MLX5_ENCAP_IPV4_VERSION         0x40
2792 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2793 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2794 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2795 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2796 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2797 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2798
2799 /**
2800  * Convert the encap action data from list of rte_flow_item to raw buffer
2801  *
2802  * @param[in] items
2803  *   Pointer to rte_flow_item objects list.
2804  * @param[out] buf
2805  *   Pointer to the output buffer.
2806  * @param[out] size
2807  *   Pointer to the output buffer size.
2808  * @param[out] error
2809  *   Pointer to the error structure.
2810  *
2811  * @return
2812  *   0 on success, a negative errno value otherwise and rte_errno is set.
2813  */
2814 static int
2815 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2816                            size_t *size, struct rte_flow_error *error)
2817 {
2818         struct rte_ether_hdr *eth = NULL;
2819         struct rte_vlan_hdr *vlan = NULL;
2820         struct rte_ipv4_hdr *ipv4 = NULL;
2821         struct rte_ipv6_hdr *ipv6 = NULL;
2822         struct rte_udp_hdr *udp = NULL;
2823         struct rte_vxlan_hdr *vxlan = NULL;
2824         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2825         struct rte_gre_hdr *gre = NULL;
2826         size_t len;
2827         size_t temp_size = 0;
2828
2829         if (!items)
2830                 return rte_flow_error_set(error, EINVAL,
2831                                           RTE_FLOW_ERROR_TYPE_ACTION,
2832                                           NULL, "invalid empty data");
2833         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2834                 len = flow_dv_get_item_len(items->type);
2835                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2836                         return rte_flow_error_set(error, EINVAL,
2837                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2838                                                   (void *)items->type,
2839                                                   "items total size is too big"
2840                                                   " for encap action");
2841                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2842                 switch (items->type) {
2843                 case RTE_FLOW_ITEM_TYPE_ETH:
2844                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2845                         break;
2846                 case RTE_FLOW_ITEM_TYPE_VLAN:
2847                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2848                         if (!eth)
2849                                 return rte_flow_error_set(error, EINVAL,
2850                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2851                                                 (void *)items->type,
2852                                                 "eth header not found");
2853                         if (!eth->ether_type)
2854                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2855                         break;
2856                 case RTE_FLOW_ITEM_TYPE_IPV4:
2857                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2858                         if (!vlan && !eth)
2859                                 return rte_flow_error_set(error, EINVAL,
2860                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2861                                                 (void *)items->type,
2862                                                 "neither eth nor vlan"
2863                                                 " header found");
2864                         if (vlan && !vlan->eth_proto)
2865                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866                         else if (eth && !eth->ether_type)
2867                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2868                         if (!ipv4->version_ihl)
2869                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2870                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2871                         if (!ipv4->time_to_live)
2872                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2873                         break;
2874                 case RTE_FLOW_ITEM_TYPE_IPV6:
2875                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2876                         if (!vlan && !eth)
2877                                 return rte_flow_error_set(error, EINVAL,
2878                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2879                                                 (void *)items->type,
2880                                                 "neither eth nor vlan"
2881                                                 " header found");
2882                         if (vlan && !vlan->eth_proto)
2883                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884                         else if (eth && !eth->ether_type)
2885                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2886                         if (!ipv6->vtc_flow)
2887                                 ipv6->vtc_flow =
2888                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2889                         if (!ipv6->hop_limits)
2890                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2891                         break;
2892                 case RTE_FLOW_ITEM_TYPE_UDP:
2893                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2894                         if (!ipv4 && !ipv6)
2895                                 return rte_flow_error_set(error, EINVAL,
2896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2897                                                 (void *)items->type,
2898                                                 "ip header not found");
2899                         if (ipv4 && !ipv4->next_proto_id)
2900                                 ipv4->next_proto_id = IPPROTO_UDP;
2901                         else if (ipv6 && !ipv6->proto)
2902                                 ipv6->proto = IPPROTO_UDP;
2903                         break;
2904                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2906                         if (!udp)
2907                                 return rte_flow_error_set(error, EINVAL,
2908                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2909                                                 (void *)items->type,
2910                                                 "udp header not found");
2911                         if (!udp->dst_port)
2912                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2913                         if (!vxlan->vx_flags)
2914                                 vxlan->vx_flags =
2915                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2916                         break;
2917                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2918                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2919                         if (!udp)
2920                                 return rte_flow_error_set(error, EINVAL,
2921                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2922                                                 (void *)items->type,
2923                                                 "udp header not found");
2924                         if (!vxlan_gpe->proto)
2925                                 return rte_flow_error_set(error, EINVAL,
2926                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2927                                                 (void *)items->type,
2928                                                 "next protocol not found");
2929                         if (!udp->dst_port)
2930                                 udp->dst_port =
2931                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2932                         if (!vxlan_gpe->vx_flags)
2933                                 vxlan_gpe->vx_flags =
2934                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2935                         break;
2936                 case RTE_FLOW_ITEM_TYPE_GRE:
2937                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2938                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2939                         if (!gre->proto)
2940                                 return rte_flow_error_set(error, EINVAL,
2941                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2942                                                 (void *)items->type,
2943                                                 "next protocol not found");
2944                         if (!ipv4 && !ipv6)
2945                                 return rte_flow_error_set(error, EINVAL,
2946                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2947                                                 (void *)items->type,
2948                                                 "ip header not found");
2949                         if (ipv4 && !ipv4->next_proto_id)
2950                                 ipv4->next_proto_id = IPPROTO_GRE;
2951                         else if (ipv6 && !ipv6->proto)
2952                                 ipv6->proto = IPPROTO_GRE;
2953                         break;
2954                 case RTE_FLOW_ITEM_TYPE_VOID:
2955                         break;
2956                 default:
2957                         return rte_flow_error_set(error, EINVAL,
2958                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2959                                                   (void *)items->type,
2960                                                   "unsupported item type");
2961                         break;
2962                 }
2963                 temp_size += len;
2964         }
2965         *size = temp_size;
2966         return 0;
2967 }
2968
2969 static int
2970 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2971 {
2972         struct rte_ether_hdr *eth = NULL;
2973         struct rte_vlan_hdr *vlan = NULL;
2974         struct rte_ipv6_hdr *ipv6 = NULL;
2975         struct rte_udp_hdr *udp = NULL;
2976         char *next_hdr;
2977         uint16_t proto;
2978
2979         eth = (struct rte_ether_hdr *)data;
2980         next_hdr = (char *)(eth + 1);
2981         proto = RTE_BE16(eth->ether_type);
2982
2983         /* VLAN skipping */
2984         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2985                 vlan = (struct rte_vlan_hdr *)next_hdr;
2986                 proto = RTE_BE16(vlan->eth_proto);
2987                 next_hdr += sizeof(struct rte_vlan_hdr);
2988         }
2989
2990         /* HW calculates IPv4 csum. no need to proceed */
2991         if (proto == RTE_ETHER_TYPE_IPV4)
2992                 return 0;
2993
2994         /* non IPv4/IPv6 header. not supported */
2995         if (proto != RTE_ETHER_TYPE_IPV6) {
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION,
2998                                           NULL, "Cannot offload non IPv4/IPv6");
2999         }
3000
3001         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3002
3003         /* ignore non UDP */
3004         if (ipv6->proto != IPPROTO_UDP)
3005                 return 0;
3006
3007         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3008         udp->dgram_cksum = 0;
3009
3010         return 0;
3011 }
3012
3013 /**
3014  * Convert L2 encap action to DV specification.
3015  *
3016  * @param[in] dev
3017  *   Pointer to rte_eth_dev structure.
3018  * @param[in] action
3019  *   Pointer to action structure.
3020  * @param[in, out] dev_flow
3021  *   Pointer to the mlx5_flow.
3022  * @param[in] transfer
3023  *   Mark if the flow is E-Switch flow.
3024  * @param[out] error
3025  *   Pointer to the error structure.
3026  *
3027  * @return
3028  *   0 on success, a negative errno value otherwise and rte_errno is set.
3029  */
3030 static int
3031 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3032                                const struct rte_flow_action *action,
3033                                struct mlx5_flow *dev_flow,
3034                                uint8_t transfer,
3035                                struct rte_flow_error *error)
3036 {
3037         const struct rte_flow_item *encap_data;
3038         const struct rte_flow_action_raw_encap *raw_encap_data;
3039         struct mlx5_flow_dv_encap_decap_resource res = {
3040                 .reformat_type =
3041                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3042                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3043                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3044         };
3045
3046         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3047                 raw_encap_data =
3048                         (const struct rte_flow_action_raw_encap *)action->conf;
3049                 res.size = raw_encap_data->size;
3050                 memcpy(res.buf, raw_encap_data->data, res.size);
3051         } else {
3052                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3053                         encap_data =
3054                                 ((const struct rte_flow_action_vxlan_encap *)
3055                                                 action->conf)->definition;
3056                 else
3057                         encap_data =
3058                                 ((const struct rte_flow_action_nvgre_encap *)
3059                                                 action->conf)->definition;
3060                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3061                                                &res.size, error))
3062                         return -rte_errno;
3063         }
3064         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3065                 return -rte_errno;
3066         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3067                 return rte_flow_error_set(error, EINVAL,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION,
3069                                           NULL, "can't create L2 encap action");
3070         return 0;
3071 }
3072
3073 /**
3074  * Convert L2 decap action to DV specification.
3075  *
3076  * @param[in] dev
3077  *   Pointer to rte_eth_dev structure.
3078  * @param[in, out] dev_flow
3079  *   Pointer to the mlx5_flow.
3080  * @param[in] transfer
3081  *   Mark if the flow is E-Switch flow.
3082  * @param[out] error
3083  *   Pointer to the error structure.
3084  *
3085  * @return
3086  *   0 on success, a negative errno value otherwise and rte_errno is set.
3087  */
3088 static int
3089 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3090                                struct mlx5_flow *dev_flow,
3091                                uint8_t transfer,
3092                                struct rte_flow_error *error)
3093 {
3094         struct mlx5_flow_dv_encap_decap_resource res = {
3095                 .size = 0,
3096                 .reformat_type =
3097                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3098                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3099                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3100         };
3101
3102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3103                 return rte_flow_error_set(error, EINVAL,
3104                                           RTE_FLOW_ERROR_TYPE_ACTION,
3105                                           NULL, "can't create L2 decap action");
3106         return 0;
3107 }
3108
3109 /**
3110  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3111  *
3112  * @param[in] dev
3113  *   Pointer to rte_eth_dev structure.
3114  * @param[in] action
3115  *   Pointer to action structure.
3116  * @param[in, out] dev_flow
3117  *   Pointer to the mlx5_flow.
3118  * @param[in] attr
3119  *   Pointer to the flow attributes.
3120  * @param[out] error
3121  *   Pointer to the error structure.
3122  *
3123  * @return
3124  *   0 on success, a negative errno value otherwise and rte_errno is set.
3125  */
3126 static int
3127 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3128                                 const struct rte_flow_action *action,
3129                                 struct mlx5_flow *dev_flow,
3130                                 const struct rte_flow_attr *attr,
3131                                 struct rte_flow_error *error)
3132 {
3133         const struct rte_flow_action_raw_encap *encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res;
3135
3136         memset(&res, 0, sizeof(res));
3137         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3138         res.size = encap_data->size;
3139         memcpy(res.buf, encap_data->data, res.size);
3140         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3141                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3142                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3143         if (attr->transfer)
3144                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3145         else
3146                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3147                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3148         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3149                 return rte_flow_error_set(error, EINVAL,
3150                                           RTE_FLOW_ERROR_TYPE_ACTION,
3151                                           NULL, "can't create encap action");
3152         return 0;
3153 }
3154
3155 /**
3156  * Create action push VLAN.
3157  *
3158  * @param[in] dev
3159  *   Pointer to rte_eth_dev structure.
3160  * @param[in] attr
3161  *   Pointer to the flow attributes.
3162  * @param[in] vlan
3163  *   Pointer to the vlan to push to the Ethernet header.
3164  * @param[in, out] dev_flow
3165  *   Pointer to the mlx5_flow.
3166  * @param[out] error
3167  *   Pointer to the error structure.
3168  *
3169  * @return
3170  *   0 on success, a negative errno value otherwise and rte_errno is set.
3171  */
3172 static int
3173 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3174                                 const struct rte_flow_attr *attr,
3175                                 const struct rte_vlan_hdr *vlan,
3176                                 struct mlx5_flow *dev_flow,
3177                                 struct rte_flow_error *error)
3178 {
3179         struct mlx5_flow_dv_push_vlan_action_resource res;
3180
3181         memset(&res, 0, sizeof(res));
3182         res.vlan_tag =
3183                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3184                                  vlan->vlan_tci);
3185         if (attr->transfer)
3186                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3187         else
3188                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3189                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3190         return flow_dv_push_vlan_action_resource_register
3191                                             (dev, &res, dev_flow, error);
3192 }
3193
3194 /**
3195  * Validate the modify-header actions.
3196  *
3197  * @param[in] action_flags
3198  *   Holds the actions detected until now.
3199  * @param[in] action
3200  *   Pointer to the modify action.
3201  * @param[out] error
3202  *   Pointer to error structure.
3203  *
3204  * @return
3205  *   0 on success, a negative errno value otherwise and rte_errno is set.
3206  */
3207 static int
3208 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3209                                    const struct rte_flow_action *action,
3210                                    struct rte_flow_error *error)
3211 {
3212         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3213                 return rte_flow_error_set(error, EINVAL,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3215                                           NULL, "action configuration not set");
3216         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3217                 return rte_flow_error_set(error, EINVAL,
3218                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3219                                           "can't have encap action before"
3220                                           " modify action");
3221         return 0;
3222 }
3223
3224 /**
3225  * Validate the modify-header MAC address actions.
3226  *
3227  * @param[in] action_flags
3228  *   Holds the actions detected until now.
3229  * @param[in] action
3230  *   Pointer to the modify action.
3231  * @param[in] item_flags
3232  *   Holds the items detected.
3233  * @param[out] error
3234  *   Pointer to error structure.
3235  *
3236  * @return
3237  *   0 on success, a negative errno value otherwise and rte_errno is set.
3238  */
3239 static int
3240 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3241                                    const struct rte_flow_action *action,
3242                                    const uint64_t item_flags,
3243                                    struct rte_flow_error *error)
3244 {
3245         int ret = 0;
3246
3247         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3248         if (!ret) {
3249                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3250                         return rte_flow_error_set(error, EINVAL,
3251                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3252                                                   NULL,
3253                                                   "no L2 item in pattern");
3254         }
3255         return ret;
3256 }
3257
3258 /**
3259  * Validate the modify-header IPv4 address actions.
3260  *
3261  * @param[in] action_flags
3262  *   Holds the actions detected until now.
3263  * @param[in] action
3264  *   Pointer to the modify action.
3265  * @param[in] item_flags
3266  *   Holds the items detected.
3267  * @param[out] error
3268  *   Pointer to error structure.
3269  *
3270  * @return
3271  *   0 on success, a negative errno value otherwise and rte_errno is set.
3272  */
3273 static int
3274 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3275                                     const struct rte_flow_action *action,
3276                                     const uint64_t item_flags,
3277                                     struct rte_flow_error *error)
3278 {
3279         int ret = 0;
3280         uint64_t layer;
3281
3282         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3283         if (!ret) {
3284                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3285                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3286                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3287                 if (!(item_flags & layer))
3288                         return rte_flow_error_set(error, EINVAL,
3289                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3290                                                   NULL,
3291                                                   "no ipv4 item in pattern");
3292         }
3293         return ret;
3294 }
3295
3296 /**
3297  * Validate the modify-header IPv6 address actions.
3298  *
3299  * @param[in] action_flags
3300  *   Holds the actions detected until now.
3301  * @param[in] action
3302  *   Pointer to the modify action.
3303  * @param[in] item_flags
3304  *   Holds the items detected.
3305  * @param[out] error
3306  *   Pointer to error structure.
3307  *
3308  * @return
3309  *   0 on success, a negative errno value otherwise and rte_errno is set.
3310  */
3311 static int
3312 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3313                                     const struct rte_flow_action *action,
3314                                     const uint64_t item_flags,
3315                                     struct rte_flow_error *error)
3316 {
3317         int ret = 0;
3318         uint64_t layer;
3319
3320         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3321         if (!ret) {
3322                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3323                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3324                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3325                 if (!(item_flags & layer))
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "no ipv6 item in pattern");
3330         }
3331         return ret;
3332 }
3333
3334 /**
3335  * Validate the modify-header TP actions.
3336  *
3337  * @param[in] action_flags
3338  *   Holds the actions detected until now.
3339  * @param[in] action
3340  *   Pointer to the modify action.
3341  * @param[in] item_flags
3342  *   Holds the items detected.
3343  * @param[out] error
3344  *   Pointer to error structure.
3345  *
3346  * @return
3347  *   0 on success, a negative errno value otherwise and rte_errno is set.
3348  */
3349 static int
3350 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3351                                   const struct rte_flow_action *action,
3352                                   const uint64_t item_flags,
3353                                   struct rte_flow_error *error)
3354 {
3355         int ret = 0;
3356         uint64_t layer;
3357
3358         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3359         if (!ret) {
3360                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3361                                  MLX5_FLOW_LAYER_INNER_L4 :
3362                                  MLX5_FLOW_LAYER_OUTER_L4;
3363                 if (!(item_flags & layer))
3364                         return rte_flow_error_set(error, EINVAL,
3365                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3366                                                   NULL, "no transport layer "
3367                                                   "in pattern");
3368         }
3369         return ret;
3370 }
3371
3372 /**
3373  * Validate the modify-header actions of increment/decrement
3374  * TCP Sequence-number.
3375  *
3376  * @param[in] action_flags
3377  *   Holds the actions detected until now.
3378  * @param[in] action
3379  *   Pointer to the modify action.
3380  * @param[in] item_flags
3381  *   Holds the items detected.
3382  * @param[out] error
3383  *   Pointer to error structure.
3384  *
3385  * @return
3386  *   0 on success, a negative errno value otherwise and rte_errno is set.
3387  */
3388 static int
3389 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3390                                        const struct rte_flow_action *action,
3391                                        const uint64_t item_flags,
3392                                        struct rte_flow_error *error)
3393 {
3394         int ret = 0;
3395         uint64_t layer;
3396
3397         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3398         if (!ret) {
3399                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3400                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3401                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3402                 if (!(item_flags & layer))
3403                         return rte_flow_error_set(error, EINVAL,
3404                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3405                                                   NULL, "no TCP item in"
3406                                                   " pattern");
3407                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3408                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3409                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3410                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3411                         return rte_flow_error_set(error, EINVAL,
3412                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                   NULL,
3414                                                   "cannot decrease and increase"
3415                                                   " TCP sequence number"
3416                                                   " at the same time");
3417         }
3418         return ret;
3419 }
3420
3421 /**
3422  * Validate the modify-header actions of increment/decrement
3423  * TCP Acknowledgment number.
3424  *
3425  * @param[in] action_flags
3426  *   Holds the actions detected until now.
3427  * @param[in] action
3428  *   Pointer to the modify action.
3429  * @param[in] item_flags
3430  *   Holds the items detected.
3431  * @param[out] error
3432  *   Pointer to error structure.
3433  *
3434  * @return
3435  *   0 on success, a negative errno value otherwise and rte_errno is set.
3436  */
3437 static int
3438 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3439                                        const struct rte_flow_action *action,
3440                                        const uint64_t item_flags,
3441                                        struct rte_flow_error *error)
3442 {
3443         int ret = 0;
3444         uint64_t layer;
3445
3446         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447         if (!ret) {
3448                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3450                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3451                 if (!(item_flags & layer))
3452                         return rte_flow_error_set(error, EINVAL,
3453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3454                                                   NULL, "no TCP item in"
3455                                                   " pattern");
3456                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3457                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3458                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3459                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3460                         return rte_flow_error_set(error, EINVAL,
3461                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3462                                                   NULL,
3463                                                   "cannot decrease and increase"
3464                                                   " TCP acknowledgment number"
3465                                                   " at the same time");
3466         }
3467         return ret;
3468 }
3469
3470 /**
3471  * Validate the modify-header TTL actions.
3472  *
3473  * @param[in] action_flags
3474  *   Holds the actions detected until now.
3475  * @param[in] action
3476  *   Pointer to the modify action.
3477  * @param[in] item_flags
3478  *   Holds the items detected.
3479  * @param[out] error
3480  *   Pointer to error structure.
3481  *
3482  * @return
3483  *   0 on success, a negative errno value otherwise and rte_errno is set.
3484  */
3485 static int
3486 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3487                                    const struct rte_flow_action *action,
3488                                    const uint64_t item_flags,
3489                                    struct rte_flow_error *error)
3490 {
3491         int ret = 0;
3492         uint64_t layer;
3493
3494         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3495         if (!ret) {
3496                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497                                  MLX5_FLOW_LAYER_INNER_L3 :
3498                                  MLX5_FLOW_LAYER_OUTER_L3;
3499                 if (!(item_flags & layer))
3500                         return rte_flow_error_set(error, EINVAL,
3501                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3502                                                   NULL,
3503                                                   "no IP protocol in pattern");
3504         }
3505         return ret;
3506 }
3507
3508 /**
3509  * Validate jump action.
3510  *
3511  * @param[in] action
3512  *   Pointer to the jump action.
3513  * @param[in] action_flags
3514  *   Holds the actions detected until now.
3515  * @param[in] attributes
3516  *   Pointer to flow attributes
3517  * @param[in] external
3518  *   Action belongs to flow rule created by request external to PMD.
3519  * @param[out] error
3520  *   Pointer to error structure.
3521  *
3522  * @return
3523  *   0 on success, a negative errno value otherwise and rte_errno is set.
3524  */
3525 static int
3526 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3527                              uint64_t action_flags,
3528                              const struct rte_flow_attr *attributes,
3529                              bool external, struct rte_flow_error *error)
3530 {
3531         uint32_t target_group, table;
3532         int ret = 0;
3533
3534         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3535                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3536                 return rte_flow_error_set(error, EINVAL,
3537                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3538                                           "can't have 2 fate actions in"
3539                                           " same flow");
3540         if (action_flags & MLX5_FLOW_ACTION_METER)
3541                 return rte_flow_error_set(error, ENOTSUP,
3542                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3543                                           "jump with meter not support");
3544         if (!action->conf)
3545                 return rte_flow_error_set(error, EINVAL,
3546                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3547                                           NULL, "action configuration not set");
3548         target_group =
3549                 ((const struct rte_flow_action_jump *)action->conf)->group;
3550         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3551                                        true, &table, error);
3552         if (ret)
3553                 return ret;
3554         if (attributes->group == target_group)
3555                 return rte_flow_error_set(error, EINVAL,
3556                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557                                           "target group must be other than"
3558                                           " the current flow group");
3559         return 0;
3560 }
3561
3562 /*
3563  * Validate the port_id action.
3564  *
3565  * @param[in] dev
3566  *   Pointer to rte_eth_dev structure.
3567  * @param[in] action_flags
3568  *   Bit-fields that holds the actions detected until now.
3569  * @param[in] action
3570  *   Port_id RTE action structure.
3571  * @param[in] attr
3572  *   Attributes of flow that includes this action.
3573  * @param[out] error
3574  *   Pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success, a negative errno value otherwise and rte_errno is set.
3578  */
3579 static int
3580 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3581                                 uint64_t action_flags,
3582                                 const struct rte_flow_action *action,
3583                                 const struct rte_flow_attr *attr,
3584                                 struct rte_flow_error *error)
3585 {
3586         const struct rte_flow_action_port_id *port_id;
3587         struct mlx5_priv *act_priv;
3588         struct mlx5_priv *dev_priv;
3589         uint16_t port;
3590
3591         if (!attr->transfer)
3592                 return rte_flow_error_set(error, ENOTSUP,
3593                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3594                                           NULL,
3595                                           "port id action is valid in transfer"
3596                                           " mode only");
3597         if (!action || !action->conf)
3598                 return rte_flow_error_set(error, ENOTSUP,
3599                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3600                                           NULL,
3601                                           "port id action parameters must be"
3602                                           " specified");
3603         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3604                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3605                 return rte_flow_error_set(error, EINVAL,
3606                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3607                                           "can have only one fate actions in"
3608                                           " a flow");
3609         dev_priv = mlx5_dev_to_eswitch_info(dev);
3610         if (!dev_priv)
3611                 return rte_flow_error_set(error, rte_errno,
3612                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3613                                           NULL,
3614                                           "failed to obtain E-Switch info");
3615         port_id = action->conf;
3616         port = port_id->original ? dev->data->port_id : port_id->id;
3617         act_priv = mlx5_port_to_eswitch_info(port, false);
3618         if (!act_priv)
3619                 return rte_flow_error_set
3620                                 (error, rte_errno,
3621                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3622                                  "failed to obtain E-Switch port id for port");
3623         if (act_priv->domain_id != dev_priv->domain_id)
3624                 return rte_flow_error_set
3625                                 (error, EINVAL,
3626                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3627                                  "port does not belong to"
3628                                  " E-Switch being configured");
3629         return 0;
3630 }
3631
3632 /**
3633  * Get the maximum number of modify header actions.
3634  *
3635  * @param dev
3636  *   Pointer to rte_eth_dev structure.
3637  * @param flags
3638  *   Flags bits to check if root level.
3639  *
3640  * @return
3641  *   Max number of modify header actions device can support.
3642  */
3643 static inline unsigned int
3644 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3645                               uint64_t flags)
3646 {
3647         /*
3648          * There's no way to directly query the max capacity from FW.
3649          * The maximal value on root table should be assumed to be supported.
3650          */
3651         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3652                 return MLX5_MAX_MODIFY_NUM;
3653         else
3654                 return MLX5_ROOT_TBL_MODIFY_NUM;
3655 }
3656
3657 /**
3658  * Validate the meter action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Pointer to the meter action.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3673  */
3674 static int
3675 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         struct mlx5_priv *priv = dev->data->dev_private;
3682         const struct rte_flow_action_meter *am = action->conf;
3683         struct mlx5_flow_meter *fm;
3684
3685         if (!am)
3686                 return rte_flow_error_set(error, EINVAL,
3687                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3688                                           "meter action conf is NULL");
3689
3690         if (action_flags & MLX5_FLOW_ACTION_METER)
3691                 return rte_flow_error_set(error, ENOTSUP,
3692                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693                                           "meter chaining not support");
3694         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3695                 return rte_flow_error_set(error, ENOTSUP,
3696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697                                           "meter with jump not support");
3698         if (!priv->mtr_en)
3699                 return rte_flow_error_set(error, ENOTSUP,
3700                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3701                                           NULL,
3702                                           "meter action not supported");
3703         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3704         if (!fm)
3705                 return rte_flow_error_set(error, EINVAL,
3706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3707                                           "Meter not found");
3708         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3709               (!fm->ingress && !attr->ingress && attr->egress) ||
3710               (!fm->egress && !attr->egress && attr->ingress))))
3711                 return rte_flow_error_set(error, EINVAL,
3712                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3713                                           "Flow attributes are either invalid "
3714                                           "or have a conflict with current "
3715                                           "meter attributes");
3716         return 0;
3717 }
3718
3719 /**
3720  * Validate the age action.
3721  *
3722  * @param[in] action_flags
3723  *   Holds the actions detected until now.
3724  * @param[in] action
3725  *   Pointer to the age action.
3726  * @param[in] dev
3727  *   Pointer to the Ethernet device structure.
3728  * @param[out] error
3729  *   Pointer to error structure.
3730  *
3731  * @return
3732  *   0 on success, a negative errno value otherwise and rte_errno is set.
3733  */
3734 static int
3735 flow_dv_validate_action_age(uint64_t action_flags,
3736                             const struct rte_flow_action *action,
3737                             struct rte_eth_dev *dev,
3738                             struct rte_flow_error *error)
3739 {
3740         struct mlx5_priv *priv = dev->data->dev_private;
3741         const struct rte_flow_action_age *age = action->conf;
3742
3743         if (!priv->config.devx || priv->counter_fallback)
3744                 return rte_flow_error_set(error, ENOTSUP,
3745                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3746                                           NULL,
3747                                           "age action not supported");
3748         if (!(action->conf))
3749                 return rte_flow_error_set(error, EINVAL,
3750                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3751                                           "configuration cannot be null");
3752         if (age->timeout >= UINT16_MAX / 2 / 10)
3753                 return rte_flow_error_set(error, ENOTSUP,
3754                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3755                                           "Max age time: 3275 seconds");
3756         if (action_flags & MLX5_FLOW_ACTION_AGE)
3757                 return rte_flow_error_set(error, EINVAL,
3758                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3759                                           "Duplicate age ctions set");
3760         return 0;
3761 }
3762
3763 /**
3764  * Validate the modify-header IPv4 DSCP actions.
3765  *
3766  * @param[in] action_flags
3767  *   Holds the actions detected until now.
3768  * @param[in] action
3769  *   Pointer to the modify action.
3770  * @param[in] item_flags
3771  *   Holds the items detected.
3772  * @param[out] error
3773  *   Pointer to error structure.
3774  *
3775  * @return
3776  *   0 on success, a negative errno value otherwise and rte_errno is set.
3777  */
3778 static int
3779 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3780                                          const struct rte_flow_action *action,
3781                                          const uint64_t item_flags,
3782                                          struct rte_flow_error *error)
3783 {
3784         int ret = 0;
3785
3786         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3787         if (!ret) {
3788                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3789                         return rte_flow_error_set(error, EINVAL,
3790                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3791                                                   NULL,
3792                                                   "no ipv4 item in pattern");
3793         }
3794         return ret;
3795 }
3796
3797 /**
3798  * Validate the modify-header IPv6 DSCP actions.
3799  *
3800  * @param[in] action_flags
3801  *   Holds the actions detected until now.
3802  * @param[in] action
3803  *   Pointer to the modify action.
3804  * @param[in] item_flags
3805  *   Holds the items detected.
3806  * @param[out] error
3807  *   Pointer to error structure.
3808  *
3809  * @return
3810  *   0 on success, a negative errno value otherwise and rte_errno is set.
3811  */
3812 static int
3813 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3814                                          const struct rte_flow_action *action,
3815                                          const uint64_t item_flags,
3816                                          struct rte_flow_error *error)
3817 {
3818         int ret = 0;
3819
3820         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3821         if (!ret) {
3822                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3823                         return rte_flow_error_set(error, EINVAL,
3824                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3825                                                   NULL,
3826                                                   "no ipv6 item in pattern");
3827         }
3828         return ret;
3829 }
3830
3831 /**
3832  * Find existing modify-header resource or create and register a new one.
3833  *
3834  * @param dev[in, out]
3835  *   Pointer to rte_eth_dev structure.
3836  * @param[in, out] resource
3837  *   Pointer to modify-header resource.
3838  * @parm[in, out] dev_flow
3839  *   Pointer to the dev_flow.
3840  * @param[out] error
3841  *   pointer to error structure.
3842  *
3843  * @return
3844  *   0 on success otherwise -errno and errno is set.
3845  */
3846 static int
3847 flow_dv_modify_hdr_resource_register
3848                         (struct rte_eth_dev *dev,
3849                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3850                          struct mlx5_flow *dev_flow,
3851                          struct rte_flow_error *error)
3852 {
3853         struct mlx5_priv *priv = dev->data->dev_private;
3854         struct mlx5_ibv_shared *sh = priv->sh;
3855         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3856         struct mlx5dv_dr_domain *ns;
3857         uint32_t actions_len;
3858
3859         resource->flags = dev_flow->dv.group ? 0 :
3860                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3861         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3862                                     resource->flags))
3863                 return rte_flow_error_set(error, EOVERFLOW,
3864                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3865                                           "too many modify header items");
3866         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3867                 ns = sh->fdb_domain;
3868         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3869                 ns = sh->tx_domain;
3870         else
3871                 ns = sh->rx_domain;
3872         /* Lookup a matching resource from cache. */
3873         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3874         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3875                 if (resource->ft_type == cache_resource->ft_type &&
3876                     resource->actions_num == cache_resource->actions_num &&
3877                     resource->flags == cache_resource->flags &&
3878                     !memcmp((const void *)resource->actions,
3879                             (const void *)cache_resource->actions,
3880                             actions_len)) {
3881                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3882                                 (void *)cache_resource,
3883                                 rte_atomic32_read(&cache_resource->refcnt));
3884                         rte_atomic32_inc(&cache_resource->refcnt);
3885                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3886                         return 0;
3887                 }
3888         }
3889         /* Register new modify-header resource. */
3890         cache_resource = rte_calloc(__func__, 1,
3891                                     sizeof(*cache_resource) + actions_len, 0);
3892         if (!cache_resource)
3893                 return rte_flow_error_set(error, ENOMEM,
3894                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3895                                           "cannot allocate resource memory");
3896         *cache_resource = *resource;
3897         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3898         cache_resource->verbs_action =
3899                 mlx5_glue->dv_create_flow_action_modify_header
3900                                         (sh->ctx, cache_resource->ft_type, ns,
3901                                          cache_resource->flags, actions_len,
3902                                          (uint64_t *)cache_resource->actions);
3903         if (!cache_resource->verbs_action) {
3904                 rte_free(cache_resource);
3905                 return rte_flow_error_set(error, ENOMEM,
3906                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3907                                           NULL, "cannot create action");
3908         }
3909         rte_atomic32_init(&cache_resource->refcnt);
3910         rte_atomic32_inc(&cache_resource->refcnt);
3911         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3912         dev_flow->handle->dvh.modify_hdr = cache_resource;
3913         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3914                 (void *)cache_resource,
3915                 rte_atomic32_read(&cache_resource->refcnt));
3916         return 0;
3917 }
3918
3919 /**
3920  * Get DV flow counter by index.
3921  *
3922  * @param[in] dev
3923  *   Pointer to the Ethernet device structure.
3924  * @param[in] idx
3925  *   mlx5 flow counter index in the container.
3926  * @param[out] ppool
3927  *   mlx5 flow counter pool in the container,
3928  *
3929  * @return
3930  *   Pointer to the counter, NULL otherwise.
3931  */
3932 static struct mlx5_flow_counter *
3933 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3934                            uint32_t idx,
3935                            struct mlx5_flow_counter_pool **ppool)
3936 {
3937         struct mlx5_priv *priv = dev->data->dev_private;
3938         struct mlx5_pools_container *cont;
3939         struct mlx5_flow_counter_pool *pool;
3940         uint32_t batch = 0, age = 0;
3941
3942         idx--;
3943         age = MLX_CNT_IS_AGE(idx);
3944         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
3945         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3946                 idx -= MLX5_CNT_BATCH_OFFSET;
3947                 batch = 1;
3948         }
3949         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
3950         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3951         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3952         MLX5_ASSERT(pool);
3953         if (ppool)
3954                 *ppool = pool;
3955         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
3956 }
3957
3958 /**
3959  * Get a pool by devx counter ID.
3960  *
3961  * @param[in] cont
3962  *   Pointer to the counter container.
3963  * @param[in] id
3964  *   The counter devx ID.
3965  *
3966  * @return
3967  *   The counter pool pointer if exists, NULL otherwise,
3968  */
3969 static struct mlx5_flow_counter_pool *
3970 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3971 {
3972         uint32_t i;
3973         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3974
3975         for (i = 0; i < n_valid; i++) {
3976                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3977                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3978                            MLX5_COUNTERS_PER_POOL;
3979
3980                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3981                         /*
3982                          * Move the pool to the head, as counter allocate
3983                          * always gets the first pool in the container.
3984                          */
3985                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3986                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3987                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3988                         }
3989                         return pool;
3990                 }
3991         }
3992         return NULL;
3993 }
3994
3995 /**
3996  * Allocate a new memory for the counter values wrapped by all the needed
3997  * management.
3998  *
3999  * @param[in] dev
4000  *   Pointer to the Ethernet device structure.
4001  * @param[in] raws_n
4002  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4003  *
4004  * @return
4005  *   The new memory management pointer on success, otherwise NULL and rte_errno
4006  *   is set.
4007  */
4008 static struct mlx5_counter_stats_mem_mng *
4009 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4010 {
4011         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4012                                         (dev->data->dev_private))->sh;
4013         struct mlx5_devx_mkey_attr mkey_attr;
4014         struct mlx5_counter_stats_mem_mng *mem_mng;
4015         volatile struct flow_counter_stats *raw_data;
4016         int size = (sizeof(struct flow_counter_stats) *
4017                         MLX5_COUNTERS_PER_POOL +
4018                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4019                         sizeof(struct mlx5_counter_stats_mem_mng);
4020         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4021         int i;
4022
4023         if (!mem) {
4024                 rte_errno = ENOMEM;
4025                 return NULL;
4026         }
4027         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4028         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4029         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4030                                                  IBV_ACCESS_LOCAL_WRITE);
4031         if (!mem_mng->umem) {
4032                 rte_errno = errno;
4033                 rte_free(mem);
4034                 return NULL;
4035         }
4036         mkey_attr.addr = (uintptr_t)mem;
4037         mkey_attr.size = size;
4038         mkey_attr.umem_id = mem_mng->umem->umem_id;
4039         mkey_attr.pd = sh->pdn;
4040         mkey_attr.log_entity_size = 0;
4041         mkey_attr.pg_access = 0;
4042         mkey_attr.klm_array = NULL;
4043         mkey_attr.klm_num = 0;
4044         mkey_attr.relaxed_ordering = 1;
4045         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4046         if (!mem_mng->dm) {
4047                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4048                 rte_errno = errno;
4049                 rte_free(mem);
4050                 return NULL;
4051         }
4052         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4053         raw_data = (volatile struct flow_counter_stats *)mem;
4054         for (i = 0; i < raws_n; ++i) {
4055                 mem_mng->raws[i].mem_mng = mem_mng;
4056                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4057         }
4058         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4059         return mem_mng;
4060 }
4061
4062 /**
4063  * Resize a counter container.
4064  *
4065  * @param[in] dev
4066  *   Pointer to the Ethernet device structure.
4067  * @param[in] batch
4068  *   Whether the pool is for counter that was allocated by batch command.
4069  * @param[in] age
4070  *   Whether the pool is for Aging counter.
4071  *
4072  * @return
4073  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4074  */
4075 static struct mlx5_pools_container *
4076 flow_dv_container_resize(struct rte_eth_dev *dev,
4077                                 uint32_t batch, uint32_t age)
4078 {
4079         struct mlx5_priv *priv = dev->data->dev_private;
4080         struct mlx5_pools_container *cont =
4081                         MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4082         struct mlx5_pools_container *new_cont =
4083                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4084         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4085         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4086         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4087         int i;
4088
4089         /* Fallback mode has no background thread. Skip the check. */
4090         if (!priv->counter_fallback &&
4091             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4092                 /* The last resize still hasn't detected by the host thread. */
4093                 rte_errno = EAGAIN;
4094                 return NULL;
4095         }
4096         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4097         if (!new_cont->pools) {
4098                 rte_errno = ENOMEM;
4099                 return NULL;
4100         }
4101         if (cont->n)
4102                 memcpy(new_cont->pools, cont->pools, cont->n *
4103                        sizeof(struct mlx5_flow_counter_pool *));
4104         /*
4105          * Fallback mode query the counter directly, no background query
4106          * resources are needed.
4107          */
4108         if (!priv->counter_fallback) {
4109                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4110                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4111                 if (!mem_mng) {
4112                         rte_free(new_cont->pools);
4113                         return NULL;
4114                 }
4115                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4116                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4117                                          mem_mng->raws +
4118                                          MLX5_CNT_CONTAINER_RESIZE +
4119                                          i, next);
4120         } else {
4121                 /*
4122                  * Release the old container pools directly as no background
4123                  * thread helps that.
4124                  */
4125                 rte_free(cont->pools);
4126         }
4127         new_cont->n = resize;
4128         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4129         TAILQ_INIT(&new_cont->pool_list);
4130         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4131         new_cont->init_mem_mng = mem_mng;
4132         rte_cio_wmb();
4133          /* Flip the master container. */
4134         priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4135         return new_cont;
4136 }
4137
4138 /**
4139  * Query a devx flow counter.
4140  *
4141  * @param[in] dev
4142  *   Pointer to the Ethernet device structure.
4143  * @param[in] cnt
4144  *   Index to the flow counter.
4145  * @param[out] pkts
4146  *   The statistics value of packets.
4147  * @param[out] bytes
4148  *   The statistics value of bytes.
4149  *
4150  * @return
4151  *   0 on success, otherwise a negative errno value and rte_errno is set.
4152  */
4153 static inline int
4154 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4155                      uint64_t *bytes)
4156 {
4157         struct mlx5_priv *priv = dev->data->dev_private;
4158         struct mlx5_flow_counter_pool *pool = NULL;
4159         struct mlx5_flow_counter *cnt;
4160         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4161         int offset;
4162
4163         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4164         MLX5_ASSERT(pool);
4165         if (counter < MLX5_CNT_BATCH_OFFSET) {
4166                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4167                 if (priv->counter_fallback)
4168                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4169                                         0, pkts, bytes, 0, NULL, NULL, 0);
4170         }
4171
4172         rte_spinlock_lock(&pool->sl);
4173         /*
4174          * The single counters allocation may allocate smaller ID than the
4175          * current allocated in parallel to the host reading.
4176          * In this case the new counter values must be reported as 0.
4177          */
4178         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4179                 *pkts = 0;
4180                 *bytes = 0;
4181         } else {
4182                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4183                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4184                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4185         }
4186         rte_spinlock_unlock(&pool->sl);
4187         return 0;
4188 }
4189
4190 /**
4191  * Create and initialize a new counter pool.
4192  *
4193  * @param[in] dev
4194  *   Pointer to the Ethernet device structure.
4195  * @param[out] dcs
4196  *   The devX counter handle.
4197  * @param[in] batch
4198  *   Whether the pool is for counter that was allocated by batch command.
4199  * @param[in] age
4200  *   Whether the pool is for counter that was allocated for aging.
4201  * @param[in/out] cont_cur
4202  *   Pointer to the container pointer, it will be update in pool resize.
4203  *
4204  * @return
4205  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4206  */
4207 static struct mlx5_pools_container *
4208 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4209                     uint32_t batch, uint32_t age)
4210 {
4211         struct mlx5_priv *priv = dev->data->dev_private;
4212         struct mlx5_flow_counter_pool *pool;
4213         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4214                                                                0, age);
4215         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4216         uint32_t size = sizeof(*pool);
4217
4218         if (cont->n == n_valid) {
4219                 cont = flow_dv_container_resize(dev, batch, age);
4220                 if (!cont)
4221                         return NULL;
4222         }
4223         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4224         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4225         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4226         pool = rte_calloc(__func__, 1, size, 0);
4227         if (!pool) {
4228                 rte_errno = ENOMEM;
4229                 return NULL;
4230         }
4231         pool->min_dcs = dcs;
4232         if (!priv->counter_fallback)
4233                 pool->raw = cont->init_mem_mng->raws + n_valid %
4234                                                      MLX5_CNT_CONTAINER_RESIZE;
4235         pool->raw_hw = NULL;
4236         pool->type = 0;
4237         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4238         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4239         rte_spinlock_init(&pool->sl);
4240         /*
4241          * The generation of the new allocated counters in this pool is 0, 2 in
4242          * the pool generation makes all the counters valid for allocation.
4243          * The start and end query generation protect the counters be released
4244          * between the query and update gap period will not be reallocated
4245          * without the last query finished and stats updated to the memory.
4246          */
4247         rte_atomic64_set(&pool->start_query_gen, 0x2);
4248         /*
4249          * There's no background query thread for fallback mode, set the
4250          * end_query_gen to the maximum value since no need to wait for
4251          * statistics update.
4252          */
4253         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4254                          INT64_MAX : 0x2);
4255         TAILQ_INIT(&pool->counters);
4256         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4257         pool->index = n_valid;
4258         cont->pools[n_valid] = pool;
4259         /* Pool initialization must be updated before host thread access. */
4260         rte_cio_wmb();
4261         rte_atomic16_add(&cont->n_valid, 1);
4262         return cont;
4263 }
4264
4265 /**
4266  * Update the minimum dcs-id for aged or no-aged counter pool.
4267  *
4268  * @param[in] dev
4269  *   Pointer to the Ethernet device structure.
4270  * @param[in] pool
4271  *   Current counter pool.
4272  * @param[in] batch
4273  *   Whether the pool is for counter that was allocated by batch command.
4274  * @param[in] age
4275  *   Whether the counter is for aging.
4276  */
4277 static void
4278 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4279                         struct mlx5_flow_counter_pool *pool,
4280                         uint32_t batch, uint32_t age)
4281 {
4282         struct mlx5_priv *priv = dev->data->dev_private;
4283         struct mlx5_flow_counter_pool *other;
4284         struct mlx5_pools_container *cont;
4285
4286         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4287         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4288         if (!other)
4289                 return;
4290         if (pool->min_dcs->id < other->min_dcs->id) {
4291                 rte_atomic64_set(&other->a64_dcs,
4292                         rte_atomic64_read(&pool->a64_dcs));
4293         } else {
4294                 rte_atomic64_set(&pool->a64_dcs,
4295                         rte_atomic64_read(&other->a64_dcs));
4296         }
4297 }
4298 /**
4299  * Prepare a new counter and/or a new counter pool.
4300  *
4301  * @param[in] dev
4302  *   Pointer to the Ethernet device structure.
4303  * @param[out] cnt_free
4304  *   Where to put the pointer of a new counter.
4305  * @param[in] batch
4306  *   Whether the pool is for counter that was allocated by batch command.
4307  * @param[in] age
4308  *   Whether the pool is for counter that was allocated for aging.
4309  *
4310  * @return
4311  *   The counter container pointer and @p cnt_free is set on success,
4312  *   NULL otherwise and rte_errno is set.
4313  */
4314 static struct mlx5_pools_container *
4315 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4316                              struct mlx5_flow_counter **cnt_free,
4317                              uint32_t batch, uint32_t age)
4318 {
4319         struct mlx5_priv *priv = dev->data->dev_private;
4320         struct mlx5_pools_container *cont;
4321         struct mlx5_flow_counter_pool *pool;
4322         struct mlx5_devx_obj *dcs = NULL;
4323         struct mlx5_flow_counter *cnt;
4324         uint32_t i;
4325
4326         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4327         if (!batch) {
4328                 /* bulk_bitmap must be 0 for single counter allocation. */
4329                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4330                 if (!dcs)
4331                         return NULL;
4332                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4333                 if (!pool) {
4334                         cont = flow_dv_pool_create(dev, dcs, batch, age);
4335                         if (!cont) {
4336                                 mlx5_devx_cmd_destroy(dcs);
4337                                 return NULL;
4338                         }
4339                         pool = TAILQ_FIRST(&cont->pool_list);
4340                 } else if (dcs->id < pool->min_dcs->id) {
4341                         rte_atomic64_set(&pool->a64_dcs,
4342                                          (int64_t)(uintptr_t)dcs);
4343                 }
4344                 flow_dv_counter_update_min_dcs(dev,
4345                                                 pool, batch, age);
4346                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4347                 cnt = MLX5_POOL_GET_CNT(pool, i);
4348                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4349                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4350                 *cnt_free = cnt;
4351                 return cont;
4352         }
4353         /* bulk_bitmap is in 128 counters units. */
4354         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4355                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4356         if (!dcs) {
4357                 rte_errno = ENODATA;
4358                 return NULL;
4359         }
4360         cont = flow_dv_pool_create(dev, dcs, batch, age);
4361         if (!cont) {
4362                 mlx5_devx_cmd_destroy(dcs);
4363                 return NULL;
4364         }
4365         pool = TAILQ_FIRST(&cont->pool_list);
4366         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4367                 cnt = MLX5_POOL_GET_CNT(pool, i);
4368                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4369         }
4370         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4371         return cont;
4372 }
4373
4374 /**
4375  * Search for existed shared counter.
4376  *
4377  * @param[in] cont
4378  *   Pointer to the relevant counter pool container.
4379  * @param[in] id
4380  *   The shared counter ID to search.
4381  * @param[out] ppool
4382  *   mlx5 flow counter pool in the container,
4383  *
4384  * @return
4385  *   NULL if not existed, otherwise pointer to the shared extend counter.
4386  */
4387 static struct mlx5_flow_counter_ext *
4388 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4389                               struct mlx5_flow_counter_pool **ppool)
4390 {
4391         static struct mlx5_flow_counter_ext *cnt;
4392         struct mlx5_flow_counter_pool *pool;
4393         uint32_t i;
4394         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4395
4396         for (i = 0; i < n_valid; i++) {
4397                 pool = cont->pools[i];
4398                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4399                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4400                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4401                                 if (ppool)
4402                                         *ppool = cont->pools[i];
4403                                 return cnt;
4404                         }
4405                 }
4406         }
4407         return NULL;
4408 }
4409
4410 /**
4411  * Allocate a flow counter.
4412  *
4413  * @param[in] dev
4414  *   Pointer to the Ethernet device structure.
4415  * @param[in] shared
4416  *   Indicate if this counter is shared with other flows.
4417  * @param[in] id
4418  *   Counter identifier.
4419  * @param[in] group
4420  *   Counter flow group.
4421  * @param[in] age
4422  *   Whether the counter was allocated for aging.
4423  *
4424  * @return
4425  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4426  */
4427 static uint32_t
4428 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4429                       uint16_t group, uint32_t age)
4430 {
4431         struct mlx5_priv *priv = dev->data->dev_private;
4432         struct mlx5_flow_counter_pool *pool = NULL;
4433         struct mlx5_flow_counter *cnt_free = NULL;
4434         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4435         /*
4436          * Currently group 0 flow counter cannot be assigned to a flow if it is
4437          * not the first one in the batch counter allocation, so it is better
4438          * to allocate counters one by one for these flows in a separate
4439          * container.
4440          * A counter can be shared between different groups so need to take
4441          * shared counters from the single container.
4442          */
4443         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4444         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4445                                                                0, age);
4446         uint32_t cnt_idx;
4447
4448         if (!priv->config.devx) {
4449                 rte_errno = ENOTSUP;
4450                 return 0;
4451         }
4452         if (shared) {
4453                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4454                 if (cnt_ext) {
4455                         if (cnt_ext->ref_cnt + 1 == 0) {
4456                                 rte_errno = E2BIG;
4457                                 return 0;
4458                         }
4459                         cnt_ext->ref_cnt++;
4460                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4461                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4462                                   + 1;
4463                         return cnt_idx;
4464                 }
4465         }
4466         /* Pools which has a free counters are in the start. */
4467         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4468                 /*
4469                  * The free counter reset values must be updated between the
4470                  * counter release to the counter allocation, so, at least one
4471                  * query must be done in this time. ensure it by saving the
4472                  * query generation in the release time.
4473                  * The free list is sorted according to the generation - so if
4474                  * the first one is not updated, all the others are not
4475                  * updated too.
4476                  */
4477                 cnt_free = TAILQ_FIRST(&pool->counters);
4478                 if (cnt_free && cnt_free->query_gen <
4479                     rte_atomic64_read(&pool->end_query_gen))
4480                         break;
4481                 cnt_free = NULL;
4482         }
4483         if (!cnt_free) {
4484                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4485                 if (!cont)
4486                         return 0;
4487                 pool = TAILQ_FIRST(&cont->pool_list);
4488         }
4489         if (!batch)
4490                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4491         /* Create a DV counter action only in the first time usage. */
4492         if (!cnt_free->action) {
4493                 uint16_t offset;
4494                 struct mlx5_devx_obj *dcs;
4495
4496                 if (batch) {
4497                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4498                         dcs = pool->min_dcs;
4499                 } else {
4500                         offset = 0;
4501                         dcs = cnt_ext->dcs;
4502                 }
4503                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4504                                         (dcs->obj, offset);
4505                 if (!cnt_free->action) {
4506                         rte_errno = errno;
4507                         return 0;
4508                 }
4509         }
4510         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4511                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4512         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4513         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4514         /* Update the counter reset values. */
4515         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4516                                  &cnt_free->bytes))
4517                 return 0;
4518         if (cnt_ext) {
4519                 cnt_ext->shared = shared;
4520                 cnt_ext->ref_cnt = 1;
4521                 cnt_ext->id = id;
4522         }
4523         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4524                 /* Start the asynchronous batch query by the host thread. */
4525                 mlx5_set_query_alarm(priv->sh);
4526         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4527         if (TAILQ_EMPTY(&pool->counters)) {
4528                 /* Move the pool to the end of the container pool list. */
4529                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4530                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4531         }
4532         return cnt_idx;
4533 }
4534
4535 /**
4536  * Get age param from counter index.
4537  *
4538  * @param[in] dev
4539  *   Pointer to the Ethernet device structure.
4540  * @param[in] counter
4541  *   Index to the counter handler.
4542  *
4543  * @return
4544  *   The aging parameter specified for the counter index.
4545  */
4546 static struct mlx5_age_param*
4547 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4548                                 uint32_t counter)
4549 {
4550         struct mlx5_flow_counter *cnt;
4551         struct mlx5_flow_counter_pool *pool = NULL;
4552
4553         flow_dv_counter_get_by_idx(dev, counter, &pool);
4554         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4555         cnt = MLX5_POOL_GET_CNT(pool, counter);
4556         return MLX5_CNT_TO_AGE(cnt);
4557 }
4558
4559 /**
4560  * Remove a flow counter from aged counter list.
4561  *
4562  * @param[in] dev
4563  *   Pointer to the Ethernet device structure.
4564  * @param[in] counter
4565  *   Index to the counter handler.
4566  * @param[in] cnt
4567  *   Pointer to the counter handler.
4568  */
4569 static void
4570 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4571                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4572 {
4573         struct mlx5_age_info *age_info;
4574         struct mlx5_age_param *age_param;
4575         struct mlx5_priv *priv = dev->data->dev_private;
4576
4577         age_info = GET_PORT_AGE_INFO(priv);
4578         age_param = flow_dv_counter_idx_get_age(dev, counter);
4579         if (rte_atomic16_cmpset((volatile uint16_t *)
4580                         &age_param->state,
4581                         AGE_CANDIDATE, AGE_FREE)
4582                         != AGE_CANDIDATE) {
4583                 /**
4584                  * We need the lock even it is age timeout,
4585                  * since counter may still in process.
4586                  */
4587                 rte_spinlock_lock(&age_info->aged_sl);
4588                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4589                 rte_spinlock_unlock(&age_info->aged_sl);
4590         }
4591         rte_atomic16_set(&age_param->state, AGE_FREE);
4592 }
4593 /**
4594  * Release a flow counter.
4595  *
4596  * @param[in] dev
4597  *   Pointer to the Ethernet device structure.
4598  * @param[in] counter
4599  *   Index to the counter handler.
4600  */
4601 static void
4602 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4603 {
4604         struct mlx5_flow_counter_pool *pool = NULL;
4605         struct mlx5_flow_counter *cnt;
4606         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4607
4608         if (!counter)
4609                 return;
4610         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4611         MLX5_ASSERT(pool);
4612         if (counter < MLX5_CNT_BATCH_OFFSET) {
4613                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4614                 if (cnt_ext && --cnt_ext->ref_cnt)
4615                         return;
4616         }
4617         if (IS_AGE_POOL(pool))
4618                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4619         /* Put the counter in the end - the last updated one. */
4620         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4621         /*
4622          * Counters released between query trigger and handler need
4623          * to wait the next round of query. Since the packets arrive
4624          * in the gap period will not be taken into account to the
4625          * old counter.
4626          */
4627         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4628 }
4629
4630 /**
4631  * Verify the @p attributes will be correctly understood by the NIC and store
4632  * them in the @p flow if everything is correct.
4633  *
4634  * @param[in] dev
4635  *   Pointer to dev struct.
4636  * @param[in] attributes
4637  *   Pointer to flow attributes
4638  * @param[in] external
4639  *   This flow rule is created by request external to PMD.
4640  * @param[out] error
4641  *   Pointer to error structure.
4642  *
4643  * @return
4644  *   - 0 on success and non root table.
4645  *   - 1 on success and root table.
4646  *   - a negative errno value otherwise and rte_errno is set.
4647  */
4648 static int
4649 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4650                             const struct rte_flow_attr *attributes,
4651                             bool external __rte_unused,
4652                             struct rte_flow_error *error)
4653 {
4654         struct mlx5_priv *priv = dev->data->dev_private;
4655         uint32_t priority_max = priv->config.flow_prio - 1;
4656         int ret = 0;
4657
4658 #ifndef HAVE_MLX5DV_DR
4659         if (attributes->group)
4660                 return rte_flow_error_set(error, ENOTSUP,
4661                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4662                                           NULL,
4663                                           "groups are not supported");
4664 #else
4665         uint32_t table = 0;
4666
4667         ret = mlx5_flow_group_to_table(attributes, external,
4668                                        attributes->group, !!priv->fdb_def_rule,
4669                                        &table, error);
4670         if (ret)
4671                 return ret;
4672         if (!table)
4673                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4674 #endif
4675         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4676             attributes->priority >= priority_max)
4677                 return rte_flow_error_set(error, ENOTSUP,
4678                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4679                                           NULL,
4680                                           "priority out of range");
4681         if (attributes->transfer) {
4682                 if (!priv->config.dv_esw_en)
4683                         return rte_flow_error_set
4684                                 (error, ENOTSUP,
4685                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4686                                  "E-Switch dr is not supported");
4687                 if (!(priv->representor || priv->master))
4688                         return rte_flow_error_set
4689                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4690                                  NULL, "E-Switch configuration can only be"
4691                                  " done by a master or a representor device");
4692                 if (attributes->egress)
4693                         return rte_flow_error_set
4694                                 (error, ENOTSUP,
4695                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4696                                  "egress is not supported");
4697         }
4698         if (!(attributes->egress ^ attributes->ingress))
4699                 return rte_flow_error_set(error, ENOTSUP,
4700                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4701                                           "must specify exactly one of "
4702                                           "ingress or egress");
4703         return ret;
4704 }
4705
4706 /**
4707  * Internal validation function. For validating both actions and items.
4708  *
4709  * @param[in] dev
4710  *   Pointer to the rte_eth_dev structure.
4711  * @param[in] attr
4712  *   Pointer to the flow attributes.
4713  * @param[in] items
4714  *   Pointer to the list of items.
4715  * @param[in] actions
4716  *   Pointer to the list of actions.
4717  * @param[in] external
4718  *   This flow rule is created by request external to PMD.
4719  * @param[in] hairpin
4720  *   Number of hairpin TX actions, 0 means classic flow.
4721  * @param[out] error
4722  *   Pointer to the error structure.
4723  *
4724  * @return
4725  *   0 on success, a negative errno value otherwise and rte_errno is set.
4726  */
4727 static int
4728 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4729                  const struct rte_flow_item items[],
4730                  const struct rte_flow_action actions[],
4731                  bool external, int hairpin, struct rte_flow_error *error)
4732 {
4733         int ret;
4734         uint64_t action_flags = 0;
4735         uint64_t item_flags = 0;
4736         uint64_t last_item = 0;
4737         uint8_t next_protocol = 0xff;
4738         uint16_t ether_type = 0;
4739         int actions_n = 0;
4740         uint8_t item_ipv6_proto = 0;
4741         const struct rte_flow_item *gre_item = NULL;
4742         const struct rte_flow_action_raw_decap *decap;
4743         const struct rte_flow_action_raw_encap *encap;
4744         const struct rte_flow_action_rss *rss;
4745         const struct rte_flow_item_tcp nic_tcp_mask = {
4746                 .hdr = {
4747                         .tcp_flags = 0xFF,
4748                         .src_port = RTE_BE16(UINT16_MAX),
4749                         .dst_port = RTE_BE16(UINT16_MAX),
4750                 }
4751         };
4752         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4753                 .hdr = {
4754                         .src_addr = RTE_BE32(0xffffffff),
4755                         .dst_addr = RTE_BE32(0xffffffff),
4756                         .type_of_service = 0xff,
4757                         .next_proto_id = 0xff,
4758                         .time_to_live = 0xff,
4759                 },
4760         };
4761         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4762                 .hdr = {
4763                         .src_addr =
4764                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4765                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4766                         .dst_addr =
4767                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4768                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4769                         .vtc_flow = RTE_BE32(0xffffffff),
4770                         .proto = 0xff,
4771                         .hop_limits = 0xff,
4772                 },
4773         };
4774         struct mlx5_priv *priv = dev->data->dev_private;
4775         struct mlx5_dev_config *dev_conf = &priv->config;
4776         uint16_t queue_index = 0xFFFF;
4777         const struct rte_flow_item_vlan *vlan_m = NULL;
4778         int16_t rw_act_num = 0;
4779         uint64_t is_root;
4780
4781         if (items == NULL)
4782                 return -1;
4783         ret = flow_dv_validate_attributes(dev, attr, external, error);
4784         if (ret < 0)
4785                 return ret;
4786         is_root = (uint64_t)ret;
4787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4788                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4789                 int type = items->type;
4790
4791                 switch (type) {
4792                 case RTE_FLOW_ITEM_TYPE_VOID:
4793                         break;
4794                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4795                         ret = flow_dv_validate_item_port_id
4796                                         (dev, items, attr, item_flags, error);
4797                         if (ret < 0)
4798                                 return ret;
4799                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4800                         break;
4801                 case RTE_FLOW_ITEM_TYPE_ETH:
4802                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4803                                                           error);
4804                         if (ret < 0)
4805                                 return ret;
4806                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4807                                              MLX5_FLOW_LAYER_OUTER_L2;
4808                         if (items->mask != NULL && items->spec != NULL) {
4809                                 ether_type =
4810                                         ((const struct rte_flow_item_eth *)
4811                                          items->spec)->type;
4812                                 ether_type &=
4813                                         ((const struct rte_flow_item_eth *)
4814                                          items->mask)->type;
4815                                 ether_type = rte_be_to_cpu_16(ether_type);
4816                         } else {
4817                                 ether_type = 0;
4818                         }
4819                         break;
4820                 case RTE_FLOW_ITEM_TYPE_VLAN:
4821                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4822                                                            dev, error);
4823                         if (ret < 0)
4824                                 return ret;
4825                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4826                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4827                         if (items->mask != NULL && items->spec != NULL) {
4828                                 ether_type =
4829                                         ((const struct rte_flow_item_vlan *)
4830                                          items->spec)->inner_type;
4831                                 ether_type &=
4832                                         ((const struct rte_flow_item_vlan *)
4833                                          items->mask)->inner_type;
4834                                 ether_type = rte_be_to_cpu_16(ether_type);
4835                         } else {
4836                                 ether_type = 0;
4837                         }
4838                         /* Store outer VLAN mask for of_push_vlan action. */
4839                         if (!tunnel)
4840                                 vlan_m = items->mask;
4841                         break;
4842                 case RTE_FLOW_ITEM_TYPE_IPV4:
4843                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4844                                                   &item_flags, &tunnel);
4845                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4846                                                            last_item,
4847                                                            ether_type,
4848                                                            &nic_ipv4_mask,
4849                                                            error);
4850                         if (ret < 0)
4851                                 return ret;
4852                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4853                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4854                         if (items->mask != NULL &&
4855                             ((const struct rte_flow_item_ipv4 *)
4856                              items->mask)->hdr.next_proto_id) {
4857                                 next_protocol =
4858                                         ((const struct rte_flow_item_ipv4 *)
4859                                          (items->spec))->hdr.next_proto_id;
4860                                 next_protocol &=
4861                                         ((const struct rte_flow_item_ipv4 *)
4862                                          (items->mask))->hdr.next_proto_id;
4863                         } else {
4864                                 /* Reset for inner layer. */
4865                                 next_protocol = 0xff;
4866                         }
4867                         break;
4868                 case RTE_FLOW_ITEM_TYPE_IPV6:
4869                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4870                                                   &item_flags, &tunnel);
4871                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4872                                                            last_item,
4873                                                            ether_type,
4874                                                            &nic_ipv6_mask,
4875                                                            error);
4876                         if (ret < 0)
4877                                 return ret;
4878                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4879                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4880                         if (items->mask != NULL &&
4881                             ((const struct rte_flow_item_ipv6 *)
4882                              items->mask)->hdr.proto) {
4883                                 item_ipv6_proto =
4884                                         ((const struct rte_flow_item_ipv6 *)
4885                                          items->spec)->hdr.proto;
4886                                 next_protocol =
4887                                         ((const struct rte_flow_item_ipv6 *)
4888                                          items->spec)->hdr.proto;
4889                                 next_protocol &=
4890                                         ((const struct rte_flow_item_ipv6 *)
4891                                          items->mask)->hdr.proto;
4892                         } else {
4893                                 /* Reset for inner layer. */
4894                                 next_protocol = 0xff;
4895                         }
4896                         break;
4897                 case RTE_FLOW_ITEM_TYPE_TCP:
4898                         ret = mlx5_flow_validate_item_tcp
4899                                                 (items, item_flags,
4900                                                  next_protocol,
4901                                                  &nic_tcp_mask,
4902                                                  error);
4903                         if (ret < 0)
4904                                 return ret;
4905                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4906                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4907                         break;
4908                 case RTE_FLOW_ITEM_TYPE_UDP:
4909                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4910                                                           next_protocol,
4911                                                           error);
4912                         if (ret < 0)
4913                                 return ret;
4914                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4915                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4916                         break;
4917                 case RTE_FLOW_ITEM_TYPE_GRE:
4918                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4919                                                           next_protocol, error);
4920                         if (ret < 0)
4921                                 return ret;
4922                         gre_item = items;
4923                         last_item = MLX5_FLOW_LAYER_GRE;
4924                         break;
4925                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4926                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4927                                                             next_protocol,
4928                                                             error);
4929                         if (ret < 0)
4930                                 return ret;
4931                         last_item = MLX5_FLOW_LAYER_NVGRE;
4932                         break;
4933                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4934                         ret = mlx5_flow_validate_item_gre_key
4935                                 (items, item_flags, gre_item, error);
4936                         if (ret < 0)
4937                                 return ret;
4938                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4939                         break;
4940                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4941                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4942                                                             error);
4943                         if (ret < 0)
4944                                 return ret;
4945                         last_item = MLX5_FLOW_LAYER_VXLAN;
4946                         break;
4947                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4948                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4949                                                                 item_flags, dev,
4950                                                                 error);
4951                         if (ret < 0)
4952                                 return ret;
4953                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4954                         break;
4955                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4956                         ret = mlx5_flow_validate_item_geneve(items,
4957                                                              item_flags, dev,
4958                                                              error);
4959                         if (ret < 0)
4960                                 return ret;
4961                         last_item = MLX5_FLOW_LAYER_GENEVE;
4962                         break;
4963                 case RTE_FLOW_ITEM_TYPE_MPLS:
4964                         ret = mlx5_flow_validate_item_mpls(dev, items,
4965                                                            item_flags,
4966                                                            last_item, error);
4967                         if (ret < 0)
4968                                 return ret;
4969                         last_item = MLX5_FLOW_LAYER_MPLS;
4970                         break;
4971
4972                 case RTE_FLOW_ITEM_TYPE_MARK:
4973                         ret = flow_dv_validate_item_mark(dev, items, attr,
4974                                                          error);
4975                         if (ret < 0)
4976                                 return ret;
4977                         last_item = MLX5_FLOW_ITEM_MARK;
4978                         break;
4979                 case RTE_FLOW_ITEM_TYPE_META:
4980                         ret = flow_dv_validate_item_meta(dev, items, attr,
4981                                                          error);
4982                         if (ret < 0)
4983                                 return ret;
4984                         last_item = MLX5_FLOW_ITEM_METADATA;
4985                         break;
4986                 case RTE_FLOW_ITEM_TYPE_ICMP:
4987                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4988                                                            next_protocol,
4989                                                            error);
4990                         if (ret < 0)
4991                                 return ret;
4992                         last_item = MLX5_FLOW_LAYER_ICMP;
4993                         break;
4994                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4995                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4996                                                             next_protocol,
4997                                                             error);
4998                         if (ret < 0)
4999                                 return ret;
5000                         item_ipv6_proto = IPPROTO_ICMPV6;
5001                         last_item = MLX5_FLOW_LAYER_ICMP6;
5002                         break;
5003                 case RTE_FLOW_ITEM_TYPE_TAG:
5004                         ret = flow_dv_validate_item_tag(dev, items,
5005                                                         attr, error);
5006                         if (ret < 0)
5007                                 return ret;
5008                         last_item = MLX5_FLOW_ITEM_TAG;
5009                         break;
5010                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5011                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5012                         break;
5013                 case RTE_FLOW_ITEM_TYPE_GTP:
5014                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5015                                                         error);
5016                         if (ret < 0)
5017                                 return ret;
5018                         last_item = MLX5_FLOW_LAYER_GTP;
5019                         break;
5020                 default:
5021                         return rte_flow_error_set(error, ENOTSUP,
5022                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5023                                                   NULL, "item not supported");
5024                 }
5025                 item_flags |= last_item;
5026         }
5027         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5028                 int type = actions->type;
5029                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5030                         return rte_flow_error_set(error, ENOTSUP,
5031                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5032                                                   actions, "too many actions");
5033                 switch (type) {
5034                 case RTE_FLOW_ACTION_TYPE_VOID:
5035                         break;
5036                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5037                         ret = flow_dv_validate_action_port_id(dev,
5038                                                               action_flags,
5039                                                               actions,
5040                                                               attr,
5041                                                               error);
5042                         if (ret)
5043                                 return ret;
5044                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5045                         ++actions_n;
5046                         break;
5047                 case RTE_FLOW_ACTION_TYPE_FLAG:
5048                         ret = flow_dv_validate_action_flag(dev, action_flags,
5049                                                            attr, error);
5050                         if (ret < 0)
5051                                 return ret;
5052                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5053                                 /* Count all modify-header actions as one. */
5054                                 if (!(action_flags &
5055                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5056                                         ++actions_n;
5057                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5058                                                 MLX5_FLOW_ACTION_MARK_EXT;
5059                         } else {
5060                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5061                                 ++actions_n;
5062                         }
5063                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5064                         break;
5065                 case RTE_FLOW_ACTION_TYPE_MARK:
5066                         ret = flow_dv_validate_action_mark(dev, actions,
5067                                                            action_flags,
5068                                                            attr, error);
5069                         if (ret < 0)
5070                                 return ret;
5071                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5072                                 /* Count all modify-header actions as one. */
5073                                 if (!(action_flags &
5074                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5075                                         ++actions_n;
5076                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5077                                                 MLX5_FLOW_ACTION_MARK_EXT;
5078                         } else {
5079                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5080                                 ++actions_n;
5081                         }
5082                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5083                         break;
5084                 case RTE_FLOW_ACTION_TYPE_SET_META:
5085                         ret = flow_dv_validate_action_set_meta(dev, actions,
5086                                                                action_flags,
5087                                                                attr, error);
5088                         if (ret < 0)
5089                                 return ret;
5090                         /* Count all modify-header actions as one action. */
5091                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5092                                 ++actions_n;
5093                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5094                         rw_act_num += MLX5_ACT_NUM_SET_META;
5095                         break;
5096                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5097                         ret = flow_dv_validate_action_set_tag(dev, actions,
5098                                                               action_flags,
5099                                                               attr, error);
5100                         if (ret < 0)
5101                                 return ret;
5102                         /* Count all modify-header actions as one action. */
5103                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5104                                 ++actions_n;
5105                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5106                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5107                         break;
5108                 case RTE_FLOW_ACTION_TYPE_DROP:
5109                         ret = mlx5_flow_validate_action_drop(action_flags,
5110                                                              attr, error);
5111                         if (ret < 0)
5112                                 return ret;
5113                         action_flags |= MLX5_FLOW_ACTION_DROP;
5114                         ++actions_n;
5115                         break;
5116                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5117                         ret = mlx5_flow_validate_action_queue(actions,
5118                                                               action_flags, dev,
5119                                                               attr, error);
5120                         if (ret < 0)
5121                                 return ret;
5122                         queue_index = ((const struct rte_flow_action_queue *)
5123                                                         (actions->conf))->index;
5124                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5125                         ++actions_n;
5126                         break;
5127                 case RTE_FLOW_ACTION_TYPE_RSS:
5128                         rss = actions->conf;
5129                         ret = mlx5_flow_validate_action_rss(actions,
5130                                                             action_flags, dev,
5131                                                             attr, item_flags,
5132                                                             error);
5133                         if (ret < 0)
5134                                 return ret;
5135                         if (rss != NULL && rss->queue_num)
5136                                 queue_index = rss->queue[0];
5137                         action_flags |= MLX5_FLOW_ACTION_RSS;
5138                         ++actions_n;
5139                         break;
5140                 case RTE_FLOW_ACTION_TYPE_COUNT:
5141                         ret = flow_dv_validate_action_count(dev, error);
5142                         if (ret < 0)
5143                                 return ret;
5144                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5145                         ++actions_n;
5146                         break;
5147                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5148                         if (flow_dv_validate_action_pop_vlan(dev,
5149                                                              action_flags,
5150                                                              actions,
5151                                                              item_flags, attr,
5152                                                              error))
5153                                 return -rte_errno;
5154                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5155                         ++actions_n;
5156                         break;
5157                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5158                         ret = flow_dv_validate_action_push_vlan(dev,
5159                                                                 action_flags,
5160                                                                 vlan_m,
5161                                                                 actions, attr,
5162                                                                 error);
5163                         if (ret < 0)
5164                                 return ret;
5165                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5166                         ++actions_n;
5167                         break;
5168                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5169                         ret = flow_dv_validate_action_set_vlan_pcp
5170                                                 (action_flags, actions, error);
5171                         if (ret < 0)
5172                                 return ret;
5173                         /* Count PCP with push_vlan command. */
5174                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5175                         break;
5176                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5177                         ret = flow_dv_validate_action_set_vlan_vid
5178                                                 (item_flags, action_flags,
5179                                                  actions, error);
5180                         if (ret < 0)
5181                                 return ret;
5182                         /* Count VID with push_vlan command. */
5183                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5184                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5185                         break;
5186                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5187                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5188                         ret = flow_dv_validate_action_l2_encap(dev,
5189                                                                action_flags,
5190                                                                actions, attr,
5191                                                                error);
5192                         if (ret < 0)
5193                                 return ret;
5194                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5195                         ++actions_n;
5196                         break;
5197                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5198                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5199                         ret = flow_dv_validate_action_decap(dev, action_flags,
5200                                                             attr, error);
5201                         if (ret < 0)
5202                                 return ret;
5203                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5204                         ++actions_n;
5205                         break;
5206                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5207                         ret = flow_dv_validate_action_raw_encap_decap
5208                                 (dev, NULL, actions->conf, attr, &action_flags,
5209                                  &actions_n, error);
5210                         if (ret < 0)
5211                                 return ret;
5212                         break;
5213                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5214                         decap = actions->conf;
5215                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5216                                 ;
5217                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5218                                 encap = NULL;
5219                                 actions--;
5220                         } else {
5221                                 encap = actions->conf;
5222                         }
5223                         ret = flow_dv_validate_action_raw_encap_decap
5224                                            (dev,
5225                                             decap ? decap : &empty_decap, encap,
5226                                             attr, &action_flags, &actions_n,
5227                                             error);
5228                         if (ret < 0)
5229                                 return ret;
5230                         break;
5231                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5232                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5233                         ret = flow_dv_validate_action_modify_mac(action_flags,
5234                                                                  actions,
5235                                                                  item_flags,
5236                                                                  error);
5237                         if (ret < 0)
5238                                 return ret;
5239                         /* Count all modify-header actions as one action. */
5240                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5241                                 ++actions_n;
5242                         action_flags |= actions->type ==
5243                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5244                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5245                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5246                         /*
5247                          * Even if the source and destination MAC addresses have
5248                          * overlap in the header with 4B alignment, the convert
5249                          * function will handle them separately and 4 SW actions
5250                          * will be created. And 2 actions will be added each
5251                          * time no matter how many bytes of address will be set.
5252                          */
5253                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5254                         break;
5255                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5256                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5257                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5258                                                                   actions,
5259                                                                   item_flags,
5260                                                                   error);
5261                         if (ret < 0)
5262                                 return ret;
5263                         /* Count all modify-header actions as one action. */
5264                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5265                                 ++actions_n;
5266                         action_flags |= actions->type ==
5267                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5268                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5269                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5270                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5271                         break;
5272                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5273                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5274                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5275                                                                   actions,
5276                                                                   item_flags,
5277                                                                   error);
5278                         if (ret < 0)
5279                                 return ret;
5280                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5281                                 return rte_flow_error_set(error, ENOTSUP,
5282                                         RTE_FLOW_ERROR_TYPE_ACTION,
5283                                         actions,
5284                                         "Can't change header "
5285                                         "with ICMPv6 proto");
5286                         /* Count all modify-header actions as one action. */
5287                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5288                                 ++actions_n;
5289                         action_flags |= actions->type ==
5290                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5291                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5292                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5293                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5294                         break;
5295                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5296                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5297                         ret = flow_dv_validate_action_modify_tp(action_flags,
5298                                                                 actions,
5299                                                                 item_flags,
5300                                                                 error);
5301                         if (ret < 0)
5302                                 return ret;
5303                         /* Count all modify-header actions as one action. */
5304                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5305                                 ++actions_n;
5306                         action_flags |= actions->type ==
5307                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5308                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5309                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5310                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5311                         break;
5312                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5313                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5314                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5315                                                                  actions,
5316                                                                  item_flags,
5317                                                                  error);
5318                         if (ret < 0)
5319                                 return ret;
5320                         /* Count all modify-header actions as one action. */
5321                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5322                                 ++actions_n;
5323                         action_flags |= actions->type ==
5324                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5325                                                 MLX5_FLOW_ACTION_SET_TTL :
5326                                                 MLX5_FLOW_ACTION_DEC_TTL;
5327                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5328                         break;
5329                 case RTE_FLOW_ACTION_TYPE_JUMP:
5330                         ret = flow_dv_validate_action_jump(actions,
5331                                                            action_flags,
5332                                                            attr, external,
5333                                                            error);
5334                         if (ret)
5335                                 return ret;
5336                         ++actions_n;
5337                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5338                         break;
5339                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5340                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5341                         ret = flow_dv_validate_action_modify_tcp_seq
5342                                                                 (action_flags,
5343                                                                  actions,
5344                                                                  item_flags,
5345                                                                  error);
5346                         if (ret < 0)
5347                                 return ret;
5348                         /* Count all modify-header actions as one action. */
5349                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5350                                 ++actions_n;
5351                         action_flags |= actions->type ==
5352                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5353                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5354                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5355                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5356                         break;
5357                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5358                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5359                         ret = flow_dv_validate_action_modify_tcp_ack
5360                                                                 (action_flags,
5361                                                                  actions,
5362                                                                  item_flags,
5363                                                                  error);
5364                         if (ret < 0)
5365                                 return ret;
5366                         /* Count all modify-header actions as one action. */
5367                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5368                                 ++actions_n;
5369                         action_flags |= actions->type ==
5370                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5371                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5372                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5373                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5374                         break;
5375                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5376                         break;
5377                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5378                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5379                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5380                         break;
5381                 case RTE_FLOW_ACTION_TYPE_METER:
5382                         ret = mlx5_flow_validate_action_meter(dev,
5383                                                               action_flags,
5384                                                               actions, attr,
5385                                                               error);
5386                         if (ret < 0)
5387                                 return ret;
5388                         action_flags |= MLX5_FLOW_ACTION_METER;
5389                         ++actions_n;
5390                         /* Meter action will add one more TAG action. */
5391                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5392                         break;
5393                 case RTE_FLOW_ACTION_TYPE_AGE:
5394                         ret = flow_dv_validate_action_age(action_flags,
5395                                                           actions, dev,
5396                                                           error);
5397                         if (ret < 0)
5398                                 return ret;
5399                         action_flags |= MLX5_FLOW_ACTION_AGE;
5400                         ++actions_n;
5401                         break;
5402                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5403                         ret = flow_dv_validate_action_modify_ipv4_dscp
5404                                                          (action_flags,
5405                                                           actions,
5406                                                           item_flags,
5407                                                           error);
5408                         if (ret < 0)
5409                                 return ret;
5410                         /* Count all modify-header actions as one action. */
5411                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5412                                 ++actions_n;
5413                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5414                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5415                         break;
5416                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5417                         ret = flow_dv_validate_action_modify_ipv6_dscp
5418                                                                 (action_flags,
5419                                                                  actions,
5420                                                                  item_flags,
5421                                                                  error);
5422                         if (ret < 0)
5423                                 return ret;
5424                         /* Count all modify-header actions as one action. */
5425                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5426                                 ++actions_n;
5427                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5428                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5429                         break;
5430                 default:
5431                         return rte_flow_error_set(error, ENOTSUP,
5432                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5433                                                   actions,
5434                                                   "action not supported");
5435                 }
5436         }
5437         /*
5438          * Validate the drop action mutual exclusion with other actions.
5439          * Drop action is mutually-exclusive with any other action, except for
5440          * Count action.
5441          */
5442         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5443             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5444                 return rte_flow_error_set(error, EINVAL,
5445                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5446                                           "Drop action is mutually-exclusive "
5447                                           "with any other action, except for "
5448                                           "Count action");
5449         /* Eswitch has few restrictions on using items and actions */
5450         if (attr->transfer) {
5451                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5452                     action_flags & MLX5_FLOW_ACTION_FLAG)
5453                         return rte_flow_error_set(error, ENOTSUP,
5454                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5455                                                   NULL,
5456                                                   "unsupported action FLAG");
5457                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5458                     action_flags & MLX5_FLOW_ACTION_MARK)
5459                         return rte_flow_error_set(error, ENOTSUP,
5460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5461                                                   NULL,
5462                                                   "unsupported action MARK");
5463                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5464                         return rte_flow_error_set(error, ENOTSUP,
5465                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5466                                                   NULL,
5467                                                   "unsupported action QUEUE");
5468                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5469                         return rte_flow_error_set(error, ENOTSUP,
5470                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5471                                                   NULL,
5472                                                   "unsupported action RSS");
5473                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5474                         return rte_flow_error_set(error, EINVAL,
5475                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5476                                                   actions,
5477                                                   "no fate action is found");
5478         } else {
5479                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5480                         return rte_flow_error_set(error, EINVAL,
5481                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5482                                                   actions,
5483                                                   "no fate action is found");
5484         }
5485         /* Continue validation for Xcap actions.*/
5486         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5487             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5488                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5489                     MLX5_FLOW_XCAP_ACTIONS)
5490                         return rte_flow_error_set(error, ENOTSUP,
5491                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5492                                                   NULL, "encap and decap "
5493                                                   "combination aren't supported");
5494                 if (!attr->transfer && attr->ingress && (action_flags &
5495                                                         MLX5_FLOW_ACTION_ENCAP))
5496                         return rte_flow_error_set(error, ENOTSUP,
5497                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5498                                                   NULL, "encap is not supported"
5499                                                   " for ingress traffic");
5500         }
5501         /* Hairpin flow will add one more TAG action. */
5502         if (hairpin > 0)
5503                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5504         /* extra metadata enabled: one more TAG action will be add. */
5505         if (dev_conf->dv_flow_en &&
5506             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5507             mlx5_flow_ext_mreg_supported(dev))
5508                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5509         if ((uint32_t)rw_act_num >
5510                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5511                 return rte_flow_error_set(error, ENOTSUP,
5512                                           RTE_FLOW_ERROR_TYPE_ACTION,
5513                                           NULL, "too many header modify"
5514                                           " actions to support");
5515         }
5516         return 0;
5517 }
5518
5519 /**
5520  * Internal preparation function. Allocates the DV flow size,
5521  * this size is constant.
5522  *
5523  * @param[in] dev
5524  *   Pointer to the rte_eth_dev structure.
5525  * @param[in] attr
5526  *   Pointer to the flow attributes.
5527  * @param[in] items
5528  *   Pointer to the list of items.
5529  * @param[in] actions
5530  *   Pointer to the list of actions.
5531  * @param[out] error
5532  *   Pointer to the error structure.
5533  *
5534  * @return
5535  *   Pointer to mlx5_flow object on success,
5536  *   otherwise NULL and rte_errno is set.
5537  */
5538 static struct mlx5_flow *
5539 flow_dv_prepare(struct rte_eth_dev *dev,
5540                 const struct rte_flow_attr *attr __rte_unused,
5541                 const struct rte_flow_item items[] __rte_unused,
5542                 const struct rte_flow_action actions[] __rte_unused,
5543                 struct rte_flow_error *error)
5544 {
5545         uint32_t handle_idx = 0;
5546         struct mlx5_flow *dev_flow;
5547         struct mlx5_flow_handle *dev_handle;
5548         struct mlx5_priv *priv = dev->data->dev_private;
5549
5550         /* In case of corrupting the memory. */
5551         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5552                 rte_flow_error_set(error, ENOSPC,
5553                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5554                                    "not free temporary device flow");
5555                 return NULL;
5556         }
5557         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5558                                    &handle_idx);
5559         if (!dev_handle) {
5560                 rte_flow_error_set(error, ENOMEM,
5561                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5562                                    "not enough memory to create flow handle");
5563                 return NULL;
5564         }
5565         /* No multi-thread supporting. */
5566         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5567         dev_flow->handle = dev_handle;
5568         dev_flow->handle_idx = handle_idx;
5569         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5570         /*
5571          * The matching value needs to be cleared to 0 before using. In the
5572          * past, it will be automatically cleared when using rte_*alloc
5573          * API. The time consumption will be almost the same as before.
5574          */
5575         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5576         dev_flow->ingress = attr->ingress;
5577         dev_flow->dv.transfer = attr->transfer;
5578         return dev_flow;
5579 }
5580
5581 #ifdef RTE_LIBRTE_MLX5_DEBUG
5582 /**
5583  * Sanity check for match mask and value. Similar to check_valid_spec() in
5584  * kernel driver. If unmasked bit is present in value, it returns failure.
5585  *
5586  * @param match_mask
5587  *   pointer to match mask buffer.
5588  * @param match_value
5589  *   pointer to match value buffer.
5590  *
5591  * @return
5592  *   0 if valid, -EINVAL otherwise.
5593  */
5594 static int
5595 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5596 {
5597         uint8_t *m = match_mask;
5598         uint8_t *v = match_value;
5599         unsigned int i;
5600
5601         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5602                 if (v[i] & ~m[i]) {
5603                         DRV_LOG(ERR,
5604                                 "match_value differs from match_criteria"
5605                                 " %p[%u] != %p[%u]",
5606                                 match_value, i, match_mask, i);
5607                         return -EINVAL;
5608                 }
5609         }
5610         return 0;
5611 }
5612 #endif
5613
5614 /**
5615  * Add match of ip_version.
5616  *
5617  * @param[in] group
5618  *   Flow group.
5619  * @param[in] headers_v
5620  *   Values header pointer.
5621  * @param[in] headers_m
5622  *   Masks header pointer.
5623  * @param[in] ip_version
5624  *   The IP version to set.
5625  */
5626 static inline void
5627 flow_dv_set_match_ip_version(uint32_t group,
5628                              void *headers_v,
5629                              void *headers_m,
5630                              uint8_t ip_version)
5631 {
5632         if (group == 0)
5633                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5634         else
5635                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5636                          ip_version);
5637         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5638 }
5639
5640 /**
5641  * Add Ethernet item to matcher and to the value.
5642  *
5643  * @param[in, out] matcher
5644  *   Flow matcher.
5645  * @param[in, out] key
5646  *   Flow matcher value.
5647  * @param[in] item
5648  *   Flow pattern to translate.
5649  * @param[in] inner
5650  *   Item is inner pattern.
5651  */
5652 static void
5653 flow_dv_translate_item_eth(void *matcher, void *key,
5654                            const struct rte_flow_item *item, int inner)
5655 {
5656         const struct rte_flow_item_eth *eth_m = item->mask;
5657         const struct rte_flow_item_eth *eth_v = item->spec;
5658         const struct rte_flow_item_eth nic_mask = {
5659                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5660                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5661                 .type = RTE_BE16(0xffff),
5662         };
5663         void *headers_m;
5664         void *headers_v;
5665         char *l24_v;
5666         unsigned int i;
5667
5668         if (!eth_v)
5669                 return;
5670         if (!eth_m)
5671                 eth_m = &nic_mask;
5672         if (inner) {
5673                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5674                                          inner_headers);
5675                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5676         } else {
5677                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5678                                          outer_headers);
5679                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5680         }
5681         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5682                &eth_m->dst, sizeof(eth_m->dst));
5683         /* The value must be in the range of the mask. */
5684         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5685         for (i = 0; i < sizeof(eth_m->dst); ++i)
5686                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5687         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5688                &eth_m->src, sizeof(eth_m->src));
5689         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5690         /* The value must be in the range of the mask. */
5691         for (i = 0; i < sizeof(eth_m->dst); ++i)
5692                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5693         if (eth_v->type) {
5694                 /* When ethertype is present set mask for tagged VLAN. */
5695                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5696                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5697                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5698                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5699                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5700                                  1);
5701                         /* Return here to avoid setting match on ethertype. */
5702                         return;
5703                 }
5704         }
5705         /*
5706          * HW supports match on one Ethertype, the Ethertype following the last
5707          * VLAN tag of the packet (see PRM).
5708          * Set match on ethertype only if ETH header is not followed by VLAN.
5709          */
5710         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5711                  rte_be_to_cpu_16(eth_m->type));
5712         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5713         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5714 }
5715
5716 /**
5717  * Add VLAN item to matcher and to the value.
5718  *
5719  * @param[in, out] dev_flow
5720  *   Flow descriptor.
5721  * @param[in, out] matcher
5722  *   Flow matcher.
5723  * @param[in, out] key
5724  *   Flow matcher value.
5725  * @param[in] item
5726  *   Flow pattern to translate.
5727  * @param[in] inner
5728  *   Item is inner pattern.
5729  */
5730 static void
5731 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5732                             void *matcher, void *key,
5733                             const struct rte_flow_item *item,
5734                             int inner)
5735 {
5736         const struct rte_flow_item_vlan *vlan_m = item->mask;
5737         const struct rte_flow_item_vlan *vlan_v = item->spec;
5738         void *headers_m;
5739         void *headers_v;
5740         uint16_t tci_m;
5741         uint16_t tci_v;
5742
5743         if (!vlan_v)
5744                 return;
5745         if (!vlan_m)
5746                 vlan_m = &rte_flow_item_vlan_mask;
5747         if (inner) {
5748                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5749                                          inner_headers);
5750                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5751         } else {
5752                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5753                                          outer_headers);
5754                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5755                 /*
5756                  * This is workaround, masks are not supported,
5757                  * and pre-validated.
5758                  */
5759                 dev_flow->handle->vf_vlan.tag =
5760                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5761         }
5762         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5763         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5764         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5765         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5766         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5767         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5768         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5769         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5770         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5771         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5772         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5773                  rte_be_to_cpu_16(vlan_m->inner_type));
5774         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5775                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5776 }
5777
5778 /**
5779  * Add IPV4 item to matcher and to the value.
5780  *
5781  * @param[in, out] matcher
5782  *   Flow matcher.
5783  * @param[in, out] key
5784  *   Flow matcher value.
5785  * @param[in] item
5786  *   Flow pattern to translate.
5787  * @param[in] item_flags
5788  *   Bit-fields that holds the items detected until now.
5789  * @param[in] inner
5790  *   Item is inner pattern.
5791  * @param[in] group
5792  *   The group to insert the rule.
5793  */
5794 static void
5795 flow_dv_translate_item_ipv4(void *matcher, void *key,
5796                             const struct rte_flow_item *item,
5797                             const uint64_t item_flags,
5798                             int inner, uint32_t group)
5799 {
5800         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5801         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5802         const struct rte_flow_item_ipv4 nic_mask = {
5803                 .hdr = {
5804                         .src_addr = RTE_BE32(0xffffffff),
5805                         .dst_addr = RTE_BE32(0xffffffff),
5806                         .type_of_service = 0xff,
5807                         .next_proto_id = 0xff,
5808                         .time_to_live = 0xff,
5809                 },
5810         };
5811         void *headers_m;
5812         void *headers_v;
5813         char *l24_m;
5814         char *l24_v;
5815         uint8_t tos;
5816
5817         if (inner) {
5818                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5819                                          inner_headers);
5820                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5821         } else {
5822                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5823                                          outer_headers);
5824                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5825         }
5826         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5827         /*
5828          * On outer header (which must contains L2), or inner header with L2,
5829          * set cvlan_tag mask bit to mark this packet as untagged.
5830          * This should be done even if item->spec is empty.
5831          */
5832         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5833                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5834         if (!ipv4_v)
5835                 return;
5836         if (!ipv4_m)
5837                 ipv4_m = &nic_mask;
5838         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5839                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5840         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5841                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5842         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5843         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5844         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5845                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5846         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5847                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5848         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5849         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5850         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5851         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5852                  ipv4_m->hdr.type_of_service);
5853         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5854         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5855                  ipv4_m->hdr.type_of_service >> 2);
5856         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5857         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5858                  ipv4_m->hdr.next_proto_id);
5859         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5860                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5861         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5862                  ipv4_m->hdr.time_to_live);
5863         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5864                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5865 }
5866
5867 /**
5868  * Add IPV6 item to matcher and to the value.
5869  *
5870  * @param[in, out] matcher
5871  *   Flow matcher.
5872  * @param[in, out] key
5873  *   Flow matcher value.
5874  * @param[in] item
5875  *   Flow pattern to translate.
5876  * @param[in] item_flags
5877  *   Bit-fields that holds the items detected until now.
5878  * @param[in] inner
5879  *   Item is inner pattern.
5880  * @param[in] group
5881  *   The group to insert the rule.
5882  */
5883 static void
5884 flow_dv_translate_item_ipv6(void *matcher, void *key,
5885                             const struct rte_flow_item *item,
5886                             const uint64_t item_flags,
5887                             int inner, uint32_t group)
5888 {
5889         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5890         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5891         const struct rte_flow_item_ipv6 nic_mask = {
5892                 .hdr = {
5893                         .src_addr =
5894                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5895                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5896                         .dst_addr =
5897                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5898                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5899                         .vtc_flow = RTE_BE32(0xffffffff),
5900                         .proto = 0xff,
5901                         .hop_limits = 0xff,
5902                 },
5903         };
5904         void *headers_m;
5905         void *headers_v;
5906         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5907         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5908         char *l24_m;
5909         char *l24_v;
5910         uint32_t vtc_m;
5911         uint32_t vtc_v;
5912         int i;
5913         int size;
5914
5915         if (inner) {
5916                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5917                                          inner_headers);
5918                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5919         } else {
5920                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5921                                          outer_headers);
5922                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5923         }
5924         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5925         /*
5926          * On outer header (which must contains L2), or inner header with L2,
5927          * set cvlan_tag mask bit to mark this packet as untagged.
5928          * This should be done even if item->spec is empty.
5929          */
5930         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5931                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5932         if (!ipv6_v)
5933                 return;
5934         if (!ipv6_m)
5935                 ipv6_m = &nic_mask;
5936         size = sizeof(ipv6_m->hdr.dst_addr);
5937         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5938                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5939         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5940                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5941         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5942         for (i = 0; i < size; ++i)
5943                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5944         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5945                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5946         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5947                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5948         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5949         for (i = 0; i < size; ++i)
5950                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5951         /* TOS. */
5952         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5953         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5954         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5955         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5956         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5957         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5958         /* Label. */
5959         if (inner) {
5960                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5961                          vtc_m);
5962                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5963                          vtc_v);
5964         } else {
5965                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5966                          vtc_m);
5967                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5968                          vtc_v);
5969         }
5970         /* Protocol. */
5971         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5972                  ipv6_m->hdr.proto);
5973         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5974                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5975         /* Hop limit. */
5976         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5977                  ipv6_m->hdr.hop_limits);
5978         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5979                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5980 }
5981
5982 /**
5983  * Add TCP item to matcher and to the value.
5984  *
5985  * @param[in, out] matcher
5986  *   Flow matcher.
5987  * @param[in, out] key
5988  *   Flow matcher value.
5989  * @param[in] item
5990  *   Flow pattern to translate.
5991  * @param[in] inner
5992  *   Item is inner pattern.
5993  */
5994 static void
5995 flow_dv_translate_item_tcp(void *matcher, void *key,
5996                            const struct rte_flow_item *item,
5997                            int inner)
5998 {
5999         const struct rte_flow_item_tcp *tcp_m = item->mask;
6000         const struct rte_flow_item_tcp *tcp_v = item->spec;
6001         void *headers_m;
6002         void *headers_v;
6003
6004         if (inner) {
6005                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6006                                          inner_headers);
6007                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6008         } else {
6009                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6010                                          outer_headers);
6011                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6012         }
6013         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6014         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6015         if (!tcp_v)
6016                 return;
6017         if (!tcp_m)
6018                 tcp_m = &rte_flow_item_tcp_mask;
6019         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6020                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6021         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6022                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6023         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6024                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6025         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6026                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6027         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6028                  tcp_m->hdr.tcp_flags);
6029         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6030                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6031 }
6032
6033 /**
6034  * Add UDP item to matcher and to the value.
6035  *
6036  * @param[in, out] matcher
6037  *   Flow matcher.
6038  * @param[in, out] key
6039  *   Flow matcher value.
6040  * @param[in] item
6041  *   Flow pattern to translate.
6042  * @param[in] inner
6043  *   Item is inner pattern.
6044  */
6045 static void
6046 flow_dv_translate_item_udp(void *matcher, void *key,
6047                            const struct rte_flow_item *item,
6048                            int inner)
6049 {
6050         const struct rte_flow_item_udp *udp_m = item->mask;
6051         const struct rte_flow_item_udp *udp_v = item->spec;
6052         void *headers_m;
6053         void *headers_v;
6054
6055         if (inner) {
6056                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6057                                          inner_headers);
6058                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6059         } else {
6060                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6061                                          outer_headers);
6062                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6063         }
6064         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6065         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6066         if (!udp_v)
6067                 return;
6068         if (!udp_m)
6069                 udp_m = &rte_flow_item_udp_mask;
6070         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6071                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6072         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6073                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6074         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6075                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6076         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6077                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6078 }
6079
6080 /**
6081  * Add GRE optional Key item to matcher and to the value.
6082  *
6083  * @param[in, out] matcher
6084  *   Flow matcher.
6085  * @param[in, out] key
6086  *   Flow matcher value.
6087  * @param[in] item
6088  *   Flow pattern to translate.
6089  * @param[in] inner
6090  *   Item is inner pattern.
6091  */
6092 static void
6093 flow_dv_translate_item_gre_key(void *matcher, void *key,
6094                                    const struct rte_flow_item *item)
6095 {
6096         const rte_be32_t *key_m = item->mask;
6097         const rte_be32_t *key_v = item->spec;
6098         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6099         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6100         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6101
6102         /* GRE K bit must be on and should already be validated */
6103         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6104         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6105         if (!key_v)
6106                 return;
6107         if (!key_m)
6108                 key_m = &gre_key_default_mask;
6109         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6110                  rte_be_to_cpu_32(*key_m) >> 8);
6111         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6112                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6113         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6114                  rte_be_to_cpu_32(*key_m) & 0xFF);
6115         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6116                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6117 }
6118
6119 /**
6120  * Add GRE item to matcher and to the value.
6121  *
6122  * @param[in, out] matcher
6123  *   Flow matcher.
6124  * @param[in, out] key
6125  *   Flow matcher value.
6126  * @param[in] item
6127  *   Flow pattern to translate.
6128  * @param[in] inner
6129  *   Item is inner pattern.
6130  */
6131 static void
6132 flow_dv_translate_item_gre(void *matcher, void *key,
6133                            const struct rte_flow_item *item,
6134                            int inner)
6135 {
6136         const struct rte_flow_item_gre *gre_m = item->mask;
6137         const struct rte_flow_item_gre *gre_v = item->spec;
6138         void *headers_m;
6139         void *headers_v;
6140         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6141         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6142         struct {
6143                 union {
6144                         __extension__
6145                         struct {
6146                                 uint16_t version:3;
6147                                 uint16_t rsvd0:9;
6148                                 uint16_t s_present:1;
6149                                 uint16_t k_present:1;
6150                                 uint16_t rsvd_bit1:1;
6151                                 uint16_t c_present:1;
6152                         };
6153                         uint16_t value;
6154                 };
6155         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6156
6157         if (inner) {
6158                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6159                                          inner_headers);
6160                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6161         } else {
6162                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6163                                          outer_headers);
6164                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6165         }
6166         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6167         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6168         if (!gre_v)
6169                 return;
6170         if (!gre_m)
6171                 gre_m = &rte_flow_item_gre_mask;
6172         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6173                  rte_be_to_cpu_16(gre_m->protocol));
6174         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6175                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6176         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6177         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6178         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6179                  gre_crks_rsvd0_ver_m.c_present);
6180         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6181                  gre_crks_rsvd0_ver_v.c_present &
6182                  gre_crks_rsvd0_ver_m.c_present);
6183         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6184                  gre_crks_rsvd0_ver_m.k_present);
6185         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6186                  gre_crks_rsvd0_ver_v.k_present &
6187                  gre_crks_rsvd0_ver_m.k_present);
6188         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6189                  gre_crks_rsvd0_ver_m.s_present);
6190         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6191                  gre_crks_rsvd0_ver_v.s_present &
6192                  gre_crks_rsvd0_ver_m.s_present);
6193 }
6194
6195 /**
6196  * Add NVGRE item to matcher and to the value.
6197  *
6198  * @param[in, out] matcher
6199  *   Flow matcher.
6200  * @param[in, out] key
6201  *   Flow matcher value.
6202  * @param[in] item
6203  *   Flow pattern to translate.
6204  * @param[in] inner
6205  *   Item is inner pattern.
6206  */
6207 static void
6208 flow_dv_translate_item_nvgre(void *matcher, void *key,
6209                              const struct rte_flow_item *item,
6210                              int inner)
6211 {
6212         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6213         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6214         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6215         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6216         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6217         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6218         char *gre_key_m;
6219         char *gre_key_v;
6220         int size;
6221         int i;
6222
6223         /* For NVGRE, GRE header fields must be set with defined values. */
6224         const struct rte_flow_item_gre gre_spec = {
6225                 .c_rsvd0_ver = RTE_BE16(0x2000),
6226                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6227         };
6228         const struct rte_flow_item_gre gre_mask = {
6229                 .c_rsvd0_ver = RTE_BE16(0xB000),
6230                 .protocol = RTE_BE16(UINT16_MAX),
6231         };
6232         const struct rte_flow_item gre_item = {
6233                 .spec = &gre_spec,
6234                 .mask = &gre_mask,
6235                 .last = NULL,
6236         };
6237         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6238         if (!nvgre_v)
6239                 return;
6240         if (!nvgre_m)
6241                 nvgre_m = &rte_flow_item_nvgre_mask;
6242         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6243         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6244         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6245         memcpy(gre_key_m, tni_flow_id_m, size);
6246         for (i = 0; i < size; ++i)
6247                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6248 }
6249
6250 /**
6251  * Add VXLAN item to matcher and to the value.
6252  *
6253  * @param[in, out] matcher
6254  *   Flow matcher.
6255  * @param[in, out] key
6256  *   Flow matcher value.
6257  * @param[in] item
6258  *   Flow pattern to translate.
6259  * @param[in] inner
6260  *   Item is inner pattern.
6261  */
6262 static void
6263 flow_dv_translate_item_vxlan(void *matcher, void *key,
6264                              const struct rte_flow_item *item,
6265                              int inner)
6266 {
6267         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6268         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6269         void *headers_m;
6270         void *headers_v;
6271         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6272         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6273         char *vni_m;
6274         char *vni_v;
6275         uint16_t dport;
6276         int size;
6277         int i;
6278
6279         if (inner) {
6280                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6281                                          inner_headers);
6282                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6283         } else {
6284                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6285                                          outer_headers);
6286                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6287         }
6288         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6289                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6290         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6291                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6292                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6293         }
6294         if (!vxlan_v)
6295                 return;
6296         if (!vxlan_m)
6297                 vxlan_m = &rte_flow_item_vxlan_mask;
6298         size = sizeof(vxlan_m->vni);
6299         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6300         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6301         memcpy(vni_m, vxlan_m->vni, size);
6302         for (i = 0; i < size; ++i)
6303                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6304 }
6305
6306 /**
6307  * Add VXLAN-GPE item to matcher and to the value.
6308  *
6309  * @param[in, out] matcher
6310  *   Flow matcher.
6311  * @param[in, out] key
6312  *   Flow matcher value.
6313  * @param[in] item
6314  *   Flow pattern to translate.
6315  * @param[in] inner
6316  *   Item is inner pattern.
6317  */
6318
6319 static void
6320 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6321                                  const struct rte_flow_item *item, int inner)
6322 {
6323         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6324         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6325         void *headers_m;
6326         void *headers_v;
6327         void *misc_m =
6328                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6329         void *misc_v =
6330                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6331         char *vni_m;
6332         char *vni_v;
6333         uint16_t dport;
6334         int size;
6335         int i;
6336         uint8_t flags_m = 0xff;
6337         uint8_t flags_v = 0xc;
6338
6339         if (inner) {
6340                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6341                                          inner_headers);
6342                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6343         } else {
6344                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6345                                          outer_headers);
6346                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6347         }
6348         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6349                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6350         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6351                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6352                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6353         }
6354         if (!vxlan_v)
6355                 return;
6356         if (!vxlan_m)
6357                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6358         size = sizeof(vxlan_m->vni);
6359         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6360         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6361         memcpy(vni_m, vxlan_m->vni, size);
6362         for (i = 0; i < size; ++i)
6363                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6364         if (vxlan_m->flags) {
6365                 flags_m = vxlan_m->flags;
6366                 flags_v = vxlan_v->flags;
6367         }
6368         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6369         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6370         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6371                  vxlan_m->protocol);
6372         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6373                  vxlan_v->protocol);
6374 }
6375
6376 /**
6377  * Add Geneve item to matcher and to the value.
6378  *
6379  * @param[in, out] matcher
6380  *   Flow matcher.
6381  * @param[in, out] key
6382  *   Flow matcher value.
6383  * @param[in] item
6384  *   Flow pattern to translate.
6385  * @param[in] inner
6386  *   Item is inner pattern.
6387  */
6388
6389 static void
6390 flow_dv_translate_item_geneve(void *matcher, void *key,
6391                               const struct rte_flow_item *item, int inner)
6392 {
6393         const struct rte_flow_item_geneve *geneve_m = item->mask;
6394         const struct rte_flow_item_geneve *geneve_v = item->spec;
6395         void *headers_m;
6396         void *headers_v;
6397         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6398         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6399         uint16_t dport;
6400         uint16_t gbhdr_m;
6401         uint16_t gbhdr_v;
6402         char *vni_m;
6403         char *vni_v;
6404         size_t size, i;
6405
6406         if (inner) {
6407                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6408                                          inner_headers);
6409                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6410         } else {
6411                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6412                                          outer_headers);
6413                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6414         }
6415         dport = MLX5_UDP_PORT_GENEVE;
6416         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6417                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6418                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6419         }
6420         if (!geneve_v)
6421                 return;
6422         if (!geneve_m)
6423                 geneve_m = &rte_flow_item_geneve_mask;
6424         size = sizeof(geneve_m->vni);
6425         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6426         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6427         memcpy(vni_m, geneve_m->vni, size);
6428         for (i = 0; i < size; ++i)
6429                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6430         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6431                  rte_be_to_cpu_16(geneve_m->protocol));
6432         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6433                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6434         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6435         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6436         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6437                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6438         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6439                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6440         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6441                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6442         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6443                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6444                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6445 }
6446
6447 /**
6448  * Add MPLS item to matcher and to the value.
6449  *
6450  * @param[in, out] matcher
6451  *   Flow matcher.
6452  * @param[in, out] key
6453  *   Flow matcher value.
6454  * @param[in] item
6455  *   Flow pattern to translate.
6456  * @param[in] prev_layer
6457  *   The protocol layer indicated in previous item.
6458  * @param[in] inner
6459  *   Item is inner pattern.
6460  */
6461 static void
6462 flow_dv_translate_item_mpls(void *matcher, void *key,
6463                             const struct rte_flow_item *item,
6464                             uint64_t prev_layer,
6465                             int inner)
6466 {
6467         const uint32_t *in_mpls_m = item->mask;
6468         const uint32_t *in_mpls_v = item->spec;
6469         uint32_t *out_mpls_m = 0;
6470         uint32_t *out_mpls_v = 0;
6471         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6472         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6473         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6474                                      misc_parameters_2);
6475         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6476         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6477         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6478
6479         switch (prev_layer) {
6480         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6481                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6482                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6483                          MLX5_UDP_PORT_MPLS);
6484                 break;
6485         case MLX5_FLOW_LAYER_GRE:
6486                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6487                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6488                          RTE_ETHER_TYPE_MPLS);
6489                 break;
6490         default:
6491                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6492                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6493                          IPPROTO_MPLS);
6494                 break;
6495         }
6496         if (!in_mpls_v)
6497                 return;
6498         if (!in_mpls_m)
6499                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6500         switch (prev_layer) {
6501         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6502                 out_mpls_m =
6503                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6504                                                  outer_first_mpls_over_udp);
6505                 out_mpls_v =
6506                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6507                                                  outer_first_mpls_over_udp);
6508                 break;
6509         case MLX5_FLOW_LAYER_GRE:
6510                 out_mpls_m =
6511                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6512                                                  outer_first_mpls_over_gre);
6513                 out_mpls_v =
6514                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6515                                                  outer_first_mpls_over_gre);
6516                 break;
6517         default:
6518                 /* Inner MPLS not over GRE is not supported. */
6519                 if (!inner) {
6520                         out_mpls_m =
6521                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6522                                                          misc2_m,
6523                                                          outer_first_mpls);
6524                         out_mpls_v =
6525                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6526                                                          misc2_v,
6527                                                          outer_first_mpls);
6528                 }
6529                 break;
6530         }
6531         if (out_mpls_m && out_mpls_v) {
6532                 *out_mpls_m = *in_mpls_m;
6533                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6534         }
6535 }
6536
6537 /**
6538  * Add metadata register item to matcher
6539  *
6540  * @param[in, out] matcher
6541  *   Flow matcher.
6542  * @param[in, out] key
6543  *   Flow matcher value.
6544  * @param[in] reg_type
6545  *   Type of device metadata register
6546  * @param[in] value
6547  *   Register value
6548  * @param[in] mask
6549  *   Register mask
6550  */
6551 static void
6552 flow_dv_match_meta_reg(void *matcher, void *key,
6553                        enum modify_reg reg_type,
6554                        uint32_t data, uint32_t mask)
6555 {
6556         void *misc2_m =
6557                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6558         void *misc2_v =
6559                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6560         uint32_t temp;
6561
6562         data &= mask;
6563         switch (reg_type) {
6564         case REG_A:
6565                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6566                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6567                 break;
6568         case REG_B:
6569                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6570                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6571                 break;
6572         case REG_C_0:
6573                 /*
6574                  * The metadata register C0 field might be divided into
6575                  * source vport index and META item value, we should set
6576                  * this field according to specified mask, not as whole one.
6577                  */
6578                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6579                 temp |= mask;
6580                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6581                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6582                 temp &= ~mask;
6583                 temp |= data;
6584                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6585                 break;
6586         case REG_C_1:
6587                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6588                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6589                 break;
6590         case REG_C_2:
6591                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6592                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6593                 break;
6594         case REG_C_3:
6595                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6596                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6597                 break;
6598         case REG_C_4:
6599                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6600                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6601                 break;
6602         case REG_C_5:
6603                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6604                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6605                 break;
6606         case REG_C_6:
6607                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6608                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6609                 break;
6610         case REG_C_7:
6611                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6612                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6613                 break;
6614         default:
6615                 MLX5_ASSERT(false);
6616                 break;
6617         }
6618 }
6619
6620 /**
6621  * Add MARK item to matcher
6622  *
6623  * @param[in] dev
6624  *   The device to configure through.
6625  * @param[in, out] matcher
6626  *   Flow matcher.
6627  * @param[in, out] key
6628  *   Flow matcher value.
6629  * @param[in] item
6630  *   Flow pattern to translate.
6631  */
6632 static void
6633 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6634                             void *matcher, void *key,
6635                             const struct rte_flow_item *item)
6636 {
6637         struct mlx5_priv *priv = dev->data->dev_private;
6638         const struct rte_flow_item_mark *mark;
6639         uint32_t value;
6640         uint32_t mask;
6641
6642         mark = item->mask ? (const void *)item->mask :
6643                             &rte_flow_item_mark_mask;
6644         mask = mark->id & priv->sh->dv_mark_mask;
6645         mark = (const void *)item->spec;
6646         MLX5_ASSERT(mark);
6647         value = mark->id & priv->sh->dv_mark_mask & mask;
6648         if (mask) {
6649                 enum modify_reg reg;
6650
6651                 /* Get the metadata register index for the mark. */
6652                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6653                 MLX5_ASSERT(reg > 0);
6654                 if (reg == REG_C_0) {
6655                         struct mlx5_priv *priv = dev->data->dev_private;
6656                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6657                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6658
6659                         mask &= msk_c0;
6660                         mask <<= shl_c0;
6661                         value <<= shl_c0;
6662                 }
6663                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6664         }
6665 }
6666
6667 /**
6668  * Add META item to matcher
6669  *
6670  * @param[in] dev
6671  *   The devich to configure through.
6672  * @param[in, out] matcher
6673  *   Flow matcher.
6674  * @param[in, out] key
6675  *   Flow matcher value.
6676  * @param[in] attr
6677  *   Attributes of flow that includes this item.
6678  * @param[in] item
6679  *   Flow pattern to translate.
6680  */
6681 static void
6682 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6683                             void *matcher, void *key,
6684                             const struct rte_flow_attr *attr,
6685                             const struct rte_flow_item *item)
6686 {
6687         const struct rte_flow_item_meta *meta_m;
6688         const struct rte_flow_item_meta *meta_v;
6689
6690         meta_m = (const void *)item->mask;
6691         if (!meta_m)
6692                 meta_m = &rte_flow_item_meta_mask;
6693         meta_v = (const void *)item->spec;
6694         if (meta_v) {
6695                 int reg;
6696                 uint32_t value = meta_v->data;
6697                 uint32_t mask = meta_m->data;
6698
6699                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6700                 if (reg < 0)
6701                         return;
6702                 /*
6703                  * In datapath code there is no endianness
6704                  * coversions for perfromance reasons, all
6705                  * pattern conversions are done in rte_flow.
6706                  */
6707                 value = rte_cpu_to_be_32(value);
6708                 mask = rte_cpu_to_be_32(mask);
6709                 if (reg == REG_C_0) {
6710                         struct mlx5_priv *priv = dev->data->dev_private;
6711                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6712                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6713 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6714                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6715
6716                         value >>= shr_c0;
6717                         mask >>= shr_c0;
6718 #endif
6719                         value <<= shl_c0;
6720                         mask <<= shl_c0;
6721                         MLX5_ASSERT(msk_c0);
6722                         MLX5_ASSERT(!(~msk_c0 & mask));
6723                 }
6724                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6725         }
6726 }
6727
6728 /**
6729  * Add vport metadata Reg C0 item to matcher
6730  *
6731  * @param[in, out] matcher
6732  *   Flow matcher.
6733  * @param[in, out] key
6734  *   Flow matcher value.
6735  * @param[in] reg
6736  *   Flow pattern to translate.
6737  */
6738 static void
6739 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6740                                   uint32_t value, uint32_t mask)
6741 {
6742         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6743 }
6744
6745 /**
6746  * Add tag item to matcher
6747  *
6748  * @param[in] dev
6749  *   The devich to configure through.
6750  * @param[in, out] matcher
6751  *   Flow matcher.
6752  * @param[in, out] key
6753  *   Flow matcher value.
6754  * @param[in] item
6755  *   Flow pattern to translate.
6756  */
6757 static void
6758 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6759                                 void *matcher, void *key,
6760                                 const struct rte_flow_item *item)
6761 {
6762         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6763         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6764         uint32_t mask, value;
6765
6766         MLX5_ASSERT(tag_v);
6767         value = tag_v->data;
6768         mask = tag_m ? tag_m->data : UINT32_MAX;
6769         if (tag_v->id == REG_C_0) {
6770                 struct mlx5_priv *priv = dev->data->dev_private;
6771                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6772                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6773
6774                 mask &= msk_c0;
6775                 mask <<= shl_c0;
6776                 value <<= shl_c0;
6777         }
6778         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6779 }
6780
6781 /**
6782  * Add TAG item to matcher
6783  *
6784  * @param[in] dev
6785  *   The devich to configure through.
6786  * @param[in, out] matcher
6787  *   Flow matcher.
6788  * @param[in, out] key
6789  *   Flow matcher value.
6790  * @param[in] item
6791  *   Flow pattern to translate.
6792  */
6793 static void
6794 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6795                            void *matcher, void *key,
6796                            const struct rte_flow_item *item)
6797 {
6798         const struct rte_flow_item_tag *tag_v = item->spec;
6799         const struct rte_flow_item_tag *tag_m = item->mask;
6800         enum modify_reg reg;
6801
6802         MLX5_ASSERT(tag_v);
6803         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6804         /* Get the metadata register index for the tag. */
6805         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6806         MLX5_ASSERT(reg > 0);
6807         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6808 }
6809
6810 /**
6811  * Add source vport match to the specified matcher.
6812  *
6813  * @param[in, out] matcher
6814  *   Flow matcher.
6815  * @param[in, out] key
6816  *   Flow matcher value.
6817  * @param[in] port
6818  *   Source vport value to match
6819  * @param[in] mask
6820  *   Mask
6821  */
6822 static void
6823 flow_dv_translate_item_source_vport(void *matcher, void *key,
6824                                     int16_t port, uint16_t mask)
6825 {
6826         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6827         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6828
6829         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6830         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6831 }
6832
6833 /**
6834  * Translate port-id item to eswitch match on  port-id.
6835  *
6836  * @param[in] dev
6837  *   The devich to configure through.
6838  * @param[in, out] matcher
6839  *   Flow matcher.
6840  * @param[in, out] key
6841  *   Flow matcher value.
6842  * @param[in] item
6843  *   Flow pattern to translate.
6844  *
6845  * @return
6846  *   0 on success, a negative errno value otherwise.
6847  */
6848 static int
6849 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6850                                void *key, const struct rte_flow_item *item)
6851 {
6852         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6853         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6854         struct mlx5_priv *priv;
6855         uint16_t mask, id;
6856
6857         mask = pid_m ? pid_m->id : 0xffff;
6858         id = pid_v ? pid_v->id : dev->data->port_id;
6859         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6860         if (!priv)
6861                 return -rte_errno;
6862         /* Translate to vport field or to metadata, depending on mode. */
6863         if (priv->vport_meta_mask)
6864                 flow_dv_translate_item_meta_vport(matcher, key,
6865                                                   priv->vport_meta_tag,
6866                                                   priv->vport_meta_mask);
6867         else
6868                 flow_dv_translate_item_source_vport(matcher, key,
6869                                                     priv->vport_id, mask);
6870         return 0;
6871 }
6872
6873 /**
6874  * Add ICMP6 item to matcher and to the value.
6875  *
6876  * @param[in, out] matcher
6877  *   Flow matcher.
6878  * @param[in, out] key
6879  *   Flow matcher value.
6880  * @param[in] item
6881  *   Flow pattern to translate.
6882  * @param[in] inner
6883  *   Item is inner pattern.
6884  */
6885 static void
6886 flow_dv_translate_item_icmp6(void *matcher, void *key,
6887                               const struct rte_flow_item *item,
6888                               int inner)
6889 {
6890         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6891         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6892         void *headers_m;
6893         void *headers_v;
6894         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6895                                      misc_parameters_3);
6896         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6897         if (inner) {
6898                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6899                                          inner_headers);
6900                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6901         } else {
6902                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6903                                          outer_headers);
6904                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6905         }
6906         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6907         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6908         if (!icmp6_v)
6909                 return;
6910         if (!icmp6_m)
6911                 icmp6_m = &rte_flow_item_icmp6_mask;
6912         /*
6913          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6914          * If only the protocol is specified, no need to match the frag.
6915          */
6916         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6917         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6918         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6919         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6920                  icmp6_v->type & icmp6_m->type);
6921         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6922         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6923                  icmp6_v->code & icmp6_m->code);
6924 }
6925
6926 /**
6927  * Add ICMP item to matcher and to the value.
6928  *
6929  * @param[in, out] matcher
6930  *   Flow matcher.
6931  * @param[in, out] key
6932  *   Flow matcher value.
6933  * @param[in] item
6934  *   Flow pattern to translate.
6935  * @param[in] inner
6936  *   Item is inner pattern.
6937  */
6938 static void
6939 flow_dv_translate_item_icmp(void *matcher, void *key,
6940                             const struct rte_flow_item *item,
6941                             int inner)
6942 {
6943         const struct rte_flow_item_icmp *icmp_m = item->mask;
6944         const struct rte_flow_item_icmp *icmp_v = item->spec;
6945         void *headers_m;
6946         void *headers_v;
6947         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6948                                      misc_parameters_3);
6949         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6950         if (inner) {
6951                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6952                                          inner_headers);
6953                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6954         } else {
6955                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6956                                          outer_headers);
6957                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6958         }
6959         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6960         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6961         if (!icmp_v)
6962                 return;
6963         if (!icmp_m)
6964                 icmp_m = &rte_flow_item_icmp_mask;
6965         /*
6966          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6967          * If only the protocol is specified, no need to match the frag.
6968          */
6969         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6970         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6971         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6972                  icmp_m->hdr.icmp_type);
6973         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6974                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6975         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6976                  icmp_m->hdr.icmp_code);
6977         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6978                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6979 }
6980
6981 /**
6982  * Add GTP item to matcher and to the value.
6983  *
6984  * @param[in, out] matcher
6985  *   Flow matcher.
6986  * @param[in, out] key
6987  *   Flow matcher value.
6988  * @param[in] item
6989  *   Flow pattern to translate.
6990  * @param[in] inner
6991  *   Item is inner pattern.
6992  */
6993 static void
6994 flow_dv_translate_item_gtp(void *matcher, void *key,
6995                            const struct rte_flow_item *item, int inner)
6996 {
6997         const struct rte_flow_item_gtp *gtp_m = item->mask;
6998         const struct rte_flow_item_gtp *gtp_v = item->spec;
6999         void *headers_m;
7000         void *headers_v;
7001         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7002                                      misc_parameters_3);
7003         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7004         uint16_t dport = RTE_GTPU_UDP_PORT;
7005
7006         if (inner) {
7007                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7008                                          inner_headers);
7009                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7010         } else {
7011                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7012                                          outer_headers);
7013                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7014         }
7015         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7016                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7017                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7018         }
7019         if (!gtp_v)
7020                 return;
7021         if (!gtp_m)
7022                 gtp_m = &rte_flow_item_gtp_mask;
7023         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7024         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7025                  gtp_v->msg_type & gtp_m->msg_type);
7026         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7027                  rte_be_to_cpu_32(gtp_m->teid));
7028         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7029                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7030 }
7031
7032 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7033
7034 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7035         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7036                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7037
7038 /**
7039  * Calculate flow matcher enable bitmap.
7040  *
7041  * @param match_criteria
7042  *   Pointer to flow matcher criteria.
7043  *
7044  * @return
7045  *   Bitmap of enabled fields.
7046  */
7047 static uint8_t
7048 flow_dv_matcher_enable(uint32_t *match_criteria)
7049 {
7050         uint8_t match_criteria_enable;
7051
7052         match_criteria_enable =
7053                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7054                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7055         match_criteria_enable |=
7056                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7057                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7058         match_criteria_enable |=
7059                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7060                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7061         match_criteria_enable |=
7062                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7063                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7064         match_criteria_enable |=
7065                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7066                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7067         return match_criteria_enable;
7068 }
7069
7070
7071 /**
7072  * Get a flow table.
7073  *
7074  * @param[in, out] dev
7075  *   Pointer to rte_eth_dev structure.
7076  * @param[in] table_id
7077  *   Table id to use.
7078  * @param[in] egress
7079  *   Direction of the table.
7080  * @param[in] transfer
7081  *   E-Switch or NIC flow.
7082  * @param[out] error
7083  *   pointer to error structure.
7084  *
7085  * @return
7086  *   Returns tables resource based on the index, NULL in case of failed.
7087  */
7088 static struct mlx5_flow_tbl_resource *
7089 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7090                          uint32_t table_id, uint8_t egress,
7091                          uint8_t transfer,
7092                          struct rte_flow_error *error)
7093 {
7094         struct mlx5_priv *priv = dev->data->dev_private;
7095         struct mlx5_ibv_shared *sh = priv->sh;
7096         struct mlx5_flow_tbl_resource *tbl;
7097         union mlx5_flow_tbl_key table_key = {
7098                 {
7099                         .table_id = table_id,
7100                         .reserved = 0,
7101                         .domain = !!transfer,
7102                         .direction = !!egress,
7103                 }
7104         };
7105         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7106                                                          table_key.v64);
7107         struct mlx5_flow_tbl_data_entry *tbl_data;
7108         uint32_t idx = 0;
7109         int ret;
7110         void *domain;
7111
7112         if (pos) {
7113                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7114                                         entry);
7115                 tbl = &tbl_data->tbl;
7116                 rte_atomic32_inc(&tbl->refcnt);
7117                 return tbl;
7118         }
7119         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7120         if (!tbl_data) {
7121                 rte_flow_error_set(error, ENOMEM,
7122                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7123                                    NULL,
7124                                    "cannot allocate flow table data entry");
7125                 return NULL;
7126         }
7127         tbl_data->idx = idx;
7128         tbl = &tbl_data->tbl;
7129         pos = &tbl_data->entry;
7130         if (transfer)
7131                 domain = sh->fdb_domain;
7132         else if (egress)
7133                 domain = sh->tx_domain;
7134         else
7135                 domain = sh->rx_domain;
7136         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7137         if (!tbl->obj) {
7138                 rte_flow_error_set(error, ENOMEM,
7139                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7140                                    NULL, "cannot create flow table object");
7141                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7142                 return NULL;
7143         }
7144         /*
7145          * No multi-threads now, but still better to initialize the reference
7146          * count before insert it into the hash list.
7147          */
7148         rte_atomic32_init(&tbl->refcnt);
7149         /* Jump action reference count is initialized here. */
7150         rte_atomic32_init(&tbl_data->jump.refcnt);
7151         pos->key = table_key.v64;
7152         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7153         if (ret < 0) {
7154                 rte_flow_error_set(error, -ret,
7155                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7156                                    "cannot insert flow table data entry");
7157                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7158                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7159         }
7160         rte_atomic32_inc(&tbl->refcnt);
7161         return tbl;
7162 }
7163
7164 /**
7165  * Release a flow table.
7166  *
7167  * @param[in] dev
7168  *   Pointer to rte_eth_dev structure.
7169  * @param[in] tbl
7170  *   Table resource to be released.
7171  *
7172  * @return
7173  *   Returns 0 if table was released, else return 1;
7174  */
7175 static int
7176 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7177                              struct mlx5_flow_tbl_resource *tbl)
7178 {
7179         struct mlx5_priv *priv = dev->data->dev_private;
7180         struct mlx5_ibv_shared *sh = priv->sh;
7181         struct mlx5_flow_tbl_data_entry *tbl_data =
7182                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7183
7184         if (!tbl)
7185                 return 0;
7186         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7187                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7188
7189                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7190                 tbl->obj = NULL;
7191                 /* remove the entry from the hash list and free memory. */
7192                 mlx5_hlist_remove(sh->flow_tbls, pos);
7193                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7194                                 tbl_data->idx);
7195                 return 0;
7196         }
7197         return 1;
7198 }
7199
7200 /**
7201  * Register the flow matcher.
7202  *
7203  * @param[in, out] dev
7204  *   Pointer to rte_eth_dev structure.
7205  * @param[in, out] matcher
7206  *   Pointer to flow matcher.
7207  * @param[in, out] key
7208  *   Pointer to flow table key.
7209  * @parm[in, out] dev_flow
7210  *   Pointer to the dev_flow.
7211  * @param[out] error
7212  *   pointer to error structure.
7213  *
7214  * @return
7215  *   0 on success otherwise -errno and errno is set.
7216  */
7217 static int
7218 flow_dv_matcher_register(struct rte_eth_dev *dev,
7219                          struct mlx5_flow_dv_matcher *matcher,
7220                          union mlx5_flow_tbl_key *key,
7221                          struct mlx5_flow *dev_flow,
7222                          struct rte_flow_error *error)
7223 {
7224         struct mlx5_priv *priv = dev->data->dev_private;
7225         struct mlx5_ibv_shared *sh = priv->sh;
7226         struct mlx5_flow_dv_matcher *cache_matcher;
7227         struct mlx5dv_flow_matcher_attr dv_attr = {
7228                 .type = IBV_FLOW_ATTR_NORMAL,
7229                 .match_mask = (void *)&matcher->mask,
7230         };
7231         struct mlx5_flow_tbl_resource *tbl;
7232         struct mlx5_flow_tbl_data_entry *tbl_data;
7233
7234         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7235                                        key->domain, error);
7236         if (!tbl)
7237                 return -rte_errno;      /* No need to refill the error info */
7238         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7239         /* Lookup from cache. */
7240         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7241                 if (matcher->crc == cache_matcher->crc &&
7242                     matcher->priority == cache_matcher->priority &&
7243                     !memcmp((const void *)matcher->mask.buf,
7244                             (const void *)cache_matcher->mask.buf,
7245                             cache_matcher->mask.size)) {
7246                         DRV_LOG(DEBUG,
7247                                 "%s group %u priority %hd use %s "
7248                                 "matcher %p: refcnt %d++",
7249                                 key->domain ? "FDB" : "NIC", key->table_id,
7250                                 cache_matcher->priority,
7251                                 key->direction ? "tx" : "rx",
7252                                 (void *)cache_matcher,
7253                                 rte_atomic32_read(&cache_matcher->refcnt));
7254                         rte_atomic32_inc(&cache_matcher->refcnt);
7255                         dev_flow->handle->dvh.matcher = cache_matcher;
7256                         /* old matcher should not make the table ref++. */
7257                         flow_dv_tbl_resource_release(dev, tbl);
7258                         return 0;
7259                 }
7260         }
7261         /* Register new matcher. */
7262         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7263         if (!cache_matcher) {
7264                 flow_dv_tbl_resource_release(dev, tbl);
7265                 return rte_flow_error_set(error, ENOMEM,
7266                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7267                                           "cannot allocate matcher memory");
7268         }
7269         *cache_matcher = *matcher;
7270         dv_attr.match_criteria_enable =
7271                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7272         dv_attr.priority = matcher->priority;
7273         if (key->direction)
7274                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7275         cache_matcher->matcher_object =
7276                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7277         if (!cache_matcher->matcher_object) {
7278                 rte_free(cache_matcher);
7279 #ifdef HAVE_MLX5DV_DR
7280                 flow_dv_tbl_resource_release(dev, tbl);
7281 #endif
7282                 return rte_flow_error_set(error, ENOMEM,
7283                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7284                                           NULL, "cannot create matcher");
7285         }
7286         /* Save the table information */
7287         cache_matcher->tbl = tbl;
7288         rte_atomic32_init(&cache_matcher->refcnt);
7289         /* only matcher ref++, table ref++ already done above in get API. */
7290         rte_atomic32_inc(&cache_matcher->refcnt);
7291         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7292         dev_flow->handle->dvh.matcher = cache_matcher;
7293         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7294                 key->domain ? "FDB" : "NIC", key->table_id,
7295                 cache_matcher->priority,
7296                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7297                 rte_atomic32_read(&cache_matcher->refcnt));
7298         return 0;
7299 }
7300
7301 /**
7302  * Find existing tag resource or create and register a new one.
7303  *
7304  * @param dev[in, out]
7305  *   Pointer to rte_eth_dev structure.
7306  * @param[in, out] tag_be24
7307  *   Tag value in big endian then R-shift 8.
7308  * @parm[in, out] dev_flow
7309  *   Pointer to the dev_flow.
7310  * @param[out] error
7311  *   pointer to error structure.
7312  *
7313  * @return
7314  *   0 on success otherwise -errno and errno is set.
7315  */
7316 static int
7317 flow_dv_tag_resource_register
7318                         (struct rte_eth_dev *dev,
7319                          uint32_t tag_be24,
7320                          struct mlx5_flow *dev_flow,
7321                          struct rte_flow_error *error)
7322 {
7323         struct mlx5_priv *priv = dev->data->dev_private;
7324         struct mlx5_ibv_shared *sh = priv->sh;
7325         struct mlx5_flow_dv_tag_resource *cache_resource;
7326         struct mlx5_hlist_entry *entry;
7327
7328         /* Lookup a matching resource from cache. */
7329         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7330         if (entry) {
7331                 cache_resource = container_of
7332                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7333                 rte_atomic32_inc(&cache_resource->refcnt);
7334                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7335                 dev_flow->dv.tag_resource = cache_resource;
7336                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7337                         (void *)cache_resource,
7338                         rte_atomic32_read(&cache_resource->refcnt));
7339                 return 0;
7340         }
7341         /* Register new resource. */
7342         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7343                                        &dev_flow->handle->dvh.rix_tag);
7344         if (!cache_resource)
7345                 return rte_flow_error_set(error, ENOMEM,
7346                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7347                                           "cannot allocate resource memory");
7348         cache_resource->entry.key = (uint64_t)tag_be24;
7349         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7350         if (!cache_resource->action) {
7351                 rte_free(cache_resource);
7352                 return rte_flow_error_set(error, ENOMEM,
7353                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7354                                           NULL, "cannot create action");
7355         }
7356         rte_atomic32_init(&cache_resource->refcnt);
7357         rte_atomic32_inc(&cache_resource->refcnt);
7358         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7359                 mlx5_glue->destroy_flow_action(cache_resource->action);
7360                 rte_free(cache_resource);
7361                 return rte_flow_error_set(error, EEXIST,
7362                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7363                                           NULL, "cannot insert tag");
7364         }
7365         dev_flow->dv.tag_resource = cache_resource;
7366         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7367                 (void *)cache_resource,
7368                 rte_atomic32_read(&cache_resource->refcnt));
7369         return 0;
7370 }
7371
7372 /**
7373  * Release the tag.
7374  *
7375  * @param dev
7376  *   Pointer to Ethernet device.
7377  * @param tag_idx
7378  *   Tag index.
7379  *
7380  * @return
7381  *   1 while a reference on it exists, 0 when freed.
7382  */
7383 static int
7384 flow_dv_tag_release(struct rte_eth_dev *dev,
7385                     uint32_t tag_idx)
7386 {
7387         struct mlx5_priv *priv = dev->data->dev_private;
7388         struct mlx5_ibv_shared *sh = priv->sh;
7389         struct mlx5_flow_dv_tag_resource *tag;
7390
7391         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7392         if (!tag)
7393                 return 0;
7394         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7395                 dev->data->port_id, (void *)tag,
7396                 rte_atomic32_read(&tag->refcnt));
7397         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7398                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7399                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7400                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7401                         dev->data->port_id, (void *)tag);
7402                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7403                 return 0;
7404         }
7405         return 1;
7406 }
7407
7408 /**
7409  * Translate port ID action to vport.
7410  *
7411  * @param[in] dev
7412  *   Pointer to rte_eth_dev structure.
7413  * @param[in] action
7414  *   Pointer to the port ID action.
7415  * @param[out] dst_port_id
7416  *   The target port ID.
7417  * @param[out] error
7418  *   Pointer to the error structure.
7419  *
7420  * @return
7421  *   0 on success, a negative errno value otherwise and rte_errno is set.
7422  */
7423 static int
7424 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7425                                  const struct rte_flow_action *action,
7426                                  uint32_t *dst_port_id,
7427                                  struct rte_flow_error *error)
7428 {
7429         uint32_t port;
7430         struct mlx5_priv *priv;
7431         const struct rte_flow_action_port_id *conf =
7432                         (const struct rte_flow_action_port_id *)action->conf;
7433
7434         port = conf->original ? dev->data->port_id : conf->id;
7435         priv = mlx5_port_to_eswitch_info(port, false);
7436         if (!priv)
7437                 return rte_flow_error_set(error, -rte_errno,
7438                                           RTE_FLOW_ERROR_TYPE_ACTION,
7439                                           NULL,
7440                                           "No eswitch info was found for port");
7441 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7442         /*
7443          * This parameter is transferred to
7444          * mlx5dv_dr_action_create_dest_ib_port().
7445          */
7446         *dst_port_id = priv->ibv_port;
7447 #else
7448         /*
7449          * Legacy mode, no LAG configurations is supported.
7450          * This parameter is transferred to
7451          * mlx5dv_dr_action_create_dest_vport().
7452          */
7453         *dst_port_id = priv->vport_id;
7454 #endif
7455         return 0;
7456 }
7457
7458 /**
7459  * Create a counter with aging configuration.
7460  *
7461  * @param[in] dev
7462  *   Pointer to rte_eth_dev structure.
7463  * @param[out] count
7464  *   Pointer to the counter action configuration.
7465  * @param[in] age
7466  *   Pointer to the aging action configuration.
7467  *
7468  * @return
7469  *   Index to flow counter on success, 0 otherwise.
7470  */
7471 static uint32_t
7472 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7473                                 struct mlx5_flow *dev_flow,
7474                                 const struct rte_flow_action_count *count,
7475                                 const struct rte_flow_action_age *age)
7476 {
7477         uint32_t counter;
7478         struct mlx5_age_param *age_param;
7479
7480         counter = flow_dv_counter_alloc(dev,
7481                                 count ? count->shared : 0,
7482                                 count ? count->id : 0,
7483                                 dev_flow->dv.group, !!age);
7484         if (!counter || age == NULL)
7485                 return counter;
7486         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7487         /*
7488          * The counter age accuracy may have a bit delay. Have 3/4
7489          * second bias on the timeount in order to let it age in time.
7490          */
7491         age_param->context = age->context ? age->context :
7492                 (void *)(uintptr_t)(dev_flow->flow_idx);
7493         /*
7494          * The counter age accuracy may have a bit delay. Have 3/4
7495          * second bias on the timeount in order to let it age in time.
7496          */
7497         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7498         /* Set expire time in unit of 0.1 sec. */
7499         age_param->port_id = dev->data->port_id;
7500         age_param->expire = age_param->timeout +
7501                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7502         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7503         return counter;
7504 }
7505 /**
7506  * Add Tx queue matcher
7507  *
7508  * @param[in] dev
7509  *   Pointer to the dev struct.
7510  * @param[in, out] matcher
7511  *   Flow matcher.
7512  * @param[in, out] key
7513  *   Flow matcher value.
7514  * @param[in] item
7515  *   Flow pattern to translate.
7516  * @param[in] inner
7517  *   Item is inner pattern.
7518  */
7519 static void
7520 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7521                                 void *matcher, void *key,
7522                                 const struct rte_flow_item *item)
7523 {
7524         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7525         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7526         void *misc_m =
7527                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7528         void *misc_v =
7529                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7530         struct mlx5_txq_ctrl *txq;
7531         uint32_t queue;
7532
7533
7534         queue_m = (const void *)item->mask;
7535         if (!queue_m)
7536                 return;
7537         queue_v = (const void *)item->spec;
7538         if (!queue_v)
7539                 return;
7540         txq = mlx5_txq_get(dev, queue_v->queue);
7541         if (!txq)
7542                 return;
7543         queue = txq->obj->sq->id;
7544         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7545         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7546                  queue & queue_m->queue);
7547         mlx5_txq_release(dev, queue_v->queue);
7548 }
7549
7550 /**
7551  * Set the hash fields according to the @p flow information.
7552  *
7553  * @param[in] dev_flow
7554  *   Pointer to the mlx5_flow.
7555  * @param[in] rss_desc
7556  *   Pointer to the mlx5_flow_rss_desc.
7557  */
7558 static void
7559 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7560                        struct mlx5_flow_rss_desc *rss_desc)
7561 {
7562         uint64_t items = dev_flow->handle->layers;
7563         int rss_inner = 0;
7564         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7565
7566         dev_flow->hash_fields = 0;
7567 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7568         if (rss_desc->level >= 2) {
7569                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7570                 rss_inner = 1;
7571         }
7572 #endif
7573         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7574             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7575                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7576                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7577                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7578                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7579                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7580                         else
7581                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7582                 }
7583         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7584                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7585                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7586                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7587                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7588                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7589                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7590                         else
7591                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7592                 }
7593         }
7594         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7595             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7596                 if (rss_types & ETH_RSS_UDP) {
7597                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7598                                 dev_flow->hash_fields |=
7599                                                 IBV_RX_HASH_SRC_PORT_UDP;
7600                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7601                                 dev_flow->hash_fields |=
7602                                                 IBV_RX_HASH_DST_PORT_UDP;
7603                         else
7604                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7605                 }
7606         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7607                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7608                 if (rss_types & ETH_RSS_TCP) {
7609                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7610                                 dev_flow->hash_fields |=
7611                                                 IBV_RX_HASH_SRC_PORT_TCP;
7612                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7613                                 dev_flow->hash_fields |=
7614                                                 IBV_RX_HASH_DST_PORT_TCP;
7615                         else
7616                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7617                 }
7618         }
7619 }
7620
7621 /**
7622  * Fill the flow with DV spec, lock free
7623  * (mutex should be acquired by caller).
7624  *
7625  * @param[in] dev
7626  *   Pointer to rte_eth_dev structure.
7627  * @param[in, out] dev_flow
7628  *   Pointer to the sub flow.
7629  * @param[in] attr
7630  *   Pointer to the flow attributes.
7631  * @param[in] items
7632  *   Pointer to the list of items.
7633  * @param[in] actions
7634  *   Pointer to the list of actions.
7635  * @param[out] error
7636  *   Pointer to the error structure.
7637  *
7638  * @return
7639  *   0 on success, a negative errno value otherwise and rte_errno is set.
7640  */
7641 static int
7642 __flow_dv_translate(struct rte_eth_dev *dev,
7643                     struct mlx5_flow *dev_flow,
7644                     const struct rte_flow_attr *attr,
7645                     const struct rte_flow_item items[],
7646                     const struct rte_flow_action actions[],
7647                     struct rte_flow_error *error)
7648 {
7649         struct mlx5_priv *priv = dev->data->dev_private;
7650         struct mlx5_dev_config *dev_conf = &priv->config;
7651         struct rte_flow *flow = dev_flow->flow;
7652         struct mlx5_flow_handle *handle = dev_flow->handle;
7653         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7654                                               priv->rss_desc)
7655                                               [!!priv->flow_nested_idx];
7656         uint64_t item_flags = 0;
7657         uint64_t last_item = 0;
7658         uint64_t action_flags = 0;
7659         uint64_t priority = attr->priority;
7660         struct mlx5_flow_dv_matcher matcher = {
7661                 .mask = {
7662                         .size = sizeof(matcher.mask.buf),
7663                 },
7664         };
7665         int actions_n = 0;
7666         bool actions_end = false;
7667         union {
7668                 struct mlx5_flow_dv_modify_hdr_resource res;
7669                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7670                             sizeof(struct mlx5_modification_cmd) *
7671                             (MLX5_MAX_MODIFY_NUM + 1)];
7672         } mhdr_dummy;
7673         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7674         const struct rte_flow_action_count *count = NULL;
7675         const struct rte_flow_action_age *age = NULL;
7676         union flow_dv_attr flow_attr = { .attr = 0 };
7677         uint32_t tag_be;
7678         union mlx5_flow_tbl_key tbl_key;
7679         uint32_t modify_action_position = UINT32_MAX;
7680         void *match_mask = matcher.mask.buf;
7681         void *match_value = dev_flow->dv.value.buf;
7682         uint8_t next_protocol = 0xff;
7683         struct rte_vlan_hdr vlan = { 0 };
7684         uint32_t table;
7685         int ret = 0;
7686
7687         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7688                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7689         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7690                                        !!priv->fdb_def_rule, &table, error);
7691         if (ret)
7692                 return ret;
7693         dev_flow->dv.group = table;
7694         if (attr->transfer)
7695                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7696         if (priority == MLX5_FLOW_PRIO_RSVD)
7697                 priority = dev_conf->flow_prio - 1;
7698         /* number of actions must be set to 0 in case of dirty stack. */
7699         mhdr_res->actions_num = 0;
7700         for (; !actions_end ; actions++) {
7701                 const struct rte_flow_action_queue *queue;
7702                 const struct rte_flow_action_rss *rss;
7703                 const struct rte_flow_action *action = actions;
7704                 const uint8_t *rss_key;
7705                 const struct rte_flow_action_jump *jump_data;
7706                 const struct rte_flow_action_meter *mtr;
7707                 struct mlx5_flow_tbl_resource *tbl;
7708                 uint32_t port_id = 0;
7709                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7710                 int action_type = actions->type;
7711                 const struct rte_flow_action *found_action = NULL;
7712                 struct mlx5_flow_meter *fm = NULL;
7713
7714                 switch (action_type) {
7715                 case RTE_FLOW_ACTION_TYPE_VOID:
7716                         break;
7717                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7718                         if (flow_dv_translate_action_port_id(dev, action,
7719                                                              &port_id, error))
7720                                 return -rte_errno;
7721                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7722                         port_id_resource.port_id = port_id;
7723                         if (flow_dv_port_id_action_resource_register
7724                             (dev, &port_id_resource, dev_flow, error))
7725                                 return -rte_errno;
7726                         MLX5_ASSERT(!handle->rix_port_id_action);
7727                         dev_flow->dv.actions[actions_n++] =
7728                                         dev_flow->dv.port_id_action->action;
7729                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7730                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7731                         break;
7732                 case RTE_FLOW_ACTION_TYPE_FLAG:
7733                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7734                         dev_flow->handle->mark = 1;
7735                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7736                                 struct rte_flow_action_mark mark = {
7737                                         .id = MLX5_FLOW_MARK_DEFAULT,
7738                                 };
7739
7740                                 if (flow_dv_convert_action_mark(dev, &mark,
7741                                                                 mhdr_res,
7742                                                                 error))
7743                                         return -rte_errno;
7744                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7745                                 break;
7746                         }
7747                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7748                         /*
7749                          * Only one FLAG or MARK is supported per device flow
7750                          * right now. So the pointer to the tag resource must be
7751                          * zero before the register process.
7752                          */
7753                         MLX5_ASSERT(!handle->dvh.rix_tag);
7754                         if (flow_dv_tag_resource_register(dev, tag_be,
7755                                                           dev_flow, error))
7756                                 return -rte_errno;
7757                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7758                         dev_flow->dv.actions[actions_n++] =
7759                                         dev_flow->dv.tag_resource->action;
7760                         break;
7761                 case RTE_FLOW_ACTION_TYPE_MARK:
7762                         action_flags |= MLX5_FLOW_ACTION_MARK;
7763                         dev_flow->handle->mark = 1;
7764                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7765                                 const struct rte_flow_action_mark *mark =
7766                                         (const struct rte_flow_action_mark *)
7767                                                 actions->conf;
7768
7769                                 if (flow_dv_convert_action_mark(dev, mark,
7770                                                                 mhdr_res,
7771                                                                 error))
7772                                         return -rte_errno;
7773                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7774                                 break;
7775                         }
7776                         /* Fall-through */
7777                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7778                         /* Legacy (non-extensive) MARK action. */
7779                         tag_be = mlx5_flow_mark_set
7780                               (((const struct rte_flow_action_mark *)
7781                                (actions->conf))->id);
7782                         MLX5_ASSERT(!handle->dvh.rix_tag);
7783                         if (flow_dv_tag_resource_register(dev, tag_be,
7784                                                           dev_flow, error))
7785                                 return -rte_errno;
7786                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7787                         dev_flow->dv.actions[actions_n++] =
7788                                         dev_flow->dv.tag_resource->action;
7789                         break;
7790                 case RTE_FLOW_ACTION_TYPE_SET_META:
7791                         if (flow_dv_convert_action_set_meta
7792                                 (dev, mhdr_res, attr,
7793                                  (const struct rte_flow_action_set_meta *)
7794                                   actions->conf, error))
7795                                 return -rte_errno;
7796                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7797                         break;
7798                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7799                         if (flow_dv_convert_action_set_tag
7800                                 (dev, mhdr_res,
7801                                  (const struct rte_flow_action_set_tag *)
7802                                   actions->conf, error))
7803                                 return -rte_errno;
7804                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7805                         break;
7806                 case RTE_FLOW_ACTION_TYPE_DROP:
7807                         action_flags |= MLX5_FLOW_ACTION_DROP;
7808                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7809                         break;
7810                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7811                         queue = actions->conf;
7812                         rss_desc->queue_num = 1;
7813                         rss_desc->queue[0] = queue->index;
7814                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7815                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7816                         break;
7817                 case RTE_FLOW_ACTION_TYPE_RSS:
7818                         rss = actions->conf;
7819                         memcpy(rss_desc->queue, rss->queue,
7820                                rss->queue_num * sizeof(uint16_t));
7821                         rss_desc->queue_num = rss->queue_num;
7822                         /* NULL RSS key indicates default RSS key. */
7823                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7824                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7825                         /*
7826                          * rss->level and rss.types should be set in advance
7827                          * when expanding items for RSS.
7828                          */
7829                         action_flags |= MLX5_FLOW_ACTION_RSS;
7830                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7831                         break;
7832                 case RTE_FLOW_ACTION_TYPE_AGE:
7833                 case RTE_FLOW_ACTION_TYPE_COUNT:
7834                         if (!dev_conf->devx) {
7835                                 return rte_flow_error_set
7836                                               (error, ENOTSUP,
7837                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7838                                                NULL,
7839                                                "count action not supported");
7840                         }
7841                         /* Save information first, will apply later. */
7842                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7843                                 count = action->conf;
7844                         else
7845                                 age = action->conf;
7846                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7847                         break;
7848                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7849                         dev_flow->dv.actions[actions_n++] =
7850                                                 priv->sh->pop_vlan_action;
7851                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7852                         break;
7853                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7854                         if (!(action_flags &
7855                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7856                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7857                         vlan.eth_proto = rte_be_to_cpu_16
7858                              ((((const struct rte_flow_action_of_push_vlan *)
7859                                                    actions->conf)->ethertype));
7860                         found_action = mlx5_flow_find_action
7861                                         (actions + 1,
7862                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7863                         if (found_action)
7864                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7865                         found_action = mlx5_flow_find_action
7866                                         (actions + 1,
7867                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7868                         if (found_action)
7869                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7870                         if (flow_dv_create_action_push_vlan
7871                                             (dev, attr, &vlan, dev_flow, error))
7872                                 return -rte_errno;
7873                         dev_flow->dv.actions[actions_n++] =
7874                                         dev_flow->dv.push_vlan_res->action;
7875                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7876                         break;
7877                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7878                         /* of_vlan_push action handled this action */
7879                         MLX5_ASSERT(action_flags &
7880                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7881                         break;
7882                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7883                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7884                                 break;
7885                         flow_dev_get_vlan_info_from_items(items, &vlan);
7886                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7887                         /* If no VLAN push - this is a modify header action */
7888                         if (flow_dv_convert_action_modify_vlan_vid
7889                                                 (mhdr_res, actions, error))
7890                                 return -rte_errno;
7891                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7892                         break;
7893                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7894                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7895                         if (flow_dv_create_action_l2_encap(dev, actions,
7896                                                            dev_flow,
7897                                                            attr->transfer,
7898                                                            error))
7899                                 return -rte_errno;
7900                         dev_flow->dv.actions[actions_n++] =
7901                                         dev_flow->dv.encap_decap->verbs_action;
7902                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7903                         break;
7904                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7905                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7906                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7907                                                            attr->transfer,
7908                                                            error))
7909                                 return -rte_errno;
7910                         dev_flow->dv.actions[actions_n++] =
7911                                         dev_flow->dv.encap_decap->verbs_action;
7912                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7913                         break;
7914                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7915                         /* Handle encap with preceding decap. */
7916                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7917                                 if (flow_dv_create_action_raw_encap
7918                                         (dev, actions, dev_flow, attr, error))
7919                                         return -rte_errno;
7920                                 dev_flow->dv.actions[actions_n++] =
7921                                         dev_flow->dv.encap_decap->verbs_action;
7922                         } else {
7923                                 /* Handle encap without preceding decap. */
7924                                 if (flow_dv_create_action_l2_encap
7925                                     (dev, actions, dev_flow, attr->transfer,
7926                                      error))
7927                                         return -rte_errno;
7928                                 dev_flow->dv.actions[actions_n++] =
7929                                         dev_flow->dv.encap_decap->verbs_action;
7930                         }
7931                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7932                         break;
7933                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7934                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7935                                 ;
7936                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7937                                 if (flow_dv_create_action_l2_decap
7938                                     (dev, dev_flow, attr->transfer, error))
7939                                         return -rte_errno;
7940                                 dev_flow->dv.actions[actions_n++] =
7941                                         dev_flow->dv.encap_decap->verbs_action;
7942                         }
7943                         /* If decap is followed by encap, handle it at encap. */
7944                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7945                         break;
7946                 case RTE_FLOW_ACTION_TYPE_JUMP:
7947                         jump_data = action->conf;
7948                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7949                                                        jump_data->group,
7950                                                        !!priv->fdb_def_rule,
7951                                                        &table, error);
7952                         if (ret)
7953                                 return ret;
7954                         tbl = flow_dv_tbl_resource_get(dev, table,
7955                                                        attr->egress,
7956                                                        attr->transfer, error);
7957                         if (!tbl)
7958                                 return rte_flow_error_set
7959                                                 (error, errno,
7960                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7961                                                  NULL,
7962                                                  "cannot create jump action.");
7963                         if (flow_dv_jump_tbl_resource_register
7964                             (dev, tbl, dev_flow, error)) {
7965                                 flow_dv_tbl_resource_release(dev, tbl);
7966                                 return rte_flow_error_set
7967                                                 (error, errno,
7968                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7969                                                  NULL,
7970                                                  "cannot create jump action.");
7971                         }
7972                         dev_flow->dv.actions[actions_n++] =
7973                                         dev_flow->dv.jump->action;
7974                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7975                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
7976                         break;
7977                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7978                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7979                         if (flow_dv_convert_action_modify_mac
7980                                         (mhdr_res, actions, error))
7981                                 return -rte_errno;
7982                         action_flags |= actions->type ==
7983                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7984                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7985                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7986                         break;
7987                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7988                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7989                         if (flow_dv_convert_action_modify_ipv4
7990                                         (mhdr_res, actions, error))
7991                                 return -rte_errno;
7992                         action_flags |= actions->type ==
7993                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7994                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7995                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7996                         break;
7997                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7998                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7999                         if (flow_dv_convert_action_modify_ipv6
8000                                         (mhdr_res, actions, error))
8001                                 return -rte_errno;
8002                         action_flags |= actions->type ==
8003                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8004                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8005                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8006                         break;
8007                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8008                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8009                         if (flow_dv_convert_action_modify_tp
8010                                         (mhdr_res, actions, items,
8011                                          &flow_attr, dev_flow, !!(action_flags &
8012                                          MLX5_FLOW_ACTION_DECAP), error))
8013                                 return -rte_errno;
8014                         action_flags |= actions->type ==
8015                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8016                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8017                                         MLX5_FLOW_ACTION_SET_TP_DST;
8018                         break;
8019                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8020                         if (flow_dv_convert_action_modify_dec_ttl
8021                                         (mhdr_res, items, &flow_attr, dev_flow,
8022                                          !!(action_flags &
8023                                          MLX5_FLOW_ACTION_DECAP), error))
8024                                 return -rte_errno;
8025                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8026                         break;
8027                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8028                         if (flow_dv_convert_action_modify_ttl
8029                                         (mhdr_res, actions, items, &flow_attr,
8030                                          dev_flow, !!(action_flags &
8031                                          MLX5_FLOW_ACTION_DECAP), error))
8032                                 return -rte_errno;
8033                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8034                         break;
8035                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8036                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8037                         if (flow_dv_convert_action_modify_tcp_seq
8038                                         (mhdr_res, actions, error))
8039                                 return -rte_errno;
8040                         action_flags |= actions->type ==
8041                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8042                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8043                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8044                         break;
8045
8046                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8047                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8048                         if (flow_dv_convert_action_modify_tcp_ack
8049                                         (mhdr_res, actions, error))
8050                                 return -rte_errno;
8051                         action_flags |= actions->type ==
8052                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8053                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8054                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8055                         break;
8056                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8057                         if (flow_dv_convert_action_set_reg
8058                                         (mhdr_res, actions, error))
8059                                 return -rte_errno;
8060                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8061                         break;
8062                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8063                         if (flow_dv_convert_action_copy_mreg
8064                                         (dev, mhdr_res, actions, error))
8065                                 return -rte_errno;
8066                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8067                         break;
8068                 case RTE_FLOW_ACTION_TYPE_METER:
8069                         mtr = actions->conf;
8070                         if (!flow->meter) {
8071                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8072                                                             attr, error);
8073                                 if (!fm)
8074                                         return rte_flow_error_set(error,
8075                                                 rte_errno,
8076                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8077                                                 NULL,
8078                                                 "meter not found "
8079                                                 "or invalid parameters");
8080                                 flow->meter = fm->idx;
8081                         }
8082                         /* Set the meter action. */
8083                         if (!fm) {
8084                                 fm = mlx5_ipool_get(priv->sh->ipool
8085                                                 [MLX5_IPOOL_MTR], flow->meter);
8086                                 if (!fm)
8087                                         return rte_flow_error_set(error,
8088                                                 rte_errno,
8089                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8090                                                 NULL,
8091                                                 "meter not found "
8092                                                 "or invalid parameters");
8093                         }
8094                         dev_flow->dv.actions[actions_n++] =
8095                                 fm->mfts->meter_action;
8096                         action_flags |= MLX5_FLOW_ACTION_METER;
8097                         break;
8098                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8099                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8100                                                               actions, error))
8101                                 return -rte_errno;
8102                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8103                         break;
8104                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8105                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8106                                                               actions, error))
8107                                 return -rte_errno;
8108                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8109                         break;
8110                 case RTE_FLOW_ACTION_TYPE_END:
8111                         actions_end = true;
8112                         if (mhdr_res->actions_num) {
8113                                 /* create modify action if needed. */
8114                                 if (flow_dv_modify_hdr_resource_register
8115                                         (dev, mhdr_res, dev_flow, error))
8116                                         return -rte_errno;
8117                                 dev_flow->dv.actions[modify_action_position] =
8118                                         handle->dvh.modify_hdr->verbs_action;
8119                         }
8120                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8121                                 flow->counter =
8122                                         flow_dv_translate_create_counter(dev,
8123                                                 dev_flow, count, age);
8124
8125                                 if (!flow->counter)
8126                                         return rte_flow_error_set
8127                                                 (error, rte_errno,
8128                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8129                                                 NULL,
8130                                                 "cannot create counter"
8131                                                 " object.");
8132                                 dev_flow->dv.actions[actions_n++] =
8133                                           (flow_dv_counter_get_by_idx(dev,
8134                                           flow->counter, NULL))->action;
8135                         }
8136                         break;
8137                 default:
8138                         break;
8139                 }
8140                 if (mhdr_res->actions_num &&
8141                     modify_action_position == UINT32_MAX)
8142                         modify_action_position = actions_n++;
8143         }
8144         dev_flow->dv.actions_n = actions_n;
8145         dev_flow->act_flags = action_flags;
8146         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8147                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8148                 int item_type = items->type;
8149
8150                 switch (item_type) {
8151                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8152                         flow_dv_translate_item_port_id(dev, match_mask,
8153                                                        match_value, items);
8154                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8155                         break;
8156                 case RTE_FLOW_ITEM_TYPE_ETH:
8157                         flow_dv_translate_item_eth(match_mask, match_value,
8158                                                    items, tunnel);
8159                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8160                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8161                                              MLX5_FLOW_LAYER_OUTER_L2;
8162                         break;
8163                 case RTE_FLOW_ITEM_TYPE_VLAN:
8164                         flow_dv_translate_item_vlan(dev_flow,
8165                                                     match_mask, match_value,
8166                                                     items, tunnel);
8167                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8168                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8169                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8170                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8171                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8172                         break;
8173                 case RTE_FLOW_ITEM_TYPE_IPV4:
8174                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8175                                                   &item_flags, &tunnel);
8176                         flow_dv_translate_item_ipv4(match_mask, match_value,
8177                                                     items, item_flags, tunnel,
8178                                                     dev_flow->dv.group);
8179                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8180                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8181                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8182                         if (items->mask != NULL &&
8183                             ((const struct rte_flow_item_ipv4 *)
8184                              items->mask)->hdr.next_proto_id) {
8185                                 next_protocol =
8186                                         ((const struct rte_flow_item_ipv4 *)
8187                                          (items->spec))->hdr.next_proto_id;
8188                                 next_protocol &=
8189                                         ((const struct rte_flow_item_ipv4 *)
8190                                          (items->mask))->hdr.next_proto_id;
8191                         } else {
8192                                 /* Reset for inner layer. */
8193                                 next_protocol = 0xff;
8194                         }
8195                         break;
8196                 case RTE_FLOW_ITEM_TYPE_IPV6:
8197                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8198                                                   &item_flags, &tunnel);
8199                         flow_dv_translate_item_ipv6(match_mask, match_value,
8200                                                     items, item_flags, tunnel,
8201                                                     dev_flow->dv.group);
8202                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8203                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8204                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8205                         if (items->mask != NULL &&
8206                             ((const struct rte_flow_item_ipv6 *)
8207                              items->mask)->hdr.proto) {
8208                                 next_protocol =
8209                                         ((const struct rte_flow_item_ipv6 *)
8210                                          items->spec)->hdr.proto;
8211                                 next_protocol &=
8212                                         ((const struct rte_flow_item_ipv6 *)
8213                                          items->mask)->hdr.proto;
8214                         } else {
8215                                 /* Reset for inner layer. */
8216                                 next_protocol = 0xff;
8217                         }
8218                         break;
8219                 case RTE_FLOW_ITEM_TYPE_TCP:
8220                         flow_dv_translate_item_tcp(match_mask, match_value,
8221                                                    items, tunnel);
8222                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8223                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8224                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8225                         break;
8226                 case RTE_FLOW_ITEM_TYPE_UDP:
8227                         flow_dv_translate_item_udp(match_mask, match_value,
8228                                                    items, tunnel);
8229                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8230                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8231                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8232                         break;
8233                 case RTE_FLOW_ITEM_TYPE_GRE:
8234                         flow_dv_translate_item_gre(match_mask, match_value,
8235                                                    items, tunnel);
8236                         matcher.priority = rss_desc->level >= 2 ?
8237                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8238                         last_item = MLX5_FLOW_LAYER_GRE;
8239                         break;
8240                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8241                         flow_dv_translate_item_gre_key(match_mask,
8242                                                        match_value, items);
8243                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8244                         break;
8245                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8246                         flow_dv_translate_item_nvgre(match_mask, match_value,
8247                                                      items, tunnel);
8248                         matcher.priority = rss_desc->level >= 2 ?
8249                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8250                         last_item = MLX5_FLOW_LAYER_GRE;
8251                         break;
8252                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8253                         flow_dv_translate_item_vxlan(match_mask, match_value,
8254                                                      items, tunnel);
8255                         matcher.priority = rss_desc->level >= 2 ?
8256                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8257                         last_item = MLX5_FLOW_LAYER_VXLAN;
8258                         break;
8259                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8260                         flow_dv_translate_item_vxlan_gpe(match_mask,
8261                                                          match_value, items,
8262                                                          tunnel);
8263                         matcher.priority = rss_desc->level >= 2 ?
8264                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8265                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8266                         break;
8267                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8268                         flow_dv_translate_item_geneve(match_mask, match_value,
8269                                                       items, tunnel);
8270                         matcher.priority = rss_desc->level >= 2 ?
8271                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8272                         last_item = MLX5_FLOW_LAYER_GENEVE;
8273                         break;
8274                 case RTE_FLOW_ITEM_TYPE_MPLS:
8275                         flow_dv_translate_item_mpls(match_mask, match_value,
8276                                                     items, last_item, tunnel);
8277                         matcher.priority = rss_desc->level >= 2 ?
8278                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8279                         last_item = MLX5_FLOW_LAYER_MPLS;
8280                         break;
8281                 case RTE_FLOW_ITEM_TYPE_MARK:
8282                         flow_dv_translate_item_mark(dev, match_mask,
8283                                                     match_value, items);
8284                         last_item = MLX5_FLOW_ITEM_MARK;
8285                         break;
8286                 case RTE_FLOW_ITEM_TYPE_META:
8287                         flow_dv_translate_item_meta(dev, match_mask,
8288                                                     match_value, attr, items);
8289                         last_item = MLX5_FLOW_ITEM_METADATA;
8290                         break;
8291                 case RTE_FLOW_ITEM_TYPE_ICMP:
8292                         flow_dv_translate_item_icmp(match_mask, match_value,
8293                                                     items, tunnel);
8294                         last_item = MLX5_FLOW_LAYER_ICMP;
8295                         break;
8296                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8297                         flow_dv_translate_item_icmp6(match_mask, match_value,
8298                                                       items, tunnel);
8299                         last_item = MLX5_FLOW_LAYER_ICMP6;
8300                         break;
8301                 case RTE_FLOW_ITEM_TYPE_TAG:
8302                         flow_dv_translate_item_tag(dev, match_mask,
8303                                                    match_value, items);
8304                         last_item = MLX5_FLOW_ITEM_TAG;
8305                         break;
8306                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8307                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8308                                                         match_value, items);
8309                         last_item = MLX5_FLOW_ITEM_TAG;
8310                         break;
8311                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8312                         flow_dv_translate_item_tx_queue(dev, match_mask,
8313                                                         match_value,
8314                                                         items);
8315                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8316                         break;
8317                 case RTE_FLOW_ITEM_TYPE_GTP:
8318                         flow_dv_translate_item_gtp(match_mask, match_value,
8319                                                    items, tunnel);
8320                         matcher.priority = rss_desc->level >= 2 ?
8321                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8322                         last_item = MLX5_FLOW_LAYER_GTP;
8323                         break;
8324                 default:
8325                         break;
8326                 }
8327                 item_flags |= last_item;
8328         }
8329         /*
8330          * When E-Switch mode is enabled, we have two cases where we need to
8331          * set the source port manually.
8332          * The first one, is in case of Nic steering rule, and the second is
8333          * E-Switch rule where no port_id item was found. In both cases
8334          * the source port is set according the current port in use.
8335          */
8336         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8337             (priv->representor || priv->master)) {
8338                 if (flow_dv_translate_item_port_id(dev, match_mask,
8339                                                    match_value, NULL))
8340                         return -rte_errno;
8341         }
8342 #ifdef RTE_LIBRTE_MLX5_DEBUG
8343         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8344                                               dev_flow->dv.value.buf));
8345 #endif
8346         /*
8347          * Layers may be already initialized from prefix flow if this dev_flow
8348          * is the suffix flow.
8349          */
8350         handle->layers |= item_flags;
8351         if (action_flags & MLX5_FLOW_ACTION_RSS)
8352                 flow_dv_hashfields_set(dev_flow, rss_desc);
8353         /* Register matcher. */
8354         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8355                                     matcher.mask.size);
8356         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8357                                                      matcher.priority);
8358         /* reserved field no needs to be set to 0 here. */
8359         tbl_key.domain = attr->transfer;
8360         tbl_key.direction = attr->egress;
8361         tbl_key.table_id = dev_flow->dv.group;
8362         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8363                 return -rte_errno;
8364         return 0;
8365 }
8366
8367 /**
8368  * Apply the flow to the NIC, lock free,
8369  * (mutex should be acquired by caller).
8370  *
8371  * @param[in] dev
8372  *   Pointer to the Ethernet device structure.
8373  * @param[in, out] flow
8374  *   Pointer to flow structure.
8375  * @param[out] error
8376  *   Pointer to error structure.
8377  *
8378  * @return
8379  *   0 on success, a negative errno value otherwise and rte_errno is set.
8380  */
8381 static int
8382 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8383                 struct rte_flow_error *error)
8384 {
8385         struct mlx5_flow_dv_workspace *dv;
8386         struct mlx5_flow_handle *dh;
8387         struct mlx5_flow_handle_dv *dv_h;
8388         struct mlx5_flow *dev_flow;
8389         struct mlx5_priv *priv = dev->data->dev_private;
8390         uint32_t handle_idx;
8391         int n;
8392         int err;
8393         int idx;
8394
8395         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8396                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8397                 dv = &dev_flow->dv;
8398                 dh = dev_flow->handle;
8399                 dv_h = &dh->dvh;
8400                 n = dv->actions_n;
8401                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8402                         if (dv->transfer) {
8403                                 dv->actions[n++] = priv->sh->esw_drop_action;
8404                         } else {
8405                                 struct mlx5_hrxq *drop_hrxq;
8406                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8407                                 if (!drop_hrxq) {
8408                                         rte_flow_error_set
8409                                                 (error, errno,
8410                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8411                                                  NULL,
8412                                                  "cannot get drop hash queue");
8413                                         goto error;
8414                                 }
8415                                 /*
8416                                  * Drop queues will be released by the specify
8417                                  * mlx5_hrxq_drop_release() function. Assign
8418                                  * the special index to hrxq to mark the queue
8419                                  * has been allocated.
8420                                  */
8421                                 dh->rix_hrxq = UINT32_MAX;
8422                                 dv->actions[n++] = drop_hrxq->action;
8423                         }
8424                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8425                         struct mlx5_hrxq *hrxq;
8426                         uint32_t hrxq_idx;
8427                         struct mlx5_flow_rss_desc *rss_desc =
8428                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8429                                 [!!priv->flow_nested_idx];
8430
8431                         MLX5_ASSERT(rss_desc->queue_num);
8432                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8433                                                  MLX5_RSS_HASH_KEY_LEN,
8434                                                  dev_flow->hash_fields,
8435                                                  rss_desc->queue,
8436                                                  rss_desc->queue_num);
8437                         if (!hrxq_idx) {
8438                                 hrxq_idx = mlx5_hrxq_new
8439                                                 (dev, rss_desc->key,
8440                                                 MLX5_RSS_HASH_KEY_LEN,
8441                                                 dev_flow->hash_fields,
8442                                                 rss_desc->queue,
8443                                                 rss_desc->queue_num,
8444                                                 !!(dh->layers &
8445                                                 MLX5_FLOW_LAYER_TUNNEL));
8446                         }
8447                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8448                                               hrxq_idx);
8449                         if (!hrxq) {
8450                                 rte_flow_error_set
8451                                         (error, rte_errno,
8452                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8453                                          "cannot get hash queue");
8454                                 goto error;
8455                         }
8456                         dh->rix_hrxq = hrxq_idx;
8457                         dv->actions[n++] = hrxq->action;
8458                 }
8459                 dh->ib_flow =
8460                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8461                                                   (void *)&dv->value, n,
8462                                                   dv->actions);
8463                 if (!dh->ib_flow) {
8464                         rte_flow_error_set(error, errno,
8465                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8466                                            NULL,
8467                                            "hardware refuses to create flow");
8468                         goto error;
8469                 }
8470                 if (priv->vmwa_context &&
8471                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8472                         /*
8473                          * The rule contains the VLAN pattern.
8474                          * For VF we are going to create VLAN
8475                          * interface to make hypervisor set correct
8476                          * e-Switch vport context.
8477                          */
8478                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8479                 }
8480         }
8481         return 0;
8482 error:
8483         err = rte_errno; /* Save rte_errno before cleanup. */
8484         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8485                        handle_idx, dh, next) {
8486                 /* hrxq is union, don't clear it if the flag is not set. */
8487                 if (dh->rix_hrxq) {
8488                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8489                                 mlx5_hrxq_drop_release(dev);
8490                                 dh->rix_hrxq = 0;
8491                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8492                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8493                                 dh->rix_hrxq = 0;
8494                         }
8495                 }
8496                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8497                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8498         }
8499         rte_errno = err; /* Restore rte_errno. */
8500         return -rte_errno;
8501 }
8502
8503 /**
8504  * Release the flow matcher.
8505  *
8506  * @param dev
8507  *   Pointer to Ethernet device.
8508  * @param handle
8509  *   Pointer to mlx5_flow_handle.
8510  *
8511  * @return
8512  *   1 while a reference on it exists, 0 when freed.
8513  */
8514 static int
8515 flow_dv_matcher_release(struct rte_eth_dev *dev,
8516                         struct mlx5_flow_handle *handle)
8517 {
8518         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8519
8520         MLX5_ASSERT(matcher->matcher_object);
8521         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8522                 dev->data->port_id, (void *)matcher,
8523                 rte_atomic32_read(&matcher->refcnt));
8524         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8525                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8526                            (matcher->matcher_object));
8527                 LIST_REMOVE(matcher, next);
8528                 /* table ref-- in release interface. */
8529                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8530                 rte_free(matcher);
8531                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8532                         dev->data->port_id, (void *)matcher);
8533                 return 0;
8534         }
8535         return 1;
8536 }
8537
8538 /**
8539  * Release an encap/decap resource.
8540  *
8541  * @param dev
8542  *   Pointer to Ethernet device.
8543  * @param handle
8544  *   Pointer to mlx5_flow_handle.
8545  *
8546  * @return
8547  *   1 while a reference on it exists, 0 when freed.
8548  */
8549 static int
8550 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8551                                      struct mlx5_flow_handle *handle)
8552 {
8553         struct mlx5_priv *priv = dev->data->dev_private;
8554         uint32_t idx = handle->dvh.rix_encap_decap;
8555         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8556
8557         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8558                          idx);
8559         if (!cache_resource)
8560                 return 0;
8561         MLX5_ASSERT(cache_resource->verbs_action);
8562         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8563                 (void *)cache_resource,
8564                 rte_atomic32_read(&cache_resource->refcnt));
8565         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8566                 claim_zero(mlx5_glue->destroy_flow_action
8567                                 (cache_resource->verbs_action));
8568                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8569                              &priv->sh->encaps_decaps, idx,
8570                              cache_resource, next);
8571                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8572                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8573                         (void *)cache_resource);
8574                 return 0;
8575         }
8576         return 1;
8577 }
8578
8579 /**
8580  * Release an jump to table action resource.
8581  *
8582  * @param dev
8583  *   Pointer to Ethernet device.
8584  * @param handle
8585  *   Pointer to mlx5_flow_handle.
8586  *
8587  * @return
8588  *   1 while a reference on it exists, 0 when freed.
8589  */
8590 static int
8591 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8592                                   struct mlx5_flow_handle *handle)
8593 {
8594         struct mlx5_priv *priv = dev->data->dev_private;
8595         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8596         struct mlx5_flow_tbl_data_entry *tbl_data;
8597
8598         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8599                              handle->rix_jump);
8600         if (!tbl_data)
8601                 return 0;
8602         cache_resource = &tbl_data->jump;
8603         MLX5_ASSERT(cache_resource->action);
8604         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8605                 (void *)cache_resource,
8606                 rte_atomic32_read(&cache_resource->refcnt));
8607         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8608                 claim_zero(mlx5_glue->destroy_flow_action
8609                                 (cache_resource->action));
8610                 /* jump action memory free is inside the table release. */
8611                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8612                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8613                         (void *)cache_resource);
8614                 return 0;
8615         }
8616         return 1;
8617 }
8618
8619 /**
8620  * Release a modify-header resource.
8621  *
8622  * @param handle
8623  *   Pointer to mlx5_flow_handle.
8624  *
8625  * @return
8626  *   1 while a reference on it exists, 0 when freed.
8627  */
8628 static int
8629 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8630 {
8631         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8632                                                         handle->dvh.modify_hdr;
8633
8634         MLX5_ASSERT(cache_resource->verbs_action);
8635         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8636                 (void *)cache_resource,
8637                 rte_atomic32_read(&cache_resource->refcnt));
8638         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8639                 claim_zero(mlx5_glue->destroy_flow_action
8640                                 (cache_resource->verbs_action));
8641                 LIST_REMOVE(cache_resource, next);
8642                 rte_free(cache_resource);
8643                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8644                         (void *)cache_resource);
8645                 return 0;
8646         }
8647         return 1;
8648 }
8649
8650 /**
8651  * Release port ID action resource.
8652  *
8653  * @param dev
8654  *   Pointer to Ethernet device.
8655  * @param handle
8656  *   Pointer to mlx5_flow_handle.
8657  *
8658  * @return
8659  *   1 while a reference on it exists, 0 when freed.
8660  */
8661 static int
8662 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8663                                         struct mlx5_flow_handle *handle)
8664 {
8665         struct mlx5_priv *priv = dev->data->dev_private;
8666         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8667         uint32_t idx = handle->rix_port_id_action;
8668
8669         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8670                                         idx);
8671         if (!cache_resource)
8672                 return 0;
8673         MLX5_ASSERT(cache_resource->action);
8674         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8675                 (void *)cache_resource,
8676                 rte_atomic32_read(&cache_resource->refcnt));
8677         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8678                 claim_zero(mlx5_glue->destroy_flow_action
8679                                 (cache_resource->action));
8680                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8681                              &priv->sh->port_id_action_list, idx,
8682                              cache_resource, next);
8683                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8684                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8685                         (void *)cache_resource);
8686                 return 0;
8687         }
8688         return 1;
8689 }
8690
8691 /**
8692  * Release push vlan action resource.
8693  *
8694  * @param dev
8695  *   Pointer to Ethernet device.
8696  * @param handle
8697  *   Pointer to mlx5_flow_handle.
8698  *
8699  * @return
8700  *   1 while a reference on it exists, 0 when freed.
8701  */
8702 static int
8703 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8704                                           struct mlx5_flow_handle *handle)
8705 {
8706         struct mlx5_priv *priv = dev->data->dev_private;
8707         uint32_t idx = handle->dvh.rix_push_vlan;
8708         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8709
8710         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8711                                         idx);
8712         if (!cache_resource)
8713                 return 0;
8714         MLX5_ASSERT(cache_resource->action);
8715         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8716                 (void *)cache_resource,
8717                 rte_atomic32_read(&cache_resource->refcnt));
8718         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8719                 claim_zero(mlx5_glue->destroy_flow_action
8720                                 (cache_resource->action));
8721                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8722                              &priv->sh->push_vlan_action_list, idx,
8723                              cache_resource, next);
8724                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8725                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8726                         (void *)cache_resource);
8727                 return 0;
8728         }
8729         return 1;
8730 }
8731
8732 /**
8733  * Release the fate resource.
8734  *
8735  * @param dev
8736  *   Pointer to Ethernet device.
8737  * @param handle
8738  *   Pointer to mlx5_flow_handle.
8739  */
8740 static void
8741 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8742                                struct mlx5_flow_handle *handle)
8743 {
8744         if (!handle->rix_fate)
8745                 return;
8746         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8747                 mlx5_hrxq_drop_release(dev);
8748         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8749                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8750         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8751                 flow_dv_jump_tbl_resource_release(dev, handle);
8752         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8753                 flow_dv_port_id_action_resource_release(dev, handle);
8754         else
8755                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8756         handle->rix_fate = 0;
8757 }
8758
8759 /**
8760  * Remove the flow from the NIC but keeps it in memory.
8761  * Lock free, (mutex should be acquired by caller).
8762  *
8763  * @param[in] dev
8764  *   Pointer to Ethernet device.
8765  * @param[in, out] flow
8766  *   Pointer to flow structure.
8767  */
8768 static void
8769 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8770 {
8771         struct mlx5_flow_handle *dh;
8772         uint32_t handle_idx;
8773         struct mlx5_priv *priv = dev->data->dev_private;
8774
8775         if (!flow)
8776                 return;
8777         handle_idx = flow->dev_handles;
8778         while (handle_idx) {
8779                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8780                                     handle_idx);
8781                 if (!dh)
8782                         return;
8783                 if (dh->ib_flow) {
8784                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8785                         dh->ib_flow = NULL;
8786                 }
8787                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8788                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8789                         flow_dv_fate_resource_release(dev, dh);
8790                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8791                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8792                 handle_idx = dh->next.next;
8793         }
8794 }
8795
8796 /**
8797  * Remove the flow from the NIC and the memory.
8798  * Lock free, (mutex should be acquired by caller).
8799  *
8800  * @param[in] dev
8801  *   Pointer to the Ethernet device structure.
8802  * @param[in, out] flow
8803  *   Pointer to flow structure.
8804  */
8805 static void
8806 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8807 {
8808         struct mlx5_flow_handle *dev_handle;
8809         struct mlx5_priv *priv = dev->data->dev_private;
8810
8811         if (!flow)
8812                 return;
8813         __flow_dv_remove(dev, flow);
8814         if (flow->counter) {
8815                 flow_dv_counter_release(dev, flow->counter);
8816                 flow->counter = 0;
8817         }
8818         if (flow->meter) {
8819                 struct mlx5_flow_meter *fm;
8820
8821                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8822                                     flow->meter);
8823                 if (fm)
8824                         mlx5_flow_meter_detach(fm);
8825                 flow->meter = 0;
8826         }
8827         while (flow->dev_handles) {
8828                 uint32_t tmp_idx = flow->dev_handles;
8829
8830                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8831                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8832                 if (!dev_handle)
8833                         return;
8834                 flow->dev_handles = dev_handle->next.next;
8835                 if (dev_handle->dvh.matcher)
8836                         flow_dv_matcher_release(dev, dev_handle);
8837                 if (dev_handle->dvh.rix_encap_decap)
8838                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8839                 if (dev_handle->dvh.modify_hdr)
8840                         flow_dv_modify_hdr_resource_release(dev_handle);
8841                 if (dev_handle->dvh.rix_push_vlan)
8842                         flow_dv_push_vlan_action_resource_release(dev,
8843                                                                   dev_handle);
8844                 if (dev_handle->dvh.rix_tag)
8845                         flow_dv_tag_release(dev,
8846                                             dev_handle->dvh.rix_tag);
8847                 flow_dv_fate_resource_release(dev, dev_handle);
8848                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8849                            tmp_idx);
8850         }
8851 }
8852
8853 /**
8854  * Query a dv flow  rule for its statistics via devx.
8855  *
8856  * @param[in] dev
8857  *   Pointer to Ethernet device.
8858  * @param[in] flow
8859  *   Pointer to the sub flow.
8860  * @param[out] data
8861  *   data retrieved by the query.
8862  * @param[out] error
8863  *   Perform verbose error reporting if not NULL.
8864  *
8865  * @return
8866  *   0 on success, a negative errno value otherwise and rte_errno is set.
8867  */
8868 static int
8869 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8870                     void *data, struct rte_flow_error *error)
8871 {
8872         struct mlx5_priv *priv = dev->data->dev_private;
8873         struct rte_flow_query_count *qc = data;
8874
8875         if (!priv->config.devx)
8876                 return rte_flow_error_set(error, ENOTSUP,
8877                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8878                                           NULL,
8879                                           "counters are not supported");
8880         if (flow->counter) {
8881                 uint64_t pkts, bytes;
8882                 struct mlx5_flow_counter *cnt;
8883
8884                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8885                                                  NULL);
8886                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8887                                                &bytes);
8888
8889                 if (err)
8890                         return rte_flow_error_set(error, -err,
8891                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8892                                         NULL, "cannot read counters");
8893                 qc->hits_set = 1;
8894                 qc->bytes_set = 1;
8895                 qc->hits = pkts - cnt->hits;
8896                 qc->bytes = bytes - cnt->bytes;
8897                 if (qc->reset) {
8898                         cnt->hits = pkts;
8899                         cnt->bytes = bytes;
8900                 }
8901                 return 0;
8902         }
8903         return rte_flow_error_set(error, EINVAL,
8904                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8905                                   NULL,
8906                                   "counters are not available");
8907 }
8908
8909 /**
8910  * Query a flow.
8911  *
8912  * @see rte_flow_query()
8913  * @see rte_flow_ops
8914  */
8915 static int
8916 flow_dv_query(struct rte_eth_dev *dev,
8917               struct rte_flow *flow __rte_unused,
8918               const struct rte_flow_action *actions __rte_unused,
8919               void *data __rte_unused,
8920               struct rte_flow_error *error __rte_unused)
8921 {
8922         int ret = -EINVAL;
8923
8924         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8925                 switch (actions->type) {
8926                 case RTE_FLOW_ACTION_TYPE_VOID:
8927                         break;
8928                 case RTE_FLOW_ACTION_TYPE_COUNT:
8929                         ret = flow_dv_query_count(dev, flow, data, error);
8930                         break;
8931                 default:
8932                         return rte_flow_error_set(error, ENOTSUP,
8933                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8934                                                   actions,
8935                                                   "action not supported");
8936                 }
8937         }
8938         return ret;
8939 }
8940
8941 /**
8942  * Destroy the meter table set.
8943  * Lock free, (mutex should be acquired by caller).
8944  *
8945  * @param[in] dev
8946  *   Pointer to Ethernet device.
8947  * @param[in] tbl
8948  *   Pointer to the meter table set.
8949  *
8950  * @return
8951  *   Always 0.
8952  */
8953 static int
8954 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8955                         struct mlx5_meter_domains_infos *tbl)
8956 {
8957         struct mlx5_priv *priv = dev->data->dev_private;
8958         struct mlx5_meter_domains_infos *mtd =
8959                                 (struct mlx5_meter_domains_infos *)tbl;
8960
8961         if (!mtd || !priv->config.dv_flow_en)
8962                 return 0;
8963         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8964                 claim_zero(mlx5_glue->dv_destroy_flow
8965                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8966         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8967                 claim_zero(mlx5_glue->dv_destroy_flow
8968                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8969         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8970                 claim_zero(mlx5_glue->dv_destroy_flow
8971                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8972         if (mtd->egress.color_matcher)
8973                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8974                           (mtd->egress.color_matcher));
8975         if (mtd->egress.any_matcher)
8976                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8977                           (mtd->egress.any_matcher));
8978         if (mtd->egress.tbl)
8979                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
8980         if (mtd->egress.sfx_tbl)
8981                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
8982         if (mtd->ingress.color_matcher)
8983                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8984                           (mtd->ingress.color_matcher));
8985         if (mtd->ingress.any_matcher)
8986                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8987                           (mtd->ingress.any_matcher));
8988         if (mtd->ingress.tbl)
8989                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
8990         if (mtd->ingress.sfx_tbl)
8991                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
8992         if (mtd->transfer.color_matcher)
8993                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8994                           (mtd->transfer.color_matcher));
8995         if (mtd->transfer.any_matcher)
8996                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8997                           (mtd->transfer.any_matcher));
8998         if (mtd->transfer.tbl)
8999                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9000         if (mtd->transfer.sfx_tbl)
9001                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9002         if (mtd->drop_actn)
9003                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9004         rte_free(mtd);
9005         return 0;
9006 }
9007
9008 /* Number of meter flow actions, count and jump or count and drop. */
9009 #define METER_ACTIONS 2
9010
9011 /**
9012  * Create specify domain meter table and suffix table.
9013  *
9014  * @param[in] dev
9015  *   Pointer to Ethernet device.
9016  * @param[in,out] mtb
9017  *   Pointer to DV meter table set.
9018  * @param[in] egress
9019  *   Table attribute.
9020  * @param[in] transfer
9021  *   Table attribute.
9022  * @param[in] color_reg_c_idx
9023  *   Reg C index for color match.
9024  *
9025  * @return
9026  *   0 on success, -1 otherwise and rte_errno is set.
9027  */
9028 static int
9029 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9030                            struct mlx5_meter_domains_infos *mtb,
9031                            uint8_t egress, uint8_t transfer,
9032                            uint32_t color_reg_c_idx)
9033 {
9034         struct mlx5_priv *priv = dev->data->dev_private;
9035         struct mlx5_ibv_shared *sh = priv->sh;
9036         struct mlx5_flow_dv_match_params mask = {
9037                 .size = sizeof(mask.buf),
9038         };
9039         struct mlx5_flow_dv_match_params value = {
9040                 .size = sizeof(value.buf),
9041         };
9042         struct mlx5dv_flow_matcher_attr dv_attr = {
9043                 .type = IBV_FLOW_ATTR_NORMAL,
9044                 .priority = 0,
9045                 .match_criteria_enable = 0,
9046                 .match_mask = (void *)&mask,
9047         };
9048         void *actions[METER_ACTIONS];
9049         struct mlx5_meter_domain_info *dtb;
9050         struct rte_flow_error error;
9051         int i = 0;
9052
9053         if (transfer)
9054                 dtb = &mtb->transfer;
9055         else if (egress)
9056                 dtb = &mtb->egress;
9057         else
9058                 dtb = &mtb->ingress;
9059         /* Create the meter table with METER level. */
9060         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9061                                             egress, transfer, &error);
9062         if (!dtb->tbl) {
9063                 DRV_LOG(ERR, "Failed to create meter policer table.");
9064                 return -1;
9065         }
9066         /* Create the meter suffix table with SUFFIX level. */
9067         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9068                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9069                                             egress, transfer, &error);
9070         if (!dtb->sfx_tbl) {
9071                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9072                 return -1;
9073         }
9074         /* Create matchers, Any and Color. */
9075         dv_attr.priority = 3;
9076         dv_attr.match_criteria_enable = 0;
9077         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9078                                                              &dv_attr,
9079                                                              dtb->tbl->obj);
9080         if (!dtb->any_matcher) {
9081                 DRV_LOG(ERR, "Failed to create meter"
9082                              " policer default matcher.");
9083                 goto error_exit;
9084         }
9085         dv_attr.priority = 0;
9086         dv_attr.match_criteria_enable =
9087                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9088         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9089                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9090         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9091                                                                &dv_attr,
9092                                                                dtb->tbl->obj);
9093         if (!dtb->color_matcher) {
9094                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9095                 goto error_exit;
9096         }
9097         if (mtb->count_actns[RTE_MTR_DROPPED])
9098                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9099         actions[i++] = mtb->drop_actn;
9100         /* Default rule: lowest priority, match any, actions: drop. */
9101         dtb->policer_rules[RTE_MTR_DROPPED] =
9102                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9103                                                  (void *)&value, i, actions);
9104         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9105                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9106                 goto error_exit;
9107         }
9108         return 0;
9109 error_exit:
9110         return -1;
9111 }
9112
9113 /**
9114  * Create the needed meter and suffix tables.
9115  * Lock free, (mutex should be acquired by caller).
9116  *
9117  * @param[in] dev
9118  *   Pointer to Ethernet device.
9119  * @param[in] fm
9120  *   Pointer to the flow meter.
9121  *
9122  * @return
9123  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9124  */
9125 static struct mlx5_meter_domains_infos *
9126 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9127                        const struct mlx5_flow_meter *fm)
9128 {
9129         struct mlx5_priv *priv = dev->data->dev_private;
9130         struct mlx5_meter_domains_infos *mtb;
9131         int ret;
9132         int i;
9133
9134         if (!priv->mtr_en) {
9135                 rte_errno = ENOTSUP;
9136                 return NULL;
9137         }
9138         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9139         if (!mtb) {
9140                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9141                 return NULL;
9142         }
9143         /* Create meter count actions */
9144         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9145                 struct mlx5_flow_counter *cnt;
9146                 if (!fm->policer_stats.cnt[i])
9147                         continue;
9148                 cnt = flow_dv_counter_get_by_idx(dev,
9149                       fm->policer_stats.cnt[i], NULL);
9150                 mtb->count_actns[i] = cnt->action;
9151         }
9152         /* Create drop action. */
9153         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9154         if (!mtb->drop_actn) {
9155                 DRV_LOG(ERR, "Failed to create drop action.");
9156                 goto error_exit;
9157         }
9158         /* Egress meter table. */
9159         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9160         if (ret) {
9161                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9162                 goto error_exit;
9163         }
9164         /* Ingress meter table. */
9165         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9166         if (ret) {
9167                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9168                 goto error_exit;
9169         }
9170         /* FDB meter table. */
9171         if (priv->config.dv_esw_en) {
9172                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9173                                                  priv->mtr_color_reg);
9174                 if (ret) {
9175                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9176                         goto error_exit;
9177                 }
9178         }
9179         return mtb;
9180 error_exit:
9181         flow_dv_destroy_mtr_tbl(dev, mtb);
9182         return NULL;
9183 }
9184
9185 /**
9186  * Destroy domain policer rule.
9187  *
9188  * @param[in] dt
9189  *   Pointer to domain table.
9190  */
9191 static void
9192 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9193 {
9194         int i;
9195
9196         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9197                 if (dt->policer_rules[i]) {
9198                         claim_zero(mlx5_glue->dv_destroy_flow
9199                                   (dt->policer_rules[i]));
9200                         dt->policer_rules[i] = NULL;
9201                 }
9202         }
9203         if (dt->jump_actn) {
9204                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9205                 dt->jump_actn = NULL;
9206         }
9207 }
9208
9209 /**
9210  * Destroy policer rules.
9211  *
9212  * @param[in] dev
9213  *   Pointer to Ethernet device.
9214  * @param[in] fm
9215  *   Pointer to flow meter structure.
9216  * @param[in] attr
9217  *   Pointer to flow attributes.
9218  *
9219  * @return
9220  *   Always 0.
9221  */
9222 static int
9223 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9224                               const struct mlx5_flow_meter *fm,
9225                               const struct rte_flow_attr *attr)
9226 {
9227         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9228
9229         if (!mtb)
9230                 return 0;
9231         if (attr->egress)
9232                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9233         if (attr->ingress)
9234                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9235         if (attr->transfer)
9236                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9237         return 0;
9238 }
9239
9240 /**
9241  * Create specify domain meter policer rule.
9242  *
9243  * @param[in] fm
9244  *   Pointer to flow meter structure.
9245  * @param[in] mtb
9246  *   Pointer to DV meter table set.
9247  * @param[in] mtr_reg_c
9248  *   Color match REG_C.
9249  *
9250  * @return
9251  *   0 on success, -1 otherwise.
9252  */
9253 static int
9254 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9255                                     struct mlx5_meter_domain_info *dtb,
9256                                     uint8_t mtr_reg_c)
9257 {
9258         struct mlx5_flow_dv_match_params matcher = {
9259                 .size = sizeof(matcher.buf),
9260         };
9261         struct mlx5_flow_dv_match_params value = {
9262                 .size = sizeof(value.buf),
9263         };
9264         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9265         void *actions[METER_ACTIONS];
9266         int i;
9267
9268         /* Create jump action. */
9269         if (!dtb->jump_actn)
9270                 dtb->jump_actn =
9271                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9272                                                         (dtb->sfx_tbl->obj);
9273         if (!dtb->jump_actn) {
9274                 DRV_LOG(ERR, "Failed to create policer jump action.");
9275                 goto error;
9276         }
9277         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9278                 int j = 0;
9279
9280                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9281                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9282                 if (mtb->count_actns[i])
9283                         actions[j++] = mtb->count_actns[i];
9284                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9285                         actions[j++] = mtb->drop_actn;
9286                 else
9287                         actions[j++] = dtb->jump_actn;
9288                 dtb->policer_rules[i] =
9289                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9290                                                  (void *)&value,
9291                                                   j, actions);
9292                 if (!dtb->policer_rules[i]) {
9293                         DRV_LOG(ERR, "Failed to create policer rule.");
9294                         goto error;
9295                 }
9296         }
9297         return 0;
9298 error:
9299         rte_errno = errno;
9300         return -1;
9301 }
9302
9303 /**
9304  * Create policer rules.
9305  *
9306  * @param[in] dev
9307  *   Pointer to Ethernet device.
9308  * @param[in] fm
9309  *   Pointer to flow meter structure.
9310  * @param[in] attr
9311  *   Pointer to flow attributes.
9312  *
9313  * @return
9314  *   0 on success, -1 otherwise.
9315  */
9316 static int
9317 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9318                              struct mlx5_flow_meter *fm,
9319                              const struct rte_flow_attr *attr)
9320 {
9321         struct mlx5_priv *priv = dev->data->dev_private;
9322         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9323         int ret;
9324
9325         if (attr->egress) {
9326                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9327                                                 priv->mtr_color_reg);
9328                 if (ret) {
9329                         DRV_LOG(ERR, "Failed to create egress policer.");
9330                         goto error;
9331                 }
9332         }
9333         if (attr->ingress) {
9334                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9335                                                 priv->mtr_color_reg);
9336                 if (ret) {
9337                         DRV_LOG(ERR, "Failed to create ingress policer.");
9338                         goto error;
9339                 }
9340         }
9341         if (attr->transfer) {
9342                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9343                                                 priv->mtr_color_reg);
9344                 if (ret) {
9345                         DRV_LOG(ERR, "Failed to create transfer policer.");
9346                         goto error;
9347                 }
9348         }
9349         return 0;
9350 error:
9351         flow_dv_destroy_policer_rules(dev, fm, attr);
9352         return -1;
9353 }
9354
9355 /**
9356  * Query a devx counter.
9357  *
9358  * @param[in] dev
9359  *   Pointer to the Ethernet device structure.
9360  * @param[in] cnt
9361  *   Index to the flow counter.
9362  * @param[in] clear
9363  *   Set to clear the counter statistics.
9364  * @param[out] pkts
9365  *   The statistics value of packets.
9366  * @param[out] bytes
9367  *   The statistics value of bytes.
9368  *
9369  * @return
9370  *   0 on success, otherwise return -1.
9371  */
9372 static int
9373 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9374                       uint64_t *pkts, uint64_t *bytes)
9375 {
9376         struct mlx5_priv *priv = dev->data->dev_private;
9377         struct mlx5_flow_counter *cnt;
9378         uint64_t inn_pkts, inn_bytes;
9379         int ret;
9380
9381         if (!priv->config.devx)
9382                 return -1;
9383
9384         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9385         if (ret)
9386                 return -1;
9387         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9388         *pkts = inn_pkts - cnt->hits;
9389         *bytes = inn_bytes - cnt->bytes;
9390         if (clear) {
9391                 cnt->hits = inn_pkts;
9392                 cnt->bytes = inn_bytes;
9393         }
9394         return 0;
9395 }
9396
9397 /**
9398  * Get aged-out flows.
9399  *
9400  * @param[in] dev
9401  *   Pointer to the Ethernet device structure.
9402  * @param[in] context
9403  *   The address of an array of pointers to the aged-out flows contexts.
9404  * @param[in] nb_contexts
9405  *   The length of context array pointers.
9406  * @param[out] error
9407  *   Perform verbose error reporting if not NULL. Initialized in case of
9408  *   error only.
9409  *
9410  * @return
9411  *   how many contexts get in success, otherwise negative errno value.
9412  *   if nb_contexts is 0, return the amount of all aged contexts.
9413  *   if nb_contexts is not 0 , return the amount of aged flows reported
9414  *   in the context array.
9415  * @note: only stub for now
9416  */
9417 static int
9418 flow_get_aged_flows(struct rte_eth_dev *dev,
9419                     void **context,
9420                     uint32_t nb_contexts,
9421                     struct rte_flow_error *error)
9422 {
9423         struct mlx5_priv *priv = dev->data->dev_private;
9424         struct mlx5_age_info *age_info;
9425         struct mlx5_age_param *age_param;
9426         struct mlx5_flow_counter *counter;
9427         int nb_flows = 0;
9428
9429         if (nb_contexts && !context)
9430                 return rte_flow_error_set(error, EINVAL,
9431                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9432                                           NULL,
9433                                           "Should assign at least one flow or"
9434                                           " context to get if nb_contexts != 0");
9435         age_info = GET_PORT_AGE_INFO(priv);
9436         rte_spinlock_lock(&age_info->aged_sl);
9437         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9438                 nb_flows++;
9439                 if (nb_contexts) {
9440                         age_param = MLX5_CNT_TO_AGE(counter);
9441                         context[nb_flows - 1] = age_param->context;
9442                         if (!(--nb_contexts))
9443                                 break;
9444                 }
9445         }
9446         rte_spinlock_unlock(&age_info->aged_sl);
9447         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9448         return nb_flows;
9449 }
9450
9451 /*
9452  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9453  */
9454 static int
9455 flow_dv_translate(struct rte_eth_dev *dev,
9456                   struct mlx5_flow *dev_flow,
9457                   const struct rte_flow_attr *attr,
9458                   const struct rte_flow_item items[],
9459                   const struct rte_flow_action actions[],
9460                   struct rte_flow_error *error)
9461 {
9462         int ret;
9463
9464         flow_dv_shared_lock(dev);
9465         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9466         flow_dv_shared_unlock(dev);
9467         return ret;
9468 }
9469
9470 /*
9471  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9472  */
9473 static int
9474 flow_dv_apply(struct rte_eth_dev *dev,
9475               struct rte_flow *flow,
9476               struct rte_flow_error *error)
9477 {
9478         int ret;
9479
9480         flow_dv_shared_lock(dev);
9481         ret = __flow_dv_apply(dev, flow, error);
9482         flow_dv_shared_unlock(dev);
9483         return ret;
9484 }
9485
9486 /*
9487  * Mutex-protected thunk to lock-free __flow_dv_remove().
9488  */
9489 static void
9490 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9491 {
9492         flow_dv_shared_lock(dev);
9493         __flow_dv_remove(dev, flow);
9494         flow_dv_shared_unlock(dev);
9495 }
9496
9497 /*
9498  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9499  */
9500 static void
9501 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9502 {
9503         flow_dv_shared_lock(dev);
9504         __flow_dv_destroy(dev, flow);
9505         flow_dv_shared_unlock(dev);
9506 }
9507
9508 /*
9509  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9510  */
9511 static uint32_t
9512 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9513 {
9514         uint32_t cnt;
9515
9516         flow_dv_shared_lock(dev);
9517         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9518         flow_dv_shared_unlock(dev);
9519         return cnt;
9520 }
9521
9522 /*
9523  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9524  */
9525 static void
9526 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9527 {
9528         flow_dv_shared_lock(dev);
9529         flow_dv_counter_release(dev, cnt);
9530         flow_dv_shared_unlock(dev);
9531 }
9532
9533 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9534         .validate = flow_dv_validate,
9535         .prepare = flow_dv_prepare,
9536         .translate = flow_dv_translate,
9537         .apply = flow_dv_apply,
9538         .remove = flow_dv_remove,
9539         .destroy = flow_dv_destroy,
9540         .query = flow_dv_query,
9541         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9542         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9543         .create_policer_rules = flow_dv_create_policer_rules,
9544         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9545         .counter_alloc = flow_dv_counter_allocate,
9546         .counter_free = flow_dv_counter_free,
9547         .counter_query = flow_dv_counter_query,
9548         .get_aged_flows = flow_get_aged_flows,
9549 };
9550
9551 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */