1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <rte_mtr_driver.h>
27 #include <mlx5_glue.h>
28 #include <mlx5_devx_cmds.h>
30 #include <mlx5_malloc.h>
32 #include "mlx5_defs.h"
34 #include "mlx5_common_os.h"
35 #include "mlx5_flow.h"
36 #include "mlx5_flow_os.h"
39 #include "rte_pmd_mlx5.h"
41 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
78 struct mlx5_flow_tbl_resource *tbl);
81 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
82 uint32_t encap_decap_idx);
85 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
88 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
91 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
95 * Initialize flow attributes structure according to flow items' types.
97 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
98 * mode. For tunnel mode, the items to be modified are the outermost ones.
101 * Pointer to item specification.
103 * Pointer to flow attributes structure.
104 * @param[in] dev_flow
105 * Pointer to the sub flow.
106 * @param[in] tunnel_decap
107 * Whether action is after tunnel decapsulation.
110 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
111 struct mlx5_flow *dev_flow, bool tunnel_decap)
113 uint64_t layers = dev_flow->handle->layers;
116 * If layers is already initialized, it means this dev_flow is the
117 * suffix flow, the layers flags is set by the prefix flow. Need to
118 * use the layer flags from prefix flow as the suffix flow may not
119 * have the user defined items as the flow is split.
122 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
124 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
126 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
128 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
133 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
134 uint8_t next_protocol = 0xff;
135 switch (item->type) {
136 case RTE_FLOW_ITEM_TYPE_GRE:
137 case RTE_FLOW_ITEM_TYPE_NVGRE:
138 case RTE_FLOW_ITEM_TYPE_VXLAN:
139 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
140 case RTE_FLOW_ITEM_TYPE_GENEVE:
141 case RTE_FLOW_ITEM_TYPE_MPLS:
145 case RTE_FLOW_ITEM_TYPE_IPV4:
148 if (item->mask != NULL &&
149 ((const struct rte_flow_item_ipv4 *)
150 item->mask)->hdr.next_proto_id)
152 ((const struct rte_flow_item_ipv4 *)
153 (item->spec))->hdr.next_proto_id &
154 ((const struct rte_flow_item_ipv4 *)
155 (item->mask))->hdr.next_proto_id;
156 if ((next_protocol == IPPROTO_IPIP ||
157 next_protocol == IPPROTO_IPV6) && tunnel_decap)
160 case RTE_FLOW_ITEM_TYPE_IPV6:
163 if (item->mask != NULL &&
164 ((const struct rte_flow_item_ipv6 *)
165 item->mask)->hdr.proto)
167 ((const struct rte_flow_item_ipv6 *)
168 (item->spec))->hdr.proto &
169 ((const struct rte_flow_item_ipv6 *)
170 (item->mask))->hdr.proto;
171 if ((next_protocol == IPPROTO_IPIP ||
172 next_protocol == IPPROTO_IPV6) && tunnel_decap)
175 case RTE_FLOW_ITEM_TYPE_UDP:
179 case RTE_FLOW_ITEM_TYPE_TCP:
191 * Convert rte_mtr_color to mlx5 color.
200 rte_col_2_mlx5_col(enum rte_color rcol)
203 case RTE_COLOR_GREEN:
204 return MLX5_FLOW_COLOR_GREEN;
205 case RTE_COLOR_YELLOW:
206 return MLX5_FLOW_COLOR_YELLOW;
208 return MLX5_FLOW_COLOR_RED;
212 return MLX5_FLOW_COLOR_UNDEFINED;
215 struct field_modify_info {
216 uint32_t size; /* Size of field in protocol header, in bytes. */
217 uint32_t offset; /* Offset of field in protocol header, in bytes. */
218 enum mlx5_modification_field id;
221 struct field_modify_info modify_eth[] = {
222 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
223 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
224 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
225 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
229 struct field_modify_info modify_vlan_out_first_vid[] = {
230 /* Size in bits !!! */
231 {12, 0, MLX5_MODI_OUT_FIRST_VID},
235 struct field_modify_info modify_ipv4[] = {
236 {1, 1, MLX5_MODI_OUT_IP_DSCP},
237 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
238 {4, 12, MLX5_MODI_OUT_SIPV4},
239 {4, 16, MLX5_MODI_OUT_DIPV4},
243 struct field_modify_info modify_ipv6[] = {
244 {1, 0, MLX5_MODI_OUT_IP_DSCP},
245 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
246 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
247 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
248 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
249 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
250 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
251 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
252 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
253 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
257 struct field_modify_info modify_udp[] = {
258 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
259 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
263 struct field_modify_info modify_tcp[] = {
264 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
265 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
266 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
267 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
271 static const struct rte_flow_item *
272 mlx5_flow_find_tunnel_item(const struct rte_flow_item *item)
274 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
275 switch (item->type) {
278 case RTE_FLOW_ITEM_TYPE_VXLAN:
279 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
280 case RTE_FLOW_ITEM_TYPE_GRE:
281 case RTE_FLOW_ITEM_TYPE_MPLS:
282 case RTE_FLOW_ITEM_TYPE_NVGRE:
283 case RTE_FLOW_ITEM_TYPE_GENEVE:
285 case RTE_FLOW_ITEM_TYPE_IPV4:
286 case RTE_FLOW_ITEM_TYPE_IPV6:
287 if (item[1].type == RTE_FLOW_ITEM_TYPE_IPV4 ||
288 item[1].type == RTE_FLOW_ITEM_TYPE_IPV6)
297 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
298 uint8_t next_protocol, uint64_t *item_flags,
301 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
302 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
303 if (next_protocol == IPPROTO_IPIP) {
304 *item_flags |= MLX5_FLOW_LAYER_IPIP;
307 if (next_protocol == IPPROTO_IPV6) {
308 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
313 /* Update VLAN's VID/PCP based on input rte_flow_action.
316 * Pointer to struct rte_flow_action.
318 * Pointer to struct rte_vlan_hdr.
321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
322 struct rte_vlan_hdr *vlan)
325 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
327 ((const struct rte_flow_action_of_set_vlan_pcp *)
328 action->conf)->vlan_pcp;
329 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
330 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
331 vlan->vlan_tci |= vlan_tci;
332 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
333 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
334 vlan->vlan_tci |= rte_be_to_cpu_16
335 (((const struct rte_flow_action_of_set_vlan_vid *)
336 action->conf)->vlan_vid);
341 * Fetch 1, 2, 3 or 4 byte field from the byte array
342 * and return as unsigned integer in host-endian format.
345 * Pointer to data array.
347 * Size of field to extract.
350 * converted field in host endian format.
352 static inline uint32_t
353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
362 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = (ret << 8) | *(data + sizeof(uint16_t));
369 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
380 * Convert modify-header action to DV specification.
382 * Data length of each action is determined by provided field description
383 * and the item mask. Data bit offset and width of each action is determined
384 * by provided item mask.
387 * Pointer to item specification.
389 * Pointer to field modification information.
390 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
394 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
395 * Negative offset value sets the same offset as source offset.
396 * size field is ignored, value is taken from source field.
397 * @param[in,out] resource
398 * Pointer to the modify-header resource.
400 * Type of modification.
402 * Pointer to the error structure.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 flow_dv_convert_modify_action(struct rte_flow_item *item,
409 struct field_modify_info *field,
410 struct field_modify_info *dcopy,
411 struct mlx5_flow_dv_modify_hdr_resource *resource,
412 uint32_t type, struct rte_flow_error *error)
414 uint32_t i = resource->actions_num;
415 struct mlx5_modification_cmd *actions = resource->actions;
418 * The item and mask are provided in big-endian format.
419 * The fields should be presented as in big-endian format either.
420 * Mask must be always present, it defines the actual field width.
422 MLX5_ASSERT(item->mask);
423 MLX5_ASSERT(field->size);
430 if (i >= MLX5_MAX_MODIFY_NUM)
431 return rte_flow_error_set(error, EINVAL,
432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
433 "too many items to modify");
434 /* Fetch variable byte size mask from the array. */
435 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
436 field->offset, field->size);
441 /* Deduce actual data width in bits from mask value. */
442 off_b = rte_bsf32(mask);
443 size_b = sizeof(uint32_t) * CHAR_BIT -
444 off_b - __builtin_clz(mask);
446 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
447 actions[i] = (struct mlx5_modification_cmd) {
453 /* Convert entire record to expected big-endian format. */
454 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
455 if (type == MLX5_MODIFICATION_TYPE_COPY) {
457 actions[i].dst_field = dcopy->id;
458 actions[i].dst_offset =
459 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
460 /* Convert entire record to big-endian format. */
461 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
464 MLX5_ASSERT(item->spec);
465 data = flow_dv_fetch_field((const uint8_t *)item->spec +
466 field->offset, field->size);
467 /* Shift out the trailing masked bits from data. */
468 data = (data & mask) >> off_b;
469 actions[i].data1 = rte_cpu_to_be_32(data);
473 } while (field->size);
474 if (resource->actions_num == i)
475 return rte_flow_error_set(error, EINVAL,
476 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
477 "invalid modification flow item");
478 resource->actions_num = i;
483 * Convert modify-header set IPv4 address action to DV specification.
485 * @param[in,out] resource
486 * Pointer to the modify-header resource.
488 * Pointer to action specification.
490 * Pointer to the error structure.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 flow_dv_convert_action_modify_ipv4
497 (struct mlx5_flow_dv_modify_hdr_resource *resource,
498 const struct rte_flow_action *action,
499 struct rte_flow_error *error)
501 const struct rte_flow_action_set_ipv4 *conf =
502 (const struct rte_flow_action_set_ipv4 *)(action->conf);
503 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
504 struct rte_flow_item_ipv4 ipv4;
505 struct rte_flow_item_ipv4 ipv4_mask;
507 memset(&ipv4, 0, sizeof(ipv4));
508 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
509 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
510 ipv4.hdr.src_addr = conf->ipv4_addr;
511 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
513 ipv4.hdr.dst_addr = conf->ipv4_addr;
514 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
517 item.mask = &ipv4_mask;
518 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
519 MLX5_MODIFICATION_TYPE_SET, error);
523 * Convert modify-header set IPv6 address action to DV specification.
525 * @param[in,out] resource
526 * Pointer to the modify-header resource.
528 * Pointer to action specification.
530 * Pointer to the error structure.
533 * 0 on success, a negative errno value otherwise and rte_errno is set.
536 flow_dv_convert_action_modify_ipv6
537 (struct mlx5_flow_dv_modify_hdr_resource *resource,
538 const struct rte_flow_action *action,
539 struct rte_flow_error *error)
541 const struct rte_flow_action_set_ipv6 *conf =
542 (const struct rte_flow_action_set_ipv6 *)(action->conf);
543 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
544 struct rte_flow_item_ipv6 ipv6;
545 struct rte_flow_item_ipv6 ipv6_mask;
547 memset(&ipv6, 0, sizeof(ipv6));
548 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
549 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
550 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
551 sizeof(ipv6.hdr.src_addr));
552 memcpy(&ipv6_mask.hdr.src_addr,
553 &rte_flow_item_ipv6_mask.hdr.src_addr,
554 sizeof(ipv6.hdr.src_addr));
556 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
557 sizeof(ipv6.hdr.dst_addr));
558 memcpy(&ipv6_mask.hdr.dst_addr,
559 &rte_flow_item_ipv6_mask.hdr.dst_addr,
560 sizeof(ipv6.hdr.dst_addr));
563 item.mask = &ipv6_mask;
564 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
565 MLX5_MODIFICATION_TYPE_SET, error);
569 * Convert modify-header set MAC address action to DV specification.
571 * @param[in,out] resource
572 * Pointer to the modify-header resource.
574 * Pointer to action specification.
576 * Pointer to the error structure.
579 * 0 on success, a negative errno value otherwise and rte_errno is set.
582 flow_dv_convert_action_modify_mac
583 (struct mlx5_flow_dv_modify_hdr_resource *resource,
584 const struct rte_flow_action *action,
585 struct rte_flow_error *error)
587 const struct rte_flow_action_set_mac *conf =
588 (const struct rte_flow_action_set_mac *)(action->conf);
589 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
590 struct rte_flow_item_eth eth;
591 struct rte_flow_item_eth eth_mask;
593 memset(ð, 0, sizeof(eth));
594 memset(ð_mask, 0, sizeof(eth_mask));
595 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
596 memcpy(ð.src.addr_bytes, &conf->mac_addr,
597 sizeof(eth.src.addr_bytes));
598 memcpy(ð_mask.src.addr_bytes,
599 &rte_flow_item_eth_mask.src.addr_bytes,
600 sizeof(eth_mask.src.addr_bytes));
602 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
603 sizeof(eth.dst.addr_bytes));
604 memcpy(ð_mask.dst.addr_bytes,
605 &rte_flow_item_eth_mask.dst.addr_bytes,
606 sizeof(eth_mask.dst.addr_bytes));
609 item.mask = ð_mask;
610 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
611 MLX5_MODIFICATION_TYPE_SET, error);
615 * Convert modify-header set VLAN VID action to DV specification.
617 * @param[in,out] resource
618 * Pointer to the modify-header resource.
620 * Pointer to action specification.
622 * Pointer to the error structure.
625 * 0 on success, a negative errno value otherwise and rte_errno is set.
628 flow_dv_convert_action_modify_vlan_vid
629 (struct mlx5_flow_dv_modify_hdr_resource *resource,
630 const struct rte_flow_action *action,
631 struct rte_flow_error *error)
633 const struct rte_flow_action_of_set_vlan_vid *conf =
634 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
635 int i = resource->actions_num;
636 struct mlx5_modification_cmd *actions = resource->actions;
637 struct field_modify_info *field = modify_vlan_out_first_vid;
639 if (i >= MLX5_MAX_MODIFY_NUM)
640 return rte_flow_error_set(error, EINVAL,
641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
642 "too many items to modify");
643 actions[i] = (struct mlx5_modification_cmd) {
644 .action_type = MLX5_MODIFICATION_TYPE_SET,
646 .length = field->size,
647 .offset = field->offset,
649 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
650 actions[i].data1 = conf->vlan_vid;
651 actions[i].data1 = actions[i].data1 << 16;
652 resource->actions_num = ++i;
657 * Convert modify-header set TP action to DV specification.
659 * @param[in,out] resource
660 * Pointer to the modify-header resource.
662 * Pointer to action specification.
664 * Pointer to rte_flow_item objects list.
666 * Pointer to flow attributes structure.
667 * @param[in] dev_flow
668 * Pointer to the sub flow.
669 * @param[in] tunnel_decap
670 * Whether action is after tunnel decapsulation.
672 * Pointer to the error structure.
675 * 0 on success, a negative errno value otherwise and rte_errno is set.
678 flow_dv_convert_action_modify_tp
679 (struct mlx5_flow_dv_modify_hdr_resource *resource,
680 const struct rte_flow_action *action,
681 const struct rte_flow_item *items,
682 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
683 bool tunnel_decap, struct rte_flow_error *error)
685 const struct rte_flow_action_set_tp *conf =
686 (const struct rte_flow_action_set_tp *)(action->conf);
687 struct rte_flow_item item;
688 struct rte_flow_item_udp udp;
689 struct rte_flow_item_udp udp_mask;
690 struct rte_flow_item_tcp tcp;
691 struct rte_flow_item_tcp tcp_mask;
692 struct field_modify_info *field;
695 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
697 memset(&udp, 0, sizeof(udp));
698 memset(&udp_mask, 0, sizeof(udp_mask));
699 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
700 udp.hdr.src_port = conf->port;
701 udp_mask.hdr.src_port =
702 rte_flow_item_udp_mask.hdr.src_port;
704 udp.hdr.dst_port = conf->port;
705 udp_mask.hdr.dst_port =
706 rte_flow_item_udp_mask.hdr.dst_port;
708 item.type = RTE_FLOW_ITEM_TYPE_UDP;
710 item.mask = &udp_mask;
713 MLX5_ASSERT(attr->tcp);
714 memset(&tcp, 0, sizeof(tcp));
715 memset(&tcp_mask, 0, sizeof(tcp_mask));
716 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
717 tcp.hdr.src_port = conf->port;
718 tcp_mask.hdr.src_port =
719 rte_flow_item_tcp_mask.hdr.src_port;
721 tcp.hdr.dst_port = conf->port;
722 tcp_mask.hdr.dst_port =
723 rte_flow_item_tcp_mask.hdr.dst_port;
725 item.type = RTE_FLOW_ITEM_TYPE_TCP;
727 item.mask = &tcp_mask;
730 return flow_dv_convert_modify_action(&item, field, NULL, resource,
731 MLX5_MODIFICATION_TYPE_SET, error);
735 * Convert modify-header set TTL action to DV specification.
737 * @param[in,out] resource
738 * Pointer to the modify-header resource.
740 * Pointer to action specification.
742 * Pointer to rte_flow_item objects list.
744 * Pointer to flow attributes structure.
745 * @param[in] dev_flow
746 * Pointer to the sub flow.
747 * @param[in] tunnel_decap
748 * Whether action is after tunnel decapsulation.
750 * Pointer to the error structure.
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
756 flow_dv_convert_action_modify_ttl
757 (struct mlx5_flow_dv_modify_hdr_resource *resource,
758 const struct rte_flow_action *action,
759 const struct rte_flow_item *items,
760 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
761 bool tunnel_decap, struct rte_flow_error *error)
763 const struct rte_flow_action_set_ttl *conf =
764 (const struct rte_flow_action_set_ttl *)(action->conf);
765 struct rte_flow_item item;
766 struct rte_flow_item_ipv4 ipv4;
767 struct rte_flow_item_ipv4 ipv4_mask;
768 struct rte_flow_item_ipv6 ipv6;
769 struct rte_flow_item_ipv6 ipv6_mask;
770 struct field_modify_info *field;
773 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
775 memset(&ipv4, 0, sizeof(ipv4));
776 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
777 ipv4.hdr.time_to_live = conf->ttl_value;
778 ipv4_mask.hdr.time_to_live = 0xFF;
779 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
781 item.mask = &ipv4_mask;
784 MLX5_ASSERT(attr->ipv6);
785 memset(&ipv6, 0, sizeof(ipv6));
786 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
787 ipv6.hdr.hop_limits = conf->ttl_value;
788 ipv6_mask.hdr.hop_limits = 0xFF;
789 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
791 item.mask = &ipv6_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header decrement TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_dec_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_item *items,
823 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
824 bool tunnel_decap, struct rte_flow_error *error)
826 struct rte_flow_item item;
827 struct rte_flow_item_ipv4 ipv4;
828 struct rte_flow_item_ipv4 ipv4_mask;
829 struct rte_flow_item_ipv6 ipv6;
830 struct rte_flow_item_ipv6 ipv6_mask;
831 struct field_modify_info *field;
834 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
836 memset(&ipv4, 0, sizeof(ipv4));
837 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
838 ipv4.hdr.time_to_live = 0xFF;
839 ipv4_mask.hdr.time_to_live = 0xFF;
840 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
842 item.mask = &ipv4_mask;
845 MLX5_ASSERT(attr->ipv6);
846 memset(&ipv6, 0, sizeof(ipv6));
847 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
848 ipv6.hdr.hop_limits = 0xFF;
849 ipv6_mask.hdr.hop_limits = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
852 item.mask = &ipv6_mask;
855 return flow_dv_convert_modify_action(&item, field, NULL, resource,
856 MLX5_MODIFICATION_TYPE_ADD, error);
860 * Convert modify-header increment/decrement TCP Sequence number
861 * to DV specification.
863 * @param[in,out] resource
864 * Pointer to the modify-header resource.
866 * Pointer to action specification.
868 * Pointer to the error structure.
871 * 0 on success, a negative errno value otherwise and rte_errno is set.
874 flow_dv_convert_action_modify_tcp_seq
875 (struct mlx5_flow_dv_modify_hdr_resource *resource,
876 const struct rte_flow_action *action,
877 struct rte_flow_error *error)
879 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
880 uint64_t value = rte_be_to_cpu_32(*conf);
881 struct rte_flow_item item;
882 struct rte_flow_item_tcp tcp;
883 struct rte_flow_item_tcp tcp_mask;
885 memset(&tcp, 0, sizeof(tcp));
886 memset(&tcp_mask, 0, sizeof(tcp_mask));
887 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
889 * The HW has no decrement operation, only increment operation.
890 * To simulate decrement X from Y using increment operation
891 * we need to add UINT32_MAX X times to Y.
892 * Each adding of UINT32_MAX decrements Y by 1.
895 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
896 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
897 item.type = RTE_FLOW_ITEM_TYPE_TCP;
899 item.mask = &tcp_mask;
900 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
901 MLX5_MODIFICATION_TYPE_ADD, error);
905 * Convert modify-header increment/decrement TCP Acknowledgment number
906 * to DV specification.
908 * @param[in,out] resource
909 * Pointer to the modify-header resource.
911 * Pointer to action specification.
913 * Pointer to the error structure.
916 * 0 on success, a negative errno value otherwise and rte_errno is set.
919 flow_dv_convert_action_modify_tcp_ack
920 (struct mlx5_flow_dv_modify_hdr_resource *resource,
921 const struct rte_flow_action *action,
922 struct rte_flow_error *error)
924 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
925 uint64_t value = rte_be_to_cpu_32(*conf);
926 struct rte_flow_item item;
927 struct rte_flow_item_tcp tcp;
928 struct rte_flow_item_tcp tcp_mask;
930 memset(&tcp, 0, sizeof(tcp));
931 memset(&tcp_mask, 0, sizeof(tcp_mask));
932 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
934 * The HW has no decrement operation, only increment operation.
935 * To simulate decrement X from Y using increment operation
936 * we need to add UINT32_MAX X times to Y.
937 * Each adding of UINT32_MAX decrements Y by 1.
940 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
941 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
942 item.type = RTE_FLOW_ITEM_TYPE_TCP;
944 item.mask = &tcp_mask;
945 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
946 MLX5_MODIFICATION_TYPE_ADD, error);
949 static enum mlx5_modification_field reg_to_field[] = {
950 [REG_NON] = MLX5_MODI_OUT_NONE,
951 [REG_A] = MLX5_MODI_META_DATA_REG_A,
952 [REG_B] = MLX5_MODI_META_DATA_REG_B,
953 [REG_C_0] = MLX5_MODI_META_REG_C_0,
954 [REG_C_1] = MLX5_MODI_META_REG_C_1,
955 [REG_C_2] = MLX5_MODI_META_REG_C_2,
956 [REG_C_3] = MLX5_MODI_META_REG_C_3,
957 [REG_C_4] = MLX5_MODI_META_REG_C_4,
958 [REG_C_5] = MLX5_MODI_META_REG_C_5,
959 [REG_C_6] = MLX5_MODI_META_REG_C_6,
960 [REG_C_7] = MLX5_MODI_META_REG_C_7,
964 * Convert register set to DV specification.
966 * @param[in,out] resource
967 * Pointer to the modify-header resource.
969 * Pointer to action specification.
971 * Pointer to the error structure.
974 * 0 on success, a negative errno value otherwise and rte_errno is set.
977 flow_dv_convert_action_set_reg
978 (struct mlx5_flow_dv_modify_hdr_resource *resource,
979 const struct rte_flow_action *action,
980 struct rte_flow_error *error)
982 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
983 struct mlx5_modification_cmd *actions = resource->actions;
984 uint32_t i = resource->actions_num;
986 if (i >= MLX5_MAX_MODIFY_NUM)
987 return rte_flow_error_set(error, EINVAL,
988 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
989 "too many items to modify");
990 MLX5_ASSERT(conf->id != REG_NON);
991 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
992 actions[i] = (struct mlx5_modification_cmd) {
993 .action_type = MLX5_MODIFICATION_TYPE_SET,
994 .field = reg_to_field[conf->id],
995 .offset = conf->offset,
996 .length = conf->length,
998 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
999 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1001 resource->actions_num = i;
1006 * Convert SET_TAG action to DV specification.
1009 * Pointer to the rte_eth_dev structure.
1010 * @param[in,out] resource
1011 * Pointer to the modify-header resource.
1013 * Pointer to action specification.
1015 * Pointer to the error structure.
1018 * 0 on success, a negative errno value otherwise and rte_errno is set.
1021 flow_dv_convert_action_set_tag
1022 (struct rte_eth_dev *dev,
1023 struct mlx5_flow_dv_modify_hdr_resource *resource,
1024 const struct rte_flow_action_set_tag *conf,
1025 struct rte_flow_error *error)
1027 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1028 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1029 struct rte_flow_item item = {
1033 struct field_modify_info reg_c_x[] = {
1036 enum mlx5_modification_field reg_type;
1039 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1042 MLX5_ASSERT(ret != REG_NON);
1043 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1044 reg_type = reg_to_field[ret];
1045 MLX5_ASSERT(reg_type > 0);
1046 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1047 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1048 MLX5_MODIFICATION_TYPE_SET, error);
1052 * Convert internal COPY_REG action to DV specification.
1055 * Pointer to the rte_eth_dev structure.
1056 * @param[in,out] res
1057 * Pointer to the modify-header resource.
1059 * Pointer to action specification.
1061 * Pointer to the error structure.
1064 * 0 on success, a negative errno value otherwise and rte_errno is set.
1067 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1068 struct mlx5_flow_dv_modify_hdr_resource *res,
1069 const struct rte_flow_action *action,
1070 struct rte_flow_error *error)
1072 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1073 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1074 struct rte_flow_item item = {
1078 struct field_modify_info reg_src[] = {
1079 {4, 0, reg_to_field[conf->src]},
1082 struct field_modify_info reg_dst = {
1084 .id = reg_to_field[conf->dst],
1086 /* Adjust reg_c[0] usage according to reported mask. */
1087 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1088 struct mlx5_priv *priv = dev->data->dev_private;
1089 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1091 MLX5_ASSERT(reg_c0);
1092 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1093 if (conf->dst == REG_C_0) {
1094 /* Copy to reg_c[0], within mask only. */
1095 reg_dst.offset = rte_bsf32(reg_c0);
1097 * Mask is ignoring the enianness, because
1098 * there is no conversion in datapath.
1100 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1101 /* Copy from destination lower bits to reg_c[0]. */
1102 mask = reg_c0 >> reg_dst.offset;
1104 /* Copy from destination upper bits to reg_c[0]. */
1105 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1106 rte_fls_u32(reg_c0));
1109 mask = rte_cpu_to_be_32(reg_c0);
1110 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1111 /* Copy from reg_c[0] to destination lower bits. */
1114 /* Copy from reg_c[0] to destination upper bits. */
1115 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1116 (rte_fls_u32(reg_c0) -
1121 return flow_dv_convert_modify_action(&item,
1122 reg_src, ®_dst, res,
1123 MLX5_MODIFICATION_TYPE_COPY,
1128 * Convert MARK action to DV specification. This routine is used
1129 * in extensive metadata only and requires metadata register to be
1130 * handled. In legacy mode hardware tag resource is engaged.
1133 * Pointer to the rte_eth_dev structure.
1135 * Pointer to MARK action specification.
1136 * @param[in,out] resource
1137 * Pointer to the modify-header resource.
1139 * Pointer to the error structure.
1142 * 0 on success, a negative errno value otherwise and rte_errno is set.
1145 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1146 const struct rte_flow_action_mark *conf,
1147 struct mlx5_flow_dv_modify_hdr_resource *resource,
1148 struct rte_flow_error *error)
1150 struct mlx5_priv *priv = dev->data->dev_private;
1151 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1152 priv->sh->dv_mark_mask);
1153 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1154 struct rte_flow_item item = {
1158 struct field_modify_info reg_c_x[] = {
1164 return rte_flow_error_set(error, EINVAL,
1165 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1166 NULL, "zero mark action mask");
1167 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1170 MLX5_ASSERT(reg > 0);
1171 if (reg == REG_C_0) {
1172 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1173 uint32_t shl_c0 = rte_bsf32(msk_c0);
1175 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1176 mask = rte_cpu_to_be_32(mask) & msk_c0;
1177 mask = rte_cpu_to_be_32(mask << shl_c0);
1179 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1180 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1181 MLX5_MODIFICATION_TYPE_SET, error);
1185 * Get metadata register index for specified steering domain.
1188 * Pointer to the rte_eth_dev structure.
1190 * Attributes of flow to determine steering domain.
1192 * Pointer to the error structure.
1195 * positive index on success, a negative errno value otherwise
1196 * and rte_errno is set.
1198 static enum modify_reg
1199 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1200 const struct rte_flow_attr *attr,
1201 struct rte_flow_error *error)
1204 mlx5_flow_get_reg_id(dev, attr->transfer ?
1208 MLX5_METADATA_RX, 0, error);
1210 return rte_flow_error_set(error,
1211 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1212 NULL, "unavailable "
1213 "metadata register");
1218 * Convert SET_META action to DV specification.
1221 * Pointer to the rte_eth_dev structure.
1222 * @param[in,out] resource
1223 * Pointer to the modify-header resource.
1225 * Attributes of flow that includes this item.
1227 * Pointer to action specification.
1229 * Pointer to the error structure.
1232 * 0 on success, a negative errno value otherwise and rte_errno is set.
1235 flow_dv_convert_action_set_meta
1236 (struct rte_eth_dev *dev,
1237 struct mlx5_flow_dv_modify_hdr_resource *resource,
1238 const struct rte_flow_attr *attr,
1239 const struct rte_flow_action_set_meta *conf,
1240 struct rte_flow_error *error)
1242 uint32_t data = conf->data;
1243 uint32_t mask = conf->mask;
1244 struct rte_flow_item item = {
1248 struct field_modify_info reg_c_x[] = {
1251 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1255 MLX5_ASSERT(reg != REG_NON);
1257 * In datapath code there is no endianness
1258 * coversions for perfromance reasons, all
1259 * pattern conversions are done in rte_flow.
1261 if (reg == REG_C_0) {
1262 struct mlx5_priv *priv = dev->data->dev_private;
1263 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1266 MLX5_ASSERT(msk_c0);
1267 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1268 shl_c0 = rte_bsf32(msk_c0);
1270 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1274 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1276 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1277 /* The routine expects parameters in memory as big-endian ones. */
1278 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1279 MLX5_MODIFICATION_TYPE_SET, error);
1283 * Convert modify-header set IPv4 DSCP action to DV specification.
1285 * @param[in,out] resource
1286 * Pointer to the modify-header resource.
1288 * Pointer to action specification.
1290 * Pointer to the error structure.
1293 * 0 on success, a negative errno value otherwise and rte_errno is set.
1296 flow_dv_convert_action_modify_ipv4_dscp
1297 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298 const struct rte_flow_action *action,
1299 struct rte_flow_error *error)
1301 const struct rte_flow_action_set_dscp *conf =
1302 (const struct rte_flow_action_set_dscp *)(action->conf);
1303 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1304 struct rte_flow_item_ipv4 ipv4;
1305 struct rte_flow_item_ipv4 ipv4_mask;
1307 memset(&ipv4, 0, sizeof(ipv4));
1308 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1309 ipv4.hdr.type_of_service = conf->dscp;
1310 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1312 item.mask = &ipv4_mask;
1313 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1314 MLX5_MODIFICATION_TYPE_SET, error);
1318 * Convert modify-header set IPv6 DSCP action to DV specification.
1320 * @param[in,out] resource
1321 * Pointer to the modify-header resource.
1323 * Pointer to action specification.
1325 * Pointer to the error structure.
1328 * 0 on success, a negative errno value otherwise and rte_errno is set.
1331 flow_dv_convert_action_modify_ipv6_dscp
1332 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333 const struct rte_flow_action *action,
1334 struct rte_flow_error *error)
1336 const struct rte_flow_action_set_dscp *conf =
1337 (const struct rte_flow_action_set_dscp *)(action->conf);
1338 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1339 struct rte_flow_item_ipv6 ipv6;
1340 struct rte_flow_item_ipv6 ipv6_mask;
1342 memset(&ipv6, 0, sizeof(ipv6));
1343 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1345 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1346 * rdma-core only accept the DSCP bits byte aligned start from
1347 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1348 * bits in IPv6 case as rdma-core requires byte aligned value.
1350 ipv6.hdr.vtc_flow = conf->dscp;
1351 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1353 item.mask = &ipv6_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1362 case RTE_FLOW_FIELD_START:
1364 case RTE_FLOW_FIELD_MAC_DST:
1365 case RTE_FLOW_FIELD_MAC_SRC:
1367 case RTE_FLOW_FIELD_VLAN_TYPE:
1369 case RTE_FLOW_FIELD_VLAN_ID:
1371 case RTE_FLOW_FIELD_MAC_TYPE:
1373 case RTE_FLOW_FIELD_IPV4_DSCP:
1375 case RTE_FLOW_FIELD_IPV4_TTL:
1377 case RTE_FLOW_FIELD_IPV4_SRC:
1378 case RTE_FLOW_FIELD_IPV4_DST:
1380 case RTE_FLOW_FIELD_IPV6_DSCP:
1382 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1384 case RTE_FLOW_FIELD_IPV6_SRC:
1385 case RTE_FLOW_FIELD_IPV6_DST:
1387 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1388 case RTE_FLOW_FIELD_TCP_PORT_DST:
1390 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1391 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1393 case RTE_FLOW_FIELD_TCP_FLAGS:
1395 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1396 case RTE_FLOW_FIELD_UDP_PORT_DST:
1398 case RTE_FLOW_FIELD_VXLAN_VNI:
1399 case RTE_FLOW_FIELD_GENEVE_VNI:
1401 case RTE_FLOW_FIELD_GTP_TEID:
1402 case RTE_FLOW_FIELD_TAG:
1404 case RTE_FLOW_FIELD_MARK:
1406 case RTE_FLOW_FIELD_META:
1408 case RTE_FLOW_FIELD_POINTER:
1409 case RTE_FLOW_FIELD_VALUE:
1418 mlx5_flow_field_id_to_modify_info
1419 (const struct rte_flow_action_modify_data *data,
1420 struct field_modify_info *info,
1421 uint32_t *mask, uint32_t *value,
1422 uint32_t width, uint32_t dst_width,
1423 struct rte_eth_dev *dev,
1424 const struct rte_flow_attr *attr,
1425 struct rte_flow_error *error)
1429 switch (data->field) {
1430 case RTE_FLOW_FIELD_START:
1431 /* not supported yet */
1434 case RTE_FLOW_FIELD_MAC_DST:
1436 if (data->offset < 32) {
1437 info[idx] = (struct field_modify_info){4, 0,
1438 MLX5_MODI_OUT_DMAC_47_16};
1441 rte_cpu_to_be_32(0xffffffff >>
1445 mask[idx] = RTE_BE32(0xffffffff);
1452 info[idx] = (struct field_modify_info){2, 4 * idx,
1453 MLX5_MODI_OUT_DMAC_15_0};
1454 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1456 if (data->offset < 32)
1457 info[idx++] = (struct field_modify_info){4, 0,
1458 MLX5_MODI_OUT_DMAC_47_16};
1459 info[idx] = (struct field_modify_info){2, 0,
1460 MLX5_MODI_OUT_DMAC_15_0};
1463 case RTE_FLOW_FIELD_MAC_SRC:
1465 if (data->offset < 32) {
1466 info[idx] = (struct field_modify_info){4, 0,
1467 MLX5_MODI_OUT_SMAC_47_16};
1470 rte_cpu_to_be_32(0xffffffff >>
1474 mask[idx] = RTE_BE32(0xffffffff);
1481 info[idx] = (struct field_modify_info){2, 4 * idx,
1482 MLX5_MODI_OUT_SMAC_15_0};
1483 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1485 if (data->offset < 32)
1486 info[idx++] = (struct field_modify_info){4, 0,
1487 MLX5_MODI_OUT_SMAC_47_16};
1488 info[idx] = (struct field_modify_info){2, 0,
1489 MLX5_MODI_OUT_SMAC_15_0};
1492 case RTE_FLOW_FIELD_VLAN_TYPE:
1493 /* not supported yet */
1495 case RTE_FLOW_FIELD_VLAN_ID:
1496 info[idx] = (struct field_modify_info){2, 0,
1497 MLX5_MODI_OUT_FIRST_VID};
1499 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1501 case RTE_FLOW_FIELD_MAC_TYPE:
1502 info[idx] = (struct field_modify_info){2, 0,
1503 MLX5_MODI_OUT_ETHERTYPE};
1505 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1507 case RTE_FLOW_FIELD_IPV4_DSCP:
1508 info[idx] = (struct field_modify_info){1, 0,
1509 MLX5_MODI_OUT_IP_DSCP};
1511 mask[idx] = 0x3f >> (6 - width);
1513 case RTE_FLOW_FIELD_IPV4_TTL:
1514 info[idx] = (struct field_modify_info){1, 0,
1515 MLX5_MODI_OUT_IPV4_TTL};
1517 mask[idx] = 0xff >> (8 - width);
1519 case RTE_FLOW_FIELD_IPV4_SRC:
1520 info[idx] = (struct field_modify_info){4, 0,
1521 MLX5_MODI_OUT_SIPV4};
1523 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1526 case RTE_FLOW_FIELD_IPV4_DST:
1527 info[idx] = (struct field_modify_info){4, 0,
1528 MLX5_MODI_OUT_DIPV4};
1530 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1533 case RTE_FLOW_FIELD_IPV6_DSCP:
1534 info[idx] = (struct field_modify_info){1, 0,
1535 MLX5_MODI_OUT_IP_DSCP};
1537 mask[idx] = 0x3f >> (6 - width);
1539 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1540 info[idx] = (struct field_modify_info){1, 0,
1541 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1543 mask[idx] = 0xff >> (8 - width);
1545 case RTE_FLOW_FIELD_IPV6_SRC:
1547 if (data->offset < 32) {
1548 info[idx] = (struct field_modify_info){4,
1550 MLX5_MODI_OUT_SIPV6_31_0};
1553 rte_cpu_to_be_32(0xffffffff >>
1557 mask[idx] = RTE_BE32(0xffffffff);
1564 if (data->offset < 64) {
1565 info[idx] = (struct field_modify_info){4,
1567 MLX5_MODI_OUT_SIPV6_63_32};
1570 rte_cpu_to_be_32(0xffffffff >>
1574 mask[idx] = RTE_BE32(0xffffffff);
1581 if (data->offset < 96) {
1582 info[idx] = (struct field_modify_info){4,
1584 MLX5_MODI_OUT_SIPV6_95_64};
1587 rte_cpu_to_be_32(0xffffffff >>
1591 mask[idx] = RTE_BE32(0xffffffff);
1598 info[idx] = (struct field_modify_info){4, 4 * idx,
1599 MLX5_MODI_OUT_SIPV6_127_96};
1600 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1603 if (data->offset < 32)
1604 info[idx++] = (struct field_modify_info){4, 0,
1605 MLX5_MODI_OUT_SIPV6_31_0};
1606 if (data->offset < 64)
1607 info[idx++] = (struct field_modify_info){4, 0,
1608 MLX5_MODI_OUT_SIPV6_63_32};
1609 if (data->offset < 96)
1610 info[idx++] = (struct field_modify_info){4, 0,
1611 MLX5_MODI_OUT_SIPV6_95_64};
1612 if (data->offset < 128)
1613 info[idx++] = (struct field_modify_info){4, 0,
1614 MLX5_MODI_OUT_SIPV6_127_96};
1617 case RTE_FLOW_FIELD_IPV6_DST:
1619 if (data->offset < 32) {
1620 info[idx] = (struct field_modify_info){4,
1622 MLX5_MODI_OUT_DIPV6_31_0};
1625 rte_cpu_to_be_32(0xffffffff >>
1629 mask[idx] = RTE_BE32(0xffffffff);
1636 if (data->offset < 64) {
1637 info[idx] = (struct field_modify_info){4,
1639 MLX5_MODI_OUT_DIPV6_63_32};
1642 rte_cpu_to_be_32(0xffffffff >>
1646 mask[idx] = RTE_BE32(0xffffffff);
1653 if (data->offset < 96) {
1654 info[idx] = (struct field_modify_info){4,
1656 MLX5_MODI_OUT_DIPV6_95_64};
1659 rte_cpu_to_be_32(0xffffffff >>
1663 mask[idx] = RTE_BE32(0xffffffff);
1670 info[idx] = (struct field_modify_info){4, 4 * idx,
1671 MLX5_MODI_OUT_DIPV6_127_96};
1672 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1675 if (data->offset < 32)
1676 info[idx++] = (struct field_modify_info){4, 0,
1677 MLX5_MODI_OUT_DIPV6_31_0};
1678 if (data->offset < 64)
1679 info[idx++] = (struct field_modify_info){4, 0,
1680 MLX5_MODI_OUT_DIPV6_63_32};
1681 if (data->offset < 96)
1682 info[idx++] = (struct field_modify_info){4, 0,
1683 MLX5_MODI_OUT_DIPV6_95_64};
1684 if (data->offset < 128)
1685 info[idx++] = (struct field_modify_info){4, 0,
1686 MLX5_MODI_OUT_DIPV6_127_96};
1689 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1690 info[idx] = (struct field_modify_info){2, 0,
1691 MLX5_MODI_OUT_TCP_SPORT};
1693 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1695 case RTE_FLOW_FIELD_TCP_PORT_DST:
1696 info[idx] = (struct field_modify_info){2, 0,
1697 MLX5_MODI_OUT_TCP_DPORT};
1699 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1701 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1702 info[idx] = (struct field_modify_info){4, 0,
1703 MLX5_MODI_OUT_TCP_SEQ_NUM};
1705 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1708 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1709 info[idx] = (struct field_modify_info){4, 0,
1710 MLX5_MODI_OUT_TCP_ACK_NUM};
1712 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1715 case RTE_FLOW_FIELD_TCP_FLAGS:
1716 info[idx] = (struct field_modify_info){2, 0,
1717 MLX5_MODI_OUT_TCP_FLAGS};
1719 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1721 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1722 info[idx] = (struct field_modify_info){2, 0,
1723 MLX5_MODI_OUT_UDP_SPORT};
1725 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1727 case RTE_FLOW_FIELD_UDP_PORT_DST:
1728 info[idx] = (struct field_modify_info){2, 0,
1729 MLX5_MODI_OUT_UDP_DPORT};
1731 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1733 case RTE_FLOW_FIELD_VXLAN_VNI:
1734 /* not supported yet */
1736 case RTE_FLOW_FIELD_GENEVE_VNI:
1737 /* not supported yet*/
1739 case RTE_FLOW_FIELD_GTP_TEID:
1740 info[idx] = (struct field_modify_info){4, 0,
1741 MLX5_MODI_GTP_TEID};
1743 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1746 case RTE_FLOW_FIELD_TAG:
1748 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1749 data->level, error);
1752 MLX5_ASSERT(reg != REG_NON);
1753 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1754 info[idx] = (struct field_modify_info){4, 0,
1758 rte_cpu_to_be_32(0xffffffff >>
1762 case RTE_FLOW_FIELD_MARK:
1764 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1768 MLX5_ASSERT(reg != REG_NON);
1769 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1770 info[idx] = (struct field_modify_info){4, 0,
1774 rte_cpu_to_be_32(0xffffffff >>
1778 case RTE_FLOW_FIELD_META:
1780 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1783 MLX5_ASSERT(reg != REG_NON);
1784 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1785 info[idx] = (struct field_modify_info){4, 0,
1789 rte_cpu_to_be_32(0xffffffff >>
1793 case RTE_FLOW_FIELD_POINTER:
1794 case RTE_FLOW_FIELD_VALUE:
1795 if (data->field == RTE_FLOW_FIELD_POINTER)
1796 memcpy(&val, (void *)(uintptr_t)data->value,
1800 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1802 if (dst_width > 16) {
1803 value[idx] = rte_cpu_to_be_32(val);
1805 } else if (dst_width > 8) {
1806 value[idx] = rte_cpu_to_be_16(val);
1809 value[idx] = (uint8_t)val;
1824 * Convert modify_field action to DV specification.
1827 * Pointer to the rte_eth_dev structure.
1828 * @param[in,out] resource
1829 * Pointer to the modify-header resource.
1831 * Pointer to action specification.
1833 * Attributes of flow that includes this item.
1835 * Pointer to the error structure.
1838 * 0 on success, a negative errno value otherwise and rte_errno is set.
1841 flow_dv_convert_action_modify_field
1842 (struct rte_eth_dev *dev,
1843 struct mlx5_flow_dv_modify_hdr_resource *resource,
1844 const struct rte_flow_action *action,
1845 const struct rte_flow_attr *attr,
1846 struct rte_flow_error *error)
1848 const struct rte_flow_action_modify_field *conf =
1849 (const struct rte_flow_action_modify_field *)(action->conf);
1850 struct rte_flow_item item;
1851 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1853 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1855 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1856 uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1858 uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1860 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1861 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1862 type = MLX5_MODIFICATION_TYPE_SET;
1863 /** For SET fill the destination field (field) first. */
1864 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1865 value, conf->width, dst_width, dev, attr, error);
1866 /** Then copy immediate value from source as per mask. */
1867 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1868 value, conf->width, dst_width, dev, attr, error);
1871 type = MLX5_MODIFICATION_TYPE_COPY;
1872 /** For COPY fill the destination field (dcopy) without mask. */
1873 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1874 value, conf->width, dst_width, dev, attr, error);
1875 /** Then construct the source field (field) with mask. */
1876 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1877 value, conf->width, dst_width, dev, attr, error);
1880 return flow_dv_convert_modify_action(&item,
1881 field, dcopy, resource, type, error);
1885 * Validate MARK item.
1888 * Pointer to the rte_eth_dev structure.
1890 * Item specification.
1892 * Attributes of flow that includes this item.
1894 * Pointer to error structure.
1897 * 0 on success, a negative errno value otherwise and rte_errno is set.
1900 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1901 const struct rte_flow_item *item,
1902 const struct rte_flow_attr *attr __rte_unused,
1903 struct rte_flow_error *error)
1905 struct mlx5_priv *priv = dev->data->dev_private;
1906 struct mlx5_dev_config *config = &priv->config;
1907 const struct rte_flow_item_mark *spec = item->spec;
1908 const struct rte_flow_item_mark *mask = item->mask;
1909 const struct rte_flow_item_mark nic_mask = {
1910 .id = priv->sh->dv_mark_mask,
1914 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1915 return rte_flow_error_set(error, ENOTSUP,
1916 RTE_FLOW_ERROR_TYPE_ITEM, item,
1917 "extended metadata feature"
1919 if (!mlx5_flow_ext_mreg_supported(dev))
1920 return rte_flow_error_set(error, ENOTSUP,
1921 RTE_FLOW_ERROR_TYPE_ITEM, item,
1922 "extended metadata register"
1923 " isn't supported");
1925 return rte_flow_error_set(error, ENOTSUP,
1926 RTE_FLOW_ERROR_TYPE_ITEM, item,
1927 "extended metadata register"
1928 " isn't available");
1929 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1933 return rte_flow_error_set(error, EINVAL,
1934 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1936 "data cannot be empty");
1937 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1941 "mark id exceeds the limit");
1945 return rte_flow_error_set(error, EINVAL,
1946 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1947 "mask cannot be zero");
1949 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1950 (const uint8_t *)&nic_mask,
1951 sizeof(struct rte_flow_item_mark),
1952 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1959 * Validate META item.
1962 * Pointer to the rte_eth_dev structure.
1964 * Item specification.
1966 * Attributes of flow that includes this item.
1968 * Pointer to error structure.
1971 * 0 on success, a negative errno value otherwise and rte_errno is set.
1974 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1975 const struct rte_flow_item *item,
1976 const struct rte_flow_attr *attr,
1977 struct rte_flow_error *error)
1979 struct mlx5_priv *priv = dev->data->dev_private;
1980 struct mlx5_dev_config *config = &priv->config;
1981 const struct rte_flow_item_meta *spec = item->spec;
1982 const struct rte_flow_item_meta *mask = item->mask;
1983 struct rte_flow_item_meta nic_mask = {
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1993 "data cannot be empty");
1994 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1995 if (!mlx5_flow_ext_mreg_supported(dev))
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ITEM, item,
1998 "extended metadata register"
1999 " isn't supported");
2000 reg = flow_dv_get_metadata_reg(dev, attr, error);
2004 return rte_flow_error_set(error, ENOTSUP,
2005 RTE_FLOW_ERROR_TYPE_ITEM, item,
2006 "unavalable extended metadata register");
2008 return rte_flow_error_set(error, ENOTSUP,
2009 RTE_FLOW_ERROR_TYPE_ITEM, item,
2013 nic_mask.data = priv->sh->dv_meta_mask;
2016 return rte_flow_error_set(error, ENOTSUP,
2017 RTE_FLOW_ERROR_TYPE_ITEM, item,
2018 "extended metadata feature "
2019 "should be enabled when "
2020 "meta item is requested "
2021 "with e-switch mode ");
2023 return rte_flow_error_set(error, ENOTSUP,
2024 RTE_FLOW_ERROR_TYPE_ITEM, item,
2025 "match on metadata for ingress "
2026 "is not supported in legacy "
2030 mask = &rte_flow_item_meta_mask;
2032 return rte_flow_error_set(error, EINVAL,
2033 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2034 "mask cannot be zero");
2036 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2037 (const uint8_t *)&nic_mask,
2038 sizeof(struct rte_flow_item_meta),
2039 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2044 * Validate TAG item.
2047 * Pointer to the rte_eth_dev structure.
2049 * Item specification.
2051 * Attributes of flow that includes this item.
2053 * Pointer to error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2060 const struct rte_flow_item *item,
2061 const struct rte_flow_attr *attr __rte_unused,
2062 struct rte_flow_error *error)
2064 const struct rte_flow_item_tag *spec = item->spec;
2065 const struct rte_flow_item_tag *mask = item->mask;
2066 const struct rte_flow_item_tag nic_mask = {
2067 .data = RTE_BE32(UINT32_MAX),
2072 if (!mlx5_flow_ext_mreg_supported(dev))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ITEM, item,
2075 "extensive metadata register"
2076 " isn't supported");
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2081 "data cannot be empty");
2083 mask = &rte_flow_item_tag_mask;
2085 return rte_flow_error_set(error, EINVAL,
2086 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2087 "mask cannot be zero");
2089 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2090 (const uint8_t *)&nic_mask,
2091 sizeof(struct rte_flow_item_tag),
2092 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2095 if (mask->index != 0xff)
2096 return rte_flow_error_set(error, EINVAL,
2097 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2098 "partial mask for tag index"
2099 " is not supported");
2100 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2103 MLX5_ASSERT(ret != REG_NON);
2108 * Validate vport item.
2111 * Pointer to the rte_eth_dev structure.
2113 * Item specification.
2115 * Attributes of flow that includes this item.
2116 * @param[in] item_flags
2117 * Bit-fields that holds the items detected until now.
2119 * Pointer to error structure.
2122 * 0 on success, a negative errno value otherwise and rte_errno is set.
2125 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2126 const struct rte_flow_item *item,
2127 const struct rte_flow_attr *attr,
2128 uint64_t item_flags,
2129 struct rte_flow_error *error)
2131 const struct rte_flow_item_port_id *spec = item->spec;
2132 const struct rte_flow_item_port_id *mask = item->mask;
2133 const struct rte_flow_item_port_id switch_mask = {
2136 struct mlx5_priv *esw_priv;
2137 struct mlx5_priv *dev_priv;
2140 if (!attr->transfer)
2141 return rte_flow_error_set(error, EINVAL,
2142 RTE_FLOW_ERROR_TYPE_ITEM,
2144 "match on port id is valid only"
2145 " when transfer flag is enabled");
2146 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2147 return rte_flow_error_set(error, ENOTSUP,
2148 RTE_FLOW_ERROR_TYPE_ITEM, item,
2149 "multiple source ports are not"
2152 mask = &switch_mask;
2153 if (mask->id != 0xffffffff)
2154 return rte_flow_error_set(error, ENOTSUP,
2155 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2157 "no support for partial mask on"
2159 ret = mlx5_flow_item_acceptable
2160 (item, (const uint8_t *)mask,
2161 (const uint8_t *)&rte_flow_item_port_id_mask,
2162 sizeof(struct rte_flow_item_port_id),
2163 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2168 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2170 return rte_flow_error_set(error, rte_errno,
2171 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2172 "failed to obtain E-Switch info for"
2174 dev_priv = mlx5_dev_to_eswitch_info(dev);
2176 return rte_flow_error_set(error, rte_errno,
2177 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2179 "failed to obtain E-Switch info");
2180 if (esw_priv->domain_id != dev_priv->domain_id)
2181 return rte_flow_error_set(error, EINVAL,
2182 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2183 "cannot match on a port from a"
2184 " different E-Switch");
2189 * Validate VLAN item.
2192 * Item specification.
2193 * @param[in] item_flags
2194 * Bit-fields that holds the items detected until now.
2196 * Ethernet device flow is being created on.
2198 * Pointer to error structure.
2201 * 0 on success, a negative errno value otherwise and rte_errno is set.
2204 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2205 uint64_t item_flags,
2206 struct rte_eth_dev *dev,
2207 struct rte_flow_error *error)
2209 const struct rte_flow_item_vlan *mask = item->mask;
2210 const struct rte_flow_item_vlan nic_mask = {
2211 .tci = RTE_BE16(UINT16_MAX),
2212 .inner_type = RTE_BE16(UINT16_MAX),
2215 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2217 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2218 MLX5_FLOW_LAYER_INNER_L4) :
2219 (MLX5_FLOW_LAYER_OUTER_L3 |
2220 MLX5_FLOW_LAYER_OUTER_L4);
2221 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2222 MLX5_FLOW_LAYER_OUTER_VLAN;
2224 if (item_flags & vlanm)
2225 return rte_flow_error_set(error, EINVAL,
2226 RTE_FLOW_ERROR_TYPE_ITEM, item,
2227 "multiple VLAN layers not supported");
2228 else if ((item_flags & l34m) != 0)
2229 return rte_flow_error_set(error, EINVAL,
2230 RTE_FLOW_ERROR_TYPE_ITEM, item,
2231 "VLAN cannot follow L3/L4 layer");
2233 mask = &rte_flow_item_vlan_mask;
2234 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2235 (const uint8_t *)&nic_mask,
2236 sizeof(struct rte_flow_item_vlan),
2237 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2240 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2241 struct mlx5_priv *priv = dev->data->dev_private;
2243 if (priv->vmwa_context) {
2245 * Non-NULL context means we have a virtual machine
2246 * and SR-IOV enabled, we have to create VLAN interface
2247 * to make hypervisor to setup E-Switch vport
2248 * context correctly. We avoid creating the multiple
2249 * VLAN interfaces, so we cannot support VLAN tag mask.
2251 return rte_flow_error_set(error, EINVAL,
2252 RTE_FLOW_ERROR_TYPE_ITEM,
2254 "VLAN tag mask is not"
2255 " supported in virtual"
2263 * GTP flags are contained in 1 byte of the format:
2264 * -------------------------------------------
2265 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2266 * |-----------------------------------------|
2267 * | value | Version | PT | Res | E | S | PN |
2268 * -------------------------------------------
2270 * Matching is supported only for GTP flags E, S, PN.
2272 #define MLX5_GTP_FLAGS_MASK 0x07
2275 * Validate GTP item.
2278 * Pointer to the rte_eth_dev structure.
2280 * Item specification.
2281 * @param[in] item_flags
2282 * Bit-fields that holds the items detected until now.
2284 * Pointer to error structure.
2287 * 0 on success, a negative errno value otherwise and rte_errno is set.
2290 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2291 const struct rte_flow_item *item,
2292 uint64_t item_flags,
2293 struct rte_flow_error *error)
2295 struct mlx5_priv *priv = dev->data->dev_private;
2296 const struct rte_flow_item_gtp *spec = item->spec;
2297 const struct rte_flow_item_gtp *mask = item->mask;
2298 const struct rte_flow_item_gtp nic_mask = {
2299 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2301 .teid = RTE_BE32(0xffffffff),
2304 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2305 return rte_flow_error_set(error, ENOTSUP,
2306 RTE_FLOW_ERROR_TYPE_ITEM, item,
2307 "GTP support is not enabled");
2308 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2309 return rte_flow_error_set(error, ENOTSUP,
2310 RTE_FLOW_ERROR_TYPE_ITEM, item,
2311 "multiple tunnel layers not"
2313 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2314 return rte_flow_error_set(error, EINVAL,
2315 RTE_FLOW_ERROR_TYPE_ITEM, item,
2316 "no outer UDP layer found");
2318 mask = &rte_flow_item_gtp_mask;
2319 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2320 return rte_flow_error_set(error, ENOTSUP,
2321 RTE_FLOW_ERROR_TYPE_ITEM, item,
2322 "Match is supported for GTP"
2324 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2325 (const uint8_t *)&nic_mask,
2326 sizeof(struct rte_flow_item_gtp),
2327 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2331 * Validate GTP PSC item.
2334 * Item specification.
2335 * @param[in] last_item
2336 * Previous validated item in the pattern items.
2337 * @param[in] gtp_item
2338 * Previous GTP item specification.
2340 * Pointer to flow attributes.
2342 * Pointer to error structure.
2345 * 0 on success, a negative errno value otherwise and rte_errno is set.
2348 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2350 const struct rte_flow_item *gtp_item,
2351 const struct rte_flow_attr *attr,
2352 struct rte_flow_error *error)
2354 const struct rte_flow_item_gtp *gtp_spec;
2355 const struct rte_flow_item_gtp *gtp_mask;
2356 const struct rte_flow_item_gtp_psc *spec;
2357 const struct rte_flow_item_gtp_psc *mask;
2358 const struct rte_flow_item_gtp_psc nic_mask = {
2363 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2364 return rte_flow_error_set
2365 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2366 "GTP PSC item must be preceded with GTP item");
2367 gtp_spec = gtp_item->spec;
2368 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2369 /* GTP spec and E flag is requested to match zero. */
2371 (gtp_mask->v_pt_rsv_flags &
2372 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2373 return rte_flow_error_set
2374 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2375 "GTP E flag must be 1 to match GTP PSC");
2376 /* Check the flow is not created in group zero. */
2377 if (!attr->transfer && !attr->group)
2378 return rte_flow_error_set
2379 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2380 "GTP PSC is not supported for group 0");
2381 /* GTP spec is here and E flag is requested to match zero. */
2385 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2386 if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2387 return rte_flow_error_set
2388 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2389 "PDU type should be smaller than 16");
2390 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2391 (const uint8_t *)&nic_mask,
2392 sizeof(struct rte_flow_item_gtp_psc),
2393 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2397 * Validate IPV4 item.
2398 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2399 * add specific validation of fragment_offset field,
2402 * Item specification.
2403 * @param[in] item_flags
2404 * Bit-fields that holds the items detected until now.
2406 * Pointer to error structure.
2409 * 0 on success, a negative errno value otherwise and rte_errno is set.
2412 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2413 uint64_t item_flags,
2415 uint16_t ether_type,
2416 struct rte_flow_error *error)
2419 const struct rte_flow_item_ipv4 *spec = item->spec;
2420 const struct rte_flow_item_ipv4 *last = item->last;
2421 const struct rte_flow_item_ipv4 *mask = item->mask;
2422 rte_be16_t fragment_offset_spec = 0;
2423 rte_be16_t fragment_offset_last = 0;
2424 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2426 .src_addr = RTE_BE32(0xffffffff),
2427 .dst_addr = RTE_BE32(0xffffffff),
2428 .type_of_service = 0xff,
2429 .fragment_offset = RTE_BE16(0xffff),
2430 .next_proto_id = 0xff,
2431 .time_to_live = 0xff,
2435 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2436 ether_type, &nic_ipv4_mask,
2437 MLX5_ITEM_RANGE_ACCEPTED, error);
2441 fragment_offset_spec = spec->hdr.fragment_offset &
2442 mask->hdr.fragment_offset;
2443 if (!fragment_offset_spec)
2446 * spec and mask are valid, enforce using full mask to make sure the
2447 * complete value is used correctly.
2449 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2450 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2451 return rte_flow_error_set(error, EINVAL,
2452 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2453 item, "must use full mask for"
2454 " fragment_offset");
2456 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2457 * indicating this is 1st fragment of fragmented packet.
2458 * This is not yet supported in MLX5, return appropriate error message.
2460 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2461 return rte_flow_error_set(error, ENOTSUP,
2462 RTE_FLOW_ERROR_TYPE_ITEM, item,
2463 "match on first fragment not "
2465 if (fragment_offset_spec && !last)
2466 return rte_flow_error_set(error, ENOTSUP,
2467 RTE_FLOW_ERROR_TYPE_ITEM, item,
2468 "specified value not supported");
2469 /* spec and last are valid, validate the specified range. */
2470 fragment_offset_last = last->hdr.fragment_offset &
2471 mask->hdr.fragment_offset;
2473 * Match on fragment_offset spec 0x2001 and last 0x3fff
2474 * means MF is 1 and frag-offset is > 0.
2475 * This packet is fragment 2nd and onward, excluding last.
2476 * This is not yet supported in MLX5, return appropriate
2479 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2480 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2481 return rte_flow_error_set(error, ENOTSUP,
2482 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2483 last, "match on following "
2484 "fragments not supported");
2486 * Match on fragment_offset spec 0x0001 and last 0x1fff
2487 * means MF is 0 and frag-offset is > 0.
2488 * This packet is last fragment of fragmented packet.
2489 * This is not yet supported in MLX5, return appropriate
2492 if (fragment_offset_spec == RTE_BE16(1) &&
2493 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2494 return rte_flow_error_set(error, ENOTSUP,
2495 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2496 last, "match on last "
2497 "fragment not supported");
2499 * Match on fragment_offset spec 0x0001 and last 0x3fff
2500 * means MF and/or frag-offset is not 0.
2501 * This is a fragmented packet.
2502 * Other range values are invalid and rejected.
2504 if (!(fragment_offset_spec == RTE_BE16(1) &&
2505 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2506 return rte_flow_error_set(error, ENOTSUP,
2507 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2508 "specified range not supported");
2513 * Validate IPV6 fragment extension item.
2516 * Item specification.
2517 * @param[in] item_flags
2518 * Bit-fields that holds the items detected until now.
2520 * Pointer to error structure.
2523 * 0 on success, a negative errno value otherwise and rte_errno is set.
2526 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2527 uint64_t item_flags,
2528 struct rte_flow_error *error)
2530 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2531 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2532 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2533 rte_be16_t frag_data_spec = 0;
2534 rte_be16_t frag_data_last = 0;
2535 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2536 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2537 MLX5_FLOW_LAYER_OUTER_L4;
2539 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2541 .next_header = 0xff,
2542 .frag_data = RTE_BE16(0xffff),
2546 if (item_flags & l4m)
2547 return rte_flow_error_set(error, EINVAL,
2548 RTE_FLOW_ERROR_TYPE_ITEM, item,
2549 "ipv6 fragment extension item cannot "
2551 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2552 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2553 return rte_flow_error_set(error, EINVAL,
2554 RTE_FLOW_ERROR_TYPE_ITEM, item,
2555 "ipv6 fragment extension item must "
2556 "follow ipv6 item");
2558 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2559 if (!frag_data_spec)
2562 * spec and mask are valid, enforce using full mask to make sure the
2563 * complete value is used correctly.
2565 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2566 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2567 return rte_flow_error_set(error, EINVAL,
2568 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2569 item, "must use full mask for"
2572 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2573 * This is 1st fragment of fragmented packet.
2575 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2576 return rte_flow_error_set(error, ENOTSUP,
2577 RTE_FLOW_ERROR_TYPE_ITEM, item,
2578 "match on first fragment not "
2580 if (frag_data_spec && !last)
2581 return rte_flow_error_set(error, EINVAL,
2582 RTE_FLOW_ERROR_TYPE_ITEM, item,
2583 "specified value not supported");
2584 ret = mlx5_flow_item_acceptable
2585 (item, (const uint8_t *)mask,
2586 (const uint8_t *)&nic_mask,
2587 sizeof(struct rte_flow_item_ipv6_frag_ext),
2588 MLX5_ITEM_RANGE_ACCEPTED, error);
2591 /* spec and last are valid, validate the specified range. */
2592 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2594 * Match on frag_data spec 0x0009 and last 0xfff9
2595 * means M is 1 and frag-offset is > 0.
2596 * This packet is fragment 2nd and onward, excluding last.
2597 * This is not yet supported in MLX5, return appropriate
2600 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2601 RTE_IPV6_EHDR_MF_MASK) &&
2602 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, ENOTSUP,
2604 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2605 last, "match on following "
2606 "fragments not supported");
2608 * Match on frag_data spec 0x0008 and last 0xfff8
2609 * means M is 0 and frag-offset is > 0.
2610 * This packet is last fragment of fragmented packet.
2611 * This is not yet supported in MLX5, return appropriate
2614 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2615 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2616 return rte_flow_error_set(error, ENOTSUP,
2617 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2618 last, "match on last "
2619 "fragment not supported");
2620 /* Other range values are invalid and rejected. */
2621 return rte_flow_error_set(error, EINVAL,
2622 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2623 "specified range not supported");
2627 * Validate the pop VLAN action.
2630 * Pointer to the rte_eth_dev structure.
2631 * @param[in] action_flags
2632 * Holds the actions detected until now.
2634 * Pointer to the pop vlan action.
2635 * @param[in] item_flags
2636 * The items found in this flow rule.
2638 * Pointer to flow attributes.
2640 * Pointer to error structure.
2643 * 0 on success, a negative errno value otherwise and rte_errno is set.
2646 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2647 uint64_t action_flags,
2648 const struct rte_flow_action *action,
2649 uint64_t item_flags,
2650 const struct rte_flow_attr *attr,
2651 struct rte_flow_error *error)
2653 const struct mlx5_priv *priv = dev->data->dev_private;
2657 if (!priv->sh->pop_vlan_action)
2658 return rte_flow_error_set(error, ENOTSUP,
2659 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2661 "pop vlan action is not supported");
2663 return rte_flow_error_set(error, ENOTSUP,
2664 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2666 "pop vlan action not supported for "
2668 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2669 return rte_flow_error_set(error, ENOTSUP,
2670 RTE_FLOW_ERROR_TYPE_ACTION, action,
2671 "no support for multiple VLAN "
2673 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2674 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2675 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2676 return rte_flow_error_set(error, ENOTSUP,
2677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2679 "cannot pop vlan after decap without "
2680 "match on inner vlan in the flow");
2681 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2682 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2683 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2684 return rte_flow_error_set(error, ENOTSUP,
2685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2687 "cannot pop vlan without a "
2688 "match on (outer) vlan in the flow");
2689 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2690 return rte_flow_error_set(error, EINVAL,
2691 RTE_FLOW_ERROR_TYPE_ACTION, action,
2692 "wrong action order, port_id should "
2693 "be after pop VLAN action");
2694 if (!attr->transfer && priv->representor)
2695 return rte_flow_error_set(error, ENOTSUP,
2696 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2697 "pop vlan action for VF representor "
2698 "not supported on NIC table");
2703 * Get VLAN default info from vlan match info.
2706 * the list of item specifications.
2708 * pointer VLAN info to fill to.
2711 * 0 on success, a negative errno value otherwise and rte_errno is set.
2714 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2715 struct rte_vlan_hdr *vlan)
2717 const struct rte_flow_item_vlan nic_mask = {
2718 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2719 MLX5DV_FLOW_VLAN_VID_MASK),
2720 .inner_type = RTE_BE16(0xffff),
2725 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2726 int type = items->type;
2728 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2729 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2732 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2733 const struct rte_flow_item_vlan *vlan_m = items->mask;
2734 const struct rte_flow_item_vlan *vlan_v = items->spec;
2736 /* If VLAN item in pattern doesn't contain data, return here. */
2741 /* Only full match values are accepted */
2742 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2743 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2744 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2746 rte_be_to_cpu_16(vlan_v->tci &
2747 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2749 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2750 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2751 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2753 rte_be_to_cpu_16(vlan_v->tci &
2754 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2756 if (vlan_m->inner_type == nic_mask.inner_type)
2757 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2758 vlan_m->inner_type);
2763 * Validate the push VLAN action.
2766 * Pointer to the rte_eth_dev structure.
2767 * @param[in] action_flags
2768 * Holds the actions detected until now.
2769 * @param[in] item_flags
2770 * The items found in this flow rule.
2772 * Pointer to the action structure.
2774 * Pointer to flow attributes
2776 * Pointer to error structure.
2779 * 0 on success, a negative errno value otherwise and rte_errno is set.
2782 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2783 uint64_t action_flags,
2784 const struct rte_flow_item_vlan *vlan_m,
2785 const struct rte_flow_action *action,
2786 const struct rte_flow_attr *attr,
2787 struct rte_flow_error *error)
2789 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2790 const struct mlx5_priv *priv = dev->data->dev_private;
2792 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2793 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2794 return rte_flow_error_set(error, EINVAL,
2795 RTE_FLOW_ERROR_TYPE_ACTION, action,
2796 "invalid vlan ethertype");
2797 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2798 return rte_flow_error_set(error, EINVAL,
2799 RTE_FLOW_ERROR_TYPE_ACTION, action,
2800 "wrong action order, port_id should "
2801 "be after push VLAN");
2802 if (!attr->transfer && priv->representor)
2803 return rte_flow_error_set(error, ENOTSUP,
2804 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2805 "push vlan action for VF representor "
2806 "not supported on NIC table");
2808 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2809 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2810 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2811 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2812 !(mlx5_flow_find_action
2813 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2814 return rte_flow_error_set(error, EINVAL,
2815 RTE_FLOW_ERROR_TYPE_ACTION, action,
2816 "not full match mask on VLAN PCP and "
2817 "there is no of_set_vlan_pcp action, "
2818 "push VLAN action cannot figure out "
2821 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2822 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2823 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2824 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2825 !(mlx5_flow_find_action
2826 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2827 return rte_flow_error_set(error, EINVAL,
2828 RTE_FLOW_ERROR_TYPE_ACTION, action,
2829 "not full match mask on VLAN VID and "
2830 "there is no of_set_vlan_vid action, "
2831 "push VLAN action cannot figure out "
2838 * Validate the set VLAN PCP.
2840 * @param[in] action_flags
2841 * Holds the actions detected until now.
2842 * @param[in] actions
2843 * Pointer to the list of actions remaining in the flow rule.
2845 * Pointer to error structure.
2848 * 0 on success, a negative errno value otherwise and rte_errno is set.
2851 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2852 const struct rte_flow_action actions[],
2853 struct rte_flow_error *error)
2855 const struct rte_flow_action *action = actions;
2856 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2858 if (conf->vlan_pcp > 7)
2859 return rte_flow_error_set(error, EINVAL,
2860 RTE_FLOW_ERROR_TYPE_ACTION, action,
2861 "VLAN PCP value is too big");
2862 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2863 return rte_flow_error_set(error, ENOTSUP,
2864 RTE_FLOW_ERROR_TYPE_ACTION, action,
2865 "set VLAN PCP action must follow "
2866 "the push VLAN action");
2867 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2868 return rte_flow_error_set(error, ENOTSUP,
2869 RTE_FLOW_ERROR_TYPE_ACTION, action,
2870 "Multiple VLAN PCP modification are "
2872 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2873 return rte_flow_error_set(error, EINVAL,
2874 RTE_FLOW_ERROR_TYPE_ACTION, action,
2875 "wrong action order, port_id should "
2876 "be after set VLAN PCP");
2881 * Validate the set VLAN VID.
2883 * @param[in] item_flags
2884 * Holds the items detected in this rule.
2885 * @param[in] action_flags
2886 * Holds the actions detected until now.
2887 * @param[in] actions
2888 * Pointer to the list of actions remaining in the flow rule.
2890 * Pointer to error structure.
2893 * 0 on success, a negative errno value otherwise and rte_errno is set.
2896 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2897 uint64_t action_flags,
2898 const struct rte_flow_action actions[],
2899 struct rte_flow_error *error)
2901 const struct rte_flow_action *action = actions;
2902 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2904 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2905 return rte_flow_error_set(error, EINVAL,
2906 RTE_FLOW_ERROR_TYPE_ACTION, action,
2907 "VLAN VID value is too big");
2908 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2909 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2910 return rte_flow_error_set(error, ENOTSUP,
2911 RTE_FLOW_ERROR_TYPE_ACTION, action,
2912 "set VLAN VID action must follow push"
2913 " VLAN action or match on VLAN item");
2914 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2915 return rte_flow_error_set(error, ENOTSUP,
2916 RTE_FLOW_ERROR_TYPE_ACTION, action,
2917 "Multiple VLAN VID modifications are "
2919 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2920 return rte_flow_error_set(error, EINVAL,
2921 RTE_FLOW_ERROR_TYPE_ACTION, action,
2922 "wrong action order, port_id should "
2923 "be after set VLAN VID");
2928 * Validate the FLAG action.
2931 * Pointer to the rte_eth_dev structure.
2932 * @param[in] action_flags
2933 * Holds the actions detected until now.
2935 * Pointer to flow attributes
2937 * Pointer to error structure.
2940 * 0 on success, a negative errno value otherwise and rte_errno is set.
2943 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2944 uint64_t action_flags,
2945 const struct rte_flow_attr *attr,
2946 struct rte_flow_error *error)
2948 struct mlx5_priv *priv = dev->data->dev_private;
2949 struct mlx5_dev_config *config = &priv->config;
2952 /* Fall back if no extended metadata register support. */
2953 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2954 return mlx5_flow_validate_action_flag(action_flags, attr,
2956 /* Extensive metadata mode requires registers. */
2957 if (!mlx5_flow_ext_mreg_supported(dev))
2958 return rte_flow_error_set(error, ENOTSUP,
2959 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2960 "no metadata registers "
2961 "to support flag action");
2962 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2963 return rte_flow_error_set(error, ENOTSUP,
2964 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2965 "extended metadata register"
2966 " isn't available");
2967 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2970 MLX5_ASSERT(ret > 0);
2971 if (action_flags & MLX5_FLOW_ACTION_MARK)
2972 return rte_flow_error_set(error, EINVAL,
2973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2974 "can't mark and flag in same flow");
2975 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2976 return rte_flow_error_set(error, EINVAL,
2977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2979 " actions in same flow");
2984 * Validate MARK action.
2987 * Pointer to the rte_eth_dev structure.
2989 * Pointer to action.
2990 * @param[in] action_flags
2991 * Holds the actions detected until now.
2993 * Pointer to flow attributes
2995 * Pointer to error structure.
2998 * 0 on success, a negative errno value otherwise and rte_errno is set.
3001 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3002 const struct rte_flow_action *action,
3003 uint64_t action_flags,
3004 const struct rte_flow_attr *attr,
3005 struct rte_flow_error *error)
3007 struct mlx5_priv *priv = dev->data->dev_private;
3008 struct mlx5_dev_config *config = &priv->config;
3009 const struct rte_flow_action_mark *mark = action->conf;
3012 if (is_tunnel_offload_active(dev))
3013 return rte_flow_error_set(error, ENOTSUP,
3014 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3016 "if tunnel offload active");
3017 /* Fall back if no extended metadata register support. */
3018 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3019 return mlx5_flow_validate_action_mark(action, action_flags,
3021 /* Extensive metadata mode requires registers. */
3022 if (!mlx5_flow_ext_mreg_supported(dev))
3023 return rte_flow_error_set(error, ENOTSUP,
3024 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025 "no metadata registers "
3026 "to support mark action");
3027 if (!priv->sh->dv_mark_mask)
3028 return rte_flow_error_set(error, ENOTSUP,
3029 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3030 "extended metadata register"
3031 " isn't available");
3032 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3035 MLX5_ASSERT(ret > 0);
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION, action,
3039 "configuration cannot be null");
3040 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3041 return rte_flow_error_set(error, EINVAL,
3042 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3044 "mark id exceeds the limit");
3045 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3046 return rte_flow_error_set(error, EINVAL,
3047 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3048 "can't flag and mark in same flow");
3049 if (action_flags & MLX5_FLOW_ACTION_MARK)
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3052 "can't have 2 mark actions in same"
3058 * Validate SET_META action.
3061 * Pointer to the rte_eth_dev structure.
3063 * Pointer to the action structure.
3064 * @param[in] action_flags
3065 * Holds the actions detected until now.
3067 * Pointer to flow attributes
3069 * Pointer to error structure.
3072 * 0 on success, a negative errno value otherwise and rte_errno is set.
3075 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3076 const struct rte_flow_action *action,
3077 uint64_t action_flags __rte_unused,
3078 const struct rte_flow_attr *attr,
3079 struct rte_flow_error *error)
3081 const struct rte_flow_action_set_meta *conf;
3082 uint32_t nic_mask = UINT32_MAX;
3085 if (!mlx5_flow_ext_mreg_supported(dev))
3086 return rte_flow_error_set(error, ENOTSUP,
3087 RTE_FLOW_ERROR_TYPE_ACTION, action,
3088 "extended metadata register"
3089 " isn't supported");
3090 reg = flow_dv_get_metadata_reg(dev, attr, error);
3094 return rte_flow_error_set(error, ENOTSUP,
3095 RTE_FLOW_ERROR_TYPE_ACTION, action,
3096 "unavalable extended metadata register");
3097 if (reg != REG_A && reg != REG_B) {
3098 struct mlx5_priv *priv = dev->data->dev_private;
3100 nic_mask = priv->sh->dv_meta_mask;
3102 if (!(action->conf))
3103 return rte_flow_error_set(error, EINVAL,
3104 RTE_FLOW_ERROR_TYPE_ACTION, action,
3105 "configuration cannot be null");
3106 conf = (const struct rte_flow_action_set_meta *)action->conf;
3108 return rte_flow_error_set(error, EINVAL,
3109 RTE_FLOW_ERROR_TYPE_ACTION, action,
3110 "zero mask doesn't have any effect");
3111 if (conf->mask & ~nic_mask)
3112 return rte_flow_error_set(error, EINVAL,
3113 RTE_FLOW_ERROR_TYPE_ACTION, action,
3114 "meta data must be within reg C0");
3119 * Validate SET_TAG action.
3122 * Pointer to the rte_eth_dev structure.
3124 * Pointer to the action structure.
3125 * @param[in] action_flags
3126 * Holds the actions detected until now.
3128 * Pointer to flow attributes
3130 * Pointer to error structure.
3133 * 0 on success, a negative errno value otherwise and rte_errno is set.
3136 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3137 const struct rte_flow_action *action,
3138 uint64_t action_flags,
3139 const struct rte_flow_attr *attr,
3140 struct rte_flow_error *error)
3142 const struct rte_flow_action_set_tag *conf;
3143 const uint64_t terminal_action_flags =
3144 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3145 MLX5_FLOW_ACTION_RSS;
3148 if (!mlx5_flow_ext_mreg_supported(dev))
3149 return rte_flow_error_set(error, ENOTSUP,
3150 RTE_FLOW_ERROR_TYPE_ACTION, action,
3151 "extensive metadata register"
3152 " isn't supported");
3153 if (!(action->conf))
3154 return rte_flow_error_set(error, EINVAL,
3155 RTE_FLOW_ERROR_TYPE_ACTION, action,
3156 "configuration cannot be null");
3157 conf = (const struct rte_flow_action_set_tag *)action->conf;
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, action,
3161 "zero mask doesn't have any effect");
3162 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3165 if (!attr->transfer && attr->ingress &&
3166 (action_flags & terminal_action_flags))
3167 return rte_flow_error_set(error, EINVAL,
3168 RTE_FLOW_ERROR_TYPE_ACTION, action,
3169 "set_tag has no effect"
3170 " with terminal actions");
3175 * Check if action counter is shared by either old or new mechanism.
3178 * Pointer to the action structure.
3181 * True when counter is shared, false otherwise.
3184 is_shared_action_count(const struct rte_flow_action *action)
3186 const struct rte_flow_action_count *count =
3187 (const struct rte_flow_action_count *)action->conf;
3189 if ((int)action->type == MLX5_RTE_FLOW_ACTION_TYPE_COUNT)
3191 return !!(count && count->shared);
3195 * Validate count action.
3198 * Pointer to rte_eth_dev structure.
3200 * Indicator if action is shared.
3201 * @param[in] action_flags
3202 * Holds the actions detected until now.
3204 * Pointer to error structure.
3207 * 0 on success, a negative errno value otherwise and rte_errno is set.
3210 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3211 uint64_t action_flags,
3212 struct rte_flow_error *error)
3214 struct mlx5_priv *priv = dev->data->dev_private;
3216 if (!priv->config.devx)
3218 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3219 return rte_flow_error_set(error, EINVAL,
3220 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3221 "duplicate count actions set");
3222 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3223 !priv->sh->flow_hit_aso_en)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3226 "old age and shared count combination is not supported");
3227 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3231 return rte_flow_error_set
3233 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3235 "count action not supported");
3239 * Validate the L2 encap action.
3242 * Pointer to the rte_eth_dev structure.
3243 * @param[in] action_flags
3244 * Holds the actions detected until now.
3246 * Pointer to the action structure.
3248 * Pointer to flow attributes.
3250 * Pointer to error structure.
3253 * 0 on success, a negative errno value otherwise and rte_errno is set.
3256 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3257 uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const struct rte_flow_attr *attr,
3260 struct rte_flow_error *error)
3262 const struct mlx5_priv *priv = dev->data->dev_private;
3264 if (!(action->conf))
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION, action,
3267 "configuration cannot be null");
3268 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3269 return rte_flow_error_set(error, EINVAL,
3270 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3271 "can only have a single encap action "
3273 if (!attr->transfer && priv->representor)
3274 return rte_flow_error_set(error, ENOTSUP,
3275 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3276 "encap action for VF representor "
3277 "not supported on NIC table");
3282 * Validate a decap action.
3285 * Pointer to the rte_eth_dev structure.
3286 * @param[in] action_flags
3287 * Holds the actions detected until now.
3289 * Pointer to the action structure.
3290 * @param[in] item_flags
3291 * Holds the items detected.
3293 * Pointer to flow attributes
3295 * Pointer to error structure.
3298 * 0 on success, a negative errno value otherwise and rte_errno is set.
3301 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3302 uint64_t action_flags,
3303 const struct rte_flow_action *action,
3304 const uint64_t item_flags,
3305 const struct rte_flow_attr *attr,
3306 struct rte_flow_error *error)
3308 const struct mlx5_priv *priv = dev->data->dev_private;
3310 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3311 !priv->config.decap_en)
3312 return rte_flow_error_set(error, ENOTSUP,
3313 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314 "decap is not enabled");
3315 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3316 return rte_flow_error_set(error, ENOTSUP,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3319 MLX5_FLOW_ACTION_DECAP ? "can only "
3320 "have a single decap action" : "decap "
3321 "after encap is not supported");
3322 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3323 return rte_flow_error_set(error, EINVAL,
3324 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3325 "can't have decap action after"
3328 return rte_flow_error_set(error, ENOTSUP,
3329 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3331 "decap action not supported for "
3333 if (!attr->transfer && priv->representor)
3334 return rte_flow_error_set(error, ENOTSUP,
3335 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3336 "decap action for VF representor "
3337 "not supported on NIC table");
3338 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3339 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3340 return rte_flow_error_set(error, ENOTSUP,
3341 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3342 "VXLAN item should be present for VXLAN decap");
3346 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3349 * Validate the raw encap and decap actions.
3352 * Pointer to the rte_eth_dev structure.
3354 * Pointer to the decap action.
3356 * Pointer to the encap action.
3358 * Pointer to flow attributes
3359 * @param[in/out] action_flags
3360 * Holds the actions detected until now.
3361 * @param[out] actions_n
3362 * pointer to the number of actions counter.
3364 * Pointer to the action structure.
3365 * @param[in] item_flags
3366 * Holds the items detected.
3368 * Pointer to error structure.
3371 * 0 on success, a negative errno value otherwise and rte_errno is set.
3374 flow_dv_validate_action_raw_encap_decap
3375 (struct rte_eth_dev *dev,
3376 const struct rte_flow_action_raw_decap *decap,
3377 const struct rte_flow_action_raw_encap *encap,
3378 const struct rte_flow_attr *attr, uint64_t *action_flags,
3379 int *actions_n, const struct rte_flow_action *action,
3380 uint64_t item_flags, struct rte_flow_error *error)
3382 const struct mlx5_priv *priv = dev->data->dev_private;
3385 if (encap && (!encap->size || !encap->data))
3386 return rte_flow_error_set(error, EINVAL,
3387 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3388 "raw encap data cannot be empty");
3389 if (decap && encap) {
3390 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3391 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3394 else if (encap->size <=
3395 MLX5_ENCAPSULATION_DECISION_SIZE &&
3397 MLX5_ENCAPSULATION_DECISION_SIZE)
3400 else if (encap->size >
3401 MLX5_ENCAPSULATION_DECISION_SIZE &&
3403 MLX5_ENCAPSULATION_DECISION_SIZE)
3404 /* 2 L2 actions: encap and decap. */
3407 return rte_flow_error_set(error,
3409 RTE_FLOW_ERROR_TYPE_ACTION,
3410 NULL, "unsupported too small "
3411 "raw decap and too small raw "
3412 "encap combination");
3415 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3416 item_flags, attr, error);
3419 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3423 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3424 return rte_flow_error_set(error, ENOTSUP,
3425 RTE_FLOW_ERROR_TYPE_ACTION,
3427 "small raw encap size");
3428 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3429 return rte_flow_error_set(error, EINVAL,
3430 RTE_FLOW_ERROR_TYPE_ACTION,
3432 "more than one encap action");
3433 if (!attr->transfer && priv->representor)
3434 return rte_flow_error_set
3436 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3437 "encap action for VF representor "
3438 "not supported on NIC table");
3439 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3446 * Match encap_decap resource.
3449 * Pointer to the hash list.
3451 * Pointer to exist resource entry object.
3453 * Key of the new entry.
3455 * Pointer to new encap_decap resource.
3458 * 0 on matching, none-zero otherwise.
3461 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3462 struct mlx5_hlist_entry *entry,
3463 uint64_t key __rte_unused, void *cb_ctx)
3465 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3466 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3467 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3469 cache_resource = container_of(entry,
3470 struct mlx5_flow_dv_encap_decap_resource,
3472 if (resource->reformat_type == cache_resource->reformat_type &&
3473 resource->ft_type == cache_resource->ft_type &&
3474 resource->flags == cache_resource->flags &&
3475 resource->size == cache_resource->size &&
3476 !memcmp((const void *)resource->buf,
3477 (const void *)cache_resource->buf,
3484 * Allocate encap_decap resource.
3487 * Pointer to the hash list.
3489 * Pointer to exist resource entry object.
3491 * Pointer to new encap_decap resource.
3494 * 0 on matching, none-zero otherwise.
3496 struct mlx5_hlist_entry *
3497 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3498 uint64_t key __rte_unused,
3501 struct mlx5_dev_ctx_shared *sh = list->ctx;
3502 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3503 struct mlx5dv_dr_domain *domain;
3504 struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3505 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3509 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3510 domain = sh->fdb_domain;
3511 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3512 domain = sh->rx_domain;
3514 domain = sh->tx_domain;
3515 /* Register new encap/decap resource. */
3516 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3518 if (!cache_resource) {
3519 rte_flow_error_set(ctx->error, ENOMEM,
3520 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3521 "cannot allocate resource memory");
3524 *cache_resource = *resource;
3525 cache_resource->idx = idx;
3526 ret = mlx5_flow_os_create_flow_action_packet_reformat
3527 (sh->ctx, domain, cache_resource,
3528 &cache_resource->action);
3530 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3531 rte_flow_error_set(ctx->error, ENOMEM,
3532 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3533 NULL, "cannot create action");
3537 return &cache_resource->entry;
3541 * Find existing encap/decap resource or create and register a new one.
3543 * @param[in, out] dev
3544 * Pointer to rte_eth_dev structure.
3545 * @param[in, out] resource
3546 * Pointer to encap/decap resource.
3547 * @parm[in, out] dev_flow
3548 * Pointer to the dev_flow.
3550 * pointer to error structure.
3553 * 0 on success otherwise -errno and errno is set.
3556 flow_dv_encap_decap_resource_register
3557 (struct rte_eth_dev *dev,
3558 struct mlx5_flow_dv_encap_decap_resource *resource,
3559 struct mlx5_flow *dev_flow,
3560 struct rte_flow_error *error)
3562 struct mlx5_priv *priv = dev->data->dev_private;
3563 struct mlx5_dev_ctx_shared *sh = priv->sh;
3564 struct mlx5_hlist_entry *entry;
3568 uint32_t refmt_type:8;
3570 * Header reformat actions can be shared between
3571 * non-root tables. One bit to indicate non-root
3575 uint32_t reserve:15;
3578 } encap_decap_key = {
3580 .ft_type = resource->ft_type,
3581 .refmt_type = resource->reformat_type,
3582 .is_root = !!dev_flow->dv.group,
3586 struct mlx5_flow_cb_ctx ctx = {
3592 resource->flags = dev_flow->dv.group ? 0 : 1;
3593 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3594 sizeof(encap_decap_key.v32), 0);
3595 if (resource->reformat_type !=
3596 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3598 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3599 entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3602 resource = container_of(entry, typeof(*resource), entry);
3603 dev_flow->dv.encap_decap = resource;
3604 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3609 * Find existing table jump resource or create and register a new one.
3611 * @param[in, out] dev
3612 * Pointer to rte_eth_dev structure.
3613 * @param[in, out] tbl
3614 * Pointer to flow table resource.
3615 * @parm[in, out] dev_flow
3616 * Pointer to the dev_flow.
3618 * pointer to error structure.
3621 * 0 on success otherwise -errno and errno is set.
3624 flow_dv_jump_tbl_resource_register
3625 (struct rte_eth_dev *dev __rte_unused,
3626 struct mlx5_flow_tbl_resource *tbl,
3627 struct mlx5_flow *dev_flow,
3628 struct rte_flow_error *error __rte_unused)
3630 struct mlx5_flow_tbl_data_entry *tbl_data =
3631 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3634 MLX5_ASSERT(tbl_data->jump.action);
3635 dev_flow->handle->rix_jump = tbl_data->idx;
3636 dev_flow->dv.jump = &tbl_data->jump;
3641 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3642 struct mlx5_cache_entry *entry, void *cb_ctx)
3644 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3645 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3646 struct mlx5_flow_dv_port_id_action_resource *res =
3647 container_of(entry, typeof(*res), entry);
3649 return ref->port_id != res->port_id;
3652 struct mlx5_cache_entry *
3653 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3654 struct mlx5_cache_entry *entry __rte_unused,
3657 struct mlx5_dev_ctx_shared *sh = list->ctx;
3658 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3659 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3660 struct mlx5_flow_dv_port_id_action_resource *cache;
3664 /* Register new port id action resource. */
3665 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3667 rte_flow_error_set(ctx->error, ENOMEM,
3668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669 "cannot allocate port_id action cache memory");
3673 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3677 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3678 rte_flow_error_set(ctx->error, ENOMEM,
3679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3680 "cannot create action");
3684 return &cache->entry;
3688 * Find existing table port ID resource or create and register a new one.
3690 * @param[in, out] dev
3691 * Pointer to rte_eth_dev structure.
3692 * @param[in, out] resource
3693 * Pointer to port ID action resource.
3694 * @parm[in, out] dev_flow
3695 * Pointer to the dev_flow.
3697 * pointer to error structure.
3700 * 0 on success otherwise -errno and errno is set.
3703 flow_dv_port_id_action_resource_register
3704 (struct rte_eth_dev *dev,
3705 struct mlx5_flow_dv_port_id_action_resource *resource,
3706 struct mlx5_flow *dev_flow,
3707 struct rte_flow_error *error)
3709 struct mlx5_priv *priv = dev->data->dev_private;
3710 struct mlx5_cache_entry *entry;
3711 struct mlx5_flow_dv_port_id_action_resource *cache;
3712 struct mlx5_flow_cb_ctx ctx = {
3717 entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3720 cache = container_of(entry, typeof(*cache), entry);
3721 dev_flow->dv.port_id_action = cache;
3722 dev_flow->handle->rix_port_id_action = cache->idx;
3727 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3728 struct mlx5_cache_entry *entry, void *cb_ctx)
3730 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3731 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3732 struct mlx5_flow_dv_push_vlan_action_resource *res =
3733 container_of(entry, typeof(*res), entry);
3735 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3738 struct mlx5_cache_entry *
3739 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3740 struct mlx5_cache_entry *entry __rte_unused,
3743 struct mlx5_dev_ctx_shared *sh = list->ctx;
3744 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3745 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3746 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3747 struct mlx5dv_dr_domain *domain;
3751 /* Register new port id action resource. */
3752 cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3754 rte_flow_error_set(ctx->error, ENOMEM,
3755 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3756 "cannot allocate push_vlan action cache memory");
3760 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3761 domain = sh->fdb_domain;
3762 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3763 domain = sh->rx_domain;
3765 domain = sh->tx_domain;
3766 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3769 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3770 rte_flow_error_set(ctx->error, ENOMEM,
3771 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3772 "cannot create push vlan action");
3776 return &cache->entry;
3780 * Find existing push vlan resource or create and register a new one.
3782 * @param [in, out] dev
3783 * Pointer to rte_eth_dev structure.
3784 * @param[in, out] resource
3785 * Pointer to port ID action resource.
3786 * @parm[in, out] dev_flow
3787 * Pointer to the dev_flow.
3789 * pointer to error structure.
3792 * 0 on success otherwise -errno and errno is set.
3795 flow_dv_push_vlan_action_resource_register
3796 (struct rte_eth_dev *dev,
3797 struct mlx5_flow_dv_push_vlan_action_resource *resource,
3798 struct mlx5_flow *dev_flow,
3799 struct rte_flow_error *error)
3801 struct mlx5_priv *priv = dev->data->dev_private;
3802 struct mlx5_flow_dv_push_vlan_action_resource *cache;
3803 struct mlx5_cache_entry *entry;
3804 struct mlx5_flow_cb_ctx ctx = {
3809 entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3812 cache = container_of(entry, typeof(*cache), entry);
3814 dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3815 dev_flow->dv.push_vlan_res = cache;
3820 * Get the size of specific rte_flow_item_type hdr size
3822 * @param[in] item_type
3823 * Tested rte_flow_item_type.
3826 * sizeof struct item_type, 0 if void or irrelevant.
3829 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3833 switch (item_type) {
3834 case RTE_FLOW_ITEM_TYPE_ETH:
3835 retval = sizeof(struct rte_ether_hdr);
3837 case RTE_FLOW_ITEM_TYPE_VLAN:
3838 retval = sizeof(struct rte_vlan_hdr);
3840 case RTE_FLOW_ITEM_TYPE_IPV4:
3841 retval = sizeof(struct rte_ipv4_hdr);
3843 case RTE_FLOW_ITEM_TYPE_IPV6:
3844 retval = sizeof(struct rte_ipv6_hdr);
3846 case RTE_FLOW_ITEM_TYPE_UDP:
3847 retval = sizeof(struct rte_udp_hdr);
3849 case RTE_FLOW_ITEM_TYPE_TCP:
3850 retval = sizeof(struct rte_tcp_hdr);
3852 case RTE_FLOW_ITEM_TYPE_VXLAN:
3853 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3854 retval = sizeof(struct rte_vxlan_hdr);
3856 case RTE_FLOW_ITEM_TYPE_GRE:
3857 case RTE_FLOW_ITEM_TYPE_NVGRE:
3858 retval = sizeof(struct rte_gre_hdr);
3860 case RTE_FLOW_ITEM_TYPE_MPLS:
3861 retval = sizeof(struct rte_mpls_hdr);
3863 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3871 #define MLX5_ENCAP_IPV4_VERSION 0x40
3872 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
3873 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
3874 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
3875 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
3876 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
3877 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
3880 * Convert the encap action data from list of rte_flow_item to raw buffer
3883 * Pointer to rte_flow_item objects list.
3885 * Pointer to the output buffer.
3887 * Pointer to the output buffer size.
3889 * Pointer to the error structure.
3892 * 0 on success, a negative errno value otherwise and rte_errno is set.
3895 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3896 size_t *size, struct rte_flow_error *error)
3898 struct rte_ether_hdr *eth = NULL;
3899 struct rte_vlan_hdr *vlan = NULL;
3900 struct rte_ipv4_hdr *ipv4 = NULL;
3901 struct rte_ipv6_hdr *ipv6 = NULL;
3902 struct rte_udp_hdr *udp = NULL;
3903 struct rte_vxlan_hdr *vxlan = NULL;
3904 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3905 struct rte_gre_hdr *gre = NULL;
3907 size_t temp_size = 0;
3910 return rte_flow_error_set(error, EINVAL,
3911 RTE_FLOW_ERROR_TYPE_ACTION,
3912 NULL, "invalid empty data");
3913 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3914 len = flow_dv_get_item_hdr_len(items->type);
3915 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3916 return rte_flow_error_set(error, EINVAL,
3917 RTE_FLOW_ERROR_TYPE_ACTION,
3918 (void *)items->type,
3919 "items total size is too big"
3920 " for encap action");
3921 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3922 switch (items->type) {
3923 case RTE_FLOW_ITEM_TYPE_ETH:
3924 eth = (struct rte_ether_hdr *)&buf[temp_size];
3926 case RTE_FLOW_ITEM_TYPE_VLAN:
3927 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3929 return rte_flow_error_set(error, EINVAL,
3930 RTE_FLOW_ERROR_TYPE_ACTION,
3931 (void *)items->type,
3932 "eth header not found");
3933 if (!eth->ether_type)
3934 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3936 case RTE_FLOW_ITEM_TYPE_IPV4:
3937 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3939 return rte_flow_error_set(error, EINVAL,
3940 RTE_FLOW_ERROR_TYPE_ACTION,
3941 (void *)items->type,
3942 "neither eth nor vlan"
3944 if (vlan && !vlan->eth_proto)
3945 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3946 else if (eth && !eth->ether_type)
3947 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3948 if (!ipv4->version_ihl)
3949 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3950 MLX5_ENCAP_IPV4_IHL_MIN;
3951 if (!ipv4->time_to_live)
3952 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3954 case RTE_FLOW_ITEM_TYPE_IPV6:
3955 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3957 return rte_flow_error_set(error, EINVAL,
3958 RTE_FLOW_ERROR_TYPE_ACTION,
3959 (void *)items->type,
3960 "neither eth nor vlan"
3962 if (vlan && !vlan->eth_proto)
3963 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3964 else if (eth && !eth->ether_type)
3965 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3966 if (!ipv6->vtc_flow)
3968 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3969 if (!ipv6->hop_limits)
3970 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3972 case RTE_FLOW_ITEM_TYPE_UDP:
3973 udp = (struct rte_udp_hdr *)&buf[temp_size];
3975 return rte_flow_error_set(error, EINVAL,
3976 RTE_FLOW_ERROR_TYPE_ACTION,
3977 (void *)items->type,
3978 "ip header not found");
3979 if (ipv4 && !ipv4->next_proto_id)
3980 ipv4->next_proto_id = IPPROTO_UDP;
3981 else if (ipv6 && !ipv6->proto)
3982 ipv6->proto = IPPROTO_UDP;
3984 case RTE_FLOW_ITEM_TYPE_VXLAN:
3985 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3987 return rte_flow_error_set(error, EINVAL,
3988 RTE_FLOW_ERROR_TYPE_ACTION,
3989 (void *)items->type,
3990 "udp header not found");
3992 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3993 if (!vxlan->vx_flags)
3995 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3997 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3998 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4000 return rte_flow_error_set(error, EINVAL,
4001 RTE_FLOW_ERROR_TYPE_ACTION,
4002 (void *)items->type,
4003 "udp header not found");
4004 if (!vxlan_gpe->proto)
4005 return rte_flow_error_set(error, EINVAL,
4006 RTE_FLOW_ERROR_TYPE_ACTION,
4007 (void *)items->type,
4008 "next protocol not found");
4011 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4012 if (!vxlan_gpe->vx_flags)
4013 vxlan_gpe->vx_flags =
4014 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4016 case RTE_FLOW_ITEM_TYPE_GRE:
4017 case RTE_FLOW_ITEM_TYPE_NVGRE:
4018 gre = (struct rte_gre_hdr *)&buf[temp_size];
4020 return rte_flow_error_set(error, EINVAL,
4021 RTE_FLOW_ERROR_TYPE_ACTION,
4022 (void *)items->type,
4023 "next protocol not found");
4025 return rte_flow_error_set(error, EINVAL,
4026 RTE_FLOW_ERROR_TYPE_ACTION,
4027 (void *)items->type,
4028 "ip header not found");
4029 if (ipv4 && !ipv4->next_proto_id)
4030 ipv4->next_proto_id = IPPROTO_GRE;
4031 else if (ipv6 && !ipv6->proto)
4032 ipv6->proto = IPPROTO_GRE;
4034 case RTE_FLOW_ITEM_TYPE_VOID:
4037 return rte_flow_error_set(error, EINVAL,
4038 RTE_FLOW_ERROR_TYPE_ACTION,
4039 (void *)items->type,
4040 "unsupported item type");
4050 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4052 struct rte_ether_hdr *eth = NULL;
4053 struct rte_vlan_hdr *vlan = NULL;
4054 struct rte_ipv6_hdr *ipv6 = NULL;
4055 struct rte_udp_hdr *udp = NULL;
4059 eth = (struct rte_ether_hdr *)data;
4060 next_hdr = (char *)(eth + 1);
4061 proto = RTE_BE16(eth->ether_type);
4064 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4065 vlan = (struct rte_vlan_hdr *)next_hdr;
4066 proto = RTE_BE16(vlan->eth_proto);
4067 next_hdr += sizeof(struct rte_vlan_hdr);
4070 /* HW calculates IPv4 csum. no need to proceed */
4071 if (proto == RTE_ETHER_TYPE_IPV4)
4074 /* non IPv4/IPv6 header. not supported */
4075 if (proto != RTE_ETHER_TYPE_IPV6) {
4076 return rte_flow_error_set(error, ENOTSUP,
4077 RTE_FLOW_ERROR_TYPE_ACTION,
4078 NULL, "Cannot offload non IPv4/IPv6");
4081 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4083 /* ignore non UDP */
4084 if (ipv6->proto != IPPROTO_UDP)
4087 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4088 udp->dgram_cksum = 0;
4094 * Convert L2 encap action to DV specification.
4097 * Pointer to rte_eth_dev structure.
4099 * Pointer to action structure.
4100 * @param[in, out] dev_flow
4101 * Pointer to the mlx5_flow.
4102 * @param[in] transfer
4103 * Mark if the flow is E-Switch flow.
4105 * Pointer to the error structure.
4108 * 0 on success, a negative errno value otherwise and rte_errno is set.
4111 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4112 const struct rte_flow_action *action,
4113 struct mlx5_flow *dev_flow,
4115 struct rte_flow_error *error)
4117 const struct rte_flow_item *encap_data;
4118 const struct rte_flow_action_raw_encap *raw_encap_data;
4119 struct mlx5_flow_dv_encap_decap_resource res = {
4121 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4122 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4123 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4126 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4128 (const struct rte_flow_action_raw_encap *)action->conf;
4129 res.size = raw_encap_data->size;
4130 memcpy(res.buf, raw_encap_data->data, res.size);
4132 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4134 ((const struct rte_flow_action_vxlan_encap *)
4135 action->conf)->definition;
4138 ((const struct rte_flow_action_nvgre_encap *)
4139 action->conf)->definition;
4140 if (flow_dv_convert_encap_data(encap_data, res.buf,
4144 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4146 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4147 return rte_flow_error_set(error, EINVAL,
4148 RTE_FLOW_ERROR_TYPE_ACTION,
4149 NULL, "can't create L2 encap action");
4154 * Convert L2 decap action to DV specification.
4157 * Pointer to rte_eth_dev structure.
4158 * @param[in, out] dev_flow
4159 * Pointer to the mlx5_flow.
4160 * @param[in] transfer
4161 * Mark if the flow is E-Switch flow.
4163 * Pointer to the error structure.
4166 * 0 on success, a negative errno value otherwise and rte_errno is set.
4169 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4170 struct mlx5_flow *dev_flow,
4172 struct rte_flow_error *error)
4174 struct mlx5_flow_dv_encap_decap_resource res = {
4177 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4178 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4179 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4182 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4183 return rte_flow_error_set(error, EINVAL,
4184 RTE_FLOW_ERROR_TYPE_ACTION,
4185 NULL, "can't create L2 decap action");
4190 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4193 * Pointer to rte_eth_dev structure.
4195 * Pointer to action structure.
4196 * @param[in, out] dev_flow
4197 * Pointer to the mlx5_flow.
4199 * Pointer to the flow attributes.
4201 * Pointer to the error structure.
4204 * 0 on success, a negative errno value otherwise and rte_errno is set.
4207 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4208 const struct rte_flow_action *action,
4209 struct mlx5_flow *dev_flow,
4210 const struct rte_flow_attr *attr,
4211 struct rte_flow_error *error)
4213 const struct rte_flow_action_raw_encap *encap_data;
4214 struct mlx5_flow_dv_encap_decap_resource res;
4216 memset(&res, 0, sizeof(res));
4217 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4218 res.size = encap_data->size;
4219 memcpy(res.buf, encap_data->data, res.size);
4220 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4221 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4222 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4224 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4226 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4227 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4228 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4229 return rte_flow_error_set(error, EINVAL,
4230 RTE_FLOW_ERROR_TYPE_ACTION,
4231 NULL, "can't create encap action");
4236 * Create action push VLAN.
4239 * Pointer to rte_eth_dev structure.
4241 * Pointer to the flow attributes.
4243 * Pointer to the vlan to push to the Ethernet header.
4244 * @param[in, out] dev_flow
4245 * Pointer to the mlx5_flow.
4247 * Pointer to the error structure.
4250 * 0 on success, a negative errno value otherwise and rte_errno is set.
4253 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4254 const struct rte_flow_attr *attr,
4255 const struct rte_vlan_hdr *vlan,
4256 struct mlx5_flow *dev_flow,
4257 struct rte_flow_error *error)
4259 struct mlx5_flow_dv_push_vlan_action_resource res;
4261 memset(&res, 0, sizeof(res));
4263 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4266 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4268 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4269 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4270 return flow_dv_push_vlan_action_resource_register
4271 (dev, &res, dev_flow, error);
4275 * Validate the modify-header actions.
4277 * @param[in] action_flags
4278 * Holds the actions detected until now.
4280 * Pointer to the modify action.
4282 * Pointer to error structure.
4285 * 0 on success, a negative errno value otherwise and rte_errno is set.
4288 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4289 const struct rte_flow_action *action,
4290 struct rte_flow_error *error)
4292 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4293 return rte_flow_error_set(error, EINVAL,
4294 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4295 NULL, "action configuration not set");
4296 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4297 return rte_flow_error_set(error, EINVAL,
4298 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4299 "can't have encap action before"
4305 * Validate the modify-header MAC address actions.
4307 * @param[in] action_flags
4308 * Holds the actions detected until now.
4310 * Pointer to the modify action.
4311 * @param[in] item_flags
4312 * Holds the items detected.
4314 * Pointer to error structure.
4317 * 0 on success, a negative errno value otherwise and rte_errno is set.
4320 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4321 const struct rte_flow_action *action,
4322 const uint64_t item_flags,
4323 struct rte_flow_error *error)
4327 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4329 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4330 return rte_flow_error_set(error, EINVAL,
4331 RTE_FLOW_ERROR_TYPE_ACTION,
4333 "no L2 item in pattern");
4339 * Validate the modify-header IPv4 address actions.
4341 * @param[in] action_flags
4342 * Holds the actions detected until now.
4344 * Pointer to the modify action.
4345 * @param[in] item_flags
4346 * Holds the items detected.
4348 * Pointer to error structure.
4351 * 0 on success, a negative errno value otherwise and rte_errno is set.
4354 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4355 const struct rte_flow_action *action,
4356 const uint64_t item_flags,
4357 struct rte_flow_error *error)
4362 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4364 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4365 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4366 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4367 if (!(item_flags & layer))
4368 return rte_flow_error_set(error, EINVAL,
4369 RTE_FLOW_ERROR_TYPE_ACTION,
4371 "no ipv4 item in pattern");
4377 * Validate the modify-header IPv6 address actions.
4379 * @param[in] action_flags
4380 * Holds the actions detected until now.
4382 * Pointer to the modify action.
4383 * @param[in] item_flags
4384 * Holds the items detected.
4386 * Pointer to error structure.
4389 * 0 on success, a negative errno value otherwise and rte_errno is set.
4392 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4393 const struct rte_flow_action *action,
4394 const uint64_t item_flags,
4395 struct rte_flow_error *error)
4400 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4402 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4403 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4404 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4405 if (!(item_flags & layer))
4406 return rte_flow_error_set(error, EINVAL,
4407 RTE_FLOW_ERROR_TYPE_ACTION,
4409 "no ipv6 item in pattern");
4415 * Validate the modify-header TP actions.
4417 * @param[in] action_flags
4418 * Holds the actions detected until now.
4420 * Pointer to the modify action.
4421 * @param[in] item_flags
4422 * Holds the items detected.
4424 * Pointer to error structure.
4427 * 0 on success, a negative errno value otherwise and rte_errno is set.
4430 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4431 const struct rte_flow_action *action,
4432 const uint64_t item_flags,
4433 struct rte_flow_error *error)
4438 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4440 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4441 MLX5_FLOW_LAYER_INNER_L4 :
4442 MLX5_FLOW_LAYER_OUTER_L4;
4443 if (!(item_flags & layer))
4444 return rte_flow_error_set(error, EINVAL,
4445 RTE_FLOW_ERROR_TYPE_ACTION,
4446 NULL, "no transport layer "
4453 * Validate the modify-header actions of increment/decrement
4454 * TCP Sequence-number.
4456 * @param[in] action_flags
4457 * Holds the actions detected until now.
4459 * Pointer to the modify action.
4460 * @param[in] item_flags
4461 * Holds the items detected.
4463 * Pointer to error structure.
4466 * 0 on success, a negative errno value otherwise and rte_errno is set.
4469 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4470 const struct rte_flow_action *action,
4471 const uint64_t item_flags,
4472 struct rte_flow_error *error)
4477 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4479 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4480 MLX5_FLOW_LAYER_INNER_L4_TCP :
4481 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4482 if (!(item_flags & layer))
4483 return rte_flow_error_set(error, EINVAL,
4484 RTE_FLOW_ERROR_TYPE_ACTION,
4485 NULL, "no TCP item in"
4487 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4488 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4489 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4490 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4491 return rte_flow_error_set(error, EINVAL,
4492 RTE_FLOW_ERROR_TYPE_ACTION,
4494 "cannot decrease and increase"
4495 " TCP sequence number"
4496 " at the same time");
4502 * Validate the modify-header actions of increment/decrement
4503 * TCP Acknowledgment number.
4505 * @param[in] action_flags
4506 * Holds the actions detected until now.
4508 * Pointer to the modify action.
4509 * @param[in] item_flags
4510 * Holds the items detected.
4512 * Pointer to error structure.
4515 * 0 on success, a negative errno value otherwise and rte_errno is set.
4518 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4519 const struct rte_flow_action *action,
4520 const uint64_t item_flags,
4521 struct rte_flow_error *error)
4526 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4528 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4529 MLX5_FLOW_LAYER_INNER_L4_TCP :
4530 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4531 if (!(item_flags & layer))
4532 return rte_flow_error_set(error, EINVAL,
4533 RTE_FLOW_ERROR_TYPE_ACTION,
4534 NULL, "no TCP item in"
4536 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4537 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4538 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4539 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4540 return rte_flow_error_set(error, EINVAL,
4541 RTE_FLOW_ERROR_TYPE_ACTION,
4543 "cannot decrease and increase"
4544 " TCP acknowledgment number"
4545 " at the same time");
4551 * Validate the modify-header TTL actions.
4553 * @param[in] action_flags
4554 * Holds the actions detected until now.
4556 * Pointer to the modify action.
4557 * @param[in] item_flags
4558 * Holds the items detected.
4560 * Pointer to error structure.
4563 * 0 on success, a negative errno value otherwise and rte_errno is set.
4566 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4567 const struct rte_flow_action *action,
4568 const uint64_t item_flags,
4569 struct rte_flow_error *error)
4574 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4576 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4577 MLX5_FLOW_LAYER_INNER_L3 :
4578 MLX5_FLOW_LAYER_OUTER_L3;
4579 if (!(item_flags & layer))
4580 return rte_flow_error_set(error, EINVAL,
4581 RTE_FLOW_ERROR_TYPE_ACTION,
4583 "no IP protocol in pattern");
4589 * Validate the generic modify field actions.
4591 * Pointer to the rte_eth_dev structure.
4592 * @param[in] action_flags
4593 * Holds the actions detected until now.
4595 * Pointer to the modify action.
4597 * Pointer to the flow attributes.
4599 * Pointer to error structure.
4602 * Number of header fields to modify (0 or more) on success,
4603 * a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4607 const uint64_t action_flags,
4608 const struct rte_flow_action *action,
4609 const struct rte_flow_attr *attr,
4610 struct rte_flow_error *error)
4613 struct mlx5_priv *priv = dev->data->dev_private;
4614 struct mlx5_dev_config *config = &priv->config;
4615 const struct rte_flow_action_modify_field *action_modify_field =
4617 uint32_t dst_width =
4618 mlx5_flow_item_field_width(action_modify_field->dst.field);
4619 uint32_t src_width =
4620 mlx5_flow_item_field_width(action_modify_field->src.field);
4622 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4626 if (action_modify_field->width == 0)
4627 return rte_flow_error_set(error, EINVAL,
4628 RTE_FLOW_ERROR_TYPE_ACTION, action,
4629 "no bits are requested to be modified");
4630 else if (action_modify_field->width > dst_width ||
4631 action_modify_field->width > src_width)
4632 return rte_flow_error_set(error, EINVAL,
4633 RTE_FLOW_ERROR_TYPE_ACTION, action,
4634 "cannot modify more bits than"
4635 " the width of a field");
4636 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4637 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4638 if ((action_modify_field->dst.offset +
4639 action_modify_field->width > dst_width) ||
4640 (action_modify_field->dst.offset % 32))
4641 return rte_flow_error_set(error, EINVAL,
4642 RTE_FLOW_ERROR_TYPE_ACTION, action,
4643 "destination offset is too big"
4644 " or not aligned to 4 bytes");
4645 if (action_modify_field->dst.level &&
4646 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4647 return rte_flow_error_set(error, ENOTSUP,
4648 RTE_FLOW_ERROR_TYPE_ACTION, action,
4649 "inner header fields modification"
4650 " is not supported");
4652 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4653 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4654 if (!attr->transfer && !attr->group)
4655 return rte_flow_error_set(error, ENOTSUP,
4656 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657 "modify field action is not"
4658 " supported for group 0");
4659 if ((action_modify_field->src.offset +
4660 action_modify_field->width > src_width) ||
4661 (action_modify_field->src.offset % 32))
4662 return rte_flow_error_set(error, EINVAL,
4663 RTE_FLOW_ERROR_TYPE_ACTION, action,
4664 "source offset is too big"
4665 " or not aligned to 4 bytes");
4666 if (action_modify_field->src.level &&
4667 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4668 return rte_flow_error_set(error, ENOTSUP,
4669 RTE_FLOW_ERROR_TYPE_ACTION, action,
4670 "inner header fields modification"
4671 " is not supported");
4673 if (action_modify_field->dst.field ==
4674 action_modify_field->src.field)
4675 return rte_flow_error_set(error, EINVAL,
4676 RTE_FLOW_ERROR_TYPE_ACTION, action,
4677 "source and destination fields"
4678 " cannot be the same");
4679 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4680 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4681 return rte_flow_error_set(error, EINVAL,
4682 RTE_FLOW_ERROR_TYPE_ACTION, action,
4683 "immediate value or a pointer to it"
4684 " cannot be used as a destination");
4685 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4686 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4687 return rte_flow_error_set(error, ENOTSUP,
4688 RTE_FLOW_ERROR_TYPE_ACTION, action,
4689 "modifications of an arbitrary"
4690 " place in a packet is not supported");
4691 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4692 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4693 return rte_flow_error_set(error, ENOTSUP,
4694 RTE_FLOW_ERROR_TYPE_ACTION, action,
4695 "modifications of the 802.1Q Tag"
4696 " Identifier is not supported");
4697 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4698 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4699 return rte_flow_error_set(error, ENOTSUP,
4700 RTE_FLOW_ERROR_TYPE_ACTION, action,
4701 "modifications of the VXLAN Network"
4702 " Identifier is not supported");
4703 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4704 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4705 return rte_flow_error_set(error, ENOTSUP,
4706 RTE_FLOW_ERROR_TYPE_ACTION, action,
4707 "modifications of the GENEVE Network"
4708 " Identifier is not supported");
4709 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4710 action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4711 action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4712 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4713 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4714 !mlx5_flow_ext_mreg_supported(dev))
4715 return rte_flow_error_set(error, ENOTSUP,
4716 RTE_FLOW_ERROR_TYPE_ACTION, action,
4717 "cannot modify mark or metadata without"
4718 " extended metadata register support");
4720 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4721 return rte_flow_error_set(error, ENOTSUP,
4722 RTE_FLOW_ERROR_TYPE_ACTION, action,
4723 "add and sub operations"
4724 " are not supported");
4725 return (action_modify_field->width / 32) +
4726 !!(action_modify_field->width % 32);
4730 * Validate jump action.
4733 * Pointer to the jump action.
4734 * @param[in] action_flags
4735 * Holds the actions detected until now.
4736 * @param[in] attributes
4737 * Pointer to flow attributes
4738 * @param[in] external
4739 * Action belongs to flow rule created by request external to PMD.
4741 * Pointer to error structure.
4744 * 0 on success, a negative errno value otherwise and rte_errno is set.
4747 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4748 const struct mlx5_flow_tunnel *tunnel,
4749 const struct rte_flow_action *action,
4750 uint64_t action_flags,
4751 const struct rte_flow_attr *attributes,
4752 bool external, struct rte_flow_error *error)
4754 uint32_t target_group, table;
4756 struct flow_grp_info grp_info = {
4757 .external = !!external,
4758 .transfer = !!attributes->transfer,
4762 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4763 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4764 return rte_flow_error_set(error, EINVAL,
4765 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4766 "can't have 2 fate actions in"
4769 return rte_flow_error_set(error, EINVAL,
4770 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4771 NULL, "action configuration not set");
4773 ((const struct rte_flow_action_jump *)action->conf)->group;
4774 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4778 if (attributes->group == target_group &&
4779 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4780 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4781 return rte_flow_error_set(error, EINVAL,
4782 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4783 "target group must be other than"
4784 " the current flow group");
4789 * Validate the port_id action.
4792 * Pointer to rte_eth_dev structure.
4793 * @param[in] action_flags
4794 * Bit-fields that holds the actions detected until now.
4796 * Port_id RTE action structure.
4798 * Attributes of flow that includes this action.
4800 * Pointer to error structure.
4803 * 0 on success, a negative errno value otherwise and rte_errno is set.
4806 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4807 uint64_t action_flags,
4808 const struct rte_flow_action *action,
4809 const struct rte_flow_attr *attr,
4810 struct rte_flow_error *error)
4812 const struct rte_flow_action_port_id *port_id;
4813 struct mlx5_priv *act_priv;
4814 struct mlx5_priv *dev_priv;
4817 if (!attr->transfer)
4818 return rte_flow_error_set(error, ENOTSUP,
4819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4821 "port id action is valid in transfer"
4823 if (!action || !action->conf)
4824 return rte_flow_error_set(error, ENOTSUP,
4825 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4827 "port id action parameters must be"
4829 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4830 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4831 return rte_flow_error_set(error, EINVAL,
4832 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4833 "can have only one fate actions in"
4835 dev_priv = mlx5_dev_to_eswitch_info(dev);
4837 return rte_flow_error_set(error, rte_errno,
4838 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4840 "failed to obtain E-Switch info");
4841 port_id = action->conf;
4842 port = port_id->original ? dev->data->port_id : port_id->id;
4843 act_priv = mlx5_port_to_eswitch_info(port, false);
4845 return rte_flow_error_set
4847 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4848 "failed to obtain E-Switch port id for port");
4849 if (act_priv->domain_id != dev_priv->domain_id)
4850 return rte_flow_error_set
4852 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4853 "port does not belong to"
4854 " E-Switch being configured");
4859 * Get the maximum number of modify header actions.
4862 * Pointer to rte_eth_dev structure.
4864 * Flags bits to check if root level.
4867 * Max number of modify header actions device can support.
4869 static inline unsigned int
4870 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4874 * There's no way to directly query the max capacity from FW.
4875 * The maximal value on root table should be assumed to be supported.
4877 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4878 return MLX5_MAX_MODIFY_NUM;
4880 return MLX5_ROOT_TBL_MODIFY_NUM;
4884 * Validate the meter action.
4887 * Pointer to rte_eth_dev structure.
4888 * @param[in] action_flags
4889 * Bit-fields that holds the actions detected until now.
4891 * Pointer to the meter action.
4893 * Attributes of flow that includes this action.
4895 * Pointer to error structure.
4898 * 0 on success, a negative errno value otherwise and rte_ernno is set.
4901 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4902 uint64_t action_flags,
4903 const struct rte_flow_action *action,
4904 const struct rte_flow_attr *attr,
4906 struct rte_flow_error *error)
4908 struct mlx5_priv *priv = dev->data->dev_private;
4909 const struct rte_flow_action_meter *am = action->conf;
4910 struct mlx5_flow_meter_info *fm;
4911 struct mlx5_flow_meter_policy *mtr_policy;
4912 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
4915 return rte_flow_error_set(error, EINVAL,
4916 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4917 "meter action conf is NULL");
4919 if (action_flags & MLX5_FLOW_ACTION_METER)
4920 return rte_flow_error_set(error, ENOTSUP,
4921 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4922 "meter chaining not support");
4923 if (action_flags & MLX5_FLOW_ACTION_JUMP)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4926 "meter with jump not support");
4928 return rte_flow_error_set(error, ENOTSUP,
4929 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4931 "meter action not supported");
4932 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4934 return rte_flow_error_set(error, EINVAL,
4935 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4937 /* aso meter can always be shared by different domains */
4938 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
4939 !(fm->transfer == attr->transfer ||
4940 (!fm->ingress && !attr->ingress && attr->egress) ||
4941 (!fm->egress && !attr->egress && attr->ingress)))
4942 return rte_flow_error_set(error, EINVAL,
4943 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4944 "Flow attributes domain are either invalid "
4945 "or have a domain conflict with current "
4946 "meter attributes");
4947 if (fm->def_policy) {
4948 if (!((attr->transfer &&
4949 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
4951 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
4953 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
4954 return rte_flow_error_set(error, EINVAL,
4955 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4956 "Flow attributes domain "
4957 "have a conflict with current "
4958 "meter domain attributes");
4961 mtr_policy = mlx5_flow_meter_policy_find(dev,
4962 fm->policy_id, NULL);
4964 return rte_flow_error_set(error, EINVAL,
4965 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4966 "Invalid policy id for meter ");
4967 if (!((attr->transfer && mtr_policy->transfer) ||
4968 (attr->egress && mtr_policy->egress) ||
4969 (attr->ingress && mtr_policy->ingress)))
4970 return rte_flow_error_set(error, EINVAL,
4971 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4972 "Flow attributes domain "
4973 "have a conflict with current "
4974 "meter domain attributes");
4975 *def_policy = false;
4981 * Validate the age action.
4983 * @param[in] action_flags
4984 * Holds the actions detected until now.
4986 * Pointer to the age action.
4988 * Pointer to the Ethernet device structure.
4990 * Pointer to error structure.
4993 * 0 on success, a negative errno value otherwise and rte_errno is set.
4996 flow_dv_validate_action_age(uint64_t action_flags,
4997 const struct rte_flow_action *action,
4998 struct rte_eth_dev *dev,
4999 struct rte_flow_error *error)
5001 struct mlx5_priv *priv = dev->data->dev_private;
5002 const struct rte_flow_action_age *age = action->conf;
5004 if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
5005 !priv->sh->aso_age_mng))
5006 return rte_flow_error_set(error, ENOTSUP,
5007 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5009 "age action not supported");
5010 if (!(action->conf))
5011 return rte_flow_error_set(error, EINVAL,
5012 RTE_FLOW_ERROR_TYPE_ACTION, action,
5013 "configuration cannot be null");
5014 if (!(age->timeout))
5015 return rte_flow_error_set(error, EINVAL,
5016 RTE_FLOW_ERROR_TYPE_ACTION, action,
5017 "invalid timeout value 0");
5018 if (action_flags & MLX5_FLOW_ACTION_AGE)
5019 return rte_flow_error_set(error, EINVAL,
5020 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5021 "duplicate age actions set");
5026 * Validate the modify-header IPv4 DSCP actions.
5028 * @param[in] action_flags
5029 * Holds the actions detected until now.
5031 * Pointer to the modify action.
5032 * @param[in] item_flags
5033 * Holds the items detected.
5035 * Pointer to error structure.
5038 * 0 on success, a negative errno value otherwise and rte_errno is set.
5041 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5042 const struct rte_flow_action *action,
5043 const uint64_t item_flags,
5044 struct rte_flow_error *error)
5048 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5050 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5051 return rte_flow_error_set(error, EINVAL,
5052 RTE_FLOW_ERROR_TYPE_ACTION,
5054 "no ipv4 item in pattern");
5060 * Validate the modify-header IPv6 DSCP actions.
5062 * @param[in] action_flags
5063 * Holds the actions detected until now.
5065 * Pointer to the modify action.
5066 * @param[in] item_flags
5067 * Holds the items detected.
5069 * Pointer to error structure.
5072 * 0 on success, a negative errno value otherwise and rte_errno is set.
5075 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5076 const struct rte_flow_action *action,
5077 const uint64_t item_flags,
5078 struct rte_flow_error *error)
5082 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5084 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5085 return rte_flow_error_set(error, EINVAL,
5086 RTE_FLOW_ERROR_TYPE_ACTION,
5088 "no ipv6 item in pattern");
5094 * Match modify-header resource.
5097 * Pointer to the hash list.
5099 * Pointer to exist resource entry object.
5101 * Key of the new entry.
5103 * Pointer to new modify-header resource.
5106 * 0 on matching, non-zero otherwise.
5109 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5110 struct mlx5_hlist_entry *entry,
5111 uint64_t key __rte_unused, void *cb_ctx)
5113 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5114 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5115 struct mlx5_flow_dv_modify_hdr_resource *resource =
5116 container_of(entry, typeof(*resource), entry);
5117 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5119 key_len += ref->actions_num * sizeof(ref->actions[0]);
5120 return ref->actions_num != resource->actions_num ||
5121 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5124 struct mlx5_hlist_entry *
5125 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5128 struct mlx5_dev_ctx_shared *sh = list->ctx;
5129 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5130 struct mlx5dv_dr_domain *ns;
5131 struct mlx5_flow_dv_modify_hdr_resource *entry;
5132 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5134 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5135 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5137 entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5140 rte_flow_error_set(ctx->error, ENOMEM,
5141 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5142 "cannot allocate resource memory");
5145 rte_memcpy(&entry->ft_type,
5146 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5147 key_len + data_len);
5148 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5149 ns = sh->fdb_domain;
5150 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5154 ret = mlx5_flow_os_create_flow_action_modify_header
5155 (sh->ctx, ns, entry,
5156 data_len, &entry->action);
5159 rte_flow_error_set(ctx->error, ENOMEM,
5160 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5161 NULL, "cannot create modification action");
5164 return &entry->entry;
5168 * Validate the sample action.
5170 * @param[in, out] action_flags
5171 * Holds the actions detected until now.
5173 * Pointer to the sample action.
5175 * Pointer to the Ethernet device structure.
5177 * Attributes of flow that includes this action.
5178 * @param[in] item_flags
5179 * Holds the items detected.
5181 * Pointer to the RSS action.
5182 * @param[out] sample_rss
5183 * Pointer to the RSS action in sample action list.
5185 * Pointer to the COUNT action in sample action list.
5186 * @param[out] fdb_mirror_limit
5187 * Pointer to the FDB mirror limitation flag.
5189 * Pointer to error structure.
5192 * 0 on success, a negative errno value otherwise and rte_errno is set.
5195 flow_dv_validate_action_sample(uint64_t *action_flags,
5196 const struct rte_flow_action *action,
5197 struct rte_eth_dev *dev,
5198 const struct rte_flow_attr *attr,
5199 uint64_t item_flags,
5200 const struct rte_flow_action_rss *rss,
5201 const struct rte_flow_action_rss **sample_rss,
5202 const struct rte_flow_action_count **count,
5203 int *fdb_mirror_limit,
5204 struct rte_flow_error *error)
5206 struct mlx5_priv *priv = dev->data->dev_private;
5207 struct mlx5_dev_config *dev_conf = &priv->config;
5208 const struct rte_flow_action_sample *sample = action->conf;
5209 const struct rte_flow_action *act;
5210 uint64_t sub_action_flags = 0;
5211 uint16_t queue_index = 0xFFFF;
5216 return rte_flow_error_set(error, EINVAL,
5217 RTE_FLOW_ERROR_TYPE_ACTION, action,
5218 "configuration cannot be NULL");
5219 if (sample->ratio == 0)
5220 return rte_flow_error_set(error, EINVAL,
5221 RTE_FLOW_ERROR_TYPE_ACTION, action,
5222 "ratio value starts from 1");
5223 if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5224 return rte_flow_error_set(error, ENOTSUP,
5225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5227 "sample action not supported");
5228 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5229 return rte_flow_error_set(error, EINVAL,
5230 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5231 "Multiple sample actions not "
5233 if (*action_flags & MLX5_FLOW_ACTION_METER)
5234 return rte_flow_error_set(error, EINVAL,
5235 RTE_FLOW_ERROR_TYPE_ACTION, action,
5236 "wrong action order, meter should "
5237 "be after sample action");
5238 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5239 return rte_flow_error_set(error, EINVAL,
5240 RTE_FLOW_ERROR_TYPE_ACTION, action,
5241 "wrong action order, jump should "
5242 "be after sample action");
5243 act = sample->actions;
5244 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5245 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5246 return rte_flow_error_set(error, ENOTSUP,
5247 RTE_FLOW_ERROR_TYPE_ACTION,
5248 act, "too many actions");
5249 switch (act->type) {
5250 case RTE_FLOW_ACTION_TYPE_QUEUE:
5251 ret = mlx5_flow_validate_action_queue(act,
5257 queue_index = ((const struct rte_flow_action_queue *)
5258 (act->conf))->index;
5259 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5262 case RTE_FLOW_ACTION_TYPE_RSS:
5263 *sample_rss = act->conf;
5264 ret = mlx5_flow_validate_action_rss(act,
5271 if (rss && *sample_rss &&
5272 ((*sample_rss)->level != rss->level ||
5273 (*sample_rss)->types != rss->types))
5274 return rte_flow_error_set(error, ENOTSUP,
5275 RTE_FLOW_ERROR_TYPE_ACTION,
5277 "Can't use the different RSS types "
5278 "or level in the same flow");
5279 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5280 queue_index = (*sample_rss)->queue[0];
5281 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5284 case RTE_FLOW_ACTION_TYPE_MARK:
5285 ret = flow_dv_validate_action_mark(dev, act,
5290 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5291 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5292 MLX5_FLOW_ACTION_MARK_EXT;
5294 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5297 case RTE_FLOW_ACTION_TYPE_COUNT:
5298 ret = flow_dv_validate_action_count
5299 (dev, is_shared_action_count(act),
5300 *action_flags | sub_action_flags,
5305 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5306 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5309 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5310 ret = flow_dv_validate_action_port_id(dev,
5317 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5320 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5321 ret = flow_dv_validate_action_raw_encap_decap
5322 (dev, NULL, act->conf, attr, &sub_action_flags,
5323 &actions_n, action, item_flags, error);
5328 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5329 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5330 ret = flow_dv_validate_action_l2_encap(dev,
5336 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5340 return rte_flow_error_set(error, ENOTSUP,
5341 RTE_FLOW_ERROR_TYPE_ACTION,
5343 "Doesn't support optional "
5347 if (attr->ingress && !attr->transfer) {
5348 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5349 MLX5_FLOW_ACTION_RSS)))
5350 return rte_flow_error_set(error, EINVAL,
5351 RTE_FLOW_ERROR_TYPE_ACTION,
5353 "Ingress must has a dest "
5354 "QUEUE for Sample");
5355 } else if (attr->egress && !attr->transfer) {
5356 return rte_flow_error_set(error, ENOTSUP,
5357 RTE_FLOW_ERROR_TYPE_ACTION,
5359 "Sample Only support Ingress "
5361 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5362 MLX5_ASSERT(attr->transfer);
5363 if (sample->ratio > 1)
5364 return rte_flow_error_set(error, ENOTSUP,
5365 RTE_FLOW_ERROR_TYPE_ACTION,
5367 "E-Switch doesn't support "
5368 "any optional action "
5370 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5371 return rte_flow_error_set(error, ENOTSUP,
5372 RTE_FLOW_ERROR_TYPE_ACTION,
5374 "unsupported action QUEUE");
5375 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5376 return rte_flow_error_set(error, ENOTSUP,
5377 RTE_FLOW_ERROR_TYPE_ACTION,
5379 "unsupported action QUEUE");
5380 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5381 return rte_flow_error_set(error, EINVAL,
5382 RTE_FLOW_ERROR_TYPE_ACTION,
5384 "E-Switch must has a dest "
5385 "port for mirroring");
5386 if (!priv->config.hca_attr.reg_c_preserve &&
5387 priv->representor_id != -1)
5388 *fdb_mirror_limit = 1;
5390 /* Continue validation for Xcap actions.*/
5391 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5392 (queue_index == 0xFFFF ||
5393 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5394 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5395 MLX5_FLOW_XCAP_ACTIONS)
5396 return rte_flow_error_set(error, ENOTSUP,
5397 RTE_FLOW_ERROR_TYPE_ACTION,
5398 NULL, "encap and decap "
5399 "combination aren't "
5401 if (!attr->transfer && attr->ingress && (sub_action_flags &
5402 MLX5_FLOW_ACTION_ENCAP))
5403 return rte_flow_error_set(error, ENOTSUP,
5404 RTE_FLOW_ERROR_TYPE_ACTION,
5405 NULL, "encap is not supported"
5406 " for ingress traffic");
5412 * Find existing modify-header resource or create and register a new one.
5414 * @param dev[in, out]
5415 * Pointer to rte_eth_dev structure.
5416 * @param[in, out] resource
5417 * Pointer to modify-header resource.
5418 * @parm[in, out] dev_flow
5419 * Pointer to the dev_flow.
5421 * pointer to error structure.
5424 * 0 on success otherwise -errno and errno is set.
5427 flow_dv_modify_hdr_resource_register
5428 (struct rte_eth_dev *dev,
5429 struct mlx5_flow_dv_modify_hdr_resource *resource,
5430 struct mlx5_flow *dev_flow,
5431 struct rte_flow_error *error)
5433 struct mlx5_priv *priv = dev->data->dev_private;
5434 struct mlx5_dev_ctx_shared *sh = priv->sh;
5435 uint32_t key_len = sizeof(*resource) -
5436 offsetof(typeof(*resource), ft_type) +
5437 resource->actions_num * sizeof(resource->actions[0]);
5438 struct mlx5_hlist_entry *entry;
5439 struct mlx5_flow_cb_ctx ctx = {
5445 resource->flags = dev_flow->dv.group ? 0 :
5446 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5447 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5449 return rte_flow_error_set(error, EOVERFLOW,
5450 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5451 "too many modify header items");
5452 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5453 entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5456 resource = container_of(entry, typeof(*resource), entry);
5457 dev_flow->handle->dvh.modify_hdr = resource;
5462 * Get DV flow counter by index.
5465 * Pointer to the Ethernet device structure.
5467 * mlx5 flow counter index in the container.
5469 * mlx5 flow counter pool in the container.
5472 * Pointer to the counter, NULL otherwise.
5474 static struct mlx5_flow_counter *
5475 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5477 struct mlx5_flow_counter_pool **ppool)
5479 struct mlx5_priv *priv = dev->data->dev_private;
5480 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5481 struct mlx5_flow_counter_pool *pool;
5483 /* Decrease to original index and clear shared bit. */
5484 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5485 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5486 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5490 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5494 * Check the devx counter belongs to the pool.
5497 * Pointer to the counter pool.
5499 * The counter devx ID.
5502 * True if counter belongs to the pool, false otherwise.
5505 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5507 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5508 MLX5_COUNTERS_PER_POOL;
5510 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5516 * Get a pool by devx counter ID.
5519 * Pointer to the counter management.
5521 * The counter devx ID.
5524 * The counter pool pointer if exists, NULL otherwise,
5526 static struct mlx5_flow_counter_pool *
5527 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5530 struct mlx5_flow_counter_pool *pool = NULL;
5532 rte_spinlock_lock(&cmng->pool_update_sl);
5533 /* Check last used pool. */
5534 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5535 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5536 pool = cmng->pools[cmng->last_pool_idx];
5539 /* ID out of range means no suitable pool in the container. */
5540 if (id > cmng->max_id || id < cmng->min_id)
5543 * Find the pool from the end of the container, since mostly counter
5544 * ID is sequence increasing, and the last pool should be the needed
5549 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5551 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5557 rte_spinlock_unlock(&cmng->pool_update_sl);
5562 * Resize a counter container.
5565 * Pointer to the Ethernet device structure.
5568 * 0 on success, otherwise negative errno value and rte_errno is set.
5571 flow_dv_container_resize(struct rte_eth_dev *dev)
5573 struct mlx5_priv *priv = dev->data->dev_private;
5574 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5575 void *old_pools = cmng->pools;
5576 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5577 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5578 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5585 memcpy(pools, old_pools, cmng->n *
5586 sizeof(struct mlx5_flow_counter_pool *));
5588 cmng->pools = pools;
5590 mlx5_free(old_pools);
5595 * Query a devx flow counter.
5598 * Pointer to the Ethernet device structure.
5599 * @param[in] counter
5600 * Index to the flow counter.
5602 * The statistics value of packets.
5604 * The statistics value of bytes.
5607 * 0 on success, otherwise a negative errno value and rte_errno is set.
5610 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5613 struct mlx5_priv *priv = dev->data->dev_private;
5614 struct mlx5_flow_counter_pool *pool = NULL;
5615 struct mlx5_flow_counter *cnt;
5618 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5620 if (priv->sh->cmng.counter_fallback)
5621 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5622 0, pkts, bytes, 0, NULL, NULL, 0);
5623 rte_spinlock_lock(&pool->sl);
5628 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5629 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5630 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5632 rte_spinlock_unlock(&pool->sl);
5637 * Create and initialize a new counter pool.
5640 * Pointer to the Ethernet device structure.
5642 * The devX counter handle.
5644 * Whether the pool is for counter that was allocated for aging.
5645 * @param[in/out] cont_cur
5646 * Pointer to the container pointer, it will be update in pool resize.
5649 * The pool container pointer on success, NULL otherwise and rte_errno is set.
5651 static struct mlx5_flow_counter_pool *
5652 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5655 struct mlx5_priv *priv = dev->data->dev_private;
5656 struct mlx5_flow_counter_pool *pool;
5657 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5658 bool fallback = priv->sh->cmng.counter_fallback;
5659 uint32_t size = sizeof(*pool);
5661 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5662 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5663 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5669 pool->is_aged = !!age;
5670 pool->query_gen = 0;
5671 pool->min_dcs = dcs;
5672 rte_spinlock_init(&pool->sl);
5673 rte_spinlock_init(&pool->csl);
5674 TAILQ_INIT(&pool->counters[0]);
5675 TAILQ_INIT(&pool->counters[1]);
5676 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5677 rte_spinlock_lock(&cmng->pool_update_sl);
5678 pool->index = cmng->n_valid;
5679 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5681 rte_spinlock_unlock(&cmng->pool_update_sl);
5684 cmng->pools[pool->index] = pool;
5686 if (unlikely(fallback)) {
5687 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5689 if (base < cmng->min_id)
5690 cmng->min_id = base;
5691 if (base > cmng->max_id)
5692 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5693 cmng->last_pool_idx = pool->index;
5695 rte_spinlock_unlock(&cmng->pool_update_sl);
5700 * Prepare a new counter and/or a new counter pool.
5703 * Pointer to the Ethernet device structure.
5704 * @param[out] cnt_free
5705 * Where to put the pointer of a new counter.
5707 * Whether the pool is for counter that was allocated for aging.
5710 * The counter pool pointer and @p cnt_free is set on success,
5711 * NULL otherwise and rte_errno is set.
5713 static struct mlx5_flow_counter_pool *
5714 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5715 struct mlx5_flow_counter **cnt_free,
5718 struct mlx5_priv *priv = dev->data->dev_private;
5719 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5720 struct mlx5_flow_counter_pool *pool;
5721 struct mlx5_counters tmp_tq;
5722 struct mlx5_devx_obj *dcs = NULL;
5723 struct mlx5_flow_counter *cnt;
5724 enum mlx5_counter_type cnt_type =
5725 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5726 bool fallback = priv->sh->cmng.counter_fallback;
5730 /* bulk_bitmap must be 0 for single counter allocation. */
5731 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5734 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5736 pool = flow_dv_pool_create(dev, dcs, age);
5738 mlx5_devx_cmd_destroy(dcs);
5742 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5743 cnt = MLX5_POOL_GET_CNT(pool, i);
5745 cnt->dcs_when_free = dcs;
5749 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5751 rte_errno = ENODATA;
5754 pool = flow_dv_pool_create(dev, dcs, age);
5756 mlx5_devx_cmd_destroy(dcs);
5759 TAILQ_INIT(&tmp_tq);
5760 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5761 cnt = MLX5_POOL_GET_CNT(pool, i);
5763 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5765 rte_spinlock_lock(&cmng->csl[cnt_type]);
5766 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5767 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5768 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5769 (*cnt_free)->pool = pool;
5774 * Allocate a flow counter.
5777 * Pointer to the Ethernet device structure.
5779 * Whether the counter was allocated for aging.
5782 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5785 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5787 struct mlx5_priv *priv = dev->data->dev_private;
5788 struct mlx5_flow_counter_pool *pool = NULL;
5789 struct mlx5_flow_counter *cnt_free = NULL;
5790 bool fallback = priv->sh->cmng.counter_fallback;
5791 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5792 enum mlx5_counter_type cnt_type =
5793 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5796 if (!priv->config.devx) {
5797 rte_errno = ENOTSUP;
5800 /* Get free counters from container. */
5801 rte_spinlock_lock(&cmng->csl[cnt_type]);
5802 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5804 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5805 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5806 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5808 pool = cnt_free->pool;
5810 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5811 /* Create a DV counter action only in the first time usage. */
5812 if (!cnt_free->action) {
5814 struct mlx5_devx_obj *dcs;
5818 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5819 dcs = pool->min_dcs;
5822 dcs = cnt_free->dcs_when_free;
5824 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5831 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5832 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5833 /* Update the counter reset values. */
5834 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5837 if (!fallback && !priv->sh->cmng.query_thread_on)
5838 /* Start the asynchronous batch query by the host thread. */
5839 mlx5_set_query_alarm(priv->sh);
5841 * When the count action isn't shared (by ID), shared_info field is
5842 * used for indirect action API's refcnt.
5843 * When the counter action is not shared neither by ID nor by indirect
5844 * action API, shared info must be 1.
5846 cnt_free->shared_info.refcnt = 1;
5850 cnt_free->pool = pool;
5852 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5853 rte_spinlock_lock(&cmng->csl[cnt_type]);
5854 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5855 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5861 * Allocate a shared flow counter.
5864 * Pointer to the shared counter configuration.
5866 * Pointer to save the allocated counter index.
5869 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5873 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5875 struct mlx5_shared_counter_conf *conf = ctx;
5876 struct rte_eth_dev *dev = conf->dev;
5877 struct mlx5_flow_counter *cnt;
5879 data->dword = flow_dv_counter_alloc(dev, 0);
5880 data->dword |= MLX5_CNT_SHARED_OFFSET;
5881 cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5882 cnt->shared_info.id = conf->id;
5887 * Get a shared flow counter.
5890 * Pointer to the Ethernet device structure.
5892 * Counter identifier.
5895 * Index to flow counter on success, 0 otherwise and rte_errno is set.
5898 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5900 struct mlx5_priv *priv = dev->data->dev_private;
5901 struct mlx5_shared_counter_conf conf = {
5905 union mlx5_l3t_data data = {
5909 mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5910 flow_dv_counter_alloc_shared_cb, &conf);
5915 * Get age param from counter index.
5918 * Pointer to the Ethernet device structure.
5919 * @param[in] counter
5920 * Index to the counter handler.
5923 * The aging parameter specified for the counter index.
5925 static struct mlx5_age_param*
5926 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5929 struct mlx5_flow_counter *cnt;
5930 struct mlx5_flow_counter_pool *pool = NULL;
5932 flow_dv_counter_get_by_idx(dev, counter, &pool);
5933 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5934 cnt = MLX5_POOL_GET_CNT(pool, counter);
5935 return MLX5_CNT_TO_AGE(cnt);
5939 * Remove a flow counter from aged counter list.
5942 * Pointer to the Ethernet device structure.
5943 * @param[in] counter
5944 * Index to the counter handler.
5946 * Pointer to the counter handler.
5949 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5950 uint32_t counter, struct mlx5_flow_counter *cnt)
5952 struct mlx5_age_info *age_info;
5953 struct mlx5_age_param *age_param;
5954 struct mlx5_priv *priv = dev->data->dev_private;
5955 uint16_t expected = AGE_CANDIDATE;
5957 age_info = GET_PORT_AGE_INFO(priv);
5958 age_param = flow_dv_counter_idx_get_age(dev, counter);
5959 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5960 AGE_FREE, false, __ATOMIC_RELAXED,
5961 __ATOMIC_RELAXED)) {
5963 * We need the lock even it is age timeout,
5964 * since counter may still in process.
5966 rte_spinlock_lock(&age_info->aged_sl);
5967 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5968 rte_spinlock_unlock(&age_info->aged_sl);
5969 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5974 * Release a flow counter.
5977 * Pointer to the Ethernet device structure.
5978 * @param[in] counter
5979 * Index to the counter handler.
5982 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5984 struct mlx5_priv *priv = dev->data->dev_private;
5985 struct mlx5_flow_counter_pool *pool = NULL;
5986 struct mlx5_flow_counter *cnt;
5987 enum mlx5_counter_type cnt_type;
5991 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5994 * If the counter action is shared by ID, the l3t_clear_entry function
5995 * reduces its references counter. If after the reduction the action is
5996 * still referenced, the function returns here and does not release it.
5998 if (IS_LEGACY_SHARED_CNT(counter) &&
5999 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
6002 * If the counter action is shared by indirect action API, the atomic
6003 * function reduces its references counter. If after the reduction the
6004 * action is still referenced, the function returns here and does not
6006 * When the counter action is not shared neither by ID nor by indirect
6007 * action API, shared info is 1 before the reduction, so this condition
6008 * is failed and function doesn't return here.
6010 if (!IS_LEGACY_SHARED_CNT(counter) &&
6011 __atomic_sub_fetch(&cnt->shared_info.refcnt, 1, __ATOMIC_RELAXED))
6014 flow_dv_counter_remove_from_age(dev, counter, cnt);
6017 * Put the counter back to list to be updated in none fallback mode.
6018 * Currently, we are using two list alternately, while one is in query,
6019 * add the freed counter to the other list based on the pool query_gen
6020 * value. After query finishes, add counter the list to the global
6021 * container counter list. The list changes while query starts. In
6022 * this case, lock will not be needed as query callback and release
6023 * function both operate with the different list.
6025 if (!priv->sh->cmng.counter_fallback) {
6026 rte_spinlock_lock(&pool->csl);
6027 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6028 rte_spinlock_unlock(&pool->csl);
6030 cnt->dcs_when_free = cnt->dcs_when_active;
6031 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6032 MLX5_COUNTER_TYPE_ORIGIN;
6033 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6034 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6036 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6041 * Resize a meter id container.
6044 * Pointer to the Ethernet device structure.
6047 * 0 on success, otherwise negative errno value and rte_errno is set.
6050 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6052 struct mlx5_priv *priv = dev->data->dev_private;
6053 struct mlx5_aso_mtr_pools_mng *pools_mng =
6054 &priv->sh->mtrmng->pools_mng;
6055 void *old_pools = pools_mng->pools;
6056 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6057 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6058 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6065 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6070 memcpy(pools, old_pools, pools_mng->n *
6071 sizeof(struct mlx5_aso_mtr_pool *));
6072 pools_mng->n = resize;
6073 pools_mng->pools = pools;
6075 mlx5_free(old_pools);
6080 * Prepare a new meter and/or a new meter pool.
6083 * Pointer to the Ethernet device structure.
6084 * @param[out] mtr_free
6085 * Where to put the pointer of a new meter.g.
6088 * The meter pool pointer and @mtr_free is set on success,
6089 * NULL otherwise and rte_errno is set.
6091 static struct mlx5_aso_mtr_pool *
6092 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
6093 struct mlx5_aso_mtr **mtr_free)
6095 struct mlx5_priv *priv = dev->data->dev_private;
6096 struct mlx5_aso_mtr_pools_mng *pools_mng =
6097 &priv->sh->mtrmng->pools_mng;
6098 struct mlx5_aso_mtr_pool *pool = NULL;
6099 struct mlx5_devx_obj *dcs = NULL;
6101 uint32_t log_obj_size;
6103 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6104 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6105 priv->sh->pdn, log_obj_size);
6107 rte_errno = ENODATA;
6110 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6113 claim_zero(mlx5_devx_cmd_destroy(dcs));
6116 pool->devx_obj = dcs;
6117 pool->index = pools_mng->n_valid;
6118 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6120 claim_zero(mlx5_devx_cmd_destroy(dcs));
6123 pools_mng->pools[pool->index] = pool;
6124 pools_mng->n_valid++;
6125 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6126 pool->mtrs[i].offset = i;
6127 LIST_INSERT_HEAD(&pools_mng->meters,
6128 &pool->mtrs[i], next);
6130 pool->mtrs[0].offset = 0;
6131 *mtr_free = &pool->mtrs[0];
6136 * Release a flow meter into pool.
6139 * Pointer to the Ethernet device structure.
6140 * @param[in] mtr_idx
6141 * Index to aso flow meter.
6144 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6146 struct mlx5_priv *priv = dev->data->dev_private;
6147 struct mlx5_aso_mtr_pools_mng *pools_mng =
6148 &priv->sh->mtrmng->pools_mng;
6149 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6151 MLX5_ASSERT(aso_mtr);
6152 rte_spinlock_lock(&pools_mng->mtrsl);
6153 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6154 aso_mtr->state = ASO_METER_FREE;
6155 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6156 rte_spinlock_unlock(&pools_mng->mtrsl);
6160 * Allocate a aso flow meter.
6163 * Pointer to the Ethernet device structure.
6166 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6169 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6171 struct mlx5_priv *priv = dev->data->dev_private;
6172 struct mlx5_aso_mtr *mtr_free = NULL;
6173 struct mlx5_aso_mtr_pools_mng *pools_mng =
6174 &priv->sh->mtrmng->pools_mng;
6175 struct mlx5_aso_mtr_pool *pool;
6176 uint32_t mtr_idx = 0;
6178 if (!priv->config.devx) {
6179 rte_errno = ENOTSUP;
6182 /* Allocate the flow meter memory. */
6183 /* Get free meters from management. */
6184 rte_spinlock_lock(&pools_mng->mtrsl);
6185 mtr_free = LIST_FIRST(&pools_mng->meters);
6187 LIST_REMOVE(mtr_free, next);
6188 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6189 rte_spinlock_unlock(&pools_mng->mtrsl);
6192 mtr_free->state = ASO_METER_WAIT;
6193 rte_spinlock_unlock(&pools_mng->mtrsl);
6194 pool = container_of(mtr_free,
6195 struct mlx5_aso_mtr_pool,
6196 mtrs[mtr_free->offset]);
6197 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6198 if (!mtr_free->fm.meter_action) {
6199 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6200 struct rte_flow_error error;
6203 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6204 mtr_free->fm.meter_action =
6205 mlx5_glue->dv_create_flow_action_aso
6206 (priv->sh->rx_domain,
6207 pool->devx_obj->obj,
6209 (1 << MLX5_FLOW_COLOR_GREEN),
6211 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6212 if (!mtr_free->fm.meter_action) {
6213 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6221 * Verify the @p attributes will be correctly understood by the NIC and store
6222 * them in the @p flow if everything is correct.
6225 * Pointer to dev struct.
6226 * @param[in] attributes
6227 * Pointer to flow attributes
6228 * @param[in] external
6229 * This flow rule is created by request external to PMD.
6231 * Pointer to error structure.
6234 * - 0 on success and non root table.
6235 * - 1 on success and root table.
6236 * - a negative errno value otherwise and rte_errno is set.
6239 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6240 const struct mlx5_flow_tunnel *tunnel,
6241 const struct rte_flow_attr *attributes,
6242 const struct flow_grp_info *grp_info,
6243 struct rte_flow_error *error)
6245 struct mlx5_priv *priv = dev->data->dev_private;
6246 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6249 #ifndef HAVE_MLX5DV_DR
6250 RTE_SET_USED(tunnel);
6251 RTE_SET_USED(grp_info);
6252 if (attributes->group)
6253 return rte_flow_error_set(error, ENOTSUP,
6254 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6256 "groups are not supported");
6260 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6265 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6267 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6268 attributes->priority > lowest_priority)
6269 return rte_flow_error_set(error, ENOTSUP,
6270 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6272 "priority out of range");
6273 if (attributes->transfer) {
6274 if (!priv->config.dv_esw_en)
6275 return rte_flow_error_set
6277 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6278 "E-Switch dr is not supported");
6279 if (!(priv->representor || priv->master))
6280 return rte_flow_error_set
6281 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6282 NULL, "E-Switch configuration can only be"
6283 " done by a master or a representor device");
6284 if (attributes->egress)
6285 return rte_flow_error_set
6287 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6288 "egress is not supported");
6290 if (!(attributes->egress ^ attributes->ingress))
6291 return rte_flow_error_set(error, ENOTSUP,
6292 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6293 "must specify exactly one of "
6294 "ingress or egress");
6299 mlx5_flow_locate_proto_l3(const struct rte_flow_item **head,
6300 const struct rte_flow_item *end)
6302 const struct rte_flow_item *item = *head;
6303 uint16_t l3_protocol;
6305 for (; item != end; item++) {
6306 switch (item->type) {
6309 case RTE_FLOW_ITEM_TYPE_IPV4:
6310 l3_protocol = RTE_ETHER_TYPE_IPV4;
6312 case RTE_FLOW_ITEM_TYPE_IPV6:
6313 l3_protocol = RTE_ETHER_TYPE_IPV6;
6315 case RTE_FLOW_ITEM_TYPE_ETH:
6316 if (item->mask && item->spec) {
6317 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_eth,
6320 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6321 l3_protocol == RTE_ETHER_TYPE_IPV6)
6325 case RTE_FLOW_ITEM_TYPE_VLAN:
6326 if (item->mask && item->spec) {
6327 MLX5_ETHER_TYPE_FROM_HEADER(rte_flow_item_vlan,
6330 if (l3_protocol == RTE_ETHER_TYPE_IPV4 ||
6331 l3_protocol == RTE_ETHER_TYPE_IPV6)
6344 mlx5_flow_locate_proto_l4(const struct rte_flow_item **head,
6345 const struct rte_flow_item *end)
6347 const struct rte_flow_item *item = *head;
6348 uint8_t l4_protocol;
6350 for (; item != end; item++) {
6351 switch (item->type) {
6354 case RTE_FLOW_ITEM_TYPE_TCP:
6355 l4_protocol = IPPROTO_TCP;
6357 case RTE_FLOW_ITEM_TYPE_UDP:
6358 l4_protocol = IPPROTO_UDP;
6360 case RTE_FLOW_ITEM_TYPE_IPV4:
6361 if (item->mask && item->spec) {
6362 const struct rte_flow_item_ipv4 *mask, *spec;
6364 mask = (typeof(mask))item->mask;
6365 spec = (typeof(spec))item->spec;
6366 l4_protocol = mask->hdr.next_proto_id &
6367 spec->hdr.next_proto_id;
6368 if (l4_protocol == IPPROTO_TCP ||
6369 l4_protocol == IPPROTO_UDP)
6373 case RTE_FLOW_ITEM_TYPE_IPV6:
6374 if (item->mask && item->spec) {
6375 const struct rte_flow_item_ipv6 *mask, *spec;
6376 mask = (typeof(mask))item->mask;
6377 spec = (typeof(spec))item->spec;
6378 l4_protocol = mask->hdr.proto & spec->hdr.proto;
6379 if (l4_protocol == IPPROTO_TCP ||
6380 l4_protocol == IPPROTO_UDP)
6393 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6394 const struct rte_flow_item *rule_items,
6395 const struct rte_flow_item *integrity_item,
6396 struct rte_flow_error *error)
6398 struct mlx5_priv *priv = dev->data->dev_private;
6399 const struct rte_flow_item *tunnel_item, *end_item, *item = rule_items;
6400 const struct rte_flow_item_integrity *mask = (typeof(mask))
6401 integrity_item->mask;
6402 const struct rte_flow_item_integrity *spec = (typeof(spec))
6403 integrity_item->spec;
6406 if (!priv->config.hca_attr.pkt_integrity_match)
6407 return rte_flow_error_set(error, ENOTSUP,
6408 RTE_FLOW_ERROR_TYPE_ITEM,
6410 "packet integrity integrity_item not supported");
6412 mask = &rte_flow_item_integrity_mask;
6413 if (!mlx5_validate_integrity_item(mask))
6414 return rte_flow_error_set(error, ENOTSUP,
6415 RTE_FLOW_ERROR_TYPE_ITEM,
6417 "unsupported integrity filter");
6418 tunnel_item = mlx5_flow_find_tunnel_item(rule_items);
6419 if (spec->level > 1) {
6421 return rte_flow_error_set(error, ENOTSUP,
6422 RTE_FLOW_ERROR_TYPE_ITEM,
6424 "missing tunnel item");
6426 end_item = mlx5_find_end_item(tunnel_item);
6428 end_item = tunnel_item ? tunnel_item :
6429 mlx5_find_end_item(integrity_item);
6431 if (mask->l3_ok || mask->ipv4_csum_ok) {
6432 protocol = mlx5_flow_locate_proto_l3(&item, end_item);
6434 return rte_flow_error_set(error, EINVAL,
6435 RTE_FLOW_ERROR_TYPE_ITEM,
6437 "missing L3 protocol");
6439 if (mask->l4_ok || mask->l4_csum_ok) {
6440 protocol = mlx5_flow_locate_proto_l4(&item, end_item);
6442 return rte_flow_error_set(error, EINVAL,
6443 RTE_FLOW_ERROR_TYPE_ITEM,
6445 "missing L4 protocol");
6451 * Internal validation function. For validating both actions and items.
6454 * Pointer to the rte_eth_dev structure.
6456 * Pointer to the flow attributes.
6458 * Pointer to the list of items.
6459 * @param[in] actions
6460 * Pointer to the list of actions.
6461 * @param[in] external
6462 * This flow rule is created by request external to PMD.
6463 * @param[in] hairpin
6464 * Number of hairpin TX actions, 0 means classic flow.
6466 * Pointer to the error structure.
6469 * 0 on success, a negative errno value otherwise and rte_errno is set.
6472 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6473 const struct rte_flow_item items[],
6474 const struct rte_flow_action actions[],
6475 bool external, int hairpin, struct rte_flow_error *error)
6478 uint64_t action_flags = 0;
6479 uint64_t item_flags = 0;
6480 uint64_t last_item = 0;
6481 uint8_t next_protocol = 0xff;
6482 uint16_t ether_type = 0;
6484 uint8_t item_ipv6_proto = 0;
6485 int fdb_mirror_limit = 0;
6486 int modify_after_mirror = 0;
6487 const struct rte_flow_item *geneve_item = NULL;
6488 const struct rte_flow_item *gre_item = NULL;
6489 const struct rte_flow_item *gtp_item = NULL;
6490 const struct rte_flow_action_raw_decap *decap;
6491 const struct rte_flow_action_raw_encap *encap;
6492 const struct rte_flow_action_rss *rss = NULL;
6493 const struct rte_flow_action_rss *sample_rss = NULL;
6494 const struct rte_flow_action_count *sample_count = NULL;
6495 const struct rte_flow_item_tcp nic_tcp_mask = {
6498 .src_port = RTE_BE16(UINT16_MAX),
6499 .dst_port = RTE_BE16(UINT16_MAX),
6502 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6505 "\xff\xff\xff\xff\xff\xff\xff\xff"
6506 "\xff\xff\xff\xff\xff\xff\xff\xff",
6508 "\xff\xff\xff\xff\xff\xff\xff\xff"
6509 "\xff\xff\xff\xff\xff\xff\xff\xff",
6510 .vtc_flow = RTE_BE32(0xffffffff),
6516 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6520 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6524 .dummy[0] = 0xffffffff,
6527 struct mlx5_priv *priv = dev->data->dev_private;
6528 struct mlx5_dev_config *dev_conf = &priv->config;
6529 uint16_t queue_index = 0xFFFF;
6530 const struct rte_flow_item_vlan *vlan_m = NULL;
6531 uint32_t rw_act_num = 0;
6533 const struct mlx5_flow_tunnel *tunnel;
6534 struct flow_grp_info grp_info = {
6535 .external = !!external,
6536 .transfer = !!attr->transfer,
6537 .fdb_def_rule = !!priv->fdb_def_rule,
6539 const struct rte_eth_hairpin_conf *conf;
6540 const struct rte_flow_item *rule_items = items;
6541 bool def_policy = false;
6545 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6546 tunnel = flow_items_to_tunnel(items);
6547 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6548 MLX5_FLOW_ACTION_DECAP;
6549 } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6550 tunnel = flow_actions_to_tunnel(actions);
6551 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6555 if (tunnel && priv->representor)
6556 return rte_flow_error_set(error, ENOTSUP,
6557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6558 "decap not supported "
6559 "for VF representor");
6560 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6561 (dev, tunnel, attr, items, actions);
6562 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6565 is_root = (uint64_t)ret;
6566 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6567 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6568 int type = items->type;
6570 if (!mlx5_flow_os_item_supported(type))
6571 return rte_flow_error_set(error, ENOTSUP,
6572 RTE_FLOW_ERROR_TYPE_ITEM,
6573 NULL, "item not supported");
6575 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6576 if (items[0].type != (typeof(items[0].type))
6577 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6578 return rte_flow_error_set
6580 RTE_FLOW_ERROR_TYPE_ITEM,
6581 NULL, "MLX5 private items "
6582 "must be the first");
6584 case RTE_FLOW_ITEM_TYPE_VOID:
6586 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6587 ret = flow_dv_validate_item_port_id
6588 (dev, items, attr, item_flags, error);
6591 last_item = MLX5_FLOW_ITEM_PORT_ID;
6593 case RTE_FLOW_ITEM_TYPE_ETH:
6594 ret = mlx5_flow_validate_item_eth(items, item_flags,
6598 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6599 MLX5_FLOW_LAYER_OUTER_L2;
6600 if (items->mask != NULL && items->spec != NULL) {
6602 ((const struct rte_flow_item_eth *)
6605 ((const struct rte_flow_item_eth *)
6607 ether_type = rte_be_to_cpu_16(ether_type);
6612 case RTE_FLOW_ITEM_TYPE_VLAN:
6613 ret = flow_dv_validate_item_vlan(items, item_flags,
6617 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6618 MLX5_FLOW_LAYER_OUTER_VLAN;
6619 if (items->mask != NULL && items->spec != NULL) {
6621 ((const struct rte_flow_item_vlan *)
6622 items->spec)->inner_type;
6624 ((const struct rte_flow_item_vlan *)
6625 items->mask)->inner_type;
6626 ether_type = rte_be_to_cpu_16(ether_type);
6630 /* Store outer VLAN mask for of_push_vlan action. */
6632 vlan_m = items->mask;
6634 case RTE_FLOW_ITEM_TYPE_IPV4:
6635 mlx5_flow_tunnel_ip_check(items, next_protocol,
6636 &item_flags, &tunnel);
6637 ret = flow_dv_validate_item_ipv4(items, item_flags,
6638 last_item, ether_type,
6642 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6643 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6644 if (items->mask != NULL &&
6645 ((const struct rte_flow_item_ipv4 *)
6646 items->mask)->hdr.next_proto_id) {
6648 ((const struct rte_flow_item_ipv4 *)
6649 (items->spec))->hdr.next_proto_id;
6651 ((const struct rte_flow_item_ipv4 *)
6652 (items->mask))->hdr.next_proto_id;
6654 /* Reset for inner layer. */
6655 next_protocol = 0xff;
6658 case RTE_FLOW_ITEM_TYPE_IPV6:
6659 mlx5_flow_tunnel_ip_check(items, next_protocol,
6660 &item_flags, &tunnel);
6661 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6668 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6669 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6670 if (items->mask != NULL &&
6671 ((const struct rte_flow_item_ipv6 *)
6672 items->mask)->hdr.proto) {
6674 ((const struct rte_flow_item_ipv6 *)
6675 items->spec)->hdr.proto;
6677 ((const struct rte_flow_item_ipv6 *)
6678 items->spec)->hdr.proto;
6680 ((const struct rte_flow_item_ipv6 *)
6681 items->mask)->hdr.proto;
6683 /* Reset for inner layer. */
6684 next_protocol = 0xff;
6687 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6688 ret = flow_dv_validate_item_ipv6_frag_ext(items,
6693 last_item = tunnel ?
6694 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6695 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6696 if (items->mask != NULL &&
6697 ((const struct rte_flow_item_ipv6_frag_ext *)
6698 items->mask)->hdr.next_header) {
6700 ((const struct rte_flow_item_ipv6_frag_ext *)
6701 items->spec)->hdr.next_header;
6703 ((const struct rte_flow_item_ipv6_frag_ext *)
6704 items->mask)->hdr.next_header;
6706 /* Reset for inner layer. */
6707 next_protocol = 0xff;
6710 case RTE_FLOW_ITEM_TYPE_TCP:
6711 ret = mlx5_flow_validate_item_tcp
6718 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6719 MLX5_FLOW_LAYER_OUTER_L4_TCP;
6721 case RTE_FLOW_ITEM_TYPE_UDP:
6722 ret = mlx5_flow_validate_item_udp(items, item_flags,
6727 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6728 MLX5_FLOW_LAYER_OUTER_L4_UDP;
6730 case RTE_FLOW_ITEM_TYPE_GRE:
6731 ret = mlx5_flow_validate_item_gre(items, item_flags,
6732 next_protocol, error);
6736 last_item = MLX5_FLOW_LAYER_GRE;
6738 case RTE_FLOW_ITEM_TYPE_NVGRE:
6739 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6744 last_item = MLX5_FLOW_LAYER_NVGRE;
6746 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6747 ret = mlx5_flow_validate_item_gre_key
6748 (items, item_flags, gre_item, error);
6751 last_item = MLX5_FLOW_LAYER_GRE_KEY;
6753 case RTE_FLOW_ITEM_TYPE_VXLAN:
6754 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6758 last_item = MLX5_FLOW_LAYER_VXLAN;
6760 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6761 ret = mlx5_flow_validate_item_vxlan_gpe(items,
6766 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6768 case RTE_FLOW_ITEM_TYPE_GENEVE:
6769 ret = mlx5_flow_validate_item_geneve(items,
6774 geneve_item = items;
6775 last_item = MLX5_FLOW_LAYER_GENEVE;
6777 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6778 ret = mlx5_flow_validate_item_geneve_opt(items,
6785 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6787 case RTE_FLOW_ITEM_TYPE_MPLS:
6788 ret = mlx5_flow_validate_item_mpls(dev, items,
6793 last_item = MLX5_FLOW_LAYER_MPLS;
6796 case RTE_FLOW_ITEM_TYPE_MARK:
6797 ret = flow_dv_validate_item_mark(dev, items, attr,
6801 last_item = MLX5_FLOW_ITEM_MARK;
6803 case RTE_FLOW_ITEM_TYPE_META:
6804 ret = flow_dv_validate_item_meta(dev, items, attr,
6808 last_item = MLX5_FLOW_ITEM_METADATA;
6810 case RTE_FLOW_ITEM_TYPE_ICMP:
6811 ret = mlx5_flow_validate_item_icmp(items, item_flags,
6816 last_item = MLX5_FLOW_LAYER_ICMP;
6818 case RTE_FLOW_ITEM_TYPE_ICMP6:
6819 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6824 item_ipv6_proto = IPPROTO_ICMPV6;
6825 last_item = MLX5_FLOW_LAYER_ICMP6;
6827 case RTE_FLOW_ITEM_TYPE_TAG:
6828 ret = flow_dv_validate_item_tag(dev, items,
6832 last_item = MLX5_FLOW_ITEM_TAG;
6834 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6835 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6837 case RTE_FLOW_ITEM_TYPE_GTP:
6838 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6843 last_item = MLX5_FLOW_LAYER_GTP;
6845 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6846 ret = flow_dv_validate_item_gtp_psc(items, last_item,
6851 last_item = MLX5_FLOW_LAYER_GTP_PSC;
6853 case RTE_FLOW_ITEM_TYPE_ECPRI:
6854 /* Capacity will be checked in the translate stage. */
6855 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6862 last_item = MLX5_FLOW_LAYER_ECPRI;
6864 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
6865 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY)
6866 return rte_flow_error_set
6868 RTE_FLOW_ERROR_TYPE_ITEM,
6869 NULL, "multiple integrity items not supported");
6870 ret = flow_dv_validate_item_integrity(dev, rule_items,
6874 last_item = MLX5_FLOW_ITEM_INTEGRITY;
6877 return rte_flow_error_set(error, ENOTSUP,
6878 RTE_FLOW_ERROR_TYPE_ITEM,
6879 NULL, "item not supported");
6881 item_flags |= last_item;
6883 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6884 int type = actions->type;
6885 bool shared_count = false;
6887 if (!mlx5_flow_os_action_supported(type))
6888 return rte_flow_error_set(error, ENOTSUP,
6889 RTE_FLOW_ERROR_TYPE_ACTION,
6891 "action not supported");
6892 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6893 return rte_flow_error_set(error, ENOTSUP,
6894 RTE_FLOW_ERROR_TYPE_ACTION,
6895 actions, "too many actions");
6897 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
6898 return rte_flow_error_set(error, ENOTSUP,
6899 RTE_FLOW_ERROR_TYPE_ACTION,
6900 NULL, "meter action with policy "
6901 "must be the last action");
6903 case RTE_FLOW_ACTION_TYPE_VOID:
6905 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6906 ret = flow_dv_validate_action_port_id(dev,
6913 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6916 case RTE_FLOW_ACTION_TYPE_FLAG:
6917 ret = flow_dv_validate_action_flag(dev, action_flags,
6921 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6922 /* Count all modify-header actions as one. */
6923 if (!(action_flags &
6924 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6926 action_flags |= MLX5_FLOW_ACTION_FLAG |
6927 MLX5_FLOW_ACTION_MARK_EXT;
6928 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6929 modify_after_mirror = 1;
6932 action_flags |= MLX5_FLOW_ACTION_FLAG;
6935 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6937 case RTE_FLOW_ACTION_TYPE_MARK:
6938 ret = flow_dv_validate_action_mark(dev, actions,
6943 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6944 /* Count all modify-header actions as one. */
6945 if (!(action_flags &
6946 MLX5_FLOW_MODIFY_HDR_ACTIONS))
6948 action_flags |= MLX5_FLOW_ACTION_MARK |
6949 MLX5_FLOW_ACTION_MARK_EXT;
6950 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6951 modify_after_mirror = 1;
6953 action_flags |= MLX5_FLOW_ACTION_MARK;
6956 rw_act_num += MLX5_ACT_NUM_SET_MARK;
6958 case RTE_FLOW_ACTION_TYPE_SET_META:
6959 ret = flow_dv_validate_action_set_meta(dev, actions,
6964 /* Count all modify-header actions as one action. */
6965 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6967 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6968 modify_after_mirror = 1;
6969 action_flags |= MLX5_FLOW_ACTION_SET_META;
6970 rw_act_num += MLX5_ACT_NUM_SET_META;
6972 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6973 ret = flow_dv_validate_action_set_tag(dev, actions,
6978 /* Count all modify-header actions as one action. */
6979 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6981 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6982 modify_after_mirror = 1;
6983 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6984 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6986 case RTE_FLOW_ACTION_TYPE_DROP:
6987 ret = mlx5_flow_validate_action_drop(action_flags,
6991 action_flags |= MLX5_FLOW_ACTION_DROP;
6994 case RTE_FLOW_ACTION_TYPE_QUEUE:
6995 ret = mlx5_flow_validate_action_queue(actions,
7000 queue_index = ((const struct rte_flow_action_queue *)
7001 (actions->conf))->index;
7002 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7005 case RTE_FLOW_ACTION_TYPE_RSS:
7006 rss = actions->conf;
7007 ret = mlx5_flow_validate_action_rss(actions,
7013 if (rss && sample_rss &&
7014 (sample_rss->level != rss->level ||
7015 sample_rss->types != rss->types))
7016 return rte_flow_error_set(error, ENOTSUP,
7017 RTE_FLOW_ERROR_TYPE_ACTION,
7019 "Can't use the different RSS types "
7020 "or level in the same flow");
7021 if (rss != NULL && rss->queue_num)
7022 queue_index = rss->queue[0];
7023 action_flags |= MLX5_FLOW_ACTION_RSS;
7026 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7028 mlx5_flow_validate_action_default_miss(action_flags,
7032 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7035 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7036 case RTE_FLOW_ACTION_TYPE_COUNT:
7037 shared_count = is_shared_action_count(actions);
7038 ret = flow_dv_validate_action_count(dev, shared_count,
7043 action_flags |= MLX5_FLOW_ACTION_COUNT;
7046 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7047 if (flow_dv_validate_action_pop_vlan(dev,
7053 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7054 modify_after_mirror = 1;
7055 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7058 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7059 ret = flow_dv_validate_action_push_vlan(dev,
7066 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7067 modify_after_mirror = 1;
7068 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7071 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7072 ret = flow_dv_validate_action_set_vlan_pcp
7073 (action_flags, actions, error);
7076 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7077 modify_after_mirror = 1;
7078 /* Count PCP with push_vlan command. */
7079 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7081 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7082 ret = flow_dv_validate_action_set_vlan_vid
7083 (item_flags, action_flags,
7087 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7088 modify_after_mirror = 1;
7089 /* Count VID with push_vlan command. */
7090 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7091 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7093 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7094 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7095 ret = flow_dv_validate_action_l2_encap(dev,
7101 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7104 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7105 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7106 ret = flow_dv_validate_action_decap(dev, action_flags,
7107 actions, item_flags,
7111 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7112 modify_after_mirror = 1;
7113 action_flags |= MLX5_FLOW_ACTION_DECAP;
7116 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7117 ret = flow_dv_validate_action_raw_encap_decap
7118 (dev, NULL, actions->conf, attr, &action_flags,
7119 &actions_n, actions, item_flags, error);
7123 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7124 decap = actions->conf;
7125 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7127 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7131 encap = actions->conf;
7133 ret = flow_dv_validate_action_raw_encap_decap
7135 decap ? decap : &empty_decap, encap,
7136 attr, &action_flags, &actions_n,
7137 actions, item_flags, error);
7140 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7141 (action_flags & MLX5_FLOW_ACTION_DECAP))
7142 modify_after_mirror = 1;
7144 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7145 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7146 ret = flow_dv_validate_action_modify_mac(action_flags,
7152 /* Count all modify-header actions as one action. */
7153 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7155 action_flags |= actions->type ==
7156 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7157 MLX5_FLOW_ACTION_SET_MAC_SRC :
7158 MLX5_FLOW_ACTION_SET_MAC_DST;
7159 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7160 modify_after_mirror = 1;
7162 * Even if the source and destination MAC addresses have
7163 * overlap in the header with 4B alignment, the convert
7164 * function will handle them separately and 4 SW actions
7165 * will be created. And 2 actions will be added each
7166 * time no matter how many bytes of address will be set.
7168 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7170 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7171 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7172 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7178 /* Count all modify-header actions as one action. */
7179 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7181 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7182 modify_after_mirror = 1;
7183 action_flags |= actions->type ==
7184 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7185 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7186 MLX5_FLOW_ACTION_SET_IPV4_DST;
7187 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7189 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7190 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7191 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7197 if (item_ipv6_proto == IPPROTO_ICMPV6)
7198 return rte_flow_error_set(error, ENOTSUP,
7199 RTE_FLOW_ERROR_TYPE_ACTION,
7201 "Can't change header "
7202 "with ICMPv6 proto");
7203 /* Count all modify-header actions as one action. */
7204 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7206 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7207 modify_after_mirror = 1;
7208 action_flags |= actions->type ==
7209 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7210 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7211 MLX5_FLOW_ACTION_SET_IPV6_DST;
7212 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7214 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7215 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7216 ret = flow_dv_validate_action_modify_tp(action_flags,
7222 /* Count all modify-header actions as one action. */
7223 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7225 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7226 modify_after_mirror = 1;
7227 action_flags |= actions->type ==
7228 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7229 MLX5_FLOW_ACTION_SET_TP_SRC :
7230 MLX5_FLOW_ACTION_SET_TP_DST;
7231 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7233 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7234 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7235 ret = flow_dv_validate_action_modify_ttl(action_flags,
7241 /* Count all modify-header actions as one action. */
7242 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7244 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7245 modify_after_mirror = 1;
7246 action_flags |= actions->type ==
7247 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7248 MLX5_FLOW_ACTION_SET_TTL :
7249 MLX5_FLOW_ACTION_DEC_TTL;
7250 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7252 case RTE_FLOW_ACTION_TYPE_JUMP:
7253 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7259 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7261 return rte_flow_error_set(error, EINVAL,
7262 RTE_FLOW_ERROR_TYPE_ACTION,
7264 "sample and jump action combination is not supported");
7266 action_flags |= MLX5_FLOW_ACTION_JUMP;
7268 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7269 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7270 ret = flow_dv_validate_action_modify_tcp_seq
7277 /* Count all modify-header actions as one action. */
7278 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7280 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7281 modify_after_mirror = 1;
7282 action_flags |= actions->type ==
7283 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7284 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7285 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7286 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7288 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7289 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7290 ret = flow_dv_validate_action_modify_tcp_ack
7297 /* Count all modify-header actions as one action. */
7298 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7300 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7301 modify_after_mirror = 1;
7302 action_flags |= actions->type ==
7303 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7304 MLX5_FLOW_ACTION_INC_TCP_ACK :
7305 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7306 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7308 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7310 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7311 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7312 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7314 case RTE_FLOW_ACTION_TYPE_METER:
7315 ret = mlx5_flow_validate_action_meter(dev,
7322 action_flags |= MLX5_FLOW_ACTION_METER;
7325 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7327 /* Meter action will add one more TAG action. */
7328 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7330 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7331 if (!attr->transfer && !attr->group)
7332 return rte_flow_error_set(error, ENOTSUP,
7333 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7335 "Shared ASO age action is not supported for group 0");
7336 if (action_flags & MLX5_FLOW_ACTION_AGE)
7337 return rte_flow_error_set
7339 RTE_FLOW_ERROR_TYPE_ACTION,
7341 "duplicate age actions set");
7342 action_flags |= MLX5_FLOW_ACTION_AGE;
7345 case RTE_FLOW_ACTION_TYPE_AGE:
7346 ret = flow_dv_validate_action_age(action_flags,
7352 * Validate the regular AGE action (using counter)
7353 * mutual exclusion with share counter actions.
7355 if (!priv->sh->flow_hit_aso_en) {
7357 return rte_flow_error_set
7359 RTE_FLOW_ERROR_TYPE_ACTION,
7361 "old age and shared count combination is not supported");
7363 return rte_flow_error_set
7365 RTE_FLOW_ERROR_TYPE_ACTION,
7367 "old age action and count must be in the same sub flow");
7369 action_flags |= MLX5_FLOW_ACTION_AGE;
7372 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7373 ret = flow_dv_validate_action_modify_ipv4_dscp
7380 /* Count all modify-header actions as one action. */
7381 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7383 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7384 modify_after_mirror = 1;
7385 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7386 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7388 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7389 ret = flow_dv_validate_action_modify_ipv6_dscp
7396 /* Count all modify-header actions as one action. */
7397 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7399 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7400 modify_after_mirror = 1;
7401 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7402 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7404 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7405 ret = flow_dv_validate_action_sample(&action_flags,
7414 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7417 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7418 if (actions[0].type != (typeof(actions[0].type))
7419 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7420 return rte_flow_error_set
7422 RTE_FLOW_ERROR_TYPE_ACTION,
7423 NULL, "MLX5 private action "
7424 "must be the first");
7426 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7428 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7429 ret = flow_dv_validate_action_modify_field(dev,
7436 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7437 modify_after_mirror = 1;
7438 /* Count all modify-header actions as one action. */
7439 if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7441 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7445 return rte_flow_error_set(error, ENOTSUP,
7446 RTE_FLOW_ERROR_TYPE_ACTION,
7448 "action not supported");
7452 * Validate actions in flow rules
7453 * - Explicit decap action is prohibited by the tunnel offload API.
7454 * - Drop action in tunnel steer rule is prohibited by the API.
7455 * - Application cannot use MARK action because it's value can mask
7456 * tunnel default miss nitification.
7457 * - JUMP in tunnel match rule has no support in current PMD
7459 * - TAG & META are reserved for future uses.
7461 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7462 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7463 MLX5_FLOW_ACTION_MARK |
7464 MLX5_FLOW_ACTION_SET_TAG |
7465 MLX5_FLOW_ACTION_SET_META |
7466 MLX5_FLOW_ACTION_DROP;
7468 if (action_flags & bad_actions_mask)
7469 return rte_flow_error_set
7471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7472 "Invalid RTE action in tunnel "
7474 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7475 return rte_flow_error_set
7477 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7478 "tunnel set decap rule must terminate "
7481 return rte_flow_error_set
7483 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7484 "tunnel flows for ingress traffic only");
7486 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7487 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7488 MLX5_FLOW_ACTION_MARK |
7489 MLX5_FLOW_ACTION_SET_TAG |
7490 MLX5_FLOW_ACTION_SET_META;
7492 if (action_flags & bad_actions_mask)
7493 return rte_flow_error_set
7495 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7496 "Invalid RTE action in tunnel "
7500 * Validate the drop action mutual exclusion with other actions.
7501 * Drop action is mutually-exclusive with any other action, except for
7503 * Drop action compatibility with tunnel offload was already validated.
7505 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7506 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7507 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7508 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7509 return rte_flow_error_set(error, EINVAL,
7510 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7511 "Drop action is mutually-exclusive "
7512 "with any other action, except for "
7514 /* Eswitch has few restrictions on using items and actions */
7515 if (attr->transfer) {
7516 if (!mlx5_flow_ext_mreg_supported(dev) &&
7517 action_flags & MLX5_FLOW_ACTION_FLAG)
7518 return rte_flow_error_set(error, ENOTSUP,
7519 RTE_FLOW_ERROR_TYPE_ACTION,
7521 "unsupported action FLAG");
7522 if (!mlx5_flow_ext_mreg_supported(dev) &&
7523 action_flags & MLX5_FLOW_ACTION_MARK)
7524 return rte_flow_error_set(error, ENOTSUP,
7525 RTE_FLOW_ERROR_TYPE_ACTION,
7527 "unsupported action MARK");
7528 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7529 return rte_flow_error_set(error, ENOTSUP,
7530 RTE_FLOW_ERROR_TYPE_ACTION,
7532 "unsupported action QUEUE");
7533 if (action_flags & MLX5_FLOW_ACTION_RSS)
7534 return rte_flow_error_set(error, ENOTSUP,
7535 RTE_FLOW_ERROR_TYPE_ACTION,
7537 "unsupported action RSS");
7538 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7539 return rte_flow_error_set(error, EINVAL,
7540 RTE_FLOW_ERROR_TYPE_ACTION,
7542 "no fate action is found");
7544 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7545 return rte_flow_error_set(error, EINVAL,
7546 RTE_FLOW_ERROR_TYPE_ACTION,
7548 "no fate action is found");
7551 * Continue validation for Xcap and VLAN actions.
7552 * If hairpin is working in explicit TX rule mode, there is no actions
7553 * splitting and the validation of hairpin ingress flow should be the
7554 * same as other standard flows.
7556 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7557 MLX5_FLOW_VLAN_ACTIONS)) &&
7558 (queue_index == 0xFFFF ||
7559 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7560 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7561 conf->tx_explicit != 0))) {
7562 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7563 MLX5_FLOW_XCAP_ACTIONS)
7564 return rte_flow_error_set(error, ENOTSUP,
7565 RTE_FLOW_ERROR_TYPE_ACTION,
7566 NULL, "encap and decap "
7567 "combination aren't supported");
7568 if (!attr->transfer && attr->ingress) {
7569 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7570 return rte_flow_error_set
7572 RTE_FLOW_ERROR_TYPE_ACTION,
7573 NULL, "encap is not supported"
7574 " for ingress traffic");
7575 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7576 return rte_flow_error_set
7578 RTE_FLOW_ERROR_TYPE_ACTION,
7579 NULL, "push VLAN action not "
7580 "supported for ingress");
7581 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7582 MLX5_FLOW_VLAN_ACTIONS)
7583 return rte_flow_error_set
7585 RTE_FLOW_ERROR_TYPE_ACTION,
7586 NULL, "no support for "
7587 "multiple VLAN actions");
7590 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7591 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7592 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7594 return rte_flow_error_set
7596 RTE_FLOW_ERROR_TYPE_ACTION,
7597 NULL, "fate action not supported for "
7598 "meter with policy");
7600 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
7601 return rte_flow_error_set
7603 RTE_FLOW_ERROR_TYPE_ACTION,
7604 NULL, "modify header action in egress "
7605 "cannot be done before meter action");
7606 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7607 return rte_flow_error_set
7609 RTE_FLOW_ERROR_TYPE_ACTION,
7610 NULL, "encap action in egress "
7611 "cannot be done before meter action");
7612 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7613 return rte_flow_error_set
7615 RTE_FLOW_ERROR_TYPE_ACTION,
7616 NULL, "push vlan action in egress "
7617 "cannot be done before meter action");
7621 * Hairpin flow will add one more TAG action in TX implicit mode.
7622 * In TX explicit mode, there will be no hairpin flow ID.
7625 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7626 /* extra metadata enabled: one more TAG action will be add. */
7627 if (dev_conf->dv_flow_en &&
7628 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7629 mlx5_flow_ext_mreg_supported(dev))
7630 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7632 flow_dv_modify_hdr_action_max(dev, is_root)) {
7633 return rte_flow_error_set(error, ENOTSUP,
7634 RTE_FLOW_ERROR_TYPE_ACTION,
7635 NULL, "too many header modify"
7636 " actions to support");
7638 /* Eswitch egress mirror and modify flow has limitation on CX5 */
7639 if (fdb_mirror_limit && modify_after_mirror)
7640 return rte_flow_error_set(error, EINVAL,
7641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7642 "sample before modify action is not supported");
7647 * Internal preparation function. Allocates the DV flow size,
7648 * this size is constant.
7651 * Pointer to the rte_eth_dev structure.
7653 * Pointer to the flow attributes.
7655 * Pointer to the list of items.
7656 * @param[in] actions
7657 * Pointer to the list of actions.
7659 * Pointer to the error structure.
7662 * Pointer to mlx5_flow object on success,
7663 * otherwise NULL and rte_errno is set.
7665 static struct mlx5_flow *
7666 flow_dv_prepare(struct rte_eth_dev *dev,
7667 const struct rte_flow_attr *attr __rte_unused,
7668 const struct rte_flow_item items[] __rte_unused,
7669 const struct rte_flow_action actions[] __rte_unused,
7670 struct rte_flow_error *error)
7672 uint32_t handle_idx = 0;
7673 struct mlx5_flow *dev_flow;
7674 struct mlx5_flow_handle *dev_handle;
7675 struct mlx5_priv *priv = dev->data->dev_private;
7676 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7679 wks->skip_matcher_reg = 0;
7680 /* In case of corrupting the memory. */
7681 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7682 rte_flow_error_set(error, ENOSPC,
7683 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7684 "not free temporary device flow");
7687 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7690 rte_flow_error_set(error, ENOMEM,
7691 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7692 "not enough memory to create flow handle");
7695 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7696 dev_flow = &wks->flows[wks->flow_idx++];
7697 memset(dev_flow, 0, sizeof(*dev_flow));
7698 dev_flow->handle = dev_handle;
7699 dev_flow->handle_idx = handle_idx;
7701 * In some old rdma-core releases, before continuing, a check of the
7702 * length of matching parameter will be done at first. It needs to use
7703 * the length without misc4 param. If the flow has misc4 support, then
7704 * the length needs to be adjusted accordingly. Each param member is
7705 * aligned with a 64B boundary naturally.
7707 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7708 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7709 dev_flow->ingress = attr->ingress;
7710 dev_flow->dv.transfer = attr->transfer;
7714 #ifdef RTE_LIBRTE_MLX5_DEBUG
7716 * Sanity check for match mask and value. Similar to check_valid_spec() in
7717 * kernel driver. If unmasked bit is present in value, it returns failure.
7720 * pointer to match mask buffer.
7721 * @param match_value
7722 * pointer to match value buffer.
7725 * 0 if valid, -EINVAL otherwise.
7728 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7730 uint8_t *m = match_mask;
7731 uint8_t *v = match_value;
7734 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7737 "match_value differs from match_criteria"
7738 " %p[%u] != %p[%u]",
7739 match_value, i, match_mask, i);
7748 * Add match of ip_version.
7752 * @param[in] headers_v
7753 * Values header pointer.
7754 * @param[in] headers_m
7755 * Masks header pointer.
7756 * @param[in] ip_version
7757 * The IP version to set.
7760 flow_dv_set_match_ip_version(uint32_t group,
7766 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7768 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7770 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7771 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7772 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7776 * Add Ethernet item to matcher and to the value.
7778 * @param[in, out] matcher
7780 * @param[in, out] key
7781 * Flow matcher value.
7783 * Flow pattern to translate.
7785 * Item is inner pattern.
7788 flow_dv_translate_item_eth(void *matcher, void *key,
7789 const struct rte_flow_item *item, int inner,
7792 const struct rte_flow_item_eth *eth_m = item->mask;
7793 const struct rte_flow_item_eth *eth_v = item->spec;
7794 const struct rte_flow_item_eth nic_mask = {
7795 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7796 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7797 .type = RTE_BE16(0xffff),
7810 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7812 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7814 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7816 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7818 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7819 ð_m->dst, sizeof(eth_m->dst));
7820 /* The value must be in the range of the mask. */
7821 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7822 for (i = 0; i < sizeof(eth_m->dst); ++i)
7823 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7825 ð_m->src, sizeof(eth_m->src));
7826 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7827 /* The value must be in the range of the mask. */
7828 for (i = 0; i < sizeof(eth_m->dst); ++i)
7829 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7831 * HW supports match on one Ethertype, the Ethertype following the last
7832 * VLAN tag of the packet (see PRM).
7833 * Set match on ethertype only if ETH header is not followed by VLAN.
7834 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7835 * ethertype, and use ip_version field instead.
7836 * eCPRI over Ether layer will use type value 0xAEFE.
7838 if (eth_m->type == 0xFFFF) {
7839 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7840 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7841 switch (eth_v->type) {
7842 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7843 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7845 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7846 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7847 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7849 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7850 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7852 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7853 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7859 if (eth_m->has_vlan) {
7860 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7861 if (eth_v->has_vlan) {
7863 * Here, when also has_more_vlan field in VLAN item is
7864 * not set, only single-tagged packets will be matched.
7866 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7870 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7871 rte_be_to_cpu_16(eth_m->type));
7872 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7873 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7877 * Add VLAN item to matcher and to the value.
7879 * @param[in, out] dev_flow
7881 * @param[in, out] matcher
7883 * @param[in, out] key
7884 * Flow matcher value.
7886 * Flow pattern to translate.
7888 * Item is inner pattern.
7891 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7892 void *matcher, void *key,
7893 const struct rte_flow_item *item,
7894 int inner, uint32_t group)
7896 const struct rte_flow_item_vlan *vlan_m = item->mask;
7897 const struct rte_flow_item_vlan *vlan_v = item->spec;
7904 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7906 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7908 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7910 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7912 * This is workaround, masks are not supported,
7913 * and pre-validated.
7916 dev_flow->handle->vf_vlan.tag =
7917 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7920 * When VLAN item exists in flow, mark packet as tagged,
7921 * even if TCI is not specified.
7923 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7924 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7925 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7930 vlan_m = &rte_flow_item_vlan_mask;
7931 tci_m = rte_be_to_cpu_16(vlan_m->tci);
7932 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7933 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7934 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7935 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7936 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7937 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7938 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7940 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7941 * ethertype, and use ip_version field instead.
7943 if (vlan_m->inner_type == 0xFFFF) {
7944 switch (vlan_v->inner_type) {
7945 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7946 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7947 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7948 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7950 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7951 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7953 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7954 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7960 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7961 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7962 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7963 /* Only one vlan_tag bit can be set. */
7964 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7967 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7968 rte_be_to_cpu_16(vlan_m->inner_type));
7969 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7970 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7974 * Add IPV4 item to matcher and to the value.
7976 * @param[in, out] matcher
7978 * @param[in, out] key
7979 * Flow matcher value.
7981 * Flow pattern to translate.
7983 * Item is inner pattern.
7985 * The group to insert the rule.
7988 flow_dv_translate_item_ipv4(void *matcher, void *key,
7989 const struct rte_flow_item *item,
7990 int inner, uint32_t group)
7992 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7993 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7994 const struct rte_flow_item_ipv4 nic_mask = {
7996 .src_addr = RTE_BE32(0xffffffff),
7997 .dst_addr = RTE_BE32(0xffffffff),
7998 .type_of_service = 0xff,
7999 .next_proto_id = 0xff,
8000 .time_to_live = 0xff,
8010 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8012 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8014 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8016 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8018 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8023 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8024 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8025 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8026 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8027 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8028 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8029 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8030 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8031 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8032 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8033 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8034 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8035 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8036 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8037 ipv4_m->hdr.type_of_service);
8038 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8039 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8040 ipv4_m->hdr.type_of_service >> 2);
8041 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8042 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8043 ipv4_m->hdr.next_proto_id);
8044 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8045 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8046 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8047 ipv4_m->hdr.time_to_live);
8048 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8049 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8050 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8051 !!(ipv4_m->hdr.fragment_offset));
8052 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8053 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8057 * Add IPV6 item to matcher and to the value.
8059 * @param[in, out] matcher
8061 * @param[in, out] key
8062 * Flow matcher value.
8064 * Flow pattern to translate.
8066 * Item is inner pattern.
8068 * The group to insert the rule.
8071 flow_dv_translate_item_ipv6(void *matcher, void *key,
8072 const struct rte_flow_item *item,
8073 int inner, uint32_t group)
8075 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8076 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8077 const struct rte_flow_item_ipv6 nic_mask = {
8080 "\xff\xff\xff\xff\xff\xff\xff\xff"
8081 "\xff\xff\xff\xff\xff\xff\xff\xff",
8083 "\xff\xff\xff\xff\xff\xff\xff\xff"
8084 "\xff\xff\xff\xff\xff\xff\xff\xff",
8085 .vtc_flow = RTE_BE32(0xffffffff),
8092 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8093 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8102 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8104 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8106 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8108 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8110 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8115 size = sizeof(ipv6_m->hdr.dst_addr);
8116 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8117 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8118 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8119 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8120 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8121 for (i = 0; i < size; ++i)
8122 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8123 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8124 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8125 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8126 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8127 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8128 for (i = 0; i < size; ++i)
8129 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8131 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8132 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8133 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8134 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8135 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8136 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8139 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8141 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8144 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8146 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8150 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8152 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8153 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8155 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8156 ipv6_m->hdr.hop_limits);
8157 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8158 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8159 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8160 !!(ipv6_m->has_frag_ext));
8161 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8162 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8166 * Add IPV6 fragment extension item to matcher and to the value.
8168 * @param[in, out] matcher
8170 * @param[in, out] key
8171 * Flow matcher value.
8173 * Flow pattern to translate.
8175 * Item is inner pattern.
8178 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8179 const struct rte_flow_item *item,
8182 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8183 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8184 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8186 .next_header = 0xff,
8187 .frag_data = RTE_BE16(0xffff),
8194 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8196 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8198 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8200 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8202 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8203 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8204 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8205 if (!ipv6_frag_ext_v)
8207 if (!ipv6_frag_ext_m)
8208 ipv6_frag_ext_m = &nic_mask;
8209 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8210 ipv6_frag_ext_m->hdr.next_header);
8211 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8212 ipv6_frag_ext_v->hdr.next_header &
8213 ipv6_frag_ext_m->hdr.next_header);
8217 * Add TCP item to matcher and to the value.
8219 * @param[in, out] matcher
8221 * @param[in, out] key
8222 * Flow matcher value.
8224 * Flow pattern to translate.
8226 * Item is inner pattern.
8229 flow_dv_translate_item_tcp(void *matcher, void *key,
8230 const struct rte_flow_item *item,
8233 const struct rte_flow_item_tcp *tcp_m = item->mask;
8234 const struct rte_flow_item_tcp *tcp_v = item->spec;
8239 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8241 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8243 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8245 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8247 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8248 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8252 tcp_m = &rte_flow_item_tcp_mask;
8253 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8254 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8255 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8256 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8257 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8258 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8259 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8260 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8262 tcp_m->hdr.tcp_flags);
8263 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8264 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8268 * Add UDP item to matcher and to the value.
8270 * @param[in, out] matcher
8272 * @param[in, out] key
8273 * Flow matcher value.
8275 * Flow pattern to translate.
8277 * Item is inner pattern.
8280 flow_dv_translate_item_udp(void *matcher, void *key,
8281 const struct rte_flow_item *item,
8284 const struct rte_flow_item_udp *udp_m = item->mask;
8285 const struct rte_flow_item_udp *udp_v = item->spec;
8290 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8292 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8294 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8296 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8298 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8299 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8303 udp_m = &rte_flow_item_udp_mask;
8304 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8305 rte_be_to_cpu_16(udp_m->hdr.src_port));
8306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8307 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8308 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8309 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8310 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8311 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8315 * Add GRE optional Key item to matcher and to the value.
8317 * @param[in, out] matcher
8319 * @param[in, out] key
8320 * Flow matcher value.
8322 * Flow pattern to translate.
8324 * Item is inner pattern.
8327 flow_dv_translate_item_gre_key(void *matcher, void *key,
8328 const struct rte_flow_item *item)
8330 const rte_be32_t *key_m = item->mask;
8331 const rte_be32_t *key_v = item->spec;
8332 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8333 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8334 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8336 /* GRE K bit must be on and should already be validated */
8337 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8338 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8342 key_m = &gre_key_default_mask;
8343 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8344 rte_be_to_cpu_32(*key_m) >> 8);
8345 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8346 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8347 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8348 rte_be_to_cpu_32(*key_m) & 0xFF);
8349 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8350 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8354 * Add GRE item to matcher and to the value.
8356 * @param[in, out] matcher
8358 * @param[in, out] key
8359 * Flow matcher value.
8361 * Flow pattern to translate.
8363 * Item is inner pattern.
8366 flow_dv_translate_item_gre(void *matcher, void *key,
8367 const struct rte_flow_item *item,
8370 const struct rte_flow_item_gre *gre_m = item->mask;
8371 const struct rte_flow_item_gre *gre_v = item->spec;
8374 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8375 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8382 uint16_t s_present:1;
8383 uint16_t k_present:1;
8384 uint16_t rsvd_bit1:1;
8385 uint16_t c_present:1;
8389 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8392 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8394 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8396 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8398 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8400 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8401 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8405 gre_m = &rte_flow_item_gre_mask;
8406 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8407 rte_be_to_cpu_16(gre_m->protocol));
8408 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8409 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8410 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8411 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8412 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8413 gre_crks_rsvd0_ver_m.c_present);
8414 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8415 gre_crks_rsvd0_ver_v.c_present &
8416 gre_crks_rsvd0_ver_m.c_present);
8417 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8418 gre_crks_rsvd0_ver_m.k_present);
8419 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8420 gre_crks_rsvd0_ver_v.k_present &
8421 gre_crks_rsvd0_ver_m.k_present);
8422 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8423 gre_crks_rsvd0_ver_m.s_present);
8424 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8425 gre_crks_rsvd0_ver_v.s_present &
8426 gre_crks_rsvd0_ver_m.s_present);
8430 * Add NVGRE item to matcher and to the value.
8432 * @param[in, out] matcher
8434 * @param[in, out] key
8435 * Flow matcher value.
8437 * Flow pattern to translate.
8439 * Item is inner pattern.
8442 flow_dv_translate_item_nvgre(void *matcher, void *key,
8443 const struct rte_flow_item *item,
8446 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8447 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8448 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8449 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8450 const char *tni_flow_id_m;
8451 const char *tni_flow_id_v;
8457 /* For NVGRE, GRE header fields must be set with defined values. */
8458 const struct rte_flow_item_gre gre_spec = {
8459 .c_rsvd0_ver = RTE_BE16(0x2000),
8460 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8462 const struct rte_flow_item_gre gre_mask = {
8463 .c_rsvd0_ver = RTE_BE16(0xB000),
8464 .protocol = RTE_BE16(UINT16_MAX),
8466 const struct rte_flow_item gre_item = {
8471 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8475 nvgre_m = &rte_flow_item_nvgre_mask;
8476 tni_flow_id_m = (const char *)nvgre_m->tni;
8477 tni_flow_id_v = (const char *)nvgre_v->tni;
8478 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8479 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8480 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8481 memcpy(gre_key_m, tni_flow_id_m, size);
8482 for (i = 0; i < size; ++i)
8483 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8487 * Add VXLAN item to matcher and to the value.
8489 * @param[in, out] matcher
8491 * @param[in, out] key
8492 * Flow matcher value.
8494 * Flow pattern to translate.
8496 * Item is inner pattern.
8499 flow_dv_translate_item_vxlan(void *matcher, void *key,
8500 const struct rte_flow_item *item,
8503 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8504 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8507 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8508 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8516 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8518 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8520 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8522 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8524 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8525 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8526 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8533 vxlan_m = &rte_flow_item_vxlan_mask;
8534 size = sizeof(vxlan_m->vni);
8535 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8536 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8537 memcpy(vni_m, vxlan_m->vni, size);
8538 for (i = 0; i < size; ++i)
8539 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8543 * Add VXLAN-GPE item to matcher and to the value.
8545 * @param[in, out] matcher
8547 * @param[in, out] key
8548 * Flow matcher value.
8550 * Flow pattern to translate.
8552 * Item is inner pattern.
8556 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8557 const struct rte_flow_item *item, int inner)
8559 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8560 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8564 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8566 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8572 uint8_t flags_m = 0xff;
8573 uint8_t flags_v = 0xc;
8576 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8578 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8580 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8582 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8584 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8585 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8586 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8587 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8588 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8593 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8594 size = sizeof(vxlan_m->vni);
8595 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8596 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8597 memcpy(vni_m, vxlan_m->vni, size);
8598 for (i = 0; i < size; ++i)
8599 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8600 if (vxlan_m->flags) {
8601 flags_m = vxlan_m->flags;
8602 flags_v = vxlan_v->flags;
8604 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8605 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8606 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8608 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8613 * Add Geneve item to matcher and to the value.
8615 * @param[in, out] matcher
8617 * @param[in, out] key
8618 * Flow matcher value.
8620 * Flow pattern to translate.
8622 * Item is inner pattern.
8626 flow_dv_translate_item_geneve(void *matcher, void *key,
8627 const struct rte_flow_item *item, int inner)
8629 const struct rte_flow_item_geneve *geneve_m = item->mask;
8630 const struct rte_flow_item_geneve *geneve_v = item->spec;
8633 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8634 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8643 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8645 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8647 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8649 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8651 dport = MLX5_UDP_PORT_GENEVE;
8652 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8653 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8654 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8659 geneve_m = &rte_flow_item_geneve_mask;
8660 size = sizeof(geneve_m->vni);
8661 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8662 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8663 memcpy(vni_m, geneve_m->vni, size);
8664 for (i = 0; i < size; ++i)
8665 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8666 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8667 rte_be_to_cpu_16(geneve_m->protocol));
8668 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8669 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8670 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8671 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8672 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8673 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8674 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8675 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8676 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8677 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8678 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8679 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8680 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8684 * Create Geneve TLV option resource.
8686 * @param dev[in, out]
8687 * Pointer to rte_eth_dev structure.
8688 * @param[in, out] tag_be24
8689 * Tag value in big endian then R-shift 8.
8690 * @parm[in, out] dev_flow
8691 * Pointer to the dev_flow.
8693 * pointer to error structure.
8696 * 0 on success otherwise -errno and errno is set.
8700 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8701 const struct rte_flow_item *item,
8702 struct rte_flow_error *error)
8704 struct mlx5_priv *priv = dev->data->dev_private;
8705 struct mlx5_dev_ctx_shared *sh = priv->sh;
8706 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8707 sh->geneve_tlv_option_resource;
8708 struct mlx5_devx_obj *obj;
8709 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8714 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8715 if (geneve_opt_resource != NULL) {
8716 if (geneve_opt_resource->option_class ==
8717 geneve_opt_v->option_class &&
8718 geneve_opt_resource->option_type ==
8719 geneve_opt_v->option_type &&
8720 geneve_opt_resource->length ==
8721 geneve_opt_v->option_len) {
8722 /* We already have GENVE TLV option obj allocated. */
8723 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8726 ret = rte_flow_error_set(error, ENOMEM,
8727 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8728 "Only one GENEVE TLV option supported");
8732 /* Create a GENEVE TLV object and resource. */
8733 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8734 geneve_opt_v->option_class,
8735 geneve_opt_v->option_type,
8736 geneve_opt_v->option_len);
8738 ret = rte_flow_error_set(error, ENODATA,
8739 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8740 "Failed to create GENEVE TLV Devx object");
8743 sh->geneve_tlv_option_resource =
8744 mlx5_malloc(MLX5_MEM_ZERO,
8745 sizeof(*geneve_opt_resource),
8747 if (!sh->geneve_tlv_option_resource) {
8748 claim_zero(mlx5_devx_cmd_destroy(obj));
8749 ret = rte_flow_error_set(error, ENOMEM,
8750 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8751 "GENEVE TLV object memory allocation failed");
8754 geneve_opt_resource = sh->geneve_tlv_option_resource;
8755 geneve_opt_resource->obj = obj;
8756 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8757 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8758 geneve_opt_resource->length = geneve_opt_v->option_len;
8759 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8763 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8768 * Add Geneve TLV option item to matcher.
8770 * @param[in, out] dev
8771 * Pointer to rte_eth_dev structure.
8772 * @param[in, out] matcher
8774 * @param[in, out] key
8775 * Flow matcher value.
8777 * Flow pattern to translate.
8779 * Pointer to error structure.
8782 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8783 void *key, const struct rte_flow_item *item,
8784 struct rte_flow_error *error)
8786 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8787 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8788 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8789 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8790 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8792 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8793 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8799 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8800 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8803 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8807 * Set the option length in GENEVE header if not requested.
8808 * The GENEVE TLV option length is expressed by the option length field
8809 * in the GENEVE header.
8810 * If the option length was not requested but the GENEVE TLV option item
8811 * is present we set the option length field implicitly.
8813 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8814 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8815 MLX5_GENEVE_OPTLEN_MASK);
8816 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8817 geneve_opt_v->option_len + 1);
8820 if (geneve_opt_v->data) {
8821 memcpy(&opt_data_key, geneve_opt_v->data,
8822 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8823 sizeof(opt_data_key)));
8824 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8825 sizeof(opt_data_key));
8826 memcpy(&opt_data_mask, geneve_opt_m->data,
8827 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8828 sizeof(opt_data_mask)));
8829 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8830 sizeof(opt_data_mask));
8831 MLX5_SET(fte_match_set_misc3, misc3_m,
8832 geneve_tlv_option_0_data,
8833 rte_be_to_cpu_32(opt_data_mask));
8834 MLX5_SET(fte_match_set_misc3, misc3_v,
8835 geneve_tlv_option_0_data,
8836 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8842 * Add MPLS item to matcher and to the value.
8844 * @param[in, out] matcher
8846 * @param[in, out] key
8847 * Flow matcher value.
8849 * Flow pattern to translate.
8850 * @param[in] prev_layer
8851 * The protocol layer indicated in previous item.
8853 * Item is inner pattern.
8856 flow_dv_translate_item_mpls(void *matcher, void *key,
8857 const struct rte_flow_item *item,
8858 uint64_t prev_layer,
8861 const uint32_t *in_mpls_m = item->mask;
8862 const uint32_t *in_mpls_v = item->spec;
8863 uint32_t *out_mpls_m = 0;
8864 uint32_t *out_mpls_v = 0;
8865 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8866 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8867 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8869 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8870 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8871 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8873 switch (prev_layer) {
8874 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8875 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8876 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8877 MLX5_UDP_PORT_MPLS);
8879 case MLX5_FLOW_LAYER_GRE:
8880 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8881 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8882 RTE_ETHER_TYPE_MPLS);
8885 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8886 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8893 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8894 switch (prev_layer) {
8895 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8897 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8898 outer_first_mpls_over_udp);
8900 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8901 outer_first_mpls_over_udp);
8903 case MLX5_FLOW_LAYER_GRE:
8905 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8906 outer_first_mpls_over_gre);
8908 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8909 outer_first_mpls_over_gre);
8912 /* Inner MPLS not over GRE is not supported. */
8915 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8919 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8925 if (out_mpls_m && out_mpls_v) {
8926 *out_mpls_m = *in_mpls_m;
8927 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8932 * Add metadata register item to matcher
8934 * @param[in, out] matcher
8936 * @param[in, out] key
8937 * Flow matcher value.
8938 * @param[in] reg_type
8939 * Type of device metadata register
8946 flow_dv_match_meta_reg(void *matcher, void *key,
8947 enum modify_reg reg_type,
8948 uint32_t data, uint32_t mask)
8951 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8953 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8959 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8960 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8963 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8964 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8968 * The metadata register C0 field might be divided into
8969 * source vport index and META item value, we should set
8970 * this field according to specified mask, not as whole one.
8972 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8974 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8975 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8978 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8981 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8982 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8985 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8986 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8989 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8990 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8993 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8994 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8997 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8998 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9001 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9002 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9005 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9006 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9015 * Add MARK item to matcher
9018 * The device to configure through.
9019 * @param[in, out] matcher
9021 * @param[in, out] key
9022 * Flow matcher value.
9024 * Flow pattern to translate.
9027 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9028 void *matcher, void *key,
9029 const struct rte_flow_item *item)
9031 struct mlx5_priv *priv = dev->data->dev_private;
9032 const struct rte_flow_item_mark *mark;
9036 mark = item->mask ? (const void *)item->mask :
9037 &rte_flow_item_mark_mask;
9038 mask = mark->id & priv->sh->dv_mark_mask;
9039 mark = (const void *)item->spec;
9041 value = mark->id & priv->sh->dv_mark_mask & mask;
9043 enum modify_reg reg;
9045 /* Get the metadata register index for the mark. */
9046 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9047 MLX5_ASSERT(reg > 0);
9048 if (reg == REG_C_0) {
9049 struct mlx5_priv *priv = dev->data->dev_private;
9050 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9051 uint32_t shl_c0 = rte_bsf32(msk_c0);
9057 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9062 * Add META item to matcher
9065 * The devich to configure through.
9066 * @param[in, out] matcher
9068 * @param[in, out] key
9069 * Flow matcher value.
9071 * Attributes of flow that includes this item.
9073 * Flow pattern to translate.
9076 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9077 void *matcher, void *key,
9078 const struct rte_flow_attr *attr,
9079 const struct rte_flow_item *item)
9081 const struct rte_flow_item_meta *meta_m;
9082 const struct rte_flow_item_meta *meta_v;
9084 meta_m = (const void *)item->mask;
9086 meta_m = &rte_flow_item_meta_mask;
9087 meta_v = (const void *)item->spec;
9090 uint32_t value = meta_v->data;
9091 uint32_t mask = meta_m->data;
9093 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9096 MLX5_ASSERT(reg != REG_NON);
9098 * In datapath code there is no endianness
9099 * coversions for perfromance reasons, all
9100 * pattern conversions are done in rte_flow.
9102 value = rte_cpu_to_be_32(value);
9103 mask = rte_cpu_to_be_32(mask);
9104 if (reg == REG_C_0) {
9105 struct mlx5_priv *priv = dev->data->dev_private;
9106 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9107 uint32_t shl_c0 = rte_bsf32(msk_c0);
9108 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
9109 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
9116 MLX5_ASSERT(msk_c0);
9117 MLX5_ASSERT(!(~msk_c0 & mask));
9119 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9124 * Add vport metadata Reg C0 item to matcher
9126 * @param[in, out] matcher
9128 * @param[in, out] key
9129 * Flow matcher value.
9131 * Flow pattern to translate.
9134 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9135 uint32_t value, uint32_t mask)
9137 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9141 * Add tag item to matcher
9144 * The devich to configure through.
9145 * @param[in, out] matcher
9147 * @param[in, out] key
9148 * Flow matcher value.
9150 * Flow pattern to translate.
9153 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9154 void *matcher, void *key,
9155 const struct rte_flow_item *item)
9157 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9158 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9159 uint32_t mask, value;
9162 value = tag_v->data;
9163 mask = tag_m ? tag_m->data : UINT32_MAX;
9164 if (tag_v->id == REG_C_0) {
9165 struct mlx5_priv *priv = dev->data->dev_private;
9166 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9167 uint32_t shl_c0 = rte_bsf32(msk_c0);
9173 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9177 * Add TAG item to matcher
9180 * The devich to configure through.
9181 * @param[in, out] matcher
9183 * @param[in, out] key
9184 * Flow matcher value.
9186 * Flow pattern to translate.
9189 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9190 void *matcher, void *key,
9191 const struct rte_flow_item *item)
9193 const struct rte_flow_item_tag *tag_v = item->spec;
9194 const struct rte_flow_item_tag *tag_m = item->mask;
9195 enum modify_reg reg;
9198 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9199 /* Get the metadata register index for the tag. */
9200 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9201 MLX5_ASSERT(reg > 0);
9202 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9206 * Add source vport match to the specified matcher.
9208 * @param[in, out] matcher
9210 * @param[in, out] key
9211 * Flow matcher value.
9213 * Source vport value to match
9218 flow_dv_translate_item_source_vport(void *matcher, void *key,
9219 int16_t port, uint16_t mask)
9221 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9222 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9224 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9225 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9229 * Translate port-id item to eswitch match on port-id.
9232 * The devich to configure through.
9233 * @param[in, out] matcher
9235 * @param[in, out] key
9236 * Flow matcher value.
9238 * Flow pattern to translate.
9243 * 0 on success, a negative errno value otherwise.
9246 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9247 void *key, const struct rte_flow_item *item,
9248 const struct rte_flow_attr *attr)
9250 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9251 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9252 struct mlx5_priv *priv;
9255 mask = pid_m ? pid_m->id : 0xffff;
9256 id = pid_v ? pid_v->id : dev->data->port_id;
9257 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9261 * Translate to vport field or to metadata, depending on mode.
9262 * Kernel can use either misc.source_port or half of C0 metadata
9265 if (priv->vport_meta_mask) {
9267 * Provide the hint for SW steering library
9268 * to insert the flow into ingress domain and
9269 * save the extra vport match.
9271 if (mask == 0xffff && priv->vport_id == 0xffff &&
9272 priv->pf_bond < 0 && attr->transfer)
9273 flow_dv_translate_item_source_vport
9274 (matcher, key, priv->vport_id, mask);
9276 * We should always set the vport metadata register,
9277 * otherwise the SW steering library can drop
9278 * the rule if wire vport metadata value is not zero,
9279 * it depends on kernel configuration.
9281 flow_dv_translate_item_meta_vport(matcher, key,
9282 priv->vport_meta_tag,
9283 priv->vport_meta_mask);
9285 flow_dv_translate_item_source_vport(matcher, key,
9286 priv->vport_id, mask);
9292 * Add ICMP6 item to matcher and to the value.
9294 * @param[in, out] matcher
9296 * @param[in, out] key
9297 * Flow matcher value.
9299 * Flow pattern to translate.
9301 * Item is inner pattern.
9304 flow_dv_translate_item_icmp6(void *matcher, void *key,
9305 const struct rte_flow_item *item,
9308 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9309 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9312 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9314 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9316 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9318 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9320 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9322 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9324 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9325 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9329 icmp6_m = &rte_flow_item_icmp6_mask;
9330 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9331 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9332 icmp6_v->type & icmp6_m->type);
9333 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9334 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9335 icmp6_v->code & icmp6_m->code);
9339 * Add ICMP item to matcher and to the value.
9341 * @param[in, out] matcher
9343 * @param[in, out] key
9344 * Flow matcher value.
9346 * Flow pattern to translate.
9348 * Item is inner pattern.
9351 flow_dv_translate_item_icmp(void *matcher, void *key,
9352 const struct rte_flow_item *item,
9355 const struct rte_flow_item_icmp *icmp_m = item->mask;
9356 const struct rte_flow_item_icmp *icmp_v = item->spec;
9357 uint32_t icmp_header_data_m = 0;
9358 uint32_t icmp_header_data_v = 0;
9361 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9363 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9365 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9367 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9369 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9371 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9373 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9378 icmp_m = &rte_flow_item_icmp_mask;
9379 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9380 icmp_m->hdr.icmp_type);
9381 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9382 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9383 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9384 icmp_m->hdr.icmp_code);
9385 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9386 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9387 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9388 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9389 if (icmp_header_data_m) {
9390 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9391 icmp_header_data_v |=
9392 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9393 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9394 icmp_header_data_m);
9395 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9396 icmp_header_data_v & icmp_header_data_m);
9401 * Add GTP item to matcher and to the value.
9403 * @param[in, out] matcher
9405 * @param[in, out] key
9406 * Flow matcher value.
9408 * Flow pattern to translate.
9410 * Item is inner pattern.
9413 flow_dv_translate_item_gtp(void *matcher, void *key,
9414 const struct rte_flow_item *item, int inner)
9416 const struct rte_flow_item_gtp *gtp_m = item->mask;
9417 const struct rte_flow_item_gtp *gtp_v = item->spec;
9420 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9422 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9423 uint16_t dport = RTE_GTPU_UDP_PORT;
9426 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9428 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9430 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9432 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9434 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9435 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9436 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9441 gtp_m = &rte_flow_item_gtp_mask;
9442 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9443 gtp_m->v_pt_rsv_flags);
9444 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9445 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9446 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9447 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9448 gtp_v->msg_type & gtp_m->msg_type);
9449 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9450 rte_be_to_cpu_32(gtp_m->teid));
9451 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9452 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9456 * Add GTP PSC item to matcher.
9458 * @param[in, out] matcher
9460 * @param[in, out] key
9461 * Flow matcher value.
9463 * Flow pattern to translate.
9466 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9467 const struct rte_flow_item *item)
9469 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9470 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9471 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9473 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9479 uint8_t next_ext_header_type;
9484 /* Always set E-flag match on one, regardless of GTP item settings. */
9485 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9486 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9487 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9488 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9489 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9490 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9491 /*Set next extension header type. */
9494 dw_2.next_ext_header_type = 0xff;
9495 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9496 rte_cpu_to_be_32(dw_2.w32));
9499 dw_2.next_ext_header_type = 0x85;
9500 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9501 rte_cpu_to_be_32(dw_2.w32));
9513 /*Set extension header PDU type and Qos. */
9515 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9517 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9518 dw_0.qfi = gtp_psc_m->qfi;
9519 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9520 rte_cpu_to_be_32(dw_0.w32));
9522 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9523 gtp_psc_m->pdu_type);
9524 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9525 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9526 rte_cpu_to_be_32(dw_0.w32));
9532 * Add eCPRI item to matcher and to the value.
9535 * The devich to configure through.
9536 * @param[in, out] matcher
9538 * @param[in, out] key
9539 * Flow matcher value.
9541 * Flow pattern to translate.
9542 * @param[in] samples
9543 * Sample IDs to be used in the matching.
9546 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9547 void *key, const struct rte_flow_item *item)
9549 struct mlx5_priv *priv = dev->data->dev_private;
9550 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9551 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9552 struct rte_ecpri_common_hdr common;
9553 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9555 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9563 ecpri_m = &rte_flow_item_ecpri_mask;
9565 * Maximal four DW samples are supported in a single matching now.
9566 * Two are used now for a eCPRI matching:
9567 * 1. Type: one byte, mask should be 0x00ff0000 in network order
9568 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9571 if (!ecpri_m->hdr.common.u32)
9573 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9574 /* Need to take the whole DW as the mask to fill the entry. */
9575 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9576 prog_sample_field_value_0);
9577 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9578 prog_sample_field_value_0);
9579 /* Already big endian (network order) in the header. */
9580 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9581 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9582 /* Sample#0, used for matching type, offset 0. */
9583 MLX5_SET(fte_match_set_misc4, misc4_m,
9584 prog_sample_field_id_0, samples[0]);
9585 /* It makes no sense to set the sample ID in the mask field. */
9586 MLX5_SET(fte_match_set_misc4, misc4_v,
9587 prog_sample_field_id_0, samples[0]);
9589 * Checking if message body part needs to be matched.
9590 * Some wildcard rules only matching type field should be supported.
9592 if (ecpri_m->hdr.dummy[0]) {
9593 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9594 switch (common.type) {
9595 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9596 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9597 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9598 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9599 prog_sample_field_value_1);
9600 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9601 prog_sample_field_value_1);
9602 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9603 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9604 ecpri_m->hdr.dummy[0];
9605 /* Sample#1, to match message body, offset 4. */
9606 MLX5_SET(fte_match_set_misc4, misc4_m,
9607 prog_sample_field_id_1, samples[1]);
9608 MLX5_SET(fte_match_set_misc4, misc4_v,
9609 prog_sample_field_id_1, samples[1]);
9612 /* Others, do not match any sample ID. */
9618 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9620 #define HEADER_IS_ZERO(match_criteria, headers) \
9621 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
9622 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9625 * Calculate flow matcher enable bitmap.
9627 * @param match_criteria
9628 * Pointer to flow matcher criteria.
9631 * Bitmap of enabled fields.
9634 flow_dv_matcher_enable(uint32_t *match_criteria)
9636 uint8_t match_criteria_enable;
9638 match_criteria_enable =
9639 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9640 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9641 match_criteria_enable |=
9642 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9643 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9644 match_criteria_enable |=
9645 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9646 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9647 match_criteria_enable |=
9648 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9649 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9650 match_criteria_enable |=
9651 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9652 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9653 match_criteria_enable |=
9654 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9655 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9656 return match_criteria_enable;
9659 struct mlx5_hlist_entry *
9660 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9662 struct mlx5_dev_ctx_shared *sh = list->ctx;
9663 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9664 struct rte_eth_dev *dev = ctx->dev;
9665 struct mlx5_flow_tbl_data_entry *tbl_data;
9666 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9667 struct rte_flow_error *error = ctx->error;
9668 union mlx5_flow_tbl_key key = { .v64 = key64 };
9669 struct mlx5_flow_tbl_resource *tbl;
9674 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9676 rte_flow_error_set(error, ENOMEM,
9677 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9679 "cannot allocate flow table data entry");
9682 tbl_data->idx = idx;
9683 tbl_data->tunnel = tt_prm->tunnel;
9684 tbl_data->group_id = tt_prm->group_id;
9685 tbl_data->external = !!tt_prm->external;
9686 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9687 tbl_data->is_egress = !!key.is_egress;
9688 tbl_data->is_transfer = !!key.is_fdb;
9689 tbl_data->dummy = !!key.dummy;
9690 tbl_data->level = key.level;
9691 tbl_data->id = key.id;
9692 tbl = &tbl_data->tbl;
9694 return &tbl_data->entry;
9696 domain = sh->fdb_domain;
9697 else if (key.is_egress)
9698 domain = sh->tx_domain;
9700 domain = sh->rx_domain;
9701 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
9703 rte_flow_error_set(error, ENOMEM,
9704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9705 NULL, "cannot create flow table object");
9706 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9709 if (key.level != 0) {
9710 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9711 (tbl->obj, &tbl_data->jump.action);
9713 rte_flow_error_set(error, ENOMEM,
9714 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9716 "cannot create flow jump action");
9717 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9718 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9722 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_cache",
9723 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
9725 mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9726 flow_dv_matcher_create_cb,
9727 flow_dv_matcher_match_cb,
9728 flow_dv_matcher_remove_cb);
9729 return &tbl_data->entry;
9733 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9734 struct mlx5_hlist_entry *entry, uint64_t key64,
9735 void *cb_ctx __rte_unused)
9737 struct mlx5_flow_tbl_data_entry *tbl_data =
9738 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9739 union mlx5_flow_tbl_key key = { .v64 = key64 };
9741 return tbl_data->level != key.level ||
9742 tbl_data->id != key.id ||
9743 tbl_data->dummy != key.dummy ||
9744 tbl_data->is_transfer != !!key.is_fdb ||
9745 tbl_data->is_egress != !!key.is_egress;
9751 * @param[in, out] dev
9752 * Pointer to rte_eth_dev structure.
9753 * @param[in] table_level
9754 * Table level to use.
9756 * Direction of the table.
9757 * @param[in] transfer
9758 * E-Switch or NIC flow.
9760 * Dummy entry for dv API.
9761 * @param[in] table_id
9764 * pointer to error structure.
9767 * Returns tables resource based on the index, NULL in case of failed.
9769 struct mlx5_flow_tbl_resource *
9770 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9771 uint32_t table_level, uint8_t egress,
9774 const struct mlx5_flow_tunnel *tunnel,
9775 uint32_t group_id, uint8_t dummy,
9777 struct rte_flow_error *error)
9779 struct mlx5_priv *priv = dev->data->dev_private;
9780 union mlx5_flow_tbl_key table_key = {
9782 .level = table_level,
9786 .is_fdb = !!transfer,
9787 .is_egress = !!egress,
9790 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9792 .group_id = group_id,
9793 .external = external,
9795 struct mlx5_flow_cb_ctx ctx = {
9800 struct mlx5_hlist_entry *entry;
9801 struct mlx5_flow_tbl_data_entry *tbl_data;
9803 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9805 rte_flow_error_set(error, ENOMEM,
9806 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9807 "cannot get table");
9810 DRV_LOG(DEBUG, "table_level %u table_id %u "
9811 "tunnel %u group %u registered.",
9812 table_level, table_id,
9813 tunnel ? tunnel->tunnel_id : 0, group_id);
9814 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9815 return &tbl_data->tbl;
9819 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9820 struct mlx5_hlist_entry *entry)
9822 struct mlx5_dev_ctx_shared *sh = list->ctx;
9823 struct mlx5_flow_tbl_data_entry *tbl_data =
9824 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9826 MLX5_ASSERT(entry && sh);
9827 if (tbl_data->jump.action)
9828 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9829 if (tbl_data->tbl.obj)
9830 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9831 if (tbl_data->tunnel_offload && tbl_data->external) {
9832 struct mlx5_hlist_entry *he;
9833 struct mlx5_hlist *tunnel_grp_hash;
9834 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9835 union tunnel_tbl_key tunnel_key = {
9836 .tunnel_id = tbl_data->tunnel ?
9837 tbl_data->tunnel->tunnel_id : 0,
9838 .group = tbl_data->group_id
9840 uint32_t table_level = tbl_data->level;
9842 tunnel_grp_hash = tbl_data->tunnel ?
9843 tbl_data->tunnel->groups :
9845 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9847 mlx5_hlist_unregister(tunnel_grp_hash, he);
9849 "table_level %u id %u tunnel %u group %u released.",
9853 tbl_data->tunnel->tunnel_id : 0,
9854 tbl_data->group_id);
9856 mlx5_cache_list_destroy(&tbl_data->matchers);
9857 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9861 * Release a flow table.
9864 * Pointer to device shared structure.
9866 * Table resource to be released.
9869 * Returns 0 if table was released, else return 1;
9872 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9873 struct mlx5_flow_tbl_resource *tbl)
9875 struct mlx5_flow_tbl_data_entry *tbl_data =
9876 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9880 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9884 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9885 struct mlx5_cache_entry *entry, void *cb_ctx)
9887 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9888 struct mlx5_flow_dv_matcher *ref = ctx->data;
9889 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9892 return cur->crc != ref->crc ||
9893 cur->priority != ref->priority ||
9894 memcmp((const void *)cur->mask.buf,
9895 (const void *)ref->mask.buf, ref->mask.size);
9898 struct mlx5_cache_entry *
9899 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9900 struct mlx5_cache_entry *entry __rte_unused,
9903 struct mlx5_dev_ctx_shared *sh = list->ctx;
9904 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9905 struct mlx5_flow_dv_matcher *ref = ctx->data;
9906 struct mlx5_flow_dv_matcher *cache;
9907 struct mlx5dv_flow_matcher_attr dv_attr = {
9908 .type = IBV_FLOW_ATTR_NORMAL,
9909 .match_mask = (void *)&ref->mask,
9911 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9915 cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9917 rte_flow_error_set(ctx->error, ENOMEM,
9918 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9919 "cannot create matcher");
9923 dv_attr.match_criteria_enable =
9924 flow_dv_matcher_enable(cache->mask.buf);
9925 dv_attr.priority = ref->priority;
9927 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9928 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9929 &cache->matcher_object);
9932 rte_flow_error_set(ctx->error, ENOMEM,
9933 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9934 "cannot create matcher");
9937 return &cache->entry;
9941 * Register the flow matcher.
9943 * @param[in, out] dev
9944 * Pointer to rte_eth_dev structure.
9945 * @param[in, out] matcher
9946 * Pointer to flow matcher.
9947 * @param[in, out] key
9948 * Pointer to flow table key.
9949 * @parm[in, out] dev_flow
9950 * Pointer to the dev_flow.
9952 * pointer to error structure.
9955 * 0 on success otherwise -errno and errno is set.
9958 flow_dv_matcher_register(struct rte_eth_dev *dev,
9959 struct mlx5_flow_dv_matcher *ref,
9960 union mlx5_flow_tbl_key *key,
9961 struct mlx5_flow *dev_flow,
9962 const struct mlx5_flow_tunnel *tunnel,
9964 struct rte_flow_error *error)
9966 struct mlx5_cache_entry *entry;
9967 struct mlx5_flow_dv_matcher *cache;
9968 struct mlx5_flow_tbl_resource *tbl;
9969 struct mlx5_flow_tbl_data_entry *tbl_data;
9970 struct mlx5_flow_cb_ctx ctx = {
9976 * tunnel offload API requires this registration for cases when
9977 * tunnel match rule was inserted before tunnel set rule.
9979 tbl = flow_dv_tbl_resource_get(dev, key->level,
9980 key->is_egress, key->is_fdb,
9981 dev_flow->external, tunnel,
9982 group_id, 0, key->id, error);
9984 return -rte_errno; /* No need to refill the error info */
9985 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9987 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9989 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9990 return rte_flow_error_set(error, ENOMEM,
9991 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9992 "cannot allocate ref memory");
9994 cache = container_of(entry, typeof(*cache), entry);
9995 dev_flow->handle->dvh.matcher = cache;
9999 struct mlx5_hlist_entry *
10000 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
10002 struct mlx5_dev_ctx_shared *sh = list->ctx;
10003 struct rte_flow_error *error = ctx;
10004 struct mlx5_flow_dv_tag_resource *entry;
10008 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10010 rte_flow_error_set(error, ENOMEM,
10011 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10012 "cannot allocate resource memory");
10016 entry->tag_id = key;
10017 ret = mlx5_flow_os_create_flow_action_tag(key,
10020 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10021 rte_flow_error_set(error, ENOMEM,
10022 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10023 NULL, "cannot create action");
10026 return &entry->entry;
10030 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
10031 struct mlx5_hlist_entry *entry, uint64_t key,
10032 void *cb_ctx __rte_unused)
10034 struct mlx5_flow_dv_tag_resource *tag =
10035 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10037 return key != tag->tag_id;
10041 * Find existing tag resource or create and register a new one.
10043 * @param dev[in, out]
10044 * Pointer to rte_eth_dev structure.
10045 * @param[in, out] tag_be24
10046 * Tag value in big endian then R-shift 8.
10047 * @parm[in, out] dev_flow
10048 * Pointer to the dev_flow.
10049 * @param[out] error
10050 * pointer to error structure.
10053 * 0 on success otherwise -errno and errno is set.
10056 flow_dv_tag_resource_register
10057 (struct rte_eth_dev *dev,
10059 struct mlx5_flow *dev_flow,
10060 struct rte_flow_error *error)
10062 struct mlx5_priv *priv = dev->data->dev_private;
10063 struct mlx5_flow_dv_tag_resource *cache_resource;
10064 struct mlx5_hlist_entry *entry;
10066 entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
10068 cache_resource = container_of
10069 (entry, struct mlx5_flow_dv_tag_resource, entry);
10070 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
10071 dev_flow->dv.tag_resource = cache_resource;
10078 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
10079 struct mlx5_hlist_entry *entry)
10081 struct mlx5_dev_ctx_shared *sh = list->ctx;
10082 struct mlx5_flow_dv_tag_resource *tag =
10083 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10085 MLX5_ASSERT(tag && sh && tag->action);
10086 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10087 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10088 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10095 * Pointer to Ethernet device.
10100 * 1 while a reference on it exists, 0 when freed.
10103 flow_dv_tag_release(struct rte_eth_dev *dev,
10106 struct mlx5_priv *priv = dev->data->dev_private;
10107 struct mlx5_flow_dv_tag_resource *tag;
10109 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10112 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10113 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10114 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10118 * Translate port ID action to vport.
10121 * Pointer to rte_eth_dev structure.
10122 * @param[in] action
10123 * Pointer to the port ID action.
10124 * @param[out] dst_port_id
10125 * The target port ID.
10126 * @param[out] error
10127 * Pointer to the error structure.
10130 * 0 on success, a negative errno value otherwise and rte_errno is set.
10133 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10134 const struct rte_flow_action *action,
10135 uint32_t *dst_port_id,
10136 struct rte_flow_error *error)
10139 struct mlx5_priv *priv;
10140 const struct rte_flow_action_port_id *conf =
10141 (const struct rte_flow_action_port_id *)action->conf;
10143 port = conf->original ? dev->data->port_id : conf->id;
10144 priv = mlx5_port_to_eswitch_info(port, false);
10146 return rte_flow_error_set(error, -rte_errno,
10147 RTE_FLOW_ERROR_TYPE_ACTION,
10149 "No eswitch info was found for port");
10150 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
10152 * This parameter is transferred to
10153 * mlx5dv_dr_action_create_dest_ib_port().
10155 *dst_port_id = priv->dev_port;
10158 * Legacy mode, no LAG configurations is supported.
10159 * This parameter is transferred to
10160 * mlx5dv_dr_action_create_dest_vport().
10162 *dst_port_id = priv->vport_id;
10168 * Create a counter with aging configuration.
10171 * Pointer to rte_eth_dev structure.
10172 * @param[in] dev_flow
10173 * Pointer to the mlx5_flow.
10174 * @param[out] count
10175 * Pointer to the counter action configuration.
10177 * Pointer to the aging action configuration.
10180 * Index to flow counter on success, 0 otherwise.
10183 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10184 struct mlx5_flow *dev_flow,
10185 const struct rte_flow_action_count *count,
10186 const struct rte_flow_action_age *age)
10189 struct mlx5_age_param *age_param;
10191 if (count && count->shared)
10192 counter = flow_dv_counter_get_shared(dev, count->id);
10194 counter = flow_dv_counter_alloc(dev, !!age);
10195 if (!counter || age == NULL)
10197 age_param = flow_dv_counter_idx_get_age(dev, counter);
10198 age_param->context = age->context ? age->context :
10199 (void *)(uintptr_t)(dev_flow->flow_idx);
10200 age_param->timeout = age->timeout;
10201 age_param->port_id = dev->data->port_id;
10202 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10203 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10208 * Add Tx queue matcher
10211 * Pointer to the dev struct.
10212 * @param[in, out] matcher
10214 * @param[in, out] key
10215 * Flow matcher value.
10217 * Flow pattern to translate.
10219 * Item is inner pattern.
10222 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10223 void *matcher, void *key,
10224 const struct rte_flow_item *item)
10226 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10227 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10229 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10231 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10232 struct mlx5_txq_ctrl *txq;
10236 queue_m = (const void *)item->mask;
10239 queue_v = (const void *)item->spec;
10242 txq = mlx5_txq_get(dev, queue_v->queue);
10245 queue = txq->obj->sq->id;
10246 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
10247 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
10248 queue & queue_m->queue);
10249 mlx5_txq_release(dev, queue_v->queue);
10253 * Set the hash fields according to the @p flow information.
10255 * @param[in] dev_flow
10256 * Pointer to the mlx5_flow.
10257 * @param[in] rss_desc
10258 * Pointer to the mlx5_flow_rss_desc.
10261 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10262 struct mlx5_flow_rss_desc *rss_desc)
10264 uint64_t items = dev_flow->handle->layers;
10266 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10268 dev_flow->hash_fields = 0;
10269 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10270 if (rss_desc->level >= 2) {
10271 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
10275 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10276 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10277 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10278 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10279 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
10280 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10281 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
10283 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
10285 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
10286 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
10287 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
10288 if (rss_types & ETH_RSS_L3_SRC_ONLY)
10289 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
10290 else if (rss_types & ETH_RSS_L3_DST_ONLY)
10291 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
10293 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
10296 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
10297 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
10298 if (rss_types & ETH_RSS_UDP) {
10299 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10300 dev_flow->hash_fields |=
10301 IBV_RX_HASH_SRC_PORT_UDP;
10302 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10303 dev_flow->hash_fields |=
10304 IBV_RX_HASH_DST_PORT_UDP;
10306 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
10308 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
10309 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
10310 if (rss_types & ETH_RSS_TCP) {
10311 if (rss_types & ETH_RSS_L4_SRC_ONLY)
10312 dev_flow->hash_fields |=
10313 IBV_RX_HASH_SRC_PORT_TCP;
10314 else if (rss_types & ETH_RSS_L4_DST_ONLY)
10315 dev_flow->hash_fields |=
10316 IBV_RX_HASH_DST_PORT_TCP;
10318 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10324 * Prepare an Rx Hash queue.
10327 * Pointer to Ethernet device.
10328 * @param[in] dev_flow
10329 * Pointer to the mlx5_flow.
10330 * @param[in] rss_desc
10331 * Pointer to the mlx5_flow_rss_desc.
10332 * @param[out] hrxq_idx
10333 * Hash Rx queue index.
10336 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10338 static struct mlx5_hrxq *
10339 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10340 struct mlx5_flow *dev_flow,
10341 struct mlx5_flow_rss_desc *rss_desc,
10342 uint32_t *hrxq_idx)
10344 struct mlx5_priv *priv = dev->data->dev_private;
10345 struct mlx5_flow_handle *dh = dev_flow->handle;
10346 struct mlx5_hrxq *hrxq;
10348 MLX5_ASSERT(rss_desc->queue_num);
10349 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10350 rss_desc->hash_fields = dev_flow->hash_fields;
10351 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10352 rss_desc->shared_rss = 0;
10353 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10356 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10362 * Release sample sub action resource.
10364 * @param[in, out] dev
10365 * Pointer to rte_eth_dev structure.
10366 * @param[in] act_res
10367 * Pointer to sample sub action resource.
10370 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10371 struct mlx5_flow_sub_actions_idx *act_res)
10373 if (act_res->rix_hrxq) {
10374 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10375 act_res->rix_hrxq = 0;
10377 if (act_res->rix_encap_decap) {
10378 flow_dv_encap_decap_resource_release(dev,
10379 act_res->rix_encap_decap);
10380 act_res->rix_encap_decap = 0;
10382 if (act_res->rix_port_id_action) {
10383 flow_dv_port_id_action_resource_release(dev,
10384 act_res->rix_port_id_action);
10385 act_res->rix_port_id_action = 0;
10387 if (act_res->rix_tag) {
10388 flow_dv_tag_release(dev, act_res->rix_tag);
10389 act_res->rix_tag = 0;
10391 if (act_res->rix_jump) {
10392 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10393 act_res->rix_jump = 0;
10398 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10399 struct mlx5_cache_entry *entry, void *cb_ctx)
10401 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10402 struct rte_eth_dev *dev = ctx->dev;
10403 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10404 struct mlx5_flow_dv_sample_resource *cache_resource =
10405 container_of(entry, typeof(*cache_resource), entry);
10407 if (resource->ratio == cache_resource->ratio &&
10408 resource->ft_type == cache_resource->ft_type &&
10409 resource->ft_id == cache_resource->ft_id &&
10410 resource->set_action == cache_resource->set_action &&
10411 !memcmp((void *)&resource->sample_act,
10412 (void *)&cache_resource->sample_act,
10413 sizeof(struct mlx5_flow_sub_actions_list))) {
10415 * Existing sample action should release the prepared
10416 * sub-actions reference counter.
10418 flow_dv_sample_sub_actions_release(dev,
10419 &resource->sample_idx);
10425 struct mlx5_cache_entry *
10426 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10427 struct mlx5_cache_entry *entry __rte_unused,
10430 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10431 struct rte_eth_dev *dev = ctx->dev;
10432 struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10433 void **sample_dv_actions = resource->sub_actions;
10434 struct mlx5_flow_dv_sample_resource *cache_resource;
10435 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10436 struct mlx5_priv *priv = dev->data->dev_private;
10437 struct mlx5_dev_ctx_shared *sh = priv->sh;
10438 struct mlx5_flow_tbl_resource *tbl;
10440 const uint32_t next_ft_step = 1;
10441 uint32_t next_ft_id = resource->ft_id + next_ft_step;
10442 uint8_t is_egress = 0;
10443 uint8_t is_transfer = 0;
10444 struct rte_flow_error *error = ctx->error;
10446 /* Register new sample resource. */
10447 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10448 if (!cache_resource) {
10449 rte_flow_error_set(error, ENOMEM,
10450 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10452 "cannot allocate resource memory");
10455 *cache_resource = *resource;
10456 /* Create normal path table level */
10457 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10459 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10461 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10462 is_egress, is_transfer,
10463 true, NULL, 0, 0, 0, error);
10465 rte_flow_error_set(error, ENOMEM,
10466 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10468 "fail to create normal path table "
10472 cache_resource->normal_path_tbl = tbl;
10473 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10474 if (!sh->default_miss_action) {
10475 rte_flow_error_set(error, ENOMEM,
10476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10478 "default miss action was not "
10482 sample_dv_actions[resource->sample_act.actions_num++] =
10483 sh->default_miss_action;
10485 /* Create a DR sample action */
10486 sampler_attr.sample_ratio = cache_resource->ratio;
10487 sampler_attr.default_next_table = tbl->obj;
10488 sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10489 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10490 &sample_dv_actions[0];
10491 sampler_attr.action = cache_resource->set_action;
10492 if (mlx5_os_flow_dr_create_flow_action_sampler
10493 (&sampler_attr, &cache_resource->verbs_action)) {
10494 rte_flow_error_set(error, ENOMEM,
10495 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10496 NULL, "cannot create sample action");
10499 cache_resource->idx = idx;
10500 cache_resource->dev = dev;
10501 return &cache_resource->entry;
10503 if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10504 flow_dv_sample_sub_actions_release(dev,
10505 &cache_resource->sample_idx);
10506 if (cache_resource->normal_path_tbl)
10507 flow_dv_tbl_resource_release(MLX5_SH(dev),
10508 cache_resource->normal_path_tbl);
10509 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10515 * Find existing sample resource or create and register a new one.
10517 * @param[in, out] dev
10518 * Pointer to rte_eth_dev structure.
10519 * @param[in] resource
10520 * Pointer to sample resource.
10521 * @parm[in, out] dev_flow
10522 * Pointer to the dev_flow.
10523 * @param[out] error
10524 * pointer to error structure.
10527 * 0 on success otherwise -errno and errno is set.
10530 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10531 struct mlx5_flow_dv_sample_resource *resource,
10532 struct mlx5_flow *dev_flow,
10533 struct rte_flow_error *error)
10535 struct mlx5_flow_dv_sample_resource *cache_resource;
10536 struct mlx5_cache_entry *entry;
10537 struct mlx5_priv *priv = dev->data->dev_private;
10538 struct mlx5_flow_cb_ctx ctx = {
10544 entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10547 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10548 dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10549 dev_flow->dv.sample_res = cache_resource;
10554 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10555 struct mlx5_cache_entry *entry, void *cb_ctx)
10557 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10558 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10559 struct rte_eth_dev *dev = ctx->dev;
10560 struct mlx5_flow_dv_dest_array_resource *cache_resource =
10561 container_of(entry, typeof(*cache_resource), entry);
10564 if (resource->num_of_dest == cache_resource->num_of_dest &&
10565 resource->ft_type == cache_resource->ft_type &&
10566 !memcmp((void *)cache_resource->sample_act,
10567 (void *)resource->sample_act,
10568 (resource->num_of_dest *
10569 sizeof(struct mlx5_flow_sub_actions_list)))) {
10571 * Existing sample action should release the prepared
10572 * sub-actions reference counter.
10574 for (idx = 0; idx < resource->num_of_dest; idx++)
10575 flow_dv_sample_sub_actions_release(dev,
10576 &resource->sample_idx[idx]);
10582 struct mlx5_cache_entry *
10583 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10584 struct mlx5_cache_entry *entry __rte_unused,
10587 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10588 struct rte_eth_dev *dev = ctx->dev;
10589 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10590 struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10591 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10592 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10593 struct mlx5_priv *priv = dev->data->dev_private;
10594 struct mlx5_dev_ctx_shared *sh = priv->sh;
10595 struct mlx5_flow_sub_actions_list *sample_act;
10596 struct mlx5dv_dr_domain *domain;
10597 uint32_t idx = 0, res_idx = 0;
10598 struct rte_flow_error *error = ctx->error;
10599 uint64_t action_flags;
10602 /* Register new destination array resource. */
10603 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10605 if (!cache_resource) {
10606 rte_flow_error_set(error, ENOMEM,
10607 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10609 "cannot allocate resource memory");
10612 *cache_resource = *resource;
10613 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10614 domain = sh->fdb_domain;
10615 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10616 domain = sh->rx_domain;
10618 domain = sh->tx_domain;
10619 for (idx = 0; idx < resource->num_of_dest; idx++) {
10620 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10621 mlx5_malloc(MLX5_MEM_ZERO,
10622 sizeof(struct mlx5dv_dr_action_dest_attr),
10624 if (!dest_attr[idx]) {
10625 rte_flow_error_set(error, ENOMEM,
10626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10628 "cannot allocate resource memory");
10631 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10632 sample_act = &resource->sample_act[idx];
10633 action_flags = sample_act->action_flags;
10634 switch (action_flags) {
10635 case MLX5_FLOW_ACTION_QUEUE:
10636 dest_attr[idx]->dest = sample_act->dr_queue_action;
10638 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10639 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10640 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10641 dest_attr[idx]->dest_reformat->reformat =
10642 sample_act->dr_encap_action;
10643 dest_attr[idx]->dest_reformat->dest =
10644 sample_act->dr_port_id_action;
10646 case MLX5_FLOW_ACTION_PORT_ID:
10647 dest_attr[idx]->dest = sample_act->dr_port_id_action;
10649 case MLX5_FLOW_ACTION_JUMP:
10650 dest_attr[idx]->dest = sample_act->dr_jump_action;
10653 rte_flow_error_set(error, EINVAL,
10654 RTE_FLOW_ERROR_TYPE_ACTION,
10656 "unsupported actions type");
10660 /* create a dest array actioin */
10661 ret = mlx5_os_flow_dr_create_flow_action_dest_array
10663 cache_resource->num_of_dest,
10665 &cache_resource->action);
10667 rte_flow_error_set(error, ENOMEM,
10668 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10670 "cannot create destination array action");
10673 cache_resource->idx = res_idx;
10674 cache_resource->dev = dev;
10675 for (idx = 0; idx < resource->num_of_dest; idx++)
10676 mlx5_free(dest_attr[idx]);
10677 return &cache_resource->entry;
10679 for (idx = 0; idx < resource->num_of_dest; idx++) {
10680 flow_dv_sample_sub_actions_release(dev,
10681 &cache_resource->sample_idx[idx]);
10682 if (dest_attr[idx])
10683 mlx5_free(dest_attr[idx]);
10686 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10691 * Find existing destination array resource or create and register a new one.
10693 * @param[in, out] dev
10694 * Pointer to rte_eth_dev structure.
10695 * @param[in] resource
10696 * Pointer to destination array resource.
10697 * @parm[in, out] dev_flow
10698 * Pointer to the dev_flow.
10699 * @param[out] error
10700 * pointer to error structure.
10703 * 0 on success otherwise -errno and errno is set.
10706 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10707 struct mlx5_flow_dv_dest_array_resource *resource,
10708 struct mlx5_flow *dev_flow,
10709 struct rte_flow_error *error)
10711 struct mlx5_flow_dv_dest_array_resource *cache_resource;
10712 struct mlx5_priv *priv = dev->data->dev_private;
10713 struct mlx5_cache_entry *entry;
10714 struct mlx5_flow_cb_ctx ctx = {
10720 entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10723 cache_resource = container_of(entry, typeof(*cache_resource), entry);
10724 dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10725 dev_flow->dv.dest_array_res = cache_resource;
10730 * Convert Sample action to DV specification.
10733 * Pointer to rte_eth_dev structure.
10734 * @param[in] action
10735 * Pointer to sample action structure.
10736 * @param[in, out] dev_flow
10737 * Pointer to the mlx5_flow.
10739 * Pointer to the flow attributes.
10740 * @param[in, out] num_of_dest
10741 * Pointer to the num of destination.
10742 * @param[in, out] sample_actions
10743 * Pointer to sample actions list.
10744 * @param[in, out] res
10745 * Pointer to sample resource.
10746 * @param[out] error
10747 * Pointer to the error structure.
10750 * 0 on success, a negative errno value otherwise and rte_errno is set.
10753 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10754 const struct rte_flow_action_sample *action,
10755 struct mlx5_flow *dev_flow,
10756 const struct rte_flow_attr *attr,
10757 uint32_t *num_of_dest,
10758 void **sample_actions,
10759 struct mlx5_flow_dv_sample_resource *res,
10760 struct rte_flow_error *error)
10762 struct mlx5_priv *priv = dev->data->dev_private;
10763 const struct rte_flow_action *sub_actions;
10764 struct mlx5_flow_sub_actions_list *sample_act;
10765 struct mlx5_flow_sub_actions_idx *sample_idx;
10766 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10767 struct rte_flow *flow = dev_flow->flow;
10768 struct mlx5_flow_rss_desc *rss_desc;
10769 uint64_t action_flags = 0;
10772 rss_desc = &wks->rss_desc;
10773 sample_act = &res->sample_act;
10774 sample_idx = &res->sample_idx;
10775 res->ratio = action->ratio;
10776 sub_actions = action->actions;
10777 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10778 int type = sub_actions->type;
10779 uint32_t pre_rix = 0;
10782 case RTE_FLOW_ACTION_TYPE_QUEUE:
10784 const struct rte_flow_action_queue *queue;
10785 struct mlx5_hrxq *hrxq;
10788 queue = sub_actions->conf;
10789 rss_desc->queue_num = 1;
10790 rss_desc->queue[0] = queue->index;
10791 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10792 rss_desc, &hrxq_idx);
10794 return rte_flow_error_set
10796 RTE_FLOW_ERROR_TYPE_ACTION,
10798 "cannot create fate queue");
10799 sample_act->dr_queue_action = hrxq->action;
10800 sample_idx->rix_hrxq = hrxq_idx;
10801 sample_actions[sample_act->actions_num++] =
10804 action_flags |= MLX5_FLOW_ACTION_QUEUE;
10805 if (action_flags & MLX5_FLOW_ACTION_MARK)
10806 dev_flow->handle->rix_hrxq = hrxq_idx;
10807 dev_flow->handle->fate_action =
10808 MLX5_FLOW_FATE_QUEUE;
10811 case RTE_FLOW_ACTION_TYPE_RSS:
10813 struct mlx5_hrxq *hrxq;
10815 const struct rte_flow_action_rss *rss;
10816 const uint8_t *rss_key;
10818 rss = sub_actions->conf;
10819 memcpy(rss_desc->queue, rss->queue,
10820 rss->queue_num * sizeof(uint16_t));
10821 rss_desc->queue_num = rss->queue_num;
10822 /* NULL RSS key indicates default RSS key. */
10823 rss_key = !rss->key ? rss_hash_default_key : rss->key;
10824 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10826 * rss->level and rss.types should be set in advance
10827 * when expanding items for RSS.
10829 flow_dv_hashfields_set(dev_flow, rss_desc);
10830 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10831 rss_desc, &hrxq_idx);
10833 return rte_flow_error_set
10835 RTE_FLOW_ERROR_TYPE_ACTION,
10837 "cannot create fate queue");
10838 sample_act->dr_queue_action = hrxq->action;
10839 sample_idx->rix_hrxq = hrxq_idx;
10840 sample_actions[sample_act->actions_num++] =
10843 action_flags |= MLX5_FLOW_ACTION_RSS;
10844 if (action_flags & MLX5_FLOW_ACTION_MARK)
10845 dev_flow->handle->rix_hrxq = hrxq_idx;
10846 dev_flow->handle->fate_action =
10847 MLX5_FLOW_FATE_QUEUE;
10850 case RTE_FLOW_ACTION_TYPE_MARK:
10852 uint32_t tag_be = mlx5_flow_mark_set
10853 (((const struct rte_flow_action_mark *)
10854 (sub_actions->conf))->id);
10856 dev_flow->handle->mark = 1;
10857 pre_rix = dev_flow->handle->dvh.rix_tag;
10858 /* Save the mark resource before sample */
10859 pre_r = dev_flow->dv.tag_resource;
10860 if (flow_dv_tag_resource_register(dev, tag_be,
10863 MLX5_ASSERT(dev_flow->dv.tag_resource);
10864 sample_act->dr_tag_action =
10865 dev_flow->dv.tag_resource->action;
10866 sample_idx->rix_tag =
10867 dev_flow->handle->dvh.rix_tag;
10868 sample_actions[sample_act->actions_num++] =
10869 sample_act->dr_tag_action;
10870 /* Recover the mark resource after sample */
10871 dev_flow->dv.tag_resource = pre_r;
10872 dev_flow->handle->dvh.rix_tag = pre_rix;
10873 action_flags |= MLX5_FLOW_ACTION_MARK;
10876 case RTE_FLOW_ACTION_TYPE_COUNT:
10878 if (!flow->counter) {
10880 flow_dv_translate_create_counter(dev,
10881 dev_flow, sub_actions->conf,
10883 if (!flow->counter)
10884 return rte_flow_error_set
10886 RTE_FLOW_ERROR_TYPE_ACTION,
10888 "cannot create counter"
10891 sample_act->dr_cnt_action =
10892 (flow_dv_counter_get_by_idx(dev,
10893 flow->counter, NULL))->action;
10894 sample_actions[sample_act->actions_num++] =
10895 sample_act->dr_cnt_action;
10896 action_flags |= MLX5_FLOW_ACTION_COUNT;
10899 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10901 struct mlx5_flow_dv_port_id_action_resource
10903 uint32_t port_id = 0;
10905 memset(&port_id_resource, 0, sizeof(port_id_resource));
10906 /* Save the port id resource before sample */
10907 pre_rix = dev_flow->handle->rix_port_id_action;
10908 pre_r = dev_flow->dv.port_id_action;
10909 if (flow_dv_translate_action_port_id(dev, sub_actions,
10912 port_id_resource.port_id = port_id;
10913 if (flow_dv_port_id_action_resource_register
10914 (dev, &port_id_resource, dev_flow, error))
10916 sample_act->dr_port_id_action =
10917 dev_flow->dv.port_id_action->action;
10918 sample_idx->rix_port_id_action =
10919 dev_flow->handle->rix_port_id_action;
10920 sample_actions[sample_act->actions_num++] =
10921 sample_act->dr_port_id_action;
10922 /* Recover the port id resource after sample */
10923 dev_flow->dv.port_id_action = pre_r;
10924 dev_flow->handle->rix_port_id_action = pre_rix;
10926 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10929 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10930 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10931 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10932 /* Save the encap resource before sample */
10933 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10934 pre_r = dev_flow->dv.encap_decap;
10935 if (flow_dv_create_action_l2_encap(dev, sub_actions,
10940 sample_act->dr_encap_action =
10941 dev_flow->dv.encap_decap->action;
10942 sample_idx->rix_encap_decap =
10943 dev_flow->handle->dvh.rix_encap_decap;
10944 sample_actions[sample_act->actions_num++] =
10945 sample_act->dr_encap_action;
10946 /* Recover the encap resource after sample */
10947 dev_flow->dv.encap_decap = pre_r;
10948 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10949 action_flags |= MLX5_FLOW_ACTION_ENCAP;
10952 return rte_flow_error_set(error, EINVAL,
10953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10955 "Not support for sampler action");
10958 sample_act->action_flags = action_flags;
10959 res->ft_id = dev_flow->dv.group;
10960 if (attr->transfer) {
10962 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10963 uint64_t set_action;
10964 } action_ctx = { .set_action = 0 };
10966 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10967 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10968 MLX5_MODIFICATION_TYPE_SET);
10969 MLX5_SET(set_action_in, action_ctx.action_in, field,
10970 MLX5_MODI_META_REG_C_0);
10971 MLX5_SET(set_action_in, action_ctx.action_in, data,
10972 priv->vport_meta_tag);
10973 res->set_action = action_ctx.set_action;
10974 } else if (attr->ingress) {
10975 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10977 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10983 * Convert Sample action to DV specification.
10986 * Pointer to rte_eth_dev structure.
10987 * @param[in, out] dev_flow
10988 * Pointer to the mlx5_flow.
10989 * @param[in] num_of_dest
10990 * The num of destination.
10991 * @param[in, out] res
10992 * Pointer to sample resource.
10993 * @param[in, out] mdest_res
10994 * Pointer to destination array resource.
10995 * @param[in] sample_actions
10996 * Pointer to sample path actions list.
10997 * @param[in] action_flags
10998 * Holds the actions detected until now.
10999 * @param[out] error
11000 * Pointer to the error structure.
11003 * 0 on success, a negative errno value otherwise and rte_errno is set.
11006 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11007 struct mlx5_flow *dev_flow,
11008 uint32_t num_of_dest,
11009 struct mlx5_flow_dv_sample_resource *res,
11010 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11011 void **sample_actions,
11012 uint64_t action_flags,
11013 struct rte_flow_error *error)
11015 /* update normal path action resource into last index of array */
11016 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11017 struct mlx5_flow_sub_actions_list *sample_act =
11018 &mdest_res->sample_act[dest_index];
11019 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11020 struct mlx5_flow_rss_desc *rss_desc;
11021 uint32_t normal_idx = 0;
11022 struct mlx5_hrxq *hrxq;
11026 rss_desc = &wks->rss_desc;
11027 if (num_of_dest > 1) {
11028 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11029 /* Handle QP action for mirroring */
11030 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11031 rss_desc, &hrxq_idx);
11033 return rte_flow_error_set
11035 RTE_FLOW_ERROR_TYPE_ACTION,
11037 "cannot create rx queue");
11039 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11040 sample_act->dr_queue_action = hrxq->action;
11041 if (action_flags & MLX5_FLOW_ACTION_MARK)
11042 dev_flow->handle->rix_hrxq = hrxq_idx;
11043 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11045 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11047 mdest_res->sample_idx[dest_index].rix_encap_decap =
11048 dev_flow->handle->dvh.rix_encap_decap;
11049 sample_act->dr_encap_action =
11050 dev_flow->dv.encap_decap->action;
11051 dev_flow->handle->dvh.rix_encap_decap = 0;
11053 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11055 mdest_res->sample_idx[dest_index].rix_port_id_action =
11056 dev_flow->handle->rix_port_id_action;
11057 sample_act->dr_port_id_action =
11058 dev_flow->dv.port_id_action->action;
11059 dev_flow->handle->rix_port_id_action = 0;
11061 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11063 mdest_res->sample_idx[dest_index].rix_jump =
11064 dev_flow->handle->rix_jump;
11065 sample_act->dr_jump_action =
11066 dev_flow->dv.jump->action;
11067 dev_flow->handle->rix_jump = 0;
11069 sample_act->actions_num = normal_idx;
11070 /* update sample action resource into first index of array */
11071 mdest_res->ft_type = res->ft_type;
11072 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11073 sizeof(struct mlx5_flow_sub_actions_idx));
11074 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11075 sizeof(struct mlx5_flow_sub_actions_list));
11076 mdest_res->num_of_dest = num_of_dest;
11077 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11079 return rte_flow_error_set(error, EINVAL,
11080 RTE_FLOW_ERROR_TYPE_ACTION,
11081 NULL, "can't create sample "
11084 res->sub_actions = sample_actions;
11085 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11086 return rte_flow_error_set(error, EINVAL,
11087 RTE_FLOW_ERROR_TYPE_ACTION,
11089 "can't create sample action");
11095 * Remove an ASO age action from age actions list.
11098 * Pointer to the Ethernet device structure.
11100 * Pointer to the aso age action handler.
11103 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11104 struct mlx5_aso_age_action *age)
11106 struct mlx5_age_info *age_info;
11107 struct mlx5_age_param *age_param = &age->age_params;
11108 struct mlx5_priv *priv = dev->data->dev_private;
11109 uint16_t expected = AGE_CANDIDATE;
11111 age_info = GET_PORT_AGE_INFO(priv);
11112 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11113 AGE_FREE, false, __ATOMIC_RELAXED,
11114 __ATOMIC_RELAXED)) {
11116 * We need the lock even it is age timeout,
11117 * since age action may still in process.
11119 rte_spinlock_lock(&age_info->aged_sl);
11120 LIST_REMOVE(age, next);
11121 rte_spinlock_unlock(&age_info->aged_sl);
11122 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11127 * Release an ASO age action.
11130 * Pointer to the Ethernet device structure.
11131 * @param[in] age_idx
11132 * Index of ASO age action to release.
11134 * True if the release operation is during flow destroy operation.
11135 * False if the release operation is during action destroy operation.
11138 * 0 when age action was removed, otherwise the number of references.
11141 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11143 struct mlx5_priv *priv = dev->data->dev_private;
11144 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11145 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11146 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11149 flow_dv_aso_age_remove_from_age(dev, age);
11150 rte_spinlock_lock(&mng->free_sl);
11151 LIST_INSERT_HEAD(&mng->free, age, next);
11152 rte_spinlock_unlock(&mng->free_sl);
11158 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11161 * Pointer to the Ethernet device structure.
11164 * 0 on success, otherwise negative errno value and rte_errno is set.
11167 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11169 struct mlx5_priv *priv = dev->data->dev_private;
11170 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11171 void *old_pools = mng->pools;
11172 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11173 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11174 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11177 rte_errno = ENOMEM;
11181 memcpy(pools, old_pools,
11182 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11183 mlx5_free(old_pools);
11185 /* First ASO flow hit allocation - starting ASO data-path. */
11186 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
11194 mng->pools = pools;
11199 * Create and initialize a new ASO aging pool.
11202 * Pointer to the Ethernet device structure.
11203 * @param[out] age_free
11204 * Where to put the pointer of a new age action.
11207 * The age actions pool pointer and @p age_free is set on success,
11208 * NULL otherwise and rte_errno is set.
11210 static struct mlx5_aso_age_pool *
11211 flow_dv_age_pool_create(struct rte_eth_dev *dev,
11212 struct mlx5_aso_age_action **age_free)
11214 struct mlx5_priv *priv = dev->data->dev_private;
11215 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11216 struct mlx5_aso_age_pool *pool = NULL;
11217 struct mlx5_devx_obj *obj = NULL;
11220 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
11223 rte_errno = ENODATA;
11224 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
11227 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
11229 claim_zero(mlx5_devx_cmd_destroy(obj));
11230 rte_errno = ENOMEM;
11233 pool->flow_hit_aso_obj = obj;
11234 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
11235 rte_spinlock_lock(&mng->resize_sl);
11236 pool->index = mng->next;
11237 /* Resize pools array if there is no room for the new pool in it. */
11238 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
11239 claim_zero(mlx5_devx_cmd_destroy(obj));
11241 rte_spinlock_unlock(&mng->resize_sl);
11244 mng->pools[pool->index] = pool;
11246 rte_spinlock_unlock(&mng->resize_sl);
11247 /* Assign the first action in the new pool, the rest go to free list. */
11248 *age_free = &pool->actions[0];
11249 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
11250 pool->actions[i].offset = i;
11251 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
11257 * Allocate a ASO aging bit.
11260 * Pointer to the Ethernet device structure.
11261 * @param[out] error
11262 * Pointer to the error structure.
11265 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
11268 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
11270 struct mlx5_priv *priv = dev->data->dev_private;
11271 const struct mlx5_aso_age_pool *pool;
11272 struct mlx5_aso_age_action *age_free = NULL;
11273 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11276 /* Try to get the next free age action bit. */
11277 rte_spinlock_lock(&mng->free_sl);
11278 age_free = LIST_FIRST(&mng->free);
11280 LIST_REMOVE(age_free, next);
11281 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
11282 rte_spinlock_unlock(&mng->free_sl);
11283 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
11284 NULL, "failed to create ASO age pool");
11285 return 0; /* 0 is an error. */
11287 rte_spinlock_unlock(&mng->free_sl);
11288 pool = container_of
11289 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
11290 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
11292 if (!age_free->dr_action) {
11293 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
11297 rte_flow_error_set(error, rte_errno,
11298 RTE_FLOW_ERROR_TYPE_ACTION,
11299 NULL, "failed to get reg_c "
11300 "for ASO flow hit");
11301 return 0; /* 0 is an error. */
11303 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
11304 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
11305 (priv->sh->rx_domain,
11306 pool->flow_hit_aso_obj->obj, age_free->offset,
11307 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
11308 (reg_c - REG_C_0));
11309 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
11310 if (!age_free->dr_action) {
11312 rte_spinlock_lock(&mng->free_sl);
11313 LIST_INSERT_HEAD(&mng->free, age_free, next);
11314 rte_spinlock_unlock(&mng->free_sl);
11315 rte_flow_error_set(error, rte_errno,
11316 RTE_FLOW_ERROR_TYPE_ACTION,
11317 NULL, "failed to create ASO "
11318 "flow hit action");
11319 return 0; /* 0 is an error. */
11322 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
11323 return pool->index | ((age_free->offset + 1) << 16);
11327 * Create a age action using ASO mechanism.
11330 * Pointer to rte_eth_dev structure.
11332 * Pointer to the aging action configuration.
11333 * @param[out] error
11334 * Pointer to the error structure.
11337 * Index to flow counter on success, 0 otherwise.
11340 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
11341 const struct rte_flow_action_age *age,
11342 struct rte_flow_error *error)
11344 uint32_t age_idx = 0;
11345 struct mlx5_aso_age_action *aso_age;
11347 age_idx = flow_dv_aso_age_alloc(dev, error);
11350 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11351 aso_age->age_params.context = age->context;
11352 aso_age->age_params.timeout = age->timeout;
11353 aso_age->age_params.port_id = dev->data->port_id;
11354 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11356 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11362 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
11363 const struct rte_flow_item_integrity *value,
11364 void *headers_m, void *headers_v)
11367 /* application l4_ok filter aggregates all hardware l4 filters
11368 * therefore hw l4_checksum_ok must be implicitly added here.
11370 struct rte_flow_item_integrity local_item;
11372 local_item.l4_csum_ok = 1;
11373 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
11374 local_item.l4_csum_ok);
11375 if (value->l4_ok) {
11376 /* application l4_ok = 1 matches sets both hw flags
11377 * l4_ok and l4_checksum_ok flags to 1.
11379 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11380 l4_checksum_ok, local_item.l4_csum_ok);
11381 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok,
11383 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok,
11386 /* application l4_ok = 0 matches on hw flag
11387 * l4_checksum_ok = 0 only.
11389 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11390 l4_checksum_ok, 0);
11392 } else if (mask->l4_csum_ok) {
11393 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok,
11395 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
11396 value->l4_csum_ok);
11401 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
11402 const struct rte_flow_item_integrity *value,
11403 void *headers_m, void *headers_v,
11407 /* application l3_ok filter aggregates all hardware l3 filters
11408 * therefore hw ipv4_checksum_ok must be implicitly added here.
11410 struct rte_flow_item_integrity local_item;
11412 local_item.ipv4_csum_ok = !!is_ipv4;
11413 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
11414 local_item.ipv4_csum_ok);
11415 if (value->l3_ok) {
11416 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11417 ipv4_checksum_ok, local_item.ipv4_csum_ok);
11418 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok,
11420 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
11423 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
11424 ipv4_checksum_ok, 0);
11426 } else if (mask->ipv4_csum_ok) {
11427 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok,
11428 mask->ipv4_csum_ok);
11429 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
11430 value->ipv4_csum_ok);
11435 flow_dv_translate_item_integrity(void *matcher, void *key,
11436 const struct rte_flow_item *head_item,
11437 const struct rte_flow_item *integrity_item)
11439 const struct rte_flow_item_integrity *mask = integrity_item->mask;
11440 const struct rte_flow_item_integrity *value = integrity_item->spec;
11441 const struct rte_flow_item *tunnel_item, *end_item, *item;
11444 uint32_t l3_protocol;
11449 mask = &rte_flow_item_integrity_mask;
11450 if (value->level > 1) {
11451 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
11453 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
11455 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
11457 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
11459 tunnel_item = mlx5_flow_find_tunnel_item(head_item);
11460 if (value->level > 1) {
11461 /* tunnel item was verified during the item validation */
11462 item = tunnel_item;
11463 end_item = mlx5_find_end_item(tunnel_item);
11466 end_item = tunnel_item ? tunnel_item :
11467 mlx5_find_end_item(integrity_item);
11469 l3_protocol = mask->l3_ok ?
11470 mlx5_flow_locate_proto_l3(&item, end_item) : 0;
11471 flow_dv_translate_integrity_l3(mask, value, headers_m, headers_v,
11472 l3_protocol == RTE_ETHER_TYPE_IPV4);
11473 flow_dv_translate_integrity_l4(mask, value, headers_m, headers_v);
11477 * Prepares DV flow counter with aging configuration.
11478 * Gets it by index when exists, creates a new one when doesn't.
11481 * Pointer to rte_eth_dev structure.
11482 * @param[in] dev_flow
11483 * Pointer to the mlx5_flow.
11484 * @param[in, out] flow
11485 * Pointer to the sub flow.
11487 * Pointer to the counter action configuration.
11489 * Pointer to the aging action configuration.
11490 * @param[out] error
11491 * Pointer to the error structure.
11494 * Pointer to the counter, NULL otherwise.
11496 static struct mlx5_flow_counter *
11497 flow_dv_prepare_counter(struct rte_eth_dev *dev,
11498 struct mlx5_flow *dev_flow,
11499 struct rte_flow *flow,
11500 const struct rte_flow_action_count *count,
11501 const struct rte_flow_action_age *age,
11502 struct rte_flow_error *error)
11504 if (!flow->counter) {
11505 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
11507 if (!flow->counter) {
11508 rte_flow_error_set(error, rte_errno,
11509 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11510 "cannot create counter object.");
11514 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
11518 * Fill the flow with DV spec, lock free
11519 * (mutex should be acquired by caller).
11522 * Pointer to rte_eth_dev structure.
11523 * @param[in, out] dev_flow
11524 * Pointer to the sub flow.
11526 * Pointer to the flow attributes.
11528 * Pointer to the list of items.
11529 * @param[in] actions
11530 * Pointer to the list of actions.
11531 * @param[out] error
11532 * Pointer to the error structure.
11535 * 0 on success, a negative errno value otherwise and rte_errno is set.
11538 flow_dv_translate(struct rte_eth_dev *dev,
11539 struct mlx5_flow *dev_flow,
11540 const struct rte_flow_attr *attr,
11541 const struct rte_flow_item items[],
11542 const struct rte_flow_action actions[],
11543 struct rte_flow_error *error)
11545 struct mlx5_priv *priv = dev->data->dev_private;
11546 struct mlx5_dev_config *dev_conf = &priv->config;
11547 struct rte_flow *flow = dev_flow->flow;
11548 struct mlx5_flow_handle *handle = dev_flow->handle;
11549 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11550 struct mlx5_flow_rss_desc *rss_desc;
11551 uint64_t item_flags = 0;
11552 uint64_t last_item = 0;
11553 uint64_t action_flags = 0;
11554 struct mlx5_flow_dv_matcher matcher = {
11556 .size = sizeof(matcher.mask.buf) -
11557 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11561 bool actions_end = false;
11563 struct mlx5_flow_dv_modify_hdr_resource res;
11564 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11565 sizeof(struct mlx5_modification_cmd) *
11566 (MLX5_MAX_MODIFY_NUM + 1)];
11568 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11569 const struct rte_flow_action_count *count = NULL;
11570 const struct rte_flow_action_age *non_shared_age = NULL;
11571 union flow_dv_attr flow_attr = { .attr = 0 };
11573 union mlx5_flow_tbl_key tbl_key;
11574 uint32_t modify_action_position = UINT32_MAX;
11575 void *match_mask = matcher.mask.buf;
11576 void *match_value = dev_flow->dv.value.buf;
11577 uint8_t next_protocol = 0xff;
11578 struct rte_vlan_hdr vlan = { 0 };
11579 struct mlx5_flow_dv_dest_array_resource mdest_res;
11580 struct mlx5_flow_dv_sample_resource sample_res;
11581 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11582 const struct rte_flow_action_sample *sample = NULL;
11583 struct mlx5_flow_sub_actions_list *sample_act;
11584 uint32_t sample_act_pos = UINT32_MAX;
11585 uint32_t age_act_pos = UINT32_MAX;
11586 uint32_t num_of_dest = 0;
11587 int tmp_actions_n = 0;
11590 const struct mlx5_flow_tunnel *tunnel;
11591 struct flow_grp_info grp_info = {
11592 .external = !!dev_flow->external,
11593 .transfer = !!attr->transfer,
11594 .fdb_def_rule = !!priv->fdb_def_rule,
11595 .skip_scale = dev_flow->skip_scale &
11596 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11598 const struct rte_flow_item *head_item = items;
11601 return rte_flow_error_set(error, ENOMEM,
11602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11604 "failed to push flow workspace");
11605 rss_desc = &wks->rss_desc;
11606 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11607 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11608 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11609 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11610 /* update normal path action resource into last index of array */
11611 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11612 tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11613 flow_items_to_tunnel(items) :
11614 is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11615 flow_actions_to_tunnel(actions) :
11616 dev_flow->tunnel ? dev_flow->tunnel : NULL;
11617 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11618 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11619 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11620 (dev, tunnel, attr, items, actions);
11621 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11625 dev_flow->dv.group = table;
11626 if (attr->transfer)
11627 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11628 /* number of actions must be set to 0 in case of dirty stack. */
11629 mhdr_res->actions_num = 0;
11630 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11632 * do not add decap action if match rule drops packet
11633 * HW rejects rules with decap & drop
11635 * if tunnel match rule was inserted before matching tunnel set
11636 * rule flow table used in the match rule must be registered.
11637 * current implementation handles that in the
11638 * flow_dv_match_register() at the function end.
11640 bool add_decap = true;
11641 const struct rte_flow_action *ptr = actions;
11643 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11644 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11650 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11654 dev_flow->dv.actions[actions_n++] =
11655 dev_flow->dv.encap_decap->action;
11656 action_flags |= MLX5_FLOW_ACTION_DECAP;
11659 for (; !actions_end ; actions++) {
11660 const struct rte_flow_action_queue *queue;
11661 const struct rte_flow_action_rss *rss;
11662 const struct rte_flow_action *action = actions;
11663 const uint8_t *rss_key;
11664 struct mlx5_flow_tbl_resource *tbl;
11665 struct mlx5_aso_age_action *age_act;
11666 struct mlx5_flow_counter *cnt_act;
11667 uint32_t port_id = 0;
11668 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11669 int action_type = actions->type;
11670 const struct rte_flow_action *found_action = NULL;
11671 uint32_t jump_group = 0;
11673 if (!mlx5_flow_os_action_supported(action_type))
11674 return rte_flow_error_set(error, ENOTSUP,
11675 RTE_FLOW_ERROR_TYPE_ACTION,
11677 "action not supported");
11678 switch (action_type) {
11679 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11680 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11682 case RTE_FLOW_ACTION_TYPE_VOID:
11684 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11685 if (flow_dv_translate_action_port_id(dev, action,
11688 port_id_resource.port_id = port_id;
11689 MLX5_ASSERT(!handle->rix_port_id_action);
11690 if (flow_dv_port_id_action_resource_register
11691 (dev, &port_id_resource, dev_flow, error))
11693 dev_flow->dv.actions[actions_n++] =
11694 dev_flow->dv.port_id_action->action;
11695 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11696 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11697 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11700 case RTE_FLOW_ACTION_TYPE_FLAG:
11701 action_flags |= MLX5_FLOW_ACTION_FLAG;
11702 dev_flow->handle->mark = 1;
11703 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11704 struct rte_flow_action_mark mark = {
11705 .id = MLX5_FLOW_MARK_DEFAULT,
11708 if (flow_dv_convert_action_mark(dev, &mark,
11712 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11715 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11717 * Only one FLAG or MARK is supported per device flow
11718 * right now. So the pointer to the tag resource must be
11719 * zero before the register process.
11721 MLX5_ASSERT(!handle->dvh.rix_tag);
11722 if (flow_dv_tag_resource_register(dev, tag_be,
11725 MLX5_ASSERT(dev_flow->dv.tag_resource);
11726 dev_flow->dv.actions[actions_n++] =
11727 dev_flow->dv.tag_resource->action;
11729 case RTE_FLOW_ACTION_TYPE_MARK:
11730 action_flags |= MLX5_FLOW_ACTION_MARK;
11731 dev_flow->handle->mark = 1;
11732 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11733 const struct rte_flow_action_mark *mark =
11734 (const struct rte_flow_action_mark *)
11737 if (flow_dv_convert_action_mark(dev, mark,
11741 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11745 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11746 /* Legacy (non-extensive) MARK action. */
11747 tag_be = mlx5_flow_mark_set
11748 (((const struct rte_flow_action_mark *)
11749 (actions->conf))->id);
11750 MLX5_ASSERT(!handle->dvh.rix_tag);
11751 if (flow_dv_tag_resource_register(dev, tag_be,
11754 MLX5_ASSERT(dev_flow->dv.tag_resource);
11755 dev_flow->dv.actions[actions_n++] =
11756 dev_flow->dv.tag_resource->action;
11758 case RTE_FLOW_ACTION_TYPE_SET_META:
11759 if (flow_dv_convert_action_set_meta
11760 (dev, mhdr_res, attr,
11761 (const struct rte_flow_action_set_meta *)
11762 actions->conf, error))
11764 action_flags |= MLX5_FLOW_ACTION_SET_META;
11766 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11767 if (flow_dv_convert_action_set_tag
11769 (const struct rte_flow_action_set_tag *)
11770 actions->conf, error))
11772 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11774 case RTE_FLOW_ACTION_TYPE_DROP:
11775 action_flags |= MLX5_FLOW_ACTION_DROP;
11776 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11778 case RTE_FLOW_ACTION_TYPE_QUEUE:
11779 queue = actions->conf;
11780 rss_desc->queue_num = 1;
11781 rss_desc->queue[0] = queue->index;
11782 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11783 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11784 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11787 case RTE_FLOW_ACTION_TYPE_RSS:
11788 rss = actions->conf;
11789 memcpy(rss_desc->queue, rss->queue,
11790 rss->queue_num * sizeof(uint16_t));
11791 rss_desc->queue_num = rss->queue_num;
11792 /* NULL RSS key indicates default RSS key. */
11793 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11794 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11796 * rss->level and rss.types should be set in advance
11797 * when expanding items for RSS.
11799 action_flags |= MLX5_FLOW_ACTION_RSS;
11800 dev_flow->handle->fate_action = rss_desc->shared_rss ?
11801 MLX5_FLOW_FATE_SHARED_RSS :
11802 MLX5_FLOW_FATE_QUEUE;
11804 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11805 flow->age = (uint32_t)(uintptr_t)(action->conf);
11806 age_act = flow_aso_age_get_by_idx(dev, flow->age);
11807 __atomic_fetch_add(&age_act->refcnt, 1,
11809 age_act_pos = actions_n++;
11810 action_flags |= MLX5_FLOW_ACTION_AGE;
11812 case RTE_FLOW_ACTION_TYPE_AGE:
11813 non_shared_age = action->conf;
11814 age_act_pos = actions_n++;
11815 action_flags |= MLX5_FLOW_ACTION_AGE;
11817 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
11818 flow->counter = (uint32_t)(uintptr_t)(action->conf);
11819 cnt_act = flow_dv_counter_get_by_idx(dev, flow->counter,
11821 __atomic_fetch_add(&cnt_act->shared_info.refcnt, 1,
11823 /* Save information first, will apply later. */
11824 action_flags |= MLX5_FLOW_ACTION_COUNT;
11826 case RTE_FLOW_ACTION_TYPE_COUNT:
11827 if (!dev_conf->devx) {
11828 return rte_flow_error_set
11830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11832 "count action not supported");
11834 /* Save information first, will apply later. */
11835 count = action->conf;
11836 action_flags |= MLX5_FLOW_ACTION_COUNT;
11838 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11839 dev_flow->dv.actions[actions_n++] =
11840 priv->sh->pop_vlan_action;
11841 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11843 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11844 if (!(action_flags &
11845 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11846 flow_dev_get_vlan_info_from_items(items, &vlan);
11847 vlan.eth_proto = rte_be_to_cpu_16
11848 ((((const struct rte_flow_action_of_push_vlan *)
11849 actions->conf)->ethertype));
11850 found_action = mlx5_flow_find_action
11852 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11854 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11855 found_action = mlx5_flow_find_action
11857 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11859 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11860 if (flow_dv_create_action_push_vlan
11861 (dev, attr, &vlan, dev_flow, error))
11863 dev_flow->dv.actions[actions_n++] =
11864 dev_flow->dv.push_vlan_res->action;
11865 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11867 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11868 /* of_vlan_push action handled this action */
11869 MLX5_ASSERT(action_flags &
11870 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11872 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11873 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11875 flow_dev_get_vlan_info_from_items(items, &vlan);
11876 mlx5_update_vlan_vid_pcp(actions, &vlan);
11877 /* If no VLAN push - this is a modify header action */
11878 if (flow_dv_convert_action_modify_vlan_vid
11879 (mhdr_res, actions, error))
11881 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11883 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11884 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11885 if (flow_dv_create_action_l2_encap(dev, actions,
11890 dev_flow->dv.actions[actions_n++] =
11891 dev_flow->dv.encap_decap->action;
11892 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11893 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11894 sample_act->action_flags |=
11895 MLX5_FLOW_ACTION_ENCAP;
11897 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11898 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11899 if (flow_dv_create_action_l2_decap(dev, dev_flow,
11903 dev_flow->dv.actions[actions_n++] =
11904 dev_flow->dv.encap_decap->action;
11905 action_flags |= MLX5_FLOW_ACTION_DECAP;
11907 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11908 /* Handle encap with preceding decap. */
11909 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11910 if (flow_dv_create_action_raw_encap
11911 (dev, actions, dev_flow, attr, error))
11913 dev_flow->dv.actions[actions_n++] =
11914 dev_flow->dv.encap_decap->action;
11916 /* Handle encap without preceding decap. */
11917 if (flow_dv_create_action_l2_encap
11918 (dev, actions, dev_flow, attr->transfer,
11921 dev_flow->dv.actions[actions_n++] =
11922 dev_flow->dv.encap_decap->action;
11924 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11925 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11926 sample_act->action_flags |=
11927 MLX5_FLOW_ACTION_ENCAP;
11929 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11930 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11932 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11933 if (flow_dv_create_action_l2_decap
11934 (dev, dev_flow, attr->transfer, error))
11936 dev_flow->dv.actions[actions_n++] =
11937 dev_flow->dv.encap_decap->action;
11939 /* If decap is followed by encap, handle it at encap. */
11940 action_flags |= MLX5_FLOW_ACTION_DECAP;
11942 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
11943 dev_flow->dv.actions[actions_n++] =
11944 (void *)(uintptr_t)action->conf;
11945 action_flags |= MLX5_FLOW_ACTION_JUMP;
11947 case RTE_FLOW_ACTION_TYPE_JUMP:
11948 jump_group = ((const struct rte_flow_action_jump *)
11949 action->conf)->group;
11950 grp_info.std_tbl_fix = 0;
11951 if (dev_flow->skip_scale &
11952 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11953 grp_info.skip_scale = 1;
11955 grp_info.skip_scale = 0;
11956 ret = mlx5_flow_group_to_table(dev, tunnel,
11962 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11964 !!dev_flow->external,
11965 tunnel, jump_group, 0,
11968 return rte_flow_error_set
11970 RTE_FLOW_ERROR_TYPE_ACTION,
11972 "cannot create jump action.");
11973 if (flow_dv_jump_tbl_resource_register
11974 (dev, tbl, dev_flow, error)) {
11975 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11976 return rte_flow_error_set
11978 RTE_FLOW_ERROR_TYPE_ACTION,
11980 "cannot create jump action.");
11982 dev_flow->dv.actions[actions_n++] =
11983 dev_flow->dv.jump->action;
11984 action_flags |= MLX5_FLOW_ACTION_JUMP;
11985 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11986 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11989 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11990 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11991 if (flow_dv_convert_action_modify_mac
11992 (mhdr_res, actions, error))
11994 action_flags |= actions->type ==
11995 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11996 MLX5_FLOW_ACTION_SET_MAC_SRC :
11997 MLX5_FLOW_ACTION_SET_MAC_DST;
11999 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
12000 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
12001 if (flow_dv_convert_action_modify_ipv4
12002 (mhdr_res, actions, error))
12004 action_flags |= actions->type ==
12005 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
12006 MLX5_FLOW_ACTION_SET_IPV4_SRC :
12007 MLX5_FLOW_ACTION_SET_IPV4_DST;
12009 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
12010 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
12011 if (flow_dv_convert_action_modify_ipv6
12012 (mhdr_res, actions, error))
12014 action_flags |= actions->type ==
12015 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
12016 MLX5_FLOW_ACTION_SET_IPV6_SRC :
12017 MLX5_FLOW_ACTION_SET_IPV6_DST;
12019 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
12020 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
12021 if (flow_dv_convert_action_modify_tp
12022 (mhdr_res, actions, items,
12023 &flow_attr, dev_flow, !!(action_flags &
12024 MLX5_FLOW_ACTION_DECAP), error))
12026 action_flags |= actions->type ==
12027 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
12028 MLX5_FLOW_ACTION_SET_TP_SRC :
12029 MLX5_FLOW_ACTION_SET_TP_DST;
12031 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
12032 if (flow_dv_convert_action_modify_dec_ttl
12033 (mhdr_res, items, &flow_attr, dev_flow,
12035 MLX5_FLOW_ACTION_DECAP), error))
12037 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
12039 case RTE_FLOW_ACTION_TYPE_SET_TTL:
12040 if (flow_dv_convert_action_modify_ttl
12041 (mhdr_res, actions, items, &flow_attr,
12042 dev_flow, !!(action_flags &
12043 MLX5_FLOW_ACTION_DECAP), error))
12045 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
12047 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
12048 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
12049 if (flow_dv_convert_action_modify_tcp_seq
12050 (mhdr_res, actions, error))
12052 action_flags |= actions->type ==
12053 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
12054 MLX5_FLOW_ACTION_INC_TCP_SEQ :
12055 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
12058 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
12059 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
12060 if (flow_dv_convert_action_modify_tcp_ack
12061 (mhdr_res, actions, error))
12063 action_flags |= actions->type ==
12064 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
12065 MLX5_FLOW_ACTION_INC_TCP_ACK :
12066 MLX5_FLOW_ACTION_DEC_TCP_ACK;
12068 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
12069 if (flow_dv_convert_action_set_reg
12070 (mhdr_res, actions, error))
12072 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12074 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
12075 if (flow_dv_convert_action_copy_mreg
12076 (dev, mhdr_res, actions, error))
12078 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12080 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
12081 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
12082 dev_flow->handle->fate_action =
12083 MLX5_FLOW_FATE_DEFAULT_MISS;
12085 case RTE_FLOW_ACTION_TYPE_METER:
12087 return rte_flow_error_set(error, rte_errno,
12088 RTE_FLOW_ERROR_TYPE_ACTION,
12089 NULL, "Failed to get meter in flow.");
12090 /* Set the meter action. */
12091 dev_flow->dv.actions[actions_n++] =
12092 wks->fm->meter_action;
12093 action_flags |= MLX5_FLOW_ACTION_METER;
12095 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
12096 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
12099 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
12101 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
12102 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
12105 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
12107 case RTE_FLOW_ACTION_TYPE_SAMPLE:
12108 sample_act_pos = actions_n;
12109 sample = (const struct rte_flow_action_sample *)
12112 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
12113 /* put encap action into group if work with port id */
12114 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
12115 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
12116 sample_act->action_flags |=
12117 MLX5_FLOW_ACTION_ENCAP;
12119 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
12120 if (flow_dv_convert_action_modify_field
12121 (dev, mhdr_res, actions, attr, error))
12123 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
12125 case RTE_FLOW_ACTION_TYPE_END:
12126 actions_end = true;
12127 if (mhdr_res->actions_num) {
12128 /* create modify action if needed. */
12129 if (flow_dv_modify_hdr_resource_register
12130 (dev, mhdr_res, dev_flow, error))
12132 dev_flow->dv.actions[modify_action_position] =
12133 handle->dvh.modify_hdr->action;
12136 * Handle AGE and COUNT action by single HW counter
12137 * when they are not shared.
12139 if (action_flags & MLX5_FLOW_ACTION_AGE) {
12140 if ((non_shared_age &&
12141 count && !count->shared) ||
12142 !(priv->sh->flow_hit_aso_en &&
12144 /* Creates age by counters. */
12145 cnt_act = flow_dv_prepare_counter
12152 dev_flow->dv.actions[age_act_pos] =
12156 if (!flow->age && non_shared_age) {
12158 flow_dv_translate_create_aso_age
12163 return rte_flow_error_set
12165 RTE_FLOW_ERROR_TYPE_ACTION,
12167 "can't create ASO age action");
12169 age_act = flow_aso_age_get_by_idx(dev,
12171 dev_flow->dv.actions[age_act_pos] =
12172 age_act->dr_action;
12174 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
12176 * Create one count action, to be used
12177 * by all sub-flows.
12179 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
12184 dev_flow->dv.actions[actions_n++] =
12190 if (mhdr_res->actions_num &&
12191 modify_action_position == UINT32_MAX)
12192 modify_action_position = actions_n++;
12194 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
12195 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
12196 int item_type = items->type;
12198 if (!mlx5_flow_os_item_supported(item_type))
12199 return rte_flow_error_set(error, ENOTSUP,
12200 RTE_FLOW_ERROR_TYPE_ITEM,
12201 NULL, "item not supported");
12202 switch (item_type) {
12203 case RTE_FLOW_ITEM_TYPE_PORT_ID:
12204 flow_dv_translate_item_port_id
12205 (dev, match_mask, match_value, items, attr);
12206 last_item = MLX5_FLOW_ITEM_PORT_ID;
12208 case RTE_FLOW_ITEM_TYPE_ETH:
12209 flow_dv_translate_item_eth(match_mask, match_value,
12211 dev_flow->dv.group);
12212 matcher.priority = action_flags &
12213 MLX5_FLOW_ACTION_DEFAULT_MISS &&
12214 !dev_flow->external ?
12215 MLX5_PRIORITY_MAP_L3 :
12216 MLX5_PRIORITY_MAP_L2;
12217 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
12218 MLX5_FLOW_LAYER_OUTER_L2;
12220 case RTE_FLOW_ITEM_TYPE_VLAN:
12221 flow_dv_translate_item_vlan(dev_flow,
12222 match_mask, match_value,
12224 dev_flow->dv.group);
12225 matcher.priority = MLX5_PRIORITY_MAP_L2;
12226 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
12227 MLX5_FLOW_LAYER_INNER_VLAN) :
12228 (MLX5_FLOW_LAYER_OUTER_L2 |
12229 MLX5_FLOW_LAYER_OUTER_VLAN);
12231 case RTE_FLOW_ITEM_TYPE_IPV4:
12232 mlx5_flow_tunnel_ip_check(items, next_protocol,
12233 &item_flags, &tunnel);
12234 flow_dv_translate_item_ipv4(match_mask, match_value,
12236 dev_flow->dv.group);
12237 matcher.priority = MLX5_PRIORITY_MAP_L3;
12238 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
12239 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
12240 if (items->mask != NULL &&
12241 ((const struct rte_flow_item_ipv4 *)
12242 items->mask)->hdr.next_proto_id) {
12244 ((const struct rte_flow_item_ipv4 *)
12245 (items->spec))->hdr.next_proto_id;
12247 ((const struct rte_flow_item_ipv4 *)
12248 (items->mask))->hdr.next_proto_id;
12250 /* Reset for inner layer. */
12251 next_protocol = 0xff;
12254 case RTE_FLOW_ITEM_TYPE_IPV6:
12255 mlx5_flow_tunnel_ip_check(items, next_protocol,
12256 &item_flags, &tunnel);
12257 flow_dv_translate_item_ipv6(match_mask, match_value,
12259 dev_flow->dv.group);
12260 matcher.priority = MLX5_PRIORITY_MAP_L3;
12261 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
12262 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
12263 if (items->mask != NULL &&
12264 ((const struct rte_flow_item_ipv6 *)
12265 items->mask)->hdr.proto) {
12267 ((const struct rte_flow_item_ipv6 *)
12268 items->spec)->hdr.proto;
12270 ((const struct rte_flow_item_ipv6 *)
12271 items->mask)->hdr.proto;
12273 /* Reset for inner layer. */
12274 next_protocol = 0xff;
12277 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
12278 flow_dv_translate_item_ipv6_frag_ext(match_mask,
12281 last_item = tunnel ?
12282 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
12283 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
12284 if (items->mask != NULL &&
12285 ((const struct rte_flow_item_ipv6_frag_ext *)
12286 items->mask)->hdr.next_header) {
12288 ((const struct rte_flow_item_ipv6_frag_ext *)
12289 items->spec)->hdr.next_header;
12291 ((const struct rte_flow_item_ipv6_frag_ext *)
12292 items->mask)->hdr.next_header;
12294 /* Reset for inner layer. */
12295 next_protocol = 0xff;
12298 case RTE_FLOW_ITEM_TYPE_TCP:
12299 flow_dv_translate_item_tcp(match_mask, match_value,
12301 matcher.priority = MLX5_PRIORITY_MAP_L4;
12302 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
12303 MLX5_FLOW_LAYER_OUTER_L4_TCP;
12305 case RTE_FLOW_ITEM_TYPE_UDP:
12306 flow_dv_translate_item_udp(match_mask, match_value,
12308 matcher.priority = MLX5_PRIORITY_MAP_L4;
12309 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
12310 MLX5_FLOW_LAYER_OUTER_L4_UDP;
12312 case RTE_FLOW_ITEM_TYPE_GRE:
12313 flow_dv_translate_item_gre(match_mask, match_value,
12315 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12316 last_item = MLX5_FLOW_LAYER_GRE;
12318 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
12319 flow_dv_translate_item_gre_key(match_mask,
12320 match_value, items);
12321 last_item = MLX5_FLOW_LAYER_GRE_KEY;
12323 case RTE_FLOW_ITEM_TYPE_NVGRE:
12324 flow_dv_translate_item_nvgre(match_mask, match_value,
12326 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12327 last_item = MLX5_FLOW_LAYER_GRE;
12329 case RTE_FLOW_ITEM_TYPE_VXLAN:
12330 flow_dv_translate_item_vxlan(match_mask, match_value,
12332 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12333 last_item = MLX5_FLOW_LAYER_VXLAN;
12335 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
12336 flow_dv_translate_item_vxlan_gpe(match_mask,
12337 match_value, items,
12339 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12340 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
12342 case RTE_FLOW_ITEM_TYPE_GENEVE:
12343 flow_dv_translate_item_geneve(match_mask, match_value,
12345 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12346 last_item = MLX5_FLOW_LAYER_GENEVE;
12348 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
12349 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
12353 return rte_flow_error_set(error, -ret,
12354 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
12355 "cannot create GENEVE TLV option");
12356 flow->geneve_tlv_option = 1;
12357 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
12359 case RTE_FLOW_ITEM_TYPE_MPLS:
12360 flow_dv_translate_item_mpls(match_mask, match_value,
12361 items, last_item, tunnel);
12362 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12363 last_item = MLX5_FLOW_LAYER_MPLS;
12365 case RTE_FLOW_ITEM_TYPE_MARK:
12366 flow_dv_translate_item_mark(dev, match_mask,
12367 match_value, items);
12368 last_item = MLX5_FLOW_ITEM_MARK;
12370 case RTE_FLOW_ITEM_TYPE_META:
12371 flow_dv_translate_item_meta(dev, match_mask,
12372 match_value, attr, items);
12373 last_item = MLX5_FLOW_ITEM_METADATA;
12375 case RTE_FLOW_ITEM_TYPE_ICMP:
12376 flow_dv_translate_item_icmp(match_mask, match_value,
12378 last_item = MLX5_FLOW_LAYER_ICMP;
12380 case RTE_FLOW_ITEM_TYPE_ICMP6:
12381 flow_dv_translate_item_icmp6(match_mask, match_value,
12383 last_item = MLX5_FLOW_LAYER_ICMP6;
12385 case RTE_FLOW_ITEM_TYPE_TAG:
12386 flow_dv_translate_item_tag(dev, match_mask,
12387 match_value, items);
12388 last_item = MLX5_FLOW_ITEM_TAG;
12390 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
12391 flow_dv_translate_mlx5_item_tag(dev, match_mask,
12392 match_value, items);
12393 last_item = MLX5_FLOW_ITEM_TAG;
12395 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
12396 flow_dv_translate_item_tx_queue(dev, match_mask,
12399 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
12401 case RTE_FLOW_ITEM_TYPE_GTP:
12402 flow_dv_translate_item_gtp(match_mask, match_value,
12404 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
12405 last_item = MLX5_FLOW_LAYER_GTP;
12407 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
12408 ret = flow_dv_translate_item_gtp_psc(match_mask,
12412 return rte_flow_error_set(error, -ret,
12413 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
12414 "cannot create GTP PSC item");
12415 last_item = MLX5_FLOW_LAYER_GTP_PSC;
12417 case RTE_FLOW_ITEM_TYPE_ECPRI:
12418 if (!mlx5_flex_parser_ecpri_exist(dev)) {
12419 /* Create it only the first time to be used. */
12420 ret = mlx5_flex_parser_ecpri_alloc(dev);
12422 return rte_flow_error_set
12424 RTE_FLOW_ERROR_TYPE_ITEM,
12426 "cannot create eCPRI parser");
12428 /* Adjust the length matcher and device flow value. */
12429 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
12430 dev_flow->dv.value.size =
12431 MLX5_ST_SZ_BYTES(fte_match_param);
12432 flow_dv_translate_item_ecpri(dev, match_mask,
12433 match_value, items);
12434 /* No other protocol should follow eCPRI layer. */
12435 last_item = MLX5_FLOW_LAYER_ECPRI;
12437 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
12438 flow_dv_translate_item_integrity(match_mask,
12445 item_flags |= last_item;
12448 * When E-Switch mode is enabled, we have two cases where we need to
12449 * set the source port manually.
12450 * The first one, is in case of Nic steering rule, and the second is
12451 * E-Switch rule where no port_id item was found. In both cases
12452 * the source port is set according the current port in use.
12454 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
12455 (priv->representor || priv->master)) {
12456 if (flow_dv_translate_item_port_id(dev, match_mask,
12457 match_value, NULL, attr))
12460 #ifdef RTE_LIBRTE_MLX5_DEBUG
12461 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
12462 dev_flow->dv.value.buf));
12465 * Layers may be already initialized from prefix flow if this dev_flow
12466 * is the suffix flow.
12468 handle->layers |= item_flags;
12469 if (action_flags & MLX5_FLOW_ACTION_RSS)
12470 flow_dv_hashfields_set(dev_flow, rss_desc);
12471 /* If has RSS action in the sample action, the Sample/Mirror resource
12472 * should be registered after the hash filed be update.
12474 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
12475 ret = flow_dv_translate_action_sample(dev,
12484 ret = flow_dv_create_action_sample(dev,
12493 return rte_flow_error_set
12495 RTE_FLOW_ERROR_TYPE_ACTION,
12497 "cannot create sample action");
12498 if (num_of_dest > 1) {
12499 dev_flow->dv.actions[sample_act_pos] =
12500 dev_flow->dv.dest_array_res->action;
12502 dev_flow->dv.actions[sample_act_pos] =
12503 dev_flow->dv.sample_res->verbs_action;
12507 * For multiple destination (sample action with ratio=1), the encap
12508 * action and port id action will be combined into group action.
12509 * So need remove the original these actions in the flow and only
12510 * use the sample action instead of.
12512 if (num_of_dest > 1 &&
12513 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
12515 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12517 for (i = 0; i < actions_n; i++) {
12518 if ((sample_act->dr_encap_action &&
12519 sample_act->dr_encap_action ==
12520 dev_flow->dv.actions[i]) ||
12521 (sample_act->dr_port_id_action &&
12522 sample_act->dr_port_id_action ==
12523 dev_flow->dv.actions[i]) ||
12524 (sample_act->dr_jump_action &&
12525 sample_act->dr_jump_action ==
12526 dev_flow->dv.actions[i]))
12528 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12530 memcpy((void *)dev_flow->dv.actions,
12531 (void *)temp_actions,
12532 tmp_actions_n * sizeof(void *));
12533 actions_n = tmp_actions_n;
12535 dev_flow->dv.actions_n = actions_n;
12536 dev_flow->act_flags = action_flags;
12537 if (wks->skip_matcher_reg)
12539 /* Register matcher. */
12540 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12541 matcher.mask.size);
12542 matcher.priority = mlx5_get_matcher_priority(dev, attr,
12544 /* reserved field no needs to be set to 0 here. */
12545 tbl_key.is_fdb = attr->transfer;
12546 tbl_key.is_egress = attr->egress;
12547 tbl_key.level = dev_flow->dv.group;
12548 tbl_key.id = dev_flow->dv.table_id;
12549 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12550 tunnel, attr->group, error))
12556 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12559 * @param[in, out] action
12560 * Shred RSS action holding hash RX queue objects.
12561 * @param[in] hash_fields
12562 * Defines combination of packet fields to participate in RX hash.
12563 * @param[in] tunnel
12565 * @param[in] hrxq_idx
12566 * Hash RX queue index to set.
12569 * 0 on success, otherwise negative errno value.
12572 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12573 const uint64_t hash_fields,
12576 uint32_t *hrxqs = action->hrxq;
12578 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12579 case MLX5_RSS_HASH_IPV4:
12580 /* fall-through. */
12581 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12582 /* fall-through. */
12583 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12584 hrxqs[0] = hrxq_idx;
12586 case MLX5_RSS_HASH_IPV4_TCP:
12587 /* fall-through. */
12588 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12589 /* fall-through. */
12590 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12591 hrxqs[1] = hrxq_idx;
12593 case MLX5_RSS_HASH_IPV4_UDP:
12594 /* fall-through. */
12595 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12596 /* fall-through. */
12597 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12598 hrxqs[2] = hrxq_idx;
12600 case MLX5_RSS_HASH_IPV6:
12601 /* fall-through. */
12602 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12603 /* fall-through. */
12604 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12605 hrxqs[3] = hrxq_idx;
12607 case MLX5_RSS_HASH_IPV6_TCP:
12608 /* fall-through. */
12609 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12610 /* fall-through. */
12611 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12612 hrxqs[4] = hrxq_idx;
12614 case MLX5_RSS_HASH_IPV6_UDP:
12615 /* fall-through. */
12616 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12617 /* fall-through. */
12618 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12619 hrxqs[5] = hrxq_idx;
12621 case MLX5_RSS_HASH_NONE:
12622 hrxqs[6] = hrxq_idx;
12630 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12634 * Pointer to the Ethernet device structure.
12636 * Shared RSS action ID holding hash RX queue objects.
12637 * @param[in] hash_fields
12638 * Defines combination of packet fields to participate in RX hash.
12639 * @param[in] tunnel
12643 * Valid hash RX queue index, otherwise 0.
12646 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12647 const uint64_t hash_fields)
12649 struct mlx5_priv *priv = dev->data->dev_private;
12650 struct mlx5_shared_action_rss *shared_rss =
12651 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12652 const uint32_t *hrxqs = shared_rss->hrxq;
12654 switch (hash_fields & ~IBV_RX_HASH_INNER) {
12655 case MLX5_RSS_HASH_IPV4:
12656 /* fall-through. */
12657 case MLX5_RSS_HASH_IPV4_DST_ONLY:
12658 /* fall-through. */
12659 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12661 case MLX5_RSS_HASH_IPV4_TCP:
12662 /* fall-through. */
12663 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12664 /* fall-through. */
12665 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12667 case MLX5_RSS_HASH_IPV4_UDP:
12668 /* fall-through. */
12669 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12670 /* fall-through. */
12671 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12673 case MLX5_RSS_HASH_IPV6:
12674 /* fall-through. */
12675 case MLX5_RSS_HASH_IPV6_DST_ONLY:
12676 /* fall-through. */
12677 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12679 case MLX5_RSS_HASH_IPV6_TCP:
12680 /* fall-through. */
12681 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12682 /* fall-through. */
12683 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12685 case MLX5_RSS_HASH_IPV6_UDP:
12686 /* fall-through. */
12687 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12688 /* fall-through. */
12689 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12691 case MLX5_RSS_HASH_NONE:
12700 * Apply the flow to the NIC, lock free,
12701 * (mutex should be acquired by caller).
12704 * Pointer to the Ethernet device structure.
12705 * @param[in, out] flow
12706 * Pointer to flow structure.
12707 * @param[out] error
12708 * Pointer to error structure.
12711 * 0 on success, a negative errno value otherwise and rte_errno is set.
12714 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12715 struct rte_flow_error *error)
12717 struct mlx5_flow_dv_workspace *dv;
12718 struct mlx5_flow_handle *dh;
12719 struct mlx5_flow_handle_dv *dv_h;
12720 struct mlx5_flow *dev_flow;
12721 struct mlx5_priv *priv = dev->data->dev_private;
12722 uint32_t handle_idx;
12726 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12727 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12730 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12731 dev_flow = &wks->flows[idx];
12732 dv = &dev_flow->dv;
12733 dh = dev_flow->handle;
12736 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12737 if (dv->transfer) {
12738 MLX5_ASSERT(priv->sh->dr_drop_action);
12739 dv->actions[n++] = priv->sh->dr_drop_action;
12741 #ifdef HAVE_MLX5DV_DR
12742 /* DR supports drop action placeholder. */
12743 MLX5_ASSERT(priv->sh->dr_drop_action);
12744 dv->actions[n++] = priv->sh->dr_drop_action;
12746 /* For DV we use the explicit drop queue. */
12747 MLX5_ASSERT(priv->drop_queue.hrxq);
12749 priv->drop_queue.hrxq->action;
12752 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12753 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12754 struct mlx5_hrxq *hrxq;
12757 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12763 "cannot get hash queue");
12766 dh->rix_hrxq = hrxq_idx;
12767 dv->actions[n++] = hrxq->action;
12768 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12769 struct mlx5_hrxq *hrxq = NULL;
12772 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12773 rss_desc->shared_rss,
12774 dev_flow->hash_fields);
12776 hrxq = mlx5_ipool_get
12777 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12782 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12783 "cannot get hash queue");
12786 dh->rix_srss = rss_desc->shared_rss;
12787 dv->actions[n++] = hrxq->action;
12788 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12789 if (!priv->sh->default_miss_action) {
12792 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12793 "default miss action not be created.");
12796 dv->actions[n++] = priv->sh->default_miss_action;
12798 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12799 (void *)&dv->value, n,
12800 dv->actions, &dh->drv_flow);
12802 rte_flow_error_set(error, errno,
12803 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12805 "hardware refuses to create flow");
12808 if (priv->vmwa_context &&
12809 dh->vf_vlan.tag && !dh->vf_vlan.created) {
12811 * The rule contains the VLAN pattern.
12812 * For VF we are going to create VLAN
12813 * interface to make hypervisor set correct
12814 * e-Switch vport context.
12816 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12821 err = rte_errno; /* Save rte_errno before cleanup. */
12822 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12823 handle_idx, dh, next) {
12824 /* hrxq is union, don't clear it if the flag is not set. */
12825 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12826 mlx5_hrxq_release(dev, dh->rix_hrxq);
12828 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12831 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12832 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12834 rte_errno = err; /* Restore rte_errno. */
12839 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12840 struct mlx5_cache_entry *entry)
12842 struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12845 claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12850 * Release the flow matcher.
12853 * Pointer to Ethernet device.
12855 * Index to port ID action resource.
12858 * 1 while a reference on it exists, 0 when freed.
12861 flow_dv_matcher_release(struct rte_eth_dev *dev,
12862 struct mlx5_flow_handle *handle)
12864 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12865 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12866 typeof(*tbl), tbl);
12869 MLX5_ASSERT(matcher->matcher_object);
12870 ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12871 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12876 * Release encap_decap resource.
12879 * Pointer to the hash list.
12881 * Pointer to exist resource entry object.
12884 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12885 struct mlx5_hlist_entry *entry)
12887 struct mlx5_dev_ctx_shared *sh = list->ctx;
12888 struct mlx5_flow_dv_encap_decap_resource *res =
12889 container_of(entry, typeof(*res), entry);
12891 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12892 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12896 * Release an encap/decap resource.
12899 * Pointer to Ethernet device.
12900 * @param encap_decap_idx
12901 * Index of encap decap resource.
12904 * 1 while a reference on it exists, 0 when freed.
12907 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12908 uint32_t encap_decap_idx)
12910 struct mlx5_priv *priv = dev->data->dev_private;
12911 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12913 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12915 if (!cache_resource)
12917 MLX5_ASSERT(cache_resource->action);
12918 return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12919 &cache_resource->entry);
12923 * Release an jump to table action resource.
12926 * Pointer to Ethernet device.
12928 * Index to the jump action resource.
12931 * 1 while a reference on it exists, 0 when freed.
12934 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12937 struct mlx5_priv *priv = dev->data->dev_private;
12938 struct mlx5_flow_tbl_data_entry *tbl_data;
12940 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12944 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12948 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12949 struct mlx5_hlist_entry *entry)
12951 struct mlx5_flow_dv_modify_hdr_resource *res =
12952 container_of(entry, typeof(*res), entry);
12954 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12959 * Release a modify-header resource.
12962 * Pointer to Ethernet device.
12964 * Pointer to mlx5_flow_handle.
12967 * 1 while a reference on it exists, 0 when freed.
12970 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12971 struct mlx5_flow_handle *handle)
12973 struct mlx5_priv *priv = dev->data->dev_private;
12974 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12976 MLX5_ASSERT(entry->action);
12977 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12981 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12982 struct mlx5_cache_entry *entry)
12984 struct mlx5_dev_ctx_shared *sh = list->ctx;
12985 struct mlx5_flow_dv_port_id_action_resource *cache =
12986 container_of(entry, typeof(*cache), entry);
12988 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12989 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12993 * Release port ID action resource.
12996 * Pointer to Ethernet device.
12998 * Pointer to mlx5_flow_handle.
13001 * 1 while a reference on it exists, 0 when freed.
13004 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
13007 struct mlx5_priv *priv = dev->data->dev_private;
13008 struct mlx5_flow_dv_port_id_action_resource *cache;
13010 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
13013 MLX5_ASSERT(cache->action);
13014 return mlx5_cache_unregister(&priv->sh->port_id_action_list,
13019 * Release shared RSS action resource.
13022 * Pointer to Ethernet device.
13024 * Shared RSS action index.
13027 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
13029 struct mlx5_priv *priv = dev->data->dev_private;
13030 struct mlx5_shared_action_rss *shared_rss;
13032 shared_rss = mlx5_ipool_get
13033 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
13034 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13038 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
13039 struct mlx5_cache_entry *entry)
13041 struct mlx5_dev_ctx_shared *sh = list->ctx;
13042 struct mlx5_flow_dv_push_vlan_action_resource *cache =
13043 container_of(entry, typeof(*cache), entry);
13045 claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
13046 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
13050 * Release push vlan action resource.
13053 * Pointer to Ethernet device.
13055 * Pointer to mlx5_flow_handle.
13058 * 1 while a reference on it exists, 0 when freed.
13061 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
13062 struct mlx5_flow_handle *handle)
13064 struct mlx5_priv *priv = dev->data->dev_private;
13065 struct mlx5_flow_dv_push_vlan_action_resource *cache;
13066 uint32_t idx = handle->dvh.rix_push_vlan;
13068 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
13071 MLX5_ASSERT(cache->action);
13072 return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
13077 * Release the fate resource.
13080 * Pointer to Ethernet device.
13082 * Pointer to mlx5_flow_handle.
13085 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
13086 struct mlx5_flow_handle *handle)
13088 if (!handle->rix_fate)
13090 switch (handle->fate_action) {
13091 case MLX5_FLOW_FATE_QUEUE:
13092 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
13093 mlx5_hrxq_release(dev, handle->rix_hrxq);
13095 case MLX5_FLOW_FATE_JUMP:
13096 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
13098 case MLX5_FLOW_FATE_PORT_ID:
13099 flow_dv_port_id_action_resource_release(dev,
13100 handle->rix_port_id_action);
13103 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
13106 handle->rix_fate = 0;
13110 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
13111 struct mlx5_cache_entry *entry)
13113 struct mlx5_flow_dv_sample_resource *cache_resource =
13114 container_of(entry, typeof(*cache_resource), entry);
13115 struct rte_eth_dev *dev = cache_resource->dev;
13116 struct mlx5_priv *priv = dev->data->dev_private;
13118 if (cache_resource->verbs_action)
13119 claim_zero(mlx5_flow_os_destroy_flow_action
13120 (cache_resource->verbs_action));
13121 if (cache_resource->normal_path_tbl)
13122 flow_dv_tbl_resource_release(MLX5_SH(dev),
13123 cache_resource->normal_path_tbl);
13124 flow_dv_sample_sub_actions_release(dev,
13125 &cache_resource->sample_idx);
13126 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
13127 cache_resource->idx);
13128 DRV_LOG(DEBUG, "sample resource %p: removed",
13129 (void *)cache_resource);
13133 * Release an sample resource.
13136 * Pointer to Ethernet device.
13138 * Pointer to mlx5_flow_handle.
13141 * 1 while a reference on it exists, 0 when freed.
13144 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
13145 struct mlx5_flow_handle *handle)
13147 struct mlx5_priv *priv = dev->data->dev_private;
13148 struct mlx5_flow_dv_sample_resource *cache_resource;
13150 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
13151 handle->dvh.rix_sample);
13152 if (!cache_resource)
13154 MLX5_ASSERT(cache_resource->verbs_action);
13155 return mlx5_cache_unregister(&priv->sh->sample_action_list,
13156 &cache_resource->entry);
13160 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
13161 struct mlx5_cache_entry *entry)
13163 struct mlx5_flow_dv_dest_array_resource *cache_resource =
13164 container_of(entry, typeof(*cache_resource), entry);
13165 struct rte_eth_dev *dev = cache_resource->dev;
13166 struct mlx5_priv *priv = dev->data->dev_private;
13169 MLX5_ASSERT(cache_resource->action);
13170 if (cache_resource->action)
13171 claim_zero(mlx5_flow_os_destroy_flow_action
13172 (cache_resource->action));
13173 for (; i < cache_resource->num_of_dest; i++)
13174 flow_dv_sample_sub_actions_release(dev,
13175 &cache_resource->sample_idx[i]);
13176 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
13177 cache_resource->idx);
13178 DRV_LOG(DEBUG, "destination array resource %p: removed",
13179 (void *)cache_resource);
13183 * Release an destination array resource.
13186 * Pointer to Ethernet device.
13188 * Pointer to mlx5_flow_handle.
13191 * 1 while a reference on it exists, 0 when freed.
13194 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
13195 struct mlx5_flow_handle *handle)
13197 struct mlx5_priv *priv = dev->data->dev_private;
13198 struct mlx5_flow_dv_dest_array_resource *cache;
13200 cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
13201 handle->dvh.rix_dest_array);
13204 MLX5_ASSERT(cache->action);
13205 return mlx5_cache_unregister(&priv->sh->dest_array_list,
13210 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
13212 struct mlx5_priv *priv = dev->data->dev_private;
13213 struct mlx5_dev_ctx_shared *sh = priv->sh;
13214 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
13215 sh->geneve_tlv_option_resource;
13216 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
13217 if (geneve_opt_resource) {
13218 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
13219 __ATOMIC_RELAXED))) {
13220 claim_zero(mlx5_devx_cmd_destroy
13221 (geneve_opt_resource->obj));
13222 mlx5_free(sh->geneve_tlv_option_resource);
13223 sh->geneve_tlv_option_resource = NULL;
13226 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
13230 * Remove the flow from the NIC but keeps it in memory.
13231 * Lock free, (mutex should be acquired by caller).
13234 * Pointer to Ethernet device.
13235 * @param[in, out] flow
13236 * Pointer to flow structure.
13239 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
13241 struct mlx5_flow_handle *dh;
13242 uint32_t handle_idx;
13243 struct mlx5_priv *priv = dev->data->dev_private;
13247 handle_idx = flow->dev_handles;
13248 while (handle_idx) {
13249 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
13253 if (dh->drv_flow) {
13254 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
13255 dh->drv_flow = NULL;
13257 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
13258 flow_dv_fate_resource_release(dev, dh);
13259 if (dh->vf_vlan.tag && dh->vf_vlan.created)
13260 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
13261 handle_idx = dh->next.next;
13266 * Remove the flow from the NIC and the memory.
13267 * Lock free, (mutex should be acquired by caller).
13270 * Pointer to the Ethernet device structure.
13271 * @param[in, out] flow
13272 * Pointer to flow structure.
13275 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
13277 struct mlx5_flow_handle *dev_handle;
13278 struct mlx5_priv *priv = dev->data->dev_private;
13279 struct mlx5_flow_meter_info *fm = NULL;
13284 flow_dv_remove(dev, flow);
13285 if (flow->counter) {
13286 flow_dv_counter_free(dev, flow->counter);
13290 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
13292 mlx5_flow_meter_detach(priv, fm);
13296 flow_dv_aso_age_release(dev, flow->age);
13297 if (flow->geneve_tlv_option) {
13298 flow_dv_geneve_tlv_option_resource_release(dev);
13299 flow->geneve_tlv_option = 0;
13301 while (flow->dev_handles) {
13302 uint32_t tmp_idx = flow->dev_handles;
13304 dev_handle = mlx5_ipool_get(priv->sh->ipool
13305 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
13308 flow->dev_handles = dev_handle->next.next;
13309 if (dev_handle->dvh.matcher)
13310 flow_dv_matcher_release(dev, dev_handle);
13311 if (dev_handle->dvh.rix_sample)
13312 flow_dv_sample_resource_release(dev, dev_handle);
13313 if (dev_handle->dvh.rix_dest_array)
13314 flow_dv_dest_array_resource_release(dev, dev_handle);
13315 if (dev_handle->dvh.rix_encap_decap)
13316 flow_dv_encap_decap_resource_release(dev,
13317 dev_handle->dvh.rix_encap_decap);
13318 if (dev_handle->dvh.modify_hdr)
13319 flow_dv_modify_hdr_resource_release(dev, dev_handle);
13320 if (dev_handle->dvh.rix_push_vlan)
13321 flow_dv_push_vlan_action_resource_release(dev,
13323 if (dev_handle->dvh.rix_tag)
13324 flow_dv_tag_release(dev,
13325 dev_handle->dvh.rix_tag);
13326 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
13327 flow_dv_fate_resource_release(dev, dev_handle);
13329 srss = dev_handle->rix_srss;
13330 if (fm && dev_handle->is_meter_flow_id &&
13331 dev_handle->split_flow_id)
13332 mlx5_ipool_free(fm->flow_ipool,
13333 dev_handle->split_flow_id);
13334 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
13338 flow_dv_shared_rss_action_release(dev, srss);
13342 * Release array of hash RX queue objects.
13346 * Pointer to the Ethernet device structure.
13347 * @param[in, out] hrxqs
13348 * Array of hash RX queue objects.
13351 * Total number of references to hash RX queue objects in *hrxqs* array
13352 * after this operation.
13355 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
13356 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
13361 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
13362 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
13372 * Release all hash RX queue objects representing shared RSS action.
13375 * Pointer to the Ethernet device structure.
13376 * @param[in, out] action
13377 * Shared RSS action to remove hash RX queue objects from.
13380 * Total number of references to hash RX queue objects stored in *action*
13381 * after this operation.
13382 * Expected to be 0 if no external references held.
13385 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
13386 struct mlx5_shared_action_rss *shared_rss)
13388 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
13392 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
13395 * Only one hash value is available for one L3+L4 combination:
13397 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
13398 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
13399 * same slot in mlx5_rss_hash_fields.
13402 * Pointer to the shared action RSS conf.
13403 * @param[in, out] hash_field
13404 * hash_field variable needed to be adjusted.
13410 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
13411 uint64_t *hash_field)
13413 uint64_t rss_types = rss->origin.types;
13415 switch (*hash_field & ~IBV_RX_HASH_INNER) {
13416 case MLX5_RSS_HASH_IPV4:
13417 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
13418 *hash_field &= ~MLX5_RSS_HASH_IPV4;
13419 if (rss_types & ETH_RSS_L3_DST_ONLY)
13420 *hash_field |= IBV_RX_HASH_DST_IPV4;
13421 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
13422 *hash_field |= IBV_RX_HASH_SRC_IPV4;
13424 *hash_field |= MLX5_RSS_HASH_IPV4;
13427 case MLX5_RSS_HASH_IPV6:
13428 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
13429 *hash_field &= ~MLX5_RSS_HASH_IPV6;
13430 if (rss_types & ETH_RSS_L3_DST_ONLY)
13431 *hash_field |= IBV_RX_HASH_DST_IPV6;
13432 else if (rss_types & ETH_RSS_L3_SRC_ONLY)
13433 *hash_field |= IBV_RX_HASH_SRC_IPV6;
13435 *hash_field |= MLX5_RSS_HASH_IPV6;
13438 case MLX5_RSS_HASH_IPV4_UDP:
13439 /* fall-through. */
13440 case MLX5_RSS_HASH_IPV6_UDP:
13441 if (rss_types & ETH_RSS_UDP) {
13442 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
13443 if (rss_types & ETH_RSS_L4_DST_ONLY)
13444 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
13445 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
13446 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
13448 *hash_field |= MLX5_UDP_IBV_RX_HASH;
13451 case MLX5_RSS_HASH_IPV4_TCP:
13452 /* fall-through. */
13453 case MLX5_RSS_HASH_IPV6_TCP:
13454 if (rss_types & ETH_RSS_TCP) {
13455 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
13456 if (rss_types & ETH_RSS_L4_DST_ONLY)
13457 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
13458 else if (rss_types & ETH_RSS_L4_SRC_ONLY)
13459 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
13461 *hash_field |= MLX5_TCP_IBV_RX_HASH;
13470 * Setup shared RSS action.
13471 * Prepare set of hash RX queue objects sufficient to handle all valid
13472 * hash_fields combinations (see enum ibv_rx_hash_fields).
13475 * Pointer to the Ethernet device structure.
13476 * @param[in] action_idx
13477 * Shared RSS action ipool index.
13478 * @param[in, out] action
13479 * Partially initialized shared RSS action.
13480 * @param[out] error
13481 * Perform verbose error reporting if not NULL. Initialized in case of
13485 * 0 on success, otherwise negative errno value.
13488 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
13489 uint32_t action_idx,
13490 struct mlx5_shared_action_rss *shared_rss,
13491 struct rte_flow_error *error)
13493 struct mlx5_flow_rss_desc rss_desc = { 0 };
13497 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
13498 return rte_flow_error_set(error, rte_errno,
13499 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13500 "cannot setup indirection table");
13502 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
13503 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
13504 rss_desc.const_q = shared_rss->origin.queue;
13505 rss_desc.queue_num = shared_rss->origin.queue_num;
13506 /* Set non-zero value to indicate a shared RSS. */
13507 rss_desc.shared_rss = action_idx;
13508 rss_desc.ind_tbl = shared_rss->ind_tbl;
13509 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
13511 uint64_t hash_fields = mlx5_rss_hash_fields[i];
13514 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
13515 if (shared_rss->origin.level > 1) {
13516 hash_fields |= IBV_RX_HASH_INNER;
13519 rss_desc.tunnel = tunnel;
13520 rss_desc.hash_fields = hash_fields;
13521 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
13525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13526 "cannot get hash queue");
13527 goto error_hrxq_new;
13529 err = __flow_dv_action_rss_hrxq_set
13530 (shared_rss, hash_fields, hrxq_idx);
13536 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13537 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13538 shared_rss->ind_tbl = NULL;
13544 * Create shared RSS action.
13547 * Pointer to the Ethernet device structure.
13549 * Shared action configuration.
13551 * RSS action specification used to create shared action.
13552 * @param[out] error
13553 * Perform verbose error reporting if not NULL. Initialized in case of
13557 * A valid shared action ID in case of success, 0 otherwise and
13558 * rte_errno is set.
13561 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13562 const struct rte_flow_indir_action_conf *conf,
13563 const struct rte_flow_action_rss *rss,
13564 struct rte_flow_error *error)
13566 struct mlx5_priv *priv = dev->data->dev_private;
13567 struct mlx5_shared_action_rss *shared_rss = NULL;
13568 void *queue = NULL;
13569 struct rte_flow_action_rss *origin;
13570 const uint8_t *rss_key;
13571 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13574 RTE_SET_USED(conf);
13575 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13577 shared_rss = mlx5_ipool_zmalloc
13578 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13579 if (!shared_rss || !queue) {
13580 rte_flow_error_set(error, ENOMEM,
13581 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13582 "cannot allocate resource memory");
13583 goto error_rss_init;
13585 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13586 rte_flow_error_set(error, E2BIG,
13587 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13588 "rss action number out of range");
13589 goto error_rss_init;
13591 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13592 sizeof(*shared_rss->ind_tbl),
13594 if (!shared_rss->ind_tbl) {
13595 rte_flow_error_set(error, ENOMEM,
13596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13597 "cannot allocate resource memory");
13598 goto error_rss_init;
13600 memcpy(queue, rss->queue, queue_size);
13601 shared_rss->ind_tbl->queues = queue;
13602 shared_rss->ind_tbl->queues_n = rss->queue_num;
13603 origin = &shared_rss->origin;
13604 origin->func = rss->func;
13605 origin->level = rss->level;
13606 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13607 origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13608 /* NULL RSS key indicates default RSS key. */
13609 rss_key = !rss->key ? rss_hash_default_key : rss->key;
13610 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13611 origin->key = &shared_rss->key[0];
13612 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13613 origin->queue = queue;
13614 origin->queue_num = rss->queue_num;
13615 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13616 goto error_rss_init;
13617 rte_spinlock_init(&shared_rss->action_rss_sl);
13618 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13619 rte_spinlock_lock(&priv->shared_act_sl);
13620 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13621 &priv->rss_shared_actions, idx, shared_rss, next);
13622 rte_spinlock_unlock(&priv->shared_act_sl);
13626 if (shared_rss->ind_tbl)
13627 mlx5_free(shared_rss->ind_tbl);
13628 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13637 * Destroy the shared RSS action.
13638 * Release related hash RX queue objects.
13641 * Pointer to the Ethernet device structure.
13643 * The shared RSS action object ID to be removed.
13644 * @param[out] error
13645 * Perform verbose error reporting if not NULL. Initialized in case of
13649 * 0 on success, otherwise negative errno value.
13652 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13653 struct rte_flow_error *error)
13655 struct mlx5_priv *priv = dev->data->dev_private;
13656 struct mlx5_shared_action_rss *shared_rss =
13657 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13658 uint32_t old_refcnt = 1;
13660 uint16_t *queue = NULL;
13663 return rte_flow_error_set(error, EINVAL,
13664 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13665 "invalid shared action");
13666 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13668 return rte_flow_error_set(error, EBUSY,
13669 RTE_FLOW_ERROR_TYPE_ACTION,
13671 "shared rss hrxq has references");
13672 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13673 0, 0, __ATOMIC_ACQUIRE,
13675 return rte_flow_error_set(error, EBUSY,
13676 RTE_FLOW_ERROR_TYPE_ACTION,
13678 "shared rss has references");
13679 queue = shared_rss->ind_tbl->queues;
13680 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13682 return rte_flow_error_set(error, EBUSY,
13683 RTE_FLOW_ERROR_TYPE_ACTION,
13685 "shared rss indirection table has"
13688 rte_spinlock_lock(&priv->shared_act_sl);
13689 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13690 &priv->rss_shared_actions, idx, shared_rss, next);
13691 rte_spinlock_unlock(&priv->shared_act_sl);
13692 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13698 * Create indirect action, lock free,
13699 * (mutex should be acquired by caller).
13700 * Dispatcher for action type specific call.
13703 * Pointer to the Ethernet device structure.
13705 * Shared action configuration.
13706 * @param[in] action
13707 * Action specification used to create indirect action.
13708 * @param[out] error
13709 * Perform verbose error reporting if not NULL. Initialized in case of
13713 * A valid shared action handle in case of success, NULL otherwise and
13714 * rte_errno is set.
13716 static struct rte_flow_action_handle *
13717 flow_dv_action_create(struct rte_eth_dev *dev,
13718 const struct rte_flow_indir_action_conf *conf,
13719 const struct rte_flow_action *action,
13720 struct rte_flow_error *err)
13725 switch (action->type) {
13726 case RTE_FLOW_ACTION_TYPE_RSS:
13727 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13728 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13729 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13731 case RTE_FLOW_ACTION_TYPE_AGE:
13732 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13733 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13734 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13736 struct mlx5_aso_age_action *aso_age =
13737 flow_aso_age_get_by_idx(dev, ret);
13739 if (!aso_age->age_params.context)
13740 aso_age->age_params.context =
13741 (void *)(uintptr_t)idx;
13744 case RTE_FLOW_ACTION_TYPE_COUNT:
13745 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
13746 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
13747 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13750 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13751 NULL, "action type not supported");
13754 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13758 * Destroy the indirect action.
13759 * Release action related resources on the NIC and the memory.
13760 * Lock free, (mutex should be acquired by caller).
13761 * Dispatcher for action type specific call.
13764 * Pointer to the Ethernet device structure.
13765 * @param[in] handle
13766 * The indirect action object handle to be removed.
13767 * @param[out] error
13768 * Perform verbose error reporting if not NULL. Initialized in case of
13772 * 0 on success, otherwise negative errno value.
13775 flow_dv_action_destroy(struct rte_eth_dev *dev,
13776 struct rte_flow_action_handle *handle,
13777 struct rte_flow_error *error)
13779 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13780 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13781 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13782 struct mlx5_flow_counter *cnt;
13783 uint32_t no_flow_refcnt = 1;
13787 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13788 return __flow_dv_action_rss_release(dev, idx, error);
13789 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
13790 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
13791 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
13792 &no_flow_refcnt, 1, false,
13795 return rte_flow_error_set(error, EBUSY,
13796 RTE_FLOW_ERROR_TYPE_ACTION,
13798 "Indirect count action has references");
13799 flow_dv_counter_free(dev, idx);
13801 case MLX5_INDIRECT_ACTION_TYPE_AGE:
13802 ret = flow_dv_aso_age_release(dev, idx);
13805 * In this case, the last flow has a reference will
13806 * actually release the age action.
13808 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13809 " released with references %d.", idx, ret);
13812 return rte_flow_error_set(error, ENOTSUP,
13813 RTE_FLOW_ERROR_TYPE_ACTION,
13815 "action type not supported");
13820 * Updates in place shared RSS action configuration.
13823 * Pointer to the Ethernet device structure.
13825 * The shared RSS action object ID to be updated.
13826 * @param[in] action_conf
13827 * RSS action specification used to modify *shared_rss*.
13828 * @param[out] error
13829 * Perform verbose error reporting if not NULL. Initialized in case of
13833 * 0 on success, otherwise negative errno value.
13834 * @note: currently only support update of RSS queues.
13837 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13838 const struct rte_flow_action_rss *action_conf,
13839 struct rte_flow_error *error)
13841 struct mlx5_priv *priv = dev->data->dev_private;
13842 struct mlx5_shared_action_rss *shared_rss =
13843 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13845 void *queue = NULL;
13846 uint16_t *queue_old = NULL;
13847 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13850 return rte_flow_error_set(error, EINVAL,
13851 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13852 "invalid shared action to update");
13853 if (priv->obj_ops.ind_table_modify == NULL)
13854 return rte_flow_error_set(error, ENOTSUP,
13855 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13856 "cannot modify indirection table");
13857 queue = mlx5_malloc(MLX5_MEM_ZERO,
13858 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13861 return rte_flow_error_set(error, ENOMEM,
13862 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13864 "cannot allocate resource memory");
13865 memcpy(queue, action_conf->queue, queue_size);
13866 MLX5_ASSERT(shared_rss->ind_tbl);
13867 rte_spinlock_lock(&shared_rss->action_rss_sl);
13868 queue_old = shared_rss->ind_tbl->queues;
13869 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13870 queue, action_conf->queue_num, true);
13873 ret = rte_flow_error_set(error, rte_errno,
13874 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13875 "cannot update indirection table");
13877 mlx5_free(queue_old);
13878 shared_rss->origin.queue = queue;
13879 shared_rss->origin.queue_num = action_conf->queue_num;
13881 rte_spinlock_unlock(&shared_rss->action_rss_sl);
13886 * Updates in place shared action configuration, lock free,
13887 * (mutex should be acquired by caller).
13890 * Pointer to the Ethernet device structure.
13891 * @param[in] handle
13892 * The indirect action object handle to be updated.
13893 * @param[in] update
13894 * Action specification used to modify the action pointed by *handle*.
13895 * *update* could be of same type with the action pointed by the *handle*
13896 * handle argument, or some other structures like a wrapper, depending on
13897 * the indirect action type.
13898 * @param[out] error
13899 * Perform verbose error reporting if not NULL. Initialized in case of
13903 * 0 on success, otherwise negative errno value.
13906 flow_dv_action_update(struct rte_eth_dev *dev,
13907 struct rte_flow_action_handle *handle,
13908 const void *update,
13909 struct rte_flow_error *err)
13911 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13912 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13913 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13914 const void *action_conf;
13917 case MLX5_INDIRECT_ACTION_TYPE_RSS:
13918 action_conf = ((const struct rte_flow_action *)update)->conf;
13919 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13921 return rte_flow_error_set(err, ENOTSUP,
13922 RTE_FLOW_ERROR_TYPE_ACTION,
13924 "action type update not supported");
13929 * Destroy the meter sub policy table rules.
13930 * Lock free, (mutex should be acquired by caller).
13933 * Pointer to Ethernet device.
13934 * @param[in] sub_policy
13935 * Pointer to meter sub policy table.
13938 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
13939 struct mlx5_flow_meter_sub_policy *sub_policy)
13941 struct mlx5_flow_tbl_data_entry *tbl;
13944 for (i = 0; i < RTE_COLORS; i++) {
13945 if (sub_policy->color_rule[i]) {
13946 claim_zero(mlx5_flow_os_destroy_flow
13947 (sub_policy->color_rule[i]));
13948 sub_policy->color_rule[i] = NULL;
13950 if (sub_policy->color_matcher[i]) {
13951 tbl = container_of(sub_policy->color_matcher[i]->tbl,
13952 typeof(*tbl), tbl);
13953 mlx5_cache_unregister(&tbl->matchers,
13954 &sub_policy->color_matcher[i]->entry);
13955 sub_policy->color_matcher[i] = NULL;
13958 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
13959 if (sub_policy->rix_hrxq[i]) {
13960 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
13961 sub_policy->rix_hrxq[i] = 0;
13963 if (sub_policy->jump_tbl[i]) {
13964 flow_dv_tbl_resource_release(MLX5_SH(dev),
13965 sub_policy->jump_tbl[i]);
13966 sub_policy->jump_tbl[i] = NULL;
13969 if (sub_policy->tbl_rsc) {
13970 flow_dv_tbl_resource_release(MLX5_SH(dev),
13971 sub_policy->tbl_rsc);
13972 sub_policy->tbl_rsc = NULL;
13977 * Destroy policy rules, lock free,
13978 * (mutex should be acquired by caller).
13979 * Dispatcher for action type specific call.
13982 * Pointer to the Ethernet device structure.
13983 * @param[in] mtr_policy
13984 * Meter policy struct.
13987 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
13988 struct mlx5_flow_meter_policy *mtr_policy)
13991 struct mlx5_flow_meter_sub_policy *sub_policy;
13992 uint16_t sub_policy_num;
13994 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
13995 sub_policy_num = (mtr_policy->sub_policy_num >>
13996 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
13997 MLX5_MTR_SUB_POLICY_NUM_MASK;
13998 for (j = 0; j < sub_policy_num; j++) {
13999 sub_policy = mtr_policy->sub_policys[i][j];
14001 __flow_dv_destroy_sub_policy_rules
14008 * Destroy policy action, lock free,
14009 * (mutex should be acquired by caller).
14010 * Dispatcher for action type specific call.
14013 * Pointer to the Ethernet device structure.
14014 * @param[in] mtr_policy
14015 * Meter policy struct.
14018 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
14019 struct mlx5_flow_meter_policy *mtr_policy)
14021 struct rte_flow_action *rss_action;
14022 struct mlx5_flow_handle dev_handle;
14025 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
14026 if (mtr_policy->act_cnt[i].rix_mark) {
14027 flow_dv_tag_release(dev,
14028 mtr_policy->act_cnt[i].rix_mark);
14029 mtr_policy->act_cnt[i].rix_mark = 0;
14031 if (mtr_policy->act_cnt[i].modify_hdr) {
14032 dev_handle.dvh.modify_hdr =
14033 mtr_policy->act_cnt[i].modify_hdr;
14034 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
14036 switch (mtr_policy->act_cnt[i].fate_action) {
14037 case MLX5_FLOW_FATE_SHARED_RSS:
14038 rss_action = mtr_policy->act_cnt[i].rss;
14039 mlx5_free(rss_action);
14041 case MLX5_FLOW_FATE_PORT_ID:
14042 if (mtr_policy->act_cnt[i].rix_port_id_action) {
14043 flow_dv_port_id_action_resource_release(dev,
14044 mtr_policy->act_cnt[i].rix_port_id_action);
14045 mtr_policy->act_cnt[i].rix_port_id_action = 0;
14048 case MLX5_FLOW_FATE_DROP:
14049 case MLX5_FLOW_FATE_JUMP:
14050 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
14051 mtr_policy->act_cnt[i].dr_jump_action[j] =
14055 /*Queue action do nothing*/
14059 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
14060 mtr_policy->dr_drop_action[j] = NULL;
14064 * Create policy action per domain, lock free,
14065 * (mutex should be acquired by caller).
14066 * Dispatcher for action type specific call.
14069 * Pointer to the Ethernet device structure.
14070 * @param[in] mtr_policy
14071 * Meter policy struct.
14072 * @param[in] action
14073 * Action specification used to create meter actions.
14074 * @param[out] error
14075 * Perform verbose error reporting if not NULL. Initialized in case of
14079 * 0 on success, otherwise negative errno value.
14082 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
14083 struct mlx5_flow_meter_policy *mtr_policy,
14084 const struct rte_flow_action *actions[RTE_COLORS],
14085 enum mlx5_meter_domain domain,
14086 struct rte_mtr_error *error)
14088 struct mlx5_priv *priv = dev->data->dev_private;
14089 struct rte_flow_error flow_err;
14090 const struct rte_flow_action *act;
14091 uint64_t action_flags = 0;
14092 struct mlx5_flow_handle dh;
14093 struct mlx5_flow dev_flow;
14094 struct mlx5_flow_dv_port_id_action_resource port_id_action;
14096 uint8_t egress, transfer;
14097 struct mlx5_meter_policy_action_container *act_cnt = NULL;
14099 struct mlx5_flow_dv_modify_hdr_resource res;
14100 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
14101 sizeof(struct mlx5_modification_cmd) *
14102 (MLX5_MAX_MODIFY_NUM + 1)];
14105 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
14106 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
14107 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
14108 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
14109 memset(&port_id_action, 0,
14110 sizeof(struct mlx5_flow_dv_port_id_action_resource));
14111 dev_flow.handle = &dh;
14112 dev_flow.dv.port_id_action = &port_id_action;
14113 dev_flow.external = true;
14114 for (i = 0; i < RTE_COLORS; i++) {
14115 if (i < MLX5_MTR_RTE_COLORS)
14116 act_cnt = &mtr_policy->act_cnt[i];
14117 for (act = actions[i];
14118 act && act->type != RTE_FLOW_ACTION_TYPE_END;
14120 switch (act->type) {
14121 case RTE_FLOW_ACTION_TYPE_MARK:
14123 uint32_t tag_be = mlx5_flow_mark_set
14124 (((const struct rte_flow_action_mark *)
14127 if (i >= MLX5_MTR_RTE_COLORS)
14128 return -rte_mtr_error_set(error,
14130 RTE_MTR_ERROR_TYPE_METER_POLICY,
14132 "cannot create policy "
14133 "mark action for this color");
14134 dev_flow.handle->mark = 1;
14135 if (flow_dv_tag_resource_register(dev, tag_be,
14136 &dev_flow, &flow_err))
14137 return -rte_mtr_error_set(error,
14139 RTE_MTR_ERROR_TYPE_METER_POLICY,
14141 "cannot setup policy mark action");
14142 MLX5_ASSERT(dev_flow.dv.tag_resource);
14143 act_cnt->rix_mark =
14144 dev_flow.handle->dvh.rix_tag;
14145 if (action_flags & MLX5_FLOW_ACTION_QUEUE) {
14146 dev_flow.handle->rix_hrxq =
14147 mtr_policy->sub_policys[domain][0]->rix_hrxq[i];
14148 flow_drv_rxq_flags_set(dev,
14151 action_flags |= MLX5_FLOW_ACTION_MARK;
14154 case RTE_FLOW_ACTION_TYPE_SET_TAG:
14156 struct mlx5_flow_dv_modify_hdr_resource
14157 *mhdr_res = &mhdr_dummy.res;
14159 if (i >= MLX5_MTR_RTE_COLORS)
14160 return -rte_mtr_error_set(error,
14162 RTE_MTR_ERROR_TYPE_METER_POLICY,
14164 "cannot create policy "
14165 "set tag action for this color");
14166 memset(mhdr_res, 0, sizeof(*mhdr_res));
14167 mhdr_res->ft_type = transfer ?
14168 MLX5DV_FLOW_TABLE_TYPE_FDB :
14170 MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
14171 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
14172 if (flow_dv_convert_action_set_tag
14174 (const struct rte_flow_action_set_tag *)
14175 act->conf, &flow_err))
14176 return -rte_mtr_error_set(error,
14178 RTE_MTR_ERROR_TYPE_METER_POLICY,
14179 NULL, "cannot convert policy "
14181 if (!mhdr_res->actions_num)
14182 return -rte_mtr_error_set(error,
14184 RTE_MTR_ERROR_TYPE_METER_POLICY,
14185 NULL, "cannot find policy "
14187 /* create modify action if needed. */
14188 dev_flow.dv.group = 1;
14189 if (flow_dv_modify_hdr_resource_register
14190 (dev, mhdr_res, &dev_flow, &flow_err))
14191 return -rte_mtr_error_set(error,
14193 RTE_MTR_ERROR_TYPE_METER_POLICY,
14194 NULL, "cannot register policy "
14196 act_cnt->modify_hdr =
14197 dev_flow.handle->dvh.modify_hdr;
14198 if (action_flags & MLX5_FLOW_ACTION_QUEUE) {
14199 dev_flow.handle->rix_hrxq =
14200 mtr_policy->sub_policys[domain][0]->rix_hrxq[i];
14201 flow_drv_rxq_flags_set(dev,
14204 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
14207 case RTE_FLOW_ACTION_TYPE_DROP:
14209 struct mlx5_flow_mtr_mng *mtrmng =
14211 struct mlx5_flow_tbl_data_entry *tbl_data;
14214 * Create the drop table with
14215 * METER DROP level.
14217 if (!mtrmng->drop_tbl[domain]) {
14218 mtrmng->drop_tbl[domain] =
14219 flow_dv_tbl_resource_get(dev,
14220 MLX5_FLOW_TABLE_LEVEL_METER,
14221 egress, transfer, false, NULL, 0,
14222 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
14223 if (!mtrmng->drop_tbl[domain])
14224 return -rte_mtr_error_set
14226 RTE_MTR_ERROR_TYPE_METER_POLICY,
14228 "Failed to create meter drop table");
14230 tbl_data = container_of
14231 (mtrmng->drop_tbl[domain],
14232 struct mlx5_flow_tbl_data_entry, tbl);
14233 if (i < MLX5_MTR_RTE_COLORS) {
14234 act_cnt->dr_jump_action[domain] =
14235 tbl_data->jump.action;
14236 act_cnt->fate_action =
14237 MLX5_FLOW_FATE_DROP;
14239 if (i == RTE_COLOR_RED)
14240 mtr_policy->dr_drop_action[domain] =
14241 tbl_data->jump.action;
14242 action_flags |= MLX5_FLOW_ACTION_DROP;
14245 case RTE_FLOW_ACTION_TYPE_QUEUE:
14247 struct mlx5_hrxq *hrxq;
14249 struct mlx5_flow_rss_desc rss_desc;
14250 struct mlx5_flow_meter_sub_policy *sub_policy =
14251 mtr_policy->sub_policys[domain][0];
14253 if (i >= MLX5_MTR_RTE_COLORS)
14254 return -rte_mtr_error_set(error,
14256 RTE_MTR_ERROR_TYPE_METER_POLICY,
14257 NULL, "cannot create policy "
14258 "fate queue for this color");
14259 memset(&rss_desc, 0,
14260 sizeof(struct mlx5_flow_rss_desc));
14261 rss_desc.queue_num = 1;
14262 rss_desc.const_q = act->conf;
14263 hrxq = flow_dv_hrxq_prepare(dev, &dev_flow,
14264 &rss_desc, &hrxq_idx);
14266 return -rte_mtr_error_set(error,
14268 RTE_MTR_ERROR_TYPE_METER_POLICY,
14270 "cannot create policy fate queue");
14271 sub_policy->rix_hrxq[i] = hrxq_idx;
14272 act_cnt->fate_action =
14273 MLX5_FLOW_FATE_QUEUE;
14274 dev_flow.handle->fate_action =
14275 MLX5_FLOW_FATE_QUEUE;
14276 if (action_flags & MLX5_FLOW_ACTION_MARK ||
14277 action_flags & MLX5_FLOW_ACTION_SET_TAG) {
14278 dev_flow.handle->rix_hrxq = hrxq_idx;
14279 flow_drv_rxq_flags_set(dev,
14282 action_flags |= MLX5_FLOW_ACTION_QUEUE;
14285 case RTE_FLOW_ACTION_TYPE_RSS:
14289 if (i >= MLX5_MTR_RTE_COLORS)
14290 return -rte_mtr_error_set(error,
14292 RTE_MTR_ERROR_TYPE_METER_POLICY,
14294 "cannot create policy "
14295 "rss action for this color");
14297 * Save RSS conf into policy struct
14298 * for translate stage.
14300 rss_size = (int)rte_flow_conv
14301 (RTE_FLOW_CONV_OP_ACTION,
14302 NULL, 0, act, &flow_err);
14304 return -rte_mtr_error_set(error,
14306 RTE_MTR_ERROR_TYPE_METER_POLICY,
14307 NULL, "Get the wrong "
14308 "rss action struct size");
14309 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
14310 rss_size, 0, SOCKET_ID_ANY);
14312 return -rte_mtr_error_set(error,
14314 RTE_MTR_ERROR_TYPE_METER_POLICY,
14316 "Fail to malloc rss action memory");
14317 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
14318 act_cnt->rss, rss_size,
14321 return -rte_mtr_error_set(error,
14323 RTE_MTR_ERROR_TYPE_METER_POLICY,
14324 NULL, "Fail to save "
14325 "rss action into policy struct");
14326 act_cnt->fate_action =
14327 MLX5_FLOW_FATE_SHARED_RSS;
14328 action_flags |= MLX5_FLOW_ACTION_RSS;
14331 case RTE_FLOW_ACTION_TYPE_PORT_ID:
14333 struct mlx5_flow_dv_port_id_action_resource
14335 uint32_t port_id = 0;
14337 if (i >= MLX5_MTR_RTE_COLORS)
14338 return -rte_mtr_error_set(error,
14340 RTE_MTR_ERROR_TYPE_METER_POLICY,
14341 NULL, "cannot create policy "
14342 "port action for this color");
14343 memset(&port_id_resource, 0,
14344 sizeof(port_id_resource));
14345 if (flow_dv_translate_action_port_id(dev, act,
14346 &port_id, &flow_err))
14347 return -rte_mtr_error_set(error,
14349 RTE_MTR_ERROR_TYPE_METER_POLICY,
14350 NULL, "cannot translate "
14351 "policy port action");
14352 port_id_resource.port_id = port_id;
14353 if (flow_dv_port_id_action_resource_register
14354 (dev, &port_id_resource,
14355 &dev_flow, &flow_err))
14356 return -rte_mtr_error_set(error,
14358 RTE_MTR_ERROR_TYPE_METER_POLICY,
14359 NULL, "cannot setup "
14360 "policy port action");
14361 act_cnt->rix_port_id_action =
14362 dev_flow.handle->rix_port_id_action;
14363 act_cnt->fate_action =
14364 MLX5_FLOW_FATE_PORT_ID;
14365 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
14368 case RTE_FLOW_ACTION_TYPE_JUMP:
14370 uint32_t jump_group = 0;
14371 uint32_t table = 0;
14372 struct mlx5_flow_tbl_data_entry *tbl_data;
14373 struct flow_grp_info grp_info = {
14374 .external = !!dev_flow.external,
14375 .transfer = !!transfer,
14376 .fdb_def_rule = !!priv->fdb_def_rule,
14378 .skip_scale = dev_flow.skip_scale &
14379 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
14381 struct mlx5_flow_meter_sub_policy *sub_policy =
14382 mtr_policy->sub_policys[domain][0];
14384 if (i >= MLX5_MTR_RTE_COLORS)
14385 return -rte_mtr_error_set(error,
14387 RTE_MTR_ERROR_TYPE_METER_POLICY,
14389 "cannot create policy "
14390 "jump action for this color");
14392 ((const struct rte_flow_action_jump *)
14394 if (mlx5_flow_group_to_table(dev, NULL,
14397 &grp_info, &flow_err))
14398 return -rte_mtr_error_set(error,
14400 RTE_MTR_ERROR_TYPE_METER_POLICY,
14401 NULL, "cannot setup "
14402 "policy jump action");
14403 sub_policy->jump_tbl[i] =
14404 flow_dv_tbl_resource_get(dev,
14407 !!dev_flow.external,
14408 NULL, jump_group, 0,
14411 (!sub_policy->jump_tbl[i])
14412 return -rte_mtr_error_set(error,
14414 RTE_MTR_ERROR_TYPE_METER_POLICY,
14415 NULL, "cannot create jump action.");
14416 tbl_data = container_of
14417 (sub_policy->jump_tbl[i],
14418 struct mlx5_flow_tbl_data_entry, tbl);
14419 act_cnt->dr_jump_action[domain] =
14420 tbl_data->jump.action;
14421 act_cnt->fate_action =
14422 MLX5_FLOW_FATE_JUMP;
14423 action_flags |= MLX5_FLOW_ACTION_JUMP;
14427 return -rte_mtr_error_set(error, ENOTSUP,
14428 RTE_MTR_ERROR_TYPE_METER_POLICY,
14429 NULL, "action type not supported");
14437 * Create policy action per domain, lock free,
14438 * (mutex should be acquired by caller).
14439 * Dispatcher for action type specific call.
14442 * Pointer to the Ethernet device structure.
14443 * @param[in] mtr_policy
14444 * Meter policy struct.
14445 * @param[in] action
14446 * Action specification used to create meter actions.
14447 * @param[out] error
14448 * Perform verbose error reporting if not NULL. Initialized in case of
14452 * 0 on success, otherwise negative errno value.
14455 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
14456 struct mlx5_flow_meter_policy *mtr_policy,
14457 const struct rte_flow_action *actions[RTE_COLORS],
14458 struct rte_mtr_error *error)
14461 uint16_t sub_policy_num;
14463 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
14464 sub_policy_num = (mtr_policy->sub_policy_num >>
14465 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
14466 MLX5_MTR_SUB_POLICY_NUM_MASK;
14467 if (sub_policy_num) {
14468 ret = __flow_dv_create_domain_policy_acts(dev,
14469 mtr_policy, actions,
14470 (enum mlx5_meter_domain)i, error);
14479 * Query a DV flow rule for its statistics via DevX.
14482 * Pointer to Ethernet device.
14483 * @param[in] cnt_idx
14484 * Index to the flow counter.
14486 * Data retrieved by the query.
14487 * @param[out] error
14488 * Perform verbose error reporting if not NULL.
14491 * 0 on success, a negative errno value otherwise and rte_errno is set.
14494 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
14495 struct rte_flow_error *error)
14497 struct mlx5_priv *priv = dev->data->dev_private;
14498 struct rte_flow_query_count *qc = data;
14500 if (!priv->config.devx)
14501 return rte_flow_error_set(error, ENOTSUP,
14502 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14504 "counters are not supported");
14506 uint64_t pkts, bytes;
14507 struct mlx5_flow_counter *cnt;
14508 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
14511 return rte_flow_error_set(error, -err,
14512 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14513 NULL, "cannot read counters");
14514 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
14517 qc->hits = pkts - cnt->hits;
14518 qc->bytes = bytes - cnt->bytes;
14521 cnt->bytes = bytes;
14525 return rte_flow_error_set(error, EINVAL,
14526 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14528 "counters are not available");
14532 flow_dv_action_query(struct rte_eth_dev *dev,
14533 const struct rte_flow_action_handle *handle, void *data,
14534 struct rte_flow_error *error)
14536 struct mlx5_age_param *age_param;
14537 struct rte_flow_query_age *resp;
14538 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
14539 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
14540 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
14543 case MLX5_INDIRECT_ACTION_TYPE_AGE:
14544 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
14546 resp->aged = __atomic_load_n(&age_param->state,
14547 __ATOMIC_RELAXED) == AGE_TMOUT ?
14549 resp->sec_since_last_hit_valid = !resp->aged;
14550 if (resp->sec_since_last_hit_valid)
14551 resp->sec_since_last_hit = __atomic_load_n
14552 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
14554 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
14555 return flow_dv_query_count(dev, idx, data, error);
14557 return rte_flow_error_set(error, ENOTSUP,
14558 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14559 "action type query not supported");
14564 * Query a flow rule AGE action for aging information.
14567 * Pointer to Ethernet device.
14569 * Pointer to the sub flow.
14571 * data retrieved by the query.
14572 * @param[out] error
14573 * Perform verbose error reporting if not NULL.
14576 * 0 on success, a negative errno value otherwise and rte_errno is set.
14579 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
14580 void *data, struct rte_flow_error *error)
14582 struct rte_flow_query_age *resp = data;
14583 struct mlx5_age_param *age_param;
14586 struct mlx5_aso_age_action *act =
14587 flow_aso_age_get_by_idx(dev, flow->age);
14589 age_param = &act->age_params;
14590 } else if (flow->counter) {
14591 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
14593 if (!age_param || !age_param->timeout)
14594 return rte_flow_error_set
14596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14597 NULL, "cannot read age data");
14599 return rte_flow_error_set(error, EINVAL,
14600 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14601 NULL, "age data not available");
14603 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
14605 resp->sec_since_last_hit_valid = !resp->aged;
14606 if (resp->sec_since_last_hit_valid)
14607 resp->sec_since_last_hit = __atomic_load_n
14608 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
14615 * @see rte_flow_query()
14616 * @see rte_flow_ops
14619 flow_dv_query(struct rte_eth_dev *dev,
14620 struct rte_flow *flow __rte_unused,
14621 const struct rte_flow_action *actions __rte_unused,
14622 void *data __rte_unused,
14623 struct rte_flow_error *error __rte_unused)
14627 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
14628 switch (actions->type) {
14629 case RTE_FLOW_ACTION_TYPE_VOID:
14631 case RTE_FLOW_ACTION_TYPE_COUNT:
14632 ret = flow_dv_query_count(dev, flow->counter, data,
14635 case RTE_FLOW_ACTION_TYPE_AGE:
14636 ret = flow_dv_query_age(dev, flow, data, error);
14639 return rte_flow_error_set(error, ENOTSUP,
14640 RTE_FLOW_ERROR_TYPE_ACTION,
14642 "action not supported");
14649 * Destroy the meter table set.
14650 * Lock free, (mutex should be acquired by caller).
14653 * Pointer to Ethernet device.
14655 * Meter information table.
14658 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
14659 struct mlx5_flow_meter_info *fm)
14661 struct mlx5_priv *priv = dev->data->dev_private;
14664 if (!fm || !priv->config.dv_flow_en)
14666 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
14667 if (fm->drop_rule[i]) {
14668 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
14669 fm->drop_rule[i] = NULL;
14675 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
14677 struct mlx5_priv *priv = dev->data->dev_private;
14678 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
14679 struct mlx5_flow_tbl_data_entry *tbl;
14682 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
14683 if (mtrmng->def_rule[i]) {
14684 claim_zero(mlx5_flow_os_destroy_flow
14685 (mtrmng->def_rule[i]));
14686 mtrmng->def_rule[i] = NULL;
14688 if (mtrmng->def_matcher[i]) {
14689 tbl = container_of(mtrmng->def_matcher[i]->tbl,
14690 struct mlx5_flow_tbl_data_entry, tbl);
14691 mlx5_cache_unregister(&tbl->matchers,
14692 &mtrmng->def_matcher[i]->entry);
14693 mtrmng->def_matcher[i] = NULL;
14695 for (j = 0; j < MLX5_REG_BITS; j++) {
14696 if (mtrmng->drop_matcher[i][j]) {
14698 container_of(mtrmng->drop_matcher[i][j]->tbl,
14699 struct mlx5_flow_tbl_data_entry,
14701 mlx5_cache_unregister(&tbl->matchers,
14702 &mtrmng->drop_matcher[i][j]->entry);
14703 mtrmng->drop_matcher[i][j] = NULL;
14706 if (mtrmng->drop_tbl[i]) {
14707 flow_dv_tbl_resource_release(MLX5_SH(dev),
14708 mtrmng->drop_tbl[i]);
14709 mtrmng->drop_tbl[i] = NULL;
14714 /* Number of meter flow actions, count and jump or count and drop. */
14715 #define METER_ACTIONS 2
14718 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
14719 enum mlx5_meter_domain domain)
14721 struct mlx5_priv *priv = dev->data->dev_private;
14722 struct mlx5_flow_meter_def_policy *def_policy =
14723 priv->sh->mtrmng->def_policy[domain];
14725 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
14726 mlx5_free(def_policy);
14727 priv->sh->mtrmng->def_policy[domain] = NULL;
14731 * Destroy the default policy table set.
14734 * Pointer to Ethernet device.
14737 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
14739 struct mlx5_priv *priv = dev->data->dev_private;
14742 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
14743 if (priv->sh->mtrmng->def_policy[i])
14744 __flow_dv_destroy_domain_def_policy(dev,
14745 (enum mlx5_meter_domain)i);
14746 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
14750 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
14751 uint32_t color_reg_c_idx,
14752 enum rte_color color, void *matcher_object,
14753 int actions_n, void *actions,
14754 bool is_default_policy, void **rule,
14755 const struct rte_flow_attr *attr)
14758 struct mlx5_flow_dv_match_params value = {
14759 .size = sizeof(value.buf) -
14760 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
14762 struct mlx5_flow_dv_match_params matcher = {
14763 .size = sizeof(matcher.buf) -
14764 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
14766 struct mlx5_priv *priv = dev->data->dev_private;
14768 if (!is_default_policy && (priv->representor || priv->master)) {
14769 if (flow_dv_translate_item_port_id(dev, matcher.buf,
14770 value.buf, NULL, attr)) {
14772 "Failed to create meter policy flow with port.");
14776 flow_dv_match_meta_reg(matcher.buf, value.buf,
14777 (enum modify_reg)color_reg_c_idx,
14778 rte_col_2_mlx5_col(color),
14780 ret = mlx5_flow_os_create_flow(matcher_object,
14781 (void *)&value, actions_n, actions, rule);
14783 DRV_LOG(ERR, "Failed to create meter policy flow.");
14790 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
14791 uint32_t color_reg_c_idx,
14793 struct mlx5_flow_meter_sub_policy *sub_policy,
14794 const struct rte_flow_attr *attr,
14795 bool is_default_policy,
14796 struct rte_flow_error *error)
14798 struct mlx5_cache_entry *entry;
14799 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
14800 struct mlx5_flow_dv_matcher matcher = {
14802 .size = sizeof(matcher.mask.buf) -
14803 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
14807 struct mlx5_flow_dv_match_params value = {
14808 .size = sizeof(value.buf) -
14809 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
14811 struct mlx5_flow_cb_ctx ctx = {
14815 struct mlx5_flow_tbl_data_entry *tbl_data;
14816 struct mlx5_priv *priv = dev->data->dev_private;
14817 uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
14819 if (!is_default_policy && (priv->representor || priv->master)) {
14820 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
14821 value.buf, NULL, attr)) {
14823 "Failed to register meter drop matcher with port.");
14827 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
14828 if (priority < RTE_COLOR_RED)
14829 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
14830 (enum modify_reg)color_reg_c_idx, 0, color_mask);
14831 matcher.priority = priority;
14832 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
14833 matcher.mask.size);
14834 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
14836 DRV_LOG(ERR, "Failed to register meter drop matcher.");
14839 sub_policy->color_matcher[priority] =
14840 container_of(entry, struct mlx5_flow_dv_matcher, entry);
14845 * Create the policy rules per domain.
14848 * Pointer to Ethernet device.
14849 * @param[in] sub_policy
14850 * Pointer to sub policy table..
14851 * @param[in] egress
14852 * Direction of the table.
14853 * @param[in] transfer
14854 * E-Switch or NIC flow.
14856 * Pointer to policy action list per color.
14859 * 0 on success, -1 otherwise.
14862 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
14863 struct mlx5_flow_meter_sub_policy *sub_policy,
14864 uint8_t egress, uint8_t transfer, bool is_default_policy,
14865 struct mlx5_meter_policy_acts acts[RTE_COLORS])
14867 struct rte_flow_error flow_err;
14868 uint32_t color_reg_c_idx;
14869 struct rte_flow_attr attr = {
14870 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
14873 .egress = !!egress,
14874 .transfer = !!transfer,
14878 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
14882 /* Create policy table with POLICY level. */
14883 if (!sub_policy->tbl_rsc)
14884 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
14885 MLX5_FLOW_TABLE_LEVEL_POLICY,
14886 egress, transfer, false, NULL, 0, 0,
14887 sub_policy->idx, &flow_err);
14888 if (!sub_policy->tbl_rsc) {
14890 "Failed to create meter sub policy table.");
14893 /* Prepare matchers. */
14894 color_reg_c_idx = ret;
14895 for (i = 0; i < RTE_COLORS; i++) {
14896 if (i == RTE_COLOR_YELLOW || !acts[i].actions_n)
14899 if (!sub_policy->color_matcher[i]) {
14900 /* Create matchers for Color. */
14901 if (__flow_dv_create_policy_matcher(dev,
14902 color_reg_c_idx, i, sub_policy,
14903 &attr, is_default_policy, &flow_err))
14906 /* Create flow, matching color. */
14907 if (acts[i].actions_n)
14908 if (__flow_dv_create_policy_flow(dev,
14909 color_reg_c_idx, (enum rte_color)i,
14910 sub_policy->color_matcher[i]->matcher_object,
14912 acts[i].dv_actions,
14914 &sub_policy->color_rule[i],
14922 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
14923 struct mlx5_flow_meter_policy *mtr_policy,
14924 struct mlx5_flow_meter_sub_policy *sub_policy,
14927 struct mlx5_priv *priv = dev->data->dev_private;
14928 struct mlx5_meter_policy_acts acts[RTE_COLORS];
14929 struct mlx5_flow_dv_tag_resource *tag;
14930 struct mlx5_flow_dv_port_id_action_resource *port_action;
14931 struct mlx5_hrxq *hrxq;
14932 uint8_t egress, transfer;
14935 for (i = 0; i < RTE_COLORS; i++) {
14936 acts[i].actions_n = 0;
14937 if (i == RTE_COLOR_YELLOW)
14939 if (i == RTE_COLOR_RED) {
14940 /* Only support drop on red. */
14941 acts[i].dv_actions[0] =
14942 mtr_policy->dr_drop_action[domain];
14943 acts[i].actions_n = 1;
14946 if (mtr_policy->act_cnt[i].rix_mark) {
14947 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
14948 mtr_policy->act_cnt[i].rix_mark);
14950 DRV_LOG(ERR, "Failed to find "
14951 "mark action for policy.");
14954 acts[i].dv_actions[acts[i].actions_n] =
14956 acts[i].actions_n++;
14958 if (mtr_policy->act_cnt[i].modify_hdr) {
14959 acts[i].dv_actions[acts[i].actions_n] =
14960 mtr_policy->act_cnt[i].modify_hdr->action;
14961 acts[i].actions_n++;
14963 if (mtr_policy->act_cnt[i].fate_action) {
14964 switch (mtr_policy->act_cnt[i].fate_action) {
14965 case MLX5_FLOW_FATE_PORT_ID:
14966 port_action = mlx5_ipool_get
14967 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
14968 mtr_policy->act_cnt[i].rix_port_id_action);
14969 if (!port_action) {
14970 DRV_LOG(ERR, "Failed to find "
14971 "port action for policy.");
14974 acts[i].dv_actions[acts[i].actions_n] =
14975 port_action->action;
14976 acts[i].actions_n++;
14978 case MLX5_FLOW_FATE_DROP:
14979 case MLX5_FLOW_FATE_JUMP:
14980 acts[i].dv_actions[acts[i].actions_n] =
14981 mtr_policy->act_cnt[i].dr_jump_action[domain];
14982 acts[i].actions_n++;
14984 case MLX5_FLOW_FATE_SHARED_RSS:
14985 case MLX5_FLOW_FATE_QUEUE:
14986 hrxq = mlx5_ipool_get
14987 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
14988 sub_policy->rix_hrxq[i]);
14990 DRV_LOG(ERR, "Failed to find "
14991 "queue action for policy.");
14994 acts[i].dv_actions[acts[i].actions_n] =
14996 acts[i].actions_n++;
14999 /*Queue action do nothing*/
15004 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15005 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15006 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
15007 egress, transfer, false, acts)) {
15009 "Failed to create policy rules per domain.");
15016 * Create the policy rules.
15019 * Pointer to Ethernet device.
15020 * @param[in,out] mtr_policy
15021 * Pointer to meter policy table.
15024 * 0 on success, -1 otherwise.
15027 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
15028 struct mlx5_flow_meter_policy *mtr_policy)
15031 uint16_t sub_policy_num;
15033 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15034 sub_policy_num = (mtr_policy->sub_policy_num >>
15035 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15036 MLX5_MTR_SUB_POLICY_NUM_MASK;
15037 if (!sub_policy_num)
15039 /* Prepare actions list and create policy rules. */
15040 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
15041 mtr_policy->sub_policys[i][0], i)) {
15043 "Failed to create policy action list per domain.");
15051 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
15053 struct mlx5_priv *priv = dev->data->dev_private;
15054 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15055 struct mlx5_flow_meter_def_policy *def_policy;
15056 struct mlx5_flow_tbl_resource *jump_tbl;
15057 struct mlx5_flow_tbl_data_entry *tbl_data;
15058 uint8_t egress, transfer;
15059 struct rte_flow_error error;
15060 struct mlx5_meter_policy_acts acts[RTE_COLORS];
15063 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15064 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15065 def_policy = mtrmng->def_policy[domain];
15067 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
15068 sizeof(struct mlx5_flow_meter_def_policy),
15069 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
15071 DRV_LOG(ERR, "Failed to alloc "
15072 "default policy table.");
15073 goto def_policy_error;
15075 mtrmng->def_policy[domain] = def_policy;
15076 /* Create the meter suffix table with SUFFIX level. */
15077 jump_tbl = flow_dv_tbl_resource_get(dev,
15078 MLX5_FLOW_TABLE_LEVEL_METER,
15079 egress, transfer, false, NULL, 0,
15080 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
15083 "Failed to create meter suffix table.");
15084 goto def_policy_error;
15086 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
15087 tbl_data = container_of(jump_tbl,
15088 struct mlx5_flow_tbl_data_entry, tbl);
15089 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
15090 tbl_data->jump.action;
15091 acts[RTE_COLOR_GREEN].dv_actions[0] =
15092 tbl_data->jump.action;
15093 acts[RTE_COLOR_GREEN].actions_n = 1;
15094 /* Create jump action to the drop table. */
15095 if (!mtrmng->drop_tbl[domain]) {
15096 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
15097 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
15098 egress, transfer, false, NULL, 0,
15099 0, MLX5_MTR_TABLE_ID_DROP, &error);
15100 if (!mtrmng->drop_tbl[domain]) {
15101 DRV_LOG(ERR, "Failed to create "
15102 "meter drop table for default policy.");
15103 goto def_policy_error;
15106 tbl_data = container_of(mtrmng->drop_tbl[domain],
15107 struct mlx5_flow_tbl_data_entry, tbl);
15108 def_policy->dr_jump_action[RTE_COLOR_RED] =
15109 tbl_data->jump.action;
15110 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
15111 acts[RTE_COLOR_RED].actions_n = 1;
15112 /* Create default policy rules. */
15113 ret = __flow_dv_create_domain_policy_rules(dev,
15114 &def_policy->sub_policy,
15115 egress, transfer, true, acts);
15117 DRV_LOG(ERR, "Failed to create "
15118 "default policy rules.");
15119 goto def_policy_error;
15124 __flow_dv_destroy_domain_def_policy(dev,
15125 (enum mlx5_meter_domain)domain);
15130 * Create the default policy table set.
15133 * Pointer to Ethernet device.
15135 * 0 on success, -1 otherwise.
15138 flow_dv_create_def_policy(struct rte_eth_dev *dev)
15140 struct mlx5_priv *priv = dev->data->dev_private;
15143 /* Non-termination policy table. */
15144 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15145 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
15147 if (__flow_dv_create_domain_def_policy(dev, i)) {
15149 "Failed to create default policy");
15157 * Create the needed meter tables.
15158 * Lock free, (mutex should be acquired by caller).
15161 * Pointer to Ethernet device.
15163 * Meter information table.
15164 * @param[in] mtr_idx
15166 * @param[in] domain_bitmap
15169 * 0 on success, -1 otherwise.
15172 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
15173 struct mlx5_flow_meter_info *fm,
15175 uint8_t domain_bitmap)
15177 struct mlx5_priv *priv = dev->data->dev_private;
15178 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
15179 struct rte_flow_error error;
15180 struct mlx5_flow_tbl_data_entry *tbl_data;
15181 uint8_t egress, transfer;
15182 void *actions[METER_ACTIONS];
15183 int domain, ret, i;
15184 struct mlx5_flow_counter *cnt;
15185 struct mlx5_flow_dv_match_params value = {
15186 .size = sizeof(value.buf) -
15187 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15189 struct mlx5_flow_dv_match_params matcher_para = {
15190 .size = sizeof(matcher_para.buf) -
15191 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15193 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
15195 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
15196 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
15197 struct mlx5_cache_entry *entry;
15198 struct mlx5_flow_dv_matcher matcher = {
15200 .size = sizeof(matcher.mask.buf) -
15201 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
15204 struct mlx5_flow_dv_matcher *drop_matcher;
15205 struct mlx5_flow_cb_ctx ctx = {
15210 if (!priv->mtr_en || mtr_id_reg_c < 0) {
15211 rte_errno = ENOTSUP;
15214 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
15215 if (!(domain_bitmap & (1 << domain)) ||
15216 (mtrmng->def_rule[domain] && !fm->drop_cnt))
15218 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15219 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15220 /* Create the drop table with METER DROP level. */
15221 if (!mtrmng->drop_tbl[domain]) {
15222 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
15223 MLX5_FLOW_TABLE_LEVEL_METER,
15224 egress, transfer, false, NULL, 0,
15225 0, MLX5_MTR_TABLE_ID_DROP, &error);
15226 if (!mtrmng->drop_tbl[domain]) {
15227 DRV_LOG(ERR, "Failed to create meter drop table.");
15231 /* Create default matcher in drop table. */
15232 matcher.tbl = mtrmng->drop_tbl[domain],
15233 tbl_data = container_of(mtrmng->drop_tbl[domain],
15234 struct mlx5_flow_tbl_data_entry, tbl);
15235 if (!mtrmng->def_matcher[domain]) {
15236 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
15237 (enum modify_reg)mtr_id_reg_c,
15239 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
15240 matcher.crc = rte_raw_cksum
15241 ((const void *)matcher.mask.buf,
15242 matcher.mask.size);
15243 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
15245 DRV_LOG(ERR, "Failed to register meter "
15246 "drop default matcher.");
15249 mtrmng->def_matcher[domain] = container_of(entry,
15250 struct mlx5_flow_dv_matcher, entry);
15252 /* Create default rule in drop table. */
15253 if (!mtrmng->def_rule[domain]) {
15255 actions[i++] = priv->sh->dr_drop_action;
15256 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
15257 (enum modify_reg)mtr_id_reg_c, 0, 0);
15258 ret = mlx5_flow_os_create_flow
15259 (mtrmng->def_matcher[domain]->matcher_object,
15260 (void *)&value, i, actions,
15261 &mtrmng->def_rule[domain]);
15263 DRV_LOG(ERR, "Failed to create meter "
15264 "default drop rule for drop table.");
15270 MLX5_ASSERT(mtrmng->max_mtr_bits);
15271 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
15272 /* Create matchers for Drop. */
15273 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
15274 (enum modify_reg)mtr_id_reg_c, 0,
15275 (mtr_id_mask << mtr_id_offset));
15276 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
15277 matcher.crc = rte_raw_cksum
15278 ((const void *)matcher.mask.buf,
15279 matcher.mask.size);
15280 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
15283 "Failed to register meter drop matcher.");
15286 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
15287 container_of(entry, struct mlx5_flow_dv_matcher,
15291 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
15292 /* Create drop rule, matching meter_id only. */
15293 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
15294 (enum modify_reg)mtr_id_reg_c,
15295 (mtr_idx << mtr_id_offset), UINT32_MAX);
15297 cnt = flow_dv_counter_get_by_idx(dev,
15298 fm->drop_cnt, NULL);
15299 actions[i++] = cnt->action;
15300 actions[i++] = priv->sh->dr_drop_action;
15301 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
15302 (void *)&value, i, actions,
15303 &fm->drop_rule[domain]);
15305 DRV_LOG(ERR, "Failed to create meter "
15306 "drop rule for drop table.");
15312 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15313 if (fm->drop_rule[i]) {
15314 claim_zero(mlx5_flow_os_destroy_flow
15315 (fm->drop_rule[i]));
15316 fm->drop_rule[i] = NULL;
15323 * Find the policy table for prefix table with RSS.
15326 * Pointer to Ethernet device.
15327 * @param[in] mtr_policy
15328 * Pointer to meter policy table.
15329 * @param[in] rss_desc
15330 * Pointer to rss_desc
15332 * Pointer to table set on success, NULL otherwise and rte_errno is set.
15334 static struct mlx5_flow_meter_sub_policy *
15335 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
15336 struct mlx5_flow_meter_policy *mtr_policy,
15337 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
15339 struct mlx5_priv *priv = dev->data->dev_private;
15340 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
15341 uint32_t sub_policy_idx = 0;
15342 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
15344 struct mlx5_hrxq *hrxq;
15345 struct mlx5_flow_handle dh;
15346 struct mlx5_meter_policy_action_container *act_cnt;
15347 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
15348 uint16_t sub_policy_num;
15350 rte_spinlock_lock(&mtr_policy->sl);
15351 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15354 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
15355 if (!hrxq_idx[i]) {
15356 rte_spinlock_unlock(&mtr_policy->sl);
15360 sub_policy_num = (mtr_policy->sub_policy_num >>
15361 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
15362 MLX5_MTR_SUB_POLICY_NUM_MASK;
15363 for (i = 0; i < sub_policy_num;
15365 for (j = 0; j < MLX5_MTR_RTE_COLORS; j++) {
15368 mtr_policy->sub_policys[domain][i]->rix_hrxq[j])
15371 if (j >= MLX5_MTR_RTE_COLORS) {
15373 * Found the sub policy table with
15374 * the same queue per color
15376 rte_spinlock_unlock(&mtr_policy->sl);
15377 for (j = 0; j < MLX5_MTR_RTE_COLORS; j++)
15378 mlx5_hrxq_release(dev, hrxq_idx[j]);
15379 return mtr_policy->sub_policys[domain][i];
15382 /* Create sub policy. */
15383 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
15384 /* Reuse the first dummy sub_policy*/
15385 sub_policy = mtr_policy->sub_policys[domain][0];
15386 sub_policy_idx = sub_policy->idx;
15388 sub_policy = mlx5_ipool_zmalloc
15389 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
15392 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
15393 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
15394 mlx5_hrxq_release(dev, hrxq_idx[i]);
15395 goto rss_sub_policy_error;
15397 sub_policy->idx = sub_policy_idx;
15398 sub_policy->main_policy = mtr_policy;
15400 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15403 sub_policy->rix_hrxq[i] = hrxq_idx[i];
15405 * Overwrite the last action from
15406 * RSS action to Queue action.
15408 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
15411 DRV_LOG(ERR, "Failed to create policy hrxq");
15412 goto rss_sub_policy_error;
15414 act_cnt = &mtr_policy->act_cnt[i];
15415 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
15416 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15417 if (act_cnt->rix_mark)
15419 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
15420 dh.rix_hrxq = hrxq_idx[i];
15421 flow_drv_rxq_flags_set(dev, &dh);
15424 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
15425 sub_policy, domain)) {
15426 DRV_LOG(ERR, "Failed to create policy "
15427 "rules per domain.");
15428 goto rss_sub_policy_error;
15430 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
15431 i = (mtr_policy->sub_policy_num >>
15432 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
15433 MLX5_MTR_SUB_POLICY_NUM_MASK;
15434 mtr_policy->sub_policys[domain][i] = sub_policy;
15436 if (i > MLX5_MTR_RSS_MAX_SUB_POLICY)
15437 goto rss_sub_policy_error;
15438 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
15439 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
15440 mtr_policy->sub_policy_num |=
15441 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
15442 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
15444 rte_spinlock_unlock(&mtr_policy->sl);
15446 rss_sub_policy_error:
15448 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
15449 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
15450 i = (mtr_policy->sub_policy_num >>
15451 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
15452 MLX5_MTR_SUB_POLICY_NUM_MASK;
15453 mtr_policy->sub_policys[domain][i] = NULL;
15455 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
15459 if (sub_policy_idx)
15460 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
15462 rte_spinlock_unlock(&mtr_policy->sl);
15467 * Validate the batch counter support in root table.
15469 * Create a simple flow with invalid counter and drop action on root table to
15470 * validate if batch counter with offset on root table is supported or not.
15473 * Pointer to rte_eth_dev structure.
15476 * 0 on success, a negative errno value otherwise and rte_errno is set.
15479 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
15481 struct mlx5_priv *priv = dev->data->dev_private;
15482 struct mlx5_dev_ctx_shared *sh = priv->sh;
15483 struct mlx5_flow_dv_match_params mask = {
15484 .size = sizeof(mask.buf),
15486 struct mlx5_flow_dv_match_params value = {
15487 .size = sizeof(value.buf),
15489 struct mlx5dv_flow_matcher_attr dv_attr = {
15490 .type = IBV_FLOW_ATTR_NORMAL,
15492 .match_criteria_enable = 0,
15493 .match_mask = (void *)&mask,
15495 void *actions[2] = { 0 };
15496 struct mlx5_flow_tbl_resource *tbl = NULL;
15497 struct mlx5_devx_obj *dcs = NULL;
15498 void *matcher = NULL;
15502 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
15506 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
15509 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
15513 actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
15514 priv->drop_queue.hrxq->action;
15515 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
15516 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
15520 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
15524 * If batch counter with offset is not supported, the driver will not
15525 * validate the invalid offset value, flow create should success.
15526 * In this case, it means batch counter is not supported in root table.
15528 * Otherwise, if flow create is failed, counter offset is supported.
15531 DRV_LOG(INFO, "Batch counter is not supported in root "
15532 "table. Switch to fallback mode.");
15533 rte_errno = ENOTSUP;
15535 claim_zero(mlx5_flow_os_destroy_flow(flow));
15537 /* Check matcher to make sure validate fail at flow create. */
15538 if (!matcher || (matcher && errno != EINVAL))
15539 DRV_LOG(ERR, "Unexpected error in counter offset "
15540 "support detection");
15544 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
15546 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
15548 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
15550 claim_zero(mlx5_devx_cmd_destroy(dcs));
15555 * Query a devx counter.
15558 * Pointer to the Ethernet device structure.
15560 * Index to the flow counter.
15562 * Set to clear the counter statistics.
15564 * The statistics value of packets.
15565 * @param[out] bytes
15566 * The statistics value of bytes.
15569 * 0 on success, otherwise return -1.
15572 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
15573 uint64_t *pkts, uint64_t *bytes)
15575 struct mlx5_priv *priv = dev->data->dev_private;
15576 struct mlx5_flow_counter *cnt;
15577 uint64_t inn_pkts, inn_bytes;
15580 if (!priv->config.devx)
15583 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
15586 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
15587 *pkts = inn_pkts - cnt->hits;
15588 *bytes = inn_bytes - cnt->bytes;
15590 cnt->hits = inn_pkts;
15591 cnt->bytes = inn_bytes;
15597 * Get aged-out flows.
15600 * Pointer to the Ethernet device structure.
15601 * @param[in] context
15602 * The address of an array of pointers to the aged-out flows contexts.
15603 * @param[in] nb_contexts
15604 * The length of context array pointers.
15605 * @param[out] error
15606 * Perform verbose error reporting if not NULL. Initialized in case of
15610 * how many contexts get in success, otherwise negative errno value.
15611 * if nb_contexts is 0, return the amount of all aged contexts.
15612 * if nb_contexts is not 0 , return the amount of aged flows reported
15613 * in the context array.
15614 * @note: only stub for now
15617 flow_get_aged_flows(struct rte_eth_dev *dev,
15619 uint32_t nb_contexts,
15620 struct rte_flow_error *error)
15622 struct mlx5_priv *priv = dev->data->dev_private;
15623 struct mlx5_age_info *age_info;
15624 struct mlx5_age_param *age_param;
15625 struct mlx5_flow_counter *counter;
15626 struct mlx5_aso_age_action *act;
15629 if (nb_contexts && !context)
15630 return rte_flow_error_set(error, EINVAL,
15631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15632 NULL, "empty context");
15633 age_info = GET_PORT_AGE_INFO(priv);
15634 rte_spinlock_lock(&age_info->aged_sl);
15635 LIST_FOREACH(act, &age_info->aged_aso, next) {
15638 context[nb_flows - 1] =
15639 act->age_params.context;
15640 if (!(--nb_contexts))
15644 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
15647 age_param = MLX5_CNT_TO_AGE(counter);
15648 context[nb_flows - 1] = age_param->context;
15649 if (!(--nb_contexts))
15653 rte_spinlock_unlock(&age_info->aged_sl);
15654 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
15659 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
15662 flow_dv_counter_allocate(struct rte_eth_dev *dev)
15664 return flow_dv_counter_alloc(dev, 0);
15668 * Validate indirect action.
15669 * Dispatcher for action type specific validation.
15672 * Pointer to the Ethernet device structure.
15674 * Indirect action configuration.
15675 * @param[in] action
15676 * The indirect action object to validate.
15677 * @param[out] error
15678 * Perform verbose error reporting if not NULL. Initialized in case of
15682 * 0 on success, otherwise negative errno value.
15685 flow_dv_action_validate(struct rte_eth_dev *dev,
15686 const struct rte_flow_indir_action_conf *conf,
15687 const struct rte_flow_action *action,
15688 struct rte_flow_error *err)
15690 struct mlx5_priv *priv = dev->data->dev_private;
15692 RTE_SET_USED(conf);
15693 switch (action->type) {
15694 case RTE_FLOW_ACTION_TYPE_RSS:
15696 * priv->obj_ops is set according to driver capabilities.
15697 * When DevX capabilities are
15698 * sufficient, it is set to devx_obj_ops.
15699 * Otherwise, it is set to ibv_obj_ops.
15700 * ibv_obj_ops doesn't support ind_table_modify operation.
15701 * In this case the indirect RSS action can't be used.
15703 if (priv->obj_ops.ind_table_modify == NULL)
15704 return rte_flow_error_set
15706 RTE_FLOW_ERROR_TYPE_ACTION,
15708 "Indirect RSS action not supported");
15709 return mlx5_validate_action_rss(dev, action, err);
15710 case RTE_FLOW_ACTION_TYPE_AGE:
15711 if (!priv->sh->aso_age_mng)
15712 return rte_flow_error_set(err, ENOTSUP,
15713 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15715 "Indirect age action not supported");
15716 return flow_dv_validate_action_age(0, action, dev, err);
15717 case RTE_FLOW_ACTION_TYPE_COUNT:
15719 * There are two mechanisms to share the action count.
15720 * The old mechanism uses the shared field to share, while the
15721 * new mechanism uses the indirect action API.
15722 * This validation comes to make sure that the two mechanisms
15723 * are not combined.
15725 if (is_shared_action_count(action))
15726 return rte_flow_error_set(err, ENOTSUP,
15727 RTE_FLOW_ERROR_TYPE_ACTION,
15729 "Mix shared and indirect counter is not supported");
15730 return flow_dv_validate_action_count(dev, true, 0, err);
15732 return rte_flow_error_set(err, ENOTSUP,
15733 RTE_FLOW_ERROR_TYPE_ACTION,
15735 "action type not supported");
15740 * Validate meter policy actions.
15741 * Dispatcher for action type specific validation.
15744 * Pointer to the Ethernet device structure.
15745 * @param[in] action
15746 * The meter policy action object to validate.
15748 * Attributes of flow to determine steering domain.
15749 * @param[out] error
15750 * Perform verbose error reporting if not NULL. Initialized in case of
15754 * 0 on success, otherwise negative errno value.
15757 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
15758 const struct rte_flow_action *actions[RTE_COLORS],
15759 struct rte_flow_attr *attr,
15761 uint8_t *domain_bitmap,
15762 bool *is_def_policy,
15763 struct rte_mtr_error *error)
15765 struct mlx5_priv *priv = dev->data->dev_private;
15766 struct mlx5_dev_config *dev_conf = &priv->config;
15767 const struct rte_flow_action *act;
15768 uint64_t action_flags = 0;
15771 struct rte_flow_error flow_err;
15772 uint8_t domain_color[RTE_COLORS] = {0};
15773 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
15775 if (!priv->config.dv_esw_en)
15776 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
15777 *domain_bitmap = def_domain;
15778 if (actions[RTE_COLOR_YELLOW] &&
15779 actions[RTE_COLOR_YELLOW]->type != RTE_FLOW_ACTION_TYPE_END)
15780 return -rte_mtr_error_set(error, ENOTSUP,
15781 RTE_MTR_ERROR_TYPE_METER_POLICY,
15783 "Yellow color does not support any action.");
15784 if (actions[RTE_COLOR_YELLOW] &&
15785 actions[RTE_COLOR_YELLOW]->type != RTE_FLOW_ACTION_TYPE_DROP)
15786 return -rte_mtr_error_set(error, ENOTSUP,
15787 RTE_MTR_ERROR_TYPE_METER_POLICY,
15788 NULL, "Red color only supports drop action.");
15790 * Check default policy actions:
15791 * Green/Yellow: no action, Red: drop action
15793 if ((!actions[RTE_COLOR_GREEN] ||
15794 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)) {
15795 *is_def_policy = true;
15798 flow_err.message = NULL;
15799 for (i = 0; i < RTE_COLORS; i++) {
15801 for (action_flags = 0, actions_n = 0;
15802 act && act->type != RTE_FLOW_ACTION_TYPE_END;
15804 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
15805 return -rte_mtr_error_set(error, ENOTSUP,
15806 RTE_MTR_ERROR_TYPE_METER_POLICY,
15807 NULL, "too many actions");
15808 switch (act->type) {
15809 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15810 if (!priv->config.dv_esw_en)
15811 return -rte_mtr_error_set(error,
15813 RTE_MTR_ERROR_TYPE_METER_POLICY,
15814 NULL, "PORT action validate check"
15815 " fail for ESW disable");
15816 ret = flow_dv_validate_action_port_id(dev,
15818 act, attr, &flow_err);
15820 return -rte_mtr_error_set(error,
15822 RTE_MTR_ERROR_TYPE_METER_POLICY,
15823 NULL, flow_err.message ?
15825 "PORT action validate check fail");
15827 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15829 case RTE_FLOW_ACTION_TYPE_MARK:
15830 ret = flow_dv_validate_action_mark(dev, act,
15834 return -rte_mtr_error_set(error,
15836 RTE_MTR_ERROR_TYPE_METER_POLICY,
15837 NULL, flow_err.message ?
15839 "Mark action validate check fail");
15840 if (dev_conf->dv_xmeta_en !=
15841 MLX5_XMETA_MODE_LEGACY)
15842 return -rte_mtr_error_set(error,
15844 RTE_MTR_ERROR_TYPE_METER_POLICY,
15845 NULL, "Extend MARK action is "
15846 "not supported. Please try use "
15847 "default policy for meter.");
15848 action_flags |= MLX5_FLOW_ACTION_MARK;
15851 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15852 ret = flow_dv_validate_action_set_tag(dev,
15856 return -rte_mtr_error_set(error,
15858 RTE_MTR_ERROR_TYPE_METER_POLICY,
15859 NULL, flow_err.message ?
15861 "Set tag action validate check fail");
15863 * Count all modify-header actions
15866 if (!(action_flags &
15867 MLX5_FLOW_MODIFY_HDR_ACTIONS))
15869 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15871 case RTE_FLOW_ACTION_TYPE_DROP:
15872 ret = mlx5_flow_validate_action_drop
15876 return -rte_mtr_error_set(error,
15878 RTE_MTR_ERROR_TYPE_METER_POLICY,
15879 NULL, flow_err.message ?
15881 "Drop action validate check fail");
15882 action_flags |= MLX5_FLOW_ACTION_DROP;
15885 case RTE_FLOW_ACTION_TYPE_QUEUE:
15887 * Check whether extensive
15888 * metadata feature is engaged.
15890 if (dev_conf->dv_flow_en &&
15891 (dev_conf->dv_xmeta_en !=
15892 MLX5_XMETA_MODE_LEGACY) &&
15893 mlx5_flow_ext_mreg_supported(dev))
15894 return -rte_mtr_error_set(error,
15896 RTE_MTR_ERROR_TYPE_METER_POLICY,
15897 NULL, "Queue action with meta "
15898 "is not supported. Please try use "
15899 "default policy for meter.");
15900 ret = mlx5_flow_validate_action_queue(act,
15904 return -rte_mtr_error_set(error,
15906 RTE_MTR_ERROR_TYPE_METER_POLICY,
15907 NULL, flow_err.message ?
15909 "Queue action validate check fail");
15910 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15913 case RTE_FLOW_ACTION_TYPE_RSS:
15914 if (dev_conf->dv_flow_en &&
15915 (dev_conf->dv_xmeta_en !=
15916 MLX5_XMETA_MODE_LEGACY) &&
15917 mlx5_flow_ext_mreg_supported(dev))
15918 return -rte_mtr_error_set(error,
15920 RTE_MTR_ERROR_TYPE_METER_POLICY,
15921 NULL, "RSS action with meta "
15922 "is not supported. Please try use "
15923 "default policy for meter.");
15924 ret = mlx5_validate_action_rss(dev, act,
15927 return -rte_mtr_error_set(error,
15929 RTE_MTR_ERROR_TYPE_METER_POLICY,
15930 NULL, flow_err.message ?
15932 "RSS action validate check fail");
15933 action_flags |= MLX5_FLOW_ACTION_RSS;
15937 case RTE_FLOW_ACTION_TYPE_JUMP:
15938 ret = flow_dv_validate_action_jump(dev,
15939 NULL, act, action_flags,
15940 attr, true, &flow_err);
15942 return -rte_mtr_error_set(error,
15944 RTE_MTR_ERROR_TYPE_METER_POLICY,
15945 NULL, flow_err.message ?
15947 "Jump action validate check fail");
15949 action_flags |= MLX5_FLOW_ACTION_JUMP;
15952 return -rte_mtr_error_set(error, ENOTSUP,
15953 RTE_MTR_ERROR_TYPE_METER_POLICY,
15955 "Doesn't support optional action");
15958 /* Yellow is not supported, just skip. */
15959 if (i == RTE_COLOR_YELLOW)
15961 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
15962 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
15963 else if ((action_flags &
15964 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
15965 (action_flags & MLX5_FLOW_ACTION_MARK))
15967 * Only support MLX5_XMETA_MODE_LEGACY
15968 * so MARK action only in ingress domain.
15970 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
15972 domain_color[i] = def_domain;
15974 * Validate the drop action mutual exclusion
15975 * with other actions. Drop action is mutually-exclusive
15976 * with any other action, except for Count action.
15978 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
15979 (action_flags & ~MLX5_FLOW_ACTION_DROP)) {
15980 return -rte_mtr_error_set(error, ENOTSUP,
15981 RTE_MTR_ERROR_TYPE_METER_POLICY,
15982 NULL, "Drop action is mutually-exclusive "
15983 "with any other action");
15985 /* Eswitch has few restrictions on using items and actions */
15986 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
15987 if (!mlx5_flow_ext_mreg_supported(dev) &&
15988 action_flags & MLX5_FLOW_ACTION_MARK)
15989 return -rte_mtr_error_set(error, ENOTSUP,
15990 RTE_MTR_ERROR_TYPE_METER_POLICY,
15991 NULL, "unsupported action MARK");
15992 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
15993 return -rte_mtr_error_set(error, ENOTSUP,
15994 RTE_MTR_ERROR_TYPE_METER_POLICY,
15995 NULL, "unsupported action QUEUE");
15996 if (action_flags & MLX5_FLOW_ACTION_RSS)
15997 return -rte_mtr_error_set(error, ENOTSUP,
15998 RTE_MTR_ERROR_TYPE_METER_POLICY,
15999 NULL, "unsupported action RSS");
16000 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
16001 return -rte_mtr_error_set(error, ENOTSUP,
16002 RTE_MTR_ERROR_TYPE_METER_POLICY,
16003 NULL, "no fate action is found");
16005 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) &&
16007 MLX5_MTR_DOMAIN_INGRESS_BIT)) {
16008 if ((domain_color[i] &
16009 MLX5_MTR_DOMAIN_EGRESS_BIT))
16011 MLX5_MTR_DOMAIN_EGRESS_BIT;
16013 return -rte_mtr_error_set(error,
16015 RTE_MTR_ERROR_TYPE_METER_POLICY,
16016 NULL, "no fate action is found");
16019 if (domain_color[i] != def_domain)
16020 *domain_bitmap = domain_color[i];
16026 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
16028 struct mlx5_priv *priv = dev->data->dev_private;
16031 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
16032 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
16037 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
16038 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
16042 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
16043 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
16050 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
16051 .validate = flow_dv_validate,
16052 .prepare = flow_dv_prepare,
16053 .translate = flow_dv_translate,
16054 .apply = flow_dv_apply,
16055 .remove = flow_dv_remove,
16056 .destroy = flow_dv_destroy,
16057 .query = flow_dv_query,
16058 .create_mtr_tbls = flow_dv_create_mtr_tbls,
16059 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
16060 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
16061 .create_meter = flow_dv_mtr_alloc,
16062 .free_meter = flow_dv_aso_mtr_release_to_pool,
16063 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
16064 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
16065 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
16066 .create_policy_rules = flow_dv_create_policy_rules,
16067 .destroy_policy_rules = flow_dv_destroy_policy_rules,
16068 .create_def_policy = flow_dv_create_def_policy,
16069 .destroy_def_policy = flow_dv_destroy_def_policy,
16070 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
16071 .counter_alloc = flow_dv_counter_allocate,
16072 .counter_free = flow_dv_counter_free,
16073 .counter_query = flow_dv_counter_query,
16074 .get_aged_flows = flow_get_aged_flows,
16075 .action_validate = flow_dv_action_validate,
16076 .action_create = flow_dv_action_create,
16077 .action_destroy = flow_dv_action_destroy,
16078 .action_update = flow_dv_action_update,
16079 .action_query = flow_dv_action_query,
16080 .sync_domain = flow_dv_sync_domain,
16083 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */